DAGCombiner.cpp revision 0cee5f4752c0ee0c90afaf20bb63d6cff167b92d
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/Compiler.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/MathExtras.h" 39#include <algorithm> 40#include <set> 41using namespace llvm; 42 43STATISTIC(NodesCombined , "Number of dag nodes combined"); 44STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 45STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 46STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 47 48namespace { 49 static cl::opt<bool> 50 CombinerAA("combiner-alias-analysis", cl::Hidden, 51 cl::desc("Turn on alias analysis during testing")); 52 53 static cl::opt<bool> 54 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 55 cl::desc("Include global information in alias analysis")); 56 57//------------------------------ DAGCombiner ---------------------------------// 58 59 class VISIBILITY_HIDDEN DAGCombiner { 60 SelectionDAG &DAG; 61 const TargetLowering &TLI; 62 CombineLevel Level; 63 CodeGenOpt::Level OptLevel; 64 bool LegalOperations; 65 bool LegalTypes; 66 67 // Worklist of all of the nodes that need to be simplified. 68 std::vector<SDNode*> WorkList; 69 70 // AA - Used for DAG load/store alias analysis. 71 AliasAnalysis &AA; 72 73 /// AddUsersToWorkList - When an instruction is simplified, add all users of 74 /// the instruction to the work lists because they might get more simplified 75 /// now. 76 /// 77 void AddUsersToWorkList(SDNode *N) { 78 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 79 UI != UE; ++UI) 80 AddToWorkList(*UI); 81 } 82 83 /// visit - call the node-specific routine that knows how to fold each 84 /// particular type of node. 85 SDValue visit(SDNode *N); 86 87 public: 88 /// AddToWorkList - Add to the work list making sure it's instance is at the 89 /// the back (next to be processed.) 90 void AddToWorkList(SDNode *N) { 91 removeFromWorkList(N); 92 WorkList.push_back(N); 93 } 94 95 /// removeFromWorkList - remove all instances of N from the worklist. 96 /// 97 void removeFromWorkList(SDNode *N) { 98 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 99 WorkList.end()); 100 } 101 102 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 103 bool AddTo = true); 104 105 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 106 return CombineTo(N, &Res, 1, AddTo); 107 } 108 109 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 110 bool AddTo = true) { 111 SDValue To[] = { Res0, Res1 }; 112 return CombineTo(N, To, 2, AddTo); 113 } 114 115 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 116 117 private: 118 119 /// SimplifyDemandedBits - Check the specified integer node value to see if 120 /// it can be simplified or if things it uses can be simplified by bit 121 /// propagation. If so, return true. 122 bool SimplifyDemandedBits(SDValue Op) { 123 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 SDValue Ptr2, int64_t Size2, 242 const Value *SrcValue2, int SrcValueOffset2) const; 243 244 /// FindAliasInfo - Extracts the relevant alias information from the memory 245 /// node. Returns true if the operand was a load. 246 bool FindAliasInfo(SDNode *N, 247 SDValue &Ptr, int64_t &Size, 248 const Value *&SrcValue, int &SrcValueOffset) const; 249 250 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 251 /// looking for a better chain (aliasing node.) 252 SDValue FindBetterChain(SDNode *N, SDValue Chain); 253 254 /// getShiftAmountTy - Returns a type large enough to hold any valid 255 /// shift amount - before type legalization these can be huge. 256 MVT getShiftAmountTy() { 257 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 258 } 259 260public: 261 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 262 : DAG(D), 263 TLI(D.getTargetLoweringInfo()), 264 Level(Unrestricted), 265 OptLevel(OL), 266 LegalOperations(false), 267 LegalTypes(false), 268 AA(A) {} 269 270 /// Run - runs the dag combiner on all nodes in the work list 271 void Run(CombineLevel AtLevel); 272 }; 273} 274 275 276namespace { 277/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 278/// nodes from the worklist. 279class VISIBILITY_HIDDEN WorkListRemover : 280 public SelectionDAG::DAGUpdateListener { 281 DAGCombiner &DC; 282public: 283 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 284 285 virtual void NodeDeleted(SDNode *N, SDNode *E) { 286 DC.removeFromWorkList(N); 287 } 288 289 virtual void NodeUpdated(SDNode *N) { 290 // Ignore updates. 291 } 292}; 293} 294 295//===----------------------------------------------------------------------===// 296// TargetLowering::DAGCombinerInfo implementation 297//===----------------------------------------------------------------------===// 298 299void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 300 ((DAGCombiner*)DC)->AddToWorkList(N); 301} 302 303SDValue TargetLowering::DAGCombinerInfo:: 304CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 305 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 306} 307 308SDValue TargetLowering::DAGCombinerInfo:: 309CombineTo(SDNode *N, SDValue Res, bool AddTo) { 310 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 311} 312 313 314SDValue TargetLowering::DAGCombinerInfo:: 315CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 316 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 317} 318 319void TargetLowering::DAGCombinerInfo:: 320CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 321 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 322} 323 324//===----------------------------------------------------------------------===// 325// Helper Functions 326//===----------------------------------------------------------------------===// 327 328/// isNegatibleForFree - Return 1 if we can compute the negated form of the 329/// specified expression for the same cost as the expression itself, or 2 if we 330/// can compute the negated form more cheaply than the expression itself. 331static char isNegatibleForFree(SDValue Op, bool LegalOperations, 332 unsigned Depth = 0) { 333 // No compile time optimizations on this type. 334 if (Op.getValueType() == MVT::ppcf128) 335 return 0; 336 337 // fneg is removable even if it has multiple uses. 338 if (Op.getOpcode() == ISD::FNEG) return 2; 339 340 // Don't allow anything with multiple uses. 341 if (!Op.hasOneUse()) return 0; 342 343 // Don't recurse exponentially. 344 if (Depth > 6) return 0; 345 346 switch (Op.getOpcode()) { 347 default: return false; 348 case ISD::ConstantFP: 349 // Don't invert constant FP values after legalize. The negated constant 350 // isn't necessarily legal. 351 return LegalOperations ? 0 : 1; 352 case ISD::FADD: 353 // FIXME: determine better conditions for this xform. 354 if (!UnsafeFPMath) return 0; 355 356 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 357 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 358 return V; 359 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 360 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 361 case ISD::FSUB: 362 // We can't turn -(A-B) into B-A when we honor signed zeros. 363 if (!UnsafeFPMath) return 0; 364 365 // fold (fneg (fsub A, B)) -> (fsub B, A) 366 return 1; 367 368 case ISD::FMUL: 369 case ISD::FDIV: 370 if (HonorSignDependentRoundingFPMath()) return 0; 371 372 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 373 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 374 return V; 375 376 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 377 378 case ISD::FP_EXTEND: 379 case ISD::FP_ROUND: 380 case ISD::FSIN: 381 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 382 } 383} 384 385/// GetNegatedExpression - If isNegatibleForFree returns true, this function 386/// returns the newly negated expression. 387static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 388 bool LegalOperations, unsigned Depth = 0) { 389 // fneg is removable even if it has multiple uses. 390 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 391 392 // Don't allow anything with multiple uses. 393 assert(Op.hasOneUse() && "Unknown reuse!"); 394 395 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 396 switch (Op.getOpcode()) { 397 default: llvm_unreachable("Unknown code"); 398 case ISD::ConstantFP: { 399 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 400 V.changeSign(); 401 return DAG.getConstantFP(V, Op.getValueType()); 402 } 403 case ISD::FADD: 404 // FIXME: determine better conditions for this xform. 405 assert(UnsafeFPMath); 406 407 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 408 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 409 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 410 GetNegatedExpression(Op.getOperand(0), DAG, 411 LegalOperations, Depth+1), 412 Op.getOperand(1)); 413 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 414 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 415 GetNegatedExpression(Op.getOperand(1), DAG, 416 LegalOperations, Depth+1), 417 Op.getOperand(0)); 418 case ISD::FSUB: 419 // We can't turn -(A-B) into B-A when we honor signed zeros. 420 assert(UnsafeFPMath); 421 422 // fold (fneg (fsub 0, B)) -> B 423 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 424 if (N0CFP->getValueAPF().isZero()) 425 return Op.getOperand(1); 426 427 // fold (fneg (fsub A, B)) -> (fsub B, A) 428 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 429 Op.getOperand(1), Op.getOperand(0)); 430 431 case ISD::FMUL: 432 case ISD::FDIV: 433 assert(!HonorSignDependentRoundingFPMath()); 434 435 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 436 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 437 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(0), DAG, 439 LegalOperations, Depth+1), 440 Op.getOperand(1)); 441 442 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 443 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 444 Op.getOperand(0), 445 GetNegatedExpression(Op.getOperand(1), DAG, 446 LegalOperations, Depth+1)); 447 448 case ISD::FP_EXTEND: 449 case ISD::FSIN: 450 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 451 GetNegatedExpression(Op.getOperand(0), DAG, 452 LegalOperations, Depth+1)); 453 case ISD::FP_ROUND: 454 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 455 GetNegatedExpression(Op.getOperand(0), DAG, 456 LegalOperations, Depth+1), 457 Op.getOperand(1)); 458 } 459} 460 461 462// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 463// that selects between the values 1 and 0, making it equivalent to a setcc. 464// Also, set the incoming LHS, RHS, and CC references to the appropriate 465// nodes based on the type of node we are checking. This simplifies life a 466// bit for the callers. 467static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 468 SDValue &CC) { 469 if (N.getOpcode() == ISD::SETCC) { 470 LHS = N.getOperand(0); 471 RHS = N.getOperand(1); 472 CC = N.getOperand(2); 473 return true; 474 } 475 if (N.getOpcode() == ISD::SELECT_CC && 476 N.getOperand(2).getOpcode() == ISD::Constant && 477 N.getOperand(3).getOpcode() == ISD::Constant && 478 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 479 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 480 LHS = N.getOperand(0); 481 RHS = N.getOperand(1); 482 CC = N.getOperand(4); 483 return true; 484 } 485 return false; 486} 487 488// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 489// one use. If this is true, it allows the users to invert the operation for 490// free when it is profitable to do so. 491static bool isOneUseSetCC(SDValue N) { 492 SDValue N0, N1, N2; 493 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 494 return true; 495 return false; 496} 497 498SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 499 SDValue N0, SDValue N1) { 500 MVT VT = N0.getValueType(); 501 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 502 if (isa<ConstantSDNode>(N1)) { 503 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 504 SDValue OpNode = 505 DAG.FoldConstantArithmetic(Opc, VT, 506 cast<ConstantSDNode>(N0.getOperand(1)), 507 cast<ConstantSDNode>(N1)); 508 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 509 } else if (N0.hasOneUse()) { 510 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 511 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 512 N0.getOperand(0), N1); 513 AddToWorkList(OpNode.getNode()); 514 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 515 } 516 } 517 518 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 519 if (isa<ConstantSDNode>(N0)) { 520 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 521 SDValue OpNode = 522 DAG.FoldConstantArithmetic(Opc, VT, 523 cast<ConstantSDNode>(N1.getOperand(1)), 524 cast<ConstantSDNode>(N0)); 525 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 526 } else if (N1.hasOneUse()) { 527 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 528 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 529 N1.getOperand(0), N0); 530 AddToWorkList(OpNode.getNode()); 531 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 532 } 533 } 534 535 return SDValue(); 536} 537 538SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 539 bool AddTo) { 540 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 541 ++NodesCombined; 542 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 543 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 544 DOUT << " and " << NumTo-1 << " other values\n"; 545 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 546 assert(N->getValueType(i) == To[i].getValueType() && 547 "Cannot combine value to value of different type!")); 548 WorkListRemover DeadNodes(*this); 549 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 550 551 if (AddTo) { 552 // Push the new nodes and any users onto the worklist 553 for (unsigned i = 0, e = NumTo; i != e; ++i) { 554 if (To[i].getNode()) { 555 AddToWorkList(To[i].getNode()); 556 AddUsersToWorkList(To[i].getNode()); 557 } 558 } 559 } 560 561 // Finally, if the node is now dead, remove it from the graph. The node 562 // may not be dead if the replacement process recursively simplified to 563 // something else needing this node. 564 if (N->use_empty()) { 565 // Nodes can be reintroduced into the worklist. Make sure we do not 566 // process a node that has been replaced. 567 removeFromWorkList(N); 568 569 // Finally, since the node is now dead, remove it from the graph. 570 DAG.DeleteNode(N); 571 } 572 return SDValue(N, 0); 573} 574 575void 576DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 577 TLO) { 578 // Replace all uses. If any nodes become isomorphic to other nodes and 579 // are deleted, make sure to remove them from our worklist. 580 WorkListRemover DeadNodes(*this); 581 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 582 583 // Push the new node and any (possibly new) users onto the worklist. 584 AddToWorkList(TLO.New.getNode()); 585 AddUsersToWorkList(TLO.New.getNode()); 586 587 // Finally, if the node is now dead, remove it from the graph. The node 588 // may not be dead if the replacement process recursively simplified to 589 // something else needing this node. 590 if (TLO.Old.getNode()->use_empty()) { 591 removeFromWorkList(TLO.Old.getNode()); 592 593 // If the operands of this node are only used by the node, they will now 594 // be dead. Make sure to visit them first to delete dead nodes early. 595 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 596 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 597 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 598 599 DAG.DeleteNode(TLO.Old.getNode()); 600 } 601} 602 603/// SimplifyDemandedBits - Check the specified integer node value to see if 604/// it can be simplified or if things it uses can be simplified by bit 605/// propagation. If so, return true. 606bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 607 TargetLowering::TargetLoweringOpt TLO(DAG); 608 APInt KnownZero, KnownOne; 609 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 610 return false; 611 612 // Revisit the node. 613 AddToWorkList(Op.getNode()); 614 615 // Replace the old value with the new one. 616 ++NodesCombined; 617 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 618 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 619 DOUT << '\n'; 620 621 CommitTargetLoweringOpt(TLO); 622 return true; 623} 624 625//===----------------------------------------------------------------------===// 626// Main DAG Combiner implementation 627//===----------------------------------------------------------------------===// 628 629void DAGCombiner::Run(CombineLevel AtLevel) { 630 // set the instance variables, so that the various visit routines may use it. 631 Level = AtLevel; 632 LegalOperations = Level >= NoIllegalOperations; 633 LegalTypes = Level >= NoIllegalTypes; 634 635 // Add all the dag nodes to the worklist. 636 WorkList.reserve(DAG.allnodes_size()); 637 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 638 E = DAG.allnodes_end(); I != E; ++I) 639 WorkList.push_back(I); 640 641 // Create a dummy node (which is not added to allnodes), that adds a reference 642 // to the root node, preventing it from being deleted, and tracking any 643 // changes of the root. 644 HandleSDNode Dummy(DAG.getRoot()); 645 646 // The root of the dag may dangle to deleted nodes until the dag combiner is 647 // done. Set it to null to avoid confusion. 648 DAG.setRoot(SDValue()); 649 650 // while the worklist isn't empty, inspect the node on the end of it and 651 // try and combine it. 652 while (!WorkList.empty()) { 653 SDNode *N = WorkList.back(); 654 WorkList.pop_back(); 655 656 // If N has no uses, it is dead. Make sure to revisit all N's operands once 657 // N is deleted from the DAG, since they too may now be dead or may have a 658 // reduced number of uses, allowing other xforms. 659 if (N->use_empty() && N != &Dummy) { 660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 661 AddToWorkList(N->getOperand(i).getNode()); 662 663 DAG.DeleteNode(N); 664 continue; 665 } 666 667 SDValue RV = combine(N); 668 669 if (RV.getNode() == 0) 670 continue; 671 672 ++NodesCombined; 673 674 // If we get back the same node we passed in, rather than a new node or 675 // zero, we know that the node must have defined multiple values and 676 // CombineTo was used. Since CombineTo takes care of the worklist 677 // mechanics for us, we have no work to do in this case. 678 if (RV.getNode() == N) 679 continue; 680 681 assert(N->getOpcode() != ISD::DELETED_NODE && 682 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 683 "Node was deleted but visit returned new node!"); 684 685 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 686 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 687 DOUT << '\n'; 688 WorkListRemover DeadNodes(*this); 689 if (N->getNumValues() == RV.getNode()->getNumValues()) 690 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 691 else { 692 assert(N->getValueType(0) == RV.getValueType() && 693 N->getNumValues() == 1 && "Type mismatch"); 694 SDValue OpV = RV; 695 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 696 } 697 698 // Push the new node and any users onto the worklist 699 AddToWorkList(RV.getNode()); 700 AddUsersToWorkList(RV.getNode()); 701 702 // Add any uses of the old node to the worklist in case this node is the 703 // last one that uses them. They may become dead after this node is 704 // deleted. 705 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 706 AddToWorkList(N->getOperand(i).getNode()); 707 708 // Finally, if the node is now dead, remove it from the graph. The node 709 // may not be dead if the replacement process recursively simplified to 710 // something else needing this node. 711 if (N->use_empty()) { 712 // Nodes can be reintroduced into the worklist. Make sure we do not 713 // process a node that has been replaced. 714 removeFromWorkList(N); 715 716 // Finally, since the node is now dead, remove it from the graph. 717 DAG.DeleteNode(N); 718 } 719 } 720 721 // If the root changed (e.g. it was a dead load, update the root). 722 DAG.setRoot(Dummy.getValue()); 723} 724 725SDValue DAGCombiner::visit(SDNode *N) { 726 switch(N->getOpcode()) { 727 default: break; 728 case ISD::TokenFactor: return visitTokenFactor(N); 729 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 730 case ISD::ADD: return visitADD(N); 731 case ISD::SUB: return visitSUB(N); 732 case ISD::ADDC: return visitADDC(N); 733 case ISD::ADDE: return visitADDE(N); 734 case ISD::MUL: return visitMUL(N); 735 case ISD::SDIV: return visitSDIV(N); 736 case ISD::UDIV: return visitUDIV(N); 737 case ISD::SREM: return visitSREM(N); 738 case ISD::UREM: return visitUREM(N); 739 case ISD::MULHU: return visitMULHU(N); 740 case ISD::MULHS: return visitMULHS(N); 741 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 742 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 743 case ISD::SDIVREM: return visitSDIVREM(N); 744 case ISD::UDIVREM: return visitUDIVREM(N); 745 case ISD::AND: return visitAND(N); 746 case ISD::OR: return visitOR(N); 747 case ISD::XOR: return visitXOR(N); 748 case ISD::SHL: return visitSHL(N); 749 case ISD::SRA: return visitSRA(N); 750 case ISD::SRL: return visitSRL(N); 751 case ISD::CTLZ: return visitCTLZ(N); 752 case ISD::CTTZ: return visitCTTZ(N); 753 case ISD::CTPOP: return visitCTPOP(N); 754 case ISD::SELECT: return visitSELECT(N); 755 case ISD::SELECT_CC: return visitSELECT_CC(N); 756 case ISD::SETCC: return visitSETCC(N); 757 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 758 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 759 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 760 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 761 case ISD::TRUNCATE: return visitTRUNCATE(N); 762 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 763 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 764 case ISD::FADD: return visitFADD(N); 765 case ISD::FSUB: return visitFSUB(N); 766 case ISD::FMUL: return visitFMUL(N); 767 case ISD::FDIV: return visitFDIV(N); 768 case ISD::FREM: return visitFREM(N); 769 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 770 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 771 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 772 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 773 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 774 case ISD::FP_ROUND: return visitFP_ROUND(N); 775 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 776 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 777 case ISD::FNEG: return visitFNEG(N); 778 case ISD::FABS: return visitFABS(N); 779 case ISD::BRCOND: return visitBRCOND(N); 780 case ISD::BR_CC: return visitBR_CC(N); 781 case ISD::LOAD: return visitLOAD(N); 782 case ISD::STORE: return visitSTORE(N); 783 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 784 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 785 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 786 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 787 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 788 } 789 return SDValue(); 790} 791 792SDValue DAGCombiner::combine(SDNode *N) { 793 SDValue RV = visit(N); 794 795 // If nothing happened, try a target-specific DAG combine. 796 if (RV.getNode() == 0) { 797 assert(N->getOpcode() != ISD::DELETED_NODE && 798 "Node was deleted but visit returned NULL!"); 799 800 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 801 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 802 803 // Expose the DAG combiner to the target combiner impls. 804 TargetLowering::DAGCombinerInfo 805 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 806 807 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 808 } 809 } 810 811 // If N is a commutative binary node, try commuting it to enable more 812 // sdisel CSE. 813 if (RV.getNode() == 0 && 814 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 815 N->getNumValues() == 1) { 816 SDValue N0 = N->getOperand(0); 817 SDValue N1 = N->getOperand(1); 818 819 // Constant operands are canonicalized to RHS. 820 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 821 SDValue Ops[] = { N1, N0 }; 822 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 823 Ops, 2); 824 if (CSENode) 825 return SDValue(CSENode, 0); 826 } 827 } 828 829 return RV; 830} 831 832/// getInputChainForNode - Given a node, return its input chain if it has one, 833/// otherwise return a null sd operand. 834static SDValue getInputChainForNode(SDNode *N) { 835 if (unsigned NumOps = N->getNumOperands()) { 836 if (N->getOperand(0).getValueType() == MVT::Other) 837 return N->getOperand(0); 838 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 839 return N->getOperand(NumOps-1); 840 for (unsigned i = 1; i < NumOps-1; ++i) 841 if (N->getOperand(i).getValueType() == MVT::Other) 842 return N->getOperand(i); 843 } 844 return SDValue(); 845} 846 847SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 848 // If N has two operands, where one has an input chain equal to the other, 849 // the 'other' chain is redundant. 850 if (N->getNumOperands() == 2) { 851 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 852 return N->getOperand(0); 853 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 854 return N->getOperand(1); 855 } 856 857 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 858 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 859 SmallPtrSet<SDNode*, 16> SeenOps; 860 bool Changed = false; // If we should replace this token factor. 861 862 // Start out with this token factor. 863 TFs.push_back(N); 864 865 // Iterate through token factors. The TFs grows when new token factors are 866 // encountered. 867 for (unsigned i = 0; i < TFs.size(); ++i) { 868 SDNode *TF = TFs[i]; 869 870 // Check each of the operands. 871 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 872 SDValue Op = TF->getOperand(i); 873 874 switch (Op.getOpcode()) { 875 case ISD::EntryToken: 876 // Entry tokens don't need to be added to the list. They are 877 // rededundant. 878 Changed = true; 879 break; 880 881 case ISD::TokenFactor: 882 if ((CombinerAA || Op.hasOneUse()) && 883 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 884 // Queue up for processing. 885 TFs.push_back(Op.getNode()); 886 // Clean up in case the token factor is removed. 887 AddToWorkList(Op.getNode()); 888 Changed = true; 889 break; 890 } 891 // Fall thru 892 893 default: 894 // Only add if it isn't already in the list. 895 if (SeenOps.insert(Op.getNode())) 896 Ops.push_back(Op); 897 else 898 Changed = true; 899 break; 900 } 901 } 902 } 903 904 SDValue Result; 905 906 // If we've change things around then replace token factor. 907 if (Changed) { 908 if (Ops.empty()) { 909 // The entry token is the only possible outcome. 910 Result = DAG.getEntryNode(); 911 } else { 912 // New and improved token factor. 913 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 914 MVT::Other, &Ops[0], Ops.size()); 915 } 916 917 // Don't add users to work list. 918 return CombineTo(N, Result, false); 919 } 920 921 return Result; 922} 923 924/// MERGE_VALUES can always be eliminated. 925SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 926 WorkListRemover DeadNodes(*this); 927 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 928 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 929 &DeadNodes); 930 removeFromWorkList(N); 931 DAG.DeleteNode(N); 932 return SDValue(N, 0); // Return N so it doesn't get rechecked! 933} 934 935static 936SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 937 SelectionDAG &DAG) { 938 MVT VT = N0.getValueType(); 939 SDValue N00 = N0.getOperand(0); 940 SDValue N01 = N0.getOperand(1); 941 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 942 943 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 944 isa<ConstantSDNode>(N00.getOperand(1))) { 945 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 946 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 947 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 948 N00.getOperand(0), N01), 949 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 950 N00.getOperand(1), N01)); 951 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 952 } 953 954 return SDValue(); 955} 956 957SDValue DAGCombiner::visitADD(SDNode *N) { 958 SDValue N0 = N->getOperand(0); 959 SDValue N1 = N->getOperand(1); 960 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 961 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 962 MVT VT = N0.getValueType(); 963 964 // fold vector ops 965 if (VT.isVector()) { 966 SDValue FoldedVOp = SimplifyVBinOp(N); 967 if (FoldedVOp.getNode()) return FoldedVOp; 968 } 969 970 // fold (add x, undef) -> undef 971 if (N0.getOpcode() == ISD::UNDEF) 972 return N0; 973 if (N1.getOpcode() == ISD::UNDEF) 974 return N1; 975 // fold (add c1, c2) -> c1+c2 976 if (N0C && N1C) 977 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 978 // canonicalize constant to RHS 979 if (N0C && !N1C) 980 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 981 // fold (add x, 0) -> x 982 if (N1C && N1C->isNullValue()) 983 return N0; 984 // fold (add Sym, c) -> Sym+c 985 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 986 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 987 GA->getOpcode() == ISD::GlobalAddress) 988 return DAG.getGlobalAddress(GA->getGlobal(), VT, 989 GA->getOffset() + 990 (uint64_t)N1C->getSExtValue()); 991 // fold ((c1-A)+c2) -> (c1+c2)-A 992 if (N1C && N0.getOpcode() == ISD::SUB) 993 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 994 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 995 DAG.getConstant(N1C->getAPIntValue()+ 996 N0C->getAPIntValue(), VT), 997 N0.getOperand(1)); 998 // reassociate add 999 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1000 if (RADD.getNode() != 0) 1001 return RADD; 1002 // fold ((0-A) + B) -> B-A 1003 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1004 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1005 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1006 // fold (A + (0-B)) -> A-B 1007 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1008 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1009 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1010 // fold (A+(B-A)) -> B 1011 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1012 return N1.getOperand(0); 1013 // fold ((B-A)+A) -> B 1014 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1015 return N0.getOperand(0); 1016 // fold (A+(B-(A+C))) to (B-C) 1017 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1018 N0 == N1.getOperand(1).getOperand(0)) 1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1020 N1.getOperand(1).getOperand(1)); 1021 // fold (A+(B-(C+A))) to (B-C) 1022 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1023 N0 == N1.getOperand(1).getOperand(1)) 1024 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1025 N1.getOperand(1).getOperand(0)); 1026 // fold (A+((B-A)+or-C)) to (B+or-C) 1027 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1028 N1.getOperand(0).getOpcode() == ISD::SUB && 1029 N0 == N1.getOperand(0).getOperand(1)) 1030 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1031 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1032 1033 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1034 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1035 SDValue N00 = N0.getOperand(0); 1036 SDValue N01 = N0.getOperand(1); 1037 SDValue N10 = N1.getOperand(0); 1038 SDValue N11 = N1.getOperand(1); 1039 1040 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1041 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1042 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1043 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1044 } 1045 1046 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1047 return SDValue(N, 0); 1048 1049 // fold (a+b) -> (a|b) iff a and b share no bits. 1050 if (VT.isInteger() && !VT.isVector()) { 1051 APInt LHSZero, LHSOne; 1052 APInt RHSZero, RHSOne; 1053 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1054 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1055 1056 if (LHSZero.getBoolValue()) { 1057 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1058 1059 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1060 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1061 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1062 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1063 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1064 } 1065 } 1066 1067 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1068 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1069 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1070 if (Result.getNode()) return Result; 1071 } 1072 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1073 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1074 if (Result.getNode()) return Result; 1075 } 1076 1077 return SDValue(); 1078} 1079 1080SDValue DAGCombiner::visitADDC(SDNode *N) { 1081 SDValue N0 = N->getOperand(0); 1082 SDValue N1 = N->getOperand(1); 1083 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1085 MVT VT = N0.getValueType(); 1086 1087 // If the flag result is dead, turn this into an ADD. 1088 if (N->hasNUsesOfValue(0, 1)) 1089 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1090 DAG.getNode(ISD::CARRY_FALSE, 1091 N->getDebugLoc(), MVT::Flag)); 1092 1093 // canonicalize constant to RHS. 1094 if (N0C && !N1C) 1095 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1096 1097 // fold (addc x, 0) -> x + no carry out 1098 if (N1C && N1C->isNullValue()) 1099 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1100 N->getDebugLoc(), MVT::Flag)); 1101 1102 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1103 APInt LHSZero, LHSOne; 1104 APInt RHSZero, RHSOne; 1105 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1106 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1107 1108 if (LHSZero.getBoolValue()) { 1109 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1110 1111 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1112 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1113 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1114 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1115 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1116 DAG.getNode(ISD::CARRY_FALSE, 1117 N->getDebugLoc(), MVT::Flag)); 1118 } 1119 1120 return SDValue(); 1121} 1122 1123SDValue DAGCombiner::visitADDE(SDNode *N) { 1124 SDValue N0 = N->getOperand(0); 1125 SDValue N1 = N->getOperand(1); 1126 SDValue CarryIn = N->getOperand(2); 1127 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1128 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1129 1130 // canonicalize constant to RHS 1131 if (N0C && !N1C) 1132 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1133 N1, N0, CarryIn); 1134 1135 // fold (adde x, y, false) -> (addc x, y) 1136 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1137 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1138 1139 return SDValue(); 1140} 1141 1142SDValue DAGCombiner::visitSUB(SDNode *N) { 1143 SDValue N0 = N->getOperand(0); 1144 SDValue N1 = N->getOperand(1); 1145 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1146 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1147 MVT VT = N0.getValueType(); 1148 1149 // fold vector ops 1150 if (VT.isVector()) { 1151 SDValue FoldedVOp = SimplifyVBinOp(N); 1152 if (FoldedVOp.getNode()) return FoldedVOp; 1153 } 1154 1155 // fold (sub x, x) -> 0 1156 if (N0 == N1) 1157 return DAG.getConstant(0, N->getValueType(0)); 1158 // fold (sub c1, c2) -> c1-c2 1159 if (N0C && N1C) 1160 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1161 // fold (sub x, c) -> (add x, -c) 1162 if (N1C) 1163 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1164 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1165 // fold (A+B)-A -> B 1166 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1167 return N0.getOperand(1); 1168 // fold (A+B)-B -> A 1169 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1170 return N0.getOperand(0); 1171 // fold ((A+(B+or-C))-B) -> A+or-C 1172 if (N0.getOpcode() == ISD::ADD && 1173 (N0.getOperand(1).getOpcode() == ISD::SUB || 1174 N0.getOperand(1).getOpcode() == ISD::ADD) && 1175 N0.getOperand(1).getOperand(0) == N1) 1176 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1177 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1178 // fold ((A+(C+B))-B) -> A+C 1179 if (N0.getOpcode() == ISD::ADD && 1180 N0.getOperand(1).getOpcode() == ISD::ADD && 1181 N0.getOperand(1).getOperand(1) == N1) 1182 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1183 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1184 // fold ((A-(B-C))-C) -> A-B 1185 if (N0.getOpcode() == ISD::SUB && 1186 N0.getOperand(1).getOpcode() == ISD::SUB && 1187 N0.getOperand(1).getOperand(1) == N1) 1188 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1189 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1190 1191 // If either operand of a sub is undef, the result is undef 1192 if (N0.getOpcode() == ISD::UNDEF) 1193 return N0; 1194 if (N1.getOpcode() == ISD::UNDEF) 1195 return N1; 1196 1197 // If the relocation model supports it, consider symbol offsets. 1198 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1199 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1200 // fold (sub Sym, c) -> Sym-c 1201 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1202 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1203 GA->getOffset() - 1204 (uint64_t)N1C->getSExtValue()); 1205 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1206 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1207 if (GA->getGlobal() == GB->getGlobal()) 1208 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1209 VT); 1210 } 1211 1212 return SDValue(); 1213} 1214 1215SDValue DAGCombiner::visitMUL(SDNode *N) { 1216 SDValue N0 = N->getOperand(0); 1217 SDValue N1 = N->getOperand(1); 1218 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1219 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1220 MVT VT = N0.getValueType(); 1221 1222 // fold vector ops 1223 if (VT.isVector()) { 1224 SDValue FoldedVOp = SimplifyVBinOp(N); 1225 if (FoldedVOp.getNode()) return FoldedVOp; 1226 } 1227 1228 // fold (mul x, undef) -> 0 1229 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1230 return DAG.getConstant(0, VT); 1231 // fold (mul c1, c2) -> c1*c2 1232 if (N0C && N1C) 1233 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1234 // canonicalize constant to RHS 1235 if (N0C && !N1C) 1236 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1237 // fold (mul x, 0) -> 0 1238 if (N1C && N1C->isNullValue()) 1239 return N1; 1240 // fold (mul x, -1) -> 0-x 1241 if (N1C && N1C->isAllOnesValue()) 1242 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1243 DAG.getConstant(0, VT), N0); 1244 // fold (mul x, (1 << c)) -> x << c 1245 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1246 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1247 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1248 getShiftAmountTy())); 1249 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1250 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1251 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1252 // FIXME: If the input is something that is easily negated (e.g. a 1253 // single-use add), we should put the negate there. 1254 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1255 DAG.getConstant(0, VT), 1256 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1257 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1258 } 1259 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1260 if (N1C && N0.getOpcode() == ISD::SHL && 1261 isa<ConstantSDNode>(N0.getOperand(1))) { 1262 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1263 N1, N0.getOperand(1)); 1264 AddToWorkList(C3.getNode()); 1265 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1266 N0.getOperand(0), C3); 1267 } 1268 1269 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1270 // use. 1271 { 1272 SDValue Sh(0,0), Y(0,0); 1273 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1274 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1275 N0.getNode()->hasOneUse()) { 1276 Sh = N0; Y = N1; 1277 } else if (N1.getOpcode() == ISD::SHL && 1278 isa<ConstantSDNode>(N1.getOperand(1)) && 1279 N1.getNode()->hasOneUse()) { 1280 Sh = N1; Y = N0; 1281 } 1282 1283 if (Sh.getNode()) { 1284 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1285 Sh.getOperand(0), Y); 1286 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1287 Mul, Sh.getOperand(1)); 1288 } 1289 } 1290 1291 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1292 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1293 isa<ConstantSDNode>(N0.getOperand(1))) 1294 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1295 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1296 N0.getOperand(0), N1), 1297 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1298 N0.getOperand(1), N1)); 1299 1300 // reassociate mul 1301 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1302 if (RMUL.getNode() != 0) 1303 return RMUL; 1304 1305 return SDValue(); 1306} 1307 1308SDValue DAGCombiner::visitSDIV(SDNode *N) { 1309 SDValue N0 = N->getOperand(0); 1310 SDValue N1 = N->getOperand(1); 1311 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1312 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1313 MVT VT = N->getValueType(0); 1314 1315 // fold vector ops 1316 if (VT.isVector()) { 1317 SDValue FoldedVOp = SimplifyVBinOp(N); 1318 if (FoldedVOp.getNode()) return FoldedVOp; 1319 } 1320 1321 // fold (sdiv c1, c2) -> c1/c2 1322 if (N0C && N1C && !N1C->isNullValue()) 1323 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1324 // fold (sdiv X, 1) -> X 1325 if (N1C && N1C->getSExtValue() == 1LL) 1326 return N0; 1327 // fold (sdiv X, -1) -> 0-X 1328 if (N1C && N1C->isAllOnesValue()) 1329 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1330 DAG.getConstant(0, VT), N0); 1331 // If we know the sign bits of both operands are zero, strength reduce to a 1332 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1333 if (!VT.isVector()) { 1334 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1335 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1336 N0, N1); 1337 } 1338 // fold (sdiv X, pow2) -> simple ops after legalize 1339 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1340 (isPowerOf2_64(N1C->getSExtValue()) || 1341 isPowerOf2_64(-N1C->getSExtValue()))) { 1342 // If dividing by powers of two is cheap, then don't perform the following 1343 // fold. 1344 if (TLI.isPow2DivCheap()) 1345 return SDValue(); 1346 1347 int64_t pow2 = N1C->getSExtValue(); 1348 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1349 unsigned lg2 = Log2_64(abs2); 1350 1351 // Splat the sign bit into the register 1352 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1353 DAG.getConstant(VT.getSizeInBits()-1, 1354 getShiftAmountTy())); 1355 AddToWorkList(SGN.getNode()); 1356 1357 // Add (N0 < 0) ? abs2 - 1 : 0; 1358 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1359 DAG.getConstant(VT.getSizeInBits() - lg2, 1360 getShiftAmountTy())); 1361 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1362 AddToWorkList(SRL.getNode()); 1363 AddToWorkList(ADD.getNode()); // Divide by pow2 1364 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1365 DAG.getConstant(lg2, getShiftAmountTy())); 1366 1367 // If we're dividing by a positive value, we're done. Otherwise, we must 1368 // negate the result. 1369 if (pow2 > 0) 1370 return SRA; 1371 1372 AddToWorkList(SRA.getNode()); 1373 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1374 DAG.getConstant(0, VT), SRA); 1375 } 1376 1377 // if integer divide is expensive and we satisfy the requirements, emit an 1378 // alternate sequence. 1379 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1380 !TLI.isIntDivCheap()) { 1381 SDValue Op = BuildSDIV(N); 1382 if (Op.getNode()) return Op; 1383 } 1384 1385 // undef / X -> 0 1386 if (N0.getOpcode() == ISD::UNDEF) 1387 return DAG.getConstant(0, VT); 1388 // X / undef -> undef 1389 if (N1.getOpcode() == ISD::UNDEF) 1390 return N1; 1391 1392 return SDValue(); 1393} 1394 1395SDValue DAGCombiner::visitUDIV(SDNode *N) { 1396 SDValue N0 = N->getOperand(0); 1397 SDValue N1 = N->getOperand(1); 1398 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1400 MVT VT = N->getValueType(0); 1401 1402 // fold vector ops 1403 if (VT.isVector()) { 1404 SDValue FoldedVOp = SimplifyVBinOp(N); 1405 if (FoldedVOp.getNode()) return FoldedVOp; 1406 } 1407 1408 // fold (udiv c1, c2) -> c1/c2 1409 if (N0C && N1C && !N1C->isNullValue()) 1410 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1411 // fold (udiv x, (1 << c)) -> x >>u c 1412 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1413 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1414 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1415 getShiftAmountTy())); 1416 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1417 if (N1.getOpcode() == ISD::SHL) { 1418 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1419 if (SHC->getAPIntValue().isPowerOf2()) { 1420 MVT ADDVT = N1.getOperand(1).getValueType(); 1421 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1422 N1.getOperand(1), 1423 DAG.getConstant(SHC->getAPIntValue() 1424 .logBase2(), 1425 ADDVT)); 1426 AddToWorkList(Add.getNode()); 1427 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1428 } 1429 } 1430 } 1431 // fold (udiv x, c) -> alternate 1432 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1433 SDValue Op = BuildUDIV(N); 1434 if (Op.getNode()) return Op; 1435 } 1436 1437 // undef / X -> 0 1438 if (N0.getOpcode() == ISD::UNDEF) 1439 return DAG.getConstant(0, VT); 1440 // X / undef -> undef 1441 if (N1.getOpcode() == ISD::UNDEF) 1442 return N1; 1443 1444 return SDValue(); 1445} 1446 1447SDValue DAGCombiner::visitSREM(SDNode *N) { 1448 SDValue N0 = N->getOperand(0); 1449 SDValue N1 = N->getOperand(1); 1450 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1451 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1452 MVT VT = N->getValueType(0); 1453 1454 // fold (srem c1, c2) -> c1%c2 1455 if (N0C && N1C && !N1C->isNullValue()) 1456 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1457 // If we know the sign bits of both operands are zero, strength reduce to a 1458 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1459 if (!VT.isVector()) { 1460 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1461 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1462 } 1463 1464 // If X/C can be simplified by the division-by-constant logic, lower 1465 // X%C to the equivalent of X-X/C*C. 1466 if (N1C && !N1C->isNullValue()) { 1467 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1468 AddToWorkList(Div.getNode()); 1469 SDValue OptimizedDiv = combine(Div.getNode()); 1470 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1471 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1472 OptimizedDiv, N1); 1473 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1474 AddToWorkList(Mul.getNode()); 1475 return Sub; 1476 } 1477 } 1478 1479 // undef % X -> 0 1480 if (N0.getOpcode() == ISD::UNDEF) 1481 return DAG.getConstant(0, VT); 1482 // X % undef -> undef 1483 if (N1.getOpcode() == ISD::UNDEF) 1484 return N1; 1485 1486 return SDValue(); 1487} 1488 1489SDValue DAGCombiner::visitUREM(SDNode *N) { 1490 SDValue N0 = N->getOperand(0); 1491 SDValue N1 = N->getOperand(1); 1492 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1493 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1494 MVT VT = N->getValueType(0); 1495 1496 // fold (urem c1, c2) -> c1%c2 1497 if (N0C && N1C && !N1C->isNullValue()) 1498 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1499 // fold (urem x, pow2) -> (and x, pow2-1) 1500 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1501 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1502 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1503 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1504 if (N1.getOpcode() == ISD::SHL) { 1505 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1506 if (SHC->getAPIntValue().isPowerOf2()) { 1507 SDValue Add = 1508 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1509 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1510 VT)); 1511 AddToWorkList(Add.getNode()); 1512 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1513 } 1514 } 1515 } 1516 1517 // If X/C can be simplified by the division-by-constant logic, lower 1518 // X%C to the equivalent of X-X/C*C. 1519 if (N1C && !N1C->isNullValue()) { 1520 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1521 AddToWorkList(Div.getNode()); 1522 SDValue OptimizedDiv = combine(Div.getNode()); 1523 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1524 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1525 OptimizedDiv, N1); 1526 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1527 AddToWorkList(Mul.getNode()); 1528 return Sub; 1529 } 1530 } 1531 1532 // undef % X -> 0 1533 if (N0.getOpcode() == ISD::UNDEF) 1534 return DAG.getConstant(0, VT); 1535 // X % undef -> undef 1536 if (N1.getOpcode() == ISD::UNDEF) 1537 return N1; 1538 1539 return SDValue(); 1540} 1541 1542SDValue DAGCombiner::visitMULHS(SDNode *N) { 1543 SDValue N0 = N->getOperand(0); 1544 SDValue N1 = N->getOperand(1); 1545 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1546 MVT VT = N->getValueType(0); 1547 1548 // fold (mulhs x, 0) -> 0 1549 if (N1C && N1C->isNullValue()) 1550 return N1; 1551 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1552 if (N1C && N1C->getAPIntValue() == 1) 1553 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1554 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1555 getShiftAmountTy())); 1556 // fold (mulhs x, undef) -> 0 1557 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1558 return DAG.getConstant(0, VT); 1559 1560 return SDValue(); 1561} 1562 1563SDValue DAGCombiner::visitMULHU(SDNode *N) { 1564 SDValue N0 = N->getOperand(0); 1565 SDValue N1 = N->getOperand(1); 1566 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1567 MVT VT = N->getValueType(0); 1568 1569 // fold (mulhu x, 0) -> 0 1570 if (N1C && N1C->isNullValue()) 1571 return N1; 1572 // fold (mulhu x, 1) -> 0 1573 if (N1C && N1C->getAPIntValue() == 1) 1574 return DAG.getConstant(0, N0.getValueType()); 1575 // fold (mulhu x, undef) -> 0 1576 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1577 return DAG.getConstant(0, VT); 1578 1579 return SDValue(); 1580} 1581 1582/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1583/// compute two values. LoOp and HiOp give the opcodes for the two computations 1584/// that are being performed. Return true if a simplification was made. 1585/// 1586SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1587 unsigned HiOp) { 1588 // If the high half is not needed, just compute the low half. 1589 bool HiExists = N->hasAnyUseOfValue(1); 1590 if (!HiExists && 1591 (!LegalOperations || 1592 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1593 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1594 N->op_begin(), N->getNumOperands()); 1595 return CombineTo(N, Res, Res); 1596 } 1597 1598 // If the low half is not needed, just compute the high half. 1599 bool LoExists = N->hasAnyUseOfValue(0); 1600 if (!LoExists && 1601 (!LegalOperations || 1602 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1603 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1604 N->op_begin(), N->getNumOperands()); 1605 return CombineTo(N, Res, Res); 1606 } 1607 1608 // If both halves are used, return as it is. 1609 if (LoExists && HiExists) 1610 return SDValue(); 1611 1612 // If the two computed results can be simplified separately, separate them. 1613 if (LoExists) { 1614 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1615 N->op_begin(), N->getNumOperands()); 1616 AddToWorkList(Lo.getNode()); 1617 SDValue LoOpt = combine(Lo.getNode()); 1618 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1619 (!LegalOperations || 1620 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1621 return CombineTo(N, LoOpt, LoOpt); 1622 } 1623 1624 if (HiExists) { 1625 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1626 N->op_begin(), N->getNumOperands()); 1627 AddToWorkList(Hi.getNode()); 1628 SDValue HiOpt = combine(Hi.getNode()); 1629 if (HiOpt.getNode() && HiOpt != Hi && 1630 (!LegalOperations || 1631 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1632 return CombineTo(N, HiOpt, HiOpt); 1633 } 1634 1635 return SDValue(); 1636} 1637 1638SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1639 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1640 if (Res.getNode()) return Res; 1641 1642 return SDValue(); 1643} 1644 1645SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1646 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1647 if (Res.getNode()) return Res; 1648 1649 return SDValue(); 1650} 1651 1652SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1653 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1654 if (Res.getNode()) return Res; 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1660 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1661 if (Res.getNode()) return Res; 1662 1663 return SDValue(); 1664} 1665 1666/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1667/// two operands of the same opcode, try to simplify it. 1668SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1669 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1670 MVT VT = N0.getValueType(); 1671 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1672 1673 // For each of OP in AND/OR/XOR: 1674 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1675 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1676 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1677 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1678 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1679 N0.getOpcode() == ISD::SIGN_EXTEND || 1680 (N0.getOpcode() == ISD::TRUNCATE && 1681 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1682 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1683 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1684 N0.getOperand(0).getValueType(), 1685 N0.getOperand(0), N1.getOperand(0)); 1686 AddToWorkList(ORNode.getNode()); 1687 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1688 } 1689 1690 // For each of OP in SHL/SRL/SRA/AND... 1691 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1692 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1693 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1694 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1695 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1696 N0.getOperand(1) == N1.getOperand(1)) { 1697 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1698 N0.getOperand(0).getValueType(), 1699 N0.getOperand(0), N1.getOperand(0)); 1700 AddToWorkList(ORNode.getNode()); 1701 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1702 ORNode, N0.getOperand(1)); 1703 } 1704 1705 return SDValue(); 1706} 1707 1708SDValue DAGCombiner::visitAND(SDNode *N) { 1709 SDValue N0 = N->getOperand(0); 1710 SDValue N1 = N->getOperand(1); 1711 SDValue LL, LR, RL, RR, CC0, CC1; 1712 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1713 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1714 MVT VT = N1.getValueType(); 1715 unsigned BitWidth = VT.getSizeInBits(); 1716 1717 // fold vector ops 1718 if (VT.isVector()) { 1719 SDValue FoldedVOp = SimplifyVBinOp(N); 1720 if (FoldedVOp.getNode()) return FoldedVOp; 1721 } 1722 1723 // fold (and x, undef) -> 0 1724 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1725 return DAG.getConstant(0, VT); 1726 // fold (and c1, c2) -> c1&c2 1727 if (N0C && N1C) 1728 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1729 // canonicalize constant to RHS 1730 if (N0C && !N1C) 1731 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1732 // fold (and x, -1) -> x 1733 if (N1C && N1C->isAllOnesValue()) 1734 return N0; 1735 // if (and x, c) is known to be zero, return 0 1736 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1737 APInt::getAllOnesValue(BitWidth))) 1738 return DAG.getConstant(0, VT); 1739 // reassociate and 1740 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1741 if (RAND.getNode() != 0) 1742 return RAND; 1743 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1744 if (N1C && N0.getOpcode() == ISD::OR) 1745 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1746 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1747 return N1; 1748 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1749 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1750 SDValue N0Op0 = N0.getOperand(0); 1751 APInt Mask = ~N1C->getAPIntValue(); 1752 Mask.trunc(N0Op0.getValueSizeInBits()); 1753 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1754 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1755 N0.getValueType(), N0Op0); 1756 1757 // Replace uses of the AND with uses of the Zero extend node. 1758 CombineTo(N, Zext); 1759 1760 // We actually want to replace all uses of the any_extend with the 1761 // zero_extend, to avoid duplicating things. This will later cause this 1762 // AND to be folded. 1763 CombineTo(N0.getNode(), Zext); 1764 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1765 } 1766 } 1767 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1768 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1769 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1770 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1771 1772 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1773 LL.getValueType().isInteger()) { 1774 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1775 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1776 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1777 LR.getValueType(), LL, RL); 1778 AddToWorkList(ORNode.getNode()); 1779 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1780 } 1781 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1782 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1783 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1784 LR.getValueType(), LL, RL); 1785 AddToWorkList(ANDNode.getNode()); 1786 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1787 } 1788 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1789 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1790 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1791 LR.getValueType(), LL, RL); 1792 AddToWorkList(ORNode.getNode()); 1793 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1794 } 1795 } 1796 // canonicalize equivalent to ll == rl 1797 if (LL == RR && LR == RL) { 1798 Op1 = ISD::getSetCCSwappedOperands(Op1); 1799 std::swap(RL, RR); 1800 } 1801 if (LL == RL && LR == RR) { 1802 bool isInteger = LL.getValueType().isInteger(); 1803 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1804 if (Result != ISD::SETCC_INVALID && 1805 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1806 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1807 LL, LR, Result); 1808 } 1809 } 1810 1811 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1812 if (N0.getOpcode() == N1.getOpcode()) { 1813 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1814 if (Tmp.getNode()) return Tmp; 1815 } 1816 1817 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1818 // fold (and (sra)) -> (and (srl)) when possible. 1819 if (!VT.isVector() && 1820 SimplifyDemandedBits(SDValue(N, 0))) 1821 return SDValue(N, 0); 1822 // fold (zext_inreg (extload x)) -> (zextload x) 1823 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1824 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1825 MVT EVT = LN0->getMemoryVT(); 1826 // If we zero all the possible extended bits, then we can turn this into 1827 // a zextload if we are running before legalize or the operation is legal. 1828 unsigned BitWidth = N1.getValueSizeInBits(); 1829 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1830 BitWidth - EVT.getSizeInBits())) && 1831 ((!LegalOperations && !LN0->isVolatile()) || 1832 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1833 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1834 LN0->getChain(), LN0->getBasePtr(), 1835 LN0->getSrcValue(), 1836 LN0->getSrcValueOffset(), EVT, 1837 LN0->isVolatile(), LN0->getAlignment()); 1838 AddToWorkList(N); 1839 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1840 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1841 } 1842 } 1843 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1844 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1845 N0.hasOneUse()) { 1846 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1847 MVT EVT = LN0->getMemoryVT(); 1848 // If we zero all the possible extended bits, then we can turn this into 1849 // a zextload if we are running before legalize or the operation is legal. 1850 unsigned BitWidth = N1.getValueSizeInBits(); 1851 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1852 BitWidth - EVT.getSizeInBits())) && 1853 ((!LegalOperations && !LN0->isVolatile()) || 1854 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1855 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1856 LN0->getChain(), 1857 LN0->getBasePtr(), LN0->getSrcValue(), 1858 LN0->getSrcValueOffset(), EVT, 1859 LN0->isVolatile(), LN0->getAlignment()); 1860 AddToWorkList(N); 1861 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1862 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1863 } 1864 } 1865 1866 // fold (and (load x), 255) -> (zextload x, i8) 1867 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1868 if (N1C && N0.getOpcode() == ISD::LOAD) { 1869 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1870 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1871 LN0->isUnindexed() && N0.hasOneUse() && 1872 // Do not change the width of a volatile load. 1873 !LN0->isVolatile()) { 1874 MVT EVT = MVT::Other; 1875 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1876 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1877 EVT = MVT::getIntegerVT(ActiveBits); 1878 1879 MVT LoadedVT = LN0->getMemoryVT(); 1880 1881 // Do not generate loads of non-round integer types since these can 1882 // be expensive (and would be wrong if the type is not byte sized). 1883 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1884 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1885 MVT PtrType = N0.getOperand(1).getValueType(); 1886 1887 // For big endian targets, we need to add an offset to the pointer to 1888 // load the correct bytes. For little endian systems, we merely need to 1889 // read fewer bytes from the same pointer. 1890 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1891 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1892 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1893 unsigned Alignment = LN0->getAlignment(); 1894 SDValue NewPtr = LN0->getBasePtr(); 1895 1896 if (TLI.isBigEndian()) { 1897 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1898 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1899 Alignment = MinAlign(Alignment, PtrOff); 1900 } 1901 1902 AddToWorkList(NewPtr.getNode()); 1903 SDValue Load = 1904 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1905 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1906 EVT, LN0->isVolatile(), Alignment); 1907 AddToWorkList(N); 1908 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1909 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1910 } 1911 } 1912 } 1913 1914 return SDValue(); 1915} 1916 1917SDValue DAGCombiner::visitOR(SDNode *N) { 1918 SDValue N0 = N->getOperand(0); 1919 SDValue N1 = N->getOperand(1); 1920 SDValue LL, LR, RL, RR, CC0, CC1; 1921 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1922 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1923 MVT VT = N1.getValueType(); 1924 1925 // fold vector ops 1926 if (VT.isVector()) { 1927 SDValue FoldedVOp = SimplifyVBinOp(N); 1928 if (FoldedVOp.getNode()) return FoldedVOp; 1929 } 1930 1931 // fold (or x, undef) -> -1 1932 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1933 return DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 1934 // fold (or c1, c2) -> c1|c2 1935 if (N0C && N1C) 1936 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1937 // canonicalize constant to RHS 1938 if (N0C && !N1C) 1939 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1940 // fold (or x, 0) -> x 1941 if (N1C && N1C->isNullValue()) 1942 return N0; 1943 // fold (or x, -1) -> -1 1944 if (N1C && N1C->isAllOnesValue()) 1945 return N1; 1946 // fold (or x, c) -> c iff (x & ~c) == 0 1947 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1948 return N1; 1949 // reassociate or 1950 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1951 if (ROR.getNode() != 0) 1952 return ROR; 1953 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1954 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1955 isa<ConstantSDNode>(N0.getOperand(1))) { 1956 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1957 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1958 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1959 N0.getOperand(0), N1), 1960 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1961 } 1962 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1963 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1964 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1965 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1966 1967 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1968 LL.getValueType().isInteger()) { 1969 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1970 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1971 if (cast<ConstantSDNode>(LR)->isNullValue() && 1972 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1973 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1974 LR.getValueType(), LL, RL); 1975 AddToWorkList(ORNode.getNode()); 1976 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1977 } 1978 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 1979 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 1980 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1981 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1982 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 1983 LR.getValueType(), LL, RL); 1984 AddToWorkList(ANDNode.getNode()); 1985 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1986 } 1987 } 1988 // canonicalize equivalent to ll == rl 1989 if (LL == RR && LR == RL) { 1990 Op1 = ISD::getSetCCSwappedOperands(Op1); 1991 std::swap(RL, RR); 1992 } 1993 if (LL == RL && LR == RR) { 1994 bool isInteger = LL.getValueType().isInteger(); 1995 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1996 if (Result != ISD::SETCC_INVALID && 1997 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1998 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1999 LL, LR, Result); 2000 } 2001 } 2002 2003 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2004 if (N0.getOpcode() == N1.getOpcode()) { 2005 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2006 if (Tmp.getNode()) return Tmp; 2007 } 2008 2009 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2010 if (N0.getOpcode() == ISD::AND && 2011 N1.getOpcode() == ISD::AND && 2012 N0.getOperand(1).getOpcode() == ISD::Constant && 2013 N1.getOperand(1).getOpcode() == ISD::Constant && 2014 // Don't increase # computations. 2015 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2016 // We can only do this xform if we know that bits from X that are set in C2 2017 // but not in C1 are already zero. Likewise for Y. 2018 const APInt &LHSMask = 2019 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2020 const APInt &RHSMask = 2021 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2022 2023 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2024 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2025 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2026 N0.getOperand(0), N1.getOperand(0)); 2027 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2028 DAG.getConstant(LHSMask | RHSMask, VT)); 2029 } 2030 } 2031 2032 // See if this is some rotate idiom. 2033 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2034 return SDValue(Rot, 0); 2035 2036 return SDValue(); 2037} 2038 2039/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2040static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2041 if (Op.getOpcode() == ISD::AND) { 2042 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2043 Mask = Op.getOperand(1); 2044 Op = Op.getOperand(0); 2045 } else { 2046 return false; 2047 } 2048 } 2049 2050 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2051 Shift = Op; 2052 return true; 2053 } 2054 2055 return false; 2056} 2057 2058// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2059// idioms for rotate, and if the target supports rotation instructions, generate 2060// a rot[lr]. 2061SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2062 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2063 MVT VT = LHS.getValueType(); 2064 if (!TLI.isTypeLegal(VT)) return 0; 2065 2066 // The target must have at least one rotate flavor. 2067 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2068 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2069 if (!HasROTL && !HasROTR) return 0; 2070 2071 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2072 SDValue LHSShift; // The shift. 2073 SDValue LHSMask; // AND value if any. 2074 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2075 return 0; // Not part of a rotate. 2076 2077 SDValue RHSShift; // The shift. 2078 SDValue RHSMask; // AND value if any. 2079 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2080 return 0; // Not part of a rotate. 2081 2082 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2083 return 0; // Not shifting the same value. 2084 2085 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2086 return 0; // Shifts must disagree. 2087 2088 // Canonicalize shl to left side in a shl/srl pair. 2089 if (RHSShift.getOpcode() == ISD::SHL) { 2090 std::swap(LHS, RHS); 2091 std::swap(LHSShift, RHSShift); 2092 std::swap(LHSMask , RHSMask ); 2093 } 2094 2095 unsigned OpSizeInBits = VT.getSizeInBits(); 2096 SDValue LHSShiftArg = LHSShift.getOperand(0); 2097 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2098 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2099 2100 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2101 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2102 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2103 RHSShiftAmt.getOpcode() == ISD::Constant) { 2104 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2105 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2106 if ((LShVal + RShVal) != OpSizeInBits) 2107 return 0; 2108 2109 SDValue Rot; 2110 if (HasROTL) 2111 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2112 else 2113 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2114 2115 // If there is an AND of either shifted operand, apply it to the result. 2116 if (LHSMask.getNode() || RHSMask.getNode()) { 2117 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2118 2119 if (LHSMask.getNode()) { 2120 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2121 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2122 } 2123 if (RHSMask.getNode()) { 2124 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2125 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2126 } 2127 2128 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2129 } 2130 2131 return Rot.getNode(); 2132 } 2133 2134 // If there is a mask here, and we have a variable shift, we can't be sure 2135 // that we're masking out the right stuff. 2136 if (LHSMask.getNode() || RHSMask.getNode()) 2137 return 0; 2138 2139 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2140 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2141 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2142 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2143 if (ConstantSDNode *SUBC = 2144 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2145 if (SUBC->getAPIntValue() == OpSizeInBits) { 2146 if (HasROTL) 2147 return DAG.getNode(ISD::ROTL, DL, VT, 2148 LHSShiftArg, LHSShiftAmt).getNode(); 2149 else 2150 return DAG.getNode(ISD::ROTR, DL, VT, 2151 LHSShiftArg, RHSShiftAmt).getNode(); 2152 } 2153 } 2154 } 2155 2156 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2157 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2158 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2159 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2160 if (ConstantSDNode *SUBC = 2161 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2162 if (SUBC->getAPIntValue() == OpSizeInBits) { 2163 if (HasROTR) 2164 return DAG.getNode(ISD::ROTR, DL, VT, 2165 LHSShiftArg, RHSShiftAmt).getNode(); 2166 else 2167 return DAG.getNode(ISD::ROTL, DL, VT, 2168 LHSShiftArg, LHSShiftAmt).getNode(); 2169 } 2170 } 2171 } 2172 2173 // Look for sign/zext/any-extended or truncate cases: 2174 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2175 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2176 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2177 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2178 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2179 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2180 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2181 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2182 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2183 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2184 if (RExtOp0.getOpcode() == ISD::SUB && 2185 RExtOp0.getOperand(1) == LExtOp0) { 2186 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2187 // (rotl x, y) 2188 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2189 // (rotr x, (sub 32, y)) 2190 if (ConstantSDNode *SUBC = 2191 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2192 if (SUBC->getAPIntValue() == OpSizeInBits) { 2193 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2194 LHSShiftArg, 2195 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2196 } 2197 } 2198 } else if (LExtOp0.getOpcode() == ISD::SUB && 2199 RExtOp0 == LExtOp0.getOperand(1)) { 2200 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2201 // (rotr x, y) 2202 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2203 // (rotl x, (sub 32, y)) 2204 if (ConstantSDNode *SUBC = 2205 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2206 if (SUBC->getAPIntValue() == OpSizeInBits) { 2207 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2208 LHSShiftArg, 2209 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2210 } 2211 } 2212 } 2213 } 2214 2215 return 0; 2216} 2217 2218SDValue DAGCombiner::visitXOR(SDNode *N) { 2219 SDValue N0 = N->getOperand(0); 2220 SDValue N1 = N->getOperand(1); 2221 SDValue LHS, RHS, CC; 2222 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2223 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2224 MVT VT = N0.getValueType(); 2225 2226 // fold vector ops 2227 if (VT.isVector()) { 2228 SDValue FoldedVOp = SimplifyVBinOp(N); 2229 if (FoldedVOp.getNode()) return FoldedVOp; 2230 } 2231 2232 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2233 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2234 return DAG.getConstant(0, VT); 2235 // fold (xor x, undef) -> undef 2236 if (N0.getOpcode() == ISD::UNDEF) 2237 return N0; 2238 if (N1.getOpcode() == ISD::UNDEF) 2239 return N1; 2240 // fold (xor c1, c2) -> c1^c2 2241 if (N0C && N1C) 2242 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2243 // canonicalize constant to RHS 2244 if (N0C && !N1C) 2245 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2246 // fold (xor x, 0) -> x 2247 if (N1C && N1C->isNullValue()) 2248 return N0; 2249 // reassociate xor 2250 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2251 if (RXOR.getNode() != 0) 2252 return RXOR; 2253 2254 // fold !(x cc y) -> (x !cc y) 2255 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2256 bool isInt = LHS.getValueType().isInteger(); 2257 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2258 isInt); 2259 2260 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2261 switch (N0.getOpcode()) { 2262 default: 2263 llvm_unreachable("Unhandled SetCC Equivalent!"); 2264 case ISD::SETCC: 2265 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2266 case ISD::SELECT_CC: 2267 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2268 N0.getOperand(3), NotCC); 2269 } 2270 } 2271 } 2272 2273 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2274 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2275 N0.getNode()->hasOneUse() && 2276 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2277 SDValue V = N0.getOperand(0); 2278 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2279 DAG.getConstant(1, V.getValueType())); 2280 AddToWorkList(V.getNode()); 2281 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2282 } 2283 2284 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2285 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2286 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2287 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2288 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2289 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2290 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2291 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2292 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2293 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2294 } 2295 } 2296 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2297 if (N1C && N1C->isAllOnesValue() && 2298 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2299 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2300 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2301 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2302 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2303 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2304 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2305 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2306 } 2307 } 2308 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2309 if (N1C && N0.getOpcode() == ISD::XOR) { 2310 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2311 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2312 if (N00C) 2313 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2314 DAG.getConstant(N1C->getAPIntValue() ^ 2315 N00C->getAPIntValue(), VT)); 2316 if (N01C) 2317 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2318 DAG.getConstant(N1C->getAPIntValue() ^ 2319 N01C->getAPIntValue(), VT)); 2320 } 2321 // fold (xor x, x) -> 0 2322 if (N0 == N1) { 2323 if (!VT.isVector()) { 2324 return DAG.getConstant(0, VT); 2325 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2326 // Produce a vector of zeros. 2327 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2328 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2329 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2330 &Ops[0], Ops.size()); 2331 } 2332 } 2333 2334 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2335 if (N0.getOpcode() == N1.getOpcode()) { 2336 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2337 if (Tmp.getNode()) return Tmp; 2338 } 2339 2340 // Simplify the expression using non-local knowledge. 2341 if (!VT.isVector() && 2342 SimplifyDemandedBits(SDValue(N, 0))) 2343 return SDValue(N, 0); 2344 2345 return SDValue(); 2346} 2347 2348/// visitShiftByConstant - Handle transforms common to the three shifts, when 2349/// the shift amount is a constant. 2350SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2351 SDNode *LHS = N->getOperand(0).getNode(); 2352 if (!LHS->hasOneUse()) return SDValue(); 2353 2354 // We want to pull some binops through shifts, so that we have (and (shift)) 2355 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2356 // thing happens with address calculations, so it's important to canonicalize 2357 // it. 2358 bool HighBitSet = false; // Can we transform this if the high bit is set? 2359 2360 switch (LHS->getOpcode()) { 2361 default: return SDValue(); 2362 case ISD::OR: 2363 case ISD::XOR: 2364 HighBitSet = false; // We can only transform sra if the high bit is clear. 2365 break; 2366 case ISD::AND: 2367 HighBitSet = true; // We can only transform sra if the high bit is set. 2368 break; 2369 case ISD::ADD: 2370 if (N->getOpcode() != ISD::SHL) 2371 return SDValue(); // only shl(add) not sr[al](add). 2372 HighBitSet = false; // We can only transform sra if the high bit is clear. 2373 break; 2374 } 2375 2376 // We require the RHS of the binop to be a constant as well. 2377 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2378 if (!BinOpCst) return SDValue(); 2379 2380 // FIXME: disable this unless the input to the binop is a shift by a constant. 2381 // If it is not a shift, it pessimizes some common cases like: 2382 // 2383 // void foo(int *X, int i) { X[i & 1235] = 1; } 2384 // int bar(int *X, int i) { return X[i & 255]; } 2385 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2386 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2387 BinOpLHSVal->getOpcode() != ISD::SRA && 2388 BinOpLHSVal->getOpcode() != ISD::SRL) || 2389 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2390 return SDValue(); 2391 2392 MVT VT = N->getValueType(0); 2393 2394 // If this is a signed shift right, and the high bit is modified by the 2395 // logical operation, do not perform the transformation. The highBitSet 2396 // boolean indicates the value of the high bit of the constant which would 2397 // cause it to be modified for this operation. 2398 if (N->getOpcode() == ISD::SRA) { 2399 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2400 if (BinOpRHSSignSet != HighBitSet) 2401 return SDValue(); 2402 } 2403 2404 // Fold the constants, shifting the binop RHS by the shift amount. 2405 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2406 N->getValueType(0), 2407 LHS->getOperand(1), N->getOperand(1)); 2408 2409 // Create the new shift. 2410 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2411 VT, LHS->getOperand(0), N->getOperand(1)); 2412 2413 // Create the new binop. 2414 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2415} 2416 2417SDValue DAGCombiner::visitSHL(SDNode *N) { 2418 SDValue N0 = N->getOperand(0); 2419 SDValue N1 = N->getOperand(1); 2420 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2421 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2422 MVT VT = N0.getValueType(); 2423 unsigned OpSizeInBits = VT.getSizeInBits(); 2424 2425 // fold (shl c1, c2) -> c1<<c2 2426 if (N0C && N1C) 2427 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2428 // fold (shl 0, x) -> 0 2429 if (N0C && N0C->isNullValue()) 2430 return N0; 2431 // fold (shl x, c >= size(x)) -> undef 2432 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2433 return DAG.getUNDEF(VT); 2434 // fold (shl x, 0) -> x 2435 if (N1C && N1C->isNullValue()) 2436 return N0; 2437 // if (shl x, c) is known to be zero, return 0 2438 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2439 APInt::getAllOnesValue(VT.getSizeInBits()))) 2440 return DAG.getConstant(0, VT); 2441 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2442 if (N1.getOpcode() == ISD::TRUNCATE && 2443 N1.getOperand(0).getOpcode() == ISD::AND && 2444 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2445 SDValue N101 = N1.getOperand(0).getOperand(1); 2446 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2447 MVT TruncVT = N1.getValueType(); 2448 SDValue N100 = N1.getOperand(0).getOperand(0); 2449 APInt TruncC = N101C->getAPIntValue(); 2450 TruncC.trunc(TruncVT.getSizeInBits()); 2451 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2452 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2453 DAG.getNode(ISD::TRUNCATE, 2454 N->getDebugLoc(), 2455 TruncVT, N100), 2456 DAG.getConstant(TruncC, TruncVT))); 2457 } 2458 } 2459 2460 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2461 return SDValue(N, 0); 2462 2463 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2464 if (N1C && N0.getOpcode() == ISD::SHL && 2465 N0.getOperand(1).getOpcode() == ISD::Constant) { 2466 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2467 uint64_t c2 = N1C->getZExtValue(); 2468 if (c1 + c2 > OpSizeInBits) 2469 return DAG.getConstant(0, VT); 2470 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2471 DAG.getConstant(c1 + c2, N1.getValueType())); 2472 } 2473 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2474 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2475 if (N1C && N0.getOpcode() == ISD::SRL && 2476 N0.getOperand(1).getOpcode() == ISD::Constant) { 2477 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2478 if (c1 < VT.getSizeInBits()) { 2479 uint64_t c2 = N1C->getZExtValue(); 2480 SDValue HiBitsMask = 2481 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2482 VT.getSizeInBits() - c1), 2483 VT); 2484 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2485 N0.getOperand(0), 2486 HiBitsMask); 2487 if (c2 > c1) 2488 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2489 DAG.getConstant(c2-c1, N1.getValueType())); 2490 else 2491 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2492 DAG.getConstant(c1-c2, N1.getValueType())); 2493 } 2494 } 2495 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2496 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2497 SDValue HiBitsMask = 2498 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2499 VT.getSizeInBits() - 2500 N1C->getZExtValue()), 2501 VT); 2502 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2503 HiBitsMask); 2504 } 2505 2506 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2507} 2508 2509SDValue DAGCombiner::visitSRA(SDNode *N) { 2510 SDValue N0 = N->getOperand(0); 2511 SDValue N1 = N->getOperand(1); 2512 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2513 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2514 MVT VT = N0.getValueType(); 2515 2516 // fold (sra c1, c2) -> (sra c1, c2) 2517 if (N0C && N1C) 2518 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2519 // fold (sra 0, x) -> 0 2520 if (N0C && N0C->isNullValue()) 2521 return N0; 2522 // fold (sra -1, x) -> -1 2523 if (N0C && N0C->isAllOnesValue()) 2524 return N0; 2525 // fold (sra x, (setge c, size(x))) -> undef 2526 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2527 return DAG.getUNDEF(VT); 2528 // fold (sra x, 0) -> x 2529 if (N1C && N1C->isNullValue()) 2530 return N0; 2531 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2532 // sext_inreg. 2533 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2534 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2535 MVT EVT = MVT::getIntegerVT(LowBits); 2536 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2537 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2538 N0.getOperand(0), DAG.getValueType(EVT)); 2539 } 2540 2541 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2542 if (N1C && N0.getOpcode() == ISD::SRA) { 2543 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2544 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2545 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2546 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2547 DAG.getConstant(Sum, N1C->getValueType(0))); 2548 } 2549 } 2550 2551 // fold (sra (shl X, m), (sub result_size, n)) 2552 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2553 // result_size - n != m. 2554 // If truncate is free for the target sext(shl) is likely to result in better 2555 // code. 2556 if (N0.getOpcode() == ISD::SHL) { 2557 // Get the two constanst of the shifts, CN0 = m, CN = n. 2558 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2559 if (N01C && N1C) { 2560 // Determine what the truncate's result bitsize and type would be. 2561 unsigned VTValSize = VT.getSizeInBits(); 2562 MVT TruncVT = 2563 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2564 // Determine the residual right-shift amount. 2565 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2566 2567 // If the shift is not a no-op (in which case this should be just a sign 2568 // extend already), the truncated to type is legal, sign_extend is legal 2569 // on that type, and the the truncate to that type is both legal and free, 2570 // perform the transform. 2571 if ((ShiftAmt > 0) && 2572 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2573 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2574 TLI.isTruncateFree(VT, TruncVT)) { 2575 2576 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2577 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2578 N0.getOperand(0), Amt); 2579 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2580 Shift); 2581 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2582 N->getValueType(0), Trunc); 2583 } 2584 } 2585 } 2586 2587 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2588 if (N1.getOpcode() == ISD::TRUNCATE && 2589 N1.getOperand(0).getOpcode() == ISD::AND && 2590 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2591 SDValue N101 = N1.getOperand(0).getOperand(1); 2592 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2593 MVT TruncVT = N1.getValueType(); 2594 SDValue N100 = N1.getOperand(0).getOperand(0); 2595 APInt TruncC = N101C->getAPIntValue(); 2596 TruncC.trunc(TruncVT.getSizeInBits()); 2597 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2598 DAG.getNode(ISD::AND, N->getDebugLoc(), 2599 TruncVT, 2600 DAG.getNode(ISD::TRUNCATE, 2601 N->getDebugLoc(), 2602 TruncVT, N100), 2603 DAG.getConstant(TruncC, TruncVT))); 2604 } 2605 } 2606 2607 // Simplify, based on bits shifted out of the LHS. 2608 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2609 return SDValue(N, 0); 2610 2611 2612 // If the sign bit is known to be zero, switch this to a SRL. 2613 if (DAG.SignBitIsZero(N0)) 2614 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2615 2616 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2617} 2618 2619SDValue DAGCombiner::visitSRL(SDNode *N) { 2620 SDValue N0 = N->getOperand(0); 2621 SDValue N1 = N->getOperand(1); 2622 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2623 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2624 MVT VT = N0.getValueType(); 2625 unsigned OpSizeInBits = VT.getSizeInBits(); 2626 2627 // fold (srl c1, c2) -> c1 >>u c2 2628 if (N0C && N1C) 2629 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2630 // fold (srl 0, x) -> 0 2631 if (N0C && N0C->isNullValue()) 2632 return N0; 2633 // fold (srl x, c >= size(x)) -> undef 2634 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2635 return DAG.getUNDEF(VT); 2636 // fold (srl x, 0) -> x 2637 if (N1C && N1C->isNullValue()) 2638 return N0; 2639 // if (srl x, c) is known to be zero, return 0 2640 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2641 APInt::getAllOnesValue(OpSizeInBits))) 2642 return DAG.getConstant(0, VT); 2643 2644 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2645 if (N1C && N0.getOpcode() == ISD::SRL && 2646 N0.getOperand(1).getOpcode() == ISD::Constant) { 2647 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2648 uint64_t c2 = N1C->getZExtValue(); 2649 if (c1 + c2 > OpSizeInBits) 2650 return DAG.getConstant(0, VT); 2651 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2652 DAG.getConstant(c1 + c2, N1.getValueType())); 2653 } 2654 2655 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2656 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2657 // Shifting in all undef bits? 2658 MVT SmallVT = N0.getOperand(0).getValueType(); 2659 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2660 return DAG.getUNDEF(VT); 2661 2662 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2663 N0.getOperand(0), N1); 2664 AddToWorkList(SmallShift.getNode()); 2665 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2666 } 2667 2668 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2669 // bit, which is unmodified by sra. 2670 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2671 if (N0.getOpcode() == ISD::SRA) 2672 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2673 } 2674 2675 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2676 if (N1C && N0.getOpcode() == ISD::CTLZ && 2677 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2678 APInt KnownZero, KnownOne; 2679 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2680 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2681 2682 // If any of the input bits are KnownOne, then the input couldn't be all 2683 // zeros, thus the result of the srl will always be zero. 2684 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2685 2686 // If all of the bits input the to ctlz node are known to be zero, then 2687 // the result of the ctlz is "32" and the result of the shift is one. 2688 APInt UnknownBits = ~KnownZero & Mask; 2689 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2690 2691 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2692 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2693 // Okay, we know that only that the single bit specified by UnknownBits 2694 // could be set on input to the CTLZ node. If this bit is set, the SRL 2695 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2696 // to an SRL/XOR pair, which is likely to simplify more. 2697 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2698 SDValue Op = N0.getOperand(0); 2699 2700 if (ShAmt) { 2701 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2702 DAG.getConstant(ShAmt, getShiftAmountTy())); 2703 AddToWorkList(Op.getNode()); 2704 } 2705 2706 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2707 Op, DAG.getConstant(1, VT)); 2708 } 2709 } 2710 2711 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2712 if (N1.getOpcode() == ISD::TRUNCATE && 2713 N1.getOperand(0).getOpcode() == ISD::AND && 2714 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2715 SDValue N101 = N1.getOperand(0).getOperand(1); 2716 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2717 MVT TruncVT = N1.getValueType(); 2718 SDValue N100 = N1.getOperand(0).getOperand(0); 2719 APInt TruncC = N101C->getAPIntValue(); 2720 TruncC.trunc(TruncVT.getSizeInBits()); 2721 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2722 DAG.getNode(ISD::AND, N->getDebugLoc(), 2723 TruncVT, 2724 DAG.getNode(ISD::TRUNCATE, 2725 N->getDebugLoc(), 2726 TruncVT, N100), 2727 DAG.getConstant(TruncC, TruncVT))); 2728 } 2729 } 2730 2731 // fold operands of srl based on knowledge that the low bits are not 2732 // demanded. 2733 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2734 return SDValue(N, 0); 2735 2736 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2737} 2738 2739SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2740 SDValue N0 = N->getOperand(0); 2741 MVT VT = N->getValueType(0); 2742 2743 // fold (ctlz c1) -> c2 2744 if (isa<ConstantSDNode>(N0)) 2745 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2746 return SDValue(); 2747} 2748 2749SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2750 SDValue N0 = N->getOperand(0); 2751 MVT VT = N->getValueType(0); 2752 2753 // fold (cttz c1) -> c2 2754 if (isa<ConstantSDNode>(N0)) 2755 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2756 return SDValue(); 2757} 2758 2759SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2760 SDValue N0 = N->getOperand(0); 2761 MVT VT = N->getValueType(0); 2762 2763 // fold (ctpop c1) -> c2 2764 if (isa<ConstantSDNode>(N0)) 2765 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2766 return SDValue(); 2767} 2768 2769SDValue DAGCombiner::visitSELECT(SDNode *N) { 2770 SDValue N0 = N->getOperand(0); 2771 SDValue N1 = N->getOperand(1); 2772 SDValue N2 = N->getOperand(2); 2773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2775 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2776 MVT VT = N->getValueType(0); 2777 MVT VT0 = N0.getValueType(); 2778 2779 // fold (select C, X, X) -> X 2780 if (N1 == N2) 2781 return N1; 2782 // fold (select true, X, Y) -> X 2783 if (N0C && !N0C->isNullValue()) 2784 return N1; 2785 // fold (select false, X, Y) -> Y 2786 if (N0C && N0C->isNullValue()) 2787 return N2; 2788 // fold (select C, 1, X) -> (or C, X) 2789 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2790 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2791 // fold (select C, 0, 1) -> (xor C, 1) 2792 if (VT.isInteger() && 2793 (VT0 == MVT::i1 || 2794 (VT0.isInteger() && 2795 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2796 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2797 SDValue XORNode; 2798 if (VT == VT0) 2799 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2800 N0, DAG.getConstant(1, VT0)); 2801 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2802 N0, DAG.getConstant(1, VT0)); 2803 AddToWorkList(XORNode.getNode()); 2804 if (VT.bitsGT(VT0)) 2805 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2806 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2807 } 2808 // fold (select C, 0, X) -> (and (not C), X) 2809 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2810 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2811 AddToWorkList(NOTNode.getNode()); 2812 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2813 } 2814 // fold (select C, X, 1) -> (or (not C), X) 2815 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2816 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2817 AddToWorkList(NOTNode.getNode()); 2818 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2819 } 2820 // fold (select C, X, 0) -> (and C, X) 2821 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2822 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2823 // fold (select X, X, Y) -> (or X, Y) 2824 // fold (select X, 1, Y) -> (or X, Y) 2825 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2826 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2827 // fold (select X, Y, X) -> (and X, Y) 2828 // fold (select X, Y, 0) -> (and X, Y) 2829 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2830 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2831 2832 // If we can fold this based on the true/false value, do so. 2833 if (SimplifySelectOps(N, N1, N2)) 2834 return SDValue(N, 0); // Don't revisit N. 2835 2836 // fold selects based on a setcc into other things, such as min/max/abs 2837 if (N0.getOpcode() == ISD::SETCC) { 2838 // FIXME: 2839 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2840 // having to say they don't support SELECT_CC on every type the DAG knows 2841 // about, since there is no way to mark an opcode illegal at all value types 2842 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2843 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2844 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2845 N0.getOperand(0), N0.getOperand(1), 2846 N1, N2, N0.getOperand(2)); 2847 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2848 } 2849 2850 return SDValue(); 2851} 2852 2853SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2854 SDValue N0 = N->getOperand(0); 2855 SDValue N1 = N->getOperand(1); 2856 SDValue N2 = N->getOperand(2); 2857 SDValue N3 = N->getOperand(3); 2858 SDValue N4 = N->getOperand(4); 2859 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2860 2861 // fold select_cc lhs, rhs, x, x, cc -> x 2862 if (N2 == N3) 2863 return N2; 2864 2865 // Determine if the condition we're dealing with is constant 2866 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2867 N0, N1, CC, N->getDebugLoc(), false); 2868 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2869 2870 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2871 if (!SCCC->isNullValue()) 2872 return N2; // cond always true -> true val 2873 else 2874 return N3; // cond always false -> false val 2875 } 2876 2877 // Fold to a simpler select_cc 2878 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2879 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2880 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2881 SCC.getOperand(2)); 2882 2883 // If we can fold this based on the true/false value, do so. 2884 if (SimplifySelectOps(N, N2, N3)) 2885 return SDValue(N, 0); // Don't revisit N. 2886 2887 // fold select_cc into other things, such as min/max/abs 2888 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2889} 2890 2891SDValue DAGCombiner::visitSETCC(SDNode *N) { 2892 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2893 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2894 N->getDebugLoc()); 2895} 2896 2897// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2898// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2899// transformation. Returns true if extension are possible and the above 2900// mentioned transformation is profitable. 2901static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2902 unsigned ExtOpc, 2903 SmallVector<SDNode*, 4> &ExtendNodes, 2904 const TargetLowering &TLI) { 2905 bool HasCopyToRegUses = false; 2906 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2907 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2908 UE = N0.getNode()->use_end(); 2909 UI != UE; ++UI) { 2910 SDNode *User = *UI; 2911 if (User == N) 2912 continue; 2913 if (UI.getUse().getResNo() != N0.getResNo()) 2914 continue; 2915 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2916 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 2917 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2918 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2919 // Sign bits will be lost after a zext. 2920 return false; 2921 bool Add = false; 2922 for (unsigned i = 0; i != 2; ++i) { 2923 SDValue UseOp = User->getOperand(i); 2924 if (UseOp == N0) 2925 continue; 2926 if (!isa<ConstantSDNode>(UseOp)) 2927 return false; 2928 Add = true; 2929 } 2930 if (Add) 2931 ExtendNodes.push_back(User); 2932 continue; 2933 } 2934 // If truncates aren't free and there are users we can't 2935 // extend, it isn't worthwhile. 2936 if (!isTruncFree) 2937 return false; 2938 // Remember if this value is live-out. 2939 if (User->getOpcode() == ISD::CopyToReg) 2940 HasCopyToRegUses = true; 2941 } 2942 2943 if (HasCopyToRegUses) { 2944 bool BothLiveOut = false; 2945 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2946 UI != UE; ++UI) { 2947 SDUse &Use = UI.getUse(); 2948 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 2949 BothLiveOut = true; 2950 break; 2951 } 2952 } 2953 if (BothLiveOut) 2954 // Both unextended and extended values are live out. There had better be 2955 // good a reason for the transformation. 2956 return ExtendNodes.size(); 2957 } 2958 return true; 2959} 2960 2961SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2962 SDValue N0 = N->getOperand(0); 2963 MVT VT = N->getValueType(0); 2964 2965 // fold (sext c1) -> c1 2966 if (isa<ConstantSDNode>(N0)) 2967 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2968 2969 // fold (sext (sext x)) -> (sext x) 2970 // fold (sext (aext x)) -> (sext x) 2971 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2972 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2973 N0.getOperand(0)); 2974 2975 if (N0.getOpcode() == ISD::TRUNCATE) { 2976 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2977 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2978 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2979 if (NarrowLoad.getNode()) { 2980 if (NarrowLoad.getNode() != N0.getNode()) 2981 CombineTo(N0.getNode(), NarrowLoad); 2982 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2983 } 2984 2985 // See if the value being truncated is already sign extended. If so, just 2986 // eliminate the trunc/sext pair. 2987 SDValue Op = N0.getOperand(0); 2988 unsigned OpBits = Op.getValueType().getSizeInBits(); 2989 unsigned MidBits = N0.getValueType().getSizeInBits(); 2990 unsigned DestBits = VT.getSizeInBits(); 2991 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2992 2993 if (OpBits == DestBits) { 2994 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2995 // bits, it is already ready. 2996 if (NumSignBits > DestBits-MidBits) 2997 return Op; 2998 } else if (OpBits < DestBits) { 2999 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3000 // bits, just sext from i32. 3001 if (NumSignBits > OpBits-MidBits) 3002 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3003 } else { 3004 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3005 // bits, just truncate to i32. 3006 if (NumSignBits > OpBits-MidBits) 3007 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3008 } 3009 3010 // fold (sext (truncate x)) -> (sextinreg x). 3011 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3012 N0.getValueType())) { 3013 if (Op.getValueType().bitsLT(VT)) 3014 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3015 else if (Op.getValueType().bitsGT(VT)) 3016 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3017 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3018 DAG.getValueType(N0.getValueType())); 3019 } 3020 } 3021 3022 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3023 if (ISD::isNON_EXTLoad(N0.getNode()) && 3024 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3025 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3026 bool DoXform = true; 3027 SmallVector<SDNode*, 4> SetCCs; 3028 if (!N0.hasOneUse()) 3029 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3030 if (DoXform) { 3031 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3032 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3033 LN0->getChain(), 3034 LN0->getBasePtr(), LN0->getSrcValue(), 3035 LN0->getSrcValueOffset(), 3036 N0.getValueType(), 3037 LN0->isVolatile(), LN0->getAlignment()); 3038 CombineTo(N, ExtLoad); 3039 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3040 N0.getValueType(), ExtLoad); 3041 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3042 3043 // Extend SetCC uses if necessary. 3044 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3045 SDNode *SetCC = SetCCs[i]; 3046 SmallVector<SDValue, 4> Ops; 3047 3048 for (unsigned j = 0; j != 2; ++j) { 3049 SDValue SOp = SetCC->getOperand(j); 3050 if (SOp == Trunc) 3051 Ops.push_back(ExtLoad); 3052 else 3053 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3054 N->getDebugLoc(), VT, SOp)); 3055 } 3056 3057 Ops.push_back(SetCC->getOperand(2)); 3058 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3059 SetCC->getValueType(0), 3060 &Ops[0], Ops.size())); 3061 } 3062 3063 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3064 } 3065 } 3066 3067 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3068 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3069 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3070 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3071 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3072 MVT EVT = LN0->getMemoryVT(); 3073 if ((!LegalOperations && !LN0->isVolatile()) || 3074 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3075 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3076 LN0->getChain(), 3077 LN0->getBasePtr(), LN0->getSrcValue(), 3078 LN0->getSrcValueOffset(), EVT, 3079 LN0->isVolatile(), LN0->getAlignment()); 3080 CombineTo(N, ExtLoad); 3081 CombineTo(N0.getNode(), 3082 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3083 N0.getValueType(), ExtLoad), 3084 ExtLoad.getValue(1)); 3085 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3086 } 3087 } 3088 3089 if (N0.getOpcode() == ISD::SETCC) { 3090 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3091 if (VT.isVector() && 3092 // We know that the # elements of the results is the same as the 3093 // # elements of the compare (and the # elements of the compare result 3094 // for that matter). Check to see that they are the same size. If so, 3095 // we know that the element size of the sext'd result matches the 3096 // element size of the compare operands. 3097 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3098 3099 // Only do this before legalize for now. 3100 !LegalOperations) { 3101 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3102 N0.getOperand(1), 3103 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3104 } 3105 3106 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3107 SDValue NegOne = 3108 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3109 SDValue SCC = 3110 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3111 NegOne, DAG.getConstant(0, VT), 3112 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3113 if (SCC.getNode()) return SCC; 3114 } 3115 3116 3117 3118 // fold (sext x) -> (zext x) if the sign bit is known zero. 3119 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3120 DAG.SignBitIsZero(N0)) 3121 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3122 3123 return SDValue(); 3124} 3125 3126SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3127 SDValue N0 = N->getOperand(0); 3128 MVT VT = N->getValueType(0); 3129 3130 // fold (zext c1) -> c1 3131 if (isa<ConstantSDNode>(N0)) 3132 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3133 // fold (zext (zext x)) -> (zext x) 3134 // fold (zext (aext x)) -> (zext x) 3135 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3136 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3137 N0.getOperand(0)); 3138 3139 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3140 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3141 if (N0.getOpcode() == ISD::TRUNCATE) { 3142 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3143 if (NarrowLoad.getNode()) { 3144 if (NarrowLoad.getNode() != N0.getNode()) 3145 CombineTo(N0.getNode(), NarrowLoad); 3146 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3147 } 3148 } 3149 3150 // fold (zext (truncate x)) -> (and x, mask) 3151 if (N0.getOpcode() == ISD::TRUNCATE && 3152 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3153 SDValue Op = N0.getOperand(0); 3154 if (Op.getValueType().bitsLT(VT)) { 3155 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3156 } else if (Op.getValueType().bitsGT(VT)) { 3157 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3158 } 3159 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3160 } 3161 3162 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3163 // if either of the casts is not free. 3164 if (N0.getOpcode() == ISD::AND && 3165 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3166 N0.getOperand(1).getOpcode() == ISD::Constant && 3167 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3168 N0.getValueType()) || 3169 !TLI.isZExtFree(N0.getValueType(), VT))) { 3170 SDValue X = N0.getOperand(0).getOperand(0); 3171 if (X.getValueType().bitsLT(VT)) { 3172 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3173 } else if (X.getValueType().bitsGT(VT)) { 3174 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3175 } 3176 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3177 Mask.zext(VT.getSizeInBits()); 3178 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3179 X, DAG.getConstant(Mask, VT)); 3180 } 3181 3182 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3183 if (ISD::isNON_EXTLoad(N0.getNode()) && 3184 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3185 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3186 bool DoXform = true; 3187 SmallVector<SDNode*, 4> SetCCs; 3188 if (!N0.hasOneUse()) 3189 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3190 if (DoXform) { 3191 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3192 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3193 LN0->getChain(), 3194 LN0->getBasePtr(), LN0->getSrcValue(), 3195 LN0->getSrcValueOffset(), 3196 N0.getValueType(), 3197 LN0->isVolatile(), LN0->getAlignment()); 3198 CombineTo(N, ExtLoad); 3199 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3200 N0.getValueType(), ExtLoad); 3201 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3202 3203 // Extend SetCC uses if necessary. 3204 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3205 SDNode *SetCC = SetCCs[i]; 3206 SmallVector<SDValue, 4> Ops; 3207 3208 for (unsigned j = 0; j != 2; ++j) { 3209 SDValue SOp = SetCC->getOperand(j); 3210 if (SOp == Trunc) 3211 Ops.push_back(ExtLoad); 3212 else 3213 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3214 N->getDebugLoc(), VT, SOp)); 3215 } 3216 3217 Ops.push_back(SetCC->getOperand(2)); 3218 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3219 SetCC->getValueType(0), 3220 &Ops[0], Ops.size())); 3221 } 3222 3223 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3224 } 3225 } 3226 3227 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3228 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3229 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3230 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3231 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3232 MVT EVT = LN0->getMemoryVT(); 3233 if ((!LegalOperations && !LN0->isVolatile()) || 3234 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3235 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3236 LN0->getChain(), 3237 LN0->getBasePtr(), LN0->getSrcValue(), 3238 LN0->getSrcValueOffset(), EVT, 3239 LN0->isVolatile(), LN0->getAlignment()); 3240 CombineTo(N, ExtLoad); 3241 CombineTo(N0.getNode(), 3242 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3243 ExtLoad), 3244 ExtLoad.getValue(1)); 3245 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3246 } 3247 } 3248 3249 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3250 if (N0.getOpcode() == ISD::SETCC) { 3251 SDValue SCC = 3252 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3253 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3254 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3255 if (SCC.getNode()) return SCC; 3256 } 3257 3258 return SDValue(); 3259} 3260 3261SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3262 SDValue N0 = N->getOperand(0); 3263 MVT VT = N->getValueType(0); 3264 3265 // fold (aext c1) -> c1 3266 if (isa<ConstantSDNode>(N0)) 3267 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3268 // fold (aext (aext x)) -> (aext x) 3269 // fold (aext (zext x)) -> (zext x) 3270 // fold (aext (sext x)) -> (sext x) 3271 if (N0.getOpcode() == ISD::ANY_EXTEND || 3272 N0.getOpcode() == ISD::ZERO_EXTEND || 3273 N0.getOpcode() == ISD::SIGN_EXTEND) 3274 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3275 3276 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3277 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3278 if (N0.getOpcode() == ISD::TRUNCATE) { 3279 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3280 if (NarrowLoad.getNode()) { 3281 if (NarrowLoad.getNode() != N0.getNode()) 3282 CombineTo(N0.getNode(), NarrowLoad); 3283 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3284 } 3285 } 3286 3287 // fold (aext (truncate x)) 3288 if (N0.getOpcode() == ISD::TRUNCATE) { 3289 SDValue TruncOp = N0.getOperand(0); 3290 if (TruncOp.getValueType() == VT) 3291 return TruncOp; // x iff x size == zext size. 3292 if (TruncOp.getValueType().bitsGT(VT)) 3293 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3294 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3295 } 3296 3297 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3298 // if the trunc is not free. 3299 if (N0.getOpcode() == ISD::AND && 3300 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3301 N0.getOperand(1).getOpcode() == ISD::Constant && 3302 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3303 N0.getValueType())) { 3304 SDValue X = N0.getOperand(0).getOperand(0); 3305 if (X.getValueType().bitsLT(VT)) { 3306 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3307 } else if (X.getValueType().bitsGT(VT)) { 3308 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3309 } 3310 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3311 Mask.zext(VT.getSizeInBits()); 3312 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3313 X, DAG.getConstant(Mask, VT)); 3314 } 3315 3316 // fold (aext (load x)) -> (aext (truncate (extload x))) 3317 if (ISD::isNON_EXTLoad(N0.getNode()) && 3318 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3319 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3320 bool DoXform = true; 3321 SmallVector<SDNode*, 4> SetCCs; 3322 if (!N0.hasOneUse()) 3323 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3324 if (DoXform) { 3325 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3326 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3327 LN0->getChain(), 3328 LN0->getBasePtr(), LN0->getSrcValue(), 3329 LN0->getSrcValueOffset(), 3330 N0.getValueType(), 3331 LN0->isVolatile(), LN0->getAlignment()); 3332 CombineTo(N, ExtLoad); 3333 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3334 N0.getValueType(), ExtLoad); 3335 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3336 3337 // Extend SetCC uses if necessary. 3338 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3339 SDNode *SetCC = SetCCs[i]; 3340 SmallVector<SDValue, 4> Ops; 3341 3342 for (unsigned j = 0; j != 2; ++j) { 3343 SDValue SOp = SetCC->getOperand(j); 3344 if (SOp == Trunc) 3345 Ops.push_back(ExtLoad); 3346 else 3347 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3348 N->getDebugLoc(), VT, SOp)); 3349 } 3350 3351 Ops.push_back(SetCC->getOperand(2)); 3352 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3353 SetCC->getValueType(0), 3354 &Ops[0], Ops.size())); 3355 } 3356 3357 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3358 } 3359 } 3360 3361 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3362 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3363 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3364 if (N0.getOpcode() == ISD::LOAD && 3365 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3366 N0.hasOneUse()) { 3367 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3368 MVT EVT = LN0->getMemoryVT(); 3369 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3370 VT, LN0->getChain(), LN0->getBasePtr(), 3371 LN0->getSrcValue(), 3372 LN0->getSrcValueOffset(), EVT, 3373 LN0->isVolatile(), LN0->getAlignment()); 3374 CombineTo(N, ExtLoad); 3375 CombineTo(N0.getNode(), 3376 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3377 N0.getValueType(), ExtLoad), 3378 ExtLoad.getValue(1)); 3379 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3380 } 3381 3382 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3383 if (N0.getOpcode() == ISD::SETCC) { 3384 SDValue SCC = 3385 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3386 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3387 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3388 if (SCC.getNode()) 3389 return SCC; 3390 } 3391 3392 return SDValue(); 3393} 3394 3395/// GetDemandedBits - See if the specified operand can be simplified with the 3396/// knowledge that only the bits specified by Mask are used. If so, return the 3397/// simpler operand, otherwise return a null SDValue. 3398SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3399 switch (V.getOpcode()) { 3400 default: break; 3401 case ISD::OR: 3402 case ISD::XOR: 3403 // If the LHS or RHS don't contribute bits to the or, drop them. 3404 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3405 return V.getOperand(1); 3406 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3407 return V.getOperand(0); 3408 break; 3409 case ISD::SRL: 3410 // Only look at single-use SRLs. 3411 if (!V.getNode()->hasOneUse()) 3412 break; 3413 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3414 // See if we can recursively simplify the LHS. 3415 unsigned Amt = RHSC->getZExtValue(); 3416 3417 // Watch out for shift count overflow though. 3418 if (Amt >= Mask.getBitWidth()) break; 3419 APInt NewMask = Mask << Amt; 3420 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3421 if (SimplifyLHS.getNode()) 3422 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3423 SimplifyLHS, V.getOperand(1)); 3424 } 3425 } 3426 return SDValue(); 3427} 3428 3429/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3430/// bits and then truncated to a narrower type and where N is a multiple 3431/// of number of bits of the narrower type, transform it to a narrower load 3432/// from address + N / num of bits of new type. If the result is to be 3433/// extended, also fold the extension to form a extending load. 3434SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3435 unsigned Opc = N->getOpcode(); 3436 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3437 SDValue N0 = N->getOperand(0); 3438 MVT VT = N->getValueType(0); 3439 MVT EVT = VT; 3440 3441 // This transformation isn't valid for vector loads. 3442 if (VT.isVector()) 3443 return SDValue(); 3444 3445 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3446 // extended to VT. 3447 if (Opc == ISD::SIGN_EXTEND_INREG) { 3448 ExtType = ISD::SEXTLOAD; 3449 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3450 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3451 return SDValue(); 3452 } 3453 3454 unsigned EVTBits = EVT.getSizeInBits(); 3455 unsigned ShAmt = 0; 3456 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3457 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3458 ShAmt = N01->getZExtValue(); 3459 // Is the shift amount a multiple of size of VT? 3460 if ((ShAmt & (EVTBits-1)) == 0) { 3461 N0 = N0.getOperand(0); 3462 if (N0.getValueType().getSizeInBits() <= EVTBits) 3463 return SDValue(); 3464 } 3465 } 3466 } 3467 3468 // Do not generate loads of non-round integer types since these can 3469 // be expensive (and would be wrong if the type is not byte sized). 3470 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3471 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3472 // Do not change the width of a volatile load. 3473 !cast<LoadSDNode>(N0)->isVolatile()) { 3474 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3475 MVT PtrType = N0.getOperand(1).getValueType(); 3476 3477 // For big endian targets, we need to adjust the offset to the pointer to 3478 // load the correct bytes. 3479 if (TLI.isBigEndian()) { 3480 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3481 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3482 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3483 } 3484 3485 uint64_t PtrOff = ShAmt / 8; 3486 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3487 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3488 PtrType, LN0->getBasePtr(), 3489 DAG.getConstant(PtrOff, PtrType)); 3490 AddToWorkList(NewPtr.getNode()); 3491 3492 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3493 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3494 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3495 LN0->isVolatile(), NewAlign) 3496 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3497 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3498 EVT, LN0->isVolatile(), NewAlign); 3499 3500 // Replace the old load's chain with the new load's chain. 3501 WorkListRemover DeadNodes(*this); 3502 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3503 &DeadNodes); 3504 3505 // Return the new loaded value. 3506 return Load; 3507 } 3508 3509 return SDValue(); 3510} 3511 3512SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3513 SDValue N0 = N->getOperand(0); 3514 SDValue N1 = N->getOperand(1); 3515 MVT VT = N->getValueType(0); 3516 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3517 unsigned VTBits = VT.getSizeInBits(); 3518 unsigned EVTBits = EVT.getSizeInBits(); 3519 3520 // fold (sext_in_reg c1) -> c1 3521 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3522 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3523 3524 // If the input is already sign extended, just drop the extension. 3525 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3526 return N0; 3527 3528 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3529 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3530 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3531 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3532 N0.getOperand(0), N1); 3533 } 3534 3535 // fold (sext_in_reg (sext x)) -> (sext x) 3536 // fold (sext_in_reg (aext x)) -> (sext x) 3537 // if x is small enough. 3538 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3539 SDValue N00 = N0.getOperand(0); 3540 if (N00.getValueType().getSizeInBits() < EVTBits) 3541 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3542 } 3543 3544 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3545 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3546 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3547 3548 // fold operands of sext_in_reg based on knowledge that the top bits are not 3549 // demanded. 3550 if (SimplifyDemandedBits(SDValue(N, 0))) 3551 return SDValue(N, 0); 3552 3553 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3554 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3555 SDValue NarrowLoad = ReduceLoadWidth(N); 3556 if (NarrowLoad.getNode()) 3557 return NarrowLoad; 3558 3559 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3560 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3561 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3562 if (N0.getOpcode() == ISD::SRL) { 3563 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3564 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3565 // We can turn this into an SRA iff the input to the SRL is already sign 3566 // extended enough. 3567 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3568 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3569 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3570 N0.getOperand(0), N0.getOperand(1)); 3571 } 3572 } 3573 3574 // fold (sext_inreg (extload x)) -> (sextload x) 3575 if (ISD::isEXTLoad(N0.getNode()) && 3576 ISD::isUNINDEXEDLoad(N0.getNode()) && 3577 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3578 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3579 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3580 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3581 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3582 LN0->getChain(), 3583 LN0->getBasePtr(), LN0->getSrcValue(), 3584 LN0->getSrcValueOffset(), EVT, 3585 LN0->isVolatile(), LN0->getAlignment()); 3586 CombineTo(N, ExtLoad); 3587 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3588 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3589 } 3590 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3591 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3592 N0.hasOneUse() && 3593 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3594 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3595 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3596 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3597 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3598 LN0->getChain(), 3599 LN0->getBasePtr(), LN0->getSrcValue(), 3600 LN0->getSrcValueOffset(), EVT, 3601 LN0->isVolatile(), LN0->getAlignment()); 3602 CombineTo(N, ExtLoad); 3603 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3604 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3605 } 3606 return SDValue(); 3607} 3608 3609SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3610 SDValue N0 = N->getOperand(0); 3611 MVT VT = N->getValueType(0); 3612 3613 // noop truncate 3614 if (N0.getValueType() == N->getValueType(0)) 3615 return N0; 3616 // fold (truncate c1) -> c1 3617 if (isa<ConstantSDNode>(N0)) 3618 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3619 // fold (truncate (truncate x)) -> (truncate x) 3620 if (N0.getOpcode() == ISD::TRUNCATE) 3621 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3622 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3623 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3624 N0.getOpcode() == ISD::ANY_EXTEND) { 3625 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3626 // if the source is smaller than the dest, we still need an extend 3627 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3628 N0.getOperand(0)); 3629 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3630 // if the source is larger than the dest, than we just need the truncate 3631 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3632 else 3633 // if the source and dest are the same type, we can drop both the extend 3634 // and the truncate 3635 return N0.getOperand(0); 3636 } 3637 3638 // See if we can simplify the input to this truncate through knowledge that 3639 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3640 // -> trunc y 3641 SDValue Shorter = 3642 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3643 VT.getSizeInBits())); 3644 if (Shorter.getNode()) 3645 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3646 3647 // fold (truncate (load x)) -> (smaller load x) 3648 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3649 return ReduceLoadWidth(N); 3650} 3651 3652static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3653 SDValue Elt = N->getOperand(i); 3654 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3655 return Elt.getNode(); 3656 return Elt.getOperand(Elt.getResNo()).getNode(); 3657} 3658 3659/// CombineConsecutiveLoads - build_pair (load, load) -> load 3660/// if load locations are consecutive. 3661SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3662 assert(N->getOpcode() == ISD::BUILD_PAIR); 3663 3664 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3665 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3666 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3667 return SDValue(); 3668 MVT LD1VT = LD1->getValueType(0); 3669 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3670 3671 if (ISD::isNON_EXTLoad(LD2) && 3672 LD2->hasOneUse() && 3673 // If both are volatile this would reduce the number of volatile loads. 3674 // If one is volatile it might be ok, but play conservative and bail out. 3675 !LD1->isVolatile() && 3676 !LD2->isVolatile() && 3677 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3678 unsigned Align = LD1->getAlignment(); 3679 unsigned NewAlign = TLI.getTargetData()-> 3680 getABITypeAlignment(VT.getTypeForMVT()); 3681 3682 if (NewAlign <= Align && 3683 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3684 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3685 LD1->getBasePtr(), LD1->getSrcValue(), 3686 LD1->getSrcValueOffset(), false, Align); 3687 } 3688 3689 return SDValue(); 3690} 3691 3692SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3693 SDValue N0 = N->getOperand(0); 3694 MVT VT = N->getValueType(0); 3695 3696 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3697 // Only do this before legalize, since afterward the target may be depending 3698 // on the bitconvert. 3699 // First check to see if this is all constant. 3700 if (!LegalTypes && 3701 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3702 VT.isVector()) { 3703 bool isSimple = true; 3704 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3705 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3706 N0.getOperand(i).getOpcode() != ISD::Constant && 3707 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3708 isSimple = false; 3709 break; 3710 } 3711 3712 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3713 assert(!DestEltVT.isVector() && 3714 "Element type of vector ValueType must not be vector!"); 3715 if (isSimple) 3716 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3717 } 3718 3719 // If the input is a constant, let getNode fold it. 3720 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3721 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3722 if (Res.getNode() != N) return Res; 3723 } 3724 3725 // (conv (conv x, t1), t2) -> (conv x, t2) 3726 if (N0.getOpcode() == ISD::BIT_CONVERT) 3727 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3728 N0.getOperand(0)); 3729 3730 // fold (conv (load x)) -> (load (conv*)x) 3731 // If the resultant load doesn't need a higher alignment than the original! 3732 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3733 // Do not change the width of a volatile load. 3734 !cast<LoadSDNode>(N0)->isVolatile() && 3735 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3736 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3737 unsigned Align = TLI.getTargetData()-> 3738 getABITypeAlignment(VT.getTypeForMVT()); 3739 unsigned OrigAlign = LN0->getAlignment(); 3740 3741 if (Align <= OrigAlign) { 3742 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3743 LN0->getBasePtr(), 3744 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3745 LN0->isVolatile(), OrigAlign); 3746 AddToWorkList(N); 3747 CombineTo(N0.getNode(), 3748 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3749 N0.getValueType(), Load), 3750 Load.getValue(1)); 3751 return Load; 3752 } 3753 } 3754 3755 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3756 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3757 // This often reduces constant pool loads. 3758 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3759 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3760 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3761 N0.getOperand(0)); 3762 AddToWorkList(NewConv.getNode()); 3763 3764 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3765 if (N0.getOpcode() == ISD::FNEG) 3766 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3767 NewConv, DAG.getConstant(SignBit, VT)); 3768 assert(N0.getOpcode() == ISD::FABS); 3769 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3770 NewConv, DAG.getConstant(~SignBit, VT)); 3771 } 3772 3773 // fold (bitconvert (fcopysign cst, x)) -> 3774 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3775 // Note that we don't handle (copysign x, cst) because this can always be 3776 // folded to an fneg or fabs. 3777 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3778 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3779 VT.isInteger() && !VT.isVector()) { 3780 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3781 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3782 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3783 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3784 IntXVT, N0.getOperand(1)); 3785 AddToWorkList(X.getNode()); 3786 3787 // If X has a different width than the result/lhs, sext it or truncate it. 3788 unsigned VTWidth = VT.getSizeInBits(); 3789 if (OrigXWidth < VTWidth) { 3790 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3791 AddToWorkList(X.getNode()); 3792 } else if (OrigXWidth > VTWidth) { 3793 // To get the sign bit in the right place, we have to shift it right 3794 // before truncating. 3795 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3796 X.getValueType(), X, 3797 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3798 AddToWorkList(X.getNode()); 3799 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3800 AddToWorkList(X.getNode()); 3801 } 3802 3803 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3804 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3805 X, DAG.getConstant(SignBit, VT)); 3806 AddToWorkList(X.getNode()); 3807 3808 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3809 VT, N0.getOperand(0)); 3810 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3811 Cst, DAG.getConstant(~SignBit, VT)); 3812 AddToWorkList(Cst.getNode()); 3813 3814 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3815 } 3816 } 3817 3818 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3819 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3820 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3821 if (CombineLD.getNode()) 3822 return CombineLD; 3823 } 3824 3825 return SDValue(); 3826} 3827 3828SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3829 MVT VT = N->getValueType(0); 3830 return CombineConsecutiveLoads(N, VT); 3831} 3832 3833/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3834/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3835/// destination element value type. 3836SDValue DAGCombiner:: 3837ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3838 MVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3839 3840 // If this is already the right type, we're done. 3841 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3842 3843 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3844 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3845 3846 // If this is a conversion of N elements of one type to N elements of another 3847 // type, convert each element. This handles FP<->INT cases. 3848 if (SrcBitSize == DstBitSize) { 3849 SmallVector<SDValue, 8> Ops; 3850 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3851 SDValue Op = BV->getOperand(i); 3852 // If the vector element type is not legal, the BUILD_VECTOR operands 3853 // are promoted and implicitly truncated. Make that explicit here. 3854 if (Op.getValueType() != SrcEltVT) 3855 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3856 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3857 DstEltVT, Op)); 3858 AddToWorkList(Ops.back().getNode()); 3859 } 3860 MVT VT = MVT::getVectorVT(DstEltVT, 3861 BV->getValueType(0).getVectorNumElements()); 3862 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3863 &Ops[0], Ops.size()); 3864 } 3865 3866 // Otherwise, we're growing or shrinking the elements. To avoid having to 3867 // handle annoying details of growing/shrinking FP values, we convert them to 3868 // int first. 3869 if (SrcEltVT.isFloatingPoint()) { 3870 // Convert the input float vector to a int vector where the elements are the 3871 // same sizes. 3872 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3873 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3874 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3875 SrcEltVT = IntVT; 3876 } 3877 3878 // Now we know the input is an integer vector. If the output is a FP type, 3879 // convert to integer first, then to FP of the right size. 3880 if (DstEltVT.isFloatingPoint()) { 3881 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3882 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3883 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3884 3885 // Next, convert to FP elements of the same size. 3886 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3887 } 3888 3889 // Okay, we know the src/dst types are both integers of differing types. 3890 // Handling growing first. 3891 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3892 if (SrcBitSize < DstBitSize) { 3893 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3894 3895 SmallVector<SDValue, 8> Ops; 3896 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3897 i += NumInputsPerOutput) { 3898 bool isLE = TLI.isLittleEndian(); 3899 APInt NewBits = APInt(DstBitSize, 0); 3900 bool EltIsUndef = true; 3901 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3902 // Shift the previously computed bits over. 3903 NewBits <<= SrcBitSize; 3904 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3905 if (Op.getOpcode() == ISD::UNDEF) continue; 3906 EltIsUndef = false; 3907 3908 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 3909 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 3910 } 3911 3912 if (EltIsUndef) 3913 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3914 else 3915 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3916 } 3917 3918 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3919 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3920 &Ops[0], Ops.size()); 3921 } 3922 3923 // Finally, this must be the case where we are shrinking elements: each input 3924 // turns into multiple outputs. 3925 bool isS2V = ISD::isScalarToVector(BV); 3926 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3927 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3928 SmallVector<SDValue, 8> Ops; 3929 3930 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3931 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3932 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3933 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3934 continue; 3935 } 3936 3937 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 3938 getAPIntValue()).zextOrTrunc(SrcBitSize); 3939 3940 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3941 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3942 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3943 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3944 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3945 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3946 Ops[0]); 3947 OpVal = OpVal.lshr(DstBitSize); 3948 } 3949 3950 // For big endian targets, swap the order of the pieces of each element. 3951 if (TLI.isBigEndian()) 3952 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3953 } 3954 3955 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3956 &Ops[0], Ops.size()); 3957} 3958 3959SDValue DAGCombiner::visitFADD(SDNode *N) { 3960 SDValue N0 = N->getOperand(0); 3961 SDValue N1 = N->getOperand(1); 3962 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3963 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3964 MVT VT = N->getValueType(0); 3965 3966 // fold vector ops 3967 if (VT.isVector()) { 3968 SDValue FoldedVOp = SimplifyVBinOp(N); 3969 if (FoldedVOp.getNode()) return FoldedVOp; 3970 } 3971 3972 // fold (fadd c1, c2) -> (fadd c1, c2) 3973 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3974 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3975 // canonicalize constant to RHS 3976 if (N0CFP && !N1CFP) 3977 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3978 // fold (fadd A, 0) -> A 3979 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3980 return N0; 3981 // fold (fadd A, (fneg B)) -> (fsub A, B) 3982 if (isNegatibleForFree(N1, LegalOperations) == 2) 3983 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3984 GetNegatedExpression(N1, DAG, LegalOperations)); 3985 // fold (fadd (fneg A), B) -> (fsub B, A) 3986 if (isNegatibleForFree(N0, LegalOperations) == 2) 3987 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3988 GetNegatedExpression(N0, DAG, LegalOperations)); 3989 3990 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3991 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3992 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3993 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3994 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3995 N0.getOperand(1), N1)); 3996 3997 return SDValue(); 3998} 3999 4000SDValue DAGCombiner::visitFSUB(SDNode *N) { 4001 SDValue N0 = N->getOperand(0); 4002 SDValue N1 = N->getOperand(1); 4003 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4004 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4005 MVT VT = N->getValueType(0); 4006 4007 // fold vector ops 4008 if (VT.isVector()) { 4009 SDValue FoldedVOp = SimplifyVBinOp(N); 4010 if (FoldedVOp.getNode()) return FoldedVOp; 4011 } 4012 4013 // fold (fsub c1, c2) -> c1-c2 4014 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4015 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4016 // fold (fsub A, 0) -> A 4017 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4018 return N0; 4019 // fold (fsub 0, B) -> -B 4020 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4021 if (isNegatibleForFree(N1, LegalOperations)) 4022 return GetNegatedExpression(N1, DAG, LegalOperations); 4023 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4024 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4025 } 4026 // fold (fsub A, (fneg B)) -> (fadd A, B) 4027 if (isNegatibleForFree(N1, LegalOperations)) 4028 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4029 GetNegatedExpression(N1, DAG, LegalOperations)); 4030 4031 return SDValue(); 4032} 4033 4034SDValue DAGCombiner::visitFMUL(SDNode *N) { 4035 SDValue N0 = N->getOperand(0); 4036 SDValue N1 = N->getOperand(1); 4037 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4038 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4039 MVT VT = N->getValueType(0); 4040 4041 // fold vector ops 4042 if (VT.isVector()) { 4043 SDValue FoldedVOp = SimplifyVBinOp(N); 4044 if (FoldedVOp.getNode()) return FoldedVOp; 4045 } 4046 4047 // fold (fmul c1, c2) -> c1*c2 4048 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4049 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4050 // canonicalize constant to RHS 4051 if (N0CFP && !N1CFP) 4052 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4053 // fold (fmul A, 0) -> 0 4054 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4055 return N1; 4056 // fold (fmul A, 0) -> 0, vector edition. 4057 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4058 return N1; 4059 // fold (fmul X, 2.0) -> (fadd X, X) 4060 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4061 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4062 // fold (fmul X, (fneg 1.0)) -> (fneg X) 4063 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4064 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4065 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4066 4067 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4068 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4069 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4070 // Both can be negated for free, check to see if at least one is cheaper 4071 // negated. 4072 if (LHSNeg == 2 || RHSNeg == 2) 4073 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4074 GetNegatedExpression(N0, DAG, LegalOperations), 4075 GetNegatedExpression(N1, DAG, LegalOperations)); 4076 } 4077 } 4078 4079 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4080 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4081 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4082 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4083 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4084 N0.getOperand(1), N1)); 4085 4086 return SDValue(); 4087} 4088 4089SDValue DAGCombiner::visitFDIV(SDNode *N) { 4090 SDValue N0 = N->getOperand(0); 4091 SDValue N1 = N->getOperand(1); 4092 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4093 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4094 MVT VT = N->getValueType(0); 4095 4096 // fold vector ops 4097 if (VT.isVector()) { 4098 SDValue FoldedVOp = SimplifyVBinOp(N); 4099 if (FoldedVOp.getNode()) return FoldedVOp; 4100 } 4101 4102 // fold (fdiv c1, c2) -> c1/c2 4103 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4104 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4105 4106 4107 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4108 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4109 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4110 // Both can be negated for free, check to see if at least one is cheaper 4111 // negated. 4112 if (LHSNeg == 2 || RHSNeg == 2) 4113 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4114 GetNegatedExpression(N0, DAG, LegalOperations), 4115 GetNegatedExpression(N1, DAG, LegalOperations)); 4116 } 4117 } 4118 4119 return SDValue(); 4120} 4121 4122SDValue DAGCombiner::visitFREM(SDNode *N) { 4123 SDValue N0 = N->getOperand(0); 4124 SDValue N1 = N->getOperand(1); 4125 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4126 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4127 MVT VT = N->getValueType(0); 4128 4129 // fold (frem c1, c2) -> fmod(c1,c2) 4130 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4131 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4132 4133 return SDValue(); 4134} 4135 4136SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4137 SDValue N0 = N->getOperand(0); 4138 SDValue N1 = N->getOperand(1); 4139 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4140 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4141 MVT VT = N->getValueType(0); 4142 4143 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4144 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4145 4146 if (N1CFP) { 4147 const APFloat& V = N1CFP->getValueAPF(); 4148 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4149 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4150 if (!V.isNegative()) { 4151 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4152 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4153 } else { 4154 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4155 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4156 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4157 } 4158 } 4159 4160 // copysign(fabs(x), y) -> copysign(x, y) 4161 // copysign(fneg(x), y) -> copysign(x, y) 4162 // copysign(copysign(x,z), y) -> copysign(x, y) 4163 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4164 N0.getOpcode() == ISD::FCOPYSIGN) 4165 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4166 N0.getOperand(0), N1); 4167 4168 // copysign(x, abs(y)) -> abs(x) 4169 if (N1.getOpcode() == ISD::FABS) 4170 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4171 4172 // copysign(x, copysign(y,z)) -> copysign(x, z) 4173 if (N1.getOpcode() == ISD::FCOPYSIGN) 4174 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4175 N0, N1.getOperand(1)); 4176 4177 // copysign(x, fp_extend(y)) -> copysign(x, y) 4178 // copysign(x, fp_round(y)) -> copysign(x, y) 4179 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4180 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4181 N0, N1.getOperand(0)); 4182 4183 return SDValue(); 4184} 4185 4186SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4187 SDValue N0 = N->getOperand(0); 4188 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4189 MVT VT = N->getValueType(0); 4190 MVT OpVT = N0.getValueType(); 4191 4192 // fold (sint_to_fp c1) -> c1fp 4193 if (N0C && OpVT != MVT::ppcf128) 4194 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4195 4196 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4197 // but UINT_TO_FP is legal on this target, try to convert. 4198 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4199 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4200 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4201 if (DAG.SignBitIsZero(N0)) 4202 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4203 } 4204 4205 return SDValue(); 4206} 4207 4208SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4209 SDValue N0 = N->getOperand(0); 4210 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4211 MVT VT = N->getValueType(0); 4212 MVT OpVT = N0.getValueType(); 4213 4214 // fold (uint_to_fp c1) -> c1fp 4215 if (N0C && OpVT != MVT::ppcf128) 4216 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4217 4218 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4219 // but SINT_TO_FP is legal on this target, try to convert. 4220 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4221 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4222 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4223 if (DAG.SignBitIsZero(N0)) 4224 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4225 } 4226 4227 return SDValue(); 4228} 4229 4230SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4231 SDValue N0 = N->getOperand(0); 4232 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4233 MVT VT = N->getValueType(0); 4234 4235 // fold (fp_to_sint c1fp) -> c1 4236 if (N0CFP) 4237 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4238 4239 return SDValue(); 4240} 4241 4242SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4243 SDValue N0 = N->getOperand(0); 4244 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4245 MVT VT = N->getValueType(0); 4246 4247 // fold (fp_to_uint c1fp) -> c1 4248 if (N0CFP && VT != MVT::ppcf128) 4249 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4250 4251 return SDValue(); 4252} 4253 4254SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4255 SDValue N0 = N->getOperand(0); 4256 SDValue N1 = N->getOperand(1); 4257 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4258 MVT VT = N->getValueType(0); 4259 4260 // fold (fp_round c1fp) -> c1fp 4261 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4262 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4263 4264 // fold (fp_round (fp_extend x)) -> x 4265 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4266 return N0.getOperand(0); 4267 4268 // fold (fp_round (fp_round x)) -> (fp_round x) 4269 if (N0.getOpcode() == ISD::FP_ROUND) { 4270 // This is a value preserving truncation if both round's are. 4271 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4272 N0.getNode()->getConstantOperandVal(1) == 1; 4273 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4274 DAG.getIntPtrConstant(IsTrunc)); 4275 } 4276 4277 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4278 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4279 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4280 N0.getOperand(0), N1); 4281 AddToWorkList(Tmp.getNode()); 4282 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4283 Tmp, N0.getOperand(1)); 4284 } 4285 4286 return SDValue(); 4287} 4288 4289SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4290 SDValue N0 = N->getOperand(0); 4291 MVT VT = N->getValueType(0); 4292 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4293 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4294 4295 // fold (fp_round_inreg c1fp) -> c1fp 4296 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4297 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4298 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4299 } 4300 4301 return SDValue(); 4302} 4303 4304SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4305 SDValue N0 = N->getOperand(0); 4306 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4307 MVT VT = N->getValueType(0); 4308 4309 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4310 if (N->hasOneUse() && 4311 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4312 return SDValue(); 4313 4314 // fold (fp_extend c1fp) -> c1fp 4315 if (N0CFP && VT != MVT::ppcf128) 4316 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4317 4318 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4319 // value of X. 4320 if (N0.getOpcode() == ISD::FP_ROUND 4321 && N0.getNode()->getConstantOperandVal(1) == 1) { 4322 SDValue In = N0.getOperand(0); 4323 if (In.getValueType() == VT) return In; 4324 if (VT.bitsLT(In.getValueType())) 4325 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4326 In, N0.getOperand(1)); 4327 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4328 } 4329 4330 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4331 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4332 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4333 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4334 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4335 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4336 LN0->getChain(), 4337 LN0->getBasePtr(), LN0->getSrcValue(), 4338 LN0->getSrcValueOffset(), 4339 N0.getValueType(), 4340 LN0->isVolatile(), LN0->getAlignment()); 4341 CombineTo(N, ExtLoad); 4342 CombineTo(N0.getNode(), 4343 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4344 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4345 ExtLoad.getValue(1)); 4346 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4347 } 4348 4349 return SDValue(); 4350} 4351 4352SDValue DAGCombiner::visitFNEG(SDNode *N) { 4353 SDValue N0 = N->getOperand(0); 4354 4355 if (isNegatibleForFree(N0, LegalOperations)) 4356 return GetNegatedExpression(N0, DAG, LegalOperations); 4357 4358 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4359 // constant pool values. 4360 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4361 N0.getOperand(0).getValueType().isInteger() && 4362 !N0.getOperand(0).getValueType().isVector()) { 4363 SDValue Int = N0.getOperand(0); 4364 MVT IntVT = Int.getValueType(); 4365 if (IntVT.isInteger() && !IntVT.isVector()) { 4366 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4367 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4368 AddToWorkList(Int.getNode()); 4369 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4370 N->getValueType(0), Int); 4371 } 4372 } 4373 4374 return SDValue(); 4375} 4376 4377SDValue DAGCombiner::visitFABS(SDNode *N) { 4378 SDValue N0 = N->getOperand(0); 4379 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4380 MVT VT = N->getValueType(0); 4381 4382 // fold (fabs c1) -> fabs(c1) 4383 if (N0CFP && VT != MVT::ppcf128) 4384 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4385 // fold (fabs (fabs x)) -> (fabs x) 4386 if (N0.getOpcode() == ISD::FABS) 4387 return N->getOperand(0); 4388 // fold (fabs (fneg x)) -> (fabs x) 4389 // fold (fabs (fcopysign x, y)) -> (fabs x) 4390 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4391 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4392 4393 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4394 // constant pool values. 4395 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4396 N0.getOperand(0).getValueType().isInteger() && 4397 !N0.getOperand(0).getValueType().isVector()) { 4398 SDValue Int = N0.getOperand(0); 4399 MVT IntVT = Int.getValueType(); 4400 if (IntVT.isInteger() && !IntVT.isVector()) { 4401 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4402 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4403 AddToWorkList(Int.getNode()); 4404 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4405 N->getValueType(0), Int); 4406 } 4407 } 4408 4409 return SDValue(); 4410} 4411 4412SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4413 SDValue Chain = N->getOperand(0); 4414 SDValue N1 = N->getOperand(1); 4415 SDValue N2 = N->getOperand(2); 4416 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4417 4418 // never taken branch, fold to chain 4419 if (N1C && N1C->isNullValue()) 4420 return Chain; 4421 // unconditional branch 4422 if (N1C && N1C->getAPIntValue() == 1) 4423 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4424 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4425 // on the target. 4426 if (N1.getOpcode() == ISD::SETCC && 4427 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4428 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4429 Chain, N1.getOperand(2), 4430 N1.getOperand(0), N1.getOperand(1), N2); 4431 } 4432 4433 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4434 // Match this pattern so that we can generate simpler code: 4435 // 4436 // %a = ... 4437 // %b = and i32 %a, 2 4438 // %c = srl i32 %b, 1 4439 // brcond i32 %c ... 4440 // 4441 // into 4442 // 4443 // %a = ... 4444 // %b = and %a, 2 4445 // %c = setcc eq %b, 0 4446 // brcond %c ... 4447 // 4448 // This applies only when the AND constant value has one bit set and the 4449 // SRL constant is equal to the log2 of the AND constant. The back-end is 4450 // smart enough to convert the result into a TEST/JMP sequence. 4451 SDValue Op0 = N1.getOperand(0); 4452 SDValue Op1 = N1.getOperand(1); 4453 4454 if (Op0.getOpcode() == ISD::AND && 4455 Op0.hasOneUse() && 4456 Op1.getOpcode() == ISD::Constant) { 4457 SDValue AndOp0 = Op0.getOperand(0); 4458 SDValue AndOp1 = Op0.getOperand(1); 4459 4460 if (AndOp1.getOpcode() == ISD::Constant) { 4461 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4462 4463 if (AndConst.isPowerOf2() && 4464 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4465 SDValue SetCC = 4466 DAG.getSetCC(N->getDebugLoc(), 4467 TLI.getSetCCResultType(Op0.getValueType()), 4468 Op0, DAG.getConstant(0, Op0.getValueType()), 4469 ISD::SETNE); 4470 4471 // Replace the uses of SRL with SETCC 4472 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4473 removeFromWorkList(N1.getNode()); 4474 DAG.DeleteNode(N1.getNode()); 4475 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4476 MVT::Other, Chain, SetCC, N2); 4477 } 4478 } 4479 } 4480 } 4481 4482 return SDValue(); 4483} 4484 4485// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4486// 4487SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4488 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4489 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4490 4491 // Use SimplifySetCC to simplify SETCC's. 4492 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4493 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4494 false); 4495 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4496 4497 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4498 4499 // fold br_cc true, dest -> br dest (unconditional branch) 4500 if (SCCC && !SCCC->isNullValue()) 4501 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4502 N->getOperand(0), N->getOperand(4)); 4503 // fold br_cc false, dest -> unconditional fall through 4504 if (SCCC && SCCC->isNullValue()) 4505 return N->getOperand(0); 4506 4507 // fold to a simpler setcc 4508 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4509 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4510 N->getOperand(0), Simp.getOperand(2), 4511 Simp.getOperand(0), Simp.getOperand(1), 4512 N->getOperand(4)); 4513 4514 return SDValue(); 4515} 4516 4517/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4518/// pre-indexed load / store when the base pointer is an add or subtract 4519/// and it has other uses besides the load / store. After the 4520/// transformation, the new indexed load / store has effectively folded 4521/// the add / subtract in and all of its other uses are redirected to the 4522/// new load / store. 4523bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4524 if (!LegalOperations) 4525 return false; 4526 4527 bool isLoad = true; 4528 SDValue Ptr; 4529 MVT VT; 4530 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4531 if (LD->isIndexed()) 4532 return false; 4533 VT = LD->getMemoryVT(); 4534 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4535 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4536 return false; 4537 Ptr = LD->getBasePtr(); 4538 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4539 if (ST->isIndexed()) 4540 return false; 4541 VT = ST->getMemoryVT(); 4542 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4543 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4544 return false; 4545 Ptr = ST->getBasePtr(); 4546 isLoad = false; 4547 } else { 4548 return false; 4549 } 4550 4551 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4552 // out. There is no reason to make this a preinc/predec. 4553 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4554 Ptr.getNode()->hasOneUse()) 4555 return false; 4556 4557 // Ask the target to do addressing mode selection. 4558 SDValue BasePtr; 4559 SDValue Offset; 4560 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4561 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4562 return false; 4563 // Don't create a indexed load / store with zero offset. 4564 if (isa<ConstantSDNode>(Offset) && 4565 cast<ConstantSDNode>(Offset)->isNullValue()) 4566 return false; 4567 4568 // Try turning it into a pre-indexed load / store except when: 4569 // 1) The new base ptr is a frame index. 4570 // 2) If N is a store and the new base ptr is either the same as or is a 4571 // predecessor of the value being stored. 4572 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4573 // that would create a cycle. 4574 // 4) All uses are load / store ops that use it as old base ptr. 4575 4576 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4577 // (plus the implicit offset) to a register to preinc anyway. 4578 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4579 return false; 4580 4581 // Check #2. 4582 if (!isLoad) { 4583 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4584 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4585 return false; 4586 } 4587 4588 // Now check for #3 and #4. 4589 bool RealUse = false; 4590 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4591 E = Ptr.getNode()->use_end(); I != E; ++I) { 4592 SDNode *Use = *I; 4593 if (Use == N) 4594 continue; 4595 if (Use->isPredecessorOf(N)) 4596 return false; 4597 4598 if (!((Use->getOpcode() == ISD::LOAD && 4599 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4600 (Use->getOpcode() == ISD::STORE && 4601 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4602 RealUse = true; 4603 } 4604 4605 if (!RealUse) 4606 return false; 4607 4608 SDValue Result; 4609 if (isLoad) 4610 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4611 BasePtr, Offset, AM); 4612 else 4613 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4614 BasePtr, Offset, AM); 4615 ++PreIndexedNodes; 4616 ++NodesCombined; 4617 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4618 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4619 DOUT << '\n'; 4620 WorkListRemover DeadNodes(*this); 4621 if (isLoad) { 4622 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4623 &DeadNodes); 4624 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4625 &DeadNodes); 4626 } else { 4627 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4628 &DeadNodes); 4629 } 4630 4631 // Finally, since the node is now dead, remove it from the graph. 4632 DAG.DeleteNode(N); 4633 4634 // Replace the uses of Ptr with uses of the updated base value. 4635 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4636 &DeadNodes); 4637 removeFromWorkList(Ptr.getNode()); 4638 DAG.DeleteNode(Ptr.getNode()); 4639 4640 return true; 4641} 4642 4643/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4644/// add / sub of the base pointer node into a post-indexed load / store. 4645/// The transformation folded the add / subtract into the new indexed 4646/// load / store effectively and all of its uses are redirected to the 4647/// new load / store. 4648bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4649 if (!LegalOperations) 4650 return false; 4651 4652 bool isLoad = true; 4653 SDValue Ptr; 4654 MVT VT; 4655 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4656 if (LD->isIndexed()) 4657 return false; 4658 VT = LD->getMemoryVT(); 4659 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4660 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4661 return false; 4662 Ptr = LD->getBasePtr(); 4663 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4664 if (ST->isIndexed()) 4665 return false; 4666 VT = ST->getMemoryVT(); 4667 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4668 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4669 return false; 4670 Ptr = ST->getBasePtr(); 4671 isLoad = false; 4672 } else { 4673 return false; 4674 } 4675 4676 if (Ptr.getNode()->hasOneUse()) 4677 return false; 4678 4679 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4680 E = Ptr.getNode()->use_end(); I != E; ++I) { 4681 SDNode *Op = *I; 4682 if (Op == N || 4683 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4684 continue; 4685 4686 SDValue BasePtr; 4687 SDValue Offset; 4688 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4689 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4690 if (Ptr == Offset) 4691 std::swap(BasePtr, Offset); 4692 if (Ptr != BasePtr) 4693 continue; 4694 // Don't create a indexed load / store with zero offset. 4695 if (isa<ConstantSDNode>(Offset) && 4696 cast<ConstantSDNode>(Offset)->isNullValue()) 4697 continue; 4698 4699 // Try turning it into a post-indexed load / store except when 4700 // 1) All uses are load / store ops that use it as base ptr. 4701 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4702 // nor a successor of N. Otherwise, if Op is folded that would 4703 // create a cycle. 4704 4705 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4706 continue; 4707 4708 // Check for #1. 4709 bool TryNext = false; 4710 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4711 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4712 SDNode *Use = *II; 4713 if (Use == Ptr.getNode()) 4714 continue; 4715 4716 // If all the uses are load / store addresses, then don't do the 4717 // transformation. 4718 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4719 bool RealUse = false; 4720 for (SDNode::use_iterator III = Use->use_begin(), 4721 EEE = Use->use_end(); III != EEE; ++III) { 4722 SDNode *UseUse = *III; 4723 if (!((UseUse->getOpcode() == ISD::LOAD && 4724 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4725 (UseUse->getOpcode() == ISD::STORE && 4726 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4727 RealUse = true; 4728 } 4729 4730 if (!RealUse) { 4731 TryNext = true; 4732 break; 4733 } 4734 } 4735 } 4736 4737 if (TryNext) 4738 continue; 4739 4740 // Check for #2 4741 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4742 SDValue Result = isLoad 4743 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4744 BasePtr, Offset, AM) 4745 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4746 BasePtr, Offset, AM); 4747 ++PostIndexedNodes; 4748 ++NodesCombined; 4749 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4750 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4751 DOUT << '\n'; 4752 WorkListRemover DeadNodes(*this); 4753 if (isLoad) { 4754 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4755 &DeadNodes); 4756 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4757 &DeadNodes); 4758 } else { 4759 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4760 &DeadNodes); 4761 } 4762 4763 // Finally, since the node is now dead, remove it from the graph. 4764 DAG.DeleteNode(N); 4765 4766 // Replace the uses of Use with uses of the updated base value. 4767 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4768 Result.getValue(isLoad ? 1 : 0), 4769 &DeadNodes); 4770 removeFromWorkList(Op); 4771 DAG.DeleteNode(Op); 4772 return true; 4773 } 4774 } 4775 } 4776 4777 return false; 4778} 4779 4780/// InferAlignment - If we can infer some alignment information from this 4781/// pointer, return it. 4782static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4783 // If this is a direct reference to a stack slot, use information about the 4784 // stack slot's alignment. 4785 int FrameIdx = 1 << 31; 4786 int64_t FrameOffset = 0; 4787 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4788 FrameIdx = FI->getIndex(); 4789 } else if (Ptr.getOpcode() == ISD::ADD && 4790 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4791 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4792 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4793 FrameOffset = Ptr.getConstantOperandVal(1); 4794 } 4795 4796 if (FrameIdx != (1 << 31)) { 4797 // FIXME: Handle FI+CST. 4798 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4799 if (MFI.isFixedObjectIndex(FrameIdx)) { 4800 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4801 4802 // The alignment of the frame index can be determined from its offset from 4803 // the incoming frame position. If the frame object is at offset 32 and 4804 // the stack is guaranteed to be 16-byte aligned, then we know that the 4805 // object is 16-byte aligned. 4806 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4807 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4808 4809 // Finally, the frame object itself may have a known alignment. Factor 4810 // the alignment + offset into a new alignment. For example, if we know 4811 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4812 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4813 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4814 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4815 FrameOffset); 4816 return std::max(Align, FIInfoAlign); 4817 } 4818 } 4819 4820 return 0; 4821} 4822 4823SDValue DAGCombiner::visitLOAD(SDNode *N) { 4824 LoadSDNode *LD = cast<LoadSDNode>(N); 4825 SDValue Chain = LD->getChain(); 4826 SDValue Ptr = LD->getBasePtr(); 4827 4828 // Try to infer better alignment information than the load already has. 4829 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4830 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4831 if (Align > LD->getAlignment()) 4832 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4833 LD->getValueType(0), 4834 Chain, Ptr, LD->getSrcValue(), 4835 LD->getSrcValueOffset(), LD->getMemoryVT(), 4836 LD->isVolatile(), Align); 4837 } 4838 } 4839 4840 // If load is not volatile and there are no uses of the loaded value (and 4841 // the updated indexed value in case of indexed loads), change uses of the 4842 // chain value into uses of the chain input (i.e. delete the dead load). 4843 if (!LD->isVolatile()) { 4844 if (N->getValueType(1) == MVT::Other) { 4845 // Unindexed loads. 4846 if (N->hasNUsesOfValue(0, 0)) { 4847 // It's not safe to use the two value CombineTo variant here. e.g. 4848 // v1, chain2 = load chain1, loc 4849 // v2, chain3 = load chain2, loc 4850 // v3 = add v2, c 4851 // Now we replace use of chain2 with chain1. This makes the second load 4852 // isomorphic to the one we are deleting, and thus makes this load live. 4853 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4854 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4855 DOUT << "\n"; 4856 WorkListRemover DeadNodes(*this); 4857 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4858 4859 if (N->use_empty()) { 4860 removeFromWorkList(N); 4861 DAG.DeleteNode(N); 4862 } 4863 4864 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4865 } 4866 } else { 4867 // Indexed loads. 4868 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4869 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4870 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4871 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4872 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4873 DOUT << " and 2 other values\n"; 4874 WorkListRemover DeadNodes(*this); 4875 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4876 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4877 DAG.getUNDEF(N->getValueType(1)), 4878 &DeadNodes); 4879 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4880 removeFromWorkList(N); 4881 DAG.DeleteNode(N); 4882 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4883 } 4884 } 4885 } 4886 4887 // If this load is directly stored, replace the load value with the stored 4888 // value. 4889 // TODO: Handle store large -> read small portion. 4890 // TODO: Handle TRUNCSTORE/LOADEXT 4891 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4892 !LD->isVolatile()) { 4893 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4894 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4895 if (PrevST->getBasePtr() == Ptr && 4896 PrevST->getValue().getValueType() == N->getValueType(0)) 4897 return CombineTo(N, Chain.getOperand(1), Chain); 4898 } 4899 } 4900 4901 if (CombinerAA) { 4902 // Walk up chain skipping non-aliasing memory nodes. 4903 SDValue BetterChain = FindBetterChain(N, Chain); 4904 4905 // If there is a better chain. 4906 if (Chain != BetterChain) { 4907 SDValue ReplLoad; 4908 4909 // Replace the chain to void dependency. 4910 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4911 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4912 BetterChain, Ptr, 4913 LD->getSrcValue(), LD->getSrcValueOffset(), 4914 LD->isVolatile(), LD->getAlignment()); 4915 } else { 4916 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4917 LD->getValueType(0), 4918 BetterChain, Ptr, LD->getSrcValue(), 4919 LD->getSrcValueOffset(), 4920 LD->getMemoryVT(), 4921 LD->isVolatile(), 4922 LD->getAlignment()); 4923 } 4924 4925 // Create token factor to keep old chain connected. 4926 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4927 MVT::Other, Chain, ReplLoad.getValue(1)); 4928 4929 // Replace uses with load result and token factor. Don't add users 4930 // to work list. 4931 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4932 } 4933 } 4934 4935 // Try transforming N to an indexed load. 4936 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4937 return SDValue(N, 0); 4938 4939 return SDValue(); 4940} 4941 4942 4943/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 4944/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 4945/// of the loaded bits, try narrowing the load and store if it would end up 4946/// being a win for performance or code size. 4947SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 4948 StoreSDNode *ST = cast<StoreSDNode>(N); 4949 if (ST->isVolatile()) 4950 return SDValue(); 4951 4952 SDValue Chain = ST->getChain(); 4953 SDValue Value = ST->getValue(); 4954 SDValue Ptr = ST->getBasePtr(); 4955 MVT VT = Value.getValueType(); 4956 4957 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 4958 return SDValue(); 4959 4960 unsigned Opc = Value.getOpcode(); 4961 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 4962 Value.getOperand(1).getOpcode() != ISD::Constant) 4963 return SDValue(); 4964 4965 SDValue N0 = Value.getOperand(0); 4966 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 4967 LoadSDNode *LD = cast<LoadSDNode>(N0); 4968 if (LD->getBasePtr() != Ptr) 4969 return SDValue(); 4970 4971 // Find the type to narrow it the load / op / store to. 4972 SDValue N1 = Value.getOperand(1); 4973 unsigned BitWidth = N1.getValueSizeInBits(); 4974 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 4975 if (Opc == ISD::AND) 4976 Imm ^= APInt::getAllOnesValue(BitWidth); 4977 if (Imm == 0 || Imm.isAllOnesValue()) 4978 return SDValue(); 4979 unsigned ShAmt = Imm.countTrailingZeros(); 4980 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 4981 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 4982 MVT NewVT = MVT::getIntegerVT(NewBW); 4983 while (NewBW < BitWidth && 4984 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 4985 TLI.isNarrowingProfitable(VT, NewVT))) { 4986 NewBW = NextPowerOf2(NewBW); 4987 NewVT = MVT::getIntegerVT(NewBW); 4988 } 4989 if (NewBW >= BitWidth) 4990 return SDValue(); 4991 4992 // If the lsb changed does not start at the type bitwidth boundary, 4993 // start at the previous one. 4994 if (ShAmt % NewBW) 4995 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 4996 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 4997 if ((Imm & Mask) == Imm) { 4998 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 4999 if (Opc == ISD::AND) 5000 NewImm ^= APInt::getAllOnesValue(NewBW); 5001 uint64_t PtrOff = ShAmt / 8; 5002 // For big endian targets, we need to adjust the offset to the pointer to 5003 // load the correct bytes. 5004 if (TLI.isBigEndian()) 5005 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5006 5007 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5008 if (NewAlign < 5009 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT())) 5010 return SDValue(); 5011 5012 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5013 Ptr.getValueType(), Ptr, 5014 DAG.getConstant(PtrOff, Ptr.getValueType())); 5015 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5016 LD->getChain(), NewPtr, 5017 LD->getSrcValue(), LD->getSrcValueOffset(), 5018 LD->isVolatile(), NewAlign); 5019 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5020 DAG.getConstant(NewImm, NewVT)); 5021 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5022 NewVal, NewPtr, 5023 ST->getSrcValue(), ST->getSrcValueOffset(), 5024 false, NewAlign); 5025 5026 AddToWorkList(NewPtr.getNode()); 5027 AddToWorkList(NewLD.getNode()); 5028 AddToWorkList(NewVal.getNode()); 5029 WorkListRemover DeadNodes(*this); 5030 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5031 &DeadNodes); 5032 ++OpsNarrowed; 5033 return NewST; 5034 } 5035 } 5036 5037 return SDValue(); 5038} 5039 5040SDValue DAGCombiner::visitSTORE(SDNode *N) { 5041 StoreSDNode *ST = cast<StoreSDNode>(N); 5042 SDValue Chain = ST->getChain(); 5043 SDValue Value = ST->getValue(); 5044 SDValue Ptr = ST->getBasePtr(); 5045 5046 // Try to infer better alignment information than the store already has. 5047 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5048 if (unsigned Align = InferAlignment(Ptr, DAG)) { 5049 if (Align > ST->getAlignment()) 5050 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5051 Ptr, ST->getSrcValue(), 5052 ST->getSrcValueOffset(), ST->getMemoryVT(), 5053 ST->isVolatile(), Align); 5054 } 5055 } 5056 5057 // If this is a store of a bit convert, store the input value if the 5058 // resultant store does not need a higher alignment than the original. 5059 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5060 ST->isUnindexed()) { 5061 unsigned OrigAlign = ST->getAlignment(); 5062 MVT SVT = Value.getOperand(0).getValueType(); 5063 unsigned Align = TLI.getTargetData()-> 5064 getABITypeAlignment(SVT.getTypeForMVT()); 5065 if (Align <= OrigAlign && 5066 ((!LegalOperations && !ST->isVolatile()) || 5067 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5068 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5069 Ptr, ST->getSrcValue(), 5070 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5071 } 5072 5073 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5074 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5075 // NOTE: If the original store is volatile, this transform must not increase 5076 // the number of stores. For example, on x86-32 an f64 can be stored in one 5077 // processor operation but an i64 (which is not legal) requires two. So the 5078 // transform should not be done in this case. 5079 if (Value.getOpcode() != ISD::TargetConstantFP) { 5080 SDValue Tmp; 5081 switch (CFP->getValueType(0).getSimpleVT()) { 5082 default: llvm_unreachable("Unknown FP type"); 5083 case MVT::f80: // We don't do this for these yet. 5084 case MVT::f128: 5085 case MVT::ppcf128: 5086 break; 5087 case MVT::f32: 5088 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5089 !ST->isVolatile()) || 5090 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5091 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5092 bitcastToAPInt().getZExtValue(), MVT::i32); 5093 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5094 Ptr, ST->getSrcValue(), 5095 ST->getSrcValueOffset(), ST->isVolatile(), 5096 ST->getAlignment()); 5097 } 5098 break; 5099 case MVT::f64: 5100 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5101 !ST->isVolatile()) || 5102 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5103 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5104 getZExtValue(), MVT::i64); 5105 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5106 Ptr, ST->getSrcValue(), 5107 ST->getSrcValueOffset(), ST->isVolatile(), 5108 ST->getAlignment()); 5109 } else if (!ST->isVolatile() && 5110 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5111 // Many FP stores are not made apparent until after legalize, e.g. for 5112 // argument passing. Since this is so common, custom legalize the 5113 // 64-bit integer store into two 32-bit stores. 5114 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5115 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5116 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5117 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5118 5119 int SVOffset = ST->getSrcValueOffset(); 5120 unsigned Alignment = ST->getAlignment(); 5121 bool isVolatile = ST->isVolatile(); 5122 5123 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5124 Ptr, ST->getSrcValue(), 5125 ST->getSrcValueOffset(), 5126 isVolatile, ST->getAlignment()); 5127 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5128 DAG.getConstant(4, Ptr.getValueType())); 5129 SVOffset += 4; 5130 Alignment = MinAlign(Alignment, 4U); 5131 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5132 Ptr, ST->getSrcValue(), 5133 SVOffset, isVolatile, Alignment); 5134 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5135 St0, St1); 5136 } 5137 5138 break; 5139 } 5140 } 5141 } 5142 5143 if (CombinerAA) { 5144 // Walk up chain skipping non-aliasing memory nodes. 5145 SDValue BetterChain = FindBetterChain(N, Chain); 5146 5147 // If there is a better chain. 5148 if (Chain != BetterChain) { 5149 // Replace the chain to avoid dependency. 5150 SDValue ReplStore; 5151 if (ST->isTruncatingStore()) { 5152 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5153 ST->getSrcValue(),ST->getSrcValueOffset(), 5154 ST->getMemoryVT(), 5155 ST->isVolatile(), ST->getAlignment()); 5156 } else { 5157 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5158 ST->getSrcValue(), ST->getSrcValueOffset(), 5159 ST->isVolatile(), ST->getAlignment()); 5160 } 5161 5162 // Create token to keep both nodes around. 5163 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5164 MVT::Other, Chain, ReplStore); 5165 5166 // Don't add users to work list. 5167 return CombineTo(N, Token, false); 5168 } 5169 } 5170 5171 // Try transforming N to an indexed store. 5172 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5173 return SDValue(N, 0); 5174 5175 // FIXME: is there such a thing as a truncating indexed store? 5176 if (ST->isTruncatingStore() && ST->isUnindexed() && 5177 Value.getValueType().isInteger()) { 5178 // See if we can simplify the input to this truncstore with knowledge that 5179 // only the low bits are being used. For example: 5180 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5181 SDValue Shorter = 5182 GetDemandedBits(Value, 5183 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5184 ST->getMemoryVT().getSizeInBits())); 5185 AddToWorkList(Value.getNode()); 5186 if (Shorter.getNode()) 5187 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5188 Ptr, ST->getSrcValue(), 5189 ST->getSrcValueOffset(), ST->getMemoryVT(), 5190 ST->isVolatile(), ST->getAlignment()); 5191 5192 // Otherwise, see if we can simplify the operation with 5193 // SimplifyDemandedBits, which only works if the value has a single use. 5194 if (SimplifyDemandedBits(Value, 5195 APInt::getLowBitsSet( 5196 Value.getValueSizeInBits(), 5197 ST->getMemoryVT().getSizeInBits()))) 5198 return SDValue(N, 0); 5199 } 5200 5201 // If this is a load followed by a store to the same location, then the store 5202 // is dead/noop. 5203 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5204 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5205 ST->isUnindexed() && !ST->isVolatile() && 5206 // There can't be any side effects between the load and store, such as 5207 // a call or store. 5208 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5209 // The store is dead, remove it. 5210 return Chain; 5211 } 5212 } 5213 5214 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5215 // truncating store. We can do this even if this is already a truncstore. 5216 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5217 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5218 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5219 ST->getMemoryVT())) { 5220 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5221 Ptr, ST->getSrcValue(), 5222 ST->getSrcValueOffset(), ST->getMemoryVT(), 5223 ST->isVolatile(), ST->getAlignment()); 5224 } 5225 5226 return ReduceLoadOpStoreWidth(N); 5227} 5228 5229SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5230 SDValue InVec = N->getOperand(0); 5231 SDValue InVal = N->getOperand(1); 5232 SDValue EltNo = N->getOperand(2); 5233 5234 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5235 // vector with the inserted element. 5236 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5237 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5238 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5239 InVec.getNode()->op_end()); 5240 if (Elt < Ops.size()) 5241 Ops[Elt] = InVal; 5242 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5243 InVec.getValueType(), &Ops[0], Ops.size()); 5244 } 5245 // If the invec is an UNDEF and if EltNo is a constant, create a new 5246 // BUILD_VECTOR with undef elements and the inserted element. 5247 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5248 isa<ConstantSDNode>(EltNo)) { 5249 MVT VT = InVec.getValueType(); 5250 MVT EVT = VT.getVectorElementType(); 5251 unsigned NElts = VT.getVectorNumElements(); 5252 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT)); 5253 5254 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5255 if (Elt < Ops.size()) 5256 Ops[Elt] = InVal; 5257 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5258 InVec.getValueType(), &Ops[0], Ops.size()); 5259 } 5260 return SDValue(); 5261} 5262 5263SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5264 // (vextract (scalar_to_vector val, 0) -> val 5265 SDValue InVec = N->getOperand(0); 5266 5267 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5268 // If the operand is wider than the vector element type then it is implicitly 5269 // truncated. Make that explicit here. 5270 MVT EltVT = InVec.getValueType().getVectorElementType(); 5271 SDValue InOp = InVec.getOperand(0); 5272 if (InOp.getValueType() != EltVT) 5273 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5274 return InOp; 5275 } 5276 5277 // Perform only after legalization to ensure build_vector / vector_shuffle 5278 // optimizations have already been done. 5279 if (!LegalOperations) return SDValue(); 5280 5281 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5282 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5283 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5284 SDValue EltNo = N->getOperand(1); 5285 5286 if (isa<ConstantSDNode>(EltNo)) { 5287 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5288 bool NewLoad = false; 5289 bool BCNumEltsChanged = false; 5290 MVT VT = InVec.getValueType(); 5291 MVT EVT = VT.getVectorElementType(); 5292 MVT LVT = EVT; 5293 5294 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5295 MVT BCVT = InVec.getOperand(0).getValueType(); 5296 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5297 return SDValue(); 5298 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5299 BCNumEltsChanged = true; 5300 InVec = InVec.getOperand(0); 5301 EVT = BCVT.getVectorElementType(); 5302 NewLoad = true; 5303 } 5304 5305 LoadSDNode *LN0 = NULL; 5306 const ShuffleVectorSDNode *SVN = NULL; 5307 if (ISD::isNormalLoad(InVec.getNode())) { 5308 LN0 = cast<LoadSDNode>(InVec); 5309 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5310 InVec.getOperand(0).getValueType() == EVT && 5311 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5312 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5313 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5314 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5315 // => 5316 // (load $addr+1*size) 5317 5318 // If the bit convert changed the number of elements, it is unsafe 5319 // to examine the mask. 5320 if (BCNumEltsChanged) 5321 return SDValue(); 5322 5323 // Select the input vector, guarding against out of range extract vector. 5324 unsigned NumElems = VT.getVectorNumElements(); 5325 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5326 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5327 5328 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5329 InVec = InVec.getOperand(0); 5330 if (ISD::isNormalLoad(InVec.getNode())) { 5331 LN0 = cast<LoadSDNode>(InVec); 5332 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5333 } 5334 } 5335 5336 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5337 return SDValue(); 5338 5339 unsigned Align = LN0->getAlignment(); 5340 if (NewLoad) { 5341 // Check the resultant load doesn't need a higher alignment than the 5342 // original load. 5343 unsigned NewAlign = 5344 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); 5345 5346 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5347 return SDValue(); 5348 5349 Align = NewAlign; 5350 } 5351 5352 SDValue NewPtr = LN0->getBasePtr(); 5353 if (Elt) { 5354 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5355 MVT PtrType = NewPtr.getValueType(); 5356 if (TLI.isBigEndian()) 5357 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5358 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5359 DAG.getConstant(PtrOff, PtrType)); 5360 } 5361 5362 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5363 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5364 LN0->isVolatile(), Align); 5365 } 5366 5367 return SDValue(); 5368} 5369 5370SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5371 unsigned NumInScalars = N->getNumOperands(); 5372 MVT VT = N->getValueType(0); 5373 MVT EltType = VT.getVectorElementType(); 5374 5375 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5376 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5377 // at most two distinct vectors, turn this into a shuffle node. 5378 SDValue VecIn1, VecIn2; 5379 for (unsigned i = 0; i != NumInScalars; ++i) { 5380 // Ignore undef inputs. 5381 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5382 5383 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5384 // constant index, bail out. 5385 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5386 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5387 VecIn1 = VecIn2 = SDValue(0, 0); 5388 break; 5389 } 5390 5391 // If the input vector type disagrees with the result of the build_vector, 5392 // we can't make a shuffle. 5393 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5394 if (ExtractedFromVec.getValueType() != VT) { 5395 VecIn1 = VecIn2 = SDValue(0, 0); 5396 break; 5397 } 5398 5399 // Otherwise, remember this. We allow up to two distinct input vectors. 5400 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5401 continue; 5402 5403 if (VecIn1.getNode() == 0) { 5404 VecIn1 = ExtractedFromVec; 5405 } else if (VecIn2.getNode() == 0) { 5406 VecIn2 = ExtractedFromVec; 5407 } else { 5408 // Too many inputs. 5409 VecIn1 = VecIn2 = SDValue(0, 0); 5410 break; 5411 } 5412 } 5413 5414 // If everything is good, we can make a shuffle operation. 5415 if (VecIn1.getNode()) { 5416 SmallVector<int, 8> Mask; 5417 for (unsigned i = 0; i != NumInScalars; ++i) { 5418 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5419 Mask.push_back(-1); 5420 continue; 5421 } 5422 5423 // If extracting from the first vector, just use the index directly. 5424 SDValue Extract = N->getOperand(i); 5425 SDValue ExtVal = Extract.getOperand(1); 5426 if (Extract.getOperand(0) == VecIn1) { 5427 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5428 if (ExtIndex > VT.getVectorNumElements()) 5429 return SDValue(); 5430 5431 Mask.push_back(ExtIndex); 5432 continue; 5433 } 5434 5435 // Otherwise, use InIdx + VecSize 5436 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5437 Mask.push_back(Idx+NumInScalars); 5438 } 5439 5440 // Add count and size info. 5441 if (!TLI.isTypeLegal(VT) && LegalTypes) 5442 return SDValue(); 5443 5444 // Return the new VECTOR_SHUFFLE node. 5445 SDValue Ops[2]; 5446 Ops[0] = VecIn1; 5447 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5448 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5449 } 5450 5451 return SDValue(); 5452} 5453 5454SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5455 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5456 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5457 // inputs come from at most two distinct vectors, turn this into a shuffle 5458 // node. 5459 5460 // If we only have one input vector, we don't need to do any concatenation. 5461 if (N->getNumOperands() == 1) 5462 return N->getOperand(0); 5463 5464 return SDValue(); 5465} 5466 5467SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5468 return SDValue(); 5469 5470 MVT VT = N->getValueType(0); 5471 unsigned NumElts = VT.getVectorNumElements(); 5472 5473 SDValue N0 = N->getOperand(0); 5474 SDValue N1 = N->getOperand(1); 5475 5476 assert(N0.getValueType().getVectorNumElements() == NumElts && 5477 "Vector shuffle must be normalized in DAG"); 5478 5479 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5480 5481 // If it is a splat, check if the argument vector is a build_vector with 5482 // all scalar elements the same. 5483 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5484 SDNode *V = N0.getNode(); 5485 5486 5487 // If this is a bit convert that changes the element type of the vector but 5488 // not the number of vector elements, look through it. Be careful not to 5489 // look though conversions that change things like v4f32 to v2f64. 5490 if (V->getOpcode() == ISD::BIT_CONVERT) { 5491 SDValue ConvInput = V->getOperand(0); 5492 if (ConvInput.getValueType().isVector() && 5493 ConvInput.getValueType().getVectorNumElements() == NumElts) 5494 V = ConvInput.getNode(); 5495 } 5496 5497 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5498 unsigned NumElems = V->getNumOperands(); 5499 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5500 if (NumElems > BaseIdx) { 5501 SDValue Base; 5502 bool AllSame = true; 5503 for (unsigned i = 0; i != NumElems; ++i) { 5504 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5505 Base = V->getOperand(i); 5506 break; 5507 } 5508 } 5509 // Splat of <u, u, u, u>, return <u, u, u, u> 5510 if (!Base.getNode()) 5511 return N0; 5512 for (unsigned i = 0; i != NumElems; ++i) { 5513 if (V->getOperand(i) != Base) { 5514 AllSame = false; 5515 break; 5516 } 5517 } 5518 // Splat of <x, x, x, x>, return <x, x, x, x> 5519 if (AllSame) 5520 return N0; 5521 } 5522 } 5523 } 5524 return SDValue(); 5525} 5526 5527/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5528/// an AND to a vector_shuffle with the destination vector and a zero vector. 5529/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5530/// vector_shuffle V, Zero, <0, 4, 2, 4> 5531SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5532 MVT VT = N->getValueType(0); 5533 DebugLoc dl = N->getDebugLoc(); 5534 SDValue LHS = N->getOperand(0); 5535 SDValue RHS = N->getOperand(1); 5536 if (N->getOpcode() == ISD::AND) { 5537 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5538 RHS = RHS.getOperand(0); 5539 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5540 SmallVector<int, 8> Indices; 5541 unsigned NumElts = RHS.getNumOperands(); 5542 for (unsigned i = 0; i != NumElts; ++i) { 5543 SDValue Elt = RHS.getOperand(i); 5544 if (!isa<ConstantSDNode>(Elt)) 5545 return SDValue(); 5546 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5547 Indices.push_back(i); 5548 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5549 Indices.push_back(NumElts); 5550 else 5551 return SDValue(); 5552 } 5553 5554 // Let's see if the target supports this vector_shuffle. 5555 MVT RVT = RHS.getValueType(); 5556 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5557 return SDValue(); 5558 5559 // Return the new VECTOR_SHUFFLE node. 5560 MVT EVT = RVT.getVectorElementType(); 5561 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5562 DAG.getConstant(0, EVT)); 5563 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5564 RVT, &ZeroOps[0], ZeroOps.size()); 5565 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5566 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5567 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5568 } 5569 } 5570 5571 return SDValue(); 5572} 5573 5574/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5575SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5576 // After legalize, the target may be depending on adds and other 5577 // binary ops to provide legal ways to construct constants or other 5578 // things. Simplifying them may result in a loss of legality. 5579 if (LegalOperations) return SDValue(); 5580 5581 MVT VT = N->getValueType(0); 5582 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5583 5584 MVT EltType = VT.getVectorElementType(); 5585 SDValue LHS = N->getOperand(0); 5586 SDValue RHS = N->getOperand(1); 5587 SDValue Shuffle = XformToShuffleWithZero(N); 5588 if (Shuffle.getNode()) return Shuffle; 5589 5590 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5591 // this operation. 5592 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5593 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5594 SmallVector<SDValue, 8> Ops; 5595 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5596 SDValue LHSOp = LHS.getOperand(i); 5597 SDValue RHSOp = RHS.getOperand(i); 5598 // If these two elements can't be folded, bail out. 5599 if ((LHSOp.getOpcode() != ISD::UNDEF && 5600 LHSOp.getOpcode() != ISD::Constant && 5601 LHSOp.getOpcode() != ISD::ConstantFP) || 5602 (RHSOp.getOpcode() != ISD::UNDEF && 5603 RHSOp.getOpcode() != ISD::Constant && 5604 RHSOp.getOpcode() != ISD::ConstantFP)) 5605 break; 5606 5607 // Can't fold divide by zero. 5608 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5609 N->getOpcode() == ISD::FDIV) { 5610 if ((RHSOp.getOpcode() == ISD::Constant && 5611 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5612 (RHSOp.getOpcode() == ISD::ConstantFP && 5613 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5614 break; 5615 } 5616 5617 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5618 EltType, LHSOp, RHSOp)); 5619 AddToWorkList(Ops.back().getNode()); 5620 assert((Ops.back().getOpcode() == ISD::UNDEF || 5621 Ops.back().getOpcode() == ISD::Constant || 5622 Ops.back().getOpcode() == ISD::ConstantFP) && 5623 "Scalar binop didn't fold!"); 5624 } 5625 5626 if (Ops.size() == LHS.getNumOperands()) { 5627 MVT VT = LHS.getValueType(); 5628 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5629 &Ops[0], Ops.size()); 5630 } 5631 } 5632 5633 return SDValue(); 5634} 5635 5636SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5637 SDValue N1, SDValue N2){ 5638 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5639 5640 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5641 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5642 5643 // If we got a simplified select_cc node back from SimplifySelectCC, then 5644 // break it down into a new SETCC node, and a new SELECT node, and then return 5645 // the SELECT node, since we were called with a SELECT node. 5646 if (SCC.getNode()) { 5647 // Check to see if we got a select_cc back (to turn into setcc/select). 5648 // Otherwise, just return whatever node we got back, like fabs. 5649 if (SCC.getOpcode() == ISD::SELECT_CC) { 5650 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5651 N0.getValueType(), 5652 SCC.getOperand(0), SCC.getOperand(1), 5653 SCC.getOperand(4)); 5654 AddToWorkList(SETCC.getNode()); 5655 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5656 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5657 } 5658 5659 return SCC; 5660 } 5661 return SDValue(); 5662} 5663 5664/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5665/// are the two values being selected between, see if we can simplify the 5666/// select. Callers of this should assume that TheSelect is deleted if this 5667/// returns true. As such, they should return the appropriate thing (e.g. the 5668/// node) back to the top-level of the DAG combiner loop to avoid it being 5669/// looked at. 5670bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5671 SDValue RHS) { 5672 5673 // If this is a select from two identical things, try to pull the operation 5674 // through the select. 5675 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5676 // If this is a load and the token chain is identical, replace the select 5677 // of two loads with a load through a select of the address to load from. 5678 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5679 // constants have been dropped into the constant pool. 5680 if (LHS.getOpcode() == ISD::LOAD && 5681 // Do not let this transformation reduce the number of volatile loads. 5682 !cast<LoadSDNode>(LHS)->isVolatile() && 5683 !cast<LoadSDNode>(RHS)->isVolatile() && 5684 // Token chains must be identical. 5685 LHS.getOperand(0) == RHS.getOperand(0)) { 5686 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5687 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5688 5689 // If this is an EXTLOAD, the VT's must match. 5690 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5691 // FIXME: this conflates two src values, discarding one. This is not 5692 // the right thing to do, but nothing uses srcvalues now. When they do, 5693 // turn SrcValue into a list of locations. 5694 SDValue Addr; 5695 if (TheSelect->getOpcode() == ISD::SELECT) { 5696 // Check that the condition doesn't reach either load. If so, folding 5697 // this will induce a cycle into the DAG. 5698 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5699 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5700 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5701 LLD->getBasePtr().getValueType(), 5702 TheSelect->getOperand(0), LLD->getBasePtr(), 5703 RLD->getBasePtr()); 5704 } 5705 } else { 5706 // Check that the condition doesn't reach either load. If so, folding 5707 // this will induce a cycle into the DAG. 5708 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5709 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5710 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5711 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5712 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5713 LLD->getBasePtr().getValueType(), 5714 TheSelect->getOperand(0), 5715 TheSelect->getOperand(1), 5716 LLD->getBasePtr(), RLD->getBasePtr(), 5717 TheSelect->getOperand(4)); 5718 } 5719 } 5720 5721 if (Addr.getNode()) { 5722 SDValue Load; 5723 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5724 Load = DAG.getLoad(TheSelect->getValueType(0), 5725 TheSelect->getDebugLoc(), 5726 LLD->getChain(), 5727 Addr,LLD->getSrcValue(), 5728 LLD->getSrcValueOffset(), 5729 LLD->isVolatile(), 5730 LLD->getAlignment()); 5731 } else { 5732 Load = DAG.getExtLoad(LLD->getExtensionType(), 5733 TheSelect->getDebugLoc(), 5734 TheSelect->getValueType(0), 5735 LLD->getChain(), Addr, LLD->getSrcValue(), 5736 LLD->getSrcValueOffset(), 5737 LLD->getMemoryVT(), 5738 LLD->isVolatile(), 5739 LLD->getAlignment()); 5740 } 5741 5742 // Users of the select now use the result of the load. 5743 CombineTo(TheSelect, Load); 5744 5745 // Users of the old loads now use the new load's chain. We know the 5746 // old-load value is dead now. 5747 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5748 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5749 return true; 5750 } 5751 } 5752 } 5753 } 5754 5755 return false; 5756} 5757 5758/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5759/// where 'cond' is the comparison specified by CC. 5760SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5761 SDValue N2, SDValue N3, 5762 ISD::CondCode CC, bool NotExtCompare) { 5763 // (x ? y : y) -> y. 5764 if (N2 == N3) return N2; 5765 5766 MVT VT = N2.getValueType(); 5767 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5768 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5769 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5770 5771 // Determine if the condition we're dealing with is constant 5772 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5773 N0, N1, CC, DL, false); 5774 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5775 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5776 5777 // fold select_cc true, x, y -> x 5778 if (SCCC && !SCCC->isNullValue()) 5779 return N2; 5780 // fold select_cc false, x, y -> y 5781 if (SCCC && SCCC->isNullValue()) 5782 return N3; 5783 5784 // Check to see if we can simplify the select into an fabs node 5785 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5786 // Allow either -0.0 or 0.0 5787 if (CFP->getValueAPF().isZero()) { 5788 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5789 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5790 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5791 N2 == N3.getOperand(0)) 5792 return DAG.getNode(ISD::FABS, DL, VT, N0); 5793 5794 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5795 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5796 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5797 N2.getOperand(0) == N3) 5798 return DAG.getNode(ISD::FABS, DL, VT, N3); 5799 } 5800 } 5801 5802 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5803 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5804 // in it. This is a win when the constant is not otherwise available because 5805 // it replaces two constant pool loads with one. We only do this if the FP 5806 // type is known to be legal, because if it isn't, then we are before legalize 5807 // types an we want the other legalization to happen first (e.g. to avoid 5808 // messing with soft float) and if the ConstantFP is not legal, because if 5809 // it is legal, we may not need to store the FP constant in a constant pool. 5810 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5811 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5812 if (TLI.isTypeLegal(N2.getValueType()) && 5813 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5814 TargetLowering::Legal) && 5815 // If both constants have multiple uses, then we won't need to do an 5816 // extra load, they are likely around in registers for other users. 5817 (TV->hasOneUse() || FV->hasOneUse())) { 5818 Constant *Elts[] = { 5819 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5820 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5821 }; 5822 const Type *FPTy = Elts[0]->getType(); 5823 const TargetData &TD = *TLI.getTargetData(); 5824 5825 // Create a ConstantArray of the two constants. 5826 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5827 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5828 TD.getPrefTypeAlignment(FPTy)); 5829 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5830 5831 // Get the offsets to the 0 and 1 element of the array so that we can 5832 // select between them. 5833 SDValue Zero = DAG.getIntPtrConstant(0); 5834 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5835 SDValue One = DAG.getIntPtrConstant(EltSize); 5836 5837 SDValue Cond = DAG.getSetCC(DL, 5838 TLI.getSetCCResultType(N0.getValueType()), 5839 N0, N1, CC); 5840 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5841 Cond, One, Zero); 5842 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5843 CstOffset); 5844 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5845 PseudoSourceValue::getConstantPool(), 0, false, 5846 Alignment); 5847 5848 } 5849 } 5850 5851 // Check to see if we can perform the "gzip trick", transforming 5852 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5853 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5854 N0.getValueType().isInteger() && 5855 N2.getValueType().isInteger() && 5856 (N1C->isNullValue() || // (a < 0) ? b : 0 5857 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5858 MVT XType = N0.getValueType(); 5859 MVT AType = N2.getValueType(); 5860 if (XType.bitsGE(AType)) { 5861 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5862 // single-bit constant. 5863 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5864 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5865 ShCtV = XType.getSizeInBits()-ShCtV-1; 5866 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5867 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5868 XType, N0, ShCt); 5869 AddToWorkList(Shift.getNode()); 5870 5871 if (XType.bitsGT(AType)) { 5872 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5873 AddToWorkList(Shift.getNode()); 5874 } 5875 5876 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5877 } 5878 5879 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5880 XType, N0, 5881 DAG.getConstant(XType.getSizeInBits()-1, 5882 getShiftAmountTy())); 5883 AddToWorkList(Shift.getNode()); 5884 5885 if (XType.bitsGT(AType)) { 5886 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5887 AddToWorkList(Shift.getNode()); 5888 } 5889 5890 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5891 } 5892 } 5893 5894 // fold select C, 16, 0 -> shl C, 4 5895 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5896 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5897 5898 // If the caller doesn't want us to simplify this into a zext of a compare, 5899 // don't do it. 5900 if (NotExtCompare && N2C->getAPIntValue() == 1) 5901 return SDValue(); 5902 5903 // Get a SetCC of the condition 5904 // FIXME: Should probably make sure that setcc is legal if we ever have a 5905 // target where it isn't. 5906 SDValue Temp, SCC; 5907 // cast from setcc result type to select result type 5908 if (LegalTypes) { 5909 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5910 N0, N1, CC); 5911 if (N2.getValueType().bitsLT(SCC.getValueType())) 5912 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5913 else 5914 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5915 N2.getValueType(), SCC); 5916 } else { 5917 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5918 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5919 N2.getValueType(), SCC); 5920 } 5921 5922 AddToWorkList(SCC.getNode()); 5923 AddToWorkList(Temp.getNode()); 5924 5925 if (N2C->getAPIntValue() == 1) 5926 return Temp; 5927 5928 // shl setcc result by log2 n2c 5929 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5930 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5931 getShiftAmountTy())); 5932 } 5933 5934 // Check to see if this is the equivalent of setcc 5935 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5936 // otherwise, go ahead with the folds. 5937 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5938 MVT XType = N0.getValueType(); 5939 if (!LegalOperations || 5940 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5941 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5942 if (Res.getValueType() != VT) 5943 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5944 return Res; 5945 } 5946 5947 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5948 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5949 (!LegalOperations || 5950 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5951 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5952 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5953 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5954 getShiftAmountTy())); 5955 } 5956 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5957 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5958 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5959 XType, DAG.getConstant(0, XType), N0); 5960 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5961 return DAG.getNode(ISD::SRL, DL, XType, 5962 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5963 DAG.getConstant(XType.getSizeInBits()-1, 5964 getShiftAmountTy())); 5965 } 5966 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5967 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5968 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5969 DAG.getConstant(XType.getSizeInBits()-1, 5970 getShiftAmountTy())); 5971 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5972 } 5973 } 5974 5975 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5976 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5977 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5978 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5979 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5980 MVT XType = N0.getValueType(); 5981 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5982 DAG.getConstant(XType.getSizeInBits()-1, 5983 getShiftAmountTy())); 5984 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5985 N0, Shift); 5986 AddToWorkList(Shift.getNode()); 5987 AddToWorkList(Add.getNode()); 5988 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5989 } 5990 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5991 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5992 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5993 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5994 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5995 MVT XType = N0.getValueType(); 5996 if (SubC->isNullValue() && XType.isInteger()) { 5997 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5998 N0, 5999 DAG.getConstant(XType.getSizeInBits()-1, 6000 getShiftAmountTy())); 6001 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6002 XType, N0, Shift); 6003 AddToWorkList(Shift.getNode()); 6004 AddToWorkList(Add.getNode()); 6005 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6006 } 6007 } 6008 } 6009 6010 return SDValue(); 6011} 6012 6013/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6014SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 6015 SDValue N1, ISD::CondCode Cond, 6016 DebugLoc DL, bool foldBooleans) { 6017 TargetLowering::DAGCombinerInfo 6018 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6019 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6020} 6021 6022/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6023/// return a DAG expression to select that will generate the same value by 6024/// multiplying by a magic number. See: 6025/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6026SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6027 std::vector<SDNode*> Built; 6028 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6029 6030 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6031 ii != ee; ++ii) 6032 AddToWorkList(*ii); 6033 return S; 6034} 6035 6036/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6037/// return a DAG expression to select that will generate the same value by 6038/// multiplying by a magic number. See: 6039/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6040SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6041 std::vector<SDNode*> Built; 6042 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6043 6044 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6045 ii != ee; ++ii) 6046 AddToWorkList(*ii); 6047 return S; 6048} 6049 6050/// FindBaseOffset - Return true if base is known not to alias with anything 6051/// but itself. Provides base object and offset as results. 6052static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 6053 // Assume it is a primitive operation. 6054 Base = Ptr; Offset = 0; 6055 6056 // If it's an adding a simple constant then integrate the offset. 6057 if (Base.getOpcode() == ISD::ADD) { 6058 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6059 Base = Base.getOperand(0); 6060 Offset += C->getZExtValue(); 6061 } 6062 } 6063 6064 // If it's any of the following then it can't alias with anything but itself. 6065 return isa<FrameIndexSDNode>(Base) || 6066 isa<ConstantPoolSDNode>(Base) || 6067 isa<GlobalAddressSDNode>(Base); 6068} 6069 6070/// isAlias - Return true if there is any possibility that the two addresses 6071/// overlap. 6072bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6073 const Value *SrcValue1, int SrcValueOffset1, 6074 SDValue Ptr2, int64_t Size2, 6075 const Value *SrcValue2, int SrcValueOffset2) const { 6076 // If they are the same then they must be aliases. 6077 if (Ptr1 == Ptr2) return true; 6078 6079 // Gather base node and offset information. 6080 SDValue Base1, Base2; 6081 int64_t Offset1, Offset2; 6082 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 6083 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 6084 6085 // If they have a same base address then... 6086 if (Base1 == Base2) 6087 // Check to see if the addresses overlap. 6088 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6089 6090 // If we know both bases then they can't alias. 6091 if (KnownBase1 && KnownBase2) return false; 6092 6093 if (CombinerGlobalAA) { 6094 // Use alias analysis information. 6095 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6096 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6097 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6098 AliasAnalysis::AliasResult AAResult = 6099 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6100 if (AAResult == AliasAnalysis::NoAlias) 6101 return false; 6102 } 6103 6104 // Otherwise we have to assume they alias. 6105 return true; 6106} 6107 6108/// FindAliasInfo - Extracts the relevant alias information from the memory 6109/// node. Returns true if the operand was a load. 6110bool DAGCombiner::FindAliasInfo(SDNode *N, 6111 SDValue &Ptr, int64_t &Size, 6112 const Value *&SrcValue, int &SrcValueOffset) const { 6113 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6114 Ptr = LD->getBasePtr(); 6115 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6116 SrcValue = LD->getSrcValue(); 6117 SrcValueOffset = LD->getSrcValueOffset(); 6118 return true; 6119 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6120 Ptr = ST->getBasePtr(); 6121 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6122 SrcValue = ST->getSrcValue(); 6123 SrcValueOffset = ST->getSrcValueOffset(); 6124 } else { 6125 llvm_unreachable("FindAliasInfo expected a memory operand"); 6126 } 6127 6128 return false; 6129} 6130 6131/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6132/// looking for aliasing nodes and adding them to the Aliases vector. 6133void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6134 SmallVector<SDValue, 8> &Aliases) { 6135 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6136 std::set<SDNode *> Visited; // Visited node set. 6137 6138 // Get alias information for node. 6139 SDValue Ptr; 6140 int64_t Size = 0; 6141 const Value *SrcValue = 0; 6142 int SrcValueOffset = 0; 6143 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6144 6145 // Starting off. 6146 Chains.push_back(OriginalChain); 6147 6148 // Look at each chain and determine if it is an alias. If so, add it to the 6149 // aliases list. If not, then continue up the chain looking for the next 6150 // candidate. 6151 while (!Chains.empty()) { 6152 SDValue Chain = Chains.back(); 6153 Chains.pop_back(); 6154 6155 // Don't bother if we've been before. 6156 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6157 Visited.insert(Chain.getNode()); 6158 6159 switch (Chain.getOpcode()) { 6160 case ISD::EntryToken: 6161 // Entry token is ideal chain operand, but handled in FindBetterChain. 6162 break; 6163 6164 case ISD::LOAD: 6165 case ISD::STORE: { 6166 // Get alias information for Chain. 6167 SDValue OpPtr; 6168 int64_t OpSize = 0; 6169 const Value *OpSrcValue = 0; 6170 int OpSrcValueOffset = 0; 6171 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6172 OpSrcValue, OpSrcValueOffset); 6173 6174 // If chain is alias then stop here. 6175 if (!(IsLoad && IsOpLoad) && 6176 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6177 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6178 Aliases.push_back(Chain); 6179 } else { 6180 // Look further up the chain. 6181 Chains.push_back(Chain.getOperand(0)); 6182 // Clean up old chain. 6183 AddToWorkList(Chain.getNode()); 6184 } 6185 break; 6186 } 6187 6188 case ISD::TokenFactor: 6189 // We have to check each of the operands of the token factor, so we queue 6190 // then up. Adding the operands to the queue (stack) in reverse order 6191 // maintains the original order and increases the likelihood that getNode 6192 // will find a matching token factor (CSE.) 6193 for (unsigned n = Chain.getNumOperands(); n;) 6194 Chains.push_back(Chain.getOperand(--n)); 6195 // Eliminate the token factor if we can. 6196 AddToWorkList(Chain.getNode()); 6197 break; 6198 6199 default: 6200 // For all other instructions we will just have to take what we can get. 6201 Aliases.push_back(Chain); 6202 break; 6203 } 6204 } 6205} 6206 6207/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6208/// for a better chain (aliasing node.) 6209SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6210 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6211 6212 // Accumulate all the aliases to this node. 6213 GatherAllAliases(N, OldChain, Aliases); 6214 6215 if (Aliases.size() == 0) { 6216 // If no operands then chain to entry token. 6217 return DAG.getEntryNode(); 6218 } else if (Aliases.size() == 1) { 6219 // If a single operand then chain to it. We don't need to revisit it. 6220 return Aliases[0]; 6221 } 6222 6223 // Construct a custom tailored token factor. 6224 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6225 &Aliases[0], Aliases.size()); 6226 6227 // Make sure the old chain gets cleaned up. 6228 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6229 6230 return NewChain; 6231} 6232 6233// SelectionDAG::Combine - This is the entry point for the file. 6234// 6235void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6236 CodeGenOpt::Level OptLevel) { 6237 /// run - This is the main entry point to this class. 6238 /// 6239 DAGCombiner(*this, AA, OptLevel).Run(Level); 6240} 6241