DAGCombiner.cpp revision 1160779f02d5369e4d9012ee1078798e866c6772
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32using namespace llvm; 33 34STATISTIC(NodesCombined , "Number of dag nodes combined"); 35STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 36STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 37 38namespace { 39#ifndef NDEBUG 40 static cl::opt<bool> 41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 42 cl::desc("Pop up a window to show dags before the first " 43 "dag combine pass")); 44 static cl::opt<bool> 45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 46 cl::desc("Pop up a window to show dags before the second " 47 "dag combine pass")); 48#else 49 static const bool ViewDAGCombine1 = false; 50 static const bool ViewDAGCombine2 = false; 51#endif 52 53 static cl::opt<bool> 54 CombinerAA("combiner-alias-analysis", cl::Hidden, 55 cl::desc("Turn on alias analysis during testing")); 56 57 static cl::opt<bool> 58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 59 cl::desc("Include global information in alias analysis")); 60 61//------------------------------ DAGCombiner ---------------------------------// 62 63 class VISIBILITY_HIDDEN DAGCombiner { 64 SelectionDAG &DAG; 65 TargetLowering &TLI; 66 bool AfterLegalize; 67 68 // Worklist of all of the nodes that need to be simplified. 69 std::vector<SDNode*> WorkList; 70 71 // AA - Used for DAG load/store alias analysis. 72 AliasAnalysis &AA; 73 74 /// AddUsersToWorkList - When an instruction is simplified, add all users of 75 /// the instruction to the work lists because they might get more simplified 76 /// now. 77 /// 78 void AddUsersToWorkList(SDNode *N) { 79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 80 UI != UE; ++UI) 81 AddToWorkList(*UI); 82 } 83 84 /// visit - call the node-specific routine that knows how to fold each 85 /// particular type of node. 86 SDOperand visit(SDNode *N); 87 88 public: 89 /// AddToWorkList - Add to the work list making sure it's instance is at the 90 /// the back (next to be processed.) 91 void AddToWorkList(SDNode *N) { 92 removeFromWorkList(N); 93 WorkList.push_back(N); 94 } 95 96 /// removeFromWorkList - remove all instances of N from the worklist. 97 /// 98 void removeFromWorkList(SDNode *N) { 99 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 100 WorkList.end()); 101 } 102 103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 104 bool AddTo = true); 105 106 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 107 return CombineTo(N, &Res, 1, AddTo); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 111 bool AddTo = true) { 112 SDOperand To[] = { Res0, Res1 }; 113 return CombineTo(N, To, 2, AddTo); 114 } 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDOperand Op) { 122 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 123 return SimplifyDemandedBits(Op, Demanded); 124 } 125 126 bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded); 127 128 bool CombineToPreIndexedLoadStore(SDNode *N); 129 bool CombineToPostIndexedLoadStore(SDNode *N); 130 131 132 /// combine - call the node-specific routine that knows how to fold each 133 /// particular type of node. If that doesn't do anything, try the 134 /// target-specific DAG combines. 135 SDOperand combine(SDNode *N); 136 137 // Visitation implementation - Implement dag node combining for different 138 // node types. The semantics are as follows: 139 // Return Value: 140 // SDOperand.Val == 0 - No change was made 141 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 142 // otherwise - N should be replaced by the returned Operand. 143 // 144 SDOperand visitTokenFactor(SDNode *N); 145 SDOperand visitMERGE_VALUES(SDNode *N); 146 SDOperand visitADD(SDNode *N); 147 SDOperand visitSUB(SDNode *N); 148 SDOperand visitADDC(SDNode *N); 149 SDOperand visitADDE(SDNode *N); 150 SDOperand visitMUL(SDNode *N); 151 SDOperand visitSDIV(SDNode *N); 152 SDOperand visitUDIV(SDNode *N); 153 SDOperand visitSREM(SDNode *N); 154 SDOperand visitUREM(SDNode *N); 155 SDOperand visitMULHU(SDNode *N); 156 SDOperand visitMULHS(SDNode *N); 157 SDOperand visitSMUL_LOHI(SDNode *N); 158 SDOperand visitUMUL_LOHI(SDNode *N); 159 SDOperand visitSDIVREM(SDNode *N); 160 SDOperand visitUDIVREM(SDNode *N); 161 SDOperand visitAND(SDNode *N); 162 SDOperand visitOR(SDNode *N); 163 SDOperand visitXOR(SDNode *N); 164 SDOperand SimplifyVBinOp(SDNode *N); 165 SDOperand visitSHL(SDNode *N); 166 SDOperand visitSRA(SDNode *N); 167 SDOperand visitSRL(SDNode *N); 168 SDOperand visitCTLZ(SDNode *N); 169 SDOperand visitCTTZ(SDNode *N); 170 SDOperand visitCTPOP(SDNode *N); 171 SDOperand visitSELECT(SDNode *N); 172 SDOperand visitSELECT_CC(SDNode *N); 173 SDOperand visitSETCC(SDNode *N); 174 SDOperand visitSIGN_EXTEND(SDNode *N); 175 SDOperand visitZERO_EXTEND(SDNode *N); 176 SDOperand visitANY_EXTEND(SDNode *N); 177 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 178 SDOperand visitTRUNCATE(SDNode *N); 179 SDOperand visitBIT_CONVERT(SDNode *N); 180 SDOperand visitFADD(SDNode *N); 181 SDOperand visitFSUB(SDNode *N); 182 SDOperand visitFMUL(SDNode *N); 183 SDOperand visitFDIV(SDNode *N); 184 SDOperand visitFREM(SDNode *N); 185 SDOperand visitFCOPYSIGN(SDNode *N); 186 SDOperand visitSINT_TO_FP(SDNode *N); 187 SDOperand visitUINT_TO_FP(SDNode *N); 188 SDOperand visitFP_TO_SINT(SDNode *N); 189 SDOperand visitFP_TO_UINT(SDNode *N); 190 SDOperand visitFP_ROUND(SDNode *N); 191 SDOperand visitFP_ROUND_INREG(SDNode *N); 192 SDOperand visitFP_EXTEND(SDNode *N); 193 SDOperand visitFNEG(SDNode *N); 194 SDOperand visitFABS(SDNode *N); 195 SDOperand visitBRCOND(SDNode *N); 196 SDOperand visitBR_CC(SDNode *N); 197 SDOperand visitLOAD(SDNode *N); 198 SDOperand visitSTORE(SDNode *N); 199 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 200 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 201 SDOperand visitBUILD_VECTOR(SDNode *N); 202 SDOperand visitCONCAT_VECTORS(SDNode *N); 203 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 204 205 SDOperand XformToShuffleWithZero(SDNode *N); 206 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 207 208 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 209 210 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 211 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 212 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 213 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 214 SDOperand N3, ISD::CondCode CC, 215 bool NotExtCompare = false); 216 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 217 ISD::CondCode Cond, bool foldBooleans = true); 218 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 219 unsigned HiOp); 220 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 221 SDOperand BuildSDIV(SDNode *N); 222 SDOperand BuildUDIV(SDNode *N); 223 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 224 SDOperand ReduceLoadWidth(SDNode *N); 225 226 SDOperand GetDemandedBits(SDOperand V, const APInt &Mask); 227 228 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 229 /// looking for aliasing nodes and adding them to the Aliases vector. 230 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 231 SmallVector<SDOperand, 8> &Aliases); 232 233 /// isAlias - Return true if there is any possibility that the two addresses 234 /// overlap. 235 bool isAlias(SDOperand Ptr1, int64_t Size1, 236 const Value *SrcValue1, int SrcValueOffset1, 237 SDOperand Ptr2, int64_t Size2, 238 const Value *SrcValue2, int SrcValueOffset2); 239 240 /// FindAliasInfo - Extracts the relevant alias information from the memory 241 /// node. Returns true if the operand was a load. 242 bool FindAliasInfo(SDNode *N, 243 SDOperand &Ptr, int64_t &Size, 244 const Value *&SrcValue, int &SrcValueOffset); 245 246 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 247 /// looking for a better chain (aliasing node.) 248 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 249 250public: 251 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 252 : DAG(D), 253 TLI(D.getTargetLoweringInfo()), 254 AfterLegalize(false), 255 AA(A) {} 256 257 /// Run - runs the dag combiner on all nodes in the work list 258 void Run(bool RunningAfterLegalize); 259 }; 260} 261 262 263namespace { 264/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 265/// nodes from the worklist. 266class VISIBILITY_HIDDEN WorkListRemover : 267 public SelectionDAG::DAGUpdateListener { 268 DAGCombiner &DC; 269public: 270 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 271 272 virtual void NodeDeleted(SDNode *N) { 273 DC.removeFromWorkList(N); 274 } 275 276 virtual void NodeUpdated(SDNode *N) { 277 // Ignore updates. 278 } 279}; 280} 281 282//===----------------------------------------------------------------------===// 283// TargetLowering::DAGCombinerInfo implementation 284//===----------------------------------------------------------------------===// 285 286void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 287 ((DAGCombiner*)DC)->AddToWorkList(N); 288} 289 290SDOperand TargetLowering::DAGCombinerInfo:: 291CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 292 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 293} 294 295SDOperand TargetLowering::DAGCombinerInfo:: 296CombineTo(SDNode *N, SDOperand Res) { 297 return ((DAGCombiner*)DC)->CombineTo(N, Res); 298} 299 300 301SDOperand TargetLowering::DAGCombinerInfo:: 302CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 303 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 304} 305 306 307//===----------------------------------------------------------------------===// 308// Helper Functions 309//===----------------------------------------------------------------------===// 310 311/// isNegatibleForFree - Return 1 if we can compute the negated form of the 312/// specified expression for the same cost as the expression itself, or 2 if we 313/// can compute the negated form more cheaply than the expression itself. 314static char isNegatibleForFree(SDOperand Op, bool AfterLegalize, 315 unsigned Depth = 0) { 316 // No compile time optimizations on this type. 317 if (Op.getValueType() == MVT::ppcf128) 318 return 0; 319 320 // fneg is removable even if it has multiple uses. 321 if (Op.getOpcode() == ISD::FNEG) return 2; 322 323 // Don't allow anything with multiple uses. 324 if (!Op.hasOneUse()) return 0; 325 326 // Don't recurse exponentially. 327 if (Depth > 6) return 0; 328 329 switch (Op.getOpcode()) { 330 default: return false; 331 case ISD::ConstantFP: 332 // Don't invert constant FP values after legalize. The negated constant 333 // isn't necessarily legal. 334 return AfterLegalize ? 0 : 1; 335 case ISD::FADD: 336 // FIXME: determine better conditions for this xform. 337 if (!UnsafeFPMath) return 0; 338 339 // -(A+B) -> -A - B 340 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 341 return V; 342 // -(A+B) -> -B - A 343 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 344 case ISD::FSUB: 345 // We can't turn -(A-B) into B-A when we honor signed zeros. 346 if (!UnsafeFPMath) return 0; 347 348 // -(A-B) -> B-A 349 return 1; 350 351 case ISD::FMUL: 352 case ISD::FDIV: 353 if (HonorSignDependentRoundingFPMath()) return 0; 354 355 // -(X*Y) -> (-X * Y) or (X*-Y) 356 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 357 return V; 358 359 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 360 361 case ISD::FP_EXTEND: 362 case ISD::FP_ROUND: 363 case ISD::FSIN: 364 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 365 } 366} 367 368/// GetNegatedExpression - If isNegatibleForFree returns true, this function 369/// returns the newly negated expression. 370static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 371 bool AfterLegalize, unsigned Depth = 0) { 372 // fneg is removable even if it has multiple uses. 373 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 374 375 // Don't allow anything with multiple uses. 376 assert(Op.hasOneUse() && "Unknown reuse!"); 377 378 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 379 switch (Op.getOpcode()) { 380 default: assert(0 && "Unknown code"); 381 case ISD::ConstantFP: { 382 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 383 V.changeSign(); 384 return DAG.getConstantFP(V, Op.getValueType()); 385 } 386 case ISD::FADD: 387 // FIXME: determine better conditions for this xform. 388 assert(UnsafeFPMath); 389 390 // -(A+B) -> -A - B 391 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 392 return DAG.getNode(ISD::FSUB, Op.getValueType(), 393 GetNegatedExpression(Op.getOperand(0), DAG, 394 AfterLegalize, Depth+1), 395 Op.getOperand(1)); 396 // -(A+B) -> -B - A 397 return DAG.getNode(ISD::FSUB, Op.getValueType(), 398 GetNegatedExpression(Op.getOperand(1), DAG, 399 AfterLegalize, Depth+1), 400 Op.getOperand(0)); 401 case ISD::FSUB: 402 // We can't turn -(A-B) into B-A when we honor signed zeros. 403 assert(UnsafeFPMath); 404 405 // -(0-B) -> B 406 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 407 if (N0CFP->getValueAPF().isZero()) 408 return Op.getOperand(1); 409 410 // -(A-B) -> B-A 411 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 412 Op.getOperand(0)); 413 414 case ISD::FMUL: 415 case ISD::FDIV: 416 assert(!HonorSignDependentRoundingFPMath()); 417 418 // -(X*Y) -> -X * Y 419 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 420 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 421 GetNegatedExpression(Op.getOperand(0), DAG, 422 AfterLegalize, Depth+1), 423 Op.getOperand(1)); 424 425 // -(X*Y) -> X * -Y 426 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 427 Op.getOperand(0), 428 GetNegatedExpression(Op.getOperand(1), DAG, 429 AfterLegalize, Depth+1)); 430 431 case ISD::FP_EXTEND: 432 case ISD::FSIN: 433 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 434 GetNegatedExpression(Op.getOperand(0), DAG, 435 AfterLegalize, Depth+1)); 436 case ISD::FP_ROUND: 437 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(0), DAG, 439 AfterLegalize, Depth+1), 440 Op.getOperand(1)); 441 } 442} 443 444 445// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 446// that selects between the values 1 and 0, making it equivalent to a setcc. 447// Also, set the incoming LHS, RHS, and CC references to the appropriate 448// nodes based on the type of node we are checking. This simplifies life a 449// bit for the callers. 450static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 451 SDOperand &CC) { 452 if (N.getOpcode() == ISD::SETCC) { 453 LHS = N.getOperand(0); 454 RHS = N.getOperand(1); 455 CC = N.getOperand(2); 456 return true; 457 } 458 if (N.getOpcode() == ISD::SELECT_CC && 459 N.getOperand(2).getOpcode() == ISD::Constant && 460 N.getOperand(3).getOpcode() == ISD::Constant && 461 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 462 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 463 LHS = N.getOperand(0); 464 RHS = N.getOperand(1); 465 CC = N.getOperand(4); 466 return true; 467 } 468 return false; 469} 470 471// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 472// one use. If this is true, it allows the users to invert the operation for 473// free when it is profitable to do so. 474static bool isOneUseSetCC(SDOperand N) { 475 SDOperand N0, N1, N2; 476 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 477 return true; 478 return false; 479} 480 481SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 482 MVT::ValueType VT = N0.getValueType(); 483 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 484 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 485 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 486 if (isa<ConstantSDNode>(N1)) { 487 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 488 AddToWorkList(OpNode.Val); 489 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 490 } else if (N0.hasOneUse()) { 491 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 492 AddToWorkList(OpNode.Val); 493 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 494 } 495 } 496 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 497 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 498 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 499 if (isa<ConstantSDNode>(N0)) { 500 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 501 AddToWorkList(OpNode.Val); 502 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 503 } else if (N1.hasOneUse()) { 504 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 505 AddToWorkList(OpNode.Val); 506 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 507 } 508 } 509 return SDOperand(); 510} 511 512SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 513 bool AddTo) { 514 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 515 ++NodesCombined; 516 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 517 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 518 DOUT << " and " << NumTo-1 << " other values\n"; 519 WorkListRemover DeadNodes(*this); 520 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 521 522 if (AddTo) { 523 // Push the new nodes and any users onto the worklist 524 for (unsigned i = 0, e = NumTo; i != e; ++i) { 525 AddToWorkList(To[i].Val); 526 AddUsersToWorkList(To[i].Val); 527 } 528 } 529 530 // Nodes can be reintroduced into the worklist. Make sure we do not 531 // process a node that has been replaced. 532 removeFromWorkList(N); 533 534 // Finally, since the node is now dead, remove it from the graph. 535 DAG.DeleteNode(N); 536 return SDOperand(N, 0); 537} 538 539/// SimplifyDemandedBits - Check the specified integer node value to see if 540/// it can be simplified or if things it uses can be simplified by bit 541/// propagation. If so, return true. 542bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) { 543 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 544 APInt KnownZero, KnownOne; 545 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 546 return false; 547 548 // Revisit the node. 549 AddToWorkList(Op.Val); 550 551 // Replace the old value with the new one. 552 ++NodesCombined; 553 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 554 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 555 DOUT << '\n'; 556 557 // Replace all uses. If any nodes become isomorphic to other nodes and 558 // are deleted, make sure to remove them from our worklist. 559 WorkListRemover DeadNodes(*this); 560 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 561 562 // Push the new node and any (possibly new) users onto the worklist. 563 AddToWorkList(TLO.New.Val); 564 AddUsersToWorkList(TLO.New.Val); 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (TLO.Old.Val->use_empty()) { 570 removeFromWorkList(TLO.Old.Val); 571 572 // If the operands of this node are only used by the node, they will now 573 // be dead. Make sure to visit them first to delete dead nodes early. 574 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 575 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 576 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 577 578 DAG.DeleteNode(TLO.Old.Val); 579 } 580 return true; 581} 582 583//===----------------------------------------------------------------------===// 584// Main DAG Combiner implementation 585//===----------------------------------------------------------------------===// 586 587void DAGCombiner::Run(bool RunningAfterLegalize) { 588 // set the instance variable, so that the various visit routines may use it. 589 AfterLegalize = RunningAfterLegalize; 590 591 // Add all the dag nodes to the worklist. 592 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 593 E = DAG.allnodes_end(); I != E; ++I) 594 WorkList.push_back(I); 595 596 // Create a dummy node (which is not added to allnodes), that adds a reference 597 // to the root node, preventing it from being deleted, and tracking any 598 // changes of the root. 599 HandleSDNode Dummy(DAG.getRoot()); 600 601 // The root of the dag may dangle to deleted nodes until the dag combiner is 602 // done. Set it to null to avoid confusion. 603 DAG.setRoot(SDOperand()); 604 605 // while the worklist isn't empty, inspect the node on the end of it and 606 // try and combine it. 607 while (!WorkList.empty()) { 608 SDNode *N = WorkList.back(); 609 WorkList.pop_back(); 610 611 // If N has no uses, it is dead. Make sure to revisit all N's operands once 612 // N is deleted from the DAG, since they too may now be dead or may have a 613 // reduced number of uses, allowing other xforms. 614 if (N->use_empty() && N != &Dummy) { 615 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 616 AddToWorkList(N->getOperand(i).Val); 617 618 DAG.DeleteNode(N); 619 continue; 620 } 621 622 SDOperand RV = combine(N); 623 624 if (RV.Val == 0) 625 continue; 626 627 ++NodesCombined; 628 629 // If we get back the same node we passed in, rather than a new node or 630 // zero, we know that the node must have defined multiple values and 631 // CombineTo was used. Since CombineTo takes care of the worklist 632 // mechanics for us, we have no work to do in this case. 633 if (RV.Val == N) 634 continue; 635 636 assert(N->getOpcode() != ISD::DELETED_NODE && 637 RV.Val->getOpcode() != ISD::DELETED_NODE && 638 "Node was deleted but visit returned new node!"); 639 640 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 641 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 642 DOUT << '\n'; 643 WorkListRemover DeadNodes(*this); 644 if (N->getNumValues() == RV.Val->getNumValues()) 645 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes); 646 else { 647 assert(N->getValueType(0) == RV.getValueType() && 648 N->getNumValues() == 1 && "Type mismatch"); 649 SDOperand OpV = RV; 650 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 651 } 652 653 // Push the new node and any users onto the worklist 654 AddToWorkList(RV.Val); 655 AddUsersToWorkList(RV.Val); 656 657 // Add any uses of the old node to the worklist in case this node is the 658 // last one that uses them. They may become dead after this node is 659 // deleted. 660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 661 AddToWorkList(N->getOperand(i).Val); 662 663 // Nodes can be reintroduced into the worklist. Make sure we do not 664 // process a node that has been replaced. 665 removeFromWorkList(N); 666 667 // Finally, since the node is now dead, remove it from the graph. 668 DAG.DeleteNode(N); 669 } 670 671 // If the root changed (e.g. it was a dead load, update the root). 672 DAG.setRoot(Dummy.getValue()); 673} 674 675SDOperand DAGCombiner::visit(SDNode *N) { 676 switch(N->getOpcode()) { 677 default: break; 678 case ISD::TokenFactor: return visitTokenFactor(N); 679 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 680 case ISD::ADD: return visitADD(N); 681 case ISD::SUB: return visitSUB(N); 682 case ISD::ADDC: return visitADDC(N); 683 case ISD::ADDE: return visitADDE(N); 684 case ISD::MUL: return visitMUL(N); 685 case ISD::SDIV: return visitSDIV(N); 686 case ISD::UDIV: return visitUDIV(N); 687 case ISD::SREM: return visitSREM(N); 688 case ISD::UREM: return visitUREM(N); 689 case ISD::MULHU: return visitMULHU(N); 690 case ISD::MULHS: return visitMULHS(N); 691 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 692 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 693 case ISD::SDIVREM: return visitSDIVREM(N); 694 case ISD::UDIVREM: return visitUDIVREM(N); 695 case ISD::AND: return visitAND(N); 696 case ISD::OR: return visitOR(N); 697 case ISD::XOR: return visitXOR(N); 698 case ISD::SHL: return visitSHL(N); 699 case ISD::SRA: return visitSRA(N); 700 case ISD::SRL: return visitSRL(N); 701 case ISD::CTLZ: return visitCTLZ(N); 702 case ISD::CTTZ: return visitCTTZ(N); 703 case ISD::CTPOP: return visitCTPOP(N); 704 case ISD::SELECT: return visitSELECT(N); 705 case ISD::SELECT_CC: return visitSELECT_CC(N); 706 case ISD::SETCC: return visitSETCC(N); 707 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 708 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 709 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 710 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 711 case ISD::TRUNCATE: return visitTRUNCATE(N); 712 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 713 case ISD::FADD: return visitFADD(N); 714 case ISD::FSUB: return visitFSUB(N); 715 case ISD::FMUL: return visitFMUL(N); 716 case ISD::FDIV: return visitFDIV(N); 717 case ISD::FREM: return visitFREM(N); 718 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 719 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 720 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 721 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 722 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 723 case ISD::FP_ROUND: return visitFP_ROUND(N); 724 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 725 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 726 case ISD::FNEG: return visitFNEG(N); 727 case ISD::FABS: return visitFABS(N); 728 case ISD::BRCOND: return visitBRCOND(N); 729 case ISD::BR_CC: return visitBR_CC(N); 730 case ISD::LOAD: return visitLOAD(N); 731 case ISD::STORE: return visitSTORE(N); 732 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 733 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 734 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 735 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 736 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 737 } 738 return SDOperand(); 739} 740 741SDOperand DAGCombiner::combine(SDNode *N) { 742 743 SDOperand RV = visit(N); 744 745 // If nothing happened, try a target-specific DAG combine. 746 if (RV.Val == 0) { 747 assert(N->getOpcode() != ISD::DELETED_NODE && 748 "Node was deleted but visit returned NULL!"); 749 750 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 751 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 752 753 // Expose the DAG combiner to the target combiner impls. 754 TargetLowering::DAGCombinerInfo 755 DagCombineInfo(DAG, !AfterLegalize, false, this); 756 757 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 758 } 759 } 760 761 return RV; 762} 763 764/// getInputChainForNode - Given a node, return its input chain if it has one, 765/// otherwise return a null sd operand. 766static SDOperand getInputChainForNode(SDNode *N) { 767 if (unsigned NumOps = N->getNumOperands()) { 768 if (N->getOperand(0).getValueType() == MVT::Other) 769 return N->getOperand(0); 770 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 771 return N->getOperand(NumOps-1); 772 for (unsigned i = 1; i < NumOps-1; ++i) 773 if (N->getOperand(i).getValueType() == MVT::Other) 774 return N->getOperand(i); 775 } 776 return SDOperand(0, 0); 777} 778 779SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 780 // If N has two operands, where one has an input chain equal to the other, 781 // the 'other' chain is redundant. 782 if (N->getNumOperands() == 2) { 783 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 784 return N->getOperand(0); 785 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 786 return N->getOperand(1); 787 } 788 789 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 790 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 791 SmallPtrSet<SDNode*, 16> SeenOps; 792 bool Changed = false; // If we should replace this token factor. 793 794 // Start out with this token factor. 795 TFs.push_back(N); 796 797 // Iterate through token factors. The TFs grows when new token factors are 798 // encountered. 799 for (unsigned i = 0; i < TFs.size(); ++i) { 800 SDNode *TF = TFs[i]; 801 802 // Check each of the operands. 803 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 804 SDOperand Op = TF->getOperand(i); 805 806 switch (Op.getOpcode()) { 807 case ISD::EntryToken: 808 // Entry tokens don't need to be added to the list. They are 809 // rededundant. 810 Changed = true; 811 break; 812 813 case ISD::TokenFactor: 814 if ((CombinerAA || Op.hasOneUse()) && 815 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 816 // Queue up for processing. 817 TFs.push_back(Op.Val); 818 // Clean up in case the token factor is removed. 819 AddToWorkList(Op.Val); 820 Changed = true; 821 break; 822 } 823 // Fall thru 824 825 default: 826 // Only add if it isn't already in the list. 827 if (SeenOps.insert(Op.Val)) 828 Ops.push_back(Op); 829 else 830 Changed = true; 831 break; 832 } 833 } 834 } 835 836 SDOperand Result; 837 838 // If we've change things around then replace token factor. 839 if (Changed) { 840 if (Ops.empty()) { 841 // The entry token is the only possible outcome. 842 Result = DAG.getEntryNode(); 843 } else { 844 // New and improved token factor. 845 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 846 } 847 848 // Don't add users to work list. 849 return CombineTo(N, Result, false); 850 } 851 852 return Result; 853} 854 855/// MERGE_VALUES can always be eliminated. 856SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) { 857 WorkListRemover DeadNodes(*this); 858 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 859 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i), 860 &DeadNodes); 861 removeFromWorkList(N); 862 DAG.DeleteNode(N); 863 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 864} 865 866 867static 868SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 869 MVT::ValueType VT = N0.getValueType(); 870 SDOperand N00 = N0.getOperand(0); 871 SDOperand N01 = N0.getOperand(1); 872 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 873 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 874 isa<ConstantSDNode>(N00.getOperand(1))) { 875 N0 = DAG.getNode(ISD::ADD, VT, 876 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 877 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 878 return DAG.getNode(ISD::ADD, VT, N0, N1); 879 } 880 return SDOperand(); 881} 882 883static 884SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 885 SelectionDAG &DAG) { 886 MVT::ValueType VT = N->getValueType(0); 887 unsigned Opc = N->getOpcode(); 888 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 889 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 890 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 891 ISD::CondCode CC = ISD::SETCC_INVALID; 892 if (isSlctCC) 893 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 894 else { 895 SDOperand CCOp = Slct.getOperand(0); 896 if (CCOp.getOpcode() == ISD::SETCC) 897 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 898 } 899 900 bool DoXform = false; 901 bool InvCC = false; 902 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 903 "Bad input!"); 904 if (LHS.getOpcode() == ISD::Constant && 905 cast<ConstantSDNode>(LHS)->isNullValue()) 906 DoXform = true; 907 else if (CC != ISD::SETCC_INVALID && 908 RHS.getOpcode() == ISD::Constant && 909 cast<ConstantSDNode>(RHS)->isNullValue()) { 910 std::swap(LHS, RHS); 911 SDOperand Op0 = Slct.getOperand(0); 912 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() 913 : Op0.getOperand(0).getValueType()); 914 CC = ISD::getSetCCInverse(CC, isInt); 915 DoXform = true; 916 InvCC = true; 917 } 918 919 if (DoXform) { 920 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 921 if (isSlctCC) 922 return DAG.getSelectCC(OtherOp, Result, 923 Slct.getOperand(0), Slct.getOperand(1), CC); 924 SDOperand CCOp = Slct.getOperand(0); 925 if (InvCC) 926 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 927 CCOp.getOperand(1), CC); 928 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 929 } 930 return SDOperand(); 931} 932 933SDOperand DAGCombiner::visitADD(SDNode *N) { 934 SDOperand N0 = N->getOperand(0); 935 SDOperand N1 = N->getOperand(1); 936 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 937 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 938 MVT::ValueType VT = N0.getValueType(); 939 940 // fold vector ops 941 if (MVT::isVector(VT)) { 942 SDOperand FoldedVOp = SimplifyVBinOp(N); 943 if (FoldedVOp.Val) return FoldedVOp; 944 } 945 946 // fold (add x, undef) -> undef 947 if (N0.getOpcode() == ISD::UNDEF) 948 return N0; 949 if (N1.getOpcode() == ISD::UNDEF) 950 return N1; 951 // fold (add c1, c2) -> c1+c2 952 if (N0C && N1C) 953 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); 954 // canonicalize constant to RHS 955 if (N0C && !N1C) 956 return DAG.getNode(ISD::ADD, VT, N1, N0); 957 // fold (add x, 0) -> x 958 if (N1C && N1C->isNullValue()) 959 return N0; 960 // fold ((c1-A)+c2) -> (c1+c2)-A 961 if (N1C && N0.getOpcode() == ISD::SUB) 962 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 963 return DAG.getNode(ISD::SUB, VT, 964 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 965 N0.getOperand(1)); 966 // reassociate add 967 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 968 if (RADD.Val != 0) 969 return RADD; 970 // fold ((0-A) + B) -> B-A 971 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 972 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 973 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 974 // fold (A + (0-B)) -> A-B 975 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 976 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 977 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 978 // fold (A+(B-A)) -> B 979 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 980 return N1.getOperand(0); 981 982 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 983 return SDOperand(N, 0); 984 985 // fold (a+b) -> (a|b) iff a and b share no bits. 986 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 987 APInt LHSZero, LHSOne; 988 APInt RHSZero, RHSOne; 989 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 990 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 991 if (LHSZero.getBoolValue()) { 992 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 993 994 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 995 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 996 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 997 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 998 return DAG.getNode(ISD::OR, VT, N0, N1); 999 } 1000 } 1001 1002 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1003 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 1004 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 1005 if (Result.Val) return Result; 1006 } 1007 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 1008 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 1009 if (Result.Val) return Result; 1010 } 1011 1012 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1013 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 1014 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 1015 if (Result.Val) return Result; 1016 } 1017 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1018 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1019 if (Result.Val) return Result; 1020 } 1021 1022 return SDOperand(); 1023} 1024 1025SDOperand DAGCombiner::visitADDC(SDNode *N) { 1026 SDOperand N0 = N->getOperand(0); 1027 SDOperand N1 = N->getOperand(1); 1028 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1029 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1030 MVT::ValueType VT = N0.getValueType(); 1031 1032 // If the flag result is dead, turn this into an ADD. 1033 if (N->hasNUsesOfValue(0, 1)) 1034 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1035 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1036 1037 // canonicalize constant to RHS. 1038 if (N0C && !N1C) { 1039 SDOperand Ops[] = { N1, N0 }; 1040 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1041 } 1042 1043 // fold (addc x, 0) -> x + no carry out 1044 if (N1C && N1C->isNullValue()) 1045 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1046 1047 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1048 APInt LHSZero, LHSOne; 1049 APInt RHSZero, RHSOne; 1050 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 1051 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1052 if (LHSZero.getBoolValue()) { 1053 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1054 1055 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1056 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1057 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1058 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1059 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1060 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1061 } 1062 1063 return SDOperand(); 1064} 1065 1066SDOperand DAGCombiner::visitADDE(SDNode *N) { 1067 SDOperand N0 = N->getOperand(0); 1068 SDOperand N1 = N->getOperand(1); 1069 SDOperand CarryIn = N->getOperand(2); 1070 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1071 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1072 //MVT::ValueType VT = N0.getValueType(); 1073 1074 // canonicalize constant to RHS 1075 if (N0C && !N1C) { 1076 SDOperand Ops[] = { N1, N0, CarryIn }; 1077 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1078 } 1079 1080 // fold (adde x, y, false) -> (addc x, y) 1081 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1082 SDOperand Ops[] = { N1, N0 }; 1083 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1084 } 1085 1086 return SDOperand(); 1087} 1088 1089 1090 1091SDOperand DAGCombiner::visitSUB(SDNode *N) { 1092 SDOperand N0 = N->getOperand(0); 1093 SDOperand N1 = N->getOperand(1); 1094 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1095 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1096 MVT::ValueType VT = N0.getValueType(); 1097 1098 // fold vector ops 1099 if (MVT::isVector(VT)) { 1100 SDOperand FoldedVOp = SimplifyVBinOp(N); 1101 if (FoldedVOp.Val) return FoldedVOp; 1102 } 1103 1104 // fold (sub x, x) -> 0 1105 if (N0 == N1) 1106 return DAG.getConstant(0, N->getValueType(0)); 1107 // fold (sub c1, c2) -> c1-c2 1108 if (N0C && N1C) 1109 return DAG.getNode(ISD::SUB, VT, N0, N1); 1110 // fold (sub x, c) -> (add x, -c) 1111 if (N1C) 1112 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1113 // fold (A+B)-A -> B 1114 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1115 return N0.getOperand(1); 1116 // fold (A+B)-B -> A 1117 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1118 return N0.getOperand(0); 1119 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1120 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1121 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1122 if (Result.Val) return Result; 1123 } 1124 // If either operand of a sub is undef, the result is undef 1125 if (N0.getOpcode() == ISD::UNDEF) 1126 return N0; 1127 if (N1.getOpcode() == ISD::UNDEF) 1128 return N1; 1129 1130 return SDOperand(); 1131} 1132 1133SDOperand DAGCombiner::visitMUL(SDNode *N) { 1134 SDOperand N0 = N->getOperand(0); 1135 SDOperand N1 = N->getOperand(1); 1136 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1137 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1138 MVT::ValueType VT = N0.getValueType(); 1139 1140 // fold vector ops 1141 if (MVT::isVector(VT)) { 1142 SDOperand FoldedVOp = SimplifyVBinOp(N); 1143 if (FoldedVOp.Val) return FoldedVOp; 1144 } 1145 1146 // fold (mul x, undef) -> 0 1147 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1148 return DAG.getConstant(0, VT); 1149 // fold (mul c1, c2) -> c1*c2 1150 if (N0C && N1C) 1151 return DAG.getNode(ISD::MUL, VT, N0, N1); 1152 // canonicalize constant to RHS 1153 if (N0C && !N1C) 1154 return DAG.getNode(ISD::MUL, VT, N1, N0); 1155 // fold (mul x, 0) -> 0 1156 if (N1C && N1C->isNullValue()) 1157 return N1; 1158 // fold (mul x, -1) -> 0-x 1159 if (N1C && N1C->isAllOnesValue()) 1160 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1161 // fold (mul x, (1 << c)) -> x << c 1162 if (N1C && isPowerOf2_64(N1C->getValue())) 1163 return DAG.getNode(ISD::SHL, VT, N0, 1164 DAG.getConstant(Log2_64(N1C->getValue()), 1165 TLI.getShiftAmountTy())); 1166 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1167 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1168 // FIXME: If the input is something that is easily negated (e.g. a 1169 // single-use add), we should put the negate there. 1170 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1171 DAG.getNode(ISD::SHL, VT, N0, 1172 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1173 TLI.getShiftAmountTy()))); 1174 } 1175 1176 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1177 if (N1C && N0.getOpcode() == ISD::SHL && 1178 isa<ConstantSDNode>(N0.getOperand(1))) { 1179 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1180 AddToWorkList(C3.Val); 1181 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1182 } 1183 1184 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1185 // use. 1186 { 1187 SDOperand Sh(0,0), Y(0,0); 1188 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1189 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1190 N0.Val->hasOneUse()) { 1191 Sh = N0; Y = N1; 1192 } else if (N1.getOpcode() == ISD::SHL && 1193 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1194 Sh = N1; Y = N0; 1195 } 1196 if (Sh.Val) { 1197 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1198 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1199 } 1200 } 1201 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1202 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1203 isa<ConstantSDNode>(N0.getOperand(1))) { 1204 return DAG.getNode(ISD::ADD, VT, 1205 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1206 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1207 } 1208 1209 // reassociate mul 1210 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1211 if (RMUL.Val != 0) 1212 return RMUL; 1213 1214 return SDOperand(); 1215} 1216 1217SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1218 SDOperand N0 = N->getOperand(0); 1219 SDOperand N1 = N->getOperand(1); 1220 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1221 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1222 MVT::ValueType VT = N->getValueType(0); 1223 1224 // fold vector ops 1225 if (MVT::isVector(VT)) { 1226 SDOperand FoldedVOp = SimplifyVBinOp(N); 1227 if (FoldedVOp.Val) return FoldedVOp; 1228 } 1229 1230 // fold (sdiv c1, c2) -> c1/c2 1231 if (N0C && N1C && !N1C->isNullValue()) 1232 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1233 // fold (sdiv X, 1) -> X 1234 if (N1C && N1C->getSignExtended() == 1LL) 1235 return N0; 1236 // fold (sdiv X, -1) -> 0-X 1237 if (N1C && N1C->isAllOnesValue()) 1238 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1239 // If we know the sign bits of both operands are zero, strength reduce to a 1240 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1241 if (!MVT::isVector(VT)) { 1242 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1243 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1244 } 1245 // fold (sdiv X, pow2) -> simple ops after legalize 1246 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1247 (isPowerOf2_64(N1C->getSignExtended()) || 1248 isPowerOf2_64(-N1C->getSignExtended()))) { 1249 // If dividing by powers of two is cheap, then don't perform the following 1250 // fold. 1251 if (TLI.isPow2DivCheap()) 1252 return SDOperand(); 1253 int64_t pow2 = N1C->getSignExtended(); 1254 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1255 unsigned lg2 = Log2_64(abs2); 1256 // Splat the sign bit into the register 1257 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1258 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1259 TLI.getShiftAmountTy())); 1260 AddToWorkList(SGN.Val); 1261 // Add (N0 < 0) ? abs2 - 1 : 0; 1262 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1263 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1264 TLI.getShiftAmountTy())); 1265 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1266 AddToWorkList(SRL.Val); 1267 AddToWorkList(ADD.Val); // Divide by pow2 1268 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1269 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1270 // If we're dividing by a positive value, we're done. Otherwise, we must 1271 // negate the result. 1272 if (pow2 > 0) 1273 return SRA; 1274 AddToWorkList(SRA.Val); 1275 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1276 } 1277 // if integer divide is expensive and we satisfy the requirements, emit an 1278 // alternate sequence. 1279 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1280 !TLI.isIntDivCheap()) { 1281 SDOperand Op = BuildSDIV(N); 1282 if (Op.Val) return Op; 1283 } 1284 1285 // undef / X -> 0 1286 if (N0.getOpcode() == ISD::UNDEF) 1287 return DAG.getConstant(0, VT); 1288 // X / undef -> undef 1289 if (N1.getOpcode() == ISD::UNDEF) 1290 return N1; 1291 1292 return SDOperand(); 1293} 1294 1295SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1296 SDOperand N0 = N->getOperand(0); 1297 SDOperand N1 = N->getOperand(1); 1298 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1299 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1300 MVT::ValueType VT = N->getValueType(0); 1301 1302 // fold vector ops 1303 if (MVT::isVector(VT)) { 1304 SDOperand FoldedVOp = SimplifyVBinOp(N); 1305 if (FoldedVOp.Val) return FoldedVOp; 1306 } 1307 1308 // fold (udiv c1, c2) -> c1/c2 1309 if (N0C && N1C && !N1C->isNullValue()) 1310 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1311 // fold (udiv x, (1 << c)) -> x >>u c 1312 if (N1C && isPowerOf2_64(N1C->getValue())) 1313 return DAG.getNode(ISD::SRL, VT, N0, 1314 DAG.getConstant(Log2_64(N1C->getValue()), 1315 TLI.getShiftAmountTy())); 1316 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1317 if (N1.getOpcode() == ISD::SHL) { 1318 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1319 if (isPowerOf2_64(SHC->getValue())) { 1320 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1321 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1322 DAG.getConstant(Log2_64(SHC->getValue()), 1323 ADDVT)); 1324 AddToWorkList(Add.Val); 1325 return DAG.getNode(ISD::SRL, VT, N0, Add); 1326 } 1327 } 1328 } 1329 // fold (udiv x, c) -> alternate 1330 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1331 SDOperand Op = BuildUDIV(N); 1332 if (Op.Val) return Op; 1333 } 1334 1335 // undef / X -> 0 1336 if (N0.getOpcode() == ISD::UNDEF) 1337 return DAG.getConstant(0, VT); 1338 // X / undef -> undef 1339 if (N1.getOpcode() == ISD::UNDEF) 1340 return N1; 1341 1342 return SDOperand(); 1343} 1344 1345SDOperand DAGCombiner::visitSREM(SDNode *N) { 1346 SDOperand N0 = N->getOperand(0); 1347 SDOperand N1 = N->getOperand(1); 1348 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1349 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1350 MVT::ValueType VT = N->getValueType(0); 1351 1352 // fold (srem c1, c2) -> c1%c2 1353 if (N0C && N1C && !N1C->isNullValue()) 1354 return DAG.getNode(ISD::SREM, VT, N0, N1); 1355 // If we know the sign bits of both operands are zero, strength reduce to a 1356 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1357 if (!MVT::isVector(VT)) { 1358 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1359 return DAG.getNode(ISD::UREM, VT, N0, N1); 1360 } 1361 1362 // If X/C can be simplified by the division-by-constant logic, lower 1363 // X%C to the equivalent of X-X/C*C. 1364 if (N1C && !N1C->isNullValue()) { 1365 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1366 AddToWorkList(Div.Val); 1367 SDOperand OptimizedDiv = combine(Div.Val); 1368 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1369 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1370 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1371 AddToWorkList(Mul.Val); 1372 return Sub; 1373 } 1374 } 1375 1376 // undef % X -> 0 1377 if (N0.getOpcode() == ISD::UNDEF) 1378 return DAG.getConstant(0, VT); 1379 // X % undef -> undef 1380 if (N1.getOpcode() == ISD::UNDEF) 1381 return N1; 1382 1383 return SDOperand(); 1384} 1385 1386SDOperand DAGCombiner::visitUREM(SDNode *N) { 1387 SDOperand N0 = N->getOperand(0); 1388 SDOperand N1 = N->getOperand(1); 1389 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1390 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1391 MVT::ValueType VT = N->getValueType(0); 1392 1393 // fold (urem c1, c2) -> c1%c2 1394 if (N0C && N1C && !N1C->isNullValue()) 1395 return DAG.getNode(ISD::UREM, VT, N0, N1); 1396 // fold (urem x, pow2) -> (and x, pow2-1) 1397 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1398 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1399 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1400 if (N1.getOpcode() == ISD::SHL) { 1401 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1402 if (isPowerOf2_64(SHC->getValue())) { 1403 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1404 AddToWorkList(Add.Val); 1405 return DAG.getNode(ISD::AND, VT, N0, Add); 1406 } 1407 } 1408 } 1409 1410 // If X/C can be simplified by the division-by-constant logic, lower 1411 // X%C to the equivalent of X-X/C*C. 1412 if (N1C && !N1C->isNullValue()) { 1413 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1414 SDOperand OptimizedDiv = combine(Div.Val); 1415 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1416 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1417 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1418 AddToWorkList(Mul.Val); 1419 return Sub; 1420 } 1421 } 1422 1423 // undef % X -> 0 1424 if (N0.getOpcode() == ISD::UNDEF) 1425 return DAG.getConstant(0, VT); 1426 // X % undef -> undef 1427 if (N1.getOpcode() == ISD::UNDEF) 1428 return N1; 1429 1430 return SDOperand(); 1431} 1432 1433SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1434 SDOperand N0 = N->getOperand(0); 1435 SDOperand N1 = N->getOperand(1); 1436 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1437 MVT::ValueType VT = N->getValueType(0); 1438 1439 // fold (mulhs x, 0) -> 0 1440 if (N1C && N1C->isNullValue()) 1441 return N1; 1442 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1443 if (N1C && N1C->getValue() == 1) 1444 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1445 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1446 TLI.getShiftAmountTy())); 1447 // fold (mulhs x, undef) -> 0 1448 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1449 return DAG.getConstant(0, VT); 1450 1451 return SDOperand(); 1452} 1453 1454SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1455 SDOperand N0 = N->getOperand(0); 1456 SDOperand N1 = N->getOperand(1); 1457 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1458 MVT::ValueType VT = N->getValueType(0); 1459 1460 // fold (mulhu x, 0) -> 0 1461 if (N1C && N1C->isNullValue()) 1462 return N1; 1463 // fold (mulhu x, 1) -> 0 1464 if (N1C && N1C->getValue() == 1) 1465 return DAG.getConstant(0, N0.getValueType()); 1466 // fold (mulhu x, undef) -> 0 1467 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1468 return DAG.getConstant(0, VT); 1469 1470 return SDOperand(); 1471} 1472 1473/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1474/// compute two values. LoOp and HiOp give the opcodes for the two computations 1475/// that are being performed. Return true if a simplification was made. 1476/// 1477SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1478 unsigned HiOp) { 1479 // If the high half is not needed, just compute the low half. 1480 bool HiExists = N->hasAnyUseOfValue(1); 1481 if (!HiExists && 1482 (!AfterLegalize || 1483 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1484 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1485 N->getNumOperands()); 1486 return CombineTo(N, Res, Res); 1487 } 1488 1489 // If the low half is not needed, just compute the high half. 1490 bool LoExists = N->hasAnyUseOfValue(0); 1491 if (!LoExists && 1492 (!AfterLegalize || 1493 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1494 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1495 N->getNumOperands()); 1496 return CombineTo(N, Res, Res); 1497 } 1498 1499 // If both halves are used, return as it is. 1500 if (LoExists && HiExists) 1501 return SDOperand(); 1502 1503 // If the two computed results can be simplified separately, separate them. 1504 if (LoExists) { 1505 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1506 N->op_begin(), N->getNumOperands()); 1507 AddToWorkList(Lo.Val); 1508 SDOperand LoOpt = combine(Lo.Val); 1509 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1510 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) 1511 return CombineTo(N, LoOpt, LoOpt); 1512 } 1513 1514 if (HiExists) { 1515 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1516 N->op_begin(), N->getNumOperands()); 1517 AddToWorkList(Hi.Val); 1518 SDOperand HiOpt = combine(Hi.Val); 1519 if (HiOpt.Val && HiOpt != Hi && 1520 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) 1521 return CombineTo(N, HiOpt, HiOpt); 1522 } 1523 return SDOperand(); 1524} 1525 1526SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1527 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1528 if (Res.Val) return Res; 1529 1530 return SDOperand(); 1531} 1532 1533SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1534 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1535 if (Res.Val) return Res; 1536 1537 return SDOperand(); 1538} 1539 1540SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1541 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1542 if (Res.Val) return Res; 1543 1544 return SDOperand(); 1545} 1546 1547SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1548 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1549 if (Res.Val) return Res; 1550 1551 return SDOperand(); 1552} 1553 1554/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1555/// two operands of the same opcode, try to simplify it. 1556SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1557 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1558 MVT::ValueType VT = N0.getValueType(); 1559 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1560 1561 // For each of OP in AND/OR/XOR: 1562 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1563 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1564 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1565 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1566 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1567 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1568 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1569 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1570 N0.getOperand(0).getValueType(), 1571 N0.getOperand(0), N1.getOperand(0)); 1572 AddToWorkList(ORNode.Val); 1573 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1574 } 1575 1576 // For each of OP in SHL/SRL/SRA/AND... 1577 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1578 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1579 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1580 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1581 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1582 N0.getOperand(1) == N1.getOperand(1)) { 1583 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1584 N0.getOperand(0).getValueType(), 1585 N0.getOperand(0), N1.getOperand(0)); 1586 AddToWorkList(ORNode.Val); 1587 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1588 } 1589 1590 return SDOperand(); 1591} 1592 1593SDOperand DAGCombiner::visitAND(SDNode *N) { 1594 SDOperand N0 = N->getOperand(0); 1595 SDOperand N1 = N->getOperand(1); 1596 SDOperand LL, LR, RL, RR, CC0, CC1; 1597 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1598 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1599 MVT::ValueType VT = N1.getValueType(); 1600 unsigned BitWidth = MVT::getSizeInBits(VT); 1601 1602 // fold vector ops 1603 if (MVT::isVector(VT)) { 1604 SDOperand FoldedVOp = SimplifyVBinOp(N); 1605 if (FoldedVOp.Val) return FoldedVOp; 1606 } 1607 1608 // fold (and x, undef) -> 0 1609 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1610 return DAG.getConstant(0, VT); 1611 // fold (and c1, c2) -> c1&c2 1612 if (N0C && N1C) 1613 return DAG.getNode(ISD::AND, VT, N0, N1); 1614 // canonicalize constant to RHS 1615 if (N0C && !N1C) 1616 return DAG.getNode(ISD::AND, VT, N1, N0); 1617 // fold (and x, -1) -> x 1618 if (N1C && N1C->isAllOnesValue()) 1619 return N0; 1620 // if (and x, c) is known to be zero, return 0 1621 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 1622 APInt::getAllOnesValue(BitWidth))) 1623 return DAG.getConstant(0, VT); 1624 // reassociate and 1625 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1626 if (RAND.Val != 0) 1627 return RAND; 1628 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1629 if (N1C && N0.getOpcode() == ISD::OR) 1630 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1631 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1632 return N1; 1633 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1634 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1635 SDOperand N0Op0 = N0.getOperand(0); 1636 APInt Mask = ~N1C->getAPIntValue(); 1637 Mask.trunc(N0Op0.getValueSizeInBits()); 1638 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1639 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1640 N0Op0); 1641 1642 // Replace uses of the AND with uses of the Zero extend node. 1643 CombineTo(N, Zext); 1644 1645 // We actually want to replace all uses of the any_extend with the 1646 // zero_extend, to avoid duplicating things. This will later cause this 1647 // AND to be folded. 1648 CombineTo(N0.Val, Zext); 1649 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1650 } 1651 } 1652 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1653 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1654 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1655 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1656 1657 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1658 MVT::isInteger(LL.getValueType())) { 1659 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1660 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1661 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1662 AddToWorkList(ORNode.Val); 1663 return DAG.getSetCC(VT, ORNode, LR, Op1); 1664 } 1665 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1666 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1667 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1668 AddToWorkList(ANDNode.Val); 1669 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1670 } 1671 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1672 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1673 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1674 AddToWorkList(ORNode.Val); 1675 return DAG.getSetCC(VT, ORNode, LR, Op1); 1676 } 1677 } 1678 // canonicalize equivalent to ll == rl 1679 if (LL == RR && LR == RL) { 1680 Op1 = ISD::getSetCCSwappedOperands(Op1); 1681 std::swap(RL, RR); 1682 } 1683 if (LL == RL && LR == RR) { 1684 bool isInteger = MVT::isInteger(LL.getValueType()); 1685 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1686 if (Result != ISD::SETCC_INVALID) 1687 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1688 } 1689 } 1690 1691 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1692 if (N0.getOpcode() == N1.getOpcode()) { 1693 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1694 if (Tmp.Val) return Tmp; 1695 } 1696 1697 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1698 // fold (and (sra)) -> (and (srl)) when possible. 1699 if (!MVT::isVector(VT) && 1700 SimplifyDemandedBits(SDOperand(N, 0))) 1701 return SDOperand(N, 0); 1702 // fold (zext_inreg (extload x)) -> (zextload x) 1703 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1704 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1705 MVT::ValueType EVT = LN0->getMemoryVT(); 1706 // If we zero all the possible extended bits, then we can turn this into 1707 // a zextload if we are running before legalize or the operation is legal. 1708 unsigned BitWidth = N1.getValueSizeInBits(); 1709 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1710 BitWidth - MVT::getSizeInBits(EVT))) && 1711 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1712 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1713 LN0->getBasePtr(), LN0->getSrcValue(), 1714 LN0->getSrcValueOffset(), EVT, 1715 LN0->isVolatile(), 1716 LN0->getAlignment()); 1717 AddToWorkList(N); 1718 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1719 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1720 } 1721 } 1722 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1723 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1724 N0.hasOneUse()) { 1725 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1726 MVT::ValueType EVT = LN0->getMemoryVT(); 1727 // If we zero all the possible extended bits, then we can turn this into 1728 // a zextload if we are running before legalize or the operation is legal. 1729 unsigned BitWidth = N1.getValueSizeInBits(); 1730 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1731 BitWidth - MVT::getSizeInBits(EVT))) && 1732 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1733 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1734 LN0->getBasePtr(), LN0->getSrcValue(), 1735 LN0->getSrcValueOffset(), EVT, 1736 LN0->isVolatile(), 1737 LN0->getAlignment()); 1738 AddToWorkList(N); 1739 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1740 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1741 } 1742 } 1743 1744 // fold (and (load x), 255) -> (zextload x, i8) 1745 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1746 if (N1C && N0.getOpcode() == ISD::LOAD) { 1747 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1748 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1749 LN0->isUnindexed() && N0.hasOneUse()) { 1750 MVT::ValueType EVT, LoadedVT; 1751 if (N1C->getValue() == 255) 1752 EVT = MVT::i8; 1753 else if (N1C->getValue() == 65535) 1754 EVT = MVT::i16; 1755 else if (N1C->getValue() == ~0U) 1756 EVT = MVT::i32; 1757 else 1758 EVT = MVT::Other; 1759 1760 LoadedVT = LN0->getMemoryVT(); 1761 if (EVT != MVT::Other && LoadedVT > EVT && 1762 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1763 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1764 // For big endian targets, we need to add an offset to the pointer to 1765 // load the correct bytes. For little endian systems, we merely need to 1766 // read fewer bytes from the same pointer. 1767 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1768 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1769 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1770 unsigned Alignment = LN0->getAlignment(); 1771 SDOperand NewPtr = LN0->getBasePtr(); 1772 if (TLI.isBigEndian()) { 1773 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1774 DAG.getConstant(PtrOff, PtrType)); 1775 Alignment = MinAlign(Alignment, PtrOff); 1776 } 1777 AddToWorkList(NewPtr.Val); 1778 SDOperand Load = 1779 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1780 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1781 LN0->isVolatile(), Alignment); 1782 AddToWorkList(N); 1783 CombineTo(N0.Val, Load, Load.getValue(1)); 1784 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1785 } 1786 } 1787 } 1788 1789 return SDOperand(); 1790} 1791 1792SDOperand DAGCombiner::visitOR(SDNode *N) { 1793 SDOperand N0 = N->getOperand(0); 1794 SDOperand N1 = N->getOperand(1); 1795 SDOperand LL, LR, RL, RR, CC0, CC1; 1796 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1797 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1798 MVT::ValueType VT = N1.getValueType(); 1799 1800 // fold vector ops 1801 if (MVT::isVector(VT)) { 1802 SDOperand FoldedVOp = SimplifyVBinOp(N); 1803 if (FoldedVOp.Val) return FoldedVOp; 1804 } 1805 1806 // fold (or x, undef) -> -1 1807 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1808 return DAG.getConstant(~0ULL, VT); 1809 // fold (or c1, c2) -> c1|c2 1810 if (N0C && N1C) 1811 return DAG.getNode(ISD::OR, VT, N0, N1); 1812 // canonicalize constant to RHS 1813 if (N0C && !N1C) 1814 return DAG.getNode(ISD::OR, VT, N1, N0); 1815 // fold (or x, 0) -> x 1816 if (N1C && N1C->isNullValue()) 1817 return N0; 1818 // fold (or x, -1) -> -1 1819 if (N1C && N1C->isAllOnesValue()) 1820 return N1; 1821 // fold (or x, c) -> c iff (x & ~c) == 0 1822 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1823 return N1; 1824 // reassociate or 1825 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1826 if (ROR.Val != 0) 1827 return ROR; 1828 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1829 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1830 isa<ConstantSDNode>(N0.getOperand(1))) { 1831 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1832 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1833 N1), 1834 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1835 } 1836 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1837 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1838 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1839 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1840 1841 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1842 MVT::isInteger(LL.getValueType())) { 1843 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1844 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1845 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1846 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1847 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1848 AddToWorkList(ORNode.Val); 1849 return DAG.getSetCC(VT, ORNode, LR, Op1); 1850 } 1851 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1852 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1853 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1854 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1855 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1856 AddToWorkList(ANDNode.Val); 1857 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1858 } 1859 } 1860 // canonicalize equivalent to ll == rl 1861 if (LL == RR && LR == RL) { 1862 Op1 = ISD::getSetCCSwappedOperands(Op1); 1863 std::swap(RL, RR); 1864 } 1865 if (LL == RL && LR == RR) { 1866 bool isInteger = MVT::isInteger(LL.getValueType()); 1867 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1868 if (Result != ISD::SETCC_INVALID) 1869 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1870 } 1871 } 1872 1873 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1874 if (N0.getOpcode() == N1.getOpcode()) { 1875 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1876 if (Tmp.Val) return Tmp; 1877 } 1878 1879 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1880 if (N0.getOpcode() == ISD::AND && 1881 N1.getOpcode() == ISD::AND && 1882 N0.getOperand(1).getOpcode() == ISD::Constant && 1883 N1.getOperand(1).getOpcode() == ISD::Constant && 1884 // Don't increase # computations. 1885 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1886 // We can only do this xform if we know that bits from X that are set in C2 1887 // but not in C1 are already zero. Likewise for Y. 1888 const APInt &LHSMask = 1889 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1890 const APInt &RHSMask = 1891 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1892 1893 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1894 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1895 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1896 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1897 } 1898 } 1899 1900 1901 // See if this is some rotate idiom. 1902 if (SDNode *Rot = MatchRotate(N0, N1)) 1903 return SDOperand(Rot, 0); 1904 1905 return SDOperand(); 1906} 1907 1908 1909/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1910static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1911 if (Op.getOpcode() == ISD::AND) { 1912 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1913 Mask = Op.getOperand(1); 1914 Op = Op.getOperand(0); 1915 } else { 1916 return false; 1917 } 1918 } 1919 1920 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1921 Shift = Op; 1922 return true; 1923 } 1924 return false; 1925} 1926 1927 1928// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1929// idioms for rotate, and if the target supports rotation instructions, generate 1930// a rot[lr]. 1931SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1932 // Must be a legal type. Expanded an promoted things won't work with rotates. 1933 MVT::ValueType VT = LHS.getValueType(); 1934 if (!TLI.isTypeLegal(VT)) return 0; 1935 1936 // The target must have at least one rotate flavor. 1937 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1938 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1939 if (!HasROTL && !HasROTR) return 0; 1940 1941 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1942 SDOperand LHSShift; // The shift. 1943 SDOperand LHSMask; // AND value if any. 1944 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1945 return 0; // Not part of a rotate. 1946 1947 SDOperand RHSShift; // The shift. 1948 SDOperand RHSMask; // AND value if any. 1949 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1950 return 0; // Not part of a rotate. 1951 1952 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1953 return 0; // Not shifting the same value. 1954 1955 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1956 return 0; // Shifts must disagree. 1957 1958 // Canonicalize shl to left side in a shl/srl pair. 1959 if (RHSShift.getOpcode() == ISD::SHL) { 1960 std::swap(LHS, RHS); 1961 std::swap(LHSShift, RHSShift); 1962 std::swap(LHSMask , RHSMask ); 1963 } 1964 1965 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1966 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1967 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1968 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1969 1970 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1971 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1972 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1973 RHSShiftAmt.getOpcode() == ISD::Constant) { 1974 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1975 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1976 if ((LShVal + RShVal) != OpSizeInBits) 1977 return 0; 1978 1979 SDOperand Rot; 1980 if (HasROTL) 1981 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1982 else 1983 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1984 1985 // If there is an AND of either shifted operand, apply it to the result. 1986 if (LHSMask.Val || RHSMask.Val) { 1987 uint64_t Mask = MVT::getIntVTBitMask(VT); 1988 1989 if (LHSMask.Val) { 1990 uint64_t RHSBits = (1ULL << LShVal)-1; 1991 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1992 } 1993 if (RHSMask.Val) { 1994 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1995 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1996 } 1997 1998 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1999 } 2000 2001 return Rot.Val; 2002 } 2003 2004 // If there is a mask here, and we have a variable shift, we can't be sure 2005 // that we're masking out the right stuff. 2006 if (LHSMask.Val || RHSMask.Val) 2007 return 0; 2008 2009 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2010 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2011 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2012 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2013 if (ConstantSDNode *SUBC = 2014 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2015 if (SUBC->getValue() == OpSizeInBits) { 2016 if (HasROTL) 2017 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2018 else 2019 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2020 } 2021 } 2022 } 2023 2024 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2025 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2026 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2027 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2028 if (ConstantSDNode *SUBC = 2029 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2030 if (SUBC->getValue() == OpSizeInBits) { 2031 if (HasROTL) 2032 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2033 else 2034 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2035 } 2036 } 2037 } 2038 2039 // Look for sign/zext/any-extended cases: 2040 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2041 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2042 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2043 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2044 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2045 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2046 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 2047 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 2048 if (RExtOp0.getOpcode() == ISD::SUB && 2049 RExtOp0.getOperand(1) == LExtOp0) { 2050 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2051 // (rotr x, y) 2052 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2053 // (rotl x, (sub 32, y)) 2054 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2055 if (SUBC->getValue() == OpSizeInBits) { 2056 if (HasROTL) 2057 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2058 else 2059 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2060 } 2061 } 2062 } else if (LExtOp0.getOpcode() == ISD::SUB && 2063 RExtOp0 == LExtOp0.getOperand(1)) { 2064 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2065 // (rotl x, y) 2066 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2067 // (rotr x, (sub 32, y)) 2068 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2069 if (SUBC->getValue() == OpSizeInBits) { 2070 if (HasROTL) 2071 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2072 else 2073 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2074 } 2075 } 2076 } 2077 } 2078 2079 return 0; 2080} 2081 2082 2083SDOperand DAGCombiner::visitXOR(SDNode *N) { 2084 SDOperand N0 = N->getOperand(0); 2085 SDOperand N1 = N->getOperand(1); 2086 SDOperand LHS, RHS, CC; 2087 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2088 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2089 MVT::ValueType VT = N0.getValueType(); 2090 2091 // fold vector ops 2092 if (MVT::isVector(VT)) { 2093 SDOperand FoldedVOp = SimplifyVBinOp(N); 2094 if (FoldedVOp.Val) return FoldedVOp; 2095 } 2096 2097 // fold (xor x, undef) -> undef 2098 if (N0.getOpcode() == ISD::UNDEF) 2099 return N0; 2100 if (N1.getOpcode() == ISD::UNDEF) 2101 return N1; 2102 // fold (xor c1, c2) -> c1^c2 2103 if (N0C && N1C) 2104 return DAG.getNode(ISD::XOR, VT, N0, N1); 2105 // canonicalize constant to RHS 2106 if (N0C && !N1C) 2107 return DAG.getNode(ISD::XOR, VT, N1, N0); 2108 // fold (xor x, 0) -> x 2109 if (N1C && N1C->isNullValue()) 2110 return N0; 2111 // reassociate xor 2112 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2113 if (RXOR.Val != 0) 2114 return RXOR; 2115 // fold !(x cc y) -> (x !cc y) 2116 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2117 bool isInt = MVT::isInteger(LHS.getValueType()); 2118 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2119 isInt); 2120 if (N0.getOpcode() == ISD::SETCC) 2121 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2122 if (N0.getOpcode() == ISD::SELECT_CC) 2123 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2124 assert(0 && "Unhandled SetCC Equivalent!"); 2125 abort(); 2126 } 2127 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2128 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2129 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2130 SDOperand V = N0.getOperand(0); 2131 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2132 DAG.getConstant(1, V.getValueType())); 2133 AddToWorkList(V.Val); 2134 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2135 } 2136 2137 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2138 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2139 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2140 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2141 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2142 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2143 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2144 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2145 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2146 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2147 } 2148 } 2149 // fold !(x or y) -> (!x and !y) iff x or y are constants 2150 if (N1C && N1C->isAllOnesValue() && 2151 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2152 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2153 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2154 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2155 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2156 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2157 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2158 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2159 } 2160 } 2161 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2162 if (N1C && N0.getOpcode() == ISD::XOR) { 2163 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2164 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2165 if (N00C) 2166 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2167 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2168 if (N01C) 2169 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2170 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2171 } 2172 // fold (xor x, x) -> 0 2173 if (N0 == N1) { 2174 if (!MVT::isVector(VT)) { 2175 return DAG.getConstant(0, VT); 2176 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2177 // Produce a vector of zeros. 2178 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2179 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2180 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2181 } 2182 } 2183 2184 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2185 if (N0.getOpcode() == N1.getOpcode()) { 2186 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2187 if (Tmp.Val) return Tmp; 2188 } 2189 2190 // Simplify the expression using non-local knowledge. 2191 if (!MVT::isVector(VT) && 2192 SimplifyDemandedBits(SDOperand(N, 0))) 2193 return SDOperand(N, 0); 2194 2195 return SDOperand(); 2196} 2197 2198/// visitShiftByConstant - Handle transforms common to the three shifts, when 2199/// the shift amount is a constant. 2200SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2201 SDNode *LHS = N->getOperand(0).Val; 2202 if (!LHS->hasOneUse()) return SDOperand(); 2203 2204 // We want to pull some binops through shifts, so that we have (and (shift)) 2205 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2206 // thing happens with address calculations, so it's important to canonicalize 2207 // it. 2208 bool HighBitSet = false; // Can we transform this if the high bit is set? 2209 2210 switch (LHS->getOpcode()) { 2211 default: return SDOperand(); 2212 case ISD::OR: 2213 case ISD::XOR: 2214 HighBitSet = false; // We can only transform sra if the high bit is clear. 2215 break; 2216 case ISD::AND: 2217 HighBitSet = true; // We can only transform sra if the high bit is set. 2218 break; 2219 case ISD::ADD: 2220 if (N->getOpcode() != ISD::SHL) 2221 return SDOperand(); // only shl(add) not sr[al](add). 2222 HighBitSet = false; // We can only transform sra if the high bit is clear. 2223 break; 2224 } 2225 2226 // We require the RHS of the binop to be a constant as well. 2227 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2228 if (!BinOpCst) return SDOperand(); 2229 2230 2231 // FIXME: disable this for unless the input to the binop is a shift by a 2232 // constant. If it is not a shift, it pessimizes some common cases like: 2233 // 2234 //void foo(int *X, int i) { X[i & 1235] = 1; } 2235 //int bar(int *X, int i) { return X[i & 255]; } 2236 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2237 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2238 BinOpLHSVal->getOpcode() != ISD::SRA && 2239 BinOpLHSVal->getOpcode() != ISD::SRL) || 2240 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2241 return SDOperand(); 2242 2243 MVT::ValueType VT = N->getValueType(0); 2244 2245 // If this is a signed shift right, and the high bit is modified 2246 // by the logical operation, do not perform the transformation. 2247 // The highBitSet boolean indicates the value of the high bit of 2248 // the constant which would cause it to be modified for this 2249 // operation. 2250 if (N->getOpcode() == ISD::SRA) { 2251 uint64_t BinOpRHSSign = BinOpCst->getValue() >> (MVT::getSizeInBits(VT)-1); 2252 if ((bool)BinOpRHSSign != HighBitSet) 2253 return SDOperand(); 2254 } 2255 2256 // Fold the constants, shifting the binop RHS by the shift amount. 2257 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2258 LHS->getOperand(1), N->getOperand(1)); 2259 2260 // Create the new shift. 2261 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2262 N->getOperand(1)); 2263 2264 // Create the new binop. 2265 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2266} 2267 2268 2269SDOperand DAGCombiner::visitSHL(SDNode *N) { 2270 SDOperand N0 = N->getOperand(0); 2271 SDOperand N1 = N->getOperand(1); 2272 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2273 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2274 MVT::ValueType VT = N0.getValueType(); 2275 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2276 2277 // fold (shl c1, c2) -> c1<<c2 2278 if (N0C && N1C) 2279 return DAG.getNode(ISD::SHL, VT, N0, N1); 2280 // fold (shl 0, x) -> 0 2281 if (N0C && N0C->isNullValue()) 2282 return N0; 2283 // fold (shl x, c >= size(x)) -> undef 2284 if (N1C && N1C->getValue() >= OpSizeInBits) 2285 return DAG.getNode(ISD::UNDEF, VT); 2286 // fold (shl x, 0) -> x 2287 if (N1C && N1C->isNullValue()) 2288 return N0; 2289 // if (shl x, c) is known to be zero, return 0 2290 if (DAG.MaskedValueIsZero(SDOperand(N, 0), 2291 APInt::getAllOnesValue(MVT::getSizeInBits(VT)))) 2292 return DAG.getConstant(0, VT); 2293 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2294 return SDOperand(N, 0); 2295 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2296 if (N1C && N0.getOpcode() == ISD::SHL && 2297 N0.getOperand(1).getOpcode() == ISD::Constant) { 2298 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2299 uint64_t c2 = N1C->getValue(); 2300 if (c1 + c2 > OpSizeInBits) 2301 return DAG.getConstant(0, VT); 2302 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2303 DAG.getConstant(c1 + c2, N1.getValueType())); 2304 } 2305 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2306 // (srl (and x, -1 << c1), c1-c2) 2307 if (N1C && N0.getOpcode() == ISD::SRL && 2308 N0.getOperand(1).getOpcode() == ISD::Constant) { 2309 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2310 uint64_t c2 = N1C->getValue(); 2311 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2312 DAG.getConstant(~0ULL << c1, VT)); 2313 if (c2 > c1) 2314 return DAG.getNode(ISD::SHL, VT, Mask, 2315 DAG.getConstant(c2-c1, N1.getValueType())); 2316 else 2317 return DAG.getNode(ISD::SRL, VT, Mask, 2318 DAG.getConstant(c1-c2, N1.getValueType())); 2319 } 2320 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2321 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2322 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2323 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2324 2325 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2326} 2327 2328SDOperand DAGCombiner::visitSRA(SDNode *N) { 2329 SDOperand N0 = N->getOperand(0); 2330 SDOperand N1 = N->getOperand(1); 2331 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2332 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2333 MVT::ValueType VT = N0.getValueType(); 2334 2335 // fold (sra c1, c2) -> c1>>c2 2336 if (N0C && N1C) 2337 return DAG.getNode(ISD::SRA, VT, N0, N1); 2338 // fold (sra 0, x) -> 0 2339 if (N0C && N0C->isNullValue()) 2340 return N0; 2341 // fold (sra -1, x) -> -1 2342 if (N0C && N0C->isAllOnesValue()) 2343 return N0; 2344 // fold (sra x, c >= size(x)) -> undef 2345 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2346 return DAG.getNode(ISD::UNDEF, VT); 2347 // fold (sra x, 0) -> x 2348 if (N1C && N1C->isNullValue()) 2349 return N0; 2350 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2351 // sext_inreg. 2352 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2353 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2354 MVT::ValueType EVT; 2355 switch (LowBits) { 2356 default: EVT = MVT::Other; break; 2357 case 1: EVT = MVT::i1; break; 2358 case 8: EVT = MVT::i8; break; 2359 case 16: EVT = MVT::i16; break; 2360 case 32: EVT = MVT::i32; break; 2361 } 2362 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2363 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2364 DAG.getValueType(EVT)); 2365 } 2366 2367 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2368 if (N1C && N0.getOpcode() == ISD::SRA) { 2369 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2370 unsigned Sum = N1C->getValue() + C1->getValue(); 2371 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2372 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2373 DAG.getConstant(Sum, N1C->getValueType(0))); 2374 } 2375 } 2376 2377 // Simplify, based on bits shifted out of the LHS. 2378 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2379 return SDOperand(N, 0); 2380 2381 2382 // If the sign bit is known to be zero, switch this to a SRL. 2383 if (DAG.SignBitIsZero(N0)) 2384 return DAG.getNode(ISD::SRL, VT, N0, N1); 2385 2386 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2387} 2388 2389SDOperand DAGCombiner::visitSRL(SDNode *N) { 2390 SDOperand N0 = N->getOperand(0); 2391 SDOperand N1 = N->getOperand(1); 2392 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2393 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2394 MVT::ValueType VT = N0.getValueType(); 2395 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2396 2397 // fold (srl c1, c2) -> c1 >>u c2 2398 if (N0C && N1C) 2399 return DAG.getNode(ISD::SRL, VT, N0, N1); 2400 // fold (srl 0, x) -> 0 2401 if (N0C && N0C->isNullValue()) 2402 return N0; 2403 // fold (srl x, c >= size(x)) -> undef 2404 if (N1C && N1C->getValue() >= OpSizeInBits) 2405 return DAG.getNode(ISD::UNDEF, VT); 2406 // fold (srl x, 0) -> x 2407 if (N1C && N1C->isNullValue()) 2408 return N0; 2409 // if (srl x, c) is known to be zero, return 0 2410 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 2411 APInt::getAllOnesValue(OpSizeInBits))) 2412 return DAG.getConstant(0, VT); 2413 2414 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2415 if (N1C && N0.getOpcode() == ISD::SRL && 2416 N0.getOperand(1).getOpcode() == ISD::Constant) { 2417 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2418 uint64_t c2 = N1C->getValue(); 2419 if (c1 + c2 > OpSizeInBits) 2420 return DAG.getConstant(0, VT); 2421 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2422 DAG.getConstant(c1 + c2, N1.getValueType())); 2423 } 2424 2425 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2426 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2427 // Shifting in all undef bits? 2428 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2429 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2430 return DAG.getNode(ISD::UNDEF, VT); 2431 2432 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2433 AddToWorkList(SmallShift.Val); 2434 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2435 } 2436 2437 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2438 // bit, which is unmodified by sra. 2439 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2440 if (N0.getOpcode() == ISD::SRA) 2441 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2442 } 2443 2444 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2445 if (N1C && N0.getOpcode() == ISD::CTLZ && 2446 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2447 APInt KnownZero, KnownOne; 2448 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 2449 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2450 2451 // If any of the input bits are KnownOne, then the input couldn't be all 2452 // zeros, thus the result of the srl will always be zero. 2453 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2454 2455 // If all of the bits input the to ctlz node are known to be zero, then 2456 // the result of the ctlz is "32" and the result of the shift is one. 2457 APInt UnknownBits = ~KnownZero & Mask; 2458 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2459 2460 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2461 if ((UnknownBits & (UnknownBits-1)) == 0) { 2462 // Okay, we know that only that the single bit specified by UnknownBits 2463 // could be set on input to the CTLZ node. If this bit is set, the SRL 2464 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2465 // to an SRL,XOR pair, which is likely to simplify more. 2466 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2467 SDOperand Op = N0.getOperand(0); 2468 if (ShAmt) { 2469 Op = DAG.getNode(ISD::SRL, VT, Op, 2470 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2471 AddToWorkList(Op.Val); 2472 } 2473 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2474 } 2475 } 2476 2477 // fold operands of srl based on knowledge that the low bits are not 2478 // demanded. 2479 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2480 return SDOperand(N, 0); 2481 2482 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2483} 2484 2485SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2486 SDOperand N0 = N->getOperand(0); 2487 MVT::ValueType VT = N->getValueType(0); 2488 2489 // fold (ctlz c1) -> c2 2490 if (isa<ConstantSDNode>(N0)) 2491 return DAG.getNode(ISD::CTLZ, VT, N0); 2492 return SDOperand(); 2493} 2494 2495SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2496 SDOperand N0 = N->getOperand(0); 2497 MVT::ValueType VT = N->getValueType(0); 2498 2499 // fold (cttz c1) -> c2 2500 if (isa<ConstantSDNode>(N0)) 2501 return DAG.getNode(ISD::CTTZ, VT, N0); 2502 return SDOperand(); 2503} 2504 2505SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2506 SDOperand N0 = N->getOperand(0); 2507 MVT::ValueType VT = N->getValueType(0); 2508 2509 // fold (ctpop c1) -> c2 2510 if (isa<ConstantSDNode>(N0)) 2511 return DAG.getNode(ISD::CTPOP, VT, N0); 2512 return SDOperand(); 2513} 2514 2515SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2516 SDOperand N0 = N->getOperand(0); 2517 SDOperand N1 = N->getOperand(1); 2518 SDOperand N2 = N->getOperand(2); 2519 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2521 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2522 MVT::ValueType VT = N->getValueType(0); 2523 MVT::ValueType VT0 = N0.getValueType(); 2524 2525 // fold select C, X, X -> X 2526 if (N1 == N2) 2527 return N1; 2528 // fold select true, X, Y -> X 2529 if (N0C && !N0C->isNullValue()) 2530 return N1; 2531 // fold select false, X, Y -> Y 2532 if (N0C && N0C->isNullValue()) 2533 return N2; 2534 // fold select C, 1, X -> C | X 2535 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2536 return DAG.getNode(ISD::OR, VT, N0, N2); 2537 // fold select C, 0, 1 -> ~C 2538 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2539 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2540 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2541 if (VT == VT0) 2542 return XORNode; 2543 AddToWorkList(XORNode.Val); 2544 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2545 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2546 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2547 } 2548 // fold select C, 0, X -> ~C & X 2549 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2550 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2551 AddToWorkList(XORNode.Val); 2552 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2553 } 2554 // fold select C, X, 1 -> ~C | X 2555 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) { 2556 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2557 AddToWorkList(XORNode.Val); 2558 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2559 } 2560 // fold select C, X, 0 -> C & X 2561 // FIXME: this should check for C type == X type, not i1? 2562 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2563 return DAG.getNode(ISD::AND, VT, N0, N1); 2564 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2565 if (MVT::i1 == VT && N0 == N1) 2566 return DAG.getNode(ISD::OR, VT, N0, N2); 2567 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2568 if (MVT::i1 == VT && N0 == N2) 2569 return DAG.getNode(ISD::AND, VT, N0, N1); 2570 2571 // If we can fold this based on the true/false value, do so. 2572 if (SimplifySelectOps(N, N1, N2)) 2573 return SDOperand(N, 0); // Don't revisit N. 2574 2575 // fold selects based on a setcc into other things, such as min/max/abs 2576 if (N0.getOpcode() == ISD::SETCC) { 2577 // FIXME: 2578 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2579 // having to say they don't support SELECT_CC on every type the DAG knows 2580 // about, since there is no way to mark an opcode illegal at all value types 2581 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2582 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2583 N1, N2, N0.getOperand(2)); 2584 else 2585 return SimplifySelect(N0, N1, N2); 2586 } 2587 return SDOperand(); 2588} 2589 2590SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2591 SDOperand N0 = N->getOperand(0); 2592 SDOperand N1 = N->getOperand(1); 2593 SDOperand N2 = N->getOperand(2); 2594 SDOperand N3 = N->getOperand(3); 2595 SDOperand N4 = N->getOperand(4); 2596 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2597 2598 // fold select_cc lhs, rhs, x, x, cc -> x 2599 if (N2 == N3) 2600 return N2; 2601 2602 // Determine if the condition we're dealing with is constant 2603 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2604 if (SCC.Val) AddToWorkList(SCC.Val); 2605 2606 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2607 if (SCCC->getValue()) 2608 return N2; // cond always true -> true val 2609 else 2610 return N3; // cond always false -> false val 2611 } 2612 2613 // Fold to a simpler select_cc 2614 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2615 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2616 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2617 SCC.getOperand(2)); 2618 2619 // If we can fold this based on the true/false value, do so. 2620 if (SimplifySelectOps(N, N2, N3)) 2621 return SDOperand(N, 0); // Don't revisit N. 2622 2623 // fold select_cc into other things, such as min/max/abs 2624 return SimplifySelectCC(N0, N1, N2, N3, CC); 2625} 2626 2627SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2628 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2629 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2630} 2631 2632// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2633// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2634// transformation. Returns true if extension are possible and the above 2635// mentioned transformation is profitable. 2636static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2637 unsigned ExtOpc, 2638 SmallVector<SDNode*, 4> &ExtendNodes, 2639 TargetLowering &TLI) { 2640 bool HasCopyToRegUses = false; 2641 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2642 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2643 UI != UE; ++UI) { 2644 SDNode *User = *UI; 2645 if (User == N) 2646 continue; 2647 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2648 if (User->getOpcode() == ISD::SETCC) { 2649 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2650 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2651 // Sign bits will be lost after a zext. 2652 return false; 2653 bool Add = false; 2654 for (unsigned i = 0; i != 2; ++i) { 2655 SDOperand UseOp = User->getOperand(i); 2656 if (UseOp == N0) 2657 continue; 2658 if (!isa<ConstantSDNode>(UseOp)) 2659 return false; 2660 Add = true; 2661 } 2662 if (Add) 2663 ExtendNodes.push_back(User); 2664 } else { 2665 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2666 SDOperand UseOp = User->getOperand(i); 2667 if (UseOp == N0) { 2668 // If truncate from extended type to original load type is free 2669 // on this target, then it's ok to extend a CopyToReg. 2670 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2671 HasCopyToRegUses = true; 2672 else 2673 return false; 2674 } 2675 } 2676 } 2677 } 2678 2679 if (HasCopyToRegUses) { 2680 bool BothLiveOut = false; 2681 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2682 UI != UE; ++UI) { 2683 SDNode *User = *UI; 2684 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2685 SDOperand UseOp = User->getOperand(i); 2686 if (UseOp.Val == N && UseOp.ResNo == 0) { 2687 BothLiveOut = true; 2688 break; 2689 } 2690 } 2691 } 2692 if (BothLiveOut) 2693 // Both unextended and extended values are live out. There had better be 2694 // good a reason for the transformation. 2695 return ExtendNodes.size(); 2696 } 2697 return true; 2698} 2699 2700SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2701 SDOperand N0 = N->getOperand(0); 2702 MVT::ValueType VT = N->getValueType(0); 2703 2704 // fold (sext c1) -> c1 2705 if (isa<ConstantSDNode>(N0)) 2706 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2707 2708 // fold (sext (sext x)) -> (sext x) 2709 // fold (sext (aext x)) -> (sext x) 2710 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2711 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2712 2713 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2714 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2715 if (N0.getOpcode() == ISD::TRUNCATE) { 2716 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2717 if (NarrowLoad.Val) { 2718 if (NarrowLoad.Val != N0.Val) 2719 CombineTo(N0.Val, NarrowLoad); 2720 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2721 } 2722 } 2723 2724 // See if the value being truncated is already sign extended. If so, just 2725 // eliminate the trunc/sext pair. 2726 if (N0.getOpcode() == ISD::TRUNCATE) { 2727 SDOperand Op = N0.getOperand(0); 2728 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2729 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2730 unsigned DestBits = MVT::getSizeInBits(VT); 2731 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2732 2733 if (OpBits == DestBits) { 2734 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2735 // bits, it is already ready. 2736 if (NumSignBits > DestBits-MidBits) 2737 return Op; 2738 } else if (OpBits < DestBits) { 2739 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2740 // bits, just sext from i32. 2741 if (NumSignBits > OpBits-MidBits) 2742 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2743 } else { 2744 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2745 // bits, just truncate to i32. 2746 if (NumSignBits > OpBits-MidBits) 2747 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2748 } 2749 2750 // fold (sext (truncate x)) -> (sextinreg x). 2751 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2752 N0.getValueType())) { 2753 if (Op.getValueType() < VT) 2754 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2755 else if (Op.getValueType() > VT) 2756 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2757 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2758 DAG.getValueType(N0.getValueType())); 2759 } 2760 } 2761 2762 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2763 if (ISD::isNON_EXTLoad(N0.Val) && 2764 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2765 bool DoXform = true; 2766 SmallVector<SDNode*, 4> SetCCs; 2767 if (!N0.hasOneUse()) 2768 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2769 if (DoXform) { 2770 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2771 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2772 LN0->getBasePtr(), LN0->getSrcValue(), 2773 LN0->getSrcValueOffset(), 2774 N0.getValueType(), 2775 LN0->isVolatile(), 2776 LN0->getAlignment()); 2777 CombineTo(N, ExtLoad); 2778 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2779 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2780 // Extend SetCC uses if necessary. 2781 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2782 SDNode *SetCC = SetCCs[i]; 2783 SmallVector<SDOperand, 4> Ops; 2784 for (unsigned j = 0; j != 2; ++j) { 2785 SDOperand SOp = SetCC->getOperand(j); 2786 if (SOp == Trunc) 2787 Ops.push_back(ExtLoad); 2788 else 2789 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2790 } 2791 Ops.push_back(SetCC->getOperand(2)); 2792 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2793 &Ops[0], Ops.size())); 2794 } 2795 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2796 } 2797 } 2798 2799 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2800 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2801 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2802 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2803 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2804 MVT::ValueType EVT = LN0->getMemoryVT(); 2805 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2806 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2807 LN0->getBasePtr(), LN0->getSrcValue(), 2808 LN0->getSrcValueOffset(), EVT, 2809 LN0->isVolatile(), 2810 LN0->getAlignment()); 2811 CombineTo(N, ExtLoad); 2812 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2813 ExtLoad.getValue(1)); 2814 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2815 } 2816 } 2817 2818 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2819 if (N0.getOpcode() == ISD::SETCC) { 2820 SDOperand SCC = 2821 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2822 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2823 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2824 if (SCC.Val) return SCC; 2825 } 2826 2827 return SDOperand(); 2828} 2829 2830SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2831 SDOperand N0 = N->getOperand(0); 2832 MVT::ValueType VT = N->getValueType(0); 2833 2834 // fold (zext c1) -> c1 2835 if (isa<ConstantSDNode>(N0)) 2836 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2837 // fold (zext (zext x)) -> (zext x) 2838 // fold (zext (aext x)) -> (zext x) 2839 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2840 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2841 2842 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2843 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2844 if (N0.getOpcode() == ISD::TRUNCATE) { 2845 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2846 if (NarrowLoad.Val) { 2847 if (NarrowLoad.Val != N0.Val) 2848 CombineTo(N0.Val, NarrowLoad); 2849 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2850 } 2851 } 2852 2853 // fold (zext (truncate x)) -> (and x, mask) 2854 if (N0.getOpcode() == ISD::TRUNCATE && 2855 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2856 SDOperand Op = N0.getOperand(0); 2857 if (Op.getValueType() < VT) { 2858 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2859 } else if (Op.getValueType() > VT) { 2860 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2861 } 2862 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2863 } 2864 2865 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2866 if (N0.getOpcode() == ISD::AND && 2867 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2868 N0.getOperand(1).getOpcode() == ISD::Constant) { 2869 SDOperand X = N0.getOperand(0).getOperand(0); 2870 if (X.getValueType() < VT) { 2871 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2872 } else if (X.getValueType() > VT) { 2873 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2874 } 2875 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2876 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2877 } 2878 2879 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2880 if (ISD::isNON_EXTLoad(N0.Val) && 2881 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2882 bool DoXform = true; 2883 SmallVector<SDNode*, 4> SetCCs; 2884 if (!N0.hasOneUse()) 2885 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2886 if (DoXform) { 2887 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2888 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2889 LN0->getBasePtr(), LN0->getSrcValue(), 2890 LN0->getSrcValueOffset(), 2891 N0.getValueType(), 2892 LN0->isVolatile(), 2893 LN0->getAlignment()); 2894 CombineTo(N, ExtLoad); 2895 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2896 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2897 // Extend SetCC uses if necessary. 2898 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2899 SDNode *SetCC = SetCCs[i]; 2900 SmallVector<SDOperand, 4> Ops; 2901 for (unsigned j = 0; j != 2; ++j) { 2902 SDOperand SOp = SetCC->getOperand(j); 2903 if (SOp == Trunc) 2904 Ops.push_back(ExtLoad); 2905 else 2906 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2907 } 2908 Ops.push_back(SetCC->getOperand(2)); 2909 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2910 &Ops[0], Ops.size())); 2911 } 2912 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2913 } 2914 } 2915 2916 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2917 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2918 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2919 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2920 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2921 MVT::ValueType EVT = LN0->getMemoryVT(); 2922 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2923 LN0->getBasePtr(), LN0->getSrcValue(), 2924 LN0->getSrcValueOffset(), EVT, 2925 LN0->isVolatile(), 2926 LN0->getAlignment()); 2927 CombineTo(N, ExtLoad); 2928 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2929 ExtLoad.getValue(1)); 2930 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2931 } 2932 2933 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2934 if (N0.getOpcode() == ISD::SETCC) { 2935 SDOperand SCC = 2936 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2937 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2938 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2939 if (SCC.Val) return SCC; 2940 } 2941 2942 return SDOperand(); 2943} 2944 2945SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2946 SDOperand N0 = N->getOperand(0); 2947 MVT::ValueType VT = N->getValueType(0); 2948 2949 // fold (aext c1) -> c1 2950 if (isa<ConstantSDNode>(N0)) 2951 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2952 // fold (aext (aext x)) -> (aext x) 2953 // fold (aext (zext x)) -> (zext x) 2954 // fold (aext (sext x)) -> (sext x) 2955 if (N0.getOpcode() == ISD::ANY_EXTEND || 2956 N0.getOpcode() == ISD::ZERO_EXTEND || 2957 N0.getOpcode() == ISD::SIGN_EXTEND) 2958 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2959 2960 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2961 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2962 if (N0.getOpcode() == ISD::TRUNCATE) { 2963 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2964 if (NarrowLoad.Val) { 2965 if (NarrowLoad.Val != N0.Val) 2966 CombineTo(N0.Val, NarrowLoad); 2967 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2968 } 2969 } 2970 2971 // fold (aext (truncate x)) 2972 if (N0.getOpcode() == ISD::TRUNCATE) { 2973 SDOperand TruncOp = N0.getOperand(0); 2974 if (TruncOp.getValueType() == VT) 2975 return TruncOp; // x iff x size == zext size. 2976 if (TruncOp.getValueType() > VT) 2977 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2978 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2979 } 2980 2981 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2982 if (N0.getOpcode() == ISD::AND && 2983 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2984 N0.getOperand(1).getOpcode() == ISD::Constant) { 2985 SDOperand X = N0.getOperand(0).getOperand(0); 2986 if (X.getValueType() < VT) { 2987 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2988 } else if (X.getValueType() > VT) { 2989 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2990 } 2991 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2992 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2993 } 2994 2995 // fold (aext (load x)) -> (aext (truncate (extload x))) 2996 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2997 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2998 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2999 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3000 LN0->getBasePtr(), LN0->getSrcValue(), 3001 LN0->getSrcValueOffset(), 3002 N0.getValueType(), 3003 LN0->isVolatile(), 3004 LN0->getAlignment()); 3005 CombineTo(N, ExtLoad); 3006 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3007 ExtLoad.getValue(1)); 3008 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3009 } 3010 3011 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3012 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3013 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3014 if (N0.getOpcode() == ISD::LOAD && 3015 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3016 N0.hasOneUse()) { 3017 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3018 MVT::ValueType EVT = LN0->getMemoryVT(); 3019 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3020 LN0->getChain(), LN0->getBasePtr(), 3021 LN0->getSrcValue(), 3022 LN0->getSrcValueOffset(), EVT, 3023 LN0->isVolatile(), 3024 LN0->getAlignment()); 3025 CombineTo(N, ExtLoad); 3026 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3027 ExtLoad.getValue(1)); 3028 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3029 } 3030 3031 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3032 if (N0.getOpcode() == ISD::SETCC) { 3033 SDOperand SCC = 3034 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3035 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3036 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3037 if (SCC.Val) 3038 return SCC; 3039 } 3040 3041 return SDOperand(); 3042} 3043 3044/// GetDemandedBits - See if the specified operand can be simplified with the 3045/// knowledge that only the bits specified by Mask are used. If so, return the 3046/// simpler operand, otherwise return a null SDOperand. 3047SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) { 3048 switch (V.getOpcode()) { 3049 default: break; 3050 case ISD::OR: 3051 case ISD::XOR: 3052 // If the LHS or RHS don't contribute bits to the or, drop them. 3053 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3054 return V.getOperand(1); 3055 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3056 return V.getOperand(0); 3057 break; 3058 case ISD::SRL: 3059 // Only look at single-use SRLs. 3060 if (!V.Val->hasOneUse()) 3061 break; 3062 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3063 // See if we can recursively simplify the LHS. 3064 unsigned Amt = RHSC->getValue(); 3065 APInt NewMask = Mask << Amt; 3066 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3067 if (SimplifyLHS.Val) { 3068 return DAG.getNode(ISD::SRL, V.getValueType(), 3069 SimplifyLHS, V.getOperand(1)); 3070 } 3071 } 3072 } 3073 return SDOperand(); 3074} 3075 3076/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3077/// bits and then truncated to a narrower type and where N is a multiple 3078/// of number of bits of the narrower type, transform it to a narrower load 3079/// from address + N / num of bits of new type. If the result is to be 3080/// extended, also fold the extension to form a extending load. 3081SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3082 unsigned Opc = N->getOpcode(); 3083 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3084 SDOperand N0 = N->getOperand(0); 3085 MVT::ValueType VT = N->getValueType(0); 3086 MVT::ValueType EVT = N->getValueType(0); 3087 3088 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3089 // extended to VT. 3090 if (Opc == ISD::SIGN_EXTEND_INREG) { 3091 ExtType = ISD::SEXTLOAD; 3092 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3093 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3094 return SDOperand(); 3095 } 3096 3097 unsigned EVTBits = MVT::getSizeInBits(EVT); 3098 unsigned ShAmt = 0; 3099 bool CombineSRL = false; 3100 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3101 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3102 ShAmt = N01->getValue(); 3103 // Is the shift amount a multiple of size of VT? 3104 if ((ShAmt & (EVTBits-1)) == 0) { 3105 N0 = N0.getOperand(0); 3106 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3107 return SDOperand(); 3108 CombineSRL = true; 3109 } 3110 } 3111 } 3112 3113 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3114 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3115 // zero extended form: by shrinking the load, we lose track of the fact 3116 // that it is already zero extended. 3117 // FIXME: This should be reevaluated. 3118 VT != MVT::i1) { 3119 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3120 "Cannot truncate to larger type!"); 3121 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3122 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3123 // For big endian targets, we need to adjust the offset to the pointer to 3124 // load the correct bytes. 3125 if (TLI.isBigEndian()) { 3126 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3127 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3128 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3129 } 3130 uint64_t PtrOff = ShAmt / 8; 3131 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3132 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3133 DAG.getConstant(PtrOff, PtrType)); 3134 AddToWorkList(NewPtr.Val); 3135 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3136 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3137 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3138 LN0->isVolatile(), NewAlign) 3139 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3140 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3141 LN0->isVolatile(), NewAlign); 3142 AddToWorkList(N); 3143 if (CombineSRL) { 3144 WorkListRemover DeadNodes(*this); 3145 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3146 &DeadNodes); 3147 CombineTo(N->getOperand(0).Val, Load); 3148 } else 3149 CombineTo(N0.Val, Load, Load.getValue(1)); 3150 if (ShAmt) { 3151 if (Opc == ISD::SIGN_EXTEND_INREG) 3152 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3153 else 3154 return DAG.getNode(Opc, VT, Load); 3155 } 3156 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3157 } 3158 3159 return SDOperand(); 3160} 3161 3162 3163SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3164 SDOperand N0 = N->getOperand(0); 3165 SDOperand N1 = N->getOperand(1); 3166 MVT::ValueType VT = N->getValueType(0); 3167 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3168 unsigned VTBits = MVT::getSizeInBits(VT); 3169 unsigned EVTBits = MVT::getSizeInBits(EVT); 3170 3171 // fold (sext_in_reg c1) -> c1 3172 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3173 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3174 3175 // If the input is already sign extended, just drop the extension. 3176 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3177 return N0; 3178 3179 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3180 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3181 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3182 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3183 } 3184 3185 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3186 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3187 return DAG.getZeroExtendInReg(N0, EVT); 3188 3189 // fold operands of sext_in_reg based on knowledge that the top bits are not 3190 // demanded. 3191 if (SimplifyDemandedBits(SDOperand(N, 0))) 3192 return SDOperand(N, 0); 3193 3194 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3195 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3196 SDOperand NarrowLoad = ReduceLoadWidth(N); 3197 if (NarrowLoad.Val) 3198 return NarrowLoad; 3199 3200 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3201 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3202 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3203 if (N0.getOpcode() == ISD::SRL) { 3204 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3205 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3206 // We can turn this into an SRA iff the input to the SRL is already sign 3207 // extended enough. 3208 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3209 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3210 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3211 } 3212 } 3213 3214 // fold (sext_inreg (extload x)) -> (sextload x) 3215 if (ISD::isEXTLoad(N0.Val) && 3216 ISD::isUNINDEXEDLoad(N0.Val) && 3217 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3218 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3219 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3220 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3221 LN0->getBasePtr(), LN0->getSrcValue(), 3222 LN0->getSrcValueOffset(), EVT, 3223 LN0->isVolatile(), 3224 LN0->getAlignment()); 3225 CombineTo(N, ExtLoad); 3226 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3227 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3228 } 3229 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3230 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3231 N0.hasOneUse() && 3232 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3233 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3234 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3235 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3236 LN0->getBasePtr(), LN0->getSrcValue(), 3237 LN0->getSrcValueOffset(), EVT, 3238 LN0->isVolatile(), 3239 LN0->getAlignment()); 3240 CombineTo(N, ExtLoad); 3241 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3242 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3243 } 3244 return SDOperand(); 3245} 3246 3247SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3248 SDOperand N0 = N->getOperand(0); 3249 MVT::ValueType VT = N->getValueType(0); 3250 3251 // noop truncate 3252 if (N0.getValueType() == N->getValueType(0)) 3253 return N0; 3254 // fold (truncate c1) -> c1 3255 if (isa<ConstantSDNode>(N0)) 3256 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3257 // fold (truncate (truncate x)) -> (truncate x) 3258 if (N0.getOpcode() == ISD::TRUNCATE) 3259 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3260 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3261 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3262 N0.getOpcode() == ISD::ANY_EXTEND) { 3263 if (N0.getOperand(0).getValueType() < VT) 3264 // if the source is smaller than the dest, we still need an extend 3265 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3266 else if (N0.getOperand(0).getValueType() > VT) 3267 // if the source is larger than the dest, than we just need the truncate 3268 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3269 else 3270 // if the source and dest are the same type, we can drop both the extend 3271 // and the truncate 3272 return N0.getOperand(0); 3273 } 3274 3275 // See if we can simplify the input to this truncate through knowledge that 3276 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3277 // -> trunc y 3278 SDOperand Shorter = 3279 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3280 MVT::getSizeInBits(VT))); 3281 if (Shorter.Val) 3282 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3283 3284 // fold (truncate (load x)) -> (smaller load x) 3285 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3286 return ReduceLoadWidth(N); 3287} 3288 3289SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3290 SDOperand N0 = N->getOperand(0); 3291 MVT::ValueType VT = N->getValueType(0); 3292 3293 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3294 // Only do this before legalize, since afterward the target may be depending 3295 // on the bitconvert. 3296 // First check to see if this is all constant. 3297 if (!AfterLegalize && 3298 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3299 MVT::isVector(VT)) { 3300 bool isSimple = true; 3301 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3302 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3303 N0.getOperand(i).getOpcode() != ISD::Constant && 3304 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3305 isSimple = false; 3306 break; 3307 } 3308 3309 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3310 assert(!MVT::isVector(DestEltVT) && 3311 "Element type of vector ValueType must not be vector!"); 3312 if (isSimple) { 3313 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3314 } 3315 } 3316 3317 // If the input is a constant, let getNode() fold it. 3318 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3319 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3320 if (Res.Val != N) return Res; 3321 } 3322 3323 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3324 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3325 3326 // fold (conv (load x)) -> (load (conv*)x) 3327 // If the resultant load doesn't need a higher alignment than the original! 3328 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3329 TLI.isOperationLegal(ISD::LOAD, VT)) { 3330 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3331 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3332 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3333 unsigned OrigAlign = LN0->getAlignment(); 3334 if (Align <= OrigAlign) { 3335 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3336 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3337 LN0->isVolatile(), Align); 3338 AddToWorkList(N); 3339 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3340 Load.getValue(1)); 3341 return Load; 3342 } 3343 } 3344 3345 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3346 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3347 // This often reduces constant pool loads. 3348 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3349 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) { 3350 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3351 AddToWorkList(NewConv.Val); 3352 3353 uint64_t SignBit = MVT::getIntVTSignBit(VT); 3354 if (N0.getOpcode() == ISD::FNEG) 3355 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3356 assert(N0.getOpcode() == ISD::FABS); 3357 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3358 } 3359 3360 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3361 // Note that we don't handle copysign(x,cst) because this can always be folded 3362 // to an fneg or fabs. 3363 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3364 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3365 MVT::isInteger(VT) && !MVT::isVector(VT)) { 3366 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType()); 3367 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth), 3368 N0.getOperand(1)); 3369 AddToWorkList(X.Val); 3370 3371 // If X has a different width than the result/lhs, sext it or truncate it. 3372 unsigned VTWidth = MVT::getSizeInBits(VT); 3373 if (OrigXWidth < VTWidth) { 3374 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3375 AddToWorkList(X.Val); 3376 } else if (OrigXWidth > VTWidth) { 3377 // To get the sign bit in the right place, we have to shift it right 3378 // before truncating. 3379 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3380 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3381 AddToWorkList(X.Val); 3382 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3383 AddToWorkList(X.Val); 3384 } 3385 3386 uint64_t SignBit = MVT::getIntVTSignBit(VT); 3387 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3388 AddToWorkList(X.Val); 3389 3390 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3391 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3392 AddToWorkList(Cst.Val); 3393 3394 return DAG.getNode(ISD::OR, VT, X, Cst); 3395 } 3396 3397 return SDOperand(); 3398} 3399 3400/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3401/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3402/// destination element value type. 3403SDOperand DAGCombiner:: 3404ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3405 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3406 3407 // If this is already the right type, we're done. 3408 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3409 3410 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3411 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3412 3413 // If this is a conversion of N elements of one type to N elements of another 3414 // type, convert each element. This handles FP<->INT cases. 3415 if (SrcBitSize == DstBitSize) { 3416 SmallVector<SDOperand, 8> Ops; 3417 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3418 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3419 AddToWorkList(Ops.back().Val); 3420 } 3421 MVT::ValueType VT = 3422 MVT::getVectorType(DstEltVT, 3423 MVT::getVectorNumElements(BV->getValueType(0))); 3424 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3425 } 3426 3427 // Otherwise, we're growing or shrinking the elements. To avoid having to 3428 // handle annoying details of growing/shrinking FP values, we convert them to 3429 // int first. 3430 if (MVT::isFloatingPoint(SrcEltVT)) { 3431 // Convert the input float vector to a int vector where the elements are the 3432 // same sizes. 3433 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3434 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3435 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3436 SrcEltVT = IntVT; 3437 } 3438 3439 // Now we know the input is an integer vector. If the output is a FP type, 3440 // convert to integer first, then to FP of the right size. 3441 if (MVT::isFloatingPoint(DstEltVT)) { 3442 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3443 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3444 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3445 3446 // Next, convert to FP elements of the same size. 3447 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3448 } 3449 3450 // Okay, we know the src/dst types are both integers of differing types. 3451 // Handling growing first. 3452 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3453 if (SrcBitSize < DstBitSize) { 3454 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3455 3456 SmallVector<SDOperand, 8> Ops; 3457 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3458 i += NumInputsPerOutput) { 3459 bool isLE = TLI.isLittleEndian(); 3460 uint64_t NewBits = 0; 3461 bool EltIsUndef = true; 3462 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3463 // Shift the previously computed bits over. 3464 NewBits <<= SrcBitSize; 3465 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3466 if (Op.getOpcode() == ISD::UNDEF) continue; 3467 EltIsUndef = false; 3468 3469 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3470 } 3471 3472 if (EltIsUndef) 3473 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3474 else 3475 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3476 } 3477 3478 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3479 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3480 } 3481 3482 // Finally, this must be the case where we are shrinking elements: each input 3483 // turns into multiple outputs. 3484 bool isS2V = ISD::isScalarToVector(BV); 3485 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3486 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3487 NumOutputsPerInput * BV->getNumOperands()); 3488 SmallVector<SDOperand, 8> Ops; 3489 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3490 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3491 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3492 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3493 continue; 3494 } 3495 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3496 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3497 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3498 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3499 if (isS2V && i == 0 && j == 0 && ThisVal == OpVal) 3500 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3501 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3502 OpVal >>= DstBitSize; 3503 } 3504 3505 // For big endian targets, swap the order of the pieces of each element. 3506 if (TLI.isBigEndian()) 3507 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3508 } 3509 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3510} 3511 3512 3513 3514SDOperand DAGCombiner::visitFADD(SDNode *N) { 3515 SDOperand N0 = N->getOperand(0); 3516 SDOperand N1 = N->getOperand(1); 3517 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3518 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3519 MVT::ValueType VT = N->getValueType(0); 3520 3521 // fold vector ops 3522 if (MVT::isVector(VT)) { 3523 SDOperand FoldedVOp = SimplifyVBinOp(N); 3524 if (FoldedVOp.Val) return FoldedVOp; 3525 } 3526 3527 // fold (fadd c1, c2) -> c1+c2 3528 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3529 return DAG.getNode(ISD::FADD, VT, N0, N1); 3530 // canonicalize constant to RHS 3531 if (N0CFP && !N1CFP) 3532 return DAG.getNode(ISD::FADD, VT, N1, N0); 3533 // fold (A + (-B)) -> A-B 3534 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3535 return DAG.getNode(ISD::FSUB, VT, N0, 3536 GetNegatedExpression(N1, DAG, AfterLegalize)); 3537 // fold ((-A) + B) -> B-A 3538 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3539 return DAG.getNode(ISD::FSUB, VT, N1, 3540 GetNegatedExpression(N0, DAG, AfterLegalize)); 3541 3542 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3543 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3544 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3545 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3546 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3547 3548 return SDOperand(); 3549} 3550 3551SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3552 SDOperand N0 = N->getOperand(0); 3553 SDOperand N1 = N->getOperand(1); 3554 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3555 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3556 MVT::ValueType VT = N->getValueType(0); 3557 3558 // fold vector ops 3559 if (MVT::isVector(VT)) { 3560 SDOperand FoldedVOp = SimplifyVBinOp(N); 3561 if (FoldedVOp.Val) return FoldedVOp; 3562 } 3563 3564 // fold (fsub c1, c2) -> c1-c2 3565 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3566 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3567 // fold (0-B) -> -B 3568 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3569 if (isNegatibleForFree(N1, AfterLegalize)) 3570 return GetNegatedExpression(N1, DAG, AfterLegalize); 3571 return DAG.getNode(ISD::FNEG, VT, N1); 3572 } 3573 // fold (A-(-B)) -> A+B 3574 if (isNegatibleForFree(N1, AfterLegalize)) 3575 return DAG.getNode(ISD::FADD, VT, N0, 3576 GetNegatedExpression(N1, DAG, AfterLegalize)); 3577 3578 return SDOperand(); 3579} 3580 3581SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3582 SDOperand N0 = N->getOperand(0); 3583 SDOperand N1 = N->getOperand(1); 3584 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3585 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3586 MVT::ValueType VT = N->getValueType(0); 3587 3588 // fold vector ops 3589 if (MVT::isVector(VT)) { 3590 SDOperand FoldedVOp = SimplifyVBinOp(N); 3591 if (FoldedVOp.Val) return FoldedVOp; 3592 } 3593 3594 // fold (fmul c1, c2) -> c1*c2 3595 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3596 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3597 // canonicalize constant to RHS 3598 if (N0CFP && !N1CFP) 3599 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3600 // fold (fmul X, 2.0) -> (fadd X, X) 3601 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3602 return DAG.getNode(ISD::FADD, VT, N0, N0); 3603 // fold (fmul X, -1.0) -> (fneg X) 3604 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3605 return DAG.getNode(ISD::FNEG, VT, N0); 3606 3607 // -X * -Y -> X*Y 3608 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3609 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3610 // Both can be negated for free, check to see if at least one is cheaper 3611 // negated. 3612 if (LHSNeg == 2 || RHSNeg == 2) 3613 return DAG.getNode(ISD::FMUL, VT, 3614 GetNegatedExpression(N0, DAG, AfterLegalize), 3615 GetNegatedExpression(N1, DAG, AfterLegalize)); 3616 } 3617 } 3618 3619 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3620 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3621 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3622 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3623 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3624 3625 return SDOperand(); 3626} 3627 3628SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3629 SDOperand N0 = N->getOperand(0); 3630 SDOperand N1 = N->getOperand(1); 3631 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3632 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3633 MVT::ValueType VT = N->getValueType(0); 3634 3635 // fold vector ops 3636 if (MVT::isVector(VT)) { 3637 SDOperand FoldedVOp = SimplifyVBinOp(N); 3638 if (FoldedVOp.Val) return FoldedVOp; 3639 } 3640 3641 // fold (fdiv c1, c2) -> c1/c2 3642 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3643 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3644 3645 3646 // -X / -Y -> X*Y 3647 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3648 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3649 // Both can be negated for free, check to see if at least one is cheaper 3650 // negated. 3651 if (LHSNeg == 2 || RHSNeg == 2) 3652 return DAG.getNode(ISD::FDIV, VT, 3653 GetNegatedExpression(N0, DAG, AfterLegalize), 3654 GetNegatedExpression(N1, DAG, AfterLegalize)); 3655 } 3656 } 3657 3658 return SDOperand(); 3659} 3660 3661SDOperand DAGCombiner::visitFREM(SDNode *N) { 3662 SDOperand N0 = N->getOperand(0); 3663 SDOperand N1 = N->getOperand(1); 3664 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3665 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3666 MVT::ValueType VT = N->getValueType(0); 3667 3668 // fold (frem c1, c2) -> fmod(c1,c2) 3669 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3670 return DAG.getNode(ISD::FREM, VT, N0, N1); 3671 3672 return SDOperand(); 3673} 3674 3675SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3676 SDOperand N0 = N->getOperand(0); 3677 SDOperand N1 = N->getOperand(1); 3678 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3679 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3680 MVT::ValueType VT = N->getValueType(0); 3681 3682 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3683 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3684 3685 if (N1CFP) { 3686 const APFloat& V = N1CFP->getValueAPF(); 3687 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3688 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3689 if (!V.isNegative()) 3690 return DAG.getNode(ISD::FABS, VT, N0); 3691 else 3692 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3693 } 3694 3695 // copysign(fabs(x), y) -> copysign(x, y) 3696 // copysign(fneg(x), y) -> copysign(x, y) 3697 // copysign(copysign(x,z), y) -> copysign(x, y) 3698 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3699 N0.getOpcode() == ISD::FCOPYSIGN) 3700 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3701 3702 // copysign(x, abs(y)) -> abs(x) 3703 if (N1.getOpcode() == ISD::FABS) 3704 return DAG.getNode(ISD::FABS, VT, N0); 3705 3706 // copysign(x, copysign(y,z)) -> copysign(x, z) 3707 if (N1.getOpcode() == ISD::FCOPYSIGN) 3708 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3709 3710 // copysign(x, fp_extend(y)) -> copysign(x, y) 3711 // copysign(x, fp_round(y)) -> copysign(x, y) 3712 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3713 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3714 3715 return SDOperand(); 3716} 3717 3718 3719 3720SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3721 SDOperand N0 = N->getOperand(0); 3722 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3723 MVT::ValueType VT = N->getValueType(0); 3724 3725 // fold (sint_to_fp c1) -> c1fp 3726 if (N0C && N0.getValueType() != MVT::ppcf128) 3727 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3728 return SDOperand(); 3729} 3730 3731SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3732 SDOperand N0 = N->getOperand(0); 3733 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3734 MVT::ValueType VT = N->getValueType(0); 3735 3736 // fold (uint_to_fp c1) -> c1fp 3737 if (N0C && N0.getValueType() != MVT::ppcf128) 3738 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3739 return SDOperand(); 3740} 3741 3742SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3743 SDOperand N0 = N->getOperand(0); 3744 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3745 MVT::ValueType VT = N->getValueType(0); 3746 3747 // fold (fp_to_sint c1fp) -> c1 3748 if (N0CFP) 3749 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3750 return SDOperand(); 3751} 3752 3753SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3754 SDOperand N0 = N->getOperand(0); 3755 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3756 MVT::ValueType VT = N->getValueType(0); 3757 3758 // fold (fp_to_uint c1fp) -> c1 3759 if (N0CFP && VT != MVT::ppcf128) 3760 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3761 return SDOperand(); 3762} 3763 3764SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3765 SDOperand N0 = N->getOperand(0); 3766 SDOperand N1 = N->getOperand(1); 3767 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3768 MVT::ValueType VT = N->getValueType(0); 3769 3770 // fold (fp_round c1fp) -> c1fp 3771 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3772 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3773 3774 // fold (fp_round (fp_extend x)) -> x 3775 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3776 return N0.getOperand(0); 3777 3778 // fold (fp_round (fp_round x)) -> (fp_round x) 3779 if (N0.getOpcode() == ISD::FP_ROUND) { 3780 // This is a value preserving truncation if both round's are. 3781 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3782 N0.Val->getConstantOperandVal(1) == 1; 3783 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3784 DAG.getIntPtrConstant(IsTrunc)); 3785 } 3786 3787 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3788 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3789 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3790 AddToWorkList(Tmp.Val); 3791 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3792 } 3793 3794 return SDOperand(); 3795} 3796 3797SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3798 SDOperand N0 = N->getOperand(0); 3799 MVT::ValueType VT = N->getValueType(0); 3800 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3801 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3802 3803 // fold (fp_round_inreg c1fp) -> c1fp 3804 if (N0CFP) { 3805 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3806 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3807 } 3808 return SDOperand(); 3809} 3810 3811SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3812 SDOperand N0 = N->getOperand(0); 3813 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3814 MVT::ValueType VT = N->getValueType(0); 3815 3816 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3817 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND) 3818 return SDOperand(); 3819 3820 // fold (fp_extend c1fp) -> c1fp 3821 if (N0CFP && VT != MVT::ppcf128) 3822 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3823 3824 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3825 // value of X. 3826 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3827 SDOperand In = N0.getOperand(0); 3828 if (In.getValueType() == VT) return In; 3829 if (VT < In.getValueType()) 3830 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3831 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3832 } 3833 3834 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3835 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3836 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3837 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3838 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3839 LN0->getBasePtr(), LN0->getSrcValue(), 3840 LN0->getSrcValueOffset(), 3841 N0.getValueType(), 3842 LN0->isVolatile(), 3843 LN0->getAlignment()); 3844 CombineTo(N, ExtLoad); 3845 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3846 DAG.getIntPtrConstant(1)), 3847 ExtLoad.getValue(1)); 3848 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3849 } 3850 3851 3852 return SDOperand(); 3853} 3854 3855SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3856 SDOperand N0 = N->getOperand(0); 3857 3858 if (isNegatibleForFree(N0, AfterLegalize)) 3859 return GetNegatedExpression(N0, DAG, AfterLegalize); 3860 3861 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 3862 // constant pool values. 3863 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3864 MVT::isInteger(N0.getOperand(0).getValueType()) && 3865 !MVT::isVector(N0.getOperand(0).getValueType())) { 3866 SDOperand Int = N0.getOperand(0); 3867 MVT::ValueType IntVT = Int.getValueType(); 3868 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3869 Int = DAG.getNode(ISD::XOR, IntVT, Int, 3870 DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT)); 3871 AddToWorkList(Int.Val); 3872 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3873 } 3874 } 3875 3876 return SDOperand(); 3877} 3878 3879SDOperand DAGCombiner::visitFABS(SDNode *N) { 3880 SDOperand N0 = N->getOperand(0); 3881 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3882 MVT::ValueType VT = N->getValueType(0); 3883 3884 // fold (fabs c1) -> fabs(c1) 3885 if (N0CFP && VT != MVT::ppcf128) 3886 return DAG.getNode(ISD::FABS, VT, N0); 3887 // fold (fabs (fabs x)) -> (fabs x) 3888 if (N0.getOpcode() == ISD::FABS) 3889 return N->getOperand(0); 3890 // fold (fabs (fneg x)) -> (fabs x) 3891 // fold (fabs (fcopysign x, y)) -> (fabs x) 3892 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3893 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3894 3895 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 3896 // constant pool values. 3897 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3898 MVT::isInteger(N0.getOperand(0).getValueType()) && 3899 !MVT::isVector(N0.getOperand(0).getValueType())) { 3900 SDOperand Int = N0.getOperand(0); 3901 MVT::ValueType IntVT = Int.getValueType(); 3902 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3903 Int = DAG.getNode(ISD::AND, IntVT, Int, 3904 DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT)); 3905 AddToWorkList(Int.Val); 3906 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3907 } 3908 } 3909 3910 return SDOperand(); 3911} 3912 3913SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3914 SDOperand Chain = N->getOperand(0); 3915 SDOperand N1 = N->getOperand(1); 3916 SDOperand N2 = N->getOperand(2); 3917 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3918 3919 // never taken branch, fold to chain 3920 if (N1C && N1C->isNullValue()) 3921 return Chain; 3922 // unconditional branch 3923 if (N1C && N1C->getValue() == 1) 3924 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3925 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3926 // on the target. 3927 if (N1.getOpcode() == ISD::SETCC && 3928 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3929 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3930 N1.getOperand(0), N1.getOperand(1), N2); 3931 } 3932 return SDOperand(); 3933} 3934 3935// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3936// 3937SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3938 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3939 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3940 3941 // Use SimplifySetCC to simplify SETCC's. 3942 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3943 if (Simp.Val) AddToWorkList(Simp.Val); 3944 3945 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3946 3947 // fold br_cc true, dest -> br dest (unconditional branch) 3948 if (SCCC && SCCC->getValue()) 3949 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3950 N->getOperand(4)); 3951 // fold br_cc false, dest -> unconditional fall through 3952 if (SCCC && SCCC->isNullValue()) 3953 return N->getOperand(0); 3954 3955 // fold to a simpler setcc 3956 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3957 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3958 Simp.getOperand(2), Simp.getOperand(0), 3959 Simp.getOperand(1), N->getOperand(4)); 3960 return SDOperand(); 3961} 3962 3963 3964/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3965/// pre-indexed load / store when the base pointer is a add or subtract 3966/// and it has other uses besides the load / store. After the 3967/// transformation, the new indexed load / store has effectively folded 3968/// the add / subtract in and all of its other uses are redirected to the 3969/// new load / store. 3970bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3971 if (!AfterLegalize) 3972 return false; 3973 3974 bool isLoad = true; 3975 SDOperand Ptr; 3976 MVT::ValueType VT; 3977 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3978 if (LD->isIndexed()) 3979 return false; 3980 VT = LD->getMemoryVT(); 3981 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3982 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3983 return false; 3984 Ptr = LD->getBasePtr(); 3985 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3986 if (ST->isIndexed()) 3987 return false; 3988 VT = ST->getMemoryVT(); 3989 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3990 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3991 return false; 3992 Ptr = ST->getBasePtr(); 3993 isLoad = false; 3994 } else 3995 return false; 3996 3997 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3998 // out. There is no reason to make this a preinc/predec. 3999 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4000 Ptr.Val->hasOneUse()) 4001 return false; 4002 4003 // Ask the target to do addressing mode selection. 4004 SDOperand BasePtr; 4005 SDOperand Offset; 4006 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4007 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4008 return false; 4009 // Don't create a indexed load / store with zero offset. 4010 if (isa<ConstantSDNode>(Offset) && 4011 cast<ConstantSDNode>(Offset)->getValue() == 0) 4012 return false; 4013 4014 // Try turning it into a pre-indexed load / store except when: 4015 // 1) The new base ptr is a frame index. 4016 // 2) If N is a store and the new base ptr is either the same as or is a 4017 // predecessor of the value being stored. 4018 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4019 // that would create a cycle. 4020 // 4) All uses are load / store ops that use it as old base ptr. 4021 4022 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4023 // (plus the implicit offset) to a register to preinc anyway. 4024 if (isa<FrameIndexSDNode>(BasePtr)) 4025 return false; 4026 4027 // Check #2. 4028 if (!isLoad) { 4029 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 4030 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 4031 return false; 4032 } 4033 4034 // Now check for #3 and #4. 4035 bool RealUse = false; 4036 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4037 E = Ptr.Val->use_end(); I != E; ++I) { 4038 SDNode *Use = *I; 4039 if (Use == N) 4040 continue; 4041 if (Use->isPredecessor(N)) 4042 return false; 4043 4044 if (!((Use->getOpcode() == ISD::LOAD && 4045 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4046 (Use->getOpcode() == ISD::STORE && 4047 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4048 RealUse = true; 4049 } 4050 if (!RealUse) 4051 return false; 4052 4053 SDOperand Result; 4054 if (isLoad) 4055 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 4056 else 4057 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4058 ++PreIndexedNodes; 4059 ++NodesCombined; 4060 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4061 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4062 DOUT << '\n'; 4063 WorkListRemover DeadNodes(*this); 4064 if (isLoad) { 4065 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4066 &DeadNodes); 4067 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4068 &DeadNodes); 4069 } else { 4070 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4071 &DeadNodes); 4072 } 4073 4074 // Finally, since the node is now dead, remove it from the graph. 4075 DAG.DeleteNode(N); 4076 4077 // Replace the uses of Ptr with uses of the updated base value. 4078 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4079 &DeadNodes); 4080 removeFromWorkList(Ptr.Val); 4081 DAG.DeleteNode(Ptr.Val); 4082 4083 return true; 4084} 4085 4086/// CombineToPostIndexedLoadStore - Try combine a load / store with a 4087/// add / sub of the base pointer node into a post-indexed load / store. 4088/// The transformation folded the add / subtract into the new indexed 4089/// load / store effectively and all of its uses are redirected to the 4090/// new load / store. 4091bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4092 if (!AfterLegalize) 4093 return false; 4094 4095 bool isLoad = true; 4096 SDOperand Ptr; 4097 MVT::ValueType VT; 4098 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4099 if (LD->isIndexed()) 4100 return false; 4101 VT = LD->getMemoryVT(); 4102 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4103 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4104 return false; 4105 Ptr = LD->getBasePtr(); 4106 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4107 if (ST->isIndexed()) 4108 return false; 4109 VT = ST->getMemoryVT(); 4110 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4111 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4112 return false; 4113 Ptr = ST->getBasePtr(); 4114 isLoad = false; 4115 } else 4116 return false; 4117 4118 if (Ptr.Val->hasOneUse()) 4119 return false; 4120 4121 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4122 E = Ptr.Val->use_end(); I != E; ++I) { 4123 SDNode *Op = *I; 4124 if (Op == N || 4125 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4126 continue; 4127 4128 SDOperand BasePtr; 4129 SDOperand Offset; 4130 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4131 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4132 if (Ptr == Offset) 4133 std::swap(BasePtr, Offset); 4134 if (Ptr != BasePtr) 4135 continue; 4136 // Don't create a indexed load / store with zero offset. 4137 if (isa<ConstantSDNode>(Offset) && 4138 cast<ConstantSDNode>(Offset)->getValue() == 0) 4139 continue; 4140 4141 // Try turning it into a post-indexed load / store except when 4142 // 1) All uses are load / store ops that use it as base ptr. 4143 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4144 // nor a successor of N. Otherwise, if Op is folded that would 4145 // create a cycle. 4146 4147 // Check for #1. 4148 bool TryNext = false; 4149 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4150 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4151 SDNode *Use = *II; 4152 if (Use == Ptr.Val) 4153 continue; 4154 4155 // If all the uses are load / store addresses, then don't do the 4156 // transformation. 4157 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4158 bool RealUse = false; 4159 for (SDNode::use_iterator III = Use->use_begin(), 4160 EEE = Use->use_end(); III != EEE; ++III) { 4161 SDNode *UseUse = *III; 4162 if (!((UseUse->getOpcode() == ISD::LOAD && 4163 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4164 (UseUse->getOpcode() == ISD::STORE && 4165 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))) 4166 RealUse = true; 4167 } 4168 4169 if (!RealUse) { 4170 TryNext = true; 4171 break; 4172 } 4173 } 4174 } 4175 if (TryNext) 4176 continue; 4177 4178 // Check for #2 4179 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 4180 SDOperand Result = isLoad 4181 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4182 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4183 ++PostIndexedNodes; 4184 ++NodesCombined; 4185 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4186 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4187 DOUT << '\n'; 4188 WorkListRemover DeadNodes(*this); 4189 if (isLoad) { 4190 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4191 &DeadNodes); 4192 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4193 &DeadNodes); 4194 } else { 4195 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4196 &DeadNodes); 4197 } 4198 4199 // Finally, since the node is now dead, remove it from the graph. 4200 DAG.DeleteNode(N); 4201 4202 // Replace the uses of Use with uses of the updated base value. 4203 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4204 Result.getValue(isLoad ? 1 : 0), 4205 &DeadNodes); 4206 removeFromWorkList(Op); 4207 DAG.DeleteNode(Op); 4208 return true; 4209 } 4210 } 4211 } 4212 return false; 4213} 4214 4215/// InferAlignment - If we can infer some alignment information from this 4216/// pointer, return it. 4217static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4218 // If this is a direct reference to a stack slot, use information about the 4219 // stack slot's alignment. 4220 int FrameIdx = 1 << 31; 4221 int64_t FrameOffset = 0; 4222 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4223 FrameIdx = FI->getIndex(); 4224 } else if (Ptr.getOpcode() == ISD::ADD && 4225 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4226 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4227 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4228 FrameOffset = Ptr.getConstantOperandVal(1); 4229 } 4230 4231 if (FrameIdx != (1 << 31)) { 4232 // FIXME: Handle FI+CST. 4233 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4234 if (MFI.isFixedObjectIndex(FrameIdx)) { 4235 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4236 4237 // The alignment of the frame index can be determined from its offset from 4238 // the incoming frame position. If the frame object is at offset 32 and 4239 // the stack is guaranteed to be 16-byte aligned, then we know that the 4240 // object is 16-byte aligned. 4241 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4242 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4243 4244 // Finally, the frame object itself may have a known alignment. Factor 4245 // the alignment + offset into a new alignment. For example, if we know 4246 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4247 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4248 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4249 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4250 FrameOffset); 4251 return std::max(Align, FIInfoAlign); 4252 } 4253 } 4254 4255 return 0; 4256} 4257 4258SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4259 LoadSDNode *LD = cast<LoadSDNode>(N); 4260 SDOperand Chain = LD->getChain(); 4261 SDOperand Ptr = LD->getBasePtr(); 4262 4263 // Try to infer better alignment information than the load already has. 4264 if (LD->isUnindexed()) { 4265 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4266 if (Align > LD->getAlignment()) 4267 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4268 Chain, Ptr, LD->getSrcValue(), 4269 LD->getSrcValueOffset(), LD->getMemoryVT(), 4270 LD->isVolatile(), Align); 4271 } 4272 } 4273 4274 4275 // If load is not volatile and there are no uses of the loaded value (and 4276 // the updated indexed value in case of indexed loads), change uses of the 4277 // chain value into uses of the chain input (i.e. delete the dead load). 4278 if (!LD->isVolatile()) { 4279 if (N->getValueType(1) == MVT::Other) { 4280 // Unindexed loads. 4281 if (N->hasNUsesOfValue(0, 0)) { 4282 // It's not safe to use the two value CombineTo variant here. e.g. 4283 // v1, chain2 = load chain1, loc 4284 // v2, chain3 = load chain2, loc 4285 // v3 = add v2, c 4286 // Now we replace use of chain2 with chain1. This makes the second load 4287 // isomorphic to the one we are deleting, and thus makes this load live. 4288 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4289 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4290 DOUT << "\n"; 4291 WorkListRemover DeadNodes(*this); 4292 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes); 4293 if (N->use_empty()) { 4294 removeFromWorkList(N); 4295 DAG.DeleteNode(N); 4296 } 4297 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4298 } 4299 } else { 4300 // Indexed loads. 4301 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4302 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4303 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4304 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4305 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4306 DOUT << " and 2 other values\n"; 4307 WorkListRemover DeadNodes(*this); 4308 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes); 4309 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4310 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4311 &DeadNodes); 4312 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes); 4313 removeFromWorkList(N); 4314 DAG.DeleteNode(N); 4315 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4316 } 4317 } 4318 } 4319 4320 // If this load is directly stored, replace the load value with the stored 4321 // value. 4322 // TODO: Handle store large -> read small portion. 4323 // TODO: Handle TRUNCSTORE/LOADEXT 4324 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4325 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4326 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4327 if (PrevST->getBasePtr() == Ptr && 4328 PrevST->getValue().getValueType() == N->getValueType(0)) 4329 return CombineTo(N, Chain.getOperand(1), Chain); 4330 } 4331 } 4332 4333 if (CombinerAA) { 4334 // Walk up chain skipping non-aliasing memory nodes. 4335 SDOperand BetterChain = FindBetterChain(N, Chain); 4336 4337 // If there is a better chain. 4338 if (Chain != BetterChain) { 4339 SDOperand ReplLoad; 4340 4341 // Replace the chain to void dependency. 4342 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4343 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4344 LD->getSrcValue(), LD->getSrcValueOffset(), 4345 LD->isVolatile(), LD->getAlignment()); 4346 } else { 4347 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4348 LD->getValueType(0), 4349 BetterChain, Ptr, LD->getSrcValue(), 4350 LD->getSrcValueOffset(), 4351 LD->getMemoryVT(), 4352 LD->isVolatile(), 4353 LD->getAlignment()); 4354 } 4355 4356 // Create token factor to keep old chain connected. 4357 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4358 Chain, ReplLoad.getValue(1)); 4359 4360 // Replace uses with load result and token factor. Don't add users 4361 // to work list. 4362 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4363 } 4364 } 4365 4366 // Try transforming N to an indexed load. 4367 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4368 return SDOperand(N, 0); 4369 4370 return SDOperand(); 4371} 4372 4373 4374SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4375 StoreSDNode *ST = cast<StoreSDNode>(N); 4376 SDOperand Chain = ST->getChain(); 4377 SDOperand Value = ST->getValue(); 4378 SDOperand Ptr = ST->getBasePtr(); 4379 4380 // Try to infer better alignment information than the store already has. 4381 if (ST->isUnindexed()) { 4382 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4383 if (Align > ST->getAlignment()) 4384 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4385 ST->getSrcValueOffset(), ST->getMemoryVT(), 4386 ST->isVolatile(), Align); 4387 } 4388 } 4389 4390 // If this is a store of a bit convert, store the input value if the 4391 // resultant store does not need a higher alignment than the original. 4392 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4393 ST->isUnindexed()) { 4394 unsigned Align = ST->getAlignment(); 4395 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4396 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4397 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4398 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4399 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4400 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4401 } 4402 4403 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4404 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4405 if (Value.getOpcode() != ISD::TargetConstantFP) { 4406 SDOperand Tmp; 4407 switch (CFP->getValueType(0)) { 4408 default: assert(0 && "Unknown FP type"); 4409 case MVT::f80: // We don't do this for these yet. 4410 case MVT::f128: 4411 case MVT::ppcf128: 4412 break; 4413 case MVT::f32: 4414 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4415 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4416 convertToAPInt().getZExtValue(), MVT::i32); 4417 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4418 ST->getSrcValueOffset(), ST->isVolatile(), 4419 ST->getAlignment()); 4420 } 4421 break; 4422 case MVT::f64: 4423 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4424 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4425 getZExtValue(), MVT::i64); 4426 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4427 ST->getSrcValueOffset(), ST->isVolatile(), 4428 ST->getAlignment()); 4429 } else if (TLI.isTypeLegal(MVT::i32)) { 4430 // Many FP stores are not made apparent until after legalize, e.g. for 4431 // argument passing. Since this is so common, custom legalize the 4432 // 64-bit integer store into two 32-bit stores. 4433 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4434 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4435 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4436 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4437 4438 int SVOffset = ST->getSrcValueOffset(); 4439 unsigned Alignment = ST->getAlignment(); 4440 bool isVolatile = ST->isVolatile(); 4441 4442 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4443 ST->getSrcValueOffset(), 4444 isVolatile, ST->getAlignment()); 4445 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4446 DAG.getConstant(4, Ptr.getValueType())); 4447 SVOffset += 4; 4448 Alignment = MinAlign(Alignment, 4U); 4449 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4450 SVOffset, isVolatile, Alignment); 4451 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4452 } 4453 break; 4454 } 4455 } 4456 } 4457 4458 if (CombinerAA) { 4459 // Walk up chain skipping non-aliasing memory nodes. 4460 SDOperand BetterChain = FindBetterChain(N, Chain); 4461 4462 // If there is a better chain. 4463 if (Chain != BetterChain) { 4464 // Replace the chain to avoid dependency. 4465 SDOperand ReplStore; 4466 if (ST->isTruncatingStore()) { 4467 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4468 ST->getSrcValue(),ST->getSrcValueOffset(), 4469 ST->getMemoryVT(), 4470 ST->isVolatile(), ST->getAlignment()); 4471 } else { 4472 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4473 ST->getSrcValue(), ST->getSrcValueOffset(), 4474 ST->isVolatile(), ST->getAlignment()); 4475 } 4476 4477 // Create token to keep both nodes around. 4478 SDOperand Token = 4479 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4480 4481 // Don't add users to work list. 4482 return CombineTo(N, Token, false); 4483 } 4484 } 4485 4486 // Try transforming N to an indexed store. 4487 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4488 return SDOperand(N, 0); 4489 4490 // FIXME: is there such a thing as a truncating indexed store? 4491 if (ST->isTruncatingStore() && ST->isUnindexed() && 4492 MVT::isInteger(Value.getValueType())) { 4493 // See if we can simplify the input to this truncstore with knowledge that 4494 // only the low bits are being used. For example: 4495 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4496 SDOperand Shorter = 4497 GetDemandedBits(Value, 4498 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4499 MVT::getSizeInBits(ST->getMemoryVT()))); 4500 AddToWorkList(Value.Val); 4501 if (Shorter.Val) 4502 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4503 ST->getSrcValueOffset(), ST->getMemoryVT(), 4504 ST->isVolatile(), ST->getAlignment()); 4505 4506 // Otherwise, see if we can simplify the operation with 4507 // SimplifyDemandedBits, which only works if the value has a single use. 4508 if (SimplifyDemandedBits(Value, 4509 APInt::getLowBitsSet( 4510 Value.getValueSizeInBits(), 4511 MVT::getSizeInBits(ST->getMemoryVT())))) 4512 return SDOperand(N, 0); 4513 } 4514 4515 // If this is a load followed by a store to the same location, then the store 4516 // is dead/noop. 4517 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4518 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4519 ST->isUnindexed() && !ST->isVolatile() && 4520 // There can't be any side effects between the load and store, such as 4521 // a call or store. 4522 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4523 // The store is dead, remove it. 4524 return Chain; 4525 } 4526 } 4527 4528 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4529 // truncating store. We can do this even if this is already a truncstore. 4530 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4531 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) && 4532 Value.Val->hasOneUse() && ST->isUnindexed() && 4533 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4534 ST->getMemoryVT())) { 4535 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4536 ST->getSrcValueOffset(), ST->getMemoryVT(), 4537 ST->isVolatile(), ST->getAlignment()); 4538 } 4539 4540 return SDOperand(); 4541} 4542 4543SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4544 SDOperand InVec = N->getOperand(0); 4545 SDOperand InVal = N->getOperand(1); 4546 SDOperand EltNo = N->getOperand(2); 4547 4548 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4549 // vector with the inserted element. 4550 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4551 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4552 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4553 if (Elt < Ops.size()) 4554 Ops[Elt] = InVal; 4555 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4556 &Ops[0], Ops.size()); 4557 } 4558 4559 return SDOperand(); 4560} 4561 4562SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4563 SDOperand InVec = N->getOperand(0); 4564 SDOperand EltNo = N->getOperand(1); 4565 4566 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4567 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4568 if (isa<ConstantSDNode>(EltNo)) { 4569 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4570 bool NewLoad = false; 4571 if (Elt == 0) { 4572 MVT::ValueType VT = InVec.getValueType(); 4573 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4574 MVT::ValueType LVT = EVT; 4575 unsigned NumElts = MVT::getVectorNumElements(VT); 4576 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4577 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4578 if (!MVT::isVector(BCVT) || 4579 NumElts != MVT::getVectorNumElements(BCVT)) 4580 return SDOperand(); 4581 InVec = InVec.getOperand(0); 4582 EVT = MVT::getVectorElementType(BCVT); 4583 NewLoad = true; 4584 } 4585 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4586 InVec.getOperand(0).getValueType() == EVT && 4587 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4588 InVec.getOperand(0).hasOneUse()) { 4589 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4590 unsigned Align = LN0->getAlignment(); 4591 if (NewLoad) { 4592 // Check the resultant load doesn't need a higher alignment than the 4593 // original load. 4594 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4595 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4596 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4597 return SDOperand(); 4598 Align = NewAlign; 4599 } 4600 4601 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4602 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4603 LN0->isVolatile(), Align); 4604 } 4605 } 4606 } 4607 return SDOperand(); 4608} 4609 4610 4611SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4612 unsigned NumInScalars = N->getNumOperands(); 4613 MVT::ValueType VT = N->getValueType(0); 4614 unsigned NumElts = MVT::getVectorNumElements(VT); 4615 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4616 4617 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4618 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4619 // at most two distinct vectors, turn this into a shuffle node. 4620 SDOperand VecIn1, VecIn2; 4621 for (unsigned i = 0; i != NumInScalars; ++i) { 4622 // Ignore undef inputs. 4623 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4624 4625 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4626 // constant index, bail out. 4627 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4628 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4629 VecIn1 = VecIn2 = SDOperand(0, 0); 4630 break; 4631 } 4632 4633 // If the input vector type disagrees with the result of the build_vector, 4634 // we can't make a shuffle. 4635 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4636 if (ExtractedFromVec.getValueType() != VT) { 4637 VecIn1 = VecIn2 = SDOperand(0, 0); 4638 break; 4639 } 4640 4641 // Otherwise, remember this. We allow up to two distinct input vectors. 4642 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4643 continue; 4644 4645 if (VecIn1.Val == 0) { 4646 VecIn1 = ExtractedFromVec; 4647 } else if (VecIn2.Val == 0) { 4648 VecIn2 = ExtractedFromVec; 4649 } else { 4650 // Too many inputs. 4651 VecIn1 = VecIn2 = SDOperand(0, 0); 4652 break; 4653 } 4654 } 4655 4656 // If everything is good, we can make a shuffle operation. 4657 if (VecIn1.Val) { 4658 SmallVector<SDOperand, 8> BuildVecIndices; 4659 for (unsigned i = 0; i != NumInScalars; ++i) { 4660 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4661 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4662 continue; 4663 } 4664 4665 SDOperand Extract = N->getOperand(i); 4666 4667 // If extracting from the first vector, just use the index directly. 4668 if (Extract.getOperand(0) == VecIn1) { 4669 BuildVecIndices.push_back(Extract.getOperand(1)); 4670 continue; 4671 } 4672 4673 // Otherwise, use InIdx + VecSize 4674 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4675 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4676 } 4677 4678 // Add count and size info. 4679 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); 4680 4681 // Return the new VECTOR_SHUFFLE node. 4682 SDOperand Ops[5]; 4683 Ops[0] = VecIn1; 4684 if (VecIn2.Val) { 4685 Ops[1] = VecIn2; 4686 } else { 4687 // Use an undef build_vector as input for the second operand. 4688 std::vector<SDOperand> UnOps(NumInScalars, 4689 DAG.getNode(ISD::UNDEF, 4690 EltType)); 4691 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4692 &UnOps[0], UnOps.size()); 4693 AddToWorkList(Ops[1].Val); 4694 } 4695 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4696 &BuildVecIndices[0], BuildVecIndices.size()); 4697 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4698 } 4699 4700 return SDOperand(); 4701} 4702 4703SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4704 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4705 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4706 // inputs come from at most two distinct vectors, turn this into a shuffle 4707 // node. 4708 4709 // If we only have one input vector, we don't need to do any concatenation. 4710 if (N->getNumOperands() == 1) { 4711 return N->getOperand(0); 4712 } 4713 4714 return SDOperand(); 4715} 4716 4717SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4718 SDOperand ShufMask = N->getOperand(2); 4719 unsigned NumElts = ShufMask.getNumOperands(); 4720 4721 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4722 bool isIdentity = true; 4723 for (unsigned i = 0; i != NumElts; ++i) { 4724 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4725 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4726 isIdentity = false; 4727 break; 4728 } 4729 } 4730 if (isIdentity) return N->getOperand(0); 4731 4732 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4733 isIdentity = true; 4734 for (unsigned i = 0; i != NumElts; ++i) { 4735 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4736 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4737 isIdentity = false; 4738 break; 4739 } 4740 } 4741 if (isIdentity) return N->getOperand(1); 4742 4743 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4744 // needed at all. 4745 bool isUnary = true; 4746 bool isSplat = true; 4747 int VecNum = -1; 4748 unsigned BaseIdx = 0; 4749 for (unsigned i = 0; i != NumElts; ++i) 4750 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4751 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4752 int V = (Idx < NumElts) ? 0 : 1; 4753 if (VecNum == -1) { 4754 VecNum = V; 4755 BaseIdx = Idx; 4756 } else { 4757 if (BaseIdx != Idx) 4758 isSplat = false; 4759 if (VecNum != V) { 4760 isUnary = false; 4761 break; 4762 } 4763 } 4764 } 4765 4766 SDOperand N0 = N->getOperand(0); 4767 SDOperand N1 = N->getOperand(1); 4768 // Normalize unary shuffle so the RHS is undef. 4769 if (isUnary && VecNum == 1) 4770 std::swap(N0, N1); 4771 4772 // If it is a splat, check if the argument vector is a build_vector with 4773 // all scalar elements the same. 4774 if (isSplat) { 4775 SDNode *V = N0.Val; 4776 4777 // If this is a bit convert that changes the element type of the vector but 4778 // not the number of vector elements, look through it. Be careful not to 4779 // look though conversions that change things like v4f32 to v2f64. 4780 if (V->getOpcode() == ISD::BIT_CONVERT) { 4781 SDOperand ConvInput = V->getOperand(0); 4782 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4783 V = ConvInput.Val; 4784 } 4785 4786 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4787 unsigned NumElems = V->getNumOperands(); 4788 if (NumElems > BaseIdx) { 4789 SDOperand Base; 4790 bool AllSame = true; 4791 for (unsigned i = 0; i != NumElems; ++i) { 4792 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4793 Base = V->getOperand(i); 4794 break; 4795 } 4796 } 4797 // Splat of <u, u, u, u>, return <u, u, u, u> 4798 if (!Base.Val) 4799 return N0; 4800 for (unsigned i = 0; i != NumElems; ++i) { 4801 if (V->getOperand(i) != Base) { 4802 AllSame = false; 4803 break; 4804 } 4805 } 4806 // Splat of <x, x, x, x>, return <x, x, x, x> 4807 if (AllSame) 4808 return N0; 4809 } 4810 } 4811 } 4812 4813 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4814 // into an undef. 4815 if (isUnary || N0 == N1) { 4816 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4817 // first operand. 4818 SmallVector<SDOperand, 8> MappedOps; 4819 for (unsigned i = 0; i != NumElts; ++i) { 4820 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4821 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4822 MappedOps.push_back(ShufMask.getOperand(i)); 4823 } else { 4824 unsigned NewIdx = 4825 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4826 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4827 } 4828 } 4829 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4830 &MappedOps[0], MappedOps.size()); 4831 AddToWorkList(ShufMask.Val); 4832 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4833 N0, 4834 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4835 ShufMask); 4836 } 4837 4838 return SDOperand(); 4839} 4840 4841/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4842/// an AND to a vector_shuffle with the destination vector and a zero vector. 4843/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4844/// vector_shuffle V, Zero, <0, 4, 2, 4> 4845SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4846 SDOperand LHS = N->getOperand(0); 4847 SDOperand RHS = N->getOperand(1); 4848 if (N->getOpcode() == ISD::AND) { 4849 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4850 RHS = RHS.getOperand(0); 4851 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4852 std::vector<SDOperand> IdxOps; 4853 unsigned NumOps = RHS.getNumOperands(); 4854 unsigned NumElts = NumOps; 4855 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4856 for (unsigned i = 0; i != NumElts; ++i) { 4857 SDOperand Elt = RHS.getOperand(i); 4858 if (!isa<ConstantSDNode>(Elt)) 4859 return SDOperand(); 4860 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4861 IdxOps.push_back(DAG.getConstant(i, EVT)); 4862 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4863 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4864 else 4865 return SDOperand(); 4866 } 4867 4868 // Let's see if the target supports this vector_shuffle. 4869 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4870 return SDOperand(); 4871 4872 // Return the new VECTOR_SHUFFLE node. 4873 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4874 std::vector<SDOperand> Ops; 4875 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4876 Ops.push_back(LHS); 4877 AddToWorkList(LHS.Val); 4878 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4879 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4880 &ZeroOps[0], ZeroOps.size())); 4881 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4882 &IdxOps[0], IdxOps.size())); 4883 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4884 &Ops[0], Ops.size()); 4885 if (VT != LHS.getValueType()) { 4886 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4887 } 4888 return Result; 4889 } 4890 } 4891 return SDOperand(); 4892} 4893 4894/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4895SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4896 // After legalize, the target may be depending on adds and other 4897 // binary ops to provide legal ways to construct constants or other 4898 // things. Simplifying them may result in a loss of legality. 4899 if (AfterLegalize) return SDOperand(); 4900 4901 MVT::ValueType VT = N->getValueType(0); 4902 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4903 4904 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4905 SDOperand LHS = N->getOperand(0); 4906 SDOperand RHS = N->getOperand(1); 4907 SDOperand Shuffle = XformToShuffleWithZero(N); 4908 if (Shuffle.Val) return Shuffle; 4909 4910 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4911 // this operation. 4912 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4913 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4914 SmallVector<SDOperand, 8> Ops; 4915 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4916 SDOperand LHSOp = LHS.getOperand(i); 4917 SDOperand RHSOp = RHS.getOperand(i); 4918 // If these two elements can't be folded, bail out. 4919 if ((LHSOp.getOpcode() != ISD::UNDEF && 4920 LHSOp.getOpcode() != ISD::Constant && 4921 LHSOp.getOpcode() != ISD::ConstantFP) || 4922 (RHSOp.getOpcode() != ISD::UNDEF && 4923 RHSOp.getOpcode() != ISD::Constant && 4924 RHSOp.getOpcode() != ISD::ConstantFP)) 4925 break; 4926 // Can't fold divide by zero. 4927 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4928 N->getOpcode() == ISD::FDIV) { 4929 if ((RHSOp.getOpcode() == ISD::Constant && 4930 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4931 (RHSOp.getOpcode() == ISD::ConstantFP && 4932 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4933 break; 4934 } 4935 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4936 AddToWorkList(Ops.back().Val); 4937 assert((Ops.back().getOpcode() == ISD::UNDEF || 4938 Ops.back().getOpcode() == ISD::Constant || 4939 Ops.back().getOpcode() == ISD::ConstantFP) && 4940 "Scalar binop didn't fold!"); 4941 } 4942 4943 if (Ops.size() == LHS.getNumOperands()) { 4944 MVT::ValueType VT = LHS.getValueType(); 4945 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4946 } 4947 } 4948 4949 return SDOperand(); 4950} 4951 4952SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4953 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4954 4955 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4956 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4957 // If we got a simplified select_cc node back from SimplifySelectCC, then 4958 // break it down into a new SETCC node, and a new SELECT node, and then return 4959 // the SELECT node, since we were called with a SELECT node. 4960 if (SCC.Val) { 4961 // Check to see if we got a select_cc back (to turn into setcc/select). 4962 // Otherwise, just return whatever node we got back, like fabs. 4963 if (SCC.getOpcode() == ISD::SELECT_CC) { 4964 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4965 SCC.getOperand(0), SCC.getOperand(1), 4966 SCC.getOperand(4)); 4967 AddToWorkList(SETCC.Val); 4968 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4969 SCC.getOperand(3), SETCC); 4970 } 4971 return SCC; 4972 } 4973 return SDOperand(); 4974} 4975 4976/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4977/// are the two values being selected between, see if we can simplify the 4978/// select. Callers of this should assume that TheSelect is deleted if this 4979/// returns true. As such, they should return the appropriate thing (e.g. the 4980/// node) back to the top-level of the DAG combiner loop to avoid it being 4981/// looked at. 4982/// 4983bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4984 SDOperand RHS) { 4985 4986 // If this is a select from two identical things, try to pull the operation 4987 // through the select. 4988 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4989 // If this is a load and the token chain is identical, replace the select 4990 // of two loads with a load through a select of the address to load from. 4991 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4992 // constants have been dropped into the constant pool. 4993 if (LHS.getOpcode() == ISD::LOAD && 4994 // Token chains must be identical. 4995 LHS.getOperand(0) == RHS.getOperand(0)) { 4996 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4997 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4998 4999 // If this is an EXTLOAD, the VT's must match. 5000 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5001 // FIXME: this conflates two src values, discarding one. This is not 5002 // the right thing to do, but nothing uses srcvalues now. When they do, 5003 // turn SrcValue into a list of locations. 5004 SDOperand Addr; 5005 if (TheSelect->getOpcode() == ISD::SELECT) { 5006 // Check that the condition doesn't reach either load. If so, folding 5007 // this will induce a cycle into the DAG. 5008 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 5009 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 5010 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5011 TheSelect->getOperand(0), LLD->getBasePtr(), 5012 RLD->getBasePtr()); 5013 } 5014 } else { 5015 // Check that the condition doesn't reach either load. If so, folding 5016 // this will induce a cycle into the DAG. 5017 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 5018 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 5019 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 5020 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 5021 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5022 TheSelect->getOperand(0), 5023 TheSelect->getOperand(1), 5024 LLD->getBasePtr(), RLD->getBasePtr(), 5025 TheSelect->getOperand(4)); 5026 } 5027 } 5028 5029 if (Addr.Val) { 5030 SDOperand Load; 5031 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5032 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5033 Addr,LLD->getSrcValue(), 5034 LLD->getSrcValueOffset(), 5035 LLD->isVolatile(), 5036 LLD->getAlignment()); 5037 else { 5038 Load = DAG.getExtLoad(LLD->getExtensionType(), 5039 TheSelect->getValueType(0), 5040 LLD->getChain(), Addr, LLD->getSrcValue(), 5041 LLD->getSrcValueOffset(), 5042 LLD->getMemoryVT(), 5043 LLD->isVolatile(), 5044 LLD->getAlignment()); 5045 } 5046 // Users of the select now use the result of the load. 5047 CombineTo(TheSelect, Load); 5048 5049 // Users of the old loads now use the new load's chain. We know the 5050 // old-load value is dead now. 5051 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 5052 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 5053 return true; 5054 } 5055 } 5056 } 5057 } 5058 5059 return false; 5060} 5061 5062SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 5063 SDOperand N2, SDOperand N3, 5064 ISD::CondCode CC, bool NotExtCompare) { 5065 5066 MVT::ValueType VT = N2.getValueType(); 5067 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5068 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5069 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5070 5071 // Determine if the condition we're dealing with is constant 5072 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 5073 if (SCC.Val) AddToWorkList(SCC.Val); 5074 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5075 5076 // fold select_cc true, x, y -> x 5077 if (SCCC && SCCC->getValue()) 5078 return N2; 5079 // fold select_cc false, x, y -> y 5080 if (SCCC && SCCC->getValue() == 0) 5081 return N3; 5082 5083 // Check to see if we can simplify the select into an fabs node 5084 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5085 // Allow either -0.0 or 0.0 5086 if (CFP->getValueAPF().isZero()) { 5087 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5088 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5089 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5090 N2 == N3.getOperand(0)) 5091 return DAG.getNode(ISD::FABS, VT, N0); 5092 5093 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5094 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5095 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5096 N2.getOperand(0) == N3) 5097 return DAG.getNode(ISD::FABS, VT, N3); 5098 } 5099 } 5100 5101 // Check to see if we can perform the "gzip trick", transforming 5102 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5103 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5104 MVT::isInteger(N0.getValueType()) && 5105 MVT::isInteger(N2.getValueType()) && 5106 (N1C->isNullValue() || // (a < 0) ? b : 0 5107 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5108 MVT::ValueType XType = N0.getValueType(); 5109 MVT::ValueType AType = N2.getValueType(); 5110 if (XType >= AType) { 5111 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5112 // single-bit constant. 5113 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 5114 unsigned ShCtV = Log2_64(N2C->getValue()); 5115 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 5116 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5117 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5118 AddToWorkList(Shift.Val); 5119 if (XType > AType) { 5120 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5121 AddToWorkList(Shift.Val); 5122 } 5123 return DAG.getNode(ISD::AND, AType, Shift, N2); 5124 } 5125 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5126 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5127 TLI.getShiftAmountTy())); 5128 AddToWorkList(Shift.Val); 5129 if (XType > AType) { 5130 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5131 AddToWorkList(Shift.Val); 5132 } 5133 return DAG.getNode(ISD::AND, AType, Shift, N2); 5134 } 5135 } 5136 5137 // fold select C, 16, 0 -> shl C, 4 5138 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 5139 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5140 5141 // If the caller doesn't want us to simplify this into a zext of a compare, 5142 // don't do it. 5143 if (NotExtCompare && N2C->getValue() == 1) 5144 return SDOperand(); 5145 5146 // Get a SetCC of the condition 5147 // FIXME: Should probably make sure that setcc is legal if we ever have a 5148 // target where it isn't. 5149 SDOperand Temp, SCC; 5150 // cast from setcc result type to select result type 5151 if (AfterLegalize) { 5152 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 5153 if (N2.getValueType() < SCC.getValueType()) 5154 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5155 else 5156 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5157 } else { 5158 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5159 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5160 } 5161 AddToWorkList(SCC.Val); 5162 AddToWorkList(Temp.Val); 5163 5164 if (N2C->getValue() == 1) 5165 return Temp; 5166 // shl setcc result by log2 n2c 5167 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5168 DAG.getConstant(Log2_64(N2C->getValue()), 5169 TLI.getShiftAmountTy())); 5170 } 5171 5172 // Check to see if this is the equivalent of setcc 5173 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5174 // otherwise, go ahead with the folds. 5175 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 5176 MVT::ValueType XType = N0.getValueType(); 5177 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 5178 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 5179 if (Res.getValueType() != VT) 5180 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5181 return Res; 5182 } 5183 5184 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5185 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5186 TLI.isOperationLegal(ISD::CTLZ, XType)) { 5187 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5188 return DAG.getNode(ISD::SRL, XType, Ctlz, 5189 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 5190 TLI.getShiftAmountTy())); 5191 } 5192 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5193 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5194 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5195 N0); 5196 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5197 DAG.getConstant(~0ULL, XType)); 5198 return DAG.getNode(ISD::SRL, XType, 5199 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5200 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5201 TLI.getShiftAmountTy())); 5202 } 5203 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5204 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5205 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5206 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5207 TLI.getShiftAmountTy())); 5208 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5209 } 5210 } 5211 5212 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5213 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5214 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5215 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5216 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 5217 MVT::ValueType XType = N0.getValueType(); 5218 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5219 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5220 TLI.getShiftAmountTy())); 5221 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5222 AddToWorkList(Shift.Val); 5223 AddToWorkList(Add.Val); 5224 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5225 } 5226 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5227 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5228 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5229 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5230 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5231 MVT::ValueType XType = N0.getValueType(); 5232 if (SubC->isNullValue() && MVT::isInteger(XType)) { 5233 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5234 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5235 TLI.getShiftAmountTy())); 5236 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5237 AddToWorkList(Shift.Val); 5238 AddToWorkList(Add.Val); 5239 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5240 } 5241 } 5242 } 5243 5244 return SDOperand(); 5245} 5246 5247/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5248SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 5249 SDOperand N1, ISD::CondCode Cond, 5250 bool foldBooleans) { 5251 TargetLowering::DAGCombinerInfo 5252 DagCombineInfo(DAG, !AfterLegalize, false, this); 5253 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5254} 5255 5256/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5257/// return a DAG expression to select that will generate the same value by 5258/// multiplying by a magic number. See: 5259/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5260SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5261 std::vector<SDNode*> Built; 5262 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5263 5264 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5265 ii != ee; ++ii) 5266 AddToWorkList(*ii); 5267 return S; 5268} 5269 5270/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5271/// return a DAG expression to select that will generate the same value by 5272/// multiplying by a magic number. See: 5273/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5274SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5275 std::vector<SDNode*> Built; 5276 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5277 5278 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5279 ii != ee; ++ii) 5280 AddToWorkList(*ii); 5281 return S; 5282} 5283 5284/// FindBaseOffset - Return true if base is known not to alias with anything 5285/// but itself. Provides base object and offset as results. 5286static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5287 // Assume it is a primitive operation. 5288 Base = Ptr; Offset = 0; 5289 5290 // If it's an adding a simple constant then integrate the offset. 5291 if (Base.getOpcode() == ISD::ADD) { 5292 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5293 Base = Base.getOperand(0); 5294 Offset += C->getValue(); 5295 } 5296 } 5297 5298 // If it's any of the following then it can't alias with anything but itself. 5299 return isa<FrameIndexSDNode>(Base) || 5300 isa<ConstantPoolSDNode>(Base) || 5301 isa<GlobalAddressSDNode>(Base); 5302} 5303 5304/// isAlias - Return true if there is any possibility that the two addresses 5305/// overlap. 5306bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5307 const Value *SrcValue1, int SrcValueOffset1, 5308 SDOperand Ptr2, int64_t Size2, 5309 const Value *SrcValue2, int SrcValueOffset2) 5310{ 5311 // If they are the same then they must be aliases. 5312 if (Ptr1 == Ptr2) return true; 5313 5314 // Gather base node and offset information. 5315 SDOperand Base1, Base2; 5316 int64_t Offset1, Offset2; 5317 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5318 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5319 5320 // If they have a same base address then... 5321 if (Base1 == Base2) { 5322 // Check to see if the addresses overlap. 5323 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5324 } 5325 5326 // If we know both bases then they can't alias. 5327 if (KnownBase1 && KnownBase2) return false; 5328 5329 if (CombinerGlobalAA) { 5330 // Use alias analysis information. 5331 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5332 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5333 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5334 AliasAnalysis::AliasResult AAResult = 5335 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5336 if (AAResult == AliasAnalysis::NoAlias) 5337 return false; 5338 } 5339 5340 // Otherwise we have to assume they alias. 5341 return true; 5342} 5343 5344/// FindAliasInfo - Extracts the relevant alias information from the memory 5345/// node. Returns true if the operand was a load. 5346bool DAGCombiner::FindAliasInfo(SDNode *N, 5347 SDOperand &Ptr, int64_t &Size, 5348 const Value *&SrcValue, int &SrcValueOffset) { 5349 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5350 Ptr = LD->getBasePtr(); 5351 Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3; 5352 SrcValue = LD->getSrcValue(); 5353 SrcValueOffset = LD->getSrcValueOffset(); 5354 return true; 5355 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5356 Ptr = ST->getBasePtr(); 5357 Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3; 5358 SrcValue = ST->getSrcValue(); 5359 SrcValueOffset = ST->getSrcValueOffset(); 5360 } else { 5361 assert(0 && "FindAliasInfo expected a memory operand"); 5362 } 5363 5364 return false; 5365} 5366 5367/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5368/// looking for aliasing nodes and adding them to the Aliases vector. 5369void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5370 SmallVector<SDOperand, 8> &Aliases) { 5371 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5372 std::set<SDNode *> Visited; // Visited node set. 5373 5374 // Get alias information for node. 5375 SDOperand Ptr; 5376 int64_t Size; 5377 const Value *SrcValue; 5378 int SrcValueOffset; 5379 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5380 5381 // Starting off. 5382 Chains.push_back(OriginalChain); 5383 5384 // Look at each chain and determine if it is an alias. If so, add it to the 5385 // aliases list. If not, then continue up the chain looking for the next 5386 // candidate. 5387 while (!Chains.empty()) { 5388 SDOperand Chain = Chains.back(); 5389 Chains.pop_back(); 5390 5391 // Don't bother if we've been before. 5392 if (Visited.find(Chain.Val) != Visited.end()) continue; 5393 Visited.insert(Chain.Val); 5394 5395 switch (Chain.getOpcode()) { 5396 case ISD::EntryToken: 5397 // Entry token is ideal chain operand, but handled in FindBetterChain. 5398 break; 5399 5400 case ISD::LOAD: 5401 case ISD::STORE: { 5402 // Get alias information for Chain. 5403 SDOperand OpPtr; 5404 int64_t OpSize; 5405 const Value *OpSrcValue; 5406 int OpSrcValueOffset; 5407 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5408 OpSrcValue, OpSrcValueOffset); 5409 5410 // If chain is alias then stop here. 5411 if (!(IsLoad && IsOpLoad) && 5412 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5413 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5414 Aliases.push_back(Chain); 5415 } else { 5416 // Look further up the chain. 5417 Chains.push_back(Chain.getOperand(0)); 5418 // Clean up old chain. 5419 AddToWorkList(Chain.Val); 5420 } 5421 break; 5422 } 5423 5424 case ISD::TokenFactor: 5425 // We have to check each of the operands of the token factor, so we queue 5426 // then up. Adding the operands to the queue (stack) in reverse order 5427 // maintains the original order and increases the likelihood that getNode 5428 // will find a matching token factor (CSE.) 5429 for (unsigned n = Chain.getNumOperands(); n;) 5430 Chains.push_back(Chain.getOperand(--n)); 5431 // Eliminate the token factor if we can. 5432 AddToWorkList(Chain.Val); 5433 break; 5434 5435 default: 5436 // For all other instructions we will just have to take what we can get. 5437 Aliases.push_back(Chain); 5438 break; 5439 } 5440 } 5441} 5442 5443/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5444/// for a better chain (aliasing node.) 5445SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5446 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5447 5448 // Accumulate all the aliases to this node. 5449 GatherAllAliases(N, OldChain, Aliases); 5450 5451 if (Aliases.size() == 0) { 5452 // If no operands then chain to entry token. 5453 return DAG.getEntryNode(); 5454 } else if (Aliases.size() == 1) { 5455 // If a single operand then chain to it. We don't need to revisit it. 5456 return Aliases[0]; 5457 } 5458 5459 // Construct a custom tailored token factor. 5460 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5461 &Aliases[0], Aliases.size()); 5462 5463 // Make sure the old chain gets cleaned up. 5464 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5465 5466 return NewChain; 5467} 5468 5469// SelectionDAG::Combine - This is the entry point for the file. 5470// 5471void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5472 if (!RunningAfterLegalize && ViewDAGCombine1) 5473 viewGraph(); 5474 if (RunningAfterLegalize && ViewDAGCombine2) 5475 viewGraph(); 5476 /// run - This is the main entry point to this class. 5477 /// 5478 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5479} 5480