DAGCombiner.cpp revision 1e3362f68ef7d05aa31fc8865291cd834add1cc6
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32using namespace llvm; 33 34STATISTIC(NodesCombined , "Number of dag nodes combined"); 35STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 36STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 37 38namespace { 39#ifndef NDEBUG 40 static cl::opt<bool> 41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 42 cl::desc("Pop up a window to show dags before the first " 43 "dag combine pass")); 44 static cl::opt<bool> 45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 46 cl::desc("Pop up a window to show dags before the second " 47 "dag combine pass")); 48#else 49 static const bool ViewDAGCombine1 = false; 50 static const bool ViewDAGCombine2 = false; 51#endif 52 53 static cl::opt<bool> 54 CombinerAA("combiner-alias-analysis", cl::Hidden, 55 cl::desc("Turn on alias analysis during testing")); 56 57 static cl::opt<bool> 58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 59 cl::desc("Include global information in alias analysis")); 60 61//------------------------------ DAGCombiner ---------------------------------// 62 63 class VISIBILITY_HIDDEN DAGCombiner { 64 SelectionDAG &DAG; 65 TargetLowering &TLI; 66 bool AfterLegalize; 67 68 // Worklist of all of the nodes that need to be simplified. 69 std::vector<SDNode*> WorkList; 70 71 // AA - Used for DAG load/store alias analysis. 72 AliasAnalysis &AA; 73 74 /// AddUsersToWorkList - When an instruction is simplified, add all users of 75 /// the instruction to the work lists because they might get more simplified 76 /// now. 77 /// 78 void AddUsersToWorkList(SDNode *N) { 79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 80 UI != UE; ++UI) 81 AddToWorkList(*UI); 82 } 83 84 /// removeFromWorkList - remove all instances of N from the worklist. 85 /// 86 void removeFromWorkList(SDNode *N) { 87 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 88 WorkList.end()); 89 } 90 91 /// visit - call the node-specific routine that knows how to fold each 92 /// particular type of node. 93 SDOperand visit(SDNode *N); 94 95 public: 96 /// AddToWorkList - Add to the work list making sure it's instance is at the 97 /// the back (next to be processed.) 98 void AddToWorkList(SDNode *N) { 99 removeFromWorkList(N); 100 WorkList.push_back(N); 101 } 102 103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 104 bool AddTo = true) { 105 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 106 ++NodesCombined; 107 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 108 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 109 DOUT << " and " << NumTo-1 << " other values\n"; 110 std::vector<SDNode*> NowDead; 111 DAG.ReplaceAllUsesWith(N, To, &NowDead); 112 113 if (AddTo) { 114 // Push the new nodes and any users onto the worklist 115 for (unsigned i = 0, e = NumTo; i != e; ++i) { 116 AddToWorkList(To[i].Val); 117 AddUsersToWorkList(To[i].Val); 118 } 119 } 120 121 // Nodes can be reintroduced into the worklist. Make sure we do not 122 // process a node that has been replaced. 123 removeFromWorkList(N); 124 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 125 removeFromWorkList(NowDead[i]); 126 127 // Finally, since the node is now dead, remove it from the graph. 128 DAG.DeleteNode(N); 129 return SDOperand(N, 0); 130 } 131 132 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 133 return CombineTo(N, &Res, 1, AddTo); 134 } 135 136 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 137 bool AddTo = true) { 138 SDOperand To[] = { Res0, Res1 }; 139 return CombineTo(N, To, 2, AddTo); 140 } 141 142 private: 143 144 /// SimplifyDemandedBits - Check the specified integer node value to see if 145 /// it can be simplified or if things it uses can be simplified by bit 146 /// propagation. If so, return true. 147 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) { 148 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 149 uint64_t KnownZero, KnownOne; 150 Demanded &= MVT::getIntVTBitMask(Op.getValueType()); 151 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 152 return false; 153 154 // Revisit the node. 155 AddToWorkList(Op.Val); 156 157 // Replace the old value with the new one. 158 ++NodesCombined; 159 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 160 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 161 DOUT << '\n'; 162 163 std::vector<SDNode*> NowDead; 164 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead); 165 166 // Push the new node and any (possibly new) users onto the worklist. 167 AddToWorkList(TLO.New.Val); 168 AddUsersToWorkList(TLO.New.Val); 169 170 // Nodes can end up on the worklist more than once. Make sure we do 171 // not process a node that has been replaced. 172 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 173 removeFromWorkList(NowDead[i]); 174 175 // Finally, if the node is now dead, remove it from the graph. The node 176 // may not be dead if the replacement process recursively simplified to 177 // something else needing this node. 178 if (TLO.Old.Val->use_empty()) { 179 removeFromWorkList(TLO.Old.Val); 180 181 // If the operands of this node are only used by the node, they will now 182 // be dead. Make sure to visit them first to delete dead nodes early. 183 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 184 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 185 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 186 187 DAG.DeleteNode(TLO.Old.Val); 188 } 189 return true; 190 } 191 192 bool CombineToPreIndexedLoadStore(SDNode *N); 193 bool CombineToPostIndexedLoadStore(SDNode *N); 194 195 196 /// combine - call the node-specific routine that knows how to fold each 197 /// particular type of node. If that doesn't do anything, try the 198 /// target-specific DAG combines. 199 SDOperand combine(SDNode *N); 200 201 // Visitation implementation - Implement dag node combining for different 202 // node types. The semantics are as follows: 203 // Return Value: 204 // SDOperand.Val == 0 - No change was made 205 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 206 // otherwise - N should be replaced by the returned Operand. 207 // 208 SDOperand visitTokenFactor(SDNode *N); 209 SDOperand visitADD(SDNode *N); 210 SDOperand visitSUB(SDNode *N); 211 SDOperand visitADDC(SDNode *N); 212 SDOperand visitADDE(SDNode *N); 213 SDOperand visitMUL(SDNode *N); 214 SDOperand visitSDIV(SDNode *N); 215 SDOperand visitUDIV(SDNode *N); 216 SDOperand visitSREM(SDNode *N); 217 SDOperand visitUREM(SDNode *N); 218 SDOperand visitMULHU(SDNode *N); 219 SDOperand visitMULHS(SDNode *N); 220 SDOperand visitSMUL_LOHI(SDNode *N); 221 SDOperand visitUMUL_LOHI(SDNode *N); 222 SDOperand visitSDIVREM(SDNode *N); 223 SDOperand visitUDIVREM(SDNode *N); 224 SDOperand visitAND(SDNode *N); 225 SDOperand visitOR(SDNode *N); 226 SDOperand visitXOR(SDNode *N); 227 SDOperand SimplifyVBinOp(SDNode *N); 228 SDOperand visitSHL(SDNode *N); 229 SDOperand visitSRA(SDNode *N); 230 SDOperand visitSRL(SDNode *N); 231 SDOperand visitCTLZ(SDNode *N); 232 SDOperand visitCTTZ(SDNode *N); 233 SDOperand visitCTPOP(SDNode *N); 234 SDOperand visitSELECT(SDNode *N); 235 SDOperand visitSELECT_CC(SDNode *N); 236 SDOperand visitSETCC(SDNode *N); 237 SDOperand visitSIGN_EXTEND(SDNode *N); 238 SDOperand visitZERO_EXTEND(SDNode *N); 239 SDOperand visitANY_EXTEND(SDNode *N); 240 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 241 SDOperand visitTRUNCATE(SDNode *N); 242 SDOperand visitBIT_CONVERT(SDNode *N); 243 SDOperand visitFADD(SDNode *N); 244 SDOperand visitFSUB(SDNode *N); 245 SDOperand visitFMUL(SDNode *N); 246 SDOperand visitFDIV(SDNode *N); 247 SDOperand visitFREM(SDNode *N); 248 SDOperand visitFCOPYSIGN(SDNode *N); 249 SDOperand visitSINT_TO_FP(SDNode *N); 250 SDOperand visitUINT_TO_FP(SDNode *N); 251 SDOperand visitFP_TO_SINT(SDNode *N); 252 SDOperand visitFP_TO_UINT(SDNode *N); 253 SDOperand visitFP_ROUND(SDNode *N); 254 SDOperand visitFP_ROUND_INREG(SDNode *N); 255 SDOperand visitFP_EXTEND(SDNode *N); 256 SDOperand visitFNEG(SDNode *N); 257 SDOperand visitFABS(SDNode *N); 258 SDOperand visitBRCOND(SDNode *N); 259 SDOperand visitBR_CC(SDNode *N); 260 SDOperand visitLOAD(SDNode *N); 261 SDOperand visitSTORE(SDNode *N); 262 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 263 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 264 SDOperand visitBUILD_VECTOR(SDNode *N); 265 SDOperand visitCONCAT_VECTORS(SDNode *N); 266 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 267 268 SDOperand XformToShuffleWithZero(SDNode *N); 269 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 270 271 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 272 273 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 274 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 275 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 276 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 277 SDOperand N3, ISD::CondCode CC, 278 bool NotExtCompare = false); 279 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 280 ISD::CondCode Cond, bool foldBooleans = true); 281 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 282 unsigned HiOp); 283 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 284 SDOperand BuildSDIV(SDNode *N); 285 SDOperand BuildUDIV(SDNode *N); 286 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 287 SDOperand ReduceLoadWidth(SDNode *N); 288 289 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask); 290 291 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 292 /// looking for aliasing nodes and adding them to the Aliases vector. 293 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 294 SmallVector<SDOperand, 8> &Aliases); 295 296 /// isAlias - Return true if there is any possibility that the two addresses 297 /// overlap. 298 bool isAlias(SDOperand Ptr1, int64_t Size1, 299 const Value *SrcValue1, int SrcValueOffset1, 300 SDOperand Ptr2, int64_t Size2, 301 const Value *SrcValue2, int SrcValueOffset2); 302 303 /// FindAliasInfo - Extracts the relevant alias information from the memory 304 /// node. Returns true if the operand was a load. 305 bool FindAliasInfo(SDNode *N, 306 SDOperand &Ptr, int64_t &Size, 307 const Value *&SrcValue, int &SrcValueOffset); 308 309 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 310 /// looking for a better chain (aliasing node.) 311 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 312 313public: 314 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 315 : DAG(D), 316 TLI(D.getTargetLoweringInfo()), 317 AfterLegalize(false), 318 AA(A) {} 319 320 /// Run - runs the dag combiner on all nodes in the work list 321 void Run(bool RunningAfterLegalize); 322 }; 323} 324 325//===----------------------------------------------------------------------===// 326// TargetLowering::DAGCombinerInfo implementation 327//===----------------------------------------------------------------------===// 328 329void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 330 ((DAGCombiner*)DC)->AddToWorkList(N); 331} 332 333SDOperand TargetLowering::DAGCombinerInfo:: 334CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 335 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 336} 337 338SDOperand TargetLowering::DAGCombinerInfo:: 339CombineTo(SDNode *N, SDOperand Res) { 340 return ((DAGCombiner*)DC)->CombineTo(N, Res); 341} 342 343 344SDOperand TargetLowering::DAGCombinerInfo:: 345CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 346 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 347} 348 349 350//===----------------------------------------------------------------------===// 351// Helper Functions 352//===----------------------------------------------------------------------===// 353 354/// isNegatibleForFree - Return 1 if we can compute the negated form of the 355/// specified expression for the same cost as the expression itself, or 2 if we 356/// can compute the negated form more cheaply than the expression itself. 357static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 358 // No compile time optimizations on this type. 359 if (Op.getValueType() == MVT::ppcf128) 360 return 0; 361 362 // fneg is removable even if it has multiple uses. 363 if (Op.getOpcode() == ISD::FNEG) return 2; 364 365 // Don't allow anything with multiple uses. 366 if (!Op.hasOneUse()) return 0; 367 368 // Don't recurse exponentially. 369 if (Depth > 6) return 0; 370 371 switch (Op.getOpcode()) { 372 default: return false; 373 case ISD::ConstantFP: 374 return 1; 375 case ISD::FADD: 376 // FIXME: determine better conditions for this xform. 377 if (!UnsafeFPMath) return 0; 378 379 // -(A+B) -> -A - B 380 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 381 return V; 382 // -(A+B) -> -B - A 383 return isNegatibleForFree(Op.getOperand(1), Depth+1); 384 case ISD::FSUB: 385 // We can't turn -(A-B) into B-A when we honor signed zeros. 386 if (!UnsafeFPMath) return 0; 387 388 // -(A-B) -> B-A 389 return 1; 390 391 case ISD::FMUL: 392 case ISD::FDIV: 393 if (HonorSignDependentRoundingFPMath()) return 0; 394 395 // -(X*Y) -> (-X * Y) or (X*-Y) 396 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 397 return V; 398 399 return isNegatibleForFree(Op.getOperand(1), Depth+1); 400 401 case ISD::FP_EXTEND: 402 case ISD::FP_ROUND: 403 case ISD::FSIN: 404 return isNegatibleForFree(Op.getOperand(0), Depth+1); 405 } 406} 407 408/// GetNegatedExpression - If isNegatibleForFree returns true, this function 409/// returns the newly negated expression. 410static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 411 unsigned Depth = 0) { 412 // fneg is removable even if it has multiple uses. 413 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 414 415 // Don't allow anything with multiple uses. 416 assert(Op.hasOneUse() && "Unknown reuse!"); 417 418 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 419 switch (Op.getOpcode()) { 420 default: assert(0 && "Unknown code"); 421 case ISD::ConstantFP: { 422 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 423 V.changeSign(); 424 return DAG.getConstantFP(V, Op.getValueType()); 425 } 426 case ISD::FADD: 427 // FIXME: determine better conditions for this xform. 428 assert(UnsafeFPMath); 429 430 // -(A+B) -> -A - B 431 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 432 return DAG.getNode(ISD::FSUB, Op.getValueType(), 433 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 434 Op.getOperand(1)); 435 // -(A+B) -> -B - A 436 return DAG.getNode(ISD::FSUB, Op.getValueType(), 437 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 438 Op.getOperand(0)); 439 case ISD::FSUB: 440 // We can't turn -(A-B) into B-A when we honor signed zeros. 441 assert(UnsafeFPMath); 442 443 // -(0-B) -> B 444 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 445 if (N0CFP->getValueAPF().isZero()) 446 return Op.getOperand(1); 447 448 // -(A-B) -> B-A 449 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 450 Op.getOperand(0)); 451 452 case ISD::FMUL: 453 case ISD::FDIV: 454 assert(!HonorSignDependentRoundingFPMath()); 455 456 // -(X*Y) -> -X * Y 457 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 458 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 459 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 460 Op.getOperand(1)); 461 462 // -(X*Y) -> X * -Y 463 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 464 Op.getOperand(0), 465 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 466 467 case ISD::FP_EXTEND: 468 case ISD::FSIN: 469 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 470 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 471 case ISD::FP_ROUND: 472 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 473 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 474 Op.getOperand(1)); 475 } 476} 477 478 479// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 480// that selects between the values 1 and 0, making it equivalent to a setcc. 481// Also, set the incoming LHS, RHS, and CC references to the appropriate 482// nodes based on the type of node we are checking. This simplifies life a 483// bit for the callers. 484static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 485 SDOperand &CC) { 486 if (N.getOpcode() == ISD::SETCC) { 487 LHS = N.getOperand(0); 488 RHS = N.getOperand(1); 489 CC = N.getOperand(2); 490 return true; 491 } 492 if (N.getOpcode() == ISD::SELECT_CC && 493 N.getOperand(2).getOpcode() == ISD::Constant && 494 N.getOperand(3).getOpcode() == ISD::Constant && 495 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 496 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 497 LHS = N.getOperand(0); 498 RHS = N.getOperand(1); 499 CC = N.getOperand(4); 500 return true; 501 } 502 return false; 503} 504 505// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 506// one use. If this is true, it allows the users to invert the operation for 507// free when it is profitable to do so. 508static bool isOneUseSetCC(SDOperand N) { 509 SDOperand N0, N1, N2; 510 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 511 return true; 512 return false; 513} 514 515SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 516 MVT::ValueType VT = N0.getValueType(); 517 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 518 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 519 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 520 if (isa<ConstantSDNode>(N1)) { 521 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 522 AddToWorkList(OpNode.Val); 523 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 524 } else if (N0.hasOneUse()) { 525 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 526 AddToWorkList(OpNode.Val); 527 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 528 } 529 } 530 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 531 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 532 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 533 if (isa<ConstantSDNode>(N0)) { 534 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 535 AddToWorkList(OpNode.Val); 536 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 537 } else if (N1.hasOneUse()) { 538 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 539 AddToWorkList(OpNode.Val); 540 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 541 } 542 } 543 return SDOperand(); 544} 545 546//===----------------------------------------------------------------------===// 547// Main DAG Combiner implementation 548//===----------------------------------------------------------------------===// 549 550void DAGCombiner::Run(bool RunningAfterLegalize) { 551 // set the instance variable, so that the various visit routines may use it. 552 AfterLegalize = RunningAfterLegalize; 553 554 // Add all the dag nodes to the worklist. 555 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 556 E = DAG.allnodes_end(); I != E; ++I) 557 WorkList.push_back(I); 558 559 // Create a dummy node (which is not added to allnodes), that adds a reference 560 // to the root node, preventing it from being deleted, and tracking any 561 // changes of the root. 562 HandleSDNode Dummy(DAG.getRoot()); 563 564 // The root of the dag may dangle to deleted nodes until the dag combiner is 565 // done. Set it to null to avoid confusion. 566 DAG.setRoot(SDOperand()); 567 568 // while the worklist isn't empty, inspect the node on the end of it and 569 // try and combine it. 570 while (!WorkList.empty()) { 571 SDNode *N = WorkList.back(); 572 WorkList.pop_back(); 573 574 // If N has no uses, it is dead. Make sure to revisit all N's operands once 575 // N is deleted from the DAG, since they too may now be dead or may have a 576 // reduced number of uses, allowing other xforms. 577 if (N->use_empty() && N != &Dummy) { 578 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 579 AddToWorkList(N->getOperand(i).Val); 580 581 DAG.DeleteNode(N); 582 continue; 583 } 584 585 SDOperand RV = combine(N); 586 587 if (RV.Val == 0) 588 continue; 589 590 ++NodesCombined; 591 592 // If we get back the same node we passed in, rather than a new node or 593 // zero, we know that the node must have defined multiple values and 594 // CombineTo was used. Since CombineTo takes care of the worklist 595 // mechanics for us, we have no work to do in this case. 596 if (RV.Val == N) 597 continue; 598 599 assert(N->getOpcode() != ISD::DELETED_NODE && 600 RV.Val->getOpcode() != ISD::DELETED_NODE && 601 "Node was deleted but visit returned new node!"); 602 603 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 604 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 605 DOUT << '\n'; 606 std::vector<SDNode*> NowDead; 607 if (N->getNumValues() == RV.Val->getNumValues()) 608 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 609 else { 610 assert(N->getValueType(0) == RV.getValueType() && 611 N->getNumValues() == 1 && "Type mismatch"); 612 SDOperand OpV = RV; 613 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 614 } 615 616 // Push the new node and any users onto the worklist 617 AddToWorkList(RV.Val); 618 AddUsersToWorkList(RV.Val); 619 620 // Add any uses of the old node to the worklist in case this node is the 621 // last one that uses them. They may become dead after this node is 622 // deleted. 623 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 624 AddToWorkList(N->getOperand(i).Val); 625 626 // Nodes can be reintroduced into the worklist. Make sure we do not 627 // process a node that has been replaced. 628 removeFromWorkList(N); 629 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 630 removeFromWorkList(NowDead[i]); 631 632 // Finally, since the node is now dead, remove it from the graph. 633 DAG.DeleteNode(N); 634 } 635 636 // If the root changed (e.g. it was a dead load, update the root). 637 DAG.setRoot(Dummy.getValue()); 638} 639 640SDOperand DAGCombiner::visit(SDNode *N) { 641 switch(N->getOpcode()) { 642 default: break; 643 case ISD::TokenFactor: return visitTokenFactor(N); 644 case ISD::ADD: return visitADD(N); 645 case ISD::SUB: return visitSUB(N); 646 case ISD::ADDC: return visitADDC(N); 647 case ISD::ADDE: return visitADDE(N); 648 case ISD::MUL: return visitMUL(N); 649 case ISD::SDIV: return visitSDIV(N); 650 case ISD::UDIV: return visitUDIV(N); 651 case ISD::SREM: return visitSREM(N); 652 case ISD::UREM: return visitUREM(N); 653 case ISD::MULHU: return visitMULHU(N); 654 case ISD::MULHS: return visitMULHS(N); 655 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 656 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 657 case ISD::SDIVREM: return visitSDIVREM(N); 658 case ISD::UDIVREM: return visitUDIVREM(N); 659 case ISD::AND: return visitAND(N); 660 case ISD::OR: return visitOR(N); 661 case ISD::XOR: return visitXOR(N); 662 case ISD::SHL: return visitSHL(N); 663 case ISD::SRA: return visitSRA(N); 664 case ISD::SRL: return visitSRL(N); 665 case ISD::CTLZ: return visitCTLZ(N); 666 case ISD::CTTZ: return visitCTTZ(N); 667 case ISD::CTPOP: return visitCTPOP(N); 668 case ISD::SELECT: return visitSELECT(N); 669 case ISD::SELECT_CC: return visitSELECT_CC(N); 670 case ISD::SETCC: return visitSETCC(N); 671 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 672 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 673 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 674 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 675 case ISD::TRUNCATE: return visitTRUNCATE(N); 676 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 677 case ISD::FADD: return visitFADD(N); 678 case ISD::FSUB: return visitFSUB(N); 679 case ISD::FMUL: return visitFMUL(N); 680 case ISD::FDIV: return visitFDIV(N); 681 case ISD::FREM: return visitFREM(N); 682 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 683 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 684 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 685 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 686 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 687 case ISD::FP_ROUND: return visitFP_ROUND(N); 688 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 689 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 690 case ISD::FNEG: return visitFNEG(N); 691 case ISD::FABS: return visitFABS(N); 692 case ISD::BRCOND: return visitBRCOND(N); 693 case ISD::BR_CC: return visitBR_CC(N); 694 case ISD::LOAD: return visitLOAD(N); 695 case ISD::STORE: return visitSTORE(N); 696 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 697 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 698 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 699 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 700 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 701 } 702 return SDOperand(); 703} 704 705SDOperand DAGCombiner::combine(SDNode *N) { 706 707 SDOperand RV = visit(N); 708 709 // If nothing happened, try a target-specific DAG combine. 710 if (RV.Val == 0) { 711 assert(N->getOpcode() != ISD::DELETED_NODE && 712 "Node was deleted but visit returned NULL!"); 713 714 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 715 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 716 717 // Expose the DAG combiner to the target combiner impls. 718 TargetLowering::DAGCombinerInfo 719 DagCombineInfo(DAG, !AfterLegalize, false, this); 720 721 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 722 } 723 } 724 725 return RV; 726} 727 728/// getInputChainForNode - Given a node, return its input chain if it has one, 729/// otherwise return a null sd operand. 730static SDOperand getInputChainForNode(SDNode *N) { 731 if (unsigned NumOps = N->getNumOperands()) { 732 if (N->getOperand(0).getValueType() == MVT::Other) 733 return N->getOperand(0); 734 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 735 return N->getOperand(NumOps-1); 736 for (unsigned i = 1; i < NumOps-1; ++i) 737 if (N->getOperand(i).getValueType() == MVT::Other) 738 return N->getOperand(i); 739 } 740 return SDOperand(0, 0); 741} 742 743SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 744 // If N has two operands, where one has an input chain equal to the other, 745 // the 'other' chain is redundant. 746 if (N->getNumOperands() == 2) { 747 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 748 return N->getOperand(0); 749 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 750 return N->getOperand(1); 751 } 752 753 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 754 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 755 SmallPtrSet<SDNode*, 16> SeenOps; 756 bool Changed = false; // If we should replace this token factor. 757 758 // Start out with this token factor. 759 TFs.push_back(N); 760 761 // Iterate through token factors. The TFs grows when new token factors are 762 // encountered. 763 for (unsigned i = 0; i < TFs.size(); ++i) { 764 SDNode *TF = TFs[i]; 765 766 // Check each of the operands. 767 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 768 SDOperand Op = TF->getOperand(i); 769 770 switch (Op.getOpcode()) { 771 case ISD::EntryToken: 772 // Entry tokens don't need to be added to the list. They are 773 // rededundant. 774 Changed = true; 775 break; 776 777 case ISD::TokenFactor: 778 if ((CombinerAA || Op.hasOneUse()) && 779 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 780 // Queue up for processing. 781 TFs.push_back(Op.Val); 782 // Clean up in case the token factor is removed. 783 AddToWorkList(Op.Val); 784 Changed = true; 785 break; 786 } 787 // Fall thru 788 789 default: 790 // Only add if it isn't already in the list. 791 if (SeenOps.insert(Op.Val)) 792 Ops.push_back(Op); 793 else 794 Changed = true; 795 break; 796 } 797 } 798 } 799 800 SDOperand Result; 801 802 // If we've change things around then replace token factor. 803 if (Changed) { 804 if (Ops.size() == 0) { 805 // The entry token is the only possible outcome. 806 Result = DAG.getEntryNode(); 807 } else { 808 // New and improved token factor. 809 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 810 } 811 812 // Don't add users to work list. 813 return CombineTo(N, Result, false); 814 } 815 816 return Result; 817} 818 819static 820SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 821 MVT::ValueType VT = N0.getValueType(); 822 SDOperand N00 = N0.getOperand(0); 823 SDOperand N01 = N0.getOperand(1); 824 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 825 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 826 isa<ConstantSDNode>(N00.getOperand(1))) { 827 N0 = DAG.getNode(ISD::ADD, VT, 828 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 829 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 830 return DAG.getNode(ISD::ADD, VT, N0, N1); 831 } 832 return SDOperand(); 833} 834 835static 836SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 837 SelectionDAG &DAG) { 838 MVT::ValueType VT = N->getValueType(0); 839 unsigned Opc = N->getOpcode(); 840 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 841 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 842 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 843 ISD::CondCode CC = ISD::SETCC_INVALID; 844 if (isSlctCC) 845 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 846 else { 847 SDOperand CCOp = Slct.getOperand(0); 848 if (CCOp.getOpcode() == ISD::SETCC) 849 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 850 } 851 852 bool DoXform = false; 853 bool InvCC = false; 854 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 855 "Bad input!"); 856 if (LHS.getOpcode() == ISD::Constant && 857 cast<ConstantSDNode>(LHS)->isNullValue()) 858 DoXform = true; 859 else if (CC != ISD::SETCC_INVALID && 860 RHS.getOpcode() == ISD::Constant && 861 cast<ConstantSDNode>(RHS)->isNullValue()) { 862 std::swap(LHS, RHS); 863 SDOperand Op0 = Slct.getOperand(0); 864 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() 865 : Op0.getOperand(0).getValueType()); 866 CC = ISD::getSetCCInverse(CC, isInt); 867 DoXform = true; 868 InvCC = true; 869 } 870 871 if (DoXform) { 872 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 873 if (isSlctCC) 874 return DAG.getSelectCC(OtherOp, Result, 875 Slct.getOperand(0), Slct.getOperand(1), CC); 876 SDOperand CCOp = Slct.getOperand(0); 877 if (InvCC) 878 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 879 CCOp.getOperand(1), CC); 880 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 881 } 882 return SDOperand(); 883} 884 885SDOperand DAGCombiner::visitADD(SDNode *N) { 886 SDOperand N0 = N->getOperand(0); 887 SDOperand N1 = N->getOperand(1); 888 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 889 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 890 MVT::ValueType VT = N0.getValueType(); 891 892 // fold vector ops 893 if (MVT::isVector(VT)) { 894 SDOperand FoldedVOp = SimplifyVBinOp(N); 895 if (FoldedVOp.Val) return FoldedVOp; 896 } 897 898 // fold (add x, undef) -> undef 899 if (N0.getOpcode() == ISD::UNDEF) 900 return N0; 901 if (N1.getOpcode() == ISD::UNDEF) 902 return N1; 903 // fold (add c1, c2) -> c1+c2 904 if (N0C && N1C) 905 return DAG.getNode(ISD::ADD, VT, N0, N1); 906 // canonicalize constant to RHS 907 if (N0C && !N1C) 908 return DAG.getNode(ISD::ADD, VT, N1, N0); 909 // fold (add x, 0) -> x 910 if (N1C && N1C->isNullValue()) 911 return N0; 912 // fold ((c1-A)+c2) -> (c1+c2)-A 913 if (N1C && N0.getOpcode() == ISD::SUB) 914 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 915 return DAG.getNode(ISD::SUB, VT, 916 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 917 N0.getOperand(1)); 918 // reassociate add 919 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 920 if (RADD.Val != 0) 921 return RADD; 922 // fold ((0-A) + B) -> B-A 923 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 924 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 925 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 926 // fold (A + (0-B)) -> A-B 927 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 928 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 929 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 930 // fold (A+(B-A)) -> B 931 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 932 return N1.getOperand(0); 933 934 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 935 return SDOperand(N, 0); 936 937 // fold (a+b) -> (a|b) iff a and b share no bits. 938 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 939 uint64_t LHSZero, LHSOne; 940 uint64_t RHSZero, RHSOne; 941 uint64_t Mask = MVT::getIntVTBitMask(VT); 942 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 943 if (LHSZero) { 944 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 945 946 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 947 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 948 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 949 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 950 return DAG.getNode(ISD::OR, VT, N0, N1); 951 } 952 } 953 954 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 955 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 956 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 957 if (Result.Val) return Result; 958 } 959 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 960 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 961 if (Result.Val) return Result; 962 } 963 964 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 965 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 966 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 967 if (Result.Val) return Result; 968 } 969 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 970 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 971 if (Result.Val) return Result; 972 } 973 974 return SDOperand(); 975} 976 977SDOperand DAGCombiner::visitADDC(SDNode *N) { 978 SDOperand N0 = N->getOperand(0); 979 SDOperand N1 = N->getOperand(1); 980 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 981 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 982 MVT::ValueType VT = N0.getValueType(); 983 984 // If the flag result is dead, turn this into an ADD. 985 if (N->hasNUsesOfValue(0, 1)) 986 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 987 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 988 989 // canonicalize constant to RHS. 990 if (N0C && !N1C) { 991 SDOperand Ops[] = { N1, N0 }; 992 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 993 } 994 995 // fold (addc x, 0) -> x + no carry out 996 if (N1C && N1C->isNullValue()) 997 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 998 999 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1000 uint64_t LHSZero, LHSOne; 1001 uint64_t RHSZero, RHSOne; 1002 uint64_t Mask = MVT::getIntVTBitMask(VT); 1003 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1004 if (LHSZero) { 1005 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1006 1007 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1008 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1009 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1010 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1011 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1012 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1013 } 1014 1015 return SDOperand(); 1016} 1017 1018SDOperand DAGCombiner::visitADDE(SDNode *N) { 1019 SDOperand N0 = N->getOperand(0); 1020 SDOperand N1 = N->getOperand(1); 1021 SDOperand CarryIn = N->getOperand(2); 1022 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1023 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1024 //MVT::ValueType VT = N0.getValueType(); 1025 1026 // canonicalize constant to RHS 1027 if (N0C && !N1C) { 1028 SDOperand Ops[] = { N1, N0, CarryIn }; 1029 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1030 } 1031 1032 // fold (adde x, y, false) -> (addc x, y) 1033 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1034 SDOperand Ops[] = { N1, N0 }; 1035 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1036 } 1037 1038 return SDOperand(); 1039} 1040 1041 1042 1043SDOperand DAGCombiner::visitSUB(SDNode *N) { 1044 SDOperand N0 = N->getOperand(0); 1045 SDOperand N1 = N->getOperand(1); 1046 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1048 MVT::ValueType VT = N0.getValueType(); 1049 1050 // fold vector ops 1051 if (MVT::isVector(VT)) { 1052 SDOperand FoldedVOp = SimplifyVBinOp(N); 1053 if (FoldedVOp.Val) return FoldedVOp; 1054 } 1055 1056 // fold (sub x, x) -> 0 1057 if (N0 == N1) 1058 return DAG.getConstant(0, N->getValueType(0)); 1059 // fold (sub c1, c2) -> c1-c2 1060 if (N0C && N1C) 1061 return DAG.getNode(ISD::SUB, VT, N0, N1); 1062 // fold (sub x, c) -> (add x, -c) 1063 if (N1C) 1064 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1065 // fold (A+B)-A -> B 1066 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1067 return N0.getOperand(1); 1068 // fold (A+B)-B -> A 1069 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1070 return N0.getOperand(0); 1071 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1072 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1073 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1074 if (Result.Val) return Result; 1075 } 1076 // If either operand of a sub is undef, the result is undef 1077 if (N0.getOpcode() == ISD::UNDEF) 1078 return N0; 1079 if (N1.getOpcode() == ISD::UNDEF) 1080 return N1; 1081 1082 return SDOperand(); 1083} 1084 1085SDOperand DAGCombiner::visitMUL(SDNode *N) { 1086 SDOperand N0 = N->getOperand(0); 1087 SDOperand N1 = N->getOperand(1); 1088 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1090 MVT::ValueType VT = N0.getValueType(); 1091 1092 // fold vector ops 1093 if (MVT::isVector(VT)) { 1094 SDOperand FoldedVOp = SimplifyVBinOp(N); 1095 if (FoldedVOp.Val) return FoldedVOp; 1096 } 1097 1098 // fold (mul x, undef) -> 0 1099 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1100 return DAG.getConstant(0, VT); 1101 // fold (mul c1, c2) -> c1*c2 1102 if (N0C && N1C) 1103 return DAG.getNode(ISD::MUL, VT, N0, N1); 1104 // canonicalize constant to RHS 1105 if (N0C && !N1C) 1106 return DAG.getNode(ISD::MUL, VT, N1, N0); 1107 // fold (mul x, 0) -> 0 1108 if (N1C && N1C->isNullValue()) 1109 return N1; 1110 // fold (mul x, -1) -> 0-x 1111 if (N1C && N1C->isAllOnesValue()) 1112 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1113 // fold (mul x, (1 << c)) -> x << c 1114 if (N1C && isPowerOf2_64(N1C->getValue())) 1115 return DAG.getNode(ISD::SHL, VT, N0, 1116 DAG.getConstant(Log2_64(N1C->getValue()), 1117 TLI.getShiftAmountTy())); 1118 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1119 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1120 // FIXME: If the input is something that is easily negated (e.g. a 1121 // single-use add), we should put the negate there. 1122 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1123 DAG.getNode(ISD::SHL, VT, N0, 1124 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1125 TLI.getShiftAmountTy()))); 1126 } 1127 1128 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1129 if (N1C && N0.getOpcode() == ISD::SHL && 1130 isa<ConstantSDNode>(N0.getOperand(1))) { 1131 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1132 AddToWorkList(C3.Val); 1133 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1134 } 1135 1136 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1137 // use. 1138 { 1139 SDOperand Sh(0,0), Y(0,0); 1140 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1141 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1142 N0.Val->hasOneUse()) { 1143 Sh = N0; Y = N1; 1144 } else if (N1.getOpcode() == ISD::SHL && 1145 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1146 Sh = N1; Y = N0; 1147 } 1148 if (Sh.Val) { 1149 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1150 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1151 } 1152 } 1153 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1154 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1155 isa<ConstantSDNode>(N0.getOperand(1))) { 1156 return DAG.getNode(ISD::ADD, VT, 1157 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1158 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1159 } 1160 1161 // reassociate mul 1162 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1163 if (RMUL.Val != 0) 1164 return RMUL; 1165 1166 return SDOperand(); 1167} 1168 1169SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1170 SDOperand N0 = N->getOperand(0); 1171 SDOperand N1 = N->getOperand(1); 1172 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1173 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1174 MVT::ValueType VT = N->getValueType(0); 1175 1176 // fold vector ops 1177 if (MVT::isVector(VT)) { 1178 SDOperand FoldedVOp = SimplifyVBinOp(N); 1179 if (FoldedVOp.Val) return FoldedVOp; 1180 } 1181 1182 // fold (sdiv c1, c2) -> c1/c2 1183 if (N0C && N1C && !N1C->isNullValue()) 1184 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1185 // fold (sdiv X, 1) -> X 1186 if (N1C && N1C->getSignExtended() == 1LL) 1187 return N0; 1188 // fold (sdiv X, -1) -> 0-X 1189 if (N1C && N1C->isAllOnesValue()) 1190 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1191 // If we know the sign bits of both operands are zero, strength reduce to a 1192 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1193 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1194 if (DAG.MaskedValueIsZero(N1, SignBit) && 1195 DAG.MaskedValueIsZero(N0, SignBit)) 1196 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1197 // fold (sdiv X, pow2) -> simple ops after legalize 1198 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1199 (isPowerOf2_64(N1C->getSignExtended()) || 1200 isPowerOf2_64(-N1C->getSignExtended()))) { 1201 // If dividing by powers of two is cheap, then don't perform the following 1202 // fold. 1203 if (TLI.isPow2DivCheap()) 1204 return SDOperand(); 1205 int64_t pow2 = N1C->getSignExtended(); 1206 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1207 unsigned lg2 = Log2_64(abs2); 1208 // Splat the sign bit into the register 1209 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1210 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1211 TLI.getShiftAmountTy())); 1212 AddToWorkList(SGN.Val); 1213 // Add (N0 < 0) ? abs2 - 1 : 0; 1214 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1215 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1216 TLI.getShiftAmountTy())); 1217 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1218 AddToWorkList(SRL.Val); 1219 AddToWorkList(ADD.Val); // Divide by pow2 1220 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1221 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1222 // If we're dividing by a positive value, we're done. Otherwise, we must 1223 // negate the result. 1224 if (pow2 > 0) 1225 return SRA; 1226 AddToWorkList(SRA.Val); 1227 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1228 } 1229 // if integer divide is expensive and we satisfy the requirements, emit an 1230 // alternate sequence. 1231 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1232 !TLI.isIntDivCheap()) { 1233 SDOperand Op = BuildSDIV(N); 1234 if (Op.Val) return Op; 1235 } 1236 1237 // undef / X -> 0 1238 if (N0.getOpcode() == ISD::UNDEF) 1239 return DAG.getConstant(0, VT); 1240 // X / undef -> undef 1241 if (N1.getOpcode() == ISD::UNDEF) 1242 return N1; 1243 1244 return SDOperand(); 1245} 1246 1247SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1248 SDOperand N0 = N->getOperand(0); 1249 SDOperand N1 = N->getOperand(1); 1250 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1251 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1252 MVT::ValueType VT = N->getValueType(0); 1253 1254 // fold vector ops 1255 if (MVT::isVector(VT)) { 1256 SDOperand FoldedVOp = SimplifyVBinOp(N); 1257 if (FoldedVOp.Val) return FoldedVOp; 1258 } 1259 1260 // fold (udiv c1, c2) -> c1/c2 1261 if (N0C && N1C && !N1C->isNullValue()) 1262 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1263 // fold (udiv x, (1 << c)) -> x >>u c 1264 if (N1C && isPowerOf2_64(N1C->getValue())) 1265 return DAG.getNode(ISD::SRL, VT, N0, 1266 DAG.getConstant(Log2_64(N1C->getValue()), 1267 TLI.getShiftAmountTy())); 1268 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1269 if (N1.getOpcode() == ISD::SHL) { 1270 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1271 if (isPowerOf2_64(SHC->getValue())) { 1272 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1273 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1274 DAG.getConstant(Log2_64(SHC->getValue()), 1275 ADDVT)); 1276 AddToWorkList(Add.Val); 1277 return DAG.getNode(ISD::SRL, VT, N0, Add); 1278 } 1279 } 1280 } 1281 // fold (udiv x, c) -> alternate 1282 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1283 SDOperand Op = BuildUDIV(N); 1284 if (Op.Val) return Op; 1285 } 1286 1287 // undef / X -> 0 1288 if (N0.getOpcode() == ISD::UNDEF) 1289 return DAG.getConstant(0, VT); 1290 // X / undef -> undef 1291 if (N1.getOpcode() == ISD::UNDEF) 1292 return N1; 1293 1294 return SDOperand(); 1295} 1296 1297SDOperand DAGCombiner::visitSREM(SDNode *N) { 1298 SDOperand N0 = N->getOperand(0); 1299 SDOperand N1 = N->getOperand(1); 1300 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1301 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1302 MVT::ValueType VT = N->getValueType(0); 1303 1304 // fold (srem c1, c2) -> c1%c2 1305 if (N0C && N1C && !N1C->isNullValue()) 1306 return DAG.getNode(ISD::SREM, VT, N0, N1); 1307 // If we know the sign bits of both operands are zero, strength reduce to a 1308 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1309 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1310 if (DAG.MaskedValueIsZero(N1, SignBit) && 1311 DAG.MaskedValueIsZero(N0, SignBit)) 1312 return DAG.getNode(ISD::UREM, VT, N0, N1); 1313 1314 // If X/C can be simplified by the division-by-constant logic, lower 1315 // X%C to the equivalent of X-X/C*C. 1316 if (N1C && !N1C->isNullValue()) { 1317 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1318 AddToWorkList(Div.Val); 1319 SDOperand OptimizedDiv = combine(Div.Val); 1320 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1321 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1322 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1323 AddToWorkList(Mul.Val); 1324 return Sub; 1325 } 1326 } 1327 1328 // undef % X -> 0 1329 if (N0.getOpcode() == ISD::UNDEF) 1330 return DAG.getConstant(0, VT); 1331 // X % undef -> undef 1332 if (N1.getOpcode() == ISD::UNDEF) 1333 return N1; 1334 1335 return SDOperand(); 1336} 1337 1338SDOperand DAGCombiner::visitUREM(SDNode *N) { 1339 SDOperand N0 = N->getOperand(0); 1340 SDOperand N1 = N->getOperand(1); 1341 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1342 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1343 MVT::ValueType VT = N->getValueType(0); 1344 1345 // fold (urem c1, c2) -> c1%c2 1346 if (N0C && N1C && !N1C->isNullValue()) 1347 return DAG.getNode(ISD::UREM, VT, N0, N1); 1348 // fold (urem x, pow2) -> (and x, pow2-1) 1349 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1350 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1351 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1352 if (N1.getOpcode() == ISD::SHL) { 1353 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1354 if (isPowerOf2_64(SHC->getValue())) { 1355 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1356 AddToWorkList(Add.Val); 1357 return DAG.getNode(ISD::AND, VT, N0, Add); 1358 } 1359 } 1360 } 1361 1362 // If X/C can be simplified by the division-by-constant logic, lower 1363 // X%C to the equivalent of X-X/C*C. 1364 if (N1C && !N1C->isNullValue()) { 1365 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1366 SDOperand OptimizedDiv = combine(Div.Val); 1367 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1368 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1369 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1370 AddToWorkList(Mul.Val); 1371 return Sub; 1372 } 1373 } 1374 1375 // undef % X -> 0 1376 if (N0.getOpcode() == ISD::UNDEF) 1377 return DAG.getConstant(0, VT); 1378 // X % undef -> undef 1379 if (N1.getOpcode() == ISD::UNDEF) 1380 return N1; 1381 1382 return SDOperand(); 1383} 1384 1385SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1386 SDOperand N0 = N->getOperand(0); 1387 SDOperand N1 = N->getOperand(1); 1388 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1389 MVT::ValueType VT = N->getValueType(0); 1390 1391 // fold (mulhs x, 0) -> 0 1392 if (N1C && N1C->isNullValue()) 1393 return N1; 1394 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1395 if (N1C && N1C->getValue() == 1) 1396 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1397 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1398 TLI.getShiftAmountTy())); 1399 // fold (mulhs x, undef) -> 0 1400 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1401 return DAG.getConstant(0, VT); 1402 1403 return SDOperand(); 1404} 1405 1406SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1407 SDOperand N0 = N->getOperand(0); 1408 SDOperand N1 = N->getOperand(1); 1409 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1410 MVT::ValueType VT = N->getValueType(0); 1411 1412 // fold (mulhu x, 0) -> 0 1413 if (N1C && N1C->isNullValue()) 1414 return N1; 1415 // fold (mulhu x, 1) -> 0 1416 if (N1C && N1C->getValue() == 1) 1417 return DAG.getConstant(0, N0.getValueType()); 1418 // fold (mulhu x, undef) -> 0 1419 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1420 return DAG.getConstant(0, VT); 1421 1422 return SDOperand(); 1423} 1424 1425/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1426/// compute two values. LoOp and HiOp give the opcodes for the two computations 1427/// that are being performed. Return true if a simplification was made. 1428/// 1429SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1430 unsigned HiOp) { 1431 // If the high half is not needed, just compute the low half. 1432 bool HiExists = N->hasAnyUseOfValue(1); 1433 if (!HiExists && 1434 (!AfterLegalize || 1435 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1436 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1437 N->getNumOperands()); 1438 return CombineTo(N, Res, Res); 1439 } 1440 1441 // If the low half is not needed, just compute the high half. 1442 bool LoExists = N->hasAnyUseOfValue(0); 1443 if (!LoExists && 1444 (!AfterLegalize || 1445 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1446 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1447 N->getNumOperands()); 1448 return CombineTo(N, Res, Res); 1449 } 1450 1451 // If both halves are used, return as it is. 1452 if (LoExists && HiExists) 1453 return SDOperand(); 1454 1455 // If the two computed results can be simplified separately, separate them. 1456 if (LoExists) { 1457 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1458 N->op_begin(), N->getNumOperands()); 1459 AddToWorkList(Lo.Val); 1460 SDOperand LoOpt = combine(Lo.Val); 1461 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1462 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) 1463 return CombineTo(N, LoOpt, LoOpt); 1464 } 1465 1466 if (HiExists) { 1467 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1468 N->op_begin(), N->getNumOperands()); 1469 AddToWorkList(Hi.Val); 1470 SDOperand HiOpt = combine(Hi.Val); 1471 if (HiOpt.Val && HiOpt != Hi && 1472 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) 1473 return CombineTo(N, HiOpt, HiOpt); 1474 } 1475 return SDOperand(); 1476} 1477 1478SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1479 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1480 if (Res.Val) return Res; 1481 1482 return SDOperand(); 1483} 1484 1485SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1486 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1487 if (Res.Val) return Res; 1488 1489 return SDOperand(); 1490} 1491 1492SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1493 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1494 if (Res.Val) return Res; 1495 1496 return SDOperand(); 1497} 1498 1499SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1500 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1501 if (Res.Val) return Res; 1502 1503 return SDOperand(); 1504} 1505 1506/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1507/// two operands of the same opcode, try to simplify it. 1508SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1509 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1510 MVT::ValueType VT = N0.getValueType(); 1511 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1512 1513 // For each of OP in AND/OR/XOR: 1514 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1515 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1516 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1517 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1518 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1519 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1520 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1521 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1522 N0.getOperand(0).getValueType(), 1523 N0.getOperand(0), N1.getOperand(0)); 1524 AddToWorkList(ORNode.Val); 1525 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1526 } 1527 1528 // For each of OP in SHL/SRL/SRA/AND... 1529 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1530 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1531 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1532 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1533 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1534 N0.getOperand(1) == N1.getOperand(1)) { 1535 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1536 N0.getOperand(0).getValueType(), 1537 N0.getOperand(0), N1.getOperand(0)); 1538 AddToWorkList(ORNode.Val); 1539 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1540 } 1541 1542 return SDOperand(); 1543} 1544 1545SDOperand DAGCombiner::visitAND(SDNode *N) { 1546 SDOperand N0 = N->getOperand(0); 1547 SDOperand N1 = N->getOperand(1); 1548 SDOperand LL, LR, RL, RR, CC0, CC1; 1549 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1551 MVT::ValueType VT = N1.getValueType(); 1552 1553 // fold vector ops 1554 if (MVT::isVector(VT)) { 1555 SDOperand FoldedVOp = SimplifyVBinOp(N); 1556 if (FoldedVOp.Val) return FoldedVOp; 1557 } 1558 1559 // fold (and x, undef) -> 0 1560 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1561 return DAG.getConstant(0, VT); 1562 // fold (and c1, c2) -> c1&c2 1563 if (N0C && N1C) 1564 return DAG.getNode(ISD::AND, VT, N0, N1); 1565 // canonicalize constant to RHS 1566 if (N0C && !N1C) 1567 return DAG.getNode(ISD::AND, VT, N1, N0); 1568 // fold (and x, -1) -> x 1569 if (N1C && N1C->isAllOnesValue()) 1570 return N0; 1571 // if (and x, c) is known to be zero, return 0 1572 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1573 return DAG.getConstant(0, VT); 1574 // reassociate and 1575 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1576 if (RAND.Val != 0) 1577 return RAND; 1578 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1579 if (N1C && N0.getOpcode() == ISD::OR) 1580 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1581 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1582 return N1; 1583 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1584 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1585 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1586 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1587 ~N1C->getValue() & InMask)) { 1588 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1589 N0.getOperand(0)); 1590 1591 // Replace uses of the AND with uses of the Zero extend node. 1592 CombineTo(N, Zext); 1593 1594 // We actually want to replace all uses of the any_extend with the 1595 // zero_extend, to avoid duplicating things. This will later cause this 1596 // AND to be folded. 1597 CombineTo(N0.Val, Zext); 1598 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1599 } 1600 } 1601 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1602 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1603 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1604 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1605 1606 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1607 MVT::isInteger(LL.getValueType())) { 1608 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1609 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1610 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1611 AddToWorkList(ORNode.Val); 1612 return DAG.getSetCC(VT, ORNode, LR, Op1); 1613 } 1614 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1615 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1616 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1617 AddToWorkList(ANDNode.Val); 1618 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1619 } 1620 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1621 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1622 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1623 AddToWorkList(ORNode.Val); 1624 return DAG.getSetCC(VT, ORNode, LR, Op1); 1625 } 1626 } 1627 // canonicalize equivalent to ll == rl 1628 if (LL == RR && LR == RL) { 1629 Op1 = ISD::getSetCCSwappedOperands(Op1); 1630 std::swap(RL, RR); 1631 } 1632 if (LL == RL && LR == RR) { 1633 bool isInteger = MVT::isInteger(LL.getValueType()); 1634 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1635 if (Result != ISD::SETCC_INVALID) 1636 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1637 } 1638 } 1639 1640 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1641 if (N0.getOpcode() == N1.getOpcode()) { 1642 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1643 if (Tmp.Val) return Tmp; 1644 } 1645 1646 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1647 // fold (and (sra)) -> (and (srl)) when possible. 1648 if (!MVT::isVector(VT) && 1649 SimplifyDemandedBits(SDOperand(N, 0))) 1650 return SDOperand(N, 0); 1651 // fold (zext_inreg (extload x)) -> (zextload x) 1652 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1653 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1654 MVT::ValueType EVT = LN0->getLoadedVT(); 1655 // If we zero all the possible extended bits, then we can turn this into 1656 // a zextload if we are running before legalize or the operation is legal. 1657 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1658 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1659 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1660 LN0->getBasePtr(), LN0->getSrcValue(), 1661 LN0->getSrcValueOffset(), EVT, 1662 LN0->isVolatile(), 1663 LN0->getAlignment()); 1664 AddToWorkList(N); 1665 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1666 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1667 } 1668 } 1669 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1670 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1671 N0.hasOneUse()) { 1672 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1673 MVT::ValueType EVT = LN0->getLoadedVT(); 1674 // If we zero all the possible extended bits, then we can turn this into 1675 // a zextload if we are running before legalize or the operation is legal. 1676 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1677 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1678 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1679 LN0->getBasePtr(), LN0->getSrcValue(), 1680 LN0->getSrcValueOffset(), EVT, 1681 LN0->isVolatile(), 1682 LN0->getAlignment()); 1683 AddToWorkList(N); 1684 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1685 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1686 } 1687 } 1688 1689 // fold (and (load x), 255) -> (zextload x, i8) 1690 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1691 if (N1C && N0.getOpcode() == ISD::LOAD) { 1692 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1693 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1694 LN0->isUnindexed() && N0.hasOneUse()) { 1695 MVT::ValueType EVT, LoadedVT; 1696 if (N1C->getValue() == 255) 1697 EVT = MVT::i8; 1698 else if (N1C->getValue() == 65535) 1699 EVT = MVT::i16; 1700 else if (N1C->getValue() == ~0U) 1701 EVT = MVT::i32; 1702 else 1703 EVT = MVT::Other; 1704 1705 LoadedVT = LN0->getLoadedVT(); 1706 if (EVT != MVT::Other && LoadedVT > EVT && 1707 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1708 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1709 // For big endian targets, we need to add an offset to the pointer to 1710 // load the correct bytes. For little endian systems, we merely need to 1711 // read fewer bytes from the same pointer. 1712 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1713 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1714 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1715 unsigned Alignment = LN0->getAlignment(); 1716 SDOperand NewPtr = LN0->getBasePtr(); 1717 if (!TLI.isLittleEndian()) { 1718 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1719 DAG.getConstant(PtrOff, PtrType)); 1720 Alignment = MinAlign(Alignment, PtrOff); 1721 } 1722 AddToWorkList(NewPtr.Val); 1723 SDOperand Load = 1724 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1725 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1726 LN0->isVolatile(), Alignment); 1727 AddToWorkList(N); 1728 CombineTo(N0.Val, Load, Load.getValue(1)); 1729 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1730 } 1731 } 1732 } 1733 1734 return SDOperand(); 1735} 1736 1737SDOperand DAGCombiner::visitOR(SDNode *N) { 1738 SDOperand N0 = N->getOperand(0); 1739 SDOperand N1 = N->getOperand(1); 1740 SDOperand LL, LR, RL, RR, CC0, CC1; 1741 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1742 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1743 MVT::ValueType VT = N1.getValueType(); 1744 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1745 1746 // fold vector ops 1747 if (MVT::isVector(VT)) { 1748 SDOperand FoldedVOp = SimplifyVBinOp(N); 1749 if (FoldedVOp.Val) return FoldedVOp; 1750 } 1751 1752 // fold (or x, undef) -> -1 1753 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1754 return DAG.getConstant(~0ULL, VT); 1755 // fold (or c1, c2) -> c1|c2 1756 if (N0C && N1C) 1757 return DAG.getNode(ISD::OR, VT, N0, N1); 1758 // canonicalize constant to RHS 1759 if (N0C && !N1C) 1760 return DAG.getNode(ISD::OR, VT, N1, N0); 1761 // fold (or x, 0) -> x 1762 if (N1C && N1C->isNullValue()) 1763 return N0; 1764 // fold (or x, -1) -> -1 1765 if (N1C && N1C->isAllOnesValue()) 1766 return N1; 1767 // fold (or x, c) -> c iff (x & ~c) == 0 1768 if (N1C && 1769 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1770 return N1; 1771 // reassociate or 1772 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1773 if (ROR.Val != 0) 1774 return ROR; 1775 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1776 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1777 isa<ConstantSDNode>(N0.getOperand(1))) { 1778 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1779 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1780 N1), 1781 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1782 } 1783 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1784 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1785 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1786 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1787 1788 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1789 MVT::isInteger(LL.getValueType())) { 1790 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1791 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1792 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1793 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1794 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1795 AddToWorkList(ORNode.Val); 1796 return DAG.getSetCC(VT, ORNode, LR, Op1); 1797 } 1798 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1799 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1800 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1801 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1802 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1803 AddToWorkList(ANDNode.Val); 1804 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1805 } 1806 } 1807 // canonicalize equivalent to ll == rl 1808 if (LL == RR && LR == RL) { 1809 Op1 = ISD::getSetCCSwappedOperands(Op1); 1810 std::swap(RL, RR); 1811 } 1812 if (LL == RL && LR == RR) { 1813 bool isInteger = MVT::isInteger(LL.getValueType()); 1814 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1815 if (Result != ISD::SETCC_INVALID) 1816 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1817 } 1818 } 1819 1820 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1821 if (N0.getOpcode() == N1.getOpcode()) { 1822 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1823 if (Tmp.Val) return Tmp; 1824 } 1825 1826 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1827 if (N0.getOpcode() == ISD::AND && 1828 N1.getOpcode() == ISD::AND && 1829 N0.getOperand(1).getOpcode() == ISD::Constant && 1830 N1.getOperand(1).getOpcode() == ISD::Constant && 1831 // Don't increase # computations. 1832 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1833 // We can only do this xform if we know that bits from X that are set in C2 1834 // but not in C1 are already zero. Likewise for Y. 1835 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1836 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1837 1838 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1839 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1840 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1841 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1842 } 1843 } 1844 1845 1846 // See if this is some rotate idiom. 1847 if (SDNode *Rot = MatchRotate(N0, N1)) 1848 return SDOperand(Rot, 0); 1849 1850 return SDOperand(); 1851} 1852 1853 1854/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1855static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1856 if (Op.getOpcode() == ISD::AND) { 1857 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1858 Mask = Op.getOperand(1); 1859 Op = Op.getOperand(0); 1860 } else { 1861 return false; 1862 } 1863 } 1864 1865 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1866 Shift = Op; 1867 return true; 1868 } 1869 return false; 1870} 1871 1872 1873// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1874// idioms for rotate, and if the target supports rotation instructions, generate 1875// a rot[lr]. 1876SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1877 // Must be a legal type. Expanded an promoted things won't work with rotates. 1878 MVT::ValueType VT = LHS.getValueType(); 1879 if (!TLI.isTypeLegal(VT)) return 0; 1880 1881 // The target must have at least one rotate flavor. 1882 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1883 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1884 if (!HasROTL && !HasROTR) return 0; 1885 1886 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1887 SDOperand LHSShift; // The shift. 1888 SDOperand LHSMask; // AND value if any. 1889 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1890 return 0; // Not part of a rotate. 1891 1892 SDOperand RHSShift; // The shift. 1893 SDOperand RHSMask; // AND value if any. 1894 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1895 return 0; // Not part of a rotate. 1896 1897 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1898 return 0; // Not shifting the same value. 1899 1900 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1901 return 0; // Shifts must disagree. 1902 1903 // Canonicalize shl to left side in a shl/srl pair. 1904 if (RHSShift.getOpcode() == ISD::SHL) { 1905 std::swap(LHS, RHS); 1906 std::swap(LHSShift, RHSShift); 1907 std::swap(LHSMask , RHSMask ); 1908 } 1909 1910 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1911 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1912 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1913 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1914 1915 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1916 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1917 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1918 RHSShiftAmt.getOpcode() == ISD::Constant) { 1919 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1920 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1921 if ((LShVal + RShVal) != OpSizeInBits) 1922 return 0; 1923 1924 SDOperand Rot; 1925 if (HasROTL) 1926 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1927 else 1928 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1929 1930 // If there is an AND of either shifted operand, apply it to the result. 1931 if (LHSMask.Val || RHSMask.Val) { 1932 uint64_t Mask = MVT::getIntVTBitMask(VT); 1933 1934 if (LHSMask.Val) { 1935 uint64_t RHSBits = (1ULL << LShVal)-1; 1936 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1937 } 1938 if (RHSMask.Val) { 1939 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1940 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1941 } 1942 1943 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1944 } 1945 1946 return Rot.Val; 1947 } 1948 1949 // If there is a mask here, and we have a variable shift, we can't be sure 1950 // that we're masking out the right stuff. 1951 if (LHSMask.Val || RHSMask.Val) 1952 return 0; 1953 1954 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1955 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1956 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1957 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1958 if (ConstantSDNode *SUBC = 1959 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1960 if (SUBC->getValue() == OpSizeInBits) 1961 if (HasROTL) 1962 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1963 else 1964 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1965 } 1966 } 1967 1968 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1969 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1970 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1971 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1972 if (ConstantSDNode *SUBC = 1973 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1974 if (SUBC->getValue() == OpSizeInBits) 1975 if (HasROTL) 1976 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1977 else 1978 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1979 } 1980 } 1981 1982 // Look for sign/zext/any-extended cases: 1983 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1984 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1985 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1986 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1987 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1988 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1989 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1990 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1991 if (RExtOp0.getOpcode() == ISD::SUB && 1992 RExtOp0.getOperand(1) == LExtOp0) { 1993 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1994 // (rotr x, y) 1995 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1996 // (rotl x, (sub 32, y)) 1997 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1998 if (SUBC->getValue() == OpSizeInBits) { 1999 if (HasROTL) 2000 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2001 else 2002 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2003 } 2004 } 2005 } else if (LExtOp0.getOpcode() == ISD::SUB && 2006 RExtOp0 == LExtOp0.getOperand(1)) { 2007 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2008 // (rotl x, y) 2009 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2010 // (rotr x, (sub 32, y)) 2011 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2012 if (SUBC->getValue() == OpSizeInBits) { 2013 if (HasROTL) 2014 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2015 else 2016 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2017 } 2018 } 2019 } 2020 } 2021 2022 return 0; 2023} 2024 2025 2026SDOperand DAGCombiner::visitXOR(SDNode *N) { 2027 SDOperand N0 = N->getOperand(0); 2028 SDOperand N1 = N->getOperand(1); 2029 SDOperand LHS, RHS, CC; 2030 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2031 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2032 MVT::ValueType VT = N0.getValueType(); 2033 2034 // fold vector ops 2035 if (MVT::isVector(VT)) { 2036 SDOperand FoldedVOp = SimplifyVBinOp(N); 2037 if (FoldedVOp.Val) return FoldedVOp; 2038 } 2039 2040 // fold (xor x, undef) -> undef 2041 if (N0.getOpcode() == ISD::UNDEF) 2042 return N0; 2043 if (N1.getOpcode() == ISD::UNDEF) 2044 return N1; 2045 // fold (xor c1, c2) -> c1^c2 2046 if (N0C && N1C) 2047 return DAG.getNode(ISD::XOR, VT, N0, N1); 2048 // canonicalize constant to RHS 2049 if (N0C && !N1C) 2050 return DAG.getNode(ISD::XOR, VT, N1, N0); 2051 // fold (xor x, 0) -> x 2052 if (N1C && N1C->isNullValue()) 2053 return N0; 2054 // reassociate xor 2055 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2056 if (RXOR.Val != 0) 2057 return RXOR; 2058 // fold !(x cc y) -> (x !cc y) 2059 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2060 bool isInt = MVT::isInteger(LHS.getValueType()); 2061 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2062 isInt); 2063 if (N0.getOpcode() == ISD::SETCC) 2064 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2065 if (N0.getOpcode() == ISD::SELECT_CC) 2066 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2067 assert(0 && "Unhandled SetCC Equivalent!"); 2068 abort(); 2069 } 2070 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2071 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2072 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2073 SDOperand V = N0.getOperand(0); 2074 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2075 DAG.getConstant(1, V.getValueType())); 2076 AddToWorkList(V.Val); 2077 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2078 } 2079 2080 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2081 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2082 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2083 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2084 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2085 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2086 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2087 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2088 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2089 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2090 } 2091 } 2092 // fold !(x or y) -> (!x and !y) iff x or y are constants 2093 if (N1C && N1C->isAllOnesValue() && 2094 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2095 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2096 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2097 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2098 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2099 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2100 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2101 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2102 } 2103 } 2104 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2105 if (N1C && N0.getOpcode() == ISD::XOR) { 2106 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2107 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2108 if (N00C) 2109 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2110 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2111 if (N01C) 2112 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2113 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2114 } 2115 // fold (xor x, x) -> 0 2116 if (N0 == N1) { 2117 if (!MVT::isVector(VT)) { 2118 return DAG.getConstant(0, VT); 2119 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2120 // Produce a vector of zeros. 2121 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2122 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2123 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2124 } 2125 } 2126 2127 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2128 if (N0.getOpcode() == N1.getOpcode()) { 2129 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2130 if (Tmp.Val) return Tmp; 2131 } 2132 2133 // Simplify the expression using non-local knowledge. 2134 if (!MVT::isVector(VT) && 2135 SimplifyDemandedBits(SDOperand(N, 0))) 2136 return SDOperand(N, 0); 2137 2138 return SDOperand(); 2139} 2140 2141/// visitShiftByConstant - Handle transforms common to the three shifts, when 2142/// the shift amount is a constant. 2143SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2144 SDNode *LHS = N->getOperand(0).Val; 2145 if (!LHS->hasOneUse()) return SDOperand(); 2146 2147 // We want to pull some binops through shifts, so that we have (and (shift)) 2148 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2149 // thing happens with address calculations, so it's important to canonicalize 2150 // it. 2151 bool HighBitSet = false; // Can we transform this if the high bit is set? 2152 2153 switch (LHS->getOpcode()) { 2154 default: return SDOperand(); 2155 case ISD::OR: 2156 case ISD::XOR: 2157 HighBitSet = false; // We can only transform sra if the high bit is clear. 2158 break; 2159 case ISD::AND: 2160 HighBitSet = true; // We can only transform sra if the high bit is set. 2161 break; 2162 case ISD::ADD: 2163 if (N->getOpcode() != ISD::SHL) 2164 return SDOperand(); // only shl(add) not sr[al](add). 2165 HighBitSet = false; // We can only transform sra if the high bit is clear. 2166 break; 2167 } 2168 2169 // We require the RHS of the binop to be a constant as well. 2170 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2171 if (!BinOpCst) return SDOperand(); 2172 2173 2174 // FIXME: disable this for unless the input to the binop is a shift by a 2175 // constant. If it is not a shift, it pessimizes some common cases like: 2176 // 2177 //void foo(int *X, int i) { X[i & 1235] = 1; } 2178 //int bar(int *X, int i) { return X[i & 255]; } 2179 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2180 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2181 BinOpLHSVal->getOpcode() != ISD::SRA && 2182 BinOpLHSVal->getOpcode() != ISD::SRL) || 2183 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2184 return SDOperand(); 2185 2186 MVT::ValueType VT = N->getValueType(0); 2187 2188 // If this is a signed shift right, and the high bit is modified 2189 // by the logical operation, do not perform the transformation. 2190 // The highBitSet boolean indicates the value of the high bit of 2191 // the constant which would cause it to be modified for this 2192 // operation. 2193 if (N->getOpcode() == ISD::SRA) { 2194 uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1; 2195 if ((bool)BinOpRHSSign != HighBitSet) 2196 return SDOperand(); 2197 } 2198 2199 // Fold the constants, shifting the binop RHS by the shift amount. 2200 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2201 LHS->getOperand(1), N->getOperand(1)); 2202 2203 // Create the new shift. 2204 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2205 N->getOperand(1)); 2206 2207 // Create the new binop. 2208 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2209} 2210 2211 2212SDOperand DAGCombiner::visitSHL(SDNode *N) { 2213 SDOperand N0 = N->getOperand(0); 2214 SDOperand N1 = N->getOperand(1); 2215 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2216 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2217 MVT::ValueType VT = N0.getValueType(); 2218 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2219 2220 // fold (shl c1, c2) -> c1<<c2 2221 if (N0C && N1C) 2222 return DAG.getNode(ISD::SHL, VT, N0, N1); 2223 // fold (shl 0, x) -> 0 2224 if (N0C && N0C->isNullValue()) 2225 return N0; 2226 // fold (shl x, c >= size(x)) -> undef 2227 if (N1C && N1C->getValue() >= OpSizeInBits) 2228 return DAG.getNode(ISD::UNDEF, VT); 2229 // fold (shl x, 0) -> x 2230 if (N1C && N1C->isNullValue()) 2231 return N0; 2232 // if (shl x, c) is known to be zero, return 0 2233 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2234 return DAG.getConstant(0, VT); 2235 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2236 return SDOperand(N, 0); 2237 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2238 if (N1C && N0.getOpcode() == ISD::SHL && 2239 N0.getOperand(1).getOpcode() == ISD::Constant) { 2240 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2241 uint64_t c2 = N1C->getValue(); 2242 if (c1 + c2 > OpSizeInBits) 2243 return DAG.getConstant(0, VT); 2244 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2245 DAG.getConstant(c1 + c2, N1.getValueType())); 2246 } 2247 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2248 // (srl (and x, -1 << c1), c1-c2) 2249 if (N1C && N0.getOpcode() == ISD::SRL && 2250 N0.getOperand(1).getOpcode() == ISD::Constant) { 2251 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2252 uint64_t c2 = N1C->getValue(); 2253 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2254 DAG.getConstant(~0ULL << c1, VT)); 2255 if (c2 > c1) 2256 return DAG.getNode(ISD::SHL, VT, Mask, 2257 DAG.getConstant(c2-c1, N1.getValueType())); 2258 else 2259 return DAG.getNode(ISD::SRL, VT, Mask, 2260 DAG.getConstant(c1-c2, N1.getValueType())); 2261 } 2262 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2263 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2264 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2265 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2266 2267 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2268} 2269 2270SDOperand DAGCombiner::visitSRA(SDNode *N) { 2271 SDOperand N0 = N->getOperand(0); 2272 SDOperand N1 = N->getOperand(1); 2273 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2274 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2275 MVT::ValueType VT = N0.getValueType(); 2276 2277 // fold (sra c1, c2) -> c1>>c2 2278 if (N0C && N1C) 2279 return DAG.getNode(ISD::SRA, VT, N0, N1); 2280 // fold (sra 0, x) -> 0 2281 if (N0C && N0C->isNullValue()) 2282 return N0; 2283 // fold (sra -1, x) -> -1 2284 if (N0C && N0C->isAllOnesValue()) 2285 return N0; 2286 // fold (sra x, c >= size(x)) -> undef 2287 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2288 return DAG.getNode(ISD::UNDEF, VT); 2289 // fold (sra x, 0) -> x 2290 if (N1C && N1C->isNullValue()) 2291 return N0; 2292 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2293 // sext_inreg. 2294 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2295 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2296 MVT::ValueType EVT; 2297 switch (LowBits) { 2298 default: EVT = MVT::Other; break; 2299 case 1: EVT = MVT::i1; break; 2300 case 8: EVT = MVT::i8; break; 2301 case 16: EVT = MVT::i16; break; 2302 case 32: EVT = MVT::i32; break; 2303 } 2304 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2305 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2306 DAG.getValueType(EVT)); 2307 } 2308 2309 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2310 if (N1C && N0.getOpcode() == ISD::SRA) { 2311 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2312 unsigned Sum = N1C->getValue() + C1->getValue(); 2313 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2314 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2315 DAG.getConstant(Sum, N1C->getValueType(0))); 2316 } 2317 } 2318 2319 // Simplify, based on bits shifted out of the LHS. 2320 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2321 return SDOperand(N, 0); 2322 2323 2324 // If the sign bit is known to be zero, switch this to a SRL. 2325 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2326 return DAG.getNode(ISD::SRL, VT, N0, N1); 2327 2328 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2329} 2330 2331SDOperand DAGCombiner::visitSRL(SDNode *N) { 2332 SDOperand N0 = N->getOperand(0); 2333 SDOperand N1 = N->getOperand(1); 2334 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2335 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2336 MVT::ValueType VT = N0.getValueType(); 2337 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2338 2339 // fold (srl c1, c2) -> c1 >>u c2 2340 if (N0C && N1C) 2341 return DAG.getNode(ISD::SRL, VT, N0, N1); 2342 // fold (srl 0, x) -> 0 2343 if (N0C && N0C->isNullValue()) 2344 return N0; 2345 // fold (srl x, c >= size(x)) -> undef 2346 if (N1C && N1C->getValue() >= OpSizeInBits) 2347 return DAG.getNode(ISD::UNDEF, VT); 2348 // fold (srl x, 0) -> x 2349 if (N1C && N1C->isNullValue()) 2350 return N0; 2351 // if (srl x, c) is known to be zero, return 0 2352 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2353 return DAG.getConstant(0, VT); 2354 2355 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2356 if (N1C && N0.getOpcode() == ISD::SRL && 2357 N0.getOperand(1).getOpcode() == ISD::Constant) { 2358 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2359 uint64_t c2 = N1C->getValue(); 2360 if (c1 + c2 > OpSizeInBits) 2361 return DAG.getConstant(0, VT); 2362 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2363 DAG.getConstant(c1 + c2, N1.getValueType())); 2364 } 2365 2366 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2367 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2368 // Shifting in all undef bits? 2369 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2370 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2371 return DAG.getNode(ISD::UNDEF, VT); 2372 2373 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2374 AddToWorkList(SmallShift.Val); 2375 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2376 } 2377 2378 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2379 // bit, which is unmodified by sra. 2380 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2381 if (N0.getOpcode() == ISD::SRA) 2382 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2383 } 2384 2385 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2386 if (N1C && N0.getOpcode() == ISD::CTLZ && 2387 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2388 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2389 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2390 2391 // If any of the input bits are KnownOne, then the input couldn't be all 2392 // zeros, thus the result of the srl will always be zero. 2393 if (KnownOne) return DAG.getConstant(0, VT); 2394 2395 // If all of the bits input the to ctlz node are known to be zero, then 2396 // the result of the ctlz is "32" and the result of the shift is one. 2397 uint64_t UnknownBits = ~KnownZero & Mask; 2398 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2399 2400 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2401 if ((UnknownBits & (UnknownBits-1)) == 0) { 2402 // Okay, we know that only that the single bit specified by UnknownBits 2403 // could be set on input to the CTLZ node. If this bit is set, the SRL 2404 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2405 // to an SRL,XOR pair, which is likely to simplify more. 2406 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2407 SDOperand Op = N0.getOperand(0); 2408 if (ShAmt) { 2409 Op = DAG.getNode(ISD::SRL, VT, Op, 2410 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2411 AddToWorkList(Op.Val); 2412 } 2413 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2414 } 2415 } 2416 2417 // fold operands of srl based on knowledge that the low bits are not 2418 // demanded. 2419 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2420 return SDOperand(N, 0); 2421 2422 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2423} 2424 2425SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2426 SDOperand N0 = N->getOperand(0); 2427 MVT::ValueType VT = N->getValueType(0); 2428 2429 // fold (ctlz c1) -> c2 2430 if (isa<ConstantSDNode>(N0)) 2431 return DAG.getNode(ISD::CTLZ, VT, N0); 2432 return SDOperand(); 2433} 2434 2435SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2436 SDOperand N0 = N->getOperand(0); 2437 MVT::ValueType VT = N->getValueType(0); 2438 2439 // fold (cttz c1) -> c2 2440 if (isa<ConstantSDNode>(N0)) 2441 return DAG.getNode(ISD::CTTZ, VT, N0); 2442 return SDOperand(); 2443} 2444 2445SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2446 SDOperand N0 = N->getOperand(0); 2447 MVT::ValueType VT = N->getValueType(0); 2448 2449 // fold (ctpop c1) -> c2 2450 if (isa<ConstantSDNode>(N0)) 2451 return DAG.getNode(ISD::CTPOP, VT, N0); 2452 return SDOperand(); 2453} 2454 2455SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2456 SDOperand N0 = N->getOperand(0); 2457 SDOperand N1 = N->getOperand(1); 2458 SDOperand N2 = N->getOperand(2); 2459 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2460 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2461 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2462 MVT::ValueType VT = N->getValueType(0); 2463 MVT::ValueType VT0 = N0.getValueType(); 2464 2465 // fold select C, X, X -> X 2466 if (N1 == N2) 2467 return N1; 2468 // fold select true, X, Y -> X 2469 if (N0C && !N0C->isNullValue()) 2470 return N1; 2471 // fold select false, X, Y -> Y 2472 if (N0C && N0C->isNullValue()) 2473 return N2; 2474 // fold select C, 1, X -> C | X 2475 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2476 return DAG.getNode(ISD::OR, VT, N0, N2); 2477 // fold select C, 0, 1 -> ~C 2478 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2479 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2480 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2481 if (VT == VT0) 2482 return XORNode; 2483 AddToWorkList(XORNode.Val); 2484 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2485 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2486 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2487 } 2488 // fold select C, 0, X -> ~C & X 2489 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2490 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2491 AddToWorkList(XORNode.Val); 2492 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2493 } 2494 // fold select C, X, 1 -> ~C | X 2495 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) { 2496 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2497 AddToWorkList(XORNode.Val); 2498 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2499 } 2500 // fold select C, X, 0 -> C & X 2501 // FIXME: this should check for C type == X type, not i1? 2502 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2503 return DAG.getNode(ISD::AND, VT, N0, N1); 2504 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2505 if (MVT::i1 == VT && N0 == N1) 2506 return DAG.getNode(ISD::OR, VT, N0, N2); 2507 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2508 if (MVT::i1 == VT && N0 == N2) 2509 return DAG.getNode(ISD::AND, VT, N0, N1); 2510 2511 // If we can fold this based on the true/false value, do so. 2512 if (SimplifySelectOps(N, N1, N2)) 2513 return SDOperand(N, 0); // Don't revisit N. 2514 2515 // fold selects based on a setcc into other things, such as min/max/abs 2516 if (N0.getOpcode() == ISD::SETCC) 2517 // FIXME: 2518 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2519 // having to say they don't support SELECT_CC on every type the DAG knows 2520 // about, since there is no way to mark an opcode illegal at all value types 2521 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2522 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2523 N1, N2, N0.getOperand(2)); 2524 else 2525 return SimplifySelect(N0, N1, N2); 2526 return SDOperand(); 2527} 2528 2529SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2530 SDOperand N0 = N->getOperand(0); 2531 SDOperand N1 = N->getOperand(1); 2532 SDOperand N2 = N->getOperand(2); 2533 SDOperand N3 = N->getOperand(3); 2534 SDOperand N4 = N->getOperand(4); 2535 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2536 2537 // fold select_cc lhs, rhs, x, x, cc -> x 2538 if (N2 == N3) 2539 return N2; 2540 2541 // Determine if the condition we're dealing with is constant 2542 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2543 if (SCC.Val) AddToWorkList(SCC.Val); 2544 2545 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2546 if (SCCC->getValue()) 2547 return N2; // cond always true -> true val 2548 else 2549 return N3; // cond always false -> false val 2550 } 2551 2552 // Fold to a simpler select_cc 2553 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2554 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2555 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2556 SCC.getOperand(2)); 2557 2558 // If we can fold this based on the true/false value, do so. 2559 if (SimplifySelectOps(N, N2, N3)) 2560 return SDOperand(N, 0); // Don't revisit N. 2561 2562 // fold select_cc into other things, such as min/max/abs 2563 return SimplifySelectCC(N0, N1, N2, N3, CC); 2564} 2565 2566SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2567 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2568 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2569} 2570 2571// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2572// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2573// transformation. Returns true if extension are possible and the above 2574// mentioned transformation is profitable. 2575static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2576 unsigned ExtOpc, 2577 SmallVector<SDNode*, 4> &ExtendNodes, 2578 TargetLowering &TLI) { 2579 bool HasCopyToRegUses = false; 2580 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2581 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2582 UI != UE; ++UI) { 2583 SDNode *User = *UI; 2584 if (User == N) 2585 continue; 2586 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2587 if (User->getOpcode() == ISD::SETCC) { 2588 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2589 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2590 // Sign bits will be lost after a zext. 2591 return false; 2592 bool Add = false; 2593 for (unsigned i = 0; i != 2; ++i) { 2594 SDOperand UseOp = User->getOperand(i); 2595 if (UseOp == N0) 2596 continue; 2597 if (!isa<ConstantSDNode>(UseOp)) 2598 return false; 2599 Add = true; 2600 } 2601 if (Add) 2602 ExtendNodes.push_back(User); 2603 } else { 2604 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2605 SDOperand UseOp = User->getOperand(i); 2606 if (UseOp == N0) { 2607 // If truncate from extended type to original load type is free 2608 // on this target, then it's ok to extend a CopyToReg. 2609 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2610 HasCopyToRegUses = true; 2611 else 2612 return false; 2613 } 2614 } 2615 } 2616 } 2617 2618 if (HasCopyToRegUses) { 2619 bool BothLiveOut = false; 2620 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2621 UI != UE; ++UI) { 2622 SDNode *User = *UI; 2623 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2624 SDOperand UseOp = User->getOperand(i); 2625 if (UseOp.Val == N && UseOp.ResNo == 0) { 2626 BothLiveOut = true; 2627 break; 2628 } 2629 } 2630 } 2631 if (BothLiveOut) 2632 // Both unextended and extended values are live out. There had better be 2633 // good a reason for the transformation. 2634 return ExtendNodes.size(); 2635 } 2636 return true; 2637} 2638 2639SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2640 SDOperand N0 = N->getOperand(0); 2641 MVT::ValueType VT = N->getValueType(0); 2642 2643 // fold (sext c1) -> c1 2644 if (isa<ConstantSDNode>(N0)) 2645 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2646 2647 // fold (sext (sext x)) -> (sext x) 2648 // fold (sext (aext x)) -> (sext x) 2649 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2650 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2651 2652 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2653 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2654 if (N0.getOpcode() == ISD::TRUNCATE) { 2655 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2656 if (NarrowLoad.Val) { 2657 if (NarrowLoad.Val != N0.Val) 2658 CombineTo(N0.Val, NarrowLoad); 2659 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2660 } 2661 } 2662 2663 // See if the value being truncated is already sign extended. If so, just 2664 // eliminate the trunc/sext pair. 2665 if (N0.getOpcode() == ISD::TRUNCATE) { 2666 SDOperand Op = N0.getOperand(0); 2667 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2668 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2669 unsigned DestBits = MVT::getSizeInBits(VT); 2670 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2671 2672 if (OpBits == DestBits) { 2673 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2674 // bits, it is already ready. 2675 if (NumSignBits > DestBits-MidBits) 2676 return Op; 2677 } else if (OpBits < DestBits) { 2678 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2679 // bits, just sext from i32. 2680 if (NumSignBits > OpBits-MidBits) 2681 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2682 } else { 2683 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2684 // bits, just truncate to i32. 2685 if (NumSignBits > OpBits-MidBits) 2686 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2687 } 2688 2689 // fold (sext (truncate x)) -> (sextinreg x). 2690 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2691 N0.getValueType())) { 2692 if (Op.getValueType() < VT) 2693 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2694 else if (Op.getValueType() > VT) 2695 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2696 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2697 DAG.getValueType(N0.getValueType())); 2698 } 2699 } 2700 2701 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2702 if (ISD::isNON_EXTLoad(N0.Val) && 2703 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2704 bool DoXform = true; 2705 SmallVector<SDNode*, 4> SetCCs; 2706 if (!N0.hasOneUse()) 2707 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2708 if (DoXform) { 2709 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2710 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2711 LN0->getBasePtr(), LN0->getSrcValue(), 2712 LN0->getSrcValueOffset(), 2713 N0.getValueType(), 2714 LN0->isVolatile(), 2715 LN0->getAlignment()); 2716 CombineTo(N, ExtLoad); 2717 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2718 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2719 // Extend SetCC uses if necessary. 2720 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2721 SDNode *SetCC = SetCCs[i]; 2722 SmallVector<SDOperand, 4> Ops; 2723 for (unsigned j = 0; j != 2; ++j) { 2724 SDOperand SOp = SetCC->getOperand(j); 2725 if (SOp == Trunc) 2726 Ops.push_back(ExtLoad); 2727 else 2728 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2729 } 2730 Ops.push_back(SetCC->getOperand(2)); 2731 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2732 &Ops[0], Ops.size())); 2733 } 2734 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2735 } 2736 } 2737 2738 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2739 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2740 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2741 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2742 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2743 MVT::ValueType EVT = LN0->getLoadedVT(); 2744 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2745 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2746 LN0->getBasePtr(), LN0->getSrcValue(), 2747 LN0->getSrcValueOffset(), EVT, 2748 LN0->isVolatile(), 2749 LN0->getAlignment()); 2750 CombineTo(N, ExtLoad); 2751 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2752 ExtLoad.getValue(1)); 2753 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2754 } 2755 } 2756 2757 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2758 if (N0.getOpcode() == ISD::SETCC) { 2759 SDOperand SCC = 2760 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2761 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2762 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2763 if (SCC.Val) return SCC; 2764 } 2765 2766 return SDOperand(); 2767} 2768 2769SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2770 SDOperand N0 = N->getOperand(0); 2771 MVT::ValueType VT = N->getValueType(0); 2772 2773 // fold (zext c1) -> c1 2774 if (isa<ConstantSDNode>(N0)) 2775 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2776 // fold (zext (zext x)) -> (zext x) 2777 // fold (zext (aext x)) -> (zext x) 2778 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2779 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2780 2781 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2782 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2783 if (N0.getOpcode() == ISD::TRUNCATE) { 2784 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2785 if (NarrowLoad.Val) { 2786 if (NarrowLoad.Val != N0.Val) 2787 CombineTo(N0.Val, NarrowLoad); 2788 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2789 } 2790 } 2791 2792 // fold (zext (truncate x)) -> (and x, mask) 2793 if (N0.getOpcode() == ISD::TRUNCATE && 2794 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2795 SDOperand Op = N0.getOperand(0); 2796 if (Op.getValueType() < VT) { 2797 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2798 } else if (Op.getValueType() > VT) { 2799 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2800 } 2801 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2802 } 2803 2804 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2805 if (N0.getOpcode() == ISD::AND && 2806 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2807 N0.getOperand(1).getOpcode() == ISD::Constant) { 2808 SDOperand X = N0.getOperand(0).getOperand(0); 2809 if (X.getValueType() < VT) { 2810 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2811 } else if (X.getValueType() > VT) { 2812 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2813 } 2814 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2815 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2816 } 2817 2818 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2819 if (ISD::isNON_EXTLoad(N0.Val) && 2820 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2821 bool DoXform = true; 2822 SmallVector<SDNode*, 4> SetCCs; 2823 if (!N0.hasOneUse()) 2824 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2825 if (DoXform) { 2826 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2827 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2828 LN0->getBasePtr(), LN0->getSrcValue(), 2829 LN0->getSrcValueOffset(), 2830 N0.getValueType(), 2831 LN0->isVolatile(), 2832 LN0->getAlignment()); 2833 CombineTo(N, ExtLoad); 2834 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2835 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2836 // Extend SetCC uses if necessary. 2837 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2838 SDNode *SetCC = SetCCs[i]; 2839 SmallVector<SDOperand, 4> Ops; 2840 for (unsigned j = 0; j != 2; ++j) { 2841 SDOperand SOp = SetCC->getOperand(j); 2842 if (SOp == Trunc) 2843 Ops.push_back(ExtLoad); 2844 else 2845 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2846 } 2847 Ops.push_back(SetCC->getOperand(2)); 2848 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2849 &Ops[0], Ops.size())); 2850 } 2851 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2852 } 2853 } 2854 2855 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2856 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2857 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2858 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2859 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2860 MVT::ValueType EVT = LN0->getLoadedVT(); 2861 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2862 LN0->getBasePtr(), LN0->getSrcValue(), 2863 LN0->getSrcValueOffset(), EVT, 2864 LN0->isVolatile(), 2865 LN0->getAlignment()); 2866 CombineTo(N, ExtLoad); 2867 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2868 ExtLoad.getValue(1)); 2869 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2870 } 2871 2872 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2873 if (N0.getOpcode() == ISD::SETCC) { 2874 SDOperand SCC = 2875 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2876 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2877 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2878 if (SCC.Val) return SCC; 2879 } 2880 2881 return SDOperand(); 2882} 2883 2884SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2885 SDOperand N0 = N->getOperand(0); 2886 MVT::ValueType VT = N->getValueType(0); 2887 2888 // fold (aext c1) -> c1 2889 if (isa<ConstantSDNode>(N0)) 2890 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2891 // fold (aext (aext x)) -> (aext x) 2892 // fold (aext (zext x)) -> (zext x) 2893 // fold (aext (sext x)) -> (sext x) 2894 if (N0.getOpcode() == ISD::ANY_EXTEND || 2895 N0.getOpcode() == ISD::ZERO_EXTEND || 2896 N0.getOpcode() == ISD::SIGN_EXTEND) 2897 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2898 2899 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2900 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2901 if (N0.getOpcode() == ISD::TRUNCATE) { 2902 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2903 if (NarrowLoad.Val) { 2904 if (NarrowLoad.Val != N0.Val) 2905 CombineTo(N0.Val, NarrowLoad); 2906 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2907 } 2908 } 2909 2910 // fold (aext (truncate x)) 2911 if (N0.getOpcode() == ISD::TRUNCATE) { 2912 SDOperand TruncOp = N0.getOperand(0); 2913 if (TruncOp.getValueType() == VT) 2914 return TruncOp; // x iff x size == zext size. 2915 if (TruncOp.getValueType() > VT) 2916 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2917 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2918 } 2919 2920 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2921 if (N0.getOpcode() == ISD::AND && 2922 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2923 N0.getOperand(1).getOpcode() == ISD::Constant) { 2924 SDOperand X = N0.getOperand(0).getOperand(0); 2925 if (X.getValueType() < VT) { 2926 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2927 } else if (X.getValueType() > VT) { 2928 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2929 } 2930 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2931 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2932 } 2933 2934 // fold (aext (load x)) -> (aext (truncate (extload x))) 2935 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2936 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2937 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2938 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2939 LN0->getBasePtr(), LN0->getSrcValue(), 2940 LN0->getSrcValueOffset(), 2941 N0.getValueType(), 2942 LN0->isVolatile(), 2943 LN0->getAlignment()); 2944 CombineTo(N, ExtLoad); 2945 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2946 ExtLoad.getValue(1)); 2947 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2948 } 2949 2950 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2951 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2952 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2953 if (N0.getOpcode() == ISD::LOAD && 2954 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2955 N0.hasOneUse()) { 2956 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2957 MVT::ValueType EVT = LN0->getLoadedVT(); 2958 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2959 LN0->getChain(), LN0->getBasePtr(), 2960 LN0->getSrcValue(), 2961 LN0->getSrcValueOffset(), EVT, 2962 LN0->isVolatile(), 2963 LN0->getAlignment()); 2964 CombineTo(N, ExtLoad); 2965 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2966 ExtLoad.getValue(1)); 2967 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2968 } 2969 2970 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2971 if (N0.getOpcode() == ISD::SETCC) { 2972 SDOperand SCC = 2973 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2974 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2975 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2976 if (SCC.Val) 2977 return SCC; 2978 } 2979 2980 return SDOperand(); 2981} 2982 2983/// GetDemandedBits - See if the specified operand can be simplified with the 2984/// knowledge that only the bits specified by Mask are used. If so, return the 2985/// simpler operand, otherwise return a null SDOperand. 2986SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) { 2987 switch (V.getOpcode()) { 2988 default: break; 2989 case ISD::OR: 2990 case ISD::XOR: 2991 // If the LHS or RHS don't contribute bits to the or, drop them. 2992 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 2993 return V.getOperand(1); 2994 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 2995 return V.getOperand(0); 2996 break; 2997 case ISD::SRL: 2998 // Only look at single-use SRLs. 2999 if (!V.Val->hasOneUse()) 3000 break; 3001 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3002 // See if we can recursively simplify the LHS. 3003 unsigned Amt = RHSC->getValue(); 3004 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType()); 3005 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask); 3006 if (SimplifyLHS.Val) { 3007 return DAG.getNode(ISD::SRL, V.getValueType(), 3008 SimplifyLHS, V.getOperand(1)); 3009 } 3010 } 3011 } 3012 return SDOperand(); 3013} 3014 3015/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3016/// bits and then truncated to a narrower type and where N is a multiple 3017/// of number of bits of the narrower type, transform it to a narrower load 3018/// from address + N / num of bits of new type. If the result is to be 3019/// extended, also fold the extension to form a extending load. 3020SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3021 unsigned Opc = N->getOpcode(); 3022 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3023 SDOperand N0 = N->getOperand(0); 3024 MVT::ValueType VT = N->getValueType(0); 3025 MVT::ValueType EVT = N->getValueType(0); 3026 3027 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3028 // extended to VT. 3029 if (Opc == ISD::SIGN_EXTEND_INREG) { 3030 ExtType = ISD::SEXTLOAD; 3031 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3032 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3033 return SDOperand(); 3034 } 3035 3036 unsigned EVTBits = MVT::getSizeInBits(EVT); 3037 unsigned ShAmt = 0; 3038 bool CombineSRL = false; 3039 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3040 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3041 ShAmt = N01->getValue(); 3042 // Is the shift amount a multiple of size of VT? 3043 if ((ShAmt & (EVTBits-1)) == 0) { 3044 N0 = N0.getOperand(0); 3045 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3046 return SDOperand(); 3047 CombineSRL = true; 3048 } 3049 } 3050 } 3051 3052 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3053 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3054 // zero extended form: by shrinking the load, we lose track of the fact 3055 // that it is already zero extended. 3056 // FIXME: This should be reevaluated. 3057 VT != MVT::i1) { 3058 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3059 "Cannot truncate to larger type!"); 3060 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3061 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3062 // For big endian targets, we need to adjust the offset to the pointer to 3063 // load the correct bytes. 3064 if (!TLI.isLittleEndian()) { 3065 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3066 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3067 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3068 } 3069 uint64_t PtrOff = ShAmt / 8; 3070 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3071 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3072 DAG.getConstant(PtrOff, PtrType)); 3073 AddToWorkList(NewPtr.Val); 3074 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3075 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3076 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3077 LN0->isVolatile(), NewAlign) 3078 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3079 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3080 LN0->isVolatile(), NewAlign); 3081 AddToWorkList(N); 3082 if (CombineSRL) { 3083 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 3084 CombineTo(N->getOperand(0).Val, Load); 3085 } else 3086 CombineTo(N0.Val, Load, Load.getValue(1)); 3087 if (ShAmt) { 3088 if (Opc == ISD::SIGN_EXTEND_INREG) 3089 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3090 else 3091 return DAG.getNode(Opc, VT, Load); 3092 } 3093 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3094 } 3095 3096 return SDOperand(); 3097} 3098 3099 3100SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3101 SDOperand N0 = N->getOperand(0); 3102 SDOperand N1 = N->getOperand(1); 3103 MVT::ValueType VT = N->getValueType(0); 3104 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3105 unsigned EVTBits = MVT::getSizeInBits(EVT); 3106 3107 // fold (sext_in_reg c1) -> c1 3108 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3109 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3110 3111 // If the input is already sign extended, just drop the extension. 3112 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3113 return N0; 3114 3115 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3116 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3117 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3118 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3119 } 3120 3121 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3122 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 3123 return DAG.getZeroExtendInReg(N0, EVT); 3124 3125 // fold operands of sext_in_reg based on knowledge that the top bits are not 3126 // demanded. 3127 if (SimplifyDemandedBits(SDOperand(N, 0))) 3128 return SDOperand(N, 0); 3129 3130 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3131 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3132 SDOperand NarrowLoad = ReduceLoadWidth(N); 3133 if (NarrowLoad.Val) 3134 return NarrowLoad; 3135 3136 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3137 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3138 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3139 if (N0.getOpcode() == ISD::SRL) { 3140 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3141 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3142 // We can turn this into an SRA iff the input to the SRL is already sign 3143 // extended enough. 3144 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3145 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3146 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3147 } 3148 } 3149 3150 // fold (sext_inreg (extload x)) -> (sextload x) 3151 if (ISD::isEXTLoad(N0.Val) && 3152 ISD::isUNINDEXEDLoad(N0.Val) && 3153 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3154 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3155 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3156 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3157 LN0->getBasePtr(), LN0->getSrcValue(), 3158 LN0->getSrcValueOffset(), EVT, 3159 LN0->isVolatile(), 3160 LN0->getAlignment()); 3161 CombineTo(N, ExtLoad); 3162 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3163 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3164 } 3165 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3166 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3167 N0.hasOneUse() && 3168 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3169 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3170 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3171 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3172 LN0->getBasePtr(), LN0->getSrcValue(), 3173 LN0->getSrcValueOffset(), EVT, 3174 LN0->isVolatile(), 3175 LN0->getAlignment()); 3176 CombineTo(N, ExtLoad); 3177 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3178 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3179 } 3180 return SDOperand(); 3181} 3182 3183SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3184 SDOperand N0 = N->getOperand(0); 3185 MVT::ValueType VT = N->getValueType(0); 3186 3187 // noop truncate 3188 if (N0.getValueType() == N->getValueType(0)) 3189 return N0; 3190 // fold (truncate c1) -> c1 3191 if (isa<ConstantSDNode>(N0)) 3192 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3193 // fold (truncate (truncate x)) -> (truncate x) 3194 if (N0.getOpcode() == ISD::TRUNCATE) 3195 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3196 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3197 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3198 N0.getOpcode() == ISD::ANY_EXTEND) { 3199 if (N0.getOperand(0).getValueType() < VT) 3200 // if the source is smaller than the dest, we still need an extend 3201 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3202 else if (N0.getOperand(0).getValueType() > VT) 3203 // if the source is larger than the dest, than we just need the truncate 3204 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3205 else 3206 // if the source and dest are the same type, we can drop both the extend 3207 // and the truncate 3208 return N0.getOperand(0); 3209 } 3210 3211 // See if we can simplify the input to this truncate through knowledge that 3212 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3213 // -> trunc y 3214 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT)); 3215 if (Shorter.Val) 3216 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3217 3218 // fold (truncate (load x)) -> (smaller load x) 3219 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3220 return ReduceLoadWidth(N); 3221} 3222 3223SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3224 SDOperand N0 = N->getOperand(0); 3225 MVT::ValueType VT = N->getValueType(0); 3226 3227 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3228 // Only do this before legalize, since afterward the target may be depending 3229 // on the bitconvert. 3230 // First check to see if this is all constant. 3231 if (!AfterLegalize && 3232 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3233 MVT::isVector(VT)) { 3234 bool isSimple = true; 3235 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3236 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3237 N0.getOperand(i).getOpcode() != ISD::Constant && 3238 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3239 isSimple = false; 3240 break; 3241 } 3242 3243 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3244 assert(!MVT::isVector(DestEltVT) && 3245 "Element type of vector ValueType must not be vector!"); 3246 if (isSimple) { 3247 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3248 } 3249 } 3250 3251 // If the input is a constant, let getNode() fold it. 3252 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3253 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3254 if (Res.Val != N) return Res; 3255 } 3256 3257 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3258 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3259 3260 // fold (conv (load x)) -> (load (conv*)x) 3261 // If the resultant load doesn't need a higher alignment than the original! 3262 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3263 TLI.isOperationLegal(ISD::LOAD, VT)) { 3264 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3265 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3266 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3267 unsigned OrigAlign = LN0->getAlignment(); 3268 if (Align <= OrigAlign) { 3269 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3270 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3271 LN0->isVolatile(), Align); 3272 AddToWorkList(N); 3273 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3274 Load.getValue(1)); 3275 return Load; 3276 } 3277 } 3278 3279 return SDOperand(); 3280} 3281 3282/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3283/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3284/// destination element value type. 3285SDOperand DAGCombiner:: 3286ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3287 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3288 3289 // If this is already the right type, we're done. 3290 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3291 3292 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3293 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3294 3295 // If this is a conversion of N elements of one type to N elements of another 3296 // type, convert each element. This handles FP<->INT cases. 3297 if (SrcBitSize == DstBitSize) { 3298 SmallVector<SDOperand, 8> Ops; 3299 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3300 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3301 AddToWorkList(Ops.back().Val); 3302 } 3303 MVT::ValueType VT = 3304 MVT::getVectorType(DstEltVT, 3305 MVT::getVectorNumElements(BV->getValueType(0))); 3306 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3307 } 3308 3309 // Otherwise, we're growing or shrinking the elements. To avoid having to 3310 // handle annoying details of growing/shrinking FP values, we convert them to 3311 // int first. 3312 if (MVT::isFloatingPoint(SrcEltVT)) { 3313 // Convert the input float vector to a int vector where the elements are the 3314 // same sizes. 3315 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3316 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3317 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3318 SrcEltVT = IntVT; 3319 } 3320 3321 // Now we know the input is an integer vector. If the output is a FP type, 3322 // convert to integer first, then to FP of the right size. 3323 if (MVT::isFloatingPoint(DstEltVT)) { 3324 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3325 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3326 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3327 3328 // Next, convert to FP elements of the same size. 3329 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3330 } 3331 3332 // Okay, we know the src/dst types are both integers of differing types. 3333 // Handling growing first. 3334 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3335 if (SrcBitSize < DstBitSize) { 3336 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3337 3338 SmallVector<SDOperand, 8> Ops; 3339 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3340 i += NumInputsPerOutput) { 3341 bool isLE = TLI.isLittleEndian(); 3342 uint64_t NewBits = 0; 3343 bool EltIsUndef = true; 3344 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3345 // Shift the previously computed bits over. 3346 NewBits <<= SrcBitSize; 3347 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3348 if (Op.getOpcode() == ISD::UNDEF) continue; 3349 EltIsUndef = false; 3350 3351 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3352 } 3353 3354 if (EltIsUndef) 3355 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3356 else 3357 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3358 } 3359 3360 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3361 Ops.size()); 3362 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3363 } 3364 3365 // Finally, this must be the case where we are shrinking elements: each input 3366 // turns into multiple outputs. 3367 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3368 SmallVector<SDOperand, 8> Ops; 3369 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3370 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3371 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3372 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3373 continue; 3374 } 3375 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3376 3377 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3378 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3379 OpVal >>= DstBitSize; 3380 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3381 } 3382 3383 // For big endian targets, swap the order of the pieces of each element. 3384 if (!TLI.isLittleEndian()) 3385 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3386 } 3387 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3388 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3389} 3390 3391 3392 3393SDOperand DAGCombiner::visitFADD(SDNode *N) { 3394 SDOperand N0 = N->getOperand(0); 3395 SDOperand N1 = N->getOperand(1); 3396 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3397 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3398 MVT::ValueType VT = N->getValueType(0); 3399 3400 // fold vector ops 3401 if (MVT::isVector(VT)) { 3402 SDOperand FoldedVOp = SimplifyVBinOp(N); 3403 if (FoldedVOp.Val) return FoldedVOp; 3404 } 3405 3406 // fold (fadd c1, c2) -> c1+c2 3407 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3408 return DAG.getNode(ISD::FADD, VT, N0, N1); 3409 // canonicalize constant to RHS 3410 if (N0CFP && !N1CFP) 3411 return DAG.getNode(ISD::FADD, VT, N1, N0); 3412 // fold (A + (-B)) -> A-B 3413 if (isNegatibleForFree(N1) == 2) 3414 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3415 // fold ((-A) + B) -> B-A 3416 if (isNegatibleForFree(N0) == 2) 3417 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3418 3419 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3420 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3421 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3422 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3423 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3424 3425 return SDOperand(); 3426} 3427 3428SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3429 SDOperand N0 = N->getOperand(0); 3430 SDOperand N1 = N->getOperand(1); 3431 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3432 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3433 MVT::ValueType VT = N->getValueType(0); 3434 3435 // fold vector ops 3436 if (MVT::isVector(VT)) { 3437 SDOperand FoldedVOp = SimplifyVBinOp(N); 3438 if (FoldedVOp.Val) return FoldedVOp; 3439 } 3440 3441 // fold (fsub c1, c2) -> c1-c2 3442 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3443 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3444 // fold (0-B) -> -B 3445 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3446 if (isNegatibleForFree(N1)) 3447 return GetNegatedExpression(N1, DAG); 3448 return DAG.getNode(ISD::FNEG, VT, N1); 3449 } 3450 // fold (A-(-B)) -> A+B 3451 if (isNegatibleForFree(N1)) 3452 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3453 3454 return SDOperand(); 3455} 3456 3457SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3458 SDOperand N0 = N->getOperand(0); 3459 SDOperand N1 = N->getOperand(1); 3460 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3461 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3462 MVT::ValueType VT = N->getValueType(0); 3463 3464 // fold vector ops 3465 if (MVT::isVector(VT)) { 3466 SDOperand FoldedVOp = SimplifyVBinOp(N); 3467 if (FoldedVOp.Val) return FoldedVOp; 3468 } 3469 3470 // fold (fmul c1, c2) -> c1*c2 3471 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3472 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3473 // canonicalize constant to RHS 3474 if (N0CFP && !N1CFP) 3475 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3476 // fold (fmul X, 2.0) -> (fadd X, X) 3477 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3478 return DAG.getNode(ISD::FADD, VT, N0, N0); 3479 // fold (fmul X, -1.0) -> (fneg X) 3480 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3481 return DAG.getNode(ISD::FNEG, VT, N0); 3482 3483 // -X * -Y -> X*Y 3484 if (char LHSNeg = isNegatibleForFree(N0)) { 3485 if (char RHSNeg = isNegatibleForFree(N1)) { 3486 // Both can be negated for free, check to see if at least one is cheaper 3487 // negated. 3488 if (LHSNeg == 2 || RHSNeg == 2) 3489 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3490 GetNegatedExpression(N1, DAG)); 3491 } 3492 } 3493 3494 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3495 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3496 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3497 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3498 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3499 3500 return SDOperand(); 3501} 3502 3503SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3504 SDOperand N0 = N->getOperand(0); 3505 SDOperand N1 = N->getOperand(1); 3506 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3507 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3508 MVT::ValueType VT = N->getValueType(0); 3509 3510 // fold vector ops 3511 if (MVT::isVector(VT)) { 3512 SDOperand FoldedVOp = SimplifyVBinOp(N); 3513 if (FoldedVOp.Val) return FoldedVOp; 3514 } 3515 3516 // fold (fdiv c1, c2) -> c1/c2 3517 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3518 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3519 3520 3521 // -X / -Y -> X*Y 3522 if (char LHSNeg = isNegatibleForFree(N0)) { 3523 if (char RHSNeg = isNegatibleForFree(N1)) { 3524 // Both can be negated for free, check to see if at least one is cheaper 3525 // negated. 3526 if (LHSNeg == 2 || RHSNeg == 2) 3527 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3528 GetNegatedExpression(N1, DAG)); 3529 } 3530 } 3531 3532 return SDOperand(); 3533} 3534 3535SDOperand DAGCombiner::visitFREM(SDNode *N) { 3536 SDOperand N0 = N->getOperand(0); 3537 SDOperand N1 = N->getOperand(1); 3538 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3539 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3540 MVT::ValueType VT = N->getValueType(0); 3541 3542 // fold (frem c1, c2) -> fmod(c1,c2) 3543 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3544 return DAG.getNode(ISD::FREM, VT, N0, N1); 3545 3546 return SDOperand(); 3547} 3548 3549SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3550 SDOperand N0 = N->getOperand(0); 3551 SDOperand N1 = N->getOperand(1); 3552 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3553 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3554 MVT::ValueType VT = N->getValueType(0); 3555 3556 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3557 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3558 3559 if (N1CFP) { 3560 const APFloat& V = N1CFP->getValueAPF(); 3561 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3562 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3563 if (!V.isNegative()) 3564 return DAG.getNode(ISD::FABS, VT, N0); 3565 else 3566 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3567 } 3568 3569 // copysign(fabs(x), y) -> copysign(x, y) 3570 // copysign(fneg(x), y) -> copysign(x, y) 3571 // copysign(copysign(x,z), y) -> copysign(x, y) 3572 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3573 N0.getOpcode() == ISD::FCOPYSIGN) 3574 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3575 3576 // copysign(x, abs(y)) -> abs(x) 3577 if (N1.getOpcode() == ISD::FABS) 3578 return DAG.getNode(ISD::FABS, VT, N0); 3579 3580 // copysign(x, copysign(y,z)) -> copysign(x, z) 3581 if (N1.getOpcode() == ISD::FCOPYSIGN) 3582 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3583 3584 // copysign(x, fp_extend(y)) -> copysign(x, y) 3585 // copysign(x, fp_round(y)) -> copysign(x, y) 3586 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3587 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3588 3589 return SDOperand(); 3590} 3591 3592 3593 3594SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3595 SDOperand N0 = N->getOperand(0); 3596 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3597 MVT::ValueType VT = N->getValueType(0); 3598 3599 // fold (sint_to_fp c1) -> c1fp 3600 if (N0C && N0.getValueType() != MVT::ppcf128) 3601 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3602 return SDOperand(); 3603} 3604 3605SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3606 SDOperand N0 = N->getOperand(0); 3607 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3608 MVT::ValueType VT = N->getValueType(0); 3609 3610 // fold (uint_to_fp c1) -> c1fp 3611 if (N0C && N0.getValueType() != MVT::ppcf128) 3612 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3613 return SDOperand(); 3614} 3615 3616SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3617 SDOperand N0 = N->getOperand(0); 3618 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3619 MVT::ValueType VT = N->getValueType(0); 3620 3621 // fold (fp_to_sint c1fp) -> c1 3622 if (N0CFP) 3623 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3624 return SDOperand(); 3625} 3626 3627SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3628 SDOperand N0 = N->getOperand(0); 3629 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3630 MVT::ValueType VT = N->getValueType(0); 3631 3632 // fold (fp_to_uint c1fp) -> c1 3633 if (N0CFP && VT != MVT::ppcf128) 3634 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3635 return SDOperand(); 3636} 3637 3638SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3639 SDOperand N0 = N->getOperand(0); 3640 SDOperand N1 = N->getOperand(1); 3641 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3642 MVT::ValueType VT = N->getValueType(0); 3643 3644 // fold (fp_round c1fp) -> c1fp 3645 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3646 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3647 3648 // fold (fp_round (fp_extend x)) -> x 3649 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3650 return N0.getOperand(0); 3651 3652 // fold (fp_round (fp_round x)) -> (fp_round x) 3653 if (N0.getOpcode() == ISD::FP_ROUND) { 3654 // This is a value preserving truncation if both round's are. 3655 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3656 N0.Val->getConstantOperandVal(1) == 1; 3657 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3658 DAG.getIntPtrConstant(IsTrunc)); 3659 } 3660 3661 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3662 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3663 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3664 AddToWorkList(Tmp.Val); 3665 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3666 } 3667 3668 return SDOperand(); 3669} 3670 3671SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3672 SDOperand N0 = N->getOperand(0); 3673 MVT::ValueType VT = N->getValueType(0); 3674 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3675 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3676 3677 // fold (fp_round_inreg c1fp) -> c1fp 3678 if (N0CFP) { 3679 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3680 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3681 } 3682 return SDOperand(); 3683} 3684 3685SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3686 SDOperand N0 = N->getOperand(0); 3687 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3688 MVT::ValueType VT = N->getValueType(0); 3689 3690 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3691 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND) 3692 return SDOperand(); 3693 3694 // fold (fp_extend c1fp) -> c1fp 3695 if (N0CFP && VT != MVT::ppcf128) 3696 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3697 3698 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3699 // value of X. 3700 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3701 SDOperand In = N0.getOperand(0); 3702 if (In.getValueType() == VT) return In; 3703 if (VT < In.getValueType()) 3704 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3705 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3706 } 3707 3708 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3709 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3710 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3711 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3712 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3713 LN0->getBasePtr(), LN0->getSrcValue(), 3714 LN0->getSrcValueOffset(), 3715 N0.getValueType(), 3716 LN0->isVolatile(), 3717 LN0->getAlignment()); 3718 CombineTo(N, ExtLoad); 3719 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3720 DAG.getIntPtrConstant(1)), 3721 ExtLoad.getValue(1)); 3722 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3723 } 3724 3725 3726 return SDOperand(); 3727} 3728 3729SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3730 SDOperand N0 = N->getOperand(0); 3731 3732 if (isNegatibleForFree(N0)) 3733 return GetNegatedExpression(N0, DAG); 3734 3735 return SDOperand(); 3736} 3737 3738SDOperand DAGCombiner::visitFABS(SDNode *N) { 3739 SDOperand N0 = N->getOperand(0); 3740 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3741 MVT::ValueType VT = N->getValueType(0); 3742 3743 // fold (fabs c1) -> fabs(c1) 3744 if (N0CFP && VT != MVT::ppcf128) 3745 return DAG.getNode(ISD::FABS, VT, N0); 3746 // fold (fabs (fabs x)) -> (fabs x) 3747 if (N0.getOpcode() == ISD::FABS) 3748 return N->getOperand(0); 3749 // fold (fabs (fneg x)) -> (fabs x) 3750 // fold (fabs (fcopysign x, y)) -> (fabs x) 3751 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3752 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3753 3754 return SDOperand(); 3755} 3756 3757SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3758 SDOperand Chain = N->getOperand(0); 3759 SDOperand N1 = N->getOperand(1); 3760 SDOperand N2 = N->getOperand(2); 3761 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3762 3763 // never taken branch, fold to chain 3764 if (N1C && N1C->isNullValue()) 3765 return Chain; 3766 // unconditional branch 3767 if (N1C && N1C->getValue() == 1) 3768 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3769 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3770 // on the target. 3771 if (N1.getOpcode() == ISD::SETCC && 3772 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3773 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3774 N1.getOperand(0), N1.getOperand(1), N2); 3775 } 3776 return SDOperand(); 3777} 3778 3779// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3780// 3781SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3782 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3783 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3784 3785 // Use SimplifySetCC to simplify SETCC's. 3786 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3787 if (Simp.Val) AddToWorkList(Simp.Val); 3788 3789 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3790 3791 // fold br_cc true, dest -> br dest (unconditional branch) 3792 if (SCCC && SCCC->getValue()) 3793 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3794 N->getOperand(4)); 3795 // fold br_cc false, dest -> unconditional fall through 3796 if (SCCC && SCCC->isNullValue()) 3797 return N->getOperand(0); 3798 3799 // fold to a simpler setcc 3800 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3801 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3802 Simp.getOperand(2), Simp.getOperand(0), 3803 Simp.getOperand(1), N->getOperand(4)); 3804 return SDOperand(); 3805} 3806 3807 3808/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3809/// pre-indexed load / store when the base pointer is a add or subtract 3810/// and it has other uses besides the load / store. After the 3811/// transformation, the new indexed load / store has effectively folded 3812/// the add / subtract in and all of its other uses are redirected to the 3813/// new load / store. 3814bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3815 if (!AfterLegalize) 3816 return false; 3817 3818 bool isLoad = true; 3819 SDOperand Ptr; 3820 MVT::ValueType VT; 3821 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3822 if (LD->isIndexed()) 3823 return false; 3824 VT = LD->getLoadedVT(); 3825 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3826 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3827 return false; 3828 Ptr = LD->getBasePtr(); 3829 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3830 if (ST->isIndexed()) 3831 return false; 3832 VT = ST->getStoredVT(); 3833 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3834 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3835 return false; 3836 Ptr = ST->getBasePtr(); 3837 isLoad = false; 3838 } else 3839 return false; 3840 3841 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3842 // out. There is no reason to make this a preinc/predec. 3843 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3844 Ptr.Val->hasOneUse()) 3845 return false; 3846 3847 // Ask the target to do addressing mode selection. 3848 SDOperand BasePtr; 3849 SDOperand Offset; 3850 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3851 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3852 return false; 3853 // Don't create a indexed load / store with zero offset. 3854 if (isa<ConstantSDNode>(Offset) && 3855 cast<ConstantSDNode>(Offset)->getValue() == 0) 3856 return false; 3857 3858 // Try turning it into a pre-indexed load / store except when: 3859 // 1) The new base ptr is a frame index. 3860 // 2) If N is a store and the new base ptr is either the same as or is a 3861 // predecessor of the value being stored. 3862 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3863 // that would create a cycle. 3864 // 4) All uses are load / store ops that use it as old base ptr. 3865 3866 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3867 // (plus the implicit offset) to a register to preinc anyway. 3868 if (isa<FrameIndexSDNode>(BasePtr)) 3869 return false; 3870 3871 // Check #2. 3872 if (!isLoad) { 3873 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3874 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3875 return false; 3876 } 3877 3878 // Now check for #3 and #4. 3879 bool RealUse = false; 3880 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3881 E = Ptr.Val->use_end(); I != E; ++I) { 3882 SDNode *Use = *I; 3883 if (Use == N) 3884 continue; 3885 if (Use->isPredecessor(N)) 3886 return false; 3887 3888 if (!((Use->getOpcode() == ISD::LOAD && 3889 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3890 (Use->getOpcode() == ISD::STORE) && 3891 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3892 RealUse = true; 3893 } 3894 if (!RealUse) 3895 return false; 3896 3897 SDOperand Result; 3898 if (isLoad) 3899 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3900 else 3901 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3902 ++PreIndexedNodes; 3903 ++NodesCombined; 3904 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 3905 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3906 DOUT << '\n'; 3907 std::vector<SDNode*> NowDead; 3908 if (isLoad) { 3909 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3910 &NowDead); 3911 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3912 &NowDead); 3913 } else { 3914 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3915 &NowDead); 3916 } 3917 3918 // Nodes can end up on the worklist more than once. Make sure we do 3919 // not process a node that has been replaced. 3920 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3921 removeFromWorkList(NowDead[i]); 3922 // Finally, since the node is now dead, remove it from the graph. 3923 DAG.DeleteNode(N); 3924 3925 // Replace the uses of Ptr with uses of the updated base value. 3926 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3927 &NowDead); 3928 removeFromWorkList(Ptr.Val); 3929 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3930 removeFromWorkList(NowDead[i]); 3931 DAG.DeleteNode(Ptr.Val); 3932 3933 return true; 3934} 3935 3936/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3937/// add / sub of the base pointer node into a post-indexed load / store. 3938/// The transformation folded the add / subtract into the new indexed 3939/// load / store effectively and all of its uses are redirected to the 3940/// new load / store. 3941bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3942 if (!AfterLegalize) 3943 return false; 3944 3945 bool isLoad = true; 3946 SDOperand Ptr; 3947 MVT::ValueType VT; 3948 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3949 if (LD->isIndexed()) 3950 return false; 3951 VT = LD->getLoadedVT(); 3952 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3953 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3954 return false; 3955 Ptr = LD->getBasePtr(); 3956 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3957 if (ST->isIndexed()) 3958 return false; 3959 VT = ST->getStoredVT(); 3960 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3961 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3962 return false; 3963 Ptr = ST->getBasePtr(); 3964 isLoad = false; 3965 } else 3966 return false; 3967 3968 if (Ptr.Val->hasOneUse()) 3969 return false; 3970 3971 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3972 E = Ptr.Val->use_end(); I != E; ++I) { 3973 SDNode *Op = *I; 3974 if (Op == N || 3975 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3976 continue; 3977 3978 SDOperand BasePtr; 3979 SDOperand Offset; 3980 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3981 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3982 if (Ptr == Offset) 3983 std::swap(BasePtr, Offset); 3984 if (Ptr != BasePtr) 3985 continue; 3986 // Don't create a indexed load / store with zero offset. 3987 if (isa<ConstantSDNode>(Offset) && 3988 cast<ConstantSDNode>(Offset)->getValue() == 0) 3989 continue; 3990 3991 // Try turning it into a post-indexed load / store except when 3992 // 1) All uses are load / store ops that use it as base ptr. 3993 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3994 // nor a successor of N. Otherwise, if Op is folded that would 3995 // create a cycle. 3996 3997 // Check for #1. 3998 bool TryNext = false; 3999 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4000 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4001 SDNode *Use = *II; 4002 if (Use == Ptr.Val) 4003 continue; 4004 4005 // If all the uses are load / store addresses, then don't do the 4006 // transformation. 4007 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4008 bool RealUse = false; 4009 for (SDNode::use_iterator III = Use->use_begin(), 4010 EEE = Use->use_end(); III != EEE; ++III) { 4011 SDNode *UseUse = *III; 4012 if (!((UseUse->getOpcode() == ISD::LOAD && 4013 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4014 (UseUse->getOpcode() == ISD::STORE) && 4015 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 4016 RealUse = true; 4017 } 4018 4019 if (!RealUse) { 4020 TryNext = true; 4021 break; 4022 } 4023 } 4024 } 4025 if (TryNext) 4026 continue; 4027 4028 // Check for #2 4029 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 4030 SDOperand Result = isLoad 4031 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4032 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4033 ++PostIndexedNodes; 4034 ++NodesCombined; 4035 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4036 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4037 DOUT << '\n'; 4038 std::vector<SDNode*> NowDead; 4039 if (isLoad) { 4040 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4041 &NowDead); 4042 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4043 &NowDead); 4044 } else { 4045 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4046 &NowDead); 4047 } 4048 4049 // Nodes can end up on the worklist more than once. Make sure we do 4050 // not process a node that has been replaced. 4051 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4052 removeFromWorkList(NowDead[i]); 4053 // Finally, since the node is now dead, remove it from the graph. 4054 DAG.DeleteNode(N); 4055 4056 // Replace the uses of Use with uses of the updated base value. 4057 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4058 Result.getValue(isLoad ? 1 : 0), 4059 &NowDead); 4060 removeFromWorkList(Op); 4061 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4062 removeFromWorkList(NowDead[i]); 4063 DAG.DeleteNode(Op); 4064 4065 return true; 4066 } 4067 } 4068 } 4069 return false; 4070} 4071 4072/// InferAlignment - If we can infer some alignment information from this 4073/// pointer, return it. 4074static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4075 // If this is a direct reference to a stack slot, use information about the 4076 // stack slot's alignment. 4077 int FrameIdx = 1 << 31; 4078 int64_t FrameOffset = 0; 4079 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4080 FrameIdx = FI->getIndex(); 4081 } else if (Ptr.getOpcode() == ISD::ADD && 4082 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4083 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4084 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4085 FrameOffset = Ptr.getConstantOperandVal(1); 4086 } 4087 4088 if (FrameIdx != (1 << 31)) { 4089 // FIXME: Handle FI+CST. 4090 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4091 if (MFI.isFixedObjectIndex(FrameIdx)) { 4092 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4093 4094 // The alignment of the frame index can be determined from its offset from 4095 // the incoming frame position. If the frame object is at offset 32 and 4096 // the stack is guaranteed to be 16-byte aligned, then we know that the 4097 // object is 16-byte aligned. 4098 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4099 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4100 4101 // Finally, the frame object itself may have a known alignment. Factor 4102 // the alignment + offset into a new alignment. For example, if we know 4103 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4104 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4105 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4106 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4107 FrameOffset); 4108 return std::max(Align, FIInfoAlign); 4109 } 4110 } 4111 4112 return 0; 4113} 4114 4115SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4116 LoadSDNode *LD = cast<LoadSDNode>(N); 4117 SDOperand Chain = LD->getChain(); 4118 SDOperand Ptr = LD->getBasePtr(); 4119 4120 // Try to infer better alignment information than the load already has. 4121 if (LD->isUnindexed()) { 4122 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4123 if (Align > LD->getAlignment()) 4124 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4125 Chain, Ptr, LD->getSrcValue(), 4126 LD->getSrcValueOffset(), LD->getLoadedVT(), 4127 LD->isVolatile(), Align); 4128 } 4129 } 4130 4131 4132 // If load is not volatile and there are no uses of the loaded value (and 4133 // the updated indexed value in case of indexed loads), change uses of the 4134 // chain value into uses of the chain input (i.e. delete the dead load). 4135 if (!LD->isVolatile()) { 4136 if (N->getValueType(1) == MVT::Other) { 4137 // Unindexed loads. 4138 if (N->hasNUsesOfValue(0, 0)) { 4139 // It's not safe to use the two value CombineTo variant here. e.g. 4140 // v1, chain2 = load chain1, loc 4141 // v2, chain3 = load chain2, loc 4142 // v3 = add v2, c 4143 // Now we replace use of chain2 with chain1. This makes the second load 4144 // isomorphic to the one we are deleting, and thus makes this load live. 4145 std::vector<SDNode*> NowDead; 4146 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4147 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4148 DOUT << "\n"; 4149 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &NowDead); 4150 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4151 removeFromWorkList(NowDead[i]); 4152 if (N->use_empty()) { 4153 removeFromWorkList(N); 4154 DAG.DeleteNode(N); 4155 } 4156 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4157 } 4158 } else { 4159 // Indexed loads. 4160 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4161 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4162 std::vector<SDNode*> NowDead; 4163 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4164 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4165 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4166 DOUT << " and 2 other values\n"; 4167 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &NowDead); 4168 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4169 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4170 &NowDead); 4171 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &NowDead); 4172 removeFromWorkList(N); 4173 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4174 removeFromWorkList(NowDead[i]); 4175 DAG.DeleteNode(N); 4176 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4177 } 4178 } 4179 } 4180 4181 // If this load is directly stored, replace the load value with the stored 4182 // value. 4183 // TODO: Handle store large -> read small portion. 4184 // TODO: Handle TRUNCSTORE/LOADEXT 4185 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4186 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4187 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4188 if (PrevST->getBasePtr() == Ptr && 4189 PrevST->getValue().getValueType() == N->getValueType(0)) 4190 return CombineTo(N, Chain.getOperand(1), Chain); 4191 } 4192 } 4193 4194 if (CombinerAA) { 4195 // Walk up chain skipping non-aliasing memory nodes. 4196 SDOperand BetterChain = FindBetterChain(N, Chain); 4197 4198 // If there is a better chain. 4199 if (Chain != BetterChain) { 4200 SDOperand ReplLoad; 4201 4202 // Replace the chain to void dependency. 4203 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4204 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4205 LD->getSrcValue(), LD->getSrcValueOffset(), 4206 LD->isVolatile(), LD->getAlignment()); 4207 } else { 4208 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4209 LD->getValueType(0), 4210 BetterChain, Ptr, LD->getSrcValue(), 4211 LD->getSrcValueOffset(), 4212 LD->getLoadedVT(), 4213 LD->isVolatile(), 4214 LD->getAlignment()); 4215 } 4216 4217 // Create token factor to keep old chain connected. 4218 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4219 Chain, ReplLoad.getValue(1)); 4220 4221 // Replace uses with load result and token factor. Don't add users 4222 // to work list. 4223 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4224 } 4225 } 4226 4227 // Try transforming N to an indexed load. 4228 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4229 return SDOperand(N, 0); 4230 4231 return SDOperand(); 4232} 4233 4234 4235SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4236 StoreSDNode *ST = cast<StoreSDNode>(N); 4237 SDOperand Chain = ST->getChain(); 4238 SDOperand Value = ST->getValue(); 4239 SDOperand Ptr = ST->getBasePtr(); 4240 4241 // Try to infer better alignment information than the store already has. 4242 if (ST->isUnindexed()) { 4243 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4244 if (Align > ST->getAlignment()) 4245 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4246 ST->getSrcValueOffset(), ST->getStoredVT(), 4247 ST->isVolatile(), Align); 4248 } 4249 } 4250 4251 // If this is a store of a bit convert, store the input value if the 4252 // resultant store does not need a higher alignment than the original. 4253 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4254 ST->isUnindexed()) { 4255 unsigned Align = ST->getAlignment(); 4256 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4257 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4258 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4259 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4260 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4261 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4262 } 4263 4264 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4265 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4266 if (Value.getOpcode() != ISD::TargetConstantFP) { 4267 SDOperand Tmp; 4268 switch (CFP->getValueType(0)) { 4269 default: assert(0 && "Unknown FP type"); 4270 case MVT::f80: // We don't do this for these yet. 4271 case MVT::f128: 4272 case MVT::ppcf128: 4273 break; 4274 case MVT::f32: 4275 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4276 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4277 convertToAPInt().getZExtValue(), MVT::i32); 4278 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4279 ST->getSrcValueOffset(), ST->isVolatile(), 4280 ST->getAlignment()); 4281 } 4282 break; 4283 case MVT::f64: 4284 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4285 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4286 getZExtValue(), MVT::i64); 4287 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4288 ST->getSrcValueOffset(), ST->isVolatile(), 4289 ST->getAlignment()); 4290 } else if (TLI.isTypeLegal(MVT::i32)) { 4291 // Many FP stores are not made apparent until after legalize, e.g. for 4292 // argument passing. Since this is so common, custom legalize the 4293 // 64-bit integer store into two 32-bit stores. 4294 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4295 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4296 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4297 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 4298 4299 int SVOffset = ST->getSrcValueOffset(); 4300 unsigned Alignment = ST->getAlignment(); 4301 bool isVolatile = ST->isVolatile(); 4302 4303 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4304 ST->getSrcValueOffset(), 4305 isVolatile, ST->getAlignment()); 4306 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4307 DAG.getConstant(4, Ptr.getValueType())); 4308 SVOffset += 4; 4309 Alignment = MinAlign(Alignment, 4U); 4310 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4311 SVOffset, isVolatile, Alignment); 4312 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4313 } 4314 break; 4315 } 4316 } 4317 } 4318 4319 if (CombinerAA) { 4320 // Walk up chain skipping non-aliasing memory nodes. 4321 SDOperand BetterChain = FindBetterChain(N, Chain); 4322 4323 // If there is a better chain. 4324 if (Chain != BetterChain) { 4325 // Replace the chain to avoid dependency. 4326 SDOperand ReplStore; 4327 if (ST->isTruncatingStore()) { 4328 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4329 ST->getSrcValue(),ST->getSrcValueOffset(), 4330 ST->getStoredVT(), 4331 ST->isVolatile(), ST->getAlignment()); 4332 } else { 4333 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4334 ST->getSrcValue(), ST->getSrcValueOffset(), 4335 ST->isVolatile(), ST->getAlignment()); 4336 } 4337 4338 // Create token to keep both nodes around. 4339 SDOperand Token = 4340 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4341 4342 // Don't add users to work list. 4343 return CombineTo(N, Token, false); 4344 } 4345 } 4346 4347 // Try transforming N to an indexed store. 4348 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4349 return SDOperand(N, 0); 4350 4351 // FIXME: is there such a thing as a truncating indexed store? 4352 if (ST->isTruncatingStore() && ST->isUnindexed() && 4353 MVT::isInteger(Value.getValueType())) { 4354 // See if we can simplify the input to this truncstore with knowledge that 4355 // only the low bits are being used. For example: 4356 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4357 SDOperand Shorter = 4358 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())); 4359 AddToWorkList(Value.Val); 4360 if (Shorter.Val) 4361 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4362 ST->getSrcValueOffset(), ST->getStoredVT(), 4363 ST->isVolatile(), ST->getAlignment()); 4364 4365 // Otherwise, see if we can simplify the operation with 4366 // SimplifyDemandedBits, which only works if the value has a single use. 4367 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()))) 4368 return SDOperand(N, 0); 4369 } 4370 4371 // If this is a load followed by a store to the same location, then the store 4372 // is dead/noop. 4373 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4374 if (Ld->getBasePtr() == Ptr && ST->getStoredVT() == Ld->getLoadedVT() && 4375 ST->isUnindexed() && !ST->isVolatile() && 4376 // There can't be any side effects between the load and store, such as 4377 // a call or store. 4378 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4379 // The store is dead, remove it. 4380 return Chain; 4381 } 4382 } 4383 4384 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4385 // truncating store. We can do this even if this is already a truncstore. 4386 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4387 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) && 4388 Value.Val->hasOneUse() && ST->isUnindexed() && 4389 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4390 ST->getStoredVT())) { 4391 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4392 ST->getSrcValueOffset(), ST->getStoredVT(), 4393 ST->isVolatile(), ST->getAlignment()); 4394 } 4395 4396 return SDOperand(); 4397} 4398 4399SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4400 SDOperand InVec = N->getOperand(0); 4401 SDOperand InVal = N->getOperand(1); 4402 SDOperand EltNo = N->getOperand(2); 4403 4404 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4405 // vector with the inserted element. 4406 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4407 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4408 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4409 if (Elt < Ops.size()) 4410 Ops[Elt] = InVal; 4411 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4412 &Ops[0], Ops.size()); 4413 } 4414 4415 return SDOperand(); 4416} 4417 4418SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4419 SDOperand InVec = N->getOperand(0); 4420 SDOperand EltNo = N->getOperand(1); 4421 4422 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4423 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4424 if (isa<ConstantSDNode>(EltNo)) { 4425 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4426 bool NewLoad = false; 4427 if (Elt == 0) { 4428 MVT::ValueType VT = InVec.getValueType(); 4429 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4430 MVT::ValueType LVT = EVT; 4431 unsigned NumElts = MVT::getVectorNumElements(VT); 4432 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4433 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4434 if (!MVT::isVector(BCVT) || 4435 NumElts != MVT::getVectorNumElements(BCVT)) 4436 return SDOperand(); 4437 InVec = InVec.getOperand(0); 4438 EVT = MVT::getVectorElementType(BCVT); 4439 NewLoad = true; 4440 } 4441 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4442 InVec.getOperand(0).getValueType() == EVT && 4443 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4444 InVec.getOperand(0).hasOneUse()) { 4445 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4446 unsigned Align = LN0->getAlignment(); 4447 if (NewLoad) { 4448 // Check the resultant load doesn't need a higher alignment than the 4449 // original load. 4450 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4451 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4452 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4453 return SDOperand(); 4454 Align = NewAlign; 4455 } 4456 4457 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4458 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4459 LN0->isVolatile(), Align); 4460 } 4461 } 4462 } 4463 return SDOperand(); 4464} 4465 4466 4467SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4468 unsigned NumInScalars = N->getNumOperands(); 4469 MVT::ValueType VT = N->getValueType(0); 4470 unsigned NumElts = MVT::getVectorNumElements(VT); 4471 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4472 4473 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4474 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4475 // at most two distinct vectors, turn this into a shuffle node. 4476 SDOperand VecIn1, VecIn2; 4477 for (unsigned i = 0; i != NumInScalars; ++i) { 4478 // Ignore undef inputs. 4479 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4480 4481 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4482 // constant index, bail out. 4483 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4484 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4485 VecIn1 = VecIn2 = SDOperand(0, 0); 4486 break; 4487 } 4488 4489 // If the input vector type disagrees with the result of the build_vector, 4490 // we can't make a shuffle. 4491 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4492 if (ExtractedFromVec.getValueType() != VT) { 4493 VecIn1 = VecIn2 = SDOperand(0, 0); 4494 break; 4495 } 4496 4497 // Otherwise, remember this. We allow up to two distinct input vectors. 4498 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4499 continue; 4500 4501 if (VecIn1.Val == 0) { 4502 VecIn1 = ExtractedFromVec; 4503 } else if (VecIn2.Val == 0) { 4504 VecIn2 = ExtractedFromVec; 4505 } else { 4506 // Too many inputs. 4507 VecIn1 = VecIn2 = SDOperand(0, 0); 4508 break; 4509 } 4510 } 4511 4512 // If everything is good, we can make a shuffle operation. 4513 if (VecIn1.Val) { 4514 SmallVector<SDOperand, 8> BuildVecIndices; 4515 for (unsigned i = 0; i != NumInScalars; ++i) { 4516 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4517 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4518 continue; 4519 } 4520 4521 SDOperand Extract = N->getOperand(i); 4522 4523 // If extracting from the first vector, just use the index directly. 4524 if (Extract.getOperand(0) == VecIn1) { 4525 BuildVecIndices.push_back(Extract.getOperand(1)); 4526 continue; 4527 } 4528 4529 // Otherwise, use InIdx + VecSize 4530 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4531 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4532 } 4533 4534 // Add count and size info. 4535 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); 4536 4537 // Return the new VECTOR_SHUFFLE node. 4538 SDOperand Ops[5]; 4539 Ops[0] = VecIn1; 4540 if (VecIn2.Val) { 4541 Ops[1] = VecIn2; 4542 } else { 4543 // Use an undef build_vector as input for the second operand. 4544 std::vector<SDOperand> UnOps(NumInScalars, 4545 DAG.getNode(ISD::UNDEF, 4546 EltType)); 4547 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4548 &UnOps[0], UnOps.size()); 4549 AddToWorkList(Ops[1].Val); 4550 } 4551 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4552 &BuildVecIndices[0], BuildVecIndices.size()); 4553 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4554 } 4555 4556 return SDOperand(); 4557} 4558 4559SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4560 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4561 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4562 // inputs come from at most two distinct vectors, turn this into a shuffle 4563 // node. 4564 4565 // If we only have one input vector, we don't need to do any concatenation. 4566 if (N->getNumOperands() == 1) { 4567 return N->getOperand(0); 4568 } 4569 4570 return SDOperand(); 4571} 4572 4573SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4574 SDOperand ShufMask = N->getOperand(2); 4575 unsigned NumElts = ShufMask.getNumOperands(); 4576 4577 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4578 bool isIdentity = true; 4579 for (unsigned i = 0; i != NumElts; ++i) { 4580 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4581 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4582 isIdentity = false; 4583 break; 4584 } 4585 } 4586 if (isIdentity) return N->getOperand(0); 4587 4588 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4589 isIdentity = true; 4590 for (unsigned i = 0; i != NumElts; ++i) { 4591 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4592 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4593 isIdentity = false; 4594 break; 4595 } 4596 } 4597 if (isIdentity) return N->getOperand(1); 4598 4599 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4600 // needed at all. 4601 bool isUnary = true; 4602 bool isSplat = true; 4603 int VecNum = -1; 4604 unsigned BaseIdx = 0; 4605 for (unsigned i = 0; i != NumElts; ++i) 4606 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4607 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4608 int V = (Idx < NumElts) ? 0 : 1; 4609 if (VecNum == -1) { 4610 VecNum = V; 4611 BaseIdx = Idx; 4612 } else { 4613 if (BaseIdx != Idx) 4614 isSplat = false; 4615 if (VecNum != V) { 4616 isUnary = false; 4617 break; 4618 } 4619 } 4620 } 4621 4622 SDOperand N0 = N->getOperand(0); 4623 SDOperand N1 = N->getOperand(1); 4624 // Normalize unary shuffle so the RHS is undef. 4625 if (isUnary && VecNum == 1) 4626 std::swap(N0, N1); 4627 4628 // If it is a splat, check if the argument vector is a build_vector with 4629 // all scalar elements the same. 4630 if (isSplat) { 4631 SDNode *V = N0.Val; 4632 4633 // If this is a bit convert that changes the element type of the vector but 4634 // not the number of vector elements, look through it. Be careful not to 4635 // look though conversions that change things like v4f32 to v2f64. 4636 if (V->getOpcode() == ISD::BIT_CONVERT) { 4637 SDOperand ConvInput = V->getOperand(0); 4638 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4639 V = ConvInput.Val; 4640 } 4641 4642 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4643 unsigned NumElems = V->getNumOperands(); 4644 if (NumElems > BaseIdx) { 4645 SDOperand Base; 4646 bool AllSame = true; 4647 for (unsigned i = 0; i != NumElems; ++i) { 4648 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4649 Base = V->getOperand(i); 4650 break; 4651 } 4652 } 4653 // Splat of <u, u, u, u>, return <u, u, u, u> 4654 if (!Base.Val) 4655 return N0; 4656 for (unsigned i = 0; i != NumElems; ++i) { 4657 if (V->getOperand(i) != Base) { 4658 AllSame = false; 4659 break; 4660 } 4661 } 4662 // Splat of <x, x, x, x>, return <x, x, x, x> 4663 if (AllSame) 4664 return N0; 4665 } 4666 } 4667 } 4668 4669 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4670 // into an undef. 4671 if (isUnary || N0 == N1) { 4672 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4673 // first operand. 4674 SmallVector<SDOperand, 8> MappedOps; 4675 for (unsigned i = 0; i != NumElts; ++i) { 4676 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4677 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4678 MappedOps.push_back(ShufMask.getOperand(i)); 4679 } else { 4680 unsigned NewIdx = 4681 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4682 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4683 } 4684 } 4685 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4686 &MappedOps[0], MappedOps.size()); 4687 AddToWorkList(ShufMask.Val); 4688 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4689 N0, 4690 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4691 ShufMask); 4692 } 4693 4694 return SDOperand(); 4695} 4696 4697/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4698/// an AND to a vector_shuffle with the destination vector and a zero vector. 4699/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4700/// vector_shuffle V, Zero, <0, 4, 2, 4> 4701SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4702 SDOperand LHS = N->getOperand(0); 4703 SDOperand RHS = N->getOperand(1); 4704 if (N->getOpcode() == ISD::AND) { 4705 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4706 RHS = RHS.getOperand(0); 4707 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4708 std::vector<SDOperand> IdxOps; 4709 unsigned NumOps = RHS.getNumOperands(); 4710 unsigned NumElts = NumOps; 4711 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4712 for (unsigned i = 0; i != NumElts; ++i) { 4713 SDOperand Elt = RHS.getOperand(i); 4714 if (!isa<ConstantSDNode>(Elt)) 4715 return SDOperand(); 4716 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4717 IdxOps.push_back(DAG.getConstant(i, EVT)); 4718 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4719 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4720 else 4721 return SDOperand(); 4722 } 4723 4724 // Let's see if the target supports this vector_shuffle. 4725 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4726 return SDOperand(); 4727 4728 // Return the new VECTOR_SHUFFLE node. 4729 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4730 std::vector<SDOperand> Ops; 4731 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4732 Ops.push_back(LHS); 4733 AddToWorkList(LHS.Val); 4734 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4735 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4736 &ZeroOps[0], ZeroOps.size())); 4737 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4738 &IdxOps[0], IdxOps.size())); 4739 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4740 &Ops[0], Ops.size()); 4741 if (VT != LHS.getValueType()) { 4742 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4743 } 4744 return Result; 4745 } 4746 } 4747 return SDOperand(); 4748} 4749 4750/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4751SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4752 // After legalize, the target may be depending on adds and other 4753 // binary ops to provide legal ways to construct constants or other 4754 // things. Simplifying them may result in a loss of legality. 4755 if (AfterLegalize) return SDOperand(); 4756 4757 MVT::ValueType VT = N->getValueType(0); 4758 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4759 4760 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4761 SDOperand LHS = N->getOperand(0); 4762 SDOperand RHS = N->getOperand(1); 4763 SDOperand Shuffle = XformToShuffleWithZero(N); 4764 if (Shuffle.Val) return Shuffle; 4765 4766 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4767 // this operation. 4768 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4769 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4770 SmallVector<SDOperand, 8> Ops; 4771 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4772 SDOperand LHSOp = LHS.getOperand(i); 4773 SDOperand RHSOp = RHS.getOperand(i); 4774 // If these two elements can't be folded, bail out. 4775 if ((LHSOp.getOpcode() != ISD::UNDEF && 4776 LHSOp.getOpcode() != ISD::Constant && 4777 LHSOp.getOpcode() != ISD::ConstantFP) || 4778 (RHSOp.getOpcode() != ISD::UNDEF && 4779 RHSOp.getOpcode() != ISD::Constant && 4780 RHSOp.getOpcode() != ISD::ConstantFP)) 4781 break; 4782 // Can't fold divide by zero. 4783 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4784 N->getOpcode() == ISD::FDIV) { 4785 if ((RHSOp.getOpcode() == ISD::Constant && 4786 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4787 (RHSOp.getOpcode() == ISD::ConstantFP && 4788 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4789 break; 4790 } 4791 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4792 AddToWorkList(Ops.back().Val); 4793 assert((Ops.back().getOpcode() == ISD::UNDEF || 4794 Ops.back().getOpcode() == ISD::Constant || 4795 Ops.back().getOpcode() == ISD::ConstantFP) && 4796 "Scalar binop didn't fold!"); 4797 } 4798 4799 if (Ops.size() == LHS.getNumOperands()) { 4800 MVT::ValueType VT = LHS.getValueType(); 4801 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4802 } 4803 } 4804 4805 return SDOperand(); 4806} 4807 4808SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4809 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4810 4811 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4812 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4813 // If we got a simplified select_cc node back from SimplifySelectCC, then 4814 // break it down into a new SETCC node, and a new SELECT node, and then return 4815 // the SELECT node, since we were called with a SELECT node. 4816 if (SCC.Val) { 4817 // Check to see if we got a select_cc back (to turn into setcc/select). 4818 // Otherwise, just return whatever node we got back, like fabs. 4819 if (SCC.getOpcode() == ISD::SELECT_CC) { 4820 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4821 SCC.getOperand(0), SCC.getOperand(1), 4822 SCC.getOperand(4)); 4823 AddToWorkList(SETCC.Val); 4824 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4825 SCC.getOperand(3), SETCC); 4826 } 4827 return SCC; 4828 } 4829 return SDOperand(); 4830} 4831 4832/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4833/// are the two values being selected between, see if we can simplify the 4834/// select. Callers of this should assume that TheSelect is deleted if this 4835/// returns true. As such, they should return the appropriate thing (e.g. the 4836/// node) back to the top-level of the DAG combiner loop to avoid it being 4837/// looked at. 4838/// 4839bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4840 SDOperand RHS) { 4841 4842 // If this is a select from two identical things, try to pull the operation 4843 // through the select. 4844 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4845 // If this is a load and the token chain is identical, replace the select 4846 // of two loads with a load through a select of the address to load from. 4847 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4848 // constants have been dropped into the constant pool. 4849 if (LHS.getOpcode() == ISD::LOAD && 4850 // Token chains must be identical. 4851 LHS.getOperand(0) == RHS.getOperand(0)) { 4852 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4853 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4854 4855 // If this is an EXTLOAD, the VT's must match. 4856 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4857 // FIXME: this conflates two src values, discarding one. This is not 4858 // the right thing to do, but nothing uses srcvalues now. When they do, 4859 // turn SrcValue into a list of locations. 4860 SDOperand Addr; 4861 if (TheSelect->getOpcode() == ISD::SELECT) { 4862 // Check that the condition doesn't reach either load. If so, folding 4863 // this will induce a cycle into the DAG. 4864 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4865 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4866 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4867 TheSelect->getOperand(0), LLD->getBasePtr(), 4868 RLD->getBasePtr()); 4869 } 4870 } else { 4871 // Check that the condition doesn't reach either load. If so, folding 4872 // this will induce a cycle into the DAG. 4873 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4874 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4875 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4876 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4877 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4878 TheSelect->getOperand(0), 4879 TheSelect->getOperand(1), 4880 LLD->getBasePtr(), RLD->getBasePtr(), 4881 TheSelect->getOperand(4)); 4882 } 4883 } 4884 4885 if (Addr.Val) { 4886 SDOperand Load; 4887 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4888 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4889 Addr,LLD->getSrcValue(), 4890 LLD->getSrcValueOffset(), 4891 LLD->isVolatile(), 4892 LLD->getAlignment()); 4893 else { 4894 Load = DAG.getExtLoad(LLD->getExtensionType(), 4895 TheSelect->getValueType(0), 4896 LLD->getChain(), Addr, LLD->getSrcValue(), 4897 LLD->getSrcValueOffset(), 4898 LLD->getLoadedVT(), 4899 LLD->isVolatile(), 4900 LLD->getAlignment()); 4901 } 4902 // Users of the select now use the result of the load. 4903 CombineTo(TheSelect, Load); 4904 4905 // Users of the old loads now use the new load's chain. We know the 4906 // old-load value is dead now. 4907 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4908 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4909 return true; 4910 } 4911 } 4912 } 4913 } 4914 4915 return false; 4916} 4917 4918SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4919 SDOperand N2, SDOperand N3, 4920 ISD::CondCode CC, bool NotExtCompare) { 4921 4922 MVT::ValueType VT = N2.getValueType(); 4923 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4924 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4925 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4926 4927 // Determine if the condition we're dealing with is constant 4928 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4929 if (SCC.Val) AddToWorkList(SCC.Val); 4930 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4931 4932 // fold select_cc true, x, y -> x 4933 if (SCCC && SCCC->getValue()) 4934 return N2; 4935 // fold select_cc false, x, y -> y 4936 if (SCCC && SCCC->getValue() == 0) 4937 return N3; 4938 4939 // Check to see if we can simplify the select into an fabs node 4940 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4941 // Allow either -0.0 or 0.0 4942 if (CFP->getValueAPF().isZero()) { 4943 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4944 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4945 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4946 N2 == N3.getOperand(0)) 4947 return DAG.getNode(ISD::FABS, VT, N0); 4948 4949 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4950 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4951 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4952 N2.getOperand(0) == N3) 4953 return DAG.getNode(ISD::FABS, VT, N3); 4954 } 4955 } 4956 4957 // Check to see if we can perform the "gzip trick", transforming 4958 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4959 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4960 MVT::isInteger(N0.getValueType()) && 4961 MVT::isInteger(N2.getValueType()) && 4962 (N1C->isNullValue() || // (a < 0) ? b : 0 4963 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4964 MVT::ValueType XType = N0.getValueType(); 4965 MVT::ValueType AType = N2.getValueType(); 4966 if (XType >= AType) { 4967 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4968 // single-bit constant. 4969 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4970 unsigned ShCtV = Log2_64(N2C->getValue()); 4971 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4972 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4973 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4974 AddToWorkList(Shift.Val); 4975 if (XType > AType) { 4976 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4977 AddToWorkList(Shift.Val); 4978 } 4979 return DAG.getNode(ISD::AND, AType, Shift, N2); 4980 } 4981 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4982 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4983 TLI.getShiftAmountTy())); 4984 AddToWorkList(Shift.Val); 4985 if (XType > AType) { 4986 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4987 AddToWorkList(Shift.Val); 4988 } 4989 return DAG.getNode(ISD::AND, AType, Shift, N2); 4990 } 4991 } 4992 4993 // fold select C, 16, 0 -> shl C, 4 4994 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4995 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4996 4997 // If the caller doesn't want us to simplify this into a zext of a compare, 4998 // don't do it. 4999 if (NotExtCompare && N2C->getValue() == 1) 5000 return SDOperand(); 5001 5002 // Get a SetCC of the condition 5003 // FIXME: Should probably make sure that setcc is legal if we ever have a 5004 // target where it isn't. 5005 SDOperand Temp, SCC; 5006 // cast from setcc result type to select result type 5007 if (AfterLegalize) { 5008 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 5009 if (N2.getValueType() < SCC.getValueType()) 5010 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5011 else 5012 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5013 } else { 5014 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5015 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5016 } 5017 AddToWorkList(SCC.Val); 5018 AddToWorkList(Temp.Val); 5019 5020 if (N2C->getValue() == 1) 5021 return Temp; 5022 // shl setcc result by log2 n2c 5023 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5024 DAG.getConstant(Log2_64(N2C->getValue()), 5025 TLI.getShiftAmountTy())); 5026 } 5027 5028 // Check to see if this is the equivalent of setcc 5029 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5030 // otherwise, go ahead with the folds. 5031 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 5032 MVT::ValueType XType = N0.getValueType(); 5033 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 5034 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 5035 if (Res.getValueType() != VT) 5036 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5037 return Res; 5038 } 5039 5040 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5041 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5042 TLI.isOperationLegal(ISD::CTLZ, XType)) { 5043 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5044 return DAG.getNode(ISD::SRL, XType, Ctlz, 5045 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 5046 TLI.getShiftAmountTy())); 5047 } 5048 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5049 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5050 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5051 N0); 5052 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5053 DAG.getConstant(~0ULL, XType)); 5054 return DAG.getNode(ISD::SRL, XType, 5055 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5056 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5057 TLI.getShiftAmountTy())); 5058 } 5059 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5060 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5061 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5062 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5063 TLI.getShiftAmountTy())); 5064 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5065 } 5066 } 5067 5068 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5069 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5070 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5071 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5072 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 5073 MVT::ValueType XType = N0.getValueType(); 5074 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5075 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5076 TLI.getShiftAmountTy())); 5077 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5078 AddToWorkList(Shift.Val); 5079 AddToWorkList(Add.Val); 5080 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5081 } 5082 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5083 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5084 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5085 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5086 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5087 MVT::ValueType XType = N0.getValueType(); 5088 if (SubC->isNullValue() && MVT::isInteger(XType)) { 5089 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5090 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5091 TLI.getShiftAmountTy())); 5092 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5093 AddToWorkList(Shift.Val); 5094 AddToWorkList(Add.Val); 5095 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5096 } 5097 } 5098 } 5099 5100 return SDOperand(); 5101} 5102 5103/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5104SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 5105 SDOperand N1, ISD::CondCode Cond, 5106 bool foldBooleans) { 5107 TargetLowering::DAGCombinerInfo 5108 DagCombineInfo(DAG, !AfterLegalize, false, this); 5109 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5110} 5111 5112/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5113/// return a DAG expression to select that will generate the same value by 5114/// multiplying by a magic number. See: 5115/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5116SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5117 std::vector<SDNode*> Built; 5118 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5119 5120 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5121 ii != ee; ++ii) 5122 AddToWorkList(*ii); 5123 return S; 5124} 5125 5126/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5127/// return a DAG expression to select that will generate the same value by 5128/// multiplying by a magic number. See: 5129/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5130SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5131 std::vector<SDNode*> Built; 5132 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5133 5134 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5135 ii != ee; ++ii) 5136 AddToWorkList(*ii); 5137 return S; 5138} 5139 5140/// FindBaseOffset - Return true if base is known not to alias with anything 5141/// but itself. Provides base object and offset as results. 5142static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5143 // Assume it is a primitive operation. 5144 Base = Ptr; Offset = 0; 5145 5146 // If it's an adding a simple constant then integrate the offset. 5147 if (Base.getOpcode() == ISD::ADD) { 5148 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5149 Base = Base.getOperand(0); 5150 Offset += C->getValue(); 5151 } 5152 } 5153 5154 // If it's any of the following then it can't alias with anything but itself. 5155 return isa<FrameIndexSDNode>(Base) || 5156 isa<ConstantPoolSDNode>(Base) || 5157 isa<GlobalAddressSDNode>(Base); 5158} 5159 5160/// isAlias - Return true if there is any possibility that the two addresses 5161/// overlap. 5162bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5163 const Value *SrcValue1, int SrcValueOffset1, 5164 SDOperand Ptr2, int64_t Size2, 5165 const Value *SrcValue2, int SrcValueOffset2) 5166{ 5167 // If they are the same then they must be aliases. 5168 if (Ptr1 == Ptr2) return true; 5169 5170 // Gather base node and offset information. 5171 SDOperand Base1, Base2; 5172 int64_t Offset1, Offset2; 5173 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5174 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5175 5176 // If they have a same base address then... 5177 if (Base1 == Base2) { 5178 // Check to see if the addresses overlap. 5179 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5180 } 5181 5182 // If we know both bases then they can't alias. 5183 if (KnownBase1 && KnownBase2) return false; 5184 5185 if (CombinerGlobalAA) { 5186 // Use alias analysis information. 5187 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5188 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5189 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5190 AliasAnalysis::AliasResult AAResult = 5191 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5192 if (AAResult == AliasAnalysis::NoAlias) 5193 return false; 5194 } 5195 5196 // Otherwise we have to assume they alias. 5197 return true; 5198} 5199 5200/// FindAliasInfo - Extracts the relevant alias information from the memory 5201/// node. Returns true if the operand was a load. 5202bool DAGCombiner::FindAliasInfo(SDNode *N, 5203 SDOperand &Ptr, int64_t &Size, 5204 const Value *&SrcValue, int &SrcValueOffset) { 5205 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5206 Ptr = LD->getBasePtr(); 5207 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 5208 SrcValue = LD->getSrcValue(); 5209 SrcValueOffset = LD->getSrcValueOffset(); 5210 return true; 5211 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5212 Ptr = ST->getBasePtr(); 5213 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 5214 SrcValue = ST->getSrcValue(); 5215 SrcValueOffset = ST->getSrcValueOffset(); 5216 } else { 5217 assert(0 && "FindAliasInfo expected a memory operand"); 5218 } 5219 5220 return false; 5221} 5222 5223/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5224/// looking for aliasing nodes and adding them to the Aliases vector. 5225void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5226 SmallVector<SDOperand, 8> &Aliases) { 5227 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5228 std::set<SDNode *> Visited; // Visited node set. 5229 5230 // Get alias information for node. 5231 SDOperand Ptr; 5232 int64_t Size; 5233 const Value *SrcValue; 5234 int SrcValueOffset; 5235 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5236 5237 // Starting off. 5238 Chains.push_back(OriginalChain); 5239 5240 // Look at each chain and determine if it is an alias. If so, add it to the 5241 // aliases list. If not, then continue up the chain looking for the next 5242 // candidate. 5243 while (!Chains.empty()) { 5244 SDOperand Chain = Chains.back(); 5245 Chains.pop_back(); 5246 5247 // Don't bother if we've been before. 5248 if (Visited.find(Chain.Val) != Visited.end()) continue; 5249 Visited.insert(Chain.Val); 5250 5251 switch (Chain.getOpcode()) { 5252 case ISD::EntryToken: 5253 // Entry token is ideal chain operand, but handled in FindBetterChain. 5254 break; 5255 5256 case ISD::LOAD: 5257 case ISD::STORE: { 5258 // Get alias information for Chain. 5259 SDOperand OpPtr; 5260 int64_t OpSize; 5261 const Value *OpSrcValue; 5262 int OpSrcValueOffset; 5263 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5264 OpSrcValue, OpSrcValueOffset); 5265 5266 // If chain is alias then stop here. 5267 if (!(IsLoad && IsOpLoad) && 5268 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5269 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5270 Aliases.push_back(Chain); 5271 } else { 5272 // Look further up the chain. 5273 Chains.push_back(Chain.getOperand(0)); 5274 // Clean up old chain. 5275 AddToWorkList(Chain.Val); 5276 } 5277 break; 5278 } 5279 5280 case ISD::TokenFactor: 5281 // We have to check each of the operands of the token factor, so we queue 5282 // then up. Adding the operands to the queue (stack) in reverse order 5283 // maintains the original order and increases the likelihood that getNode 5284 // will find a matching token factor (CSE.) 5285 for (unsigned n = Chain.getNumOperands(); n;) 5286 Chains.push_back(Chain.getOperand(--n)); 5287 // Eliminate the token factor if we can. 5288 AddToWorkList(Chain.Val); 5289 break; 5290 5291 default: 5292 // For all other instructions we will just have to take what we can get. 5293 Aliases.push_back(Chain); 5294 break; 5295 } 5296 } 5297} 5298 5299/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5300/// for a better chain (aliasing node.) 5301SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5302 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5303 5304 // Accumulate all the aliases to this node. 5305 GatherAllAliases(N, OldChain, Aliases); 5306 5307 if (Aliases.size() == 0) { 5308 // If no operands then chain to entry token. 5309 return DAG.getEntryNode(); 5310 } else if (Aliases.size() == 1) { 5311 // If a single operand then chain to it. We don't need to revisit it. 5312 return Aliases[0]; 5313 } 5314 5315 // Construct a custom tailored token factor. 5316 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5317 &Aliases[0], Aliases.size()); 5318 5319 // Make sure the old chain gets cleaned up. 5320 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5321 5322 return NewChain; 5323} 5324 5325// SelectionDAG::Combine - This is the entry point for the file. 5326// 5327void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5328 if (!RunningAfterLegalize && ViewDAGCombine1) 5329 viewGraph(); 5330 if (RunningAfterLegalize && ViewDAGCombine2) 5331 viewGraph(); 5332 /// run - This is the main entry point to this class. 5333 /// 5334 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5335} 5336