DAGCombiner.cpp revision 1ec05d1bb4e8903321caf29f57a805952f5b8b86
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: make truncate see through SIGN_EXTEND and AND 26// FIXME: divide by zero is currently left unfolded. do we want to turn this 27// into an undef? 28// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "dagcombine" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include <algorithm> 39#include <cmath> 40#include <iostream> 41using namespace llvm; 42 43namespace { 44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 45 46 class DAGCombiner { 47 SelectionDAG &DAG; 48 TargetLowering &TLI; 49 bool AfterLegalize; 50 51 // Worklist of all of the nodes that need to be simplified. 52 std::vector<SDNode*> WorkList; 53 54 /// AddUsersToWorkList - When an instruction is simplified, add all users of 55 /// the instruction to the work lists because they might get more simplified 56 /// now. 57 /// 58 void AddUsersToWorkList(SDNode *N) { 59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 60 UI != UE; ++UI) 61 WorkList.push_back(*UI); 62 } 63 64 /// removeFromWorkList - remove all instances of N from the worklist. 65 /// 66 void removeFromWorkList(SDNode *N) { 67 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 68 WorkList.end()); 69 } 70 71 public: 72 void AddToWorkList(SDNode *N) { 73 WorkList.push_back(N); 74 } 75 76 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 77 ++NodesCombined; 78 DEBUG(std::cerr << "\nReplacing "; N->dump(); 79 std::cerr << "\nWith: "; To[0].Val->dump(); 80 std::cerr << " and " << To.size()-1 << " other values\n"); 81 std::vector<SDNode*> NowDead; 82 DAG.ReplaceAllUsesWith(N, To, &NowDead); 83 84 // Push the new nodes and any users onto the worklist 85 for (unsigned i = 0, e = To.size(); i != e; ++i) { 86 WorkList.push_back(To[i].Val); 87 AddUsersToWorkList(To[i].Val); 88 } 89 90 // Nodes can end up on the worklist more than once. Make sure we do 91 // not process a node that has been replaced. 92 removeFromWorkList(N); 93 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 94 removeFromWorkList(NowDead[i]); 95 96 // Finally, since the node is now dead, remove it from the graph. 97 DAG.DeleteNode(N); 98 return SDOperand(N, 0); 99 } 100 101 SDOperand CombineTo(SDNode *N, SDOperand Res) { 102 std::vector<SDOperand> To; 103 To.push_back(Res); 104 return CombineTo(N, To); 105 } 106 107 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 108 std::vector<SDOperand> To; 109 To.push_back(Res0); 110 To.push_back(Res1); 111 return CombineTo(N, To); 112 } 113 private: 114 115 /// SimplifyDemandedBits - Check the specified integer node value to see if 116 /// it can be simplified or if things it uses can be simplified by bit 117 /// propagation. If so, return true. 118 bool SimplifyDemandedBits(SDOperand Op) { 119 TargetLowering::TargetLoweringOpt TLO(DAG); 120 uint64_t KnownZero, KnownOne; 121 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 122 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 123 return false; 124 125 // Revisit the node. 126 WorkList.push_back(Op.Val); 127 128 // Replace the old value with the new one. 129 ++NodesCombined; 130 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 131 std::cerr << "\nWith: "; TLO.New.Val->dump()); 132 133 std::vector<SDNode*> NowDead; 134 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 135 136 // Push the new node and any (possibly new) users onto the worklist. 137 WorkList.push_back(TLO.New.Val); 138 AddUsersToWorkList(TLO.New.Val); 139 140 // Nodes can end up on the worklist more than once. Make sure we do 141 // not process a node that has been replaced. 142 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 143 removeFromWorkList(NowDead[i]); 144 145 // Finally, if the node is now dead, remove it from the graph. The node 146 // may not be dead if the replacement process recursively simplified to 147 // something else needing this node. 148 if (TLO.Old.Val->use_empty()) { 149 removeFromWorkList(TLO.Old.Val); 150 DAG.DeleteNode(TLO.Old.Val); 151 } 152 return true; 153 } 154 155 /// visit - call the node-specific routine that knows how to fold each 156 /// particular type of node. 157 SDOperand visit(SDNode *N); 158 159 // Visitation implementation - Implement dag node combining for different 160 // node types. The semantics are as follows: 161 // Return Value: 162 // SDOperand.Val == 0 - No change was made 163 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 164 // otherwise - N should be replaced by the returned Operand. 165 // 166 SDOperand visitTokenFactor(SDNode *N); 167 SDOperand visitADD(SDNode *N); 168 SDOperand visitSUB(SDNode *N); 169 SDOperand visitMUL(SDNode *N); 170 SDOperand visitSDIV(SDNode *N); 171 SDOperand visitUDIV(SDNode *N); 172 SDOperand visitSREM(SDNode *N); 173 SDOperand visitUREM(SDNode *N); 174 SDOperand visitMULHU(SDNode *N); 175 SDOperand visitMULHS(SDNode *N); 176 SDOperand visitAND(SDNode *N); 177 SDOperand visitOR(SDNode *N); 178 SDOperand visitXOR(SDNode *N); 179 SDOperand visitSHL(SDNode *N); 180 SDOperand visitSRA(SDNode *N); 181 SDOperand visitSRL(SDNode *N); 182 SDOperand visitCTLZ(SDNode *N); 183 SDOperand visitCTTZ(SDNode *N); 184 SDOperand visitCTPOP(SDNode *N); 185 SDOperand visitSELECT(SDNode *N); 186 SDOperand visitSELECT_CC(SDNode *N); 187 SDOperand visitSETCC(SDNode *N); 188 SDOperand visitSIGN_EXTEND(SDNode *N); 189 SDOperand visitZERO_EXTEND(SDNode *N); 190 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 191 SDOperand visitTRUNCATE(SDNode *N); 192 SDOperand visitBIT_CONVERT(SDNode *N); 193 SDOperand visitFADD(SDNode *N); 194 SDOperand visitFSUB(SDNode *N); 195 SDOperand visitFMUL(SDNode *N); 196 SDOperand visitFDIV(SDNode *N); 197 SDOperand visitFREM(SDNode *N); 198 SDOperand visitSINT_TO_FP(SDNode *N); 199 SDOperand visitUINT_TO_FP(SDNode *N); 200 SDOperand visitFP_TO_SINT(SDNode *N); 201 SDOperand visitFP_TO_UINT(SDNode *N); 202 SDOperand visitFP_ROUND(SDNode *N); 203 SDOperand visitFP_ROUND_INREG(SDNode *N); 204 SDOperand visitFP_EXTEND(SDNode *N); 205 SDOperand visitFNEG(SDNode *N); 206 SDOperand visitFABS(SDNode *N); 207 SDOperand visitBRCOND(SDNode *N); 208 SDOperand visitBRCONDTWOWAY(SDNode *N); 209 SDOperand visitBR_CC(SDNode *N); 210 SDOperand visitBRTWOWAY_CC(SDNode *N); 211 SDOperand visitLOAD(SDNode *N); 212 SDOperand visitSTORE(SDNode *N); 213 214 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 215 216 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 217 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 218 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 219 SDOperand N3, ISD::CondCode CC); 220 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 221 ISD::CondCode Cond, bool foldBooleans = true); 222 223 SDOperand BuildSDIV(SDNode *N); 224 SDOperand BuildUDIV(SDNode *N); 225public: 226 DAGCombiner(SelectionDAG &D) 227 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 228 229 /// Run - runs the dag combiner on all nodes in the work list 230 void Run(bool RunningAfterLegalize); 231 }; 232} 233 234//===----------------------------------------------------------------------===// 235// TargetLowering::DAGCombinerInfo implementation 236//===----------------------------------------------------------------------===// 237 238void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 239 ((DAGCombiner*)DC)->AddToWorkList(N); 240} 241 242SDOperand TargetLowering::DAGCombinerInfo:: 243CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 244 return ((DAGCombiner*)DC)->CombineTo(N, To); 245} 246 247SDOperand TargetLowering::DAGCombinerInfo:: 248CombineTo(SDNode *N, SDOperand Res) { 249 return ((DAGCombiner*)DC)->CombineTo(N, Res); 250} 251 252 253SDOperand TargetLowering::DAGCombinerInfo:: 254CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 255 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 256} 257 258 259 260 261//===----------------------------------------------------------------------===// 262 263 264struct ms { 265 int64_t m; // magic number 266 int64_t s; // shift amount 267}; 268 269struct mu { 270 uint64_t m; // magic number 271 int64_t a; // add indicator 272 int64_t s; // shift amount 273}; 274 275/// magic - calculate the magic numbers required to codegen an integer sdiv as 276/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 277/// or -1. 278static ms magic32(int32_t d) { 279 int32_t p; 280 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 281 const uint32_t two31 = 0x80000000U; 282 struct ms mag; 283 284 ad = abs(d); 285 t = two31 + ((uint32_t)d >> 31); 286 anc = t - 1 - t%ad; // absolute value of nc 287 p = 31; // initialize p 288 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 289 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 290 q2 = two31/ad; // initialize q2 = 2p/abs(d) 291 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 292 do { 293 p = p + 1; 294 q1 = 2*q1; // update q1 = 2p/abs(nc) 295 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 296 if (r1 >= anc) { // must be unsigned comparison 297 q1 = q1 + 1; 298 r1 = r1 - anc; 299 } 300 q2 = 2*q2; // update q2 = 2p/abs(d) 301 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 302 if (r2 >= ad) { // must be unsigned comparison 303 q2 = q2 + 1; 304 r2 = r2 - ad; 305 } 306 delta = ad - r2; 307 } while (q1 < delta || (q1 == delta && r1 == 0)); 308 309 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 310 if (d < 0) mag.m = -mag.m; // resulting magic number 311 mag.s = p - 32; // resulting shift 312 return mag; 313} 314 315/// magicu - calculate the magic numbers required to codegen an integer udiv as 316/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 317static mu magicu32(uint32_t d) { 318 int32_t p; 319 uint32_t nc, delta, q1, r1, q2, r2; 320 struct mu magu; 321 magu.a = 0; // initialize "add" indicator 322 nc = - 1 - (-d)%d; 323 p = 31; // initialize p 324 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 325 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 326 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 327 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 328 do { 329 p = p + 1; 330 if (r1 >= nc - r1 ) { 331 q1 = 2*q1 + 1; // update q1 332 r1 = 2*r1 - nc; // update r1 333 } 334 else { 335 q1 = 2*q1; // update q1 336 r1 = 2*r1; // update r1 337 } 338 if (r2 + 1 >= d - r2) { 339 if (q2 >= 0x7FFFFFFF) magu.a = 1; 340 q2 = 2*q2 + 1; // update q2 341 r2 = 2*r2 + 1 - d; // update r2 342 } 343 else { 344 if (q2 >= 0x80000000) magu.a = 1; 345 q2 = 2*q2; // update q2 346 r2 = 2*r2 + 1; // update r2 347 } 348 delta = d - 1 - r2; 349 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 350 magu.m = q2 + 1; // resulting magic number 351 magu.s = p - 32; // resulting shift 352 return magu; 353} 354 355/// magic - calculate the magic numbers required to codegen an integer sdiv as 356/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 357/// or -1. 358static ms magic64(int64_t d) { 359 int64_t p; 360 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 361 const uint64_t two63 = 9223372036854775808ULL; // 2^63 362 struct ms mag; 363 364 ad = d >= 0 ? d : -d; 365 t = two63 + ((uint64_t)d >> 63); 366 anc = t - 1 - t%ad; // absolute value of nc 367 p = 63; // initialize p 368 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 369 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 370 q2 = two63/ad; // initialize q2 = 2p/abs(d) 371 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 372 do { 373 p = p + 1; 374 q1 = 2*q1; // update q1 = 2p/abs(nc) 375 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 376 if (r1 >= anc) { // must be unsigned comparison 377 q1 = q1 + 1; 378 r1 = r1 - anc; 379 } 380 q2 = 2*q2; // update q2 = 2p/abs(d) 381 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 382 if (r2 >= ad) { // must be unsigned comparison 383 q2 = q2 + 1; 384 r2 = r2 - ad; 385 } 386 delta = ad - r2; 387 } while (q1 < delta || (q1 == delta && r1 == 0)); 388 389 mag.m = q2 + 1; 390 if (d < 0) mag.m = -mag.m; // resulting magic number 391 mag.s = p - 64; // resulting shift 392 return mag; 393} 394 395/// magicu - calculate the magic numbers required to codegen an integer udiv as 396/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 397static mu magicu64(uint64_t d) 398{ 399 int64_t p; 400 uint64_t nc, delta, q1, r1, q2, r2; 401 struct mu magu; 402 magu.a = 0; // initialize "add" indicator 403 nc = - 1 - (-d)%d; 404 p = 63; // initialize p 405 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 406 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 407 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 408 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 409 do { 410 p = p + 1; 411 if (r1 >= nc - r1 ) { 412 q1 = 2*q1 + 1; // update q1 413 r1 = 2*r1 - nc; // update r1 414 } 415 else { 416 q1 = 2*q1; // update q1 417 r1 = 2*r1; // update r1 418 } 419 if (r2 + 1 >= d - r2) { 420 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 421 q2 = 2*q2 + 1; // update q2 422 r2 = 2*r2 + 1 - d; // update r2 423 } 424 else { 425 if (q2 >= 0x8000000000000000ull) magu.a = 1; 426 q2 = 2*q2; // update q2 427 r2 = 2*r2 + 1; // update r2 428 } 429 delta = d - 1 - r2; 430 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 431 magu.m = q2 + 1; // resulting magic number 432 magu.s = p - 64; // resulting shift 433 return magu; 434} 435 436// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 437// that selects between the values 1 and 0, making it equivalent to a setcc. 438// Also, set the incoming LHS, RHS, and CC references to the appropriate 439// nodes based on the type of node we are checking. This simplifies life a 440// bit for the callers. 441static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 442 SDOperand &CC) { 443 if (N.getOpcode() == ISD::SETCC) { 444 LHS = N.getOperand(0); 445 RHS = N.getOperand(1); 446 CC = N.getOperand(2); 447 return true; 448 } 449 if (N.getOpcode() == ISD::SELECT_CC && 450 N.getOperand(2).getOpcode() == ISD::Constant && 451 N.getOperand(3).getOpcode() == ISD::Constant && 452 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 453 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 454 LHS = N.getOperand(0); 455 RHS = N.getOperand(1); 456 CC = N.getOperand(4); 457 return true; 458 } 459 return false; 460} 461 462// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 463// one use. If this is true, it allows the users to invert the operation for 464// free when it is profitable to do so. 465static bool isOneUseSetCC(SDOperand N) { 466 SDOperand N0, N1, N2; 467 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 468 return true; 469 return false; 470} 471 472// FIXME: This should probably go in the ISD class rather than being duplicated 473// in several files. 474static bool isCommutativeBinOp(unsigned Opcode) { 475 switch (Opcode) { 476 case ISD::ADD: 477 case ISD::MUL: 478 case ISD::AND: 479 case ISD::OR: 480 case ISD::XOR: return true; 481 default: return false; // FIXME: Need commutative info for user ops! 482 } 483} 484 485SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 486 MVT::ValueType VT = N0.getValueType(); 487 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 488 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 489 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 490 if (isa<ConstantSDNode>(N1)) { 491 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 492 AddToWorkList(OpNode.Val); 493 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 494 } else if (N0.hasOneUse()) { 495 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 496 AddToWorkList(OpNode.Val); 497 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 498 } 499 } 500 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 501 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 502 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 503 if (isa<ConstantSDNode>(N0)) { 504 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 505 AddToWorkList(OpNode.Val); 506 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 507 } else if (N1.hasOneUse()) { 508 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 509 AddToWorkList(OpNode.Val); 510 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 511 } 512 } 513 return SDOperand(); 514} 515 516void DAGCombiner::Run(bool RunningAfterLegalize) { 517 // set the instance variable, so that the various visit routines may use it. 518 AfterLegalize = RunningAfterLegalize; 519 520 // Add all the dag nodes to the worklist. 521 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 522 E = DAG.allnodes_end(); I != E; ++I) 523 WorkList.push_back(I); 524 525 // Create a dummy node (which is not added to allnodes), that adds a reference 526 // to the root node, preventing it from being deleted, and tracking any 527 // changes of the root. 528 HandleSDNode Dummy(DAG.getRoot()); 529 530 531 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 532 TargetLowering::DAGCombinerInfo 533 DagCombineInfo(DAG, !RunningAfterLegalize, this); 534 535 // while the worklist isn't empty, inspect the node on the end of it and 536 // try and combine it. 537 while (!WorkList.empty()) { 538 SDNode *N = WorkList.back(); 539 WorkList.pop_back(); 540 541 // If N has no uses, it is dead. Make sure to revisit all N's operands once 542 // N is deleted from the DAG, since they too may now be dead or may have a 543 // reduced number of uses, allowing other xforms. 544 if (N->use_empty() && N != &Dummy) { 545 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 546 WorkList.push_back(N->getOperand(i).Val); 547 548 removeFromWorkList(N); 549 DAG.DeleteNode(N); 550 continue; 551 } 552 553 SDOperand RV = visit(N); 554 555 // If nothing happened, try a target-specific DAG combine. 556 if (RV.Val == 0) { 557 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 558 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 559 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 560 } 561 562 if (RV.Val) { 563 ++NodesCombined; 564 // If we get back the same node we passed in, rather than a new node or 565 // zero, we know that the node must have defined multiple values and 566 // CombineTo was used. Since CombineTo takes care of the worklist 567 // mechanics for us, we have no work to do in this case. 568 if (RV.Val != N) { 569 DEBUG(std::cerr << "\nReplacing "; N->dump(); 570 std::cerr << "\nWith: "; RV.Val->dump(); 571 std::cerr << '\n'); 572 std::vector<SDNode*> NowDead; 573 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 574 575 // Push the new node and any users onto the worklist 576 WorkList.push_back(RV.Val); 577 AddUsersToWorkList(RV.Val); 578 579 // Nodes can end up on the worklist more than once. Make sure we do 580 // not process a node that has been replaced. 581 removeFromWorkList(N); 582 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 583 removeFromWorkList(NowDead[i]); 584 585 // Finally, since the node is now dead, remove it from the graph. 586 DAG.DeleteNode(N); 587 } 588 } 589 } 590 591 // If the root changed (e.g. it was a dead load, update the root). 592 DAG.setRoot(Dummy.getValue()); 593} 594 595SDOperand DAGCombiner::visit(SDNode *N) { 596 switch(N->getOpcode()) { 597 default: break; 598 case ISD::TokenFactor: return visitTokenFactor(N); 599 case ISD::ADD: return visitADD(N); 600 case ISD::SUB: return visitSUB(N); 601 case ISD::MUL: return visitMUL(N); 602 case ISD::SDIV: return visitSDIV(N); 603 case ISD::UDIV: return visitUDIV(N); 604 case ISD::SREM: return visitSREM(N); 605 case ISD::UREM: return visitUREM(N); 606 case ISD::MULHU: return visitMULHU(N); 607 case ISD::MULHS: return visitMULHS(N); 608 case ISD::AND: return visitAND(N); 609 case ISD::OR: return visitOR(N); 610 case ISD::XOR: return visitXOR(N); 611 case ISD::SHL: return visitSHL(N); 612 case ISD::SRA: return visitSRA(N); 613 case ISD::SRL: return visitSRL(N); 614 case ISD::CTLZ: return visitCTLZ(N); 615 case ISD::CTTZ: return visitCTTZ(N); 616 case ISD::CTPOP: return visitCTPOP(N); 617 case ISD::SELECT: return visitSELECT(N); 618 case ISD::SELECT_CC: return visitSELECT_CC(N); 619 case ISD::SETCC: return visitSETCC(N); 620 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 621 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 622 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 623 case ISD::TRUNCATE: return visitTRUNCATE(N); 624 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 625 case ISD::FADD: return visitFADD(N); 626 case ISD::FSUB: return visitFSUB(N); 627 case ISD::FMUL: return visitFMUL(N); 628 case ISD::FDIV: return visitFDIV(N); 629 case ISD::FREM: return visitFREM(N); 630 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 631 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 632 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 633 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 634 case ISD::FP_ROUND: return visitFP_ROUND(N); 635 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 636 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 637 case ISD::FNEG: return visitFNEG(N); 638 case ISD::FABS: return visitFABS(N); 639 case ISD::BRCOND: return visitBRCOND(N); 640 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 641 case ISD::BR_CC: return visitBR_CC(N); 642 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 643 case ISD::LOAD: return visitLOAD(N); 644 case ISD::STORE: return visitSTORE(N); 645 } 646 return SDOperand(); 647} 648 649SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 650 std::vector<SDOperand> Ops; 651 bool Changed = false; 652 653 // If the token factor has two operands and one is the entry token, replace 654 // the token factor with the other operand. 655 if (N->getNumOperands() == 2) { 656 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 657 return N->getOperand(1); 658 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 659 return N->getOperand(0); 660 } 661 662 // fold (tokenfactor (tokenfactor)) -> tokenfactor 663 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 664 SDOperand Op = N->getOperand(i); 665 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 666 Changed = true; 667 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 668 Ops.push_back(Op.getOperand(j)); 669 } else { 670 Ops.push_back(Op); 671 } 672 } 673 if (Changed) 674 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 675 return SDOperand(); 676} 677 678SDOperand DAGCombiner::visitADD(SDNode *N) { 679 SDOperand N0 = N->getOperand(0); 680 SDOperand N1 = N->getOperand(1); 681 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 682 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 683 MVT::ValueType VT = N0.getValueType(); 684 685 // fold (add c1, c2) -> c1+c2 686 if (N0C && N1C) 687 return DAG.getNode(ISD::ADD, VT, N0, N1); 688 // canonicalize constant to RHS 689 if (N0C && !N1C) 690 return DAG.getNode(ISD::ADD, VT, N1, N0); 691 // fold (add x, 0) -> x 692 if (N1C && N1C->isNullValue()) 693 return N0; 694 // fold ((c1-A)+c2) -> (c1+c2)-A 695 if (N1C && N0.getOpcode() == ISD::SUB) 696 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 697 return DAG.getNode(ISD::SUB, VT, 698 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 699 N0.getOperand(1)); 700 // reassociate add 701 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 702 if (RADD.Val != 0) 703 return RADD; 704 // fold ((0-A) + B) -> B-A 705 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 706 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 707 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 708 // fold (A + (0-B)) -> A-B 709 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 710 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 711 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 712 // fold (A+(B-A)) -> B 713 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 714 return N1.getOperand(0); 715 // 716 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 717 return SDOperand(); 718 return SDOperand(); 719} 720 721SDOperand DAGCombiner::visitSUB(SDNode *N) { 722 SDOperand N0 = N->getOperand(0); 723 SDOperand N1 = N->getOperand(1); 724 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 725 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 726 MVT::ValueType VT = N0.getValueType(); 727 728 // fold (sub x, x) -> 0 729 if (N0 == N1) 730 return DAG.getConstant(0, N->getValueType(0)); 731 // fold (sub c1, c2) -> c1-c2 732 if (N0C && N1C) 733 return DAG.getNode(ISD::SUB, VT, N0, N1); 734 // fold (sub x, c) -> (add x, -c) 735 if (N1C) 736 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 737 // fold (A+B)-A -> B 738 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 739 return N0.getOperand(1); 740 // fold (A+B)-B -> A 741 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 742 return N0.getOperand(0); 743 return SDOperand(); 744} 745 746SDOperand DAGCombiner::visitMUL(SDNode *N) { 747 SDOperand N0 = N->getOperand(0); 748 SDOperand N1 = N->getOperand(1); 749 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 750 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 751 MVT::ValueType VT = N0.getValueType(); 752 753 // fold (mul c1, c2) -> c1*c2 754 if (N0C && N1C) 755 return DAG.getNode(ISD::MUL, VT, N0, N1); 756 // canonicalize constant to RHS 757 if (N0C && !N1C) 758 return DAG.getNode(ISD::MUL, VT, N1, N0); 759 // fold (mul x, 0) -> 0 760 if (N1C && N1C->isNullValue()) 761 return N1; 762 // fold (mul x, -1) -> 0-x 763 if (N1C && N1C->isAllOnesValue()) 764 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 765 // fold (mul x, (1 << c)) -> x << c 766 if (N1C && isPowerOf2_64(N1C->getValue())) 767 return DAG.getNode(ISD::SHL, VT, N0, 768 DAG.getConstant(Log2_64(N1C->getValue()), 769 TLI.getShiftAmountTy())); 770 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 771 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 772 // FIXME: If the input is something that is easily negated (e.g. a 773 // single-use add), we should put the negate there. 774 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 775 DAG.getNode(ISD::SHL, VT, N0, 776 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 777 TLI.getShiftAmountTy()))); 778 } 779 780 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 781 if (N1C && N0.getOpcode() == ISD::SHL && 782 isa<ConstantSDNode>(N0.getOperand(1))) { 783 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 784 AddToWorkList(C3.Val); 785 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 786 } 787 788 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 789 // use. 790 { 791 SDOperand Sh(0,0), Y(0,0); 792 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 793 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 794 N0.Val->hasOneUse()) { 795 Sh = N0; Y = N1; 796 } else if (N1.getOpcode() == ISD::SHL && 797 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 798 Sh = N1; Y = N0; 799 } 800 if (Sh.Val) { 801 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 802 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 803 } 804 } 805 806 807 // reassociate mul 808 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 809 if (RMUL.Val != 0) 810 return RMUL; 811 return SDOperand(); 812} 813 814SDOperand DAGCombiner::visitSDIV(SDNode *N) { 815 SDOperand N0 = N->getOperand(0); 816 SDOperand N1 = N->getOperand(1); 817 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 818 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 819 MVT::ValueType VT = N->getValueType(0); 820 821 // fold (sdiv c1, c2) -> c1/c2 822 if (N0C && N1C && !N1C->isNullValue()) 823 return DAG.getNode(ISD::SDIV, VT, N0, N1); 824 // fold (sdiv X, 1) -> X 825 if (N1C && N1C->getSignExtended() == 1LL) 826 return N0; 827 // fold (sdiv X, -1) -> 0-X 828 if (N1C && N1C->isAllOnesValue()) 829 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 830 // If we know the sign bits of both operands are zero, strength reduce to a 831 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 832 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 833 if (TLI.MaskedValueIsZero(N1, SignBit) && 834 TLI.MaskedValueIsZero(N0, SignBit)) 835 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 836 // fold (sdiv X, pow2) -> simple ops after legalize 837 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 838 (isPowerOf2_64(N1C->getSignExtended()) || 839 isPowerOf2_64(-N1C->getSignExtended()))) { 840 // If dividing by powers of two is cheap, then don't perform the following 841 // fold. 842 if (TLI.isPow2DivCheap()) 843 return SDOperand(); 844 int64_t pow2 = N1C->getSignExtended(); 845 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 846 unsigned lg2 = Log2_64(abs2); 847 // Splat the sign bit into the register 848 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 849 DAG.getConstant(MVT::getSizeInBits(VT)-1, 850 TLI.getShiftAmountTy())); 851 AddToWorkList(SGN.Val); 852 // Add (N0 < 0) ? abs2 - 1 : 0; 853 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 854 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 855 TLI.getShiftAmountTy())); 856 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 857 AddToWorkList(SRL.Val); 858 AddToWorkList(ADD.Val); // Divide by pow2 859 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 860 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 861 // If we're dividing by a positive value, we're done. Otherwise, we must 862 // negate the result. 863 if (pow2 > 0) 864 return SRA; 865 AddToWorkList(SRA.Val); 866 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 867 } 868 // if integer divide is expensive and we satisfy the requirements, emit an 869 // alternate sequence. 870 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 871 !TLI.isIntDivCheap()) { 872 SDOperand Op = BuildSDIV(N); 873 if (Op.Val) return Op; 874 } 875 return SDOperand(); 876} 877 878SDOperand DAGCombiner::visitUDIV(SDNode *N) { 879 SDOperand N0 = N->getOperand(0); 880 SDOperand N1 = N->getOperand(1); 881 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 882 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 883 MVT::ValueType VT = N->getValueType(0); 884 885 // fold (udiv c1, c2) -> c1/c2 886 if (N0C && N1C && !N1C->isNullValue()) 887 return DAG.getNode(ISD::UDIV, VT, N0, N1); 888 // fold (udiv x, (1 << c)) -> x >>u c 889 if (N1C && isPowerOf2_64(N1C->getValue())) 890 return DAG.getNode(ISD::SRL, VT, N0, 891 DAG.getConstant(Log2_64(N1C->getValue()), 892 TLI.getShiftAmountTy())); 893 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 894 if (N1.getOpcode() == ISD::SHL) { 895 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 896 if (isPowerOf2_64(SHC->getValue())) { 897 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 898 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 899 DAG.getConstant(Log2_64(SHC->getValue()), 900 ADDVT)); 901 AddToWorkList(Add.Val); 902 return DAG.getNode(ISD::SRL, VT, N0, Add); 903 } 904 } 905 } 906 // fold (udiv x, c) -> alternate 907 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 908 SDOperand Op = BuildUDIV(N); 909 if (Op.Val) return Op; 910 } 911 return SDOperand(); 912} 913 914SDOperand DAGCombiner::visitSREM(SDNode *N) { 915 SDOperand N0 = N->getOperand(0); 916 SDOperand N1 = N->getOperand(1); 917 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 918 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 919 MVT::ValueType VT = N->getValueType(0); 920 921 // fold (srem c1, c2) -> c1%c2 922 if (N0C && N1C && !N1C->isNullValue()) 923 return DAG.getNode(ISD::SREM, VT, N0, N1); 924 // If we know the sign bits of both operands are zero, strength reduce to a 925 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 926 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 927 if (TLI.MaskedValueIsZero(N1, SignBit) && 928 TLI.MaskedValueIsZero(N0, SignBit)) 929 return DAG.getNode(ISD::UREM, VT, N0, N1); 930 return SDOperand(); 931} 932 933SDOperand DAGCombiner::visitUREM(SDNode *N) { 934 SDOperand N0 = N->getOperand(0); 935 SDOperand N1 = N->getOperand(1); 936 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 937 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 938 MVT::ValueType VT = N->getValueType(0); 939 940 // fold (urem c1, c2) -> c1%c2 941 if (N0C && N1C && !N1C->isNullValue()) 942 return DAG.getNode(ISD::UREM, VT, N0, N1); 943 // fold (urem x, pow2) -> (and x, pow2-1) 944 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 945 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 946 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 947 if (N1.getOpcode() == ISD::SHL) { 948 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 949 if (isPowerOf2_64(SHC->getValue())) { 950 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 951 AddToWorkList(Add.Val); 952 return DAG.getNode(ISD::AND, VT, N0, Add); 953 } 954 } 955 } 956 return SDOperand(); 957} 958 959SDOperand DAGCombiner::visitMULHS(SDNode *N) { 960 SDOperand N0 = N->getOperand(0); 961 SDOperand N1 = N->getOperand(1); 962 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 963 964 // fold (mulhs x, 0) -> 0 965 if (N1C && N1C->isNullValue()) 966 return N1; 967 // fold (mulhs x, 1) -> (sra x, size(x)-1) 968 if (N1C && N1C->getValue() == 1) 969 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 970 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 971 TLI.getShiftAmountTy())); 972 return SDOperand(); 973} 974 975SDOperand DAGCombiner::visitMULHU(SDNode *N) { 976 SDOperand N0 = N->getOperand(0); 977 SDOperand N1 = N->getOperand(1); 978 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 979 980 // fold (mulhu x, 0) -> 0 981 if (N1C && N1C->isNullValue()) 982 return N1; 983 // fold (mulhu x, 1) -> 0 984 if (N1C && N1C->getValue() == 1) 985 return DAG.getConstant(0, N0.getValueType()); 986 return SDOperand(); 987} 988 989SDOperand DAGCombiner::visitAND(SDNode *N) { 990 SDOperand N0 = N->getOperand(0); 991 SDOperand N1 = N->getOperand(1); 992 SDOperand LL, LR, RL, RR, CC0, CC1; 993 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 994 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 995 MVT::ValueType VT = N1.getValueType(); 996 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 997 998 // fold (and c1, c2) -> c1&c2 999 if (N0C && N1C) 1000 return DAG.getNode(ISD::AND, VT, N0, N1); 1001 // canonicalize constant to RHS 1002 if (N0C && !N1C) 1003 return DAG.getNode(ISD::AND, VT, N1, N0); 1004 // fold (and x, -1) -> x 1005 if (N1C && N1C->isAllOnesValue()) 1006 return N0; 1007 // if (and x, c) is known to be zero, return 0 1008 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1009 return DAG.getConstant(0, VT); 1010 // reassociate and 1011 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1012 if (RAND.Val != 0) 1013 return RAND; 1014 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1015 if (N1C && N0.getOpcode() == ISD::OR) 1016 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1017 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1018 return N1; 1019 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1020 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1021 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1022 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1023 ~N1C->getValue() & InMask)) { 1024 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1025 N0.getOperand(0)); 1026 1027 // Replace uses of the AND with uses of the Zero extend node. 1028 CombineTo(N, Zext); 1029 1030 // We actually want to replace all uses of the any_extend with the 1031 // zero_extend, to avoid duplicating things. This will later cause this 1032 // AND to be folded. 1033 CombineTo(N0.Val, Zext); 1034 return SDOperand(); 1035 } 1036 } 1037 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1038 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1039 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1040 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1041 1042 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1043 MVT::isInteger(LL.getValueType())) { 1044 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1045 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1046 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1047 AddToWorkList(ORNode.Val); 1048 return DAG.getSetCC(VT, ORNode, LR, Op1); 1049 } 1050 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1051 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1052 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1053 AddToWorkList(ANDNode.Val); 1054 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1055 } 1056 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1057 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1058 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1059 AddToWorkList(ORNode.Val); 1060 return DAG.getSetCC(VT, ORNode, LR, Op1); 1061 } 1062 } 1063 // canonicalize equivalent to ll == rl 1064 if (LL == RR && LR == RL) { 1065 Op1 = ISD::getSetCCSwappedOperands(Op1); 1066 std::swap(RL, RR); 1067 } 1068 if (LL == RL && LR == RR) { 1069 bool isInteger = MVT::isInteger(LL.getValueType()); 1070 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1071 if (Result != ISD::SETCC_INVALID) 1072 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1073 } 1074 } 1075 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 1076 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1077 N1.getOpcode() == ISD::ZERO_EXTEND && 1078 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1079 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1080 N0.getOperand(0), N1.getOperand(0)); 1081 AddToWorkList(ANDNode.Val); 1082 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 1083 } 1084 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y)) 1085 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1086 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1087 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1088 N0.getOperand(1) == N1.getOperand(1)) { 1089 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1090 N0.getOperand(0), N1.getOperand(0)); 1091 AddToWorkList(ANDNode.Val); 1092 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 1093 } 1094 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1095 // fold (and (sra)) -> (and (srl)) when possible. 1096 if (SimplifyDemandedBits(SDOperand(N, 0))) 1097 return SDOperand(); 1098 // fold (zext_inreg (extload x)) -> (zextload x) 1099 if (N0.getOpcode() == ISD::EXTLOAD) { 1100 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1101 // If we zero all the possible extended bits, then we can turn this into 1102 // a zextload if we are running before legalize or the operation is legal. 1103 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1104 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1105 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1106 N0.getOperand(1), N0.getOperand(2), 1107 EVT); 1108 AddToWorkList(N); 1109 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1110 return SDOperand(); 1111 } 1112 } 1113 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1114 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1115 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1116 // If we zero all the possible extended bits, then we can turn this into 1117 // a zextload if we are running before legalize or the operation is legal. 1118 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1119 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1120 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1121 N0.getOperand(1), N0.getOperand(2), 1122 EVT); 1123 AddToWorkList(N); 1124 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1125 return SDOperand(); 1126 } 1127 } 1128 1129 // fold (and (load x), 255) -> (zextload x, i8) 1130 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1131 if (N1C && 1132 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD || 1133 N0.getOpcode() == ISD::ZEXTLOAD) && 1134 N0.hasOneUse()) { 1135 MVT::ValueType EVT, LoadedVT; 1136 if (N1C->getValue() == 255) 1137 EVT = MVT::i8; 1138 else if (N1C->getValue() == 65535) 1139 EVT = MVT::i16; 1140 else if (N1C->getValue() == ~0U) 1141 EVT = MVT::i32; 1142 else 1143 EVT = MVT::Other; 1144 1145 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : 1146 cast<VTSDNode>(N0.getOperand(3))->getVT(); 1147 if (EVT != MVT::Other && LoadedVT > EVT) { 1148 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1149 // For big endian targets, we need to add an offset to the pointer to load 1150 // the correct bytes. For little endian systems, we merely need to read 1151 // fewer bytes from the same pointer. 1152 unsigned PtrOff = 1153 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1154 SDOperand NewPtr = N0.getOperand(1); 1155 if (!TLI.isLittleEndian()) 1156 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1157 DAG.getConstant(PtrOff, PtrType)); 1158 AddToWorkList(NewPtr.Val); 1159 SDOperand Load = 1160 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr, 1161 N0.getOperand(2), EVT); 1162 AddToWorkList(N); 1163 CombineTo(N0.Val, Load, Load.getValue(1)); 1164 return SDOperand(); 1165 } 1166 } 1167 1168 return SDOperand(); 1169} 1170 1171SDOperand DAGCombiner::visitOR(SDNode *N) { 1172 SDOperand N0 = N->getOperand(0); 1173 SDOperand N1 = N->getOperand(1); 1174 SDOperand LL, LR, RL, RR, CC0, CC1; 1175 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1176 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1177 MVT::ValueType VT = N1.getValueType(); 1178 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1179 1180 // fold (or c1, c2) -> c1|c2 1181 if (N0C && N1C) 1182 return DAG.getNode(ISD::OR, VT, N0, N1); 1183 // canonicalize constant to RHS 1184 if (N0C && !N1C) 1185 return DAG.getNode(ISD::OR, VT, N1, N0); 1186 // fold (or x, 0) -> x 1187 if (N1C && N1C->isNullValue()) 1188 return N0; 1189 // fold (or x, -1) -> -1 1190 if (N1C && N1C->isAllOnesValue()) 1191 return N1; 1192 // fold (or x, c) -> c iff (x & ~c) == 0 1193 if (N1C && 1194 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1195 return N1; 1196 // reassociate or 1197 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1198 if (ROR.Val != 0) 1199 return ROR; 1200 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1201 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1202 isa<ConstantSDNode>(N0.getOperand(1))) { 1203 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1204 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1205 N1), 1206 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1207 } 1208 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1209 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1210 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1211 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1212 1213 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1214 MVT::isInteger(LL.getValueType())) { 1215 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1216 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1217 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1218 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1219 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1220 AddToWorkList(ORNode.Val); 1221 return DAG.getSetCC(VT, ORNode, LR, Op1); 1222 } 1223 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1224 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1225 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1226 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1227 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1228 AddToWorkList(ANDNode.Val); 1229 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1230 } 1231 } 1232 // canonicalize equivalent to ll == rl 1233 if (LL == RR && LR == RL) { 1234 Op1 = ISD::getSetCCSwappedOperands(Op1); 1235 std::swap(RL, RR); 1236 } 1237 if (LL == RL && LR == RR) { 1238 bool isInteger = MVT::isInteger(LL.getValueType()); 1239 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1240 if (Result != ISD::SETCC_INVALID) 1241 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1242 } 1243 } 1244 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 1245 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1246 N1.getOpcode() == ISD::ZERO_EXTEND && 1247 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1248 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1249 N0.getOperand(0), N1.getOperand(0)); 1250 AddToWorkList(ORNode.Val); 1251 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 1252 } 1253 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y)) 1254 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1255 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1256 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1257 N0.getOperand(1) == N1.getOperand(1)) { 1258 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1259 N0.getOperand(0), N1.getOperand(0)); 1260 AddToWorkList(ORNode.Val); 1261 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1262 } 1263 // canonicalize shl to left side in a shl/srl pair, to match rotate 1264 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 1265 std::swap(N0, N1); 1266 // check for rotl, rotr 1267 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 1268 N0.getOperand(0) == N1.getOperand(0) && 1269 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 1270 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1271 if (N0.getOperand(1).getOpcode() == ISD::Constant && 1272 N1.getOperand(1).getOpcode() == ISD::Constant) { 1273 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1274 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1275 if ((c1val + c2val) == OpSizeInBits) 1276 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1277 } 1278 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1279 if (N1.getOperand(1).getOpcode() == ISD::SUB && 1280 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 1281 if (ConstantSDNode *SUBC = 1282 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 1283 if (SUBC->getValue() == OpSizeInBits) 1284 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1285 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1286 if (N0.getOperand(1).getOpcode() == ISD::SUB && 1287 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 1288 if (ConstantSDNode *SUBC = 1289 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 1290 if (SUBC->getValue() == OpSizeInBits) { 1291 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 1292 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 1293 N1.getOperand(1)); 1294 else 1295 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 1296 N0.getOperand(1)); 1297 } 1298 } 1299 return SDOperand(); 1300} 1301 1302SDOperand DAGCombiner::visitXOR(SDNode *N) { 1303 SDOperand N0 = N->getOperand(0); 1304 SDOperand N1 = N->getOperand(1); 1305 SDOperand LHS, RHS, CC; 1306 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1307 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1308 MVT::ValueType VT = N0.getValueType(); 1309 1310 // fold (xor c1, c2) -> c1^c2 1311 if (N0C && N1C) 1312 return DAG.getNode(ISD::XOR, VT, N0, N1); 1313 // canonicalize constant to RHS 1314 if (N0C && !N1C) 1315 return DAG.getNode(ISD::XOR, VT, N1, N0); 1316 // fold (xor x, 0) -> x 1317 if (N1C && N1C->isNullValue()) 1318 return N0; 1319 // reassociate xor 1320 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1321 if (RXOR.Val != 0) 1322 return RXOR; 1323 // fold !(x cc y) -> (x !cc y) 1324 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1325 bool isInt = MVT::isInteger(LHS.getValueType()); 1326 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1327 isInt); 1328 if (N0.getOpcode() == ISD::SETCC) 1329 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1330 if (N0.getOpcode() == ISD::SELECT_CC) 1331 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1332 assert(0 && "Unhandled SetCC Equivalent!"); 1333 abort(); 1334 } 1335 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1336 if (N1C && N1C->getValue() == 1 && 1337 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1338 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1339 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1340 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1341 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1342 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1343 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1344 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1345 } 1346 } 1347 // fold !(x or y) -> (!x and !y) iff x or y are constants 1348 if (N1C && N1C->isAllOnesValue() && 1349 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1350 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1351 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1352 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1353 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1354 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1355 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1356 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1357 } 1358 } 1359 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1360 if (N1C && N0.getOpcode() == ISD::XOR) { 1361 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1362 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1363 if (N00C) 1364 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1365 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1366 if (N01C) 1367 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1368 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1369 } 1370 // fold (xor x, x) -> 0 1371 if (N0 == N1) 1372 return DAG.getConstant(0, VT); 1373 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1374 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1375 N1.getOpcode() == ISD::ZERO_EXTEND && 1376 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1377 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1378 N0.getOperand(0), N1.getOperand(0)); 1379 AddToWorkList(XORNode.Val); 1380 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1381 } 1382 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y)) 1383 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1384 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1385 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1386 N0.getOperand(1) == N1.getOperand(1)) { 1387 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1388 N0.getOperand(0), N1.getOperand(0)); 1389 AddToWorkList(XORNode.Val); 1390 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1)); 1391 } 1392 return SDOperand(); 1393} 1394 1395SDOperand DAGCombiner::visitSHL(SDNode *N) { 1396 SDOperand N0 = N->getOperand(0); 1397 SDOperand N1 = N->getOperand(1); 1398 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1400 MVT::ValueType VT = N0.getValueType(); 1401 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1402 1403 // fold (shl c1, c2) -> c1<<c2 1404 if (N0C && N1C) 1405 return DAG.getNode(ISD::SHL, VT, N0, N1); 1406 // fold (shl 0, x) -> 0 1407 if (N0C && N0C->isNullValue()) 1408 return N0; 1409 // fold (shl x, c >= size(x)) -> undef 1410 if (N1C && N1C->getValue() >= OpSizeInBits) 1411 return DAG.getNode(ISD::UNDEF, VT); 1412 // fold (shl x, 0) -> x 1413 if (N1C && N1C->isNullValue()) 1414 return N0; 1415 // if (shl x, c) is known to be zero, return 0 1416 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1417 return DAG.getConstant(0, VT); 1418 if (SimplifyDemandedBits(SDOperand(N, 0))) 1419 return SDOperand(); 1420 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1421 if (N1C && N0.getOpcode() == ISD::SHL && 1422 N0.getOperand(1).getOpcode() == ISD::Constant) { 1423 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1424 uint64_t c2 = N1C->getValue(); 1425 if (c1 + c2 > OpSizeInBits) 1426 return DAG.getConstant(0, VT); 1427 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1428 DAG.getConstant(c1 + c2, N1.getValueType())); 1429 } 1430 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1431 // (srl (and x, -1 << c1), c1-c2) 1432 if (N1C && N0.getOpcode() == ISD::SRL && 1433 N0.getOperand(1).getOpcode() == ISD::Constant) { 1434 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1435 uint64_t c2 = N1C->getValue(); 1436 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1437 DAG.getConstant(~0ULL << c1, VT)); 1438 if (c2 > c1) 1439 return DAG.getNode(ISD::SHL, VT, Mask, 1440 DAG.getConstant(c2-c1, N1.getValueType())); 1441 else 1442 return DAG.getNode(ISD::SRL, VT, Mask, 1443 DAG.getConstant(c1-c2, N1.getValueType())); 1444 } 1445 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1446 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1447 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1448 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1449 return SDOperand(); 1450} 1451 1452SDOperand DAGCombiner::visitSRA(SDNode *N) { 1453 SDOperand N0 = N->getOperand(0); 1454 SDOperand N1 = N->getOperand(1); 1455 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1456 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1457 MVT::ValueType VT = N0.getValueType(); 1458 1459 // fold (sra c1, c2) -> c1>>c2 1460 if (N0C && N1C) 1461 return DAG.getNode(ISD::SRA, VT, N0, N1); 1462 // fold (sra 0, x) -> 0 1463 if (N0C && N0C->isNullValue()) 1464 return N0; 1465 // fold (sra -1, x) -> -1 1466 if (N0C && N0C->isAllOnesValue()) 1467 return N0; 1468 // fold (sra x, c >= size(x)) -> undef 1469 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1470 return DAG.getNode(ISD::UNDEF, VT); 1471 // fold (sra x, 0) -> x 1472 if (N1C && N1C->isNullValue()) 1473 return N0; 1474 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1475 // sext_inreg. 1476 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1477 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1478 MVT::ValueType EVT; 1479 switch (LowBits) { 1480 default: EVT = MVT::Other; break; 1481 case 1: EVT = MVT::i1; break; 1482 case 8: EVT = MVT::i8; break; 1483 case 16: EVT = MVT::i16; break; 1484 case 32: EVT = MVT::i32; break; 1485 } 1486 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1487 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1488 DAG.getValueType(EVT)); 1489 } 1490 1491 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1492 if (N1C && N0.getOpcode() == ISD::SRA) { 1493 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1494 unsigned Sum = N1C->getValue() + C1->getValue(); 1495 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1496 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1497 DAG.getConstant(Sum, N1C->getValueType(0))); 1498 } 1499 } 1500 1501 // If the sign bit is known to be zero, switch this to a SRL. 1502 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1503 return DAG.getNode(ISD::SRL, VT, N0, N1); 1504 return SDOperand(); 1505} 1506 1507SDOperand DAGCombiner::visitSRL(SDNode *N) { 1508 SDOperand N0 = N->getOperand(0); 1509 SDOperand N1 = N->getOperand(1); 1510 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1511 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1512 MVT::ValueType VT = N0.getValueType(); 1513 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1514 1515 // fold (srl c1, c2) -> c1 >>u c2 1516 if (N0C && N1C) 1517 return DAG.getNode(ISD::SRL, VT, N0, N1); 1518 // fold (srl 0, x) -> 0 1519 if (N0C && N0C->isNullValue()) 1520 return N0; 1521 // fold (srl x, c >= size(x)) -> undef 1522 if (N1C && N1C->getValue() >= OpSizeInBits) 1523 return DAG.getNode(ISD::UNDEF, VT); 1524 // fold (srl x, 0) -> x 1525 if (N1C && N1C->isNullValue()) 1526 return N0; 1527 // if (srl x, c) is known to be zero, return 0 1528 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1529 return DAG.getConstant(0, VT); 1530 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1531 if (N1C && N0.getOpcode() == ISD::SRL && 1532 N0.getOperand(1).getOpcode() == ISD::Constant) { 1533 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1534 uint64_t c2 = N1C->getValue(); 1535 if (c1 + c2 > OpSizeInBits) 1536 return DAG.getConstant(0, VT); 1537 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1538 DAG.getConstant(c1 + c2, N1.getValueType())); 1539 } 1540 return SDOperand(); 1541} 1542 1543SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1544 SDOperand N0 = N->getOperand(0); 1545 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1546 MVT::ValueType VT = N->getValueType(0); 1547 1548 // fold (ctlz c1) -> c2 1549 if (N0C) 1550 return DAG.getNode(ISD::CTLZ, VT, N0); 1551 return SDOperand(); 1552} 1553 1554SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1555 SDOperand N0 = N->getOperand(0); 1556 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1557 MVT::ValueType VT = N->getValueType(0); 1558 1559 // fold (cttz c1) -> c2 1560 if (N0C) 1561 return DAG.getNode(ISD::CTTZ, VT, N0); 1562 return SDOperand(); 1563} 1564 1565SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1566 SDOperand N0 = N->getOperand(0); 1567 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1568 MVT::ValueType VT = N->getValueType(0); 1569 1570 // fold (ctpop c1) -> c2 1571 if (N0C) 1572 return DAG.getNode(ISD::CTPOP, VT, N0); 1573 return SDOperand(); 1574} 1575 1576SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1577 SDOperand N0 = N->getOperand(0); 1578 SDOperand N1 = N->getOperand(1); 1579 SDOperand N2 = N->getOperand(2); 1580 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1581 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1582 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1583 MVT::ValueType VT = N->getValueType(0); 1584 1585 // fold select C, X, X -> X 1586 if (N1 == N2) 1587 return N1; 1588 // fold select true, X, Y -> X 1589 if (N0C && !N0C->isNullValue()) 1590 return N1; 1591 // fold select false, X, Y -> Y 1592 if (N0C && N0C->isNullValue()) 1593 return N2; 1594 // fold select C, 1, X -> C | X 1595 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1596 return DAG.getNode(ISD::OR, VT, N0, N2); 1597 // fold select C, 0, X -> ~C & X 1598 // FIXME: this should check for C type == X type, not i1? 1599 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1600 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1601 AddToWorkList(XORNode.Val); 1602 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1603 } 1604 // fold select C, X, 1 -> ~C | X 1605 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1606 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1607 AddToWorkList(XORNode.Val); 1608 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1609 } 1610 // fold select C, X, 0 -> C & X 1611 // FIXME: this should check for C type == X type, not i1? 1612 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1613 return DAG.getNode(ISD::AND, VT, N0, N1); 1614 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1615 if (MVT::i1 == VT && N0 == N1) 1616 return DAG.getNode(ISD::OR, VT, N0, N2); 1617 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1618 if (MVT::i1 == VT && N0 == N2) 1619 return DAG.getNode(ISD::AND, VT, N0, N1); 1620 // If we can fold this based on the true/false value, do so. 1621 if (SimplifySelectOps(N, N1, N2)) 1622 return SDOperand(); 1623 // fold selects based on a setcc into other things, such as min/max/abs 1624 if (N0.getOpcode() == ISD::SETCC) 1625 // FIXME: 1626 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1627 // having to say they don't support SELECT_CC on every type the DAG knows 1628 // about, since there is no way to mark an opcode illegal at all value types 1629 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1630 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1631 N1, N2, N0.getOperand(2)); 1632 else 1633 return SimplifySelect(N0, N1, N2); 1634 return SDOperand(); 1635} 1636 1637SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1638 SDOperand N0 = N->getOperand(0); 1639 SDOperand N1 = N->getOperand(1); 1640 SDOperand N2 = N->getOperand(2); 1641 SDOperand N3 = N->getOperand(3); 1642 SDOperand N4 = N->getOperand(4); 1643 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1644 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1645 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1646 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1647 1648 // Determine if the condition we're dealing with is constant 1649 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1650 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1651 1652 // fold select_cc lhs, rhs, x, x, cc -> x 1653 if (N2 == N3) 1654 return N2; 1655 1656 // If we can fold this based on the true/false value, do so. 1657 if (SimplifySelectOps(N, N2, N3)) 1658 return SDOperand(); 1659 1660 // fold select_cc into other things, such as min/max/abs 1661 return SimplifySelectCC(N0, N1, N2, N3, CC); 1662} 1663 1664SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1665 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1666 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1667} 1668 1669SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1670 SDOperand N0 = N->getOperand(0); 1671 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1672 MVT::ValueType VT = N->getValueType(0); 1673 1674 // fold (sext c1) -> c1 1675 if (N0C) 1676 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1677 // fold (sext (sext x)) -> (sext x) 1678 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1679 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1680 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1681 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1682 (!AfterLegalize || 1683 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1684 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1685 DAG.getValueType(N0.getValueType())); 1686 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1687 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1688 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1689 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1690 N0.getOperand(1), N0.getOperand(2), 1691 N0.getValueType()); 1692 CombineTo(N, ExtLoad); 1693 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1694 ExtLoad.getValue(1)); 1695 return SDOperand(); 1696 } 1697 1698 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1699 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1700 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1701 N0.hasOneUse()) { 1702 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0), 1703 N0.getOperand(1), N0.getOperand(2), 1704 N0.getOperand(3)); 1705 CombineTo(N, ExtLoad); 1706 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1707 ExtLoad.getValue(1)); 1708 return SDOperand(); 1709 } 1710 1711 return SDOperand(); 1712} 1713 1714SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1715 SDOperand N0 = N->getOperand(0); 1716 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1717 MVT::ValueType VT = N->getValueType(0); 1718 1719 // fold (zext c1) -> c1 1720 if (N0C) 1721 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1722 // fold (zext (zext x)) -> (zext x) 1723 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1724 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1725 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1726 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1727 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1728 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1729 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1730 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1731 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1732 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1733 N0.getOperand(1), N0.getOperand(2), 1734 N0.getValueType()); 1735 CombineTo(N, ExtLoad); 1736 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1737 ExtLoad.getValue(1)); 1738 return SDOperand(); 1739 } 1740 1741 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1742 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1743 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1744 N0.hasOneUse()) { 1745 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1746 N0.getOperand(1), N0.getOperand(2), 1747 N0.getOperand(3)); 1748 CombineTo(N, ExtLoad); 1749 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1750 ExtLoad.getValue(1)); 1751 return SDOperand(); 1752 } 1753 return SDOperand(); 1754} 1755 1756SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1757 SDOperand N0 = N->getOperand(0); 1758 SDOperand N1 = N->getOperand(1); 1759 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1760 MVT::ValueType VT = N->getValueType(0); 1761 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1762 unsigned EVTBits = MVT::getSizeInBits(EVT); 1763 1764 // fold (sext_in_reg c1) -> c1 1765 if (N0C) { 1766 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1767 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1768 } 1769 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1770 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1771 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1772 return N0; 1773 } 1774 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1775 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1776 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1777 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1778 } 1779 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1780 if (N0.getOpcode() == ISD::AssertSext && 1781 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1782 return N0; 1783 } 1784 // fold (sext_in_reg (sextload x)) -> (sextload x) 1785 if (N0.getOpcode() == ISD::SEXTLOAD && 1786 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1787 return N0; 1788 } 1789 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1790 if (N0.getOpcode() == ISD::SETCC && 1791 TLI.getSetCCResultContents() == 1792 TargetLowering::ZeroOrNegativeOneSetCCResult) 1793 return N0; 1794 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1795 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1796 return DAG.getZeroExtendInReg(N0, EVT); 1797 // fold (sext_in_reg (srl x)) -> sra x 1798 if (N0.getOpcode() == ISD::SRL && 1799 N0.getOperand(1).getOpcode() == ISD::Constant && 1800 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1801 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1802 N0.getOperand(1)); 1803 } 1804 // fold (sext_inreg (extload x)) -> (sextload x) 1805 if (N0.getOpcode() == ISD::EXTLOAD && 1806 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1807 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1808 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1809 N0.getOperand(1), N0.getOperand(2), 1810 EVT); 1811 CombineTo(N, ExtLoad); 1812 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1813 return SDOperand(); 1814 } 1815 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1816 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1817 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1818 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1819 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1820 N0.getOperand(1), N0.getOperand(2), 1821 EVT); 1822 CombineTo(N, ExtLoad); 1823 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1824 return SDOperand(); 1825 } 1826 return SDOperand(); 1827} 1828 1829SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1830 SDOperand N0 = N->getOperand(0); 1831 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1832 MVT::ValueType VT = N->getValueType(0); 1833 1834 // noop truncate 1835 if (N0.getValueType() == N->getValueType(0)) 1836 return N0; 1837 // fold (truncate c1) -> c1 1838 if (N0C) 1839 return DAG.getNode(ISD::TRUNCATE, VT, N0); 1840 // fold (truncate (truncate x)) -> (truncate x) 1841 if (N0.getOpcode() == ISD::TRUNCATE) 1842 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1843 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1844 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1845 if (N0.getValueType() < VT) 1846 // if the source is smaller than the dest, we still need an extend 1847 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1848 else if (N0.getValueType() > VT) 1849 // if the source is larger than the dest, than we just need the truncate 1850 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1851 else 1852 // if the source and dest are the same type, we can drop both the extend 1853 // and the truncate 1854 return N0.getOperand(0); 1855 } 1856 // fold (truncate (load x)) -> (smaller load x) 1857 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1858 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1859 "Cannot truncate to larger type!"); 1860 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1861 // For big endian targets, we need to add an offset to the pointer to load 1862 // the correct bytes. For little endian systems, we merely need to read 1863 // fewer bytes from the same pointer. 1864 uint64_t PtrOff = 1865 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1866 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1867 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1868 DAG.getConstant(PtrOff, PtrType)); 1869 AddToWorkList(NewPtr.Val); 1870 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1871 AddToWorkList(N); 1872 CombineTo(N0.Val, Load, Load.getValue(1)); 1873 return SDOperand(); 1874 } 1875 return SDOperand(); 1876} 1877 1878SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 1879 SDOperand N0 = N->getOperand(0); 1880 MVT::ValueType VT = N->getValueType(0); 1881 1882 // If the input is a constant, let getNode() fold it. 1883 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 1884 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 1885 if (Res.Val != N) return Res; 1886 } 1887 1888 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 1889 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 1890 1891 // fold (conv (load x)) -> (load (conv*)x) 1892 // FIXME: These xforms need to know that the resultant load doesn't need a 1893 // higher alignment than the original! 1894 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1895 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 1896 N0.getOperand(2)); 1897 AddToWorkList(N); 1898 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 1899 Load.getValue(1)); 1900 return Load; 1901 } 1902 1903 return SDOperand(); 1904} 1905 1906SDOperand DAGCombiner::visitFADD(SDNode *N) { 1907 SDOperand N0 = N->getOperand(0); 1908 SDOperand N1 = N->getOperand(1); 1909 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1910 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1911 MVT::ValueType VT = N->getValueType(0); 1912 1913 // fold (fadd c1, c2) -> c1+c2 1914 if (N0CFP && N1CFP) 1915 return DAG.getNode(ISD::FADD, VT, N0, N1); 1916 // canonicalize constant to RHS 1917 if (N0CFP && !N1CFP) 1918 return DAG.getNode(ISD::FADD, VT, N1, N0); 1919 // fold (A + (-B)) -> A-B 1920 if (N1.getOpcode() == ISD::FNEG) 1921 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1922 // fold ((-A) + B) -> B-A 1923 if (N0.getOpcode() == ISD::FNEG) 1924 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1925 return SDOperand(); 1926} 1927 1928SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1929 SDOperand N0 = N->getOperand(0); 1930 SDOperand N1 = N->getOperand(1); 1931 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1932 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1933 MVT::ValueType VT = N->getValueType(0); 1934 1935 // fold (fsub c1, c2) -> c1-c2 1936 if (N0CFP && N1CFP) 1937 return DAG.getNode(ISD::FSUB, VT, N0, N1); 1938 // fold (A-(-B)) -> A+B 1939 if (N1.getOpcode() == ISD::FNEG) 1940 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 1941 return SDOperand(); 1942} 1943 1944SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1945 SDOperand N0 = N->getOperand(0); 1946 SDOperand N1 = N->getOperand(1); 1947 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1948 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1949 MVT::ValueType VT = N->getValueType(0); 1950 1951 // fold (fmul c1, c2) -> c1*c2 1952 if (N0CFP && N1CFP) 1953 return DAG.getNode(ISD::FMUL, VT, N0, N1); 1954 // canonicalize constant to RHS 1955 if (N0CFP && !N1CFP) 1956 return DAG.getNode(ISD::FMUL, VT, N1, N0); 1957 // fold (fmul X, 2.0) -> (fadd X, X) 1958 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 1959 return DAG.getNode(ISD::FADD, VT, N0, N0); 1960 return SDOperand(); 1961} 1962 1963SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1964 SDOperand N0 = N->getOperand(0); 1965 SDOperand N1 = N->getOperand(1); 1966 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1967 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1968 MVT::ValueType VT = N->getValueType(0); 1969 1970 // fold (fdiv c1, c2) -> c1/c2 1971 if (N0CFP && N1CFP) 1972 return DAG.getNode(ISD::FDIV, VT, N0, N1); 1973 return SDOperand(); 1974} 1975 1976SDOperand DAGCombiner::visitFREM(SDNode *N) { 1977 SDOperand N0 = N->getOperand(0); 1978 SDOperand N1 = N->getOperand(1); 1979 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1980 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1981 MVT::ValueType VT = N->getValueType(0); 1982 1983 // fold (frem c1, c2) -> fmod(c1,c2) 1984 if (N0CFP && N1CFP) 1985 return DAG.getNode(ISD::FREM, VT, N0, N1); 1986 return SDOperand(); 1987} 1988 1989 1990SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1991 SDOperand N0 = N->getOperand(0); 1992 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1993 MVT::ValueType VT = N->getValueType(0); 1994 1995 // fold (sint_to_fp c1) -> c1fp 1996 if (N0C) 1997 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 1998 return SDOperand(); 1999} 2000 2001SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2002 SDOperand N0 = N->getOperand(0); 2003 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2004 MVT::ValueType VT = N->getValueType(0); 2005 2006 // fold (uint_to_fp c1) -> c1fp 2007 if (N0C) 2008 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2009 return SDOperand(); 2010} 2011 2012SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2013 SDOperand N0 = N->getOperand(0); 2014 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2015 MVT::ValueType VT = N->getValueType(0); 2016 2017 // fold (fp_to_sint c1fp) -> c1 2018 if (N0CFP) 2019 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2020 return SDOperand(); 2021} 2022 2023SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2024 SDOperand N0 = N->getOperand(0); 2025 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2026 MVT::ValueType VT = N->getValueType(0); 2027 2028 // fold (fp_to_uint c1fp) -> c1 2029 if (N0CFP) 2030 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2031 return SDOperand(); 2032} 2033 2034SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2035 SDOperand N0 = N->getOperand(0); 2036 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2037 MVT::ValueType VT = N->getValueType(0); 2038 2039 // fold (fp_round c1fp) -> c1fp 2040 if (N0CFP) 2041 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2042 return SDOperand(); 2043} 2044 2045SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2046 SDOperand N0 = N->getOperand(0); 2047 MVT::ValueType VT = N->getValueType(0); 2048 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2049 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2050 2051 // fold (fp_round_inreg c1fp) -> c1fp 2052 if (N0CFP) { 2053 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2054 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2055 } 2056 return SDOperand(); 2057} 2058 2059SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2060 SDOperand N0 = N->getOperand(0); 2061 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2062 MVT::ValueType VT = N->getValueType(0); 2063 2064 // fold (fp_extend c1fp) -> c1fp 2065 if (N0CFP) 2066 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2067 return SDOperand(); 2068} 2069 2070SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2071 SDOperand N0 = N->getOperand(0); 2072 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2073 MVT::ValueType VT = N->getValueType(0); 2074 2075 // fold (fneg c1) -> -c1 2076 if (N0CFP) 2077 return DAG.getNode(ISD::FNEG, VT, N0); 2078 // fold (fneg (sub x, y)) -> (sub y, x) 2079 if (N->getOperand(0).getOpcode() == ISD::SUB) 2080 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0)); 2081 // fold (fneg (fneg x)) -> x 2082 if (N->getOperand(0).getOpcode() == ISD::FNEG) 2083 return N->getOperand(0).getOperand(0); 2084 return SDOperand(); 2085} 2086 2087SDOperand DAGCombiner::visitFABS(SDNode *N) { 2088 SDOperand N0 = N->getOperand(0); 2089 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2090 MVT::ValueType VT = N->getValueType(0); 2091 2092 // fold (fabs c1) -> fabs(c1) 2093 if (N0CFP) 2094 return DAG.getNode(ISD::FABS, VT, N0); 2095 // fold (fabs (fabs x)) -> (fabs x) 2096 if (N->getOperand(0).getOpcode() == ISD::FABS) 2097 return N->getOperand(0); 2098 // fold (fabs (fneg x)) -> (fabs x) 2099 if (N->getOperand(0).getOpcode() == ISD::FNEG) 2100 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0)); 2101 return SDOperand(); 2102} 2103 2104SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2105 SDOperand Chain = N->getOperand(0); 2106 SDOperand N1 = N->getOperand(1); 2107 SDOperand N2 = N->getOperand(2); 2108 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2109 2110 // never taken branch, fold to chain 2111 if (N1C && N1C->isNullValue()) 2112 return Chain; 2113 // unconditional branch 2114 if (N1C && N1C->getValue() == 1) 2115 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2116 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2117 // on the target. 2118 if (N1.getOpcode() == ISD::SETCC && 2119 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2120 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2121 N1.getOperand(0), N1.getOperand(1), N2); 2122 } 2123 return SDOperand(); 2124} 2125 2126SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 2127 SDOperand Chain = N->getOperand(0); 2128 SDOperand N1 = N->getOperand(1); 2129 SDOperand N2 = N->getOperand(2); 2130 SDOperand N3 = N->getOperand(3); 2131 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2132 2133 // unconditional branch to true mbb 2134 if (N1C && N1C->getValue() == 1) 2135 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2136 // unconditional branch to false mbb 2137 if (N1C && N1C->isNullValue()) 2138 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 2139 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if 2140 // BRTWOWAY_CC is legal on the target. 2141 if (N1.getOpcode() == ISD::SETCC && 2142 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 2143 std::vector<SDOperand> Ops; 2144 Ops.push_back(Chain); 2145 Ops.push_back(N1.getOperand(2)); 2146 Ops.push_back(N1.getOperand(0)); 2147 Ops.push_back(N1.getOperand(1)); 2148 Ops.push_back(N2); 2149 Ops.push_back(N3); 2150 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2151 } 2152 return SDOperand(); 2153} 2154 2155// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2156// 2157SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2158 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2159 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2160 2161 // Use SimplifySetCC to simplify SETCC's. 2162 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2163 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2164 2165 // fold br_cc true, dest -> br dest (unconditional branch) 2166 if (SCCC && SCCC->getValue()) 2167 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2168 N->getOperand(4)); 2169 // fold br_cc false, dest -> unconditional fall through 2170 if (SCCC && SCCC->isNullValue()) 2171 return N->getOperand(0); 2172 // fold to a simpler setcc 2173 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2174 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2175 Simp.getOperand(2), Simp.getOperand(0), 2176 Simp.getOperand(1), N->getOperand(4)); 2177 return SDOperand(); 2178} 2179 2180SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 2181 SDOperand Chain = N->getOperand(0); 2182 SDOperand CCN = N->getOperand(1); 2183 SDOperand LHS = N->getOperand(2); 2184 SDOperand RHS = N->getOperand(3); 2185 SDOperand N4 = N->getOperand(4); 2186 SDOperand N5 = N->getOperand(5); 2187 2188 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 2189 cast<CondCodeSDNode>(CCN)->get(), false); 2190 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2191 2192 // fold select_cc lhs, rhs, x, x, cc -> x 2193 if (N4 == N5) 2194 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2195 // fold select_cc true, x, y -> x 2196 if (SCCC && SCCC->getValue()) 2197 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2198 // fold select_cc false, x, y -> y 2199 if (SCCC && SCCC->isNullValue()) 2200 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 2201 // fold to a simpler setcc 2202 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) { 2203 std::vector<SDOperand> Ops; 2204 Ops.push_back(Chain); 2205 Ops.push_back(SCC.getOperand(2)); 2206 Ops.push_back(SCC.getOperand(0)); 2207 Ops.push_back(SCC.getOperand(1)); 2208 Ops.push_back(N4); 2209 Ops.push_back(N5); 2210 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2211 } 2212 return SDOperand(); 2213} 2214 2215SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2216 SDOperand Chain = N->getOperand(0); 2217 SDOperand Ptr = N->getOperand(1); 2218 SDOperand SrcValue = N->getOperand(2); 2219 2220 // If this load is directly stored, replace the load value with the stored 2221 // value. 2222 // TODO: Handle store large -> read small portion. 2223 // TODO: Handle TRUNCSTORE/EXTLOAD 2224 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2225 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2226 return CombineTo(N, Chain.getOperand(1), Chain); 2227 2228 return SDOperand(); 2229} 2230 2231SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2232 SDOperand Chain = N->getOperand(0); 2233 SDOperand Value = N->getOperand(1); 2234 SDOperand Ptr = N->getOperand(2); 2235 SDOperand SrcValue = N->getOperand(3); 2236 2237 // If this is a store that kills a previous store, remove the previous store. 2238 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2239 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2240 // Make sure that these stores are the same value type: 2241 // FIXME: we really care that the second store is >= size of the first. 2242 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2243 // Create a new store of Value that replaces both stores. 2244 SDNode *PrevStore = Chain.Val; 2245 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2246 return Chain; 2247 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2248 PrevStore->getOperand(0), Value, Ptr, 2249 SrcValue); 2250 CombineTo(N, NewStore); // Nuke this store. 2251 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2252 return SDOperand(N, 0); 2253 } 2254 2255 // If this is a store of a bit convert, store the input value. 2256 // FIXME: This needs to know that the resultant store does not need a 2257 // higher alignment than the original. 2258 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2259 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2260 Ptr, SrcValue); 2261 2262 return SDOperand(); 2263} 2264 2265SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2266 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2267 2268 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2269 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2270 // If we got a simplified select_cc node back from SimplifySelectCC, then 2271 // break it down into a new SETCC node, and a new SELECT node, and then return 2272 // the SELECT node, since we were called with a SELECT node. 2273 if (SCC.Val) { 2274 // Check to see if we got a select_cc back (to turn into setcc/select). 2275 // Otherwise, just return whatever node we got back, like fabs. 2276 if (SCC.getOpcode() == ISD::SELECT_CC) { 2277 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2278 SCC.getOperand(0), SCC.getOperand(1), 2279 SCC.getOperand(4)); 2280 AddToWorkList(SETCC.Val); 2281 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2282 SCC.getOperand(3), SETCC); 2283 } 2284 return SCC; 2285 } 2286 return SDOperand(); 2287} 2288 2289/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2290/// are the two values being selected between, see if we can simplify the 2291/// select. 2292/// 2293bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2294 SDOperand RHS) { 2295 2296 // If this is a select from two identical things, try to pull the operation 2297 // through the select. 2298 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2299#if 0 2300 std::cerr << "SELECT: ["; LHS.Val->dump(); 2301 std::cerr << "] ["; RHS.Val->dump(); 2302 std::cerr << "]\n"; 2303#endif 2304 2305 // If this is a load and the token chain is identical, replace the select 2306 // of two loads with a load through a select of the address to load from. 2307 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2308 // constants have been dropped into the constant pool. 2309 if ((LHS.getOpcode() == ISD::LOAD || 2310 LHS.getOpcode() == ISD::EXTLOAD || 2311 LHS.getOpcode() == ISD::ZEXTLOAD || 2312 LHS.getOpcode() == ISD::SEXTLOAD) && 2313 // Token chains must be identical. 2314 LHS.getOperand(0) == RHS.getOperand(0) && 2315 // If this is an EXTLOAD, the VT's must match. 2316 (LHS.getOpcode() == ISD::LOAD || 2317 LHS.getOperand(3) == RHS.getOperand(3))) { 2318 // FIXME: this conflates two src values, discarding one. This is not 2319 // the right thing to do, but nothing uses srcvalues now. When they do, 2320 // turn SrcValue into a list of locations. 2321 SDOperand Addr; 2322 if (TheSelect->getOpcode() == ISD::SELECT) 2323 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2324 TheSelect->getOperand(0), LHS.getOperand(1), 2325 RHS.getOperand(1)); 2326 else 2327 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2328 TheSelect->getOperand(0), 2329 TheSelect->getOperand(1), 2330 LHS.getOperand(1), RHS.getOperand(1), 2331 TheSelect->getOperand(4)); 2332 2333 SDOperand Load; 2334 if (LHS.getOpcode() == ISD::LOAD) 2335 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2336 Addr, LHS.getOperand(2)); 2337 else 2338 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2339 LHS.getOperand(0), Addr, LHS.getOperand(2), 2340 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2341 // Users of the select now use the result of the load. 2342 CombineTo(TheSelect, Load); 2343 2344 // Users of the old loads now use the new load's chain. We know the 2345 // old-load value is dead now. 2346 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2347 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2348 return true; 2349 } 2350 } 2351 2352 return false; 2353} 2354 2355SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2356 SDOperand N2, SDOperand N3, 2357 ISD::CondCode CC) { 2358 2359 MVT::ValueType VT = N2.getValueType(); 2360 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2361 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2362 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2363 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2364 2365 // Determine if the condition we're dealing with is constant 2366 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2367 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2368 2369 // fold select_cc true, x, y -> x 2370 if (SCCC && SCCC->getValue()) 2371 return N2; 2372 // fold select_cc false, x, y -> y 2373 if (SCCC && SCCC->getValue() == 0) 2374 return N3; 2375 2376 // Check to see if we can simplify the select into an fabs node 2377 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2378 // Allow either -0.0 or 0.0 2379 if (CFP->getValue() == 0.0) { 2380 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2381 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2382 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2383 N2 == N3.getOperand(0)) 2384 return DAG.getNode(ISD::FABS, VT, N0); 2385 2386 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2387 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2388 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2389 N2.getOperand(0) == N3) 2390 return DAG.getNode(ISD::FABS, VT, N3); 2391 } 2392 } 2393 2394 // Check to see if we can perform the "gzip trick", transforming 2395 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2396 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2397 MVT::isInteger(N0.getValueType()) && 2398 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2399 MVT::ValueType XType = N0.getValueType(); 2400 MVT::ValueType AType = N2.getValueType(); 2401 if (XType >= AType) { 2402 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2403 // single-bit constant. 2404 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2405 unsigned ShCtV = Log2_64(N2C->getValue()); 2406 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 2407 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 2408 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 2409 AddToWorkList(Shift.Val); 2410 if (XType > AType) { 2411 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2412 AddToWorkList(Shift.Val); 2413 } 2414 return DAG.getNode(ISD::AND, AType, Shift, N2); 2415 } 2416 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2417 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2418 TLI.getShiftAmountTy())); 2419 AddToWorkList(Shift.Val); 2420 if (XType > AType) { 2421 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2422 AddToWorkList(Shift.Val); 2423 } 2424 return DAG.getNode(ISD::AND, AType, Shift, N2); 2425 } 2426 } 2427 2428 // fold select C, 16, 0 -> shl C, 4 2429 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 2430 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 2431 // Get a SetCC of the condition 2432 // FIXME: Should probably make sure that setcc is legal if we ever have a 2433 // target where it isn't. 2434 SDOperand Temp, SCC; 2435 // cast from setcc result type to select result type 2436 if (AfterLegalize) { 2437 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2438 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 2439 } else { 2440 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 2441 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 2442 } 2443 AddToWorkList(SCC.Val); 2444 AddToWorkList(Temp.Val); 2445 // shl setcc result by log2 n2c 2446 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 2447 DAG.getConstant(Log2_64(N2C->getValue()), 2448 TLI.getShiftAmountTy())); 2449 } 2450 2451 // Check to see if this is the equivalent of setcc 2452 // FIXME: Turn all of these into setcc if setcc if setcc is legal 2453 // otherwise, go ahead with the folds. 2454 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 2455 MVT::ValueType XType = N0.getValueType(); 2456 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 2457 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2458 if (Res.getValueType() != VT) 2459 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 2460 return Res; 2461 } 2462 2463 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 2464 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 2465 TLI.isOperationLegal(ISD::CTLZ, XType)) { 2466 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 2467 return DAG.getNode(ISD::SRL, XType, Ctlz, 2468 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 2469 TLI.getShiftAmountTy())); 2470 } 2471 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 2472 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 2473 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 2474 N0); 2475 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 2476 DAG.getConstant(~0ULL, XType)); 2477 return DAG.getNode(ISD::SRL, XType, 2478 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 2479 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2480 TLI.getShiftAmountTy())); 2481 } 2482 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 2483 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 2484 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 2485 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2486 TLI.getShiftAmountTy())); 2487 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 2488 } 2489 } 2490 2491 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 2492 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2493 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 2494 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 2495 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 2496 MVT::ValueType XType = N0.getValueType(); 2497 if (SubC->isNullValue() && MVT::isInteger(XType)) { 2498 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2499 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2500 TLI.getShiftAmountTy())); 2501 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 2502 AddToWorkList(Shift.Val); 2503 AddToWorkList(Add.Val); 2504 return DAG.getNode(ISD::XOR, XType, Add, Shift); 2505 } 2506 } 2507 } 2508 2509 return SDOperand(); 2510} 2511 2512SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 2513 SDOperand N1, ISD::CondCode Cond, 2514 bool foldBooleans) { 2515 // These setcc operations always fold. 2516 switch (Cond) { 2517 default: break; 2518 case ISD::SETFALSE: 2519 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 2520 case ISD::SETTRUE: 2521 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 2522 } 2523 2524 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 2525 uint64_t C1 = N1C->getValue(); 2526 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 2527 uint64_t C0 = N0C->getValue(); 2528 2529 // Sign extend the operands if required 2530 if (ISD::isSignedIntSetCC(Cond)) { 2531 C0 = N0C->getSignExtended(); 2532 C1 = N1C->getSignExtended(); 2533 } 2534 2535 switch (Cond) { 2536 default: assert(0 && "Unknown integer setcc!"); 2537 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2538 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2539 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 2540 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 2541 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 2542 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 2543 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 2544 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 2545 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 2546 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 2547 } 2548 } else { 2549 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2550 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2551 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 2552 2553 // If the comparison constant has bits in the upper part, the 2554 // zero-extended value could never match. 2555 if (C1 & (~0ULL << InSize)) { 2556 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 2557 switch (Cond) { 2558 case ISD::SETUGT: 2559 case ISD::SETUGE: 2560 case ISD::SETEQ: return DAG.getConstant(0, VT); 2561 case ISD::SETULT: 2562 case ISD::SETULE: 2563 case ISD::SETNE: return DAG.getConstant(1, VT); 2564 case ISD::SETGT: 2565 case ISD::SETGE: 2566 // True if the sign bit of C1 is set. 2567 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 2568 case ISD::SETLT: 2569 case ISD::SETLE: 2570 // True if the sign bit of C1 isn't set. 2571 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 2572 default: 2573 break; 2574 } 2575 } 2576 2577 // Otherwise, we can perform the comparison with the low bits. 2578 switch (Cond) { 2579 case ISD::SETEQ: 2580 case ISD::SETNE: 2581 case ISD::SETUGT: 2582 case ISD::SETUGE: 2583 case ISD::SETULT: 2584 case ISD::SETULE: 2585 return DAG.getSetCC(VT, N0.getOperand(0), 2586 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 2587 Cond); 2588 default: 2589 break; // todo, be more careful with signed comparisons 2590 } 2591 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2592 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2593 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2594 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 2595 MVT::ValueType ExtDstTy = N0.getValueType(); 2596 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 2597 2598 // If the extended part has any inconsistent bits, it cannot ever 2599 // compare equal. In other words, they have to be all ones or all 2600 // zeros. 2601 uint64_t ExtBits = 2602 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 2603 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 2604 return DAG.getConstant(Cond == ISD::SETNE, VT); 2605 2606 SDOperand ZextOp; 2607 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 2608 if (Op0Ty == ExtSrcTy) { 2609 ZextOp = N0.getOperand(0); 2610 } else { 2611 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 2612 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 2613 DAG.getConstant(Imm, Op0Ty)); 2614 } 2615 AddToWorkList(ZextOp.Val); 2616 // Otherwise, make this a use of a zext. 2617 return DAG.getSetCC(VT, ZextOp, 2618 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 2619 ExtDstTy), 2620 Cond); 2621 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 2622 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2623 (N0.getOpcode() == ISD::XOR || 2624 (N0.getOpcode() == ISD::AND && 2625 N0.getOperand(0).getOpcode() == ISD::XOR && 2626 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2627 isa<ConstantSDNode>(N0.getOperand(1)) && 2628 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 2629 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 2630 // only do this if the top bits are known zero. 2631 if (TLI.MaskedValueIsZero(N1, 2632 MVT::getIntVTBitMask(N0.getValueType())-1)) { 2633 // Okay, get the un-inverted input value. 2634 SDOperand Val; 2635 if (N0.getOpcode() == ISD::XOR) 2636 Val = N0.getOperand(0); 2637 else { 2638 assert(N0.getOpcode() == ISD::AND && 2639 N0.getOperand(0).getOpcode() == ISD::XOR); 2640 // ((X^1)&1)^1 -> X & 1 2641 Val = DAG.getNode(ISD::AND, N0.getValueType(), 2642 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 2643 } 2644 return DAG.getSetCC(VT, Val, N1, 2645 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2646 } 2647 } 2648 2649 uint64_t MinVal, MaxVal; 2650 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 2651 if (ISD::isSignedIntSetCC(Cond)) { 2652 MinVal = 1ULL << (OperandBitSize-1); 2653 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2654 MaxVal = ~0ULL >> (65-OperandBitSize); 2655 else 2656 MaxVal = 0; 2657 } else { 2658 MinVal = 0; 2659 MaxVal = ~0ULL >> (64-OperandBitSize); 2660 } 2661 2662 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2663 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2664 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2665 --C1; // X >= C0 --> X > (C0-1) 2666 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2667 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2668 } 2669 2670 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2671 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2672 ++C1; // X <= C0 --> X < (C0+1) 2673 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2674 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2675 } 2676 2677 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2678 return DAG.getConstant(0, VT); // X < MIN --> false 2679 2680 // Canonicalize setgt X, Min --> setne X, Min 2681 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2682 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2683 // Canonicalize setlt X, Max --> setne X, Max 2684 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2685 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2686 2687 // If we have setult X, 1, turn it into seteq X, 0 2688 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2689 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2690 ISD::SETEQ); 2691 // If we have setugt X, Max-1, turn it into seteq X, Max 2692 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2693 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2694 ISD::SETEQ); 2695 2696 // If we have "setcc X, C0", check to see if we can shrink the immediate 2697 // by changing cc. 2698 2699 // SETUGT X, SINTMAX -> SETLT X, 0 2700 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2701 C1 == (~0ULL >> (65-OperandBitSize))) 2702 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2703 ISD::SETLT); 2704 2705 // FIXME: Implement the rest of these. 2706 2707 // Fold bit comparisons when we can. 2708 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2709 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2710 if (ConstantSDNode *AndRHS = 2711 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2712 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2713 // Perform the xform if the AND RHS is a single bit. 2714 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2715 return DAG.getNode(ISD::SRL, VT, N0, 2716 DAG.getConstant(Log2_64(AndRHS->getValue()), 2717 TLI.getShiftAmountTy())); 2718 } 2719 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2720 // (X & 8) == 8 --> (X & 8) >> 3 2721 // Perform the xform if C1 is a single bit. 2722 if ((C1 & (C1-1)) == 0) { 2723 return DAG.getNode(ISD::SRL, VT, N0, 2724 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2725 } 2726 } 2727 } 2728 } 2729 } else if (isa<ConstantSDNode>(N0.Val)) { 2730 // Ensure that the constant occurs on the RHS. 2731 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2732 } 2733 2734 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2735 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2736 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2737 2738 switch (Cond) { 2739 default: break; // FIXME: Implement the rest of these! 2740 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2741 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2742 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2743 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2744 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2745 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2746 } 2747 } else { 2748 // Ensure that the constant occurs on the RHS. 2749 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2750 } 2751 2752 if (N0 == N1) { 2753 // We can always fold X == Y for integer setcc's. 2754 if (MVT::isInteger(N0.getValueType())) 2755 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2756 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2757 if (UOF == 2) // FP operators that are undefined on NaNs. 2758 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2759 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2760 return DAG.getConstant(UOF, VT); 2761 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2762 // if it is not already. 2763 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2764 if (NewCond != Cond) 2765 return DAG.getSetCC(VT, N0, N1, NewCond); 2766 } 2767 2768 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2769 MVT::isInteger(N0.getValueType())) { 2770 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2771 N0.getOpcode() == ISD::XOR) { 2772 // Simplify (X+Y) == (X+Z) --> Y == Z 2773 if (N0.getOpcode() == N1.getOpcode()) { 2774 if (N0.getOperand(0) == N1.getOperand(0)) 2775 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2776 if (N0.getOperand(1) == N1.getOperand(1)) 2777 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2778 if (isCommutativeBinOp(N0.getOpcode())) { 2779 // If X op Y == Y op X, try other combinations. 2780 if (N0.getOperand(0) == N1.getOperand(1)) 2781 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2782 if (N0.getOperand(1) == N1.getOperand(0)) 2783 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 2784 } 2785 } 2786 2787 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2788 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2789 // Turn (X+C1) == C2 --> X == C2-C1 2790 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 2791 return DAG.getSetCC(VT, N0.getOperand(0), 2792 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 2793 N0.getValueType()), Cond); 2794 } 2795 2796 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2797 if (N0.getOpcode() == ISD::XOR) 2798 // If we know that all of the inverted bits are zero, don't bother 2799 // performing the inversion. 2800 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 2801 return DAG.getSetCC(VT, N0.getOperand(0), 2802 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 2803 N0.getValueType()), Cond); 2804 } 2805 2806 // Turn (C1-X) == C2 --> X == C1-C2 2807 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2808 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 2809 return DAG.getSetCC(VT, N0.getOperand(1), 2810 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 2811 N0.getValueType()), Cond); 2812 } 2813 } 2814 } 2815 2816 // Simplify (X+Z) == X --> Z == 0 2817 if (N0.getOperand(0) == N1) 2818 return DAG.getSetCC(VT, N0.getOperand(1), 2819 DAG.getConstant(0, N0.getValueType()), Cond); 2820 if (N0.getOperand(1) == N1) { 2821 if (isCommutativeBinOp(N0.getOpcode())) 2822 return DAG.getSetCC(VT, N0.getOperand(0), 2823 DAG.getConstant(0, N0.getValueType()), Cond); 2824 else { 2825 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2826 // (Z-X) == X --> Z == X<<1 2827 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2828 N1, 2829 DAG.getConstant(1,TLI.getShiftAmountTy())); 2830 AddToWorkList(SH.Val); 2831 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2832 } 2833 } 2834 } 2835 2836 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2837 N1.getOpcode() == ISD::XOR) { 2838 // Simplify X == (X+Z) --> Z == 0 2839 if (N1.getOperand(0) == N0) { 2840 return DAG.getSetCC(VT, N1.getOperand(1), 2841 DAG.getConstant(0, N1.getValueType()), Cond); 2842 } else if (N1.getOperand(1) == N0) { 2843 if (isCommutativeBinOp(N1.getOpcode())) { 2844 return DAG.getSetCC(VT, N1.getOperand(0), 2845 DAG.getConstant(0, N1.getValueType()), Cond); 2846 } else { 2847 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2848 // X == (Z-X) --> X<<1 == Z 2849 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2850 DAG.getConstant(1,TLI.getShiftAmountTy())); 2851 AddToWorkList(SH.Val); 2852 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2853 } 2854 } 2855 } 2856 } 2857 2858 // Fold away ALL boolean setcc's. 2859 SDOperand Temp; 2860 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2861 switch (Cond) { 2862 default: assert(0 && "Unknown integer setcc!"); 2863 case ISD::SETEQ: // X == Y -> (X^Y)^1 2864 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2865 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2866 AddToWorkList(Temp.Val); 2867 break; 2868 case ISD::SETNE: // X != Y --> (X^Y) 2869 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2870 break; 2871 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2872 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2873 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2874 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2875 AddToWorkList(Temp.Val); 2876 break; 2877 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2878 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2879 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2880 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2881 AddToWorkList(Temp.Val); 2882 break; 2883 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2884 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2885 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2886 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2887 AddToWorkList(Temp.Val); 2888 break; 2889 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2890 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2891 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2892 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2893 break; 2894 } 2895 if (VT != MVT::i1) { 2896 AddToWorkList(N0.Val); 2897 // FIXME: If running after legalize, we probably can't do this. 2898 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2899 } 2900 return N0; 2901 } 2902 2903 // Could not fold it. 2904 return SDOperand(); 2905} 2906 2907/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2908/// return a DAG expression to select that will generate the same value by 2909/// multiplying by a magic number. See: 2910/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2911SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 2912 MVT::ValueType VT = N->getValueType(0); 2913 2914 // Check to see if we can do this. 2915 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2916 return SDOperand(); // BuildSDIV only operates on i32 or i64 2917 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 2918 return SDOperand(); // Make sure the target supports MULHS. 2919 2920 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2921 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2922 2923 // Multiply the numerator (operand 0) by the magic value 2924 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2925 DAG.getConstant(magics.m, VT)); 2926 // If d > 0 and m < 0, add the numerator 2927 if (d > 0 && magics.m < 0) { 2928 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2929 AddToWorkList(Q.Val); 2930 } 2931 // If d < 0 and m > 0, subtract the numerator. 2932 if (d < 0 && magics.m > 0) { 2933 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2934 AddToWorkList(Q.Val); 2935 } 2936 // Shift right algebraic if shift value is nonzero 2937 if (magics.s > 0) { 2938 Q = DAG.getNode(ISD::SRA, VT, Q, 2939 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2940 AddToWorkList(Q.Val); 2941 } 2942 // Extract the sign bit and add it to the quotient 2943 SDOperand T = 2944 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 2945 TLI.getShiftAmountTy())); 2946 AddToWorkList(T.Val); 2947 return DAG.getNode(ISD::ADD, VT, Q, T); 2948} 2949 2950/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2951/// return a DAG expression to select that will generate the same value by 2952/// multiplying by a magic number. See: 2953/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2954SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 2955 MVT::ValueType VT = N->getValueType(0); 2956 2957 // Check to see if we can do this. 2958 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2959 return SDOperand(); // BuildUDIV only operates on i32 or i64 2960 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 2961 return SDOperand(); // Make sure the target supports MULHU. 2962 2963 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2964 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2965 2966 // Multiply the numerator (operand 0) by the magic value 2967 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2968 DAG.getConstant(magics.m, VT)); 2969 AddToWorkList(Q.Val); 2970 2971 if (magics.a == 0) { 2972 return DAG.getNode(ISD::SRL, VT, Q, 2973 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2974 } else { 2975 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2976 AddToWorkList(NPQ.Val); 2977 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2978 DAG.getConstant(1, TLI.getShiftAmountTy())); 2979 AddToWorkList(NPQ.Val); 2980 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2981 AddToWorkList(NPQ.Val); 2982 return DAG.getNode(ISD::SRL, VT, NPQ, 2983 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 2984 } 2985} 2986 2987// SelectionDAG::Combine - This is the entry point for the file. 2988// 2989void SelectionDAG::Combine(bool RunningAfterLegalize) { 2990 /// run - This is the main entry point to this class. 2991 /// 2992 DAGCombiner(*this).Run(RunningAfterLegalize); 2993} 2994