DAGCombiner.cpp revision 204301f0459c1deb6c535723760c848ba2fcd42b
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/SmallPtrSet.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/Analysis/AliasAnalysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/DataLayout.h" 27#include "llvm/DerivedTypes.h" 28#include "llvm/LLVMContext.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/ErrorHandling.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetLowering.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetOptions.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue SimplifyVUnaryOp(SDNode *N); 198 SDValue visitSHL(SDNode *N); 199 SDValue visitSRA(SDNode *N); 200 SDValue visitSRL(SDNode *N); 201 SDValue visitCTLZ(SDNode *N); 202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 203 SDValue visitCTTZ(SDNode *N); 204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 205 SDValue visitCTPOP(SDNode *N); 206 SDValue visitSELECT(SDNode *N); 207 SDValue visitSELECT_CC(SDNode *N); 208 SDValue visitSETCC(SDNode *N); 209 SDValue visitSIGN_EXTEND(SDNode *N); 210 SDValue visitZERO_EXTEND(SDNode *N); 211 SDValue visitANY_EXTEND(SDNode *N); 212 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 213 SDValue visitTRUNCATE(SDNode *N); 214 SDValue visitBITCAST(SDNode *N); 215 SDValue visitBUILD_PAIR(SDNode *N); 216 SDValue visitFADD(SDNode *N); 217 SDValue visitFSUB(SDNode *N); 218 SDValue visitFMUL(SDNode *N); 219 SDValue visitFMA(SDNode *N); 220 SDValue visitFDIV(SDNode *N); 221 SDValue visitFREM(SDNode *N); 222 SDValue visitFCOPYSIGN(SDNode *N); 223 SDValue visitSINT_TO_FP(SDNode *N); 224 SDValue visitUINT_TO_FP(SDNode *N); 225 SDValue visitFP_TO_SINT(SDNode *N); 226 SDValue visitFP_TO_UINT(SDNode *N); 227 SDValue visitFP_ROUND(SDNode *N); 228 SDValue visitFP_ROUND_INREG(SDNode *N); 229 SDValue visitFP_EXTEND(SDNode *N); 230 SDValue visitFNEG(SDNode *N); 231 SDValue visitFABS(SDNode *N); 232 SDValue visitFCEIL(SDNode *N); 233 SDValue visitFTRUNC(SDNode *N); 234 SDValue visitFFLOOR(SDNode *N); 235 SDValue visitBRCOND(SDNode *N); 236 SDValue visitBR_CC(SDNode *N); 237 SDValue visitLOAD(SDNode *N); 238 SDValue visitSTORE(SDNode *N); 239 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 241 SDValue visitBUILD_VECTOR(SDNode *N); 242 SDValue visitCONCAT_VECTORS(SDNode *N); 243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 244 SDValue visitVECTOR_SHUFFLE(SDNode *N); 245 SDValue visitMEMBARRIER(SDNode *N); 246 247 SDValue XformToShuffleWithZero(SDNode *N); 248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 249 250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 251 252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 256 SDValue N3, ISD::CondCode CC, 257 bool NotExtCompare = false); 258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 259 DebugLoc DL, bool foldBooleans = true); 260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 261 unsigned HiOp); 262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 264 SDValue BuildSDIV(SDNode *N); 265 SDValue BuildUDIV(SDNode *N); 266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 267 bool DemandHighBits = true); 268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 270 SDValue ReduceLoadWidth(SDNode *N); 271 SDValue ReduceLoadOpStoreWidth(SDNode *N); 272 SDValue TransformFPLoadStorePair(SDNode *N); 273 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N); 274 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N); 275 276 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 277 278 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 279 /// looking for aliasing nodes and adding them to the Aliases vector. 280 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 281 SmallVector<SDValue, 8> &Aliases); 282 283 /// isAlias - Return true if there is any possibility that the two addresses 284 /// overlap. 285 bool isAlias(SDValue Ptr1, int64_t Size1, 286 const Value *SrcValue1, int SrcValueOffset1, 287 unsigned SrcValueAlign1, 288 const MDNode *TBAAInfo1, 289 SDValue Ptr2, int64_t Size2, 290 const Value *SrcValue2, int SrcValueOffset2, 291 unsigned SrcValueAlign2, 292 const MDNode *TBAAInfo2) const; 293 294 /// isAlias - Return true if there is any possibility that the two addresses 295 /// overlap. 296 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1); 297 298 /// FindAliasInfo - Extracts the relevant alias information from the memory 299 /// node. Returns true if the operand was a load. 300 bool FindAliasInfo(SDNode *N, 301 SDValue &Ptr, int64_t &Size, 302 const Value *&SrcValue, int &SrcValueOffset, 303 unsigned &SrcValueAlignment, 304 const MDNode *&TBAAInfo) const; 305 306 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 307 /// looking for a better chain (aliasing node.) 308 SDValue FindBetterChain(SDNode *N, SDValue Chain); 309 310 /// Merge consecutive store operations into a wide store. 311 /// This optimization uses wide integers or vectors when possible. 312 /// \return True if some memory operations were changed. 313 bool MergeConsecutiveStores(StoreSDNode *N); 314 315 public: 316 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 317 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 318 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 319 320 /// Run - runs the dag combiner on all nodes in the work list 321 void Run(CombineLevel AtLevel); 322 323 SelectionDAG &getDAG() const { return DAG; } 324 325 /// getShiftAmountTy - Returns a type large enough to hold any valid 326 /// shift amount - before type legalization these can be huge. 327 EVT getShiftAmountTy(EVT LHSTy) { 328 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 329 } 330 331 /// isTypeLegal - This method returns true if we are running before type 332 /// legalization or if the specified VT is legal. 333 bool isTypeLegal(const EVT &VT) { 334 if (!LegalTypes) return true; 335 return TLI.isTypeLegal(VT); 336 } 337 }; 338} 339 340 341namespace { 342/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 343/// nodes from the worklist. 344class WorkListRemover : public SelectionDAG::DAGUpdateListener { 345 DAGCombiner &DC; 346public: 347 explicit WorkListRemover(DAGCombiner &dc) 348 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 349 350 virtual void NodeDeleted(SDNode *N, SDNode *E) { 351 DC.removeFromWorkList(N); 352 } 353}; 354} 355 356//===----------------------------------------------------------------------===// 357// TargetLowering::DAGCombinerInfo implementation 358//===----------------------------------------------------------------------===// 359 360void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 361 ((DAGCombiner*)DC)->AddToWorkList(N); 362} 363 364void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 365 ((DAGCombiner*)DC)->removeFromWorkList(N); 366} 367 368SDValue TargetLowering::DAGCombinerInfo:: 369CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 370 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 371} 372 373SDValue TargetLowering::DAGCombinerInfo:: 374CombineTo(SDNode *N, SDValue Res, bool AddTo) { 375 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 376} 377 378 379SDValue TargetLowering::DAGCombinerInfo:: 380CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 381 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 382} 383 384void TargetLowering::DAGCombinerInfo:: 385CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 386 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 387} 388 389//===----------------------------------------------------------------------===// 390// Helper Functions 391//===----------------------------------------------------------------------===// 392 393/// isNegatibleForFree - Return 1 if we can compute the negated form of the 394/// specified expression for the same cost as the expression itself, or 2 if we 395/// can compute the negated form more cheaply than the expression itself. 396static char isNegatibleForFree(SDValue Op, bool LegalOperations, 397 const TargetLowering &TLI, 398 const TargetOptions *Options, 399 unsigned Depth = 0) { 400 // fneg is removable even if it has multiple uses. 401 if (Op.getOpcode() == ISD::FNEG) return 2; 402 403 // Don't allow anything with multiple uses. 404 if (!Op.hasOneUse()) return 0; 405 406 // Don't recurse exponentially. 407 if (Depth > 6) return 0; 408 409 switch (Op.getOpcode()) { 410 default: return false; 411 case ISD::ConstantFP: 412 // Don't invert constant FP values after legalize. The negated constant 413 // isn't necessarily legal. 414 return LegalOperations ? 0 : 1; 415 case ISD::FADD: 416 // FIXME: determine better conditions for this xform. 417 if (!Options->UnsafeFPMath) return 0; 418 419 // After operation legalization, it might not be legal to create new FSUBs. 420 if (LegalOperations && 421 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 422 return 0; 423 424 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 425 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 426 Options, Depth + 1)) 427 return V; 428 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 429 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 430 Depth + 1); 431 case ISD::FSUB: 432 // We can't turn -(A-B) into B-A when we honor signed zeros. 433 if (!Options->UnsafeFPMath) return 0; 434 435 // fold (fneg (fsub A, B)) -> (fsub B, A) 436 return 1; 437 438 case ISD::FMUL: 439 case ISD::FDIV: 440 if (Options->HonorSignDependentRoundingFPMath()) return 0; 441 442 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 443 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 444 Options, Depth + 1)) 445 return V; 446 447 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 448 Depth + 1); 449 450 case ISD::FP_EXTEND: 451 case ISD::FP_ROUND: 452 case ISD::FSIN: 453 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 454 Depth + 1); 455 } 456} 457 458/// GetNegatedExpression - If isNegatibleForFree returns true, this function 459/// returns the newly negated expression. 460static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 461 bool LegalOperations, unsigned Depth = 0) { 462 // fneg is removable even if it has multiple uses. 463 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 464 465 // Don't allow anything with multiple uses. 466 assert(Op.hasOneUse() && "Unknown reuse!"); 467 468 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 469 switch (Op.getOpcode()) { 470 default: llvm_unreachable("Unknown code"); 471 case ISD::ConstantFP: { 472 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 473 V.changeSign(); 474 return DAG.getConstantFP(V, Op.getValueType()); 475 } 476 case ISD::FADD: 477 // FIXME: determine better conditions for this xform. 478 assert(DAG.getTarget().Options.UnsafeFPMath); 479 480 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 481 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 482 DAG.getTargetLoweringInfo(), 483 &DAG.getTarget().Options, Depth+1)) 484 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 485 GetNegatedExpression(Op.getOperand(0), DAG, 486 LegalOperations, Depth+1), 487 Op.getOperand(1)); 488 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 489 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 490 GetNegatedExpression(Op.getOperand(1), DAG, 491 LegalOperations, Depth+1), 492 Op.getOperand(0)); 493 case ISD::FSUB: 494 // We can't turn -(A-B) into B-A when we honor signed zeros. 495 assert(DAG.getTarget().Options.UnsafeFPMath); 496 497 // fold (fneg (fsub 0, B)) -> B 498 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 499 if (N0CFP->getValueAPF().isZero()) 500 return Op.getOperand(1); 501 502 // fold (fneg (fsub A, B)) -> (fsub B, A) 503 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 504 Op.getOperand(1), Op.getOperand(0)); 505 506 case ISD::FMUL: 507 case ISD::FDIV: 508 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 509 510 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 511 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 512 DAG.getTargetLoweringInfo(), 513 &DAG.getTarget().Options, Depth+1)) 514 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 515 GetNegatedExpression(Op.getOperand(0), DAG, 516 LegalOperations, Depth+1), 517 Op.getOperand(1)); 518 519 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 520 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 521 Op.getOperand(0), 522 GetNegatedExpression(Op.getOperand(1), DAG, 523 LegalOperations, Depth+1)); 524 525 case ISD::FP_EXTEND: 526 case ISD::FSIN: 527 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 528 GetNegatedExpression(Op.getOperand(0), DAG, 529 LegalOperations, Depth+1)); 530 case ISD::FP_ROUND: 531 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 532 GetNegatedExpression(Op.getOperand(0), DAG, 533 LegalOperations, Depth+1), 534 Op.getOperand(1)); 535 } 536} 537 538 539// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 540// that selects between the values 1 and 0, making it equivalent to a setcc. 541// Also, set the incoming LHS, RHS, and CC references to the appropriate 542// nodes based on the type of node we are checking. This simplifies life a 543// bit for the callers. 544static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 545 SDValue &CC) { 546 if (N.getOpcode() == ISD::SETCC) { 547 LHS = N.getOperand(0); 548 RHS = N.getOperand(1); 549 CC = N.getOperand(2); 550 return true; 551 } 552 if (N.getOpcode() == ISD::SELECT_CC && 553 N.getOperand(2).getOpcode() == ISD::Constant && 554 N.getOperand(3).getOpcode() == ISD::Constant && 555 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 556 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 557 LHS = N.getOperand(0); 558 RHS = N.getOperand(1); 559 CC = N.getOperand(4); 560 return true; 561 } 562 return false; 563} 564 565// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 566// one use. If this is true, it allows the users to invert the operation for 567// free when it is profitable to do so. 568static bool isOneUseSetCC(SDValue N) { 569 SDValue N0, N1, N2; 570 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 571 return true; 572 return false; 573} 574 575SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 576 SDValue N0, SDValue N1) { 577 EVT VT = N0.getValueType(); 578 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 579 if (isa<ConstantSDNode>(N1)) { 580 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 581 SDValue OpNode = 582 DAG.FoldConstantArithmetic(Opc, VT, 583 cast<ConstantSDNode>(N0.getOperand(1)), 584 cast<ConstantSDNode>(N1)); 585 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 586 } 587 if (N0.hasOneUse()) { 588 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 589 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 590 N0.getOperand(0), N1); 591 AddToWorkList(OpNode.getNode()); 592 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 593 } 594 } 595 596 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 597 if (isa<ConstantSDNode>(N0)) { 598 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 599 SDValue OpNode = 600 DAG.FoldConstantArithmetic(Opc, VT, 601 cast<ConstantSDNode>(N1.getOperand(1)), 602 cast<ConstantSDNode>(N0)); 603 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 604 } 605 if (N1.hasOneUse()) { 606 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 607 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 608 N1.getOperand(0), N0); 609 AddToWorkList(OpNode.getNode()); 610 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 611 } 612 } 613 614 return SDValue(); 615} 616 617SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 618 bool AddTo) { 619 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 620 ++NodesCombined; 621 DEBUG(dbgs() << "\nReplacing.1 "; 622 N->dump(&DAG); 623 dbgs() << "\nWith: "; 624 To[0].getNode()->dump(&DAG); 625 dbgs() << " and " << NumTo-1 << " other values\n"; 626 for (unsigned i = 0, e = NumTo; i != e; ++i) 627 assert((!To[i].getNode() || 628 N->getValueType(i) == To[i].getValueType()) && 629 "Cannot combine value to value of different type!")); 630 WorkListRemover DeadNodes(*this); 631 DAG.ReplaceAllUsesWith(N, To); 632 if (AddTo) { 633 // Push the new nodes and any users onto the worklist 634 for (unsigned i = 0, e = NumTo; i != e; ++i) { 635 if (To[i].getNode()) { 636 AddToWorkList(To[i].getNode()); 637 AddUsersToWorkList(To[i].getNode()); 638 } 639 } 640 } 641 642 // Finally, if the node is now dead, remove it from the graph. The node 643 // may not be dead if the replacement process recursively simplified to 644 // something else needing this node. 645 if (N->use_empty()) { 646 // Nodes can be reintroduced into the worklist. Make sure we do not 647 // process a node that has been replaced. 648 removeFromWorkList(N); 649 650 // Finally, since the node is now dead, remove it from the graph. 651 DAG.DeleteNode(N); 652 } 653 return SDValue(N, 0); 654} 655 656void DAGCombiner:: 657CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 658 // Replace all uses. If any nodes become isomorphic to other nodes and 659 // are deleted, make sure to remove them from our worklist. 660 WorkListRemover DeadNodes(*this); 661 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 662 663 // Push the new node and any (possibly new) users onto the worklist. 664 AddToWorkList(TLO.New.getNode()); 665 AddUsersToWorkList(TLO.New.getNode()); 666 667 // Finally, if the node is now dead, remove it from the graph. The node 668 // may not be dead if the replacement process recursively simplified to 669 // something else needing this node. 670 if (TLO.Old.getNode()->use_empty()) { 671 removeFromWorkList(TLO.Old.getNode()); 672 673 // If the operands of this node are only used by the node, they will now 674 // be dead. Make sure to visit them first to delete dead nodes early. 675 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 676 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 677 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 678 679 DAG.DeleteNode(TLO.Old.getNode()); 680 } 681} 682 683/// SimplifyDemandedBits - Check the specified integer node value to see if 684/// it can be simplified or if things it uses can be simplified by bit 685/// propagation. If so, return true. 686bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 687 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 688 APInt KnownZero, KnownOne; 689 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 690 return false; 691 692 // Revisit the node. 693 AddToWorkList(Op.getNode()); 694 695 // Replace the old value with the new one. 696 ++NodesCombined; 697 DEBUG(dbgs() << "\nReplacing.2 "; 698 TLO.Old.getNode()->dump(&DAG); 699 dbgs() << "\nWith: "; 700 TLO.New.getNode()->dump(&DAG); 701 dbgs() << '\n'); 702 703 CommitTargetLoweringOpt(TLO); 704 return true; 705} 706 707void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 708 DebugLoc dl = Load->getDebugLoc(); 709 EVT VT = Load->getValueType(0); 710 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 711 712 DEBUG(dbgs() << "\nReplacing.9 "; 713 Load->dump(&DAG); 714 dbgs() << "\nWith: "; 715 Trunc.getNode()->dump(&DAG); 716 dbgs() << '\n'); 717 WorkListRemover DeadNodes(*this); 718 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 719 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 720 removeFromWorkList(Load); 721 DAG.DeleteNode(Load); 722 AddToWorkList(Trunc.getNode()); 723} 724 725SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 726 Replace = false; 727 DebugLoc dl = Op.getDebugLoc(); 728 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 729 EVT MemVT = LD->getMemoryVT(); 730 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 731 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 732 : ISD::EXTLOAD) 733 : LD->getExtensionType(); 734 Replace = true; 735 return DAG.getExtLoad(ExtType, dl, PVT, 736 LD->getChain(), LD->getBasePtr(), 737 LD->getPointerInfo(), 738 MemVT, LD->isVolatile(), 739 LD->isNonTemporal(), LD->getAlignment()); 740 } 741 742 unsigned Opc = Op.getOpcode(); 743 switch (Opc) { 744 default: break; 745 case ISD::AssertSext: 746 return DAG.getNode(ISD::AssertSext, dl, PVT, 747 SExtPromoteOperand(Op.getOperand(0), PVT), 748 Op.getOperand(1)); 749 case ISD::AssertZext: 750 return DAG.getNode(ISD::AssertZext, dl, PVT, 751 ZExtPromoteOperand(Op.getOperand(0), PVT), 752 Op.getOperand(1)); 753 case ISD::Constant: { 754 unsigned ExtOpc = 755 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 756 return DAG.getNode(ExtOpc, dl, PVT, Op); 757 } 758 } 759 760 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 761 return SDValue(); 762 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 763} 764 765SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 766 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 767 return SDValue(); 768 EVT OldVT = Op.getValueType(); 769 DebugLoc dl = Op.getDebugLoc(); 770 bool Replace = false; 771 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 772 if (NewOp.getNode() == 0) 773 return SDValue(); 774 AddToWorkList(NewOp.getNode()); 775 776 if (Replace) 777 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 778 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 779 DAG.getValueType(OldVT)); 780} 781 782SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 783 EVT OldVT = Op.getValueType(); 784 DebugLoc dl = Op.getDebugLoc(); 785 bool Replace = false; 786 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 787 if (NewOp.getNode() == 0) 788 return SDValue(); 789 AddToWorkList(NewOp.getNode()); 790 791 if (Replace) 792 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 793 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 794} 795 796/// PromoteIntBinOp - Promote the specified integer binary operation if the 797/// target indicates it is beneficial. e.g. On x86, it's usually better to 798/// promote i16 operations to i32 since i16 instructions are longer. 799SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 800 if (!LegalOperations) 801 return SDValue(); 802 803 EVT VT = Op.getValueType(); 804 if (VT.isVector() || !VT.isInteger()) 805 return SDValue(); 806 807 // If operation type is 'undesirable', e.g. i16 on x86, consider 808 // promoting it. 809 unsigned Opc = Op.getOpcode(); 810 if (TLI.isTypeDesirableForOp(Opc, VT)) 811 return SDValue(); 812 813 EVT PVT = VT; 814 // Consult target whether it is a good idea to promote this operation and 815 // what's the right type to promote it to. 816 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 817 assert(PVT != VT && "Don't know what type to promote to!"); 818 819 bool Replace0 = false; 820 SDValue N0 = Op.getOperand(0); 821 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 822 if (NN0.getNode() == 0) 823 return SDValue(); 824 825 bool Replace1 = false; 826 SDValue N1 = Op.getOperand(1); 827 SDValue NN1; 828 if (N0 == N1) 829 NN1 = NN0; 830 else { 831 NN1 = PromoteOperand(N1, PVT, Replace1); 832 if (NN1.getNode() == 0) 833 return SDValue(); 834 } 835 836 AddToWorkList(NN0.getNode()); 837 if (NN1.getNode()) 838 AddToWorkList(NN1.getNode()); 839 840 if (Replace0) 841 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 842 if (Replace1) 843 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 844 845 DEBUG(dbgs() << "\nPromoting "; 846 Op.getNode()->dump(&DAG)); 847 DebugLoc dl = Op.getDebugLoc(); 848 return DAG.getNode(ISD::TRUNCATE, dl, VT, 849 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 850 } 851 return SDValue(); 852} 853 854/// PromoteIntShiftOp - Promote the specified integer shift operation if the 855/// target indicates it is beneficial. e.g. On x86, it's usually better to 856/// promote i16 operations to i32 since i16 instructions are longer. 857SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 858 if (!LegalOperations) 859 return SDValue(); 860 861 EVT VT = Op.getValueType(); 862 if (VT.isVector() || !VT.isInteger()) 863 return SDValue(); 864 865 // If operation type is 'undesirable', e.g. i16 on x86, consider 866 // promoting it. 867 unsigned Opc = Op.getOpcode(); 868 if (TLI.isTypeDesirableForOp(Opc, VT)) 869 return SDValue(); 870 871 EVT PVT = VT; 872 // Consult target whether it is a good idea to promote this operation and 873 // what's the right type to promote it to. 874 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 875 assert(PVT != VT && "Don't know what type to promote to!"); 876 877 bool Replace = false; 878 SDValue N0 = Op.getOperand(0); 879 if (Opc == ISD::SRA) 880 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 881 else if (Opc == ISD::SRL) 882 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 883 else 884 N0 = PromoteOperand(N0, PVT, Replace); 885 if (N0.getNode() == 0) 886 return SDValue(); 887 888 AddToWorkList(N0.getNode()); 889 if (Replace) 890 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 891 892 DEBUG(dbgs() << "\nPromoting "; 893 Op.getNode()->dump(&DAG)); 894 DebugLoc dl = Op.getDebugLoc(); 895 return DAG.getNode(ISD::TRUNCATE, dl, VT, 896 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 897 } 898 return SDValue(); 899} 900 901SDValue DAGCombiner::PromoteExtend(SDValue Op) { 902 if (!LegalOperations) 903 return SDValue(); 904 905 EVT VT = Op.getValueType(); 906 if (VT.isVector() || !VT.isInteger()) 907 return SDValue(); 908 909 // If operation type is 'undesirable', e.g. i16 on x86, consider 910 // promoting it. 911 unsigned Opc = Op.getOpcode(); 912 if (TLI.isTypeDesirableForOp(Opc, VT)) 913 return SDValue(); 914 915 EVT PVT = VT; 916 // Consult target whether it is a good idea to promote this operation and 917 // what's the right type to promote it to. 918 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 919 assert(PVT != VT && "Don't know what type to promote to!"); 920 // fold (aext (aext x)) -> (aext x) 921 // fold (aext (zext x)) -> (zext x) 922 // fold (aext (sext x)) -> (sext x) 923 DEBUG(dbgs() << "\nPromoting "; 924 Op.getNode()->dump(&DAG)); 925 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 926 } 927 return SDValue(); 928} 929 930bool DAGCombiner::PromoteLoad(SDValue Op) { 931 if (!LegalOperations) 932 return false; 933 934 EVT VT = Op.getValueType(); 935 if (VT.isVector() || !VT.isInteger()) 936 return false; 937 938 // If operation type is 'undesirable', e.g. i16 on x86, consider 939 // promoting it. 940 unsigned Opc = Op.getOpcode(); 941 if (TLI.isTypeDesirableForOp(Opc, VT)) 942 return false; 943 944 EVT PVT = VT; 945 // Consult target whether it is a good idea to promote this operation and 946 // what's the right type to promote it to. 947 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 948 assert(PVT != VT && "Don't know what type to promote to!"); 949 950 DebugLoc dl = Op.getDebugLoc(); 951 SDNode *N = Op.getNode(); 952 LoadSDNode *LD = cast<LoadSDNode>(N); 953 EVT MemVT = LD->getMemoryVT(); 954 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 955 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 956 : ISD::EXTLOAD) 957 : LD->getExtensionType(); 958 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 959 LD->getChain(), LD->getBasePtr(), 960 LD->getPointerInfo(), 961 MemVT, LD->isVolatile(), 962 LD->isNonTemporal(), LD->getAlignment()); 963 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 964 965 DEBUG(dbgs() << "\nPromoting "; 966 N->dump(&DAG); 967 dbgs() << "\nTo: "; 968 Result.getNode()->dump(&DAG); 969 dbgs() << '\n'); 970 WorkListRemover DeadNodes(*this); 971 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 973 removeFromWorkList(N); 974 DAG.DeleteNode(N); 975 AddToWorkList(Result.getNode()); 976 return true; 977 } 978 return false; 979} 980 981 982//===----------------------------------------------------------------------===// 983// Main DAG Combiner implementation 984//===----------------------------------------------------------------------===// 985 986void DAGCombiner::Run(CombineLevel AtLevel) { 987 // set the instance variables, so that the various visit routines may use it. 988 Level = AtLevel; 989 LegalOperations = Level >= AfterLegalizeVectorOps; 990 LegalTypes = Level >= AfterLegalizeTypes; 991 992 // Add all the dag nodes to the worklist. 993 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 994 E = DAG.allnodes_end(); I != E; ++I) 995 AddToWorkList(I); 996 997 // Create a dummy node (which is not added to allnodes), that adds a reference 998 // to the root node, preventing it from being deleted, and tracking any 999 // changes of the root. 1000 HandleSDNode Dummy(DAG.getRoot()); 1001 1002 // The root of the dag may dangle to deleted nodes until the dag combiner is 1003 // done. Set it to null to avoid confusion. 1004 DAG.setRoot(SDValue()); 1005 1006 // while the worklist isn't empty, find a node and 1007 // try and combine it. 1008 while (!WorkListContents.empty()) { 1009 SDNode *N; 1010 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1011 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1012 // worklist *should* contain, and check the node we want to visit is should 1013 // actually be visited. 1014 do { 1015 N = WorkListOrder.pop_back_val(); 1016 } while (!WorkListContents.erase(N)); 1017 1018 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1019 // N is deleted from the DAG, since they too may now be dead or may have a 1020 // reduced number of uses, allowing other xforms. 1021 if (N->use_empty() && N != &Dummy) { 1022 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1023 AddToWorkList(N->getOperand(i).getNode()); 1024 1025 DAG.DeleteNode(N); 1026 continue; 1027 } 1028 1029 SDValue RV = combine(N); 1030 1031 if (RV.getNode() == 0) 1032 continue; 1033 1034 ++NodesCombined; 1035 1036 // If we get back the same node we passed in, rather than a new node or 1037 // zero, we know that the node must have defined multiple values and 1038 // CombineTo was used. Since CombineTo takes care of the worklist 1039 // mechanics for us, we have no work to do in this case. 1040 if (RV.getNode() == N) 1041 continue; 1042 1043 assert(N->getOpcode() != ISD::DELETED_NODE && 1044 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1045 "Node was deleted but visit returned new node!"); 1046 1047 DEBUG(dbgs() << "\nReplacing.3 "; 1048 N->dump(&DAG); 1049 dbgs() << "\nWith: "; 1050 RV.getNode()->dump(&DAG); 1051 dbgs() << '\n'); 1052 1053 // Transfer debug value. 1054 DAG.TransferDbgValues(SDValue(N, 0), RV); 1055 WorkListRemover DeadNodes(*this); 1056 if (N->getNumValues() == RV.getNode()->getNumValues()) 1057 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1058 else { 1059 assert(N->getValueType(0) == RV.getValueType() && 1060 N->getNumValues() == 1 && "Type mismatch"); 1061 SDValue OpV = RV; 1062 DAG.ReplaceAllUsesWith(N, &OpV); 1063 } 1064 1065 // Push the new node and any users onto the worklist 1066 AddToWorkList(RV.getNode()); 1067 AddUsersToWorkList(RV.getNode()); 1068 1069 // Add any uses of the old node to the worklist in case this node is the 1070 // last one that uses them. They may become dead after this node is 1071 // deleted. 1072 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1073 AddToWorkList(N->getOperand(i).getNode()); 1074 1075 // Finally, if the node is now dead, remove it from the graph. The node 1076 // may not be dead if the replacement process recursively simplified to 1077 // something else needing this node. 1078 if (N->use_empty()) { 1079 // Nodes can be reintroduced into the worklist. Make sure we do not 1080 // process a node that has been replaced. 1081 removeFromWorkList(N); 1082 1083 // Finally, since the node is now dead, remove it from the graph. 1084 DAG.DeleteNode(N); 1085 } 1086 } 1087 1088 // If the root changed (e.g. it was a dead load, update the root). 1089 DAG.setRoot(Dummy.getValue()); 1090 DAG.RemoveDeadNodes(); 1091} 1092 1093SDValue DAGCombiner::visit(SDNode *N) { 1094 switch (N->getOpcode()) { 1095 default: break; 1096 case ISD::TokenFactor: return visitTokenFactor(N); 1097 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1098 case ISD::ADD: return visitADD(N); 1099 case ISD::SUB: return visitSUB(N); 1100 case ISD::ADDC: return visitADDC(N); 1101 case ISD::SUBC: return visitSUBC(N); 1102 case ISD::ADDE: return visitADDE(N); 1103 case ISD::SUBE: return visitSUBE(N); 1104 case ISD::MUL: return visitMUL(N); 1105 case ISD::SDIV: return visitSDIV(N); 1106 case ISD::UDIV: return visitUDIV(N); 1107 case ISD::SREM: return visitSREM(N); 1108 case ISD::UREM: return visitUREM(N); 1109 case ISD::MULHU: return visitMULHU(N); 1110 case ISD::MULHS: return visitMULHS(N); 1111 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1112 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1113 case ISD::SMULO: return visitSMULO(N); 1114 case ISD::UMULO: return visitUMULO(N); 1115 case ISD::SDIVREM: return visitSDIVREM(N); 1116 case ISD::UDIVREM: return visitUDIVREM(N); 1117 case ISD::AND: return visitAND(N); 1118 case ISD::OR: return visitOR(N); 1119 case ISD::XOR: return visitXOR(N); 1120 case ISD::SHL: return visitSHL(N); 1121 case ISD::SRA: return visitSRA(N); 1122 case ISD::SRL: return visitSRL(N); 1123 case ISD::CTLZ: return visitCTLZ(N); 1124 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1125 case ISD::CTTZ: return visitCTTZ(N); 1126 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1127 case ISD::CTPOP: return visitCTPOP(N); 1128 case ISD::SELECT: return visitSELECT(N); 1129 case ISD::SELECT_CC: return visitSELECT_CC(N); 1130 case ISD::SETCC: return visitSETCC(N); 1131 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1132 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1133 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1134 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1135 case ISD::TRUNCATE: return visitTRUNCATE(N); 1136 case ISD::BITCAST: return visitBITCAST(N); 1137 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1138 case ISD::FADD: return visitFADD(N); 1139 case ISD::FSUB: return visitFSUB(N); 1140 case ISD::FMUL: return visitFMUL(N); 1141 case ISD::FMA: return visitFMA(N); 1142 case ISD::FDIV: return visitFDIV(N); 1143 case ISD::FREM: return visitFREM(N); 1144 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1145 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1146 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1147 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1148 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1149 case ISD::FP_ROUND: return visitFP_ROUND(N); 1150 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1151 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1152 case ISD::FNEG: return visitFNEG(N); 1153 case ISD::FABS: return visitFABS(N); 1154 case ISD::FFLOOR: return visitFFLOOR(N); 1155 case ISD::FCEIL: return visitFCEIL(N); 1156 case ISD::FTRUNC: return visitFTRUNC(N); 1157 case ISD::BRCOND: return visitBRCOND(N); 1158 case ISD::BR_CC: return visitBR_CC(N); 1159 case ISD::LOAD: return visitLOAD(N); 1160 case ISD::STORE: return visitSTORE(N); 1161 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1162 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1163 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1164 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1165 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1166 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1167 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1168 } 1169 return SDValue(); 1170} 1171 1172SDValue DAGCombiner::combine(SDNode *N) { 1173 SDValue RV = visit(N); 1174 1175 // If nothing happened, try a target-specific DAG combine. 1176 if (RV.getNode() == 0) { 1177 assert(N->getOpcode() != ISD::DELETED_NODE && 1178 "Node was deleted but visit returned NULL!"); 1179 1180 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1181 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1182 1183 // Expose the DAG combiner to the target combiner impls. 1184 TargetLowering::DAGCombinerInfo 1185 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1186 1187 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1188 } 1189 } 1190 1191 // If nothing happened still, try promoting the operation. 1192 if (RV.getNode() == 0) { 1193 switch (N->getOpcode()) { 1194 default: break; 1195 case ISD::ADD: 1196 case ISD::SUB: 1197 case ISD::MUL: 1198 case ISD::AND: 1199 case ISD::OR: 1200 case ISD::XOR: 1201 RV = PromoteIntBinOp(SDValue(N, 0)); 1202 break; 1203 case ISD::SHL: 1204 case ISD::SRA: 1205 case ISD::SRL: 1206 RV = PromoteIntShiftOp(SDValue(N, 0)); 1207 break; 1208 case ISD::SIGN_EXTEND: 1209 case ISD::ZERO_EXTEND: 1210 case ISD::ANY_EXTEND: 1211 RV = PromoteExtend(SDValue(N, 0)); 1212 break; 1213 case ISD::LOAD: 1214 if (PromoteLoad(SDValue(N, 0))) 1215 RV = SDValue(N, 0); 1216 break; 1217 } 1218 } 1219 1220 // If N is a commutative binary node, try commuting it to enable more 1221 // sdisel CSE. 1222 if (RV.getNode() == 0 && 1223 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1224 N->getNumValues() == 1) { 1225 SDValue N0 = N->getOperand(0); 1226 SDValue N1 = N->getOperand(1); 1227 1228 // Constant operands are canonicalized to RHS. 1229 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1230 SDValue Ops[] = { N1, N0 }; 1231 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1232 Ops, 2); 1233 if (CSENode) 1234 return SDValue(CSENode, 0); 1235 } 1236 } 1237 1238 return RV; 1239} 1240 1241/// getInputChainForNode - Given a node, return its input chain if it has one, 1242/// otherwise return a null sd operand. 1243static SDValue getInputChainForNode(SDNode *N) { 1244 if (unsigned NumOps = N->getNumOperands()) { 1245 if (N->getOperand(0).getValueType() == MVT::Other) 1246 return N->getOperand(0); 1247 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1248 return N->getOperand(NumOps-1); 1249 for (unsigned i = 1; i < NumOps-1; ++i) 1250 if (N->getOperand(i).getValueType() == MVT::Other) 1251 return N->getOperand(i); 1252 } 1253 return SDValue(); 1254} 1255 1256SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1257 // If N has two operands, where one has an input chain equal to the other, 1258 // the 'other' chain is redundant. 1259 if (N->getNumOperands() == 2) { 1260 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1261 return N->getOperand(0); 1262 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1263 return N->getOperand(1); 1264 } 1265 1266 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1267 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1268 SmallPtrSet<SDNode*, 16> SeenOps; 1269 bool Changed = false; // If we should replace this token factor. 1270 1271 // Start out with this token factor. 1272 TFs.push_back(N); 1273 1274 // Iterate through token factors. The TFs grows when new token factors are 1275 // encountered. 1276 for (unsigned i = 0; i < TFs.size(); ++i) { 1277 SDNode *TF = TFs[i]; 1278 1279 // Check each of the operands. 1280 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1281 SDValue Op = TF->getOperand(i); 1282 1283 switch (Op.getOpcode()) { 1284 case ISD::EntryToken: 1285 // Entry tokens don't need to be added to the list. They are 1286 // rededundant. 1287 Changed = true; 1288 break; 1289 1290 case ISD::TokenFactor: 1291 if (Op.hasOneUse() && 1292 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1293 // Queue up for processing. 1294 TFs.push_back(Op.getNode()); 1295 // Clean up in case the token factor is removed. 1296 AddToWorkList(Op.getNode()); 1297 Changed = true; 1298 break; 1299 } 1300 // Fall thru 1301 1302 default: 1303 // Only add if it isn't already in the list. 1304 if (SeenOps.insert(Op.getNode())) 1305 Ops.push_back(Op); 1306 else 1307 Changed = true; 1308 break; 1309 } 1310 } 1311 } 1312 1313 SDValue Result; 1314 1315 // If we've change things around then replace token factor. 1316 if (Changed) { 1317 if (Ops.empty()) { 1318 // The entry token is the only possible outcome. 1319 Result = DAG.getEntryNode(); 1320 } else { 1321 // New and improved token factor. 1322 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1323 MVT::Other, &Ops[0], Ops.size()); 1324 } 1325 1326 // Don't add users to work list. 1327 return CombineTo(N, Result, false); 1328 } 1329 1330 return Result; 1331} 1332 1333/// MERGE_VALUES can always be eliminated. 1334SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1335 WorkListRemover DeadNodes(*this); 1336 // Replacing results may cause a different MERGE_VALUES to suddenly 1337 // be CSE'd with N, and carry its uses with it. Iterate until no 1338 // uses remain, to ensure that the node can be safely deleted. 1339 // First add the users of this node to the work list so that they 1340 // can be tried again once they have new operands. 1341 AddUsersToWorkList(N); 1342 do { 1343 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1344 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1345 } while (!N->use_empty()); 1346 removeFromWorkList(N); 1347 DAG.DeleteNode(N); 1348 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1349} 1350 1351static 1352SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1353 SelectionDAG &DAG) { 1354 EVT VT = N0.getValueType(); 1355 SDValue N00 = N0.getOperand(0); 1356 SDValue N01 = N0.getOperand(1); 1357 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1358 1359 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1360 isa<ConstantSDNode>(N00.getOperand(1))) { 1361 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1362 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1363 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1364 N00.getOperand(0), N01), 1365 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1366 N00.getOperand(1), N01)); 1367 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1368 } 1369 1370 return SDValue(); 1371} 1372 1373SDValue DAGCombiner::visitADD(SDNode *N) { 1374 SDValue N0 = N->getOperand(0); 1375 SDValue N1 = N->getOperand(1); 1376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1378 EVT VT = N0.getValueType(); 1379 1380 // fold vector ops 1381 if (VT.isVector()) { 1382 SDValue FoldedVOp = SimplifyVBinOp(N); 1383 if (FoldedVOp.getNode()) return FoldedVOp; 1384 1385 // fold (add x, 0) -> x, vector edition 1386 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1387 return N0; 1388 if (ISD::isBuildVectorAllZeros(N0.getNode())) 1389 return N1; 1390 } 1391 1392 // fold (add x, undef) -> undef 1393 if (N0.getOpcode() == ISD::UNDEF) 1394 return N0; 1395 if (N1.getOpcode() == ISD::UNDEF) 1396 return N1; 1397 // fold (add c1, c2) -> c1+c2 1398 if (N0C && N1C) 1399 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1400 // canonicalize constant to RHS 1401 if (N0C && !N1C) 1402 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1403 // fold (add x, 0) -> x 1404 if (N1C && N1C->isNullValue()) 1405 return N0; 1406 // fold (add Sym, c) -> Sym+c 1407 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1408 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1409 GA->getOpcode() == ISD::GlobalAddress) 1410 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1411 GA->getOffset() + 1412 (uint64_t)N1C->getSExtValue()); 1413 // fold ((c1-A)+c2) -> (c1+c2)-A 1414 if (N1C && N0.getOpcode() == ISD::SUB) 1415 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1416 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1417 DAG.getConstant(N1C->getAPIntValue()+ 1418 N0C->getAPIntValue(), VT), 1419 N0.getOperand(1)); 1420 // reassociate add 1421 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1422 if (RADD.getNode() != 0) 1423 return RADD; 1424 // fold ((0-A) + B) -> B-A 1425 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1426 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1427 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1428 // fold (A + (0-B)) -> A-B 1429 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1430 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1431 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1432 // fold (A+(B-A)) -> B 1433 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1434 return N1.getOperand(0); 1435 // fold ((B-A)+A) -> B 1436 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1437 return N0.getOperand(0); 1438 // fold (A+(B-(A+C))) to (B-C) 1439 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1440 N0 == N1.getOperand(1).getOperand(0)) 1441 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1442 N1.getOperand(1).getOperand(1)); 1443 // fold (A+(B-(C+A))) to (B-C) 1444 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1445 N0 == N1.getOperand(1).getOperand(1)) 1446 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1447 N1.getOperand(1).getOperand(0)); 1448 // fold (A+((B-A)+or-C)) to (B+or-C) 1449 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1450 N1.getOperand(0).getOpcode() == ISD::SUB && 1451 N0 == N1.getOperand(0).getOperand(1)) 1452 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1453 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1454 1455 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1456 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1457 SDValue N00 = N0.getOperand(0); 1458 SDValue N01 = N0.getOperand(1); 1459 SDValue N10 = N1.getOperand(0); 1460 SDValue N11 = N1.getOperand(1); 1461 1462 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1463 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1464 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1465 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1466 } 1467 1468 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1469 return SDValue(N, 0); 1470 1471 // fold (a+b) -> (a|b) iff a and b share no bits. 1472 if (VT.isInteger() && !VT.isVector()) { 1473 APInt LHSZero, LHSOne; 1474 APInt RHSZero, RHSOne; 1475 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1476 1477 if (LHSZero.getBoolValue()) { 1478 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1479 1480 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1481 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1482 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1483 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1484 } 1485 } 1486 1487 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1488 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1489 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1490 if (Result.getNode()) return Result; 1491 } 1492 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1493 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1494 if (Result.getNode()) return Result; 1495 } 1496 1497 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1498 if (N1.getOpcode() == ISD::SHL && 1499 N1.getOperand(0).getOpcode() == ISD::SUB) 1500 if (ConstantSDNode *C = 1501 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1502 if (C->getAPIntValue() == 0) 1503 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1504 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1505 N1.getOperand(0).getOperand(1), 1506 N1.getOperand(1))); 1507 if (N0.getOpcode() == ISD::SHL && 1508 N0.getOperand(0).getOpcode() == ISD::SUB) 1509 if (ConstantSDNode *C = 1510 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1511 if (C->getAPIntValue() == 0) 1512 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1513 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1514 N0.getOperand(0).getOperand(1), 1515 N0.getOperand(1))); 1516 1517 if (N1.getOpcode() == ISD::AND) { 1518 SDValue AndOp0 = N1.getOperand(0); 1519 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1520 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1521 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1522 1523 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1524 // and similar xforms where the inner op is either ~0 or 0. 1525 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1526 DebugLoc DL = N->getDebugLoc(); 1527 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1528 } 1529 } 1530 1531 // add (sext i1), X -> sub X, (zext i1) 1532 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1533 N0.getOperand(0).getValueType() == MVT::i1 && 1534 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1535 DebugLoc DL = N->getDebugLoc(); 1536 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1537 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1538 } 1539 1540 return SDValue(); 1541} 1542 1543SDValue DAGCombiner::visitADDC(SDNode *N) { 1544 SDValue N0 = N->getOperand(0); 1545 SDValue N1 = N->getOperand(1); 1546 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1547 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1548 EVT VT = N0.getValueType(); 1549 1550 // If the flag result is dead, turn this into an ADD. 1551 if (!N->hasAnyUseOfValue(1)) 1552 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1553 DAG.getNode(ISD::CARRY_FALSE, 1554 N->getDebugLoc(), MVT::Glue)); 1555 1556 // canonicalize constant to RHS. 1557 if (N0C && !N1C) 1558 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1559 1560 // fold (addc x, 0) -> x + no carry out 1561 if (N1C && N1C->isNullValue()) 1562 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1563 N->getDebugLoc(), MVT::Glue)); 1564 1565 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1566 APInt LHSZero, LHSOne; 1567 APInt RHSZero, RHSOne; 1568 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1569 1570 if (LHSZero.getBoolValue()) { 1571 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1572 1573 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1574 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1575 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1576 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1577 DAG.getNode(ISD::CARRY_FALSE, 1578 N->getDebugLoc(), MVT::Glue)); 1579 } 1580 1581 return SDValue(); 1582} 1583 1584SDValue DAGCombiner::visitADDE(SDNode *N) { 1585 SDValue N0 = N->getOperand(0); 1586 SDValue N1 = N->getOperand(1); 1587 SDValue CarryIn = N->getOperand(2); 1588 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1589 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1590 1591 // canonicalize constant to RHS 1592 if (N0C && !N1C) 1593 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1594 N1, N0, CarryIn); 1595 1596 // fold (adde x, y, false) -> (addc x, y) 1597 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1598 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1599 1600 return SDValue(); 1601} 1602 1603// Since it may not be valid to emit a fold to zero for vector initializers 1604// check if we can before folding. 1605static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1606 SelectionDAG &DAG, bool LegalOperations) { 1607 if (!VT.isVector()) { 1608 return DAG.getConstant(0, VT); 1609 } 1610 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1611 // Produce a vector of zeros. 1612 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1613 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1614 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1615 &Ops[0], Ops.size()); 1616 } 1617 return SDValue(); 1618} 1619 1620SDValue DAGCombiner::visitSUB(SDNode *N) { 1621 SDValue N0 = N->getOperand(0); 1622 SDValue N1 = N->getOperand(1); 1623 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1624 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1625 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1626 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1627 EVT VT = N0.getValueType(); 1628 1629 // fold vector ops 1630 if (VT.isVector()) { 1631 SDValue FoldedVOp = SimplifyVBinOp(N); 1632 if (FoldedVOp.getNode()) return FoldedVOp; 1633 1634 // fold (sub x, 0) -> x, vector edition 1635 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1636 return N0; 1637 } 1638 1639 // fold (sub x, x) -> 0 1640 // FIXME: Refactor this and xor and other similar operations together. 1641 if (N0 == N1) 1642 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1643 // fold (sub c1, c2) -> c1-c2 1644 if (N0C && N1C) 1645 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1646 // fold (sub x, c) -> (add x, -c) 1647 if (N1C) 1648 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1649 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1650 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1651 if (N0C && N0C->isAllOnesValue()) 1652 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1653 // fold A-(A-B) -> B 1654 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1655 return N1.getOperand(1); 1656 // fold (A+B)-A -> B 1657 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1658 return N0.getOperand(1); 1659 // fold (A+B)-B -> A 1660 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1661 return N0.getOperand(0); 1662 // fold C2-(A+C1) -> (C2-C1)-A 1663 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1664 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), 1665 VT); 1666 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1667 N1.getOperand(0)); 1668 } 1669 // fold ((A+(B+or-C))-B) -> A+or-C 1670 if (N0.getOpcode() == ISD::ADD && 1671 (N0.getOperand(1).getOpcode() == ISD::SUB || 1672 N0.getOperand(1).getOpcode() == ISD::ADD) && 1673 N0.getOperand(1).getOperand(0) == N1) 1674 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1675 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1676 // fold ((A+(C+B))-B) -> A+C 1677 if (N0.getOpcode() == ISD::ADD && 1678 N0.getOperand(1).getOpcode() == ISD::ADD && 1679 N0.getOperand(1).getOperand(1) == N1) 1680 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1681 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1682 // fold ((A-(B-C))-C) -> A-B 1683 if (N0.getOpcode() == ISD::SUB && 1684 N0.getOperand(1).getOpcode() == ISD::SUB && 1685 N0.getOperand(1).getOperand(1) == N1) 1686 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1687 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1688 1689 // If either operand of a sub is undef, the result is undef 1690 if (N0.getOpcode() == ISD::UNDEF) 1691 return N0; 1692 if (N1.getOpcode() == ISD::UNDEF) 1693 return N1; 1694 1695 // If the relocation model supports it, consider symbol offsets. 1696 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1697 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1698 // fold (sub Sym, c) -> Sym-c 1699 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1700 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1701 GA->getOffset() - 1702 (uint64_t)N1C->getSExtValue()); 1703 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1704 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1705 if (GA->getGlobal() == GB->getGlobal()) 1706 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1707 VT); 1708 } 1709 1710 return SDValue(); 1711} 1712 1713SDValue DAGCombiner::visitSUBC(SDNode *N) { 1714 SDValue N0 = N->getOperand(0); 1715 SDValue N1 = N->getOperand(1); 1716 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1717 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1718 EVT VT = N0.getValueType(); 1719 1720 // If the flag result is dead, turn this into an SUB. 1721 if (!N->hasAnyUseOfValue(1)) 1722 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1723 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1724 MVT::Glue)); 1725 1726 // fold (subc x, x) -> 0 + no borrow 1727 if (N0 == N1) 1728 return CombineTo(N, DAG.getConstant(0, VT), 1729 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1730 MVT::Glue)); 1731 1732 // fold (subc x, 0) -> x + no borrow 1733 if (N1C && N1C->isNullValue()) 1734 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1735 MVT::Glue)); 1736 1737 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1738 if (N0C && N0C->isAllOnesValue()) 1739 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1740 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1741 MVT::Glue)); 1742 1743 return SDValue(); 1744} 1745 1746SDValue DAGCombiner::visitSUBE(SDNode *N) { 1747 SDValue N0 = N->getOperand(0); 1748 SDValue N1 = N->getOperand(1); 1749 SDValue CarryIn = N->getOperand(2); 1750 1751 // fold (sube x, y, false) -> (subc x, y) 1752 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1753 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1754 1755 return SDValue(); 1756} 1757 1758SDValue DAGCombiner::visitMUL(SDNode *N) { 1759 SDValue N0 = N->getOperand(0); 1760 SDValue N1 = N->getOperand(1); 1761 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1762 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1763 EVT VT = N0.getValueType(); 1764 1765 // fold vector ops 1766 if (VT.isVector()) { 1767 SDValue FoldedVOp = SimplifyVBinOp(N); 1768 if (FoldedVOp.getNode()) return FoldedVOp; 1769 } 1770 1771 // fold (mul x, undef) -> 0 1772 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1773 return DAG.getConstant(0, VT); 1774 // fold (mul c1, c2) -> c1*c2 1775 if (N0C && N1C) 1776 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1777 // canonicalize constant to RHS 1778 if (N0C && !N1C) 1779 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1780 // fold (mul x, 0) -> 0 1781 if (N1C && N1C->isNullValue()) 1782 return N1; 1783 // fold (mul x, -1) -> 0-x 1784 if (N1C && N1C->isAllOnesValue()) 1785 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1786 DAG.getConstant(0, VT), N0); 1787 // fold (mul x, (1 << c)) -> x << c 1788 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1789 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1790 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1791 getShiftAmountTy(N0.getValueType()))); 1792 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1793 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1794 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1795 // FIXME: If the input is something that is easily negated (e.g. a 1796 // single-use add), we should put the negate there. 1797 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1798 DAG.getConstant(0, VT), 1799 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1800 DAG.getConstant(Log2Val, 1801 getShiftAmountTy(N0.getValueType())))); 1802 } 1803 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1804 if (N1C && N0.getOpcode() == ISD::SHL && 1805 isa<ConstantSDNode>(N0.getOperand(1))) { 1806 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1807 N1, N0.getOperand(1)); 1808 AddToWorkList(C3.getNode()); 1809 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1810 N0.getOperand(0), C3); 1811 } 1812 1813 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1814 // use. 1815 { 1816 SDValue Sh(0,0), Y(0,0); 1817 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1818 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1819 N0.getNode()->hasOneUse()) { 1820 Sh = N0; Y = N1; 1821 } else if (N1.getOpcode() == ISD::SHL && 1822 isa<ConstantSDNode>(N1.getOperand(1)) && 1823 N1.getNode()->hasOneUse()) { 1824 Sh = N1; Y = N0; 1825 } 1826 1827 if (Sh.getNode()) { 1828 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1829 Sh.getOperand(0), Y); 1830 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1831 Mul, Sh.getOperand(1)); 1832 } 1833 } 1834 1835 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1836 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1837 isa<ConstantSDNode>(N0.getOperand(1))) 1838 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1839 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1840 N0.getOperand(0), N1), 1841 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1842 N0.getOperand(1), N1)); 1843 1844 // reassociate mul 1845 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1846 if (RMUL.getNode() != 0) 1847 return RMUL; 1848 1849 return SDValue(); 1850} 1851 1852SDValue DAGCombiner::visitSDIV(SDNode *N) { 1853 SDValue N0 = N->getOperand(0); 1854 SDValue N1 = N->getOperand(1); 1855 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1856 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1857 EVT VT = N->getValueType(0); 1858 1859 // fold vector ops 1860 if (VT.isVector()) { 1861 SDValue FoldedVOp = SimplifyVBinOp(N); 1862 if (FoldedVOp.getNode()) return FoldedVOp; 1863 } 1864 1865 // fold (sdiv c1, c2) -> c1/c2 1866 if (N0C && N1C && !N1C->isNullValue()) 1867 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1868 // fold (sdiv X, 1) -> X 1869 if (N1C && N1C->getAPIntValue() == 1LL) 1870 return N0; 1871 // fold (sdiv X, -1) -> 0-X 1872 if (N1C && N1C->isAllOnesValue()) 1873 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1874 DAG.getConstant(0, VT), N0); 1875 // If we know the sign bits of both operands are zero, strength reduce to a 1876 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1877 if (!VT.isVector()) { 1878 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1879 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1880 N0, N1); 1881 } 1882 // fold (sdiv X, pow2) -> simple ops after legalize 1883 if (N1C && !N1C->isNullValue() && 1884 (N1C->getAPIntValue().isPowerOf2() || 1885 (-N1C->getAPIntValue()).isPowerOf2())) { 1886 // If dividing by powers of two is cheap, then don't perform the following 1887 // fold. 1888 if (TLI.isPow2DivCheap()) 1889 return SDValue(); 1890 1891 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1892 1893 // Splat the sign bit into the register 1894 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1895 DAG.getConstant(VT.getSizeInBits()-1, 1896 getShiftAmountTy(N0.getValueType()))); 1897 AddToWorkList(SGN.getNode()); 1898 1899 // Add (N0 < 0) ? abs2 - 1 : 0; 1900 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1901 DAG.getConstant(VT.getSizeInBits() - lg2, 1902 getShiftAmountTy(SGN.getValueType()))); 1903 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1904 AddToWorkList(SRL.getNode()); 1905 AddToWorkList(ADD.getNode()); // Divide by pow2 1906 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1907 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1908 1909 // If we're dividing by a positive value, we're done. Otherwise, we must 1910 // negate the result. 1911 if (N1C->getAPIntValue().isNonNegative()) 1912 return SRA; 1913 1914 AddToWorkList(SRA.getNode()); 1915 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1916 DAG.getConstant(0, VT), SRA); 1917 } 1918 1919 // if integer divide is expensive and we satisfy the requirements, emit an 1920 // alternate sequence. 1921 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1922 SDValue Op = BuildSDIV(N); 1923 if (Op.getNode()) return Op; 1924 } 1925 1926 // undef / X -> 0 1927 if (N0.getOpcode() == ISD::UNDEF) 1928 return DAG.getConstant(0, VT); 1929 // X / undef -> undef 1930 if (N1.getOpcode() == ISD::UNDEF) 1931 return N1; 1932 1933 return SDValue(); 1934} 1935 1936SDValue DAGCombiner::visitUDIV(SDNode *N) { 1937 SDValue N0 = N->getOperand(0); 1938 SDValue N1 = N->getOperand(1); 1939 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1941 EVT VT = N->getValueType(0); 1942 1943 // fold vector ops 1944 if (VT.isVector()) { 1945 SDValue FoldedVOp = SimplifyVBinOp(N); 1946 if (FoldedVOp.getNode()) return FoldedVOp; 1947 } 1948 1949 // fold (udiv c1, c2) -> c1/c2 1950 if (N0C && N1C && !N1C->isNullValue()) 1951 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1952 // fold (udiv x, (1 << c)) -> x >>u c 1953 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1954 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1955 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1956 getShiftAmountTy(N0.getValueType()))); 1957 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1958 if (N1.getOpcode() == ISD::SHL) { 1959 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1960 if (SHC->getAPIntValue().isPowerOf2()) { 1961 EVT ADDVT = N1.getOperand(1).getValueType(); 1962 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1963 N1.getOperand(1), 1964 DAG.getConstant(SHC->getAPIntValue() 1965 .logBase2(), 1966 ADDVT)); 1967 AddToWorkList(Add.getNode()); 1968 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1969 } 1970 } 1971 } 1972 // fold (udiv x, c) -> alternate 1973 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1974 SDValue Op = BuildUDIV(N); 1975 if (Op.getNode()) return Op; 1976 } 1977 1978 // undef / X -> 0 1979 if (N0.getOpcode() == ISD::UNDEF) 1980 return DAG.getConstant(0, VT); 1981 // X / undef -> undef 1982 if (N1.getOpcode() == ISD::UNDEF) 1983 return N1; 1984 1985 return SDValue(); 1986} 1987 1988SDValue DAGCombiner::visitSREM(SDNode *N) { 1989 SDValue N0 = N->getOperand(0); 1990 SDValue N1 = N->getOperand(1); 1991 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1992 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1993 EVT VT = N->getValueType(0); 1994 1995 // fold (srem c1, c2) -> c1%c2 1996 if (N0C && N1C && !N1C->isNullValue()) 1997 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1998 // If we know the sign bits of both operands are zero, strength reduce to a 1999 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 2000 if (!VT.isVector()) { 2001 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 2002 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 2003 } 2004 2005 // If X/C can be simplified by the division-by-constant logic, lower 2006 // X%C to the equivalent of X-X/C*C. 2007 if (N1C && !N1C->isNullValue()) { 2008 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 2009 AddToWorkList(Div.getNode()); 2010 SDValue OptimizedDiv = combine(Div.getNode()); 2011 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2012 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2013 OptimizedDiv, N1); 2014 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2015 AddToWorkList(Mul.getNode()); 2016 return Sub; 2017 } 2018 } 2019 2020 // undef % X -> 0 2021 if (N0.getOpcode() == ISD::UNDEF) 2022 return DAG.getConstant(0, VT); 2023 // X % undef -> undef 2024 if (N1.getOpcode() == ISD::UNDEF) 2025 return N1; 2026 2027 return SDValue(); 2028} 2029 2030SDValue DAGCombiner::visitUREM(SDNode *N) { 2031 SDValue N0 = N->getOperand(0); 2032 SDValue N1 = N->getOperand(1); 2033 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2034 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2035 EVT VT = N->getValueType(0); 2036 2037 // fold (urem c1, c2) -> c1%c2 2038 if (N0C && N1C && !N1C->isNullValue()) 2039 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2040 // fold (urem x, pow2) -> (and x, pow2-1) 2041 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2042 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2043 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2044 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2045 if (N1.getOpcode() == ISD::SHL) { 2046 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2047 if (SHC->getAPIntValue().isPowerOf2()) { 2048 SDValue Add = 2049 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2050 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2051 VT)); 2052 AddToWorkList(Add.getNode()); 2053 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2054 } 2055 } 2056 } 2057 2058 // If X/C can be simplified by the division-by-constant logic, lower 2059 // X%C to the equivalent of X-X/C*C. 2060 if (N1C && !N1C->isNullValue()) { 2061 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2062 AddToWorkList(Div.getNode()); 2063 SDValue OptimizedDiv = combine(Div.getNode()); 2064 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2065 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2066 OptimizedDiv, N1); 2067 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2068 AddToWorkList(Mul.getNode()); 2069 return Sub; 2070 } 2071 } 2072 2073 // undef % X -> 0 2074 if (N0.getOpcode() == ISD::UNDEF) 2075 return DAG.getConstant(0, VT); 2076 // X % undef -> undef 2077 if (N1.getOpcode() == ISD::UNDEF) 2078 return N1; 2079 2080 return SDValue(); 2081} 2082 2083SDValue DAGCombiner::visitMULHS(SDNode *N) { 2084 SDValue N0 = N->getOperand(0); 2085 SDValue N1 = N->getOperand(1); 2086 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2087 EVT VT = N->getValueType(0); 2088 DebugLoc DL = N->getDebugLoc(); 2089 2090 // fold (mulhs x, 0) -> 0 2091 if (N1C && N1C->isNullValue()) 2092 return N1; 2093 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2094 if (N1C && N1C->getAPIntValue() == 1) 2095 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2096 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2097 getShiftAmountTy(N0.getValueType()))); 2098 // fold (mulhs x, undef) -> 0 2099 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2100 return DAG.getConstant(0, VT); 2101 2102 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2103 // plus a shift. 2104 if (VT.isSimple() && !VT.isVector()) { 2105 MVT Simple = VT.getSimpleVT(); 2106 unsigned SimpleSize = Simple.getSizeInBits(); 2107 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2108 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2109 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2110 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2111 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2112 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2113 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2114 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2115 } 2116 } 2117 2118 return SDValue(); 2119} 2120 2121SDValue DAGCombiner::visitMULHU(SDNode *N) { 2122 SDValue N0 = N->getOperand(0); 2123 SDValue N1 = N->getOperand(1); 2124 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2125 EVT VT = N->getValueType(0); 2126 DebugLoc DL = N->getDebugLoc(); 2127 2128 // fold (mulhu x, 0) -> 0 2129 if (N1C && N1C->isNullValue()) 2130 return N1; 2131 // fold (mulhu x, 1) -> 0 2132 if (N1C && N1C->getAPIntValue() == 1) 2133 return DAG.getConstant(0, N0.getValueType()); 2134 // fold (mulhu x, undef) -> 0 2135 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2136 return DAG.getConstant(0, VT); 2137 2138 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2139 // plus a shift. 2140 if (VT.isSimple() && !VT.isVector()) { 2141 MVT Simple = VT.getSimpleVT(); 2142 unsigned SimpleSize = Simple.getSizeInBits(); 2143 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2144 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2145 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2146 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2147 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2148 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2149 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2150 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2151 } 2152 } 2153 2154 return SDValue(); 2155} 2156 2157/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2158/// compute two values. LoOp and HiOp give the opcodes for the two computations 2159/// that are being performed. Return true if a simplification was made. 2160/// 2161SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2162 unsigned HiOp) { 2163 // If the high half is not needed, just compute the low half. 2164 bool HiExists = N->hasAnyUseOfValue(1); 2165 if (!HiExists && 2166 (!LegalOperations || 2167 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2168 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2169 N->op_begin(), N->getNumOperands()); 2170 return CombineTo(N, Res, Res); 2171 } 2172 2173 // If the low half is not needed, just compute the high half. 2174 bool LoExists = N->hasAnyUseOfValue(0); 2175 if (!LoExists && 2176 (!LegalOperations || 2177 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2178 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2179 N->op_begin(), N->getNumOperands()); 2180 return CombineTo(N, Res, Res); 2181 } 2182 2183 // If both halves are used, return as it is. 2184 if (LoExists && HiExists) 2185 return SDValue(); 2186 2187 // If the two computed results can be simplified separately, separate them. 2188 if (LoExists) { 2189 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2190 N->op_begin(), N->getNumOperands()); 2191 AddToWorkList(Lo.getNode()); 2192 SDValue LoOpt = combine(Lo.getNode()); 2193 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2194 (!LegalOperations || 2195 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2196 return CombineTo(N, LoOpt, LoOpt); 2197 } 2198 2199 if (HiExists) { 2200 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2201 N->op_begin(), N->getNumOperands()); 2202 AddToWorkList(Hi.getNode()); 2203 SDValue HiOpt = combine(Hi.getNode()); 2204 if (HiOpt.getNode() && HiOpt != Hi && 2205 (!LegalOperations || 2206 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2207 return CombineTo(N, HiOpt, HiOpt); 2208 } 2209 2210 return SDValue(); 2211} 2212 2213SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2214 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2215 if (Res.getNode()) return Res; 2216 2217 EVT VT = N->getValueType(0); 2218 DebugLoc DL = N->getDebugLoc(); 2219 2220 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2221 // plus a shift. 2222 if (VT.isSimple() && !VT.isVector()) { 2223 MVT Simple = VT.getSimpleVT(); 2224 unsigned SimpleSize = Simple.getSizeInBits(); 2225 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2226 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2227 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2228 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2229 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2230 // Compute the high part as N1. 2231 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2232 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2233 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2234 // Compute the low part as N0. 2235 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2236 return CombineTo(N, Lo, Hi); 2237 } 2238 } 2239 2240 return SDValue(); 2241} 2242 2243SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2244 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2245 if (Res.getNode()) return Res; 2246 2247 EVT VT = N->getValueType(0); 2248 DebugLoc DL = N->getDebugLoc(); 2249 2250 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2251 // plus a shift. 2252 if (VT.isSimple() && !VT.isVector()) { 2253 MVT Simple = VT.getSimpleVT(); 2254 unsigned SimpleSize = Simple.getSizeInBits(); 2255 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2256 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2257 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2258 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2259 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2260 // Compute the high part as N1. 2261 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2262 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2263 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2264 // Compute the low part as N0. 2265 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2266 return CombineTo(N, Lo, Hi); 2267 } 2268 } 2269 2270 return SDValue(); 2271} 2272 2273SDValue DAGCombiner::visitSMULO(SDNode *N) { 2274 // (smulo x, 2) -> (saddo x, x) 2275 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2276 if (C2->getAPIntValue() == 2) 2277 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2278 N->getOperand(0), N->getOperand(0)); 2279 2280 return SDValue(); 2281} 2282 2283SDValue DAGCombiner::visitUMULO(SDNode *N) { 2284 // (umulo x, 2) -> (uaddo x, x) 2285 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2286 if (C2->getAPIntValue() == 2) 2287 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2288 N->getOperand(0), N->getOperand(0)); 2289 2290 return SDValue(); 2291} 2292 2293SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2294 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2295 if (Res.getNode()) return Res; 2296 2297 return SDValue(); 2298} 2299 2300SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2301 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2302 if (Res.getNode()) return Res; 2303 2304 return SDValue(); 2305} 2306 2307/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2308/// two operands of the same opcode, try to simplify it. 2309SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2310 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2311 EVT VT = N0.getValueType(); 2312 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2313 2314 // Bail early if none of these transforms apply. 2315 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2316 2317 // For each of OP in AND/OR/XOR: 2318 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2319 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2320 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2321 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2322 // 2323 // do not sink logical op inside of a vector extend, since it may combine 2324 // into a vsetcc. 2325 EVT Op0VT = N0.getOperand(0).getValueType(); 2326 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2327 N0.getOpcode() == ISD::SIGN_EXTEND || 2328 // Avoid infinite looping with PromoteIntBinOp. 2329 (N0.getOpcode() == ISD::ANY_EXTEND && 2330 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2331 (N0.getOpcode() == ISD::TRUNCATE && 2332 (!TLI.isZExtFree(VT, Op0VT) || 2333 !TLI.isTruncateFree(Op0VT, VT)) && 2334 TLI.isTypeLegal(Op0VT))) && 2335 !VT.isVector() && 2336 Op0VT == N1.getOperand(0).getValueType() && 2337 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2338 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2339 N0.getOperand(0).getValueType(), 2340 N0.getOperand(0), N1.getOperand(0)); 2341 AddToWorkList(ORNode.getNode()); 2342 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2343 } 2344 2345 // For each of OP in SHL/SRL/SRA/AND... 2346 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2347 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2348 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2349 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2350 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2351 N0.getOperand(1) == N1.getOperand(1)) { 2352 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2353 N0.getOperand(0).getValueType(), 2354 N0.getOperand(0), N1.getOperand(0)); 2355 AddToWorkList(ORNode.getNode()); 2356 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2357 ORNode, N0.getOperand(1)); 2358 } 2359 2360 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2361 // Only perform this optimization after type legalization and before 2362 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2363 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2364 // we don't want to undo this promotion. 2365 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2366 // on scalars. 2367 if ((N0.getOpcode() == ISD::BITCAST || 2368 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && 2369 Level == AfterLegalizeTypes) { 2370 SDValue In0 = N0.getOperand(0); 2371 SDValue In1 = N1.getOperand(0); 2372 EVT In0Ty = In0.getValueType(); 2373 EVT In1Ty = In1.getValueType(); 2374 DebugLoc DL = N->getDebugLoc(); 2375 // If both incoming values are integers, and the original types are the 2376 // same. 2377 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2378 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1); 2379 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op); 2380 AddToWorkList(Op.getNode()); 2381 return BC; 2382 } 2383 } 2384 2385 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2386 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2387 // If both shuffles use the same mask, and both shuffle within a single 2388 // vector, then it is worthwhile to move the swizzle after the operation. 2389 // The type-legalizer generates this pattern when loading illegal 2390 // vector types from memory. In many cases this allows additional shuffle 2391 // optimizations. 2392 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2393 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2394 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2395 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2396 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2397 2398 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2399 "Inputs to shuffles are not the same type"); 2400 2401 unsigned NumElts = VT.getVectorNumElements(); 2402 2403 // Check that both shuffles use the same mask. The masks are known to be of 2404 // the same length because the result vector type is the same. 2405 bool SameMask = true; 2406 for (unsigned i = 0; i != NumElts; ++i) { 2407 int Idx0 = SVN0->getMaskElt(i); 2408 int Idx1 = SVN1->getMaskElt(i); 2409 if (Idx0 != Idx1) { 2410 SameMask = false; 2411 break; 2412 } 2413 } 2414 2415 if (SameMask) { 2416 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2417 N0.getOperand(0), N1.getOperand(0)); 2418 AddToWorkList(Op.getNode()); 2419 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2420 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2421 } 2422 } 2423 2424 return SDValue(); 2425} 2426 2427SDValue DAGCombiner::visitAND(SDNode *N) { 2428 SDValue N0 = N->getOperand(0); 2429 SDValue N1 = N->getOperand(1); 2430 SDValue LL, LR, RL, RR, CC0, CC1; 2431 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2432 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2433 EVT VT = N1.getValueType(); 2434 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2435 2436 // fold vector ops 2437 if (VT.isVector()) { 2438 SDValue FoldedVOp = SimplifyVBinOp(N); 2439 if (FoldedVOp.getNode()) return FoldedVOp; 2440 2441 // fold (and x, 0) -> 0, vector edition 2442 if (ISD::isBuildVectorAllZeros(N0.getNode())) 2443 return N0; 2444 if (ISD::isBuildVectorAllZeros(N1.getNode())) 2445 return N1; 2446 2447 // fold (and x, -1) -> x, vector edition 2448 if (ISD::isBuildVectorAllOnes(N0.getNode())) 2449 return N1; 2450 if (ISD::isBuildVectorAllOnes(N1.getNode())) 2451 return N0; 2452 } 2453 2454 // fold (and x, undef) -> 0 2455 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2456 return DAG.getConstant(0, VT); 2457 // fold (and c1, c2) -> c1&c2 2458 if (N0C && N1C) 2459 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2460 // canonicalize constant to RHS 2461 if (N0C && !N1C) 2462 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2463 // fold (and x, -1) -> x 2464 if (N1C && N1C->isAllOnesValue()) 2465 return N0; 2466 // if (and x, c) is known to be zero, return 0 2467 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2468 APInt::getAllOnesValue(BitWidth))) 2469 return DAG.getConstant(0, VT); 2470 // reassociate and 2471 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2472 if (RAND.getNode() != 0) 2473 return RAND; 2474 // fold (and (or x, C), D) -> D if (C & D) == D 2475 if (N1C && N0.getOpcode() == ISD::OR) 2476 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2477 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2478 return N1; 2479 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2480 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2481 SDValue N0Op0 = N0.getOperand(0); 2482 APInt Mask = ~N1C->getAPIntValue(); 2483 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2484 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2485 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2486 N0.getValueType(), N0Op0); 2487 2488 // Replace uses of the AND with uses of the Zero extend node. 2489 CombineTo(N, Zext); 2490 2491 // We actually want to replace all uses of the any_extend with the 2492 // zero_extend, to avoid duplicating things. This will later cause this 2493 // AND to be folded. 2494 CombineTo(N0.getNode(), Zext); 2495 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2496 } 2497 } 2498 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2499 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2500 // already be zero by virtue of the width of the base type of the load. 2501 // 2502 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2503 // more cases. 2504 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2505 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2506 N0.getOpcode() == ISD::LOAD) { 2507 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2508 N0 : N0.getOperand(0) ); 2509 2510 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2511 // This can be a pure constant or a vector splat, in which case we treat the 2512 // vector as a scalar and use the splat value. 2513 APInt Constant = APInt::getNullValue(1); 2514 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2515 Constant = C->getAPIntValue(); 2516 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2517 APInt SplatValue, SplatUndef; 2518 unsigned SplatBitSize; 2519 bool HasAnyUndefs; 2520 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2521 SplatBitSize, HasAnyUndefs); 2522 if (IsSplat) { 2523 // Undef bits can contribute to a possible optimisation if set, so 2524 // set them. 2525 SplatValue |= SplatUndef; 2526 2527 // The splat value may be something like "0x00FFFFFF", which means 0 for 2528 // the first vector value and FF for the rest, repeating. We need a mask 2529 // that will apply equally to all members of the vector, so AND all the 2530 // lanes of the constant together. 2531 EVT VT = Vector->getValueType(0); 2532 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2533 2534 // If the splat value has been compressed to a bitlength lower 2535 // than the size of the vector lane, we need to re-expand it to 2536 // the lane size. 2537 if (BitWidth > SplatBitSize) 2538 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2539 SplatBitSize < BitWidth; 2540 SplatBitSize = SplatBitSize * 2) 2541 SplatValue |= SplatValue.shl(SplatBitSize); 2542 2543 Constant = APInt::getAllOnesValue(BitWidth); 2544 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2545 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2546 } 2547 } 2548 2549 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2550 // actually legal and isn't going to get expanded, else this is a false 2551 // optimisation. 2552 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2553 Load->getMemoryVT()); 2554 2555 // Resize the constant to the same size as the original memory access before 2556 // extension. If it is still the AllOnesValue then this AND is completely 2557 // unneeded. 2558 Constant = 2559 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2560 2561 bool B; 2562 switch (Load->getExtensionType()) { 2563 default: B = false; break; 2564 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2565 case ISD::ZEXTLOAD: 2566 case ISD::NON_EXTLOAD: B = true; break; 2567 } 2568 2569 if (B && Constant.isAllOnesValue()) { 2570 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2571 // preserve semantics once we get rid of the AND. 2572 SDValue NewLoad(Load, 0); 2573 if (Load->getExtensionType() == ISD::EXTLOAD) { 2574 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2575 Load->getValueType(0), Load->getDebugLoc(), 2576 Load->getChain(), Load->getBasePtr(), 2577 Load->getOffset(), Load->getMemoryVT(), 2578 Load->getMemOperand()); 2579 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2580 if (Load->getNumValues() == 3) { 2581 // PRE/POST_INC loads have 3 values. 2582 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2583 NewLoad.getValue(2) }; 2584 CombineTo(Load, To, 3, true); 2585 } else { 2586 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2587 } 2588 } 2589 2590 // Fold the AND away, taking care not to fold to the old load node if we 2591 // replaced it. 2592 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2593 2594 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2595 } 2596 } 2597 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2598 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2599 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2600 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2601 2602 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2603 LL.getValueType().isInteger()) { 2604 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2605 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2606 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2607 LR.getValueType(), LL, RL); 2608 AddToWorkList(ORNode.getNode()); 2609 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2610 } 2611 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2612 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2613 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2614 LR.getValueType(), LL, RL); 2615 AddToWorkList(ANDNode.getNode()); 2616 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2617 } 2618 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2619 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2620 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2621 LR.getValueType(), LL, RL); 2622 AddToWorkList(ORNode.getNode()); 2623 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2624 } 2625 } 2626 // canonicalize equivalent to ll == rl 2627 if (LL == RR && LR == RL) { 2628 Op1 = ISD::getSetCCSwappedOperands(Op1); 2629 std::swap(RL, RR); 2630 } 2631 if (LL == RL && LR == RR) { 2632 bool isInteger = LL.getValueType().isInteger(); 2633 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2634 if (Result != ISD::SETCC_INVALID && 2635 (!LegalOperations || 2636 TLI.isCondCodeLegal(Result, LL.getSimpleValueType()))) 2637 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2638 LL, LR, Result); 2639 } 2640 } 2641 2642 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2643 if (N0.getOpcode() == N1.getOpcode()) { 2644 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2645 if (Tmp.getNode()) return Tmp; 2646 } 2647 2648 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2649 // fold (and (sra)) -> (and (srl)) when possible. 2650 if (!VT.isVector() && 2651 SimplifyDemandedBits(SDValue(N, 0))) 2652 return SDValue(N, 0); 2653 2654 // fold (zext_inreg (extload x)) -> (zextload x) 2655 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2656 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2657 EVT MemVT = LN0->getMemoryVT(); 2658 // If we zero all the possible extended bits, then we can turn this into 2659 // a zextload if we are running before legalize or the operation is legal. 2660 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2661 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2662 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2663 ((!LegalOperations && !LN0->isVolatile()) || 2664 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2665 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2666 LN0->getChain(), LN0->getBasePtr(), 2667 LN0->getPointerInfo(), MemVT, 2668 LN0->isVolatile(), LN0->isNonTemporal(), 2669 LN0->getAlignment()); 2670 AddToWorkList(N); 2671 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2672 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2673 } 2674 } 2675 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2676 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2677 N0.hasOneUse()) { 2678 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2679 EVT MemVT = LN0->getMemoryVT(); 2680 // If we zero all the possible extended bits, then we can turn this into 2681 // a zextload if we are running before legalize or the operation is legal. 2682 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2683 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2684 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2685 ((!LegalOperations && !LN0->isVolatile()) || 2686 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2687 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2688 LN0->getChain(), 2689 LN0->getBasePtr(), LN0->getPointerInfo(), 2690 MemVT, 2691 LN0->isVolatile(), LN0->isNonTemporal(), 2692 LN0->getAlignment()); 2693 AddToWorkList(N); 2694 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2695 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2696 } 2697 } 2698 2699 // fold (and (load x), 255) -> (zextload x, i8) 2700 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2701 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2702 if (N1C && (N0.getOpcode() == ISD::LOAD || 2703 (N0.getOpcode() == ISD::ANY_EXTEND && 2704 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2705 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2706 LoadSDNode *LN0 = HasAnyExt 2707 ? cast<LoadSDNode>(N0.getOperand(0)) 2708 : cast<LoadSDNode>(N0); 2709 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2710 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2711 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2712 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2713 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2714 EVT LoadedVT = LN0->getMemoryVT(); 2715 2716 if (ExtVT == LoadedVT && 2717 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2718 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2719 2720 SDValue NewLoad = 2721 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2722 LN0->getChain(), LN0->getBasePtr(), 2723 LN0->getPointerInfo(), 2724 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2725 LN0->getAlignment()); 2726 AddToWorkList(N); 2727 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2728 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2729 } 2730 2731 // Do not change the width of a volatile load. 2732 // Do not generate loads of non-round integer types since these can 2733 // be expensive (and would be wrong if the type is not byte sized). 2734 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2735 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2736 EVT PtrType = LN0->getOperand(1).getValueType(); 2737 2738 unsigned Alignment = LN0->getAlignment(); 2739 SDValue NewPtr = LN0->getBasePtr(); 2740 2741 // For big endian targets, we need to add an offset to the pointer 2742 // to load the correct bytes. For little endian systems, we merely 2743 // need to read fewer bytes from the same pointer. 2744 if (TLI.isBigEndian()) { 2745 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2746 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2747 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2748 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2749 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2750 Alignment = MinAlign(Alignment, PtrOff); 2751 } 2752 2753 AddToWorkList(NewPtr.getNode()); 2754 2755 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2756 SDValue Load = 2757 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2758 LN0->getChain(), NewPtr, 2759 LN0->getPointerInfo(), 2760 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2761 Alignment); 2762 AddToWorkList(N); 2763 CombineTo(LN0, Load, Load.getValue(1)); 2764 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2765 } 2766 } 2767 } 2768 } 2769 2770 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2771 VT.getSizeInBits() <= 64) { 2772 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2773 APInt ADDC = ADDI->getAPIntValue(); 2774 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2775 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2776 // immediate for an add, but it is legal if its top c2 bits are set, 2777 // transform the ADD so the immediate doesn't need to be materialized 2778 // in a register. 2779 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2780 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2781 SRLI->getZExtValue()); 2782 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2783 ADDC |= Mask; 2784 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2785 SDValue NewAdd = 2786 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 2787 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2788 CombineTo(N0.getNode(), NewAdd); 2789 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2790 } 2791 } 2792 } 2793 } 2794 } 2795 } 2796 2797 return SDValue(); 2798} 2799 2800/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2801/// 2802SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2803 bool DemandHighBits) { 2804 if (!LegalOperations) 2805 return SDValue(); 2806 2807 EVT VT = N->getValueType(0); 2808 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2809 return SDValue(); 2810 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2811 return SDValue(); 2812 2813 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2814 bool LookPassAnd0 = false; 2815 bool LookPassAnd1 = false; 2816 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2817 std::swap(N0, N1); 2818 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2819 std::swap(N0, N1); 2820 if (N0.getOpcode() == ISD::AND) { 2821 if (!N0.getNode()->hasOneUse()) 2822 return SDValue(); 2823 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2824 if (!N01C || N01C->getZExtValue() != 0xFF00) 2825 return SDValue(); 2826 N0 = N0.getOperand(0); 2827 LookPassAnd0 = true; 2828 } 2829 2830 if (N1.getOpcode() == ISD::AND) { 2831 if (!N1.getNode()->hasOneUse()) 2832 return SDValue(); 2833 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2834 if (!N11C || N11C->getZExtValue() != 0xFF) 2835 return SDValue(); 2836 N1 = N1.getOperand(0); 2837 LookPassAnd1 = true; 2838 } 2839 2840 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2841 std::swap(N0, N1); 2842 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2843 return SDValue(); 2844 if (!N0.getNode()->hasOneUse() || 2845 !N1.getNode()->hasOneUse()) 2846 return SDValue(); 2847 2848 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2849 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2850 if (!N01C || !N11C) 2851 return SDValue(); 2852 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2853 return SDValue(); 2854 2855 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2856 SDValue N00 = N0->getOperand(0); 2857 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2858 if (!N00.getNode()->hasOneUse()) 2859 return SDValue(); 2860 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2861 if (!N001C || N001C->getZExtValue() != 0xFF) 2862 return SDValue(); 2863 N00 = N00.getOperand(0); 2864 LookPassAnd0 = true; 2865 } 2866 2867 SDValue N10 = N1->getOperand(0); 2868 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2869 if (!N10.getNode()->hasOneUse()) 2870 return SDValue(); 2871 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2872 if (!N101C || N101C->getZExtValue() != 0xFF00) 2873 return SDValue(); 2874 N10 = N10.getOperand(0); 2875 LookPassAnd1 = true; 2876 } 2877 2878 if (N00 != N10) 2879 return SDValue(); 2880 2881 // Make sure everything beyond the low halfword is zero since the SRL 16 2882 // will clear the top bits. 2883 unsigned OpSizeInBits = VT.getSizeInBits(); 2884 if (DemandHighBits && OpSizeInBits > 16 && 2885 (!LookPassAnd0 || !LookPassAnd1) && 2886 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2887 return SDValue(); 2888 2889 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2890 if (OpSizeInBits > 16) 2891 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2892 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2893 return Res; 2894} 2895 2896/// isBSwapHWordElement - Return true if the specified node is an element 2897/// that makes up a 32-bit packed halfword byteswap. i.e. 2898/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2899static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2900 if (!N.getNode()->hasOneUse()) 2901 return false; 2902 2903 unsigned Opc = N.getOpcode(); 2904 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2905 return false; 2906 2907 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2908 if (!N1C) 2909 return false; 2910 2911 unsigned Num; 2912 switch (N1C->getZExtValue()) { 2913 default: 2914 return false; 2915 case 0xFF: Num = 0; break; 2916 case 0xFF00: Num = 1; break; 2917 case 0xFF0000: Num = 2; break; 2918 case 0xFF000000: Num = 3; break; 2919 } 2920 2921 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2922 SDValue N0 = N.getOperand(0); 2923 if (Opc == ISD::AND) { 2924 if (Num == 0 || Num == 2) { 2925 // (x >> 8) & 0xff 2926 // (x >> 8) & 0xff0000 2927 if (N0.getOpcode() != ISD::SRL) 2928 return false; 2929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2930 if (!C || C->getZExtValue() != 8) 2931 return false; 2932 } else { 2933 // (x << 8) & 0xff00 2934 // (x << 8) & 0xff000000 2935 if (N0.getOpcode() != ISD::SHL) 2936 return false; 2937 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2938 if (!C || C->getZExtValue() != 8) 2939 return false; 2940 } 2941 } else if (Opc == ISD::SHL) { 2942 // (x & 0xff) << 8 2943 // (x & 0xff0000) << 8 2944 if (Num != 0 && Num != 2) 2945 return false; 2946 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2947 if (!C || C->getZExtValue() != 8) 2948 return false; 2949 } else { // Opc == ISD::SRL 2950 // (x & 0xff00) >> 8 2951 // (x & 0xff000000) >> 8 2952 if (Num != 1 && Num != 3) 2953 return false; 2954 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2955 if (!C || C->getZExtValue() != 8) 2956 return false; 2957 } 2958 2959 if (Parts[Num]) 2960 return false; 2961 2962 Parts[Num] = N0.getOperand(0).getNode(); 2963 return true; 2964} 2965 2966/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2967/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2968/// => (rotl (bswap x), 16) 2969SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2970 if (!LegalOperations) 2971 return SDValue(); 2972 2973 EVT VT = N->getValueType(0); 2974 if (VT != MVT::i32) 2975 return SDValue(); 2976 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2977 return SDValue(); 2978 2979 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2980 // Look for either 2981 // (or (or (and), (and)), (or (and), (and))) 2982 // (or (or (or (and), (and)), (and)), (and)) 2983 if (N0.getOpcode() != ISD::OR) 2984 return SDValue(); 2985 SDValue N00 = N0.getOperand(0); 2986 SDValue N01 = N0.getOperand(1); 2987 2988 if (N1.getOpcode() == ISD::OR) { 2989 // (or (or (and), (and)), (or (and), (and))) 2990 SDValue N000 = N00.getOperand(0); 2991 if (!isBSwapHWordElement(N000, Parts)) 2992 return SDValue(); 2993 2994 SDValue N001 = N00.getOperand(1); 2995 if (!isBSwapHWordElement(N001, Parts)) 2996 return SDValue(); 2997 SDValue N010 = N01.getOperand(0); 2998 if (!isBSwapHWordElement(N010, Parts)) 2999 return SDValue(); 3000 SDValue N011 = N01.getOperand(1); 3001 if (!isBSwapHWordElement(N011, Parts)) 3002 return SDValue(); 3003 } else { 3004 // (or (or (or (and), (and)), (and)), (and)) 3005 if (!isBSwapHWordElement(N1, Parts)) 3006 return SDValue(); 3007 if (!isBSwapHWordElement(N01, Parts)) 3008 return SDValue(); 3009 if (N00.getOpcode() != ISD::OR) 3010 return SDValue(); 3011 SDValue N000 = N00.getOperand(0); 3012 if (!isBSwapHWordElement(N000, Parts)) 3013 return SDValue(); 3014 SDValue N001 = N00.getOperand(1); 3015 if (!isBSwapHWordElement(N001, Parts)) 3016 return SDValue(); 3017 } 3018 3019 // Make sure the parts are all coming from the same node. 3020 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 3021 return SDValue(); 3022 3023 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 3024 SDValue(Parts[0],0)); 3025 3026 // Result of the bswap should be rotated by 16. If it's not legal, than 3027 // do (x << 16) | (x >> 16). 3028 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 3029 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3030 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 3031 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3032 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 3033 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 3034 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 3035 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 3036} 3037 3038SDValue DAGCombiner::visitOR(SDNode *N) { 3039 SDValue N0 = N->getOperand(0); 3040 SDValue N1 = N->getOperand(1); 3041 SDValue LL, LR, RL, RR, CC0, CC1; 3042 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3043 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3044 EVT VT = N1.getValueType(); 3045 3046 // fold vector ops 3047 if (VT.isVector()) { 3048 SDValue FoldedVOp = SimplifyVBinOp(N); 3049 if (FoldedVOp.getNode()) return FoldedVOp; 3050 3051 // fold (or x, 0) -> x, vector edition 3052 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3053 return N1; 3054 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3055 return N0; 3056 3057 // fold (or x, -1) -> -1, vector edition 3058 if (ISD::isBuildVectorAllOnes(N0.getNode())) 3059 return N0; 3060 if (ISD::isBuildVectorAllOnes(N1.getNode())) 3061 return N1; 3062 } 3063 3064 // fold (or x, undef) -> -1 3065 if (!LegalOperations && 3066 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3067 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3068 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3069 } 3070 // fold (or c1, c2) -> c1|c2 3071 if (N0C && N1C) 3072 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3073 // canonicalize constant to RHS 3074 if (N0C && !N1C) 3075 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 3076 // fold (or x, 0) -> x 3077 if (N1C && N1C->isNullValue()) 3078 return N0; 3079 // fold (or x, -1) -> -1 3080 if (N1C && N1C->isAllOnesValue()) 3081 return N1; 3082 // fold (or x, c) -> c iff (x & ~c) == 0 3083 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3084 return N1; 3085 3086 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3087 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3088 if (BSwap.getNode() != 0) 3089 return BSwap; 3090 BSwap = MatchBSwapHWordLow(N, N0, N1); 3091 if (BSwap.getNode() != 0) 3092 return BSwap; 3093 3094 // reassociate or 3095 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3096 if (ROR.getNode() != 0) 3097 return ROR; 3098 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3099 // iff (c1 & c2) == 0. 3100 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3101 isa<ConstantSDNode>(N0.getOperand(1))) { 3102 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3103 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3104 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3105 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3106 N0.getOperand(0), N1), 3107 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3108 } 3109 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3110 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3111 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3112 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3113 3114 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3115 LL.getValueType().isInteger()) { 3116 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3117 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3118 if (cast<ConstantSDNode>(LR)->isNullValue() && 3119 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3120 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3121 LR.getValueType(), LL, RL); 3122 AddToWorkList(ORNode.getNode()); 3123 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3124 } 3125 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3126 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3127 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3128 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3129 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3130 LR.getValueType(), LL, RL); 3131 AddToWorkList(ANDNode.getNode()); 3132 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3133 } 3134 } 3135 // canonicalize equivalent to ll == rl 3136 if (LL == RR && LR == RL) { 3137 Op1 = ISD::getSetCCSwappedOperands(Op1); 3138 std::swap(RL, RR); 3139 } 3140 if (LL == RL && LR == RR) { 3141 bool isInteger = LL.getValueType().isInteger(); 3142 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3143 if (Result != ISD::SETCC_INVALID && 3144 (!LegalOperations || 3145 TLI.isCondCodeLegal(Result, LL.getSimpleValueType()))) 3146 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3147 LL, LR, Result); 3148 } 3149 } 3150 3151 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3152 if (N0.getOpcode() == N1.getOpcode()) { 3153 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3154 if (Tmp.getNode()) return Tmp; 3155 } 3156 3157 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3158 if (N0.getOpcode() == ISD::AND && 3159 N1.getOpcode() == ISD::AND && 3160 N0.getOperand(1).getOpcode() == ISD::Constant && 3161 N1.getOperand(1).getOpcode() == ISD::Constant && 3162 // Don't increase # computations. 3163 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3164 // We can only do this xform if we know that bits from X that are set in C2 3165 // but not in C1 are already zero. Likewise for Y. 3166 const APInt &LHSMask = 3167 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3168 const APInt &RHSMask = 3169 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3170 3171 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3172 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3173 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3174 N0.getOperand(0), N1.getOperand(0)); 3175 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3176 DAG.getConstant(LHSMask | RHSMask, VT)); 3177 } 3178 } 3179 3180 // See if this is some rotate idiom. 3181 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3182 return SDValue(Rot, 0); 3183 3184 // Simplify the operands using demanded-bits information. 3185 if (!VT.isVector() && 3186 SimplifyDemandedBits(SDValue(N, 0))) 3187 return SDValue(N, 0); 3188 3189 return SDValue(); 3190} 3191 3192/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3193static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3194 if (Op.getOpcode() == ISD::AND) { 3195 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3196 Mask = Op.getOperand(1); 3197 Op = Op.getOperand(0); 3198 } else { 3199 return false; 3200 } 3201 } 3202 3203 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3204 Shift = Op; 3205 return true; 3206 } 3207 3208 return false; 3209} 3210 3211// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3212// idioms for rotate, and if the target supports rotation instructions, generate 3213// a rot[lr]. 3214SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3215 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3216 EVT VT = LHS.getValueType(); 3217 if (!TLI.isTypeLegal(VT)) return 0; 3218 3219 // The target must have at least one rotate flavor. 3220 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3221 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3222 if (!HasROTL && !HasROTR) return 0; 3223 3224 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3225 SDValue LHSShift; // The shift. 3226 SDValue LHSMask; // AND value if any. 3227 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3228 return 0; // Not part of a rotate. 3229 3230 SDValue RHSShift; // The shift. 3231 SDValue RHSMask; // AND value if any. 3232 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3233 return 0; // Not part of a rotate. 3234 3235 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3236 return 0; // Not shifting the same value. 3237 3238 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3239 return 0; // Shifts must disagree. 3240 3241 // Canonicalize shl to left side in a shl/srl pair. 3242 if (RHSShift.getOpcode() == ISD::SHL) { 3243 std::swap(LHS, RHS); 3244 std::swap(LHSShift, RHSShift); 3245 std::swap(LHSMask , RHSMask ); 3246 } 3247 3248 unsigned OpSizeInBits = VT.getSizeInBits(); 3249 SDValue LHSShiftArg = LHSShift.getOperand(0); 3250 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3251 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3252 3253 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3254 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3255 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3256 RHSShiftAmt.getOpcode() == ISD::Constant) { 3257 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3258 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3259 if ((LShVal + RShVal) != OpSizeInBits) 3260 return 0; 3261 3262 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3263 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt); 3264 3265 // If there is an AND of either shifted operand, apply it to the result. 3266 if (LHSMask.getNode() || RHSMask.getNode()) { 3267 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3268 3269 if (LHSMask.getNode()) { 3270 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3271 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3272 } 3273 if (RHSMask.getNode()) { 3274 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3275 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3276 } 3277 3278 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3279 } 3280 3281 return Rot.getNode(); 3282 } 3283 3284 // If there is a mask here, and we have a variable shift, we can't be sure 3285 // that we're masking out the right stuff. 3286 if (LHSMask.getNode() || RHSMask.getNode()) 3287 return 0; 3288 3289 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3290 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3291 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3292 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3293 if (ConstantSDNode *SUBC = 3294 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3295 if (SUBC->getAPIntValue() == OpSizeInBits) { 3296 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, 3297 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3298 } 3299 } 3300 } 3301 3302 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3303 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3304 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3305 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3306 if (ConstantSDNode *SUBC = 3307 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3308 if (SUBC->getAPIntValue() == OpSizeInBits) { 3309 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, 3310 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3311 } 3312 } 3313 } 3314 3315 // Look for sign/zext/any-extended or truncate cases: 3316 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3317 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3318 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3319 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3320 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3321 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3322 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3323 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3324 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3325 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3326 if (RExtOp0.getOpcode() == ISD::SUB && 3327 RExtOp0.getOperand(1) == LExtOp0) { 3328 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3329 // (rotl x, y) 3330 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3331 // (rotr x, (sub 32, y)) 3332 if (ConstantSDNode *SUBC = 3333 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3334 if (SUBC->getAPIntValue() == OpSizeInBits) { 3335 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3336 LHSShiftArg, 3337 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3338 } 3339 } 3340 } else if (LExtOp0.getOpcode() == ISD::SUB && 3341 RExtOp0 == LExtOp0.getOperand(1)) { 3342 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3343 // (rotr x, y) 3344 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3345 // (rotl x, (sub 32, y)) 3346 if (ConstantSDNode *SUBC = 3347 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3348 if (SUBC->getAPIntValue() == OpSizeInBits) { 3349 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3350 LHSShiftArg, 3351 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3352 } 3353 } 3354 } 3355 } 3356 3357 return 0; 3358} 3359 3360SDValue DAGCombiner::visitXOR(SDNode *N) { 3361 SDValue N0 = N->getOperand(0); 3362 SDValue N1 = N->getOperand(1); 3363 SDValue LHS, RHS, CC; 3364 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3365 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3366 EVT VT = N0.getValueType(); 3367 3368 // fold vector ops 3369 if (VT.isVector()) { 3370 SDValue FoldedVOp = SimplifyVBinOp(N); 3371 if (FoldedVOp.getNode()) return FoldedVOp; 3372 3373 // fold (xor x, 0) -> x, vector edition 3374 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3375 return N1; 3376 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3377 return N0; 3378 } 3379 3380 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3381 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3382 return DAG.getConstant(0, VT); 3383 // fold (xor x, undef) -> undef 3384 if (N0.getOpcode() == ISD::UNDEF) 3385 return N0; 3386 if (N1.getOpcode() == ISD::UNDEF) 3387 return N1; 3388 // fold (xor c1, c2) -> c1^c2 3389 if (N0C && N1C) 3390 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3391 // canonicalize constant to RHS 3392 if (N0C && !N1C) 3393 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3394 // fold (xor x, 0) -> x 3395 if (N1C && N1C->isNullValue()) 3396 return N0; 3397 // reassociate xor 3398 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3399 if (RXOR.getNode() != 0) 3400 return RXOR; 3401 3402 // fold !(x cc y) -> (x !cc y) 3403 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3404 bool isInt = LHS.getValueType().isInteger(); 3405 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3406 isInt); 3407 3408 if (!LegalOperations || 3409 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) { 3410 switch (N0.getOpcode()) { 3411 default: 3412 llvm_unreachable("Unhandled SetCC Equivalent!"); 3413 case ISD::SETCC: 3414 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3415 case ISD::SELECT_CC: 3416 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3417 N0.getOperand(3), NotCC); 3418 } 3419 } 3420 } 3421 3422 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3423 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3424 N0.getNode()->hasOneUse() && 3425 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3426 SDValue V = N0.getOperand(0); 3427 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3428 DAG.getConstant(1, V.getValueType())); 3429 AddToWorkList(V.getNode()); 3430 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3431 } 3432 3433 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3434 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3435 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3436 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3437 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3438 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3439 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3440 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3441 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3442 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3443 } 3444 } 3445 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3446 if (N1C && N1C->isAllOnesValue() && 3447 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3448 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3449 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3450 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3451 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3452 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3453 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3454 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3455 } 3456 } 3457 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3458 if (N1C && N0.getOpcode() == ISD::XOR) { 3459 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3460 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3461 if (N00C) 3462 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3463 DAG.getConstant(N1C->getAPIntValue() ^ 3464 N00C->getAPIntValue(), VT)); 3465 if (N01C) 3466 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3467 DAG.getConstant(N1C->getAPIntValue() ^ 3468 N01C->getAPIntValue(), VT)); 3469 } 3470 // fold (xor x, x) -> 0 3471 if (N0 == N1) 3472 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3473 3474 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3475 if (N0.getOpcode() == N1.getOpcode()) { 3476 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3477 if (Tmp.getNode()) return Tmp; 3478 } 3479 3480 // Simplify the expression using non-local knowledge. 3481 if (!VT.isVector() && 3482 SimplifyDemandedBits(SDValue(N, 0))) 3483 return SDValue(N, 0); 3484 3485 return SDValue(); 3486} 3487 3488/// visitShiftByConstant - Handle transforms common to the three shifts, when 3489/// the shift amount is a constant. 3490SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3491 SDNode *LHS = N->getOperand(0).getNode(); 3492 if (!LHS->hasOneUse()) return SDValue(); 3493 3494 // We want to pull some binops through shifts, so that we have (and (shift)) 3495 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3496 // thing happens with address calculations, so it's important to canonicalize 3497 // it. 3498 bool HighBitSet = false; // Can we transform this if the high bit is set? 3499 3500 switch (LHS->getOpcode()) { 3501 default: return SDValue(); 3502 case ISD::OR: 3503 case ISD::XOR: 3504 HighBitSet = false; // We can only transform sra if the high bit is clear. 3505 break; 3506 case ISD::AND: 3507 HighBitSet = true; // We can only transform sra if the high bit is set. 3508 break; 3509 case ISD::ADD: 3510 if (N->getOpcode() != ISD::SHL) 3511 return SDValue(); // only shl(add) not sr[al](add). 3512 HighBitSet = false; // We can only transform sra if the high bit is clear. 3513 break; 3514 } 3515 3516 // We require the RHS of the binop to be a constant as well. 3517 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3518 if (!BinOpCst) return SDValue(); 3519 3520 // FIXME: disable this unless the input to the binop is a shift by a constant. 3521 // If it is not a shift, it pessimizes some common cases like: 3522 // 3523 // void foo(int *X, int i) { X[i & 1235] = 1; } 3524 // int bar(int *X, int i) { return X[i & 255]; } 3525 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3526 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3527 BinOpLHSVal->getOpcode() != ISD::SRA && 3528 BinOpLHSVal->getOpcode() != ISD::SRL) || 3529 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3530 return SDValue(); 3531 3532 EVT VT = N->getValueType(0); 3533 3534 // If this is a signed shift right, and the high bit is modified by the 3535 // logical operation, do not perform the transformation. The highBitSet 3536 // boolean indicates the value of the high bit of the constant which would 3537 // cause it to be modified for this operation. 3538 if (N->getOpcode() == ISD::SRA) { 3539 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3540 if (BinOpRHSSignSet != HighBitSet) 3541 return SDValue(); 3542 } 3543 3544 // Fold the constants, shifting the binop RHS by the shift amount. 3545 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3546 N->getValueType(0), 3547 LHS->getOperand(1), N->getOperand(1)); 3548 3549 // Create the new shift. 3550 SDValue NewShift = DAG.getNode(N->getOpcode(), 3551 LHS->getOperand(0).getDebugLoc(), 3552 VT, LHS->getOperand(0), N->getOperand(1)); 3553 3554 // Create the new binop. 3555 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3556} 3557 3558SDValue DAGCombiner::visitSHL(SDNode *N) { 3559 SDValue N0 = N->getOperand(0); 3560 SDValue N1 = N->getOperand(1); 3561 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3562 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3563 EVT VT = N0.getValueType(); 3564 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3565 3566 // fold (shl c1, c2) -> c1<<c2 3567 if (N0C && N1C) 3568 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3569 // fold (shl 0, x) -> 0 3570 if (N0C && N0C->isNullValue()) 3571 return N0; 3572 // fold (shl x, c >= size(x)) -> undef 3573 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3574 return DAG.getUNDEF(VT); 3575 // fold (shl x, 0) -> x 3576 if (N1C && N1C->isNullValue()) 3577 return N0; 3578 // fold (shl undef, x) -> 0 3579 if (N0.getOpcode() == ISD::UNDEF) 3580 return DAG.getConstant(0, VT); 3581 // if (shl x, c) is known to be zero, return 0 3582 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3583 APInt::getAllOnesValue(OpSizeInBits))) 3584 return DAG.getConstant(0, VT); 3585 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3586 if (N1.getOpcode() == ISD::TRUNCATE && 3587 N1.getOperand(0).getOpcode() == ISD::AND && 3588 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3589 SDValue N101 = N1.getOperand(0).getOperand(1); 3590 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3591 EVT TruncVT = N1.getValueType(); 3592 SDValue N100 = N1.getOperand(0).getOperand(0); 3593 APInt TruncC = N101C->getAPIntValue(); 3594 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3595 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3596 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3597 DAG.getNode(ISD::TRUNCATE, 3598 N->getDebugLoc(), 3599 TruncVT, N100), 3600 DAG.getConstant(TruncC, TruncVT))); 3601 } 3602 } 3603 3604 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3605 return SDValue(N, 0); 3606 3607 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3608 if (N1C && N0.getOpcode() == ISD::SHL && 3609 N0.getOperand(1).getOpcode() == ISD::Constant) { 3610 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3611 uint64_t c2 = N1C->getZExtValue(); 3612 if (c1 + c2 >= OpSizeInBits) 3613 return DAG.getConstant(0, VT); 3614 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3615 DAG.getConstant(c1 + c2, N1.getValueType())); 3616 } 3617 3618 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3619 // For this to be valid, the second form must not preserve any of the bits 3620 // that are shifted out by the inner shift in the first form. This means 3621 // the outer shift size must be >= the number of bits added by the ext. 3622 // As a corollary, we don't care what kind of ext it is. 3623 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3624 N0.getOpcode() == ISD::ANY_EXTEND || 3625 N0.getOpcode() == ISD::SIGN_EXTEND) && 3626 N0.getOperand(0).getOpcode() == ISD::SHL && 3627 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3628 uint64_t c1 = 3629 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3630 uint64_t c2 = N1C->getZExtValue(); 3631 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3632 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3633 if (c2 >= OpSizeInBits - InnerShiftSize) { 3634 if (c1 + c2 >= OpSizeInBits) 3635 return DAG.getConstant(0, VT); 3636 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3637 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3638 N0.getOperand(0)->getOperand(0)), 3639 DAG.getConstant(c1 + c2, N1.getValueType())); 3640 } 3641 } 3642 3643 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3644 // (and (srl x, (sub c1, c2), MASK) 3645 // Only fold this if the inner shift has no other uses -- if it does, folding 3646 // this will increase the total number of instructions. 3647 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3648 N0.getOperand(1).getOpcode() == ISD::Constant) { 3649 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3650 if (c1 < VT.getSizeInBits()) { 3651 uint64_t c2 = N1C->getZExtValue(); 3652 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3653 VT.getSizeInBits() - c1); 3654 SDValue Shift; 3655 if (c2 > c1) { 3656 Mask = Mask.shl(c2-c1); 3657 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3658 DAG.getConstant(c2-c1, N1.getValueType())); 3659 } else { 3660 Mask = Mask.lshr(c1-c2); 3661 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3662 DAG.getConstant(c1-c2, N1.getValueType())); 3663 } 3664 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3665 DAG.getConstant(Mask, VT)); 3666 } 3667 } 3668 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3669 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3670 SDValue HiBitsMask = 3671 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3672 VT.getSizeInBits() - 3673 N1C->getZExtValue()), 3674 VT); 3675 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3676 HiBitsMask); 3677 } 3678 3679 if (N1C) { 3680 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3681 if (NewSHL.getNode()) 3682 return NewSHL; 3683 } 3684 3685 return SDValue(); 3686} 3687 3688SDValue DAGCombiner::visitSRA(SDNode *N) { 3689 SDValue N0 = N->getOperand(0); 3690 SDValue N1 = N->getOperand(1); 3691 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3692 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3693 EVT VT = N0.getValueType(); 3694 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3695 3696 // fold (sra c1, c2) -> (sra c1, c2) 3697 if (N0C && N1C) 3698 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3699 // fold (sra 0, x) -> 0 3700 if (N0C && N0C->isNullValue()) 3701 return N0; 3702 // fold (sra -1, x) -> -1 3703 if (N0C && N0C->isAllOnesValue()) 3704 return N0; 3705 // fold (sra x, (setge c, size(x))) -> undef 3706 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3707 return DAG.getUNDEF(VT); 3708 // fold (sra x, 0) -> x 3709 if (N1C && N1C->isNullValue()) 3710 return N0; 3711 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3712 // sext_inreg. 3713 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3714 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3715 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3716 if (VT.isVector()) 3717 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3718 ExtVT, VT.getVectorNumElements()); 3719 if ((!LegalOperations || 3720 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3721 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3722 N0.getOperand(0), DAG.getValueType(ExtVT)); 3723 } 3724 3725 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3726 if (N1C && N0.getOpcode() == ISD::SRA) { 3727 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3728 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3729 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3730 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3731 DAG.getConstant(Sum, N1C->getValueType(0))); 3732 } 3733 } 3734 3735 // fold (sra (shl X, m), (sub result_size, n)) 3736 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3737 // result_size - n != m. 3738 // If truncate is free for the target sext(shl) is likely to result in better 3739 // code. 3740 if (N0.getOpcode() == ISD::SHL) { 3741 // Get the two constanst of the shifts, CN0 = m, CN = n. 3742 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3743 if (N01C && N1C) { 3744 // Determine what the truncate's result bitsize and type would be. 3745 EVT TruncVT = 3746 EVT::getIntegerVT(*DAG.getContext(), 3747 OpSizeInBits - N1C->getZExtValue()); 3748 // Determine the residual right-shift amount. 3749 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3750 3751 // If the shift is not a no-op (in which case this should be just a sign 3752 // extend already), the truncated to type is legal, sign_extend is legal 3753 // on that type, and the truncate to that type is both legal and free, 3754 // perform the transform. 3755 if ((ShiftAmt > 0) && 3756 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3757 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3758 TLI.isTruncateFree(VT, TruncVT)) { 3759 3760 SDValue Amt = DAG.getConstant(ShiftAmt, 3761 getShiftAmountTy(N0.getOperand(0).getValueType())); 3762 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3763 N0.getOperand(0), Amt); 3764 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3765 Shift); 3766 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3767 N->getValueType(0), Trunc); 3768 } 3769 } 3770 } 3771 3772 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3773 if (N1.getOpcode() == ISD::TRUNCATE && 3774 N1.getOperand(0).getOpcode() == ISD::AND && 3775 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3776 SDValue N101 = N1.getOperand(0).getOperand(1); 3777 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3778 EVT TruncVT = N1.getValueType(); 3779 SDValue N100 = N1.getOperand(0).getOperand(0); 3780 APInt TruncC = N101C->getAPIntValue(); 3781 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3782 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3783 DAG.getNode(ISD::AND, N->getDebugLoc(), 3784 TruncVT, 3785 DAG.getNode(ISD::TRUNCATE, 3786 N->getDebugLoc(), 3787 TruncVT, N100), 3788 DAG.getConstant(TruncC, TruncVT))); 3789 } 3790 } 3791 3792 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3793 // if c1 is equal to the number of bits the trunc removes 3794 if (N0.getOpcode() == ISD::TRUNCATE && 3795 (N0.getOperand(0).getOpcode() == ISD::SRL || 3796 N0.getOperand(0).getOpcode() == ISD::SRA) && 3797 N0.getOperand(0).hasOneUse() && 3798 N0.getOperand(0).getOperand(1).hasOneUse() && 3799 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3800 EVT LargeVT = N0.getOperand(0).getValueType(); 3801 ConstantSDNode *LargeShiftAmt = 3802 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3803 3804 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3805 LargeShiftAmt->getZExtValue()) { 3806 SDValue Amt = 3807 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3808 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3809 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3810 N0.getOperand(0).getOperand(0), Amt); 3811 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3812 } 3813 } 3814 3815 // Simplify, based on bits shifted out of the LHS. 3816 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3817 return SDValue(N, 0); 3818 3819 3820 // If the sign bit is known to be zero, switch this to a SRL. 3821 if (DAG.SignBitIsZero(N0)) 3822 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3823 3824 if (N1C) { 3825 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3826 if (NewSRA.getNode()) 3827 return NewSRA; 3828 } 3829 3830 return SDValue(); 3831} 3832 3833SDValue DAGCombiner::visitSRL(SDNode *N) { 3834 SDValue N0 = N->getOperand(0); 3835 SDValue N1 = N->getOperand(1); 3836 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3837 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3838 EVT VT = N0.getValueType(); 3839 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3840 3841 // fold (srl c1, c2) -> c1 >>u c2 3842 if (N0C && N1C) 3843 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3844 // fold (srl 0, x) -> 0 3845 if (N0C && N0C->isNullValue()) 3846 return N0; 3847 // fold (srl x, c >= size(x)) -> undef 3848 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3849 return DAG.getUNDEF(VT); 3850 // fold (srl x, 0) -> x 3851 if (N1C && N1C->isNullValue()) 3852 return N0; 3853 // if (srl x, c) is known to be zero, return 0 3854 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3855 APInt::getAllOnesValue(OpSizeInBits))) 3856 return DAG.getConstant(0, VT); 3857 3858 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3859 if (N1C && N0.getOpcode() == ISD::SRL && 3860 N0.getOperand(1).getOpcode() == ISD::Constant) { 3861 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3862 uint64_t c2 = N1C->getZExtValue(); 3863 if (c1 + c2 >= OpSizeInBits) 3864 return DAG.getConstant(0, VT); 3865 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3866 DAG.getConstant(c1 + c2, N1.getValueType())); 3867 } 3868 3869 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3870 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3871 N0.getOperand(0).getOpcode() == ISD::SRL && 3872 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3873 uint64_t c1 = 3874 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3875 uint64_t c2 = N1C->getZExtValue(); 3876 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3877 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3878 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3879 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3880 if (c1 + OpSizeInBits == InnerShiftSize) { 3881 if (c1 + c2 >= InnerShiftSize) 3882 return DAG.getConstant(0, VT); 3883 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3884 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3885 N0.getOperand(0)->getOperand(0), 3886 DAG.getConstant(c1 + c2, ShiftCountVT))); 3887 } 3888 } 3889 3890 // fold (srl (shl x, c), c) -> (and x, cst2) 3891 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3892 N0.getValueSizeInBits() <= 64) { 3893 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3894 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3895 DAG.getConstant(~0ULL >> ShAmt, VT)); 3896 } 3897 3898 3899 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3900 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3901 // Shifting in all undef bits? 3902 EVT SmallVT = N0.getOperand(0).getValueType(); 3903 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3904 return DAG.getUNDEF(VT); 3905 3906 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3907 uint64_t ShiftAmt = N1C->getZExtValue(); 3908 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3909 N0.getOperand(0), 3910 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3911 AddToWorkList(SmallShift.getNode()); 3912 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3913 } 3914 } 3915 3916 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3917 // bit, which is unmodified by sra. 3918 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3919 if (N0.getOpcode() == ISD::SRA) 3920 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3921 } 3922 3923 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3924 if (N1C && N0.getOpcode() == ISD::CTLZ && 3925 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3926 APInt KnownZero, KnownOne; 3927 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3928 3929 // If any of the input bits are KnownOne, then the input couldn't be all 3930 // zeros, thus the result of the srl will always be zero. 3931 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3932 3933 // If all of the bits input the to ctlz node are known to be zero, then 3934 // the result of the ctlz is "32" and the result of the shift is one. 3935 APInt UnknownBits = ~KnownZero; 3936 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3937 3938 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3939 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3940 // Okay, we know that only that the single bit specified by UnknownBits 3941 // could be set on input to the CTLZ node. If this bit is set, the SRL 3942 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3943 // to an SRL/XOR pair, which is likely to simplify more. 3944 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3945 SDValue Op = N0.getOperand(0); 3946 3947 if (ShAmt) { 3948 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3949 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3950 AddToWorkList(Op.getNode()); 3951 } 3952 3953 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3954 Op, DAG.getConstant(1, VT)); 3955 } 3956 } 3957 3958 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3959 if (N1.getOpcode() == ISD::TRUNCATE && 3960 N1.getOperand(0).getOpcode() == ISD::AND && 3961 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3962 SDValue N101 = N1.getOperand(0).getOperand(1); 3963 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3964 EVT TruncVT = N1.getValueType(); 3965 SDValue N100 = N1.getOperand(0).getOperand(0); 3966 APInt TruncC = N101C->getAPIntValue(); 3967 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3968 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3969 DAG.getNode(ISD::AND, N->getDebugLoc(), 3970 TruncVT, 3971 DAG.getNode(ISD::TRUNCATE, 3972 N->getDebugLoc(), 3973 TruncVT, N100), 3974 DAG.getConstant(TruncC, TruncVT))); 3975 } 3976 } 3977 3978 // fold operands of srl based on knowledge that the low bits are not 3979 // demanded. 3980 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3981 return SDValue(N, 0); 3982 3983 if (N1C) { 3984 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3985 if (NewSRL.getNode()) 3986 return NewSRL; 3987 } 3988 3989 // Attempt to convert a srl of a load into a narrower zero-extending load. 3990 SDValue NarrowLoad = ReduceLoadWidth(N); 3991 if (NarrowLoad.getNode()) 3992 return NarrowLoad; 3993 3994 // Here is a common situation. We want to optimize: 3995 // 3996 // %a = ... 3997 // %b = and i32 %a, 2 3998 // %c = srl i32 %b, 1 3999 // brcond i32 %c ... 4000 // 4001 // into 4002 // 4003 // %a = ... 4004 // %b = and %a, 2 4005 // %c = setcc eq %b, 0 4006 // brcond %c ... 4007 // 4008 // However when after the source operand of SRL is optimized into AND, the SRL 4009 // itself may not be optimized further. Look for it and add the BRCOND into 4010 // the worklist. 4011 if (N->hasOneUse()) { 4012 SDNode *Use = *N->use_begin(); 4013 if (Use->getOpcode() == ISD::BRCOND) 4014 AddToWorkList(Use); 4015 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 4016 // Also look pass the truncate. 4017 Use = *Use->use_begin(); 4018 if (Use->getOpcode() == ISD::BRCOND) 4019 AddToWorkList(Use); 4020 } 4021 } 4022 4023 return SDValue(); 4024} 4025 4026SDValue DAGCombiner::visitCTLZ(SDNode *N) { 4027 SDValue N0 = N->getOperand(0); 4028 EVT VT = N->getValueType(0); 4029 4030 // fold (ctlz c1) -> c2 4031 if (isa<ConstantSDNode>(N0)) 4032 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 4033 return SDValue(); 4034} 4035 4036SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 4037 SDValue N0 = N->getOperand(0); 4038 EVT VT = N->getValueType(0); 4039 4040 // fold (ctlz_zero_undef c1) -> c2 4041 if (isa<ConstantSDNode>(N0)) 4042 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4043 return SDValue(); 4044} 4045 4046SDValue DAGCombiner::visitCTTZ(SDNode *N) { 4047 SDValue N0 = N->getOperand(0); 4048 EVT VT = N->getValueType(0); 4049 4050 // fold (cttz c1) -> c2 4051 if (isa<ConstantSDNode>(N0)) 4052 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 4053 return SDValue(); 4054} 4055 4056SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4057 SDValue N0 = N->getOperand(0); 4058 EVT VT = N->getValueType(0); 4059 4060 // fold (cttz_zero_undef c1) -> c2 4061 if (isa<ConstantSDNode>(N0)) 4062 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4063 return SDValue(); 4064} 4065 4066SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4067 SDValue N0 = N->getOperand(0); 4068 EVT VT = N->getValueType(0); 4069 4070 // fold (ctpop c1) -> c2 4071 if (isa<ConstantSDNode>(N0)) 4072 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 4073 return SDValue(); 4074} 4075 4076SDValue DAGCombiner::visitSELECT(SDNode *N) { 4077 SDValue N0 = N->getOperand(0); 4078 SDValue N1 = N->getOperand(1); 4079 SDValue N2 = N->getOperand(2); 4080 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4081 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4082 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4083 EVT VT = N->getValueType(0); 4084 EVT VT0 = N0.getValueType(); 4085 4086 // fold (select C, X, X) -> X 4087 if (N1 == N2) 4088 return N1; 4089 // fold (select true, X, Y) -> X 4090 if (N0C && !N0C->isNullValue()) 4091 return N1; 4092 // fold (select false, X, Y) -> Y 4093 if (N0C && N0C->isNullValue()) 4094 return N2; 4095 // fold (select C, 1, X) -> (or C, X) 4096 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4097 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4098 // fold (select C, 0, 1) -> (xor C, 1) 4099 if (VT.isInteger() && 4100 (VT0 == MVT::i1 || 4101 (VT0.isInteger() && 4102 TLI.getBooleanContents(false) == 4103 TargetLowering::ZeroOrOneBooleanContent)) && 4104 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4105 SDValue XORNode; 4106 if (VT == VT0) 4107 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4108 N0, DAG.getConstant(1, VT0)); 4109 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4110 N0, DAG.getConstant(1, VT0)); 4111 AddToWorkList(XORNode.getNode()); 4112 if (VT.bitsGT(VT0)) 4113 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4114 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4115 } 4116 // fold (select C, 0, X) -> (and (not C), X) 4117 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4118 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4119 AddToWorkList(NOTNode.getNode()); 4120 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4121 } 4122 // fold (select C, X, 1) -> (or (not C), X) 4123 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4124 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4125 AddToWorkList(NOTNode.getNode()); 4126 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4127 } 4128 // fold (select C, X, 0) -> (and C, X) 4129 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4130 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4131 // fold (select X, X, Y) -> (or X, Y) 4132 // fold (select X, 1, Y) -> (or X, Y) 4133 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4134 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4135 // fold (select X, Y, X) -> (and X, Y) 4136 // fold (select X, Y, 0) -> (and X, Y) 4137 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4138 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4139 4140 // If we can fold this based on the true/false value, do so. 4141 if (SimplifySelectOps(N, N1, N2)) 4142 return SDValue(N, 0); // Don't revisit N. 4143 4144 // fold selects based on a setcc into other things, such as min/max/abs 4145 if (N0.getOpcode() == ISD::SETCC) { 4146 // FIXME: 4147 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4148 // having to say they don't support SELECT_CC on every type the DAG knows 4149 // about, since there is no way to mark an opcode illegal at all value types 4150 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4151 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4152 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4153 N0.getOperand(0), N0.getOperand(1), 4154 N1, N2, N0.getOperand(2)); 4155 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4156 } 4157 4158 return SDValue(); 4159} 4160 4161SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4162 SDValue N0 = N->getOperand(0); 4163 SDValue N1 = N->getOperand(1); 4164 SDValue N2 = N->getOperand(2); 4165 SDValue N3 = N->getOperand(3); 4166 SDValue N4 = N->getOperand(4); 4167 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4168 4169 // fold select_cc lhs, rhs, x, x, cc -> x 4170 if (N2 == N3) 4171 return N2; 4172 4173 // Determine if the condition we're dealing with is constant 4174 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4175 N0, N1, CC, N->getDebugLoc(), false); 4176 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4177 4178 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4179 if (!SCCC->isNullValue()) 4180 return N2; // cond always true -> true val 4181 else 4182 return N3; // cond always false -> false val 4183 } 4184 4185 // Fold to a simpler select_cc 4186 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4187 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4188 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4189 SCC.getOperand(2)); 4190 4191 // If we can fold this based on the true/false value, do so. 4192 if (SimplifySelectOps(N, N2, N3)) 4193 return SDValue(N, 0); // Don't revisit N. 4194 4195 // fold select_cc into other things, such as min/max/abs 4196 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4197} 4198 4199SDValue DAGCombiner::visitSETCC(SDNode *N) { 4200 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4201 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4202 N->getDebugLoc()); 4203} 4204 4205// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4206// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4207// transformation. Returns true if extension are possible and the above 4208// mentioned transformation is profitable. 4209static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4210 unsigned ExtOpc, 4211 SmallVector<SDNode*, 4> &ExtendNodes, 4212 const TargetLowering &TLI) { 4213 bool HasCopyToRegUses = false; 4214 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4215 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4216 UE = N0.getNode()->use_end(); 4217 UI != UE; ++UI) { 4218 SDNode *User = *UI; 4219 if (User == N) 4220 continue; 4221 if (UI.getUse().getResNo() != N0.getResNo()) 4222 continue; 4223 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4224 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4225 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4226 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4227 // Sign bits will be lost after a zext. 4228 return false; 4229 bool Add = false; 4230 for (unsigned i = 0; i != 2; ++i) { 4231 SDValue UseOp = User->getOperand(i); 4232 if (UseOp == N0) 4233 continue; 4234 if (!isa<ConstantSDNode>(UseOp)) 4235 return false; 4236 Add = true; 4237 } 4238 if (Add) 4239 ExtendNodes.push_back(User); 4240 continue; 4241 } 4242 // If truncates aren't free and there are users we can't 4243 // extend, it isn't worthwhile. 4244 if (!isTruncFree) 4245 return false; 4246 // Remember if this value is live-out. 4247 if (User->getOpcode() == ISD::CopyToReg) 4248 HasCopyToRegUses = true; 4249 } 4250 4251 if (HasCopyToRegUses) { 4252 bool BothLiveOut = false; 4253 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4254 UI != UE; ++UI) { 4255 SDUse &Use = UI.getUse(); 4256 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4257 BothLiveOut = true; 4258 break; 4259 } 4260 } 4261 if (BothLiveOut) 4262 // Both unextended and extended values are live out. There had better be 4263 // a good reason for the transformation. 4264 return ExtendNodes.size(); 4265 } 4266 return true; 4267} 4268 4269void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4270 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4271 ISD::NodeType ExtType) { 4272 // Extend SetCC uses if necessary. 4273 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4274 SDNode *SetCC = SetCCs[i]; 4275 SmallVector<SDValue, 4> Ops; 4276 4277 for (unsigned j = 0; j != 2; ++j) { 4278 SDValue SOp = SetCC->getOperand(j); 4279 if (SOp == Trunc) 4280 Ops.push_back(ExtLoad); 4281 else 4282 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4283 } 4284 4285 Ops.push_back(SetCC->getOperand(2)); 4286 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4287 &Ops[0], Ops.size())); 4288 } 4289} 4290 4291SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4292 SDValue N0 = N->getOperand(0); 4293 EVT VT = N->getValueType(0); 4294 4295 // fold (sext c1) -> c1 4296 if (isa<ConstantSDNode>(N0)) 4297 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4298 4299 // fold (sext (sext x)) -> (sext x) 4300 // fold (sext (aext x)) -> (sext x) 4301 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4302 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4303 N0.getOperand(0)); 4304 4305 if (N0.getOpcode() == ISD::TRUNCATE) { 4306 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4307 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4308 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4309 if (NarrowLoad.getNode()) { 4310 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4311 if (NarrowLoad.getNode() != N0.getNode()) { 4312 CombineTo(N0.getNode(), NarrowLoad); 4313 // CombineTo deleted the truncate, if needed, but not what's under it. 4314 AddToWorkList(oye); 4315 } 4316 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4317 } 4318 4319 // See if the value being truncated is already sign extended. If so, just 4320 // eliminate the trunc/sext pair. 4321 SDValue Op = N0.getOperand(0); 4322 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4323 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4324 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4325 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4326 4327 if (OpBits == DestBits) { 4328 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4329 // bits, it is already ready. 4330 if (NumSignBits > DestBits-MidBits) 4331 return Op; 4332 } else if (OpBits < DestBits) { 4333 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4334 // bits, just sext from i32. 4335 if (NumSignBits > OpBits-MidBits) 4336 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4337 } else { 4338 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4339 // bits, just truncate to i32. 4340 if (NumSignBits > OpBits-MidBits) 4341 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4342 } 4343 4344 // fold (sext (truncate x)) -> (sextinreg x). 4345 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4346 N0.getValueType())) { 4347 if (OpBits < DestBits) 4348 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4349 else if (OpBits > DestBits) 4350 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4351 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4352 DAG.getValueType(N0.getValueType())); 4353 } 4354 } 4355 4356 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4357 // None of the supported targets knows how to perform load and sign extend 4358 // on vectors in one instruction. We only perform this transformation on 4359 // scalars. 4360 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4361 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4362 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4363 bool DoXform = true; 4364 SmallVector<SDNode*, 4> SetCCs; 4365 if (!N0.hasOneUse()) 4366 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4367 if (DoXform) { 4368 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4369 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4370 LN0->getChain(), 4371 LN0->getBasePtr(), LN0->getPointerInfo(), 4372 N0.getValueType(), 4373 LN0->isVolatile(), LN0->isNonTemporal(), 4374 LN0->getAlignment()); 4375 CombineTo(N, ExtLoad); 4376 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4377 N0.getValueType(), ExtLoad); 4378 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4379 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4380 ISD::SIGN_EXTEND); 4381 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4382 } 4383 } 4384 4385 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4386 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4387 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4388 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4389 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4390 EVT MemVT = LN0->getMemoryVT(); 4391 if ((!LegalOperations && !LN0->isVolatile()) || 4392 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4393 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4394 LN0->getChain(), 4395 LN0->getBasePtr(), LN0->getPointerInfo(), 4396 MemVT, 4397 LN0->isVolatile(), LN0->isNonTemporal(), 4398 LN0->getAlignment()); 4399 CombineTo(N, ExtLoad); 4400 CombineTo(N0.getNode(), 4401 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4402 N0.getValueType(), ExtLoad), 4403 ExtLoad.getValue(1)); 4404 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4405 } 4406 } 4407 4408 // fold (sext (and/or/xor (load x), cst)) -> 4409 // (and/or/xor (sextload x), (sext cst)) 4410 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4411 N0.getOpcode() == ISD::XOR) && 4412 isa<LoadSDNode>(N0.getOperand(0)) && 4413 N0.getOperand(1).getOpcode() == ISD::Constant && 4414 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4415 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4416 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4417 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4418 bool DoXform = true; 4419 SmallVector<SDNode*, 4> SetCCs; 4420 if (!N0.hasOneUse()) 4421 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4422 SetCCs, TLI); 4423 if (DoXform) { 4424 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4425 LN0->getChain(), LN0->getBasePtr(), 4426 LN0->getPointerInfo(), 4427 LN0->getMemoryVT(), 4428 LN0->isVolatile(), 4429 LN0->isNonTemporal(), 4430 LN0->getAlignment()); 4431 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4432 Mask = Mask.sext(VT.getSizeInBits()); 4433 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4434 ExtLoad, DAG.getConstant(Mask, VT)); 4435 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4436 N0.getOperand(0).getDebugLoc(), 4437 N0.getOperand(0).getValueType(), ExtLoad); 4438 CombineTo(N, And); 4439 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4440 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4441 ISD::SIGN_EXTEND); 4442 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4443 } 4444 } 4445 } 4446 4447 if (N0.getOpcode() == ISD::SETCC) { 4448 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4449 // Only do this before legalize for now. 4450 if (VT.isVector() && !LegalOperations) { 4451 EVT N0VT = N0.getOperand(0).getValueType(); 4452 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4453 // of the same size as the compared operands. Only optimize sext(setcc()) 4454 // if this is the case. 4455 EVT SVT = TLI.getSetCCResultType(N0VT); 4456 4457 // We know that the # elements of the results is the same as the 4458 // # elements of the compare (and the # elements of the compare result 4459 // for that matter). Check to see that they are the same size. If so, 4460 // we know that the element size of the sext'd result matches the 4461 // element size of the compare operands. 4462 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4463 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4464 N0.getOperand(1), 4465 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4466 // If the desired elements are smaller or larger than the source 4467 // elements we can use a matching integer vector type and then 4468 // truncate/sign extend 4469 EVT MatchingElementType = 4470 EVT::getIntegerVT(*DAG.getContext(), 4471 N0VT.getScalarType().getSizeInBits()); 4472 EVT MatchingVectorType = 4473 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4474 N0VT.getVectorNumElements()); 4475 4476 if (SVT == MatchingVectorType) { 4477 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4478 N0.getOperand(0), N0.getOperand(1), 4479 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4480 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4481 } 4482 } 4483 4484 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4485 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4486 SDValue NegOne = 4487 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4488 SDValue SCC = 4489 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4490 NegOne, DAG.getConstant(0, VT), 4491 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4492 if (SCC.getNode()) return SCC; 4493 if (!LegalOperations || 4494 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4495 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4496 DAG.getSetCC(N->getDebugLoc(), 4497 TLI.getSetCCResultType(VT), 4498 N0.getOperand(0), N0.getOperand(1), 4499 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4500 NegOne, DAG.getConstant(0, VT)); 4501 } 4502 4503 // fold (sext x) -> (zext x) if the sign bit is known zero. 4504 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4505 DAG.SignBitIsZero(N0)) 4506 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4507 4508 return SDValue(); 4509} 4510 4511// isTruncateOf - If N is a truncate of some other value, return true, record 4512// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4513// This function computes KnownZero to avoid a duplicated call to 4514// ComputeMaskedBits in the caller. 4515static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4516 APInt &KnownZero) { 4517 APInt KnownOne; 4518 if (N->getOpcode() == ISD::TRUNCATE) { 4519 Op = N->getOperand(0); 4520 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4521 return true; 4522 } 4523 4524 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4525 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4526 return false; 4527 4528 SDValue Op0 = N->getOperand(0); 4529 SDValue Op1 = N->getOperand(1); 4530 assert(Op0.getValueType() == Op1.getValueType()); 4531 4532 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4533 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4534 if (COp0 && COp0->isNullValue()) 4535 Op = Op1; 4536 else if (COp1 && COp1->isNullValue()) 4537 Op = Op0; 4538 else 4539 return false; 4540 4541 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4542 4543 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4544 return false; 4545 4546 return true; 4547} 4548 4549SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4550 SDValue N0 = N->getOperand(0); 4551 EVT VT = N->getValueType(0); 4552 4553 // fold (zext c1) -> c1 4554 if (isa<ConstantSDNode>(N0)) 4555 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4556 // fold (zext (zext x)) -> (zext x) 4557 // fold (zext (aext x)) -> (zext x) 4558 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4559 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4560 N0.getOperand(0)); 4561 4562 // fold (zext (truncate x)) -> (zext x) or 4563 // (zext (truncate x)) -> (truncate x) 4564 // This is valid when the truncated bits of x are already zero. 4565 // FIXME: We should extend this to work for vectors too. 4566 SDValue Op; 4567 APInt KnownZero; 4568 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4569 APInt TruncatedBits = 4570 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4571 APInt(Op.getValueSizeInBits(), 0) : 4572 APInt::getBitsSet(Op.getValueSizeInBits(), 4573 N0.getValueSizeInBits(), 4574 std::min(Op.getValueSizeInBits(), 4575 VT.getSizeInBits())); 4576 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4577 if (VT.bitsGT(Op.getValueType())) 4578 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4579 if (VT.bitsLT(Op.getValueType())) 4580 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4581 4582 return Op; 4583 } 4584 } 4585 4586 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4587 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4588 if (N0.getOpcode() == ISD::TRUNCATE) { 4589 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4590 if (NarrowLoad.getNode()) { 4591 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4592 if (NarrowLoad.getNode() != N0.getNode()) { 4593 CombineTo(N0.getNode(), NarrowLoad); 4594 // CombineTo deleted the truncate, if needed, but not what's under it. 4595 AddToWorkList(oye); 4596 } 4597 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4598 } 4599 } 4600 4601 // fold (zext (truncate x)) -> (and x, mask) 4602 if (N0.getOpcode() == ISD::TRUNCATE && 4603 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4604 4605 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4606 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4607 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4608 if (NarrowLoad.getNode()) { 4609 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4610 if (NarrowLoad.getNode() != N0.getNode()) { 4611 CombineTo(N0.getNode(), NarrowLoad); 4612 // CombineTo deleted the truncate, if needed, but not what's under it. 4613 AddToWorkList(oye); 4614 } 4615 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4616 } 4617 4618 SDValue Op = N0.getOperand(0); 4619 if (Op.getValueType().bitsLT(VT)) { 4620 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4621 AddToWorkList(Op.getNode()); 4622 } else if (Op.getValueType().bitsGT(VT)) { 4623 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4624 AddToWorkList(Op.getNode()); 4625 } 4626 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4627 N0.getValueType().getScalarType()); 4628 } 4629 4630 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4631 // if either of the casts is not free. 4632 if (N0.getOpcode() == ISD::AND && 4633 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4634 N0.getOperand(1).getOpcode() == ISD::Constant && 4635 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4636 N0.getValueType()) || 4637 !TLI.isZExtFree(N0.getValueType(), VT))) { 4638 SDValue X = N0.getOperand(0).getOperand(0); 4639 if (X.getValueType().bitsLT(VT)) { 4640 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4641 } else if (X.getValueType().bitsGT(VT)) { 4642 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4643 } 4644 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4645 Mask = Mask.zext(VT.getSizeInBits()); 4646 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4647 X, DAG.getConstant(Mask, VT)); 4648 } 4649 4650 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4651 // None of the supported targets knows how to perform load and vector_zext 4652 // on vectors in one instruction. We only perform this transformation on 4653 // scalars. 4654 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4655 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4656 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4657 bool DoXform = true; 4658 SmallVector<SDNode*, 4> SetCCs; 4659 if (!N0.hasOneUse()) 4660 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4661 if (DoXform) { 4662 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4663 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4664 LN0->getChain(), 4665 LN0->getBasePtr(), LN0->getPointerInfo(), 4666 N0.getValueType(), 4667 LN0->isVolatile(), LN0->isNonTemporal(), 4668 LN0->getAlignment()); 4669 CombineTo(N, ExtLoad); 4670 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4671 N0.getValueType(), ExtLoad); 4672 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4673 4674 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4675 ISD::ZERO_EXTEND); 4676 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4677 } 4678 } 4679 4680 // fold (zext (and/or/xor (load x), cst)) -> 4681 // (and/or/xor (zextload x), (zext cst)) 4682 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4683 N0.getOpcode() == ISD::XOR) && 4684 isa<LoadSDNode>(N0.getOperand(0)) && 4685 N0.getOperand(1).getOpcode() == ISD::Constant && 4686 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4687 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4688 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4689 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4690 bool DoXform = true; 4691 SmallVector<SDNode*, 4> SetCCs; 4692 if (!N0.hasOneUse()) 4693 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4694 SetCCs, TLI); 4695 if (DoXform) { 4696 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4697 LN0->getChain(), LN0->getBasePtr(), 4698 LN0->getPointerInfo(), 4699 LN0->getMemoryVT(), 4700 LN0->isVolatile(), 4701 LN0->isNonTemporal(), 4702 LN0->getAlignment()); 4703 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4704 Mask = Mask.zext(VT.getSizeInBits()); 4705 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4706 ExtLoad, DAG.getConstant(Mask, VT)); 4707 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4708 N0.getOperand(0).getDebugLoc(), 4709 N0.getOperand(0).getValueType(), ExtLoad); 4710 CombineTo(N, And); 4711 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4712 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4713 ISD::ZERO_EXTEND); 4714 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4715 } 4716 } 4717 } 4718 4719 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4720 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4721 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4722 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4723 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4724 EVT MemVT = LN0->getMemoryVT(); 4725 if ((!LegalOperations && !LN0->isVolatile()) || 4726 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4727 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4728 LN0->getChain(), 4729 LN0->getBasePtr(), LN0->getPointerInfo(), 4730 MemVT, 4731 LN0->isVolatile(), LN0->isNonTemporal(), 4732 LN0->getAlignment()); 4733 CombineTo(N, ExtLoad); 4734 CombineTo(N0.getNode(), 4735 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4736 ExtLoad), 4737 ExtLoad.getValue(1)); 4738 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4739 } 4740 } 4741 4742 if (N0.getOpcode() == ISD::SETCC) { 4743 if (!LegalOperations && VT.isVector()) { 4744 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4745 // Only do this before legalize for now. 4746 EVT N0VT = N0.getOperand(0).getValueType(); 4747 EVT EltVT = VT.getVectorElementType(); 4748 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4749 DAG.getConstant(1, EltVT)); 4750 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4751 // We know that the # elements of the results is the same as the 4752 // # elements of the compare (and the # elements of the compare result 4753 // for that matter). Check to see that they are the same size. If so, 4754 // we know that the element size of the sext'd result matches the 4755 // element size of the compare operands. 4756 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4757 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4758 N0.getOperand(1), 4759 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4760 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4761 &OneOps[0], OneOps.size())); 4762 4763 // If the desired elements are smaller or larger than the source 4764 // elements we can use a matching integer vector type and then 4765 // truncate/sign extend 4766 EVT MatchingElementType = 4767 EVT::getIntegerVT(*DAG.getContext(), 4768 N0VT.getScalarType().getSizeInBits()); 4769 EVT MatchingVectorType = 4770 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4771 N0VT.getVectorNumElements()); 4772 SDValue VsetCC = 4773 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4774 N0.getOperand(1), 4775 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4776 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4777 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4778 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4779 &OneOps[0], OneOps.size())); 4780 } 4781 4782 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4783 SDValue SCC = 4784 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4785 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4786 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4787 if (SCC.getNode()) return SCC; 4788 } 4789 4790 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4791 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4792 isa<ConstantSDNode>(N0.getOperand(1)) && 4793 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4794 N0.hasOneUse()) { 4795 SDValue ShAmt = N0.getOperand(1); 4796 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4797 if (N0.getOpcode() == ISD::SHL) { 4798 SDValue InnerZExt = N0.getOperand(0); 4799 // If the original shl may be shifting out bits, do not perform this 4800 // transformation. 4801 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4802 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4803 if (ShAmtVal > KnownZeroBits) 4804 return SDValue(); 4805 } 4806 4807 DebugLoc DL = N->getDebugLoc(); 4808 4809 // Ensure that the shift amount is wide enough for the shifted value. 4810 if (VT.getSizeInBits() >= 256) 4811 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4812 4813 return DAG.getNode(N0.getOpcode(), DL, VT, 4814 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4815 ShAmt); 4816 } 4817 4818 return SDValue(); 4819} 4820 4821SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4822 SDValue N0 = N->getOperand(0); 4823 EVT VT = N->getValueType(0); 4824 4825 // fold (aext c1) -> c1 4826 if (isa<ConstantSDNode>(N0)) 4827 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4828 // fold (aext (aext x)) -> (aext x) 4829 // fold (aext (zext x)) -> (zext x) 4830 // fold (aext (sext x)) -> (sext x) 4831 if (N0.getOpcode() == ISD::ANY_EXTEND || 4832 N0.getOpcode() == ISD::ZERO_EXTEND || 4833 N0.getOpcode() == ISD::SIGN_EXTEND) 4834 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4835 4836 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4837 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4838 if (N0.getOpcode() == ISD::TRUNCATE) { 4839 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4840 if (NarrowLoad.getNode()) { 4841 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4842 if (NarrowLoad.getNode() != N0.getNode()) { 4843 CombineTo(N0.getNode(), NarrowLoad); 4844 // CombineTo deleted the truncate, if needed, but not what's under it. 4845 AddToWorkList(oye); 4846 } 4847 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4848 } 4849 } 4850 4851 // fold (aext (truncate x)) 4852 if (N0.getOpcode() == ISD::TRUNCATE) { 4853 SDValue TruncOp = N0.getOperand(0); 4854 if (TruncOp.getValueType() == VT) 4855 return TruncOp; // x iff x size == zext size. 4856 if (TruncOp.getValueType().bitsGT(VT)) 4857 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4858 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4859 } 4860 4861 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4862 // if the trunc is not free. 4863 if (N0.getOpcode() == ISD::AND && 4864 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4865 N0.getOperand(1).getOpcode() == ISD::Constant && 4866 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4867 N0.getValueType())) { 4868 SDValue X = N0.getOperand(0).getOperand(0); 4869 if (X.getValueType().bitsLT(VT)) { 4870 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4871 } else if (X.getValueType().bitsGT(VT)) { 4872 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4873 } 4874 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4875 Mask = Mask.zext(VT.getSizeInBits()); 4876 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4877 X, DAG.getConstant(Mask, VT)); 4878 } 4879 4880 // fold (aext (load x)) -> (aext (truncate (extload x))) 4881 // None of the supported targets knows how to perform load and any_ext 4882 // on vectors in one instruction. We only perform this transformation on 4883 // scalars. 4884 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4885 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4886 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4887 bool DoXform = true; 4888 SmallVector<SDNode*, 4> SetCCs; 4889 if (!N0.hasOneUse()) 4890 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4891 if (DoXform) { 4892 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4893 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4894 LN0->getChain(), 4895 LN0->getBasePtr(), LN0->getPointerInfo(), 4896 N0.getValueType(), 4897 LN0->isVolatile(), LN0->isNonTemporal(), 4898 LN0->getAlignment()); 4899 CombineTo(N, ExtLoad); 4900 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4901 N0.getValueType(), ExtLoad); 4902 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4903 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4904 ISD::ANY_EXTEND); 4905 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4906 } 4907 } 4908 4909 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4910 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4911 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4912 if (N0.getOpcode() == ISD::LOAD && 4913 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4914 N0.hasOneUse()) { 4915 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4916 EVT MemVT = LN0->getMemoryVT(); 4917 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4918 VT, LN0->getChain(), LN0->getBasePtr(), 4919 LN0->getPointerInfo(), MemVT, 4920 LN0->isVolatile(), LN0->isNonTemporal(), 4921 LN0->getAlignment()); 4922 CombineTo(N, ExtLoad); 4923 CombineTo(N0.getNode(), 4924 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4925 N0.getValueType(), ExtLoad), 4926 ExtLoad.getValue(1)); 4927 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4928 } 4929 4930 if (N0.getOpcode() == ISD::SETCC) { 4931 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4932 // Only do this before legalize for now. 4933 if (VT.isVector() && !LegalOperations) { 4934 EVT N0VT = N0.getOperand(0).getValueType(); 4935 // We know that the # elements of the results is the same as the 4936 // # elements of the compare (and the # elements of the compare result 4937 // for that matter). Check to see that they are the same size. If so, 4938 // we know that the element size of the sext'd result matches the 4939 // element size of the compare operands. 4940 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4941 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4942 N0.getOperand(1), 4943 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4944 // If the desired elements are smaller or larger than the source 4945 // elements we can use a matching integer vector type and then 4946 // truncate/sign extend 4947 else { 4948 EVT MatchingElementType = 4949 EVT::getIntegerVT(*DAG.getContext(), 4950 N0VT.getScalarType().getSizeInBits()); 4951 EVT MatchingVectorType = 4952 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4953 N0VT.getVectorNumElements()); 4954 SDValue VsetCC = 4955 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4956 N0.getOperand(1), 4957 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4958 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4959 } 4960 } 4961 4962 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4963 SDValue SCC = 4964 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4965 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4966 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4967 if (SCC.getNode()) 4968 return SCC; 4969 } 4970 4971 return SDValue(); 4972} 4973 4974/// GetDemandedBits - See if the specified operand can be simplified with the 4975/// knowledge that only the bits specified by Mask are used. If so, return the 4976/// simpler operand, otherwise return a null SDValue. 4977SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4978 switch (V.getOpcode()) { 4979 default: break; 4980 case ISD::Constant: { 4981 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4982 assert(CV != 0 && "Const value should be ConstSDNode."); 4983 const APInt &CVal = CV->getAPIntValue(); 4984 APInt NewVal = CVal & Mask; 4985 if (NewVal != CVal) { 4986 return DAG.getConstant(NewVal, V.getValueType()); 4987 } 4988 break; 4989 } 4990 case ISD::OR: 4991 case ISD::XOR: 4992 // If the LHS or RHS don't contribute bits to the or, drop them. 4993 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4994 return V.getOperand(1); 4995 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4996 return V.getOperand(0); 4997 break; 4998 case ISD::SRL: 4999 // Only look at single-use SRLs. 5000 if (!V.getNode()->hasOneUse()) 5001 break; 5002 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 5003 // See if we can recursively simplify the LHS. 5004 unsigned Amt = RHSC->getZExtValue(); 5005 5006 // Watch out for shift count overflow though. 5007 if (Amt >= Mask.getBitWidth()) break; 5008 APInt NewMask = Mask << Amt; 5009 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 5010 if (SimplifyLHS.getNode()) 5011 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 5012 SimplifyLHS, V.getOperand(1)); 5013 } 5014 } 5015 return SDValue(); 5016} 5017 5018/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 5019/// bits and then truncated to a narrower type and where N is a multiple 5020/// of number of bits of the narrower type, transform it to a narrower load 5021/// from address + N / num of bits of new type. If the result is to be 5022/// extended, also fold the extension to form a extending load. 5023SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 5024 unsigned Opc = N->getOpcode(); 5025 5026 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 5027 SDValue N0 = N->getOperand(0); 5028 EVT VT = N->getValueType(0); 5029 EVT ExtVT = VT; 5030 5031 // This transformation isn't valid for vector loads. 5032 if (VT.isVector()) 5033 return SDValue(); 5034 5035 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 5036 // extended to VT. 5037 if (Opc == ISD::SIGN_EXTEND_INREG) { 5038 ExtType = ISD::SEXTLOAD; 5039 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5040 } else if (Opc == ISD::SRL) { 5041 // Another special-case: SRL is basically zero-extending a narrower value. 5042 ExtType = ISD::ZEXTLOAD; 5043 N0 = SDValue(N, 0); 5044 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 5045 if (!N01) return SDValue(); 5046 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 5047 VT.getSizeInBits() - N01->getZExtValue()); 5048 } 5049 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5050 return SDValue(); 5051 5052 unsigned EVTBits = ExtVT.getSizeInBits(); 5053 5054 // Do not generate loads of non-round integer types since these can 5055 // be expensive (and would be wrong if the type is not byte sized). 5056 if (!ExtVT.isRound()) 5057 return SDValue(); 5058 5059 unsigned ShAmt = 0; 5060 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5061 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5062 ShAmt = N01->getZExtValue(); 5063 // Is the shift amount a multiple of size of VT? 5064 if ((ShAmt & (EVTBits-1)) == 0) { 5065 N0 = N0.getOperand(0); 5066 // Is the load width a multiple of size of VT? 5067 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5068 return SDValue(); 5069 } 5070 5071 // At this point, we must have a load or else we can't do the transform. 5072 if (!isa<LoadSDNode>(N0)) return SDValue(); 5073 5074 // Because a SRL must be assumed to *need* to zero-extend the high bits 5075 // (as opposed to anyext the high bits), we can't combine the zextload 5076 // lowering of SRL and an sextload. 5077 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD) 5078 return SDValue(); 5079 5080 // If the shift amount is larger than the input type then we're not 5081 // accessing any of the loaded bytes. If the load was a zextload/extload 5082 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5083 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5084 return SDValue(); 5085 } 5086 } 5087 5088 // If the load is shifted left (and the result isn't shifted back right), 5089 // we can fold the truncate through the shift. 5090 unsigned ShLeftAmt = 0; 5091 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5092 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5093 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5094 ShLeftAmt = N01->getZExtValue(); 5095 N0 = N0.getOperand(0); 5096 } 5097 } 5098 5099 // If we haven't found a load, we can't narrow it. Don't transform one with 5100 // multiple uses, this would require adding a new load. 5101 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 5102 // Don't change the width of a volatile load. 5103 cast<LoadSDNode>(N0)->isVolatile()) 5104 return SDValue(); 5105 5106 // Verify that we are actually reducing a load width here. 5107 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 5108 return SDValue(); 5109 5110 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5111 EVT PtrType = N0.getOperand(1).getValueType(); 5112 5113 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5114 // It's not possible to generate a constant of extended or untyped type. 5115 return SDValue(); 5116 5117 // For big endian targets, we need to adjust the offset to the pointer to 5118 // load the correct bytes. 5119 if (TLI.isBigEndian()) { 5120 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5121 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5122 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5123 } 5124 5125 uint64_t PtrOff = ShAmt / 8; 5126 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5127 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5128 PtrType, LN0->getBasePtr(), 5129 DAG.getConstant(PtrOff, PtrType)); 5130 AddToWorkList(NewPtr.getNode()); 5131 5132 SDValue Load; 5133 if (ExtType == ISD::NON_EXTLOAD) 5134 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5135 LN0->getPointerInfo().getWithOffset(PtrOff), 5136 LN0->isVolatile(), LN0->isNonTemporal(), 5137 LN0->isInvariant(), NewAlign); 5138 else 5139 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5140 LN0->getPointerInfo().getWithOffset(PtrOff), 5141 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5142 NewAlign); 5143 5144 // Replace the old load's chain with the new load's chain. 5145 WorkListRemover DeadNodes(*this); 5146 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5147 5148 // Shift the result left, if we've swallowed a left shift. 5149 SDValue Result = Load; 5150 if (ShLeftAmt != 0) { 5151 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5152 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5153 ShImmTy = VT; 5154 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5155 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5156 } 5157 5158 // Return the new loaded value. 5159 return Result; 5160} 5161 5162SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5163 SDValue N0 = N->getOperand(0); 5164 SDValue N1 = N->getOperand(1); 5165 EVT VT = N->getValueType(0); 5166 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5167 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5168 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5169 5170 // fold (sext_in_reg c1) -> c1 5171 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5172 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5173 5174 // If the input is already sign extended, just drop the extension. 5175 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5176 return N0; 5177 5178 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5179 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5180 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5181 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5182 N0.getOperand(0), N1); 5183 } 5184 5185 // fold (sext_in_reg (sext x)) -> (sext x) 5186 // fold (sext_in_reg (aext x)) -> (sext x) 5187 // if x is small enough. 5188 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5189 SDValue N00 = N0.getOperand(0); 5190 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5191 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5192 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5193 } 5194 5195 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5196 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5197 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5198 5199 // fold operands of sext_in_reg based on knowledge that the top bits are not 5200 // demanded. 5201 if (SimplifyDemandedBits(SDValue(N, 0))) 5202 return SDValue(N, 0); 5203 5204 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5205 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5206 SDValue NarrowLoad = ReduceLoadWidth(N); 5207 if (NarrowLoad.getNode()) 5208 return NarrowLoad; 5209 5210 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5211 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5212 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5213 if (N0.getOpcode() == ISD::SRL) { 5214 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5215 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5216 // We can turn this into an SRA iff the input to the SRL is already sign 5217 // extended enough. 5218 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5219 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5220 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5221 N0.getOperand(0), N0.getOperand(1)); 5222 } 5223 } 5224 5225 // fold (sext_inreg (extload x)) -> (sextload x) 5226 if (ISD::isEXTLoad(N0.getNode()) && 5227 ISD::isUNINDEXEDLoad(N0.getNode()) && 5228 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5229 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5230 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5231 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5232 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5233 LN0->getChain(), 5234 LN0->getBasePtr(), LN0->getPointerInfo(), 5235 EVT, 5236 LN0->isVolatile(), LN0->isNonTemporal(), 5237 LN0->getAlignment()); 5238 CombineTo(N, ExtLoad); 5239 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5240 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5241 } 5242 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5243 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5244 N0.hasOneUse() && 5245 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5246 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5247 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5248 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5249 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5250 LN0->getChain(), 5251 LN0->getBasePtr(), LN0->getPointerInfo(), 5252 EVT, 5253 LN0->isVolatile(), LN0->isNonTemporal(), 5254 LN0->getAlignment()); 5255 CombineTo(N, ExtLoad); 5256 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5257 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5258 } 5259 5260 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5261 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5262 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5263 N0.getOperand(1), false); 5264 if (BSwap.getNode() != 0) 5265 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5266 BSwap, N1); 5267 } 5268 5269 return SDValue(); 5270} 5271 5272SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5273 SDValue N0 = N->getOperand(0); 5274 EVT VT = N->getValueType(0); 5275 bool isLE = TLI.isLittleEndian(); 5276 5277 // noop truncate 5278 if (N0.getValueType() == N->getValueType(0)) 5279 return N0; 5280 // fold (truncate c1) -> c1 5281 if (isa<ConstantSDNode>(N0)) 5282 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5283 // fold (truncate (truncate x)) -> (truncate x) 5284 if (N0.getOpcode() == ISD::TRUNCATE) 5285 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5286 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5287 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5288 N0.getOpcode() == ISD::SIGN_EXTEND || 5289 N0.getOpcode() == ISD::ANY_EXTEND) { 5290 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5291 // if the source is smaller than the dest, we still need an extend 5292 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5293 N0.getOperand(0)); 5294 if (N0.getOperand(0).getValueType().bitsGT(VT)) 5295 // if the source is larger than the dest, than we just need the truncate 5296 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5297 // if the source and dest are the same type, we can drop both the extend 5298 // and the truncate. 5299 return N0.getOperand(0); 5300 } 5301 5302 // Fold extract-and-trunc into a narrow extract. For example: 5303 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5304 // i32 y = TRUNCATE(i64 x) 5305 // -- becomes -- 5306 // v16i8 b = BITCAST (v2i64 val) 5307 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5308 // 5309 // Note: We only run this optimization after type legalization (which often 5310 // creates this pattern) and before operation legalization after which 5311 // we need to be more careful about the vector instructions that we generate. 5312 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5313 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5314 5315 EVT VecTy = N0.getOperand(0).getValueType(); 5316 EVT ExTy = N0.getValueType(); 5317 EVT TrTy = N->getValueType(0); 5318 5319 unsigned NumElem = VecTy.getVectorNumElements(); 5320 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5321 5322 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5323 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5324 5325 SDValue EltNo = N0->getOperand(1); 5326 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5327 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5328 EVT IndexTy = N0->getOperand(1).getValueType(); 5329 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5330 5331 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5332 NVT, N0.getOperand(0)); 5333 5334 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5335 N->getDebugLoc(), TrTy, V, 5336 DAG.getConstant(Index, IndexTy)); 5337 } 5338 } 5339 5340 // See if we can simplify the input to this truncate through knowledge that 5341 // only the low bits are being used. 5342 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5343 // Currently we only perform this optimization on scalars because vectors 5344 // may have different active low bits. 5345 if (!VT.isVector()) { 5346 SDValue Shorter = 5347 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5348 VT.getSizeInBits())); 5349 if (Shorter.getNode()) 5350 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5351 } 5352 // fold (truncate (load x)) -> (smaller load x) 5353 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5354 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5355 SDValue Reduced = ReduceLoadWidth(N); 5356 if (Reduced.getNode()) 5357 return Reduced; 5358 } 5359 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)), 5360 // where ... are all 'undef'. 5361 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { 5362 SmallVector<EVT, 8> VTs; 5363 SDValue V; 5364 unsigned Idx = 0; 5365 unsigned NumDefs = 0; 5366 5367 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 5368 SDValue X = N0.getOperand(i); 5369 if (X.getOpcode() != ISD::UNDEF) { 5370 V = X; 5371 Idx = i; 5372 NumDefs++; 5373 } 5374 // Stop if more than one members are non-undef. 5375 if (NumDefs > 1) 5376 break; 5377 VTs.push_back(EVT::getVectorVT(*DAG.getContext(), 5378 VT.getVectorElementType(), 5379 X.getValueType().getVectorNumElements())); 5380 } 5381 5382 if (NumDefs == 0) 5383 return DAG.getUNDEF(VT); 5384 5385 if (NumDefs == 1) { 5386 assert(V.getNode() && "The single defined operand is empty!"); 5387 SmallVector<SDValue, 8> Opnds; 5388 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 5389 if (i != Idx) { 5390 Opnds.push_back(DAG.getUNDEF(VTs[i])); 5391 continue; 5392 } 5393 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V); 5394 AddToWorkList(NV.getNode()); 5395 Opnds.push_back(NV); 5396 } 5397 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 5398 &Opnds[0], Opnds.size()); 5399 } 5400 } 5401 5402 // Simplify the operands using demanded-bits information. 5403 if (!VT.isVector() && 5404 SimplifyDemandedBits(SDValue(N, 0))) 5405 return SDValue(N, 0); 5406 5407 return SDValue(); 5408} 5409 5410static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5411 SDValue Elt = N->getOperand(i); 5412 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5413 return Elt.getNode(); 5414 return Elt.getOperand(Elt.getResNo()).getNode(); 5415} 5416 5417/// CombineConsecutiveLoads - build_pair (load, load) -> load 5418/// if load locations are consecutive. 5419SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5420 assert(N->getOpcode() == ISD::BUILD_PAIR); 5421 5422 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5423 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5424 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5425 LD1->getPointerInfo().getAddrSpace() != 5426 LD2->getPointerInfo().getAddrSpace()) 5427 return SDValue(); 5428 EVT LD1VT = LD1->getValueType(0); 5429 5430 if (ISD::isNON_EXTLoad(LD2) && 5431 LD2->hasOneUse() && 5432 // If both are volatile this would reduce the number of volatile loads. 5433 // If one is volatile it might be ok, but play conservative and bail out. 5434 !LD1->isVolatile() && 5435 !LD2->isVolatile() && 5436 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5437 unsigned Align = LD1->getAlignment(); 5438 unsigned NewAlign = TLI.getDataLayout()-> 5439 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5440 5441 if (NewAlign <= Align && 5442 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5443 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5444 LD1->getBasePtr(), LD1->getPointerInfo(), 5445 false, false, false, Align); 5446 } 5447 5448 return SDValue(); 5449} 5450 5451SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5452 SDValue N0 = N->getOperand(0); 5453 EVT VT = N->getValueType(0); 5454 5455 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5456 // Only do this before legalize, since afterward the target may be depending 5457 // on the bitconvert. 5458 // First check to see if this is all constant. 5459 if (!LegalTypes && 5460 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5461 VT.isVector()) { 5462 bool isSimple = true; 5463 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5464 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5465 N0.getOperand(i).getOpcode() != ISD::Constant && 5466 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5467 isSimple = false; 5468 break; 5469 } 5470 5471 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5472 assert(!DestEltVT.isVector() && 5473 "Element type of vector ValueType must not be vector!"); 5474 if (isSimple) 5475 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5476 } 5477 5478 // If the input is a constant, let getNode fold it. 5479 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5480 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5481 if (Res.getNode() != N) { 5482 if (!LegalOperations || 5483 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5484 return Res; 5485 5486 // Folding it resulted in an illegal node, and it's too late to 5487 // do that. Clean up the old node and forego the transformation. 5488 // Ideally this won't happen very often, because instcombine 5489 // and the earlier dagcombine runs (where illegal nodes are 5490 // permitted) should have folded most of them already. 5491 DAG.DeleteNode(Res.getNode()); 5492 } 5493 } 5494 5495 // (conv (conv x, t1), t2) -> (conv x, t2) 5496 if (N0.getOpcode() == ISD::BITCAST) 5497 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5498 N0.getOperand(0)); 5499 5500 // fold (conv (load x)) -> (load (conv*)x) 5501 // If the resultant load doesn't need a higher alignment than the original! 5502 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5503 // Do not change the width of a volatile load. 5504 !cast<LoadSDNode>(N0)->isVolatile() && 5505 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5506 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5507 unsigned Align = TLI.getDataLayout()-> 5508 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5509 unsigned OrigAlign = LN0->getAlignment(); 5510 5511 if (Align <= OrigAlign) { 5512 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5513 LN0->getBasePtr(), LN0->getPointerInfo(), 5514 LN0->isVolatile(), LN0->isNonTemporal(), 5515 LN0->isInvariant(), OrigAlign); 5516 AddToWorkList(N); 5517 CombineTo(N0.getNode(), 5518 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5519 N0.getValueType(), Load), 5520 Load.getValue(1)); 5521 return Load; 5522 } 5523 } 5524 5525 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5526 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5527 // This often reduces constant pool loads. 5528 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5529 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5530 N0.getNode()->hasOneUse() && VT.isInteger() && 5531 !VT.isVector() && !N0.getValueType().isVector()) { 5532 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5533 N0.getOperand(0)); 5534 AddToWorkList(NewConv.getNode()); 5535 5536 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5537 if (N0.getOpcode() == ISD::FNEG) 5538 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5539 NewConv, DAG.getConstant(SignBit, VT)); 5540 assert(N0.getOpcode() == ISD::FABS); 5541 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5542 NewConv, DAG.getConstant(~SignBit, VT)); 5543 } 5544 5545 // fold (bitconvert (fcopysign cst, x)) -> 5546 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5547 // Note that we don't handle (copysign x, cst) because this can always be 5548 // folded to an fneg or fabs. 5549 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5550 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5551 VT.isInteger() && !VT.isVector()) { 5552 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5553 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5554 if (isTypeLegal(IntXVT)) { 5555 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5556 IntXVT, N0.getOperand(1)); 5557 AddToWorkList(X.getNode()); 5558 5559 // If X has a different width than the result/lhs, sext it or truncate it. 5560 unsigned VTWidth = VT.getSizeInBits(); 5561 if (OrigXWidth < VTWidth) { 5562 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5563 AddToWorkList(X.getNode()); 5564 } else if (OrigXWidth > VTWidth) { 5565 // To get the sign bit in the right place, we have to shift it right 5566 // before truncating. 5567 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5568 X.getValueType(), X, 5569 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5570 AddToWorkList(X.getNode()); 5571 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5572 AddToWorkList(X.getNode()); 5573 } 5574 5575 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5576 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5577 X, DAG.getConstant(SignBit, VT)); 5578 AddToWorkList(X.getNode()); 5579 5580 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5581 VT, N0.getOperand(0)); 5582 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5583 Cst, DAG.getConstant(~SignBit, VT)); 5584 AddToWorkList(Cst.getNode()); 5585 5586 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5587 } 5588 } 5589 5590 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5591 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5592 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5593 if (CombineLD.getNode()) 5594 return CombineLD; 5595 } 5596 5597 return SDValue(); 5598} 5599 5600SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5601 EVT VT = N->getValueType(0); 5602 return CombineConsecutiveLoads(N, VT); 5603} 5604 5605/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5606/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5607/// destination element value type. 5608SDValue DAGCombiner:: 5609ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5610 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5611 5612 // If this is already the right type, we're done. 5613 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5614 5615 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5616 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5617 5618 // If this is a conversion of N elements of one type to N elements of another 5619 // type, convert each element. This handles FP<->INT cases. 5620 if (SrcBitSize == DstBitSize) { 5621 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5622 BV->getValueType(0).getVectorNumElements()); 5623 5624 // Due to the FP element handling below calling this routine recursively, 5625 // we can end up with a scalar-to-vector node here. 5626 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5627 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5628 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5629 DstEltVT, BV->getOperand(0))); 5630 5631 SmallVector<SDValue, 8> Ops; 5632 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5633 SDValue Op = BV->getOperand(i); 5634 // If the vector element type is not legal, the BUILD_VECTOR operands 5635 // are promoted and implicitly truncated. Make that explicit here. 5636 if (Op.getValueType() != SrcEltVT) 5637 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5638 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5639 DstEltVT, Op)); 5640 AddToWorkList(Ops.back().getNode()); 5641 } 5642 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5643 &Ops[0], Ops.size()); 5644 } 5645 5646 // Otherwise, we're growing or shrinking the elements. To avoid having to 5647 // handle annoying details of growing/shrinking FP values, we convert them to 5648 // int first. 5649 if (SrcEltVT.isFloatingPoint()) { 5650 // Convert the input float vector to a int vector where the elements are the 5651 // same sizes. 5652 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5653 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5654 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5655 SrcEltVT = IntVT; 5656 } 5657 5658 // Now we know the input is an integer vector. If the output is a FP type, 5659 // convert to integer first, then to FP of the right size. 5660 if (DstEltVT.isFloatingPoint()) { 5661 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5662 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5663 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5664 5665 // Next, convert to FP elements of the same size. 5666 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5667 } 5668 5669 // Okay, we know the src/dst types are both integers of differing types. 5670 // Handling growing first. 5671 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5672 if (SrcBitSize < DstBitSize) { 5673 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5674 5675 SmallVector<SDValue, 8> Ops; 5676 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5677 i += NumInputsPerOutput) { 5678 bool isLE = TLI.isLittleEndian(); 5679 APInt NewBits = APInt(DstBitSize, 0); 5680 bool EltIsUndef = true; 5681 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5682 // Shift the previously computed bits over. 5683 NewBits <<= SrcBitSize; 5684 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5685 if (Op.getOpcode() == ISD::UNDEF) continue; 5686 EltIsUndef = false; 5687 5688 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5689 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5690 } 5691 5692 if (EltIsUndef) 5693 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5694 else 5695 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5696 } 5697 5698 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5699 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5700 &Ops[0], Ops.size()); 5701 } 5702 5703 // Finally, this must be the case where we are shrinking elements: each input 5704 // turns into multiple outputs. 5705 bool isS2V = ISD::isScalarToVector(BV); 5706 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5707 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5708 NumOutputsPerInput*BV->getNumOperands()); 5709 SmallVector<SDValue, 8> Ops; 5710 5711 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5712 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5713 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5714 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5715 continue; 5716 } 5717 5718 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5719 getAPIntValue().zextOrTrunc(SrcBitSize); 5720 5721 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5722 APInt ThisVal = OpVal.trunc(DstBitSize); 5723 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5724 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5725 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5726 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5727 Ops[0]); 5728 OpVal = OpVal.lshr(DstBitSize); 5729 } 5730 5731 // For big endian targets, swap the order of the pieces of each element. 5732 if (TLI.isBigEndian()) 5733 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5734 } 5735 5736 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5737 &Ops[0], Ops.size()); 5738} 5739 5740SDValue DAGCombiner::visitFADD(SDNode *N) { 5741 SDValue N0 = N->getOperand(0); 5742 SDValue N1 = N->getOperand(1); 5743 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5744 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5745 EVT VT = N->getValueType(0); 5746 5747 // fold vector ops 5748 if (VT.isVector()) { 5749 SDValue FoldedVOp = SimplifyVBinOp(N); 5750 if (FoldedVOp.getNode()) return FoldedVOp; 5751 } 5752 5753 // fold (fadd c1, c2) -> c1 + c2 5754 if (N0CFP && N1CFP) 5755 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5756 // canonicalize constant to RHS 5757 if (N0CFP && !N1CFP) 5758 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5759 // fold (fadd A, 0) -> A 5760 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5761 N1CFP->getValueAPF().isZero()) 5762 return N0; 5763 // fold (fadd A, (fneg B)) -> (fsub A, B) 5764 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5765 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5766 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5767 GetNegatedExpression(N1, DAG, LegalOperations)); 5768 // fold (fadd (fneg A), B) -> (fsub B, A) 5769 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5770 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5771 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5772 GetNegatedExpression(N0, DAG, LegalOperations)); 5773 5774 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5775 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5776 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5777 isa<ConstantFPSDNode>(N0.getOperand(1))) 5778 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5779 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5780 N0.getOperand(1), N1)); 5781 5782 // If allow, fold (fadd (fneg x), x) -> 0.0 5783 if (DAG.getTarget().Options.UnsafeFPMath && 5784 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) { 5785 return DAG.getConstantFP(0.0, VT); 5786 } 5787 5788 // If allow, fold (fadd x, (fneg x)) -> 0.0 5789 if (DAG.getTarget().Options.UnsafeFPMath && 5790 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) { 5791 return DAG.getConstantFP(0.0, VT); 5792 } 5793 5794 // In unsafe math mode, we can fold chains of FADD's of the same value 5795 // into multiplications. This transform is not safe in general because 5796 // we are reducing the number of rounding steps. 5797 if (DAG.getTarget().Options.UnsafeFPMath && 5798 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5799 !N0CFP && !N1CFP) { 5800 if (N0.getOpcode() == ISD::FMUL) { 5801 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5802 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 5803 5804 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5805 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 5806 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5807 SDValue(CFP00, 0), 5808 DAG.getConstantFP(1.0, VT)); 5809 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5810 N1, NewCFP); 5811 } 5812 5813 // (fadd (fmul x, c), x) -> (fmul c+1, x) 5814 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 5815 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5816 SDValue(CFP01, 0), 5817 DAG.getConstantFP(1.0, VT)); 5818 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5819 N1, NewCFP); 5820 } 5821 5822 // (fadd (fadd x, x), x) -> (fmul 3.0, x) 5823 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) && 5824 N0.getOperand(0) == N1) { 5825 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5826 N1, DAG.getConstantFP(3.0, VT)); 5827 } 5828 5829 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x) 5830 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 5831 N1.getOperand(0) == N1.getOperand(1) && 5832 N0.getOperand(1) == N1.getOperand(0)) { 5833 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5834 SDValue(CFP00, 0), 5835 DAG.getConstantFP(2.0, VT)); 5836 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5837 N0.getOperand(1), NewCFP); 5838 } 5839 5840 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x) 5841 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 5842 N1.getOperand(0) == N1.getOperand(1) && 5843 N0.getOperand(0) == N1.getOperand(0)) { 5844 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5845 SDValue(CFP01, 0), 5846 DAG.getConstantFP(2.0, VT)); 5847 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5848 N0.getOperand(0), NewCFP); 5849 } 5850 } 5851 5852 if (N1.getOpcode() == ISD::FMUL) { 5853 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5854 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 5855 5856 // (fadd x, (fmul c, x)) -> (fmul c+1, x) 5857 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 5858 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5859 SDValue(CFP10, 0), 5860 DAG.getConstantFP(1.0, VT)); 5861 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5862 N0, NewCFP); 5863 } 5864 5865 // (fadd x, (fmul x, c)) -> (fmul c+1, x) 5866 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 5867 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5868 SDValue(CFP11, 0), 5869 DAG.getConstantFP(1.0, VT)); 5870 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5871 N0, NewCFP); 5872 } 5873 5874 // (fadd x, (fadd x, x)) -> (fmul 3.0, x) 5875 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) && 5876 N1.getOperand(0) == N0) { 5877 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5878 N0, DAG.getConstantFP(3.0, VT)); 5879 } 5880 5881 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x) 5882 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD && 5883 N1.getOperand(0) == N1.getOperand(1) && 5884 N0.getOperand(1) == N1.getOperand(0)) { 5885 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5886 SDValue(CFP10, 0), 5887 DAG.getConstantFP(2.0, VT)); 5888 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5889 N0.getOperand(1), NewCFP); 5890 } 5891 5892 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x) 5893 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD && 5894 N1.getOperand(0) == N1.getOperand(1) && 5895 N0.getOperand(0) == N1.getOperand(0)) { 5896 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5897 SDValue(CFP11, 0), 5898 DAG.getConstantFP(2.0, VT)); 5899 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5900 N0.getOperand(0), NewCFP); 5901 } 5902 } 5903 5904 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x) 5905 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 5906 N0.getOperand(0) == N0.getOperand(1) && 5907 N1.getOperand(0) == N1.getOperand(1) && 5908 N0.getOperand(0) == N1.getOperand(0)) { 5909 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5910 N0.getOperand(0), 5911 DAG.getConstantFP(4.0, VT)); 5912 } 5913 } 5914 5915 // FADD -> FMA combines: 5916 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5917 DAG.getTarget().Options.UnsafeFPMath) && 5918 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5919 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5920 5921 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 5922 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5923 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5924 N0.getOperand(0), N0.getOperand(1), N1); 5925 } 5926 5927 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 5928 // Note: Commutes FADD operands. 5929 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5930 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5931 N1.getOperand(0), N1.getOperand(1), N0); 5932 } 5933 } 5934 5935 return SDValue(); 5936} 5937 5938SDValue DAGCombiner::visitFSUB(SDNode *N) { 5939 SDValue N0 = N->getOperand(0); 5940 SDValue N1 = N->getOperand(1); 5941 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5942 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5943 EVT VT = N->getValueType(0); 5944 DebugLoc dl = N->getDebugLoc(); 5945 5946 // fold vector ops 5947 if (VT.isVector()) { 5948 SDValue FoldedVOp = SimplifyVBinOp(N); 5949 if (FoldedVOp.getNode()) return FoldedVOp; 5950 } 5951 5952 // fold (fsub c1, c2) -> c1-c2 5953 if (N0CFP && N1CFP) 5954 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5955 // fold (fsub A, 0) -> A 5956 if (DAG.getTarget().Options.UnsafeFPMath && 5957 N1CFP && N1CFP->getValueAPF().isZero()) 5958 return N0; 5959 // fold (fsub 0, B) -> -B 5960 if (DAG.getTarget().Options.UnsafeFPMath && 5961 N0CFP && N0CFP->getValueAPF().isZero()) { 5962 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5963 return GetNegatedExpression(N1, DAG, LegalOperations); 5964 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5965 return DAG.getNode(ISD::FNEG, dl, VT, N1); 5966 } 5967 // fold (fsub A, (fneg B)) -> (fadd A, B) 5968 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5969 return DAG.getNode(ISD::FADD, dl, VT, N0, 5970 GetNegatedExpression(N1, DAG, LegalOperations)); 5971 5972 // If 'unsafe math' is enabled, fold 5973 // (fsub x, x) -> 0.0 & 5974 // (fsub x, (fadd x, y)) -> (fneg y) & 5975 // (fsub x, (fadd y, x)) -> (fneg y) 5976 if (DAG.getTarget().Options.UnsafeFPMath) { 5977 if (N0 == N1) 5978 return DAG.getConstantFP(0.0f, VT); 5979 5980 if (N1.getOpcode() == ISD::FADD) { 5981 SDValue N10 = N1->getOperand(0); 5982 SDValue N11 = N1->getOperand(1); 5983 5984 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5985 &DAG.getTarget().Options)) 5986 return GetNegatedExpression(N11, DAG, LegalOperations); 5987 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5988 &DAG.getTarget().Options)) 5989 return GetNegatedExpression(N10, DAG, LegalOperations); 5990 } 5991 } 5992 5993 // FSUB -> FMA combines: 5994 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5995 DAG.getTarget().Options.UnsafeFPMath) && 5996 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5997 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5998 5999 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 6000 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 6001 return DAG.getNode(ISD::FMA, dl, VT, 6002 N0.getOperand(0), N0.getOperand(1), 6003 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6004 } 6005 6006 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 6007 // Note: Commutes FSUB operands. 6008 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 6009 return DAG.getNode(ISD::FMA, dl, VT, 6010 DAG.getNode(ISD::FNEG, dl, VT, 6011 N1.getOperand(0)), 6012 N1.getOperand(1), N0); 6013 } 6014 6015 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 6016 if (N0.getOpcode() == ISD::FNEG && 6017 N0.getOperand(0).getOpcode() == ISD::FMUL && 6018 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 6019 SDValue N00 = N0.getOperand(0).getOperand(0); 6020 SDValue N01 = N0.getOperand(0).getOperand(1); 6021 return DAG.getNode(ISD::FMA, dl, VT, 6022 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 6023 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6024 } 6025 } 6026 6027 return SDValue(); 6028} 6029 6030SDValue DAGCombiner::visitFMUL(SDNode *N) { 6031 SDValue N0 = N->getOperand(0); 6032 SDValue N1 = N->getOperand(1); 6033 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6034 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6035 EVT VT = N->getValueType(0); 6036 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6037 6038 // fold vector ops 6039 if (VT.isVector()) { 6040 SDValue FoldedVOp = SimplifyVBinOp(N); 6041 if (FoldedVOp.getNode()) return FoldedVOp; 6042 } 6043 6044 // fold (fmul c1, c2) -> c1*c2 6045 if (N0CFP && N1CFP) 6046 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 6047 // canonicalize constant to RHS 6048 if (N0CFP && !N1CFP) 6049 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 6050 // fold (fmul A, 0) -> 0 6051 if (DAG.getTarget().Options.UnsafeFPMath && 6052 N1CFP && N1CFP->getValueAPF().isZero()) 6053 return N1; 6054 // fold (fmul A, 0) -> 0, vector edition. 6055 if (DAG.getTarget().Options.UnsafeFPMath && 6056 ISD::isBuildVectorAllZeros(N1.getNode())) 6057 return N1; 6058 // fold (fmul A, 1.0) -> A 6059 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6060 return N0; 6061 // fold (fmul X, 2.0) -> (fadd X, X) 6062 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 6063 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 6064 // fold (fmul X, -1.0) -> (fneg X) 6065 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 6066 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6067 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 6068 6069 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 6070 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6071 &DAG.getTarget().Options)) { 6072 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6073 &DAG.getTarget().Options)) { 6074 // Both can be negated for free, check to see if at least one is cheaper 6075 // negated. 6076 if (LHSNeg == 2 || RHSNeg == 2) 6077 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6078 GetNegatedExpression(N0, DAG, LegalOperations), 6079 GetNegatedExpression(N1, DAG, LegalOperations)); 6080 } 6081 } 6082 6083 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 6084 if (DAG.getTarget().Options.UnsafeFPMath && 6085 N1CFP && N0.getOpcode() == ISD::FMUL && 6086 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 6087 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 6088 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6089 N0.getOperand(1), N1)); 6090 6091 return SDValue(); 6092} 6093 6094SDValue DAGCombiner::visitFMA(SDNode *N) { 6095 SDValue N0 = N->getOperand(0); 6096 SDValue N1 = N->getOperand(1); 6097 SDValue N2 = N->getOperand(2); 6098 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6099 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6100 EVT VT = N->getValueType(0); 6101 DebugLoc dl = N->getDebugLoc(); 6102 6103 if (DAG.getTarget().Options.UnsafeFPMath) { 6104 if (N0CFP && N0CFP->isZero()) 6105 return N2; 6106 if (N1CFP && N1CFP->isZero()) 6107 return N2; 6108 } 6109 if (N0CFP && N0CFP->isExactlyValue(1.0)) 6110 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); 6111 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6112 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); 6113 6114 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6115 if (N0CFP && !N1CFP) 6116 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); 6117 6118 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6119 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6120 N2.getOpcode() == ISD::FMUL && 6121 N0 == N2.getOperand(0) && 6122 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6123 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6124 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6125 } 6126 6127 6128 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6129 if (DAG.getTarget().Options.UnsafeFPMath && 6130 N0.getOpcode() == ISD::FMUL && N1CFP && 6131 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6132 return DAG.getNode(ISD::FMA, dl, VT, 6133 N0.getOperand(0), 6134 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6135 N2); 6136 } 6137 6138 // (fma x, 1, y) -> (fadd x, y) 6139 // (fma x, -1, y) -> (fadd (fneg x), y) 6140 if (N1CFP) { 6141 if (N1CFP->isExactlyValue(1.0)) 6142 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6143 6144 if (N1CFP->isExactlyValue(-1.0) && 6145 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6146 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6147 AddToWorkList(RHSNeg.getNode()); 6148 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6149 } 6150 } 6151 6152 // (fma x, c, x) -> (fmul x, (c+1)) 6153 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) { 6154 return DAG.getNode(ISD::FMUL, dl, VT, 6155 N0, 6156 DAG.getNode(ISD::FADD, dl, VT, 6157 N1, DAG.getConstantFP(1.0, VT))); 6158 } 6159 6160 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6161 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6162 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { 6163 return DAG.getNode(ISD::FMUL, dl, VT, 6164 N0, 6165 DAG.getNode(ISD::FADD, dl, VT, 6166 N1, DAG.getConstantFP(-1.0, VT))); 6167 } 6168 6169 6170 return SDValue(); 6171} 6172 6173SDValue DAGCombiner::visitFDIV(SDNode *N) { 6174 SDValue N0 = N->getOperand(0); 6175 SDValue N1 = N->getOperand(1); 6176 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6177 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6178 EVT VT = N->getValueType(0); 6179 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6180 6181 // fold vector ops 6182 if (VT.isVector()) { 6183 SDValue FoldedVOp = SimplifyVBinOp(N); 6184 if (FoldedVOp.getNode()) return FoldedVOp; 6185 } 6186 6187 // fold (fdiv c1, c2) -> c1/c2 6188 if (N0CFP && N1CFP) 6189 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 6190 6191 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6192 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) { 6193 // Compute the reciprocal 1.0 / c2. 6194 APFloat N1APF = N1CFP->getValueAPF(); 6195 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6196 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6197 // Only do the transform if the reciprocal is a legal fp immediate that 6198 // isn't too nasty (eg NaN, denormal, ...). 6199 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6200 (!LegalOperations || 6201 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6202 // backend)... we should handle this gracefully after Legalize. 6203 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6204 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6205 TLI.isFPImmLegal(Recip, VT))) 6206 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 6207 DAG.getConstantFP(Recip, VT)); 6208 } 6209 6210 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6211 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6212 &DAG.getTarget().Options)) { 6213 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6214 &DAG.getTarget().Options)) { 6215 // Both can be negated for free, check to see if at least one is cheaper 6216 // negated. 6217 if (LHSNeg == 2 || RHSNeg == 2) 6218 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 6219 GetNegatedExpression(N0, DAG, LegalOperations), 6220 GetNegatedExpression(N1, DAG, LegalOperations)); 6221 } 6222 } 6223 6224 return SDValue(); 6225} 6226 6227SDValue DAGCombiner::visitFREM(SDNode *N) { 6228 SDValue N0 = N->getOperand(0); 6229 SDValue N1 = N->getOperand(1); 6230 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6231 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6232 EVT VT = N->getValueType(0); 6233 6234 // fold (frem c1, c2) -> fmod(c1,c2) 6235 if (N0CFP && N1CFP) 6236 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 6237 6238 return SDValue(); 6239} 6240 6241SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6242 SDValue N0 = N->getOperand(0); 6243 SDValue N1 = N->getOperand(1); 6244 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6245 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6246 EVT VT = N->getValueType(0); 6247 6248 if (N0CFP && N1CFP) // Constant fold 6249 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 6250 6251 if (N1CFP) { 6252 const APFloat& V = N1CFP->getValueAPF(); 6253 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6254 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6255 if (!V.isNegative()) { 6256 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6257 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6258 } else { 6259 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6260 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6261 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 6262 } 6263 } 6264 6265 // copysign(fabs(x), y) -> copysign(x, y) 6266 // copysign(fneg(x), y) -> copysign(x, y) 6267 // copysign(copysign(x,z), y) -> copysign(x, y) 6268 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6269 N0.getOpcode() == ISD::FCOPYSIGN) 6270 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6271 N0.getOperand(0), N1); 6272 6273 // copysign(x, abs(y)) -> abs(x) 6274 if (N1.getOpcode() == ISD::FABS) 6275 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6276 6277 // copysign(x, copysign(y,z)) -> copysign(x, z) 6278 if (N1.getOpcode() == ISD::FCOPYSIGN) 6279 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6280 N0, N1.getOperand(1)); 6281 6282 // copysign(x, fp_extend(y)) -> copysign(x, y) 6283 // copysign(x, fp_round(y)) -> copysign(x, y) 6284 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6285 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6286 N0, N1.getOperand(0)); 6287 6288 return SDValue(); 6289} 6290 6291SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6292 SDValue N0 = N->getOperand(0); 6293 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6294 EVT VT = N->getValueType(0); 6295 EVT OpVT = N0.getValueType(); 6296 6297 // fold (sint_to_fp c1) -> c1fp 6298 if (N0C && 6299 // ...but only if the target supports immediate floating-point values 6300 (!LegalOperations || 6301 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6302 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6303 6304 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6305 // but UINT_TO_FP is legal on this target, try to convert. 6306 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6307 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6308 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6309 if (DAG.SignBitIsZero(N0)) 6310 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6311 } 6312 6313 // The next optimizations are desireable only if SELECT_CC can be lowered. 6314 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6315 // having to say they don't support SELECT_CC on every type the DAG knows 6316 // about, since there is no way to mark an opcode illegal at all value types 6317 // (See also visitSELECT) 6318 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6319 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6320 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6321 !VT.isVector() && 6322 (!LegalOperations || 6323 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6324 SDValue Ops[] = 6325 { N0.getOperand(0), N0.getOperand(1), 6326 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6327 N0.getOperand(2) }; 6328 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6329 } 6330 6331 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6332 // (select_cc x, y, 1.0, 0.0,, cc) 6333 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6334 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6335 (!LegalOperations || 6336 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6337 SDValue Ops[] = 6338 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6339 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6340 N0.getOperand(0).getOperand(2) }; 6341 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6342 } 6343 } 6344 6345 return SDValue(); 6346} 6347 6348SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6349 SDValue N0 = N->getOperand(0); 6350 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6351 EVT VT = N->getValueType(0); 6352 EVT OpVT = N0.getValueType(); 6353 6354 // fold (uint_to_fp c1) -> c1fp 6355 if (N0C && 6356 // ...but only if the target supports immediate floating-point values 6357 (!LegalOperations || 6358 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6359 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6360 6361 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6362 // but SINT_TO_FP is legal on this target, try to convert. 6363 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6364 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6365 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6366 if (DAG.SignBitIsZero(N0)) 6367 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6368 } 6369 6370 // The next optimizations are desireable only if SELECT_CC can be lowered. 6371 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6372 // having to say they don't support SELECT_CC on every type the DAG knows 6373 // about, since there is no way to mark an opcode illegal at all value types 6374 // (See also visitSELECT) 6375 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6376 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6377 6378 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6379 (!LegalOperations || 6380 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6381 SDValue Ops[] = 6382 { N0.getOperand(0), N0.getOperand(1), 6383 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6384 N0.getOperand(2) }; 6385 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6386 } 6387 } 6388 6389 return SDValue(); 6390} 6391 6392SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6393 SDValue N0 = N->getOperand(0); 6394 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6395 EVT VT = N->getValueType(0); 6396 6397 // fold (fp_to_sint c1fp) -> c1 6398 if (N0CFP) 6399 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 6400 6401 return SDValue(); 6402} 6403 6404SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6405 SDValue N0 = N->getOperand(0); 6406 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6407 EVT VT = N->getValueType(0); 6408 6409 // fold (fp_to_uint c1fp) -> c1 6410 if (N0CFP) 6411 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 6412 6413 return SDValue(); 6414} 6415 6416SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6417 SDValue N0 = N->getOperand(0); 6418 SDValue N1 = N->getOperand(1); 6419 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6420 EVT VT = N->getValueType(0); 6421 6422 // fold (fp_round c1fp) -> c1fp 6423 if (N0CFP) 6424 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 6425 6426 // fold (fp_round (fp_extend x)) -> x 6427 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6428 return N0.getOperand(0); 6429 6430 // fold (fp_round (fp_round x)) -> (fp_round x) 6431 if (N0.getOpcode() == ISD::FP_ROUND) { 6432 // This is a value preserving truncation if both round's are. 6433 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6434 N0.getNode()->getConstantOperandVal(1) == 1; 6435 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 6436 DAG.getIntPtrConstant(IsTrunc)); 6437 } 6438 6439 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6440 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6441 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 6442 N0.getOperand(0), N1); 6443 AddToWorkList(Tmp.getNode()); 6444 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6445 Tmp, N0.getOperand(1)); 6446 } 6447 6448 return SDValue(); 6449} 6450 6451SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6452 SDValue N0 = N->getOperand(0); 6453 EVT VT = N->getValueType(0); 6454 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6455 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6456 6457 // fold (fp_round_inreg c1fp) -> c1fp 6458 if (N0CFP && isTypeLegal(EVT)) { 6459 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6460 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 6461 } 6462 6463 return SDValue(); 6464} 6465 6466SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6467 SDValue N0 = N->getOperand(0); 6468 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6469 EVT VT = N->getValueType(0); 6470 6471 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6472 if (N->hasOneUse() && 6473 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6474 return SDValue(); 6475 6476 // fold (fp_extend c1fp) -> c1fp 6477 if (N0CFP) 6478 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6479 6480 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6481 // value of X. 6482 if (N0.getOpcode() == ISD::FP_ROUND 6483 && N0.getNode()->getConstantOperandVal(1) == 1) { 6484 SDValue In = N0.getOperand(0); 6485 if (In.getValueType() == VT) return In; 6486 if (VT.bitsLT(In.getValueType())) 6487 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6488 In, N0.getOperand(1)); 6489 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6490 } 6491 6492 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6493 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6494 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6495 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6496 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6497 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6498 LN0->getChain(), 6499 LN0->getBasePtr(), LN0->getPointerInfo(), 6500 N0.getValueType(), 6501 LN0->isVolatile(), LN0->isNonTemporal(), 6502 LN0->getAlignment()); 6503 CombineTo(N, ExtLoad); 6504 CombineTo(N0.getNode(), 6505 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6506 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6507 ExtLoad.getValue(1)); 6508 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6509 } 6510 6511 return SDValue(); 6512} 6513 6514SDValue DAGCombiner::visitFNEG(SDNode *N) { 6515 SDValue N0 = N->getOperand(0); 6516 EVT VT = N->getValueType(0); 6517 6518 if (VT.isVector()) { 6519 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6520 if (FoldedVOp.getNode()) return FoldedVOp; 6521 } 6522 6523 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6524 &DAG.getTarget().Options)) 6525 return GetNegatedExpression(N0, DAG, LegalOperations); 6526 6527 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6528 // constant pool values. 6529 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6530 !VT.isVector() && 6531 N0.getNode()->hasOneUse() && 6532 N0.getOperand(0).getValueType().isInteger()) { 6533 SDValue Int = N0.getOperand(0); 6534 EVT IntVT = Int.getValueType(); 6535 if (IntVT.isInteger() && !IntVT.isVector()) { 6536 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6537 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6538 AddToWorkList(Int.getNode()); 6539 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6540 VT, Int); 6541 } 6542 } 6543 6544 // (fneg (fmul c, x)) -> (fmul -c, x) 6545 if (N0.getOpcode() == ISD::FMUL) { 6546 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6547 if (CFP1) { 6548 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6549 N0.getOperand(0), 6550 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6551 N0.getOperand(1))); 6552 } 6553 } 6554 6555 return SDValue(); 6556} 6557 6558SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6559 SDValue N0 = N->getOperand(0); 6560 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6561 EVT VT = N->getValueType(0); 6562 6563 // fold (fceil c1) -> fceil(c1) 6564 if (N0CFP) 6565 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0); 6566 6567 return SDValue(); 6568} 6569 6570SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6571 SDValue N0 = N->getOperand(0); 6572 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6573 EVT VT = N->getValueType(0); 6574 6575 // fold (ftrunc c1) -> ftrunc(c1) 6576 if (N0CFP) 6577 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0); 6578 6579 return SDValue(); 6580} 6581 6582SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6583 SDValue N0 = N->getOperand(0); 6584 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6585 EVT VT = N->getValueType(0); 6586 6587 // fold (ffloor c1) -> ffloor(c1) 6588 if (N0CFP) 6589 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0); 6590 6591 return SDValue(); 6592} 6593 6594SDValue DAGCombiner::visitFABS(SDNode *N) { 6595 SDValue N0 = N->getOperand(0); 6596 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6597 EVT VT = N->getValueType(0); 6598 6599 if (VT.isVector()) { 6600 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6601 if (FoldedVOp.getNode()) return FoldedVOp; 6602 } 6603 6604 // fold (fabs c1) -> fabs(c1) 6605 if (N0CFP) 6606 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6607 // fold (fabs (fabs x)) -> (fabs x) 6608 if (N0.getOpcode() == ISD::FABS) 6609 return N->getOperand(0); 6610 // fold (fabs (fneg x)) -> (fabs x) 6611 // fold (fabs (fcopysign x, y)) -> (fabs x) 6612 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6613 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6614 6615 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6616 // constant pool values. 6617 if (!TLI.isFAbsFree(VT) && 6618 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6619 N0.getOperand(0).getValueType().isInteger() && 6620 !N0.getOperand(0).getValueType().isVector()) { 6621 SDValue Int = N0.getOperand(0); 6622 EVT IntVT = Int.getValueType(); 6623 if (IntVT.isInteger() && !IntVT.isVector()) { 6624 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6625 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6626 AddToWorkList(Int.getNode()); 6627 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6628 N->getValueType(0), Int); 6629 } 6630 } 6631 6632 return SDValue(); 6633} 6634 6635SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6636 SDValue Chain = N->getOperand(0); 6637 SDValue N1 = N->getOperand(1); 6638 SDValue N2 = N->getOperand(2); 6639 6640 // If N is a constant we could fold this into a fallthrough or unconditional 6641 // branch. However that doesn't happen very often in normal code, because 6642 // Instcombine/SimplifyCFG should have handled the available opportunities. 6643 // If we did this folding here, it would be necessary to update the 6644 // MachineBasicBlock CFG, which is awkward. 6645 6646 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6647 // on the target. 6648 if (N1.getOpcode() == ISD::SETCC && 6649 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6650 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6651 Chain, N1.getOperand(2), 6652 N1.getOperand(0), N1.getOperand(1), N2); 6653 } 6654 6655 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6656 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6657 (N1.getOperand(0).hasOneUse() && 6658 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6659 SDNode *Trunc = 0; 6660 if (N1.getOpcode() == ISD::TRUNCATE) { 6661 // Look pass the truncate. 6662 Trunc = N1.getNode(); 6663 N1 = N1.getOperand(0); 6664 } 6665 6666 // Match this pattern so that we can generate simpler code: 6667 // 6668 // %a = ... 6669 // %b = and i32 %a, 2 6670 // %c = srl i32 %b, 1 6671 // brcond i32 %c ... 6672 // 6673 // into 6674 // 6675 // %a = ... 6676 // %b = and i32 %a, 2 6677 // %c = setcc eq %b, 0 6678 // brcond %c ... 6679 // 6680 // This applies only when the AND constant value has one bit set and the 6681 // SRL constant is equal to the log2 of the AND constant. The back-end is 6682 // smart enough to convert the result into a TEST/JMP sequence. 6683 SDValue Op0 = N1.getOperand(0); 6684 SDValue Op1 = N1.getOperand(1); 6685 6686 if (Op0.getOpcode() == ISD::AND && 6687 Op1.getOpcode() == ISD::Constant) { 6688 SDValue AndOp1 = Op0.getOperand(1); 6689 6690 if (AndOp1.getOpcode() == ISD::Constant) { 6691 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6692 6693 if (AndConst.isPowerOf2() && 6694 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6695 SDValue SetCC = 6696 DAG.getSetCC(N->getDebugLoc(), 6697 TLI.getSetCCResultType(Op0.getValueType()), 6698 Op0, DAG.getConstant(0, Op0.getValueType()), 6699 ISD::SETNE); 6700 6701 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6702 MVT::Other, Chain, SetCC, N2); 6703 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6704 // will convert it back to (X & C1) >> C2. 6705 CombineTo(N, NewBRCond, false); 6706 // Truncate is dead. 6707 if (Trunc) { 6708 removeFromWorkList(Trunc); 6709 DAG.DeleteNode(Trunc); 6710 } 6711 // Replace the uses of SRL with SETCC 6712 WorkListRemover DeadNodes(*this); 6713 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6714 removeFromWorkList(N1.getNode()); 6715 DAG.DeleteNode(N1.getNode()); 6716 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6717 } 6718 } 6719 } 6720 6721 if (Trunc) 6722 // Restore N1 if the above transformation doesn't match. 6723 N1 = N->getOperand(1); 6724 } 6725 6726 // Transform br(xor(x, y)) -> br(x != y) 6727 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6728 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6729 SDNode *TheXor = N1.getNode(); 6730 SDValue Op0 = TheXor->getOperand(0); 6731 SDValue Op1 = TheXor->getOperand(1); 6732 if (Op0.getOpcode() == Op1.getOpcode()) { 6733 // Avoid missing important xor optimizations. 6734 SDValue Tmp = visitXOR(TheXor); 6735 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6736 DEBUG(dbgs() << "\nReplacing.8 "; 6737 TheXor->dump(&DAG); 6738 dbgs() << "\nWith: "; 6739 Tmp.getNode()->dump(&DAG); 6740 dbgs() << '\n'); 6741 WorkListRemover DeadNodes(*this); 6742 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6743 removeFromWorkList(TheXor); 6744 DAG.DeleteNode(TheXor); 6745 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6746 MVT::Other, Chain, Tmp, N2); 6747 } 6748 } 6749 6750 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6751 bool Equal = false; 6752 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6753 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6754 Op0.getOpcode() == ISD::XOR) { 6755 TheXor = Op0.getNode(); 6756 Equal = true; 6757 } 6758 6759 EVT SetCCVT = N1.getValueType(); 6760 if (LegalTypes) 6761 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6762 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6763 SetCCVT, 6764 Op0, Op1, 6765 Equal ? ISD::SETEQ : ISD::SETNE); 6766 // Replace the uses of XOR with SETCC 6767 WorkListRemover DeadNodes(*this); 6768 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6769 removeFromWorkList(N1.getNode()); 6770 DAG.DeleteNode(N1.getNode()); 6771 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6772 MVT::Other, Chain, SetCC, N2); 6773 } 6774 } 6775 6776 return SDValue(); 6777} 6778 6779// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6780// 6781SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6782 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6783 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6784 6785 // If N is a constant we could fold this into a fallthrough or unconditional 6786 // branch. However that doesn't happen very often in normal code, because 6787 // Instcombine/SimplifyCFG should have handled the available opportunities. 6788 // If we did this folding here, it would be necessary to update the 6789 // MachineBasicBlock CFG, which is awkward. 6790 6791 // Use SimplifySetCC to simplify SETCC's. 6792 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6793 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6794 false); 6795 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6796 6797 // fold to a simpler setcc 6798 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6799 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6800 N->getOperand(0), Simp.getOperand(2), 6801 Simp.getOperand(0), Simp.getOperand(1), 6802 N->getOperand(4)); 6803 6804 return SDValue(); 6805} 6806 6807/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6808/// uses N as its base pointer and that N may be folded in the load / store 6809/// addressing mode. 6810static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6811 SelectionDAG &DAG, 6812 const TargetLowering &TLI) { 6813 EVT VT; 6814 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6815 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6816 return false; 6817 VT = Use->getValueType(0); 6818 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6819 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6820 return false; 6821 VT = ST->getValue().getValueType(); 6822 } else 6823 return false; 6824 6825 AddrMode AM; 6826 if (N->getOpcode() == ISD::ADD) { 6827 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6828 if (Offset) 6829 // [reg +/- imm] 6830 AM.BaseOffs = Offset->getSExtValue(); 6831 else 6832 // [reg +/- reg] 6833 AM.Scale = 1; 6834 } else if (N->getOpcode() == ISD::SUB) { 6835 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6836 if (Offset) 6837 // [reg +/- imm] 6838 AM.BaseOffs = -Offset->getSExtValue(); 6839 else 6840 // [reg +/- reg] 6841 AM.Scale = 1; 6842 } else 6843 return false; 6844 6845 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6846} 6847 6848/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6849/// pre-indexed load / store when the base pointer is an add or subtract 6850/// and it has other uses besides the load / store. After the 6851/// transformation, the new indexed load / store has effectively folded 6852/// the add / subtract in and all of its other uses are redirected to the 6853/// new load / store. 6854bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6855 if (Level < AfterLegalizeDAG) 6856 return false; 6857 6858 bool isLoad = true; 6859 SDValue Ptr; 6860 EVT VT; 6861 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6862 if (LD->isIndexed()) 6863 return false; 6864 VT = LD->getMemoryVT(); 6865 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6866 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6867 return false; 6868 Ptr = LD->getBasePtr(); 6869 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6870 if (ST->isIndexed()) 6871 return false; 6872 VT = ST->getMemoryVT(); 6873 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6874 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6875 return false; 6876 Ptr = ST->getBasePtr(); 6877 isLoad = false; 6878 } else { 6879 return false; 6880 } 6881 6882 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6883 // out. There is no reason to make this a preinc/predec. 6884 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6885 Ptr.getNode()->hasOneUse()) 6886 return false; 6887 6888 // Ask the target to do addressing mode selection. 6889 SDValue BasePtr; 6890 SDValue Offset; 6891 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6892 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6893 return false; 6894 // Don't create a indexed load / store with zero offset. 6895 if (isa<ConstantSDNode>(Offset) && 6896 cast<ConstantSDNode>(Offset)->isNullValue()) 6897 return false; 6898 6899 // Try turning it into a pre-indexed load / store except when: 6900 // 1) The new base ptr is a frame index. 6901 // 2) If N is a store and the new base ptr is either the same as or is a 6902 // predecessor of the value being stored. 6903 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6904 // that would create a cycle. 6905 // 4) All uses are load / store ops that use it as old base ptr. 6906 6907 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6908 // (plus the implicit offset) to a register to preinc anyway. 6909 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6910 return false; 6911 6912 // Check #2. 6913 if (!isLoad) { 6914 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6915 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6916 return false; 6917 } 6918 6919 // Now check for #3 and #4. 6920 bool RealUse = false; 6921 6922 // Caches for hasPredecessorHelper 6923 SmallPtrSet<const SDNode *, 32> Visited; 6924 SmallVector<const SDNode *, 16> Worklist; 6925 6926 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6927 E = Ptr.getNode()->use_end(); I != E; ++I) { 6928 SDNode *Use = *I; 6929 if (Use == N) 6930 continue; 6931 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6932 return false; 6933 6934 // If Ptr may be folded in addressing mode of other use, then it's 6935 // not profitable to do this transformation. 6936 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6937 RealUse = true; 6938 } 6939 6940 if (!RealUse) 6941 return false; 6942 6943 SDValue Result; 6944 if (isLoad) 6945 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6946 BasePtr, Offset, AM); 6947 else 6948 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6949 BasePtr, Offset, AM); 6950 ++PreIndexedNodes; 6951 ++NodesCombined; 6952 DEBUG(dbgs() << "\nReplacing.4 "; 6953 N->dump(&DAG); 6954 dbgs() << "\nWith: "; 6955 Result.getNode()->dump(&DAG); 6956 dbgs() << '\n'); 6957 WorkListRemover DeadNodes(*this); 6958 if (isLoad) { 6959 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6960 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6961 } else { 6962 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6963 } 6964 6965 // Finally, since the node is now dead, remove it from the graph. 6966 DAG.DeleteNode(N); 6967 6968 // Replace the uses of Ptr with uses of the updated base value. 6969 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 6970 removeFromWorkList(Ptr.getNode()); 6971 DAG.DeleteNode(Ptr.getNode()); 6972 6973 return true; 6974} 6975 6976/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6977/// add / sub of the base pointer node into a post-indexed load / store. 6978/// The transformation folded the add / subtract into the new indexed 6979/// load / store effectively and all of its uses are redirected to the 6980/// new load / store. 6981bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6982 if (Level < AfterLegalizeDAG) 6983 return false; 6984 6985 bool isLoad = true; 6986 SDValue Ptr; 6987 EVT VT; 6988 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6989 if (LD->isIndexed()) 6990 return false; 6991 VT = LD->getMemoryVT(); 6992 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6993 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6994 return false; 6995 Ptr = LD->getBasePtr(); 6996 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6997 if (ST->isIndexed()) 6998 return false; 6999 VT = ST->getMemoryVT(); 7000 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 7001 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 7002 return false; 7003 Ptr = ST->getBasePtr(); 7004 isLoad = false; 7005 } else { 7006 return false; 7007 } 7008 7009 if (Ptr.getNode()->hasOneUse()) 7010 return false; 7011 7012 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 7013 E = Ptr.getNode()->use_end(); I != E; ++I) { 7014 SDNode *Op = *I; 7015 if (Op == N || 7016 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 7017 continue; 7018 7019 SDValue BasePtr; 7020 SDValue Offset; 7021 ISD::MemIndexedMode AM = ISD::UNINDEXED; 7022 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 7023 // Don't create a indexed load / store with zero offset. 7024 if (isa<ConstantSDNode>(Offset) && 7025 cast<ConstantSDNode>(Offset)->isNullValue()) 7026 continue; 7027 7028 // Try turning it into a post-indexed load / store except when 7029 // 1) All uses are load / store ops that use it as base ptr (and 7030 // it may be folded as addressing mmode). 7031 // 2) Op must be independent of N, i.e. Op is neither a predecessor 7032 // nor a successor of N. Otherwise, if Op is folded that would 7033 // create a cycle. 7034 7035 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 7036 continue; 7037 7038 // Check for #1. 7039 bool TryNext = false; 7040 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 7041 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 7042 SDNode *Use = *II; 7043 if (Use == Ptr.getNode()) 7044 continue; 7045 7046 // If all the uses are load / store addresses, then don't do the 7047 // transformation. 7048 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 7049 bool RealUse = false; 7050 for (SDNode::use_iterator III = Use->use_begin(), 7051 EEE = Use->use_end(); III != EEE; ++III) { 7052 SDNode *UseUse = *III; 7053 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 7054 RealUse = true; 7055 } 7056 7057 if (!RealUse) { 7058 TryNext = true; 7059 break; 7060 } 7061 } 7062 } 7063 7064 if (TryNext) 7065 continue; 7066 7067 // Check for #2 7068 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 7069 SDValue Result = isLoad 7070 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 7071 BasePtr, Offset, AM) 7072 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 7073 BasePtr, Offset, AM); 7074 ++PostIndexedNodes; 7075 ++NodesCombined; 7076 DEBUG(dbgs() << "\nReplacing.5 "; 7077 N->dump(&DAG); 7078 dbgs() << "\nWith: "; 7079 Result.getNode()->dump(&DAG); 7080 dbgs() << '\n'); 7081 WorkListRemover DeadNodes(*this); 7082 if (isLoad) { 7083 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7084 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7085 } else { 7086 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7087 } 7088 7089 // Finally, since the node is now dead, remove it from the graph. 7090 DAG.DeleteNode(N); 7091 7092 // Replace the uses of Use with uses of the updated base value. 7093 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 7094 Result.getValue(isLoad ? 1 : 0)); 7095 removeFromWorkList(Op); 7096 DAG.DeleteNode(Op); 7097 return true; 7098 } 7099 } 7100 } 7101 7102 return false; 7103} 7104 7105SDValue DAGCombiner::visitLOAD(SDNode *N) { 7106 LoadSDNode *LD = cast<LoadSDNode>(N); 7107 SDValue Chain = LD->getChain(); 7108 SDValue Ptr = LD->getBasePtr(); 7109 7110 // If load is not volatile and there are no uses of the loaded value (and 7111 // the updated indexed value in case of indexed loads), change uses of the 7112 // chain value into uses of the chain input (i.e. delete the dead load). 7113 if (!LD->isVolatile()) { 7114 if (N->getValueType(1) == MVT::Other) { 7115 // Unindexed loads. 7116 if (!N->hasAnyUseOfValue(0)) { 7117 // It's not safe to use the two value CombineTo variant here. e.g. 7118 // v1, chain2 = load chain1, loc 7119 // v2, chain3 = load chain2, loc 7120 // v3 = add v2, c 7121 // Now we replace use of chain2 with chain1. This makes the second load 7122 // isomorphic to the one we are deleting, and thus makes this load live. 7123 DEBUG(dbgs() << "\nReplacing.6 "; 7124 N->dump(&DAG); 7125 dbgs() << "\nWith chain: "; 7126 Chain.getNode()->dump(&DAG); 7127 dbgs() << "\n"); 7128 WorkListRemover DeadNodes(*this); 7129 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7130 7131 if (N->use_empty()) { 7132 removeFromWorkList(N); 7133 DAG.DeleteNode(N); 7134 } 7135 7136 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7137 } 7138 } else { 7139 // Indexed loads. 7140 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7141 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7142 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7143 DEBUG(dbgs() << "\nReplacing.7 "; 7144 N->dump(&DAG); 7145 dbgs() << "\nWith: "; 7146 Undef.getNode()->dump(&DAG); 7147 dbgs() << " and 2 other values\n"); 7148 WorkListRemover DeadNodes(*this); 7149 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7150 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7151 DAG.getUNDEF(N->getValueType(1))); 7152 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7153 removeFromWorkList(N); 7154 DAG.DeleteNode(N); 7155 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7156 } 7157 } 7158 } 7159 7160 // If this load is directly stored, replace the load value with the stored 7161 // value. 7162 // TODO: Handle store large -> read small portion. 7163 // TODO: Handle TRUNCSTORE/LOADEXT 7164 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7165 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7166 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7167 if (PrevST->getBasePtr() == Ptr && 7168 PrevST->getValue().getValueType() == N->getValueType(0)) 7169 return CombineTo(N, Chain.getOperand(1), Chain); 7170 } 7171 } 7172 7173 // Try to infer better alignment information than the load already has. 7174 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7175 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7176 if (Align > LD->getAlignment()) 7177 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 7178 LD->getValueType(0), 7179 Chain, Ptr, LD->getPointerInfo(), 7180 LD->getMemoryVT(), 7181 LD->isVolatile(), LD->isNonTemporal(), Align); 7182 } 7183 } 7184 7185 if (CombinerAA) { 7186 // Walk up chain skipping non-aliasing memory nodes. 7187 SDValue BetterChain = FindBetterChain(N, Chain); 7188 7189 // If there is a better chain. 7190 if (Chain != BetterChain) { 7191 SDValue ReplLoad; 7192 7193 // Replace the chain to void dependency. 7194 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7195 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 7196 BetterChain, Ptr, LD->getPointerInfo(), 7197 LD->isVolatile(), LD->isNonTemporal(), 7198 LD->isInvariant(), LD->getAlignment()); 7199 } else { 7200 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 7201 LD->getValueType(0), 7202 BetterChain, Ptr, LD->getPointerInfo(), 7203 LD->getMemoryVT(), 7204 LD->isVolatile(), 7205 LD->isNonTemporal(), 7206 LD->getAlignment()); 7207 } 7208 7209 // Create token factor to keep old chain connected. 7210 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7211 MVT::Other, Chain, ReplLoad.getValue(1)); 7212 7213 // Make sure the new and old chains are cleaned up. 7214 AddToWorkList(Token.getNode()); 7215 7216 // Replace uses with load result and token factor. Don't add users 7217 // to work list. 7218 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7219 } 7220 } 7221 7222 // Try transforming N to an indexed load. 7223 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7224 return SDValue(N, 0); 7225 7226 return SDValue(); 7227} 7228 7229/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 7230/// load is having specific bytes cleared out. If so, return the byte size 7231/// being masked out and the shift amount. 7232static std::pair<unsigned, unsigned> 7233CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 7234 std::pair<unsigned, unsigned> Result(0, 0); 7235 7236 // Check for the structure we're looking for. 7237 if (V->getOpcode() != ISD::AND || 7238 !isa<ConstantSDNode>(V->getOperand(1)) || 7239 !ISD::isNormalLoad(V->getOperand(0).getNode())) 7240 return Result; 7241 7242 // Check the chain and pointer. 7243 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 7244 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 7245 7246 // The store should be chained directly to the load or be an operand of a 7247 // tokenfactor. 7248 if (LD == Chain.getNode()) 7249 ; // ok. 7250 else if (Chain->getOpcode() != ISD::TokenFactor) 7251 return Result; // Fail. 7252 else { 7253 bool isOk = false; 7254 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 7255 if (Chain->getOperand(i).getNode() == LD) { 7256 isOk = true; 7257 break; 7258 } 7259 if (!isOk) return Result; 7260 } 7261 7262 // This only handles simple types. 7263 if (V.getValueType() != MVT::i16 && 7264 V.getValueType() != MVT::i32 && 7265 V.getValueType() != MVT::i64) 7266 return Result; 7267 7268 // Check the constant mask. Invert it so that the bits being masked out are 7269 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 7270 // follow the sign bit for uniformity. 7271 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 7272 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 7273 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 7274 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 7275 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 7276 if (NotMaskLZ == 64) return Result; // All zero mask. 7277 7278 // See if we have a continuous run of bits. If so, we have 0*1+0* 7279 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 7280 return Result; 7281 7282 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 7283 if (V.getValueType() != MVT::i64 && NotMaskLZ) 7284 NotMaskLZ -= 64-V.getValueSizeInBits(); 7285 7286 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 7287 switch (MaskedBytes) { 7288 case 1: 7289 case 2: 7290 case 4: break; 7291 default: return Result; // All one mask, or 5-byte mask. 7292 } 7293 7294 // Verify that the first bit starts at a multiple of mask so that the access 7295 // is aligned the same as the access width. 7296 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 7297 7298 Result.first = MaskedBytes; 7299 Result.second = NotMaskTZ/8; 7300 return Result; 7301} 7302 7303 7304/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 7305/// provides a value as specified by MaskInfo. If so, replace the specified 7306/// store with a narrower store of truncated IVal. 7307static SDNode * 7308ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 7309 SDValue IVal, StoreSDNode *St, 7310 DAGCombiner *DC) { 7311 unsigned NumBytes = MaskInfo.first; 7312 unsigned ByteShift = MaskInfo.second; 7313 SelectionDAG &DAG = DC->getDAG(); 7314 7315 // Check to see if IVal is all zeros in the part being masked in by the 'or' 7316 // that uses this. If not, this is not a replacement. 7317 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 7318 ByteShift*8, (ByteShift+NumBytes)*8); 7319 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 7320 7321 // Check that it is legal on the target to do this. It is legal if the new 7322 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 7323 // legalization. 7324 MVT VT = MVT::getIntegerVT(NumBytes*8); 7325 if (!DC->isTypeLegal(VT)) 7326 return 0; 7327 7328 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 7329 // shifted by ByteShift and truncated down to NumBytes. 7330 if (ByteShift) 7331 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 7332 DAG.getConstant(ByteShift*8, 7333 DC->getShiftAmountTy(IVal.getValueType()))); 7334 7335 // Figure out the offset for the store and the alignment of the access. 7336 unsigned StOffset; 7337 unsigned NewAlign = St->getAlignment(); 7338 7339 if (DAG.getTargetLoweringInfo().isLittleEndian()) 7340 StOffset = ByteShift; 7341 else 7342 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 7343 7344 SDValue Ptr = St->getBasePtr(); 7345 if (StOffset) { 7346 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 7347 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 7348 NewAlign = MinAlign(NewAlign, StOffset); 7349 } 7350 7351 // Truncate down to the new size. 7352 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 7353 7354 ++OpsNarrowed; 7355 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 7356 St->getPointerInfo().getWithOffset(StOffset), 7357 false, false, NewAlign).getNode(); 7358} 7359 7360 7361/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 7362/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 7363/// of the loaded bits, try narrowing the load and store if it would end up 7364/// being a win for performance or code size. 7365SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 7366 StoreSDNode *ST = cast<StoreSDNode>(N); 7367 if (ST->isVolatile()) 7368 return SDValue(); 7369 7370 SDValue Chain = ST->getChain(); 7371 SDValue Value = ST->getValue(); 7372 SDValue Ptr = ST->getBasePtr(); 7373 EVT VT = Value.getValueType(); 7374 7375 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 7376 return SDValue(); 7377 7378 unsigned Opc = Value.getOpcode(); 7379 7380 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 7381 // is a byte mask indicating a consecutive number of bytes, check to see if 7382 // Y is known to provide just those bytes. If so, we try to replace the 7383 // load + replace + store sequence with a single (narrower) store, which makes 7384 // the load dead. 7385 if (Opc == ISD::OR) { 7386 std::pair<unsigned, unsigned> MaskedLoad; 7387 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 7388 if (MaskedLoad.first) 7389 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7390 Value.getOperand(1), ST,this)) 7391 return SDValue(NewST, 0); 7392 7393 // Or is commutative, so try swapping X and Y. 7394 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 7395 if (MaskedLoad.first) 7396 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7397 Value.getOperand(0), ST,this)) 7398 return SDValue(NewST, 0); 7399 } 7400 7401 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 7402 Value.getOperand(1).getOpcode() != ISD::Constant) 7403 return SDValue(); 7404 7405 SDValue N0 = Value.getOperand(0); 7406 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 7407 Chain == SDValue(N0.getNode(), 1)) { 7408 LoadSDNode *LD = cast<LoadSDNode>(N0); 7409 if (LD->getBasePtr() != Ptr || 7410 LD->getPointerInfo().getAddrSpace() != 7411 ST->getPointerInfo().getAddrSpace()) 7412 return SDValue(); 7413 7414 // Find the type to narrow it the load / op / store to. 7415 SDValue N1 = Value.getOperand(1); 7416 unsigned BitWidth = N1.getValueSizeInBits(); 7417 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 7418 if (Opc == ISD::AND) 7419 Imm ^= APInt::getAllOnesValue(BitWidth); 7420 if (Imm == 0 || Imm.isAllOnesValue()) 7421 return SDValue(); 7422 unsigned ShAmt = Imm.countTrailingZeros(); 7423 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 7424 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 7425 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7426 while (NewBW < BitWidth && 7427 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 7428 TLI.isNarrowingProfitable(VT, NewVT))) { 7429 NewBW = NextPowerOf2(NewBW); 7430 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7431 } 7432 if (NewBW >= BitWidth) 7433 return SDValue(); 7434 7435 // If the lsb changed does not start at the type bitwidth boundary, 7436 // start at the previous one. 7437 if (ShAmt % NewBW) 7438 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 7439 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 7440 if ((Imm & Mask) == Imm) { 7441 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 7442 if (Opc == ISD::AND) 7443 NewImm ^= APInt::getAllOnesValue(NewBW); 7444 uint64_t PtrOff = ShAmt / 8; 7445 // For big endian targets, we need to adjust the offset to the pointer to 7446 // load the correct bytes. 7447 if (TLI.isBigEndian()) 7448 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 7449 7450 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 7451 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 7452 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy)) 7453 return SDValue(); 7454 7455 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 7456 Ptr.getValueType(), Ptr, 7457 DAG.getConstant(PtrOff, Ptr.getValueType())); 7458 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 7459 LD->getChain(), NewPtr, 7460 LD->getPointerInfo().getWithOffset(PtrOff), 7461 LD->isVolatile(), LD->isNonTemporal(), 7462 LD->isInvariant(), NewAlign); 7463 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 7464 DAG.getConstant(NewImm, NewVT)); 7465 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 7466 NewVal, NewPtr, 7467 ST->getPointerInfo().getWithOffset(PtrOff), 7468 false, false, NewAlign); 7469 7470 AddToWorkList(NewPtr.getNode()); 7471 AddToWorkList(NewLD.getNode()); 7472 AddToWorkList(NewVal.getNode()); 7473 WorkListRemover DeadNodes(*this); 7474 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7475 ++OpsNarrowed; 7476 return NewST; 7477 } 7478 } 7479 7480 return SDValue(); 7481} 7482 7483/// TransformFPLoadStorePair - For a given floating point load / store pair, 7484/// if the load value isn't used by any other operations, then consider 7485/// transforming the pair to integer load / store operations if the target 7486/// deems the transformation profitable. 7487SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7488 StoreSDNode *ST = cast<StoreSDNode>(N); 7489 SDValue Chain = ST->getChain(); 7490 SDValue Value = ST->getValue(); 7491 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7492 Value.hasOneUse() && 7493 Chain == SDValue(Value.getNode(), 1)) { 7494 LoadSDNode *LD = cast<LoadSDNode>(Value); 7495 EVT VT = LD->getMemoryVT(); 7496 if (!VT.isFloatingPoint() || 7497 VT != ST->getMemoryVT() || 7498 LD->isNonTemporal() || 7499 ST->isNonTemporal() || 7500 LD->getPointerInfo().getAddrSpace() != 0 || 7501 ST->getPointerInfo().getAddrSpace() != 0) 7502 return SDValue(); 7503 7504 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7505 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7506 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7507 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7508 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7509 return SDValue(); 7510 7511 unsigned LDAlign = LD->getAlignment(); 7512 unsigned STAlign = ST->getAlignment(); 7513 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7514 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy); 7515 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7516 return SDValue(); 7517 7518 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 7519 LD->getChain(), LD->getBasePtr(), 7520 LD->getPointerInfo(), 7521 false, false, false, LDAlign); 7522 7523 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 7524 NewLD, ST->getBasePtr(), 7525 ST->getPointerInfo(), 7526 false, false, STAlign); 7527 7528 AddToWorkList(NewLD.getNode()); 7529 AddToWorkList(NewST.getNode()); 7530 WorkListRemover DeadNodes(*this); 7531 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7532 ++LdStFP2Int; 7533 return NewST; 7534 } 7535 7536 return SDValue(); 7537} 7538 7539/// Returns the base pointer and an integer offset from that object. 7540static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) { 7541 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) { 7542 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue(); 7543 SDValue Base = Ptr->getOperand(0); 7544 return std::make_pair(Base, Offset); 7545 } 7546 7547 return std::make_pair(Ptr, 0); 7548} 7549 7550/// Holds a pointer to an LSBaseSDNode as well as information on where it 7551/// is located in a sequence of memory operations connected by a chain. 7552struct MemOpLink { 7553 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq): 7554 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { } 7555 // Ptr to the mem node. 7556 LSBaseSDNode *MemNode; 7557 // Offset from the base ptr. 7558 int64_t OffsetFromBase; 7559 // What is the sequence number of this mem node. 7560 // Lowest mem operand in the DAG starts at zero. 7561 unsigned SequenceNum; 7562}; 7563 7564/// Sorts store nodes in a link according to their offset from a shared 7565// base ptr. 7566struct ConsecutiveMemoryChainSorter { 7567 bool operator()(MemOpLink LHS, MemOpLink RHS) { 7568 return LHS.OffsetFromBase < RHS.OffsetFromBase; 7569 } 7570}; 7571 7572bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) { 7573 EVT MemVT = St->getMemoryVT(); 7574 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8; 7575 7576 // Don't merge vectors into wider inputs. 7577 if (MemVT.isVector() || !MemVT.isSimple()) 7578 return false; 7579 7580 // Perform an early exit check. Do not bother looking at stored values that 7581 // are not constants or loads. 7582 SDValue StoredVal = St->getValue(); 7583 bool IsLoadSrc = isa<LoadSDNode>(StoredVal); 7584 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) && 7585 !IsLoadSrc) 7586 return false; 7587 7588 // Only look at ends of store sequences. 7589 SDValue Chain = SDValue(St, 1); 7590 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE) 7591 return false; 7592 7593 // This holds the base pointer and the offset in bytes from the base pointer. 7594 std::pair<SDValue, int64_t> BasePtr = 7595 GetPointerBaseAndOffset(St->getBasePtr()); 7596 7597 // We must have a base and an offset. 7598 if (!BasePtr.first.getNode()) 7599 return false; 7600 7601 // Do not handle stores to undef base pointers. 7602 if (BasePtr.first.getOpcode() == ISD::UNDEF) 7603 return false; 7604 7605 // Save the LoadSDNodes that we find in the chain. 7606 // We need to make sure that these nodes do not interfere with 7607 // any of the store nodes. 7608 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes; 7609 7610 // Save the StoreSDNodes that we find in the chain. 7611 SmallVector<MemOpLink, 8> StoreNodes; 7612 7613 // Walk up the chain and look for nodes with offsets from the same 7614 // base pointer. Stop when reaching an instruction with a different kind 7615 // or instruction which has a different base pointer. 7616 unsigned Seq = 0; 7617 StoreSDNode *Index = St; 7618 while (Index) { 7619 // If the chain has more than one use, then we can't reorder the mem ops. 7620 if (Index != St && !SDValue(Index, 1)->hasOneUse()) 7621 break; 7622 7623 // Find the base pointer and offset for this memory node. 7624 std::pair<SDValue, int64_t> Ptr = 7625 GetPointerBaseAndOffset(Index->getBasePtr()); 7626 7627 // Check that the base pointer is the same as the original one. 7628 if (Ptr.first.getNode() != BasePtr.first.getNode()) 7629 break; 7630 7631 // Check that the alignment is the same. 7632 if (Index->getAlignment() != St->getAlignment()) 7633 break; 7634 7635 // The memory operands must not be volatile. 7636 if (Index->isVolatile() || Index->isIndexed()) 7637 break; 7638 7639 // No truncation. 7640 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index)) 7641 if (St->isTruncatingStore()) 7642 break; 7643 7644 // The stored memory type must be the same. 7645 if (Index->getMemoryVT() != MemVT) 7646 break; 7647 7648 // We do not allow unaligned stores because we want to prevent overriding 7649 // stores. 7650 if (Index->getAlignment()*8 != MemVT.getSizeInBits()) 7651 break; 7652 7653 // We found a potential memory operand to merge. 7654 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++)); 7655 7656 // Find the next memory operand in the chain. If the next operand in the 7657 // chain is a store then move up and continue the scan with the next 7658 // memory operand. If the next operand is a load save it and use alias 7659 // information to check if it interferes with anything. 7660 SDNode *NextInChain = Index->getChain().getNode(); 7661 while (1) { 7662 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) { 7663 // We found a store node. Use it for the next iteration. 7664 Index = STn; 7665 break; 7666 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) { 7667 // Save the load node for later. Continue the scan. 7668 AliasLoadNodes.push_back(Ldn); 7669 NextInChain = Ldn->getChain().getNode(); 7670 continue; 7671 } else { 7672 Index = NULL; 7673 break; 7674 } 7675 } 7676 } 7677 7678 // Check if there is anything to merge. 7679 if (StoreNodes.size() < 2) 7680 return false; 7681 7682 // Sort the memory operands according to their distance from the base pointer. 7683 std::sort(StoreNodes.begin(), StoreNodes.end(), 7684 ConsecutiveMemoryChainSorter()); 7685 7686 // Scan the memory operations on the chain and find the first non-consecutive 7687 // store memory address. 7688 unsigned LastConsecutiveStore = 0; 7689 int64_t StartAddress = StoreNodes[0].OffsetFromBase; 7690 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) { 7691 7692 // Check that the addresses are consecutive starting from the second 7693 // element in the list of stores. 7694 if (i > 0) { 7695 int64_t CurrAddress = StoreNodes[i].OffsetFromBase; 7696 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7697 break; 7698 } 7699 7700 bool Alias = false; 7701 // Check if this store interferes with any of the loads that we found. 7702 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld) 7703 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) { 7704 Alias = true; 7705 break; 7706 } 7707 // We found a load that alias with this store. Stop the sequence. 7708 if (Alias) 7709 break; 7710 7711 // Mark this node as useful. 7712 LastConsecutiveStore = i; 7713 } 7714 7715 // The node with the lowest store address. 7716 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; 7717 7718 // Store the constants into memory as one consecutive store. 7719 if (!IsLoadSrc) { 7720 unsigned LastLegalType = 0; 7721 unsigned LastLegalVectorType = 0; 7722 bool NonZero = false; 7723 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7724 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7725 SDValue StoredVal = St->getValue(); 7726 7727 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) { 7728 NonZero |= !C->isNullValue(); 7729 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) { 7730 NonZero |= !C->getConstantFPValue()->isNullValue(); 7731 } else { 7732 // Non constant. 7733 break; 7734 } 7735 7736 // Find a legal type for the constant store. 7737 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7738 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7739 if (TLI.isTypeLegal(StoreTy)) 7740 LastLegalType = i+1; 7741 7742 // Find a legal type for the vector store. 7743 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7744 if (TLI.isTypeLegal(Ty)) 7745 LastLegalVectorType = i + 1; 7746 } 7747 7748 // We only use vectors if the constant is known to be zero. 7749 if (NonZero) 7750 LastLegalVectorType = 0; 7751 7752 // Check if we found a legal integer type to store. 7753 if (LastLegalType == 0 && LastLegalVectorType == 0) 7754 return false; 7755 7756 bool UseVector = LastLegalVectorType > LastLegalType; 7757 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType; 7758 7759 // Make sure we have something to merge. 7760 if (NumElem < 2) 7761 return false; 7762 7763 unsigned EarliestNodeUsed = 0; 7764 for (unsigned i=0; i < NumElem; ++i) { 7765 // Find a chain for the new wide-store operand. Notice that some 7766 // of the store nodes that we found may not be selected for inclusion 7767 // in the wide store. The chain we use needs to be the chain of the 7768 // earliest store node which is *used* and replaced by the wide store. 7769 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7770 EarliestNodeUsed = i; 7771 } 7772 7773 // The earliest Node in the DAG. 7774 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7775 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc(); 7776 7777 SDValue StoredVal; 7778 if (UseVector) { 7779 // Find a legal type for the vector store. 7780 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7781 assert(TLI.isTypeLegal(Ty) && "Illegal vector store"); 7782 StoredVal = DAG.getConstant(0, Ty); 7783 } else { 7784 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7785 APInt StoreInt(StoreBW, 0); 7786 7787 // Construct a single integer constant which is made of the smaller 7788 // constant inputs. 7789 bool IsLE = TLI.isLittleEndian(); 7790 for (unsigned i = 0; i < NumElem ; ++i) { 7791 unsigned Idx = IsLE ?(NumElem - 1 - i) : i; 7792 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode); 7793 SDValue Val = St->getValue(); 7794 StoreInt<<=ElementSizeBytes*8; 7795 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) { 7796 StoreInt|=C->getAPIntValue().zext(StoreBW); 7797 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) { 7798 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW); 7799 } else { 7800 assert(false && "Invalid constant element type"); 7801 } 7802 } 7803 7804 // Create the new Load and Store operations. 7805 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7806 StoredVal = DAG.getConstant(StoreInt, StoreTy); 7807 } 7808 7809 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal, 7810 FirstInChain->getBasePtr(), 7811 FirstInChain->getPointerInfo(), 7812 false, false, 7813 FirstInChain->getAlignment()); 7814 7815 // Replace the first store with the new store 7816 CombineTo(EarliestOp, NewStore); 7817 // Erase all other stores. 7818 for (unsigned i = 0; i < NumElem ; ++i) { 7819 if (StoreNodes[i].MemNode == EarliestOp) 7820 continue; 7821 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7822 // ReplaceAllUsesWith will replace all uses that existed when it was 7823 // called, but graph optimizations may cause new ones to appear. For 7824 // example, the case in pr14333 looks like 7825 // 7826 // St's chain -> St -> another store -> X 7827 // 7828 // And the only difference from St to the other store is the chain. 7829 // When we change it's chain to be St's chain they become identical, 7830 // get CSEed and the net result is that X is now a use of St. 7831 // Since we know that St is redundant, just iterate. 7832 while (!St->use_empty()) 7833 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain()); 7834 removeFromWorkList(St); 7835 DAG.DeleteNode(St); 7836 } 7837 7838 return true; 7839 } 7840 7841 // Below we handle the case of multiple consecutive stores that 7842 // come from multiple consecutive loads. We merge them into a single 7843 // wide load and a single wide store. 7844 7845 // Look for load nodes which are used by the stored values. 7846 SmallVector<MemOpLink, 8> LoadNodes; 7847 7848 // Find acceptable loads. Loads need to have the same chain (token factor), 7849 // must not be zext, volatile, indexed, and they must be consecutive. 7850 SDValue LdBasePtr; 7851 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7852 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7853 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue()); 7854 if (!Ld) break; 7855 7856 // Loads must only have one use. 7857 if (!Ld->hasNUsesOfValue(1, 0)) 7858 break; 7859 7860 // Check that the alignment is the same as the stores. 7861 if (Ld->getAlignment() != St->getAlignment()) 7862 break; 7863 7864 // The memory operands must not be volatile. 7865 if (Ld->isVolatile() || Ld->isIndexed()) 7866 break; 7867 7868 // We do not accept ext loads. 7869 if (Ld->getExtensionType() != ISD::NON_EXTLOAD) 7870 break; 7871 7872 // The stored memory type must be the same. 7873 if (Ld->getMemoryVT() != MemVT) 7874 break; 7875 7876 std::pair<SDValue, int64_t> LdPtr = 7877 GetPointerBaseAndOffset(Ld->getBasePtr()); 7878 7879 // If this is not the first ptr that we check. 7880 if (LdBasePtr.getNode()) { 7881 // The base ptr must be the same. 7882 if (LdPtr.first != LdBasePtr) 7883 break; 7884 } else { 7885 // Check that all other base pointers are the same as this one. 7886 LdBasePtr = LdPtr.first; 7887 } 7888 7889 // We found a potential memory operand to merge. 7890 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0)); 7891 } 7892 7893 if (LoadNodes.size() < 2) 7894 return false; 7895 7896 // Scan the memory operations on the chain and find the first non-consecutive 7897 // load memory address. These variables hold the index in the store node 7898 // array. 7899 unsigned LastConsecutiveLoad = 0; 7900 // This variable refers to the size and not index in the array. 7901 unsigned LastLegalVectorType = 0; 7902 unsigned LastLegalIntegerType = 0; 7903 StartAddress = LoadNodes[0].OffsetFromBase; 7904 SDValue FirstChain = LoadNodes[0].MemNode->getChain(); 7905 for (unsigned i = 1; i < LoadNodes.size(); ++i) { 7906 // All loads much share the same chain. 7907 if (LoadNodes[i].MemNode->getChain() != FirstChain) 7908 break; 7909 7910 int64_t CurrAddress = LoadNodes[i].OffsetFromBase; 7911 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7912 break; 7913 LastConsecutiveLoad = i; 7914 7915 // Find a legal type for the vector store. 7916 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7917 if (TLI.isTypeLegal(StoreTy)) 7918 LastLegalVectorType = i + 1; 7919 7920 // Find a legal type for the integer store. 7921 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7922 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7923 if (TLI.isTypeLegal(StoreTy)) 7924 LastLegalIntegerType = i + 1; 7925 } 7926 7927 // Only use vector types if the vector type is larger than the integer type. 7928 // If they are the same, use integers. 7929 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType; 7930 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType); 7931 7932 // We add +1 here because the LastXXX variables refer to location while 7933 // the NumElem refers to array/index size. 7934 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1; 7935 NumElem = std::min(LastLegalType, NumElem); 7936 7937 if (NumElem < 2) 7938 return false; 7939 7940 // The earliest Node in the DAG. 7941 unsigned EarliestNodeUsed = 0; 7942 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7943 for (unsigned i=1; i<NumElem; ++i) { 7944 // Find a chain for the new wide-store operand. Notice that some 7945 // of the store nodes that we found may not be selected for inclusion 7946 // in the wide store. The chain we use needs to be the chain of the 7947 // earliest store node which is *used* and replaced by the wide store. 7948 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7949 EarliestNodeUsed = i; 7950 } 7951 7952 // Find if it is better to use vectors or integers to load and store 7953 // to memory. 7954 EVT JointMemOpVT; 7955 if (UseVectorTy) { 7956 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7957 } else { 7958 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7959 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7960 } 7961 7962 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc(); 7963 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc(); 7964 7965 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode); 7966 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL, 7967 FirstLoad->getChain(), 7968 FirstLoad->getBasePtr(), 7969 FirstLoad->getPointerInfo(), 7970 false, false, false, 7971 FirstLoad->getAlignment()); 7972 7973 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad, 7974 FirstInChain->getBasePtr(), 7975 FirstInChain->getPointerInfo(), false, false, 7976 FirstInChain->getAlignment()); 7977 7978 // Replace one of the loads with the new load. 7979 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode); 7980 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), 7981 SDValue(NewLoad.getNode(), 1)); 7982 7983 // Remove the rest of the load chains. 7984 for (unsigned i = 1; i < NumElem ; ++i) { 7985 // Replace all chain users of the old load nodes with the chain of the new 7986 // load node. 7987 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode); 7988 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain()); 7989 } 7990 7991 // Replace the first store with the new store. 7992 CombineTo(EarliestOp, NewStore); 7993 // Erase all other stores. 7994 for (unsigned i = 0; i < NumElem ; ++i) { 7995 // Remove all Store nodes. 7996 if (StoreNodes[i].MemNode == EarliestOp) 7997 continue; 7998 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7999 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain()); 8000 removeFromWorkList(St); 8001 DAG.DeleteNode(St); 8002 } 8003 8004 return true; 8005} 8006 8007SDValue DAGCombiner::visitSTORE(SDNode *N) { 8008 StoreSDNode *ST = cast<StoreSDNode>(N); 8009 SDValue Chain = ST->getChain(); 8010 SDValue Value = ST->getValue(); 8011 SDValue Ptr = ST->getBasePtr(); 8012 8013 // If this is a store of a bit convert, store the input value if the 8014 // resultant store does not need a higher alignment than the original. 8015 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 8016 ST->isUnindexed()) { 8017 unsigned OrigAlign = ST->getAlignment(); 8018 EVT SVT = Value.getOperand(0).getValueType(); 8019 unsigned Align = TLI.getDataLayout()-> 8020 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 8021 if (Align <= OrigAlign && 8022 ((!LegalOperations && !ST->isVolatile()) || 8023 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 8024 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8025 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8026 ST->isNonTemporal(), OrigAlign); 8027 } 8028 8029 // Turn 'store undef, Ptr' -> nothing. 8030 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 8031 return Chain; 8032 8033 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 8034 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 8035 // NOTE: If the original store is volatile, this transform must not increase 8036 // the number of stores. For example, on x86-32 an f64 can be stored in one 8037 // processor operation but an i64 (which is not legal) requires two. So the 8038 // transform should not be done in this case. 8039 if (Value.getOpcode() != ISD::TargetConstantFP) { 8040 SDValue Tmp; 8041 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 8042 default: llvm_unreachable("Unknown FP type"); 8043 case MVT::f16: // We don't do this for these yet. 8044 case MVT::f80: 8045 case MVT::f128: 8046 case MVT::ppcf128: 8047 break; 8048 case MVT::f32: 8049 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 8050 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8051 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 8052 bitcastToAPInt().getZExtValue(), MVT::i32); 8053 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 8054 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8055 ST->isNonTemporal(), ST->getAlignment()); 8056 } 8057 break; 8058 case MVT::f64: 8059 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 8060 !ST->isVolatile()) || 8061 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 8062 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 8063 getZExtValue(), MVT::i64); 8064 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 8065 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8066 ST->isNonTemporal(), ST->getAlignment()); 8067 } 8068 8069 if (!ST->isVolatile() && 8070 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8071 // Many FP stores are not made apparent until after legalize, e.g. for 8072 // argument passing. Since this is so common, custom legalize the 8073 // 64-bit integer store into two 32-bit stores. 8074 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 8075 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 8076 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 8077 if (TLI.isBigEndian()) std::swap(Lo, Hi); 8078 8079 unsigned Alignment = ST->getAlignment(); 8080 bool isVolatile = ST->isVolatile(); 8081 bool isNonTemporal = ST->isNonTemporal(); 8082 8083 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 8084 Ptr, ST->getPointerInfo(), 8085 isVolatile, isNonTemporal, 8086 ST->getAlignment()); 8087 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 8088 DAG.getConstant(4, Ptr.getValueType())); 8089 Alignment = MinAlign(Alignment, 4U); 8090 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 8091 Ptr, ST->getPointerInfo().getWithOffset(4), 8092 isVolatile, isNonTemporal, 8093 Alignment); 8094 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8095 St0, St1); 8096 } 8097 8098 break; 8099 } 8100 } 8101 } 8102 8103 // Try to infer better alignment information than the store already has. 8104 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 8105 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 8106 if (Align > ST->getAlignment()) 8107 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 8108 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8109 ST->isVolatile(), ST->isNonTemporal(), Align); 8110 } 8111 } 8112 8113 // Try transforming a pair floating point load / store ops to integer 8114 // load / store ops. 8115 SDValue NewST = TransformFPLoadStorePair(N); 8116 if (NewST.getNode()) 8117 return NewST; 8118 8119 if (CombinerAA) { 8120 // Walk up chain skipping non-aliasing memory nodes. 8121 SDValue BetterChain = FindBetterChain(N, Chain); 8122 8123 // If there is a better chain. 8124 if (Chain != BetterChain) { 8125 SDValue ReplStore; 8126 8127 // Replace the chain to avoid dependency. 8128 if (ST->isTruncatingStore()) { 8129 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8130 ST->getPointerInfo(), 8131 ST->getMemoryVT(), ST->isVolatile(), 8132 ST->isNonTemporal(), ST->getAlignment()); 8133 } else { 8134 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8135 ST->getPointerInfo(), 8136 ST->isVolatile(), ST->isNonTemporal(), 8137 ST->getAlignment()); 8138 } 8139 8140 // Create token to keep both nodes around. 8141 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 8142 MVT::Other, Chain, ReplStore); 8143 8144 // Make sure the new and old chains are cleaned up. 8145 AddToWorkList(Token.getNode()); 8146 8147 // Don't add users to work list. 8148 return CombineTo(N, Token, false); 8149 } 8150 } 8151 8152 // Try transforming N to an indexed store. 8153 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 8154 return SDValue(N, 0); 8155 8156 // FIXME: is there such a thing as a truncating indexed store? 8157 if (ST->isTruncatingStore() && ST->isUnindexed() && 8158 Value.getValueType().isInteger()) { 8159 // See if we can simplify the input to this truncstore with knowledge that 8160 // only the low bits are being used. For example: 8161 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 8162 SDValue Shorter = 8163 GetDemandedBits(Value, 8164 APInt::getLowBitsSet( 8165 Value.getValueType().getScalarType().getSizeInBits(), 8166 ST->getMemoryVT().getScalarType().getSizeInBits())); 8167 AddToWorkList(Value.getNode()); 8168 if (Shorter.getNode()) 8169 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 8170 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8171 ST->isVolatile(), ST->isNonTemporal(), 8172 ST->getAlignment()); 8173 8174 // Otherwise, see if we can simplify the operation with 8175 // SimplifyDemandedBits, which only works if the value has a single use. 8176 if (SimplifyDemandedBits(Value, 8177 APInt::getLowBitsSet( 8178 Value.getValueType().getScalarType().getSizeInBits(), 8179 ST->getMemoryVT().getScalarType().getSizeInBits()))) 8180 return SDValue(N, 0); 8181 } 8182 8183 // If this is a load followed by a store to the same location, then the store 8184 // is dead/noop. 8185 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 8186 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 8187 ST->isUnindexed() && !ST->isVolatile() && 8188 // There can't be any side effects between the load and store, such as 8189 // a call or store. 8190 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 8191 // The store is dead, remove it. 8192 return Chain; 8193 } 8194 } 8195 8196 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 8197 // truncating store. We can do this even if this is already a truncstore. 8198 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 8199 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 8200 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 8201 ST->getMemoryVT())) { 8202 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8203 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8204 ST->isVolatile(), ST->isNonTemporal(), 8205 ST->getAlignment()); 8206 } 8207 8208 // Only perform this optimization before the types are legal, because we 8209 // don't want to perform this optimization on every DAGCombine invocation. 8210 if (!LegalTypes) { 8211 bool EverChanged = false; 8212 8213 do { 8214 // There can be multiple store sequences on the same chain. 8215 // Keep trying to merge store sequences until we are unable to do so 8216 // or until we merge the last store on the chain. 8217 bool Changed = MergeConsecutiveStores(ST); 8218 EverChanged |= Changed; 8219 if (!Changed) break; 8220 } while (ST->getOpcode() != ISD::DELETED_NODE); 8221 8222 if (EverChanged) 8223 return SDValue(N, 0); 8224 } 8225 8226 return ReduceLoadOpStoreWidth(N); 8227} 8228 8229SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 8230 SDValue InVec = N->getOperand(0); 8231 SDValue InVal = N->getOperand(1); 8232 SDValue EltNo = N->getOperand(2); 8233 DebugLoc dl = N->getDebugLoc(); 8234 8235 // If the inserted element is an UNDEF, just use the input vector. 8236 if (InVal.getOpcode() == ISD::UNDEF) 8237 return InVec; 8238 8239 EVT VT = InVec.getValueType(); 8240 8241 // If we can't generate a legal BUILD_VECTOR, exit 8242 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 8243 return SDValue(); 8244 8245 // Check that we know which element is being inserted 8246 if (!isa<ConstantSDNode>(EltNo)) 8247 return SDValue(); 8248 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8249 8250 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 8251 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 8252 // vector elements. 8253 SmallVector<SDValue, 8> Ops; 8254 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 8255 Ops.append(InVec.getNode()->op_begin(), 8256 InVec.getNode()->op_end()); 8257 } else if (InVec.getOpcode() == ISD::UNDEF) { 8258 unsigned NElts = VT.getVectorNumElements(); 8259 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 8260 } else { 8261 return SDValue(); 8262 } 8263 8264 // Insert the element 8265 if (Elt < Ops.size()) { 8266 // All the operands of BUILD_VECTOR must have the same type; 8267 // we enforce that here. 8268 EVT OpVT = Ops[0].getValueType(); 8269 if (InVal.getValueType() != OpVT) 8270 InVal = OpVT.bitsGT(InVal.getValueType()) ? 8271 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 8272 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 8273 Ops[Elt] = InVal; 8274 } 8275 8276 // Return the new vector 8277 return DAG.getNode(ISD::BUILD_VECTOR, dl, 8278 VT, &Ops[0], Ops.size()); 8279} 8280 8281SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 8282 // (vextract (scalar_to_vector val, 0) -> val 8283 SDValue InVec = N->getOperand(0); 8284 EVT VT = InVec.getValueType(); 8285 EVT NVT = N->getValueType(0); 8286 8287 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 8288 // Check if the result type doesn't match the inserted element type. A 8289 // SCALAR_TO_VECTOR may truncate the inserted element and the 8290 // EXTRACT_VECTOR_ELT may widen the extracted vector. 8291 SDValue InOp = InVec.getOperand(0); 8292 if (InOp.getValueType() != NVT) { 8293 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 8294 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 8295 } 8296 return InOp; 8297 } 8298 8299 SDValue EltNo = N->getOperand(1); 8300 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 8301 8302 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 8303 // We only perform this optimization before the op legalization phase because 8304 // we may introduce new vector instructions which are not backed by TD 8305 // patterns. For example on AVX, extracting elements from a wide vector 8306 // without using extract_subvector. 8307 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 8308 && ConstEltNo && !LegalOperations) { 8309 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8310 int NumElem = VT.getVectorNumElements(); 8311 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 8312 // Find the new index to extract from. 8313 int OrigElt = SVOp->getMaskElt(Elt); 8314 8315 // Extracting an undef index is undef. 8316 if (OrigElt == -1) 8317 return DAG.getUNDEF(NVT); 8318 8319 // Select the right vector half to extract from. 8320 if (OrigElt < NumElem) { 8321 InVec = InVec->getOperand(0); 8322 } else { 8323 InVec = InVec->getOperand(1); 8324 OrigElt -= NumElem; 8325 } 8326 8327 EVT IndexTy = N->getOperand(1).getValueType(); 8328 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 8329 InVec, DAG.getConstant(OrigElt, IndexTy)); 8330 } 8331 8332 // Perform only after legalization to ensure build_vector / vector_shuffle 8333 // optimizations have already been done. 8334 if (!LegalOperations) return SDValue(); 8335 8336 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 8337 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 8338 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 8339 8340 if (ConstEltNo) { 8341 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8342 bool NewLoad = false; 8343 bool BCNumEltsChanged = false; 8344 EVT ExtVT = VT.getVectorElementType(); 8345 EVT LVT = ExtVT; 8346 8347 // If the result of load has to be truncated, then it's not necessarily 8348 // profitable. 8349 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 8350 return SDValue(); 8351 8352 if (InVec.getOpcode() == ISD::BITCAST) { 8353 // Don't duplicate a load with other uses. 8354 if (!InVec.hasOneUse()) 8355 return SDValue(); 8356 8357 EVT BCVT = InVec.getOperand(0).getValueType(); 8358 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 8359 return SDValue(); 8360 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 8361 BCNumEltsChanged = true; 8362 InVec = InVec.getOperand(0); 8363 ExtVT = BCVT.getVectorElementType(); 8364 NewLoad = true; 8365 } 8366 8367 LoadSDNode *LN0 = NULL; 8368 const ShuffleVectorSDNode *SVN = NULL; 8369 if (ISD::isNormalLoad(InVec.getNode())) { 8370 LN0 = cast<LoadSDNode>(InVec); 8371 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 8372 InVec.getOperand(0).getValueType() == ExtVT && 8373 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 8374 // Don't duplicate a load with other uses. 8375 if (!InVec.hasOneUse()) 8376 return SDValue(); 8377 8378 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 8379 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 8380 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 8381 // => 8382 // (load $addr+1*size) 8383 8384 // Don't duplicate a load with other uses. 8385 if (!InVec.hasOneUse()) 8386 return SDValue(); 8387 8388 // If the bit convert changed the number of elements, it is unsafe 8389 // to examine the mask. 8390 if (BCNumEltsChanged) 8391 return SDValue(); 8392 8393 // Select the input vector, guarding against out of range extract vector. 8394 unsigned NumElems = VT.getVectorNumElements(); 8395 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 8396 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 8397 8398 if (InVec.getOpcode() == ISD::BITCAST) { 8399 // Don't duplicate a load with other uses. 8400 if (!InVec.hasOneUse()) 8401 return SDValue(); 8402 8403 InVec = InVec.getOperand(0); 8404 } 8405 if (ISD::isNormalLoad(InVec.getNode())) { 8406 LN0 = cast<LoadSDNode>(InVec); 8407 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 8408 } 8409 } 8410 8411 // Make sure we found a non-volatile load and the extractelement is 8412 // the only use. 8413 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 8414 return SDValue(); 8415 8416 // If Idx was -1 above, Elt is going to be -1, so just return undef. 8417 if (Elt == -1) 8418 return DAG.getUNDEF(LVT); 8419 8420 unsigned Align = LN0->getAlignment(); 8421 if (NewLoad) { 8422 // Check the resultant load doesn't need a higher alignment than the 8423 // original load. 8424 unsigned NewAlign = 8425 TLI.getDataLayout() 8426 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 8427 8428 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 8429 return SDValue(); 8430 8431 Align = NewAlign; 8432 } 8433 8434 SDValue NewPtr = LN0->getBasePtr(); 8435 unsigned PtrOff = 0; 8436 8437 if (Elt) { 8438 PtrOff = LVT.getSizeInBits() * Elt / 8; 8439 EVT PtrType = NewPtr.getValueType(); 8440 if (TLI.isBigEndian()) 8441 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 8442 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 8443 DAG.getConstant(PtrOff, PtrType)); 8444 } 8445 8446 // The replacement we need to do here is a little tricky: we need to 8447 // replace an extractelement of a load with a load. 8448 // Use ReplaceAllUsesOfValuesWith to do the replacement. 8449 // Note that this replacement assumes that the extractvalue is the only 8450 // use of the load; that's okay because we don't want to perform this 8451 // transformation in other cases anyway. 8452 SDValue Load; 8453 SDValue Chain; 8454 if (NVT.bitsGT(LVT)) { 8455 // If the result type of vextract is wider than the load, then issue an 8456 // extending load instead. 8457 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 8458 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 8459 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 8460 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 8461 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 8462 Chain = Load.getValue(1); 8463 } else { 8464 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 8465 LN0->getPointerInfo().getWithOffset(PtrOff), 8466 LN0->isVolatile(), LN0->isNonTemporal(), 8467 LN0->isInvariant(), Align); 8468 Chain = Load.getValue(1); 8469 if (NVT.bitsLT(LVT)) 8470 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 8471 else 8472 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 8473 } 8474 WorkListRemover DeadNodes(*this); 8475 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 8476 SDValue To[] = { Load, Chain }; 8477 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 8478 // Since we're explcitly calling ReplaceAllUses, add the new node to the 8479 // worklist explicitly as well. 8480 AddToWorkList(Load.getNode()); 8481 AddUsersToWorkList(Load.getNode()); // Add users too 8482 // Make sure to revisit this node to clean it up; it will usually be dead. 8483 AddToWorkList(N); 8484 return SDValue(N, 0); 8485 } 8486 8487 return SDValue(); 8488} 8489 8490// Simplify (build_vec (ext )) to (bitcast (build_vec )) 8491SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) { 8492 // We perform this optimization post type-legalization because 8493 // the type-legalizer often scalarizes integer-promoted vectors. 8494 // Performing this optimization before may create bit-casts which 8495 // will be type-legalized to complex code sequences. 8496 // We perform this optimization only before the operation legalizer because we 8497 // may introduce illegal operations. 8498 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) 8499 return SDValue(); 8500 8501 unsigned NumInScalars = N->getNumOperands(); 8502 DebugLoc dl = N->getDebugLoc(); 8503 EVT VT = N->getValueType(0); 8504 8505 // Check to see if this is a BUILD_VECTOR of a bunch of values 8506 // which come from any_extend or zero_extend nodes. If so, we can create 8507 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 8508 // optimizations. We do not handle sign-extend because we can't fill the sign 8509 // using shuffles. 8510 EVT SourceType = MVT::Other; 8511 bool AllAnyExt = true; 8512 8513 for (unsigned i = 0; i != NumInScalars; ++i) { 8514 SDValue In = N->getOperand(i); 8515 // Ignore undef inputs. 8516 if (In.getOpcode() == ISD::UNDEF) continue; 8517 8518 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 8519 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 8520 8521 // Abort if the element is not an extension. 8522 if (!ZeroExt && !AnyExt) { 8523 SourceType = MVT::Other; 8524 break; 8525 } 8526 8527 // The input is a ZeroExt or AnyExt. Check the original type. 8528 EVT InTy = In.getOperand(0).getValueType(); 8529 8530 // Check that all of the widened source types are the same. 8531 if (SourceType == MVT::Other) 8532 // First time. 8533 SourceType = InTy; 8534 else if (InTy != SourceType) { 8535 // Multiple income types. Abort. 8536 SourceType = MVT::Other; 8537 break; 8538 } 8539 8540 // Check if all of the extends are ANY_EXTENDs. 8541 AllAnyExt &= AnyExt; 8542 } 8543 8544 // In order to have valid types, all of the inputs must be extended from the 8545 // same source type and all of the inputs must be any or zero extend. 8546 // Scalar sizes must be a power of two. 8547 EVT OutScalarTy = VT.getScalarType(); 8548 bool ValidTypes = SourceType != MVT::Other && 8549 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 8550 isPowerOf2_32(SourceType.getSizeInBits()); 8551 8552 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 8553 // turn into a single shuffle instruction. 8554 if (!ValidTypes) 8555 return SDValue(); 8556 8557 bool isLE = TLI.isLittleEndian(); 8558 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 8559 assert(ElemRatio > 1 && "Invalid element size ratio"); 8560 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 8561 DAG.getConstant(0, SourceType); 8562 8563 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements(); 8564 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 8565 8566 // Populate the new build_vector 8567 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 8568 SDValue Cast = N->getOperand(i); 8569 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 8570 Cast.getOpcode() == ISD::ZERO_EXTEND || 8571 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 8572 SDValue In; 8573 if (Cast.getOpcode() == ISD::UNDEF) 8574 In = DAG.getUNDEF(SourceType); 8575 else 8576 In = Cast->getOperand(0); 8577 unsigned Index = isLE ? (i * ElemRatio) : 8578 (i * ElemRatio + (ElemRatio - 1)); 8579 8580 assert(Index < Ops.size() && "Invalid index"); 8581 Ops[Index] = In; 8582 } 8583 8584 // The type of the new BUILD_VECTOR node. 8585 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 8586 assert(VecVT.getSizeInBits() == VT.getSizeInBits() && 8587 "Invalid vector size"); 8588 // Check if the new vector type is legal. 8589 if (!isTypeLegal(VecVT)) return SDValue(); 8590 8591 // Make the new BUILD_VECTOR. 8592 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size()); 8593 8594 // The new BUILD_VECTOR node has the potential to be further optimized. 8595 AddToWorkList(BV.getNode()); 8596 // Bitcast to the desired type. 8597 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 8598} 8599 8600SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) { 8601 EVT VT = N->getValueType(0); 8602 8603 unsigned NumInScalars = N->getNumOperands(); 8604 DebugLoc dl = N->getDebugLoc(); 8605 8606 EVT SrcVT = MVT::Other; 8607 unsigned Opcode = ISD::DELETED_NODE; 8608 unsigned NumDefs = 0; 8609 8610 for (unsigned i = 0; i != NumInScalars; ++i) { 8611 SDValue In = N->getOperand(i); 8612 unsigned Opc = In.getOpcode(); 8613 8614 if (Opc == ISD::UNDEF) 8615 continue; 8616 8617 // If all scalar values are floats and converted from integers. 8618 if (Opcode == ISD::DELETED_NODE && 8619 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { 8620 Opcode = Opc; 8621 // If not supported by target, bail out. 8622 if (TLI.getOperationAction(Opcode, VT) != TargetLowering::Legal && 8623 TLI.getOperationAction(Opcode, VT) != TargetLowering::Custom) 8624 return SDValue(); 8625 } 8626 if (Opc != Opcode) 8627 return SDValue(); 8628 8629 EVT InVT = In.getOperand(0).getValueType(); 8630 8631 // If all scalar values are typed differently, bail out. It's chosen to 8632 // simplify BUILD_VECTOR of integer types. 8633 if (SrcVT == MVT::Other) 8634 SrcVT = InVT; 8635 if (SrcVT != InVT) 8636 return SDValue(); 8637 NumDefs++; 8638 } 8639 8640 // If the vector has just one element defined, it's not worth to fold it into 8641 // a vectorized one. 8642 if (NumDefs < 2) 8643 return SDValue(); 8644 8645 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) 8646 && "Should only handle conversion from integer to float."); 8647 assert(SrcVT != MVT::Other && "Cannot determine source type!"); 8648 8649 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars); 8650 SmallVector<SDValue, 8> Opnds; 8651 for (unsigned i = 0; i != NumInScalars; ++i) { 8652 SDValue In = N->getOperand(i); 8653 8654 if (In.getOpcode() == ISD::UNDEF) 8655 Opnds.push_back(DAG.getUNDEF(SrcVT)); 8656 else 8657 Opnds.push_back(In.getOperand(0)); 8658 } 8659 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, 8660 &Opnds[0], Opnds.size()); 8661 AddToWorkList(BV.getNode()); 8662 8663 return DAG.getNode(Opcode, dl, VT, BV); 8664} 8665 8666SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 8667 unsigned NumInScalars = N->getNumOperands(); 8668 DebugLoc dl = N->getDebugLoc(); 8669 EVT VT = N->getValueType(0); 8670 8671 // A vector built entirely of undefs is undef. 8672 if (ISD::allOperandsUndef(N)) 8673 return DAG.getUNDEF(VT); 8674 8675 SDValue V = reduceBuildVecExtToExtBuildVec(N); 8676 if (V.getNode()) 8677 return V; 8678 8679 V = reduceBuildVecConvertToConvertBuildVec(N); 8680 if (V.getNode()) 8681 return V; 8682 8683 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 8684 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 8685 // at most two distinct vectors, turn this into a shuffle node. 8686 8687 // May only combine to shuffle after legalize if shuffle is legal. 8688 if (LegalOperations && 8689 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 8690 return SDValue(); 8691 8692 SDValue VecIn1, VecIn2; 8693 for (unsigned i = 0; i != NumInScalars; ++i) { 8694 // Ignore undef inputs. 8695 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 8696 8697 // If this input is something other than a EXTRACT_VECTOR_ELT with a 8698 // constant index, bail out. 8699 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 8700 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 8701 VecIn1 = VecIn2 = SDValue(0, 0); 8702 break; 8703 } 8704 8705 // We allow up to two distinct input vectors. 8706 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 8707 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 8708 continue; 8709 8710 if (VecIn1.getNode() == 0) { 8711 VecIn1 = ExtractedFromVec; 8712 } else if (VecIn2.getNode() == 0) { 8713 VecIn2 = ExtractedFromVec; 8714 } else { 8715 // Too many inputs. 8716 VecIn1 = VecIn2 = SDValue(0, 0); 8717 break; 8718 } 8719 } 8720 8721 // If everything is good, we can make a shuffle operation. 8722 if (VecIn1.getNode()) { 8723 SmallVector<int, 8> Mask; 8724 for (unsigned i = 0; i != NumInScalars; ++i) { 8725 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 8726 Mask.push_back(-1); 8727 continue; 8728 } 8729 8730 // If extracting from the first vector, just use the index directly. 8731 SDValue Extract = N->getOperand(i); 8732 SDValue ExtVal = Extract.getOperand(1); 8733 if (Extract.getOperand(0) == VecIn1) { 8734 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8735 if (ExtIndex > VT.getVectorNumElements()) 8736 return SDValue(); 8737 8738 Mask.push_back(ExtIndex); 8739 continue; 8740 } 8741 8742 // Otherwise, use InIdx + VecSize 8743 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8744 Mask.push_back(Idx+NumInScalars); 8745 } 8746 8747 // We can't generate a shuffle node with mismatched input and output types. 8748 // Attempt to transform a single input vector to the correct type. 8749 if ((VT != VecIn1.getValueType())) { 8750 // We don't support shuffeling between TWO values of different types. 8751 if (VecIn2.getNode() != 0) 8752 return SDValue(); 8753 8754 // We only support widening of vectors which are half the size of the 8755 // output registers. For example XMM->YMM widening on X86 with AVX. 8756 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 8757 return SDValue(); 8758 8759 // If the input vector type has a different base type to the output 8760 // vector type, bail out. 8761 if (VecIn1.getValueType().getVectorElementType() != 8762 VT.getVectorElementType()) 8763 return SDValue(); 8764 8765 // Widen the input vector by adding undef values. 8766 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8767 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 8768 } 8769 8770 // If VecIn2 is unused then change it to undef. 8771 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 8772 8773 // Check that we were able to transform all incoming values to the same 8774 // type. 8775 if (VecIn2.getValueType() != VecIn1.getValueType() || 8776 VecIn1.getValueType() != VT) 8777 return SDValue(); 8778 8779 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 8780 if (!isTypeLegal(VT)) 8781 return SDValue(); 8782 8783 // Return the new VECTOR_SHUFFLE node. 8784 SDValue Ops[2]; 8785 Ops[0] = VecIn1; 8786 Ops[1] = VecIn2; 8787 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]); 8788 } 8789 8790 return SDValue(); 8791} 8792 8793SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 8794 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 8795 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 8796 // inputs come from at most two distinct vectors, turn this into a shuffle 8797 // node. 8798 8799 // If we only have one input vector, we don't need to do any concatenation. 8800 if (N->getNumOperands() == 1) 8801 return N->getOperand(0); 8802 8803 // Check if all of the operands are undefs. 8804 if (ISD::allOperandsUndef(N)) 8805 return DAG.getUNDEF(N->getValueType(0)); 8806 8807 return SDValue(); 8808} 8809 8810SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 8811 EVT NVT = N->getValueType(0); 8812 SDValue V = N->getOperand(0); 8813 8814 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 8815 // Handle only simple case where vector being inserted and vector 8816 // being extracted are of same type, and are half size of larger vectors. 8817 EVT BigVT = V->getOperand(0).getValueType(); 8818 EVT SmallVT = V->getOperand(1).getValueType(); 8819 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 8820 return SDValue(); 8821 8822 // Only handle cases where both indexes are constants with the same type. 8823 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8824 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 8825 8826 if (InsIdx && ExtIdx && 8827 InsIdx->getValueType(0).getSizeInBits() <= 64 && 8828 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 8829 // Combine: 8830 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 8831 // Into: 8832 // indices are equal => V1 8833 // otherwise => (extract_subvec V1, ExtIdx) 8834 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 8835 return V->getOperand(1); 8836 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 8837 V->getOperand(0), N->getOperand(1)); 8838 } 8839 } 8840 8841 if (V->getOpcode() == ISD::CONCAT_VECTORS) { 8842 // Combine: 8843 // (extract_subvec (concat V1, V2, ...), i) 8844 // Into: 8845 // Vi if possible 8846 // Only operand 0 is checked as 'concat' assumes all inputs of the same type. 8847 if (V->getOperand(0).getValueType() != NVT) 8848 return SDValue(); 8849 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 8850 unsigned NumElems = NVT.getVectorNumElements(); 8851 assert((Idx % NumElems) == 0 && 8852 "IDX in concat is not a multiple of the result vector length."); 8853 return V->getOperand(Idx / NumElems); 8854 } 8855 8856 return SDValue(); 8857} 8858 8859SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 8860 EVT VT = N->getValueType(0); 8861 unsigned NumElts = VT.getVectorNumElements(); 8862 8863 SDValue N0 = N->getOperand(0); 8864 SDValue N1 = N->getOperand(1); 8865 8866 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 8867 8868 // Canonicalize shuffle undef, undef -> undef 8869 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 8870 return DAG.getUNDEF(VT); 8871 8872 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8873 8874 // Canonicalize shuffle v, v -> v, undef 8875 if (N0 == N1) { 8876 SmallVector<int, 8> NewMask; 8877 for (unsigned i = 0; i != NumElts; ++i) { 8878 int Idx = SVN->getMaskElt(i); 8879 if (Idx >= (int)NumElts) Idx -= NumElts; 8880 NewMask.push_back(Idx); 8881 } 8882 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 8883 &NewMask[0]); 8884 } 8885 8886 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 8887 if (N0.getOpcode() == ISD::UNDEF) { 8888 SmallVector<int, 8> NewMask; 8889 for (unsigned i = 0; i != NumElts; ++i) { 8890 int Idx = SVN->getMaskElt(i); 8891 if (Idx >= 0) { 8892 if (Idx < (int)NumElts) 8893 Idx += NumElts; 8894 else 8895 Idx -= NumElts; 8896 } 8897 NewMask.push_back(Idx); 8898 } 8899 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 8900 &NewMask[0]); 8901 } 8902 8903 // Remove references to rhs if it is undef 8904 if (N1.getOpcode() == ISD::UNDEF) { 8905 bool Changed = false; 8906 SmallVector<int, 8> NewMask; 8907 for (unsigned i = 0; i != NumElts; ++i) { 8908 int Idx = SVN->getMaskElt(i); 8909 if (Idx >= (int)NumElts) { 8910 Idx = -1; 8911 Changed = true; 8912 } 8913 NewMask.push_back(Idx); 8914 } 8915 if (Changed) 8916 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 8917 } 8918 8919 // If it is a splat, check if the argument vector is another splat or a 8920 // build_vector with all scalar elements the same. 8921 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 8922 SDNode *V = N0.getNode(); 8923 8924 // If this is a bit convert that changes the element type of the vector but 8925 // not the number of vector elements, look through it. Be careful not to 8926 // look though conversions that change things like v4f32 to v2f64. 8927 if (V->getOpcode() == ISD::BITCAST) { 8928 SDValue ConvInput = V->getOperand(0); 8929 if (ConvInput.getValueType().isVector() && 8930 ConvInput.getValueType().getVectorNumElements() == NumElts) 8931 V = ConvInput.getNode(); 8932 } 8933 8934 if (V->getOpcode() == ISD::BUILD_VECTOR) { 8935 assert(V->getNumOperands() == NumElts && 8936 "BUILD_VECTOR has wrong number of operands"); 8937 SDValue Base; 8938 bool AllSame = true; 8939 for (unsigned i = 0; i != NumElts; ++i) { 8940 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 8941 Base = V->getOperand(i); 8942 break; 8943 } 8944 } 8945 // Splat of <u, u, u, u>, return <u, u, u, u> 8946 if (!Base.getNode()) 8947 return N0; 8948 for (unsigned i = 0; i != NumElts; ++i) { 8949 if (V->getOperand(i) != Base) { 8950 AllSame = false; 8951 break; 8952 } 8953 } 8954 // Splat of <x, x, x, x>, return <x, x, x, x> 8955 if (AllSame) 8956 return N0; 8957 } 8958 } 8959 8960 // If this shuffle node is simply a swizzle of another shuffle node, 8961 // and it reverses the swizzle of the previous shuffle then we can 8962 // optimize shuffle(shuffle(x, undef), undef) -> x. 8963 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 8964 N1.getOpcode() == ISD::UNDEF) { 8965 8966 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 8967 8968 // Shuffle nodes can only reverse shuffles with a single non-undef value. 8969 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 8970 return SDValue(); 8971 8972 // The incoming shuffle must be of the same type as the result of the 8973 // current shuffle. 8974 assert(OtherSV->getOperand(0).getValueType() == VT && 8975 "Shuffle types don't match"); 8976 8977 for (unsigned i = 0; i != NumElts; ++i) { 8978 int Idx = SVN->getMaskElt(i); 8979 assert(Idx < (int)NumElts && "Index references undef operand"); 8980 // Next, this index comes from the first value, which is the incoming 8981 // shuffle. Adopt the incoming index. 8982 if (Idx >= 0) 8983 Idx = OtherSV->getMaskElt(Idx); 8984 8985 // The combined shuffle must map each index to itself. 8986 if (Idx >= 0 && (unsigned)Idx != i) 8987 return SDValue(); 8988 } 8989 8990 return OtherSV->getOperand(0); 8991 } 8992 8993 return SDValue(); 8994} 8995 8996SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 8997 if (!TLI.getShouldFoldAtomicFences()) 8998 return SDValue(); 8999 9000 SDValue atomic = N->getOperand(0); 9001 switch (atomic.getOpcode()) { 9002 case ISD::ATOMIC_CMP_SWAP: 9003 case ISD::ATOMIC_SWAP: 9004 case ISD::ATOMIC_LOAD_ADD: 9005 case ISD::ATOMIC_LOAD_SUB: 9006 case ISD::ATOMIC_LOAD_AND: 9007 case ISD::ATOMIC_LOAD_OR: 9008 case ISD::ATOMIC_LOAD_XOR: 9009 case ISD::ATOMIC_LOAD_NAND: 9010 case ISD::ATOMIC_LOAD_MIN: 9011 case ISD::ATOMIC_LOAD_MAX: 9012 case ISD::ATOMIC_LOAD_UMIN: 9013 case ISD::ATOMIC_LOAD_UMAX: 9014 break; 9015 default: 9016 return SDValue(); 9017 } 9018 9019 SDValue fence = atomic.getOperand(0); 9020 if (fence.getOpcode() != ISD::MEMBARRIER) 9021 return SDValue(); 9022 9023 switch (atomic.getOpcode()) { 9024 case ISD::ATOMIC_CMP_SWAP: 9025 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 9026 fence.getOperand(0), 9027 atomic.getOperand(1), atomic.getOperand(2), 9028 atomic.getOperand(3)), atomic.getResNo()); 9029 case ISD::ATOMIC_SWAP: 9030 case ISD::ATOMIC_LOAD_ADD: 9031 case ISD::ATOMIC_LOAD_SUB: 9032 case ISD::ATOMIC_LOAD_AND: 9033 case ISD::ATOMIC_LOAD_OR: 9034 case ISD::ATOMIC_LOAD_XOR: 9035 case ISD::ATOMIC_LOAD_NAND: 9036 case ISD::ATOMIC_LOAD_MIN: 9037 case ISD::ATOMIC_LOAD_MAX: 9038 case ISD::ATOMIC_LOAD_UMIN: 9039 case ISD::ATOMIC_LOAD_UMAX: 9040 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 9041 fence.getOperand(0), 9042 atomic.getOperand(1), atomic.getOperand(2)), 9043 atomic.getResNo()); 9044 default: 9045 return SDValue(); 9046 } 9047} 9048 9049/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 9050/// an AND to a vector_shuffle with the destination vector and a zero vector. 9051/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 9052/// vector_shuffle V, Zero, <0, 4, 2, 4> 9053SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 9054 EVT VT = N->getValueType(0); 9055 DebugLoc dl = N->getDebugLoc(); 9056 SDValue LHS = N->getOperand(0); 9057 SDValue RHS = N->getOperand(1); 9058 if (N->getOpcode() == ISD::AND) { 9059 if (RHS.getOpcode() == ISD::BITCAST) 9060 RHS = RHS.getOperand(0); 9061 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 9062 SmallVector<int, 8> Indices; 9063 unsigned NumElts = RHS.getNumOperands(); 9064 for (unsigned i = 0; i != NumElts; ++i) { 9065 SDValue Elt = RHS.getOperand(i); 9066 if (!isa<ConstantSDNode>(Elt)) 9067 return SDValue(); 9068 9069 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 9070 Indices.push_back(i); 9071 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 9072 Indices.push_back(NumElts); 9073 else 9074 return SDValue(); 9075 } 9076 9077 // Let's see if the target supports this vector_shuffle. 9078 EVT RVT = RHS.getValueType(); 9079 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 9080 return SDValue(); 9081 9082 // Return the new VECTOR_SHUFFLE node. 9083 EVT EltVT = RVT.getVectorElementType(); 9084 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 9085 DAG.getConstant(0, EltVT)); 9086 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9087 RVT, &ZeroOps[0], ZeroOps.size()); 9088 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 9089 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 9090 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 9091 } 9092 } 9093 9094 return SDValue(); 9095} 9096 9097/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 9098SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 9099 // After legalize, the target may be depending on adds and other 9100 // binary ops to provide legal ways to construct constants or other 9101 // things. Simplifying them may result in a loss of legality. 9102 if (LegalOperations) return SDValue(); 9103 9104 assert(N->getValueType(0).isVector() && 9105 "SimplifyVBinOp only works on vectors!"); 9106 9107 SDValue LHS = N->getOperand(0); 9108 SDValue RHS = N->getOperand(1); 9109 SDValue Shuffle = XformToShuffleWithZero(N); 9110 if (Shuffle.getNode()) return Shuffle; 9111 9112 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 9113 // this operation. 9114 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 9115 RHS.getOpcode() == ISD::BUILD_VECTOR) { 9116 SmallVector<SDValue, 8> Ops; 9117 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 9118 SDValue LHSOp = LHS.getOperand(i); 9119 SDValue RHSOp = RHS.getOperand(i); 9120 // If these two elements can't be folded, bail out. 9121 if ((LHSOp.getOpcode() != ISD::UNDEF && 9122 LHSOp.getOpcode() != ISD::Constant && 9123 LHSOp.getOpcode() != ISD::ConstantFP) || 9124 (RHSOp.getOpcode() != ISD::UNDEF && 9125 RHSOp.getOpcode() != ISD::Constant && 9126 RHSOp.getOpcode() != ISD::ConstantFP)) 9127 break; 9128 9129 // Can't fold divide by zero. 9130 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 9131 N->getOpcode() == ISD::FDIV) { 9132 if ((RHSOp.getOpcode() == ISD::Constant && 9133 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 9134 (RHSOp.getOpcode() == ISD::ConstantFP && 9135 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 9136 break; 9137 } 9138 9139 EVT VT = LHSOp.getValueType(); 9140 EVT RVT = RHSOp.getValueType(); 9141 if (RVT != VT) { 9142 // Integer BUILD_VECTOR operands may have types larger than the element 9143 // size (e.g., when the element type is not legal). Prior to type 9144 // legalization, the types may not match between the two BUILD_VECTORS. 9145 // Truncate one of the operands to make them match. 9146 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 9147 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 9148 } else { 9149 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 9150 VT = RVT; 9151 } 9152 } 9153 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 9154 LHSOp, RHSOp); 9155 if (FoldOp.getOpcode() != ISD::UNDEF && 9156 FoldOp.getOpcode() != ISD::Constant && 9157 FoldOp.getOpcode() != ISD::ConstantFP) 9158 break; 9159 Ops.push_back(FoldOp); 9160 AddToWorkList(FoldOp.getNode()); 9161 } 9162 9163 if (Ops.size() == LHS.getNumOperands()) 9164 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9165 LHS.getValueType(), &Ops[0], Ops.size()); 9166 } 9167 9168 return SDValue(); 9169} 9170 9171/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 9172SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 9173 // After legalize, the target may be depending on adds and other 9174 // binary ops to provide legal ways to construct constants or other 9175 // things. Simplifying them may result in a loss of legality. 9176 if (LegalOperations) return SDValue(); 9177 9178 assert(N->getValueType(0).isVector() && 9179 "SimplifyVUnaryOp only works on vectors!"); 9180 9181 SDValue N0 = N->getOperand(0); 9182 9183 if (N0.getOpcode() != ISD::BUILD_VECTOR) 9184 return SDValue(); 9185 9186 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 9187 SmallVector<SDValue, 8> Ops; 9188 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 9189 SDValue Op = N0.getOperand(i); 9190 if (Op.getOpcode() != ISD::UNDEF && 9191 Op.getOpcode() != ISD::ConstantFP) 9192 break; 9193 EVT EltVT = Op.getValueType(); 9194 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op); 9195 if (FoldOp.getOpcode() != ISD::UNDEF && 9196 FoldOp.getOpcode() != ISD::ConstantFP) 9197 break; 9198 Ops.push_back(FoldOp); 9199 AddToWorkList(FoldOp.getNode()); 9200 } 9201 9202 if (Ops.size() != N0.getNumOperands()) 9203 return SDValue(); 9204 9205 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9206 N0.getValueType(), &Ops[0], Ops.size()); 9207} 9208 9209SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 9210 SDValue N1, SDValue N2){ 9211 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 9212 9213 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 9214 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 9215 9216 // If we got a simplified select_cc node back from SimplifySelectCC, then 9217 // break it down into a new SETCC node, and a new SELECT node, and then return 9218 // the SELECT node, since we were called with a SELECT node. 9219 if (SCC.getNode()) { 9220 // Check to see if we got a select_cc back (to turn into setcc/select). 9221 // Otherwise, just return whatever node we got back, like fabs. 9222 if (SCC.getOpcode() == ISD::SELECT_CC) { 9223 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 9224 N0.getValueType(), 9225 SCC.getOperand(0), SCC.getOperand(1), 9226 SCC.getOperand(4)); 9227 AddToWorkList(SETCC.getNode()); 9228 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 9229 SCC.getOperand(2), SCC.getOperand(3), SETCC); 9230 } 9231 9232 return SCC; 9233 } 9234 return SDValue(); 9235} 9236 9237/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 9238/// are the two values being selected between, see if we can simplify the 9239/// select. Callers of this should assume that TheSelect is deleted if this 9240/// returns true. As such, they should return the appropriate thing (e.g. the 9241/// node) back to the top-level of the DAG combiner loop to avoid it being 9242/// looked at. 9243bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 9244 SDValue RHS) { 9245 9246 // Cannot simplify select with vector condition 9247 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 9248 9249 // If this is a select from two identical things, try to pull the operation 9250 // through the select. 9251 if (LHS.getOpcode() != RHS.getOpcode() || 9252 !LHS.hasOneUse() || !RHS.hasOneUse()) 9253 return false; 9254 9255 // If this is a load and the token chain is identical, replace the select 9256 // of two loads with a load through a select of the address to load from. 9257 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 9258 // constants have been dropped into the constant pool. 9259 if (LHS.getOpcode() == ISD::LOAD) { 9260 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 9261 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 9262 9263 // Token chains must be identical. 9264 if (LHS.getOperand(0) != RHS.getOperand(0) || 9265 // Do not let this transformation reduce the number of volatile loads. 9266 LLD->isVolatile() || RLD->isVolatile() || 9267 // If this is an EXTLOAD, the VT's must match. 9268 LLD->getMemoryVT() != RLD->getMemoryVT() || 9269 // If this is an EXTLOAD, the kind of extension must match. 9270 (LLD->getExtensionType() != RLD->getExtensionType() && 9271 // The only exception is if one of the extensions is anyext. 9272 LLD->getExtensionType() != ISD::EXTLOAD && 9273 RLD->getExtensionType() != ISD::EXTLOAD) || 9274 // FIXME: this discards src value information. This is 9275 // over-conservative. It would be beneficial to be able to remember 9276 // both potential memory locations. Since we are discarding 9277 // src value info, don't do the transformation if the memory 9278 // locations are not in the default address space. 9279 LLD->getPointerInfo().getAddrSpace() != 0 || 9280 RLD->getPointerInfo().getAddrSpace() != 0) 9281 return false; 9282 9283 // Check that the select condition doesn't reach either load. If so, 9284 // folding this will induce a cycle into the DAG. If not, this is safe to 9285 // xform, so create a select of the addresses. 9286 SDValue Addr; 9287 if (TheSelect->getOpcode() == ISD::SELECT) { 9288 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 9289 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 9290 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 9291 return false; 9292 // The loads must not depend on one another. 9293 if (LLD->isPredecessorOf(RLD) || 9294 RLD->isPredecessorOf(LLD)) 9295 return false; 9296 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 9297 LLD->getBasePtr().getValueType(), 9298 TheSelect->getOperand(0), LLD->getBasePtr(), 9299 RLD->getBasePtr()); 9300 } else { // Otherwise SELECT_CC 9301 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 9302 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 9303 9304 if ((LLD->hasAnyUseOfValue(1) && 9305 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 9306 (RLD->hasAnyUseOfValue(1) && 9307 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 9308 return false; 9309 9310 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 9311 LLD->getBasePtr().getValueType(), 9312 TheSelect->getOperand(0), 9313 TheSelect->getOperand(1), 9314 LLD->getBasePtr(), RLD->getBasePtr(), 9315 TheSelect->getOperand(4)); 9316 } 9317 9318 SDValue Load; 9319 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 9320 Load = DAG.getLoad(TheSelect->getValueType(0), 9321 TheSelect->getDebugLoc(), 9322 // FIXME: Discards pointer info. 9323 LLD->getChain(), Addr, MachinePointerInfo(), 9324 LLD->isVolatile(), LLD->isNonTemporal(), 9325 LLD->isInvariant(), LLD->getAlignment()); 9326 } else { 9327 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 9328 RLD->getExtensionType() : LLD->getExtensionType(), 9329 TheSelect->getDebugLoc(), 9330 TheSelect->getValueType(0), 9331 // FIXME: Discards pointer info. 9332 LLD->getChain(), Addr, MachinePointerInfo(), 9333 LLD->getMemoryVT(), LLD->isVolatile(), 9334 LLD->isNonTemporal(), LLD->getAlignment()); 9335 } 9336 9337 // Users of the select now use the result of the load. 9338 CombineTo(TheSelect, Load); 9339 9340 // Users of the old loads now use the new load's chain. We know the 9341 // old-load value is dead now. 9342 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 9343 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 9344 return true; 9345 } 9346 9347 return false; 9348} 9349 9350/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 9351/// where 'cond' is the comparison specified by CC. 9352SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 9353 SDValue N2, SDValue N3, 9354 ISD::CondCode CC, bool NotExtCompare) { 9355 // (x ? y : y) -> y. 9356 if (N2 == N3) return N2; 9357 9358 EVT VT = N2.getValueType(); 9359 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 9360 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 9361 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 9362 9363 // Determine if the condition we're dealing with is constant 9364 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 9365 N0, N1, CC, DL, false); 9366 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 9367 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 9368 9369 // fold select_cc true, x, y -> x 9370 if (SCCC && !SCCC->isNullValue()) 9371 return N2; 9372 // fold select_cc false, x, y -> y 9373 if (SCCC && SCCC->isNullValue()) 9374 return N3; 9375 9376 // Check to see if we can simplify the select into an fabs node 9377 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 9378 // Allow either -0.0 or 0.0 9379 if (CFP->getValueAPF().isZero()) { 9380 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 9381 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 9382 N0 == N2 && N3.getOpcode() == ISD::FNEG && 9383 N2 == N3.getOperand(0)) 9384 return DAG.getNode(ISD::FABS, DL, VT, N0); 9385 9386 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 9387 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 9388 N0 == N3 && N2.getOpcode() == ISD::FNEG && 9389 N2.getOperand(0) == N3) 9390 return DAG.getNode(ISD::FABS, DL, VT, N3); 9391 } 9392 } 9393 9394 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 9395 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 9396 // in it. This is a win when the constant is not otherwise available because 9397 // it replaces two constant pool loads with one. We only do this if the FP 9398 // type is known to be legal, because if it isn't, then we are before legalize 9399 // types an we want the other legalization to happen first (e.g. to avoid 9400 // messing with soft float) and if the ConstantFP is not legal, because if 9401 // it is legal, we may not need to store the FP constant in a constant pool. 9402 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 9403 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 9404 if (TLI.isTypeLegal(N2.getValueType()) && 9405 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 9406 TargetLowering::Legal) && 9407 // If both constants have multiple uses, then we won't need to do an 9408 // extra load, they are likely around in registers for other users. 9409 (TV->hasOneUse() || FV->hasOneUse())) { 9410 Constant *Elts[] = { 9411 const_cast<ConstantFP*>(FV->getConstantFPValue()), 9412 const_cast<ConstantFP*>(TV->getConstantFPValue()) 9413 }; 9414 Type *FPTy = Elts[0]->getType(); 9415 const DataLayout &TD = *TLI.getDataLayout(); 9416 9417 // Create a ConstantArray of the two constants. 9418 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 9419 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 9420 TD.getPrefTypeAlignment(FPTy)); 9421 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 9422 9423 // Get the offsets to the 0 and 1 element of the array so that we can 9424 // select between them. 9425 SDValue Zero = DAG.getIntPtrConstant(0); 9426 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 9427 SDValue One = DAG.getIntPtrConstant(EltSize); 9428 9429 SDValue Cond = DAG.getSetCC(DL, 9430 TLI.getSetCCResultType(N0.getValueType()), 9431 N0, N1, CC); 9432 AddToWorkList(Cond.getNode()); 9433 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 9434 Cond, One, Zero); 9435 AddToWorkList(CstOffset.getNode()); 9436 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 9437 CstOffset); 9438 AddToWorkList(CPIdx.getNode()); 9439 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 9440 MachinePointerInfo::getConstantPool(), false, 9441 false, false, Alignment); 9442 9443 } 9444 } 9445 9446 // Check to see if we can perform the "gzip trick", transforming 9447 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 9448 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 9449 (N1C->isNullValue() || // (a < 0) ? b : 0 9450 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 9451 EVT XType = N0.getValueType(); 9452 EVT AType = N2.getValueType(); 9453 if (XType.bitsGE(AType)) { 9454 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 9455 // single-bit constant. 9456 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 9457 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 9458 ShCtV = XType.getSizeInBits()-ShCtV-1; 9459 SDValue ShCt = DAG.getConstant(ShCtV, 9460 getShiftAmountTy(N0.getValueType())); 9461 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 9462 XType, N0, ShCt); 9463 AddToWorkList(Shift.getNode()); 9464 9465 if (XType.bitsGT(AType)) { 9466 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9467 AddToWorkList(Shift.getNode()); 9468 } 9469 9470 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9471 } 9472 9473 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 9474 XType, N0, 9475 DAG.getConstant(XType.getSizeInBits()-1, 9476 getShiftAmountTy(N0.getValueType()))); 9477 AddToWorkList(Shift.getNode()); 9478 9479 if (XType.bitsGT(AType)) { 9480 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9481 AddToWorkList(Shift.getNode()); 9482 } 9483 9484 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9485 } 9486 } 9487 9488 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 9489 // where y is has a single bit set. 9490 // A plaintext description would be, we can turn the SELECT_CC into an AND 9491 // when the condition can be materialized as an all-ones register. Any 9492 // single bit-test can be materialized as an all-ones register with 9493 // shift-left and shift-right-arith. 9494 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 9495 N0->getValueType(0) == VT && 9496 N1C && N1C->isNullValue() && 9497 N2C && N2C->isNullValue()) { 9498 SDValue AndLHS = N0->getOperand(0); 9499 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 9500 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 9501 // Shift the tested bit over the sign bit. 9502 APInt AndMask = ConstAndRHS->getAPIntValue(); 9503 SDValue ShlAmt = 9504 DAG.getConstant(AndMask.countLeadingZeros(), 9505 getShiftAmountTy(AndLHS.getValueType())); 9506 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 9507 9508 // Now arithmetic right shift it all the way over, so the result is either 9509 // all-ones, or zero. 9510 SDValue ShrAmt = 9511 DAG.getConstant(AndMask.getBitWidth()-1, 9512 getShiftAmountTy(Shl.getValueType())); 9513 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 9514 9515 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 9516 } 9517 } 9518 9519 // fold select C, 16, 0 -> shl C, 4 9520 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 9521 TLI.getBooleanContents(N0.getValueType().isVector()) == 9522 TargetLowering::ZeroOrOneBooleanContent) { 9523 9524 // If the caller doesn't want us to simplify this into a zext of a compare, 9525 // don't do it. 9526 if (NotExtCompare && N2C->getAPIntValue() == 1) 9527 return SDValue(); 9528 9529 // Get a SetCC of the condition 9530 // NOTE: Don't create a SETCC if it's not legal on this target. 9531 if (!LegalOperations || 9532 TLI.isOperationLegal(ISD::SETCC, 9533 LegalTypes ? TLI.getSetCCResultType(N0.getValueType()) : MVT::i1)) { 9534 SDValue Temp, SCC; 9535 // cast from setcc result type to select result type 9536 if (LegalTypes) { 9537 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 9538 N0, N1, CC); 9539 if (N2.getValueType().bitsLT(SCC.getValueType())) 9540 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), 9541 N2.getValueType()); 9542 else 9543 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9544 N2.getValueType(), SCC); 9545 } else { 9546 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 9547 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9548 N2.getValueType(), SCC); 9549 } 9550 9551 AddToWorkList(SCC.getNode()); 9552 AddToWorkList(Temp.getNode()); 9553 9554 if (N2C->getAPIntValue() == 1) 9555 return Temp; 9556 9557 // shl setcc result by log2 n2c 9558 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 9559 DAG.getConstant(N2C->getAPIntValue().logBase2(), 9560 getShiftAmountTy(Temp.getValueType()))); 9561 } 9562 } 9563 9564 // Check to see if this is the equivalent of setcc 9565 // FIXME: Turn all of these into setcc if setcc if setcc is legal 9566 // otherwise, go ahead with the folds. 9567 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 9568 EVT XType = N0.getValueType(); 9569 if (!LegalOperations || 9570 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 9571 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 9572 if (Res.getValueType() != VT) 9573 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 9574 return Res; 9575 } 9576 9577 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 9578 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 9579 (!LegalOperations || 9580 TLI.isOperationLegal(ISD::CTLZ, XType))) { 9581 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 9582 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 9583 DAG.getConstant(Log2_32(XType.getSizeInBits()), 9584 getShiftAmountTy(Ctlz.getValueType()))); 9585 } 9586 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 9587 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 9588 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 9589 XType, DAG.getConstant(0, XType), N0); 9590 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 9591 return DAG.getNode(ISD::SRL, DL, XType, 9592 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 9593 DAG.getConstant(XType.getSizeInBits()-1, 9594 getShiftAmountTy(XType))); 9595 } 9596 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 9597 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 9598 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 9599 DAG.getConstant(XType.getSizeInBits()-1, 9600 getShiftAmountTy(N0.getValueType()))); 9601 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 9602 } 9603 } 9604 9605 // Check to see if this is an integer abs. 9606 // select_cc setg[te] X, 0, X, -X -> 9607 // select_cc setgt X, -1, X, -X -> 9608 // select_cc setl[te] X, 0, -X, X -> 9609 // select_cc setlt X, 1, -X, X -> 9610 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 9611 if (N1C) { 9612 ConstantSDNode *SubC = NULL; 9613 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 9614 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 9615 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 9616 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 9617 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 9618 (N1C->isOne() && CC == ISD::SETLT)) && 9619 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 9620 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 9621 9622 EVT XType = N0.getValueType(); 9623 if (SubC && SubC->isNullValue() && XType.isInteger()) { 9624 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 9625 N0, 9626 DAG.getConstant(XType.getSizeInBits()-1, 9627 getShiftAmountTy(N0.getValueType()))); 9628 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 9629 XType, N0, Shift); 9630 AddToWorkList(Shift.getNode()); 9631 AddToWorkList(Add.getNode()); 9632 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 9633 } 9634 } 9635 9636 return SDValue(); 9637} 9638 9639/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 9640SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 9641 SDValue N1, ISD::CondCode Cond, 9642 DebugLoc DL, bool foldBooleans) { 9643 TargetLowering::DAGCombinerInfo 9644 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 9645 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 9646} 9647 9648/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 9649/// return a DAG expression to select that will generate the same value by 9650/// multiplying by a magic number. See: 9651/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9652SDValue DAGCombiner::BuildSDIV(SDNode *N) { 9653 std::vector<SDNode*> Built; 9654 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 9655 9656 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9657 ii != ee; ++ii) 9658 AddToWorkList(*ii); 9659 return S; 9660} 9661 9662/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 9663/// return a DAG expression to select that will generate the same value by 9664/// multiplying by a magic number. See: 9665/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9666SDValue DAGCombiner::BuildUDIV(SDNode *N) { 9667 std::vector<SDNode*> Built; 9668 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 9669 9670 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9671 ii != ee; ++ii) 9672 AddToWorkList(*ii); 9673 return S; 9674} 9675 9676/// FindBaseOffset - Return true if base is a frame index, which is known not 9677// to alias with anything but itself. Provides base object and offset as 9678// results. 9679static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 9680 const GlobalValue *&GV, const void *&CV) { 9681 // Assume it is a primitive operation. 9682 Base = Ptr; Offset = 0; GV = 0; CV = 0; 9683 9684 // If it's an adding a simple constant then integrate the offset. 9685 if (Base.getOpcode() == ISD::ADD) { 9686 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 9687 Base = Base.getOperand(0); 9688 Offset += C->getZExtValue(); 9689 } 9690 } 9691 9692 // Return the underlying GlobalValue, and update the Offset. Return false 9693 // for GlobalAddressSDNode since the same GlobalAddress may be represented 9694 // by multiple nodes with different offsets. 9695 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 9696 GV = G->getGlobal(); 9697 Offset += G->getOffset(); 9698 return false; 9699 } 9700 9701 // Return the underlying Constant value, and update the Offset. Return false 9702 // for ConstantSDNodes since the same constant pool entry may be represented 9703 // by multiple nodes with different offsets. 9704 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 9705 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 9706 : (const void *)C->getConstVal(); 9707 Offset += C->getOffset(); 9708 return false; 9709 } 9710 // If it's any of the following then it can't alias with anything but itself. 9711 return isa<FrameIndexSDNode>(Base); 9712} 9713 9714/// isAlias - Return true if there is any possibility that the two addresses 9715/// overlap. 9716bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 9717 const Value *SrcValue1, int SrcValueOffset1, 9718 unsigned SrcValueAlign1, 9719 const MDNode *TBAAInfo1, 9720 SDValue Ptr2, int64_t Size2, 9721 const Value *SrcValue2, int SrcValueOffset2, 9722 unsigned SrcValueAlign2, 9723 const MDNode *TBAAInfo2) const { 9724 // If they are the same then they must be aliases. 9725 if (Ptr1 == Ptr2) return true; 9726 9727 // Gather base node and offset information. 9728 SDValue Base1, Base2; 9729 int64_t Offset1, Offset2; 9730 const GlobalValue *GV1, *GV2; 9731 const void *CV1, *CV2; 9732 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 9733 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 9734 9735 // If they have a same base address then check to see if they overlap. 9736 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 9737 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9738 9739 // It is possible for different frame indices to alias each other, mostly 9740 // when tail call optimization reuses return address slots for arguments. 9741 // To catch this case, look up the actual index of frame indices to compute 9742 // the real alias relationship. 9743 if (isFrameIndex1 && isFrameIndex2) { 9744 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9745 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 9746 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 9747 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9748 } 9749 9750 // Otherwise, if we know what the bases are, and they aren't identical, then 9751 // we know they cannot alias. 9752 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 9753 return false; 9754 9755 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 9756 // compared to the size and offset of the access, we may be able to prove they 9757 // do not alias. This check is conservative for now to catch cases created by 9758 // splitting vector types. 9759 if ((SrcValueAlign1 == SrcValueAlign2) && 9760 (SrcValueOffset1 != SrcValueOffset2) && 9761 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 9762 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 9763 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 9764 9765 // There is no overlap between these relatively aligned accesses of similar 9766 // size, return no alias. 9767 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 9768 return false; 9769 } 9770 9771 if (CombinerGlobalAA) { 9772 // Use alias analysis information. 9773 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 9774 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 9775 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 9776 AliasAnalysis::AliasResult AAResult = 9777 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 9778 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 9779 if (AAResult == AliasAnalysis::NoAlias) 9780 return false; 9781 } 9782 9783 // Otherwise we have to assume they alias. 9784 return true; 9785} 9786 9787bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) { 9788 SDValue Ptr0, Ptr1; 9789 int64_t Size0, Size1; 9790 const Value *SrcValue0, *SrcValue1; 9791 int SrcValueOffset0, SrcValueOffset1; 9792 unsigned SrcValueAlign0, SrcValueAlign1; 9793 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1; 9794 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0, 9795 SrcValueAlign0, SrcTBAAInfo0); 9796 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1, 9797 SrcValueAlign1, SrcTBAAInfo1); 9798 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0, 9799 SrcValueAlign0, SrcTBAAInfo0, 9800 Ptr1, Size1, SrcValue1, SrcValueOffset1, 9801 SrcValueAlign1, SrcTBAAInfo1); 9802} 9803 9804/// FindAliasInfo - Extracts the relevant alias information from the memory 9805/// node. Returns true if the operand was a load. 9806bool DAGCombiner::FindAliasInfo(SDNode *N, 9807 SDValue &Ptr, int64_t &Size, 9808 const Value *&SrcValue, 9809 int &SrcValueOffset, 9810 unsigned &SrcValueAlign, 9811 const MDNode *&TBAAInfo) const { 9812 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 9813 9814 Ptr = LS->getBasePtr(); 9815 Size = LS->getMemoryVT().getSizeInBits() >> 3; 9816 SrcValue = LS->getSrcValue(); 9817 SrcValueOffset = LS->getSrcValueOffset(); 9818 SrcValueAlign = LS->getOriginalAlignment(); 9819 TBAAInfo = LS->getTBAAInfo(); 9820 return isa<LoadSDNode>(LS); 9821} 9822 9823/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 9824/// looking for aliasing nodes and adding them to the Aliases vector. 9825void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 9826 SmallVector<SDValue, 8> &Aliases) { 9827 SmallVector<SDValue, 8> Chains; // List of chains to visit. 9828 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 9829 9830 // Get alias information for node. 9831 SDValue Ptr; 9832 int64_t Size; 9833 const Value *SrcValue; 9834 int SrcValueOffset; 9835 unsigned SrcValueAlign; 9836 const MDNode *SrcTBAAInfo; 9837 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 9838 SrcValueAlign, SrcTBAAInfo); 9839 9840 // Starting off. 9841 Chains.push_back(OriginalChain); 9842 unsigned Depth = 0; 9843 9844 // Look at each chain and determine if it is an alias. If so, add it to the 9845 // aliases list. If not, then continue up the chain looking for the next 9846 // candidate. 9847 while (!Chains.empty()) { 9848 SDValue Chain = Chains.back(); 9849 Chains.pop_back(); 9850 9851 // For TokenFactor nodes, look at each operand and only continue up the 9852 // chain until we find two aliases. If we've seen two aliases, assume we'll 9853 // find more and revert to original chain since the xform is unlikely to be 9854 // profitable. 9855 // 9856 // FIXME: The depth check could be made to return the last non-aliasing 9857 // chain we found before we hit a tokenfactor rather than the original 9858 // chain. 9859 if (Depth > 6 || Aliases.size() == 2) { 9860 Aliases.clear(); 9861 Aliases.push_back(OriginalChain); 9862 break; 9863 } 9864 9865 // Don't bother if we've been before. 9866 if (!Visited.insert(Chain.getNode())) 9867 continue; 9868 9869 switch (Chain.getOpcode()) { 9870 case ISD::EntryToken: 9871 // Entry token is ideal chain operand, but handled in FindBetterChain. 9872 break; 9873 9874 case ISD::LOAD: 9875 case ISD::STORE: { 9876 // Get alias information for Chain. 9877 SDValue OpPtr; 9878 int64_t OpSize; 9879 const Value *OpSrcValue; 9880 int OpSrcValueOffset; 9881 unsigned OpSrcValueAlign; 9882 const MDNode *OpSrcTBAAInfo; 9883 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 9884 OpSrcValue, OpSrcValueOffset, 9885 OpSrcValueAlign, 9886 OpSrcTBAAInfo); 9887 9888 // If chain is alias then stop here. 9889 if (!(IsLoad && IsOpLoad) && 9890 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 9891 SrcTBAAInfo, 9892 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 9893 OpSrcValueAlign, OpSrcTBAAInfo)) { 9894 Aliases.push_back(Chain); 9895 } else { 9896 // Look further up the chain. 9897 Chains.push_back(Chain.getOperand(0)); 9898 ++Depth; 9899 } 9900 break; 9901 } 9902 9903 case ISD::TokenFactor: 9904 // We have to check each of the operands of the token factor for "small" 9905 // token factors, so we queue them up. Adding the operands to the queue 9906 // (stack) in reverse order maintains the original order and increases the 9907 // likelihood that getNode will find a matching token factor (CSE.) 9908 if (Chain.getNumOperands() > 16) { 9909 Aliases.push_back(Chain); 9910 break; 9911 } 9912 for (unsigned n = Chain.getNumOperands(); n;) 9913 Chains.push_back(Chain.getOperand(--n)); 9914 ++Depth; 9915 break; 9916 9917 default: 9918 // For all other instructions we will just have to take what we can get. 9919 Aliases.push_back(Chain); 9920 break; 9921 } 9922 } 9923} 9924 9925/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 9926/// for a better chain (aliasing node.) 9927SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 9928 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 9929 9930 // Accumulate all the aliases to this node. 9931 GatherAllAliases(N, OldChain, Aliases); 9932 9933 // If no operands then chain to entry token. 9934 if (Aliases.size() == 0) 9935 return DAG.getEntryNode(); 9936 9937 // If a single operand then chain to it. We don't need to revisit it. 9938 if (Aliases.size() == 1) 9939 return Aliases[0]; 9940 9941 // Construct a custom tailored token factor. 9942 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 9943 &Aliases[0], Aliases.size()); 9944} 9945 9946// SelectionDAG::Combine - This is the entry point for the file. 9947// 9948void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 9949 CodeGenOpt::Level OptLevel) { 9950 /// run - This is the main entry point to this class. 9951 /// 9952 DAGCombiner(*this, AA, OptLevel).Run(Level); 9953} 9954