DAGCombiner.cpp revision 21e8a955ef3481976b562d7f10db967f6def3d2d
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32using namespace llvm; 33 34STATISTIC(NodesCombined , "Number of dag nodes combined"); 35STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 36STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 37 38namespace { 39#ifndef NDEBUG 40 static cl::opt<bool> 41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 42 cl::desc("Pop up a window to show dags before the first " 43 "dag combine pass")); 44 static cl::opt<bool> 45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 46 cl::desc("Pop up a window to show dags before the second " 47 "dag combine pass")); 48#else 49 static const bool ViewDAGCombine1 = false; 50 static const bool ViewDAGCombine2 = false; 51#endif 52 53 static cl::opt<bool> 54 CombinerAA("combiner-alias-analysis", cl::Hidden, 55 cl::desc("Turn on alias analysis during testing")); 56 57 static cl::opt<bool> 58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 59 cl::desc("Include global information in alias analysis")); 60 61//------------------------------ DAGCombiner ---------------------------------// 62 63 class VISIBILITY_HIDDEN DAGCombiner { 64 SelectionDAG &DAG; 65 TargetLowering &TLI; 66 bool AfterLegalize; 67 68 // Worklist of all of the nodes that need to be simplified. 69 std::vector<SDNode*> WorkList; 70 71 // AA - Used for DAG load/store alias analysis. 72 AliasAnalysis &AA; 73 74 /// AddUsersToWorkList - When an instruction is simplified, add all users of 75 /// the instruction to the work lists because they might get more simplified 76 /// now. 77 /// 78 void AddUsersToWorkList(SDNode *N) { 79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 80 UI != UE; ++UI) 81 AddToWorkList(*UI); 82 } 83 84 /// visit - call the node-specific routine that knows how to fold each 85 /// particular type of node. 86 SDOperand visit(SDNode *N); 87 88 public: 89 /// AddToWorkList - Add to the work list making sure it's instance is at the 90 /// the back (next to be processed.) 91 void AddToWorkList(SDNode *N) { 92 removeFromWorkList(N); 93 WorkList.push_back(N); 94 } 95 96 /// removeFromWorkList - remove all instances of N from the worklist. 97 /// 98 void removeFromWorkList(SDNode *N) { 99 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 100 WorkList.end()); 101 } 102 103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 104 bool AddTo = true); 105 106 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 107 return CombineTo(N, &Res, 1, AddTo); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 111 bool AddTo = true) { 112 SDOperand To[] = { Res0, Res1 }; 113 return CombineTo(N, To, 2, AddTo); 114 } 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDOperand Op) { 122 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 123 return SimplifyDemandedBits(Op, Demanded); 124 } 125 126 bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded); 127 128 bool CombineToPreIndexedLoadStore(SDNode *N); 129 bool CombineToPostIndexedLoadStore(SDNode *N); 130 131 132 /// combine - call the node-specific routine that knows how to fold each 133 /// particular type of node. If that doesn't do anything, try the 134 /// target-specific DAG combines. 135 SDOperand combine(SDNode *N); 136 137 // Visitation implementation - Implement dag node combining for different 138 // node types. The semantics are as follows: 139 // Return Value: 140 // SDOperand.Val == 0 - No change was made 141 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 142 // otherwise - N should be replaced by the returned Operand. 143 // 144 SDOperand visitTokenFactor(SDNode *N); 145 SDOperand visitMERGE_VALUES(SDNode *N); 146 SDOperand visitADD(SDNode *N); 147 SDOperand visitSUB(SDNode *N); 148 SDOperand visitADDC(SDNode *N); 149 SDOperand visitADDE(SDNode *N); 150 SDOperand visitMUL(SDNode *N); 151 SDOperand visitSDIV(SDNode *N); 152 SDOperand visitUDIV(SDNode *N); 153 SDOperand visitSREM(SDNode *N); 154 SDOperand visitUREM(SDNode *N); 155 SDOperand visitMULHU(SDNode *N); 156 SDOperand visitMULHS(SDNode *N); 157 SDOperand visitSMUL_LOHI(SDNode *N); 158 SDOperand visitUMUL_LOHI(SDNode *N); 159 SDOperand visitSDIVREM(SDNode *N); 160 SDOperand visitUDIVREM(SDNode *N); 161 SDOperand visitAND(SDNode *N); 162 SDOperand visitOR(SDNode *N); 163 SDOperand visitXOR(SDNode *N); 164 SDOperand SimplifyVBinOp(SDNode *N); 165 SDOperand visitSHL(SDNode *N); 166 SDOperand visitSRA(SDNode *N); 167 SDOperand visitSRL(SDNode *N); 168 SDOperand visitCTLZ(SDNode *N); 169 SDOperand visitCTTZ(SDNode *N); 170 SDOperand visitCTPOP(SDNode *N); 171 SDOperand visitSELECT(SDNode *N); 172 SDOperand visitSELECT_CC(SDNode *N); 173 SDOperand visitSETCC(SDNode *N); 174 SDOperand visitSIGN_EXTEND(SDNode *N); 175 SDOperand visitZERO_EXTEND(SDNode *N); 176 SDOperand visitANY_EXTEND(SDNode *N); 177 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 178 SDOperand visitTRUNCATE(SDNode *N); 179 SDOperand visitBIT_CONVERT(SDNode *N); 180 SDOperand visitFADD(SDNode *N); 181 SDOperand visitFSUB(SDNode *N); 182 SDOperand visitFMUL(SDNode *N); 183 SDOperand visitFDIV(SDNode *N); 184 SDOperand visitFREM(SDNode *N); 185 SDOperand visitFCOPYSIGN(SDNode *N); 186 SDOperand visitSINT_TO_FP(SDNode *N); 187 SDOperand visitUINT_TO_FP(SDNode *N); 188 SDOperand visitFP_TO_SINT(SDNode *N); 189 SDOperand visitFP_TO_UINT(SDNode *N); 190 SDOperand visitFP_ROUND(SDNode *N); 191 SDOperand visitFP_ROUND_INREG(SDNode *N); 192 SDOperand visitFP_EXTEND(SDNode *N); 193 SDOperand visitFNEG(SDNode *N); 194 SDOperand visitFABS(SDNode *N); 195 SDOperand visitBRCOND(SDNode *N); 196 SDOperand visitBR_CC(SDNode *N); 197 SDOperand visitLOAD(SDNode *N); 198 SDOperand visitSTORE(SDNode *N); 199 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 200 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 201 SDOperand visitBUILD_VECTOR(SDNode *N); 202 SDOperand visitCONCAT_VECTORS(SDNode *N); 203 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 204 205 SDOperand XformToShuffleWithZero(SDNode *N); 206 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 207 208 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 209 210 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 211 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 212 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 213 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 214 SDOperand N3, ISD::CondCode CC, 215 bool NotExtCompare = false); 216 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 217 ISD::CondCode Cond, bool foldBooleans = true); 218 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 219 unsigned HiOp); 220 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 221 SDOperand BuildSDIV(SDNode *N); 222 SDOperand BuildUDIV(SDNode *N); 223 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 224 SDOperand ReduceLoadWidth(SDNode *N); 225 226 SDOperand GetDemandedBits(SDOperand V, const APInt &Mask); 227 228 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 229 /// looking for aliasing nodes and adding them to the Aliases vector. 230 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 231 SmallVector<SDOperand, 8> &Aliases); 232 233 /// isAlias - Return true if there is any possibility that the two addresses 234 /// overlap. 235 bool isAlias(SDOperand Ptr1, int64_t Size1, 236 const Value *SrcValue1, int SrcValueOffset1, 237 SDOperand Ptr2, int64_t Size2, 238 const Value *SrcValue2, int SrcValueOffset2); 239 240 /// FindAliasInfo - Extracts the relevant alias information from the memory 241 /// node. Returns true if the operand was a load. 242 bool FindAliasInfo(SDNode *N, 243 SDOperand &Ptr, int64_t &Size, 244 const Value *&SrcValue, int &SrcValueOffset); 245 246 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 247 /// looking for a better chain (aliasing node.) 248 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 249 250public: 251 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 252 : DAG(D), 253 TLI(D.getTargetLoweringInfo()), 254 AfterLegalize(false), 255 AA(A) {} 256 257 /// Run - runs the dag combiner on all nodes in the work list 258 void Run(bool RunningAfterLegalize); 259 }; 260} 261 262 263namespace { 264/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 265/// nodes from the worklist. 266class VISIBILITY_HIDDEN WorkListRemover : 267 public SelectionDAG::DAGUpdateListener { 268 DAGCombiner &DC; 269public: 270 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 271 272 virtual void NodeDeleted(SDNode *N) { 273 DC.removeFromWorkList(N); 274 } 275 276 virtual void NodeUpdated(SDNode *N) { 277 // Ignore updates. 278 } 279}; 280} 281 282//===----------------------------------------------------------------------===// 283// TargetLowering::DAGCombinerInfo implementation 284//===----------------------------------------------------------------------===// 285 286void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 287 ((DAGCombiner*)DC)->AddToWorkList(N); 288} 289 290SDOperand TargetLowering::DAGCombinerInfo:: 291CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 292 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 293} 294 295SDOperand TargetLowering::DAGCombinerInfo:: 296CombineTo(SDNode *N, SDOperand Res) { 297 return ((DAGCombiner*)DC)->CombineTo(N, Res); 298} 299 300 301SDOperand TargetLowering::DAGCombinerInfo:: 302CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 303 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 304} 305 306 307//===----------------------------------------------------------------------===// 308// Helper Functions 309//===----------------------------------------------------------------------===// 310 311/// isNegatibleForFree - Return 1 if we can compute the negated form of the 312/// specified expression for the same cost as the expression itself, or 2 if we 313/// can compute the negated form more cheaply than the expression itself. 314static char isNegatibleForFree(SDOperand Op, bool AfterLegalize, 315 unsigned Depth = 0) { 316 // No compile time optimizations on this type. 317 if (Op.getValueType() == MVT::ppcf128) 318 return 0; 319 320 // fneg is removable even if it has multiple uses. 321 if (Op.getOpcode() == ISD::FNEG) return 2; 322 323 // Don't allow anything with multiple uses. 324 if (!Op.hasOneUse()) return 0; 325 326 // Don't recurse exponentially. 327 if (Depth > 6) return 0; 328 329 switch (Op.getOpcode()) { 330 default: return false; 331 case ISD::ConstantFP: 332 // Don't invert constant FP values after legalize. The negated constant 333 // isn't necessarily legal. 334 return AfterLegalize ? 0 : 1; 335 case ISD::FADD: 336 // FIXME: determine better conditions for this xform. 337 if (!UnsafeFPMath) return 0; 338 339 // -(A+B) -> -A - B 340 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 341 return V; 342 // -(A+B) -> -B - A 343 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 344 case ISD::FSUB: 345 // We can't turn -(A-B) into B-A when we honor signed zeros. 346 if (!UnsafeFPMath) return 0; 347 348 // -(A-B) -> B-A 349 return 1; 350 351 case ISD::FMUL: 352 case ISD::FDIV: 353 if (HonorSignDependentRoundingFPMath()) return 0; 354 355 // -(X*Y) -> (-X * Y) or (X*-Y) 356 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 357 return V; 358 359 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 360 361 case ISD::FP_EXTEND: 362 case ISD::FP_ROUND: 363 case ISD::FSIN: 364 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 365 } 366} 367 368/// GetNegatedExpression - If isNegatibleForFree returns true, this function 369/// returns the newly negated expression. 370static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 371 bool AfterLegalize, unsigned Depth = 0) { 372 // fneg is removable even if it has multiple uses. 373 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 374 375 // Don't allow anything with multiple uses. 376 assert(Op.hasOneUse() && "Unknown reuse!"); 377 378 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 379 switch (Op.getOpcode()) { 380 default: assert(0 && "Unknown code"); 381 case ISD::ConstantFP: { 382 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 383 V.changeSign(); 384 return DAG.getConstantFP(V, Op.getValueType()); 385 } 386 case ISD::FADD: 387 // FIXME: determine better conditions for this xform. 388 assert(UnsafeFPMath); 389 390 // -(A+B) -> -A - B 391 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 392 return DAG.getNode(ISD::FSUB, Op.getValueType(), 393 GetNegatedExpression(Op.getOperand(0), DAG, 394 AfterLegalize, Depth+1), 395 Op.getOperand(1)); 396 // -(A+B) -> -B - A 397 return DAG.getNode(ISD::FSUB, Op.getValueType(), 398 GetNegatedExpression(Op.getOperand(1), DAG, 399 AfterLegalize, Depth+1), 400 Op.getOperand(0)); 401 case ISD::FSUB: 402 // We can't turn -(A-B) into B-A when we honor signed zeros. 403 assert(UnsafeFPMath); 404 405 // -(0-B) -> B 406 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 407 if (N0CFP->getValueAPF().isZero()) 408 return Op.getOperand(1); 409 410 // -(A-B) -> B-A 411 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 412 Op.getOperand(0)); 413 414 case ISD::FMUL: 415 case ISD::FDIV: 416 assert(!HonorSignDependentRoundingFPMath()); 417 418 // -(X*Y) -> -X * Y 419 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 420 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 421 GetNegatedExpression(Op.getOperand(0), DAG, 422 AfterLegalize, Depth+1), 423 Op.getOperand(1)); 424 425 // -(X*Y) -> X * -Y 426 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 427 Op.getOperand(0), 428 GetNegatedExpression(Op.getOperand(1), DAG, 429 AfterLegalize, Depth+1)); 430 431 case ISD::FP_EXTEND: 432 case ISD::FSIN: 433 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 434 GetNegatedExpression(Op.getOperand(0), DAG, 435 AfterLegalize, Depth+1)); 436 case ISD::FP_ROUND: 437 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(0), DAG, 439 AfterLegalize, Depth+1), 440 Op.getOperand(1)); 441 } 442} 443 444 445// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 446// that selects between the values 1 and 0, making it equivalent to a setcc. 447// Also, set the incoming LHS, RHS, and CC references to the appropriate 448// nodes based on the type of node we are checking. This simplifies life a 449// bit for the callers. 450static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 451 SDOperand &CC) { 452 if (N.getOpcode() == ISD::SETCC) { 453 LHS = N.getOperand(0); 454 RHS = N.getOperand(1); 455 CC = N.getOperand(2); 456 return true; 457 } 458 if (N.getOpcode() == ISD::SELECT_CC && 459 N.getOperand(2).getOpcode() == ISD::Constant && 460 N.getOperand(3).getOpcode() == ISD::Constant && 461 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 462 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 463 LHS = N.getOperand(0); 464 RHS = N.getOperand(1); 465 CC = N.getOperand(4); 466 return true; 467 } 468 return false; 469} 470 471// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 472// one use. If this is true, it allows the users to invert the operation for 473// free when it is profitable to do so. 474static bool isOneUseSetCC(SDOperand N) { 475 SDOperand N0, N1, N2; 476 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 477 return true; 478 return false; 479} 480 481SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 482 MVT::ValueType VT = N0.getValueType(); 483 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 484 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 485 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 486 if (isa<ConstantSDNode>(N1)) { 487 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 488 AddToWorkList(OpNode.Val); 489 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 490 } else if (N0.hasOneUse()) { 491 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 492 AddToWorkList(OpNode.Val); 493 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 494 } 495 } 496 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 497 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 498 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 499 if (isa<ConstantSDNode>(N0)) { 500 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 501 AddToWorkList(OpNode.Val); 502 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 503 } else if (N1.hasOneUse()) { 504 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 505 AddToWorkList(OpNode.Val); 506 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 507 } 508 } 509 return SDOperand(); 510} 511 512SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 513 bool AddTo) { 514 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 515 ++NodesCombined; 516 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 517 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 518 DOUT << " and " << NumTo-1 << " other values\n"; 519 WorkListRemover DeadNodes(*this); 520 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 521 522 if (AddTo) { 523 // Push the new nodes and any users onto the worklist 524 for (unsigned i = 0, e = NumTo; i != e; ++i) { 525 AddToWorkList(To[i].Val); 526 AddUsersToWorkList(To[i].Val); 527 } 528 } 529 530 // Nodes can be reintroduced into the worklist. Make sure we do not 531 // process a node that has been replaced. 532 removeFromWorkList(N); 533 534 // Finally, since the node is now dead, remove it from the graph. 535 DAG.DeleteNode(N); 536 return SDOperand(N, 0); 537} 538 539/// SimplifyDemandedBits - Check the specified integer node value to see if 540/// it can be simplified or if things it uses can be simplified by bit 541/// propagation. If so, return true. 542bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) { 543 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 544 APInt KnownZero, KnownOne; 545 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 546 return false; 547 548 // Revisit the node. 549 AddToWorkList(Op.Val); 550 551 // Replace the old value with the new one. 552 ++NodesCombined; 553 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 554 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 555 DOUT << '\n'; 556 557 // Replace all uses. If any nodes become isomorphic to other nodes and 558 // are deleted, make sure to remove them from our worklist. 559 WorkListRemover DeadNodes(*this); 560 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 561 562 // Push the new node and any (possibly new) users onto the worklist. 563 AddToWorkList(TLO.New.Val); 564 AddUsersToWorkList(TLO.New.Val); 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (TLO.Old.Val->use_empty()) { 570 removeFromWorkList(TLO.Old.Val); 571 572 // If the operands of this node are only used by the node, they will now 573 // be dead. Make sure to visit them first to delete dead nodes early. 574 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 575 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 576 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 577 578 DAG.DeleteNode(TLO.Old.Val); 579 } 580 return true; 581} 582 583//===----------------------------------------------------------------------===// 584// Main DAG Combiner implementation 585//===----------------------------------------------------------------------===// 586 587void DAGCombiner::Run(bool RunningAfterLegalize) { 588 // set the instance variable, so that the various visit routines may use it. 589 AfterLegalize = RunningAfterLegalize; 590 591 // Add all the dag nodes to the worklist. 592 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 593 E = DAG.allnodes_end(); I != E; ++I) 594 WorkList.push_back(I); 595 596 // Create a dummy node (which is not added to allnodes), that adds a reference 597 // to the root node, preventing it from being deleted, and tracking any 598 // changes of the root. 599 HandleSDNode Dummy(DAG.getRoot()); 600 601 // The root of the dag may dangle to deleted nodes until the dag combiner is 602 // done. Set it to null to avoid confusion. 603 DAG.setRoot(SDOperand()); 604 605 // while the worklist isn't empty, inspect the node on the end of it and 606 // try and combine it. 607 while (!WorkList.empty()) { 608 SDNode *N = WorkList.back(); 609 WorkList.pop_back(); 610 611 // If N has no uses, it is dead. Make sure to revisit all N's operands once 612 // N is deleted from the DAG, since they too may now be dead or may have a 613 // reduced number of uses, allowing other xforms. 614 if (N->use_empty() && N != &Dummy) { 615 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 616 AddToWorkList(N->getOperand(i).Val); 617 618 DAG.DeleteNode(N); 619 continue; 620 } 621 622 SDOperand RV = combine(N); 623 624 if (RV.Val == 0) 625 continue; 626 627 ++NodesCombined; 628 629 // If we get back the same node we passed in, rather than a new node or 630 // zero, we know that the node must have defined multiple values and 631 // CombineTo was used. Since CombineTo takes care of the worklist 632 // mechanics for us, we have no work to do in this case. 633 if (RV.Val == N) 634 continue; 635 636 assert(N->getOpcode() != ISD::DELETED_NODE && 637 RV.Val->getOpcode() != ISD::DELETED_NODE && 638 "Node was deleted but visit returned new node!"); 639 640 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 641 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 642 DOUT << '\n'; 643 WorkListRemover DeadNodes(*this); 644 if (N->getNumValues() == RV.Val->getNumValues()) 645 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes); 646 else { 647 assert(N->getValueType(0) == RV.getValueType() && 648 N->getNumValues() == 1 && "Type mismatch"); 649 SDOperand OpV = RV; 650 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 651 } 652 653 // Push the new node and any users onto the worklist 654 AddToWorkList(RV.Val); 655 AddUsersToWorkList(RV.Val); 656 657 // Add any uses of the old node to the worklist in case this node is the 658 // last one that uses them. They may become dead after this node is 659 // deleted. 660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 661 AddToWorkList(N->getOperand(i).Val); 662 663 // Nodes can be reintroduced into the worklist. Make sure we do not 664 // process a node that has been replaced. 665 removeFromWorkList(N); 666 667 // Finally, since the node is now dead, remove it from the graph. 668 DAG.DeleteNode(N); 669 } 670 671 // If the root changed (e.g. it was a dead load, update the root). 672 DAG.setRoot(Dummy.getValue()); 673} 674 675SDOperand DAGCombiner::visit(SDNode *N) { 676 switch(N->getOpcode()) { 677 default: break; 678 case ISD::TokenFactor: return visitTokenFactor(N); 679 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 680 case ISD::ADD: return visitADD(N); 681 case ISD::SUB: return visitSUB(N); 682 case ISD::ADDC: return visitADDC(N); 683 case ISD::ADDE: return visitADDE(N); 684 case ISD::MUL: return visitMUL(N); 685 case ISD::SDIV: return visitSDIV(N); 686 case ISD::UDIV: return visitUDIV(N); 687 case ISD::SREM: return visitSREM(N); 688 case ISD::UREM: return visitUREM(N); 689 case ISD::MULHU: return visitMULHU(N); 690 case ISD::MULHS: return visitMULHS(N); 691 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 692 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 693 case ISD::SDIVREM: return visitSDIVREM(N); 694 case ISD::UDIVREM: return visitUDIVREM(N); 695 case ISD::AND: return visitAND(N); 696 case ISD::OR: return visitOR(N); 697 case ISD::XOR: return visitXOR(N); 698 case ISD::SHL: return visitSHL(N); 699 case ISD::SRA: return visitSRA(N); 700 case ISD::SRL: return visitSRL(N); 701 case ISD::CTLZ: return visitCTLZ(N); 702 case ISD::CTTZ: return visitCTTZ(N); 703 case ISD::CTPOP: return visitCTPOP(N); 704 case ISD::SELECT: return visitSELECT(N); 705 case ISD::SELECT_CC: return visitSELECT_CC(N); 706 case ISD::SETCC: return visitSETCC(N); 707 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 708 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 709 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 710 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 711 case ISD::TRUNCATE: return visitTRUNCATE(N); 712 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 713 case ISD::FADD: return visitFADD(N); 714 case ISD::FSUB: return visitFSUB(N); 715 case ISD::FMUL: return visitFMUL(N); 716 case ISD::FDIV: return visitFDIV(N); 717 case ISD::FREM: return visitFREM(N); 718 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 719 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 720 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 721 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 722 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 723 case ISD::FP_ROUND: return visitFP_ROUND(N); 724 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 725 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 726 case ISD::FNEG: return visitFNEG(N); 727 case ISD::FABS: return visitFABS(N); 728 case ISD::BRCOND: return visitBRCOND(N); 729 case ISD::BR_CC: return visitBR_CC(N); 730 case ISD::LOAD: return visitLOAD(N); 731 case ISD::STORE: return visitSTORE(N); 732 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 733 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 734 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 735 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 736 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 737 } 738 return SDOperand(); 739} 740 741SDOperand DAGCombiner::combine(SDNode *N) { 742 743 SDOperand RV = visit(N); 744 745 // If nothing happened, try a target-specific DAG combine. 746 if (RV.Val == 0) { 747 assert(N->getOpcode() != ISD::DELETED_NODE && 748 "Node was deleted but visit returned NULL!"); 749 750 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 751 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 752 753 // Expose the DAG combiner to the target combiner impls. 754 TargetLowering::DAGCombinerInfo 755 DagCombineInfo(DAG, !AfterLegalize, false, this); 756 757 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 758 } 759 } 760 761 return RV; 762} 763 764/// getInputChainForNode - Given a node, return its input chain if it has one, 765/// otherwise return a null sd operand. 766static SDOperand getInputChainForNode(SDNode *N) { 767 if (unsigned NumOps = N->getNumOperands()) { 768 if (N->getOperand(0).getValueType() == MVT::Other) 769 return N->getOperand(0); 770 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 771 return N->getOperand(NumOps-1); 772 for (unsigned i = 1; i < NumOps-1; ++i) 773 if (N->getOperand(i).getValueType() == MVT::Other) 774 return N->getOperand(i); 775 } 776 return SDOperand(0, 0); 777} 778 779SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 780 // If N has two operands, where one has an input chain equal to the other, 781 // the 'other' chain is redundant. 782 if (N->getNumOperands() == 2) { 783 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 784 return N->getOperand(0); 785 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 786 return N->getOperand(1); 787 } 788 789 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 790 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 791 SmallPtrSet<SDNode*, 16> SeenOps; 792 bool Changed = false; // If we should replace this token factor. 793 794 // Start out with this token factor. 795 TFs.push_back(N); 796 797 // Iterate through token factors. The TFs grows when new token factors are 798 // encountered. 799 for (unsigned i = 0; i < TFs.size(); ++i) { 800 SDNode *TF = TFs[i]; 801 802 // Check each of the operands. 803 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 804 SDOperand Op = TF->getOperand(i); 805 806 switch (Op.getOpcode()) { 807 case ISD::EntryToken: 808 // Entry tokens don't need to be added to the list. They are 809 // rededundant. 810 Changed = true; 811 break; 812 813 case ISD::TokenFactor: 814 if ((CombinerAA || Op.hasOneUse()) && 815 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 816 // Queue up for processing. 817 TFs.push_back(Op.Val); 818 // Clean up in case the token factor is removed. 819 AddToWorkList(Op.Val); 820 Changed = true; 821 break; 822 } 823 // Fall thru 824 825 default: 826 // Only add if it isn't already in the list. 827 if (SeenOps.insert(Op.Val)) 828 Ops.push_back(Op); 829 else 830 Changed = true; 831 break; 832 } 833 } 834 } 835 836 SDOperand Result; 837 838 // If we've change things around then replace token factor. 839 if (Changed) { 840 if (Ops.empty()) { 841 // The entry token is the only possible outcome. 842 Result = DAG.getEntryNode(); 843 } else { 844 // New and improved token factor. 845 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 846 } 847 848 // Don't add users to work list. 849 return CombineTo(N, Result, false); 850 } 851 852 return Result; 853} 854 855/// MERGE_VALUES can always be eliminated. 856SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) { 857 WorkListRemover DeadNodes(*this); 858 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 859 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i), 860 &DeadNodes); 861 removeFromWorkList(N); 862 DAG.DeleteNode(N); 863 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 864} 865 866 867static 868SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 869 MVT::ValueType VT = N0.getValueType(); 870 SDOperand N00 = N0.getOperand(0); 871 SDOperand N01 = N0.getOperand(1); 872 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 873 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 874 isa<ConstantSDNode>(N00.getOperand(1))) { 875 N0 = DAG.getNode(ISD::ADD, VT, 876 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 877 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 878 return DAG.getNode(ISD::ADD, VT, N0, N1); 879 } 880 return SDOperand(); 881} 882 883static 884SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 885 SelectionDAG &DAG) { 886 MVT::ValueType VT = N->getValueType(0); 887 unsigned Opc = N->getOpcode(); 888 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 889 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 890 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 891 ISD::CondCode CC = ISD::SETCC_INVALID; 892 if (isSlctCC) 893 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 894 else { 895 SDOperand CCOp = Slct.getOperand(0); 896 if (CCOp.getOpcode() == ISD::SETCC) 897 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 898 } 899 900 bool DoXform = false; 901 bool InvCC = false; 902 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 903 "Bad input!"); 904 if (LHS.getOpcode() == ISD::Constant && 905 cast<ConstantSDNode>(LHS)->isNullValue()) 906 DoXform = true; 907 else if (CC != ISD::SETCC_INVALID && 908 RHS.getOpcode() == ISD::Constant && 909 cast<ConstantSDNode>(RHS)->isNullValue()) { 910 std::swap(LHS, RHS); 911 SDOperand Op0 = Slct.getOperand(0); 912 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() 913 : Op0.getOperand(0).getValueType()); 914 CC = ISD::getSetCCInverse(CC, isInt); 915 DoXform = true; 916 InvCC = true; 917 } 918 919 if (DoXform) { 920 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 921 if (isSlctCC) 922 return DAG.getSelectCC(OtherOp, Result, 923 Slct.getOperand(0), Slct.getOperand(1), CC); 924 SDOperand CCOp = Slct.getOperand(0); 925 if (InvCC) 926 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 927 CCOp.getOperand(1), CC); 928 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 929 } 930 return SDOperand(); 931} 932 933SDOperand DAGCombiner::visitADD(SDNode *N) { 934 SDOperand N0 = N->getOperand(0); 935 SDOperand N1 = N->getOperand(1); 936 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 937 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 938 MVT::ValueType VT = N0.getValueType(); 939 940 // fold vector ops 941 if (MVT::isVector(VT)) { 942 SDOperand FoldedVOp = SimplifyVBinOp(N); 943 if (FoldedVOp.Val) return FoldedVOp; 944 } 945 946 // fold (add x, undef) -> undef 947 if (N0.getOpcode() == ISD::UNDEF) 948 return N0; 949 if (N1.getOpcode() == ISD::UNDEF) 950 return N1; 951 // fold (add c1, c2) -> c1+c2 952 if (N0C && N1C) 953 return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT); 954 // canonicalize constant to RHS 955 if (N0C && !N1C) 956 return DAG.getNode(ISD::ADD, VT, N1, N0); 957 // fold (add x, 0) -> x 958 if (N1C && N1C->isNullValue()) 959 return N0; 960 // fold ((c1-A)+c2) -> (c1+c2)-A 961 if (N1C && N0.getOpcode() == ISD::SUB) 962 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 963 return DAG.getNode(ISD::SUB, VT, 964 DAG.getConstant(N1C->getAPIntValue()+ 965 N0C->getAPIntValue(), VT), 966 N0.getOperand(1)); 967 // reassociate add 968 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 969 if (RADD.Val != 0) 970 return RADD; 971 // fold ((0-A) + B) -> B-A 972 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 973 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 974 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 975 // fold (A + (0-B)) -> A-B 976 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 977 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 978 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 979 // fold (A+(B-A)) -> B 980 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 981 return N1.getOperand(0); 982 983 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 984 return SDOperand(N, 0); 985 986 // fold (a+b) -> (a|b) iff a and b share no bits. 987 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 988 APInt LHSZero, LHSOne; 989 APInt RHSZero, RHSOne; 990 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 991 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 992 if (LHSZero.getBoolValue()) { 993 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 994 995 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 996 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 997 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 998 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 999 return DAG.getNode(ISD::OR, VT, N0, N1); 1000 } 1001 } 1002 1003 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1004 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 1005 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 1006 if (Result.Val) return Result; 1007 } 1008 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 1009 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 1010 if (Result.Val) return Result; 1011 } 1012 1013 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1014 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 1015 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 1016 if (Result.Val) return Result; 1017 } 1018 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1019 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1020 if (Result.Val) return Result; 1021 } 1022 1023 return SDOperand(); 1024} 1025 1026SDOperand DAGCombiner::visitADDC(SDNode *N) { 1027 SDOperand N0 = N->getOperand(0); 1028 SDOperand N1 = N->getOperand(1); 1029 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1030 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1031 MVT::ValueType VT = N0.getValueType(); 1032 1033 // If the flag result is dead, turn this into an ADD. 1034 if (N->hasNUsesOfValue(0, 1)) 1035 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1036 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1037 1038 // canonicalize constant to RHS. 1039 if (N0C && !N1C) { 1040 SDOperand Ops[] = { N1, N0 }; 1041 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1042 } 1043 1044 // fold (addc x, 0) -> x + no carry out 1045 if (N1C && N1C->isNullValue()) 1046 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1047 1048 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1049 APInt LHSZero, LHSOne; 1050 APInt RHSZero, RHSOne; 1051 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 1052 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1053 if (LHSZero.getBoolValue()) { 1054 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1055 1056 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1057 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1058 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1059 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1060 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1061 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1062 } 1063 1064 return SDOperand(); 1065} 1066 1067SDOperand DAGCombiner::visitADDE(SDNode *N) { 1068 SDOperand N0 = N->getOperand(0); 1069 SDOperand N1 = N->getOperand(1); 1070 SDOperand CarryIn = N->getOperand(2); 1071 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1072 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1073 //MVT::ValueType VT = N0.getValueType(); 1074 1075 // canonicalize constant to RHS 1076 if (N0C && !N1C) { 1077 SDOperand Ops[] = { N1, N0, CarryIn }; 1078 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1079 } 1080 1081 // fold (adde x, y, false) -> (addc x, y) 1082 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1083 SDOperand Ops[] = { N1, N0 }; 1084 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1085 } 1086 1087 return SDOperand(); 1088} 1089 1090 1091 1092SDOperand DAGCombiner::visitSUB(SDNode *N) { 1093 SDOperand N0 = N->getOperand(0); 1094 SDOperand N1 = N->getOperand(1); 1095 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1096 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1097 MVT::ValueType VT = N0.getValueType(); 1098 1099 // fold vector ops 1100 if (MVT::isVector(VT)) { 1101 SDOperand FoldedVOp = SimplifyVBinOp(N); 1102 if (FoldedVOp.Val) return FoldedVOp; 1103 } 1104 1105 // fold (sub x, x) -> 0 1106 if (N0 == N1) 1107 return DAG.getConstant(0, N->getValueType(0)); 1108 // fold (sub c1, c2) -> c1-c2 1109 if (N0C && N1C) 1110 return DAG.getNode(ISD::SUB, VT, N0, N1); 1111 // fold (sub x, c) -> (add x, -c) 1112 if (N1C) 1113 return DAG.getNode(ISD::ADD, VT, N0, 1114 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1115 // fold (A+B)-A -> B 1116 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1117 return N0.getOperand(1); 1118 // fold (A+B)-B -> A 1119 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1120 return N0.getOperand(0); 1121 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1122 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1123 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1124 if (Result.Val) return Result; 1125 } 1126 // If either operand of a sub is undef, the result is undef 1127 if (N0.getOpcode() == ISD::UNDEF) 1128 return N0; 1129 if (N1.getOpcode() == ISD::UNDEF) 1130 return N1; 1131 1132 return SDOperand(); 1133} 1134 1135SDOperand DAGCombiner::visitMUL(SDNode *N) { 1136 SDOperand N0 = N->getOperand(0); 1137 SDOperand N1 = N->getOperand(1); 1138 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1139 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1140 MVT::ValueType VT = N0.getValueType(); 1141 1142 // fold vector ops 1143 if (MVT::isVector(VT)) { 1144 SDOperand FoldedVOp = SimplifyVBinOp(N); 1145 if (FoldedVOp.Val) return FoldedVOp; 1146 } 1147 1148 // fold (mul x, undef) -> 0 1149 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1150 return DAG.getConstant(0, VT); 1151 // fold (mul c1, c2) -> c1*c2 1152 if (N0C && N1C) 1153 return DAG.getNode(ISD::MUL, VT, N0, N1); 1154 // canonicalize constant to RHS 1155 if (N0C && !N1C) 1156 return DAG.getNode(ISD::MUL, VT, N1, N0); 1157 // fold (mul x, 0) -> 0 1158 if (N1C && N1C->isNullValue()) 1159 return N1; 1160 // fold (mul x, -1) -> 0-x 1161 if (N1C && N1C->isAllOnesValue()) 1162 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1163 // fold (mul x, (1 << c)) -> x << c 1164 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1165 return DAG.getNode(ISD::SHL, VT, N0, 1166 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1167 TLI.getShiftAmountTy())); 1168 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1169 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1170 // FIXME: If the input is something that is easily negated (e.g. a 1171 // single-use add), we should put the negate there. 1172 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1173 DAG.getNode(ISD::SHL, VT, N0, 1174 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1175 TLI.getShiftAmountTy()))); 1176 } 1177 1178 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1179 if (N1C && N0.getOpcode() == ISD::SHL && 1180 isa<ConstantSDNode>(N0.getOperand(1))) { 1181 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1182 AddToWorkList(C3.Val); 1183 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1184 } 1185 1186 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1187 // use. 1188 { 1189 SDOperand Sh(0,0), Y(0,0); 1190 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1191 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1192 N0.Val->hasOneUse()) { 1193 Sh = N0; Y = N1; 1194 } else if (N1.getOpcode() == ISD::SHL && 1195 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1196 Sh = N1; Y = N0; 1197 } 1198 if (Sh.Val) { 1199 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1200 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1201 } 1202 } 1203 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1204 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1205 isa<ConstantSDNode>(N0.getOperand(1))) { 1206 return DAG.getNode(ISD::ADD, VT, 1207 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1208 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1209 } 1210 1211 // reassociate mul 1212 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1213 if (RMUL.Val != 0) 1214 return RMUL; 1215 1216 return SDOperand(); 1217} 1218 1219SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1220 SDOperand N0 = N->getOperand(0); 1221 SDOperand N1 = N->getOperand(1); 1222 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1223 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1224 MVT::ValueType VT = N->getValueType(0); 1225 1226 // fold vector ops 1227 if (MVT::isVector(VT)) { 1228 SDOperand FoldedVOp = SimplifyVBinOp(N); 1229 if (FoldedVOp.Val) return FoldedVOp; 1230 } 1231 1232 // fold (sdiv c1, c2) -> c1/c2 1233 if (N0C && N1C && !N1C->isNullValue()) 1234 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1235 // fold (sdiv X, 1) -> X 1236 if (N1C && N1C->getSignExtended() == 1LL) 1237 return N0; 1238 // fold (sdiv X, -1) -> 0-X 1239 if (N1C && N1C->isAllOnesValue()) 1240 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1241 // If we know the sign bits of both operands are zero, strength reduce to a 1242 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1243 if (!MVT::isVector(VT)) { 1244 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1245 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1246 } 1247 // fold (sdiv X, pow2) -> simple ops after legalize 1248 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1249 (isPowerOf2_64(N1C->getSignExtended()) || 1250 isPowerOf2_64(-N1C->getSignExtended()))) { 1251 // If dividing by powers of two is cheap, then don't perform the following 1252 // fold. 1253 if (TLI.isPow2DivCheap()) 1254 return SDOperand(); 1255 int64_t pow2 = N1C->getSignExtended(); 1256 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1257 unsigned lg2 = Log2_64(abs2); 1258 // Splat the sign bit into the register 1259 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1260 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1261 TLI.getShiftAmountTy())); 1262 AddToWorkList(SGN.Val); 1263 // Add (N0 < 0) ? abs2 - 1 : 0; 1264 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1265 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1266 TLI.getShiftAmountTy())); 1267 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1268 AddToWorkList(SRL.Val); 1269 AddToWorkList(ADD.Val); // Divide by pow2 1270 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1271 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1272 // If we're dividing by a positive value, we're done. Otherwise, we must 1273 // negate the result. 1274 if (pow2 > 0) 1275 return SRA; 1276 AddToWorkList(SRA.Val); 1277 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1278 } 1279 // if integer divide is expensive and we satisfy the requirements, emit an 1280 // alternate sequence. 1281 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1282 !TLI.isIntDivCheap()) { 1283 SDOperand Op = BuildSDIV(N); 1284 if (Op.Val) return Op; 1285 } 1286 1287 // undef / X -> 0 1288 if (N0.getOpcode() == ISD::UNDEF) 1289 return DAG.getConstant(0, VT); 1290 // X / undef -> undef 1291 if (N1.getOpcode() == ISD::UNDEF) 1292 return N1; 1293 1294 return SDOperand(); 1295} 1296 1297SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1298 SDOperand N0 = N->getOperand(0); 1299 SDOperand N1 = N->getOperand(1); 1300 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1301 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1302 MVT::ValueType VT = N->getValueType(0); 1303 1304 // fold vector ops 1305 if (MVT::isVector(VT)) { 1306 SDOperand FoldedVOp = SimplifyVBinOp(N); 1307 if (FoldedVOp.Val) return FoldedVOp; 1308 } 1309 1310 // fold (udiv c1, c2) -> c1/c2 1311 if (N0C && N1C && !N1C->isNullValue()) 1312 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1313 // fold (udiv x, (1 << c)) -> x >>u c 1314 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1315 return DAG.getNode(ISD::SRL, VT, N0, 1316 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1317 TLI.getShiftAmountTy())); 1318 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1319 if (N1.getOpcode() == ISD::SHL) { 1320 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1321 if (SHC->getAPIntValue().isPowerOf2()) { 1322 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1323 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1324 DAG.getConstant(SHC->getAPIntValue() 1325 .logBase2(), 1326 ADDVT)); 1327 AddToWorkList(Add.Val); 1328 return DAG.getNode(ISD::SRL, VT, N0, Add); 1329 } 1330 } 1331 } 1332 // fold (udiv x, c) -> alternate 1333 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1334 SDOperand Op = BuildUDIV(N); 1335 if (Op.Val) return Op; 1336 } 1337 1338 // undef / X -> 0 1339 if (N0.getOpcode() == ISD::UNDEF) 1340 return DAG.getConstant(0, VT); 1341 // X / undef -> undef 1342 if (N1.getOpcode() == ISD::UNDEF) 1343 return N1; 1344 1345 return SDOperand(); 1346} 1347 1348SDOperand DAGCombiner::visitSREM(SDNode *N) { 1349 SDOperand N0 = N->getOperand(0); 1350 SDOperand N1 = N->getOperand(1); 1351 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1352 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1353 MVT::ValueType VT = N->getValueType(0); 1354 1355 // fold (srem c1, c2) -> c1%c2 1356 if (N0C && N1C && !N1C->isNullValue()) 1357 return DAG.getNode(ISD::SREM, VT, N0, N1); 1358 // If we know the sign bits of both operands are zero, strength reduce to a 1359 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1360 if (!MVT::isVector(VT)) { 1361 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1362 return DAG.getNode(ISD::UREM, VT, N0, N1); 1363 } 1364 1365 // If X/C can be simplified by the division-by-constant logic, lower 1366 // X%C to the equivalent of X-X/C*C. 1367 if (N1C && !N1C->isNullValue()) { 1368 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1369 AddToWorkList(Div.Val); 1370 SDOperand OptimizedDiv = combine(Div.Val); 1371 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1372 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1373 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1374 AddToWorkList(Mul.Val); 1375 return Sub; 1376 } 1377 } 1378 1379 // undef % X -> 0 1380 if (N0.getOpcode() == ISD::UNDEF) 1381 return DAG.getConstant(0, VT); 1382 // X % undef -> undef 1383 if (N1.getOpcode() == ISD::UNDEF) 1384 return N1; 1385 1386 return SDOperand(); 1387} 1388 1389SDOperand DAGCombiner::visitUREM(SDNode *N) { 1390 SDOperand N0 = N->getOperand(0); 1391 SDOperand N1 = N->getOperand(1); 1392 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1393 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1394 MVT::ValueType VT = N->getValueType(0); 1395 1396 // fold (urem c1, c2) -> c1%c2 1397 if (N0C && N1C && !N1C->isNullValue()) 1398 return DAG.getNode(ISD::UREM, VT, N0, N1); 1399 // fold (urem x, pow2) -> (and x, pow2-1) 1400 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1401 return DAG.getNode(ISD::AND, VT, N0, 1402 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1403 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1404 if (N1.getOpcode() == ISD::SHL) { 1405 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1406 if (SHC->getAPIntValue().isPowerOf2()) { 1407 SDOperand Add = 1408 DAG.getNode(ISD::ADD, VT, N1, 1409 DAG.getConstant(APInt::getAllOnesValue(MVT::getSizeInBits(VT)), 1410 VT)); 1411 AddToWorkList(Add.Val); 1412 return DAG.getNode(ISD::AND, VT, N0, Add); 1413 } 1414 } 1415 } 1416 1417 // If X/C can be simplified by the division-by-constant logic, lower 1418 // X%C to the equivalent of X-X/C*C. 1419 if (N1C && !N1C->isNullValue()) { 1420 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1421 SDOperand OptimizedDiv = combine(Div.Val); 1422 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1423 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1424 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1425 AddToWorkList(Mul.Val); 1426 return Sub; 1427 } 1428 } 1429 1430 // undef % X -> 0 1431 if (N0.getOpcode() == ISD::UNDEF) 1432 return DAG.getConstant(0, VT); 1433 // X % undef -> undef 1434 if (N1.getOpcode() == ISD::UNDEF) 1435 return N1; 1436 1437 return SDOperand(); 1438} 1439 1440SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1441 SDOperand N0 = N->getOperand(0); 1442 SDOperand N1 = N->getOperand(1); 1443 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1444 MVT::ValueType VT = N->getValueType(0); 1445 1446 // fold (mulhs x, 0) -> 0 1447 if (N1C && N1C->isNullValue()) 1448 return N1; 1449 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1450 if (N1C && N1C->getAPIntValue() == 1) 1451 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1452 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1453 TLI.getShiftAmountTy())); 1454 // fold (mulhs x, undef) -> 0 1455 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1456 return DAG.getConstant(0, VT); 1457 1458 return SDOperand(); 1459} 1460 1461SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1462 SDOperand N0 = N->getOperand(0); 1463 SDOperand N1 = N->getOperand(1); 1464 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1465 MVT::ValueType VT = N->getValueType(0); 1466 1467 // fold (mulhu x, 0) -> 0 1468 if (N1C && N1C->isNullValue()) 1469 return N1; 1470 // fold (mulhu x, 1) -> 0 1471 if (N1C && N1C->getAPIntValue() == 1) 1472 return DAG.getConstant(0, N0.getValueType()); 1473 // fold (mulhu x, undef) -> 0 1474 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1475 return DAG.getConstant(0, VT); 1476 1477 return SDOperand(); 1478} 1479 1480/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1481/// compute two values. LoOp and HiOp give the opcodes for the two computations 1482/// that are being performed. Return true if a simplification was made. 1483/// 1484SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1485 unsigned HiOp) { 1486 // If the high half is not needed, just compute the low half. 1487 bool HiExists = N->hasAnyUseOfValue(1); 1488 if (!HiExists && 1489 (!AfterLegalize || 1490 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1491 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1492 N->getNumOperands()); 1493 return CombineTo(N, Res, Res); 1494 } 1495 1496 // If the low half is not needed, just compute the high half. 1497 bool LoExists = N->hasAnyUseOfValue(0); 1498 if (!LoExists && 1499 (!AfterLegalize || 1500 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1501 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1502 N->getNumOperands()); 1503 return CombineTo(N, Res, Res); 1504 } 1505 1506 // If both halves are used, return as it is. 1507 if (LoExists && HiExists) 1508 return SDOperand(); 1509 1510 // If the two computed results can be simplified separately, separate them. 1511 if (LoExists) { 1512 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1513 N->op_begin(), N->getNumOperands()); 1514 AddToWorkList(Lo.Val); 1515 SDOperand LoOpt = combine(Lo.Val); 1516 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1517 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) 1518 return CombineTo(N, LoOpt, LoOpt); 1519 } 1520 1521 if (HiExists) { 1522 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1523 N->op_begin(), N->getNumOperands()); 1524 AddToWorkList(Hi.Val); 1525 SDOperand HiOpt = combine(Hi.Val); 1526 if (HiOpt.Val && HiOpt != Hi && 1527 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) 1528 return CombineTo(N, HiOpt, HiOpt); 1529 } 1530 return SDOperand(); 1531} 1532 1533SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1534 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1535 if (Res.Val) return Res; 1536 1537 return SDOperand(); 1538} 1539 1540SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1541 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1542 if (Res.Val) return Res; 1543 1544 return SDOperand(); 1545} 1546 1547SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1548 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1549 if (Res.Val) return Res; 1550 1551 return SDOperand(); 1552} 1553 1554SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1555 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1556 if (Res.Val) return Res; 1557 1558 return SDOperand(); 1559} 1560 1561/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1562/// two operands of the same opcode, try to simplify it. 1563SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1564 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1565 MVT::ValueType VT = N0.getValueType(); 1566 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1567 1568 // For each of OP in AND/OR/XOR: 1569 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1570 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1571 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1572 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1573 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1574 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1575 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1576 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1577 N0.getOperand(0).getValueType(), 1578 N0.getOperand(0), N1.getOperand(0)); 1579 AddToWorkList(ORNode.Val); 1580 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1581 } 1582 1583 // For each of OP in SHL/SRL/SRA/AND... 1584 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1585 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1586 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1587 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1588 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1589 N0.getOperand(1) == N1.getOperand(1)) { 1590 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1591 N0.getOperand(0).getValueType(), 1592 N0.getOperand(0), N1.getOperand(0)); 1593 AddToWorkList(ORNode.Val); 1594 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1595 } 1596 1597 return SDOperand(); 1598} 1599 1600SDOperand DAGCombiner::visitAND(SDNode *N) { 1601 SDOperand N0 = N->getOperand(0); 1602 SDOperand N1 = N->getOperand(1); 1603 SDOperand LL, LR, RL, RR, CC0, CC1; 1604 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1605 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1606 MVT::ValueType VT = N1.getValueType(); 1607 unsigned BitWidth = MVT::getSizeInBits(VT); 1608 1609 // fold vector ops 1610 if (MVT::isVector(VT)) { 1611 SDOperand FoldedVOp = SimplifyVBinOp(N); 1612 if (FoldedVOp.Val) return FoldedVOp; 1613 } 1614 1615 // fold (and x, undef) -> 0 1616 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1617 return DAG.getConstant(0, VT); 1618 // fold (and c1, c2) -> c1&c2 1619 if (N0C && N1C) 1620 return DAG.getNode(ISD::AND, VT, N0, N1); 1621 // canonicalize constant to RHS 1622 if (N0C && !N1C) 1623 return DAG.getNode(ISD::AND, VT, N1, N0); 1624 // fold (and x, -1) -> x 1625 if (N1C && N1C->isAllOnesValue()) 1626 return N0; 1627 // if (and x, c) is known to be zero, return 0 1628 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 1629 APInt::getAllOnesValue(BitWidth))) 1630 return DAG.getConstant(0, VT); 1631 // reassociate and 1632 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1633 if (RAND.Val != 0) 1634 return RAND; 1635 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1636 if (N1C && N0.getOpcode() == ISD::OR) 1637 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1638 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1639 return N1; 1640 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1641 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1642 SDOperand N0Op0 = N0.getOperand(0); 1643 APInt Mask = ~N1C->getAPIntValue(); 1644 Mask.trunc(N0Op0.getValueSizeInBits()); 1645 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1646 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1647 N0Op0); 1648 1649 // Replace uses of the AND with uses of the Zero extend node. 1650 CombineTo(N, Zext); 1651 1652 // We actually want to replace all uses of the any_extend with the 1653 // zero_extend, to avoid duplicating things. This will later cause this 1654 // AND to be folded. 1655 CombineTo(N0.Val, Zext); 1656 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1657 } 1658 } 1659 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1660 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1661 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1662 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1663 1664 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1665 MVT::isInteger(LL.getValueType())) { 1666 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1667 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1668 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1669 AddToWorkList(ORNode.Val); 1670 return DAG.getSetCC(VT, ORNode, LR, Op1); 1671 } 1672 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1673 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1674 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1675 AddToWorkList(ANDNode.Val); 1676 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1677 } 1678 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1679 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1680 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1681 AddToWorkList(ORNode.Val); 1682 return DAG.getSetCC(VT, ORNode, LR, Op1); 1683 } 1684 } 1685 // canonicalize equivalent to ll == rl 1686 if (LL == RR && LR == RL) { 1687 Op1 = ISD::getSetCCSwappedOperands(Op1); 1688 std::swap(RL, RR); 1689 } 1690 if (LL == RL && LR == RR) { 1691 bool isInteger = MVT::isInteger(LL.getValueType()); 1692 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1693 if (Result != ISD::SETCC_INVALID) 1694 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1695 } 1696 } 1697 1698 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1699 if (N0.getOpcode() == N1.getOpcode()) { 1700 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1701 if (Tmp.Val) return Tmp; 1702 } 1703 1704 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1705 // fold (and (sra)) -> (and (srl)) when possible. 1706 if (!MVT::isVector(VT) && 1707 SimplifyDemandedBits(SDOperand(N, 0))) 1708 return SDOperand(N, 0); 1709 // fold (zext_inreg (extload x)) -> (zextload x) 1710 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1711 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1712 MVT::ValueType EVT = LN0->getMemoryVT(); 1713 // If we zero all the possible extended bits, then we can turn this into 1714 // a zextload if we are running before legalize or the operation is legal. 1715 unsigned BitWidth = N1.getValueSizeInBits(); 1716 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1717 BitWidth - MVT::getSizeInBits(EVT))) && 1718 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1719 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1720 LN0->getBasePtr(), LN0->getSrcValue(), 1721 LN0->getSrcValueOffset(), EVT, 1722 LN0->isVolatile(), 1723 LN0->getAlignment()); 1724 AddToWorkList(N); 1725 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1726 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1727 } 1728 } 1729 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1730 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1731 N0.hasOneUse()) { 1732 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1733 MVT::ValueType EVT = LN0->getMemoryVT(); 1734 // If we zero all the possible extended bits, then we can turn this into 1735 // a zextload if we are running before legalize or the operation is legal. 1736 unsigned BitWidth = N1.getValueSizeInBits(); 1737 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1738 BitWidth - MVT::getSizeInBits(EVT))) && 1739 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1740 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1741 LN0->getBasePtr(), LN0->getSrcValue(), 1742 LN0->getSrcValueOffset(), EVT, 1743 LN0->isVolatile(), 1744 LN0->getAlignment()); 1745 AddToWorkList(N); 1746 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1747 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1748 } 1749 } 1750 1751 // fold (and (load x), 255) -> (zextload x, i8) 1752 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1753 if (N1C && N0.getOpcode() == ISD::LOAD) { 1754 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1755 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1756 LN0->isUnindexed() && N0.hasOneUse()) { 1757 MVT::ValueType EVT, LoadedVT; 1758 if (N1C->getAPIntValue() == 255) 1759 EVT = MVT::i8; 1760 else if (N1C->getAPIntValue() == 65535) 1761 EVT = MVT::i16; 1762 else if (N1C->getAPIntValue() == ~0U) 1763 EVT = MVT::i32; 1764 else 1765 EVT = MVT::Other; 1766 1767 LoadedVT = LN0->getMemoryVT(); 1768 if (EVT != MVT::Other && LoadedVT > EVT && 1769 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1770 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1771 // For big endian targets, we need to add an offset to the pointer to 1772 // load the correct bytes. For little endian systems, we merely need to 1773 // read fewer bytes from the same pointer. 1774 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1775 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1776 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1777 unsigned Alignment = LN0->getAlignment(); 1778 SDOperand NewPtr = LN0->getBasePtr(); 1779 if (TLI.isBigEndian()) { 1780 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1781 DAG.getConstant(PtrOff, PtrType)); 1782 Alignment = MinAlign(Alignment, PtrOff); 1783 } 1784 AddToWorkList(NewPtr.Val); 1785 SDOperand Load = 1786 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1787 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1788 LN0->isVolatile(), Alignment); 1789 AddToWorkList(N); 1790 CombineTo(N0.Val, Load, Load.getValue(1)); 1791 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1792 } 1793 } 1794 } 1795 1796 return SDOperand(); 1797} 1798 1799SDOperand DAGCombiner::visitOR(SDNode *N) { 1800 SDOperand N0 = N->getOperand(0); 1801 SDOperand N1 = N->getOperand(1); 1802 SDOperand LL, LR, RL, RR, CC0, CC1; 1803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1805 MVT::ValueType VT = N1.getValueType(); 1806 1807 // fold vector ops 1808 if (MVT::isVector(VT)) { 1809 SDOperand FoldedVOp = SimplifyVBinOp(N); 1810 if (FoldedVOp.Val) return FoldedVOp; 1811 } 1812 1813 // fold (or x, undef) -> -1 1814 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1815 return DAG.getConstant(~0ULL, VT); 1816 // fold (or c1, c2) -> c1|c2 1817 if (N0C && N1C) 1818 return DAG.getNode(ISD::OR, VT, N0, N1); 1819 // canonicalize constant to RHS 1820 if (N0C && !N1C) 1821 return DAG.getNode(ISD::OR, VT, N1, N0); 1822 // fold (or x, 0) -> x 1823 if (N1C && N1C->isNullValue()) 1824 return N0; 1825 // fold (or x, -1) -> -1 1826 if (N1C && N1C->isAllOnesValue()) 1827 return N1; 1828 // fold (or x, c) -> c iff (x & ~c) == 0 1829 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1830 return N1; 1831 // reassociate or 1832 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1833 if (ROR.Val != 0) 1834 return ROR; 1835 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1836 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1837 isa<ConstantSDNode>(N0.getOperand(1))) { 1838 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1839 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1840 N1), 1841 DAG.getConstant(N1C->getAPIntValue() | 1842 C1->getAPIntValue(), VT)); 1843 } 1844 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1845 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1846 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1847 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1848 1849 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1850 MVT::isInteger(LL.getValueType())) { 1851 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1852 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1853 if (cast<ConstantSDNode>(LR)->isNullValue() && 1854 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1855 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1856 AddToWorkList(ORNode.Val); 1857 return DAG.getSetCC(VT, ORNode, LR, Op1); 1858 } 1859 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1860 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1861 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1862 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1863 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1864 AddToWorkList(ANDNode.Val); 1865 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1866 } 1867 } 1868 // canonicalize equivalent to ll == rl 1869 if (LL == RR && LR == RL) { 1870 Op1 = ISD::getSetCCSwappedOperands(Op1); 1871 std::swap(RL, RR); 1872 } 1873 if (LL == RL && LR == RR) { 1874 bool isInteger = MVT::isInteger(LL.getValueType()); 1875 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1876 if (Result != ISD::SETCC_INVALID) 1877 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1878 } 1879 } 1880 1881 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1882 if (N0.getOpcode() == N1.getOpcode()) { 1883 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1884 if (Tmp.Val) return Tmp; 1885 } 1886 1887 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1888 if (N0.getOpcode() == ISD::AND && 1889 N1.getOpcode() == ISD::AND && 1890 N0.getOperand(1).getOpcode() == ISD::Constant && 1891 N1.getOperand(1).getOpcode() == ISD::Constant && 1892 // Don't increase # computations. 1893 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1894 // We can only do this xform if we know that bits from X that are set in C2 1895 // but not in C1 are already zero. Likewise for Y. 1896 const APInt &LHSMask = 1897 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1898 const APInt &RHSMask = 1899 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1900 1901 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1902 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1903 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1904 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1905 } 1906 } 1907 1908 1909 // See if this is some rotate idiom. 1910 if (SDNode *Rot = MatchRotate(N0, N1)) 1911 return SDOperand(Rot, 0); 1912 1913 return SDOperand(); 1914} 1915 1916 1917/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1918static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1919 if (Op.getOpcode() == ISD::AND) { 1920 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1921 Mask = Op.getOperand(1); 1922 Op = Op.getOperand(0); 1923 } else { 1924 return false; 1925 } 1926 } 1927 1928 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1929 Shift = Op; 1930 return true; 1931 } 1932 return false; 1933} 1934 1935 1936// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1937// idioms for rotate, and if the target supports rotation instructions, generate 1938// a rot[lr]. 1939SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1940 // Must be a legal type. Expanded an promoted things won't work with rotates. 1941 MVT::ValueType VT = LHS.getValueType(); 1942 if (!TLI.isTypeLegal(VT)) return 0; 1943 1944 // The target must have at least one rotate flavor. 1945 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1946 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1947 if (!HasROTL && !HasROTR) return 0; 1948 1949 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1950 SDOperand LHSShift; // The shift. 1951 SDOperand LHSMask; // AND value if any. 1952 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1953 return 0; // Not part of a rotate. 1954 1955 SDOperand RHSShift; // The shift. 1956 SDOperand RHSMask; // AND value if any. 1957 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1958 return 0; // Not part of a rotate. 1959 1960 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1961 return 0; // Not shifting the same value. 1962 1963 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1964 return 0; // Shifts must disagree. 1965 1966 // Canonicalize shl to left side in a shl/srl pair. 1967 if (RHSShift.getOpcode() == ISD::SHL) { 1968 std::swap(LHS, RHS); 1969 std::swap(LHSShift, RHSShift); 1970 std::swap(LHSMask , RHSMask ); 1971 } 1972 1973 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1974 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1975 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1976 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1977 1978 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1979 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1980 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1981 RHSShiftAmt.getOpcode() == ISD::Constant) { 1982 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1983 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1984 if ((LShVal + RShVal) != OpSizeInBits) 1985 return 0; 1986 1987 SDOperand Rot; 1988 if (HasROTL) 1989 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1990 else 1991 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1992 1993 // If there is an AND of either shifted operand, apply it to the result. 1994 if (LHSMask.Val || RHSMask.Val) { 1995 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 1996 1997 if (LHSMask.Val) { 1998 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 1999 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2000 } 2001 if (RHSMask.Val) { 2002 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2003 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2004 } 2005 2006 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2007 } 2008 2009 return Rot.Val; 2010 } 2011 2012 // If there is a mask here, and we have a variable shift, we can't be sure 2013 // that we're masking out the right stuff. 2014 if (LHSMask.Val || RHSMask.Val) 2015 return 0; 2016 2017 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2018 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2019 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2020 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2021 if (ConstantSDNode *SUBC = 2022 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2023 if (SUBC->getAPIntValue() == OpSizeInBits) { 2024 if (HasROTL) 2025 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2026 else 2027 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2028 } 2029 } 2030 } 2031 2032 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2033 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2034 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2035 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2036 if (ConstantSDNode *SUBC = 2037 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2038 if (SUBC->getAPIntValue() == OpSizeInBits) { 2039 if (HasROTL) 2040 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2041 else 2042 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2043 } 2044 } 2045 } 2046 2047 // Look for sign/zext/any-extended cases: 2048 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2049 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2050 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2051 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2052 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2053 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2054 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 2055 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 2056 if (RExtOp0.getOpcode() == ISD::SUB && 2057 RExtOp0.getOperand(1) == LExtOp0) { 2058 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2059 // (rotr x, y) 2060 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2061 // (rotl x, (sub 32, y)) 2062 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2063 if (SUBC->getAPIntValue() == OpSizeInBits) { 2064 if (HasROTL) 2065 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2066 else 2067 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2068 } 2069 } 2070 } else if (LExtOp0.getOpcode() == ISD::SUB && 2071 RExtOp0 == LExtOp0.getOperand(1)) { 2072 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2073 // (rotl x, y) 2074 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2075 // (rotr x, (sub 32, y)) 2076 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2077 if (SUBC->getAPIntValue() == OpSizeInBits) { 2078 if (HasROTL) 2079 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2080 else 2081 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2082 } 2083 } 2084 } 2085 } 2086 2087 return 0; 2088} 2089 2090 2091SDOperand DAGCombiner::visitXOR(SDNode *N) { 2092 SDOperand N0 = N->getOperand(0); 2093 SDOperand N1 = N->getOperand(1); 2094 SDOperand LHS, RHS, CC; 2095 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2096 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2097 MVT::ValueType VT = N0.getValueType(); 2098 2099 // fold vector ops 2100 if (MVT::isVector(VT)) { 2101 SDOperand FoldedVOp = SimplifyVBinOp(N); 2102 if (FoldedVOp.Val) return FoldedVOp; 2103 } 2104 2105 // fold (xor x, undef) -> undef 2106 if (N0.getOpcode() == ISD::UNDEF) 2107 return N0; 2108 if (N1.getOpcode() == ISD::UNDEF) 2109 return N1; 2110 // fold (xor c1, c2) -> c1^c2 2111 if (N0C && N1C) 2112 return DAG.getNode(ISD::XOR, VT, N0, N1); 2113 // canonicalize constant to RHS 2114 if (N0C && !N1C) 2115 return DAG.getNode(ISD::XOR, VT, N1, N0); 2116 // fold (xor x, 0) -> x 2117 if (N1C && N1C->isNullValue()) 2118 return N0; 2119 // reassociate xor 2120 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2121 if (RXOR.Val != 0) 2122 return RXOR; 2123 // fold !(x cc y) -> (x !cc y) 2124 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2125 bool isInt = MVT::isInteger(LHS.getValueType()); 2126 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2127 isInt); 2128 if (N0.getOpcode() == ISD::SETCC) 2129 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2130 if (N0.getOpcode() == ISD::SELECT_CC) 2131 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2132 assert(0 && "Unhandled SetCC Equivalent!"); 2133 abort(); 2134 } 2135 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2136 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2137 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2138 SDOperand V = N0.getOperand(0); 2139 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2140 DAG.getConstant(1, V.getValueType())); 2141 AddToWorkList(V.Val); 2142 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2143 } 2144 2145 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2146 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2147 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2148 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2149 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2150 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2151 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2152 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2153 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2154 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2155 } 2156 } 2157 // fold !(x or y) -> (!x and !y) iff x or y are constants 2158 if (N1C && N1C->isAllOnesValue() && 2159 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2160 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2161 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2162 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2163 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2164 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2165 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2166 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2167 } 2168 } 2169 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2170 if (N1C && N0.getOpcode() == ISD::XOR) { 2171 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2172 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2173 if (N00C) 2174 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2175 DAG.getConstant(N1C->getAPIntValue()^ 2176 N00C->getAPIntValue(), VT)); 2177 if (N01C) 2178 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2179 DAG.getConstant(N1C->getAPIntValue()^ 2180 N01C->getAPIntValue(), VT)); 2181 } 2182 // fold (xor x, x) -> 0 2183 if (N0 == N1) { 2184 if (!MVT::isVector(VT)) { 2185 return DAG.getConstant(0, VT); 2186 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2187 // Produce a vector of zeros. 2188 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2189 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2190 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2191 } 2192 } 2193 2194 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2195 if (N0.getOpcode() == N1.getOpcode()) { 2196 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2197 if (Tmp.Val) return Tmp; 2198 } 2199 2200 // Simplify the expression using non-local knowledge. 2201 if (!MVT::isVector(VT) && 2202 SimplifyDemandedBits(SDOperand(N, 0))) 2203 return SDOperand(N, 0); 2204 2205 return SDOperand(); 2206} 2207 2208/// visitShiftByConstant - Handle transforms common to the three shifts, when 2209/// the shift amount is a constant. 2210SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2211 SDNode *LHS = N->getOperand(0).Val; 2212 if (!LHS->hasOneUse()) return SDOperand(); 2213 2214 // We want to pull some binops through shifts, so that we have (and (shift)) 2215 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2216 // thing happens with address calculations, so it's important to canonicalize 2217 // it. 2218 bool HighBitSet = false; // Can we transform this if the high bit is set? 2219 2220 switch (LHS->getOpcode()) { 2221 default: return SDOperand(); 2222 case ISD::OR: 2223 case ISD::XOR: 2224 HighBitSet = false; // We can only transform sra if the high bit is clear. 2225 break; 2226 case ISD::AND: 2227 HighBitSet = true; // We can only transform sra if the high bit is set. 2228 break; 2229 case ISD::ADD: 2230 if (N->getOpcode() != ISD::SHL) 2231 return SDOperand(); // only shl(add) not sr[al](add). 2232 HighBitSet = false; // We can only transform sra if the high bit is clear. 2233 break; 2234 } 2235 2236 // We require the RHS of the binop to be a constant as well. 2237 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2238 if (!BinOpCst) return SDOperand(); 2239 2240 2241 // FIXME: disable this for unless the input to the binop is a shift by a 2242 // constant. If it is not a shift, it pessimizes some common cases like: 2243 // 2244 //void foo(int *X, int i) { X[i & 1235] = 1; } 2245 //int bar(int *X, int i) { return X[i & 255]; } 2246 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2247 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2248 BinOpLHSVal->getOpcode() != ISD::SRA && 2249 BinOpLHSVal->getOpcode() != ISD::SRL) || 2250 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2251 return SDOperand(); 2252 2253 MVT::ValueType VT = N->getValueType(0); 2254 2255 // If this is a signed shift right, and the high bit is modified 2256 // by the logical operation, do not perform the transformation. 2257 // The highBitSet boolean indicates the value of the high bit of 2258 // the constant which would cause it to be modified for this 2259 // operation. 2260 if (N->getOpcode() == ISD::SRA) { 2261 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2262 if (BinOpRHSSignSet != HighBitSet) 2263 return SDOperand(); 2264 } 2265 2266 // Fold the constants, shifting the binop RHS by the shift amount. 2267 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2268 LHS->getOperand(1), N->getOperand(1)); 2269 2270 // Create the new shift. 2271 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2272 N->getOperand(1)); 2273 2274 // Create the new binop. 2275 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2276} 2277 2278 2279SDOperand DAGCombiner::visitSHL(SDNode *N) { 2280 SDOperand N0 = N->getOperand(0); 2281 SDOperand N1 = N->getOperand(1); 2282 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2283 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2284 MVT::ValueType VT = N0.getValueType(); 2285 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2286 2287 // fold (shl c1, c2) -> c1<<c2 2288 if (N0C && N1C) 2289 return DAG.getNode(ISD::SHL, VT, N0, N1); 2290 // fold (shl 0, x) -> 0 2291 if (N0C && N0C->isNullValue()) 2292 return N0; 2293 // fold (shl x, c >= size(x)) -> undef 2294 if (N1C && N1C->getValue() >= OpSizeInBits) 2295 return DAG.getNode(ISD::UNDEF, VT); 2296 // fold (shl x, 0) -> x 2297 if (N1C && N1C->isNullValue()) 2298 return N0; 2299 // if (shl x, c) is known to be zero, return 0 2300 if (DAG.MaskedValueIsZero(SDOperand(N, 0), 2301 APInt::getAllOnesValue(MVT::getSizeInBits(VT)))) 2302 return DAG.getConstant(0, VT); 2303 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2304 return SDOperand(N, 0); 2305 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2306 if (N1C && N0.getOpcode() == ISD::SHL && 2307 N0.getOperand(1).getOpcode() == ISD::Constant) { 2308 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2309 uint64_t c2 = N1C->getValue(); 2310 if (c1 + c2 > OpSizeInBits) 2311 return DAG.getConstant(0, VT); 2312 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2313 DAG.getConstant(c1 + c2, N1.getValueType())); 2314 } 2315 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2316 // (srl (and x, -1 << c1), c1-c2) 2317 if (N1C && N0.getOpcode() == ISD::SRL && 2318 N0.getOperand(1).getOpcode() == ISD::Constant) { 2319 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2320 uint64_t c2 = N1C->getValue(); 2321 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2322 DAG.getConstant(~0ULL << c1, VT)); 2323 if (c2 > c1) 2324 return DAG.getNode(ISD::SHL, VT, Mask, 2325 DAG.getConstant(c2-c1, N1.getValueType())); 2326 else 2327 return DAG.getNode(ISD::SRL, VT, Mask, 2328 DAG.getConstant(c1-c2, N1.getValueType())); 2329 } 2330 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2331 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2332 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2333 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2334 2335 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2336} 2337 2338SDOperand DAGCombiner::visitSRA(SDNode *N) { 2339 SDOperand N0 = N->getOperand(0); 2340 SDOperand N1 = N->getOperand(1); 2341 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2342 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2343 MVT::ValueType VT = N0.getValueType(); 2344 2345 // fold (sra c1, c2) -> c1>>c2 2346 if (N0C && N1C) 2347 return DAG.getNode(ISD::SRA, VT, N0, N1); 2348 // fold (sra 0, x) -> 0 2349 if (N0C && N0C->isNullValue()) 2350 return N0; 2351 // fold (sra -1, x) -> -1 2352 if (N0C && N0C->isAllOnesValue()) 2353 return N0; 2354 // fold (sra x, c >= size(x)) -> undef 2355 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2356 return DAG.getNode(ISD::UNDEF, VT); 2357 // fold (sra x, 0) -> x 2358 if (N1C && N1C->isNullValue()) 2359 return N0; 2360 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2361 // sext_inreg. 2362 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2363 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2364 MVT::ValueType EVT; 2365 switch (LowBits) { 2366 default: EVT = MVT::Other; break; 2367 case 1: EVT = MVT::i1; break; 2368 case 8: EVT = MVT::i8; break; 2369 case 16: EVT = MVT::i16; break; 2370 case 32: EVT = MVT::i32; break; 2371 } 2372 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2373 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2374 DAG.getValueType(EVT)); 2375 } 2376 2377 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2378 if (N1C && N0.getOpcode() == ISD::SRA) { 2379 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2380 unsigned Sum = N1C->getValue() + C1->getValue(); 2381 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2382 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2383 DAG.getConstant(Sum, N1C->getValueType(0))); 2384 } 2385 } 2386 2387 // fold sra (shl X, m), result_size - n 2388 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2389 // result_size - n != m. 2390 // If truncate is free for the target sext(shl) is likely to result in better 2391 // code. 2392 if (N0.getOpcode() == ISD::SHL) { 2393 // Get the two constanst of the shifts, CN0 = m, CN = n. 2394 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2395 if (N01C && N1C) { 2396 // Determine what the truncate's result bitsize and type would be. 2397 unsigned VTValSize = MVT::getSizeInBits(VT); 2398 MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue()); 2399 // Determine the residual right-shift amount. 2400 unsigned ShiftAmt = N1C->getValue() - N01C->getValue(); 2401 2402 // If the shift is not a no-op (in which case this should be just a sign 2403 // extend already), the truncated to type is legal, sign_extend is legal 2404 // on that type, and the the truncate to that type is both legal and free, 2405 // perform the transform. 2406 if (ShiftAmt && 2407 TLI.isTypeLegal(TruncVT) && 2408 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2409 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2410 TLI.isTruncateFree(VT, TruncVT)) { 2411 2412 SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2413 SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2414 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2415 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2416 } 2417 } 2418 } 2419 2420 // Simplify, based on bits shifted out of the LHS. 2421 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2422 return SDOperand(N, 0); 2423 2424 2425 // If the sign bit is known to be zero, switch this to a SRL. 2426 if (DAG.SignBitIsZero(N0)) 2427 return DAG.getNode(ISD::SRL, VT, N0, N1); 2428 2429 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2430} 2431 2432SDOperand DAGCombiner::visitSRL(SDNode *N) { 2433 SDOperand N0 = N->getOperand(0); 2434 SDOperand N1 = N->getOperand(1); 2435 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2436 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2437 MVT::ValueType VT = N0.getValueType(); 2438 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2439 2440 // fold (srl c1, c2) -> c1 >>u c2 2441 if (N0C && N1C) 2442 return DAG.getNode(ISD::SRL, VT, N0, N1); 2443 // fold (srl 0, x) -> 0 2444 if (N0C && N0C->isNullValue()) 2445 return N0; 2446 // fold (srl x, c >= size(x)) -> undef 2447 if (N1C && N1C->getValue() >= OpSizeInBits) 2448 return DAG.getNode(ISD::UNDEF, VT); 2449 // fold (srl x, 0) -> x 2450 if (N1C && N1C->isNullValue()) 2451 return N0; 2452 // if (srl x, c) is known to be zero, return 0 2453 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 2454 APInt::getAllOnesValue(OpSizeInBits))) 2455 return DAG.getConstant(0, VT); 2456 2457 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2458 if (N1C && N0.getOpcode() == ISD::SRL && 2459 N0.getOperand(1).getOpcode() == ISD::Constant) { 2460 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2461 uint64_t c2 = N1C->getValue(); 2462 if (c1 + c2 > OpSizeInBits) 2463 return DAG.getConstant(0, VT); 2464 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2465 DAG.getConstant(c1 + c2, N1.getValueType())); 2466 } 2467 2468 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2469 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2470 // Shifting in all undef bits? 2471 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2472 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2473 return DAG.getNode(ISD::UNDEF, VT); 2474 2475 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2476 AddToWorkList(SmallShift.Val); 2477 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2478 } 2479 2480 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2481 // bit, which is unmodified by sra. 2482 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2483 if (N0.getOpcode() == ISD::SRA) 2484 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2485 } 2486 2487 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2488 if (N1C && N0.getOpcode() == ISD::CTLZ && 2489 N1C->getAPIntValue() == Log2_32(MVT::getSizeInBits(VT))) { 2490 APInt KnownZero, KnownOne; 2491 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 2492 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2493 2494 // If any of the input bits are KnownOne, then the input couldn't be all 2495 // zeros, thus the result of the srl will always be zero. 2496 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2497 2498 // If all of the bits input the to ctlz node are known to be zero, then 2499 // the result of the ctlz is "32" and the result of the shift is one. 2500 APInt UnknownBits = ~KnownZero & Mask; 2501 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2502 2503 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2504 if ((UnknownBits & (UnknownBits-1)) == 0) { 2505 // Okay, we know that only that the single bit specified by UnknownBits 2506 // could be set on input to the CTLZ node. If this bit is set, the SRL 2507 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2508 // to an SRL,XOR pair, which is likely to simplify more. 2509 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2510 SDOperand Op = N0.getOperand(0); 2511 if (ShAmt) { 2512 Op = DAG.getNode(ISD::SRL, VT, Op, 2513 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2514 AddToWorkList(Op.Val); 2515 } 2516 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2517 } 2518 } 2519 2520 // fold operands of srl based on knowledge that the low bits are not 2521 // demanded. 2522 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2523 return SDOperand(N, 0); 2524 2525 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2526} 2527 2528SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2529 SDOperand N0 = N->getOperand(0); 2530 MVT::ValueType VT = N->getValueType(0); 2531 2532 // fold (ctlz c1) -> c2 2533 if (isa<ConstantSDNode>(N0)) 2534 return DAG.getNode(ISD::CTLZ, VT, N0); 2535 return SDOperand(); 2536} 2537 2538SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2539 SDOperand N0 = N->getOperand(0); 2540 MVT::ValueType VT = N->getValueType(0); 2541 2542 // fold (cttz c1) -> c2 2543 if (isa<ConstantSDNode>(N0)) 2544 return DAG.getNode(ISD::CTTZ, VT, N0); 2545 return SDOperand(); 2546} 2547 2548SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2549 SDOperand N0 = N->getOperand(0); 2550 MVT::ValueType VT = N->getValueType(0); 2551 2552 // fold (ctpop c1) -> c2 2553 if (isa<ConstantSDNode>(N0)) 2554 return DAG.getNode(ISD::CTPOP, VT, N0); 2555 return SDOperand(); 2556} 2557 2558SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2559 SDOperand N0 = N->getOperand(0); 2560 SDOperand N1 = N->getOperand(1); 2561 SDOperand N2 = N->getOperand(2); 2562 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2563 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2564 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2565 MVT::ValueType VT = N->getValueType(0); 2566 MVT::ValueType VT0 = N0.getValueType(); 2567 2568 // fold select C, X, X -> X 2569 if (N1 == N2) 2570 return N1; 2571 // fold select true, X, Y -> X 2572 if (N0C && !N0C->isNullValue()) 2573 return N1; 2574 // fold select false, X, Y -> Y 2575 if (N0C && N0C->isNullValue()) 2576 return N2; 2577 // fold select C, 1, X -> C | X 2578 if (MVT::i1 == VT && N1C && N1C->getAPIntValue() == 1) 2579 return DAG.getNode(ISD::OR, VT, N0, N2); 2580 // fold select C, 0, 1 -> ~C 2581 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2582 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2583 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2584 if (VT == VT0) 2585 return XORNode; 2586 AddToWorkList(XORNode.Val); 2587 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2588 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2589 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2590 } 2591 // fold select C, 0, X -> ~C & X 2592 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2593 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2594 AddToWorkList(XORNode.Val); 2595 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2596 } 2597 // fold select C, X, 1 -> ~C | X 2598 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2599 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2600 AddToWorkList(XORNode.Val); 2601 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2602 } 2603 // fold select C, X, 0 -> C & X 2604 // FIXME: this should check for C type == X type, not i1? 2605 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2606 return DAG.getNode(ISD::AND, VT, N0, N1); 2607 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2608 if (MVT::i1 == VT && N0 == N1) 2609 return DAG.getNode(ISD::OR, VT, N0, N2); 2610 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2611 if (MVT::i1 == VT && N0 == N2) 2612 return DAG.getNode(ISD::AND, VT, N0, N1); 2613 2614 // If we can fold this based on the true/false value, do so. 2615 if (SimplifySelectOps(N, N1, N2)) 2616 return SDOperand(N, 0); // Don't revisit N. 2617 2618 // fold selects based on a setcc into other things, such as min/max/abs 2619 if (N0.getOpcode() == ISD::SETCC) { 2620 // FIXME: 2621 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2622 // having to say they don't support SELECT_CC on every type the DAG knows 2623 // about, since there is no way to mark an opcode illegal at all value types 2624 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2625 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2626 N1, N2, N0.getOperand(2)); 2627 else 2628 return SimplifySelect(N0, N1, N2); 2629 } 2630 return SDOperand(); 2631} 2632 2633SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2634 SDOperand N0 = N->getOperand(0); 2635 SDOperand N1 = N->getOperand(1); 2636 SDOperand N2 = N->getOperand(2); 2637 SDOperand N3 = N->getOperand(3); 2638 SDOperand N4 = N->getOperand(4); 2639 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2640 2641 // fold select_cc lhs, rhs, x, x, cc -> x 2642 if (N2 == N3) 2643 return N2; 2644 2645 // Determine if the condition we're dealing with is constant 2646 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2647 if (SCC.Val) AddToWorkList(SCC.Val); 2648 2649 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2650 if (!SCCC->isNullValue()) 2651 return N2; // cond always true -> true val 2652 else 2653 return N3; // cond always false -> false val 2654 } 2655 2656 // Fold to a simpler select_cc 2657 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2658 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2659 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2660 SCC.getOperand(2)); 2661 2662 // If we can fold this based on the true/false value, do so. 2663 if (SimplifySelectOps(N, N2, N3)) 2664 return SDOperand(N, 0); // Don't revisit N. 2665 2666 // fold select_cc into other things, such as min/max/abs 2667 return SimplifySelectCC(N0, N1, N2, N3, CC); 2668} 2669 2670SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2671 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2672 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2673} 2674 2675// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2676// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2677// transformation. Returns true if extension are possible and the above 2678// mentioned transformation is profitable. 2679static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2680 unsigned ExtOpc, 2681 SmallVector<SDNode*, 4> &ExtendNodes, 2682 TargetLowering &TLI) { 2683 bool HasCopyToRegUses = false; 2684 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2685 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2686 UI != UE; ++UI) { 2687 SDNode *User = *UI; 2688 if (User == N) 2689 continue; 2690 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2691 if (User->getOpcode() == ISD::SETCC) { 2692 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2693 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2694 // Sign bits will be lost after a zext. 2695 return false; 2696 bool Add = false; 2697 for (unsigned i = 0; i != 2; ++i) { 2698 SDOperand UseOp = User->getOperand(i); 2699 if (UseOp == N0) 2700 continue; 2701 if (!isa<ConstantSDNode>(UseOp)) 2702 return false; 2703 Add = true; 2704 } 2705 if (Add) 2706 ExtendNodes.push_back(User); 2707 } else { 2708 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2709 SDOperand UseOp = User->getOperand(i); 2710 if (UseOp == N0) { 2711 // If truncate from extended type to original load type is free 2712 // on this target, then it's ok to extend a CopyToReg. 2713 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2714 HasCopyToRegUses = true; 2715 else 2716 return false; 2717 } 2718 } 2719 } 2720 } 2721 2722 if (HasCopyToRegUses) { 2723 bool BothLiveOut = false; 2724 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2725 UI != UE; ++UI) { 2726 SDNode *User = *UI; 2727 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2728 SDOperand UseOp = User->getOperand(i); 2729 if (UseOp.Val == N && UseOp.ResNo == 0) { 2730 BothLiveOut = true; 2731 break; 2732 } 2733 } 2734 } 2735 if (BothLiveOut) 2736 // Both unextended and extended values are live out. There had better be 2737 // good a reason for the transformation. 2738 return ExtendNodes.size(); 2739 } 2740 return true; 2741} 2742 2743SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2744 SDOperand N0 = N->getOperand(0); 2745 MVT::ValueType VT = N->getValueType(0); 2746 2747 // fold (sext c1) -> c1 2748 if (isa<ConstantSDNode>(N0)) 2749 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2750 2751 // fold (sext (sext x)) -> (sext x) 2752 // fold (sext (aext x)) -> (sext x) 2753 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2754 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2755 2756 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2757 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2758 if (N0.getOpcode() == ISD::TRUNCATE) { 2759 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2760 if (NarrowLoad.Val) { 2761 if (NarrowLoad.Val != N0.Val) 2762 CombineTo(N0.Val, NarrowLoad); 2763 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2764 } 2765 } 2766 2767 // See if the value being truncated is already sign extended. If so, just 2768 // eliminate the trunc/sext pair. 2769 if (N0.getOpcode() == ISD::TRUNCATE) { 2770 SDOperand Op = N0.getOperand(0); 2771 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2772 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2773 unsigned DestBits = MVT::getSizeInBits(VT); 2774 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2775 2776 if (OpBits == DestBits) { 2777 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2778 // bits, it is already ready. 2779 if (NumSignBits > DestBits-MidBits) 2780 return Op; 2781 } else if (OpBits < DestBits) { 2782 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2783 // bits, just sext from i32. 2784 if (NumSignBits > OpBits-MidBits) 2785 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2786 } else { 2787 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2788 // bits, just truncate to i32. 2789 if (NumSignBits > OpBits-MidBits) 2790 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2791 } 2792 2793 // fold (sext (truncate x)) -> (sextinreg x). 2794 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2795 N0.getValueType())) { 2796 if (Op.getValueType() < VT) 2797 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2798 else if (Op.getValueType() > VT) 2799 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2800 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2801 DAG.getValueType(N0.getValueType())); 2802 } 2803 } 2804 2805 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2806 if (ISD::isNON_EXTLoad(N0.Val) && 2807 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2808 bool DoXform = true; 2809 SmallVector<SDNode*, 4> SetCCs; 2810 if (!N0.hasOneUse()) 2811 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2812 if (DoXform) { 2813 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2814 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2815 LN0->getBasePtr(), LN0->getSrcValue(), 2816 LN0->getSrcValueOffset(), 2817 N0.getValueType(), 2818 LN0->isVolatile(), 2819 LN0->getAlignment()); 2820 CombineTo(N, ExtLoad); 2821 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2822 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2823 // Extend SetCC uses if necessary. 2824 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2825 SDNode *SetCC = SetCCs[i]; 2826 SmallVector<SDOperand, 4> Ops; 2827 for (unsigned j = 0; j != 2; ++j) { 2828 SDOperand SOp = SetCC->getOperand(j); 2829 if (SOp == Trunc) 2830 Ops.push_back(ExtLoad); 2831 else 2832 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2833 } 2834 Ops.push_back(SetCC->getOperand(2)); 2835 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2836 &Ops[0], Ops.size())); 2837 } 2838 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2839 } 2840 } 2841 2842 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2843 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2844 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2845 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2846 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2847 MVT::ValueType EVT = LN0->getMemoryVT(); 2848 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2849 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2850 LN0->getBasePtr(), LN0->getSrcValue(), 2851 LN0->getSrcValueOffset(), EVT, 2852 LN0->isVolatile(), 2853 LN0->getAlignment()); 2854 CombineTo(N, ExtLoad); 2855 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2856 ExtLoad.getValue(1)); 2857 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2858 } 2859 } 2860 2861 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2862 if (N0.getOpcode() == ISD::SETCC) { 2863 SDOperand SCC = 2864 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2865 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2866 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2867 if (SCC.Val) return SCC; 2868 } 2869 2870 return SDOperand(); 2871} 2872 2873SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2874 SDOperand N0 = N->getOperand(0); 2875 MVT::ValueType VT = N->getValueType(0); 2876 2877 // fold (zext c1) -> c1 2878 if (isa<ConstantSDNode>(N0)) 2879 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2880 // fold (zext (zext x)) -> (zext x) 2881 // fold (zext (aext x)) -> (zext x) 2882 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2883 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2884 2885 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2886 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2887 if (N0.getOpcode() == ISD::TRUNCATE) { 2888 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2889 if (NarrowLoad.Val) { 2890 if (NarrowLoad.Val != N0.Val) 2891 CombineTo(N0.Val, NarrowLoad); 2892 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2893 } 2894 } 2895 2896 // fold (zext (truncate x)) -> (and x, mask) 2897 if (N0.getOpcode() == ISD::TRUNCATE && 2898 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2899 SDOperand Op = N0.getOperand(0); 2900 if (Op.getValueType() < VT) { 2901 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2902 } else if (Op.getValueType() > VT) { 2903 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2904 } 2905 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2906 } 2907 2908 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2909 if (N0.getOpcode() == ISD::AND && 2910 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2911 N0.getOperand(1).getOpcode() == ISD::Constant) { 2912 SDOperand X = N0.getOperand(0).getOperand(0); 2913 if (X.getValueType() < VT) { 2914 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2915 } else if (X.getValueType() > VT) { 2916 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2917 } 2918 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2919 Mask.zext(MVT::getSizeInBits(VT)); 2920 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2921 } 2922 2923 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2924 if (ISD::isNON_EXTLoad(N0.Val) && 2925 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2926 bool DoXform = true; 2927 SmallVector<SDNode*, 4> SetCCs; 2928 if (!N0.hasOneUse()) 2929 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2930 if (DoXform) { 2931 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2932 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2933 LN0->getBasePtr(), LN0->getSrcValue(), 2934 LN0->getSrcValueOffset(), 2935 N0.getValueType(), 2936 LN0->isVolatile(), 2937 LN0->getAlignment()); 2938 CombineTo(N, ExtLoad); 2939 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2940 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2941 // Extend SetCC uses if necessary. 2942 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2943 SDNode *SetCC = SetCCs[i]; 2944 SmallVector<SDOperand, 4> Ops; 2945 for (unsigned j = 0; j != 2; ++j) { 2946 SDOperand SOp = SetCC->getOperand(j); 2947 if (SOp == Trunc) 2948 Ops.push_back(ExtLoad); 2949 else 2950 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2951 } 2952 Ops.push_back(SetCC->getOperand(2)); 2953 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2954 &Ops[0], Ops.size())); 2955 } 2956 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2957 } 2958 } 2959 2960 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2961 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2962 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2963 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2964 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2965 MVT::ValueType EVT = LN0->getMemoryVT(); 2966 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2967 LN0->getBasePtr(), LN0->getSrcValue(), 2968 LN0->getSrcValueOffset(), EVT, 2969 LN0->isVolatile(), 2970 LN0->getAlignment()); 2971 CombineTo(N, ExtLoad); 2972 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2973 ExtLoad.getValue(1)); 2974 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2975 } 2976 2977 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2978 if (N0.getOpcode() == ISD::SETCC) { 2979 SDOperand SCC = 2980 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2981 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2982 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2983 if (SCC.Val) return SCC; 2984 } 2985 2986 return SDOperand(); 2987} 2988 2989SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2990 SDOperand N0 = N->getOperand(0); 2991 MVT::ValueType VT = N->getValueType(0); 2992 2993 // fold (aext c1) -> c1 2994 if (isa<ConstantSDNode>(N0)) 2995 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2996 // fold (aext (aext x)) -> (aext x) 2997 // fold (aext (zext x)) -> (zext x) 2998 // fold (aext (sext x)) -> (sext x) 2999 if (N0.getOpcode() == ISD::ANY_EXTEND || 3000 N0.getOpcode() == ISD::ZERO_EXTEND || 3001 N0.getOpcode() == ISD::SIGN_EXTEND) 3002 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3003 3004 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3005 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3006 if (N0.getOpcode() == ISD::TRUNCATE) { 3007 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 3008 if (NarrowLoad.Val) { 3009 if (NarrowLoad.Val != N0.Val) 3010 CombineTo(N0.Val, NarrowLoad); 3011 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3012 } 3013 } 3014 3015 // fold (aext (truncate x)) 3016 if (N0.getOpcode() == ISD::TRUNCATE) { 3017 SDOperand TruncOp = N0.getOperand(0); 3018 if (TruncOp.getValueType() == VT) 3019 return TruncOp; // x iff x size == zext size. 3020 if (TruncOp.getValueType() > VT) 3021 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3022 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3023 } 3024 3025 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3026 if (N0.getOpcode() == ISD::AND && 3027 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3028 N0.getOperand(1).getOpcode() == ISD::Constant) { 3029 SDOperand X = N0.getOperand(0).getOperand(0); 3030 if (X.getValueType() < VT) { 3031 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3032 } else if (X.getValueType() > VT) { 3033 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3034 } 3035 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3036 Mask.zext(MVT::getSizeInBits(VT)); 3037 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3038 } 3039 3040 // fold (aext (load x)) -> (aext (truncate (extload x))) 3041 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3042 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3043 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3044 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3045 LN0->getBasePtr(), LN0->getSrcValue(), 3046 LN0->getSrcValueOffset(), 3047 N0.getValueType(), 3048 LN0->isVolatile(), 3049 LN0->getAlignment()); 3050 CombineTo(N, ExtLoad); 3051 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3052 ExtLoad.getValue(1)); 3053 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3054 } 3055 3056 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3057 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3058 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3059 if (N0.getOpcode() == ISD::LOAD && 3060 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3061 N0.hasOneUse()) { 3062 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3063 MVT::ValueType EVT = LN0->getMemoryVT(); 3064 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3065 LN0->getChain(), LN0->getBasePtr(), 3066 LN0->getSrcValue(), 3067 LN0->getSrcValueOffset(), EVT, 3068 LN0->isVolatile(), 3069 LN0->getAlignment()); 3070 CombineTo(N, ExtLoad); 3071 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3072 ExtLoad.getValue(1)); 3073 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3074 } 3075 3076 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3077 if (N0.getOpcode() == ISD::SETCC) { 3078 SDOperand SCC = 3079 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3080 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3081 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3082 if (SCC.Val) 3083 return SCC; 3084 } 3085 3086 return SDOperand(); 3087} 3088 3089/// GetDemandedBits - See if the specified operand can be simplified with the 3090/// knowledge that only the bits specified by Mask are used. If so, return the 3091/// simpler operand, otherwise return a null SDOperand. 3092SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) { 3093 switch (V.getOpcode()) { 3094 default: break; 3095 case ISD::OR: 3096 case ISD::XOR: 3097 // If the LHS or RHS don't contribute bits to the or, drop them. 3098 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3099 return V.getOperand(1); 3100 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3101 return V.getOperand(0); 3102 break; 3103 case ISD::SRL: 3104 // Only look at single-use SRLs. 3105 if (!V.Val->hasOneUse()) 3106 break; 3107 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3108 // See if we can recursively simplify the LHS. 3109 unsigned Amt = RHSC->getValue(); 3110 APInt NewMask = Mask << Amt; 3111 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3112 if (SimplifyLHS.Val) { 3113 return DAG.getNode(ISD::SRL, V.getValueType(), 3114 SimplifyLHS, V.getOperand(1)); 3115 } 3116 } 3117 } 3118 return SDOperand(); 3119} 3120 3121/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3122/// bits and then truncated to a narrower type and where N is a multiple 3123/// of number of bits of the narrower type, transform it to a narrower load 3124/// from address + N / num of bits of new type. If the result is to be 3125/// extended, also fold the extension to form a extending load. 3126SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3127 unsigned Opc = N->getOpcode(); 3128 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3129 SDOperand N0 = N->getOperand(0); 3130 MVT::ValueType VT = N->getValueType(0); 3131 MVT::ValueType EVT = N->getValueType(0); 3132 3133 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3134 // extended to VT. 3135 if (Opc == ISD::SIGN_EXTEND_INREG) { 3136 ExtType = ISD::SEXTLOAD; 3137 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3138 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3139 return SDOperand(); 3140 } 3141 3142 unsigned EVTBits = MVT::getSizeInBits(EVT); 3143 unsigned ShAmt = 0; 3144 bool CombineSRL = false; 3145 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3146 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3147 ShAmt = N01->getValue(); 3148 // Is the shift amount a multiple of size of VT? 3149 if ((ShAmt & (EVTBits-1)) == 0) { 3150 N0 = N0.getOperand(0); 3151 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3152 return SDOperand(); 3153 CombineSRL = true; 3154 } 3155 } 3156 } 3157 3158 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3159 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3160 // zero extended form: by shrinking the load, we lose track of the fact 3161 // that it is already zero extended. 3162 // FIXME: This should be reevaluated. 3163 VT != MVT::i1) { 3164 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3165 "Cannot truncate to larger type!"); 3166 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3167 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3168 // For big endian targets, we need to adjust the offset to the pointer to 3169 // load the correct bytes. 3170 if (TLI.isBigEndian()) { 3171 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3172 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3173 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3174 } 3175 uint64_t PtrOff = ShAmt / 8; 3176 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3177 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3178 DAG.getConstant(PtrOff, PtrType)); 3179 AddToWorkList(NewPtr.Val); 3180 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3181 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3182 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3183 LN0->isVolatile(), NewAlign) 3184 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3185 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3186 LN0->isVolatile(), NewAlign); 3187 AddToWorkList(N); 3188 if (CombineSRL) { 3189 WorkListRemover DeadNodes(*this); 3190 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3191 &DeadNodes); 3192 CombineTo(N->getOperand(0).Val, Load); 3193 } else 3194 CombineTo(N0.Val, Load, Load.getValue(1)); 3195 if (ShAmt) { 3196 if (Opc == ISD::SIGN_EXTEND_INREG) 3197 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3198 else 3199 return DAG.getNode(Opc, VT, Load); 3200 } 3201 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3202 } 3203 3204 return SDOperand(); 3205} 3206 3207 3208SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3209 SDOperand N0 = N->getOperand(0); 3210 SDOperand N1 = N->getOperand(1); 3211 MVT::ValueType VT = N->getValueType(0); 3212 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3213 unsigned VTBits = MVT::getSizeInBits(VT); 3214 unsigned EVTBits = MVT::getSizeInBits(EVT); 3215 3216 // fold (sext_in_reg c1) -> c1 3217 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3218 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3219 3220 // If the input is already sign extended, just drop the extension. 3221 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3222 return N0; 3223 3224 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3225 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3226 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3227 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3228 } 3229 3230 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3231 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3232 return DAG.getZeroExtendInReg(N0, EVT); 3233 3234 // fold operands of sext_in_reg based on knowledge that the top bits are not 3235 // demanded. 3236 if (SimplifyDemandedBits(SDOperand(N, 0))) 3237 return SDOperand(N, 0); 3238 3239 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3240 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3241 SDOperand NarrowLoad = ReduceLoadWidth(N); 3242 if (NarrowLoad.Val) 3243 return NarrowLoad; 3244 3245 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3246 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3247 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3248 if (N0.getOpcode() == ISD::SRL) { 3249 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3250 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3251 // We can turn this into an SRA iff the input to the SRL is already sign 3252 // extended enough. 3253 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3254 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3255 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3256 } 3257 } 3258 3259 // fold (sext_inreg (extload x)) -> (sextload x) 3260 if (ISD::isEXTLoad(N0.Val) && 3261 ISD::isUNINDEXEDLoad(N0.Val) && 3262 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3263 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3264 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3265 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3266 LN0->getBasePtr(), LN0->getSrcValue(), 3267 LN0->getSrcValueOffset(), EVT, 3268 LN0->isVolatile(), 3269 LN0->getAlignment()); 3270 CombineTo(N, ExtLoad); 3271 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3272 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3273 } 3274 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3275 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3276 N0.hasOneUse() && 3277 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3278 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3279 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3280 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3281 LN0->getBasePtr(), LN0->getSrcValue(), 3282 LN0->getSrcValueOffset(), EVT, 3283 LN0->isVolatile(), 3284 LN0->getAlignment()); 3285 CombineTo(N, ExtLoad); 3286 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3287 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3288 } 3289 return SDOperand(); 3290} 3291 3292SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3293 SDOperand N0 = N->getOperand(0); 3294 MVT::ValueType VT = N->getValueType(0); 3295 3296 // noop truncate 3297 if (N0.getValueType() == N->getValueType(0)) 3298 return N0; 3299 // fold (truncate c1) -> c1 3300 if (isa<ConstantSDNode>(N0)) 3301 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3302 // fold (truncate (truncate x)) -> (truncate x) 3303 if (N0.getOpcode() == ISD::TRUNCATE) 3304 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3305 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3306 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3307 N0.getOpcode() == ISD::ANY_EXTEND) { 3308 if (N0.getOperand(0).getValueType() < VT) 3309 // if the source is smaller than the dest, we still need an extend 3310 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3311 else if (N0.getOperand(0).getValueType() > VT) 3312 // if the source is larger than the dest, than we just need the truncate 3313 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3314 else 3315 // if the source and dest are the same type, we can drop both the extend 3316 // and the truncate 3317 return N0.getOperand(0); 3318 } 3319 3320 // See if we can simplify the input to this truncate through knowledge that 3321 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3322 // -> trunc y 3323 SDOperand Shorter = 3324 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3325 MVT::getSizeInBits(VT))); 3326 if (Shorter.Val) 3327 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3328 3329 // fold (truncate (load x)) -> (smaller load x) 3330 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3331 return ReduceLoadWidth(N); 3332} 3333 3334SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3335 SDOperand N0 = N->getOperand(0); 3336 MVT::ValueType VT = N->getValueType(0); 3337 3338 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3339 // Only do this before legalize, since afterward the target may be depending 3340 // on the bitconvert. 3341 // First check to see if this is all constant. 3342 if (!AfterLegalize && 3343 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3344 MVT::isVector(VT)) { 3345 bool isSimple = true; 3346 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3347 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3348 N0.getOperand(i).getOpcode() != ISD::Constant && 3349 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3350 isSimple = false; 3351 break; 3352 } 3353 3354 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3355 assert(!MVT::isVector(DestEltVT) && 3356 "Element type of vector ValueType must not be vector!"); 3357 if (isSimple) { 3358 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3359 } 3360 } 3361 3362 // If the input is a constant, let getNode() fold it. 3363 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3364 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3365 if (Res.Val != N) return Res; 3366 } 3367 3368 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3369 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3370 3371 // fold (conv (load x)) -> (load (conv*)x) 3372 // If the resultant load doesn't need a higher alignment than the original! 3373 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3374 TLI.isOperationLegal(ISD::LOAD, VT)) { 3375 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3376 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3377 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3378 unsigned OrigAlign = LN0->getAlignment(); 3379 if (Align <= OrigAlign) { 3380 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3381 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3382 LN0->isVolatile(), Align); 3383 AddToWorkList(N); 3384 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3385 Load.getValue(1)); 3386 return Load; 3387 } 3388 } 3389 3390 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3391 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3392 // This often reduces constant pool loads. 3393 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3394 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) { 3395 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3396 AddToWorkList(NewConv.Val); 3397 3398 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); 3399 if (N0.getOpcode() == ISD::FNEG) 3400 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3401 assert(N0.getOpcode() == ISD::FABS); 3402 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3403 } 3404 3405 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3406 // Note that we don't handle copysign(x,cst) because this can always be folded 3407 // to an fneg or fabs. 3408 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3409 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3410 MVT::isInteger(VT) && !MVT::isVector(VT)) { 3411 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType()); 3412 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth), 3413 N0.getOperand(1)); 3414 AddToWorkList(X.Val); 3415 3416 // If X has a different width than the result/lhs, sext it or truncate it. 3417 unsigned VTWidth = MVT::getSizeInBits(VT); 3418 if (OrigXWidth < VTWidth) { 3419 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3420 AddToWorkList(X.Val); 3421 } else if (OrigXWidth > VTWidth) { 3422 // To get the sign bit in the right place, we have to shift it right 3423 // before truncating. 3424 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3425 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3426 AddToWorkList(X.Val); 3427 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3428 AddToWorkList(X.Val); 3429 } 3430 3431 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); 3432 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3433 AddToWorkList(X.Val); 3434 3435 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3436 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3437 AddToWorkList(Cst.Val); 3438 3439 return DAG.getNode(ISD::OR, VT, X, Cst); 3440 } 3441 3442 return SDOperand(); 3443} 3444 3445/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3446/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3447/// destination element value type. 3448SDOperand DAGCombiner:: 3449ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3450 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3451 3452 // If this is already the right type, we're done. 3453 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3454 3455 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3456 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3457 3458 // If this is a conversion of N elements of one type to N elements of another 3459 // type, convert each element. This handles FP<->INT cases. 3460 if (SrcBitSize == DstBitSize) { 3461 SmallVector<SDOperand, 8> Ops; 3462 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3463 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3464 AddToWorkList(Ops.back().Val); 3465 } 3466 MVT::ValueType VT = 3467 MVT::getVectorType(DstEltVT, 3468 MVT::getVectorNumElements(BV->getValueType(0))); 3469 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3470 } 3471 3472 // Otherwise, we're growing or shrinking the elements. To avoid having to 3473 // handle annoying details of growing/shrinking FP values, we convert them to 3474 // int first. 3475 if (MVT::isFloatingPoint(SrcEltVT)) { 3476 // Convert the input float vector to a int vector where the elements are the 3477 // same sizes. 3478 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3479 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3480 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3481 SrcEltVT = IntVT; 3482 } 3483 3484 // Now we know the input is an integer vector. If the output is a FP type, 3485 // convert to integer first, then to FP of the right size. 3486 if (MVT::isFloatingPoint(DstEltVT)) { 3487 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3488 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3489 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3490 3491 // Next, convert to FP elements of the same size. 3492 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3493 } 3494 3495 // Okay, we know the src/dst types are both integers of differing types. 3496 // Handling growing first. 3497 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3498 if (SrcBitSize < DstBitSize) { 3499 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3500 3501 SmallVector<SDOperand, 8> Ops; 3502 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3503 i += NumInputsPerOutput) { 3504 bool isLE = TLI.isLittleEndian(); 3505 APInt NewBits = APInt(DstBitSize, 0); 3506 bool EltIsUndef = true; 3507 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3508 // Shift the previously computed bits over. 3509 NewBits <<= SrcBitSize; 3510 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3511 if (Op.getOpcode() == ISD::UNDEF) continue; 3512 EltIsUndef = false; 3513 3514 NewBits |= 3515 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3516 } 3517 3518 if (EltIsUndef) 3519 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3520 else 3521 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3522 } 3523 3524 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3525 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3526 } 3527 3528 // Finally, this must be the case where we are shrinking elements: each input 3529 // turns into multiple outputs. 3530 bool isS2V = ISD::isScalarToVector(BV); 3531 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3532 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3533 NumOutputsPerInput * BV->getNumOperands()); 3534 SmallVector<SDOperand, 8> Ops; 3535 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3536 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3537 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3538 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3539 continue; 3540 } 3541 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3542 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3543 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3544 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3545 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3546 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3547 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3548 OpVal = OpVal.lshr(DstBitSize); 3549 } 3550 3551 // For big endian targets, swap the order of the pieces of each element. 3552 if (TLI.isBigEndian()) 3553 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3554 } 3555 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3556} 3557 3558 3559 3560SDOperand DAGCombiner::visitFADD(SDNode *N) { 3561 SDOperand N0 = N->getOperand(0); 3562 SDOperand N1 = N->getOperand(1); 3563 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3564 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3565 MVT::ValueType VT = N->getValueType(0); 3566 3567 // fold vector ops 3568 if (MVT::isVector(VT)) { 3569 SDOperand FoldedVOp = SimplifyVBinOp(N); 3570 if (FoldedVOp.Val) return FoldedVOp; 3571 } 3572 3573 // fold (fadd c1, c2) -> c1+c2 3574 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3575 return DAG.getNode(ISD::FADD, VT, N0, N1); 3576 // canonicalize constant to RHS 3577 if (N0CFP && !N1CFP) 3578 return DAG.getNode(ISD::FADD, VT, N1, N0); 3579 // fold (A + (-B)) -> A-B 3580 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3581 return DAG.getNode(ISD::FSUB, VT, N0, 3582 GetNegatedExpression(N1, DAG, AfterLegalize)); 3583 // fold ((-A) + B) -> B-A 3584 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3585 return DAG.getNode(ISD::FSUB, VT, N1, 3586 GetNegatedExpression(N0, DAG, AfterLegalize)); 3587 3588 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3589 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3590 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3591 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3592 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3593 3594 return SDOperand(); 3595} 3596 3597SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3598 SDOperand N0 = N->getOperand(0); 3599 SDOperand N1 = N->getOperand(1); 3600 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3601 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3602 MVT::ValueType VT = N->getValueType(0); 3603 3604 // fold vector ops 3605 if (MVT::isVector(VT)) { 3606 SDOperand FoldedVOp = SimplifyVBinOp(N); 3607 if (FoldedVOp.Val) return FoldedVOp; 3608 } 3609 3610 // fold (fsub c1, c2) -> c1-c2 3611 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3612 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3613 // fold (0-B) -> -B 3614 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3615 if (isNegatibleForFree(N1, AfterLegalize)) 3616 return GetNegatedExpression(N1, DAG, AfterLegalize); 3617 return DAG.getNode(ISD::FNEG, VT, N1); 3618 } 3619 // fold (A-(-B)) -> A+B 3620 if (isNegatibleForFree(N1, AfterLegalize)) 3621 return DAG.getNode(ISD::FADD, VT, N0, 3622 GetNegatedExpression(N1, DAG, AfterLegalize)); 3623 3624 return SDOperand(); 3625} 3626 3627SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3628 SDOperand N0 = N->getOperand(0); 3629 SDOperand N1 = N->getOperand(1); 3630 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3631 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3632 MVT::ValueType VT = N->getValueType(0); 3633 3634 // fold vector ops 3635 if (MVT::isVector(VT)) { 3636 SDOperand FoldedVOp = SimplifyVBinOp(N); 3637 if (FoldedVOp.Val) return FoldedVOp; 3638 } 3639 3640 // fold (fmul c1, c2) -> c1*c2 3641 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3642 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3643 // canonicalize constant to RHS 3644 if (N0CFP && !N1CFP) 3645 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3646 // fold (fmul X, 2.0) -> (fadd X, X) 3647 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3648 return DAG.getNode(ISD::FADD, VT, N0, N0); 3649 // fold (fmul X, -1.0) -> (fneg X) 3650 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3651 return DAG.getNode(ISD::FNEG, VT, N0); 3652 3653 // -X * -Y -> X*Y 3654 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3655 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3656 // Both can be negated for free, check to see if at least one is cheaper 3657 // negated. 3658 if (LHSNeg == 2 || RHSNeg == 2) 3659 return DAG.getNode(ISD::FMUL, VT, 3660 GetNegatedExpression(N0, DAG, AfterLegalize), 3661 GetNegatedExpression(N1, DAG, AfterLegalize)); 3662 } 3663 } 3664 3665 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3666 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3667 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3668 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3669 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3670 3671 return SDOperand(); 3672} 3673 3674SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3675 SDOperand N0 = N->getOperand(0); 3676 SDOperand N1 = N->getOperand(1); 3677 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3678 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3679 MVT::ValueType VT = N->getValueType(0); 3680 3681 // fold vector ops 3682 if (MVT::isVector(VT)) { 3683 SDOperand FoldedVOp = SimplifyVBinOp(N); 3684 if (FoldedVOp.Val) return FoldedVOp; 3685 } 3686 3687 // fold (fdiv c1, c2) -> c1/c2 3688 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3689 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3690 3691 3692 // -X / -Y -> X*Y 3693 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3694 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3695 // Both can be negated for free, check to see if at least one is cheaper 3696 // negated. 3697 if (LHSNeg == 2 || RHSNeg == 2) 3698 return DAG.getNode(ISD::FDIV, VT, 3699 GetNegatedExpression(N0, DAG, AfterLegalize), 3700 GetNegatedExpression(N1, DAG, AfterLegalize)); 3701 } 3702 } 3703 3704 return SDOperand(); 3705} 3706 3707SDOperand DAGCombiner::visitFREM(SDNode *N) { 3708 SDOperand N0 = N->getOperand(0); 3709 SDOperand N1 = N->getOperand(1); 3710 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3711 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3712 MVT::ValueType VT = N->getValueType(0); 3713 3714 // fold (frem c1, c2) -> fmod(c1,c2) 3715 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3716 return DAG.getNode(ISD::FREM, VT, N0, N1); 3717 3718 return SDOperand(); 3719} 3720 3721SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3722 SDOperand N0 = N->getOperand(0); 3723 SDOperand N1 = N->getOperand(1); 3724 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3725 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3726 MVT::ValueType VT = N->getValueType(0); 3727 3728 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3729 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3730 3731 if (N1CFP) { 3732 const APFloat& V = N1CFP->getValueAPF(); 3733 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3734 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3735 if (!V.isNegative()) 3736 return DAG.getNode(ISD::FABS, VT, N0); 3737 else 3738 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3739 } 3740 3741 // copysign(fabs(x), y) -> copysign(x, y) 3742 // copysign(fneg(x), y) -> copysign(x, y) 3743 // copysign(copysign(x,z), y) -> copysign(x, y) 3744 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3745 N0.getOpcode() == ISD::FCOPYSIGN) 3746 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3747 3748 // copysign(x, abs(y)) -> abs(x) 3749 if (N1.getOpcode() == ISD::FABS) 3750 return DAG.getNode(ISD::FABS, VT, N0); 3751 3752 // copysign(x, copysign(y,z)) -> copysign(x, z) 3753 if (N1.getOpcode() == ISD::FCOPYSIGN) 3754 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3755 3756 // copysign(x, fp_extend(y)) -> copysign(x, y) 3757 // copysign(x, fp_round(y)) -> copysign(x, y) 3758 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3759 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3760 3761 return SDOperand(); 3762} 3763 3764 3765 3766SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3767 SDOperand N0 = N->getOperand(0); 3768 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3769 MVT::ValueType VT = N->getValueType(0); 3770 3771 // fold (sint_to_fp c1) -> c1fp 3772 if (N0C && N0.getValueType() != MVT::ppcf128) 3773 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3774 return SDOperand(); 3775} 3776 3777SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3778 SDOperand N0 = N->getOperand(0); 3779 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3780 MVT::ValueType VT = N->getValueType(0); 3781 3782 // fold (uint_to_fp c1) -> c1fp 3783 if (N0C && N0.getValueType() != MVT::ppcf128) 3784 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3785 return SDOperand(); 3786} 3787 3788SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3789 SDOperand N0 = N->getOperand(0); 3790 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3791 MVT::ValueType VT = N->getValueType(0); 3792 3793 // fold (fp_to_sint c1fp) -> c1 3794 if (N0CFP) 3795 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3796 return SDOperand(); 3797} 3798 3799SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3800 SDOperand N0 = N->getOperand(0); 3801 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3802 MVT::ValueType VT = N->getValueType(0); 3803 3804 // fold (fp_to_uint c1fp) -> c1 3805 if (N0CFP && VT != MVT::ppcf128) 3806 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3807 return SDOperand(); 3808} 3809 3810SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3811 SDOperand N0 = N->getOperand(0); 3812 SDOperand N1 = N->getOperand(1); 3813 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3814 MVT::ValueType VT = N->getValueType(0); 3815 3816 // fold (fp_round c1fp) -> c1fp 3817 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3818 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3819 3820 // fold (fp_round (fp_extend x)) -> x 3821 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3822 return N0.getOperand(0); 3823 3824 // fold (fp_round (fp_round x)) -> (fp_round x) 3825 if (N0.getOpcode() == ISD::FP_ROUND) { 3826 // This is a value preserving truncation if both round's are. 3827 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3828 N0.Val->getConstantOperandVal(1) == 1; 3829 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3830 DAG.getIntPtrConstant(IsTrunc)); 3831 } 3832 3833 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3834 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3835 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3836 AddToWorkList(Tmp.Val); 3837 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3838 } 3839 3840 return SDOperand(); 3841} 3842 3843SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3844 SDOperand N0 = N->getOperand(0); 3845 MVT::ValueType VT = N->getValueType(0); 3846 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3847 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3848 3849 // fold (fp_round_inreg c1fp) -> c1fp 3850 if (N0CFP) { 3851 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3852 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3853 } 3854 return SDOperand(); 3855} 3856 3857SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3858 SDOperand N0 = N->getOperand(0); 3859 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3860 MVT::ValueType VT = N->getValueType(0); 3861 3862 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3863 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND) 3864 return SDOperand(); 3865 3866 // fold (fp_extend c1fp) -> c1fp 3867 if (N0CFP && VT != MVT::ppcf128) 3868 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3869 3870 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3871 // value of X. 3872 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3873 SDOperand In = N0.getOperand(0); 3874 if (In.getValueType() == VT) return In; 3875 if (VT < In.getValueType()) 3876 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3877 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3878 } 3879 3880 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3881 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3882 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3883 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3884 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3885 LN0->getBasePtr(), LN0->getSrcValue(), 3886 LN0->getSrcValueOffset(), 3887 N0.getValueType(), 3888 LN0->isVolatile(), 3889 LN0->getAlignment()); 3890 CombineTo(N, ExtLoad); 3891 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3892 DAG.getIntPtrConstant(1)), 3893 ExtLoad.getValue(1)); 3894 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3895 } 3896 3897 3898 return SDOperand(); 3899} 3900 3901SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3902 SDOperand N0 = N->getOperand(0); 3903 3904 if (isNegatibleForFree(N0, AfterLegalize)) 3905 return GetNegatedExpression(N0, DAG, AfterLegalize); 3906 3907 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 3908 // constant pool values. 3909 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3910 MVT::isInteger(N0.getOperand(0).getValueType()) && 3911 !MVT::isVector(N0.getOperand(0).getValueType())) { 3912 SDOperand Int = N0.getOperand(0); 3913 MVT::ValueType IntVT = Int.getValueType(); 3914 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3915 Int = DAG.getNode(ISD::XOR, IntVT, Int, 3916 DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT)); 3917 AddToWorkList(Int.Val); 3918 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3919 } 3920 } 3921 3922 return SDOperand(); 3923} 3924 3925SDOperand DAGCombiner::visitFABS(SDNode *N) { 3926 SDOperand N0 = N->getOperand(0); 3927 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3928 MVT::ValueType VT = N->getValueType(0); 3929 3930 // fold (fabs c1) -> fabs(c1) 3931 if (N0CFP && VT != MVT::ppcf128) 3932 return DAG.getNode(ISD::FABS, VT, N0); 3933 // fold (fabs (fabs x)) -> (fabs x) 3934 if (N0.getOpcode() == ISD::FABS) 3935 return N->getOperand(0); 3936 // fold (fabs (fneg x)) -> (fabs x) 3937 // fold (fabs (fcopysign x, y)) -> (fabs x) 3938 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3939 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3940 3941 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 3942 // constant pool values. 3943 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3944 MVT::isInteger(N0.getOperand(0).getValueType()) && 3945 !MVT::isVector(N0.getOperand(0).getValueType())) { 3946 SDOperand Int = N0.getOperand(0); 3947 MVT::ValueType IntVT = Int.getValueType(); 3948 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3949 Int = DAG.getNode(ISD::AND, IntVT, Int, 3950 DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT)); 3951 AddToWorkList(Int.Val); 3952 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3953 } 3954 } 3955 3956 return SDOperand(); 3957} 3958 3959SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3960 SDOperand Chain = N->getOperand(0); 3961 SDOperand N1 = N->getOperand(1); 3962 SDOperand N2 = N->getOperand(2); 3963 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3964 3965 // never taken branch, fold to chain 3966 if (N1C && N1C->isNullValue()) 3967 return Chain; 3968 // unconditional branch 3969 if (N1C && N1C->getAPIntValue() == 1) 3970 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3971 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3972 // on the target. 3973 if (N1.getOpcode() == ISD::SETCC && 3974 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3975 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3976 N1.getOperand(0), N1.getOperand(1), N2); 3977 } 3978 return SDOperand(); 3979} 3980 3981// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3982// 3983SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3984 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3985 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3986 3987 // Use SimplifySetCC to simplify SETCC's. 3988 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3989 if (Simp.Val) AddToWorkList(Simp.Val); 3990 3991 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3992 3993 // fold br_cc true, dest -> br dest (unconditional branch) 3994 if (SCCC && !SCCC->isNullValue()) 3995 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3996 N->getOperand(4)); 3997 // fold br_cc false, dest -> unconditional fall through 3998 if (SCCC && SCCC->isNullValue()) 3999 return N->getOperand(0); 4000 4001 // fold to a simpler setcc 4002 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 4003 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4004 Simp.getOperand(2), Simp.getOperand(0), 4005 Simp.getOperand(1), N->getOperand(4)); 4006 return SDOperand(); 4007} 4008 4009 4010/// CombineToPreIndexedLoadStore - Try turning a load / store and a 4011/// pre-indexed load / store when the base pointer is a add or subtract 4012/// and it has other uses besides the load / store. After the 4013/// transformation, the new indexed load / store has effectively folded 4014/// the add / subtract in and all of its other uses are redirected to the 4015/// new load / store. 4016bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4017 if (!AfterLegalize) 4018 return false; 4019 4020 bool isLoad = true; 4021 SDOperand Ptr; 4022 MVT::ValueType VT; 4023 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4024 if (LD->isIndexed()) 4025 return false; 4026 VT = LD->getMemoryVT(); 4027 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4028 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4029 return false; 4030 Ptr = LD->getBasePtr(); 4031 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4032 if (ST->isIndexed()) 4033 return false; 4034 VT = ST->getMemoryVT(); 4035 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4036 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4037 return false; 4038 Ptr = ST->getBasePtr(); 4039 isLoad = false; 4040 } else 4041 return false; 4042 4043 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4044 // out. There is no reason to make this a preinc/predec. 4045 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4046 Ptr.Val->hasOneUse()) 4047 return false; 4048 4049 // Ask the target to do addressing mode selection. 4050 SDOperand BasePtr; 4051 SDOperand Offset; 4052 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4053 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4054 return false; 4055 // Don't create a indexed load / store with zero offset. 4056 if (isa<ConstantSDNode>(Offset) && 4057 cast<ConstantSDNode>(Offset)->isNullValue()) 4058 return false; 4059 4060 // Try turning it into a pre-indexed load / store except when: 4061 // 1) The new base ptr is a frame index. 4062 // 2) If N is a store and the new base ptr is either the same as or is a 4063 // predecessor of the value being stored. 4064 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4065 // that would create a cycle. 4066 // 4) All uses are load / store ops that use it as old base ptr. 4067 4068 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4069 // (plus the implicit offset) to a register to preinc anyway. 4070 if (isa<FrameIndexSDNode>(BasePtr)) 4071 return false; 4072 4073 // Check #2. 4074 if (!isLoad) { 4075 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 4076 if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val)) 4077 return false; 4078 } 4079 4080 // Now check for #3 and #4. 4081 bool RealUse = false; 4082 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4083 E = Ptr.Val->use_end(); I != E; ++I) { 4084 SDNode *Use = *I; 4085 if (Use == N) 4086 continue; 4087 if (Use->isPredecessorOf(N)) 4088 return false; 4089 4090 if (!((Use->getOpcode() == ISD::LOAD && 4091 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4092 (Use->getOpcode() == ISD::STORE && 4093 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4094 RealUse = true; 4095 } 4096 if (!RealUse) 4097 return false; 4098 4099 SDOperand Result; 4100 if (isLoad) 4101 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 4102 else 4103 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4104 ++PreIndexedNodes; 4105 ++NodesCombined; 4106 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4107 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4108 DOUT << '\n'; 4109 WorkListRemover DeadNodes(*this); 4110 if (isLoad) { 4111 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4112 &DeadNodes); 4113 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4114 &DeadNodes); 4115 } else { 4116 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4117 &DeadNodes); 4118 } 4119 4120 // Finally, since the node is now dead, remove it from the graph. 4121 DAG.DeleteNode(N); 4122 4123 // Replace the uses of Ptr with uses of the updated base value. 4124 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4125 &DeadNodes); 4126 removeFromWorkList(Ptr.Val); 4127 DAG.DeleteNode(Ptr.Val); 4128 4129 return true; 4130} 4131 4132/// CombineToPostIndexedLoadStore - Try combine a load / store with a 4133/// add / sub of the base pointer node into a post-indexed load / store. 4134/// The transformation folded the add / subtract into the new indexed 4135/// load / store effectively and all of its uses are redirected to the 4136/// new load / store. 4137bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4138 if (!AfterLegalize) 4139 return false; 4140 4141 bool isLoad = true; 4142 SDOperand Ptr; 4143 MVT::ValueType VT; 4144 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4145 if (LD->isIndexed()) 4146 return false; 4147 VT = LD->getMemoryVT(); 4148 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4149 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4150 return false; 4151 Ptr = LD->getBasePtr(); 4152 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4153 if (ST->isIndexed()) 4154 return false; 4155 VT = ST->getMemoryVT(); 4156 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4157 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4158 return false; 4159 Ptr = ST->getBasePtr(); 4160 isLoad = false; 4161 } else 4162 return false; 4163 4164 if (Ptr.Val->hasOneUse()) 4165 return false; 4166 4167 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4168 E = Ptr.Val->use_end(); I != E; ++I) { 4169 SDNode *Op = *I; 4170 if (Op == N || 4171 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4172 continue; 4173 4174 SDOperand BasePtr; 4175 SDOperand Offset; 4176 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4177 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4178 if (Ptr == Offset) 4179 std::swap(BasePtr, Offset); 4180 if (Ptr != BasePtr) 4181 continue; 4182 // Don't create a indexed load / store with zero offset. 4183 if (isa<ConstantSDNode>(Offset) && 4184 cast<ConstantSDNode>(Offset)->isNullValue()) 4185 continue; 4186 4187 // Try turning it into a post-indexed load / store except when 4188 // 1) All uses are load / store ops that use it as base ptr. 4189 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4190 // nor a successor of N. Otherwise, if Op is folded that would 4191 // create a cycle. 4192 4193 // Check for #1. 4194 bool TryNext = false; 4195 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4196 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4197 SDNode *Use = *II; 4198 if (Use == Ptr.Val) 4199 continue; 4200 4201 // If all the uses are load / store addresses, then don't do the 4202 // transformation. 4203 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4204 bool RealUse = false; 4205 for (SDNode::use_iterator III = Use->use_begin(), 4206 EEE = Use->use_end(); III != EEE; ++III) { 4207 SDNode *UseUse = *III; 4208 if (!((UseUse->getOpcode() == ISD::LOAD && 4209 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4210 (UseUse->getOpcode() == ISD::STORE && 4211 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))) 4212 RealUse = true; 4213 } 4214 4215 if (!RealUse) { 4216 TryNext = true; 4217 break; 4218 } 4219 } 4220 } 4221 if (TryNext) 4222 continue; 4223 4224 // Check for #2 4225 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4226 SDOperand Result = isLoad 4227 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4228 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4229 ++PostIndexedNodes; 4230 ++NodesCombined; 4231 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4232 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4233 DOUT << '\n'; 4234 WorkListRemover DeadNodes(*this); 4235 if (isLoad) { 4236 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4237 &DeadNodes); 4238 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4239 &DeadNodes); 4240 } else { 4241 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4242 &DeadNodes); 4243 } 4244 4245 // Finally, since the node is now dead, remove it from the graph. 4246 DAG.DeleteNode(N); 4247 4248 // Replace the uses of Use with uses of the updated base value. 4249 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4250 Result.getValue(isLoad ? 1 : 0), 4251 &DeadNodes); 4252 removeFromWorkList(Op); 4253 DAG.DeleteNode(Op); 4254 return true; 4255 } 4256 } 4257 } 4258 return false; 4259} 4260 4261/// InferAlignment - If we can infer some alignment information from this 4262/// pointer, return it. 4263static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4264 // If this is a direct reference to a stack slot, use information about the 4265 // stack slot's alignment. 4266 int FrameIdx = 1 << 31; 4267 int64_t FrameOffset = 0; 4268 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4269 FrameIdx = FI->getIndex(); 4270 } else if (Ptr.getOpcode() == ISD::ADD && 4271 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4272 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4273 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4274 FrameOffset = Ptr.getConstantOperandVal(1); 4275 } 4276 4277 if (FrameIdx != (1 << 31)) { 4278 // FIXME: Handle FI+CST. 4279 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4280 if (MFI.isFixedObjectIndex(FrameIdx)) { 4281 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4282 4283 // The alignment of the frame index can be determined from its offset from 4284 // the incoming frame position. If the frame object is at offset 32 and 4285 // the stack is guaranteed to be 16-byte aligned, then we know that the 4286 // object is 16-byte aligned. 4287 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4288 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4289 4290 // Finally, the frame object itself may have a known alignment. Factor 4291 // the alignment + offset into a new alignment. For example, if we know 4292 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4293 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4294 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4295 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4296 FrameOffset); 4297 return std::max(Align, FIInfoAlign); 4298 } 4299 } 4300 4301 return 0; 4302} 4303 4304SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4305 LoadSDNode *LD = cast<LoadSDNode>(N); 4306 SDOperand Chain = LD->getChain(); 4307 SDOperand Ptr = LD->getBasePtr(); 4308 4309 // Try to infer better alignment information than the load already has. 4310 if (LD->isUnindexed()) { 4311 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4312 if (Align > LD->getAlignment()) 4313 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4314 Chain, Ptr, LD->getSrcValue(), 4315 LD->getSrcValueOffset(), LD->getMemoryVT(), 4316 LD->isVolatile(), Align); 4317 } 4318 } 4319 4320 4321 // If load is not volatile and there are no uses of the loaded value (and 4322 // the updated indexed value in case of indexed loads), change uses of the 4323 // chain value into uses of the chain input (i.e. delete the dead load). 4324 if (!LD->isVolatile()) { 4325 if (N->getValueType(1) == MVT::Other) { 4326 // Unindexed loads. 4327 if (N->hasNUsesOfValue(0, 0)) { 4328 // It's not safe to use the two value CombineTo variant here. e.g. 4329 // v1, chain2 = load chain1, loc 4330 // v2, chain3 = load chain2, loc 4331 // v3 = add v2, c 4332 // Now we replace use of chain2 with chain1. This makes the second load 4333 // isomorphic to the one we are deleting, and thus makes this load live. 4334 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4335 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4336 DOUT << "\n"; 4337 WorkListRemover DeadNodes(*this); 4338 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes); 4339 if (N->use_empty()) { 4340 removeFromWorkList(N); 4341 DAG.DeleteNode(N); 4342 } 4343 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4344 } 4345 } else { 4346 // Indexed loads. 4347 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4348 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4349 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4350 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4351 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4352 DOUT << " and 2 other values\n"; 4353 WorkListRemover DeadNodes(*this); 4354 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes); 4355 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4356 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4357 &DeadNodes); 4358 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes); 4359 removeFromWorkList(N); 4360 DAG.DeleteNode(N); 4361 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4362 } 4363 } 4364 } 4365 4366 // If this load is directly stored, replace the load value with the stored 4367 // value. 4368 // TODO: Handle store large -> read small portion. 4369 // TODO: Handle TRUNCSTORE/LOADEXT 4370 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4371 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4372 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4373 if (PrevST->getBasePtr() == Ptr && 4374 PrevST->getValue().getValueType() == N->getValueType(0)) 4375 return CombineTo(N, Chain.getOperand(1), Chain); 4376 } 4377 } 4378 4379 if (CombinerAA) { 4380 // Walk up chain skipping non-aliasing memory nodes. 4381 SDOperand BetterChain = FindBetterChain(N, Chain); 4382 4383 // If there is a better chain. 4384 if (Chain != BetterChain) { 4385 SDOperand ReplLoad; 4386 4387 // Replace the chain to void dependency. 4388 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4389 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4390 LD->getSrcValue(), LD->getSrcValueOffset(), 4391 LD->isVolatile(), LD->getAlignment()); 4392 } else { 4393 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4394 LD->getValueType(0), 4395 BetterChain, Ptr, LD->getSrcValue(), 4396 LD->getSrcValueOffset(), 4397 LD->getMemoryVT(), 4398 LD->isVolatile(), 4399 LD->getAlignment()); 4400 } 4401 4402 // Create token factor to keep old chain connected. 4403 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4404 Chain, ReplLoad.getValue(1)); 4405 4406 // Replace uses with load result and token factor. Don't add users 4407 // to work list. 4408 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4409 } 4410 } 4411 4412 // Try transforming N to an indexed load. 4413 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4414 return SDOperand(N, 0); 4415 4416 return SDOperand(); 4417} 4418 4419 4420SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4421 StoreSDNode *ST = cast<StoreSDNode>(N); 4422 SDOperand Chain = ST->getChain(); 4423 SDOperand Value = ST->getValue(); 4424 SDOperand Ptr = ST->getBasePtr(); 4425 4426 // Try to infer better alignment information than the store already has. 4427 if (ST->isUnindexed()) { 4428 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4429 if (Align > ST->getAlignment()) 4430 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4431 ST->getSrcValueOffset(), ST->getMemoryVT(), 4432 ST->isVolatile(), Align); 4433 } 4434 } 4435 4436 // If this is a store of a bit convert, store the input value if the 4437 // resultant store does not need a higher alignment than the original. 4438 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4439 ST->isUnindexed()) { 4440 unsigned Align = ST->getAlignment(); 4441 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4442 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4443 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4444 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4445 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4446 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4447 } 4448 4449 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4450 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4451 if (Value.getOpcode() != ISD::TargetConstantFP) { 4452 SDOperand Tmp; 4453 switch (CFP->getValueType(0)) { 4454 default: assert(0 && "Unknown FP type"); 4455 case MVT::f80: // We don't do this for these yet. 4456 case MVT::f128: 4457 case MVT::ppcf128: 4458 break; 4459 case MVT::f32: 4460 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4461 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4462 convertToAPInt().getZExtValue(), MVT::i32); 4463 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4464 ST->getSrcValueOffset(), ST->isVolatile(), 4465 ST->getAlignment()); 4466 } 4467 break; 4468 case MVT::f64: 4469 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4470 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4471 getZExtValue(), MVT::i64); 4472 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4473 ST->getSrcValueOffset(), ST->isVolatile(), 4474 ST->getAlignment()); 4475 } else if (TLI.isTypeLegal(MVT::i32)) { 4476 // Many FP stores are not made apparent until after legalize, e.g. for 4477 // argument passing. Since this is so common, custom legalize the 4478 // 64-bit integer store into two 32-bit stores. 4479 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4480 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4481 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4482 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4483 4484 int SVOffset = ST->getSrcValueOffset(); 4485 unsigned Alignment = ST->getAlignment(); 4486 bool isVolatile = ST->isVolatile(); 4487 4488 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4489 ST->getSrcValueOffset(), 4490 isVolatile, ST->getAlignment()); 4491 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4492 DAG.getConstant(4, Ptr.getValueType())); 4493 SVOffset += 4; 4494 Alignment = MinAlign(Alignment, 4U); 4495 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4496 SVOffset, isVolatile, Alignment); 4497 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4498 } 4499 break; 4500 } 4501 } 4502 } 4503 4504 if (CombinerAA) { 4505 // Walk up chain skipping non-aliasing memory nodes. 4506 SDOperand BetterChain = FindBetterChain(N, Chain); 4507 4508 // If there is a better chain. 4509 if (Chain != BetterChain) { 4510 // Replace the chain to avoid dependency. 4511 SDOperand ReplStore; 4512 if (ST->isTruncatingStore()) { 4513 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4514 ST->getSrcValue(),ST->getSrcValueOffset(), 4515 ST->getMemoryVT(), 4516 ST->isVolatile(), ST->getAlignment()); 4517 } else { 4518 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4519 ST->getSrcValue(), ST->getSrcValueOffset(), 4520 ST->isVolatile(), ST->getAlignment()); 4521 } 4522 4523 // Create token to keep both nodes around. 4524 SDOperand Token = 4525 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4526 4527 // Don't add users to work list. 4528 return CombineTo(N, Token, false); 4529 } 4530 } 4531 4532 // Try transforming N to an indexed store. 4533 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4534 return SDOperand(N, 0); 4535 4536 // FIXME: is there such a thing as a truncating indexed store? 4537 if (ST->isTruncatingStore() && ST->isUnindexed() && 4538 MVT::isInteger(Value.getValueType())) { 4539 // See if we can simplify the input to this truncstore with knowledge that 4540 // only the low bits are being used. For example: 4541 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4542 SDOperand Shorter = 4543 GetDemandedBits(Value, 4544 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4545 MVT::getSizeInBits(ST->getMemoryVT()))); 4546 AddToWorkList(Value.Val); 4547 if (Shorter.Val) 4548 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4549 ST->getSrcValueOffset(), ST->getMemoryVT(), 4550 ST->isVolatile(), ST->getAlignment()); 4551 4552 // Otherwise, see if we can simplify the operation with 4553 // SimplifyDemandedBits, which only works if the value has a single use. 4554 if (SimplifyDemandedBits(Value, 4555 APInt::getLowBitsSet( 4556 Value.getValueSizeInBits(), 4557 MVT::getSizeInBits(ST->getMemoryVT())))) 4558 return SDOperand(N, 0); 4559 } 4560 4561 // If this is a load followed by a store to the same location, then the store 4562 // is dead/noop. 4563 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4564 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4565 ST->isUnindexed() && !ST->isVolatile() && 4566 // There can't be any side effects between the load and store, such as 4567 // a call or store. 4568 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4569 // The store is dead, remove it. 4570 return Chain; 4571 } 4572 } 4573 4574 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4575 // truncating store. We can do this even if this is already a truncstore. 4576 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4577 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) && 4578 Value.Val->hasOneUse() && ST->isUnindexed() && 4579 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4580 ST->getMemoryVT())) { 4581 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4582 ST->getSrcValueOffset(), ST->getMemoryVT(), 4583 ST->isVolatile(), ST->getAlignment()); 4584 } 4585 4586 return SDOperand(); 4587} 4588 4589SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4590 SDOperand InVec = N->getOperand(0); 4591 SDOperand InVal = N->getOperand(1); 4592 SDOperand EltNo = N->getOperand(2); 4593 4594 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4595 // vector with the inserted element. 4596 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4597 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4598 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4599 if (Elt < Ops.size()) 4600 Ops[Elt] = InVal; 4601 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4602 &Ops[0], Ops.size()); 4603 } 4604 4605 return SDOperand(); 4606} 4607 4608SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4609 SDOperand InVec = N->getOperand(0); 4610 SDOperand EltNo = N->getOperand(1); 4611 4612 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4613 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4614 if (isa<ConstantSDNode>(EltNo)) { 4615 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4616 bool NewLoad = false; 4617 if (Elt == 0) { 4618 MVT::ValueType VT = InVec.getValueType(); 4619 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4620 MVT::ValueType LVT = EVT; 4621 unsigned NumElts = MVT::getVectorNumElements(VT); 4622 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4623 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4624 if (!MVT::isVector(BCVT) || 4625 NumElts != MVT::getVectorNumElements(BCVT)) 4626 return SDOperand(); 4627 InVec = InVec.getOperand(0); 4628 EVT = MVT::getVectorElementType(BCVT); 4629 NewLoad = true; 4630 } 4631 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4632 InVec.getOperand(0).getValueType() == EVT && 4633 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4634 InVec.getOperand(0).hasOneUse()) { 4635 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4636 unsigned Align = LN0->getAlignment(); 4637 if (NewLoad) { 4638 // Check the resultant load doesn't need a higher alignment than the 4639 // original load. 4640 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4641 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4642 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4643 return SDOperand(); 4644 Align = NewAlign; 4645 } 4646 4647 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4648 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4649 LN0->isVolatile(), Align); 4650 } 4651 } 4652 } 4653 return SDOperand(); 4654} 4655 4656 4657SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4658 unsigned NumInScalars = N->getNumOperands(); 4659 MVT::ValueType VT = N->getValueType(0); 4660 unsigned NumElts = MVT::getVectorNumElements(VT); 4661 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4662 4663 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4664 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4665 // at most two distinct vectors, turn this into a shuffle node. 4666 SDOperand VecIn1, VecIn2; 4667 for (unsigned i = 0; i != NumInScalars; ++i) { 4668 // Ignore undef inputs. 4669 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4670 4671 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4672 // constant index, bail out. 4673 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4674 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4675 VecIn1 = VecIn2 = SDOperand(0, 0); 4676 break; 4677 } 4678 4679 // If the input vector type disagrees with the result of the build_vector, 4680 // we can't make a shuffle. 4681 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4682 if (ExtractedFromVec.getValueType() != VT) { 4683 VecIn1 = VecIn2 = SDOperand(0, 0); 4684 break; 4685 } 4686 4687 // Otherwise, remember this. We allow up to two distinct input vectors. 4688 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4689 continue; 4690 4691 if (VecIn1.Val == 0) { 4692 VecIn1 = ExtractedFromVec; 4693 } else if (VecIn2.Val == 0) { 4694 VecIn2 = ExtractedFromVec; 4695 } else { 4696 // Too many inputs. 4697 VecIn1 = VecIn2 = SDOperand(0, 0); 4698 break; 4699 } 4700 } 4701 4702 // If everything is good, we can make a shuffle operation. 4703 if (VecIn1.Val) { 4704 SmallVector<SDOperand, 8> BuildVecIndices; 4705 for (unsigned i = 0; i != NumInScalars; ++i) { 4706 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4707 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4708 continue; 4709 } 4710 4711 SDOperand Extract = N->getOperand(i); 4712 4713 // If extracting from the first vector, just use the index directly. 4714 if (Extract.getOperand(0) == VecIn1) { 4715 BuildVecIndices.push_back(Extract.getOperand(1)); 4716 continue; 4717 } 4718 4719 // Otherwise, use InIdx + VecSize 4720 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4721 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4722 } 4723 4724 // Add count and size info. 4725 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); 4726 4727 // Return the new VECTOR_SHUFFLE node. 4728 SDOperand Ops[5]; 4729 Ops[0] = VecIn1; 4730 if (VecIn2.Val) { 4731 Ops[1] = VecIn2; 4732 } else { 4733 // Use an undef build_vector as input for the second operand. 4734 std::vector<SDOperand> UnOps(NumInScalars, 4735 DAG.getNode(ISD::UNDEF, 4736 EltType)); 4737 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4738 &UnOps[0], UnOps.size()); 4739 AddToWorkList(Ops[1].Val); 4740 } 4741 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4742 &BuildVecIndices[0], BuildVecIndices.size()); 4743 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4744 } 4745 4746 return SDOperand(); 4747} 4748 4749SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4750 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4751 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4752 // inputs come from at most two distinct vectors, turn this into a shuffle 4753 // node. 4754 4755 // If we only have one input vector, we don't need to do any concatenation. 4756 if (N->getNumOperands() == 1) { 4757 return N->getOperand(0); 4758 } 4759 4760 return SDOperand(); 4761} 4762 4763SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4764 SDOperand ShufMask = N->getOperand(2); 4765 unsigned NumElts = ShufMask.getNumOperands(); 4766 4767 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4768 bool isIdentity = true; 4769 for (unsigned i = 0; i != NumElts; ++i) { 4770 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4771 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4772 isIdentity = false; 4773 break; 4774 } 4775 } 4776 if (isIdentity) return N->getOperand(0); 4777 4778 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4779 isIdentity = true; 4780 for (unsigned i = 0; i != NumElts; ++i) { 4781 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4782 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4783 isIdentity = false; 4784 break; 4785 } 4786 } 4787 if (isIdentity) return N->getOperand(1); 4788 4789 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4790 // needed at all. 4791 bool isUnary = true; 4792 bool isSplat = true; 4793 int VecNum = -1; 4794 unsigned BaseIdx = 0; 4795 for (unsigned i = 0; i != NumElts; ++i) 4796 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4797 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4798 int V = (Idx < NumElts) ? 0 : 1; 4799 if (VecNum == -1) { 4800 VecNum = V; 4801 BaseIdx = Idx; 4802 } else { 4803 if (BaseIdx != Idx) 4804 isSplat = false; 4805 if (VecNum != V) { 4806 isUnary = false; 4807 break; 4808 } 4809 } 4810 } 4811 4812 SDOperand N0 = N->getOperand(0); 4813 SDOperand N1 = N->getOperand(1); 4814 // Normalize unary shuffle so the RHS is undef. 4815 if (isUnary && VecNum == 1) 4816 std::swap(N0, N1); 4817 4818 // If it is a splat, check if the argument vector is a build_vector with 4819 // all scalar elements the same. 4820 if (isSplat) { 4821 SDNode *V = N0.Val; 4822 4823 // If this is a bit convert that changes the element type of the vector but 4824 // not the number of vector elements, look through it. Be careful not to 4825 // look though conversions that change things like v4f32 to v2f64. 4826 if (V->getOpcode() == ISD::BIT_CONVERT) { 4827 SDOperand ConvInput = V->getOperand(0); 4828 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4829 V = ConvInput.Val; 4830 } 4831 4832 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4833 unsigned NumElems = V->getNumOperands(); 4834 if (NumElems > BaseIdx) { 4835 SDOperand Base; 4836 bool AllSame = true; 4837 for (unsigned i = 0; i != NumElems; ++i) { 4838 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4839 Base = V->getOperand(i); 4840 break; 4841 } 4842 } 4843 // Splat of <u, u, u, u>, return <u, u, u, u> 4844 if (!Base.Val) 4845 return N0; 4846 for (unsigned i = 0; i != NumElems; ++i) { 4847 if (V->getOperand(i) != Base) { 4848 AllSame = false; 4849 break; 4850 } 4851 } 4852 // Splat of <x, x, x, x>, return <x, x, x, x> 4853 if (AllSame) 4854 return N0; 4855 } 4856 } 4857 } 4858 4859 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4860 // into an undef. 4861 if (isUnary || N0 == N1) { 4862 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4863 // first operand. 4864 SmallVector<SDOperand, 8> MappedOps; 4865 for (unsigned i = 0; i != NumElts; ++i) { 4866 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4867 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4868 MappedOps.push_back(ShufMask.getOperand(i)); 4869 } else { 4870 unsigned NewIdx = 4871 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4872 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4873 } 4874 } 4875 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4876 &MappedOps[0], MappedOps.size()); 4877 AddToWorkList(ShufMask.Val); 4878 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4879 N0, 4880 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4881 ShufMask); 4882 } 4883 4884 return SDOperand(); 4885} 4886 4887/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4888/// an AND to a vector_shuffle with the destination vector and a zero vector. 4889/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4890/// vector_shuffle V, Zero, <0, 4, 2, 4> 4891SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4892 SDOperand LHS = N->getOperand(0); 4893 SDOperand RHS = N->getOperand(1); 4894 if (N->getOpcode() == ISD::AND) { 4895 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4896 RHS = RHS.getOperand(0); 4897 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4898 std::vector<SDOperand> IdxOps; 4899 unsigned NumOps = RHS.getNumOperands(); 4900 unsigned NumElts = NumOps; 4901 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4902 for (unsigned i = 0; i != NumElts; ++i) { 4903 SDOperand Elt = RHS.getOperand(i); 4904 if (!isa<ConstantSDNode>(Elt)) 4905 return SDOperand(); 4906 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4907 IdxOps.push_back(DAG.getConstant(i, EVT)); 4908 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4909 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4910 else 4911 return SDOperand(); 4912 } 4913 4914 // Let's see if the target supports this vector_shuffle. 4915 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4916 return SDOperand(); 4917 4918 // Return the new VECTOR_SHUFFLE node. 4919 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4920 std::vector<SDOperand> Ops; 4921 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4922 Ops.push_back(LHS); 4923 AddToWorkList(LHS.Val); 4924 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4925 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4926 &ZeroOps[0], ZeroOps.size())); 4927 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4928 &IdxOps[0], IdxOps.size())); 4929 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4930 &Ops[0], Ops.size()); 4931 if (VT != LHS.getValueType()) { 4932 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4933 } 4934 return Result; 4935 } 4936 } 4937 return SDOperand(); 4938} 4939 4940/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4941SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4942 // After legalize, the target may be depending on adds and other 4943 // binary ops to provide legal ways to construct constants or other 4944 // things. Simplifying them may result in a loss of legality. 4945 if (AfterLegalize) return SDOperand(); 4946 4947 MVT::ValueType VT = N->getValueType(0); 4948 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4949 4950 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4951 SDOperand LHS = N->getOperand(0); 4952 SDOperand RHS = N->getOperand(1); 4953 SDOperand Shuffle = XformToShuffleWithZero(N); 4954 if (Shuffle.Val) return Shuffle; 4955 4956 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4957 // this operation. 4958 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4959 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4960 SmallVector<SDOperand, 8> Ops; 4961 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4962 SDOperand LHSOp = LHS.getOperand(i); 4963 SDOperand RHSOp = RHS.getOperand(i); 4964 // If these two elements can't be folded, bail out. 4965 if ((LHSOp.getOpcode() != ISD::UNDEF && 4966 LHSOp.getOpcode() != ISD::Constant && 4967 LHSOp.getOpcode() != ISD::ConstantFP) || 4968 (RHSOp.getOpcode() != ISD::UNDEF && 4969 RHSOp.getOpcode() != ISD::Constant && 4970 RHSOp.getOpcode() != ISD::ConstantFP)) 4971 break; 4972 // Can't fold divide by zero. 4973 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4974 N->getOpcode() == ISD::FDIV) { 4975 if ((RHSOp.getOpcode() == ISD::Constant && 4976 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4977 (RHSOp.getOpcode() == ISD::ConstantFP && 4978 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4979 break; 4980 } 4981 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4982 AddToWorkList(Ops.back().Val); 4983 assert((Ops.back().getOpcode() == ISD::UNDEF || 4984 Ops.back().getOpcode() == ISD::Constant || 4985 Ops.back().getOpcode() == ISD::ConstantFP) && 4986 "Scalar binop didn't fold!"); 4987 } 4988 4989 if (Ops.size() == LHS.getNumOperands()) { 4990 MVT::ValueType VT = LHS.getValueType(); 4991 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4992 } 4993 } 4994 4995 return SDOperand(); 4996} 4997 4998SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4999 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5000 5001 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5002 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5003 // If we got a simplified select_cc node back from SimplifySelectCC, then 5004 // break it down into a new SETCC node, and a new SELECT node, and then return 5005 // the SELECT node, since we were called with a SELECT node. 5006 if (SCC.Val) { 5007 // Check to see if we got a select_cc back (to turn into setcc/select). 5008 // Otherwise, just return whatever node we got back, like fabs. 5009 if (SCC.getOpcode() == ISD::SELECT_CC) { 5010 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5011 SCC.getOperand(0), SCC.getOperand(1), 5012 SCC.getOperand(4)); 5013 AddToWorkList(SETCC.Val); 5014 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5015 SCC.getOperand(3), SETCC); 5016 } 5017 return SCC; 5018 } 5019 return SDOperand(); 5020} 5021 5022/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5023/// are the two values being selected between, see if we can simplify the 5024/// select. Callers of this should assume that TheSelect is deleted if this 5025/// returns true. As such, they should return the appropriate thing (e.g. the 5026/// node) back to the top-level of the DAG combiner loop to avoid it being 5027/// looked at. 5028/// 5029bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 5030 SDOperand RHS) { 5031 5032 // If this is a select from two identical things, try to pull the operation 5033 // through the select. 5034 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5035 // If this is a load and the token chain is identical, replace the select 5036 // of two loads with a load through a select of the address to load from. 5037 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5038 // constants have been dropped into the constant pool. 5039 if (LHS.getOpcode() == ISD::LOAD && 5040 // Token chains must be identical. 5041 LHS.getOperand(0) == RHS.getOperand(0)) { 5042 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5043 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5044 5045 // If this is an EXTLOAD, the VT's must match. 5046 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5047 // FIXME: this conflates two src values, discarding one. This is not 5048 // the right thing to do, but nothing uses srcvalues now. When they do, 5049 // turn SrcValue into a list of locations. 5050 SDOperand Addr; 5051 if (TheSelect->getOpcode() == ISD::SELECT) { 5052 // Check that the condition doesn't reach either load. If so, folding 5053 // this will induce a cycle into the DAG. 5054 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5055 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) { 5056 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5057 TheSelect->getOperand(0), LLD->getBasePtr(), 5058 RLD->getBasePtr()); 5059 } 5060 } else { 5061 // Check that the condition doesn't reach either load. If so, folding 5062 // this will induce a cycle into the DAG. 5063 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5064 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5065 !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) && 5066 !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) { 5067 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5068 TheSelect->getOperand(0), 5069 TheSelect->getOperand(1), 5070 LLD->getBasePtr(), RLD->getBasePtr(), 5071 TheSelect->getOperand(4)); 5072 } 5073 } 5074 5075 if (Addr.Val) { 5076 SDOperand Load; 5077 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5078 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5079 Addr,LLD->getSrcValue(), 5080 LLD->getSrcValueOffset(), 5081 LLD->isVolatile(), 5082 LLD->getAlignment()); 5083 else { 5084 Load = DAG.getExtLoad(LLD->getExtensionType(), 5085 TheSelect->getValueType(0), 5086 LLD->getChain(), Addr, LLD->getSrcValue(), 5087 LLD->getSrcValueOffset(), 5088 LLD->getMemoryVT(), 5089 LLD->isVolatile(), 5090 LLD->getAlignment()); 5091 } 5092 // Users of the select now use the result of the load. 5093 CombineTo(TheSelect, Load); 5094 5095 // Users of the old loads now use the new load's chain. We know the 5096 // old-load value is dead now. 5097 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 5098 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 5099 return true; 5100 } 5101 } 5102 } 5103 } 5104 5105 return false; 5106} 5107 5108SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 5109 SDOperand N2, SDOperand N3, 5110 ISD::CondCode CC, bool NotExtCompare) { 5111 5112 MVT::ValueType VT = N2.getValueType(); 5113 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5114 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5115 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5116 5117 // Determine if the condition we're dealing with is constant 5118 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5119 if (SCC.Val) AddToWorkList(SCC.Val); 5120 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5121 5122 // fold select_cc true, x, y -> x 5123 if (SCCC && !SCCC->isNullValue()) 5124 return N2; 5125 // fold select_cc false, x, y -> y 5126 if (SCCC && SCCC->isNullValue()) 5127 return N3; 5128 5129 // Check to see if we can simplify the select into an fabs node 5130 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5131 // Allow either -0.0 or 0.0 5132 if (CFP->getValueAPF().isZero()) { 5133 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5134 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5135 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5136 N2 == N3.getOperand(0)) 5137 return DAG.getNode(ISD::FABS, VT, N0); 5138 5139 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5140 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5141 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5142 N2.getOperand(0) == N3) 5143 return DAG.getNode(ISD::FABS, VT, N3); 5144 } 5145 } 5146 5147 // Check to see if we can perform the "gzip trick", transforming 5148 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5149 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5150 MVT::isInteger(N0.getValueType()) && 5151 MVT::isInteger(N2.getValueType()) && 5152 (N1C->isNullValue() || // (a < 0) ? b : 0 5153 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5154 MVT::ValueType XType = N0.getValueType(); 5155 MVT::ValueType AType = N2.getValueType(); 5156 if (XType >= AType) { 5157 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5158 // single-bit constant. 5159 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5160 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5161 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 5162 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5163 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5164 AddToWorkList(Shift.Val); 5165 if (XType > AType) { 5166 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5167 AddToWorkList(Shift.Val); 5168 } 5169 return DAG.getNode(ISD::AND, AType, Shift, N2); 5170 } 5171 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5172 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5173 TLI.getShiftAmountTy())); 5174 AddToWorkList(Shift.Val); 5175 if (XType > AType) { 5176 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5177 AddToWorkList(Shift.Val); 5178 } 5179 return DAG.getNode(ISD::AND, AType, Shift, N2); 5180 } 5181 } 5182 5183 // fold select C, 16, 0 -> shl C, 4 5184 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5185 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5186 5187 // If the caller doesn't want us to simplify this into a zext of a compare, 5188 // don't do it. 5189 if (NotExtCompare && N2C->getAPIntValue() == 1) 5190 return SDOperand(); 5191 5192 // Get a SetCC of the condition 5193 // FIXME: Should probably make sure that setcc is legal if we ever have a 5194 // target where it isn't. 5195 SDOperand Temp, SCC; 5196 // cast from setcc result type to select result type 5197 if (AfterLegalize) { 5198 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5199 if (N2.getValueType() < SCC.getValueType()) 5200 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5201 else 5202 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5203 } else { 5204 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5205 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5206 } 5207 AddToWorkList(SCC.Val); 5208 AddToWorkList(Temp.Val); 5209 5210 if (N2C->getAPIntValue() == 1) 5211 return Temp; 5212 // shl setcc result by log2 n2c 5213 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5214 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5215 TLI.getShiftAmountTy())); 5216 } 5217 5218 // Check to see if this is the equivalent of setcc 5219 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5220 // otherwise, go ahead with the folds. 5221 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5222 MVT::ValueType XType = N0.getValueType(); 5223 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5224 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5225 if (Res.getValueType() != VT) 5226 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5227 return Res; 5228 } 5229 5230 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5231 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5232 TLI.isOperationLegal(ISD::CTLZ, XType)) { 5233 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5234 return DAG.getNode(ISD::SRL, XType, Ctlz, 5235 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 5236 TLI.getShiftAmountTy())); 5237 } 5238 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5239 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5240 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5241 N0); 5242 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5243 DAG.getConstant(~0ULL, XType)); 5244 return DAG.getNode(ISD::SRL, XType, 5245 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5246 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5247 TLI.getShiftAmountTy())); 5248 } 5249 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5250 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5251 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5252 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5253 TLI.getShiftAmountTy())); 5254 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5255 } 5256 } 5257 5258 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5259 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5260 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5261 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5262 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 5263 MVT::ValueType XType = N0.getValueType(); 5264 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5265 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5266 TLI.getShiftAmountTy())); 5267 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5268 AddToWorkList(Shift.Val); 5269 AddToWorkList(Add.Val); 5270 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5271 } 5272 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5273 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5274 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5275 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5276 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5277 MVT::ValueType XType = N0.getValueType(); 5278 if (SubC->isNullValue() && MVT::isInteger(XType)) { 5279 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5280 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5281 TLI.getShiftAmountTy())); 5282 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5283 AddToWorkList(Shift.Val); 5284 AddToWorkList(Add.Val); 5285 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5286 } 5287 } 5288 } 5289 5290 return SDOperand(); 5291} 5292 5293/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5294SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 5295 SDOperand N1, ISD::CondCode Cond, 5296 bool foldBooleans) { 5297 TargetLowering::DAGCombinerInfo 5298 DagCombineInfo(DAG, !AfterLegalize, false, this); 5299 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5300} 5301 5302/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5303/// return a DAG expression to select that will generate the same value by 5304/// multiplying by a magic number. See: 5305/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5306SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5307 std::vector<SDNode*> Built; 5308 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5309 5310 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5311 ii != ee; ++ii) 5312 AddToWorkList(*ii); 5313 return S; 5314} 5315 5316/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5317/// return a DAG expression to select that will generate the same value by 5318/// multiplying by a magic number. See: 5319/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5320SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5321 std::vector<SDNode*> Built; 5322 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5323 5324 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5325 ii != ee; ++ii) 5326 AddToWorkList(*ii); 5327 return S; 5328} 5329 5330/// FindBaseOffset - Return true if base is known not to alias with anything 5331/// but itself. Provides base object and offset as results. 5332static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5333 // Assume it is a primitive operation. 5334 Base = Ptr; Offset = 0; 5335 5336 // If it's an adding a simple constant then integrate the offset. 5337 if (Base.getOpcode() == ISD::ADD) { 5338 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5339 Base = Base.getOperand(0); 5340 Offset += C->getValue(); 5341 } 5342 } 5343 5344 // If it's any of the following then it can't alias with anything but itself. 5345 return isa<FrameIndexSDNode>(Base) || 5346 isa<ConstantPoolSDNode>(Base) || 5347 isa<GlobalAddressSDNode>(Base); 5348} 5349 5350/// isAlias - Return true if there is any possibility that the two addresses 5351/// overlap. 5352bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5353 const Value *SrcValue1, int SrcValueOffset1, 5354 SDOperand Ptr2, int64_t Size2, 5355 const Value *SrcValue2, int SrcValueOffset2) 5356{ 5357 // If they are the same then they must be aliases. 5358 if (Ptr1 == Ptr2) return true; 5359 5360 // Gather base node and offset information. 5361 SDOperand Base1, Base2; 5362 int64_t Offset1, Offset2; 5363 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5364 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5365 5366 // If they have a same base address then... 5367 if (Base1 == Base2) { 5368 // Check to see if the addresses overlap. 5369 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5370 } 5371 5372 // If we know both bases then they can't alias. 5373 if (KnownBase1 && KnownBase2) return false; 5374 5375 if (CombinerGlobalAA) { 5376 // Use alias analysis information. 5377 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5378 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5379 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5380 AliasAnalysis::AliasResult AAResult = 5381 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5382 if (AAResult == AliasAnalysis::NoAlias) 5383 return false; 5384 } 5385 5386 // Otherwise we have to assume they alias. 5387 return true; 5388} 5389 5390/// FindAliasInfo - Extracts the relevant alias information from the memory 5391/// node. Returns true if the operand was a load. 5392bool DAGCombiner::FindAliasInfo(SDNode *N, 5393 SDOperand &Ptr, int64_t &Size, 5394 const Value *&SrcValue, int &SrcValueOffset) { 5395 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5396 Ptr = LD->getBasePtr(); 5397 Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3; 5398 SrcValue = LD->getSrcValue(); 5399 SrcValueOffset = LD->getSrcValueOffset(); 5400 return true; 5401 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5402 Ptr = ST->getBasePtr(); 5403 Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3; 5404 SrcValue = ST->getSrcValue(); 5405 SrcValueOffset = ST->getSrcValueOffset(); 5406 } else { 5407 assert(0 && "FindAliasInfo expected a memory operand"); 5408 } 5409 5410 return false; 5411} 5412 5413/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5414/// looking for aliasing nodes and adding them to the Aliases vector. 5415void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5416 SmallVector<SDOperand, 8> &Aliases) { 5417 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5418 std::set<SDNode *> Visited; // Visited node set. 5419 5420 // Get alias information for node. 5421 SDOperand Ptr; 5422 int64_t Size; 5423 const Value *SrcValue; 5424 int SrcValueOffset; 5425 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5426 5427 // Starting off. 5428 Chains.push_back(OriginalChain); 5429 5430 // Look at each chain and determine if it is an alias. If so, add it to the 5431 // aliases list. If not, then continue up the chain looking for the next 5432 // candidate. 5433 while (!Chains.empty()) { 5434 SDOperand Chain = Chains.back(); 5435 Chains.pop_back(); 5436 5437 // Don't bother if we've been before. 5438 if (Visited.find(Chain.Val) != Visited.end()) continue; 5439 Visited.insert(Chain.Val); 5440 5441 switch (Chain.getOpcode()) { 5442 case ISD::EntryToken: 5443 // Entry token is ideal chain operand, but handled in FindBetterChain. 5444 break; 5445 5446 case ISD::LOAD: 5447 case ISD::STORE: { 5448 // Get alias information for Chain. 5449 SDOperand OpPtr; 5450 int64_t OpSize; 5451 const Value *OpSrcValue; 5452 int OpSrcValueOffset; 5453 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5454 OpSrcValue, OpSrcValueOffset); 5455 5456 // If chain is alias then stop here. 5457 if (!(IsLoad && IsOpLoad) && 5458 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5459 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5460 Aliases.push_back(Chain); 5461 } else { 5462 // Look further up the chain. 5463 Chains.push_back(Chain.getOperand(0)); 5464 // Clean up old chain. 5465 AddToWorkList(Chain.Val); 5466 } 5467 break; 5468 } 5469 5470 case ISD::TokenFactor: 5471 // We have to check each of the operands of the token factor, so we queue 5472 // then up. Adding the operands to the queue (stack) in reverse order 5473 // maintains the original order and increases the likelihood that getNode 5474 // will find a matching token factor (CSE.) 5475 for (unsigned n = Chain.getNumOperands(); n;) 5476 Chains.push_back(Chain.getOperand(--n)); 5477 // Eliminate the token factor if we can. 5478 AddToWorkList(Chain.Val); 5479 break; 5480 5481 default: 5482 // For all other instructions we will just have to take what we can get. 5483 Aliases.push_back(Chain); 5484 break; 5485 } 5486 } 5487} 5488 5489/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5490/// for a better chain (aliasing node.) 5491SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5492 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5493 5494 // Accumulate all the aliases to this node. 5495 GatherAllAliases(N, OldChain, Aliases); 5496 5497 if (Aliases.size() == 0) { 5498 // If no operands then chain to entry token. 5499 return DAG.getEntryNode(); 5500 } else if (Aliases.size() == 1) { 5501 // If a single operand then chain to it. We don't need to revisit it. 5502 return Aliases[0]; 5503 } 5504 5505 // Construct a custom tailored token factor. 5506 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5507 &Aliases[0], Aliases.size()); 5508 5509 // Make sure the old chain gets cleaned up. 5510 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5511 5512 return NewChain; 5513} 5514 5515// SelectionDAG::Combine - This is the entry point for the file. 5516// 5517void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5518 if (!RunningAfterLegalize && ViewDAGCombine1) 5519 viewGraph(); 5520 if (RunningAfterLegalize && ViewDAGCombine2) 5521 viewGraph(); 5522 /// run - This is the main entry point to this class. 5523 /// 5524 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5525} 5526