DAGCombiner.cpp revision 2550e3aa67fc6b5192976b0a6ad5c8cd7829cf32
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/CodeGen/SelectionDAG.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/Target/TargetData.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include "llvm/ADT/Statistic.h" 40#include "llvm/Support/Compiler.h" 41#include "llvm/Support/CommandLine.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Support/MathExtras.h" 44#include <algorithm> 45using namespace llvm; 46 47STATISTIC(NodesCombined , "Number of dag nodes combined"); 48STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 49STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 50 51namespace { 52#ifndef NDEBUG 53 static cl::opt<bool> 54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 55 cl::desc("Pop up a window to show dags before the first " 56 "dag combine pass")); 57 static cl::opt<bool> 58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 59 cl::desc("Pop up a window to show dags before the second " 60 "dag combine pass")); 61#else 62 static const bool ViewDAGCombine1 = false; 63 static const bool ViewDAGCombine2 = false; 64#endif 65 66 static cl::opt<bool> 67 CombinerAA("combiner-alias-analysis", cl::Hidden, 68 cl::desc("Turn on alias analysis during testing")); 69 70 static cl::opt<bool> 71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 72 cl::desc("Include global information in alias analysis")); 73 74//------------------------------ DAGCombiner ---------------------------------// 75 76 class VISIBILITY_HIDDEN DAGCombiner { 77 SelectionDAG &DAG; 78 TargetLowering &TLI; 79 bool AfterLegalize; 80 81 // Worklist of all of the nodes that need to be simplified. 82 std::vector<SDNode*> WorkList; 83 84 // AA - Used for DAG load/store alias analysis. 85 AliasAnalysis &AA; 86 87 /// AddUsersToWorkList - When an instruction is simplified, add all users of 88 /// the instruction to the work lists because they might get more simplified 89 /// now. 90 /// 91 void AddUsersToWorkList(SDNode *N) { 92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 93 UI != UE; ++UI) 94 AddToWorkList(*UI); 95 } 96 97 /// removeFromWorkList - remove all instances of N from the worklist. 98 /// 99 void removeFromWorkList(SDNode *N) { 100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 101 WorkList.end()); 102 } 103 104 /// visit - call the node-specific routine that knows how to fold each 105 /// particular type of node. 106 SDOperand visit(SDNode *N); 107 108 public: 109 /// AddToWorkList - Add to the work list making sure it's instance is at the 110 /// the back (next to be processed.) 111 void AddToWorkList(SDNode *N) { 112 removeFromWorkList(N); 113 WorkList.push_back(N); 114 } 115 116 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 117 bool AddTo = true) { 118 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 119 ++NodesCombined; 120 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 121 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 122 DOUT << " and " << NumTo-1 << " other values\n"; 123 std::vector<SDNode*> NowDead; 124 DAG.ReplaceAllUsesWith(N, To, &NowDead); 125 126 if (AddTo) { 127 // Push the new nodes and any users onto the worklist 128 for (unsigned i = 0, e = NumTo; i != e; ++i) { 129 AddToWorkList(To[i].Val); 130 AddUsersToWorkList(To[i].Val); 131 } 132 } 133 134 // Nodes can be reintroduced into the worklist. Make sure we do not 135 // process a node that has been replaced. 136 removeFromWorkList(N); 137 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 138 removeFromWorkList(NowDead[i]); 139 140 // Finally, since the node is now dead, remove it from the graph. 141 DAG.DeleteNode(N); 142 return SDOperand(N, 0); 143 } 144 145 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 146 return CombineTo(N, &Res, 1, AddTo); 147 } 148 149 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 150 bool AddTo = true) { 151 SDOperand To[] = { Res0, Res1 }; 152 return CombineTo(N, To, 2, AddTo); 153 } 154 private: 155 156 /// SimplifyDemandedBits - Check the specified integer node value to see if 157 /// it can be simplified or if things it uses can be simplified by bit 158 /// propagation. If so, return true. 159 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) { 160 TargetLowering::TargetLoweringOpt TLO(DAG); 161 uint64_t KnownZero, KnownOne; 162 Demanded &= MVT::getIntVTBitMask(Op.getValueType()); 163 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 164 return false; 165 166 // Revisit the node. 167 AddToWorkList(Op.Val); 168 169 // Replace the old value with the new one. 170 ++NodesCombined; 171 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 172 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 173 DOUT << '\n'; 174 175 std::vector<SDNode*> NowDead; 176 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead); 177 178 // Push the new node and any (possibly new) users onto the worklist. 179 AddToWorkList(TLO.New.Val); 180 AddUsersToWorkList(TLO.New.Val); 181 182 // Nodes can end up on the worklist more than once. Make sure we do 183 // not process a node that has been replaced. 184 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 185 removeFromWorkList(NowDead[i]); 186 187 // Finally, if the node is now dead, remove it from the graph. The node 188 // may not be dead if the replacement process recursively simplified to 189 // something else needing this node. 190 if (TLO.Old.Val->use_empty()) { 191 removeFromWorkList(TLO.Old.Val); 192 193 // If the operands of this node are only used by the node, they will now 194 // be dead. Make sure to visit them first to delete dead nodes early. 195 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 196 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 197 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 198 199 DAG.DeleteNode(TLO.Old.Val); 200 } 201 return true; 202 } 203 204 bool CombineToPreIndexedLoadStore(SDNode *N); 205 bool CombineToPostIndexedLoadStore(SDNode *N); 206 207 208 /// combine - call the node-specific routine that knows how to fold each 209 /// particular type of node. If that doesn't do anything, try the 210 /// target-specific DAG combines. 211 SDOperand combine(SDNode *N); 212 213 // Visitation implementation - Implement dag node combining for different 214 // node types. The semantics are as follows: 215 // Return Value: 216 // SDOperand.Val == 0 - No change was made 217 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 218 // otherwise - N should be replaced by the returned Operand. 219 // 220 SDOperand visitTokenFactor(SDNode *N); 221 SDOperand visitADD(SDNode *N); 222 SDOperand visitSUB(SDNode *N); 223 SDOperand visitADDC(SDNode *N); 224 SDOperand visitADDE(SDNode *N); 225 SDOperand visitMUL(SDNode *N); 226 SDOperand visitSDIV(SDNode *N); 227 SDOperand visitUDIV(SDNode *N); 228 SDOperand visitSREM(SDNode *N); 229 SDOperand visitUREM(SDNode *N); 230 SDOperand visitMULHU(SDNode *N); 231 SDOperand visitMULHS(SDNode *N); 232 SDOperand visitSMUL_LOHI(SDNode *N); 233 SDOperand visitUMUL_LOHI(SDNode *N); 234 SDOperand visitSDIVREM(SDNode *N); 235 SDOperand visitUDIVREM(SDNode *N); 236 SDOperand visitAND(SDNode *N); 237 SDOperand visitOR(SDNode *N); 238 SDOperand visitXOR(SDNode *N); 239 SDOperand SimplifyVBinOp(SDNode *N); 240 SDOperand visitSHL(SDNode *N); 241 SDOperand visitSRA(SDNode *N); 242 SDOperand visitSRL(SDNode *N); 243 SDOperand visitCTLZ(SDNode *N); 244 SDOperand visitCTTZ(SDNode *N); 245 SDOperand visitCTPOP(SDNode *N); 246 SDOperand visitSELECT(SDNode *N); 247 SDOperand visitSELECT_CC(SDNode *N); 248 SDOperand visitSETCC(SDNode *N); 249 SDOperand visitSIGN_EXTEND(SDNode *N); 250 SDOperand visitZERO_EXTEND(SDNode *N); 251 SDOperand visitANY_EXTEND(SDNode *N); 252 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 253 SDOperand visitTRUNCATE(SDNode *N); 254 SDOperand visitBIT_CONVERT(SDNode *N); 255 SDOperand visitFADD(SDNode *N); 256 SDOperand visitFSUB(SDNode *N); 257 SDOperand visitFMUL(SDNode *N); 258 SDOperand visitFDIV(SDNode *N); 259 SDOperand visitFREM(SDNode *N); 260 SDOperand visitFCOPYSIGN(SDNode *N); 261 SDOperand visitSINT_TO_FP(SDNode *N); 262 SDOperand visitUINT_TO_FP(SDNode *N); 263 SDOperand visitFP_TO_SINT(SDNode *N); 264 SDOperand visitFP_TO_UINT(SDNode *N); 265 SDOperand visitFP_ROUND(SDNode *N); 266 SDOperand visitFP_ROUND_INREG(SDNode *N); 267 SDOperand visitFP_EXTEND(SDNode *N); 268 SDOperand visitFNEG(SDNode *N); 269 SDOperand visitFABS(SDNode *N); 270 SDOperand visitBRCOND(SDNode *N); 271 SDOperand visitBR_CC(SDNode *N); 272 SDOperand visitLOAD(SDNode *N); 273 SDOperand visitSTORE(SDNode *N); 274 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 275 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 276 SDOperand visitBUILD_VECTOR(SDNode *N); 277 SDOperand visitCONCAT_VECTORS(SDNode *N); 278 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 279 280 SDOperand XformToShuffleWithZero(SDNode *N); 281 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 282 283 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 284 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 285 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 286 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 287 SDOperand N3, ISD::CondCode CC, 288 bool NotExtCompare = false); 289 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 290 ISD::CondCode Cond, bool foldBooleans = true); 291 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp); 292 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 293 SDOperand BuildSDIV(SDNode *N); 294 SDOperand BuildUDIV(SDNode *N); 295 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 296 SDOperand ReduceLoadWidth(SDNode *N); 297 298 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask); 299 300 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 301 /// looking for aliasing nodes and adding them to the Aliases vector. 302 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 303 SmallVector<SDOperand, 8> &Aliases); 304 305 /// isAlias - Return true if there is any possibility that the two addresses 306 /// overlap. 307 bool isAlias(SDOperand Ptr1, int64_t Size1, 308 const Value *SrcValue1, int SrcValueOffset1, 309 SDOperand Ptr2, int64_t Size2, 310 const Value *SrcValue2, int SrcValueOffset2); 311 312 /// FindAliasInfo - Extracts the relevant alias information from the memory 313 /// node. Returns true if the operand was a load. 314 bool FindAliasInfo(SDNode *N, 315 SDOperand &Ptr, int64_t &Size, 316 const Value *&SrcValue, int &SrcValueOffset); 317 318 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 319 /// looking for a better chain (aliasing node.) 320 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 321 322public: 323 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 324 : DAG(D), 325 TLI(D.getTargetLoweringInfo()), 326 AfterLegalize(false), 327 AA(A) {} 328 329 /// Run - runs the dag combiner on all nodes in the work list 330 void Run(bool RunningAfterLegalize); 331 }; 332} 333 334//===----------------------------------------------------------------------===// 335// TargetLowering::DAGCombinerInfo implementation 336//===----------------------------------------------------------------------===// 337 338void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 339 ((DAGCombiner*)DC)->AddToWorkList(N); 340} 341 342SDOperand TargetLowering::DAGCombinerInfo:: 343CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 344 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 345} 346 347SDOperand TargetLowering::DAGCombinerInfo:: 348CombineTo(SDNode *N, SDOperand Res) { 349 return ((DAGCombiner*)DC)->CombineTo(N, Res); 350} 351 352 353SDOperand TargetLowering::DAGCombinerInfo:: 354CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 355 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 356} 357 358 359//===----------------------------------------------------------------------===// 360// Helper Functions 361//===----------------------------------------------------------------------===// 362 363/// isNegatibleForFree - Return 1 if we can compute the negated form of the 364/// specified expression for the same cost as the expression itself, or 2 if we 365/// can compute the negated form more cheaply than the expression itself. 366static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 367 // No compile time optimizations on this type. 368 if (Op.getValueType() == MVT::ppcf128) 369 return 0; 370 371 // fneg is removable even if it has multiple uses. 372 if (Op.getOpcode() == ISD::FNEG) return 2; 373 374 // Don't allow anything with multiple uses. 375 if (!Op.hasOneUse()) return 0; 376 377 // Don't recurse exponentially. 378 if (Depth > 6) return 0; 379 380 switch (Op.getOpcode()) { 381 default: return false; 382 case ISD::ConstantFP: 383 return 1; 384 case ISD::FADD: 385 // FIXME: determine better conditions for this xform. 386 if (!UnsafeFPMath) return 0; 387 388 // -(A+B) -> -A - B 389 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 390 return V; 391 // -(A+B) -> -B - A 392 return isNegatibleForFree(Op.getOperand(1), Depth+1); 393 case ISD::FSUB: 394 // We can't turn -(A-B) into B-A when we honor signed zeros. 395 if (!UnsafeFPMath) return 0; 396 397 // -(A-B) -> B-A 398 return 1; 399 400 case ISD::FMUL: 401 case ISD::FDIV: 402 if (HonorSignDependentRoundingFPMath()) return 0; 403 404 // -(X*Y) -> (-X * Y) or (X*-Y) 405 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 406 return V; 407 408 return isNegatibleForFree(Op.getOperand(1), Depth+1); 409 410 case ISD::FP_EXTEND: 411 case ISD::FP_ROUND: 412 case ISD::FSIN: 413 return isNegatibleForFree(Op.getOperand(0), Depth+1); 414 } 415} 416 417/// GetNegatedExpression - If isNegatibleForFree returns true, this function 418/// returns the newly negated expression. 419static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 420 unsigned Depth = 0) { 421 // fneg is removable even if it has multiple uses. 422 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 423 424 // Don't allow anything with multiple uses. 425 assert(Op.hasOneUse() && "Unknown reuse!"); 426 427 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 428 switch (Op.getOpcode()) { 429 default: assert(0 && "Unknown code"); 430 case ISD::ConstantFP: { 431 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 432 V.changeSign(); 433 return DAG.getConstantFP(V, Op.getValueType()); 434 } 435 case ISD::FADD: 436 // FIXME: determine better conditions for this xform. 437 assert(UnsafeFPMath); 438 439 // -(A+B) -> -A - B 440 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 441 return DAG.getNode(ISD::FSUB, Op.getValueType(), 442 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 443 Op.getOperand(1)); 444 // -(A+B) -> -B - A 445 return DAG.getNode(ISD::FSUB, Op.getValueType(), 446 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 447 Op.getOperand(0)); 448 case ISD::FSUB: 449 // We can't turn -(A-B) into B-A when we honor signed zeros. 450 assert(UnsafeFPMath); 451 452 // -(0-B) -> B 453 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 454 if (N0CFP->getValueAPF().isZero()) 455 return Op.getOperand(1); 456 457 // -(A-B) -> B-A 458 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 459 Op.getOperand(0)); 460 461 case ISD::FMUL: 462 case ISD::FDIV: 463 assert(!HonorSignDependentRoundingFPMath()); 464 465 // -(X*Y) -> -X * Y 466 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 467 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 468 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 469 Op.getOperand(1)); 470 471 // -(X*Y) -> X * -Y 472 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 473 Op.getOperand(0), 474 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 475 476 case ISD::FP_EXTEND: 477 case ISD::FP_ROUND: 478 case ISD::FSIN: 479 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 480 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 481 } 482} 483 484 485// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 486// that selects between the values 1 and 0, making it equivalent to a setcc. 487// Also, set the incoming LHS, RHS, and CC references to the appropriate 488// nodes based on the type of node we are checking. This simplifies life a 489// bit for the callers. 490static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 491 SDOperand &CC) { 492 if (N.getOpcode() == ISD::SETCC) { 493 LHS = N.getOperand(0); 494 RHS = N.getOperand(1); 495 CC = N.getOperand(2); 496 return true; 497 } 498 if (N.getOpcode() == ISD::SELECT_CC && 499 N.getOperand(2).getOpcode() == ISD::Constant && 500 N.getOperand(3).getOpcode() == ISD::Constant && 501 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 502 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 503 LHS = N.getOperand(0); 504 RHS = N.getOperand(1); 505 CC = N.getOperand(4); 506 return true; 507 } 508 return false; 509} 510 511// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 512// one use. If this is true, it allows the users to invert the operation for 513// free when it is profitable to do so. 514static bool isOneUseSetCC(SDOperand N) { 515 SDOperand N0, N1, N2; 516 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 517 return true; 518 return false; 519} 520 521SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 522 MVT::ValueType VT = N0.getValueType(); 523 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 524 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 525 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 526 if (isa<ConstantSDNode>(N1)) { 527 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 528 AddToWorkList(OpNode.Val); 529 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 530 } else if (N0.hasOneUse()) { 531 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 532 AddToWorkList(OpNode.Val); 533 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 534 } 535 } 536 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 537 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 538 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 539 if (isa<ConstantSDNode>(N0)) { 540 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 541 AddToWorkList(OpNode.Val); 542 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 543 } else if (N1.hasOneUse()) { 544 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 545 AddToWorkList(OpNode.Val); 546 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 547 } 548 } 549 return SDOperand(); 550} 551 552//===----------------------------------------------------------------------===// 553// Main DAG Combiner implementation 554//===----------------------------------------------------------------------===// 555 556void DAGCombiner::Run(bool RunningAfterLegalize) { 557 // set the instance variable, so that the various visit routines may use it. 558 AfterLegalize = RunningAfterLegalize; 559 560 // Add all the dag nodes to the worklist. 561 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 562 E = DAG.allnodes_end(); I != E; ++I) 563 WorkList.push_back(I); 564 565 // Create a dummy node (which is not added to allnodes), that adds a reference 566 // to the root node, preventing it from being deleted, and tracking any 567 // changes of the root. 568 HandleSDNode Dummy(DAG.getRoot()); 569 570 // The root of the dag may dangle to deleted nodes until the dag combiner is 571 // done. Set it to null to avoid confusion. 572 DAG.setRoot(SDOperand()); 573 574 // while the worklist isn't empty, inspect the node on the end of it and 575 // try and combine it. 576 while (!WorkList.empty()) { 577 SDNode *N = WorkList.back(); 578 WorkList.pop_back(); 579 580 // If N has no uses, it is dead. Make sure to revisit all N's operands once 581 // N is deleted from the DAG, since they too may now be dead or may have a 582 // reduced number of uses, allowing other xforms. 583 if (N->use_empty() && N != &Dummy) { 584 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 585 AddToWorkList(N->getOperand(i).Val); 586 587 DAG.DeleteNode(N); 588 continue; 589 } 590 591 SDOperand RV = combine(N); 592 593 if (RV.Val) { 594 ++NodesCombined; 595 // If we get back the same node we passed in, rather than a new node or 596 // zero, we know that the node must have defined multiple values and 597 // CombineTo was used. Since CombineTo takes care of the worklist 598 // mechanics for us, we have no work to do in this case. 599 if (RV.Val != N) { 600 assert(N->getOpcode() != ISD::DELETED_NODE && 601 RV.Val->getOpcode() != ISD::DELETED_NODE && 602 "Node was deleted but visit returned new node!"); 603 604 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 605 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 606 DOUT << '\n'; 607 std::vector<SDNode*> NowDead; 608 if (N->getNumValues() == RV.Val->getNumValues()) 609 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 610 else { 611 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 612 SDOperand OpV = RV; 613 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 614 } 615 616 // Push the new node and any users onto the worklist 617 AddToWorkList(RV.Val); 618 AddUsersToWorkList(RV.Val); 619 620 // Nodes can be reintroduced into the worklist. Make sure we do not 621 // process a node that has been replaced. 622 removeFromWorkList(N); 623 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 624 removeFromWorkList(NowDead[i]); 625 626 // Finally, since the node is now dead, remove it from the graph. 627 DAG.DeleteNode(N); 628 } 629 } 630 } 631 632 // If the root changed (e.g. it was a dead load, update the root). 633 DAG.setRoot(Dummy.getValue()); 634} 635 636SDOperand DAGCombiner::visit(SDNode *N) { 637 switch(N->getOpcode()) { 638 default: break; 639 case ISD::TokenFactor: return visitTokenFactor(N); 640 case ISD::ADD: return visitADD(N); 641 case ISD::SUB: return visitSUB(N); 642 case ISD::ADDC: return visitADDC(N); 643 case ISD::ADDE: return visitADDE(N); 644 case ISD::MUL: return visitMUL(N); 645 case ISD::SDIV: return visitSDIV(N); 646 case ISD::UDIV: return visitUDIV(N); 647 case ISD::SREM: return visitSREM(N); 648 case ISD::UREM: return visitUREM(N); 649 case ISD::MULHU: return visitMULHU(N); 650 case ISD::MULHS: return visitMULHS(N); 651 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 652 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 653 case ISD::SDIVREM: return visitSDIVREM(N); 654 case ISD::UDIVREM: return visitUDIVREM(N); 655 case ISD::AND: return visitAND(N); 656 case ISD::OR: return visitOR(N); 657 case ISD::XOR: return visitXOR(N); 658 case ISD::SHL: return visitSHL(N); 659 case ISD::SRA: return visitSRA(N); 660 case ISD::SRL: return visitSRL(N); 661 case ISD::CTLZ: return visitCTLZ(N); 662 case ISD::CTTZ: return visitCTTZ(N); 663 case ISD::CTPOP: return visitCTPOP(N); 664 case ISD::SELECT: return visitSELECT(N); 665 case ISD::SELECT_CC: return visitSELECT_CC(N); 666 case ISD::SETCC: return visitSETCC(N); 667 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 668 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 669 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 670 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 671 case ISD::TRUNCATE: return visitTRUNCATE(N); 672 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 673 case ISD::FADD: return visitFADD(N); 674 case ISD::FSUB: return visitFSUB(N); 675 case ISD::FMUL: return visitFMUL(N); 676 case ISD::FDIV: return visitFDIV(N); 677 case ISD::FREM: return visitFREM(N); 678 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 679 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 680 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 681 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 682 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 683 case ISD::FP_ROUND: return visitFP_ROUND(N); 684 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 685 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 686 case ISD::FNEG: return visitFNEG(N); 687 case ISD::FABS: return visitFABS(N); 688 case ISD::BRCOND: return visitBRCOND(N); 689 case ISD::BR_CC: return visitBR_CC(N); 690 case ISD::LOAD: return visitLOAD(N); 691 case ISD::STORE: return visitSTORE(N); 692 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 693 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 694 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 695 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 696 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 697 } 698 return SDOperand(); 699} 700 701SDOperand DAGCombiner::combine(SDNode *N) { 702 703 SDOperand RV = visit(N); 704 705 // If nothing happened, try a target-specific DAG combine. 706 if (RV.Val == 0) { 707 assert(N->getOpcode() != ISD::DELETED_NODE && 708 "Node was deleted but visit returned NULL!"); 709 710 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 711 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 712 713 // Expose the DAG combiner to the target combiner impls. 714 TargetLowering::DAGCombinerInfo 715 DagCombineInfo(DAG, !AfterLegalize, false, this); 716 717 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 718 } 719 } 720 721 return RV; 722} 723 724/// getInputChainForNode - Given a node, return its input chain if it has one, 725/// otherwise return a null sd operand. 726static SDOperand getInputChainForNode(SDNode *N) { 727 if (unsigned NumOps = N->getNumOperands()) { 728 if (N->getOperand(0).getValueType() == MVT::Other) 729 return N->getOperand(0); 730 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 731 return N->getOperand(NumOps-1); 732 for (unsigned i = 1; i < NumOps-1; ++i) 733 if (N->getOperand(i).getValueType() == MVT::Other) 734 return N->getOperand(i); 735 } 736 return SDOperand(0, 0); 737} 738 739SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 740 // If N has two operands, where one has an input chain equal to the other, 741 // the 'other' chain is redundant. 742 if (N->getNumOperands() == 2) { 743 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 744 return N->getOperand(0); 745 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 746 return N->getOperand(1); 747 } 748 749 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 750 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 751 SmallPtrSet<SDNode*, 16> SeenOps; 752 bool Changed = false; // If we should replace this token factor. 753 754 // Start out with this token factor. 755 TFs.push_back(N); 756 757 // Iterate through token factors. The TFs grows when new token factors are 758 // encountered. 759 for (unsigned i = 0; i < TFs.size(); ++i) { 760 SDNode *TF = TFs[i]; 761 762 // Check each of the operands. 763 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 764 SDOperand Op = TF->getOperand(i); 765 766 switch (Op.getOpcode()) { 767 case ISD::EntryToken: 768 // Entry tokens don't need to be added to the list. They are 769 // rededundant. 770 Changed = true; 771 break; 772 773 case ISD::TokenFactor: 774 if ((CombinerAA || Op.hasOneUse()) && 775 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 776 // Queue up for processing. 777 TFs.push_back(Op.Val); 778 // Clean up in case the token factor is removed. 779 AddToWorkList(Op.Val); 780 Changed = true; 781 break; 782 } 783 // Fall thru 784 785 default: 786 // Only add if it isn't already in the list. 787 if (SeenOps.insert(Op.Val)) 788 Ops.push_back(Op); 789 else 790 Changed = true; 791 break; 792 } 793 } 794 } 795 796 SDOperand Result; 797 798 // If we've change things around then replace token factor. 799 if (Changed) { 800 if (Ops.size() == 0) { 801 // The entry token is the only possible outcome. 802 Result = DAG.getEntryNode(); 803 } else { 804 // New and improved token factor. 805 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 806 } 807 808 // Don't add users to work list. 809 return CombineTo(N, Result, false); 810 } 811 812 return Result; 813} 814 815static 816SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 817 MVT::ValueType VT = N0.getValueType(); 818 SDOperand N00 = N0.getOperand(0); 819 SDOperand N01 = N0.getOperand(1); 820 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 821 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 822 isa<ConstantSDNode>(N00.getOperand(1))) { 823 N0 = DAG.getNode(ISD::ADD, VT, 824 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 825 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 826 return DAG.getNode(ISD::ADD, VT, N0, N1); 827 } 828 return SDOperand(); 829} 830 831static 832SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 833 SelectionDAG &DAG) { 834 MVT::ValueType VT = N->getValueType(0); 835 unsigned Opc = N->getOpcode(); 836 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 837 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 838 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 839 ISD::CondCode CC = ISD::SETCC_INVALID; 840 if (isSlctCC) 841 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 842 else { 843 SDOperand CCOp = Slct.getOperand(0); 844 if (CCOp.getOpcode() == ISD::SETCC) 845 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 846 } 847 848 bool DoXform = false; 849 bool InvCC = false; 850 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 851 "Bad input!"); 852 if (LHS.getOpcode() == ISD::Constant && 853 cast<ConstantSDNode>(LHS)->isNullValue()) 854 DoXform = true; 855 else if (CC != ISD::SETCC_INVALID && 856 RHS.getOpcode() == ISD::Constant && 857 cast<ConstantSDNode>(RHS)->isNullValue()) { 858 std::swap(LHS, RHS); 859 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType() 860 : Slct.getOperand(0).getOperand(0).getValueType()); 861 CC = ISD::getSetCCInverse(CC, isInt); 862 DoXform = true; 863 InvCC = true; 864 } 865 866 if (DoXform) { 867 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 868 if (isSlctCC) 869 return DAG.getSelectCC(OtherOp, Result, 870 Slct.getOperand(0), Slct.getOperand(1), CC); 871 SDOperand CCOp = Slct.getOperand(0); 872 if (InvCC) 873 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 874 CCOp.getOperand(1), CC); 875 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 876 } 877 return SDOperand(); 878} 879 880SDOperand DAGCombiner::visitADD(SDNode *N) { 881 SDOperand N0 = N->getOperand(0); 882 SDOperand N1 = N->getOperand(1); 883 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 884 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 885 MVT::ValueType VT = N0.getValueType(); 886 887 // fold vector ops 888 if (MVT::isVector(VT)) { 889 SDOperand FoldedVOp = SimplifyVBinOp(N); 890 if (FoldedVOp.Val) return FoldedVOp; 891 } 892 893 // fold (add x, undef) -> undef 894 if (N0.getOpcode() == ISD::UNDEF) 895 return N0; 896 if (N1.getOpcode() == ISD::UNDEF) 897 return N1; 898 // fold (add c1, c2) -> c1+c2 899 if (N0C && N1C) 900 return DAG.getNode(ISD::ADD, VT, N0, N1); 901 // canonicalize constant to RHS 902 if (N0C && !N1C) 903 return DAG.getNode(ISD::ADD, VT, N1, N0); 904 // fold (add x, 0) -> x 905 if (N1C && N1C->isNullValue()) 906 return N0; 907 // fold ((c1-A)+c2) -> (c1+c2)-A 908 if (N1C && N0.getOpcode() == ISD::SUB) 909 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 910 return DAG.getNode(ISD::SUB, VT, 911 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 912 N0.getOperand(1)); 913 // reassociate add 914 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 915 if (RADD.Val != 0) 916 return RADD; 917 // fold ((0-A) + B) -> B-A 918 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 919 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 920 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 921 // fold (A + (0-B)) -> A-B 922 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 923 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 924 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 925 // fold (A+(B-A)) -> B 926 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 927 return N1.getOperand(0); 928 929 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 930 return SDOperand(N, 0); 931 932 // fold (a+b) -> (a|b) iff a and b share no bits. 933 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 934 uint64_t LHSZero, LHSOne; 935 uint64_t RHSZero, RHSOne; 936 uint64_t Mask = MVT::getIntVTBitMask(VT); 937 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 938 if (LHSZero) { 939 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 940 941 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 942 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 943 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 944 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 945 return DAG.getNode(ISD::OR, VT, N0, N1); 946 } 947 } 948 949 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 950 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 951 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 952 if (Result.Val) return Result; 953 } 954 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 955 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 956 if (Result.Val) return Result; 957 } 958 959 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 960 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 961 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 962 if (Result.Val) return Result; 963 } 964 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 965 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 966 if (Result.Val) return Result; 967 } 968 969 return SDOperand(); 970} 971 972SDOperand DAGCombiner::visitADDC(SDNode *N) { 973 SDOperand N0 = N->getOperand(0); 974 SDOperand N1 = N->getOperand(1); 975 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 976 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 977 MVT::ValueType VT = N0.getValueType(); 978 979 // If the flag result is dead, turn this into an ADD. 980 if (N->hasNUsesOfValue(0, 1)) 981 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 982 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 983 984 // canonicalize constant to RHS. 985 if (N0C && !N1C) { 986 SDOperand Ops[] = { N1, N0 }; 987 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 988 } 989 990 // fold (addc x, 0) -> x + no carry out 991 if (N1C && N1C->isNullValue()) 992 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 993 994 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 995 uint64_t LHSZero, LHSOne; 996 uint64_t RHSZero, RHSOne; 997 uint64_t Mask = MVT::getIntVTBitMask(VT); 998 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 999 if (LHSZero) { 1000 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1001 1002 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1003 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1004 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1005 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1006 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1007 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1008 } 1009 1010 return SDOperand(); 1011} 1012 1013SDOperand DAGCombiner::visitADDE(SDNode *N) { 1014 SDOperand N0 = N->getOperand(0); 1015 SDOperand N1 = N->getOperand(1); 1016 SDOperand CarryIn = N->getOperand(2); 1017 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1018 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1019 //MVT::ValueType VT = N0.getValueType(); 1020 1021 // canonicalize constant to RHS 1022 if (N0C && !N1C) { 1023 SDOperand Ops[] = { N1, N0, CarryIn }; 1024 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1025 } 1026 1027 // fold (adde x, y, false) -> (addc x, y) 1028 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1029 SDOperand Ops[] = { N1, N0 }; 1030 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1031 } 1032 1033 return SDOperand(); 1034} 1035 1036 1037 1038SDOperand DAGCombiner::visitSUB(SDNode *N) { 1039 SDOperand N0 = N->getOperand(0); 1040 SDOperand N1 = N->getOperand(1); 1041 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1042 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1043 MVT::ValueType VT = N0.getValueType(); 1044 1045 // fold vector ops 1046 if (MVT::isVector(VT)) { 1047 SDOperand FoldedVOp = SimplifyVBinOp(N); 1048 if (FoldedVOp.Val) return FoldedVOp; 1049 } 1050 1051 // fold (sub x, x) -> 0 1052 if (N0 == N1) 1053 return DAG.getConstant(0, N->getValueType(0)); 1054 // fold (sub c1, c2) -> c1-c2 1055 if (N0C && N1C) 1056 return DAG.getNode(ISD::SUB, VT, N0, N1); 1057 // fold (sub x, c) -> (add x, -c) 1058 if (N1C) 1059 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1060 // fold (A+B)-A -> B 1061 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1062 return N0.getOperand(1); 1063 // fold (A+B)-B -> A 1064 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1065 return N0.getOperand(0); 1066 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1067 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1068 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1069 if (Result.Val) return Result; 1070 } 1071 // If either operand of a sub is undef, the result is undef 1072 if (N0.getOpcode() == ISD::UNDEF) 1073 return N0; 1074 if (N1.getOpcode() == ISD::UNDEF) 1075 return N1; 1076 1077 return SDOperand(); 1078} 1079 1080SDOperand DAGCombiner::visitMUL(SDNode *N) { 1081 SDOperand N0 = N->getOperand(0); 1082 SDOperand N1 = N->getOperand(1); 1083 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1085 MVT::ValueType VT = N0.getValueType(); 1086 1087 // fold vector ops 1088 if (MVT::isVector(VT)) { 1089 SDOperand FoldedVOp = SimplifyVBinOp(N); 1090 if (FoldedVOp.Val) return FoldedVOp; 1091 } 1092 1093 // fold (mul x, undef) -> 0 1094 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1095 return DAG.getConstant(0, VT); 1096 // fold (mul c1, c2) -> c1*c2 1097 if (N0C && N1C) 1098 return DAG.getNode(ISD::MUL, VT, N0, N1); 1099 // canonicalize constant to RHS 1100 if (N0C && !N1C) 1101 return DAG.getNode(ISD::MUL, VT, N1, N0); 1102 // fold (mul x, 0) -> 0 1103 if (N1C && N1C->isNullValue()) 1104 return N1; 1105 // fold (mul x, -1) -> 0-x 1106 if (N1C && N1C->isAllOnesValue()) 1107 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1108 // fold (mul x, (1 << c)) -> x << c 1109 if (N1C && isPowerOf2_64(N1C->getValue())) 1110 return DAG.getNode(ISD::SHL, VT, N0, 1111 DAG.getConstant(Log2_64(N1C->getValue()), 1112 TLI.getShiftAmountTy())); 1113 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1114 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1115 // FIXME: If the input is something that is easily negated (e.g. a 1116 // single-use add), we should put the negate there. 1117 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1118 DAG.getNode(ISD::SHL, VT, N0, 1119 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1120 TLI.getShiftAmountTy()))); 1121 } 1122 1123 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1124 if (N1C && N0.getOpcode() == ISD::SHL && 1125 isa<ConstantSDNode>(N0.getOperand(1))) { 1126 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1127 AddToWorkList(C3.Val); 1128 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1129 } 1130 1131 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1132 // use. 1133 { 1134 SDOperand Sh(0,0), Y(0,0); 1135 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1136 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1137 N0.Val->hasOneUse()) { 1138 Sh = N0; Y = N1; 1139 } else if (N1.getOpcode() == ISD::SHL && 1140 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1141 Sh = N1; Y = N0; 1142 } 1143 if (Sh.Val) { 1144 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1145 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1146 } 1147 } 1148 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1149 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1150 isa<ConstantSDNode>(N0.getOperand(1))) { 1151 return DAG.getNode(ISD::ADD, VT, 1152 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1153 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1154 } 1155 1156 // reassociate mul 1157 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1158 if (RMUL.Val != 0) 1159 return RMUL; 1160 1161 return SDOperand(); 1162} 1163 1164SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1165 SDOperand N0 = N->getOperand(0); 1166 SDOperand N1 = N->getOperand(1); 1167 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1168 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1169 MVT::ValueType VT = N->getValueType(0); 1170 1171 // fold vector ops 1172 if (MVT::isVector(VT)) { 1173 SDOperand FoldedVOp = SimplifyVBinOp(N); 1174 if (FoldedVOp.Val) return FoldedVOp; 1175 } 1176 1177 // fold (sdiv c1, c2) -> c1/c2 1178 if (N0C && N1C && !N1C->isNullValue()) 1179 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1180 // fold (sdiv X, 1) -> X 1181 if (N1C && N1C->getSignExtended() == 1LL) 1182 return N0; 1183 // fold (sdiv X, -1) -> 0-X 1184 if (N1C && N1C->isAllOnesValue()) 1185 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1186 // If we know the sign bits of both operands are zero, strength reduce to a 1187 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1188 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1189 if (DAG.MaskedValueIsZero(N1, SignBit) && 1190 DAG.MaskedValueIsZero(N0, SignBit)) 1191 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1192 // fold (sdiv X, pow2) -> simple ops after legalize 1193 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1194 (isPowerOf2_64(N1C->getSignExtended()) || 1195 isPowerOf2_64(-N1C->getSignExtended()))) { 1196 // If dividing by powers of two is cheap, then don't perform the following 1197 // fold. 1198 if (TLI.isPow2DivCheap()) 1199 return SDOperand(); 1200 int64_t pow2 = N1C->getSignExtended(); 1201 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1202 unsigned lg2 = Log2_64(abs2); 1203 // Splat the sign bit into the register 1204 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1205 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1206 TLI.getShiftAmountTy())); 1207 AddToWorkList(SGN.Val); 1208 // Add (N0 < 0) ? abs2 - 1 : 0; 1209 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1210 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1211 TLI.getShiftAmountTy())); 1212 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1213 AddToWorkList(SRL.Val); 1214 AddToWorkList(ADD.Val); // Divide by pow2 1215 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1216 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1217 // If we're dividing by a positive value, we're done. Otherwise, we must 1218 // negate the result. 1219 if (pow2 > 0) 1220 return SRA; 1221 AddToWorkList(SRA.Val); 1222 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1223 } 1224 // if integer divide is expensive and we satisfy the requirements, emit an 1225 // alternate sequence. 1226 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1227 !TLI.isIntDivCheap()) { 1228 SDOperand Op = BuildSDIV(N); 1229 if (Op.Val) return Op; 1230 } 1231 1232 // undef / X -> 0 1233 if (N0.getOpcode() == ISD::UNDEF) 1234 return DAG.getConstant(0, VT); 1235 // X / undef -> undef 1236 if (N1.getOpcode() == ISD::UNDEF) 1237 return N1; 1238 1239 return SDOperand(); 1240} 1241 1242SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1243 SDOperand N0 = N->getOperand(0); 1244 SDOperand N1 = N->getOperand(1); 1245 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1246 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1247 MVT::ValueType VT = N->getValueType(0); 1248 1249 // fold vector ops 1250 if (MVT::isVector(VT)) { 1251 SDOperand FoldedVOp = SimplifyVBinOp(N); 1252 if (FoldedVOp.Val) return FoldedVOp; 1253 } 1254 1255 // fold (udiv c1, c2) -> c1/c2 1256 if (N0C && N1C && !N1C->isNullValue()) 1257 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1258 // fold (udiv x, (1 << c)) -> x >>u c 1259 if (N1C && isPowerOf2_64(N1C->getValue())) 1260 return DAG.getNode(ISD::SRL, VT, N0, 1261 DAG.getConstant(Log2_64(N1C->getValue()), 1262 TLI.getShiftAmountTy())); 1263 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1264 if (N1.getOpcode() == ISD::SHL) { 1265 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1266 if (isPowerOf2_64(SHC->getValue())) { 1267 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1268 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1269 DAG.getConstant(Log2_64(SHC->getValue()), 1270 ADDVT)); 1271 AddToWorkList(Add.Val); 1272 return DAG.getNode(ISD::SRL, VT, N0, Add); 1273 } 1274 } 1275 } 1276 // fold (udiv x, c) -> alternate 1277 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1278 SDOperand Op = BuildUDIV(N); 1279 if (Op.Val) return Op; 1280 } 1281 1282 // undef / X -> 0 1283 if (N0.getOpcode() == ISD::UNDEF) 1284 return DAG.getConstant(0, VT); 1285 // X / undef -> undef 1286 if (N1.getOpcode() == ISD::UNDEF) 1287 return N1; 1288 1289 return SDOperand(); 1290} 1291 1292SDOperand DAGCombiner::visitSREM(SDNode *N) { 1293 SDOperand N0 = N->getOperand(0); 1294 SDOperand N1 = N->getOperand(1); 1295 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1296 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1297 MVT::ValueType VT = N->getValueType(0); 1298 1299 // fold (srem c1, c2) -> c1%c2 1300 if (N0C && N1C && !N1C->isNullValue()) 1301 return DAG.getNode(ISD::SREM, VT, N0, N1); 1302 // If we know the sign bits of both operands are zero, strength reduce to a 1303 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1304 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1305 if (DAG.MaskedValueIsZero(N1, SignBit) && 1306 DAG.MaskedValueIsZero(N0, SignBit)) 1307 return DAG.getNode(ISD::UREM, VT, N0, N1); 1308 1309 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1310 // the remainder operation. 1311 if (N1C && !N1C->isNullValue()) { 1312 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1313 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1314 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1315 AddToWorkList(Div.Val); 1316 AddToWorkList(Mul.Val); 1317 return Sub; 1318 } 1319 1320 // undef % X -> 0 1321 if (N0.getOpcode() == ISD::UNDEF) 1322 return DAG.getConstant(0, VT); 1323 // X % undef -> undef 1324 if (N1.getOpcode() == ISD::UNDEF) 1325 return N1; 1326 1327 return SDOperand(); 1328} 1329 1330SDOperand DAGCombiner::visitUREM(SDNode *N) { 1331 SDOperand N0 = N->getOperand(0); 1332 SDOperand N1 = N->getOperand(1); 1333 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1334 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1335 MVT::ValueType VT = N->getValueType(0); 1336 1337 // fold (urem c1, c2) -> c1%c2 1338 if (N0C && N1C && !N1C->isNullValue()) 1339 return DAG.getNode(ISD::UREM, VT, N0, N1); 1340 // fold (urem x, pow2) -> (and x, pow2-1) 1341 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1342 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1343 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1344 if (N1.getOpcode() == ISD::SHL) { 1345 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1346 if (isPowerOf2_64(SHC->getValue())) { 1347 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1348 AddToWorkList(Add.Val); 1349 return DAG.getNode(ISD::AND, VT, N0, Add); 1350 } 1351 } 1352 } 1353 1354 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1355 // the remainder operation. 1356 if (N1C && !N1C->isNullValue()) { 1357 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1358 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1359 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1360 AddToWorkList(Div.Val); 1361 AddToWorkList(Mul.Val); 1362 return Sub; 1363 } 1364 1365 // undef % X -> 0 1366 if (N0.getOpcode() == ISD::UNDEF) 1367 return DAG.getConstant(0, VT); 1368 // X % undef -> undef 1369 if (N1.getOpcode() == ISD::UNDEF) 1370 return N1; 1371 1372 return SDOperand(); 1373} 1374 1375SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1376 SDOperand N0 = N->getOperand(0); 1377 SDOperand N1 = N->getOperand(1); 1378 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1379 MVT::ValueType VT = N->getValueType(0); 1380 1381 // fold (mulhs x, 0) -> 0 1382 if (N1C && N1C->isNullValue()) 1383 return N1; 1384 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1385 if (N1C && N1C->getValue() == 1) 1386 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1387 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1388 TLI.getShiftAmountTy())); 1389 // fold (mulhs x, undef) -> 0 1390 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1391 return DAG.getConstant(0, VT); 1392 1393 return SDOperand(); 1394} 1395 1396SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1397 SDOperand N0 = N->getOperand(0); 1398 SDOperand N1 = N->getOperand(1); 1399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1400 MVT::ValueType VT = N->getValueType(0); 1401 1402 // fold (mulhu x, 0) -> 0 1403 if (N1C && N1C->isNullValue()) 1404 return N1; 1405 // fold (mulhu x, 1) -> 0 1406 if (N1C && N1C->getValue() == 1) 1407 return DAG.getConstant(0, N0.getValueType()); 1408 // fold (mulhu x, undef) -> 0 1409 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1410 return DAG.getConstant(0, VT); 1411 1412 return SDOperand(); 1413} 1414 1415/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1416/// compute two values. LoOp and HiOp give the opcodes for the two computations 1417/// that are being performed. Return true if a simplification was made. 1418/// 1419bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, 1420 unsigned LoOp, unsigned HiOp) { 1421 // If the high half is not needed, just compute the low half. 1422 if (!N->hasAnyUseOfValue(1) && 1423 (!AfterLegalize || 1424 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1425 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), 1426 DAG.getNode(LoOp, N->getValueType(0), 1427 N->op_begin(), 1428 N->getNumOperands())); 1429 return true; 1430 } 1431 1432 // If the low half is not needed, just compute the high half. 1433 if (!N->hasAnyUseOfValue(0) && 1434 (!AfterLegalize || 1435 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1436 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 1437 DAG.getNode(HiOp, N->getValueType(1), 1438 N->op_begin(), 1439 N->getNumOperands())); 1440 return true; 1441 } 1442 1443 // If the two computed results can be siplified separately, separate them. 1444 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1445 N->op_begin(), N->getNumOperands()); 1446 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1447 N->op_begin(), N->getNumOperands()); 1448 unsigned LoExists = !Lo.use_empty(); 1449 unsigned HiExists = !Hi.use_empty(); 1450 SDOperand LoOpt = Lo; 1451 SDOperand HiOpt = Hi; 1452 if (!LoExists || !HiExists) { 1453 SDOperand Pair = DAG.getNode(ISD::BUILD_PAIR, MVT::Other, Lo, Hi); 1454 assert(Pair.use_empty() && "Pair with type MVT::Other already exists!"); 1455 LoOpt = combine(Lo.Val); 1456 HiOpt = combine(Hi.Val); 1457 if (!LoOpt.Val) 1458 LoOpt = Pair.getOperand(0); 1459 if (!HiOpt.Val) 1460 HiOpt = Pair.getOperand(1); 1461 DAG.DeleteNode(Pair.Val); 1462 } 1463 if ((LoExists || LoOpt != Lo) && 1464 (HiExists || HiOpt != Hi) && 1465 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()) && 1466 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) { 1467 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt); 1468 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt); 1469 return true; 1470 } 1471 1472 return false; 1473} 1474 1475SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1476 1477 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS)) 1478 return SDOperand(); 1479 1480 return SDOperand(); 1481} 1482 1483SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1484 1485 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU)) 1486 return SDOperand(); 1487 1488 return SDOperand(); 1489} 1490 1491SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1492 1493 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM)) 1494 return SDOperand(); 1495 1496 return SDOperand(); 1497} 1498 1499SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1500 1501 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM)) 1502 return SDOperand(); 1503 1504 return SDOperand(); 1505} 1506 1507/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1508/// two operands of the same opcode, try to simplify it. 1509SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1510 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1511 MVT::ValueType VT = N0.getValueType(); 1512 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1513 1514 // For each of OP in AND/OR/XOR: 1515 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1516 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1517 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1518 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1519 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1520 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1521 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1522 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1523 N0.getOperand(0).getValueType(), 1524 N0.getOperand(0), N1.getOperand(0)); 1525 AddToWorkList(ORNode.Val); 1526 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1527 } 1528 1529 // For each of OP in SHL/SRL/SRA/AND... 1530 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1531 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1532 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1533 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1534 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1535 N0.getOperand(1) == N1.getOperand(1)) { 1536 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1537 N0.getOperand(0).getValueType(), 1538 N0.getOperand(0), N1.getOperand(0)); 1539 AddToWorkList(ORNode.Val); 1540 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1541 } 1542 1543 return SDOperand(); 1544} 1545 1546SDOperand DAGCombiner::visitAND(SDNode *N) { 1547 SDOperand N0 = N->getOperand(0); 1548 SDOperand N1 = N->getOperand(1); 1549 SDOperand LL, LR, RL, RR, CC0, CC1; 1550 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1551 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1552 MVT::ValueType VT = N1.getValueType(); 1553 1554 // fold vector ops 1555 if (MVT::isVector(VT)) { 1556 SDOperand FoldedVOp = SimplifyVBinOp(N); 1557 if (FoldedVOp.Val) return FoldedVOp; 1558 } 1559 1560 // fold (and x, undef) -> 0 1561 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1562 return DAG.getConstant(0, VT); 1563 // fold (and c1, c2) -> c1&c2 1564 if (N0C && N1C) 1565 return DAG.getNode(ISD::AND, VT, N0, N1); 1566 // canonicalize constant to RHS 1567 if (N0C && !N1C) 1568 return DAG.getNode(ISD::AND, VT, N1, N0); 1569 // fold (and x, -1) -> x 1570 if (N1C && N1C->isAllOnesValue()) 1571 return N0; 1572 // if (and x, c) is known to be zero, return 0 1573 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1574 return DAG.getConstant(0, VT); 1575 // reassociate and 1576 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1577 if (RAND.Val != 0) 1578 return RAND; 1579 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1580 if (N1C && N0.getOpcode() == ISD::OR) 1581 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1582 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1583 return N1; 1584 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1585 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1586 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1587 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1588 ~N1C->getValue() & InMask)) { 1589 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1590 N0.getOperand(0)); 1591 1592 // Replace uses of the AND with uses of the Zero extend node. 1593 CombineTo(N, Zext); 1594 1595 // We actually want to replace all uses of the any_extend with the 1596 // zero_extend, to avoid duplicating things. This will later cause this 1597 // AND to be folded. 1598 CombineTo(N0.Val, Zext); 1599 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1600 } 1601 } 1602 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1603 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1604 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1605 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1606 1607 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1608 MVT::isInteger(LL.getValueType())) { 1609 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1610 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1611 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1612 AddToWorkList(ORNode.Val); 1613 return DAG.getSetCC(VT, ORNode, LR, Op1); 1614 } 1615 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1616 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1617 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1618 AddToWorkList(ANDNode.Val); 1619 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1620 } 1621 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1622 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1623 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1624 AddToWorkList(ORNode.Val); 1625 return DAG.getSetCC(VT, ORNode, LR, Op1); 1626 } 1627 } 1628 // canonicalize equivalent to ll == rl 1629 if (LL == RR && LR == RL) { 1630 Op1 = ISD::getSetCCSwappedOperands(Op1); 1631 std::swap(RL, RR); 1632 } 1633 if (LL == RL && LR == RR) { 1634 bool isInteger = MVT::isInteger(LL.getValueType()); 1635 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1636 if (Result != ISD::SETCC_INVALID) 1637 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1638 } 1639 } 1640 1641 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1642 if (N0.getOpcode() == N1.getOpcode()) { 1643 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1644 if (Tmp.Val) return Tmp; 1645 } 1646 1647 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1648 // fold (and (sra)) -> (and (srl)) when possible. 1649 if (!MVT::isVector(VT) && 1650 SimplifyDemandedBits(SDOperand(N, 0))) 1651 return SDOperand(N, 0); 1652 // fold (zext_inreg (extload x)) -> (zextload x) 1653 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1654 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1655 MVT::ValueType EVT = LN0->getLoadedVT(); 1656 // If we zero all the possible extended bits, then we can turn this into 1657 // a zextload if we are running before legalize or the operation is legal. 1658 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1659 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1660 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1661 LN0->getBasePtr(), LN0->getSrcValue(), 1662 LN0->getSrcValueOffset(), EVT, 1663 LN0->isVolatile(), 1664 LN0->getAlignment()); 1665 AddToWorkList(N); 1666 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1667 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1668 } 1669 } 1670 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1671 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1672 N0.hasOneUse()) { 1673 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1674 MVT::ValueType EVT = LN0->getLoadedVT(); 1675 // If we zero all the possible extended bits, then we can turn this into 1676 // a zextload if we are running before legalize or the operation is legal. 1677 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1678 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1679 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1680 LN0->getBasePtr(), LN0->getSrcValue(), 1681 LN0->getSrcValueOffset(), EVT, 1682 LN0->isVolatile(), 1683 LN0->getAlignment()); 1684 AddToWorkList(N); 1685 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1686 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1687 } 1688 } 1689 1690 // fold (and (load x), 255) -> (zextload x, i8) 1691 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1692 if (N1C && N0.getOpcode() == ISD::LOAD) { 1693 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1694 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1695 LN0->getAddressingMode() == ISD::UNINDEXED && 1696 N0.hasOneUse()) { 1697 MVT::ValueType EVT, LoadedVT; 1698 if (N1C->getValue() == 255) 1699 EVT = MVT::i8; 1700 else if (N1C->getValue() == 65535) 1701 EVT = MVT::i16; 1702 else if (N1C->getValue() == ~0U) 1703 EVT = MVT::i32; 1704 else 1705 EVT = MVT::Other; 1706 1707 LoadedVT = LN0->getLoadedVT(); 1708 if (EVT != MVT::Other && LoadedVT > EVT && 1709 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1710 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1711 // For big endian targets, we need to add an offset to the pointer to 1712 // load the correct bytes. For little endian systems, we merely need to 1713 // read fewer bytes from the same pointer. 1714 unsigned PtrOff = 1715 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1716 SDOperand NewPtr = LN0->getBasePtr(); 1717 if (!TLI.isLittleEndian()) 1718 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1719 DAG.getConstant(PtrOff, PtrType)); 1720 AddToWorkList(NewPtr.Val); 1721 SDOperand Load = 1722 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1723 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1724 LN0->isVolatile(), LN0->getAlignment()); 1725 AddToWorkList(N); 1726 CombineTo(N0.Val, Load, Load.getValue(1)); 1727 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1728 } 1729 } 1730 } 1731 1732 return SDOperand(); 1733} 1734 1735SDOperand DAGCombiner::visitOR(SDNode *N) { 1736 SDOperand N0 = N->getOperand(0); 1737 SDOperand N1 = N->getOperand(1); 1738 SDOperand LL, LR, RL, RR, CC0, CC1; 1739 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1740 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1741 MVT::ValueType VT = N1.getValueType(); 1742 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1743 1744 // fold vector ops 1745 if (MVT::isVector(VT)) { 1746 SDOperand FoldedVOp = SimplifyVBinOp(N); 1747 if (FoldedVOp.Val) return FoldedVOp; 1748 } 1749 1750 // fold (or x, undef) -> -1 1751 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1752 return DAG.getConstant(~0ULL, VT); 1753 // fold (or c1, c2) -> c1|c2 1754 if (N0C && N1C) 1755 return DAG.getNode(ISD::OR, VT, N0, N1); 1756 // canonicalize constant to RHS 1757 if (N0C && !N1C) 1758 return DAG.getNode(ISD::OR, VT, N1, N0); 1759 // fold (or x, 0) -> x 1760 if (N1C && N1C->isNullValue()) 1761 return N0; 1762 // fold (or x, -1) -> -1 1763 if (N1C && N1C->isAllOnesValue()) 1764 return N1; 1765 // fold (or x, c) -> c iff (x & ~c) == 0 1766 if (N1C && 1767 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1768 return N1; 1769 // reassociate or 1770 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1771 if (ROR.Val != 0) 1772 return ROR; 1773 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1774 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1775 isa<ConstantSDNode>(N0.getOperand(1))) { 1776 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1777 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1778 N1), 1779 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1780 } 1781 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1782 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1783 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1784 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1785 1786 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1787 MVT::isInteger(LL.getValueType())) { 1788 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1789 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1790 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1791 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1792 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1793 AddToWorkList(ORNode.Val); 1794 return DAG.getSetCC(VT, ORNode, LR, Op1); 1795 } 1796 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1797 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1798 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1799 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1800 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1801 AddToWorkList(ANDNode.Val); 1802 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1803 } 1804 } 1805 // canonicalize equivalent to ll == rl 1806 if (LL == RR && LR == RL) { 1807 Op1 = ISD::getSetCCSwappedOperands(Op1); 1808 std::swap(RL, RR); 1809 } 1810 if (LL == RL && LR == RR) { 1811 bool isInteger = MVT::isInteger(LL.getValueType()); 1812 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1813 if (Result != ISD::SETCC_INVALID) 1814 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1815 } 1816 } 1817 1818 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1819 if (N0.getOpcode() == N1.getOpcode()) { 1820 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1821 if (Tmp.Val) return Tmp; 1822 } 1823 1824 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1825 if (N0.getOpcode() == ISD::AND && 1826 N1.getOpcode() == ISD::AND && 1827 N0.getOperand(1).getOpcode() == ISD::Constant && 1828 N1.getOperand(1).getOpcode() == ISD::Constant && 1829 // Don't increase # computations. 1830 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1831 // We can only do this xform if we know that bits from X that are set in C2 1832 // but not in C1 are already zero. Likewise for Y. 1833 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1834 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1835 1836 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1837 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1838 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1839 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1840 } 1841 } 1842 1843 1844 // See if this is some rotate idiom. 1845 if (SDNode *Rot = MatchRotate(N0, N1)) 1846 return SDOperand(Rot, 0); 1847 1848 return SDOperand(); 1849} 1850 1851 1852/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1853static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1854 if (Op.getOpcode() == ISD::AND) { 1855 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1856 Mask = Op.getOperand(1); 1857 Op = Op.getOperand(0); 1858 } else { 1859 return false; 1860 } 1861 } 1862 1863 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1864 Shift = Op; 1865 return true; 1866 } 1867 return false; 1868} 1869 1870 1871// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1872// idioms for rotate, and if the target supports rotation instructions, generate 1873// a rot[lr]. 1874SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1875 // Must be a legal type. Expanded an promoted things won't work with rotates. 1876 MVT::ValueType VT = LHS.getValueType(); 1877 if (!TLI.isTypeLegal(VT)) return 0; 1878 1879 // The target must have at least one rotate flavor. 1880 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1881 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1882 if (!HasROTL && !HasROTR) return 0; 1883 1884 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1885 SDOperand LHSShift; // The shift. 1886 SDOperand LHSMask; // AND value if any. 1887 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1888 return 0; // Not part of a rotate. 1889 1890 SDOperand RHSShift; // The shift. 1891 SDOperand RHSMask; // AND value if any. 1892 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1893 return 0; // Not part of a rotate. 1894 1895 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1896 return 0; // Not shifting the same value. 1897 1898 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1899 return 0; // Shifts must disagree. 1900 1901 // Canonicalize shl to left side in a shl/srl pair. 1902 if (RHSShift.getOpcode() == ISD::SHL) { 1903 std::swap(LHS, RHS); 1904 std::swap(LHSShift, RHSShift); 1905 std::swap(LHSMask , RHSMask ); 1906 } 1907 1908 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1909 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1910 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1911 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1912 1913 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1914 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1915 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1916 RHSShiftAmt.getOpcode() == ISD::Constant) { 1917 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1918 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1919 if ((LShVal + RShVal) != OpSizeInBits) 1920 return 0; 1921 1922 SDOperand Rot; 1923 if (HasROTL) 1924 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1925 else 1926 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1927 1928 // If there is an AND of either shifted operand, apply it to the result. 1929 if (LHSMask.Val || RHSMask.Val) { 1930 uint64_t Mask = MVT::getIntVTBitMask(VT); 1931 1932 if (LHSMask.Val) { 1933 uint64_t RHSBits = (1ULL << LShVal)-1; 1934 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1935 } 1936 if (RHSMask.Val) { 1937 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1938 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1939 } 1940 1941 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1942 } 1943 1944 return Rot.Val; 1945 } 1946 1947 // If there is a mask here, and we have a variable shift, we can't be sure 1948 // that we're masking out the right stuff. 1949 if (LHSMask.Val || RHSMask.Val) 1950 return 0; 1951 1952 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1953 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1954 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1955 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1956 if (ConstantSDNode *SUBC = 1957 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1958 if (SUBC->getValue() == OpSizeInBits) 1959 if (HasROTL) 1960 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1961 else 1962 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1963 } 1964 } 1965 1966 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1967 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1968 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1969 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1970 if (ConstantSDNode *SUBC = 1971 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1972 if (SUBC->getValue() == OpSizeInBits) 1973 if (HasROTL) 1974 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1975 else 1976 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1977 } 1978 } 1979 1980 // Look for sign/zext/any-extended cases: 1981 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1982 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1983 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1984 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1985 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1986 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1987 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1988 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1989 if (RExtOp0.getOpcode() == ISD::SUB && 1990 RExtOp0.getOperand(1) == LExtOp0) { 1991 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1992 // (rotr x, y) 1993 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1994 // (rotl x, (sub 32, y)) 1995 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1996 if (SUBC->getValue() == OpSizeInBits) { 1997 if (HasROTL) 1998 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1999 else 2000 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2001 } 2002 } 2003 } else if (LExtOp0.getOpcode() == ISD::SUB && 2004 RExtOp0 == LExtOp0.getOperand(1)) { 2005 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2006 // (rotl x, y) 2007 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2008 // (rotr x, (sub 32, y)) 2009 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2010 if (SUBC->getValue() == OpSizeInBits) { 2011 if (HasROTL) 2012 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2013 else 2014 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2015 } 2016 } 2017 } 2018 } 2019 2020 return 0; 2021} 2022 2023 2024SDOperand DAGCombiner::visitXOR(SDNode *N) { 2025 SDOperand N0 = N->getOperand(0); 2026 SDOperand N1 = N->getOperand(1); 2027 SDOperand LHS, RHS, CC; 2028 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2029 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2030 MVT::ValueType VT = N0.getValueType(); 2031 2032 // fold vector ops 2033 if (MVT::isVector(VT)) { 2034 SDOperand FoldedVOp = SimplifyVBinOp(N); 2035 if (FoldedVOp.Val) return FoldedVOp; 2036 } 2037 2038 // fold (xor x, undef) -> undef 2039 if (N0.getOpcode() == ISD::UNDEF) 2040 return N0; 2041 if (N1.getOpcode() == ISD::UNDEF) 2042 return N1; 2043 // fold (xor c1, c2) -> c1^c2 2044 if (N0C && N1C) 2045 return DAG.getNode(ISD::XOR, VT, N0, N1); 2046 // canonicalize constant to RHS 2047 if (N0C && !N1C) 2048 return DAG.getNode(ISD::XOR, VT, N1, N0); 2049 // fold (xor x, 0) -> x 2050 if (N1C && N1C->isNullValue()) 2051 return N0; 2052 // reassociate xor 2053 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2054 if (RXOR.Val != 0) 2055 return RXOR; 2056 // fold !(x cc y) -> (x !cc y) 2057 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2058 bool isInt = MVT::isInteger(LHS.getValueType()); 2059 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2060 isInt); 2061 if (N0.getOpcode() == ISD::SETCC) 2062 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2063 if (N0.getOpcode() == ISD::SELECT_CC) 2064 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2065 assert(0 && "Unhandled SetCC Equivalent!"); 2066 abort(); 2067 } 2068 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2069 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2070 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2071 SDOperand V = N0.getOperand(0); 2072 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2073 DAG.getConstant(1, V.getValueType())); 2074 AddToWorkList(V.Val); 2075 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2076 } 2077 2078 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2079 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2080 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2081 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2082 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2083 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2084 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2085 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2086 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2087 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2088 } 2089 } 2090 // fold !(x or y) -> (!x and !y) iff x or y are constants 2091 if (N1C && N1C->isAllOnesValue() && 2092 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2093 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2094 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2095 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2096 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2097 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2098 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2099 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2100 } 2101 } 2102 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2103 if (N1C && N0.getOpcode() == ISD::XOR) { 2104 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2105 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2106 if (N00C) 2107 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2108 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2109 if (N01C) 2110 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2111 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2112 } 2113 // fold (xor x, x) -> 0 2114 if (N0 == N1) { 2115 if (!MVT::isVector(VT)) { 2116 return DAG.getConstant(0, VT); 2117 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2118 // Produce a vector of zeros. 2119 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2120 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2121 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2122 } 2123 } 2124 2125 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2126 if (N0.getOpcode() == N1.getOpcode()) { 2127 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2128 if (Tmp.Val) return Tmp; 2129 } 2130 2131 // Simplify the expression using non-local knowledge. 2132 if (!MVT::isVector(VT) && 2133 SimplifyDemandedBits(SDOperand(N, 0))) 2134 return SDOperand(N, 0); 2135 2136 return SDOperand(); 2137} 2138 2139SDOperand DAGCombiner::visitSHL(SDNode *N) { 2140 SDOperand N0 = N->getOperand(0); 2141 SDOperand N1 = N->getOperand(1); 2142 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2143 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2144 MVT::ValueType VT = N0.getValueType(); 2145 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2146 2147 // fold (shl c1, c2) -> c1<<c2 2148 if (N0C && N1C) 2149 return DAG.getNode(ISD::SHL, VT, N0, N1); 2150 // fold (shl 0, x) -> 0 2151 if (N0C && N0C->isNullValue()) 2152 return N0; 2153 // fold (shl x, c >= size(x)) -> undef 2154 if (N1C && N1C->getValue() >= OpSizeInBits) 2155 return DAG.getNode(ISD::UNDEF, VT); 2156 // fold (shl x, 0) -> x 2157 if (N1C && N1C->isNullValue()) 2158 return N0; 2159 // if (shl x, c) is known to be zero, return 0 2160 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2161 return DAG.getConstant(0, VT); 2162 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2163 return SDOperand(N, 0); 2164 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2165 if (N1C && N0.getOpcode() == ISD::SHL && 2166 N0.getOperand(1).getOpcode() == ISD::Constant) { 2167 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2168 uint64_t c2 = N1C->getValue(); 2169 if (c1 + c2 > OpSizeInBits) 2170 return DAG.getConstant(0, VT); 2171 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2172 DAG.getConstant(c1 + c2, N1.getValueType())); 2173 } 2174 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2175 // (srl (and x, -1 << c1), c1-c2) 2176 if (N1C && N0.getOpcode() == ISD::SRL && 2177 N0.getOperand(1).getOpcode() == ISD::Constant) { 2178 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2179 uint64_t c2 = N1C->getValue(); 2180 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2181 DAG.getConstant(~0ULL << c1, VT)); 2182 if (c2 > c1) 2183 return DAG.getNode(ISD::SHL, VT, Mask, 2184 DAG.getConstant(c2-c1, N1.getValueType())); 2185 else 2186 return DAG.getNode(ISD::SRL, VT, Mask, 2187 DAG.getConstant(c1-c2, N1.getValueType())); 2188 } 2189 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2190 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2191 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2192 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2193 return SDOperand(); 2194} 2195 2196SDOperand DAGCombiner::visitSRA(SDNode *N) { 2197 SDOperand N0 = N->getOperand(0); 2198 SDOperand N1 = N->getOperand(1); 2199 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2200 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2201 MVT::ValueType VT = N0.getValueType(); 2202 2203 // fold (sra c1, c2) -> c1>>c2 2204 if (N0C && N1C) 2205 return DAG.getNode(ISD::SRA, VT, N0, N1); 2206 // fold (sra 0, x) -> 0 2207 if (N0C && N0C->isNullValue()) 2208 return N0; 2209 // fold (sra -1, x) -> -1 2210 if (N0C && N0C->isAllOnesValue()) 2211 return N0; 2212 // fold (sra x, c >= size(x)) -> undef 2213 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2214 return DAG.getNode(ISD::UNDEF, VT); 2215 // fold (sra x, 0) -> x 2216 if (N1C && N1C->isNullValue()) 2217 return N0; 2218 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2219 // sext_inreg. 2220 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2221 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2222 MVT::ValueType EVT; 2223 switch (LowBits) { 2224 default: EVT = MVT::Other; break; 2225 case 1: EVT = MVT::i1; break; 2226 case 8: EVT = MVT::i8; break; 2227 case 16: EVT = MVT::i16; break; 2228 case 32: EVT = MVT::i32; break; 2229 } 2230 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2231 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2232 DAG.getValueType(EVT)); 2233 } 2234 2235 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2236 if (N1C && N0.getOpcode() == ISD::SRA) { 2237 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2238 unsigned Sum = N1C->getValue() + C1->getValue(); 2239 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2240 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2241 DAG.getConstant(Sum, N1C->getValueType(0))); 2242 } 2243 } 2244 2245 // Simplify, based on bits shifted out of the LHS. 2246 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2247 return SDOperand(N, 0); 2248 2249 2250 // If the sign bit is known to be zero, switch this to a SRL. 2251 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2252 return DAG.getNode(ISD::SRL, VT, N0, N1); 2253 return SDOperand(); 2254} 2255 2256SDOperand DAGCombiner::visitSRL(SDNode *N) { 2257 SDOperand N0 = N->getOperand(0); 2258 SDOperand N1 = N->getOperand(1); 2259 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2260 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2261 MVT::ValueType VT = N0.getValueType(); 2262 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2263 2264 // fold (srl c1, c2) -> c1 >>u c2 2265 if (N0C && N1C) 2266 return DAG.getNode(ISD::SRL, VT, N0, N1); 2267 // fold (srl 0, x) -> 0 2268 if (N0C && N0C->isNullValue()) 2269 return N0; 2270 // fold (srl x, c >= size(x)) -> undef 2271 if (N1C && N1C->getValue() >= OpSizeInBits) 2272 return DAG.getNode(ISD::UNDEF, VT); 2273 // fold (srl x, 0) -> x 2274 if (N1C && N1C->isNullValue()) 2275 return N0; 2276 // if (srl x, c) is known to be zero, return 0 2277 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2278 return DAG.getConstant(0, VT); 2279 2280 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2281 if (N1C && N0.getOpcode() == ISD::SRL && 2282 N0.getOperand(1).getOpcode() == ISD::Constant) { 2283 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2284 uint64_t c2 = N1C->getValue(); 2285 if (c1 + c2 > OpSizeInBits) 2286 return DAG.getConstant(0, VT); 2287 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2288 DAG.getConstant(c1 + c2, N1.getValueType())); 2289 } 2290 2291 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2292 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2293 // Shifting in all undef bits? 2294 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2295 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2296 return DAG.getNode(ISD::UNDEF, VT); 2297 2298 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2299 AddToWorkList(SmallShift.Val); 2300 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2301 } 2302 2303 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2304 // bit, which is unmodified by sra. 2305 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2306 if (N0.getOpcode() == ISD::SRA) 2307 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2308 } 2309 2310 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2311 if (N1C && N0.getOpcode() == ISD::CTLZ && 2312 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2313 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2314 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2315 2316 // If any of the input bits are KnownOne, then the input couldn't be all 2317 // zeros, thus the result of the srl will always be zero. 2318 if (KnownOne) return DAG.getConstant(0, VT); 2319 2320 // If all of the bits input the to ctlz node are known to be zero, then 2321 // the result of the ctlz is "32" and the result of the shift is one. 2322 uint64_t UnknownBits = ~KnownZero & Mask; 2323 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2324 2325 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2326 if ((UnknownBits & (UnknownBits-1)) == 0) { 2327 // Okay, we know that only that the single bit specified by UnknownBits 2328 // could be set on input to the CTLZ node. If this bit is set, the SRL 2329 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2330 // to an SRL,XOR pair, which is likely to simplify more. 2331 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2332 SDOperand Op = N0.getOperand(0); 2333 if (ShAmt) { 2334 Op = DAG.getNode(ISD::SRL, VT, Op, 2335 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2336 AddToWorkList(Op.Val); 2337 } 2338 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2339 } 2340 } 2341 2342 // fold operands of srl based on knowledge that the low bits are not 2343 // demanded. 2344 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2345 return SDOperand(N, 0); 2346 2347 return SDOperand(); 2348} 2349 2350SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2351 SDOperand N0 = N->getOperand(0); 2352 MVT::ValueType VT = N->getValueType(0); 2353 2354 // fold (ctlz c1) -> c2 2355 if (isa<ConstantSDNode>(N0)) 2356 return DAG.getNode(ISD::CTLZ, VT, N0); 2357 return SDOperand(); 2358} 2359 2360SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2361 SDOperand N0 = N->getOperand(0); 2362 MVT::ValueType VT = N->getValueType(0); 2363 2364 // fold (cttz c1) -> c2 2365 if (isa<ConstantSDNode>(N0)) 2366 return DAG.getNode(ISD::CTTZ, VT, N0); 2367 return SDOperand(); 2368} 2369 2370SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2371 SDOperand N0 = N->getOperand(0); 2372 MVT::ValueType VT = N->getValueType(0); 2373 2374 // fold (ctpop c1) -> c2 2375 if (isa<ConstantSDNode>(N0)) 2376 return DAG.getNode(ISD::CTPOP, VT, N0); 2377 return SDOperand(); 2378} 2379 2380SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2381 SDOperand N0 = N->getOperand(0); 2382 SDOperand N1 = N->getOperand(1); 2383 SDOperand N2 = N->getOperand(2); 2384 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2385 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2386 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2387 MVT::ValueType VT = N->getValueType(0); 2388 MVT::ValueType VT0 = N0.getValueType(); 2389 2390 // fold select C, X, X -> X 2391 if (N1 == N2) 2392 return N1; 2393 // fold select true, X, Y -> X 2394 if (N0C && !N0C->isNullValue()) 2395 return N1; 2396 // fold select false, X, Y -> Y 2397 if (N0C && N0C->isNullValue()) 2398 return N2; 2399 // fold select C, 1, X -> C | X 2400 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2401 return DAG.getNode(ISD::OR, VT, N0, N2); 2402 // fold select C, 0, 1 -> ~C 2403 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2404 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2405 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2406 if (VT == VT0) 2407 return XORNode; 2408 AddToWorkList(XORNode.Val); 2409 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2410 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2411 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2412 } 2413 // fold select C, 0, X -> ~C & X 2414 if (VT == VT0 && N1C && N1C->isNullValue()) { 2415 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2416 AddToWorkList(XORNode.Val); 2417 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2418 } 2419 // fold select C, X, 1 -> ~C | X 2420 if (VT == VT0 && N2C && N2C->getValue() == 1) { 2421 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2422 AddToWorkList(XORNode.Val); 2423 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2424 } 2425 // fold select C, X, 0 -> C & X 2426 // FIXME: this should check for C type == X type, not i1? 2427 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2428 return DAG.getNode(ISD::AND, VT, N0, N1); 2429 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2430 if (MVT::i1 == VT && N0 == N1) 2431 return DAG.getNode(ISD::OR, VT, N0, N2); 2432 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2433 if (MVT::i1 == VT && N0 == N2) 2434 return DAG.getNode(ISD::AND, VT, N0, N1); 2435 2436 // If we can fold this based on the true/false value, do so. 2437 if (SimplifySelectOps(N, N1, N2)) 2438 return SDOperand(N, 0); // Don't revisit N. 2439 2440 // fold selects based on a setcc into other things, such as min/max/abs 2441 if (N0.getOpcode() == ISD::SETCC) 2442 // FIXME: 2443 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2444 // having to say they don't support SELECT_CC on every type the DAG knows 2445 // about, since there is no way to mark an opcode illegal at all value types 2446 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2447 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2448 N1, N2, N0.getOperand(2)); 2449 else 2450 return SimplifySelect(N0, N1, N2); 2451 return SDOperand(); 2452} 2453 2454SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2455 SDOperand N0 = N->getOperand(0); 2456 SDOperand N1 = N->getOperand(1); 2457 SDOperand N2 = N->getOperand(2); 2458 SDOperand N3 = N->getOperand(3); 2459 SDOperand N4 = N->getOperand(4); 2460 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2461 2462 // fold select_cc lhs, rhs, x, x, cc -> x 2463 if (N2 == N3) 2464 return N2; 2465 2466 // Determine if the condition we're dealing with is constant 2467 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2468 if (SCC.Val) AddToWorkList(SCC.Val); 2469 2470 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2471 if (SCCC->getValue()) 2472 return N2; // cond always true -> true val 2473 else 2474 return N3; // cond always false -> false val 2475 } 2476 2477 // Fold to a simpler select_cc 2478 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2479 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2480 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2481 SCC.getOperand(2)); 2482 2483 // If we can fold this based on the true/false value, do so. 2484 if (SimplifySelectOps(N, N2, N3)) 2485 return SDOperand(N, 0); // Don't revisit N. 2486 2487 // fold select_cc into other things, such as min/max/abs 2488 return SimplifySelectCC(N0, N1, N2, N3, CC); 2489} 2490 2491SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2492 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2493 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2494} 2495 2496SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2497 SDOperand N0 = N->getOperand(0); 2498 MVT::ValueType VT = N->getValueType(0); 2499 2500 // fold (sext c1) -> c1 2501 if (isa<ConstantSDNode>(N0)) 2502 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2503 2504 // fold (sext (sext x)) -> (sext x) 2505 // fold (sext (aext x)) -> (sext x) 2506 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2507 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2508 2509 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2510 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2511 if (N0.getOpcode() == ISD::TRUNCATE) { 2512 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2513 if (NarrowLoad.Val) { 2514 if (NarrowLoad.Val != N0.Val) 2515 CombineTo(N0.Val, NarrowLoad); 2516 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2517 } 2518 } 2519 2520 // See if the value being truncated is already sign extended. If so, just 2521 // eliminate the trunc/sext pair. 2522 if (N0.getOpcode() == ISD::TRUNCATE) { 2523 SDOperand Op = N0.getOperand(0); 2524 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2525 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2526 unsigned DestBits = MVT::getSizeInBits(VT); 2527 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2528 2529 if (OpBits == DestBits) { 2530 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2531 // bits, it is already ready. 2532 if (NumSignBits > DestBits-MidBits) 2533 return Op; 2534 } else if (OpBits < DestBits) { 2535 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2536 // bits, just sext from i32. 2537 if (NumSignBits > OpBits-MidBits) 2538 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2539 } else { 2540 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2541 // bits, just truncate to i32. 2542 if (NumSignBits > OpBits-MidBits) 2543 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2544 } 2545 2546 // fold (sext (truncate x)) -> (sextinreg x). 2547 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2548 N0.getValueType())) { 2549 if (Op.getValueType() < VT) 2550 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2551 else if (Op.getValueType() > VT) 2552 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2553 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2554 DAG.getValueType(N0.getValueType())); 2555 } 2556 } 2557 2558 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2559 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2560 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2561 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2562 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2563 LN0->getBasePtr(), LN0->getSrcValue(), 2564 LN0->getSrcValueOffset(), 2565 N0.getValueType(), 2566 LN0->isVolatile(), 2567 LN0->getAlignment()); 2568 CombineTo(N, ExtLoad); 2569 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2570 ExtLoad.getValue(1)); 2571 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2572 } 2573 2574 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2575 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2576 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2577 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2578 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2579 MVT::ValueType EVT = LN0->getLoadedVT(); 2580 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2581 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2582 LN0->getBasePtr(), LN0->getSrcValue(), 2583 LN0->getSrcValueOffset(), EVT, 2584 LN0->isVolatile(), 2585 LN0->getAlignment()); 2586 CombineTo(N, ExtLoad); 2587 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2588 ExtLoad.getValue(1)); 2589 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2590 } 2591 } 2592 2593 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2594 if (N0.getOpcode() == ISD::SETCC) { 2595 SDOperand SCC = 2596 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2597 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2598 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2599 if (SCC.Val) return SCC; 2600 } 2601 2602 return SDOperand(); 2603} 2604 2605SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2606 SDOperand N0 = N->getOperand(0); 2607 MVT::ValueType VT = N->getValueType(0); 2608 2609 // fold (zext c1) -> c1 2610 if (isa<ConstantSDNode>(N0)) 2611 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2612 // fold (zext (zext x)) -> (zext x) 2613 // fold (zext (aext x)) -> (zext x) 2614 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2615 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2616 2617 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2618 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2619 if (N0.getOpcode() == ISD::TRUNCATE) { 2620 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2621 if (NarrowLoad.Val) { 2622 if (NarrowLoad.Val != N0.Val) 2623 CombineTo(N0.Val, NarrowLoad); 2624 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2625 } 2626 } 2627 2628 // fold (zext (truncate x)) -> (and x, mask) 2629 if (N0.getOpcode() == ISD::TRUNCATE && 2630 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2631 SDOperand Op = N0.getOperand(0); 2632 if (Op.getValueType() < VT) { 2633 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2634 } else if (Op.getValueType() > VT) { 2635 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2636 } 2637 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2638 } 2639 2640 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2641 if (N0.getOpcode() == ISD::AND && 2642 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2643 N0.getOperand(1).getOpcode() == ISD::Constant) { 2644 SDOperand X = N0.getOperand(0).getOperand(0); 2645 if (X.getValueType() < VT) { 2646 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2647 } else if (X.getValueType() > VT) { 2648 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2649 } 2650 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2651 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2652 } 2653 2654 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2655 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2656 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2657 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2658 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2659 LN0->getBasePtr(), LN0->getSrcValue(), 2660 LN0->getSrcValueOffset(), 2661 N0.getValueType(), 2662 LN0->isVolatile(), 2663 LN0->getAlignment()); 2664 CombineTo(N, ExtLoad); 2665 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2666 ExtLoad.getValue(1)); 2667 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2668 } 2669 2670 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2671 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2672 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2673 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2674 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2675 MVT::ValueType EVT = LN0->getLoadedVT(); 2676 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2677 LN0->getBasePtr(), LN0->getSrcValue(), 2678 LN0->getSrcValueOffset(), EVT, 2679 LN0->isVolatile(), 2680 LN0->getAlignment()); 2681 CombineTo(N, ExtLoad); 2682 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2683 ExtLoad.getValue(1)); 2684 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2685 } 2686 2687 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2688 if (N0.getOpcode() == ISD::SETCC) { 2689 SDOperand SCC = 2690 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2691 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2692 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2693 if (SCC.Val) return SCC; 2694 } 2695 2696 return SDOperand(); 2697} 2698 2699SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2700 SDOperand N0 = N->getOperand(0); 2701 MVT::ValueType VT = N->getValueType(0); 2702 2703 // fold (aext c1) -> c1 2704 if (isa<ConstantSDNode>(N0)) 2705 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2706 // fold (aext (aext x)) -> (aext x) 2707 // fold (aext (zext x)) -> (zext x) 2708 // fold (aext (sext x)) -> (sext x) 2709 if (N0.getOpcode() == ISD::ANY_EXTEND || 2710 N0.getOpcode() == ISD::ZERO_EXTEND || 2711 N0.getOpcode() == ISD::SIGN_EXTEND) 2712 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2713 2714 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2715 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2716 if (N0.getOpcode() == ISD::TRUNCATE) { 2717 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2718 if (NarrowLoad.Val) { 2719 if (NarrowLoad.Val != N0.Val) 2720 CombineTo(N0.Val, NarrowLoad); 2721 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2722 } 2723 } 2724 2725 // fold (aext (truncate x)) 2726 if (N0.getOpcode() == ISD::TRUNCATE) { 2727 SDOperand TruncOp = N0.getOperand(0); 2728 if (TruncOp.getValueType() == VT) 2729 return TruncOp; // x iff x size == zext size. 2730 if (TruncOp.getValueType() > VT) 2731 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2732 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2733 } 2734 2735 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2736 if (N0.getOpcode() == ISD::AND && 2737 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2738 N0.getOperand(1).getOpcode() == ISD::Constant) { 2739 SDOperand X = N0.getOperand(0).getOperand(0); 2740 if (X.getValueType() < VT) { 2741 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2742 } else if (X.getValueType() > VT) { 2743 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2744 } 2745 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2746 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2747 } 2748 2749 // fold (aext (load x)) -> (aext (truncate (extload x))) 2750 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2751 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2752 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2753 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2754 LN0->getBasePtr(), LN0->getSrcValue(), 2755 LN0->getSrcValueOffset(), 2756 N0.getValueType(), 2757 LN0->isVolatile(), 2758 LN0->getAlignment()); 2759 CombineTo(N, ExtLoad); 2760 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2761 ExtLoad.getValue(1)); 2762 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2763 } 2764 2765 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2766 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2767 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2768 if (N0.getOpcode() == ISD::LOAD && 2769 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2770 N0.hasOneUse()) { 2771 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2772 MVT::ValueType EVT = LN0->getLoadedVT(); 2773 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2774 LN0->getChain(), LN0->getBasePtr(), 2775 LN0->getSrcValue(), 2776 LN0->getSrcValueOffset(), EVT, 2777 LN0->isVolatile(), 2778 LN0->getAlignment()); 2779 CombineTo(N, ExtLoad); 2780 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2781 ExtLoad.getValue(1)); 2782 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2783 } 2784 2785 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2786 if (N0.getOpcode() == ISD::SETCC) { 2787 SDOperand SCC = 2788 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2789 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2790 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2791 if (SCC.Val) 2792 return SCC; 2793 } 2794 2795 return SDOperand(); 2796} 2797 2798/// GetDemandedBits - See if the specified operand can be simplified with the 2799/// knowledge that only the bits specified by Mask are used. If so, return the 2800/// simpler operand, otherwise return a null SDOperand. 2801SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) { 2802 switch (V.getOpcode()) { 2803 default: break; 2804 case ISD::OR: 2805 case ISD::XOR: 2806 // If the LHS or RHS don't contribute bits to the or, drop them. 2807 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 2808 return V.getOperand(1); 2809 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 2810 return V.getOperand(0); 2811 break; 2812 case ISD::SRL: 2813 // Only look at single-use SRLs. 2814 if (!V.Val->hasOneUse()) 2815 break; 2816 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 2817 // See if we can recursively simplify the LHS. 2818 unsigned Amt = RHSC->getValue(); 2819 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType()); 2820 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask); 2821 if (SimplifyLHS.Val) { 2822 return DAG.getNode(ISD::SRL, V.getValueType(), 2823 SimplifyLHS, V.getOperand(1)); 2824 } 2825 } 2826 } 2827 return SDOperand(); 2828} 2829 2830/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2831/// bits and then truncated to a narrower type and where N is a multiple 2832/// of number of bits of the narrower type, transform it to a narrower load 2833/// from address + N / num of bits of new type. If the result is to be 2834/// extended, also fold the extension to form a extending load. 2835SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2836 unsigned Opc = N->getOpcode(); 2837 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2838 SDOperand N0 = N->getOperand(0); 2839 MVT::ValueType VT = N->getValueType(0); 2840 MVT::ValueType EVT = N->getValueType(0); 2841 2842 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2843 // extended to VT. 2844 if (Opc == ISD::SIGN_EXTEND_INREG) { 2845 ExtType = ISD::SEXTLOAD; 2846 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2847 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2848 return SDOperand(); 2849 } 2850 2851 unsigned EVTBits = MVT::getSizeInBits(EVT); 2852 unsigned ShAmt = 0; 2853 bool CombineSRL = false; 2854 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2855 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2856 ShAmt = N01->getValue(); 2857 // Is the shift amount a multiple of size of VT? 2858 if ((ShAmt & (EVTBits-1)) == 0) { 2859 N0 = N0.getOperand(0); 2860 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2861 return SDOperand(); 2862 CombineSRL = true; 2863 } 2864 } 2865 } 2866 2867 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2868 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2869 // zero extended form: by shrinking the load, we lose track of the fact 2870 // that it is already zero extended. 2871 // FIXME: This should be reevaluated. 2872 VT != MVT::i1) { 2873 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 2874 "Cannot truncate to larger type!"); 2875 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2876 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2877 // For big endian targets, we need to adjust the offset to the pointer to 2878 // load the correct bytes. 2879 if (!TLI.isLittleEndian()) 2880 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; 2881 uint64_t PtrOff = ShAmt / 8; 2882 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2883 DAG.getConstant(PtrOff, PtrType)); 2884 AddToWorkList(NewPtr.Val); 2885 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 2886 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 2887 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2888 LN0->isVolatile(), LN0->getAlignment()) 2889 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 2890 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 2891 LN0->isVolatile(), LN0->getAlignment()); 2892 AddToWorkList(N); 2893 if (CombineSRL) { 2894 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 2895 CombineTo(N->getOperand(0).Val, Load); 2896 } else 2897 CombineTo(N0.Val, Load, Load.getValue(1)); 2898 if (ShAmt) { 2899 if (Opc == ISD::SIGN_EXTEND_INREG) 2900 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 2901 else 2902 return DAG.getNode(Opc, VT, Load); 2903 } 2904 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2905 } 2906 2907 return SDOperand(); 2908} 2909 2910 2911SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2912 SDOperand N0 = N->getOperand(0); 2913 SDOperand N1 = N->getOperand(1); 2914 MVT::ValueType VT = N->getValueType(0); 2915 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2916 unsigned EVTBits = MVT::getSizeInBits(EVT); 2917 2918 // fold (sext_in_reg c1) -> c1 2919 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2920 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2921 2922 // If the input is already sign extended, just drop the extension. 2923 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2924 return N0; 2925 2926 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2927 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2928 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2929 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2930 } 2931 2932 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 2933 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2934 return DAG.getZeroExtendInReg(N0, EVT); 2935 2936 // fold operands of sext_in_reg based on knowledge that the top bits are not 2937 // demanded. 2938 if (SimplifyDemandedBits(SDOperand(N, 0))) 2939 return SDOperand(N, 0); 2940 2941 // fold (sext_in_reg (load x)) -> (smaller sextload x) 2942 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 2943 SDOperand NarrowLoad = ReduceLoadWidth(N); 2944 if (NarrowLoad.Val) 2945 return NarrowLoad; 2946 2947 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2948 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2949 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2950 if (N0.getOpcode() == ISD::SRL) { 2951 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2952 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2953 // We can turn this into an SRA iff the input to the SRL is already sign 2954 // extended enough. 2955 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 2956 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2957 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2958 } 2959 } 2960 2961 // fold (sext_inreg (extload x)) -> (sextload x) 2962 if (ISD::isEXTLoad(N0.Val) && 2963 ISD::isUNINDEXEDLoad(N0.Val) && 2964 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2965 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2966 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2967 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2968 LN0->getBasePtr(), LN0->getSrcValue(), 2969 LN0->getSrcValueOffset(), EVT, 2970 LN0->isVolatile(), 2971 LN0->getAlignment()); 2972 CombineTo(N, ExtLoad); 2973 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2974 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2975 } 2976 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2977 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2978 N0.hasOneUse() && 2979 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2980 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2981 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2982 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2983 LN0->getBasePtr(), LN0->getSrcValue(), 2984 LN0->getSrcValueOffset(), EVT, 2985 LN0->isVolatile(), 2986 LN0->getAlignment()); 2987 CombineTo(N, ExtLoad); 2988 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2989 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2990 } 2991 return SDOperand(); 2992} 2993 2994SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2995 SDOperand N0 = N->getOperand(0); 2996 MVT::ValueType VT = N->getValueType(0); 2997 2998 // noop truncate 2999 if (N0.getValueType() == N->getValueType(0)) 3000 return N0; 3001 // fold (truncate c1) -> c1 3002 if (isa<ConstantSDNode>(N0)) 3003 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3004 // fold (truncate (truncate x)) -> (truncate x) 3005 if (N0.getOpcode() == ISD::TRUNCATE) 3006 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3007 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3008 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3009 N0.getOpcode() == ISD::ANY_EXTEND) { 3010 if (N0.getOperand(0).getValueType() < VT) 3011 // if the source is smaller than the dest, we still need an extend 3012 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3013 else if (N0.getOperand(0).getValueType() > VT) 3014 // if the source is larger than the dest, than we just need the truncate 3015 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3016 else 3017 // if the source and dest are the same type, we can drop both the extend 3018 // and the truncate 3019 return N0.getOperand(0); 3020 } 3021 3022 // See if we can simplify the input to this truncate through knowledge that 3023 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3024 // -> trunc y 3025 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT)); 3026 if (Shorter.Val) 3027 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3028 3029 // fold (truncate (load x)) -> (smaller load x) 3030 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3031 return ReduceLoadWidth(N); 3032} 3033 3034SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3035 SDOperand N0 = N->getOperand(0); 3036 MVT::ValueType VT = N->getValueType(0); 3037 3038 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3039 // Only do this before legalize, since afterward the target may be depending 3040 // on the bitconvert. 3041 // First check to see if this is all constant. 3042 if (!AfterLegalize && 3043 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3044 MVT::isVector(VT)) { 3045 bool isSimple = true; 3046 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3047 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3048 N0.getOperand(i).getOpcode() != ISD::Constant && 3049 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3050 isSimple = false; 3051 break; 3052 } 3053 3054 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3055 assert(!MVT::isVector(DestEltVT) && 3056 "Element type of vector ValueType must not be vector!"); 3057 if (isSimple) { 3058 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3059 } 3060 } 3061 3062 // If the input is a constant, let getNode() fold it. 3063 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3064 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3065 if (Res.Val != N) return Res; 3066 } 3067 3068 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3069 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3070 3071 // fold (conv (load x)) -> (load (conv*)x) 3072 // If the resultant load doesn't need a higher alignment than the original! 3073 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3074 TLI.isOperationLegal(ISD::LOAD, VT)) { 3075 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3076 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3077 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3078 unsigned OrigAlign = LN0->getAlignment(); 3079 if (Align <= OrigAlign) { 3080 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3081 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3082 LN0->isVolatile(), Align); 3083 AddToWorkList(N); 3084 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3085 Load.getValue(1)); 3086 return Load; 3087 } 3088 } 3089 3090 return SDOperand(); 3091} 3092 3093/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3094/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3095/// destination element value type. 3096SDOperand DAGCombiner:: 3097ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3098 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3099 3100 // If this is already the right type, we're done. 3101 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3102 3103 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3104 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3105 3106 // If this is a conversion of N elements of one type to N elements of another 3107 // type, convert each element. This handles FP<->INT cases. 3108 if (SrcBitSize == DstBitSize) { 3109 SmallVector<SDOperand, 8> Ops; 3110 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3111 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3112 AddToWorkList(Ops.back().Val); 3113 } 3114 MVT::ValueType VT = 3115 MVT::getVectorType(DstEltVT, 3116 MVT::getVectorNumElements(BV->getValueType(0))); 3117 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3118 } 3119 3120 // Otherwise, we're growing or shrinking the elements. To avoid having to 3121 // handle annoying details of growing/shrinking FP values, we convert them to 3122 // int first. 3123 if (MVT::isFloatingPoint(SrcEltVT)) { 3124 // Convert the input float vector to a int vector where the elements are the 3125 // same sizes. 3126 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3127 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3128 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3129 SrcEltVT = IntVT; 3130 } 3131 3132 // Now we know the input is an integer vector. If the output is a FP type, 3133 // convert to integer first, then to FP of the right size. 3134 if (MVT::isFloatingPoint(DstEltVT)) { 3135 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3136 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3137 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3138 3139 // Next, convert to FP elements of the same size. 3140 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3141 } 3142 3143 // Okay, we know the src/dst types are both integers of differing types. 3144 // Handling growing first. 3145 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3146 if (SrcBitSize < DstBitSize) { 3147 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3148 3149 SmallVector<SDOperand, 8> Ops; 3150 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3151 i += NumInputsPerOutput) { 3152 bool isLE = TLI.isLittleEndian(); 3153 uint64_t NewBits = 0; 3154 bool EltIsUndef = true; 3155 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3156 // Shift the previously computed bits over. 3157 NewBits <<= SrcBitSize; 3158 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3159 if (Op.getOpcode() == ISD::UNDEF) continue; 3160 EltIsUndef = false; 3161 3162 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3163 } 3164 3165 if (EltIsUndef) 3166 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3167 else 3168 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3169 } 3170 3171 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3172 Ops.size()); 3173 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3174 } 3175 3176 // Finally, this must be the case where we are shrinking elements: each input 3177 // turns into multiple outputs. 3178 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3179 SmallVector<SDOperand, 8> Ops; 3180 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3181 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3182 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3183 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3184 continue; 3185 } 3186 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3187 3188 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3189 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3190 OpVal >>= DstBitSize; 3191 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3192 } 3193 3194 // For big endian targets, swap the order of the pieces of each element. 3195 if (!TLI.isLittleEndian()) 3196 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3197 } 3198 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3199 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3200} 3201 3202 3203 3204SDOperand DAGCombiner::visitFADD(SDNode *N) { 3205 SDOperand N0 = N->getOperand(0); 3206 SDOperand N1 = N->getOperand(1); 3207 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3208 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3209 MVT::ValueType VT = N->getValueType(0); 3210 3211 // fold vector ops 3212 if (MVT::isVector(VT)) { 3213 SDOperand FoldedVOp = SimplifyVBinOp(N); 3214 if (FoldedVOp.Val) return FoldedVOp; 3215 } 3216 3217 // fold (fadd c1, c2) -> c1+c2 3218 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3219 return DAG.getNode(ISD::FADD, VT, N0, N1); 3220 // canonicalize constant to RHS 3221 if (N0CFP && !N1CFP) 3222 return DAG.getNode(ISD::FADD, VT, N1, N0); 3223 // fold (A + (-B)) -> A-B 3224 if (isNegatibleForFree(N1) == 2) 3225 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3226 // fold ((-A) + B) -> B-A 3227 if (isNegatibleForFree(N0) == 2) 3228 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3229 3230 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3231 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3232 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3233 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3234 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3235 3236 return SDOperand(); 3237} 3238 3239SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3240 SDOperand N0 = N->getOperand(0); 3241 SDOperand N1 = N->getOperand(1); 3242 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3243 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3244 MVT::ValueType VT = N->getValueType(0); 3245 3246 // fold vector ops 3247 if (MVT::isVector(VT)) { 3248 SDOperand FoldedVOp = SimplifyVBinOp(N); 3249 if (FoldedVOp.Val) return FoldedVOp; 3250 } 3251 3252 // fold (fsub c1, c2) -> c1-c2 3253 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3254 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3255 // fold (0-B) -> -B 3256 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3257 if (isNegatibleForFree(N1)) 3258 return GetNegatedExpression(N1, DAG); 3259 return DAG.getNode(ISD::FNEG, VT, N1); 3260 } 3261 // fold (A-(-B)) -> A+B 3262 if (isNegatibleForFree(N1)) 3263 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3264 3265 return SDOperand(); 3266} 3267 3268SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3269 SDOperand N0 = N->getOperand(0); 3270 SDOperand N1 = N->getOperand(1); 3271 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3272 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3273 MVT::ValueType VT = N->getValueType(0); 3274 3275 // fold vector ops 3276 if (MVT::isVector(VT)) { 3277 SDOperand FoldedVOp = SimplifyVBinOp(N); 3278 if (FoldedVOp.Val) return FoldedVOp; 3279 } 3280 3281 // fold (fmul c1, c2) -> c1*c2 3282 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3283 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3284 // canonicalize constant to RHS 3285 if (N0CFP && !N1CFP) 3286 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3287 // fold (fmul X, 2.0) -> (fadd X, X) 3288 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3289 return DAG.getNode(ISD::FADD, VT, N0, N0); 3290 // fold (fmul X, -1.0) -> (fneg X) 3291 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3292 return DAG.getNode(ISD::FNEG, VT, N0); 3293 3294 // -X * -Y -> X*Y 3295 if (char LHSNeg = isNegatibleForFree(N0)) { 3296 if (char RHSNeg = isNegatibleForFree(N1)) { 3297 // Both can be negated for free, check to see if at least one is cheaper 3298 // negated. 3299 if (LHSNeg == 2 || RHSNeg == 2) 3300 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3301 GetNegatedExpression(N1, DAG)); 3302 } 3303 } 3304 3305 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3306 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3307 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3308 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3309 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3310 3311 return SDOperand(); 3312} 3313 3314SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3315 SDOperand N0 = N->getOperand(0); 3316 SDOperand N1 = N->getOperand(1); 3317 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3318 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3319 MVT::ValueType VT = N->getValueType(0); 3320 3321 // fold vector ops 3322 if (MVT::isVector(VT)) { 3323 SDOperand FoldedVOp = SimplifyVBinOp(N); 3324 if (FoldedVOp.Val) return FoldedVOp; 3325 } 3326 3327 // fold (fdiv c1, c2) -> c1/c2 3328 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3329 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3330 3331 3332 // -X / -Y -> X*Y 3333 if (char LHSNeg = isNegatibleForFree(N0)) { 3334 if (char RHSNeg = isNegatibleForFree(N1)) { 3335 // Both can be negated for free, check to see if at least one is cheaper 3336 // negated. 3337 if (LHSNeg == 2 || RHSNeg == 2) 3338 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3339 GetNegatedExpression(N1, DAG)); 3340 } 3341 } 3342 3343 return SDOperand(); 3344} 3345 3346SDOperand DAGCombiner::visitFREM(SDNode *N) { 3347 SDOperand N0 = N->getOperand(0); 3348 SDOperand N1 = N->getOperand(1); 3349 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3350 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3351 MVT::ValueType VT = N->getValueType(0); 3352 3353 // fold (frem c1, c2) -> fmod(c1,c2) 3354 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3355 return DAG.getNode(ISD::FREM, VT, N0, N1); 3356 3357 return SDOperand(); 3358} 3359 3360SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3361 SDOperand N0 = N->getOperand(0); 3362 SDOperand N1 = N->getOperand(1); 3363 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3364 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3365 MVT::ValueType VT = N->getValueType(0); 3366 3367 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3368 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3369 3370 if (N1CFP) { 3371 const APFloat& V = N1CFP->getValueAPF(); 3372 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3373 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3374 if (!V.isNegative()) 3375 return DAG.getNode(ISD::FABS, VT, N0); 3376 else 3377 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3378 } 3379 3380 // copysign(fabs(x), y) -> copysign(x, y) 3381 // copysign(fneg(x), y) -> copysign(x, y) 3382 // copysign(copysign(x,z), y) -> copysign(x, y) 3383 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3384 N0.getOpcode() == ISD::FCOPYSIGN) 3385 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3386 3387 // copysign(x, abs(y)) -> abs(x) 3388 if (N1.getOpcode() == ISD::FABS) 3389 return DAG.getNode(ISD::FABS, VT, N0); 3390 3391 // copysign(x, copysign(y,z)) -> copysign(x, z) 3392 if (N1.getOpcode() == ISD::FCOPYSIGN) 3393 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3394 3395 // copysign(x, fp_extend(y)) -> copysign(x, y) 3396 // copysign(x, fp_round(y)) -> copysign(x, y) 3397 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3398 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3399 3400 return SDOperand(); 3401} 3402 3403 3404 3405SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3406 SDOperand N0 = N->getOperand(0); 3407 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3408 MVT::ValueType VT = N->getValueType(0); 3409 3410 // fold (sint_to_fp c1) -> c1fp 3411 if (N0C && N0.getValueType() != MVT::ppcf128) 3412 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3413 return SDOperand(); 3414} 3415 3416SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3417 SDOperand N0 = N->getOperand(0); 3418 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3419 MVT::ValueType VT = N->getValueType(0); 3420 3421 // fold (uint_to_fp c1) -> c1fp 3422 if (N0C && N0.getValueType() != MVT::ppcf128) 3423 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3424 return SDOperand(); 3425} 3426 3427SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3428 SDOperand N0 = N->getOperand(0); 3429 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3430 MVT::ValueType VT = N->getValueType(0); 3431 3432 // fold (fp_to_sint c1fp) -> c1 3433 if (N0CFP) 3434 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3435 return SDOperand(); 3436} 3437 3438SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3439 SDOperand N0 = N->getOperand(0); 3440 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3441 MVT::ValueType VT = N->getValueType(0); 3442 3443 // fold (fp_to_uint c1fp) -> c1 3444 if (N0CFP && VT != MVT::ppcf128) 3445 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3446 return SDOperand(); 3447} 3448 3449SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3450 SDOperand N0 = N->getOperand(0); 3451 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3452 MVT::ValueType VT = N->getValueType(0); 3453 3454 // fold (fp_round c1fp) -> c1fp 3455 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3456 return DAG.getNode(ISD::FP_ROUND, VT, N0); 3457 3458 // fold (fp_round (fp_extend x)) -> x 3459 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3460 return N0.getOperand(0); 3461 3462 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3463 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3464 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 3465 AddToWorkList(Tmp.Val); 3466 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3467 } 3468 3469 return SDOperand(); 3470} 3471 3472SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3473 SDOperand N0 = N->getOperand(0); 3474 MVT::ValueType VT = N->getValueType(0); 3475 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3476 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3477 3478 // fold (fp_round_inreg c1fp) -> c1fp 3479 if (N0CFP) { 3480 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3481 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3482 } 3483 return SDOperand(); 3484} 3485 3486SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3487 SDOperand N0 = N->getOperand(0); 3488 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3489 MVT::ValueType VT = N->getValueType(0); 3490 3491 // fold (fp_extend c1fp) -> c1fp 3492 if (N0CFP && VT != MVT::ppcf128) 3493 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3494 3495 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 3496 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3497 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3498 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3499 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3500 LN0->getBasePtr(), LN0->getSrcValue(), 3501 LN0->getSrcValueOffset(), 3502 N0.getValueType(), 3503 LN0->isVolatile(), 3504 LN0->getAlignment()); 3505 CombineTo(N, ExtLoad); 3506 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 3507 ExtLoad.getValue(1)); 3508 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3509 } 3510 3511 3512 return SDOperand(); 3513} 3514 3515SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3516 SDOperand N0 = N->getOperand(0); 3517 3518 if (isNegatibleForFree(N0)) 3519 return GetNegatedExpression(N0, DAG); 3520 3521 return SDOperand(); 3522} 3523 3524SDOperand DAGCombiner::visitFABS(SDNode *N) { 3525 SDOperand N0 = N->getOperand(0); 3526 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3527 MVT::ValueType VT = N->getValueType(0); 3528 3529 // fold (fabs c1) -> fabs(c1) 3530 if (N0CFP && VT != MVT::ppcf128) 3531 return DAG.getNode(ISD::FABS, VT, N0); 3532 // fold (fabs (fabs x)) -> (fabs x) 3533 if (N0.getOpcode() == ISD::FABS) 3534 return N->getOperand(0); 3535 // fold (fabs (fneg x)) -> (fabs x) 3536 // fold (fabs (fcopysign x, y)) -> (fabs x) 3537 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3538 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3539 3540 return SDOperand(); 3541} 3542 3543SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3544 SDOperand Chain = N->getOperand(0); 3545 SDOperand N1 = N->getOperand(1); 3546 SDOperand N2 = N->getOperand(2); 3547 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3548 3549 // never taken branch, fold to chain 3550 if (N1C && N1C->isNullValue()) 3551 return Chain; 3552 // unconditional branch 3553 if (N1C && N1C->getValue() == 1) 3554 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3555 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3556 // on the target. 3557 if (N1.getOpcode() == ISD::SETCC && 3558 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3559 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3560 N1.getOperand(0), N1.getOperand(1), N2); 3561 } 3562 return SDOperand(); 3563} 3564 3565// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3566// 3567SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3568 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3569 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3570 3571 // Use SimplifySetCC to simplify SETCC's. 3572 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3573 if (Simp.Val) AddToWorkList(Simp.Val); 3574 3575 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3576 3577 // fold br_cc true, dest -> br dest (unconditional branch) 3578 if (SCCC && SCCC->getValue()) 3579 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3580 N->getOperand(4)); 3581 // fold br_cc false, dest -> unconditional fall through 3582 if (SCCC && SCCC->isNullValue()) 3583 return N->getOperand(0); 3584 3585 // fold to a simpler setcc 3586 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3587 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3588 Simp.getOperand(2), Simp.getOperand(0), 3589 Simp.getOperand(1), N->getOperand(4)); 3590 return SDOperand(); 3591} 3592 3593 3594/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3595/// pre-indexed load / store when the base pointer is a add or subtract 3596/// and it has other uses besides the load / store. After the 3597/// transformation, the new indexed load / store has effectively folded 3598/// the add / subtract in and all of its other uses are redirected to the 3599/// new load / store. 3600bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3601 if (!AfterLegalize) 3602 return false; 3603 3604 bool isLoad = true; 3605 SDOperand Ptr; 3606 MVT::ValueType VT; 3607 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3608 if (LD->getAddressingMode() != ISD::UNINDEXED) 3609 return false; 3610 VT = LD->getLoadedVT(); 3611 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3612 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3613 return false; 3614 Ptr = LD->getBasePtr(); 3615 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3616 if (ST->getAddressingMode() != ISD::UNINDEXED) 3617 return false; 3618 VT = ST->getStoredVT(); 3619 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3620 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3621 return false; 3622 Ptr = ST->getBasePtr(); 3623 isLoad = false; 3624 } else 3625 return false; 3626 3627 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3628 // out. There is no reason to make this a preinc/predec. 3629 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3630 Ptr.Val->hasOneUse()) 3631 return false; 3632 3633 // Ask the target to do addressing mode selection. 3634 SDOperand BasePtr; 3635 SDOperand Offset; 3636 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3637 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3638 return false; 3639 // Don't create a indexed load / store with zero offset. 3640 if (isa<ConstantSDNode>(Offset) && 3641 cast<ConstantSDNode>(Offset)->getValue() == 0) 3642 return false; 3643 3644 // Try turning it into a pre-indexed load / store except when: 3645 // 1) The new base ptr is a frame index. 3646 // 2) If N is a store and the new base ptr is either the same as or is a 3647 // predecessor of the value being stored. 3648 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3649 // that would create a cycle. 3650 // 4) All uses are load / store ops that use it as old base ptr. 3651 3652 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3653 // (plus the implicit offset) to a register to preinc anyway. 3654 if (isa<FrameIndexSDNode>(BasePtr)) 3655 return false; 3656 3657 // Check #2. 3658 if (!isLoad) { 3659 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3660 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3661 return false; 3662 } 3663 3664 // Now check for #3 and #4. 3665 bool RealUse = false; 3666 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3667 E = Ptr.Val->use_end(); I != E; ++I) { 3668 SDNode *Use = *I; 3669 if (Use == N) 3670 continue; 3671 if (Use->isPredecessor(N)) 3672 return false; 3673 3674 if (!((Use->getOpcode() == ISD::LOAD && 3675 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3676 (Use->getOpcode() == ISD::STORE) && 3677 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3678 RealUse = true; 3679 } 3680 if (!RealUse) 3681 return false; 3682 3683 SDOperand Result; 3684 if (isLoad) 3685 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3686 else 3687 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3688 ++PreIndexedNodes; 3689 ++NodesCombined; 3690 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 3691 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3692 DOUT << '\n'; 3693 std::vector<SDNode*> NowDead; 3694 if (isLoad) { 3695 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3696 &NowDead); 3697 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3698 &NowDead); 3699 } else { 3700 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3701 &NowDead); 3702 } 3703 3704 // Nodes can end up on the worklist more than once. Make sure we do 3705 // not process a node that has been replaced. 3706 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3707 removeFromWorkList(NowDead[i]); 3708 // Finally, since the node is now dead, remove it from the graph. 3709 DAG.DeleteNode(N); 3710 3711 // Replace the uses of Ptr with uses of the updated base value. 3712 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3713 &NowDead); 3714 removeFromWorkList(Ptr.Val); 3715 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3716 removeFromWorkList(NowDead[i]); 3717 DAG.DeleteNode(Ptr.Val); 3718 3719 return true; 3720} 3721 3722/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3723/// add / sub of the base pointer node into a post-indexed load / store. 3724/// The transformation folded the add / subtract into the new indexed 3725/// load / store effectively and all of its uses are redirected to the 3726/// new load / store. 3727bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3728 if (!AfterLegalize) 3729 return false; 3730 3731 bool isLoad = true; 3732 SDOperand Ptr; 3733 MVT::ValueType VT; 3734 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3735 if (LD->getAddressingMode() != ISD::UNINDEXED) 3736 return false; 3737 VT = LD->getLoadedVT(); 3738 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3739 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3740 return false; 3741 Ptr = LD->getBasePtr(); 3742 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3743 if (ST->getAddressingMode() != ISD::UNINDEXED) 3744 return false; 3745 VT = ST->getStoredVT(); 3746 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3747 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3748 return false; 3749 Ptr = ST->getBasePtr(); 3750 isLoad = false; 3751 } else 3752 return false; 3753 3754 if (Ptr.Val->hasOneUse()) 3755 return false; 3756 3757 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3758 E = Ptr.Val->use_end(); I != E; ++I) { 3759 SDNode *Op = *I; 3760 if (Op == N || 3761 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3762 continue; 3763 3764 SDOperand BasePtr; 3765 SDOperand Offset; 3766 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3767 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3768 if (Ptr == Offset) 3769 std::swap(BasePtr, Offset); 3770 if (Ptr != BasePtr) 3771 continue; 3772 // Don't create a indexed load / store with zero offset. 3773 if (isa<ConstantSDNode>(Offset) && 3774 cast<ConstantSDNode>(Offset)->getValue() == 0) 3775 continue; 3776 3777 // Try turning it into a post-indexed load / store except when 3778 // 1) All uses are load / store ops that use it as base ptr. 3779 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3780 // nor a successor of N. Otherwise, if Op is folded that would 3781 // create a cycle. 3782 3783 // Check for #1. 3784 bool TryNext = false; 3785 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3786 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3787 SDNode *Use = *II; 3788 if (Use == Ptr.Val) 3789 continue; 3790 3791 // If all the uses are load / store addresses, then don't do the 3792 // transformation. 3793 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3794 bool RealUse = false; 3795 for (SDNode::use_iterator III = Use->use_begin(), 3796 EEE = Use->use_end(); III != EEE; ++III) { 3797 SDNode *UseUse = *III; 3798 if (!((UseUse->getOpcode() == ISD::LOAD && 3799 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3800 (UseUse->getOpcode() == ISD::STORE) && 3801 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3802 RealUse = true; 3803 } 3804 3805 if (!RealUse) { 3806 TryNext = true; 3807 break; 3808 } 3809 } 3810 } 3811 if (TryNext) 3812 continue; 3813 3814 // Check for #2 3815 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3816 SDOperand Result = isLoad 3817 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3818 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3819 ++PostIndexedNodes; 3820 ++NodesCombined; 3821 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 3822 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3823 DOUT << '\n'; 3824 std::vector<SDNode*> NowDead; 3825 if (isLoad) { 3826 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3827 &NowDead); 3828 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3829 &NowDead); 3830 } else { 3831 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3832 &NowDead); 3833 } 3834 3835 // Nodes can end up on the worklist more than once. Make sure we do 3836 // not process a node that has been replaced. 3837 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3838 removeFromWorkList(NowDead[i]); 3839 // Finally, since the node is now dead, remove it from the graph. 3840 DAG.DeleteNode(N); 3841 3842 // Replace the uses of Use with uses of the updated base value. 3843 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3844 Result.getValue(isLoad ? 1 : 0), 3845 &NowDead); 3846 removeFromWorkList(Op); 3847 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3848 removeFromWorkList(NowDead[i]); 3849 DAG.DeleteNode(Op); 3850 3851 return true; 3852 } 3853 } 3854 } 3855 return false; 3856} 3857 3858 3859SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3860 LoadSDNode *LD = cast<LoadSDNode>(N); 3861 SDOperand Chain = LD->getChain(); 3862 SDOperand Ptr = LD->getBasePtr(); 3863 3864 // If load is not volatile and there are no uses of the loaded value (and 3865 // the updated indexed value in case of indexed loads), change uses of the 3866 // chain value into uses of the chain input (i.e. delete the dead load). 3867 if (!LD->isVolatile()) { 3868 if (N->getValueType(1) == MVT::Other) { 3869 // Unindexed loads. 3870 if (N->hasNUsesOfValue(0, 0)) 3871 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3872 } else { 3873 // Indexed loads. 3874 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 3875 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 3876 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3877 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1)); 3878 SDOperand To[] = { Undef0, Undef1, Chain }; 3879 return CombineTo(N, To, 3); 3880 } 3881 } 3882 } 3883 3884 // If this load is directly stored, replace the load value with the stored 3885 // value. 3886 // TODO: Handle store large -> read small portion. 3887 // TODO: Handle TRUNCSTORE/LOADEXT 3888 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3889 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3890 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3891 if (PrevST->getBasePtr() == Ptr && 3892 PrevST->getValue().getValueType() == N->getValueType(0)) 3893 return CombineTo(N, Chain.getOperand(1), Chain); 3894 } 3895 } 3896 3897 if (CombinerAA) { 3898 // Walk up chain skipping non-aliasing memory nodes. 3899 SDOperand BetterChain = FindBetterChain(N, Chain); 3900 3901 // If there is a better chain. 3902 if (Chain != BetterChain) { 3903 SDOperand ReplLoad; 3904 3905 // Replace the chain to void dependency. 3906 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3907 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3908 LD->getSrcValue(), LD->getSrcValueOffset(), 3909 LD->isVolatile(), LD->getAlignment()); 3910 } else { 3911 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3912 LD->getValueType(0), 3913 BetterChain, Ptr, LD->getSrcValue(), 3914 LD->getSrcValueOffset(), 3915 LD->getLoadedVT(), 3916 LD->isVolatile(), 3917 LD->getAlignment()); 3918 } 3919 3920 // Create token factor to keep old chain connected. 3921 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3922 Chain, ReplLoad.getValue(1)); 3923 3924 // Replace uses with load result and token factor. Don't add users 3925 // to work list. 3926 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3927 } 3928 } 3929 3930 // Try transforming N to an indexed load. 3931 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3932 return SDOperand(N, 0); 3933 3934 return SDOperand(); 3935} 3936 3937SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3938 StoreSDNode *ST = cast<StoreSDNode>(N); 3939 SDOperand Chain = ST->getChain(); 3940 SDOperand Value = ST->getValue(); 3941 SDOperand Ptr = ST->getBasePtr(); 3942 3943 // If this is a store of a bit convert, store the input value if the 3944 // resultant store does not need a higher alignment than the original. 3945 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 3946 ST->getAddressingMode() == ISD::UNINDEXED) { 3947 unsigned Align = ST->getAlignment(); 3948 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 3949 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 3950 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 3951 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 3952 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3953 ST->getSrcValueOffset(), ST->isVolatile(), Align); 3954 } 3955 3956 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3957 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3958 if (Value.getOpcode() != ISD::TargetConstantFP) { 3959 SDOperand Tmp; 3960 switch (CFP->getValueType(0)) { 3961 default: assert(0 && "Unknown FP type"); 3962 case MVT::f80: // We don't do this for these yet. 3963 case MVT::f128: 3964 case MVT::ppcf128: 3965 break; 3966 case MVT::f32: 3967 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3968 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 3969 convertToAPInt().getZExtValue(), MVT::i32); 3970 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3971 ST->getSrcValueOffset(), ST->isVolatile(), 3972 ST->getAlignment()); 3973 } 3974 break; 3975 case MVT::f64: 3976 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3977 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 3978 getZExtValue(), MVT::i64); 3979 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3980 ST->getSrcValueOffset(), ST->isVolatile(), 3981 ST->getAlignment()); 3982 } else if (TLI.isTypeLegal(MVT::i32)) { 3983 // Many FP stores are not make apparent until after legalize, e.g. for 3984 // argument passing. Since this is so common, custom legalize the 3985 // 64-bit integer store into two 32-bit stores. 3986 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 3987 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3988 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3989 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3990 3991 int SVOffset = ST->getSrcValueOffset(); 3992 unsigned Alignment = ST->getAlignment(); 3993 bool isVolatile = ST->isVolatile(); 3994 3995 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3996 ST->getSrcValueOffset(), 3997 isVolatile, ST->getAlignment()); 3998 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3999 DAG.getConstant(4, Ptr.getValueType())); 4000 SVOffset += 4; 4001 if (Alignment > 4) 4002 Alignment = 4; 4003 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4004 SVOffset, isVolatile, Alignment); 4005 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4006 } 4007 break; 4008 } 4009 } 4010 } 4011 4012 if (CombinerAA) { 4013 // Walk up chain skipping non-aliasing memory nodes. 4014 SDOperand BetterChain = FindBetterChain(N, Chain); 4015 4016 // If there is a better chain. 4017 if (Chain != BetterChain) { 4018 // Replace the chain to avoid dependency. 4019 SDOperand ReplStore; 4020 if (ST->isTruncatingStore()) { 4021 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4022 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(), 4023 ST->isVolatile(), ST->getAlignment()); 4024 } else { 4025 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4026 ST->getSrcValue(), ST->getSrcValueOffset(), 4027 ST->isVolatile(), ST->getAlignment()); 4028 } 4029 4030 // Create token to keep both nodes around. 4031 SDOperand Token = 4032 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4033 4034 // Don't add users to work list. 4035 return CombineTo(N, Token, false); 4036 } 4037 } 4038 4039 // Try transforming N to an indexed store. 4040 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4041 return SDOperand(N, 0); 4042 4043 // FIXME: is there such a think as a truncating indexed store? 4044 if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED && 4045 MVT::isInteger(Value.getValueType())) { 4046 // See if we can simplify the input to this truncstore with knowledge that 4047 // only the low bits are being used. For example: 4048 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4049 SDOperand Shorter = 4050 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())); 4051 AddToWorkList(Value.Val); 4052 if (Shorter.Val) 4053 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4054 ST->getSrcValueOffset(), ST->getStoredVT(), 4055 ST->isVolatile(), ST->getAlignment()); 4056 4057 // Otherwise, see if we can simplify the operation with 4058 // SimplifyDemandedBits, which only works if the value has a single use. 4059 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()))) 4060 return SDOperand(N, 0); 4061 } 4062 4063 return SDOperand(); 4064} 4065 4066SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4067 SDOperand InVec = N->getOperand(0); 4068 SDOperand InVal = N->getOperand(1); 4069 SDOperand EltNo = N->getOperand(2); 4070 4071 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4072 // vector with the inserted element. 4073 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4074 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4075 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4076 if (Elt < Ops.size()) 4077 Ops[Elt] = InVal; 4078 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4079 &Ops[0], Ops.size()); 4080 } 4081 4082 return SDOperand(); 4083} 4084 4085SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4086 SDOperand InVec = N->getOperand(0); 4087 SDOperand EltNo = N->getOperand(1); 4088 4089 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4090 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4091 if (isa<ConstantSDNode>(EltNo)) { 4092 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4093 bool NewLoad = false; 4094 if (Elt == 0) { 4095 MVT::ValueType VT = InVec.getValueType(); 4096 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4097 MVT::ValueType LVT = EVT; 4098 unsigned NumElts = MVT::getVectorNumElements(VT); 4099 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4100 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4101 if (NumElts != MVT::getVectorNumElements(BCVT)) 4102 return SDOperand(); 4103 InVec = InVec.getOperand(0); 4104 EVT = MVT::getVectorElementType(BCVT); 4105 NewLoad = true; 4106 } 4107 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4108 InVec.getOperand(0).getValueType() == EVT && 4109 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4110 InVec.getOperand(0).hasOneUse()) { 4111 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4112 unsigned Align = LN0->getAlignment(); 4113 if (NewLoad) { 4114 // Check the resultant load doesn't need a higher alignment than the 4115 // original load. 4116 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4117 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4118 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4119 return SDOperand(); 4120 Align = NewAlign; 4121 } 4122 4123 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4124 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4125 LN0->isVolatile(), Align); 4126 } 4127 } 4128 } 4129 return SDOperand(); 4130} 4131 4132 4133SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4134 unsigned NumInScalars = N->getNumOperands(); 4135 MVT::ValueType VT = N->getValueType(0); 4136 unsigned NumElts = MVT::getVectorNumElements(VT); 4137 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4138 4139 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4140 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4141 // at most two distinct vectors, turn this into a shuffle node. 4142 SDOperand VecIn1, VecIn2; 4143 for (unsigned i = 0; i != NumInScalars; ++i) { 4144 // Ignore undef inputs. 4145 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4146 4147 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4148 // constant index, bail out. 4149 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4150 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4151 VecIn1 = VecIn2 = SDOperand(0, 0); 4152 break; 4153 } 4154 4155 // If the input vector type disagrees with the result of the build_vector, 4156 // we can't make a shuffle. 4157 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4158 if (ExtractedFromVec.getValueType() != VT) { 4159 VecIn1 = VecIn2 = SDOperand(0, 0); 4160 break; 4161 } 4162 4163 // Otherwise, remember this. We allow up to two distinct input vectors. 4164 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4165 continue; 4166 4167 if (VecIn1.Val == 0) { 4168 VecIn1 = ExtractedFromVec; 4169 } else if (VecIn2.Val == 0) { 4170 VecIn2 = ExtractedFromVec; 4171 } else { 4172 // Too many inputs. 4173 VecIn1 = VecIn2 = SDOperand(0, 0); 4174 break; 4175 } 4176 } 4177 4178 // If everything is good, we can make a shuffle operation. 4179 if (VecIn1.Val) { 4180 SmallVector<SDOperand, 8> BuildVecIndices; 4181 for (unsigned i = 0; i != NumInScalars; ++i) { 4182 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4183 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4184 continue; 4185 } 4186 4187 SDOperand Extract = N->getOperand(i); 4188 4189 // If extracting from the first vector, just use the index directly. 4190 if (Extract.getOperand(0) == VecIn1) { 4191 BuildVecIndices.push_back(Extract.getOperand(1)); 4192 continue; 4193 } 4194 4195 // Otherwise, use InIdx + VecSize 4196 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4197 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 4198 TLI.getPointerTy())); 4199 } 4200 4201 // Add count and size info. 4202 MVT::ValueType BuildVecVT = 4203 MVT::getVectorType(TLI.getPointerTy(), NumElts); 4204 4205 // Return the new VECTOR_SHUFFLE node. 4206 SDOperand Ops[5]; 4207 Ops[0] = VecIn1; 4208 if (VecIn2.Val) { 4209 Ops[1] = VecIn2; 4210 } else { 4211 // Use an undef build_vector as input for the second operand. 4212 std::vector<SDOperand> UnOps(NumInScalars, 4213 DAG.getNode(ISD::UNDEF, 4214 EltType)); 4215 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4216 &UnOps[0], UnOps.size()); 4217 AddToWorkList(Ops[1].Val); 4218 } 4219 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4220 &BuildVecIndices[0], BuildVecIndices.size()); 4221 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4222 } 4223 4224 return SDOperand(); 4225} 4226 4227SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4228 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4229 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4230 // inputs come from at most two distinct vectors, turn this into a shuffle 4231 // node. 4232 4233 // If we only have one input vector, we don't need to do any concatenation. 4234 if (N->getNumOperands() == 1) { 4235 return N->getOperand(0); 4236 } 4237 4238 return SDOperand(); 4239} 4240 4241SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4242 SDOperand ShufMask = N->getOperand(2); 4243 unsigned NumElts = ShufMask.getNumOperands(); 4244 4245 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4246 bool isIdentity = true; 4247 for (unsigned i = 0; i != NumElts; ++i) { 4248 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4249 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4250 isIdentity = false; 4251 break; 4252 } 4253 } 4254 if (isIdentity) return N->getOperand(0); 4255 4256 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4257 isIdentity = true; 4258 for (unsigned i = 0; i != NumElts; ++i) { 4259 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4260 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4261 isIdentity = false; 4262 break; 4263 } 4264 } 4265 if (isIdentity) return N->getOperand(1); 4266 4267 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4268 // needed at all. 4269 bool isUnary = true; 4270 bool isSplat = true; 4271 int VecNum = -1; 4272 unsigned BaseIdx = 0; 4273 for (unsigned i = 0; i != NumElts; ++i) 4274 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4275 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4276 int V = (Idx < NumElts) ? 0 : 1; 4277 if (VecNum == -1) { 4278 VecNum = V; 4279 BaseIdx = Idx; 4280 } else { 4281 if (BaseIdx != Idx) 4282 isSplat = false; 4283 if (VecNum != V) { 4284 isUnary = false; 4285 break; 4286 } 4287 } 4288 } 4289 4290 SDOperand N0 = N->getOperand(0); 4291 SDOperand N1 = N->getOperand(1); 4292 // Normalize unary shuffle so the RHS is undef. 4293 if (isUnary && VecNum == 1) 4294 std::swap(N0, N1); 4295 4296 // If it is a splat, check if the argument vector is a build_vector with 4297 // all scalar elements the same. 4298 if (isSplat) { 4299 SDNode *V = N0.Val; 4300 4301 // If this is a bit convert that changes the element type of the vector but 4302 // not the number of vector elements, look through it. Be careful not to 4303 // look though conversions that change things like v4f32 to v2f64. 4304 if (V->getOpcode() == ISD::BIT_CONVERT) { 4305 SDOperand ConvInput = V->getOperand(0); 4306 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4307 V = ConvInput.Val; 4308 } 4309 4310 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4311 unsigned NumElems = V->getNumOperands(); 4312 if (NumElems > BaseIdx) { 4313 SDOperand Base; 4314 bool AllSame = true; 4315 for (unsigned i = 0; i != NumElems; ++i) { 4316 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4317 Base = V->getOperand(i); 4318 break; 4319 } 4320 } 4321 // Splat of <u, u, u, u>, return <u, u, u, u> 4322 if (!Base.Val) 4323 return N0; 4324 for (unsigned i = 0; i != NumElems; ++i) { 4325 if (V->getOperand(i) != Base) { 4326 AllSame = false; 4327 break; 4328 } 4329 } 4330 // Splat of <x, x, x, x>, return <x, x, x, x> 4331 if (AllSame) 4332 return N0; 4333 } 4334 } 4335 } 4336 4337 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4338 // into an undef. 4339 if (isUnary || N0 == N1) { 4340 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4341 // first operand. 4342 SmallVector<SDOperand, 8> MappedOps; 4343 for (unsigned i = 0; i != NumElts; ++i) { 4344 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4345 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4346 MappedOps.push_back(ShufMask.getOperand(i)); 4347 } else { 4348 unsigned NewIdx = 4349 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4350 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4351 } 4352 } 4353 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4354 &MappedOps[0], MappedOps.size()); 4355 AddToWorkList(ShufMask.Val); 4356 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4357 N0, 4358 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4359 ShufMask); 4360 } 4361 4362 return SDOperand(); 4363} 4364 4365/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4366/// an AND to a vector_shuffle with the destination vector and a zero vector. 4367/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4368/// vector_shuffle V, Zero, <0, 4, 2, 4> 4369SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4370 SDOperand LHS = N->getOperand(0); 4371 SDOperand RHS = N->getOperand(1); 4372 if (N->getOpcode() == ISD::AND) { 4373 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4374 RHS = RHS.getOperand(0); 4375 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4376 std::vector<SDOperand> IdxOps; 4377 unsigned NumOps = RHS.getNumOperands(); 4378 unsigned NumElts = NumOps; 4379 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4380 for (unsigned i = 0; i != NumElts; ++i) { 4381 SDOperand Elt = RHS.getOperand(i); 4382 if (!isa<ConstantSDNode>(Elt)) 4383 return SDOperand(); 4384 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4385 IdxOps.push_back(DAG.getConstant(i, EVT)); 4386 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4387 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4388 else 4389 return SDOperand(); 4390 } 4391 4392 // Let's see if the target supports this vector_shuffle. 4393 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4394 return SDOperand(); 4395 4396 // Return the new VECTOR_SHUFFLE node. 4397 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4398 std::vector<SDOperand> Ops; 4399 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4400 Ops.push_back(LHS); 4401 AddToWorkList(LHS.Val); 4402 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4403 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4404 &ZeroOps[0], ZeroOps.size())); 4405 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4406 &IdxOps[0], IdxOps.size())); 4407 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4408 &Ops[0], Ops.size()); 4409 if (VT != LHS.getValueType()) { 4410 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4411 } 4412 return Result; 4413 } 4414 } 4415 return SDOperand(); 4416} 4417 4418/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4419SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4420 // After legalize, the target may be depending on adds and other 4421 // binary ops to provide legal ways to construct constants or other 4422 // things. Simplifying them may result in a loss of legality. 4423 if (AfterLegalize) return SDOperand(); 4424 4425 MVT::ValueType VT = N->getValueType(0); 4426 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4427 4428 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4429 SDOperand LHS = N->getOperand(0); 4430 SDOperand RHS = N->getOperand(1); 4431 SDOperand Shuffle = XformToShuffleWithZero(N); 4432 if (Shuffle.Val) return Shuffle; 4433 4434 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4435 // this operation. 4436 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4437 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4438 SmallVector<SDOperand, 8> Ops; 4439 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4440 SDOperand LHSOp = LHS.getOperand(i); 4441 SDOperand RHSOp = RHS.getOperand(i); 4442 // If these two elements can't be folded, bail out. 4443 if ((LHSOp.getOpcode() != ISD::UNDEF && 4444 LHSOp.getOpcode() != ISD::Constant && 4445 LHSOp.getOpcode() != ISD::ConstantFP) || 4446 (RHSOp.getOpcode() != ISD::UNDEF && 4447 RHSOp.getOpcode() != ISD::Constant && 4448 RHSOp.getOpcode() != ISD::ConstantFP)) 4449 break; 4450 // Can't fold divide by zero. 4451 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4452 N->getOpcode() == ISD::FDIV) { 4453 if ((RHSOp.getOpcode() == ISD::Constant && 4454 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4455 (RHSOp.getOpcode() == ISD::ConstantFP && 4456 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4457 break; 4458 } 4459 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4460 AddToWorkList(Ops.back().Val); 4461 assert((Ops.back().getOpcode() == ISD::UNDEF || 4462 Ops.back().getOpcode() == ISD::Constant || 4463 Ops.back().getOpcode() == ISD::ConstantFP) && 4464 "Scalar binop didn't fold!"); 4465 } 4466 4467 if (Ops.size() == LHS.getNumOperands()) { 4468 MVT::ValueType VT = LHS.getValueType(); 4469 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4470 } 4471 } 4472 4473 return SDOperand(); 4474} 4475 4476SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4477 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4478 4479 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4480 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4481 // If we got a simplified select_cc node back from SimplifySelectCC, then 4482 // break it down into a new SETCC node, and a new SELECT node, and then return 4483 // the SELECT node, since we were called with a SELECT node. 4484 if (SCC.Val) { 4485 // Check to see if we got a select_cc back (to turn into setcc/select). 4486 // Otherwise, just return whatever node we got back, like fabs. 4487 if (SCC.getOpcode() == ISD::SELECT_CC) { 4488 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4489 SCC.getOperand(0), SCC.getOperand(1), 4490 SCC.getOperand(4)); 4491 AddToWorkList(SETCC.Val); 4492 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4493 SCC.getOperand(3), SETCC); 4494 } 4495 return SCC; 4496 } 4497 return SDOperand(); 4498} 4499 4500/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4501/// are the two values being selected between, see if we can simplify the 4502/// select. Callers of this should assume that TheSelect is deleted if this 4503/// returns true. As such, they should return the appropriate thing (e.g. the 4504/// node) back to the top-level of the DAG combiner loop to avoid it being 4505/// looked at. 4506/// 4507bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4508 SDOperand RHS) { 4509 4510 // If this is a select from two identical things, try to pull the operation 4511 // through the select. 4512 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4513 // If this is a load and the token chain is identical, replace the select 4514 // of two loads with a load through a select of the address to load from. 4515 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4516 // constants have been dropped into the constant pool. 4517 if (LHS.getOpcode() == ISD::LOAD && 4518 // Token chains must be identical. 4519 LHS.getOperand(0) == RHS.getOperand(0)) { 4520 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4521 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4522 4523 // If this is an EXTLOAD, the VT's must match. 4524 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4525 // FIXME: this conflates two src values, discarding one. This is not 4526 // the right thing to do, but nothing uses srcvalues now. When they do, 4527 // turn SrcValue into a list of locations. 4528 SDOperand Addr; 4529 if (TheSelect->getOpcode() == ISD::SELECT) { 4530 // Check that the condition doesn't reach either load. If so, folding 4531 // this will induce a cycle into the DAG. 4532 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4533 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4534 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4535 TheSelect->getOperand(0), LLD->getBasePtr(), 4536 RLD->getBasePtr()); 4537 } 4538 } else { 4539 // Check that the condition doesn't reach either load. If so, folding 4540 // this will induce a cycle into the DAG. 4541 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4542 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4543 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4544 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4545 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4546 TheSelect->getOperand(0), 4547 TheSelect->getOperand(1), 4548 LLD->getBasePtr(), RLD->getBasePtr(), 4549 TheSelect->getOperand(4)); 4550 } 4551 } 4552 4553 if (Addr.Val) { 4554 SDOperand Load; 4555 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4556 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4557 Addr,LLD->getSrcValue(), 4558 LLD->getSrcValueOffset(), 4559 LLD->isVolatile(), 4560 LLD->getAlignment()); 4561 else { 4562 Load = DAG.getExtLoad(LLD->getExtensionType(), 4563 TheSelect->getValueType(0), 4564 LLD->getChain(), Addr, LLD->getSrcValue(), 4565 LLD->getSrcValueOffset(), 4566 LLD->getLoadedVT(), 4567 LLD->isVolatile(), 4568 LLD->getAlignment()); 4569 } 4570 // Users of the select now use the result of the load. 4571 CombineTo(TheSelect, Load); 4572 4573 // Users of the old loads now use the new load's chain. We know the 4574 // old-load value is dead now. 4575 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4576 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4577 return true; 4578 } 4579 } 4580 } 4581 } 4582 4583 return false; 4584} 4585 4586SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4587 SDOperand N2, SDOperand N3, 4588 ISD::CondCode CC, bool NotExtCompare) { 4589 4590 MVT::ValueType VT = N2.getValueType(); 4591 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4592 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4593 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4594 4595 // Determine if the condition we're dealing with is constant 4596 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4597 if (SCC.Val) AddToWorkList(SCC.Val); 4598 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4599 4600 // fold select_cc true, x, y -> x 4601 if (SCCC && SCCC->getValue()) 4602 return N2; 4603 // fold select_cc false, x, y -> y 4604 if (SCCC && SCCC->getValue() == 0) 4605 return N3; 4606 4607 // Check to see if we can simplify the select into an fabs node 4608 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4609 // Allow either -0.0 or 0.0 4610 if (CFP->getValueAPF().isZero()) { 4611 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4612 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4613 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4614 N2 == N3.getOperand(0)) 4615 return DAG.getNode(ISD::FABS, VT, N0); 4616 4617 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4618 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4619 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4620 N2.getOperand(0) == N3) 4621 return DAG.getNode(ISD::FABS, VT, N3); 4622 } 4623 } 4624 4625 // Check to see if we can perform the "gzip trick", transforming 4626 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4627 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4628 MVT::isInteger(N0.getValueType()) && 4629 MVT::isInteger(N2.getValueType()) && 4630 (N1C->isNullValue() || // (a < 0) ? b : 0 4631 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4632 MVT::ValueType XType = N0.getValueType(); 4633 MVT::ValueType AType = N2.getValueType(); 4634 if (XType >= AType) { 4635 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4636 // single-bit constant. 4637 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4638 unsigned ShCtV = Log2_64(N2C->getValue()); 4639 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4640 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4641 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4642 AddToWorkList(Shift.Val); 4643 if (XType > AType) { 4644 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4645 AddToWorkList(Shift.Val); 4646 } 4647 return DAG.getNode(ISD::AND, AType, Shift, N2); 4648 } 4649 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4650 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4651 TLI.getShiftAmountTy())); 4652 AddToWorkList(Shift.Val); 4653 if (XType > AType) { 4654 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4655 AddToWorkList(Shift.Val); 4656 } 4657 return DAG.getNode(ISD::AND, AType, Shift, N2); 4658 } 4659 } 4660 4661 // fold select C, 16, 0 -> shl C, 4 4662 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4663 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4664 4665 // If the caller doesn't want us to simplify this into a zext of a compare, 4666 // don't do it. 4667 if (NotExtCompare && N2C->getValue() == 1) 4668 return SDOperand(); 4669 4670 // Get a SetCC of the condition 4671 // FIXME: Should probably make sure that setcc is legal if we ever have a 4672 // target where it isn't. 4673 SDOperand Temp, SCC; 4674 // cast from setcc result type to select result type 4675 if (AfterLegalize) { 4676 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4677 if (N2.getValueType() < SCC.getValueType()) 4678 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4679 else 4680 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4681 } else { 4682 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4683 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4684 } 4685 AddToWorkList(SCC.Val); 4686 AddToWorkList(Temp.Val); 4687 4688 if (N2C->getValue() == 1) 4689 return Temp; 4690 // shl setcc result by log2 n2c 4691 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4692 DAG.getConstant(Log2_64(N2C->getValue()), 4693 TLI.getShiftAmountTy())); 4694 } 4695 4696 // Check to see if this is the equivalent of setcc 4697 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4698 // otherwise, go ahead with the folds. 4699 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4700 MVT::ValueType XType = N0.getValueType(); 4701 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4702 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4703 if (Res.getValueType() != VT) 4704 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4705 return Res; 4706 } 4707 4708 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4709 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4710 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4711 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4712 return DAG.getNode(ISD::SRL, XType, Ctlz, 4713 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4714 TLI.getShiftAmountTy())); 4715 } 4716 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4717 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4718 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4719 N0); 4720 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4721 DAG.getConstant(~0ULL, XType)); 4722 return DAG.getNode(ISD::SRL, XType, 4723 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4724 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4725 TLI.getShiftAmountTy())); 4726 } 4727 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4728 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4729 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4730 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4731 TLI.getShiftAmountTy())); 4732 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4733 } 4734 } 4735 4736 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4737 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4738 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4739 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4740 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4741 MVT::ValueType XType = N0.getValueType(); 4742 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4743 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4744 TLI.getShiftAmountTy())); 4745 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4746 AddToWorkList(Shift.Val); 4747 AddToWorkList(Add.Val); 4748 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4749 } 4750 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4751 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4752 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4753 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4754 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4755 MVT::ValueType XType = N0.getValueType(); 4756 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4757 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4758 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4759 TLI.getShiftAmountTy())); 4760 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4761 AddToWorkList(Shift.Val); 4762 AddToWorkList(Add.Val); 4763 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4764 } 4765 } 4766 } 4767 4768 return SDOperand(); 4769} 4770 4771/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4772SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4773 SDOperand N1, ISD::CondCode Cond, 4774 bool foldBooleans) { 4775 TargetLowering::DAGCombinerInfo 4776 DagCombineInfo(DAG, !AfterLegalize, false, this); 4777 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4778} 4779 4780/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4781/// return a DAG expression to select that will generate the same value by 4782/// multiplying by a magic number. See: 4783/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4784SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4785 std::vector<SDNode*> Built; 4786 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4787 4788 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4789 ii != ee; ++ii) 4790 AddToWorkList(*ii); 4791 return S; 4792} 4793 4794/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4795/// return a DAG expression to select that will generate the same value by 4796/// multiplying by a magic number. See: 4797/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4798SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4799 std::vector<SDNode*> Built; 4800 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4801 4802 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4803 ii != ee; ++ii) 4804 AddToWorkList(*ii); 4805 return S; 4806} 4807 4808/// FindBaseOffset - Return true if base is known not to alias with anything 4809/// but itself. Provides base object and offset as results. 4810static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4811 // Assume it is a primitive operation. 4812 Base = Ptr; Offset = 0; 4813 4814 // If it's an adding a simple constant then integrate the offset. 4815 if (Base.getOpcode() == ISD::ADD) { 4816 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4817 Base = Base.getOperand(0); 4818 Offset += C->getValue(); 4819 } 4820 } 4821 4822 // If it's any of the following then it can't alias with anything but itself. 4823 return isa<FrameIndexSDNode>(Base) || 4824 isa<ConstantPoolSDNode>(Base) || 4825 isa<GlobalAddressSDNode>(Base); 4826} 4827 4828/// isAlias - Return true if there is any possibility that the two addresses 4829/// overlap. 4830bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4831 const Value *SrcValue1, int SrcValueOffset1, 4832 SDOperand Ptr2, int64_t Size2, 4833 const Value *SrcValue2, int SrcValueOffset2) 4834{ 4835 // If they are the same then they must be aliases. 4836 if (Ptr1 == Ptr2) return true; 4837 4838 // Gather base node and offset information. 4839 SDOperand Base1, Base2; 4840 int64_t Offset1, Offset2; 4841 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4842 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4843 4844 // If they have a same base address then... 4845 if (Base1 == Base2) { 4846 // Check to see if the addresses overlap. 4847 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4848 } 4849 4850 // If we know both bases then they can't alias. 4851 if (KnownBase1 && KnownBase2) return false; 4852 4853 if (CombinerGlobalAA) { 4854 // Use alias analysis information. 4855 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 4856 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 4857 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 4858 AliasAnalysis::AliasResult AAResult = 4859 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4860 if (AAResult == AliasAnalysis::NoAlias) 4861 return false; 4862 } 4863 4864 // Otherwise we have to assume they alias. 4865 return true; 4866} 4867 4868/// FindAliasInfo - Extracts the relevant alias information from the memory 4869/// node. Returns true if the operand was a load. 4870bool DAGCombiner::FindAliasInfo(SDNode *N, 4871 SDOperand &Ptr, int64_t &Size, 4872 const Value *&SrcValue, int &SrcValueOffset) { 4873 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4874 Ptr = LD->getBasePtr(); 4875 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4876 SrcValue = LD->getSrcValue(); 4877 SrcValueOffset = LD->getSrcValueOffset(); 4878 return true; 4879 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4880 Ptr = ST->getBasePtr(); 4881 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4882 SrcValue = ST->getSrcValue(); 4883 SrcValueOffset = ST->getSrcValueOffset(); 4884 } else { 4885 assert(0 && "FindAliasInfo expected a memory operand"); 4886 } 4887 4888 return false; 4889} 4890 4891/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4892/// looking for aliasing nodes and adding them to the Aliases vector. 4893void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4894 SmallVector<SDOperand, 8> &Aliases) { 4895 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4896 std::set<SDNode *> Visited; // Visited node set. 4897 4898 // Get alias information for node. 4899 SDOperand Ptr; 4900 int64_t Size; 4901 const Value *SrcValue; 4902 int SrcValueOffset; 4903 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4904 4905 // Starting off. 4906 Chains.push_back(OriginalChain); 4907 4908 // Look at each chain and determine if it is an alias. If so, add it to the 4909 // aliases list. If not, then continue up the chain looking for the next 4910 // candidate. 4911 while (!Chains.empty()) { 4912 SDOperand Chain = Chains.back(); 4913 Chains.pop_back(); 4914 4915 // Don't bother if we've been before. 4916 if (Visited.find(Chain.Val) != Visited.end()) continue; 4917 Visited.insert(Chain.Val); 4918 4919 switch (Chain.getOpcode()) { 4920 case ISD::EntryToken: 4921 // Entry token is ideal chain operand, but handled in FindBetterChain. 4922 break; 4923 4924 case ISD::LOAD: 4925 case ISD::STORE: { 4926 // Get alias information for Chain. 4927 SDOperand OpPtr; 4928 int64_t OpSize; 4929 const Value *OpSrcValue; 4930 int OpSrcValueOffset; 4931 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4932 OpSrcValue, OpSrcValueOffset); 4933 4934 // If chain is alias then stop here. 4935 if (!(IsLoad && IsOpLoad) && 4936 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4937 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4938 Aliases.push_back(Chain); 4939 } else { 4940 // Look further up the chain. 4941 Chains.push_back(Chain.getOperand(0)); 4942 // Clean up old chain. 4943 AddToWorkList(Chain.Val); 4944 } 4945 break; 4946 } 4947 4948 case ISD::TokenFactor: 4949 // We have to check each of the operands of the token factor, so we queue 4950 // then up. Adding the operands to the queue (stack) in reverse order 4951 // maintains the original order and increases the likelihood that getNode 4952 // will find a matching token factor (CSE.) 4953 for (unsigned n = Chain.getNumOperands(); n;) 4954 Chains.push_back(Chain.getOperand(--n)); 4955 // Eliminate the token factor if we can. 4956 AddToWorkList(Chain.Val); 4957 break; 4958 4959 default: 4960 // For all other instructions we will just have to take what we can get. 4961 Aliases.push_back(Chain); 4962 break; 4963 } 4964 } 4965} 4966 4967/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4968/// for a better chain (aliasing node.) 4969SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4970 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4971 4972 // Accumulate all the aliases to this node. 4973 GatherAllAliases(N, OldChain, Aliases); 4974 4975 if (Aliases.size() == 0) { 4976 // If no operands then chain to entry token. 4977 return DAG.getEntryNode(); 4978 } else if (Aliases.size() == 1) { 4979 // If a single operand then chain to it. We don't need to revisit it. 4980 return Aliases[0]; 4981 } 4982 4983 // Construct a custom tailored token factor. 4984 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4985 &Aliases[0], Aliases.size()); 4986 4987 // Make sure the old chain gets cleaned up. 4988 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4989 4990 return NewChain; 4991} 4992 4993// SelectionDAG::Combine - This is the entry point for the file. 4994// 4995void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4996 if (!RunningAfterLegalize && ViewDAGCombine1) 4997 viewGraph(); 4998 if (RunningAfterLegalize && ViewDAGCombine2) 4999 viewGraph(); 5000 /// run - This is the main entry point to this class. 5001 /// 5002 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5003} 5004