DAGCombiner.cpp revision 272ea0323999890d8bcf75b873a1c8ab2cdcba0d
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/DataLayout.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue SimplifyVUnaryOp(SDNode *N); 198 SDValue visitSHL(SDNode *N); 199 SDValue visitSRA(SDNode *N); 200 SDValue visitSRL(SDNode *N); 201 SDValue visitCTLZ(SDNode *N); 202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 203 SDValue visitCTTZ(SDNode *N); 204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 205 SDValue visitCTPOP(SDNode *N); 206 SDValue visitSELECT(SDNode *N); 207 SDValue visitSELECT_CC(SDNode *N); 208 SDValue visitSETCC(SDNode *N); 209 SDValue visitSIGN_EXTEND(SDNode *N); 210 SDValue visitZERO_EXTEND(SDNode *N); 211 SDValue visitANY_EXTEND(SDNode *N); 212 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 213 SDValue visitTRUNCATE(SDNode *N); 214 SDValue visitBITCAST(SDNode *N); 215 SDValue visitBUILD_PAIR(SDNode *N); 216 SDValue visitFADD(SDNode *N); 217 SDValue visitFSUB(SDNode *N); 218 SDValue visitFMUL(SDNode *N); 219 SDValue visitFMA(SDNode *N); 220 SDValue visitFDIV(SDNode *N); 221 SDValue visitFREM(SDNode *N); 222 SDValue visitFCOPYSIGN(SDNode *N); 223 SDValue visitSINT_TO_FP(SDNode *N); 224 SDValue visitUINT_TO_FP(SDNode *N); 225 SDValue visitFP_TO_SINT(SDNode *N); 226 SDValue visitFP_TO_UINT(SDNode *N); 227 SDValue visitFP_ROUND(SDNode *N); 228 SDValue visitFP_ROUND_INREG(SDNode *N); 229 SDValue visitFP_EXTEND(SDNode *N); 230 SDValue visitFNEG(SDNode *N); 231 SDValue visitFABS(SDNode *N); 232 SDValue visitFCEIL(SDNode *N); 233 SDValue visitFTRUNC(SDNode *N); 234 SDValue visitFFLOOR(SDNode *N); 235 SDValue visitBRCOND(SDNode *N); 236 SDValue visitBR_CC(SDNode *N); 237 SDValue visitLOAD(SDNode *N); 238 SDValue visitSTORE(SDNode *N); 239 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 241 SDValue visitBUILD_VECTOR(SDNode *N); 242 SDValue visitCONCAT_VECTORS(SDNode *N); 243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 244 SDValue visitVECTOR_SHUFFLE(SDNode *N); 245 SDValue visitMEMBARRIER(SDNode *N); 246 247 SDValue XformToShuffleWithZero(SDNode *N); 248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 249 250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 251 252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 256 SDValue N3, ISD::CondCode CC, 257 bool NotExtCompare = false); 258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 259 DebugLoc DL, bool foldBooleans = true); 260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 261 unsigned HiOp); 262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 264 SDValue BuildSDIV(SDNode *N); 265 SDValue BuildUDIV(SDNode *N); 266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 267 bool DemandHighBits = true); 268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 270 SDValue ReduceLoadWidth(SDNode *N); 271 SDValue ReduceLoadOpStoreWidth(SDNode *N); 272 SDValue TransformFPLoadStorePair(SDNode *N); 273 274 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 275 276 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 277 /// looking for aliasing nodes and adding them to the Aliases vector. 278 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 279 SmallVector<SDValue, 8> &Aliases); 280 281 /// isAlias - Return true if there is any possibility that the two addresses 282 /// overlap. 283 bool isAlias(SDValue Ptr1, int64_t Size1, 284 const Value *SrcValue1, int SrcValueOffset1, 285 unsigned SrcValueAlign1, 286 const MDNode *TBAAInfo1, 287 SDValue Ptr2, int64_t Size2, 288 const Value *SrcValue2, int SrcValueOffset2, 289 unsigned SrcValueAlign2, 290 const MDNode *TBAAInfo2) const; 291 292 /// FindAliasInfo - Extracts the relevant alias information from the memory 293 /// node. Returns true if the operand was a load. 294 bool FindAliasInfo(SDNode *N, 295 SDValue &Ptr, int64_t &Size, 296 const Value *&SrcValue, int &SrcValueOffset, 297 unsigned &SrcValueAlignment, 298 const MDNode *&TBAAInfo) const; 299 300 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 301 /// looking for a better chain (aliasing node.) 302 SDValue FindBetterChain(SDNode *N, SDValue Chain); 303 304 /// Merge consecutive store operations into a wide store. 305 /// This optimization uses wide integers or vectors when possible. 306 /// \return True if some memory operations were changed. 307 bool MergeConsecutiveStores(StoreSDNode *N); 308 309 public: 310 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 311 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 312 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 313 314 /// Run - runs the dag combiner on all nodes in the work list 315 void Run(CombineLevel AtLevel); 316 317 SelectionDAG &getDAG() const { return DAG; } 318 319 /// getShiftAmountTy - Returns a type large enough to hold any valid 320 /// shift amount - before type legalization these can be huge. 321 EVT getShiftAmountTy(EVT LHSTy) { 322 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 323 } 324 325 /// isTypeLegal - This method returns true if we are running before type 326 /// legalization or if the specified VT is legal. 327 bool isTypeLegal(const EVT &VT) { 328 if (!LegalTypes) return true; 329 return TLI.isTypeLegal(VT); 330 } 331 }; 332} 333 334 335namespace { 336/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 337/// nodes from the worklist. 338class WorkListRemover : public SelectionDAG::DAGUpdateListener { 339 DAGCombiner &DC; 340public: 341 explicit WorkListRemover(DAGCombiner &dc) 342 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 343 344 virtual void NodeDeleted(SDNode *N, SDNode *E) { 345 DC.removeFromWorkList(N); 346 } 347}; 348} 349 350//===----------------------------------------------------------------------===// 351// TargetLowering::DAGCombinerInfo implementation 352//===----------------------------------------------------------------------===// 353 354void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 355 ((DAGCombiner*)DC)->AddToWorkList(N); 356} 357 358void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 359 ((DAGCombiner*)DC)->removeFromWorkList(N); 360} 361 362SDValue TargetLowering::DAGCombinerInfo:: 363CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 364 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 365} 366 367SDValue TargetLowering::DAGCombinerInfo:: 368CombineTo(SDNode *N, SDValue Res, bool AddTo) { 369 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 370} 371 372 373SDValue TargetLowering::DAGCombinerInfo:: 374CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 375 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 376} 377 378void TargetLowering::DAGCombinerInfo:: 379CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 380 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 381} 382 383//===----------------------------------------------------------------------===// 384// Helper Functions 385//===----------------------------------------------------------------------===// 386 387/// isNegatibleForFree - Return 1 if we can compute the negated form of the 388/// specified expression for the same cost as the expression itself, or 2 if we 389/// can compute the negated form more cheaply than the expression itself. 390static char isNegatibleForFree(SDValue Op, bool LegalOperations, 391 const TargetLowering &TLI, 392 const TargetOptions *Options, 393 unsigned Depth = 0) { 394 // No compile time optimizations on this type. 395 if (Op.getValueType() == MVT::ppcf128) 396 return 0; 397 398 // fneg is removable even if it has multiple uses. 399 if (Op.getOpcode() == ISD::FNEG) return 2; 400 401 // Don't allow anything with multiple uses. 402 if (!Op.hasOneUse()) return 0; 403 404 // Don't recurse exponentially. 405 if (Depth > 6) return 0; 406 407 switch (Op.getOpcode()) { 408 default: return false; 409 case ISD::ConstantFP: 410 // Don't invert constant FP values after legalize. The negated constant 411 // isn't necessarily legal. 412 return LegalOperations ? 0 : 1; 413 case ISD::FADD: 414 // FIXME: determine better conditions for this xform. 415 if (!Options->UnsafeFPMath) return 0; 416 417 // After operation legalization, it might not be legal to create new FSUBs. 418 if (LegalOperations && 419 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 420 return 0; 421 422 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 423 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 424 Options, Depth + 1)) 425 return V; 426 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 427 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 428 Depth + 1); 429 case ISD::FSUB: 430 // We can't turn -(A-B) into B-A when we honor signed zeros. 431 if (!Options->UnsafeFPMath) return 0; 432 433 // fold (fneg (fsub A, B)) -> (fsub B, A) 434 return 1; 435 436 case ISD::FMUL: 437 case ISD::FDIV: 438 if (Options->HonorSignDependentRoundingFPMath()) return 0; 439 440 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 441 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 442 Options, Depth + 1)) 443 return V; 444 445 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 446 Depth + 1); 447 448 case ISD::FP_EXTEND: 449 case ISD::FP_ROUND: 450 case ISD::FSIN: 451 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 452 Depth + 1); 453 } 454} 455 456/// GetNegatedExpression - If isNegatibleForFree returns true, this function 457/// returns the newly negated expression. 458static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 459 bool LegalOperations, unsigned Depth = 0) { 460 // fneg is removable even if it has multiple uses. 461 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 462 463 // Don't allow anything with multiple uses. 464 assert(Op.hasOneUse() && "Unknown reuse!"); 465 466 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 467 switch (Op.getOpcode()) { 468 default: llvm_unreachable("Unknown code"); 469 case ISD::ConstantFP: { 470 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 471 V.changeSign(); 472 return DAG.getConstantFP(V, Op.getValueType()); 473 } 474 case ISD::FADD: 475 // FIXME: determine better conditions for this xform. 476 assert(DAG.getTarget().Options.UnsafeFPMath); 477 478 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 479 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 480 DAG.getTargetLoweringInfo(), 481 &DAG.getTarget().Options, Depth+1)) 482 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 483 GetNegatedExpression(Op.getOperand(0), DAG, 484 LegalOperations, Depth+1), 485 Op.getOperand(1)); 486 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 487 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 488 GetNegatedExpression(Op.getOperand(1), DAG, 489 LegalOperations, Depth+1), 490 Op.getOperand(0)); 491 case ISD::FSUB: 492 // We can't turn -(A-B) into B-A when we honor signed zeros. 493 assert(DAG.getTarget().Options.UnsafeFPMath); 494 495 // fold (fneg (fsub 0, B)) -> B 496 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 497 if (N0CFP->getValueAPF().isZero()) 498 return Op.getOperand(1); 499 500 // fold (fneg (fsub A, B)) -> (fsub B, A) 501 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 502 Op.getOperand(1), Op.getOperand(0)); 503 504 case ISD::FMUL: 505 case ISD::FDIV: 506 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 507 508 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 509 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 510 DAG.getTargetLoweringInfo(), 511 &DAG.getTarget().Options, Depth+1)) 512 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 513 GetNegatedExpression(Op.getOperand(0), DAG, 514 LegalOperations, Depth+1), 515 Op.getOperand(1)); 516 517 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 518 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 519 Op.getOperand(0), 520 GetNegatedExpression(Op.getOperand(1), DAG, 521 LegalOperations, Depth+1)); 522 523 case ISD::FP_EXTEND: 524 case ISD::FSIN: 525 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 526 GetNegatedExpression(Op.getOperand(0), DAG, 527 LegalOperations, Depth+1)); 528 case ISD::FP_ROUND: 529 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 530 GetNegatedExpression(Op.getOperand(0), DAG, 531 LegalOperations, Depth+1), 532 Op.getOperand(1)); 533 } 534} 535 536 537// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 538// that selects between the values 1 and 0, making it equivalent to a setcc. 539// Also, set the incoming LHS, RHS, and CC references to the appropriate 540// nodes based on the type of node we are checking. This simplifies life a 541// bit for the callers. 542static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 543 SDValue &CC) { 544 if (N.getOpcode() == ISD::SETCC) { 545 LHS = N.getOperand(0); 546 RHS = N.getOperand(1); 547 CC = N.getOperand(2); 548 return true; 549 } 550 if (N.getOpcode() == ISD::SELECT_CC && 551 N.getOperand(2).getOpcode() == ISD::Constant && 552 N.getOperand(3).getOpcode() == ISD::Constant && 553 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 554 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 555 LHS = N.getOperand(0); 556 RHS = N.getOperand(1); 557 CC = N.getOperand(4); 558 return true; 559 } 560 return false; 561} 562 563// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 564// one use. If this is true, it allows the users to invert the operation for 565// free when it is profitable to do so. 566static bool isOneUseSetCC(SDValue N) { 567 SDValue N0, N1, N2; 568 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 569 return true; 570 return false; 571} 572 573SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 574 SDValue N0, SDValue N1) { 575 EVT VT = N0.getValueType(); 576 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 577 if (isa<ConstantSDNode>(N1)) { 578 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 579 SDValue OpNode = 580 DAG.FoldConstantArithmetic(Opc, VT, 581 cast<ConstantSDNode>(N0.getOperand(1)), 582 cast<ConstantSDNode>(N1)); 583 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 584 } 585 if (N0.hasOneUse()) { 586 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 587 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 588 N0.getOperand(0), N1); 589 AddToWorkList(OpNode.getNode()); 590 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 591 } 592 } 593 594 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 595 if (isa<ConstantSDNode>(N0)) { 596 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 597 SDValue OpNode = 598 DAG.FoldConstantArithmetic(Opc, VT, 599 cast<ConstantSDNode>(N1.getOperand(1)), 600 cast<ConstantSDNode>(N0)); 601 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 602 } 603 if (N1.hasOneUse()) { 604 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 605 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 606 N1.getOperand(0), N0); 607 AddToWorkList(OpNode.getNode()); 608 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 609 } 610 } 611 612 return SDValue(); 613} 614 615SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 616 bool AddTo) { 617 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 618 ++NodesCombined; 619 DEBUG(dbgs() << "\nReplacing.1 "; 620 N->dump(&DAG); 621 dbgs() << "\nWith: "; 622 To[0].getNode()->dump(&DAG); 623 dbgs() << " and " << NumTo-1 << " other values\n"; 624 for (unsigned i = 0, e = NumTo; i != e; ++i) 625 assert((!To[i].getNode() || 626 N->getValueType(i) == To[i].getValueType()) && 627 "Cannot combine value to value of different type!")); 628 WorkListRemover DeadNodes(*this); 629 DAG.ReplaceAllUsesWith(N, To); 630 if (AddTo) { 631 // Push the new nodes and any users onto the worklist 632 for (unsigned i = 0, e = NumTo; i != e; ++i) { 633 if (To[i].getNode()) { 634 AddToWorkList(To[i].getNode()); 635 AddUsersToWorkList(To[i].getNode()); 636 } 637 } 638 } 639 640 // Finally, if the node is now dead, remove it from the graph. The node 641 // may not be dead if the replacement process recursively simplified to 642 // something else needing this node. 643 if (N->use_empty()) { 644 // Nodes can be reintroduced into the worklist. Make sure we do not 645 // process a node that has been replaced. 646 removeFromWorkList(N); 647 648 // Finally, since the node is now dead, remove it from the graph. 649 DAG.DeleteNode(N); 650 } 651 return SDValue(N, 0); 652} 653 654void DAGCombiner:: 655CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 656 // Replace all uses. If any nodes become isomorphic to other nodes and 657 // are deleted, make sure to remove them from our worklist. 658 WorkListRemover DeadNodes(*this); 659 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 660 661 // Push the new node and any (possibly new) users onto the worklist. 662 AddToWorkList(TLO.New.getNode()); 663 AddUsersToWorkList(TLO.New.getNode()); 664 665 // Finally, if the node is now dead, remove it from the graph. The node 666 // may not be dead if the replacement process recursively simplified to 667 // something else needing this node. 668 if (TLO.Old.getNode()->use_empty()) { 669 removeFromWorkList(TLO.Old.getNode()); 670 671 // If the operands of this node are only used by the node, they will now 672 // be dead. Make sure to visit them first to delete dead nodes early. 673 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 674 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 675 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 676 677 DAG.DeleteNode(TLO.Old.getNode()); 678 } 679} 680 681/// SimplifyDemandedBits - Check the specified integer node value to see if 682/// it can be simplified or if things it uses can be simplified by bit 683/// propagation. If so, return true. 684bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 685 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 686 APInt KnownZero, KnownOne; 687 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 688 return false; 689 690 // Revisit the node. 691 AddToWorkList(Op.getNode()); 692 693 // Replace the old value with the new one. 694 ++NodesCombined; 695 DEBUG(dbgs() << "\nReplacing.2 "; 696 TLO.Old.getNode()->dump(&DAG); 697 dbgs() << "\nWith: "; 698 TLO.New.getNode()->dump(&DAG); 699 dbgs() << '\n'); 700 701 CommitTargetLoweringOpt(TLO); 702 return true; 703} 704 705void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 706 DebugLoc dl = Load->getDebugLoc(); 707 EVT VT = Load->getValueType(0); 708 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 709 710 DEBUG(dbgs() << "\nReplacing.9 "; 711 Load->dump(&DAG); 712 dbgs() << "\nWith: "; 713 Trunc.getNode()->dump(&DAG); 714 dbgs() << '\n'); 715 WorkListRemover DeadNodes(*this); 716 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 717 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 718 removeFromWorkList(Load); 719 DAG.DeleteNode(Load); 720 AddToWorkList(Trunc.getNode()); 721} 722 723SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 724 Replace = false; 725 DebugLoc dl = Op.getDebugLoc(); 726 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 727 EVT MemVT = LD->getMemoryVT(); 728 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 729 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 730 : ISD::EXTLOAD) 731 : LD->getExtensionType(); 732 Replace = true; 733 return DAG.getExtLoad(ExtType, dl, PVT, 734 LD->getChain(), LD->getBasePtr(), 735 LD->getPointerInfo(), 736 MemVT, LD->isVolatile(), 737 LD->isNonTemporal(), LD->getAlignment()); 738 } 739 740 unsigned Opc = Op.getOpcode(); 741 switch (Opc) { 742 default: break; 743 case ISD::AssertSext: 744 return DAG.getNode(ISD::AssertSext, dl, PVT, 745 SExtPromoteOperand(Op.getOperand(0), PVT), 746 Op.getOperand(1)); 747 case ISD::AssertZext: 748 return DAG.getNode(ISD::AssertZext, dl, PVT, 749 ZExtPromoteOperand(Op.getOperand(0), PVT), 750 Op.getOperand(1)); 751 case ISD::Constant: { 752 unsigned ExtOpc = 753 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 754 return DAG.getNode(ExtOpc, dl, PVT, Op); 755 } 756 } 757 758 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 759 return SDValue(); 760 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 761} 762 763SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 764 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 765 return SDValue(); 766 EVT OldVT = Op.getValueType(); 767 DebugLoc dl = Op.getDebugLoc(); 768 bool Replace = false; 769 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 770 if (NewOp.getNode() == 0) 771 return SDValue(); 772 AddToWorkList(NewOp.getNode()); 773 774 if (Replace) 775 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 776 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 777 DAG.getValueType(OldVT)); 778} 779 780SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 781 EVT OldVT = Op.getValueType(); 782 DebugLoc dl = Op.getDebugLoc(); 783 bool Replace = false; 784 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 785 if (NewOp.getNode() == 0) 786 return SDValue(); 787 AddToWorkList(NewOp.getNode()); 788 789 if (Replace) 790 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 791 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 792} 793 794/// PromoteIntBinOp - Promote the specified integer binary operation if the 795/// target indicates it is beneficial. e.g. On x86, it's usually better to 796/// promote i16 operations to i32 since i16 instructions are longer. 797SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 798 if (!LegalOperations) 799 return SDValue(); 800 801 EVT VT = Op.getValueType(); 802 if (VT.isVector() || !VT.isInteger()) 803 return SDValue(); 804 805 // If operation type is 'undesirable', e.g. i16 on x86, consider 806 // promoting it. 807 unsigned Opc = Op.getOpcode(); 808 if (TLI.isTypeDesirableForOp(Opc, VT)) 809 return SDValue(); 810 811 EVT PVT = VT; 812 // Consult target whether it is a good idea to promote this operation and 813 // what's the right type to promote it to. 814 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 815 assert(PVT != VT && "Don't know what type to promote to!"); 816 817 bool Replace0 = false; 818 SDValue N0 = Op.getOperand(0); 819 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 820 if (NN0.getNode() == 0) 821 return SDValue(); 822 823 bool Replace1 = false; 824 SDValue N1 = Op.getOperand(1); 825 SDValue NN1; 826 if (N0 == N1) 827 NN1 = NN0; 828 else { 829 NN1 = PromoteOperand(N1, PVT, Replace1); 830 if (NN1.getNode() == 0) 831 return SDValue(); 832 } 833 834 AddToWorkList(NN0.getNode()); 835 if (NN1.getNode()) 836 AddToWorkList(NN1.getNode()); 837 838 if (Replace0) 839 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 840 if (Replace1) 841 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 842 843 DEBUG(dbgs() << "\nPromoting "; 844 Op.getNode()->dump(&DAG)); 845 DebugLoc dl = Op.getDebugLoc(); 846 return DAG.getNode(ISD::TRUNCATE, dl, VT, 847 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 848 } 849 return SDValue(); 850} 851 852/// PromoteIntShiftOp - Promote the specified integer shift operation if the 853/// target indicates it is beneficial. e.g. On x86, it's usually better to 854/// promote i16 operations to i32 since i16 instructions are longer. 855SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 856 if (!LegalOperations) 857 return SDValue(); 858 859 EVT VT = Op.getValueType(); 860 if (VT.isVector() || !VT.isInteger()) 861 return SDValue(); 862 863 // If operation type is 'undesirable', e.g. i16 on x86, consider 864 // promoting it. 865 unsigned Opc = Op.getOpcode(); 866 if (TLI.isTypeDesirableForOp(Opc, VT)) 867 return SDValue(); 868 869 EVT PVT = VT; 870 // Consult target whether it is a good idea to promote this operation and 871 // what's the right type to promote it to. 872 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 873 assert(PVT != VT && "Don't know what type to promote to!"); 874 875 bool Replace = false; 876 SDValue N0 = Op.getOperand(0); 877 if (Opc == ISD::SRA) 878 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 879 else if (Opc == ISD::SRL) 880 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 881 else 882 N0 = PromoteOperand(N0, PVT, Replace); 883 if (N0.getNode() == 0) 884 return SDValue(); 885 886 AddToWorkList(N0.getNode()); 887 if (Replace) 888 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 889 890 DEBUG(dbgs() << "\nPromoting "; 891 Op.getNode()->dump(&DAG)); 892 DebugLoc dl = Op.getDebugLoc(); 893 return DAG.getNode(ISD::TRUNCATE, dl, VT, 894 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 895 } 896 return SDValue(); 897} 898 899SDValue DAGCombiner::PromoteExtend(SDValue Op) { 900 if (!LegalOperations) 901 return SDValue(); 902 903 EVT VT = Op.getValueType(); 904 if (VT.isVector() || !VT.isInteger()) 905 return SDValue(); 906 907 // If operation type is 'undesirable', e.g. i16 on x86, consider 908 // promoting it. 909 unsigned Opc = Op.getOpcode(); 910 if (TLI.isTypeDesirableForOp(Opc, VT)) 911 return SDValue(); 912 913 EVT PVT = VT; 914 // Consult target whether it is a good idea to promote this operation and 915 // what's the right type to promote it to. 916 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 917 assert(PVT != VT && "Don't know what type to promote to!"); 918 // fold (aext (aext x)) -> (aext x) 919 // fold (aext (zext x)) -> (zext x) 920 // fold (aext (sext x)) -> (sext x) 921 DEBUG(dbgs() << "\nPromoting "; 922 Op.getNode()->dump(&DAG)); 923 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 924 } 925 return SDValue(); 926} 927 928bool DAGCombiner::PromoteLoad(SDValue Op) { 929 if (!LegalOperations) 930 return false; 931 932 EVT VT = Op.getValueType(); 933 if (VT.isVector() || !VT.isInteger()) 934 return false; 935 936 // If operation type is 'undesirable', e.g. i16 on x86, consider 937 // promoting it. 938 unsigned Opc = Op.getOpcode(); 939 if (TLI.isTypeDesirableForOp(Opc, VT)) 940 return false; 941 942 EVT PVT = VT; 943 // Consult target whether it is a good idea to promote this operation and 944 // what's the right type to promote it to. 945 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 946 assert(PVT != VT && "Don't know what type to promote to!"); 947 948 DebugLoc dl = Op.getDebugLoc(); 949 SDNode *N = Op.getNode(); 950 LoadSDNode *LD = cast<LoadSDNode>(N); 951 EVT MemVT = LD->getMemoryVT(); 952 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 953 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 954 : ISD::EXTLOAD) 955 : LD->getExtensionType(); 956 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 957 LD->getChain(), LD->getBasePtr(), 958 LD->getPointerInfo(), 959 MemVT, LD->isVolatile(), 960 LD->isNonTemporal(), LD->getAlignment()); 961 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 962 963 DEBUG(dbgs() << "\nPromoting "; 964 N->dump(&DAG); 965 dbgs() << "\nTo: "; 966 Result.getNode()->dump(&DAG); 967 dbgs() << '\n'); 968 WorkListRemover DeadNodes(*this); 969 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 970 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 971 removeFromWorkList(N); 972 DAG.DeleteNode(N); 973 AddToWorkList(Result.getNode()); 974 return true; 975 } 976 return false; 977} 978 979 980//===----------------------------------------------------------------------===// 981// Main DAG Combiner implementation 982//===----------------------------------------------------------------------===// 983 984void DAGCombiner::Run(CombineLevel AtLevel) { 985 // set the instance variables, so that the various visit routines may use it. 986 Level = AtLevel; 987 LegalOperations = Level >= AfterLegalizeVectorOps; 988 LegalTypes = Level >= AfterLegalizeTypes; 989 990 // Add all the dag nodes to the worklist. 991 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 992 E = DAG.allnodes_end(); I != E; ++I) 993 AddToWorkList(I); 994 995 // Create a dummy node (which is not added to allnodes), that adds a reference 996 // to the root node, preventing it from being deleted, and tracking any 997 // changes of the root. 998 HandleSDNode Dummy(DAG.getRoot()); 999 1000 // The root of the dag may dangle to deleted nodes until the dag combiner is 1001 // done. Set it to null to avoid confusion. 1002 DAG.setRoot(SDValue()); 1003 1004 // while the worklist isn't empty, find a node and 1005 // try and combine it. 1006 while (!WorkListContents.empty()) { 1007 SDNode *N; 1008 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1009 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1010 // worklist *should* contain, and check the node we want to visit is should 1011 // actually be visited. 1012 do { 1013 N = WorkListOrder.pop_back_val(); 1014 } while (!WorkListContents.erase(N)); 1015 1016 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1017 // N is deleted from the DAG, since they too may now be dead or may have a 1018 // reduced number of uses, allowing other xforms. 1019 if (N->use_empty() && N != &Dummy) { 1020 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1021 AddToWorkList(N->getOperand(i).getNode()); 1022 1023 DAG.DeleteNode(N); 1024 continue; 1025 } 1026 1027 SDValue RV = combine(N); 1028 1029 if (RV.getNode() == 0) 1030 continue; 1031 1032 ++NodesCombined; 1033 1034 // If we get back the same node we passed in, rather than a new node or 1035 // zero, we know that the node must have defined multiple values and 1036 // CombineTo was used. Since CombineTo takes care of the worklist 1037 // mechanics for us, we have no work to do in this case. 1038 if (RV.getNode() == N) 1039 continue; 1040 1041 assert(N->getOpcode() != ISD::DELETED_NODE && 1042 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1043 "Node was deleted but visit returned new node!"); 1044 1045 DEBUG(dbgs() << "\nReplacing.3 "; 1046 N->dump(&DAG); 1047 dbgs() << "\nWith: "; 1048 RV.getNode()->dump(&DAG); 1049 dbgs() << '\n'); 1050 1051 // Transfer debug value. 1052 DAG.TransferDbgValues(SDValue(N, 0), RV); 1053 WorkListRemover DeadNodes(*this); 1054 if (N->getNumValues() == RV.getNode()->getNumValues()) 1055 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1056 else { 1057 assert(N->getValueType(0) == RV.getValueType() && 1058 N->getNumValues() == 1 && "Type mismatch"); 1059 SDValue OpV = RV; 1060 DAG.ReplaceAllUsesWith(N, &OpV); 1061 } 1062 1063 // Push the new node and any users onto the worklist 1064 AddToWorkList(RV.getNode()); 1065 AddUsersToWorkList(RV.getNode()); 1066 1067 // Add any uses of the old node to the worklist in case this node is the 1068 // last one that uses them. They may become dead after this node is 1069 // deleted. 1070 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1071 AddToWorkList(N->getOperand(i).getNode()); 1072 1073 // Finally, if the node is now dead, remove it from the graph. The node 1074 // may not be dead if the replacement process recursively simplified to 1075 // something else needing this node. 1076 if (N->use_empty()) { 1077 // Nodes can be reintroduced into the worklist. Make sure we do not 1078 // process a node that has been replaced. 1079 removeFromWorkList(N); 1080 1081 // Finally, since the node is now dead, remove it from the graph. 1082 DAG.DeleteNode(N); 1083 } 1084 } 1085 1086 // If the root changed (e.g. it was a dead load, update the root). 1087 DAG.setRoot(Dummy.getValue()); 1088 DAG.RemoveDeadNodes(); 1089} 1090 1091SDValue DAGCombiner::visit(SDNode *N) { 1092 switch (N->getOpcode()) { 1093 default: break; 1094 case ISD::TokenFactor: return visitTokenFactor(N); 1095 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1096 case ISD::ADD: return visitADD(N); 1097 case ISD::SUB: return visitSUB(N); 1098 case ISD::ADDC: return visitADDC(N); 1099 case ISD::SUBC: return visitSUBC(N); 1100 case ISD::ADDE: return visitADDE(N); 1101 case ISD::SUBE: return visitSUBE(N); 1102 case ISD::MUL: return visitMUL(N); 1103 case ISD::SDIV: return visitSDIV(N); 1104 case ISD::UDIV: return visitUDIV(N); 1105 case ISD::SREM: return visitSREM(N); 1106 case ISD::UREM: return visitUREM(N); 1107 case ISD::MULHU: return visitMULHU(N); 1108 case ISD::MULHS: return visitMULHS(N); 1109 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1110 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1111 case ISD::SMULO: return visitSMULO(N); 1112 case ISD::UMULO: return visitUMULO(N); 1113 case ISD::SDIVREM: return visitSDIVREM(N); 1114 case ISD::UDIVREM: return visitUDIVREM(N); 1115 case ISD::AND: return visitAND(N); 1116 case ISD::OR: return visitOR(N); 1117 case ISD::XOR: return visitXOR(N); 1118 case ISD::SHL: return visitSHL(N); 1119 case ISD::SRA: return visitSRA(N); 1120 case ISD::SRL: return visitSRL(N); 1121 case ISD::CTLZ: return visitCTLZ(N); 1122 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1123 case ISD::CTTZ: return visitCTTZ(N); 1124 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1125 case ISD::CTPOP: return visitCTPOP(N); 1126 case ISD::SELECT: return visitSELECT(N); 1127 case ISD::SELECT_CC: return visitSELECT_CC(N); 1128 case ISD::SETCC: return visitSETCC(N); 1129 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1130 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1131 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1132 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1133 case ISD::TRUNCATE: return visitTRUNCATE(N); 1134 case ISD::BITCAST: return visitBITCAST(N); 1135 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1136 case ISD::FADD: return visitFADD(N); 1137 case ISD::FSUB: return visitFSUB(N); 1138 case ISD::FMUL: return visitFMUL(N); 1139 case ISD::FMA: return visitFMA(N); 1140 case ISD::FDIV: return visitFDIV(N); 1141 case ISD::FREM: return visitFREM(N); 1142 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1143 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1144 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1145 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1146 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1147 case ISD::FP_ROUND: return visitFP_ROUND(N); 1148 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1149 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1150 case ISD::FNEG: return visitFNEG(N); 1151 case ISD::FABS: return visitFABS(N); 1152 case ISD::FFLOOR: return visitFFLOOR(N); 1153 case ISD::FCEIL: return visitFCEIL(N); 1154 case ISD::FTRUNC: return visitFTRUNC(N); 1155 case ISD::BRCOND: return visitBRCOND(N); 1156 case ISD::BR_CC: return visitBR_CC(N); 1157 case ISD::LOAD: return visitLOAD(N); 1158 case ISD::STORE: return visitSTORE(N); 1159 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1160 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1161 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1162 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1163 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1164 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1165 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1166 } 1167 return SDValue(); 1168} 1169 1170SDValue DAGCombiner::combine(SDNode *N) { 1171 SDValue RV = visit(N); 1172 1173 // If nothing happened, try a target-specific DAG combine. 1174 if (RV.getNode() == 0) { 1175 assert(N->getOpcode() != ISD::DELETED_NODE && 1176 "Node was deleted but visit returned NULL!"); 1177 1178 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1179 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1180 1181 // Expose the DAG combiner to the target combiner impls. 1182 TargetLowering::DAGCombinerInfo 1183 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1184 1185 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1186 } 1187 } 1188 1189 // If nothing happened still, try promoting the operation. 1190 if (RV.getNode() == 0) { 1191 switch (N->getOpcode()) { 1192 default: break; 1193 case ISD::ADD: 1194 case ISD::SUB: 1195 case ISD::MUL: 1196 case ISD::AND: 1197 case ISD::OR: 1198 case ISD::XOR: 1199 RV = PromoteIntBinOp(SDValue(N, 0)); 1200 break; 1201 case ISD::SHL: 1202 case ISD::SRA: 1203 case ISD::SRL: 1204 RV = PromoteIntShiftOp(SDValue(N, 0)); 1205 break; 1206 case ISD::SIGN_EXTEND: 1207 case ISD::ZERO_EXTEND: 1208 case ISD::ANY_EXTEND: 1209 RV = PromoteExtend(SDValue(N, 0)); 1210 break; 1211 case ISD::LOAD: 1212 if (PromoteLoad(SDValue(N, 0))) 1213 RV = SDValue(N, 0); 1214 break; 1215 } 1216 } 1217 1218 // If N is a commutative binary node, try commuting it to enable more 1219 // sdisel CSE. 1220 if (RV.getNode() == 0 && 1221 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1222 N->getNumValues() == 1) { 1223 SDValue N0 = N->getOperand(0); 1224 SDValue N1 = N->getOperand(1); 1225 1226 // Constant operands are canonicalized to RHS. 1227 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1228 SDValue Ops[] = { N1, N0 }; 1229 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1230 Ops, 2); 1231 if (CSENode) 1232 return SDValue(CSENode, 0); 1233 } 1234 } 1235 1236 return RV; 1237} 1238 1239/// getInputChainForNode - Given a node, return its input chain if it has one, 1240/// otherwise return a null sd operand. 1241static SDValue getInputChainForNode(SDNode *N) { 1242 if (unsigned NumOps = N->getNumOperands()) { 1243 if (N->getOperand(0).getValueType() == MVT::Other) 1244 return N->getOperand(0); 1245 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1246 return N->getOperand(NumOps-1); 1247 for (unsigned i = 1; i < NumOps-1; ++i) 1248 if (N->getOperand(i).getValueType() == MVT::Other) 1249 return N->getOperand(i); 1250 } 1251 return SDValue(); 1252} 1253 1254SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1255 // If N has two operands, where one has an input chain equal to the other, 1256 // the 'other' chain is redundant. 1257 if (N->getNumOperands() == 2) { 1258 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1259 return N->getOperand(0); 1260 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1261 return N->getOperand(1); 1262 } 1263 1264 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1265 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1266 SmallPtrSet<SDNode*, 16> SeenOps; 1267 bool Changed = false; // If we should replace this token factor. 1268 1269 // Start out with this token factor. 1270 TFs.push_back(N); 1271 1272 // Iterate through token factors. The TFs grows when new token factors are 1273 // encountered. 1274 for (unsigned i = 0; i < TFs.size(); ++i) { 1275 SDNode *TF = TFs[i]; 1276 1277 // Check each of the operands. 1278 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1279 SDValue Op = TF->getOperand(i); 1280 1281 switch (Op.getOpcode()) { 1282 case ISD::EntryToken: 1283 // Entry tokens don't need to be added to the list. They are 1284 // rededundant. 1285 Changed = true; 1286 break; 1287 1288 case ISD::TokenFactor: 1289 if (Op.hasOneUse() && 1290 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1291 // Queue up for processing. 1292 TFs.push_back(Op.getNode()); 1293 // Clean up in case the token factor is removed. 1294 AddToWorkList(Op.getNode()); 1295 Changed = true; 1296 break; 1297 } 1298 // Fall thru 1299 1300 default: 1301 // Only add if it isn't already in the list. 1302 if (SeenOps.insert(Op.getNode())) 1303 Ops.push_back(Op); 1304 else 1305 Changed = true; 1306 break; 1307 } 1308 } 1309 } 1310 1311 SDValue Result; 1312 1313 // If we've change things around then replace token factor. 1314 if (Changed) { 1315 if (Ops.empty()) { 1316 // The entry token is the only possible outcome. 1317 Result = DAG.getEntryNode(); 1318 } else { 1319 // New and improved token factor. 1320 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1321 MVT::Other, &Ops[0], Ops.size()); 1322 } 1323 1324 // Don't add users to work list. 1325 return CombineTo(N, Result, false); 1326 } 1327 1328 return Result; 1329} 1330 1331/// MERGE_VALUES can always be eliminated. 1332SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1333 WorkListRemover DeadNodes(*this); 1334 // Replacing results may cause a different MERGE_VALUES to suddenly 1335 // be CSE'd with N, and carry its uses with it. Iterate until no 1336 // uses remain, to ensure that the node can be safely deleted. 1337 // First add the users of this node to the work list so that they 1338 // can be tried again once they have new operands. 1339 AddUsersToWorkList(N); 1340 do { 1341 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1342 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1343 } while (!N->use_empty()); 1344 removeFromWorkList(N); 1345 DAG.DeleteNode(N); 1346 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1347} 1348 1349static 1350SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1351 SelectionDAG &DAG) { 1352 EVT VT = N0.getValueType(); 1353 SDValue N00 = N0.getOperand(0); 1354 SDValue N01 = N0.getOperand(1); 1355 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1356 1357 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1358 isa<ConstantSDNode>(N00.getOperand(1))) { 1359 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1360 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1361 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1362 N00.getOperand(0), N01), 1363 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1364 N00.getOperand(1), N01)); 1365 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1366 } 1367 1368 return SDValue(); 1369} 1370 1371SDValue DAGCombiner::visitADD(SDNode *N) { 1372 SDValue N0 = N->getOperand(0); 1373 SDValue N1 = N->getOperand(1); 1374 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1375 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1376 EVT VT = N0.getValueType(); 1377 1378 // fold vector ops 1379 if (VT.isVector()) { 1380 SDValue FoldedVOp = SimplifyVBinOp(N); 1381 if (FoldedVOp.getNode()) return FoldedVOp; 1382 } 1383 1384 // fold (add x, undef) -> undef 1385 if (N0.getOpcode() == ISD::UNDEF) 1386 return N0; 1387 if (N1.getOpcode() == ISD::UNDEF) 1388 return N1; 1389 // fold (add c1, c2) -> c1+c2 1390 if (N0C && N1C) 1391 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1392 // canonicalize constant to RHS 1393 if (N0C && !N1C) 1394 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1395 // fold (add x, 0) -> x 1396 if (N1C && N1C->isNullValue()) 1397 return N0; 1398 // fold (add Sym, c) -> Sym+c 1399 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1400 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1401 GA->getOpcode() == ISD::GlobalAddress) 1402 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1403 GA->getOffset() + 1404 (uint64_t)N1C->getSExtValue()); 1405 // fold ((c1-A)+c2) -> (c1+c2)-A 1406 if (N1C && N0.getOpcode() == ISD::SUB) 1407 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1408 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1409 DAG.getConstant(N1C->getAPIntValue()+ 1410 N0C->getAPIntValue(), VT), 1411 N0.getOperand(1)); 1412 // reassociate add 1413 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1414 if (RADD.getNode() != 0) 1415 return RADD; 1416 // fold ((0-A) + B) -> B-A 1417 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1418 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1419 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1420 // fold (A + (0-B)) -> A-B 1421 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1422 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1423 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1424 // fold (A+(B-A)) -> B 1425 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1426 return N1.getOperand(0); 1427 // fold ((B-A)+A) -> B 1428 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1429 return N0.getOperand(0); 1430 // fold (A+(B-(A+C))) to (B-C) 1431 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1432 N0 == N1.getOperand(1).getOperand(0)) 1433 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1434 N1.getOperand(1).getOperand(1)); 1435 // fold (A+(B-(C+A))) to (B-C) 1436 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1437 N0 == N1.getOperand(1).getOperand(1)) 1438 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1439 N1.getOperand(1).getOperand(0)); 1440 // fold (A+((B-A)+or-C)) to (B+or-C) 1441 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1442 N1.getOperand(0).getOpcode() == ISD::SUB && 1443 N0 == N1.getOperand(0).getOperand(1)) 1444 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1445 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1446 1447 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1448 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1449 SDValue N00 = N0.getOperand(0); 1450 SDValue N01 = N0.getOperand(1); 1451 SDValue N10 = N1.getOperand(0); 1452 SDValue N11 = N1.getOperand(1); 1453 1454 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1455 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1456 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1457 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1458 } 1459 1460 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1461 return SDValue(N, 0); 1462 1463 // fold (a+b) -> (a|b) iff a and b share no bits. 1464 if (VT.isInteger() && !VT.isVector()) { 1465 APInt LHSZero, LHSOne; 1466 APInt RHSZero, RHSOne; 1467 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1468 1469 if (LHSZero.getBoolValue()) { 1470 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1471 1472 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1473 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1474 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1475 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1476 } 1477 } 1478 1479 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1480 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1481 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1482 if (Result.getNode()) return Result; 1483 } 1484 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1485 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1486 if (Result.getNode()) return Result; 1487 } 1488 1489 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1490 if (N1.getOpcode() == ISD::SHL && 1491 N1.getOperand(0).getOpcode() == ISD::SUB) 1492 if (ConstantSDNode *C = 1493 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1494 if (C->getAPIntValue() == 0) 1495 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1496 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1497 N1.getOperand(0).getOperand(1), 1498 N1.getOperand(1))); 1499 if (N0.getOpcode() == ISD::SHL && 1500 N0.getOperand(0).getOpcode() == ISD::SUB) 1501 if (ConstantSDNode *C = 1502 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1503 if (C->getAPIntValue() == 0) 1504 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1505 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1506 N0.getOperand(0).getOperand(1), 1507 N0.getOperand(1))); 1508 1509 if (N1.getOpcode() == ISD::AND) { 1510 SDValue AndOp0 = N1.getOperand(0); 1511 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1512 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1513 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1514 1515 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1516 // and similar xforms where the inner op is either ~0 or 0. 1517 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1518 DebugLoc DL = N->getDebugLoc(); 1519 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1520 } 1521 } 1522 1523 // add (sext i1), X -> sub X, (zext i1) 1524 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1525 N0.getOperand(0).getValueType() == MVT::i1 && 1526 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1527 DebugLoc DL = N->getDebugLoc(); 1528 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1529 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1530 } 1531 1532 return SDValue(); 1533} 1534 1535SDValue DAGCombiner::visitADDC(SDNode *N) { 1536 SDValue N0 = N->getOperand(0); 1537 SDValue N1 = N->getOperand(1); 1538 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1539 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1540 EVT VT = N0.getValueType(); 1541 1542 // If the flag result is dead, turn this into an ADD. 1543 if (!N->hasAnyUseOfValue(1)) 1544 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1545 DAG.getNode(ISD::CARRY_FALSE, 1546 N->getDebugLoc(), MVT::Glue)); 1547 1548 // canonicalize constant to RHS. 1549 if (N0C && !N1C) 1550 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1551 1552 // fold (addc x, 0) -> x + no carry out 1553 if (N1C && N1C->isNullValue()) 1554 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1555 N->getDebugLoc(), MVT::Glue)); 1556 1557 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1558 APInt LHSZero, LHSOne; 1559 APInt RHSZero, RHSOne; 1560 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1561 1562 if (LHSZero.getBoolValue()) { 1563 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1564 1565 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1566 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1567 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1568 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1569 DAG.getNode(ISD::CARRY_FALSE, 1570 N->getDebugLoc(), MVT::Glue)); 1571 } 1572 1573 return SDValue(); 1574} 1575 1576SDValue DAGCombiner::visitADDE(SDNode *N) { 1577 SDValue N0 = N->getOperand(0); 1578 SDValue N1 = N->getOperand(1); 1579 SDValue CarryIn = N->getOperand(2); 1580 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1581 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1582 1583 // canonicalize constant to RHS 1584 if (N0C && !N1C) 1585 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1586 N1, N0, CarryIn); 1587 1588 // fold (adde x, y, false) -> (addc x, y) 1589 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1590 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1591 1592 return SDValue(); 1593} 1594 1595// Since it may not be valid to emit a fold to zero for vector initializers 1596// check if we can before folding. 1597static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1598 SelectionDAG &DAG, bool LegalOperations) { 1599 if (!VT.isVector()) { 1600 return DAG.getConstant(0, VT); 1601 } 1602 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1603 // Produce a vector of zeros. 1604 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1605 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1606 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1607 &Ops[0], Ops.size()); 1608 } 1609 return SDValue(); 1610} 1611 1612SDValue DAGCombiner::visitSUB(SDNode *N) { 1613 SDValue N0 = N->getOperand(0); 1614 SDValue N1 = N->getOperand(1); 1615 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1616 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1617 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1618 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1619 EVT VT = N0.getValueType(); 1620 1621 // fold vector ops 1622 if (VT.isVector()) { 1623 SDValue FoldedVOp = SimplifyVBinOp(N); 1624 if (FoldedVOp.getNode()) return FoldedVOp; 1625 } 1626 1627 // fold (sub x, x) -> 0 1628 // FIXME: Refactor this and xor and other similar operations together. 1629 if (N0 == N1) 1630 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1631 // fold (sub c1, c2) -> c1-c2 1632 if (N0C && N1C) 1633 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1634 // fold (sub x, c) -> (add x, -c) 1635 if (N1C) 1636 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1637 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1638 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1639 if (N0C && N0C->isAllOnesValue()) 1640 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1641 // fold A-(A-B) -> B 1642 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1643 return N1.getOperand(1); 1644 // fold (A+B)-A -> B 1645 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1646 return N0.getOperand(1); 1647 // fold (A+B)-B -> A 1648 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1649 return N0.getOperand(0); 1650 // fold C2-(A+C1) -> (C2-C1)-A 1651 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1652 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), 1653 VT); 1654 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1655 N1.getOperand(0)); 1656 } 1657 // fold ((A+(B+or-C))-B) -> A+or-C 1658 if (N0.getOpcode() == ISD::ADD && 1659 (N0.getOperand(1).getOpcode() == ISD::SUB || 1660 N0.getOperand(1).getOpcode() == ISD::ADD) && 1661 N0.getOperand(1).getOperand(0) == N1) 1662 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1663 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1664 // fold ((A+(C+B))-B) -> A+C 1665 if (N0.getOpcode() == ISD::ADD && 1666 N0.getOperand(1).getOpcode() == ISD::ADD && 1667 N0.getOperand(1).getOperand(1) == N1) 1668 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1669 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1670 // fold ((A-(B-C))-C) -> A-B 1671 if (N0.getOpcode() == ISD::SUB && 1672 N0.getOperand(1).getOpcode() == ISD::SUB && 1673 N0.getOperand(1).getOperand(1) == N1) 1674 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1675 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1676 1677 // If either operand of a sub is undef, the result is undef 1678 if (N0.getOpcode() == ISD::UNDEF) 1679 return N0; 1680 if (N1.getOpcode() == ISD::UNDEF) 1681 return N1; 1682 1683 // If the relocation model supports it, consider symbol offsets. 1684 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1685 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1686 // fold (sub Sym, c) -> Sym-c 1687 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1688 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1689 GA->getOffset() - 1690 (uint64_t)N1C->getSExtValue()); 1691 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1692 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1693 if (GA->getGlobal() == GB->getGlobal()) 1694 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1695 VT); 1696 } 1697 1698 return SDValue(); 1699} 1700 1701SDValue DAGCombiner::visitSUBC(SDNode *N) { 1702 SDValue N0 = N->getOperand(0); 1703 SDValue N1 = N->getOperand(1); 1704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1706 EVT VT = N0.getValueType(); 1707 1708 // If the flag result is dead, turn this into an SUB. 1709 if (!N->hasAnyUseOfValue(1)) 1710 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1711 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1712 MVT::Glue)); 1713 1714 // fold (subc x, x) -> 0 + no borrow 1715 if (N0 == N1) 1716 return CombineTo(N, DAG.getConstant(0, VT), 1717 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1718 MVT::Glue)); 1719 1720 // fold (subc x, 0) -> x + no borrow 1721 if (N1C && N1C->isNullValue()) 1722 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1723 MVT::Glue)); 1724 1725 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1726 if (N0C && N0C->isAllOnesValue()) 1727 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1728 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1729 MVT::Glue)); 1730 1731 return SDValue(); 1732} 1733 1734SDValue DAGCombiner::visitSUBE(SDNode *N) { 1735 SDValue N0 = N->getOperand(0); 1736 SDValue N1 = N->getOperand(1); 1737 SDValue CarryIn = N->getOperand(2); 1738 1739 // fold (sube x, y, false) -> (subc x, y) 1740 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1741 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1742 1743 return SDValue(); 1744} 1745 1746SDValue DAGCombiner::visitMUL(SDNode *N) { 1747 SDValue N0 = N->getOperand(0); 1748 SDValue N1 = N->getOperand(1); 1749 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1750 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1751 EVT VT = N0.getValueType(); 1752 1753 // fold vector ops 1754 if (VT.isVector()) { 1755 SDValue FoldedVOp = SimplifyVBinOp(N); 1756 if (FoldedVOp.getNode()) return FoldedVOp; 1757 } 1758 1759 // fold (mul x, undef) -> 0 1760 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1761 return DAG.getConstant(0, VT); 1762 // fold (mul c1, c2) -> c1*c2 1763 if (N0C && N1C) 1764 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1765 // canonicalize constant to RHS 1766 if (N0C && !N1C) 1767 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1768 // fold (mul x, 0) -> 0 1769 if (N1C && N1C->isNullValue()) 1770 return N1; 1771 // fold (mul x, -1) -> 0-x 1772 if (N1C && N1C->isAllOnesValue()) 1773 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1774 DAG.getConstant(0, VT), N0); 1775 // fold (mul x, (1 << c)) -> x << c 1776 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1777 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1778 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1779 getShiftAmountTy(N0.getValueType()))); 1780 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1781 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1782 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1783 // FIXME: If the input is something that is easily negated (e.g. a 1784 // single-use add), we should put the negate there. 1785 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1786 DAG.getConstant(0, VT), 1787 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1788 DAG.getConstant(Log2Val, 1789 getShiftAmountTy(N0.getValueType())))); 1790 } 1791 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1792 if (N1C && N0.getOpcode() == ISD::SHL && 1793 isa<ConstantSDNode>(N0.getOperand(1))) { 1794 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1795 N1, N0.getOperand(1)); 1796 AddToWorkList(C3.getNode()); 1797 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1798 N0.getOperand(0), C3); 1799 } 1800 1801 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1802 // use. 1803 { 1804 SDValue Sh(0,0), Y(0,0); 1805 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1806 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1807 N0.getNode()->hasOneUse()) { 1808 Sh = N0; Y = N1; 1809 } else if (N1.getOpcode() == ISD::SHL && 1810 isa<ConstantSDNode>(N1.getOperand(1)) && 1811 N1.getNode()->hasOneUse()) { 1812 Sh = N1; Y = N0; 1813 } 1814 1815 if (Sh.getNode()) { 1816 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1817 Sh.getOperand(0), Y); 1818 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1819 Mul, Sh.getOperand(1)); 1820 } 1821 } 1822 1823 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1824 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1825 isa<ConstantSDNode>(N0.getOperand(1))) 1826 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1827 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1828 N0.getOperand(0), N1), 1829 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1830 N0.getOperand(1), N1)); 1831 1832 // reassociate mul 1833 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1834 if (RMUL.getNode() != 0) 1835 return RMUL; 1836 1837 return SDValue(); 1838} 1839 1840SDValue DAGCombiner::visitSDIV(SDNode *N) { 1841 SDValue N0 = N->getOperand(0); 1842 SDValue N1 = N->getOperand(1); 1843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1845 EVT VT = N->getValueType(0); 1846 1847 // fold vector ops 1848 if (VT.isVector()) { 1849 SDValue FoldedVOp = SimplifyVBinOp(N); 1850 if (FoldedVOp.getNode()) return FoldedVOp; 1851 } 1852 1853 // fold (sdiv c1, c2) -> c1/c2 1854 if (N0C && N1C && !N1C->isNullValue()) 1855 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1856 // fold (sdiv X, 1) -> X 1857 if (N1C && N1C->getAPIntValue() == 1LL) 1858 return N0; 1859 // fold (sdiv X, -1) -> 0-X 1860 if (N1C && N1C->isAllOnesValue()) 1861 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1862 DAG.getConstant(0, VT), N0); 1863 // If we know the sign bits of both operands are zero, strength reduce to a 1864 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1865 if (!VT.isVector()) { 1866 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1867 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1868 N0, N1); 1869 } 1870 // fold (sdiv X, pow2) -> simple ops after legalize 1871 if (N1C && !N1C->isNullValue() && 1872 (N1C->getAPIntValue().isPowerOf2() || 1873 (-N1C->getAPIntValue()).isPowerOf2())) { 1874 // If dividing by powers of two is cheap, then don't perform the following 1875 // fold. 1876 if (TLI.isPow2DivCheap()) 1877 return SDValue(); 1878 1879 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1880 1881 // Splat the sign bit into the register 1882 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1883 DAG.getConstant(VT.getSizeInBits()-1, 1884 getShiftAmountTy(N0.getValueType()))); 1885 AddToWorkList(SGN.getNode()); 1886 1887 // Add (N0 < 0) ? abs2 - 1 : 0; 1888 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1889 DAG.getConstant(VT.getSizeInBits() - lg2, 1890 getShiftAmountTy(SGN.getValueType()))); 1891 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1892 AddToWorkList(SRL.getNode()); 1893 AddToWorkList(ADD.getNode()); // Divide by pow2 1894 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1895 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1896 1897 // If we're dividing by a positive value, we're done. Otherwise, we must 1898 // negate the result. 1899 if (N1C->getAPIntValue().isNonNegative()) 1900 return SRA; 1901 1902 AddToWorkList(SRA.getNode()); 1903 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1904 DAG.getConstant(0, VT), SRA); 1905 } 1906 1907 // if integer divide is expensive and we satisfy the requirements, emit an 1908 // alternate sequence. 1909 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1910 SDValue Op = BuildSDIV(N); 1911 if (Op.getNode()) return Op; 1912 } 1913 1914 // undef / X -> 0 1915 if (N0.getOpcode() == ISD::UNDEF) 1916 return DAG.getConstant(0, VT); 1917 // X / undef -> undef 1918 if (N1.getOpcode() == ISD::UNDEF) 1919 return N1; 1920 1921 return SDValue(); 1922} 1923 1924SDValue DAGCombiner::visitUDIV(SDNode *N) { 1925 SDValue N0 = N->getOperand(0); 1926 SDValue N1 = N->getOperand(1); 1927 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1928 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1929 EVT VT = N->getValueType(0); 1930 1931 // fold vector ops 1932 if (VT.isVector()) { 1933 SDValue FoldedVOp = SimplifyVBinOp(N); 1934 if (FoldedVOp.getNode()) return FoldedVOp; 1935 } 1936 1937 // fold (udiv c1, c2) -> c1/c2 1938 if (N0C && N1C && !N1C->isNullValue()) 1939 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1940 // fold (udiv x, (1 << c)) -> x >>u c 1941 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1942 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1943 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1944 getShiftAmountTy(N0.getValueType()))); 1945 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1946 if (N1.getOpcode() == ISD::SHL) { 1947 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1948 if (SHC->getAPIntValue().isPowerOf2()) { 1949 EVT ADDVT = N1.getOperand(1).getValueType(); 1950 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1951 N1.getOperand(1), 1952 DAG.getConstant(SHC->getAPIntValue() 1953 .logBase2(), 1954 ADDVT)); 1955 AddToWorkList(Add.getNode()); 1956 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1957 } 1958 } 1959 } 1960 // fold (udiv x, c) -> alternate 1961 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1962 SDValue Op = BuildUDIV(N); 1963 if (Op.getNode()) return Op; 1964 } 1965 1966 // undef / X -> 0 1967 if (N0.getOpcode() == ISD::UNDEF) 1968 return DAG.getConstant(0, VT); 1969 // X / undef -> undef 1970 if (N1.getOpcode() == ISD::UNDEF) 1971 return N1; 1972 1973 return SDValue(); 1974} 1975 1976SDValue DAGCombiner::visitSREM(SDNode *N) { 1977 SDValue N0 = N->getOperand(0); 1978 SDValue N1 = N->getOperand(1); 1979 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1980 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1981 EVT VT = N->getValueType(0); 1982 1983 // fold (srem c1, c2) -> c1%c2 1984 if (N0C && N1C && !N1C->isNullValue()) 1985 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1986 // If we know the sign bits of both operands are zero, strength reduce to a 1987 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1988 if (!VT.isVector()) { 1989 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1990 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1991 } 1992 1993 // If X/C can be simplified by the division-by-constant logic, lower 1994 // X%C to the equivalent of X-X/C*C. 1995 if (N1C && !N1C->isNullValue()) { 1996 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1997 AddToWorkList(Div.getNode()); 1998 SDValue OptimizedDiv = combine(Div.getNode()); 1999 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2000 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2001 OptimizedDiv, N1); 2002 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2003 AddToWorkList(Mul.getNode()); 2004 return Sub; 2005 } 2006 } 2007 2008 // undef % X -> 0 2009 if (N0.getOpcode() == ISD::UNDEF) 2010 return DAG.getConstant(0, VT); 2011 // X % undef -> undef 2012 if (N1.getOpcode() == ISD::UNDEF) 2013 return N1; 2014 2015 return SDValue(); 2016} 2017 2018SDValue DAGCombiner::visitUREM(SDNode *N) { 2019 SDValue N0 = N->getOperand(0); 2020 SDValue N1 = N->getOperand(1); 2021 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2022 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2023 EVT VT = N->getValueType(0); 2024 2025 // fold (urem c1, c2) -> c1%c2 2026 if (N0C && N1C && !N1C->isNullValue()) 2027 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2028 // fold (urem x, pow2) -> (and x, pow2-1) 2029 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2030 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2031 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2032 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2033 if (N1.getOpcode() == ISD::SHL) { 2034 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2035 if (SHC->getAPIntValue().isPowerOf2()) { 2036 SDValue Add = 2037 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2038 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2039 VT)); 2040 AddToWorkList(Add.getNode()); 2041 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2042 } 2043 } 2044 } 2045 2046 // If X/C can be simplified by the division-by-constant logic, lower 2047 // X%C to the equivalent of X-X/C*C. 2048 if (N1C && !N1C->isNullValue()) { 2049 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2050 AddToWorkList(Div.getNode()); 2051 SDValue OptimizedDiv = combine(Div.getNode()); 2052 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2053 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2054 OptimizedDiv, N1); 2055 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2056 AddToWorkList(Mul.getNode()); 2057 return Sub; 2058 } 2059 } 2060 2061 // undef % X -> 0 2062 if (N0.getOpcode() == ISD::UNDEF) 2063 return DAG.getConstant(0, VT); 2064 // X % undef -> undef 2065 if (N1.getOpcode() == ISD::UNDEF) 2066 return N1; 2067 2068 return SDValue(); 2069} 2070 2071SDValue DAGCombiner::visitMULHS(SDNode *N) { 2072 SDValue N0 = N->getOperand(0); 2073 SDValue N1 = N->getOperand(1); 2074 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2075 EVT VT = N->getValueType(0); 2076 DebugLoc DL = N->getDebugLoc(); 2077 2078 // fold (mulhs x, 0) -> 0 2079 if (N1C && N1C->isNullValue()) 2080 return N1; 2081 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2082 if (N1C && N1C->getAPIntValue() == 1) 2083 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2084 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2085 getShiftAmountTy(N0.getValueType()))); 2086 // fold (mulhs x, undef) -> 0 2087 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2088 return DAG.getConstant(0, VT); 2089 2090 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2091 // plus a shift. 2092 if (VT.isSimple() && !VT.isVector()) { 2093 MVT Simple = VT.getSimpleVT(); 2094 unsigned SimpleSize = Simple.getSizeInBits(); 2095 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2096 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2097 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2098 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2099 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2100 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2101 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2102 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2103 } 2104 } 2105 2106 return SDValue(); 2107} 2108 2109SDValue DAGCombiner::visitMULHU(SDNode *N) { 2110 SDValue N0 = N->getOperand(0); 2111 SDValue N1 = N->getOperand(1); 2112 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2113 EVT VT = N->getValueType(0); 2114 DebugLoc DL = N->getDebugLoc(); 2115 2116 // fold (mulhu x, 0) -> 0 2117 if (N1C && N1C->isNullValue()) 2118 return N1; 2119 // fold (mulhu x, 1) -> 0 2120 if (N1C && N1C->getAPIntValue() == 1) 2121 return DAG.getConstant(0, N0.getValueType()); 2122 // fold (mulhu x, undef) -> 0 2123 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2124 return DAG.getConstant(0, VT); 2125 2126 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2127 // plus a shift. 2128 if (VT.isSimple() && !VT.isVector()) { 2129 MVT Simple = VT.getSimpleVT(); 2130 unsigned SimpleSize = Simple.getSizeInBits(); 2131 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2132 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2133 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2134 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2135 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2136 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2137 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2138 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2139 } 2140 } 2141 2142 return SDValue(); 2143} 2144 2145/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2146/// compute two values. LoOp and HiOp give the opcodes for the two computations 2147/// that are being performed. Return true if a simplification was made. 2148/// 2149SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2150 unsigned HiOp) { 2151 // If the high half is not needed, just compute the low half. 2152 bool HiExists = N->hasAnyUseOfValue(1); 2153 if (!HiExists && 2154 (!LegalOperations || 2155 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2156 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2157 N->op_begin(), N->getNumOperands()); 2158 return CombineTo(N, Res, Res); 2159 } 2160 2161 // If the low half is not needed, just compute the high half. 2162 bool LoExists = N->hasAnyUseOfValue(0); 2163 if (!LoExists && 2164 (!LegalOperations || 2165 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2166 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2167 N->op_begin(), N->getNumOperands()); 2168 return CombineTo(N, Res, Res); 2169 } 2170 2171 // If both halves are used, return as it is. 2172 if (LoExists && HiExists) 2173 return SDValue(); 2174 2175 // If the two computed results can be simplified separately, separate them. 2176 if (LoExists) { 2177 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2178 N->op_begin(), N->getNumOperands()); 2179 AddToWorkList(Lo.getNode()); 2180 SDValue LoOpt = combine(Lo.getNode()); 2181 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2182 (!LegalOperations || 2183 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2184 return CombineTo(N, LoOpt, LoOpt); 2185 } 2186 2187 if (HiExists) { 2188 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2189 N->op_begin(), N->getNumOperands()); 2190 AddToWorkList(Hi.getNode()); 2191 SDValue HiOpt = combine(Hi.getNode()); 2192 if (HiOpt.getNode() && HiOpt != Hi && 2193 (!LegalOperations || 2194 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2195 return CombineTo(N, HiOpt, HiOpt); 2196 } 2197 2198 return SDValue(); 2199} 2200 2201SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2202 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2203 if (Res.getNode()) return Res; 2204 2205 EVT VT = N->getValueType(0); 2206 DebugLoc DL = N->getDebugLoc(); 2207 2208 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2209 // plus a shift. 2210 if (VT.isSimple() && !VT.isVector()) { 2211 MVT Simple = VT.getSimpleVT(); 2212 unsigned SimpleSize = Simple.getSizeInBits(); 2213 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2214 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2215 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2216 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2217 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2218 // Compute the high part as N1. 2219 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2220 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2221 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2222 // Compute the low part as N0. 2223 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2224 return CombineTo(N, Lo, Hi); 2225 } 2226 } 2227 2228 return SDValue(); 2229} 2230 2231SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2232 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2233 if (Res.getNode()) return Res; 2234 2235 EVT VT = N->getValueType(0); 2236 DebugLoc DL = N->getDebugLoc(); 2237 2238 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2239 // plus a shift. 2240 if (VT.isSimple() && !VT.isVector()) { 2241 MVT Simple = VT.getSimpleVT(); 2242 unsigned SimpleSize = Simple.getSizeInBits(); 2243 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2244 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2245 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2246 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2247 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2248 // Compute the high part as N1. 2249 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2250 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2251 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2252 // Compute the low part as N0. 2253 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2254 return CombineTo(N, Lo, Hi); 2255 } 2256 } 2257 2258 return SDValue(); 2259} 2260 2261SDValue DAGCombiner::visitSMULO(SDNode *N) { 2262 // (smulo x, 2) -> (saddo x, x) 2263 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2264 if (C2->getAPIntValue() == 2) 2265 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2266 N->getOperand(0), N->getOperand(0)); 2267 2268 return SDValue(); 2269} 2270 2271SDValue DAGCombiner::visitUMULO(SDNode *N) { 2272 // (umulo x, 2) -> (uaddo x, x) 2273 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2274 if (C2->getAPIntValue() == 2) 2275 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2276 N->getOperand(0), N->getOperand(0)); 2277 2278 return SDValue(); 2279} 2280 2281SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2282 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2283 if (Res.getNode()) return Res; 2284 2285 return SDValue(); 2286} 2287 2288SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2289 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2290 if (Res.getNode()) return Res; 2291 2292 return SDValue(); 2293} 2294 2295/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2296/// two operands of the same opcode, try to simplify it. 2297SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2298 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2299 EVT VT = N0.getValueType(); 2300 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2301 2302 // Bail early if none of these transforms apply. 2303 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2304 2305 // For each of OP in AND/OR/XOR: 2306 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2307 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2308 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2309 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2310 // 2311 // do not sink logical op inside of a vector extend, since it may combine 2312 // into a vsetcc. 2313 EVT Op0VT = N0.getOperand(0).getValueType(); 2314 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2315 N0.getOpcode() == ISD::SIGN_EXTEND || 2316 // Avoid infinite looping with PromoteIntBinOp. 2317 (N0.getOpcode() == ISD::ANY_EXTEND && 2318 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2319 (N0.getOpcode() == ISD::TRUNCATE && 2320 (!TLI.isZExtFree(VT, Op0VT) || 2321 !TLI.isTruncateFree(Op0VT, VT)) && 2322 TLI.isTypeLegal(Op0VT))) && 2323 !VT.isVector() && 2324 Op0VT == N1.getOperand(0).getValueType() && 2325 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2326 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2327 N0.getOperand(0).getValueType(), 2328 N0.getOperand(0), N1.getOperand(0)); 2329 AddToWorkList(ORNode.getNode()); 2330 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2331 } 2332 2333 // For each of OP in SHL/SRL/SRA/AND... 2334 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2335 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2336 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2337 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2338 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2339 N0.getOperand(1) == N1.getOperand(1)) { 2340 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2341 N0.getOperand(0).getValueType(), 2342 N0.getOperand(0), N1.getOperand(0)); 2343 AddToWorkList(ORNode.getNode()); 2344 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2345 ORNode, N0.getOperand(1)); 2346 } 2347 2348 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2349 // Only perform this optimization after type legalization and before 2350 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2351 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2352 // we don't want to undo this promotion. 2353 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2354 // on scalars. 2355 if ((N0.getOpcode() == ISD::BITCAST || 2356 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && 2357 Level == AfterLegalizeTypes) { 2358 SDValue In0 = N0.getOperand(0); 2359 SDValue In1 = N1.getOperand(0); 2360 EVT In0Ty = In0.getValueType(); 2361 EVT In1Ty = In1.getValueType(); 2362 DebugLoc DL = N->getDebugLoc(); 2363 // If both incoming values are integers, and the original types are the 2364 // same. 2365 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2366 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1); 2367 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op); 2368 AddToWorkList(Op.getNode()); 2369 return BC; 2370 } 2371 } 2372 2373 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2374 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2375 // If both shuffles use the same mask, and both shuffle within a single 2376 // vector, then it is worthwhile to move the swizzle after the operation. 2377 // The type-legalizer generates this pattern when loading illegal 2378 // vector types from memory. In many cases this allows additional shuffle 2379 // optimizations. 2380 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2381 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2382 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2383 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2384 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2385 2386 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2387 "Inputs to shuffles are not the same type"); 2388 2389 unsigned NumElts = VT.getVectorNumElements(); 2390 2391 // Check that both shuffles use the same mask. The masks are known to be of 2392 // the same length because the result vector type is the same. 2393 bool SameMask = true; 2394 for (unsigned i = 0; i != NumElts; ++i) { 2395 int Idx0 = SVN0->getMaskElt(i); 2396 int Idx1 = SVN1->getMaskElt(i); 2397 if (Idx0 != Idx1) { 2398 SameMask = false; 2399 break; 2400 } 2401 } 2402 2403 if (SameMask) { 2404 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2405 N0.getOperand(0), N1.getOperand(0)); 2406 AddToWorkList(Op.getNode()); 2407 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2408 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2409 } 2410 } 2411 2412 return SDValue(); 2413} 2414 2415SDValue DAGCombiner::visitAND(SDNode *N) { 2416 SDValue N0 = N->getOperand(0); 2417 SDValue N1 = N->getOperand(1); 2418 SDValue LL, LR, RL, RR, CC0, CC1; 2419 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2420 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2421 EVT VT = N1.getValueType(); 2422 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2423 2424 // fold vector ops 2425 if (VT.isVector()) { 2426 SDValue FoldedVOp = SimplifyVBinOp(N); 2427 if (FoldedVOp.getNode()) return FoldedVOp; 2428 } 2429 2430 // fold (and x, undef) -> 0 2431 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2432 return DAG.getConstant(0, VT); 2433 // fold (and c1, c2) -> c1&c2 2434 if (N0C && N1C) 2435 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2436 // canonicalize constant to RHS 2437 if (N0C && !N1C) 2438 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2439 // fold (and x, -1) -> x 2440 if (N1C && N1C->isAllOnesValue()) 2441 return N0; 2442 // if (and x, c) is known to be zero, return 0 2443 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2444 APInt::getAllOnesValue(BitWidth))) 2445 return DAG.getConstant(0, VT); 2446 // reassociate and 2447 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2448 if (RAND.getNode() != 0) 2449 return RAND; 2450 // fold (and (or x, C), D) -> D if (C & D) == D 2451 if (N1C && N0.getOpcode() == ISD::OR) 2452 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2453 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2454 return N1; 2455 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2456 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2457 SDValue N0Op0 = N0.getOperand(0); 2458 APInt Mask = ~N1C->getAPIntValue(); 2459 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2460 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2461 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2462 N0.getValueType(), N0Op0); 2463 2464 // Replace uses of the AND with uses of the Zero extend node. 2465 CombineTo(N, Zext); 2466 2467 // We actually want to replace all uses of the any_extend with the 2468 // zero_extend, to avoid duplicating things. This will later cause this 2469 // AND to be folded. 2470 CombineTo(N0.getNode(), Zext); 2471 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2472 } 2473 } 2474 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2475 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2476 // already be zero by virtue of the width of the base type of the load. 2477 // 2478 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2479 // more cases. 2480 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2481 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2482 N0.getOpcode() == ISD::LOAD) { 2483 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2484 N0 : N0.getOperand(0) ); 2485 2486 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2487 // This can be a pure constant or a vector splat, in which case we treat the 2488 // vector as a scalar and use the splat value. 2489 APInt Constant = APInt::getNullValue(1); 2490 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2491 Constant = C->getAPIntValue(); 2492 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2493 APInt SplatValue, SplatUndef; 2494 unsigned SplatBitSize; 2495 bool HasAnyUndefs; 2496 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2497 SplatBitSize, HasAnyUndefs); 2498 if (IsSplat) { 2499 // Undef bits can contribute to a possible optimisation if set, so 2500 // set them. 2501 SplatValue |= SplatUndef; 2502 2503 // The splat value may be something like "0x00FFFFFF", which means 0 for 2504 // the first vector value and FF for the rest, repeating. We need a mask 2505 // that will apply equally to all members of the vector, so AND all the 2506 // lanes of the constant together. 2507 EVT VT = Vector->getValueType(0); 2508 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2509 2510 // If the splat value has been compressed to a bitlength lower 2511 // than the size of the vector lane, we need to re-expand it to 2512 // the lane size. 2513 if (BitWidth > SplatBitSize) 2514 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2515 SplatBitSize < BitWidth; 2516 SplatBitSize = SplatBitSize * 2) 2517 SplatValue |= SplatValue.shl(SplatBitSize); 2518 2519 Constant = APInt::getAllOnesValue(BitWidth); 2520 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2521 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2522 } 2523 } 2524 2525 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2526 // actually legal and isn't going to get expanded, else this is a false 2527 // optimisation. 2528 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2529 Load->getMemoryVT()); 2530 2531 // Resize the constant to the same size as the original memory access before 2532 // extension. If it is still the AllOnesValue then this AND is completely 2533 // unneeded. 2534 Constant = 2535 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2536 2537 bool B; 2538 switch (Load->getExtensionType()) { 2539 default: B = false; break; 2540 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2541 case ISD::ZEXTLOAD: 2542 case ISD::NON_EXTLOAD: B = true; break; 2543 } 2544 2545 if (B && Constant.isAllOnesValue()) { 2546 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2547 // preserve semantics once we get rid of the AND. 2548 SDValue NewLoad(Load, 0); 2549 if (Load->getExtensionType() == ISD::EXTLOAD) { 2550 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2551 Load->getValueType(0), Load->getDebugLoc(), 2552 Load->getChain(), Load->getBasePtr(), 2553 Load->getOffset(), Load->getMemoryVT(), 2554 Load->getMemOperand()); 2555 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2556 if (Load->getNumValues() == 3) { 2557 // PRE/POST_INC loads have 3 values. 2558 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2559 NewLoad.getValue(2) }; 2560 CombineTo(Load, To, 3, true); 2561 } else { 2562 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2563 } 2564 } 2565 2566 // Fold the AND away, taking care not to fold to the old load node if we 2567 // replaced it. 2568 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2569 2570 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2571 } 2572 } 2573 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2574 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2575 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2576 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2577 2578 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2579 LL.getValueType().isInteger()) { 2580 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2581 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2582 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2583 LR.getValueType(), LL, RL); 2584 AddToWorkList(ORNode.getNode()); 2585 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2586 } 2587 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2588 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2589 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2590 LR.getValueType(), LL, RL); 2591 AddToWorkList(ANDNode.getNode()); 2592 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2593 } 2594 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2595 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2596 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2597 LR.getValueType(), LL, RL); 2598 AddToWorkList(ORNode.getNode()); 2599 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2600 } 2601 } 2602 // canonicalize equivalent to ll == rl 2603 if (LL == RR && LR == RL) { 2604 Op1 = ISD::getSetCCSwappedOperands(Op1); 2605 std::swap(RL, RR); 2606 } 2607 if (LL == RL && LR == RR) { 2608 bool isInteger = LL.getValueType().isInteger(); 2609 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2610 if (Result != ISD::SETCC_INVALID && 2611 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2612 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2613 LL, LR, Result); 2614 } 2615 } 2616 2617 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2618 if (N0.getOpcode() == N1.getOpcode()) { 2619 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2620 if (Tmp.getNode()) return Tmp; 2621 } 2622 2623 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2624 // fold (and (sra)) -> (and (srl)) when possible. 2625 if (!VT.isVector() && 2626 SimplifyDemandedBits(SDValue(N, 0))) 2627 return SDValue(N, 0); 2628 2629 // fold (zext_inreg (extload x)) -> (zextload x) 2630 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2631 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2632 EVT MemVT = LN0->getMemoryVT(); 2633 // If we zero all the possible extended bits, then we can turn this into 2634 // a zextload if we are running before legalize or the operation is legal. 2635 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2636 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2637 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2638 ((!LegalOperations && !LN0->isVolatile()) || 2639 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2640 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2641 LN0->getChain(), LN0->getBasePtr(), 2642 LN0->getPointerInfo(), MemVT, 2643 LN0->isVolatile(), LN0->isNonTemporal(), 2644 LN0->getAlignment()); 2645 AddToWorkList(N); 2646 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2647 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2648 } 2649 } 2650 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2651 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2652 N0.hasOneUse()) { 2653 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2654 EVT MemVT = LN0->getMemoryVT(); 2655 // If we zero all the possible extended bits, then we can turn this into 2656 // a zextload if we are running before legalize or the operation is legal. 2657 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2658 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2659 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2660 ((!LegalOperations && !LN0->isVolatile()) || 2661 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2662 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2663 LN0->getChain(), 2664 LN0->getBasePtr(), LN0->getPointerInfo(), 2665 MemVT, 2666 LN0->isVolatile(), LN0->isNonTemporal(), 2667 LN0->getAlignment()); 2668 AddToWorkList(N); 2669 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2670 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2671 } 2672 } 2673 2674 // fold (and (load x), 255) -> (zextload x, i8) 2675 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2676 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2677 if (N1C && (N0.getOpcode() == ISD::LOAD || 2678 (N0.getOpcode() == ISD::ANY_EXTEND && 2679 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2680 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2681 LoadSDNode *LN0 = HasAnyExt 2682 ? cast<LoadSDNode>(N0.getOperand(0)) 2683 : cast<LoadSDNode>(N0); 2684 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2685 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2686 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2687 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2688 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2689 EVT LoadedVT = LN0->getMemoryVT(); 2690 2691 if (ExtVT == LoadedVT && 2692 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2693 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2694 2695 SDValue NewLoad = 2696 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2697 LN0->getChain(), LN0->getBasePtr(), 2698 LN0->getPointerInfo(), 2699 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2700 LN0->getAlignment()); 2701 AddToWorkList(N); 2702 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2703 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2704 } 2705 2706 // Do not change the width of a volatile load. 2707 // Do not generate loads of non-round integer types since these can 2708 // be expensive (and would be wrong if the type is not byte sized). 2709 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2710 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2711 EVT PtrType = LN0->getOperand(1).getValueType(); 2712 2713 unsigned Alignment = LN0->getAlignment(); 2714 SDValue NewPtr = LN0->getBasePtr(); 2715 2716 // For big endian targets, we need to add an offset to the pointer 2717 // to load the correct bytes. For little endian systems, we merely 2718 // need to read fewer bytes from the same pointer. 2719 if (TLI.isBigEndian()) { 2720 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2721 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2722 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2723 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2724 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2725 Alignment = MinAlign(Alignment, PtrOff); 2726 } 2727 2728 AddToWorkList(NewPtr.getNode()); 2729 2730 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2731 SDValue Load = 2732 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2733 LN0->getChain(), NewPtr, 2734 LN0->getPointerInfo(), 2735 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2736 Alignment); 2737 AddToWorkList(N); 2738 CombineTo(LN0, Load, Load.getValue(1)); 2739 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2740 } 2741 } 2742 } 2743 } 2744 2745 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2746 VT.getSizeInBits() <= 64) { 2747 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2748 APInt ADDC = ADDI->getAPIntValue(); 2749 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2750 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2751 // immediate for an add, but it is legal if its top c2 bits are set, 2752 // transform the ADD so the immediate doesn't need to be materialized 2753 // in a register. 2754 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2755 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2756 SRLI->getZExtValue()); 2757 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2758 ADDC |= Mask; 2759 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2760 SDValue NewAdd = 2761 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 2762 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2763 CombineTo(N0.getNode(), NewAdd); 2764 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2765 } 2766 } 2767 } 2768 } 2769 } 2770 } 2771 2772 2773 return SDValue(); 2774} 2775 2776/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2777/// 2778SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2779 bool DemandHighBits) { 2780 if (!LegalOperations) 2781 return SDValue(); 2782 2783 EVT VT = N->getValueType(0); 2784 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2785 return SDValue(); 2786 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2787 return SDValue(); 2788 2789 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2790 bool LookPassAnd0 = false; 2791 bool LookPassAnd1 = false; 2792 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2793 std::swap(N0, N1); 2794 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2795 std::swap(N0, N1); 2796 if (N0.getOpcode() == ISD::AND) { 2797 if (!N0.getNode()->hasOneUse()) 2798 return SDValue(); 2799 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2800 if (!N01C || N01C->getZExtValue() != 0xFF00) 2801 return SDValue(); 2802 N0 = N0.getOperand(0); 2803 LookPassAnd0 = true; 2804 } 2805 2806 if (N1.getOpcode() == ISD::AND) { 2807 if (!N1.getNode()->hasOneUse()) 2808 return SDValue(); 2809 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2810 if (!N11C || N11C->getZExtValue() != 0xFF) 2811 return SDValue(); 2812 N1 = N1.getOperand(0); 2813 LookPassAnd1 = true; 2814 } 2815 2816 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2817 std::swap(N0, N1); 2818 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2819 return SDValue(); 2820 if (!N0.getNode()->hasOneUse() || 2821 !N1.getNode()->hasOneUse()) 2822 return SDValue(); 2823 2824 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2825 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2826 if (!N01C || !N11C) 2827 return SDValue(); 2828 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2829 return SDValue(); 2830 2831 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2832 SDValue N00 = N0->getOperand(0); 2833 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2834 if (!N00.getNode()->hasOneUse()) 2835 return SDValue(); 2836 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2837 if (!N001C || N001C->getZExtValue() != 0xFF) 2838 return SDValue(); 2839 N00 = N00.getOperand(0); 2840 LookPassAnd0 = true; 2841 } 2842 2843 SDValue N10 = N1->getOperand(0); 2844 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2845 if (!N10.getNode()->hasOneUse()) 2846 return SDValue(); 2847 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2848 if (!N101C || N101C->getZExtValue() != 0xFF00) 2849 return SDValue(); 2850 N10 = N10.getOperand(0); 2851 LookPassAnd1 = true; 2852 } 2853 2854 if (N00 != N10) 2855 return SDValue(); 2856 2857 // Make sure everything beyond the low halfword is zero since the SRL 16 2858 // will clear the top bits. 2859 unsigned OpSizeInBits = VT.getSizeInBits(); 2860 if (DemandHighBits && OpSizeInBits > 16 && 2861 (!LookPassAnd0 || !LookPassAnd1) && 2862 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2863 return SDValue(); 2864 2865 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2866 if (OpSizeInBits > 16) 2867 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2868 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2869 return Res; 2870} 2871 2872/// isBSwapHWordElement - Return true if the specified node is an element 2873/// that makes up a 32-bit packed halfword byteswap. i.e. 2874/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2875static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2876 if (!N.getNode()->hasOneUse()) 2877 return false; 2878 2879 unsigned Opc = N.getOpcode(); 2880 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2881 return false; 2882 2883 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2884 if (!N1C) 2885 return false; 2886 2887 unsigned Num; 2888 switch (N1C->getZExtValue()) { 2889 default: 2890 return false; 2891 case 0xFF: Num = 0; break; 2892 case 0xFF00: Num = 1; break; 2893 case 0xFF0000: Num = 2; break; 2894 case 0xFF000000: Num = 3; break; 2895 } 2896 2897 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2898 SDValue N0 = N.getOperand(0); 2899 if (Opc == ISD::AND) { 2900 if (Num == 0 || Num == 2) { 2901 // (x >> 8) & 0xff 2902 // (x >> 8) & 0xff0000 2903 if (N0.getOpcode() != ISD::SRL) 2904 return false; 2905 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2906 if (!C || C->getZExtValue() != 8) 2907 return false; 2908 } else { 2909 // (x << 8) & 0xff00 2910 // (x << 8) & 0xff000000 2911 if (N0.getOpcode() != ISD::SHL) 2912 return false; 2913 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2914 if (!C || C->getZExtValue() != 8) 2915 return false; 2916 } 2917 } else if (Opc == ISD::SHL) { 2918 // (x & 0xff) << 8 2919 // (x & 0xff0000) << 8 2920 if (Num != 0 && Num != 2) 2921 return false; 2922 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2923 if (!C || C->getZExtValue() != 8) 2924 return false; 2925 } else { // Opc == ISD::SRL 2926 // (x & 0xff00) >> 8 2927 // (x & 0xff000000) >> 8 2928 if (Num != 1 && Num != 3) 2929 return false; 2930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2931 if (!C || C->getZExtValue() != 8) 2932 return false; 2933 } 2934 2935 if (Parts[Num]) 2936 return false; 2937 2938 Parts[Num] = N0.getOperand(0).getNode(); 2939 return true; 2940} 2941 2942/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2943/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2944/// => (rotl (bswap x), 16) 2945SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2946 if (!LegalOperations) 2947 return SDValue(); 2948 2949 EVT VT = N->getValueType(0); 2950 if (VT != MVT::i32) 2951 return SDValue(); 2952 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2953 return SDValue(); 2954 2955 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2956 // Look for either 2957 // (or (or (and), (and)), (or (and), (and))) 2958 // (or (or (or (and), (and)), (and)), (and)) 2959 if (N0.getOpcode() != ISD::OR) 2960 return SDValue(); 2961 SDValue N00 = N0.getOperand(0); 2962 SDValue N01 = N0.getOperand(1); 2963 2964 if (N1.getOpcode() == ISD::OR) { 2965 // (or (or (and), (and)), (or (and), (and))) 2966 SDValue N000 = N00.getOperand(0); 2967 if (!isBSwapHWordElement(N000, Parts)) 2968 return SDValue(); 2969 2970 SDValue N001 = N00.getOperand(1); 2971 if (!isBSwapHWordElement(N001, Parts)) 2972 return SDValue(); 2973 SDValue N010 = N01.getOperand(0); 2974 if (!isBSwapHWordElement(N010, Parts)) 2975 return SDValue(); 2976 SDValue N011 = N01.getOperand(1); 2977 if (!isBSwapHWordElement(N011, Parts)) 2978 return SDValue(); 2979 } else { 2980 // (or (or (or (and), (and)), (and)), (and)) 2981 if (!isBSwapHWordElement(N1, Parts)) 2982 return SDValue(); 2983 if (!isBSwapHWordElement(N01, Parts)) 2984 return SDValue(); 2985 if (N00.getOpcode() != ISD::OR) 2986 return SDValue(); 2987 SDValue N000 = N00.getOperand(0); 2988 if (!isBSwapHWordElement(N000, Parts)) 2989 return SDValue(); 2990 SDValue N001 = N00.getOperand(1); 2991 if (!isBSwapHWordElement(N001, Parts)) 2992 return SDValue(); 2993 } 2994 2995 // Make sure the parts are all coming from the same node. 2996 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2997 return SDValue(); 2998 2999 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 3000 SDValue(Parts[0],0)); 3001 3002 // Result of the bswap should be rotated by 16. If it's not legal, than 3003 // do (x << 16) | (x >> 16). 3004 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 3005 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3006 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 3007 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3008 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 3009 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 3010 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 3011 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 3012} 3013 3014SDValue DAGCombiner::visitOR(SDNode *N) { 3015 SDValue N0 = N->getOperand(0); 3016 SDValue N1 = N->getOperand(1); 3017 SDValue LL, LR, RL, RR, CC0, CC1; 3018 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3019 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3020 EVT VT = N1.getValueType(); 3021 3022 // fold vector ops 3023 if (VT.isVector()) { 3024 SDValue FoldedVOp = SimplifyVBinOp(N); 3025 if (FoldedVOp.getNode()) return FoldedVOp; 3026 } 3027 3028 // fold (or x, undef) -> -1 3029 if (!LegalOperations && 3030 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3031 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3032 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3033 } 3034 // fold (or c1, c2) -> c1|c2 3035 if (N0C && N1C) 3036 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3037 // canonicalize constant to RHS 3038 if (N0C && !N1C) 3039 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 3040 // fold (or x, 0) -> x 3041 if (N1C && N1C->isNullValue()) 3042 return N0; 3043 // fold (or x, -1) -> -1 3044 if (N1C && N1C->isAllOnesValue()) 3045 return N1; 3046 // fold (or x, c) -> c iff (x & ~c) == 0 3047 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3048 return N1; 3049 3050 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3051 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3052 if (BSwap.getNode() != 0) 3053 return BSwap; 3054 BSwap = MatchBSwapHWordLow(N, N0, N1); 3055 if (BSwap.getNode() != 0) 3056 return BSwap; 3057 3058 // reassociate or 3059 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3060 if (ROR.getNode() != 0) 3061 return ROR; 3062 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3063 // iff (c1 & c2) == 0. 3064 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3065 isa<ConstantSDNode>(N0.getOperand(1))) { 3066 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3067 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3068 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3069 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3070 N0.getOperand(0), N1), 3071 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3072 } 3073 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3074 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3075 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3076 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3077 3078 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3079 LL.getValueType().isInteger()) { 3080 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3081 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3082 if (cast<ConstantSDNode>(LR)->isNullValue() && 3083 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3084 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3085 LR.getValueType(), LL, RL); 3086 AddToWorkList(ORNode.getNode()); 3087 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3088 } 3089 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3090 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3091 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3092 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3093 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3094 LR.getValueType(), LL, RL); 3095 AddToWorkList(ANDNode.getNode()); 3096 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3097 } 3098 } 3099 // canonicalize equivalent to ll == rl 3100 if (LL == RR && LR == RL) { 3101 Op1 = ISD::getSetCCSwappedOperands(Op1); 3102 std::swap(RL, RR); 3103 } 3104 if (LL == RL && LR == RR) { 3105 bool isInteger = LL.getValueType().isInteger(); 3106 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3107 if (Result != ISD::SETCC_INVALID && 3108 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3109 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3110 LL, LR, Result); 3111 } 3112 } 3113 3114 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3115 if (N0.getOpcode() == N1.getOpcode()) { 3116 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3117 if (Tmp.getNode()) return Tmp; 3118 } 3119 3120 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3121 if (N0.getOpcode() == ISD::AND && 3122 N1.getOpcode() == ISD::AND && 3123 N0.getOperand(1).getOpcode() == ISD::Constant && 3124 N1.getOperand(1).getOpcode() == ISD::Constant && 3125 // Don't increase # computations. 3126 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3127 // We can only do this xform if we know that bits from X that are set in C2 3128 // but not in C1 are already zero. Likewise for Y. 3129 const APInt &LHSMask = 3130 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3131 const APInt &RHSMask = 3132 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3133 3134 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3135 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3136 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3137 N0.getOperand(0), N1.getOperand(0)); 3138 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3139 DAG.getConstant(LHSMask | RHSMask, VT)); 3140 } 3141 } 3142 3143 // See if this is some rotate idiom. 3144 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3145 return SDValue(Rot, 0); 3146 3147 // Simplify the operands using demanded-bits information. 3148 if (!VT.isVector() && 3149 SimplifyDemandedBits(SDValue(N, 0))) 3150 return SDValue(N, 0); 3151 3152 return SDValue(); 3153} 3154 3155/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3156static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3157 if (Op.getOpcode() == ISD::AND) { 3158 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3159 Mask = Op.getOperand(1); 3160 Op = Op.getOperand(0); 3161 } else { 3162 return false; 3163 } 3164 } 3165 3166 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3167 Shift = Op; 3168 return true; 3169 } 3170 3171 return false; 3172} 3173 3174// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3175// idioms for rotate, and if the target supports rotation instructions, generate 3176// a rot[lr]. 3177SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3178 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3179 EVT VT = LHS.getValueType(); 3180 if (!TLI.isTypeLegal(VT)) return 0; 3181 3182 // The target must have at least one rotate flavor. 3183 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3184 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3185 if (!HasROTL && !HasROTR) return 0; 3186 3187 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3188 SDValue LHSShift; // The shift. 3189 SDValue LHSMask; // AND value if any. 3190 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3191 return 0; // Not part of a rotate. 3192 3193 SDValue RHSShift; // The shift. 3194 SDValue RHSMask; // AND value if any. 3195 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3196 return 0; // Not part of a rotate. 3197 3198 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3199 return 0; // Not shifting the same value. 3200 3201 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3202 return 0; // Shifts must disagree. 3203 3204 // Canonicalize shl to left side in a shl/srl pair. 3205 if (RHSShift.getOpcode() == ISD::SHL) { 3206 std::swap(LHS, RHS); 3207 std::swap(LHSShift, RHSShift); 3208 std::swap(LHSMask , RHSMask ); 3209 } 3210 3211 unsigned OpSizeInBits = VT.getSizeInBits(); 3212 SDValue LHSShiftArg = LHSShift.getOperand(0); 3213 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3214 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3215 3216 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3217 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3218 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3219 RHSShiftAmt.getOpcode() == ISD::Constant) { 3220 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3221 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3222 if ((LShVal + RShVal) != OpSizeInBits) 3223 return 0; 3224 3225 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3226 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt); 3227 3228 // If there is an AND of either shifted operand, apply it to the result. 3229 if (LHSMask.getNode() || RHSMask.getNode()) { 3230 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3231 3232 if (LHSMask.getNode()) { 3233 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3234 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3235 } 3236 if (RHSMask.getNode()) { 3237 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3238 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3239 } 3240 3241 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3242 } 3243 3244 return Rot.getNode(); 3245 } 3246 3247 // If there is a mask here, and we have a variable shift, we can't be sure 3248 // that we're masking out the right stuff. 3249 if (LHSMask.getNode() || RHSMask.getNode()) 3250 return 0; 3251 3252 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3253 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3254 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3255 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3256 if (ConstantSDNode *SUBC = 3257 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3258 if (SUBC->getAPIntValue() == OpSizeInBits) { 3259 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, 3260 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3261 } 3262 } 3263 } 3264 3265 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3266 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3267 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3268 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3269 if (ConstantSDNode *SUBC = 3270 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3271 if (SUBC->getAPIntValue() == OpSizeInBits) { 3272 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, 3273 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3274 } 3275 } 3276 } 3277 3278 // Look for sign/zext/any-extended or truncate cases: 3279 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3280 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3281 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3282 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3283 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3284 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3285 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3286 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3287 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3288 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3289 if (RExtOp0.getOpcode() == ISD::SUB && 3290 RExtOp0.getOperand(1) == LExtOp0) { 3291 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3292 // (rotl x, y) 3293 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3294 // (rotr x, (sub 32, y)) 3295 if (ConstantSDNode *SUBC = 3296 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3297 if (SUBC->getAPIntValue() == OpSizeInBits) { 3298 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3299 LHSShiftArg, 3300 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3301 } 3302 } 3303 } else if (LExtOp0.getOpcode() == ISD::SUB && 3304 RExtOp0 == LExtOp0.getOperand(1)) { 3305 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3306 // (rotr x, y) 3307 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3308 // (rotl x, (sub 32, y)) 3309 if (ConstantSDNode *SUBC = 3310 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3311 if (SUBC->getAPIntValue() == OpSizeInBits) { 3312 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3313 LHSShiftArg, 3314 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3315 } 3316 } 3317 } 3318 } 3319 3320 return 0; 3321} 3322 3323SDValue DAGCombiner::visitXOR(SDNode *N) { 3324 SDValue N0 = N->getOperand(0); 3325 SDValue N1 = N->getOperand(1); 3326 SDValue LHS, RHS, CC; 3327 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3328 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3329 EVT VT = N0.getValueType(); 3330 3331 // fold vector ops 3332 if (VT.isVector()) { 3333 SDValue FoldedVOp = SimplifyVBinOp(N); 3334 if (FoldedVOp.getNode()) return FoldedVOp; 3335 } 3336 3337 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3338 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3339 return DAG.getConstant(0, VT); 3340 // fold (xor x, undef) -> undef 3341 if (N0.getOpcode() == ISD::UNDEF) 3342 return N0; 3343 if (N1.getOpcode() == ISD::UNDEF) 3344 return N1; 3345 // fold (xor c1, c2) -> c1^c2 3346 if (N0C && N1C) 3347 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3348 // canonicalize constant to RHS 3349 if (N0C && !N1C) 3350 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3351 // fold (xor x, 0) -> x 3352 if (N1C && N1C->isNullValue()) 3353 return N0; 3354 // reassociate xor 3355 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3356 if (RXOR.getNode() != 0) 3357 return RXOR; 3358 3359 // fold !(x cc y) -> (x !cc y) 3360 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3361 bool isInt = LHS.getValueType().isInteger(); 3362 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3363 isInt); 3364 3365 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3366 switch (N0.getOpcode()) { 3367 default: 3368 llvm_unreachable("Unhandled SetCC Equivalent!"); 3369 case ISD::SETCC: 3370 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3371 case ISD::SELECT_CC: 3372 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3373 N0.getOperand(3), NotCC); 3374 } 3375 } 3376 } 3377 3378 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3379 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3380 N0.getNode()->hasOneUse() && 3381 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3382 SDValue V = N0.getOperand(0); 3383 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3384 DAG.getConstant(1, V.getValueType())); 3385 AddToWorkList(V.getNode()); 3386 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3387 } 3388 3389 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3390 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3391 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3392 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3393 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3394 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3395 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3396 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3397 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3398 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3399 } 3400 } 3401 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3402 if (N1C && N1C->isAllOnesValue() && 3403 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3404 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3405 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3406 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3407 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3408 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3409 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3410 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3411 } 3412 } 3413 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3414 if (N1C && N0.getOpcode() == ISD::XOR) { 3415 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3416 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3417 if (N00C) 3418 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3419 DAG.getConstant(N1C->getAPIntValue() ^ 3420 N00C->getAPIntValue(), VT)); 3421 if (N01C) 3422 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3423 DAG.getConstant(N1C->getAPIntValue() ^ 3424 N01C->getAPIntValue(), VT)); 3425 } 3426 // fold (xor x, x) -> 0 3427 if (N0 == N1) 3428 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3429 3430 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3431 if (N0.getOpcode() == N1.getOpcode()) { 3432 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3433 if (Tmp.getNode()) return Tmp; 3434 } 3435 3436 // Simplify the expression using non-local knowledge. 3437 if (!VT.isVector() && 3438 SimplifyDemandedBits(SDValue(N, 0))) 3439 return SDValue(N, 0); 3440 3441 return SDValue(); 3442} 3443 3444/// visitShiftByConstant - Handle transforms common to the three shifts, when 3445/// the shift amount is a constant. 3446SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3447 SDNode *LHS = N->getOperand(0).getNode(); 3448 if (!LHS->hasOneUse()) return SDValue(); 3449 3450 // We want to pull some binops through shifts, so that we have (and (shift)) 3451 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3452 // thing happens with address calculations, so it's important to canonicalize 3453 // it. 3454 bool HighBitSet = false; // Can we transform this if the high bit is set? 3455 3456 switch (LHS->getOpcode()) { 3457 default: return SDValue(); 3458 case ISD::OR: 3459 case ISD::XOR: 3460 HighBitSet = false; // We can only transform sra if the high bit is clear. 3461 break; 3462 case ISD::AND: 3463 HighBitSet = true; // We can only transform sra if the high bit is set. 3464 break; 3465 case ISD::ADD: 3466 if (N->getOpcode() != ISD::SHL) 3467 return SDValue(); // only shl(add) not sr[al](add). 3468 HighBitSet = false; // We can only transform sra if the high bit is clear. 3469 break; 3470 } 3471 3472 // We require the RHS of the binop to be a constant as well. 3473 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3474 if (!BinOpCst) return SDValue(); 3475 3476 // FIXME: disable this unless the input to the binop is a shift by a constant. 3477 // If it is not a shift, it pessimizes some common cases like: 3478 // 3479 // void foo(int *X, int i) { X[i & 1235] = 1; } 3480 // int bar(int *X, int i) { return X[i & 255]; } 3481 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3482 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3483 BinOpLHSVal->getOpcode() != ISD::SRA && 3484 BinOpLHSVal->getOpcode() != ISD::SRL) || 3485 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3486 return SDValue(); 3487 3488 EVT VT = N->getValueType(0); 3489 3490 // If this is a signed shift right, and the high bit is modified by the 3491 // logical operation, do not perform the transformation. The highBitSet 3492 // boolean indicates the value of the high bit of the constant which would 3493 // cause it to be modified for this operation. 3494 if (N->getOpcode() == ISD::SRA) { 3495 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3496 if (BinOpRHSSignSet != HighBitSet) 3497 return SDValue(); 3498 } 3499 3500 // Fold the constants, shifting the binop RHS by the shift amount. 3501 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3502 N->getValueType(0), 3503 LHS->getOperand(1), N->getOperand(1)); 3504 3505 // Create the new shift. 3506 SDValue NewShift = DAG.getNode(N->getOpcode(), 3507 LHS->getOperand(0).getDebugLoc(), 3508 VT, LHS->getOperand(0), N->getOperand(1)); 3509 3510 // Create the new binop. 3511 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3512} 3513 3514SDValue DAGCombiner::visitSHL(SDNode *N) { 3515 SDValue N0 = N->getOperand(0); 3516 SDValue N1 = N->getOperand(1); 3517 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3518 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3519 EVT VT = N0.getValueType(); 3520 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3521 3522 // fold (shl c1, c2) -> c1<<c2 3523 if (N0C && N1C) 3524 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3525 // fold (shl 0, x) -> 0 3526 if (N0C && N0C->isNullValue()) 3527 return N0; 3528 // fold (shl x, c >= size(x)) -> undef 3529 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3530 return DAG.getUNDEF(VT); 3531 // fold (shl x, 0) -> x 3532 if (N1C && N1C->isNullValue()) 3533 return N0; 3534 // fold (shl undef, x) -> 0 3535 if (N0.getOpcode() == ISD::UNDEF) 3536 return DAG.getConstant(0, VT); 3537 // if (shl x, c) is known to be zero, return 0 3538 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3539 APInt::getAllOnesValue(OpSizeInBits))) 3540 return DAG.getConstant(0, VT); 3541 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3542 if (N1.getOpcode() == ISD::TRUNCATE && 3543 N1.getOperand(0).getOpcode() == ISD::AND && 3544 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3545 SDValue N101 = N1.getOperand(0).getOperand(1); 3546 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3547 EVT TruncVT = N1.getValueType(); 3548 SDValue N100 = N1.getOperand(0).getOperand(0); 3549 APInt TruncC = N101C->getAPIntValue(); 3550 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3551 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3552 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3553 DAG.getNode(ISD::TRUNCATE, 3554 N->getDebugLoc(), 3555 TruncVT, N100), 3556 DAG.getConstant(TruncC, TruncVT))); 3557 } 3558 } 3559 3560 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3561 return SDValue(N, 0); 3562 3563 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3564 if (N1C && N0.getOpcode() == ISD::SHL && 3565 N0.getOperand(1).getOpcode() == ISD::Constant) { 3566 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3567 uint64_t c2 = N1C->getZExtValue(); 3568 if (c1 + c2 >= OpSizeInBits) 3569 return DAG.getConstant(0, VT); 3570 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3571 DAG.getConstant(c1 + c2, N1.getValueType())); 3572 } 3573 3574 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3575 // For this to be valid, the second form must not preserve any of the bits 3576 // that are shifted out by the inner shift in the first form. This means 3577 // the outer shift size must be >= the number of bits added by the ext. 3578 // As a corollary, we don't care what kind of ext it is. 3579 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3580 N0.getOpcode() == ISD::ANY_EXTEND || 3581 N0.getOpcode() == ISD::SIGN_EXTEND) && 3582 N0.getOperand(0).getOpcode() == ISD::SHL && 3583 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3584 uint64_t c1 = 3585 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3586 uint64_t c2 = N1C->getZExtValue(); 3587 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3588 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3589 if (c2 >= OpSizeInBits - InnerShiftSize) { 3590 if (c1 + c2 >= OpSizeInBits) 3591 return DAG.getConstant(0, VT); 3592 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3593 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3594 N0.getOperand(0)->getOperand(0)), 3595 DAG.getConstant(c1 + c2, N1.getValueType())); 3596 } 3597 } 3598 3599 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3600 // (and (srl x, (sub c1, c2), MASK) 3601 // Only fold this if the inner shift has no other uses -- if it does, folding 3602 // this will increase the total number of instructions. 3603 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3604 N0.getOperand(1).getOpcode() == ISD::Constant) { 3605 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3606 if (c1 < VT.getSizeInBits()) { 3607 uint64_t c2 = N1C->getZExtValue(); 3608 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3609 VT.getSizeInBits() - c1); 3610 SDValue Shift; 3611 if (c2 > c1) { 3612 Mask = Mask.shl(c2-c1); 3613 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3614 DAG.getConstant(c2-c1, N1.getValueType())); 3615 } else { 3616 Mask = Mask.lshr(c1-c2); 3617 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3618 DAG.getConstant(c1-c2, N1.getValueType())); 3619 } 3620 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3621 DAG.getConstant(Mask, VT)); 3622 } 3623 } 3624 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3625 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3626 SDValue HiBitsMask = 3627 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3628 VT.getSizeInBits() - 3629 N1C->getZExtValue()), 3630 VT); 3631 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3632 HiBitsMask); 3633 } 3634 3635 if (N1C) { 3636 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3637 if (NewSHL.getNode()) 3638 return NewSHL; 3639 } 3640 3641 return SDValue(); 3642} 3643 3644SDValue DAGCombiner::visitSRA(SDNode *N) { 3645 SDValue N0 = N->getOperand(0); 3646 SDValue N1 = N->getOperand(1); 3647 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3648 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3649 EVT VT = N0.getValueType(); 3650 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3651 3652 // fold (sra c1, c2) -> (sra c1, c2) 3653 if (N0C && N1C) 3654 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3655 // fold (sra 0, x) -> 0 3656 if (N0C && N0C->isNullValue()) 3657 return N0; 3658 // fold (sra -1, x) -> -1 3659 if (N0C && N0C->isAllOnesValue()) 3660 return N0; 3661 // fold (sra x, (setge c, size(x))) -> undef 3662 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3663 return DAG.getUNDEF(VT); 3664 // fold (sra x, 0) -> x 3665 if (N1C && N1C->isNullValue()) 3666 return N0; 3667 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3668 // sext_inreg. 3669 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3670 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3671 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3672 if (VT.isVector()) 3673 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3674 ExtVT, VT.getVectorNumElements()); 3675 if ((!LegalOperations || 3676 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3677 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3678 N0.getOperand(0), DAG.getValueType(ExtVT)); 3679 } 3680 3681 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3682 if (N1C && N0.getOpcode() == ISD::SRA) { 3683 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3684 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3685 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3686 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3687 DAG.getConstant(Sum, N1C->getValueType(0))); 3688 } 3689 } 3690 3691 // fold (sra (shl X, m), (sub result_size, n)) 3692 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3693 // result_size - n != m. 3694 // If truncate is free for the target sext(shl) is likely to result in better 3695 // code. 3696 if (N0.getOpcode() == ISD::SHL) { 3697 // Get the two constanst of the shifts, CN0 = m, CN = n. 3698 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3699 if (N01C && N1C) { 3700 // Determine what the truncate's result bitsize and type would be. 3701 EVT TruncVT = 3702 EVT::getIntegerVT(*DAG.getContext(), 3703 OpSizeInBits - N1C->getZExtValue()); 3704 // Determine the residual right-shift amount. 3705 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3706 3707 // If the shift is not a no-op (in which case this should be just a sign 3708 // extend already), the truncated to type is legal, sign_extend is legal 3709 // on that type, and the truncate to that type is both legal and free, 3710 // perform the transform. 3711 if ((ShiftAmt > 0) && 3712 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3713 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3714 TLI.isTruncateFree(VT, TruncVT)) { 3715 3716 SDValue Amt = DAG.getConstant(ShiftAmt, 3717 getShiftAmountTy(N0.getOperand(0).getValueType())); 3718 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3719 N0.getOperand(0), Amt); 3720 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3721 Shift); 3722 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3723 N->getValueType(0), Trunc); 3724 } 3725 } 3726 } 3727 3728 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3729 if (N1.getOpcode() == ISD::TRUNCATE && 3730 N1.getOperand(0).getOpcode() == ISD::AND && 3731 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3732 SDValue N101 = N1.getOperand(0).getOperand(1); 3733 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3734 EVT TruncVT = N1.getValueType(); 3735 SDValue N100 = N1.getOperand(0).getOperand(0); 3736 APInt TruncC = N101C->getAPIntValue(); 3737 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3738 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3739 DAG.getNode(ISD::AND, N->getDebugLoc(), 3740 TruncVT, 3741 DAG.getNode(ISD::TRUNCATE, 3742 N->getDebugLoc(), 3743 TruncVT, N100), 3744 DAG.getConstant(TruncC, TruncVT))); 3745 } 3746 } 3747 3748 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3749 // if c1 is equal to the number of bits the trunc removes 3750 if (N0.getOpcode() == ISD::TRUNCATE && 3751 (N0.getOperand(0).getOpcode() == ISD::SRL || 3752 N0.getOperand(0).getOpcode() == ISD::SRA) && 3753 N0.getOperand(0).hasOneUse() && 3754 N0.getOperand(0).getOperand(1).hasOneUse() && 3755 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3756 EVT LargeVT = N0.getOperand(0).getValueType(); 3757 ConstantSDNode *LargeShiftAmt = 3758 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3759 3760 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3761 LargeShiftAmt->getZExtValue()) { 3762 SDValue Amt = 3763 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3764 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3765 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3766 N0.getOperand(0).getOperand(0), Amt); 3767 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3768 } 3769 } 3770 3771 // Simplify, based on bits shifted out of the LHS. 3772 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3773 return SDValue(N, 0); 3774 3775 3776 // If the sign bit is known to be zero, switch this to a SRL. 3777 if (DAG.SignBitIsZero(N0)) 3778 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3779 3780 if (N1C) { 3781 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3782 if (NewSRA.getNode()) 3783 return NewSRA; 3784 } 3785 3786 return SDValue(); 3787} 3788 3789SDValue DAGCombiner::visitSRL(SDNode *N) { 3790 SDValue N0 = N->getOperand(0); 3791 SDValue N1 = N->getOperand(1); 3792 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3793 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3794 EVT VT = N0.getValueType(); 3795 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3796 3797 // fold (srl c1, c2) -> c1 >>u c2 3798 if (N0C && N1C) 3799 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3800 // fold (srl 0, x) -> 0 3801 if (N0C && N0C->isNullValue()) 3802 return N0; 3803 // fold (srl x, c >= size(x)) -> undef 3804 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3805 return DAG.getUNDEF(VT); 3806 // fold (srl x, 0) -> x 3807 if (N1C && N1C->isNullValue()) 3808 return N0; 3809 // if (srl x, c) is known to be zero, return 0 3810 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3811 APInt::getAllOnesValue(OpSizeInBits))) 3812 return DAG.getConstant(0, VT); 3813 3814 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3815 if (N1C && N0.getOpcode() == ISD::SRL && 3816 N0.getOperand(1).getOpcode() == ISD::Constant) { 3817 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3818 uint64_t c2 = N1C->getZExtValue(); 3819 if (c1 + c2 >= OpSizeInBits) 3820 return DAG.getConstant(0, VT); 3821 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3822 DAG.getConstant(c1 + c2, N1.getValueType())); 3823 } 3824 3825 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3826 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3827 N0.getOperand(0).getOpcode() == ISD::SRL && 3828 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3829 uint64_t c1 = 3830 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3831 uint64_t c2 = N1C->getZExtValue(); 3832 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3833 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3834 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3835 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3836 if (c1 + OpSizeInBits == InnerShiftSize) { 3837 if (c1 + c2 >= InnerShiftSize) 3838 return DAG.getConstant(0, VT); 3839 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3840 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3841 N0.getOperand(0)->getOperand(0), 3842 DAG.getConstant(c1 + c2, ShiftCountVT))); 3843 } 3844 } 3845 3846 // fold (srl (shl x, c), c) -> (and x, cst2) 3847 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3848 N0.getValueSizeInBits() <= 64) { 3849 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3850 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3851 DAG.getConstant(~0ULL >> ShAmt, VT)); 3852 } 3853 3854 3855 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3856 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3857 // Shifting in all undef bits? 3858 EVT SmallVT = N0.getOperand(0).getValueType(); 3859 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3860 return DAG.getUNDEF(VT); 3861 3862 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3863 uint64_t ShiftAmt = N1C->getZExtValue(); 3864 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3865 N0.getOperand(0), 3866 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3867 AddToWorkList(SmallShift.getNode()); 3868 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3869 } 3870 } 3871 3872 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3873 // bit, which is unmodified by sra. 3874 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3875 if (N0.getOpcode() == ISD::SRA) 3876 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3877 } 3878 3879 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3880 if (N1C && N0.getOpcode() == ISD::CTLZ && 3881 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3882 APInt KnownZero, KnownOne; 3883 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3884 3885 // If any of the input bits are KnownOne, then the input couldn't be all 3886 // zeros, thus the result of the srl will always be zero. 3887 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3888 3889 // If all of the bits input the to ctlz node are known to be zero, then 3890 // the result of the ctlz is "32" and the result of the shift is one. 3891 APInt UnknownBits = ~KnownZero; 3892 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3893 3894 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3895 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3896 // Okay, we know that only that the single bit specified by UnknownBits 3897 // could be set on input to the CTLZ node. If this bit is set, the SRL 3898 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3899 // to an SRL/XOR pair, which is likely to simplify more. 3900 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3901 SDValue Op = N0.getOperand(0); 3902 3903 if (ShAmt) { 3904 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3905 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3906 AddToWorkList(Op.getNode()); 3907 } 3908 3909 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3910 Op, DAG.getConstant(1, VT)); 3911 } 3912 } 3913 3914 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3915 if (N1.getOpcode() == ISD::TRUNCATE && 3916 N1.getOperand(0).getOpcode() == ISD::AND && 3917 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3918 SDValue N101 = N1.getOperand(0).getOperand(1); 3919 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3920 EVT TruncVT = N1.getValueType(); 3921 SDValue N100 = N1.getOperand(0).getOperand(0); 3922 APInt TruncC = N101C->getAPIntValue(); 3923 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3924 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3925 DAG.getNode(ISD::AND, N->getDebugLoc(), 3926 TruncVT, 3927 DAG.getNode(ISD::TRUNCATE, 3928 N->getDebugLoc(), 3929 TruncVT, N100), 3930 DAG.getConstant(TruncC, TruncVT))); 3931 } 3932 } 3933 3934 // fold operands of srl based on knowledge that the low bits are not 3935 // demanded. 3936 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3937 return SDValue(N, 0); 3938 3939 if (N1C) { 3940 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3941 if (NewSRL.getNode()) 3942 return NewSRL; 3943 } 3944 3945 // Attempt to convert a srl of a load into a narrower zero-extending load. 3946 SDValue NarrowLoad = ReduceLoadWidth(N); 3947 if (NarrowLoad.getNode()) 3948 return NarrowLoad; 3949 3950 // Here is a common situation. We want to optimize: 3951 // 3952 // %a = ... 3953 // %b = and i32 %a, 2 3954 // %c = srl i32 %b, 1 3955 // brcond i32 %c ... 3956 // 3957 // into 3958 // 3959 // %a = ... 3960 // %b = and %a, 2 3961 // %c = setcc eq %b, 0 3962 // brcond %c ... 3963 // 3964 // However when after the source operand of SRL is optimized into AND, the SRL 3965 // itself may not be optimized further. Look for it and add the BRCOND into 3966 // the worklist. 3967 if (N->hasOneUse()) { 3968 SDNode *Use = *N->use_begin(); 3969 if (Use->getOpcode() == ISD::BRCOND) 3970 AddToWorkList(Use); 3971 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3972 // Also look pass the truncate. 3973 Use = *Use->use_begin(); 3974 if (Use->getOpcode() == ISD::BRCOND) 3975 AddToWorkList(Use); 3976 } 3977 } 3978 3979 return SDValue(); 3980} 3981 3982SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3983 SDValue N0 = N->getOperand(0); 3984 EVT VT = N->getValueType(0); 3985 3986 // fold (ctlz c1) -> c2 3987 if (isa<ConstantSDNode>(N0)) 3988 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3989 return SDValue(); 3990} 3991 3992SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3993 SDValue N0 = N->getOperand(0); 3994 EVT VT = N->getValueType(0); 3995 3996 // fold (ctlz_zero_undef c1) -> c2 3997 if (isa<ConstantSDNode>(N0)) 3998 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3999 return SDValue(); 4000} 4001 4002SDValue DAGCombiner::visitCTTZ(SDNode *N) { 4003 SDValue N0 = N->getOperand(0); 4004 EVT VT = N->getValueType(0); 4005 4006 // fold (cttz c1) -> c2 4007 if (isa<ConstantSDNode>(N0)) 4008 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 4009 return SDValue(); 4010} 4011 4012SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4013 SDValue N0 = N->getOperand(0); 4014 EVT VT = N->getValueType(0); 4015 4016 // fold (cttz_zero_undef c1) -> c2 4017 if (isa<ConstantSDNode>(N0)) 4018 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4019 return SDValue(); 4020} 4021 4022SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4023 SDValue N0 = N->getOperand(0); 4024 EVT VT = N->getValueType(0); 4025 4026 // fold (ctpop c1) -> c2 4027 if (isa<ConstantSDNode>(N0)) 4028 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 4029 return SDValue(); 4030} 4031 4032SDValue DAGCombiner::visitSELECT(SDNode *N) { 4033 SDValue N0 = N->getOperand(0); 4034 SDValue N1 = N->getOperand(1); 4035 SDValue N2 = N->getOperand(2); 4036 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4037 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4038 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4039 EVT VT = N->getValueType(0); 4040 EVT VT0 = N0.getValueType(); 4041 4042 // fold (select C, X, X) -> X 4043 if (N1 == N2) 4044 return N1; 4045 // fold (select true, X, Y) -> X 4046 if (N0C && !N0C->isNullValue()) 4047 return N1; 4048 // fold (select false, X, Y) -> Y 4049 if (N0C && N0C->isNullValue()) 4050 return N2; 4051 // fold (select C, 1, X) -> (or C, X) 4052 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4053 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4054 // fold (select C, 0, 1) -> (xor C, 1) 4055 if (VT.isInteger() && 4056 (VT0 == MVT::i1 || 4057 (VT0.isInteger() && 4058 TLI.getBooleanContents(false) == 4059 TargetLowering::ZeroOrOneBooleanContent)) && 4060 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4061 SDValue XORNode; 4062 if (VT == VT0) 4063 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4064 N0, DAG.getConstant(1, VT0)); 4065 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4066 N0, DAG.getConstant(1, VT0)); 4067 AddToWorkList(XORNode.getNode()); 4068 if (VT.bitsGT(VT0)) 4069 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4070 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4071 } 4072 // fold (select C, 0, X) -> (and (not C), X) 4073 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4074 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4075 AddToWorkList(NOTNode.getNode()); 4076 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4077 } 4078 // fold (select C, X, 1) -> (or (not C), X) 4079 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4080 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4081 AddToWorkList(NOTNode.getNode()); 4082 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4083 } 4084 // fold (select C, X, 0) -> (and C, X) 4085 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4086 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4087 // fold (select X, X, Y) -> (or X, Y) 4088 // fold (select X, 1, Y) -> (or X, Y) 4089 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4090 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4091 // fold (select X, Y, X) -> (and X, Y) 4092 // fold (select X, Y, 0) -> (and X, Y) 4093 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4094 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4095 4096 // If we can fold this based on the true/false value, do so. 4097 if (SimplifySelectOps(N, N1, N2)) 4098 return SDValue(N, 0); // Don't revisit N. 4099 4100 // fold selects based on a setcc into other things, such as min/max/abs 4101 if (N0.getOpcode() == ISD::SETCC) { 4102 // FIXME: 4103 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4104 // having to say they don't support SELECT_CC on every type the DAG knows 4105 // about, since there is no way to mark an opcode illegal at all value types 4106 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4107 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4108 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4109 N0.getOperand(0), N0.getOperand(1), 4110 N1, N2, N0.getOperand(2)); 4111 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4112 } 4113 4114 return SDValue(); 4115} 4116 4117SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4118 SDValue N0 = N->getOperand(0); 4119 SDValue N1 = N->getOperand(1); 4120 SDValue N2 = N->getOperand(2); 4121 SDValue N3 = N->getOperand(3); 4122 SDValue N4 = N->getOperand(4); 4123 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4124 4125 // fold select_cc lhs, rhs, x, x, cc -> x 4126 if (N2 == N3) 4127 return N2; 4128 4129 // Determine if the condition we're dealing with is constant 4130 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4131 N0, N1, CC, N->getDebugLoc(), false); 4132 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4133 4134 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4135 if (!SCCC->isNullValue()) 4136 return N2; // cond always true -> true val 4137 else 4138 return N3; // cond always false -> false val 4139 } 4140 4141 // Fold to a simpler select_cc 4142 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4143 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4144 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4145 SCC.getOperand(2)); 4146 4147 // If we can fold this based on the true/false value, do so. 4148 if (SimplifySelectOps(N, N2, N3)) 4149 return SDValue(N, 0); // Don't revisit N. 4150 4151 // fold select_cc into other things, such as min/max/abs 4152 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4153} 4154 4155SDValue DAGCombiner::visitSETCC(SDNode *N) { 4156 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4157 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4158 N->getDebugLoc()); 4159} 4160 4161// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4162// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4163// transformation. Returns true if extension are possible and the above 4164// mentioned transformation is profitable. 4165static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4166 unsigned ExtOpc, 4167 SmallVector<SDNode*, 4> &ExtendNodes, 4168 const TargetLowering &TLI) { 4169 bool HasCopyToRegUses = false; 4170 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4171 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4172 UE = N0.getNode()->use_end(); 4173 UI != UE; ++UI) { 4174 SDNode *User = *UI; 4175 if (User == N) 4176 continue; 4177 if (UI.getUse().getResNo() != N0.getResNo()) 4178 continue; 4179 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4180 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4181 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4182 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4183 // Sign bits will be lost after a zext. 4184 return false; 4185 bool Add = false; 4186 for (unsigned i = 0; i != 2; ++i) { 4187 SDValue UseOp = User->getOperand(i); 4188 if (UseOp == N0) 4189 continue; 4190 if (!isa<ConstantSDNode>(UseOp)) 4191 return false; 4192 Add = true; 4193 } 4194 if (Add) 4195 ExtendNodes.push_back(User); 4196 continue; 4197 } 4198 // If truncates aren't free and there are users we can't 4199 // extend, it isn't worthwhile. 4200 if (!isTruncFree) 4201 return false; 4202 // Remember if this value is live-out. 4203 if (User->getOpcode() == ISD::CopyToReg) 4204 HasCopyToRegUses = true; 4205 } 4206 4207 if (HasCopyToRegUses) { 4208 bool BothLiveOut = false; 4209 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4210 UI != UE; ++UI) { 4211 SDUse &Use = UI.getUse(); 4212 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4213 BothLiveOut = true; 4214 break; 4215 } 4216 } 4217 if (BothLiveOut) 4218 // Both unextended and extended values are live out. There had better be 4219 // a good reason for the transformation. 4220 return ExtendNodes.size(); 4221 } 4222 return true; 4223} 4224 4225void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4226 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4227 ISD::NodeType ExtType) { 4228 // Extend SetCC uses if necessary. 4229 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4230 SDNode *SetCC = SetCCs[i]; 4231 SmallVector<SDValue, 4> Ops; 4232 4233 for (unsigned j = 0; j != 2; ++j) { 4234 SDValue SOp = SetCC->getOperand(j); 4235 if (SOp == Trunc) 4236 Ops.push_back(ExtLoad); 4237 else 4238 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4239 } 4240 4241 Ops.push_back(SetCC->getOperand(2)); 4242 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4243 &Ops[0], Ops.size())); 4244 } 4245} 4246 4247SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4248 SDValue N0 = N->getOperand(0); 4249 EVT VT = N->getValueType(0); 4250 4251 // fold (sext c1) -> c1 4252 if (isa<ConstantSDNode>(N0)) 4253 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4254 4255 // fold (sext (sext x)) -> (sext x) 4256 // fold (sext (aext x)) -> (sext x) 4257 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4258 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4259 N0.getOperand(0)); 4260 4261 if (N0.getOpcode() == ISD::TRUNCATE) { 4262 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4263 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4264 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4265 if (NarrowLoad.getNode()) { 4266 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4267 if (NarrowLoad.getNode() != N0.getNode()) { 4268 CombineTo(N0.getNode(), NarrowLoad); 4269 // CombineTo deleted the truncate, if needed, but not what's under it. 4270 AddToWorkList(oye); 4271 } 4272 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4273 } 4274 4275 // See if the value being truncated is already sign extended. If so, just 4276 // eliminate the trunc/sext pair. 4277 SDValue Op = N0.getOperand(0); 4278 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4279 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4280 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4281 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4282 4283 if (OpBits == DestBits) { 4284 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4285 // bits, it is already ready. 4286 if (NumSignBits > DestBits-MidBits) 4287 return Op; 4288 } else if (OpBits < DestBits) { 4289 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4290 // bits, just sext from i32. 4291 if (NumSignBits > OpBits-MidBits) 4292 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4293 } else { 4294 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4295 // bits, just truncate to i32. 4296 if (NumSignBits > OpBits-MidBits) 4297 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4298 } 4299 4300 // fold (sext (truncate x)) -> (sextinreg x). 4301 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4302 N0.getValueType())) { 4303 if (OpBits < DestBits) 4304 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4305 else if (OpBits > DestBits) 4306 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4307 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4308 DAG.getValueType(N0.getValueType())); 4309 } 4310 } 4311 4312 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4313 // None of the supported targets knows how to perform load and sign extend 4314 // on vectors in one instruction. We only perform this transformation on 4315 // scalars. 4316 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4317 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4318 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4319 bool DoXform = true; 4320 SmallVector<SDNode*, 4> SetCCs; 4321 if (!N0.hasOneUse()) 4322 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4323 if (DoXform) { 4324 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4325 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4326 LN0->getChain(), 4327 LN0->getBasePtr(), LN0->getPointerInfo(), 4328 N0.getValueType(), 4329 LN0->isVolatile(), LN0->isNonTemporal(), 4330 LN0->getAlignment()); 4331 CombineTo(N, ExtLoad); 4332 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4333 N0.getValueType(), ExtLoad); 4334 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4335 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4336 ISD::SIGN_EXTEND); 4337 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4338 } 4339 } 4340 4341 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4342 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4343 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4344 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4345 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4346 EVT MemVT = LN0->getMemoryVT(); 4347 if ((!LegalOperations && !LN0->isVolatile()) || 4348 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4349 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4350 LN0->getChain(), 4351 LN0->getBasePtr(), LN0->getPointerInfo(), 4352 MemVT, 4353 LN0->isVolatile(), LN0->isNonTemporal(), 4354 LN0->getAlignment()); 4355 CombineTo(N, ExtLoad); 4356 CombineTo(N0.getNode(), 4357 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4358 N0.getValueType(), ExtLoad), 4359 ExtLoad.getValue(1)); 4360 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4361 } 4362 } 4363 4364 // fold (sext (and/or/xor (load x), cst)) -> 4365 // (and/or/xor (sextload x), (sext cst)) 4366 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4367 N0.getOpcode() == ISD::XOR) && 4368 isa<LoadSDNode>(N0.getOperand(0)) && 4369 N0.getOperand(1).getOpcode() == ISD::Constant && 4370 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4371 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4372 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4373 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4374 bool DoXform = true; 4375 SmallVector<SDNode*, 4> SetCCs; 4376 if (!N0.hasOneUse()) 4377 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4378 SetCCs, TLI); 4379 if (DoXform) { 4380 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4381 LN0->getChain(), LN0->getBasePtr(), 4382 LN0->getPointerInfo(), 4383 LN0->getMemoryVT(), 4384 LN0->isVolatile(), 4385 LN0->isNonTemporal(), 4386 LN0->getAlignment()); 4387 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4388 Mask = Mask.sext(VT.getSizeInBits()); 4389 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4390 ExtLoad, DAG.getConstant(Mask, VT)); 4391 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4392 N0.getOperand(0).getDebugLoc(), 4393 N0.getOperand(0).getValueType(), ExtLoad); 4394 CombineTo(N, And); 4395 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4396 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4397 ISD::SIGN_EXTEND); 4398 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4399 } 4400 } 4401 } 4402 4403 if (N0.getOpcode() == ISD::SETCC) { 4404 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4405 // Only do this before legalize for now. 4406 if (VT.isVector() && !LegalOperations) { 4407 EVT N0VT = N0.getOperand(0).getValueType(); 4408 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4409 // of the same size as the compared operands. Only optimize sext(setcc()) 4410 // if this is the case. 4411 EVT SVT = TLI.getSetCCResultType(N0VT); 4412 4413 // We know that the # elements of the results is the same as the 4414 // # elements of the compare (and the # elements of the compare result 4415 // for that matter). Check to see that they are the same size. If so, 4416 // we know that the element size of the sext'd result matches the 4417 // element size of the compare operands. 4418 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4419 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4420 N0.getOperand(1), 4421 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4422 // If the desired elements are smaller or larger than the source 4423 // elements we can use a matching integer vector type and then 4424 // truncate/sign extend 4425 EVT MatchingElementType = 4426 EVT::getIntegerVT(*DAG.getContext(), 4427 N0VT.getScalarType().getSizeInBits()); 4428 EVT MatchingVectorType = 4429 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4430 N0VT.getVectorNumElements()); 4431 4432 if (SVT == MatchingVectorType) { 4433 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4434 N0.getOperand(0), N0.getOperand(1), 4435 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4436 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4437 } 4438 } 4439 4440 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4441 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4442 SDValue NegOne = 4443 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4444 SDValue SCC = 4445 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4446 NegOne, DAG.getConstant(0, VT), 4447 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4448 if (SCC.getNode()) return SCC; 4449 if (!LegalOperations || 4450 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4451 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4452 DAG.getSetCC(N->getDebugLoc(), 4453 TLI.getSetCCResultType(VT), 4454 N0.getOperand(0), N0.getOperand(1), 4455 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4456 NegOne, DAG.getConstant(0, VT)); 4457 } 4458 4459 // fold (sext x) -> (zext x) if the sign bit is known zero. 4460 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4461 DAG.SignBitIsZero(N0)) 4462 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4463 4464 return SDValue(); 4465} 4466 4467// isTruncateOf - If N is a truncate of some other value, return true, record 4468// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4469// This function computes KnownZero to avoid a duplicated call to 4470// ComputeMaskedBits in the caller. 4471static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4472 APInt &KnownZero) { 4473 APInt KnownOne; 4474 if (N->getOpcode() == ISD::TRUNCATE) { 4475 Op = N->getOperand(0); 4476 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4477 return true; 4478 } 4479 4480 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4481 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4482 return false; 4483 4484 SDValue Op0 = N->getOperand(0); 4485 SDValue Op1 = N->getOperand(1); 4486 assert(Op0.getValueType() == Op1.getValueType()); 4487 4488 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4489 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4490 if (COp0 && COp0->isNullValue()) 4491 Op = Op1; 4492 else if (COp1 && COp1->isNullValue()) 4493 Op = Op0; 4494 else 4495 return false; 4496 4497 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4498 4499 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4500 return false; 4501 4502 return true; 4503} 4504 4505SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4506 SDValue N0 = N->getOperand(0); 4507 EVT VT = N->getValueType(0); 4508 4509 // fold (zext c1) -> c1 4510 if (isa<ConstantSDNode>(N0)) 4511 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4512 // fold (zext (zext x)) -> (zext x) 4513 // fold (zext (aext x)) -> (zext x) 4514 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4515 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4516 N0.getOperand(0)); 4517 4518 // fold (zext (truncate x)) -> (zext x) or 4519 // (zext (truncate x)) -> (truncate x) 4520 // This is valid when the truncated bits of x are already zero. 4521 // FIXME: We should extend this to work for vectors too. 4522 SDValue Op; 4523 APInt KnownZero; 4524 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4525 APInt TruncatedBits = 4526 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4527 APInt(Op.getValueSizeInBits(), 0) : 4528 APInt::getBitsSet(Op.getValueSizeInBits(), 4529 N0.getValueSizeInBits(), 4530 std::min(Op.getValueSizeInBits(), 4531 VT.getSizeInBits())); 4532 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4533 if (VT.bitsGT(Op.getValueType())) 4534 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4535 if (VT.bitsLT(Op.getValueType())) 4536 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4537 4538 return Op; 4539 } 4540 } 4541 4542 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4543 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4544 if (N0.getOpcode() == ISD::TRUNCATE) { 4545 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4546 if (NarrowLoad.getNode()) { 4547 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4548 if (NarrowLoad.getNode() != N0.getNode()) { 4549 CombineTo(N0.getNode(), NarrowLoad); 4550 // CombineTo deleted the truncate, if needed, but not what's under it. 4551 AddToWorkList(oye); 4552 } 4553 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4554 } 4555 } 4556 4557 // fold (zext (truncate x)) -> (and x, mask) 4558 if (N0.getOpcode() == ISD::TRUNCATE && 4559 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4560 4561 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4562 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4563 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4564 if (NarrowLoad.getNode()) { 4565 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4566 if (NarrowLoad.getNode() != N0.getNode()) { 4567 CombineTo(N0.getNode(), NarrowLoad); 4568 // CombineTo deleted the truncate, if needed, but not what's under it. 4569 AddToWorkList(oye); 4570 } 4571 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4572 } 4573 4574 SDValue Op = N0.getOperand(0); 4575 if (Op.getValueType().bitsLT(VT)) { 4576 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4577 AddToWorkList(Op.getNode()); 4578 } else if (Op.getValueType().bitsGT(VT)) { 4579 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4580 AddToWorkList(Op.getNode()); 4581 } 4582 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4583 N0.getValueType().getScalarType()); 4584 } 4585 4586 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4587 // if either of the casts is not free. 4588 if (N0.getOpcode() == ISD::AND && 4589 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4590 N0.getOperand(1).getOpcode() == ISD::Constant && 4591 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4592 N0.getValueType()) || 4593 !TLI.isZExtFree(N0.getValueType(), VT))) { 4594 SDValue X = N0.getOperand(0).getOperand(0); 4595 if (X.getValueType().bitsLT(VT)) { 4596 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4597 } else if (X.getValueType().bitsGT(VT)) { 4598 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4599 } 4600 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4601 Mask = Mask.zext(VT.getSizeInBits()); 4602 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4603 X, DAG.getConstant(Mask, VT)); 4604 } 4605 4606 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4607 // None of the supported targets knows how to perform load and vector_zext 4608 // on vectors in one instruction. We only perform this transformation on 4609 // scalars. 4610 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4611 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4612 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4613 bool DoXform = true; 4614 SmallVector<SDNode*, 4> SetCCs; 4615 if (!N0.hasOneUse()) 4616 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4617 if (DoXform) { 4618 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4619 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4620 LN0->getChain(), 4621 LN0->getBasePtr(), LN0->getPointerInfo(), 4622 N0.getValueType(), 4623 LN0->isVolatile(), LN0->isNonTemporal(), 4624 LN0->getAlignment()); 4625 CombineTo(N, ExtLoad); 4626 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4627 N0.getValueType(), ExtLoad); 4628 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4629 4630 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4631 ISD::ZERO_EXTEND); 4632 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4633 } 4634 } 4635 4636 // fold (zext (and/or/xor (load x), cst)) -> 4637 // (and/or/xor (zextload x), (zext cst)) 4638 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4639 N0.getOpcode() == ISD::XOR) && 4640 isa<LoadSDNode>(N0.getOperand(0)) && 4641 N0.getOperand(1).getOpcode() == ISD::Constant && 4642 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4643 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4644 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4645 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4646 bool DoXform = true; 4647 SmallVector<SDNode*, 4> SetCCs; 4648 if (!N0.hasOneUse()) 4649 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4650 SetCCs, TLI); 4651 if (DoXform) { 4652 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4653 LN0->getChain(), LN0->getBasePtr(), 4654 LN0->getPointerInfo(), 4655 LN0->getMemoryVT(), 4656 LN0->isVolatile(), 4657 LN0->isNonTemporal(), 4658 LN0->getAlignment()); 4659 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4660 Mask = Mask.zext(VT.getSizeInBits()); 4661 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4662 ExtLoad, DAG.getConstant(Mask, VT)); 4663 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4664 N0.getOperand(0).getDebugLoc(), 4665 N0.getOperand(0).getValueType(), ExtLoad); 4666 CombineTo(N, And); 4667 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4668 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4669 ISD::ZERO_EXTEND); 4670 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4671 } 4672 } 4673 } 4674 4675 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4676 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4677 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4678 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4679 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4680 EVT MemVT = LN0->getMemoryVT(); 4681 if ((!LegalOperations && !LN0->isVolatile()) || 4682 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4683 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4684 LN0->getChain(), 4685 LN0->getBasePtr(), LN0->getPointerInfo(), 4686 MemVT, 4687 LN0->isVolatile(), LN0->isNonTemporal(), 4688 LN0->getAlignment()); 4689 CombineTo(N, ExtLoad); 4690 CombineTo(N0.getNode(), 4691 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4692 ExtLoad), 4693 ExtLoad.getValue(1)); 4694 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4695 } 4696 } 4697 4698 if (N0.getOpcode() == ISD::SETCC) { 4699 if (!LegalOperations && VT.isVector()) { 4700 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4701 // Only do this before legalize for now. 4702 EVT N0VT = N0.getOperand(0).getValueType(); 4703 EVT EltVT = VT.getVectorElementType(); 4704 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4705 DAG.getConstant(1, EltVT)); 4706 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4707 // We know that the # elements of the results is the same as the 4708 // # elements of the compare (and the # elements of the compare result 4709 // for that matter). Check to see that they are the same size. If so, 4710 // we know that the element size of the sext'd result matches the 4711 // element size of the compare operands. 4712 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4713 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4714 N0.getOperand(1), 4715 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4716 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4717 &OneOps[0], OneOps.size())); 4718 4719 // If the desired elements are smaller or larger than the source 4720 // elements we can use a matching integer vector type and then 4721 // truncate/sign extend 4722 EVT MatchingElementType = 4723 EVT::getIntegerVT(*DAG.getContext(), 4724 N0VT.getScalarType().getSizeInBits()); 4725 EVT MatchingVectorType = 4726 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4727 N0VT.getVectorNumElements()); 4728 SDValue VsetCC = 4729 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4730 N0.getOperand(1), 4731 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4732 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4733 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4734 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4735 &OneOps[0], OneOps.size())); 4736 } 4737 4738 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4739 SDValue SCC = 4740 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4741 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4742 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4743 if (SCC.getNode()) return SCC; 4744 } 4745 4746 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4747 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4748 isa<ConstantSDNode>(N0.getOperand(1)) && 4749 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4750 N0.hasOneUse()) { 4751 SDValue ShAmt = N0.getOperand(1); 4752 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4753 if (N0.getOpcode() == ISD::SHL) { 4754 SDValue InnerZExt = N0.getOperand(0); 4755 // If the original shl may be shifting out bits, do not perform this 4756 // transformation. 4757 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4758 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4759 if (ShAmtVal > KnownZeroBits) 4760 return SDValue(); 4761 } 4762 4763 DebugLoc DL = N->getDebugLoc(); 4764 4765 // Ensure that the shift amount is wide enough for the shifted value. 4766 if (VT.getSizeInBits() >= 256) 4767 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4768 4769 return DAG.getNode(N0.getOpcode(), DL, VT, 4770 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4771 ShAmt); 4772 } 4773 4774 return SDValue(); 4775} 4776 4777SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4778 SDValue N0 = N->getOperand(0); 4779 EVT VT = N->getValueType(0); 4780 4781 // fold (aext c1) -> c1 4782 if (isa<ConstantSDNode>(N0)) 4783 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4784 // fold (aext (aext x)) -> (aext x) 4785 // fold (aext (zext x)) -> (zext x) 4786 // fold (aext (sext x)) -> (sext x) 4787 if (N0.getOpcode() == ISD::ANY_EXTEND || 4788 N0.getOpcode() == ISD::ZERO_EXTEND || 4789 N0.getOpcode() == ISD::SIGN_EXTEND) 4790 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4791 4792 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4793 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4794 if (N0.getOpcode() == ISD::TRUNCATE) { 4795 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4796 if (NarrowLoad.getNode()) { 4797 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4798 if (NarrowLoad.getNode() != N0.getNode()) { 4799 CombineTo(N0.getNode(), NarrowLoad); 4800 // CombineTo deleted the truncate, if needed, but not what's under it. 4801 AddToWorkList(oye); 4802 } 4803 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4804 } 4805 } 4806 4807 // fold (aext (truncate x)) 4808 if (N0.getOpcode() == ISD::TRUNCATE) { 4809 SDValue TruncOp = N0.getOperand(0); 4810 if (TruncOp.getValueType() == VT) 4811 return TruncOp; // x iff x size == zext size. 4812 if (TruncOp.getValueType().bitsGT(VT)) 4813 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4814 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4815 } 4816 4817 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4818 // if the trunc is not free. 4819 if (N0.getOpcode() == ISD::AND && 4820 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4821 N0.getOperand(1).getOpcode() == ISD::Constant && 4822 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4823 N0.getValueType())) { 4824 SDValue X = N0.getOperand(0).getOperand(0); 4825 if (X.getValueType().bitsLT(VT)) { 4826 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4827 } else if (X.getValueType().bitsGT(VT)) { 4828 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4829 } 4830 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4831 Mask = Mask.zext(VT.getSizeInBits()); 4832 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4833 X, DAG.getConstant(Mask, VT)); 4834 } 4835 4836 // fold (aext (load x)) -> (aext (truncate (extload x))) 4837 // None of the supported targets knows how to perform load and any_ext 4838 // on vectors in one instruction. We only perform this transformation on 4839 // scalars. 4840 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4841 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4842 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4843 bool DoXform = true; 4844 SmallVector<SDNode*, 4> SetCCs; 4845 if (!N0.hasOneUse()) 4846 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4847 if (DoXform) { 4848 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4849 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4850 LN0->getChain(), 4851 LN0->getBasePtr(), LN0->getPointerInfo(), 4852 N0.getValueType(), 4853 LN0->isVolatile(), LN0->isNonTemporal(), 4854 LN0->getAlignment()); 4855 CombineTo(N, ExtLoad); 4856 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4857 N0.getValueType(), ExtLoad); 4858 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4859 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4860 ISD::ANY_EXTEND); 4861 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4862 } 4863 } 4864 4865 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4866 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4867 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4868 if (N0.getOpcode() == ISD::LOAD && 4869 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4870 N0.hasOneUse()) { 4871 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4872 EVT MemVT = LN0->getMemoryVT(); 4873 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4874 VT, LN0->getChain(), LN0->getBasePtr(), 4875 LN0->getPointerInfo(), MemVT, 4876 LN0->isVolatile(), LN0->isNonTemporal(), 4877 LN0->getAlignment()); 4878 CombineTo(N, ExtLoad); 4879 CombineTo(N0.getNode(), 4880 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4881 N0.getValueType(), ExtLoad), 4882 ExtLoad.getValue(1)); 4883 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4884 } 4885 4886 if (N0.getOpcode() == ISD::SETCC) { 4887 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4888 // Only do this before legalize for now. 4889 if (VT.isVector() && !LegalOperations) { 4890 EVT N0VT = N0.getOperand(0).getValueType(); 4891 // We know that the # elements of the results is the same as the 4892 // # elements of the compare (and the # elements of the compare result 4893 // for that matter). Check to see that they are the same size. If so, 4894 // we know that the element size of the sext'd result matches the 4895 // element size of the compare operands. 4896 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4897 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4898 N0.getOperand(1), 4899 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4900 // If the desired elements are smaller or larger than the source 4901 // elements we can use a matching integer vector type and then 4902 // truncate/sign extend 4903 else { 4904 EVT MatchingElementType = 4905 EVT::getIntegerVT(*DAG.getContext(), 4906 N0VT.getScalarType().getSizeInBits()); 4907 EVT MatchingVectorType = 4908 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4909 N0VT.getVectorNumElements()); 4910 SDValue VsetCC = 4911 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4912 N0.getOperand(1), 4913 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4914 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4915 } 4916 } 4917 4918 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4919 SDValue SCC = 4920 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4921 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4922 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4923 if (SCC.getNode()) 4924 return SCC; 4925 } 4926 4927 return SDValue(); 4928} 4929 4930/// GetDemandedBits - See if the specified operand can be simplified with the 4931/// knowledge that only the bits specified by Mask are used. If so, return the 4932/// simpler operand, otherwise return a null SDValue. 4933SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4934 switch (V.getOpcode()) { 4935 default: break; 4936 case ISD::Constant: { 4937 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4938 assert(CV != 0 && "Const value should be ConstSDNode."); 4939 const APInt &CVal = CV->getAPIntValue(); 4940 APInt NewVal = CVal & Mask; 4941 if (NewVal != CVal) { 4942 return DAG.getConstant(NewVal, V.getValueType()); 4943 } 4944 break; 4945 } 4946 case ISD::OR: 4947 case ISD::XOR: 4948 // If the LHS or RHS don't contribute bits to the or, drop them. 4949 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4950 return V.getOperand(1); 4951 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4952 return V.getOperand(0); 4953 break; 4954 case ISD::SRL: 4955 // Only look at single-use SRLs. 4956 if (!V.getNode()->hasOneUse()) 4957 break; 4958 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4959 // See if we can recursively simplify the LHS. 4960 unsigned Amt = RHSC->getZExtValue(); 4961 4962 // Watch out for shift count overflow though. 4963 if (Amt >= Mask.getBitWidth()) break; 4964 APInt NewMask = Mask << Amt; 4965 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4966 if (SimplifyLHS.getNode()) 4967 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4968 SimplifyLHS, V.getOperand(1)); 4969 } 4970 } 4971 return SDValue(); 4972} 4973 4974/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4975/// bits and then truncated to a narrower type and where N is a multiple 4976/// of number of bits of the narrower type, transform it to a narrower load 4977/// from address + N / num of bits of new type. If the result is to be 4978/// extended, also fold the extension to form a extending load. 4979SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4980 unsigned Opc = N->getOpcode(); 4981 4982 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4983 SDValue N0 = N->getOperand(0); 4984 EVT VT = N->getValueType(0); 4985 EVT ExtVT = VT; 4986 4987 // This transformation isn't valid for vector loads. 4988 if (VT.isVector()) 4989 return SDValue(); 4990 4991 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4992 // extended to VT. 4993 if (Opc == ISD::SIGN_EXTEND_INREG) { 4994 ExtType = ISD::SEXTLOAD; 4995 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4996 } else if (Opc == ISD::SRL) { 4997 // Another special-case: SRL is basically zero-extending a narrower value. 4998 ExtType = ISD::ZEXTLOAD; 4999 N0 = SDValue(N, 0); 5000 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 5001 if (!N01) return SDValue(); 5002 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 5003 VT.getSizeInBits() - N01->getZExtValue()); 5004 } 5005 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5006 return SDValue(); 5007 5008 unsigned EVTBits = ExtVT.getSizeInBits(); 5009 5010 // Do not generate loads of non-round integer types since these can 5011 // be expensive (and would be wrong if the type is not byte sized). 5012 if (!ExtVT.isRound()) 5013 return SDValue(); 5014 5015 unsigned ShAmt = 0; 5016 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5017 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5018 ShAmt = N01->getZExtValue(); 5019 // Is the shift amount a multiple of size of VT? 5020 if ((ShAmt & (EVTBits-1)) == 0) { 5021 N0 = N0.getOperand(0); 5022 // Is the load width a multiple of size of VT? 5023 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5024 return SDValue(); 5025 } 5026 5027 // At this point, we must have a load or else we can't do the transform. 5028 if (!isa<LoadSDNode>(N0)) return SDValue(); 5029 5030 // If the shift amount is larger than the input type then we're not 5031 // accessing any of the loaded bytes. If the load was a zextload/extload 5032 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5033 // If the load was a sextload then the result is a splat of the sign bit 5034 // of the extended byte. This is not worth optimizing for. 5035 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5036 return SDValue(); 5037 } 5038 } 5039 5040 // If the load is shifted left (and the result isn't shifted back right), 5041 // we can fold the truncate through the shift. 5042 unsigned ShLeftAmt = 0; 5043 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5044 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5045 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5046 ShLeftAmt = N01->getZExtValue(); 5047 N0 = N0.getOperand(0); 5048 } 5049 } 5050 5051 // If we haven't found a load, we can't narrow it. Don't transform one with 5052 // multiple uses, this would require adding a new load. 5053 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 5054 // Don't change the width of a volatile load. 5055 cast<LoadSDNode>(N0)->isVolatile()) 5056 return SDValue(); 5057 5058 // Verify that we are actually reducing a load width here. 5059 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 5060 return SDValue(); 5061 5062 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5063 EVT PtrType = N0.getOperand(1).getValueType(); 5064 5065 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5066 // It's not possible to generate a constant of extended or untyped type. 5067 return SDValue(); 5068 5069 // For big endian targets, we need to adjust the offset to the pointer to 5070 // load the correct bytes. 5071 if (TLI.isBigEndian()) { 5072 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5073 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5074 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5075 } 5076 5077 uint64_t PtrOff = ShAmt / 8; 5078 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5079 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5080 PtrType, LN0->getBasePtr(), 5081 DAG.getConstant(PtrOff, PtrType)); 5082 AddToWorkList(NewPtr.getNode()); 5083 5084 SDValue Load; 5085 if (ExtType == ISD::NON_EXTLOAD) 5086 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5087 LN0->getPointerInfo().getWithOffset(PtrOff), 5088 LN0->isVolatile(), LN0->isNonTemporal(), 5089 LN0->isInvariant(), NewAlign); 5090 else 5091 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5092 LN0->getPointerInfo().getWithOffset(PtrOff), 5093 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5094 NewAlign); 5095 5096 // Replace the old load's chain with the new load's chain. 5097 WorkListRemover DeadNodes(*this); 5098 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5099 5100 // Shift the result left, if we've swallowed a left shift. 5101 SDValue Result = Load; 5102 if (ShLeftAmt != 0) { 5103 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5104 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5105 ShImmTy = VT; 5106 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5107 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5108 } 5109 5110 // Return the new loaded value. 5111 return Result; 5112} 5113 5114SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5115 SDValue N0 = N->getOperand(0); 5116 SDValue N1 = N->getOperand(1); 5117 EVT VT = N->getValueType(0); 5118 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5119 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5120 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5121 5122 // fold (sext_in_reg c1) -> c1 5123 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5124 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5125 5126 // If the input is already sign extended, just drop the extension. 5127 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5128 return N0; 5129 5130 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5131 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5132 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5133 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5134 N0.getOperand(0), N1); 5135 } 5136 5137 // fold (sext_in_reg (sext x)) -> (sext x) 5138 // fold (sext_in_reg (aext x)) -> (sext x) 5139 // if x is small enough. 5140 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5141 SDValue N00 = N0.getOperand(0); 5142 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5143 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5144 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5145 } 5146 5147 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5148 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5149 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5150 5151 // fold operands of sext_in_reg based on knowledge that the top bits are not 5152 // demanded. 5153 if (SimplifyDemandedBits(SDValue(N, 0))) 5154 return SDValue(N, 0); 5155 5156 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5157 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5158 SDValue NarrowLoad = ReduceLoadWidth(N); 5159 if (NarrowLoad.getNode()) 5160 return NarrowLoad; 5161 5162 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5163 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5164 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5165 if (N0.getOpcode() == ISD::SRL) { 5166 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5167 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5168 // We can turn this into an SRA iff the input to the SRL is already sign 5169 // extended enough. 5170 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5171 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5172 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5173 N0.getOperand(0), N0.getOperand(1)); 5174 } 5175 } 5176 5177 // fold (sext_inreg (extload x)) -> (sextload x) 5178 if (ISD::isEXTLoad(N0.getNode()) && 5179 ISD::isUNINDEXEDLoad(N0.getNode()) && 5180 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5181 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5182 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5183 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5184 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5185 LN0->getChain(), 5186 LN0->getBasePtr(), LN0->getPointerInfo(), 5187 EVT, 5188 LN0->isVolatile(), LN0->isNonTemporal(), 5189 LN0->getAlignment()); 5190 CombineTo(N, ExtLoad); 5191 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5192 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5193 } 5194 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5195 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5196 N0.hasOneUse() && 5197 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5198 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5199 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5200 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5201 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5202 LN0->getChain(), 5203 LN0->getBasePtr(), LN0->getPointerInfo(), 5204 EVT, 5205 LN0->isVolatile(), LN0->isNonTemporal(), 5206 LN0->getAlignment()); 5207 CombineTo(N, ExtLoad); 5208 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5209 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5210 } 5211 5212 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5213 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5214 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5215 N0.getOperand(1), false); 5216 if (BSwap.getNode() != 0) 5217 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5218 BSwap, N1); 5219 } 5220 5221 return SDValue(); 5222} 5223 5224SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5225 SDValue N0 = N->getOperand(0); 5226 EVT VT = N->getValueType(0); 5227 bool isLE = TLI.isLittleEndian(); 5228 5229 // noop truncate 5230 if (N0.getValueType() == N->getValueType(0)) 5231 return N0; 5232 // fold (truncate c1) -> c1 5233 if (isa<ConstantSDNode>(N0)) 5234 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5235 // fold (truncate (truncate x)) -> (truncate x) 5236 if (N0.getOpcode() == ISD::TRUNCATE) 5237 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5238 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5239 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5240 N0.getOpcode() == ISD::SIGN_EXTEND || 5241 N0.getOpcode() == ISD::ANY_EXTEND) { 5242 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5243 // if the source is smaller than the dest, we still need an extend 5244 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5245 N0.getOperand(0)); 5246 if (N0.getOperand(0).getValueType().bitsGT(VT)) 5247 // if the source is larger than the dest, than we just need the truncate 5248 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5249 // if the source and dest are the same type, we can drop both the extend 5250 // and the truncate. 5251 return N0.getOperand(0); 5252 } 5253 5254 // Fold extract-and-trunc into a narrow extract. For example: 5255 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5256 // i32 y = TRUNCATE(i64 x) 5257 // -- becomes -- 5258 // v16i8 b = BITCAST (v2i64 val) 5259 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5260 // 5261 // Note: We only run this optimization after type legalization (which often 5262 // creates this pattern) and before operation legalization after which 5263 // we need to be more careful about the vector instructions that we generate. 5264 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5265 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5266 5267 EVT VecTy = N0.getOperand(0).getValueType(); 5268 EVT ExTy = N0.getValueType(); 5269 EVT TrTy = N->getValueType(0); 5270 5271 unsigned NumElem = VecTy.getVectorNumElements(); 5272 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5273 5274 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5275 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5276 5277 SDValue EltNo = N0->getOperand(1); 5278 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5279 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5280 EVT IndexTy = N0->getOperand(1).getValueType(); 5281 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5282 5283 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5284 NVT, N0.getOperand(0)); 5285 5286 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5287 N->getDebugLoc(), TrTy, V, 5288 DAG.getConstant(Index, IndexTy)); 5289 } 5290 } 5291 5292 // See if we can simplify the input to this truncate through knowledge that 5293 // only the low bits are being used. 5294 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5295 // Currently we only perform this optimization on scalars because vectors 5296 // may have different active low bits. 5297 if (!VT.isVector()) { 5298 SDValue Shorter = 5299 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5300 VT.getSizeInBits())); 5301 if (Shorter.getNode()) 5302 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5303 } 5304 // fold (truncate (load x)) -> (smaller load x) 5305 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5306 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5307 SDValue Reduced = ReduceLoadWidth(N); 5308 if (Reduced.getNode()) 5309 return Reduced; 5310 } 5311 // fold (trunc (fptoXi x)) -> (smaller fptoXi x) 5312 if ((N0.getOpcode() == ISD::FP_TO_UINT || 5313 N0.getOpcode() == ISD::FP_TO_SINT) && !LegalTypes) 5314 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 5315 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)), 5316 // where ... are all 'undef'. 5317 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { 5318 SmallVector<EVT, 8> VTs; 5319 SDValue V; 5320 unsigned Idx = 0; 5321 unsigned NumDefs = 0; 5322 5323 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 5324 SDValue X = N0.getOperand(i); 5325 if (X.getOpcode() != ISD::UNDEF) { 5326 V = X; 5327 Idx = i; 5328 NumDefs++; 5329 } 5330 // Stop if more than one members are non-undef. 5331 if (NumDefs > 1) 5332 break; 5333 VTs.push_back(EVT::getVectorVT(*DAG.getContext(), 5334 VT.getVectorElementType(), 5335 X.getValueType().getVectorNumElements())); 5336 } 5337 5338 if (NumDefs == 0) 5339 return DAG.getUNDEF(VT); 5340 5341 if (NumDefs == 1) { 5342 assert(V.getNode() && "The single defined operand is empty!"); 5343 SmallVector<SDValue, 8> Opnds; 5344 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 5345 if (i != Idx) { 5346 Opnds.push_back(DAG.getUNDEF(VTs[i])); 5347 continue; 5348 } 5349 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V); 5350 AddToWorkList(NV.getNode()); 5351 Opnds.push_back(NV); 5352 } 5353 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 5354 &Opnds[0], Opnds.size()); 5355 } 5356 } 5357 5358 // Simplify the operands using demanded-bits information. 5359 if (!VT.isVector() && 5360 SimplifyDemandedBits(SDValue(N, 0))) 5361 return SDValue(N, 0); 5362 5363 return SDValue(); 5364} 5365 5366static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5367 SDValue Elt = N->getOperand(i); 5368 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5369 return Elt.getNode(); 5370 return Elt.getOperand(Elt.getResNo()).getNode(); 5371} 5372 5373/// CombineConsecutiveLoads - build_pair (load, load) -> load 5374/// if load locations are consecutive. 5375SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5376 assert(N->getOpcode() == ISD::BUILD_PAIR); 5377 5378 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5379 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5380 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5381 LD1->getPointerInfo().getAddrSpace() != 5382 LD2->getPointerInfo().getAddrSpace()) 5383 return SDValue(); 5384 EVT LD1VT = LD1->getValueType(0); 5385 5386 if (ISD::isNON_EXTLoad(LD2) && 5387 LD2->hasOneUse() && 5388 // If both are volatile this would reduce the number of volatile loads. 5389 // If one is volatile it might be ok, but play conservative and bail out. 5390 !LD1->isVolatile() && 5391 !LD2->isVolatile() && 5392 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5393 unsigned Align = LD1->getAlignment(); 5394 unsigned NewAlign = TLI.getDataLayout()-> 5395 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5396 5397 if (NewAlign <= Align && 5398 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5399 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5400 LD1->getBasePtr(), LD1->getPointerInfo(), 5401 false, false, false, Align); 5402 } 5403 5404 return SDValue(); 5405} 5406 5407SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5408 SDValue N0 = N->getOperand(0); 5409 EVT VT = N->getValueType(0); 5410 5411 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5412 // Only do this before legalize, since afterward the target may be depending 5413 // on the bitconvert. 5414 // First check to see if this is all constant. 5415 if (!LegalTypes && 5416 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5417 VT.isVector()) { 5418 bool isSimple = true; 5419 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5420 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5421 N0.getOperand(i).getOpcode() != ISD::Constant && 5422 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5423 isSimple = false; 5424 break; 5425 } 5426 5427 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5428 assert(!DestEltVT.isVector() && 5429 "Element type of vector ValueType must not be vector!"); 5430 if (isSimple) 5431 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5432 } 5433 5434 // If the input is a constant, let getNode fold it. 5435 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5436 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5437 if (Res.getNode() != N) { 5438 if (!LegalOperations || 5439 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5440 return Res; 5441 5442 // Folding it resulted in an illegal node, and it's too late to 5443 // do that. Clean up the old node and forego the transformation. 5444 // Ideally this won't happen very often, because instcombine 5445 // and the earlier dagcombine runs (where illegal nodes are 5446 // permitted) should have folded most of them already. 5447 DAG.DeleteNode(Res.getNode()); 5448 } 5449 } 5450 5451 // (conv (conv x, t1), t2) -> (conv x, t2) 5452 if (N0.getOpcode() == ISD::BITCAST) 5453 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5454 N0.getOperand(0)); 5455 5456 // fold (conv (load x)) -> (load (conv*)x) 5457 // If the resultant load doesn't need a higher alignment than the original! 5458 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5459 // Do not change the width of a volatile load. 5460 !cast<LoadSDNode>(N0)->isVolatile() && 5461 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5462 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5463 unsigned Align = TLI.getDataLayout()-> 5464 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5465 unsigned OrigAlign = LN0->getAlignment(); 5466 5467 if (Align <= OrigAlign) { 5468 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5469 LN0->getBasePtr(), LN0->getPointerInfo(), 5470 LN0->isVolatile(), LN0->isNonTemporal(), 5471 LN0->isInvariant(), OrigAlign); 5472 AddToWorkList(N); 5473 CombineTo(N0.getNode(), 5474 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5475 N0.getValueType(), Load), 5476 Load.getValue(1)); 5477 return Load; 5478 } 5479 } 5480 5481 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5482 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5483 // This often reduces constant pool loads. 5484 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5485 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5486 N0.getNode()->hasOneUse() && VT.isInteger() && 5487 !VT.isVector() && !N0.getValueType().isVector()) { 5488 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5489 N0.getOperand(0)); 5490 AddToWorkList(NewConv.getNode()); 5491 5492 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5493 if (N0.getOpcode() == ISD::FNEG) 5494 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5495 NewConv, DAG.getConstant(SignBit, VT)); 5496 assert(N0.getOpcode() == ISD::FABS); 5497 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5498 NewConv, DAG.getConstant(~SignBit, VT)); 5499 } 5500 5501 // fold (bitconvert (fcopysign cst, x)) -> 5502 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5503 // Note that we don't handle (copysign x, cst) because this can always be 5504 // folded to an fneg or fabs. 5505 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5506 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5507 VT.isInteger() && !VT.isVector()) { 5508 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5509 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5510 if (isTypeLegal(IntXVT)) { 5511 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5512 IntXVT, N0.getOperand(1)); 5513 AddToWorkList(X.getNode()); 5514 5515 // If X has a different width than the result/lhs, sext it or truncate it. 5516 unsigned VTWidth = VT.getSizeInBits(); 5517 if (OrigXWidth < VTWidth) { 5518 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5519 AddToWorkList(X.getNode()); 5520 } else if (OrigXWidth > VTWidth) { 5521 // To get the sign bit in the right place, we have to shift it right 5522 // before truncating. 5523 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5524 X.getValueType(), X, 5525 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5526 AddToWorkList(X.getNode()); 5527 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5528 AddToWorkList(X.getNode()); 5529 } 5530 5531 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5532 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5533 X, DAG.getConstant(SignBit, VT)); 5534 AddToWorkList(X.getNode()); 5535 5536 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5537 VT, N0.getOperand(0)); 5538 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5539 Cst, DAG.getConstant(~SignBit, VT)); 5540 AddToWorkList(Cst.getNode()); 5541 5542 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5543 } 5544 } 5545 5546 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5547 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5548 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5549 if (CombineLD.getNode()) 5550 return CombineLD; 5551 } 5552 5553 return SDValue(); 5554} 5555 5556SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5557 EVT VT = N->getValueType(0); 5558 return CombineConsecutiveLoads(N, VT); 5559} 5560 5561/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5562/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5563/// destination element value type. 5564SDValue DAGCombiner:: 5565ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5566 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5567 5568 // If this is already the right type, we're done. 5569 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5570 5571 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5572 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5573 5574 // If this is a conversion of N elements of one type to N elements of another 5575 // type, convert each element. This handles FP<->INT cases. 5576 if (SrcBitSize == DstBitSize) { 5577 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5578 BV->getValueType(0).getVectorNumElements()); 5579 5580 // Due to the FP element handling below calling this routine recursively, 5581 // we can end up with a scalar-to-vector node here. 5582 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5583 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5584 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5585 DstEltVT, BV->getOperand(0))); 5586 5587 SmallVector<SDValue, 8> Ops; 5588 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5589 SDValue Op = BV->getOperand(i); 5590 // If the vector element type is not legal, the BUILD_VECTOR operands 5591 // are promoted and implicitly truncated. Make that explicit here. 5592 if (Op.getValueType() != SrcEltVT) 5593 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5594 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5595 DstEltVT, Op)); 5596 AddToWorkList(Ops.back().getNode()); 5597 } 5598 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5599 &Ops[0], Ops.size()); 5600 } 5601 5602 // Otherwise, we're growing or shrinking the elements. To avoid having to 5603 // handle annoying details of growing/shrinking FP values, we convert them to 5604 // int first. 5605 if (SrcEltVT.isFloatingPoint()) { 5606 // Convert the input float vector to a int vector where the elements are the 5607 // same sizes. 5608 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5609 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5610 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5611 SrcEltVT = IntVT; 5612 } 5613 5614 // Now we know the input is an integer vector. If the output is a FP type, 5615 // convert to integer first, then to FP of the right size. 5616 if (DstEltVT.isFloatingPoint()) { 5617 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5618 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5619 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5620 5621 // Next, convert to FP elements of the same size. 5622 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5623 } 5624 5625 // Okay, we know the src/dst types are both integers of differing types. 5626 // Handling growing first. 5627 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5628 if (SrcBitSize < DstBitSize) { 5629 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5630 5631 SmallVector<SDValue, 8> Ops; 5632 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5633 i += NumInputsPerOutput) { 5634 bool isLE = TLI.isLittleEndian(); 5635 APInt NewBits = APInt(DstBitSize, 0); 5636 bool EltIsUndef = true; 5637 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5638 // Shift the previously computed bits over. 5639 NewBits <<= SrcBitSize; 5640 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5641 if (Op.getOpcode() == ISD::UNDEF) continue; 5642 EltIsUndef = false; 5643 5644 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5645 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5646 } 5647 5648 if (EltIsUndef) 5649 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5650 else 5651 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5652 } 5653 5654 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5655 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5656 &Ops[0], Ops.size()); 5657 } 5658 5659 // Finally, this must be the case where we are shrinking elements: each input 5660 // turns into multiple outputs. 5661 bool isS2V = ISD::isScalarToVector(BV); 5662 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5663 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5664 NumOutputsPerInput*BV->getNumOperands()); 5665 SmallVector<SDValue, 8> Ops; 5666 5667 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5668 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5669 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5670 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5671 continue; 5672 } 5673 5674 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5675 getAPIntValue().zextOrTrunc(SrcBitSize); 5676 5677 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5678 APInt ThisVal = OpVal.trunc(DstBitSize); 5679 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5680 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5681 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5682 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5683 Ops[0]); 5684 OpVal = OpVal.lshr(DstBitSize); 5685 } 5686 5687 // For big endian targets, swap the order of the pieces of each element. 5688 if (TLI.isBigEndian()) 5689 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5690 } 5691 5692 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5693 &Ops[0], Ops.size()); 5694} 5695 5696SDValue DAGCombiner::visitFADD(SDNode *N) { 5697 SDValue N0 = N->getOperand(0); 5698 SDValue N1 = N->getOperand(1); 5699 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5700 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5701 EVT VT = N->getValueType(0); 5702 5703 // fold vector ops 5704 if (VT.isVector()) { 5705 SDValue FoldedVOp = SimplifyVBinOp(N); 5706 if (FoldedVOp.getNode()) return FoldedVOp; 5707 } 5708 5709 // fold (fadd c1, c2) -> c1 + c2 5710 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5711 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5712 // canonicalize constant to RHS 5713 if (N0CFP && !N1CFP) 5714 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5715 // fold (fadd A, 0) -> A 5716 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5717 N1CFP->getValueAPF().isZero()) 5718 return N0; 5719 // fold (fadd A, (fneg B)) -> (fsub A, B) 5720 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5721 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5722 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5723 GetNegatedExpression(N1, DAG, LegalOperations)); 5724 // fold (fadd (fneg A), B) -> (fsub B, A) 5725 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5726 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5727 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5728 GetNegatedExpression(N0, DAG, LegalOperations)); 5729 5730 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5731 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5732 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5733 isa<ConstantFPSDNode>(N0.getOperand(1))) 5734 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5735 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5736 N0.getOperand(1), N1)); 5737 5738 // In unsafe math mode, we can fold chains of FADD's of the same value 5739 // into multiplications. This transform is not safe in general because 5740 // we are reducing the number of rounding steps. 5741 if (DAG.getTarget().Options.UnsafeFPMath && 5742 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5743 !N0CFP && !N1CFP) { 5744 if (N0.getOpcode() == ISD::FMUL) { 5745 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5746 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 5747 5748 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5749 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 5750 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5751 SDValue(CFP00, 0), 5752 DAG.getConstantFP(1.0, VT)); 5753 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5754 N1, NewCFP); 5755 } 5756 5757 // (fadd (fmul x, c), x) -> (fmul c+1, x) 5758 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 5759 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5760 SDValue(CFP01, 0), 5761 DAG.getConstantFP(1.0, VT)); 5762 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5763 N1, NewCFP); 5764 } 5765 5766 // (fadd (fadd x, x), x) -> (fmul 3.0, x) 5767 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) && 5768 N0.getOperand(0) == N1) { 5769 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5770 N1, DAG.getConstantFP(3.0, VT)); 5771 } 5772 5773 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x) 5774 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 5775 N1.getOperand(0) == N1.getOperand(1) && 5776 N0.getOperand(1) == N1.getOperand(0)) { 5777 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5778 SDValue(CFP00, 0), 5779 DAG.getConstantFP(2.0, VT)); 5780 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5781 N0.getOperand(1), NewCFP); 5782 } 5783 5784 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x) 5785 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 5786 N1.getOperand(0) == N1.getOperand(1) && 5787 N0.getOperand(0) == N1.getOperand(0)) { 5788 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5789 SDValue(CFP01, 0), 5790 DAG.getConstantFP(2.0, VT)); 5791 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5792 N0.getOperand(0), NewCFP); 5793 } 5794 } 5795 5796 if (N1.getOpcode() == ISD::FMUL) { 5797 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5798 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 5799 5800 // (fadd x, (fmul c, x)) -> (fmul c+1, x) 5801 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 5802 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5803 SDValue(CFP10, 0), 5804 DAG.getConstantFP(1.0, VT)); 5805 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5806 N0, NewCFP); 5807 } 5808 5809 // (fadd x, (fmul x, c)) -> (fmul c+1, x) 5810 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 5811 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5812 SDValue(CFP11, 0), 5813 DAG.getConstantFP(1.0, VT)); 5814 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5815 N0, NewCFP); 5816 } 5817 5818 // (fadd x, (fadd x, x)) -> (fmul 3.0, x) 5819 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) && 5820 N1.getOperand(0) == N0) { 5821 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5822 N0, DAG.getConstantFP(3.0, VT)); 5823 } 5824 5825 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x) 5826 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD && 5827 N1.getOperand(0) == N1.getOperand(1) && 5828 N0.getOperand(1) == N1.getOperand(0)) { 5829 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5830 SDValue(CFP10, 0), 5831 DAG.getConstantFP(2.0, VT)); 5832 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5833 N0.getOperand(1), NewCFP); 5834 } 5835 5836 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x) 5837 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD && 5838 N1.getOperand(0) == N1.getOperand(1) && 5839 N0.getOperand(0) == N1.getOperand(0)) { 5840 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5841 SDValue(CFP11, 0), 5842 DAG.getConstantFP(2.0, VT)); 5843 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5844 N0.getOperand(0), NewCFP); 5845 } 5846 } 5847 5848 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x) 5849 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 5850 N0.getOperand(0) == N0.getOperand(1) && 5851 N1.getOperand(0) == N1.getOperand(1) && 5852 N0.getOperand(0) == N1.getOperand(0)) { 5853 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5854 N0.getOperand(0), 5855 DAG.getConstantFP(4.0, VT)); 5856 } 5857 } 5858 5859 // FADD -> FMA combines: 5860 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5861 DAG.getTarget().Options.UnsafeFPMath) && 5862 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5863 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5864 5865 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 5866 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5867 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5868 N0.getOperand(0), N0.getOperand(1), N1); 5869 } 5870 5871 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 5872 // Note: Commutes FADD operands. 5873 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5874 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5875 N1.getOperand(0), N1.getOperand(1), N0); 5876 } 5877 } 5878 5879 return SDValue(); 5880} 5881 5882SDValue DAGCombiner::visitFSUB(SDNode *N) { 5883 SDValue N0 = N->getOperand(0); 5884 SDValue N1 = N->getOperand(1); 5885 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5886 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5887 EVT VT = N->getValueType(0); 5888 DebugLoc dl = N->getDebugLoc(); 5889 5890 // fold vector ops 5891 if (VT.isVector()) { 5892 SDValue FoldedVOp = SimplifyVBinOp(N); 5893 if (FoldedVOp.getNode()) return FoldedVOp; 5894 } 5895 5896 // fold (fsub c1, c2) -> c1-c2 5897 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5898 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5899 // fold (fsub A, 0) -> A 5900 if (DAG.getTarget().Options.UnsafeFPMath && 5901 N1CFP && N1CFP->getValueAPF().isZero()) 5902 return N0; 5903 // fold (fsub 0, B) -> -B 5904 if (DAG.getTarget().Options.UnsafeFPMath && 5905 N0CFP && N0CFP->getValueAPF().isZero()) { 5906 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5907 return GetNegatedExpression(N1, DAG, LegalOperations); 5908 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5909 return DAG.getNode(ISD::FNEG, dl, VT, N1); 5910 } 5911 // fold (fsub A, (fneg B)) -> (fadd A, B) 5912 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5913 return DAG.getNode(ISD::FADD, dl, VT, N0, 5914 GetNegatedExpression(N1, DAG, LegalOperations)); 5915 5916 // If 'unsafe math' is enabled, fold 5917 // (fsub x, x) -> 0.0 & 5918 // (fsub x, (fadd x, y)) -> (fneg y) & 5919 // (fsub x, (fadd y, x)) -> (fneg y) 5920 if (DAG.getTarget().Options.UnsafeFPMath) { 5921 if (N0 == N1) 5922 return DAG.getConstantFP(0.0f, VT); 5923 5924 if (N1.getOpcode() == ISD::FADD) { 5925 SDValue N10 = N1->getOperand(0); 5926 SDValue N11 = N1->getOperand(1); 5927 5928 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5929 &DAG.getTarget().Options)) 5930 return GetNegatedExpression(N11, DAG, LegalOperations); 5931 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5932 &DAG.getTarget().Options)) 5933 return GetNegatedExpression(N10, DAG, LegalOperations); 5934 } 5935 } 5936 5937 // FSUB -> FMA combines: 5938 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5939 DAG.getTarget().Options.UnsafeFPMath) && 5940 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5941 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5942 5943 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 5944 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5945 return DAG.getNode(ISD::FMA, dl, VT, 5946 N0.getOperand(0), N0.getOperand(1), 5947 DAG.getNode(ISD::FNEG, dl, VT, N1)); 5948 } 5949 5950 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 5951 // Note: Commutes FSUB operands. 5952 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5953 return DAG.getNode(ISD::FMA, dl, VT, 5954 DAG.getNode(ISD::FNEG, dl, VT, 5955 N1.getOperand(0)), 5956 N1.getOperand(1), N0); 5957 } 5958 5959 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 5960 if (N0.getOpcode() == ISD::FNEG && 5961 N0.getOperand(0).getOpcode() == ISD::FMUL && 5962 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 5963 SDValue N00 = N0.getOperand(0).getOperand(0); 5964 SDValue N01 = N0.getOperand(0).getOperand(1); 5965 return DAG.getNode(ISD::FMA, dl, VT, 5966 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 5967 DAG.getNode(ISD::FNEG, dl, VT, N1)); 5968 } 5969 } 5970 5971 return SDValue(); 5972} 5973 5974SDValue DAGCombiner::visitFMUL(SDNode *N) { 5975 SDValue N0 = N->getOperand(0); 5976 SDValue N1 = N->getOperand(1); 5977 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5978 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5979 EVT VT = N->getValueType(0); 5980 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5981 5982 // fold vector ops 5983 if (VT.isVector()) { 5984 SDValue FoldedVOp = SimplifyVBinOp(N); 5985 if (FoldedVOp.getNode()) return FoldedVOp; 5986 } 5987 5988 // fold (fmul c1, c2) -> c1*c2 5989 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5990 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5991 // canonicalize constant to RHS 5992 if (N0CFP && !N1CFP) 5993 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5994 // fold (fmul A, 0) -> 0 5995 if (DAG.getTarget().Options.UnsafeFPMath && 5996 N1CFP && N1CFP->getValueAPF().isZero()) 5997 return N1; 5998 // fold (fmul A, 0) -> 0, vector edition. 5999 if (DAG.getTarget().Options.UnsafeFPMath && 6000 ISD::isBuildVectorAllZeros(N1.getNode())) 6001 return N1; 6002 // fold (fmul A, 1.0) -> A 6003 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6004 return N0; 6005 // fold (fmul X, 2.0) -> (fadd X, X) 6006 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 6007 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 6008 // fold (fmul X, -1.0) -> (fneg X) 6009 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 6010 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6011 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 6012 6013 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 6014 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6015 &DAG.getTarget().Options)) { 6016 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6017 &DAG.getTarget().Options)) { 6018 // Both can be negated for free, check to see if at least one is cheaper 6019 // negated. 6020 if (LHSNeg == 2 || RHSNeg == 2) 6021 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6022 GetNegatedExpression(N0, DAG, LegalOperations), 6023 GetNegatedExpression(N1, DAG, LegalOperations)); 6024 } 6025 } 6026 6027 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 6028 if (DAG.getTarget().Options.UnsafeFPMath && 6029 N1CFP && N0.getOpcode() == ISD::FMUL && 6030 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 6031 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 6032 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6033 N0.getOperand(1), N1)); 6034 6035 return SDValue(); 6036} 6037 6038SDValue DAGCombiner::visitFMA(SDNode *N) { 6039 SDValue N0 = N->getOperand(0); 6040 SDValue N1 = N->getOperand(1); 6041 SDValue N2 = N->getOperand(2); 6042 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6043 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6044 EVT VT = N->getValueType(0); 6045 DebugLoc dl = N->getDebugLoc(); 6046 6047 if (N0CFP && N0CFP->isExactlyValue(1.0)) 6048 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); 6049 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6050 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); 6051 6052 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6053 if (N0CFP && !N1CFP) 6054 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); 6055 6056 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6057 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6058 N2.getOpcode() == ISD::FMUL && 6059 N0 == N2.getOperand(0) && 6060 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6061 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6062 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6063 } 6064 6065 6066 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6067 if (DAG.getTarget().Options.UnsafeFPMath && 6068 N0.getOpcode() == ISD::FMUL && N1CFP && 6069 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6070 return DAG.getNode(ISD::FMA, dl, VT, 6071 N0.getOperand(0), 6072 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6073 N2); 6074 } 6075 6076 // (fma x, 1, y) -> (fadd x, y) 6077 // (fma x, -1, y) -> (fadd (fneg x), y) 6078 if (N1CFP) { 6079 if (N1CFP->isExactlyValue(1.0)) 6080 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6081 6082 if (N1CFP->isExactlyValue(-1.0) && 6083 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6084 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6085 AddToWorkList(RHSNeg.getNode()); 6086 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6087 } 6088 } 6089 6090 // (fma x, c, x) -> (fmul x, (c+1)) 6091 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) { 6092 return DAG.getNode(ISD::FMUL, dl, VT, 6093 N0, 6094 DAG.getNode(ISD::FADD, dl, VT, 6095 N1, DAG.getConstantFP(1.0, VT))); 6096 } 6097 6098 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6099 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6100 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { 6101 return DAG.getNode(ISD::FMUL, dl, VT, 6102 N0, 6103 DAG.getNode(ISD::FADD, dl, VT, 6104 N1, DAG.getConstantFP(-1.0, VT))); 6105 } 6106 6107 6108 return SDValue(); 6109} 6110 6111SDValue DAGCombiner::visitFDIV(SDNode *N) { 6112 SDValue N0 = N->getOperand(0); 6113 SDValue N1 = N->getOperand(1); 6114 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6115 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6116 EVT VT = N->getValueType(0); 6117 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6118 6119 // fold vector ops 6120 if (VT.isVector()) { 6121 SDValue FoldedVOp = SimplifyVBinOp(N); 6122 if (FoldedVOp.getNode()) return FoldedVOp; 6123 } 6124 6125 // fold (fdiv c1, c2) -> c1/c2 6126 if (N0CFP && N1CFP && VT != MVT::ppcf128) 6127 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 6128 6129 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6130 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) { 6131 // Compute the reciprocal 1.0 / c2. 6132 APFloat N1APF = N1CFP->getValueAPF(); 6133 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6134 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6135 // Only do the transform if the reciprocal is a legal fp immediate that 6136 // isn't too nasty (eg NaN, denormal, ...). 6137 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6138 (!LegalOperations || 6139 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6140 // backend)... we should handle this gracefully after Legalize. 6141 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6142 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6143 TLI.isFPImmLegal(Recip, VT))) 6144 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 6145 DAG.getConstantFP(Recip, VT)); 6146 } 6147 6148 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6149 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6150 &DAG.getTarget().Options)) { 6151 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6152 &DAG.getTarget().Options)) { 6153 // Both can be negated for free, check to see if at least one is cheaper 6154 // negated. 6155 if (LHSNeg == 2 || RHSNeg == 2) 6156 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 6157 GetNegatedExpression(N0, DAG, LegalOperations), 6158 GetNegatedExpression(N1, DAG, LegalOperations)); 6159 } 6160 } 6161 6162 return SDValue(); 6163} 6164 6165SDValue DAGCombiner::visitFREM(SDNode *N) { 6166 SDValue N0 = N->getOperand(0); 6167 SDValue N1 = N->getOperand(1); 6168 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6169 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6170 EVT VT = N->getValueType(0); 6171 6172 // fold (frem c1, c2) -> fmod(c1,c2) 6173 if (N0CFP && N1CFP && VT != MVT::ppcf128) 6174 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 6175 6176 return SDValue(); 6177} 6178 6179SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6180 SDValue N0 = N->getOperand(0); 6181 SDValue N1 = N->getOperand(1); 6182 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6183 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6184 EVT VT = N->getValueType(0); 6185 6186 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 6187 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 6188 6189 if (N1CFP) { 6190 const APFloat& V = N1CFP->getValueAPF(); 6191 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6192 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6193 if (!V.isNegative()) { 6194 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6195 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6196 } else { 6197 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6198 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6199 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 6200 } 6201 } 6202 6203 // copysign(fabs(x), y) -> copysign(x, y) 6204 // copysign(fneg(x), y) -> copysign(x, y) 6205 // copysign(copysign(x,z), y) -> copysign(x, y) 6206 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6207 N0.getOpcode() == ISD::FCOPYSIGN) 6208 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6209 N0.getOperand(0), N1); 6210 6211 // copysign(x, abs(y)) -> abs(x) 6212 if (N1.getOpcode() == ISD::FABS) 6213 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6214 6215 // copysign(x, copysign(y,z)) -> copysign(x, z) 6216 if (N1.getOpcode() == ISD::FCOPYSIGN) 6217 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6218 N0, N1.getOperand(1)); 6219 6220 // copysign(x, fp_extend(y)) -> copysign(x, y) 6221 // copysign(x, fp_round(y)) -> copysign(x, y) 6222 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6223 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6224 N0, N1.getOperand(0)); 6225 6226 return SDValue(); 6227} 6228 6229SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6230 SDValue N0 = N->getOperand(0); 6231 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6232 EVT VT = N->getValueType(0); 6233 EVT OpVT = N0.getValueType(); 6234 6235 // fold (sint_to_fp c1) -> c1fp 6236 if (N0C && OpVT != MVT::ppcf128 && 6237 // ...but only if the target supports immediate floating-point values 6238 (!LegalOperations || 6239 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6240 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6241 6242 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6243 // but UINT_TO_FP is legal on this target, try to convert. 6244 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6245 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6246 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6247 if (DAG.SignBitIsZero(N0)) 6248 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6249 } 6250 6251 // The next optimizations are desireable only if SELECT_CC can be lowered. 6252 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6253 // having to say they don't support SELECT_CC on every type the DAG knows 6254 // about, since there is no way to mark an opcode illegal at all value types 6255 // (See also visitSELECT) 6256 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6257 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6258 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6259 !VT.isVector() && 6260 (!LegalOperations || 6261 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6262 SDValue Ops[] = 6263 { N0.getOperand(0), N0.getOperand(1), 6264 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6265 N0.getOperand(2) }; 6266 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6267 } 6268 6269 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6270 // (select_cc x, y, 1.0, 0.0,, cc) 6271 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6272 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6273 (!LegalOperations || 6274 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6275 SDValue Ops[] = 6276 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6277 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6278 N0.getOperand(0).getOperand(2) }; 6279 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6280 } 6281 } 6282 6283 return SDValue(); 6284} 6285 6286SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6287 SDValue N0 = N->getOperand(0); 6288 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6289 EVT VT = N->getValueType(0); 6290 EVT OpVT = N0.getValueType(); 6291 6292 // fold (uint_to_fp c1) -> c1fp 6293 if (N0C && OpVT != MVT::ppcf128 && 6294 // ...but only if the target supports immediate floating-point values 6295 (!LegalOperations || 6296 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6297 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6298 6299 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6300 // but SINT_TO_FP is legal on this target, try to convert. 6301 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6302 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6303 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6304 if (DAG.SignBitIsZero(N0)) 6305 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6306 } 6307 6308 // The next optimizations are desireable only if SELECT_CC can be lowered. 6309 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6310 // having to say they don't support SELECT_CC on every type the DAG knows 6311 // about, since there is no way to mark an opcode illegal at all value types 6312 // (See also visitSELECT) 6313 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6314 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6315 6316 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6317 (!LegalOperations || 6318 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6319 SDValue Ops[] = 6320 { N0.getOperand(0), N0.getOperand(1), 6321 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6322 N0.getOperand(2) }; 6323 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6324 } 6325 } 6326 6327 return SDValue(); 6328} 6329 6330SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6331 SDValue N0 = N->getOperand(0); 6332 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6333 EVT VT = N->getValueType(0); 6334 6335 // fold (fp_to_sint c1fp) -> c1 6336 if (N0CFP) 6337 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 6338 6339 return SDValue(); 6340} 6341 6342SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6343 SDValue N0 = N->getOperand(0); 6344 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6345 EVT VT = N->getValueType(0); 6346 6347 // fold (fp_to_uint c1fp) -> c1 6348 if (N0CFP && VT != MVT::ppcf128) 6349 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 6350 6351 return SDValue(); 6352} 6353 6354SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6355 SDValue N0 = N->getOperand(0); 6356 SDValue N1 = N->getOperand(1); 6357 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6358 EVT VT = N->getValueType(0); 6359 6360 // fold (fp_round c1fp) -> c1fp 6361 if (N0CFP && N0.getValueType() != MVT::ppcf128) 6362 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 6363 6364 // fold (fp_round (fp_extend x)) -> x 6365 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6366 return N0.getOperand(0); 6367 6368 // fold (fp_round (fp_round x)) -> (fp_round x) 6369 if (N0.getOpcode() == ISD::FP_ROUND) { 6370 // This is a value preserving truncation if both round's are. 6371 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6372 N0.getNode()->getConstantOperandVal(1) == 1; 6373 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 6374 DAG.getIntPtrConstant(IsTrunc)); 6375 } 6376 6377 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6378 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6379 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 6380 N0.getOperand(0), N1); 6381 AddToWorkList(Tmp.getNode()); 6382 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6383 Tmp, N0.getOperand(1)); 6384 } 6385 6386 return SDValue(); 6387} 6388 6389SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6390 SDValue N0 = N->getOperand(0); 6391 EVT VT = N->getValueType(0); 6392 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6393 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6394 6395 // fold (fp_round_inreg c1fp) -> c1fp 6396 if (N0CFP && isTypeLegal(EVT)) { 6397 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6398 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 6399 } 6400 6401 return SDValue(); 6402} 6403 6404SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6405 SDValue N0 = N->getOperand(0); 6406 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6407 EVT VT = N->getValueType(0); 6408 6409 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6410 if (N->hasOneUse() && 6411 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6412 return SDValue(); 6413 6414 // fold (fp_extend c1fp) -> c1fp 6415 if (N0CFP && VT != MVT::ppcf128) 6416 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6417 6418 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6419 // value of X. 6420 if (N0.getOpcode() == ISD::FP_ROUND 6421 && N0.getNode()->getConstantOperandVal(1) == 1) { 6422 SDValue In = N0.getOperand(0); 6423 if (In.getValueType() == VT) return In; 6424 if (VT.bitsLT(In.getValueType())) 6425 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6426 In, N0.getOperand(1)); 6427 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6428 } 6429 6430 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6431 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6432 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6433 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6434 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6435 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6436 LN0->getChain(), 6437 LN0->getBasePtr(), LN0->getPointerInfo(), 6438 N0.getValueType(), 6439 LN0->isVolatile(), LN0->isNonTemporal(), 6440 LN0->getAlignment()); 6441 CombineTo(N, ExtLoad); 6442 CombineTo(N0.getNode(), 6443 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6444 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6445 ExtLoad.getValue(1)); 6446 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6447 } 6448 6449 return SDValue(); 6450} 6451 6452SDValue DAGCombiner::visitFNEG(SDNode *N) { 6453 SDValue N0 = N->getOperand(0); 6454 EVT VT = N->getValueType(0); 6455 6456 if (VT.isVector()) { 6457 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6458 if (FoldedVOp.getNode()) return FoldedVOp; 6459 } 6460 6461 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6462 &DAG.getTarget().Options)) 6463 return GetNegatedExpression(N0, DAG, LegalOperations); 6464 6465 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6466 // constant pool values. 6467 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6468 !VT.isVector() && 6469 N0.getNode()->hasOneUse() && 6470 N0.getOperand(0).getValueType().isInteger()) { 6471 SDValue Int = N0.getOperand(0); 6472 EVT IntVT = Int.getValueType(); 6473 if (IntVT.isInteger() && !IntVT.isVector()) { 6474 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6475 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6476 AddToWorkList(Int.getNode()); 6477 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6478 VT, Int); 6479 } 6480 } 6481 6482 // (fneg (fmul c, x)) -> (fmul -c, x) 6483 if (N0.getOpcode() == ISD::FMUL) { 6484 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6485 if (CFP1) { 6486 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6487 N0.getOperand(0), 6488 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6489 N0.getOperand(1))); 6490 } 6491 } 6492 6493 return SDValue(); 6494} 6495 6496SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6497 SDValue N0 = N->getOperand(0); 6498 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6499 EVT VT = N->getValueType(0); 6500 6501 // fold (fceil c1) -> fceil(c1) 6502 if (N0CFP && VT != MVT::ppcf128) 6503 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0); 6504 6505 return SDValue(); 6506} 6507 6508SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6509 SDValue N0 = N->getOperand(0); 6510 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6511 EVT VT = N->getValueType(0); 6512 6513 // fold (ftrunc c1) -> ftrunc(c1) 6514 if (N0CFP && VT != MVT::ppcf128) 6515 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0); 6516 6517 return SDValue(); 6518} 6519 6520SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6521 SDValue N0 = N->getOperand(0); 6522 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6523 EVT VT = N->getValueType(0); 6524 6525 // fold (ffloor c1) -> ffloor(c1) 6526 if (N0CFP && VT != MVT::ppcf128) 6527 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0); 6528 6529 return SDValue(); 6530} 6531 6532SDValue DAGCombiner::visitFABS(SDNode *N) { 6533 SDValue N0 = N->getOperand(0); 6534 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6535 EVT VT = N->getValueType(0); 6536 6537 if (VT.isVector()) { 6538 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6539 if (FoldedVOp.getNode()) return FoldedVOp; 6540 } 6541 6542 // fold (fabs c1) -> fabs(c1) 6543 if (N0CFP && VT != MVT::ppcf128) 6544 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6545 // fold (fabs (fabs x)) -> (fabs x) 6546 if (N0.getOpcode() == ISD::FABS) 6547 return N->getOperand(0); 6548 // fold (fabs (fneg x)) -> (fabs x) 6549 // fold (fabs (fcopysign x, y)) -> (fabs x) 6550 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6551 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6552 6553 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6554 // constant pool values. 6555 if (!TLI.isFAbsFree(VT) && 6556 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6557 N0.getOperand(0).getValueType().isInteger() && 6558 !N0.getOperand(0).getValueType().isVector()) { 6559 SDValue Int = N0.getOperand(0); 6560 EVT IntVT = Int.getValueType(); 6561 if (IntVT.isInteger() && !IntVT.isVector()) { 6562 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6563 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6564 AddToWorkList(Int.getNode()); 6565 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6566 N->getValueType(0), Int); 6567 } 6568 } 6569 6570 return SDValue(); 6571} 6572 6573SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6574 SDValue Chain = N->getOperand(0); 6575 SDValue N1 = N->getOperand(1); 6576 SDValue N2 = N->getOperand(2); 6577 6578 // If N is a constant we could fold this into a fallthrough or unconditional 6579 // branch. However that doesn't happen very often in normal code, because 6580 // Instcombine/SimplifyCFG should have handled the available opportunities. 6581 // If we did this folding here, it would be necessary to update the 6582 // MachineBasicBlock CFG, which is awkward. 6583 6584 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6585 // on the target. 6586 if (N1.getOpcode() == ISD::SETCC && 6587 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6588 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6589 Chain, N1.getOperand(2), 6590 N1.getOperand(0), N1.getOperand(1), N2); 6591 } 6592 6593 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6594 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6595 (N1.getOperand(0).hasOneUse() && 6596 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6597 SDNode *Trunc = 0; 6598 if (N1.getOpcode() == ISD::TRUNCATE) { 6599 // Look pass the truncate. 6600 Trunc = N1.getNode(); 6601 N1 = N1.getOperand(0); 6602 } 6603 6604 // Match this pattern so that we can generate simpler code: 6605 // 6606 // %a = ... 6607 // %b = and i32 %a, 2 6608 // %c = srl i32 %b, 1 6609 // brcond i32 %c ... 6610 // 6611 // into 6612 // 6613 // %a = ... 6614 // %b = and i32 %a, 2 6615 // %c = setcc eq %b, 0 6616 // brcond %c ... 6617 // 6618 // This applies only when the AND constant value has one bit set and the 6619 // SRL constant is equal to the log2 of the AND constant. The back-end is 6620 // smart enough to convert the result into a TEST/JMP sequence. 6621 SDValue Op0 = N1.getOperand(0); 6622 SDValue Op1 = N1.getOperand(1); 6623 6624 if (Op0.getOpcode() == ISD::AND && 6625 Op1.getOpcode() == ISD::Constant) { 6626 SDValue AndOp1 = Op0.getOperand(1); 6627 6628 if (AndOp1.getOpcode() == ISD::Constant) { 6629 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6630 6631 if (AndConst.isPowerOf2() && 6632 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6633 SDValue SetCC = 6634 DAG.getSetCC(N->getDebugLoc(), 6635 TLI.getSetCCResultType(Op0.getValueType()), 6636 Op0, DAG.getConstant(0, Op0.getValueType()), 6637 ISD::SETNE); 6638 6639 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6640 MVT::Other, Chain, SetCC, N2); 6641 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6642 // will convert it back to (X & C1) >> C2. 6643 CombineTo(N, NewBRCond, false); 6644 // Truncate is dead. 6645 if (Trunc) { 6646 removeFromWorkList(Trunc); 6647 DAG.DeleteNode(Trunc); 6648 } 6649 // Replace the uses of SRL with SETCC 6650 WorkListRemover DeadNodes(*this); 6651 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6652 removeFromWorkList(N1.getNode()); 6653 DAG.DeleteNode(N1.getNode()); 6654 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6655 } 6656 } 6657 } 6658 6659 if (Trunc) 6660 // Restore N1 if the above transformation doesn't match. 6661 N1 = N->getOperand(1); 6662 } 6663 6664 // Transform br(xor(x, y)) -> br(x != y) 6665 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6666 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6667 SDNode *TheXor = N1.getNode(); 6668 SDValue Op0 = TheXor->getOperand(0); 6669 SDValue Op1 = TheXor->getOperand(1); 6670 if (Op0.getOpcode() == Op1.getOpcode()) { 6671 // Avoid missing important xor optimizations. 6672 SDValue Tmp = visitXOR(TheXor); 6673 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6674 DEBUG(dbgs() << "\nReplacing.8 "; 6675 TheXor->dump(&DAG); 6676 dbgs() << "\nWith: "; 6677 Tmp.getNode()->dump(&DAG); 6678 dbgs() << '\n'); 6679 WorkListRemover DeadNodes(*this); 6680 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6681 removeFromWorkList(TheXor); 6682 DAG.DeleteNode(TheXor); 6683 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6684 MVT::Other, Chain, Tmp, N2); 6685 } 6686 } 6687 6688 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6689 bool Equal = false; 6690 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6691 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6692 Op0.getOpcode() == ISD::XOR) { 6693 TheXor = Op0.getNode(); 6694 Equal = true; 6695 } 6696 6697 EVT SetCCVT = N1.getValueType(); 6698 if (LegalTypes) 6699 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6700 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6701 SetCCVT, 6702 Op0, Op1, 6703 Equal ? ISD::SETEQ : ISD::SETNE); 6704 // Replace the uses of XOR with SETCC 6705 WorkListRemover DeadNodes(*this); 6706 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6707 removeFromWorkList(N1.getNode()); 6708 DAG.DeleteNode(N1.getNode()); 6709 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6710 MVT::Other, Chain, SetCC, N2); 6711 } 6712 } 6713 6714 return SDValue(); 6715} 6716 6717// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6718// 6719SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6720 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6721 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6722 6723 // If N is a constant we could fold this into a fallthrough or unconditional 6724 // branch. However that doesn't happen very often in normal code, because 6725 // Instcombine/SimplifyCFG should have handled the available opportunities. 6726 // If we did this folding here, it would be necessary to update the 6727 // MachineBasicBlock CFG, which is awkward. 6728 6729 // Use SimplifySetCC to simplify SETCC's. 6730 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6731 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6732 false); 6733 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6734 6735 // fold to a simpler setcc 6736 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6737 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6738 N->getOperand(0), Simp.getOperand(2), 6739 Simp.getOperand(0), Simp.getOperand(1), 6740 N->getOperand(4)); 6741 6742 return SDValue(); 6743} 6744 6745/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6746/// uses N as its base pointer and that N may be folded in the load / store 6747/// addressing mode. 6748static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6749 SelectionDAG &DAG, 6750 const TargetLowering &TLI) { 6751 EVT VT; 6752 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6753 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6754 return false; 6755 VT = Use->getValueType(0); 6756 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6757 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6758 return false; 6759 VT = ST->getValue().getValueType(); 6760 } else 6761 return false; 6762 6763 AddrMode AM; 6764 if (N->getOpcode() == ISD::ADD) { 6765 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6766 if (Offset) 6767 // [reg +/- imm] 6768 AM.BaseOffs = Offset->getSExtValue(); 6769 else 6770 // [reg +/- reg] 6771 AM.Scale = 1; 6772 } else if (N->getOpcode() == ISD::SUB) { 6773 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6774 if (Offset) 6775 // [reg +/- imm] 6776 AM.BaseOffs = -Offset->getSExtValue(); 6777 else 6778 // [reg +/- reg] 6779 AM.Scale = 1; 6780 } else 6781 return false; 6782 6783 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6784} 6785 6786/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6787/// pre-indexed load / store when the base pointer is an add or subtract 6788/// and it has other uses besides the load / store. After the 6789/// transformation, the new indexed load / store has effectively folded 6790/// the add / subtract in and all of its other uses are redirected to the 6791/// new load / store. 6792bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6793 if (Level < AfterLegalizeDAG) 6794 return false; 6795 6796 bool isLoad = true; 6797 SDValue Ptr; 6798 EVT VT; 6799 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6800 if (LD->isIndexed()) 6801 return false; 6802 VT = LD->getMemoryVT(); 6803 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6804 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6805 return false; 6806 Ptr = LD->getBasePtr(); 6807 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6808 if (ST->isIndexed()) 6809 return false; 6810 VT = ST->getMemoryVT(); 6811 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6812 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6813 return false; 6814 Ptr = ST->getBasePtr(); 6815 isLoad = false; 6816 } else { 6817 return false; 6818 } 6819 6820 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6821 // out. There is no reason to make this a preinc/predec. 6822 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6823 Ptr.getNode()->hasOneUse()) 6824 return false; 6825 6826 // Ask the target to do addressing mode selection. 6827 SDValue BasePtr; 6828 SDValue Offset; 6829 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6830 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6831 return false; 6832 // Don't create a indexed load / store with zero offset. 6833 if (isa<ConstantSDNode>(Offset) && 6834 cast<ConstantSDNode>(Offset)->isNullValue()) 6835 return false; 6836 6837 // Try turning it into a pre-indexed load / store except when: 6838 // 1) The new base ptr is a frame index. 6839 // 2) If N is a store and the new base ptr is either the same as or is a 6840 // predecessor of the value being stored. 6841 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6842 // that would create a cycle. 6843 // 4) All uses are load / store ops that use it as old base ptr. 6844 6845 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6846 // (plus the implicit offset) to a register to preinc anyway. 6847 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6848 return false; 6849 6850 // Check #2. 6851 if (!isLoad) { 6852 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6853 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6854 return false; 6855 } 6856 6857 // Now check for #3 and #4. 6858 bool RealUse = false; 6859 6860 // Caches for hasPredecessorHelper 6861 SmallPtrSet<const SDNode *, 32> Visited; 6862 SmallVector<const SDNode *, 16> Worklist; 6863 6864 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6865 E = Ptr.getNode()->use_end(); I != E; ++I) { 6866 SDNode *Use = *I; 6867 if (Use == N) 6868 continue; 6869 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6870 return false; 6871 6872 // If Ptr may be folded in addressing mode of other use, then it's 6873 // not profitable to do this transformation. 6874 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6875 RealUse = true; 6876 } 6877 6878 if (!RealUse) 6879 return false; 6880 6881 SDValue Result; 6882 if (isLoad) 6883 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6884 BasePtr, Offset, AM); 6885 else 6886 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6887 BasePtr, Offset, AM); 6888 ++PreIndexedNodes; 6889 ++NodesCombined; 6890 DEBUG(dbgs() << "\nReplacing.4 "; 6891 N->dump(&DAG); 6892 dbgs() << "\nWith: "; 6893 Result.getNode()->dump(&DAG); 6894 dbgs() << '\n'); 6895 WorkListRemover DeadNodes(*this); 6896 if (isLoad) { 6897 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6898 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6899 } else { 6900 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6901 } 6902 6903 // Finally, since the node is now dead, remove it from the graph. 6904 DAG.DeleteNode(N); 6905 6906 // Replace the uses of Ptr with uses of the updated base value. 6907 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 6908 removeFromWorkList(Ptr.getNode()); 6909 DAG.DeleteNode(Ptr.getNode()); 6910 6911 return true; 6912} 6913 6914/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6915/// add / sub of the base pointer node into a post-indexed load / store. 6916/// The transformation folded the add / subtract into the new indexed 6917/// load / store effectively and all of its uses are redirected to the 6918/// new load / store. 6919bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6920 if (Level < AfterLegalizeDAG) 6921 return false; 6922 6923 bool isLoad = true; 6924 SDValue Ptr; 6925 EVT VT; 6926 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6927 if (LD->isIndexed()) 6928 return false; 6929 VT = LD->getMemoryVT(); 6930 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6931 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6932 return false; 6933 Ptr = LD->getBasePtr(); 6934 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6935 if (ST->isIndexed()) 6936 return false; 6937 VT = ST->getMemoryVT(); 6938 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6939 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6940 return false; 6941 Ptr = ST->getBasePtr(); 6942 isLoad = false; 6943 } else { 6944 return false; 6945 } 6946 6947 if (Ptr.getNode()->hasOneUse()) 6948 return false; 6949 6950 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6951 E = Ptr.getNode()->use_end(); I != E; ++I) { 6952 SDNode *Op = *I; 6953 if (Op == N || 6954 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6955 continue; 6956 6957 SDValue BasePtr; 6958 SDValue Offset; 6959 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6960 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6961 // Don't create a indexed load / store with zero offset. 6962 if (isa<ConstantSDNode>(Offset) && 6963 cast<ConstantSDNode>(Offset)->isNullValue()) 6964 continue; 6965 6966 // Try turning it into a post-indexed load / store except when 6967 // 1) All uses are load / store ops that use it as base ptr (and 6968 // it may be folded as addressing mmode). 6969 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6970 // nor a successor of N. Otherwise, if Op is folded that would 6971 // create a cycle. 6972 6973 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6974 continue; 6975 6976 // Check for #1. 6977 bool TryNext = false; 6978 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6979 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6980 SDNode *Use = *II; 6981 if (Use == Ptr.getNode()) 6982 continue; 6983 6984 // If all the uses are load / store addresses, then don't do the 6985 // transformation. 6986 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6987 bool RealUse = false; 6988 for (SDNode::use_iterator III = Use->use_begin(), 6989 EEE = Use->use_end(); III != EEE; ++III) { 6990 SDNode *UseUse = *III; 6991 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6992 RealUse = true; 6993 } 6994 6995 if (!RealUse) { 6996 TryNext = true; 6997 break; 6998 } 6999 } 7000 } 7001 7002 if (TryNext) 7003 continue; 7004 7005 // Check for #2 7006 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 7007 SDValue Result = isLoad 7008 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 7009 BasePtr, Offset, AM) 7010 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 7011 BasePtr, Offset, AM); 7012 ++PostIndexedNodes; 7013 ++NodesCombined; 7014 DEBUG(dbgs() << "\nReplacing.5 "; 7015 N->dump(&DAG); 7016 dbgs() << "\nWith: "; 7017 Result.getNode()->dump(&DAG); 7018 dbgs() << '\n'); 7019 WorkListRemover DeadNodes(*this); 7020 if (isLoad) { 7021 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7022 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7023 } else { 7024 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7025 } 7026 7027 // Finally, since the node is now dead, remove it from the graph. 7028 DAG.DeleteNode(N); 7029 7030 // Replace the uses of Use with uses of the updated base value. 7031 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 7032 Result.getValue(isLoad ? 1 : 0)); 7033 removeFromWorkList(Op); 7034 DAG.DeleteNode(Op); 7035 return true; 7036 } 7037 } 7038 } 7039 7040 return false; 7041} 7042 7043SDValue DAGCombiner::visitLOAD(SDNode *N) { 7044 LoadSDNode *LD = cast<LoadSDNode>(N); 7045 SDValue Chain = LD->getChain(); 7046 SDValue Ptr = LD->getBasePtr(); 7047 7048 // If load is not volatile and there are no uses of the loaded value (and 7049 // the updated indexed value in case of indexed loads), change uses of the 7050 // chain value into uses of the chain input (i.e. delete the dead load). 7051 if (!LD->isVolatile()) { 7052 if (N->getValueType(1) == MVT::Other) { 7053 // Unindexed loads. 7054 if (!N->hasAnyUseOfValue(0)) { 7055 // It's not safe to use the two value CombineTo variant here. e.g. 7056 // v1, chain2 = load chain1, loc 7057 // v2, chain3 = load chain2, loc 7058 // v3 = add v2, c 7059 // Now we replace use of chain2 with chain1. This makes the second load 7060 // isomorphic to the one we are deleting, and thus makes this load live. 7061 DEBUG(dbgs() << "\nReplacing.6 "; 7062 N->dump(&DAG); 7063 dbgs() << "\nWith chain: "; 7064 Chain.getNode()->dump(&DAG); 7065 dbgs() << "\n"); 7066 WorkListRemover DeadNodes(*this); 7067 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7068 7069 if (N->use_empty()) { 7070 removeFromWorkList(N); 7071 DAG.DeleteNode(N); 7072 } 7073 7074 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7075 } 7076 } else { 7077 // Indexed loads. 7078 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7079 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7080 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7081 DEBUG(dbgs() << "\nReplacing.7 "; 7082 N->dump(&DAG); 7083 dbgs() << "\nWith: "; 7084 Undef.getNode()->dump(&DAG); 7085 dbgs() << " and 2 other values\n"); 7086 WorkListRemover DeadNodes(*this); 7087 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7088 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7089 DAG.getUNDEF(N->getValueType(1))); 7090 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7091 removeFromWorkList(N); 7092 DAG.DeleteNode(N); 7093 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7094 } 7095 } 7096 } 7097 7098 // If this load is directly stored, replace the load value with the stored 7099 // value. 7100 // TODO: Handle store large -> read small portion. 7101 // TODO: Handle TRUNCSTORE/LOADEXT 7102 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7103 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7104 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7105 if (PrevST->getBasePtr() == Ptr && 7106 PrevST->getValue().getValueType() == N->getValueType(0)) 7107 return CombineTo(N, Chain.getOperand(1), Chain); 7108 } 7109 } 7110 7111 // Try to infer better alignment information than the load already has. 7112 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7113 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7114 if (Align > LD->getAlignment()) 7115 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 7116 LD->getValueType(0), 7117 Chain, Ptr, LD->getPointerInfo(), 7118 LD->getMemoryVT(), 7119 LD->isVolatile(), LD->isNonTemporal(), Align); 7120 } 7121 } 7122 7123 if (CombinerAA) { 7124 // Walk up chain skipping non-aliasing memory nodes. 7125 SDValue BetterChain = FindBetterChain(N, Chain); 7126 7127 // If there is a better chain. 7128 if (Chain != BetterChain) { 7129 SDValue ReplLoad; 7130 7131 // Replace the chain to void dependency. 7132 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7133 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 7134 BetterChain, Ptr, LD->getPointerInfo(), 7135 LD->isVolatile(), LD->isNonTemporal(), 7136 LD->isInvariant(), LD->getAlignment()); 7137 } else { 7138 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 7139 LD->getValueType(0), 7140 BetterChain, Ptr, LD->getPointerInfo(), 7141 LD->getMemoryVT(), 7142 LD->isVolatile(), 7143 LD->isNonTemporal(), 7144 LD->getAlignment()); 7145 } 7146 7147 // Create token factor to keep old chain connected. 7148 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7149 MVT::Other, Chain, ReplLoad.getValue(1)); 7150 7151 // Make sure the new and old chains are cleaned up. 7152 AddToWorkList(Token.getNode()); 7153 7154 // Replace uses with load result and token factor. Don't add users 7155 // to work list. 7156 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7157 } 7158 } 7159 7160 // Try transforming N to an indexed load. 7161 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7162 return SDValue(N, 0); 7163 7164 return SDValue(); 7165} 7166 7167/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 7168/// load is having specific bytes cleared out. If so, return the byte size 7169/// being masked out and the shift amount. 7170static std::pair<unsigned, unsigned> 7171CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 7172 std::pair<unsigned, unsigned> Result(0, 0); 7173 7174 // Check for the structure we're looking for. 7175 if (V->getOpcode() != ISD::AND || 7176 !isa<ConstantSDNode>(V->getOperand(1)) || 7177 !ISD::isNormalLoad(V->getOperand(0).getNode())) 7178 return Result; 7179 7180 // Check the chain and pointer. 7181 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 7182 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 7183 7184 // The store should be chained directly to the load or be an operand of a 7185 // tokenfactor. 7186 if (LD == Chain.getNode()) 7187 ; // ok. 7188 else if (Chain->getOpcode() != ISD::TokenFactor) 7189 return Result; // Fail. 7190 else { 7191 bool isOk = false; 7192 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 7193 if (Chain->getOperand(i).getNode() == LD) { 7194 isOk = true; 7195 break; 7196 } 7197 if (!isOk) return Result; 7198 } 7199 7200 // This only handles simple types. 7201 if (V.getValueType() != MVT::i16 && 7202 V.getValueType() != MVT::i32 && 7203 V.getValueType() != MVT::i64) 7204 return Result; 7205 7206 // Check the constant mask. Invert it so that the bits being masked out are 7207 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 7208 // follow the sign bit for uniformity. 7209 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 7210 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 7211 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 7212 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 7213 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 7214 if (NotMaskLZ == 64) return Result; // All zero mask. 7215 7216 // See if we have a continuous run of bits. If so, we have 0*1+0* 7217 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 7218 return Result; 7219 7220 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 7221 if (V.getValueType() != MVT::i64 && NotMaskLZ) 7222 NotMaskLZ -= 64-V.getValueSizeInBits(); 7223 7224 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 7225 switch (MaskedBytes) { 7226 case 1: 7227 case 2: 7228 case 4: break; 7229 default: return Result; // All one mask, or 5-byte mask. 7230 } 7231 7232 // Verify that the first bit starts at a multiple of mask so that the access 7233 // is aligned the same as the access width. 7234 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 7235 7236 Result.first = MaskedBytes; 7237 Result.second = NotMaskTZ/8; 7238 return Result; 7239} 7240 7241 7242/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 7243/// provides a value as specified by MaskInfo. If so, replace the specified 7244/// store with a narrower store of truncated IVal. 7245static SDNode * 7246ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 7247 SDValue IVal, StoreSDNode *St, 7248 DAGCombiner *DC) { 7249 unsigned NumBytes = MaskInfo.first; 7250 unsigned ByteShift = MaskInfo.second; 7251 SelectionDAG &DAG = DC->getDAG(); 7252 7253 // Check to see if IVal is all zeros in the part being masked in by the 'or' 7254 // that uses this. If not, this is not a replacement. 7255 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 7256 ByteShift*8, (ByteShift+NumBytes)*8); 7257 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 7258 7259 // Check that it is legal on the target to do this. It is legal if the new 7260 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 7261 // legalization. 7262 MVT VT = MVT::getIntegerVT(NumBytes*8); 7263 if (!DC->isTypeLegal(VT)) 7264 return 0; 7265 7266 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 7267 // shifted by ByteShift and truncated down to NumBytes. 7268 if (ByteShift) 7269 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 7270 DAG.getConstant(ByteShift*8, 7271 DC->getShiftAmountTy(IVal.getValueType()))); 7272 7273 // Figure out the offset for the store and the alignment of the access. 7274 unsigned StOffset; 7275 unsigned NewAlign = St->getAlignment(); 7276 7277 if (DAG.getTargetLoweringInfo().isLittleEndian()) 7278 StOffset = ByteShift; 7279 else 7280 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 7281 7282 SDValue Ptr = St->getBasePtr(); 7283 if (StOffset) { 7284 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 7285 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 7286 NewAlign = MinAlign(NewAlign, StOffset); 7287 } 7288 7289 // Truncate down to the new size. 7290 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 7291 7292 ++OpsNarrowed; 7293 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 7294 St->getPointerInfo().getWithOffset(StOffset), 7295 false, false, NewAlign).getNode(); 7296} 7297 7298 7299/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 7300/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 7301/// of the loaded bits, try narrowing the load and store if it would end up 7302/// being a win for performance or code size. 7303SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 7304 StoreSDNode *ST = cast<StoreSDNode>(N); 7305 if (ST->isVolatile()) 7306 return SDValue(); 7307 7308 SDValue Chain = ST->getChain(); 7309 SDValue Value = ST->getValue(); 7310 SDValue Ptr = ST->getBasePtr(); 7311 EVT VT = Value.getValueType(); 7312 7313 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 7314 return SDValue(); 7315 7316 unsigned Opc = Value.getOpcode(); 7317 7318 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 7319 // is a byte mask indicating a consecutive number of bytes, check to see if 7320 // Y is known to provide just those bytes. If so, we try to replace the 7321 // load + replace + store sequence with a single (narrower) store, which makes 7322 // the load dead. 7323 if (Opc == ISD::OR) { 7324 std::pair<unsigned, unsigned> MaskedLoad; 7325 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 7326 if (MaskedLoad.first) 7327 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7328 Value.getOperand(1), ST,this)) 7329 return SDValue(NewST, 0); 7330 7331 // Or is commutative, so try swapping X and Y. 7332 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 7333 if (MaskedLoad.first) 7334 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7335 Value.getOperand(0), ST,this)) 7336 return SDValue(NewST, 0); 7337 } 7338 7339 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 7340 Value.getOperand(1).getOpcode() != ISD::Constant) 7341 return SDValue(); 7342 7343 SDValue N0 = Value.getOperand(0); 7344 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 7345 Chain == SDValue(N0.getNode(), 1)) { 7346 LoadSDNode *LD = cast<LoadSDNode>(N0); 7347 if (LD->getBasePtr() != Ptr || 7348 LD->getPointerInfo().getAddrSpace() != 7349 ST->getPointerInfo().getAddrSpace()) 7350 return SDValue(); 7351 7352 // Find the type to narrow it the load / op / store to. 7353 SDValue N1 = Value.getOperand(1); 7354 unsigned BitWidth = N1.getValueSizeInBits(); 7355 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 7356 if (Opc == ISD::AND) 7357 Imm ^= APInt::getAllOnesValue(BitWidth); 7358 if (Imm == 0 || Imm.isAllOnesValue()) 7359 return SDValue(); 7360 unsigned ShAmt = Imm.countTrailingZeros(); 7361 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 7362 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 7363 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7364 while (NewBW < BitWidth && 7365 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 7366 TLI.isNarrowingProfitable(VT, NewVT))) { 7367 NewBW = NextPowerOf2(NewBW); 7368 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7369 } 7370 if (NewBW >= BitWidth) 7371 return SDValue(); 7372 7373 // If the lsb changed does not start at the type bitwidth boundary, 7374 // start at the previous one. 7375 if (ShAmt % NewBW) 7376 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 7377 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 7378 if ((Imm & Mask) == Imm) { 7379 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 7380 if (Opc == ISD::AND) 7381 NewImm ^= APInt::getAllOnesValue(NewBW); 7382 uint64_t PtrOff = ShAmt / 8; 7383 // For big endian targets, we need to adjust the offset to the pointer to 7384 // load the correct bytes. 7385 if (TLI.isBigEndian()) 7386 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 7387 7388 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 7389 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 7390 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy)) 7391 return SDValue(); 7392 7393 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 7394 Ptr.getValueType(), Ptr, 7395 DAG.getConstant(PtrOff, Ptr.getValueType())); 7396 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 7397 LD->getChain(), NewPtr, 7398 LD->getPointerInfo().getWithOffset(PtrOff), 7399 LD->isVolatile(), LD->isNonTemporal(), 7400 LD->isInvariant(), NewAlign); 7401 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 7402 DAG.getConstant(NewImm, NewVT)); 7403 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 7404 NewVal, NewPtr, 7405 ST->getPointerInfo().getWithOffset(PtrOff), 7406 false, false, NewAlign); 7407 7408 AddToWorkList(NewPtr.getNode()); 7409 AddToWorkList(NewLD.getNode()); 7410 AddToWorkList(NewVal.getNode()); 7411 WorkListRemover DeadNodes(*this); 7412 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7413 ++OpsNarrowed; 7414 return NewST; 7415 } 7416 } 7417 7418 return SDValue(); 7419} 7420 7421/// TransformFPLoadStorePair - For a given floating point load / store pair, 7422/// if the load value isn't used by any other operations, then consider 7423/// transforming the pair to integer load / store operations if the target 7424/// deems the transformation profitable. 7425SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7426 StoreSDNode *ST = cast<StoreSDNode>(N); 7427 SDValue Chain = ST->getChain(); 7428 SDValue Value = ST->getValue(); 7429 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7430 Value.hasOneUse() && 7431 Chain == SDValue(Value.getNode(), 1)) { 7432 LoadSDNode *LD = cast<LoadSDNode>(Value); 7433 EVT VT = LD->getMemoryVT(); 7434 if (!VT.isFloatingPoint() || 7435 VT != ST->getMemoryVT() || 7436 LD->isNonTemporal() || 7437 ST->isNonTemporal() || 7438 LD->getPointerInfo().getAddrSpace() != 0 || 7439 ST->getPointerInfo().getAddrSpace() != 0) 7440 return SDValue(); 7441 7442 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7443 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7444 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7445 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7446 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7447 return SDValue(); 7448 7449 unsigned LDAlign = LD->getAlignment(); 7450 unsigned STAlign = ST->getAlignment(); 7451 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7452 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy); 7453 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7454 return SDValue(); 7455 7456 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 7457 LD->getChain(), LD->getBasePtr(), 7458 LD->getPointerInfo(), 7459 false, false, false, LDAlign); 7460 7461 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 7462 NewLD, ST->getBasePtr(), 7463 ST->getPointerInfo(), 7464 false, false, STAlign); 7465 7466 AddToWorkList(NewLD.getNode()); 7467 AddToWorkList(NewST.getNode()); 7468 WorkListRemover DeadNodes(*this); 7469 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7470 ++LdStFP2Int; 7471 return NewST; 7472 } 7473 7474 return SDValue(); 7475} 7476 7477/// Returns the base pointer and an integer offset from that object. 7478static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) { 7479 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) { 7480 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue(); 7481 SDValue Base = Ptr->getOperand(0); 7482 return std::make_pair(Base, Offset); 7483 } 7484 7485 return std::make_pair(Ptr, 0); 7486} 7487 7488/// Holds a pointer to an LSBaseSDNode as well as information on where it 7489/// is located in a sequence of memory operations connected by a chain. 7490struct MemOpLink { 7491 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq): 7492 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { } 7493 // Ptr to the mem node. 7494 LSBaseSDNode *MemNode; 7495 // Offset from the base ptr. 7496 int64_t OffsetFromBase; 7497 // What is the sequence number of this mem node. 7498 // Lowest mem operand in the DAG starts at zero. 7499 unsigned SequenceNum; 7500}; 7501 7502/// Sorts store nodes in a link according to their offset from a shared 7503// base ptr. 7504struct ConsecutiveMemoryChainSorter { 7505 bool operator()(MemOpLink LHS, MemOpLink RHS) { 7506 return LHS.OffsetFromBase < RHS.OffsetFromBase; 7507 } 7508}; 7509 7510bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) { 7511 EVT MemVT = St->getMemoryVT(); 7512 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8; 7513 7514 // Don't merge vectors into wider inputs. 7515 if (MemVT.isVector() || !MemVT.isSimple()) 7516 return false; 7517 7518 // Perform an early exit check. Do not bother looking at stored values that 7519 // are not constants or loads. 7520 SDValue StoredVal = St->getValue(); 7521 bool IsLoadSrc = isa<LoadSDNode>(StoredVal); 7522 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) && 7523 !IsLoadSrc) 7524 return false; 7525 7526 // Only look at ends of store sequences. 7527 SDValue Chain = SDValue(St, 1); 7528 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE) 7529 return false; 7530 7531 // This holds the base pointer and the offset in bytes from the base pointer. 7532 std::pair<SDValue, int64_t> BasePtr = 7533 GetPointerBaseAndOffset(St->getBasePtr()); 7534 7535 // We must have a base and an offset. 7536 if (!BasePtr.first.getNode()) 7537 return false; 7538 7539 // Do not handle stores to undef base pointers. 7540 if (BasePtr.first.getOpcode() == ISD::UNDEF) 7541 return false; 7542 7543 SmallVector<MemOpLink, 8> StoreNodes; 7544 // Walk up the chain and look for nodes with offsets from the same 7545 // base pointer. Stop when reaching an instruction with a different kind 7546 // or instruction which has a different base pointer. 7547 unsigned Seq = 0; 7548 StoreSDNode *Index = St; 7549 while (Index) { 7550 // If the chain has more than one use, then we can't reorder the mem ops. 7551 if (Index != St && !SDValue(Index, 1)->hasOneUse()) 7552 break; 7553 7554 // Find the base pointer and offset for this memory node. 7555 std::pair<SDValue, int64_t> Ptr = 7556 GetPointerBaseAndOffset(Index->getBasePtr()); 7557 7558 // Check that the base pointer is the same as the original one. 7559 if (Ptr.first.getNode() != BasePtr.first.getNode()) 7560 break; 7561 7562 // Check that the alignment is the same. 7563 if (Index->getAlignment() != St->getAlignment()) 7564 break; 7565 7566 // The memory operands must not be volatile. 7567 if (Index->isVolatile() || Index->isIndexed()) 7568 break; 7569 7570 // No truncation. 7571 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index)) 7572 if (St->isTruncatingStore()) 7573 break; 7574 7575 // The stored memory type must be the same. 7576 if (Index->getMemoryVT() != MemVT) 7577 break; 7578 7579 // We do not allow unaligned stores because we want to prevent overriding 7580 // stores. 7581 if (Index->getAlignment()*8 != MemVT.getSizeInBits()) 7582 break; 7583 7584 // We found a potential memory operand to merge. 7585 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++)); 7586 7587 // Move up the chain to the next memory operation. 7588 Index = dyn_cast<StoreSDNode>(Index->getChain().getNode()); 7589 } 7590 7591 // Check if there is anything to merge. 7592 if (StoreNodes.size() < 2) 7593 return false; 7594 7595 // Sort the memory operands according to their distance from the base pointer. 7596 std::sort(StoreNodes.begin(), StoreNodes.end(), 7597 ConsecutiveMemoryChainSorter()); 7598 7599 // Scan the memory operations on the chain and find the first non-consecutive 7600 // store memory address. 7601 unsigned LastConsecutiveStore = 0; 7602 int64_t StartAddress = StoreNodes[0].OffsetFromBase; 7603 for (unsigned i=1; i<StoreNodes.size(); ++i) { 7604 int64_t CurrAddress = StoreNodes[i].OffsetFromBase; 7605 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7606 break; 7607 7608 // Mark this node as useful. 7609 LastConsecutiveStore = i; 7610 } 7611 7612 // The node with the lowest store address. 7613 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; 7614 7615 // Store the constants into memory as one consecutive store. 7616 if (!IsLoadSrc) { 7617 unsigned LastLegalType = 0; 7618 unsigned LastLegalVectorType = 0; 7619 bool NonZero = false; 7620 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7621 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7622 SDValue StoredVal = St->getValue(); 7623 7624 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) { 7625 NonZero |= !C->isNullValue(); 7626 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) { 7627 NonZero |= !C->getConstantFPValue()->isNullValue(); 7628 } else { 7629 // Non constant. 7630 break; 7631 } 7632 7633 // Find a legal type for the constant store. 7634 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7635 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7636 if (TLI.isTypeLegal(StoreTy)) 7637 LastLegalType = i+1; 7638 7639 // Find a legal type for the vector store. 7640 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7641 if (TLI.isTypeLegal(Ty)) 7642 LastLegalVectorType = i + 1; 7643 } 7644 7645 // We only use vectors if the constant is known to be zero. 7646 if (NonZero) 7647 LastLegalVectorType = 0; 7648 7649 // Check if we found a legal integer type to store. 7650 if (LastLegalType == 0 && LastLegalVectorType == 0) 7651 return false; 7652 7653 bool UseVector = LastLegalVectorType > LastLegalType; 7654 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType; 7655 7656 // Make sure we have something to merge. 7657 if (NumElem < 2) 7658 return false; 7659 7660 unsigned EarliestNodeUsed = 0; 7661 for (unsigned i=0; i < NumElem; ++i) { 7662 // Find a chain for the new wide-store operand. Notice that some 7663 // of the store nodes that we found may not be selected for inclusion 7664 // in the wide store. The chain we use needs to be the chain of the 7665 // earliest store node which is *used* and replaced by the wide store. 7666 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7667 EarliestNodeUsed = i; 7668 } 7669 7670 // The earliest Node in the DAG. 7671 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7672 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc(); 7673 7674 SDValue StoredVal; 7675 if (UseVector) { 7676 // Find a legal type for the vector store. 7677 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7678 assert(TLI.isTypeLegal(Ty) && "Illegal vector store"); 7679 StoredVal = DAG.getConstant(0, Ty); 7680 } else { 7681 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7682 APInt StoreInt(StoreBW, 0); 7683 7684 // Construct a single integer constant which is made of the smaller 7685 // constant inputs. 7686 bool IsLE = TLI.isLittleEndian(); 7687 for (unsigned i = 0; i < NumElem ; ++i) { 7688 unsigned Idx = IsLE ?(NumElem - 1 - i) : i; 7689 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode); 7690 SDValue Val = St->getValue(); 7691 StoreInt<<=ElementSizeBytes*8; 7692 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) { 7693 StoreInt|=C->getAPIntValue().zext(StoreBW); 7694 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) { 7695 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW); 7696 } else { 7697 assert(false && "Invalid constant element type"); 7698 } 7699 } 7700 7701 // Create the new Load and Store operations. 7702 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7703 StoredVal = DAG.getConstant(StoreInt, StoreTy); 7704 } 7705 7706 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal, 7707 FirstInChain->getBasePtr(), 7708 FirstInChain->getPointerInfo(), 7709 false, false, 7710 FirstInChain->getAlignment()); 7711 7712 // Replace the first store with the new store 7713 CombineTo(EarliestOp, NewStore); 7714 // Erase all other stores. 7715 for (unsigned i = 0; i < NumElem ; ++i) { 7716 if (StoreNodes[i].MemNode == EarliestOp) 7717 continue; 7718 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7719 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain()); 7720 removeFromWorkList(St); 7721 DAG.DeleteNode(St); 7722 } 7723 7724 return true; 7725 } 7726 7727 // Below we handle the case of multiple consecutive stores that 7728 // come from multiple consecutive loads. We merge them into a single 7729 // wide load and a single wide store. 7730 7731 // Look for load nodes which are used by the stored values. 7732 SmallVector<MemOpLink, 8> LoadNodes; 7733 7734 // Find acceptable loads. Loads need to have the same chain (token factor), 7735 // must not be zext, volatile, indexed, and they must be consecutive. 7736 SDValue LdBasePtr; 7737 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7738 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7739 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue()); 7740 if (!Ld) break; 7741 7742 // Loads must only have one use. 7743 if (!Ld->hasNUsesOfValue(1, 0)) 7744 break; 7745 7746 // Check that the alignment is the same as the stores. 7747 if (Ld->getAlignment() != St->getAlignment()) 7748 break; 7749 7750 // The memory operands must not be volatile. 7751 if (Ld->isVolatile() || Ld->isIndexed()) 7752 break; 7753 7754 // We do not accept ext loads. 7755 if (Ld->getExtensionType() != ISD::NON_EXTLOAD) 7756 break; 7757 7758 // The stored memory type must be the same. 7759 if (Ld->getMemoryVT() != MemVT) 7760 break; 7761 7762 std::pair<SDValue, int64_t> LdPtr = 7763 GetPointerBaseAndOffset(Ld->getBasePtr()); 7764 7765 // If this is not the first ptr that we check. 7766 if (LdBasePtr.getNode()) { 7767 // The base ptr must be the same. 7768 if (LdPtr.first != LdBasePtr) 7769 break; 7770 } else { 7771 // Check that all other base pointers are the same as this one. 7772 LdBasePtr = LdPtr.first; 7773 } 7774 7775 // We found a potential memory operand to merge. 7776 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0)); 7777 } 7778 7779 if (LoadNodes.size() < 2) 7780 return false; 7781 7782 // Scan the memory operations on the chain and find the first non-consecutive 7783 // load memory address. These variables hold the index in the store node 7784 // array. 7785 unsigned LastConsecutiveLoad = 0; 7786 // This variable refers to the size and not index in the array. 7787 unsigned LastLegalVectorType = 0; 7788 unsigned LastLegalIntegerType = 0; 7789 StartAddress = LoadNodes[0].OffsetFromBase; 7790 SDValue FirstChain = LoadNodes[0].MemNode->getChain(); 7791 for (unsigned i = 1; i < LoadNodes.size(); ++i) { 7792 // All loads much share the same chain. 7793 if (LoadNodes[i].MemNode->getChain() != FirstChain) 7794 break; 7795 7796 int64_t CurrAddress = LoadNodes[i].OffsetFromBase; 7797 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7798 break; 7799 LastConsecutiveLoad = i; 7800 7801 // Find a legal type for the vector store. 7802 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7803 if (TLI.isTypeLegal(StoreTy)) 7804 LastLegalVectorType = i + 1; 7805 7806 // Find a legal type for the integer store. 7807 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7808 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7809 if (TLI.isTypeLegal(StoreTy)) 7810 LastLegalIntegerType = i + 1; 7811 } 7812 7813 // Only use vector types if the vector type is larger than the integer type. 7814 // If they are the same, use integers. 7815 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType; 7816 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType); 7817 7818 // We add +1 here because the LastXXX variables refer to location while 7819 // the NumElem refers to array/index size. 7820 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1; 7821 NumElem = std::min(LastLegalType, NumElem); 7822 7823 if (NumElem < 2) 7824 return false; 7825 7826 // The earliest Node in the DAG. 7827 unsigned EarliestNodeUsed = 0; 7828 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7829 for (unsigned i=1; i<NumElem; ++i) { 7830 // Find a chain for the new wide-store operand. Notice that some 7831 // of the store nodes that we found may not be selected for inclusion 7832 // in the wide store. The chain we use needs to be the chain of the 7833 // earliest store node which is *used* and replaced by the wide store. 7834 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7835 EarliestNodeUsed = i; 7836 } 7837 7838 // Find if it is better to use vectors or integers to load and store 7839 // to memory. 7840 EVT JointMemOpVT; 7841 if (UseVectorTy) { 7842 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7843 } else { 7844 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7845 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7846 } 7847 7848 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc(); 7849 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc(); 7850 7851 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode); 7852 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL, 7853 FirstLoad->getChain(), 7854 FirstLoad->getBasePtr(), 7855 FirstLoad->getPointerInfo(), 7856 false, false, false, 7857 FirstLoad->getAlignment()); 7858 7859 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad, 7860 FirstInChain->getBasePtr(), 7861 FirstInChain->getPointerInfo(), false, false, 7862 FirstInChain->getAlignment()); 7863 7864 // Replace one of the loads with the new load. 7865 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode); 7866 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), 7867 SDValue(NewLoad.getNode(), 1)); 7868 7869 // Remove the rest of the load chains. 7870 for (unsigned i = 1; i < NumElem ; ++i) { 7871 // Replace all chain users of the old load nodes with the chain of the new 7872 // load node. 7873 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode); 7874 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain()); 7875 } 7876 7877 // Replace the first store with the new store. 7878 CombineTo(EarliestOp, NewStore); 7879 // Erase all other stores. 7880 for (unsigned i = 0; i < NumElem ; ++i) { 7881 // Remove all Store nodes. 7882 if (StoreNodes[i].MemNode == EarliestOp) 7883 continue; 7884 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7885 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain()); 7886 removeFromWorkList(St); 7887 DAG.DeleteNode(St); 7888 } 7889 7890 return true; 7891} 7892 7893SDValue DAGCombiner::visitSTORE(SDNode *N) { 7894 StoreSDNode *ST = cast<StoreSDNode>(N); 7895 SDValue Chain = ST->getChain(); 7896 SDValue Value = ST->getValue(); 7897 SDValue Ptr = ST->getBasePtr(); 7898 7899 // If this is a store of a bit convert, store the input value if the 7900 // resultant store does not need a higher alignment than the original. 7901 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 7902 ST->isUnindexed()) { 7903 unsigned OrigAlign = ST->getAlignment(); 7904 EVT SVT = Value.getOperand(0).getValueType(); 7905 unsigned Align = TLI.getDataLayout()-> 7906 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 7907 if (Align <= OrigAlign && 7908 ((!LegalOperations && !ST->isVolatile()) || 7909 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 7910 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7911 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7912 ST->isNonTemporal(), OrigAlign); 7913 } 7914 7915 // Turn 'store undef, Ptr' -> nothing. 7916 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 7917 return Chain; 7918 7919 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 7920 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 7921 // NOTE: If the original store is volatile, this transform must not increase 7922 // the number of stores. For example, on x86-32 an f64 can be stored in one 7923 // processor operation but an i64 (which is not legal) requires two. So the 7924 // transform should not be done in this case. 7925 if (Value.getOpcode() != ISD::TargetConstantFP) { 7926 SDValue Tmp; 7927 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 7928 default: llvm_unreachable("Unknown FP type"); 7929 case MVT::f16: // We don't do this for these yet. 7930 case MVT::f80: 7931 case MVT::f128: 7932 case MVT::ppcf128: 7933 break; 7934 case MVT::f32: 7935 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 7936 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7937 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 7938 bitcastToAPInt().getZExtValue(), MVT::i32); 7939 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7940 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7941 ST->isNonTemporal(), ST->getAlignment()); 7942 } 7943 break; 7944 case MVT::f64: 7945 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 7946 !ST->isVolatile()) || 7947 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 7948 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 7949 getZExtValue(), MVT::i64); 7950 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7951 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7952 ST->isNonTemporal(), ST->getAlignment()); 7953 } 7954 7955 if (!ST->isVolatile() && 7956 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7957 // Many FP stores are not made apparent until after legalize, e.g. for 7958 // argument passing. Since this is so common, custom legalize the 7959 // 64-bit integer store into two 32-bit stores. 7960 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 7961 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 7962 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 7963 if (TLI.isBigEndian()) std::swap(Lo, Hi); 7964 7965 unsigned Alignment = ST->getAlignment(); 7966 bool isVolatile = ST->isVolatile(); 7967 bool isNonTemporal = ST->isNonTemporal(); 7968 7969 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 7970 Ptr, ST->getPointerInfo(), 7971 isVolatile, isNonTemporal, 7972 ST->getAlignment()); 7973 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 7974 DAG.getConstant(4, Ptr.getValueType())); 7975 Alignment = MinAlign(Alignment, 4U); 7976 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 7977 Ptr, ST->getPointerInfo().getWithOffset(4), 7978 isVolatile, isNonTemporal, 7979 Alignment); 7980 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7981 St0, St1); 7982 } 7983 7984 break; 7985 } 7986 } 7987 } 7988 7989 // Try to infer better alignment information than the store already has. 7990 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 7991 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7992 if (Align > ST->getAlignment()) 7993 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 7994 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7995 ST->isVolatile(), ST->isNonTemporal(), Align); 7996 } 7997 } 7998 7999 // Try transforming a pair floating point load / store ops to integer 8000 // load / store ops. 8001 SDValue NewST = TransformFPLoadStorePair(N); 8002 if (NewST.getNode()) 8003 return NewST; 8004 8005 if (CombinerAA) { 8006 // Walk up chain skipping non-aliasing memory nodes. 8007 SDValue BetterChain = FindBetterChain(N, Chain); 8008 8009 // If there is a better chain. 8010 if (Chain != BetterChain) { 8011 SDValue ReplStore; 8012 8013 // Replace the chain to avoid dependency. 8014 if (ST->isTruncatingStore()) { 8015 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8016 ST->getPointerInfo(), 8017 ST->getMemoryVT(), ST->isVolatile(), 8018 ST->isNonTemporal(), ST->getAlignment()); 8019 } else { 8020 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8021 ST->getPointerInfo(), 8022 ST->isVolatile(), ST->isNonTemporal(), 8023 ST->getAlignment()); 8024 } 8025 8026 // Create token to keep both nodes around. 8027 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 8028 MVT::Other, Chain, ReplStore); 8029 8030 // Make sure the new and old chains are cleaned up. 8031 AddToWorkList(Token.getNode()); 8032 8033 // Don't add users to work list. 8034 return CombineTo(N, Token, false); 8035 } 8036 } 8037 8038 // Try transforming N to an indexed store. 8039 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 8040 return SDValue(N, 0); 8041 8042 // FIXME: is there such a thing as a truncating indexed store? 8043 if (ST->isTruncatingStore() && ST->isUnindexed() && 8044 Value.getValueType().isInteger()) { 8045 // See if we can simplify the input to this truncstore with knowledge that 8046 // only the low bits are being used. For example: 8047 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 8048 SDValue Shorter = 8049 GetDemandedBits(Value, 8050 APInt::getLowBitsSet( 8051 Value.getValueType().getScalarType().getSizeInBits(), 8052 ST->getMemoryVT().getScalarType().getSizeInBits())); 8053 AddToWorkList(Value.getNode()); 8054 if (Shorter.getNode()) 8055 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 8056 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8057 ST->isVolatile(), ST->isNonTemporal(), 8058 ST->getAlignment()); 8059 8060 // Otherwise, see if we can simplify the operation with 8061 // SimplifyDemandedBits, which only works if the value has a single use. 8062 if (SimplifyDemandedBits(Value, 8063 APInt::getLowBitsSet( 8064 Value.getValueType().getScalarType().getSizeInBits(), 8065 ST->getMemoryVT().getScalarType().getSizeInBits()))) 8066 return SDValue(N, 0); 8067 } 8068 8069 // If this is a load followed by a store to the same location, then the store 8070 // is dead/noop. 8071 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 8072 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 8073 ST->isUnindexed() && !ST->isVolatile() && 8074 // There can't be any side effects between the load and store, such as 8075 // a call or store. 8076 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 8077 // The store is dead, remove it. 8078 return Chain; 8079 } 8080 } 8081 8082 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 8083 // truncating store. We can do this even if this is already a truncstore. 8084 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 8085 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 8086 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 8087 ST->getMemoryVT())) { 8088 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8089 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8090 ST->isVolatile(), ST->isNonTemporal(), 8091 ST->getAlignment()); 8092 } 8093 8094 // Only perform this optimization before the types are legal, because we 8095 // don't want to perform this optimization on every DAGCombine invocation. 8096 if (!LegalTypes && MergeConsecutiveStores(ST)) 8097 return SDValue(N, 0); 8098 8099 return ReduceLoadOpStoreWidth(N); 8100} 8101 8102SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 8103 SDValue InVec = N->getOperand(0); 8104 SDValue InVal = N->getOperand(1); 8105 SDValue EltNo = N->getOperand(2); 8106 DebugLoc dl = N->getDebugLoc(); 8107 8108 // If the inserted element is an UNDEF, just use the input vector. 8109 if (InVal.getOpcode() == ISD::UNDEF) 8110 return InVec; 8111 8112 EVT VT = InVec.getValueType(); 8113 8114 // If we can't generate a legal BUILD_VECTOR, exit 8115 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 8116 return SDValue(); 8117 8118 // Check that we know which element is being inserted 8119 if (!isa<ConstantSDNode>(EltNo)) 8120 return SDValue(); 8121 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8122 8123 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 8124 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 8125 // vector elements. 8126 SmallVector<SDValue, 8> Ops; 8127 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 8128 Ops.append(InVec.getNode()->op_begin(), 8129 InVec.getNode()->op_end()); 8130 } else if (InVec.getOpcode() == ISD::UNDEF) { 8131 unsigned NElts = VT.getVectorNumElements(); 8132 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 8133 } else { 8134 return SDValue(); 8135 } 8136 8137 // Insert the element 8138 if (Elt < Ops.size()) { 8139 // All the operands of BUILD_VECTOR must have the same type; 8140 // we enforce that here. 8141 EVT OpVT = Ops[0].getValueType(); 8142 if (InVal.getValueType() != OpVT) 8143 InVal = OpVT.bitsGT(InVal.getValueType()) ? 8144 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 8145 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 8146 Ops[Elt] = InVal; 8147 } 8148 8149 // Return the new vector 8150 return DAG.getNode(ISD::BUILD_VECTOR, dl, 8151 VT, &Ops[0], Ops.size()); 8152} 8153 8154SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 8155 // (vextract (scalar_to_vector val, 0) -> val 8156 SDValue InVec = N->getOperand(0); 8157 EVT VT = InVec.getValueType(); 8158 EVT NVT = N->getValueType(0); 8159 8160 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 8161 // Check if the result type doesn't match the inserted element type. A 8162 // SCALAR_TO_VECTOR may truncate the inserted element and the 8163 // EXTRACT_VECTOR_ELT may widen the extracted vector. 8164 SDValue InOp = InVec.getOperand(0); 8165 if (InOp.getValueType() != NVT) { 8166 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 8167 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 8168 } 8169 return InOp; 8170 } 8171 8172 SDValue EltNo = N->getOperand(1); 8173 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 8174 8175 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 8176 // We only perform this optimization before the op legalization phase because 8177 // we may introduce new vector instructions which are not backed by TD 8178 // patterns. For example on AVX, extracting elements from a wide vector 8179 // without using extract_subvector. 8180 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 8181 && ConstEltNo && !LegalOperations) { 8182 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8183 int NumElem = VT.getVectorNumElements(); 8184 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 8185 // Find the new index to extract from. 8186 int OrigElt = SVOp->getMaskElt(Elt); 8187 8188 // Extracting an undef index is undef. 8189 if (OrigElt == -1) 8190 return DAG.getUNDEF(NVT); 8191 8192 // Select the right vector half to extract from. 8193 if (OrigElt < NumElem) { 8194 InVec = InVec->getOperand(0); 8195 } else { 8196 InVec = InVec->getOperand(1); 8197 OrigElt -= NumElem; 8198 } 8199 8200 EVT IndexTy = N->getOperand(1).getValueType(); 8201 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 8202 InVec, DAG.getConstant(OrigElt, IndexTy)); 8203 } 8204 8205 // Perform only after legalization to ensure build_vector / vector_shuffle 8206 // optimizations have already been done. 8207 if (!LegalOperations) return SDValue(); 8208 8209 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 8210 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 8211 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 8212 8213 if (ConstEltNo) { 8214 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8215 bool NewLoad = false; 8216 bool BCNumEltsChanged = false; 8217 EVT ExtVT = VT.getVectorElementType(); 8218 EVT LVT = ExtVT; 8219 8220 // If the result of load has to be truncated, then it's not necessarily 8221 // profitable. 8222 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 8223 return SDValue(); 8224 8225 if (InVec.getOpcode() == ISD::BITCAST) { 8226 // Don't duplicate a load with other uses. 8227 if (!InVec.hasOneUse()) 8228 return SDValue(); 8229 8230 EVT BCVT = InVec.getOperand(0).getValueType(); 8231 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 8232 return SDValue(); 8233 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 8234 BCNumEltsChanged = true; 8235 InVec = InVec.getOperand(0); 8236 ExtVT = BCVT.getVectorElementType(); 8237 NewLoad = true; 8238 } 8239 8240 LoadSDNode *LN0 = NULL; 8241 const ShuffleVectorSDNode *SVN = NULL; 8242 if (ISD::isNormalLoad(InVec.getNode())) { 8243 LN0 = cast<LoadSDNode>(InVec); 8244 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 8245 InVec.getOperand(0).getValueType() == ExtVT && 8246 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 8247 // Don't duplicate a load with other uses. 8248 if (!InVec.hasOneUse()) 8249 return SDValue(); 8250 8251 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 8252 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 8253 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 8254 // => 8255 // (load $addr+1*size) 8256 8257 // Don't duplicate a load with other uses. 8258 if (!InVec.hasOneUse()) 8259 return SDValue(); 8260 8261 // If the bit convert changed the number of elements, it is unsafe 8262 // to examine the mask. 8263 if (BCNumEltsChanged) 8264 return SDValue(); 8265 8266 // Select the input vector, guarding against out of range extract vector. 8267 unsigned NumElems = VT.getVectorNumElements(); 8268 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 8269 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 8270 8271 if (InVec.getOpcode() == ISD::BITCAST) { 8272 // Don't duplicate a load with other uses. 8273 if (!InVec.hasOneUse()) 8274 return SDValue(); 8275 8276 InVec = InVec.getOperand(0); 8277 } 8278 if (ISD::isNormalLoad(InVec.getNode())) { 8279 LN0 = cast<LoadSDNode>(InVec); 8280 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 8281 } 8282 } 8283 8284 // Make sure we found a non-volatile load and the extractelement is 8285 // the only use. 8286 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 8287 return SDValue(); 8288 8289 // If Idx was -1 above, Elt is going to be -1, so just return undef. 8290 if (Elt == -1) 8291 return DAG.getUNDEF(LVT); 8292 8293 unsigned Align = LN0->getAlignment(); 8294 if (NewLoad) { 8295 // Check the resultant load doesn't need a higher alignment than the 8296 // original load. 8297 unsigned NewAlign = 8298 TLI.getDataLayout() 8299 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 8300 8301 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 8302 return SDValue(); 8303 8304 Align = NewAlign; 8305 } 8306 8307 SDValue NewPtr = LN0->getBasePtr(); 8308 unsigned PtrOff = 0; 8309 8310 if (Elt) { 8311 PtrOff = LVT.getSizeInBits() * Elt / 8; 8312 EVT PtrType = NewPtr.getValueType(); 8313 if (TLI.isBigEndian()) 8314 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 8315 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 8316 DAG.getConstant(PtrOff, PtrType)); 8317 } 8318 8319 // The replacement we need to do here is a little tricky: we need to 8320 // replace an extractelement of a load with a load. 8321 // Use ReplaceAllUsesOfValuesWith to do the replacement. 8322 // Note that this replacement assumes that the extractvalue is the only 8323 // use of the load; that's okay because we don't want to perform this 8324 // transformation in other cases anyway. 8325 SDValue Load; 8326 SDValue Chain; 8327 if (NVT.bitsGT(LVT)) { 8328 // If the result type of vextract is wider than the load, then issue an 8329 // extending load instead. 8330 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 8331 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 8332 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 8333 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 8334 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 8335 Chain = Load.getValue(1); 8336 } else { 8337 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 8338 LN0->getPointerInfo().getWithOffset(PtrOff), 8339 LN0->isVolatile(), LN0->isNonTemporal(), 8340 LN0->isInvariant(), Align); 8341 Chain = Load.getValue(1); 8342 if (NVT.bitsLT(LVT)) 8343 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 8344 else 8345 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 8346 } 8347 WorkListRemover DeadNodes(*this); 8348 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 8349 SDValue To[] = { Load, Chain }; 8350 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 8351 // Since we're explcitly calling ReplaceAllUses, add the new node to the 8352 // worklist explicitly as well. 8353 AddToWorkList(Load.getNode()); 8354 AddUsersToWorkList(Load.getNode()); // Add users too 8355 // Make sure to revisit this node to clean it up; it will usually be dead. 8356 AddToWorkList(N); 8357 return SDValue(N, 0); 8358 } 8359 8360 return SDValue(); 8361} 8362 8363SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 8364 unsigned NumInScalars = N->getNumOperands(); 8365 DebugLoc dl = N->getDebugLoc(); 8366 EVT VT = N->getValueType(0); 8367 8368 // A vector built entirely of undefs is undef. 8369 if (ISD::allOperandsUndef(N)) 8370 return DAG.getUNDEF(VT); 8371 8372 // Check to see if this is a BUILD_VECTOR of a bunch of values 8373 // which come from any_extend or zero_extend nodes. If so, we can create 8374 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 8375 // optimizations. We do not handle sign-extend because we can't fill the sign 8376 // using shuffles. 8377 EVT SourceType = MVT::Other; 8378 bool AllAnyExt = true; 8379 8380 for (unsigned i = 0; i != NumInScalars; ++i) { 8381 SDValue In = N->getOperand(i); 8382 // Ignore undef inputs. 8383 if (In.getOpcode() == ISD::UNDEF) continue; 8384 8385 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 8386 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 8387 8388 // Abort if the element is not an extension. 8389 if (!ZeroExt && !AnyExt) { 8390 SourceType = MVT::Other; 8391 break; 8392 } 8393 8394 // The input is a ZeroExt or AnyExt. Check the original type. 8395 EVT InTy = In.getOperand(0).getValueType(); 8396 8397 // Check that all of the widened source types are the same. 8398 if (SourceType == MVT::Other) 8399 // First time. 8400 SourceType = InTy; 8401 else if (InTy != SourceType) { 8402 // Multiple income types. Abort. 8403 SourceType = MVT::Other; 8404 break; 8405 } 8406 8407 // Check if all of the extends are ANY_EXTENDs. 8408 AllAnyExt &= AnyExt; 8409 } 8410 8411 // In order to have valid types, all of the inputs must be extended from the 8412 // same source type and all of the inputs must be any or zero extend. 8413 // Scalar sizes must be a power of two. 8414 EVT OutScalarTy = N->getValueType(0).getScalarType(); 8415 bool ValidTypes = SourceType != MVT::Other && 8416 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 8417 isPowerOf2_32(SourceType.getSizeInBits()); 8418 8419 // We perform this optimization post type-legalization because 8420 // the type-legalizer often scalarizes integer-promoted vectors. 8421 // Performing this optimization before may create bit-casts which 8422 // will be type-legalized to complex code sequences. 8423 // We perform this optimization only before the operation legalizer because we 8424 // may introduce illegal operations. 8425 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 8426 // turn into a single shuffle instruction. 8427 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 8428 ValidTypes) { 8429 bool isLE = TLI.isLittleEndian(); 8430 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 8431 assert(ElemRatio > 1 && "Invalid element size ratio"); 8432 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 8433 DAG.getConstant(0, SourceType); 8434 8435 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 8436 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 8437 8438 // Populate the new build_vector 8439 for (unsigned i=0; i < N->getNumOperands(); ++i) { 8440 SDValue Cast = N->getOperand(i); 8441 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 8442 Cast.getOpcode() == ISD::ZERO_EXTEND || 8443 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 8444 SDValue In; 8445 if (Cast.getOpcode() == ISD::UNDEF) 8446 In = DAG.getUNDEF(SourceType); 8447 else 8448 In = Cast->getOperand(0); 8449 unsigned Index = isLE ? (i * ElemRatio) : 8450 (i * ElemRatio + (ElemRatio - 1)); 8451 8452 assert(Index < Ops.size() && "Invalid index"); 8453 Ops[Index] = In; 8454 } 8455 8456 // The type of the new BUILD_VECTOR node. 8457 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 8458 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 8459 "Invalid vector size"); 8460 // Check if the new vector type is legal. 8461 if (!isTypeLegal(VecVT)) return SDValue(); 8462 8463 // Make the new BUILD_VECTOR. 8464 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8465 VecVT, &Ops[0], Ops.size()); 8466 8467 // The new BUILD_VECTOR node has the potential to be further optimized. 8468 AddToWorkList(BV.getNode()); 8469 // Bitcast to the desired type. 8470 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 8471 } 8472 8473 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 8474 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 8475 // at most two distinct vectors, turn this into a shuffle node. 8476 8477 // May only combine to shuffle after legalize if shuffle is legal. 8478 if (LegalOperations && 8479 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 8480 return SDValue(); 8481 8482 SDValue VecIn1, VecIn2; 8483 for (unsigned i = 0; i != NumInScalars; ++i) { 8484 // Ignore undef inputs. 8485 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 8486 8487 // If this input is something other than a EXTRACT_VECTOR_ELT with a 8488 // constant index, bail out. 8489 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 8490 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 8491 VecIn1 = VecIn2 = SDValue(0, 0); 8492 break; 8493 } 8494 8495 // We allow up to two distinct input vectors. 8496 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 8497 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 8498 continue; 8499 8500 if (VecIn1.getNode() == 0) { 8501 VecIn1 = ExtractedFromVec; 8502 } else if (VecIn2.getNode() == 0) { 8503 VecIn2 = ExtractedFromVec; 8504 } else { 8505 // Too many inputs. 8506 VecIn1 = VecIn2 = SDValue(0, 0); 8507 break; 8508 } 8509 } 8510 8511 // If everything is good, we can make a shuffle operation. 8512 if (VecIn1.getNode()) { 8513 SmallVector<int, 8> Mask; 8514 for (unsigned i = 0; i != NumInScalars; ++i) { 8515 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 8516 Mask.push_back(-1); 8517 continue; 8518 } 8519 8520 // If extracting from the first vector, just use the index directly. 8521 SDValue Extract = N->getOperand(i); 8522 SDValue ExtVal = Extract.getOperand(1); 8523 if (Extract.getOperand(0) == VecIn1) { 8524 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8525 if (ExtIndex > VT.getVectorNumElements()) 8526 return SDValue(); 8527 8528 Mask.push_back(ExtIndex); 8529 continue; 8530 } 8531 8532 // Otherwise, use InIdx + VecSize 8533 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8534 Mask.push_back(Idx+NumInScalars); 8535 } 8536 8537 // We can't generate a shuffle node with mismatched input and output types. 8538 // Attempt to transform a single input vector to the correct type. 8539 if ((VT != VecIn1.getValueType())) { 8540 // We don't support shuffeling between TWO values of different types. 8541 if (VecIn2.getNode() != 0) 8542 return SDValue(); 8543 8544 // We only support widening of vectors which are half the size of the 8545 // output registers. For example XMM->YMM widening on X86 with AVX. 8546 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 8547 return SDValue(); 8548 8549 // If the input vector type has a different base type to the output 8550 // vector type, bail out. 8551 if (VecIn1.getValueType().getVectorElementType() != 8552 VT.getVectorElementType()) 8553 return SDValue(); 8554 8555 // Widen the input vector by adding undef values. 8556 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 8557 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 8558 } 8559 8560 // If VecIn2 is unused then change it to undef. 8561 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 8562 8563 // Check that we were able to transform all incoming values to the same 8564 // type. 8565 if (VecIn2.getValueType() != VecIn1.getValueType() || 8566 VecIn1.getValueType() != VT) 8567 return SDValue(); 8568 8569 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 8570 if (!isTypeLegal(VT)) 8571 return SDValue(); 8572 8573 // Return the new VECTOR_SHUFFLE node. 8574 SDValue Ops[2]; 8575 Ops[0] = VecIn1; 8576 Ops[1] = VecIn2; 8577 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 8578 } 8579 8580 return SDValue(); 8581} 8582 8583SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 8584 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 8585 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 8586 // inputs come from at most two distinct vectors, turn this into a shuffle 8587 // node. 8588 8589 // If we only have one input vector, we don't need to do any concatenation. 8590 if (N->getNumOperands() == 1) 8591 return N->getOperand(0); 8592 8593 // Check if all of the operands are undefs. 8594 if (ISD::allOperandsUndef(N)) 8595 return DAG.getUNDEF(N->getValueType(0)); 8596 8597 return SDValue(); 8598} 8599 8600SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 8601 EVT NVT = N->getValueType(0); 8602 SDValue V = N->getOperand(0); 8603 8604 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 8605 // Handle only simple case where vector being inserted and vector 8606 // being extracted are of same type, and are half size of larger vectors. 8607 EVT BigVT = V->getOperand(0).getValueType(); 8608 EVT SmallVT = V->getOperand(1).getValueType(); 8609 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 8610 return SDValue(); 8611 8612 // Only handle cases where both indexes are constants with the same type. 8613 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8614 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 8615 8616 if (InsIdx && ExtIdx && 8617 InsIdx->getValueType(0).getSizeInBits() <= 64 && 8618 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 8619 // Combine: 8620 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 8621 // Into: 8622 // indices are equal => V1 8623 // otherwise => (extract_subvec V1, ExtIdx) 8624 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 8625 return V->getOperand(1); 8626 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 8627 V->getOperand(0), N->getOperand(1)); 8628 } 8629 } 8630 8631 return SDValue(); 8632} 8633 8634SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 8635 EVT VT = N->getValueType(0); 8636 unsigned NumElts = VT.getVectorNumElements(); 8637 8638 SDValue N0 = N->getOperand(0); 8639 SDValue N1 = N->getOperand(1); 8640 8641 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 8642 8643 // Canonicalize shuffle undef, undef -> undef 8644 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 8645 return DAG.getUNDEF(VT); 8646 8647 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8648 8649 // Canonicalize shuffle v, v -> v, undef 8650 if (N0 == N1) { 8651 SmallVector<int, 8> NewMask; 8652 for (unsigned i = 0; i != NumElts; ++i) { 8653 int Idx = SVN->getMaskElt(i); 8654 if (Idx >= (int)NumElts) Idx -= NumElts; 8655 NewMask.push_back(Idx); 8656 } 8657 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 8658 &NewMask[0]); 8659 } 8660 8661 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 8662 if (N0.getOpcode() == ISD::UNDEF) { 8663 SmallVector<int, 8> NewMask; 8664 for (unsigned i = 0; i != NumElts; ++i) { 8665 int Idx = SVN->getMaskElt(i); 8666 if (Idx >= 0) { 8667 if (Idx < (int)NumElts) 8668 Idx += NumElts; 8669 else 8670 Idx -= NumElts; 8671 } 8672 NewMask.push_back(Idx); 8673 } 8674 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 8675 &NewMask[0]); 8676 } 8677 8678 // Remove references to rhs if it is undef 8679 if (N1.getOpcode() == ISD::UNDEF) { 8680 bool Changed = false; 8681 SmallVector<int, 8> NewMask; 8682 for (unsigned i = 0; i != NumElts; ++i) { 8683 int Idx = SVN->getMaskElt(i); 8684 if (Idx >= (int)NumElts) { 8685 Idx = -1; 8686 Changed = true; 8687 } 8688 NewMask.push_back(Idx); 8689 } 8690 if (Changed) 8691 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 8692 } 8693 8694 // If it is a splat, check if the argument vector is another splat or a 8695 // build_vector with all scalar elements the same. 8696 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 8697 SDNode *V = N0.getNode(); 8698 8699 // If this is a bit convert that changes the element type of the vector but 8700 // not the number of vector elements, look through it. Be careful not to 8701 // look though conversions that change things like v4f32 to v2f64. 8702 if (V->getOpcode() == ISD::BITCAST) { 8703 SDValue ConvInput = V->getOperand(0); 8704 if (ConvInput.getValueType().isVector() && 8705 ConvInput.getValueType().getVectorNumElements() == NumElts) 8706 V = ConvInput.getNode(); 8707 } 8708 8709 if (V->getOpcode() == ISD::BUILD_VECTOR) { 8710 assert(V->getNumOperands() == NumElts && 8711 "BUILD_VECTOR has wrong number of operands"); 8712 SDValue Base; 8713 bool AllSame = true; 8714 for (unsigned i = 0; i != NumElts; ++i) { 8715 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 8716 Base = V->getOperand(i); 8717 break; 8718 } 8719 } 8720 // Splat of <u, u, u, u>, return <u, u, u, u> 8721 if (!Base.getNode()) 8722 return N0; 8723 for (unsigned i = 0; i != NumElts; ++i) { 8724 if (V->getOperand(i) != Base) { 8725 AllSame = false; 8726 break; 8727 } 8728 } 8729 // Splat of <x, x, x, x>, return <x, x, x, x> 8730 if (AllSame) 8731 return N0; 8732 } 8733 } 8734 8735 // If this shuffle node is simply a swizzle of another shuffle node, 8736 // and it reverses the swizzle of the previous shuffle then we can 8737 // optimize shuffle(shuffle(x, undef), undef) -> x. 8738 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 8739 N1.getOpcode() == ISD::UNDEF) { 8740 8741 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 8742 8743 // Shuffle nodes can only reverse shuffles with a single non-undef value. 8744 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 8745 return SDValue(); 8746 8747 // The incoming shuffle must be of the same type as the result of the 8748 // current shuffle. 8749 assert(OtherSV->getOperand(0).getValueType() == VT && 8750 "Shuffle types don't match"); 8751 8752 for (unsigned i = 0; i != NumElts; ++i) { 8753 int Idx = SVN->getMaskElt(i); 8754 assert(Idx < (int)NumElts && "Index references undef operand"); 8755 // Next, this index comes from the first value, which is the incoming 8756 // shuffle. Adopt the incoming index. 8757 if (Idx >= 0) 8758 Idx = OtherSV->getMaskElt(Idx); 8759 8760 // The combined shuffle must map each index to itself. 8761 if (Idx >= 0 && (unsigned)Idx != i) 8762 return SDValue(); 8763 } 8764 8765 return OtherSV->getOperand(0); 8766 } 8767 8768 return SDValue(); 8769} 8770 8771SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 8772 if (!TLI.getShouldFoldAtomicFences()) 8773 return SDValue(); 8774 8775 SDValue atomic = N->getOperand(0); 8776 switch (atomic.getOpcode()) { 8777 case ISD::ATOMIC_CMP_SWAP: 8778 case ISD::ATOMIC_SWAP: 8779 case ISD::ATOMIC_LOAD_ADD: 8780 case ISD::ATOMIC_LOAD_SUB: 8781 case ISD::ATOMIC_LOAD_AND: 8782 case ISD::ATOMIC_LOAD_OR: 8783 case ISD::ATOMIC_LOAD_XOR: 8784 case ISD::ATOMIC_LOAD_NAND: 8785 case ISD::ATOMIC_LOAD_MIN: 8786 case ISD::ATOMIC_LOAD_MAX: 8787 case ISD::ATOMIC_LOAD_UMIN: 8788 case ISD::ATOMIC_LOAD_UMAX: 8789 break; 8790 default: 8791 return SDValue(); 8792 } 8793 8794 SDValue fence = atomic.getOperand(0); 8795 if (fence.getOpcode() != ISD::MEMBARRIER) 8796 return SDValue(); 8797 8798 switch (atomic.getOpcode()) { 8799 case ISD::ATOMIC_CMP_SWAP: 8800 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 8801 fence.getOperand(0), 8802 atomic.getOperand(1), atomic.getOperand(2), 8803 atomic.getOperand(3)), atomic.getResNo()); 8804 case ISD::ATOMIC_SWAP: 8805 case ISD::ATOMIC_LOAD_ADD: 8806 case ISD::ATOMIC_LOAD_SUB: 8807 case ISD::ATOMIC_LOAD_AND: 8808 case ISD::ATOMIC_LOAD_OR: 8809 case ISD::ATOMIC_LOAD_XOR: 8810 case ISD::ATOMIC_LOAD_NAND: 8811 case ISD::ATOMIC_LOAD_MIN: 8812 case ISD::ATOMIC_LOAD_MAX: 8813 case ISD::ATOMIC_LOAD_UMIN: 8814 case ISD::ATOMIC_LOAD_UMAX: 8815 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 8816 fence.getOperand(0), 8817 atomic.getOperand(1), atomic.getOperand(2)), 8818 atomic.getResNo()); 8819 default: 8820 return SDValue(); 8821 } 8822} 8823 8824/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 8825/// an AND to a vector_shuffle with the destination vector and a zero vector. 8826/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 8827/// vector_shuffle V, Zero, <0, 4, 2, 4> 8828SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 8829 EVT VT = N->getValueType(0); 8830 DebugLoc dl = N->getDebugLoc(); 8831 SDValue LHS = N->getOperand(0); 8832 SDValue RHS = N->getOperand(1); 8833 if (N->getOpcode() == ISD::AND) { 8834 if (RHS.getOpcode() == ISD::BITCAST) 8835 RHS = RHS.getOperand(0); 8836 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 8837 SmallVector<int, 8> Indices; 8838 unsigned NumElts = RHS.getNumOperands(); 8839 for (unsigned i = 0; i != NumElts; ++i) { 8840 SDValue Elt = RHS.getOperand(i); 8841 if (!isa<ConstantSDNode>(Elt)) 8842 return SDValue(); 8843 8844 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 8845 Indices.push_back(i); 8846 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 8847 Indices.push_back(NumElts); 8848 else 8849 return SDValue(); 8850 } 8851 8852 // Let's see if the target supports this vector_shuffle. 8853 EVT RVT = RHS.getValueType(); 8854 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 8855 return SDValue(); 8856 8857 // Return the new VECTOR_SHUFFLE node. 8858 EVT EltVT = RVT.getVectorElementType(); 8859 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 8860 DAG.getConstant(0, EltVT)); 8861 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8862 RVT, &ZeroOps[0], ZeroOps.size()); 8863 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 8864 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 8865 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 8866 } 8867 } 8868 8869 return SDValue(); 8870} 8871 8872/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 8873SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 8874 // After legalize, the target may be depending on adds and other 8875 // binary ops to provide legal ways to construct constants or other 8876 // things. Simplifying them may result in a loss of legality. 8877 if (LegalOperations) return SDValue(); 8878 8879 assert(N->getValueType(0).isVector() && 8880 "SimplifyVBinOp only works on vectors!"); 8881 8882 SDValue LHS = N->getOperand(0); 8883 SDValue RHS = N->getOperand(1); 8884 SDValue Shuffle = XformToShuffleWithZero(N); 8885 if (Shuffle.getNode()) return Shuffle; 8886 8887 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 8888 // this operation. 8889 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 8890 RHS.getOpcode() == ISD::BUILD_VECTOR) { 8891 SmallVector<SDValue, 8> Ops; 8892 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 8893 SDValue LHSOp = LHS.getOperand(i); 8894 SDValue RHSOp = RHS.getOperand(i); 8895 // If these two elements can't be folded, bail out. 8896 if ((LHSOp.getOpcode() != ISD::UNDEF && 8897 LHSOp.getOpcode() != ISD::Constant && 8898 LHSOp.getOpcode() != ISD::ConstantFP) || 8899 (RHSOp.getOpcode() != ISD::UNDEF && 8900 RHSOp.getOpcode() != ISD::Constant && 8901 RHSOp.getOpcode() != ISD::ConstantFP)) 8902 break; 8903 8904 // Can't fold divide by zero. 8905 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 8906 N->getOpcode() == ISD::FDIV) { 8907 if ((RHSOp.getOpcode() == ISD::Constant && 8908 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 8909 (RHSOp.getOpcode() == ISD::ConstantFP && 8910 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 8911 break; 8912 } 8913 8914 EVT VT = LHSOp.getValueType(); 8915 EVT RVT = RHSOp.getValueType(); 8916 if (RVT != VT) { 8917 // Integer BUILD_VECTOR operands may have types larger than the element 8918 // size (e.g., when the element type is not legal). Prior to type 8919 // legalization, the types may not match between the two BUILD_VECTORS. 8920 // Truncate one of the operands to make them match. 8921 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 8922 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 8923 } else { 8924 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 8925 VT = RVT; 8926 } 8927 } 8928 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 8929 LHSOp, RHSOp); 8930 if (FoldOp.getOpcode() != ISD::UNDEF && 8931 FoldOp.getOpcode() != ISD::Constant && 8932 FoldOp.getOpcode() != ISD::ConstantFP) 8933 break; 8934 Ops.push_back(FoldOp); 8935 AddToWorkList(FoldOp.getNode()); 8936 } 8937 8938 if (Ops.size() == LHS.getNumOperands()) 8939 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8940 LHS.getValueType(), &Ops[0], Ops.size()); 8941 } 8942 8943 return SDValue(); 8944} 8945 8946/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 8947SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 8948 // After legalize, the target may be depending on adds and other 8949 // binary ops to provide legal ways to construct constants or other 8950 // things. Simplifying them may result in a loss of legality. 8951 if (LegalOperations) return SDValue(); 8952 8953 assert(N->getValueType(0).isVector() && 8954 "SimplifyVUnaryOp only works on vectors!"); 8955 8956 SDValue N0 = N->getOperand(0); 8957 8958 if (N0.getOpcode() != ISD::BUILD_VECTOR) 8959 return SDValue(); 8960 8961 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 8962 SmallVector<SDValue, 8> Ops; 8963 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 8964 SDValue Op = N0.getOperand(i); 8965 if (Op.getOpcode() != ISD::UNDEF && 8966 Op.getOpcode() != ISD::ConstantFP) 8967 break; 8968 EVT EltVT = Op.getValueType(); 8969 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op); 8970 if (FoldOp.getOpcode() != ISD::UNDEF && 8971 FoldOp.getOpcode() != ISD::ConstantFP) 8972 break; 8973 Ops.push_back(FoldOp); 8974 AddToWorkList(FoldOp.getNode()); 8975 } 8976 8977 if (Ops.size() != N0.getNumOperands()) 8978 return SDValue(); 8979 8980 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8981 N0.getValueType(), &Ops[0], Ops.size()); 8982} 8983 8984SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 8985 SDValue N1, SDValue N2){ 8986 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 8987 8988 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 8989 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 8990 8991 // If we got a simplified select_cc node back from SimplifySelectCC, then 8992 // break it down into a new SETCC node, and a new SELECT node, and then return 8993 // the SELECT node, since we were called with a SELECT node. 8994 if (SCC.getNode()) { 8995 // Check to see if we got a select_cc back (to turn into setcc/select). 8996 // Otherwise, just return whatever node we got back, like fabs. 8997 if (SCC.getOpcode() == ISD::SELECT_CC) { 8998 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 8999 N0.getValueType(), 9000 SCC.getOperand(0), SCC.getOperand(1), 9001 SCC.getOperand(4)); 9002 AddToWorkList(SETCC.getNode()); 9003 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 9004 SCC.getOperand(2), SCC.getOperand(3), SETCC); 9005 } 9006 9007 return SCC; 9008 } 9009 return SDValue(); 9010} 9011 9012/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 9013/// are the two values being selected between, see if we can simplify the 9014/// select. Callers of this should assume that TheSelect is deleted if this 9015/// returns true. As such, they should return the appropriate thing (e.g. the 9016/// node) back to the top-level of the DAG combiner loop to avoid it being 9017/// looked at. 9018bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 9019 SDValue RHS) { 9020 9021 // Cannot simplify select with vector condition 9022 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 9023 9024 // If this is a select from two identical things, try to pull the operation 9025 // through the select. 9026 if (LHS.getOpcode() != RHS.getOpcode() || 9027 !LHS.hasOneUse() || !RHS.hasOneUse()) 9028 return false; 9029 9030 // If this is a load and the token chain is identical, replace the select 9031 // of two loads with a load through a select of the address to load from. 9032 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 9033 // constants have been dropped into the constant pool. 9034 if (LHS.getOpcode() == ISD::LOAD) { 9035 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 9036 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 9037 9038 // Token chains must be identical. 9039 if (LHS.getOperand(0) != RHS.getOperand(0) || 9040 // Do not let this transformation reduce the number of volatile loads. 9041 LLD->isVolatile() || RLD->isVolatile() || 9042 // If this is an EXTLOAD, the VT's must match. 9043 LLD->getMemoryVT() != RLD->getMemoryVT() || 9044 // If this is an EXTLOAD, the kind of extension must match. 9045 (LLD->getExtensionType() != RLD->getExtensionType() && 9046 // The only exception is if one of the extensions is anyext. 9047 LLD->getExtensionType() != ISD::EXTLOAD && 9048 RLD->getExtensionType() != ISD::EXTLOAD) || 9049 // FIXME: this discards src value information. This is 9050 // over-conservative. It would be beneficial to be able to remember 9051 // both potential memory locations. Since we are discarding 9052 // src value info, don't do the transformation if the memory 9053 // locations are not in the default address space. 9054 LLD->getPointerInfo().getAddrSpace() != 0 || 9055 RLD->getPointerInfo().getAddrSpace() != 0) 9056 return false; 9057 9058 // Check that the select condition doesn't reach either load. If so, 9059 // folding this will induce a cycle into the DAG. If not, this is safe to 9060 // xform, so create a select of the addresses. 9061 SDValue Addr; 9062 if (TheSelect->getOpcode() == ISD::SELECT) { 9063 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 9064 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 9065 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 9066 return false; 9067 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 9068 LLD->getBasePtr().getValueType(), 9069 TheSelect->getOperand(0), LLD->getBasePtr(), 9070 RLD->getBasePtr()); 9071 } else { // Otherwise SELECT_CC 9072 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 9073 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 9074 9075 if ((LLD->hasAnyUseOfValue(1) && 9076 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 9077 (RLD->hasAnyUseOfValue(1) && 9078 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 9079 return false; 9080 9081 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 9082 LLD->getBasePtr().getValueType(), 9083 TheSelect->getOperand(0), 9084 TheSelect->getOperand(1), 9085 LLD->getBasePtr(), RLD->getBasePtr(), 9086 TheSelect->getOperand(4)); 9087 } 9088 9089 SDValue Load; 9090 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 9091 Load = DAG.getLoad(TheSelect->getValueType(0), 9092 TheSelect->getDebugLoc(), 9093 // FIXME: Discards pointer info. 9094 LLD->getChain(), Addr, MachinePointerInfo(), 9095 LLD->isVolatile(), LLD->isNonTemporal(), 9096 LLD->isInvariant(), LLD->getAlignment()); 9097 } else { 9098 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 9099 RLD->getExtensionType() : LLD->getExtensionType(), 9100 TheSelect->getDebugLoc(), 9101 TheSelect->getValueType(0), 9102 // FIXME: Discards pointer info. 9103 LLD->getChain(), Addr, MachinePointerInfo(), 9104 LLD->getMemoryVT(), LLD->isVolatile(), 9105 LLD->isNonTemporal(), LLD->getAlignment()); 9106 } 9107 9108 // Users of the select now use the result of the load. 9109 CombineTo(TheSelect, Load); 9110 9111 // Users of the old loads now use the new load's chain. We know the 9112 // old-load value is dead now. 9113 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 9114 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 9115 return true; 9116 } 9117 9118 return false; 9119} 9120 9121/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 9122/// where 'cond' is the comparison specified by CC. 9123SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 9124 SDValue N2, SDValue N3, 9125 ISD::CondCode CC, bool NotExtCompare) { 9126 // (x ? y : y) -> y. 9127 if (N2 == N3) return N2; 9128 9129 EVT VT = N2.getValueType(); 9130 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 9131 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 9132 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 9133 9134 // Determine if the condition we're dealing with is constant 9135 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 9136 N0, N1, CC, DL, false); 9137 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 9138 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 9139 9140 // fold select_cc true, x, y -> x 9141 if (SCCC && !SCCC->isNullValue()) 9142 return N2; 9143 // fold select_cc false, x, y -> y 9144 if (SCCC && SCCC->isNullValue()) 9145 return N3; 9146 9147 // Check to see if we can simplify the select into an fabs node 9148 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 9149 // Allow either -0.0 or 0.0 9150 if (CFP->getValueAPF().isZero()) { 9151 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 9152 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 9153 N0 == N2 && N3.getOpcode() == ISD::FNEG && 9154 N2 == N3.getOperand(0)) 9155 return DAG.getNode(ISD::FABS, DL, VT, N0); 9156 9157 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 9158 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 9159 N0 == N3 && N2.getOpcode() == ISD::FNEG && 9160 N2.getOperand(0) == N3) 9161 return DAG.getNode(ISD::FABS, DL, VT, N3); 9162 } 9163 } 9164 9165 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 9166 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 9167 // in it. This is a win when the constant is not otherwise available because 9168 // it replaces two constant pool loads with one. We only do this if the FP 9169 // type is known to be legal, because if it isn't, then we are before legalize 9170 // types an we want the other legalization to happen first (e.g. to avoid 9171 // messing with soft float) and if the ConstantFP is not legal, because if 9172 // it is legal, we may not need to store the FP constant in a constant pool. 9173 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 9174 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 9175 if (TLI.isTypeLegal(N2.getValueType()) && 9176 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 9177 TargetLowering::Legal) && 9178 // If both constants have multiple uses, then we won't need to do an 9179 // extra load, they are likely around in registers for other users. 9180 (TV->hasOneUse() || FV->hasOneUse())) { 9181 Constant *Elts[] = { 9182 const_cast<ConstantFP*>(FV->getConstantFPValue()), 9183 const_cast<ConstantFP*>(TV->getConstantFPValue()) 9184 }; 9185 Type *FPTy = Elts[0]->getType(); 9186 const DataLayout &TD = *TLI.getDataLayout(); 9187 9188 // Create a ConstantArray of the two constants. 9189 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 9190 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 9191 TD.getPrefTypeAlignment(FPTy)); 9192 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 9193 9194 // Get the offsets to the 0 and 1 element of the array so that we can 9195 // select between them. 9196 SDValue Zero = DAG.getIntPtrConstant(0); 9197 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 9198 SDValue One = DAG.getIntPtrConstant(EltSize); 9199 9200 SDValue Cond = DAG.getSetCC(DL, 9201 TLI.getSetCCResultType(N0.getValueType()), 9202 N0, N1, CC); 9203 AddToWorkList(Cond.getNode()); 9204 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 9205 Cond, One, Zero); 9206 AddToWorkList(CstOffset.getNode()); 9207 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 9208 CstOffset); 9209 AddToWorkList(CPIdx.getNode()); 9210 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 9211 MachinePointerInfo::getConstantPool(), false, 9212 false, false, Alignment); 9213 9214 } 9215 } 9216 9217 // Check to see if we can perform the "gzip trick", transforming 9218 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 9219 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 9220 (N1C->isNullValue() || // (a < 0) ? b : 0 9221 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 9222 EVT XType = N0.getValueType(); 9223 EVT AType = N2.getValueType(); 9224 if (XType.bitsGE(AType)) { 9225 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 9226 // single-bit constant. 9227 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 9228 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 9229 ShCtV = XType.getSizeInBits()-ShCtV-1; 9230 SDValue ShCt = DAG.getConstant(ShCtV, 9231 getShiftAmountTy(N0.getValueType())); 9232 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 9233 XType, N0, ShCt); 9234 AddToWorkList(Shift.getNode()); 9235 9236 if (XType.bitsGT(AType)) { 9237 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9238 AddToWorkList(Shift.getNode()); 9239 } 9240 9241 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9242 } 9243 9244 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 9245 XType, N0, 9246 DAG.getConstant(XType.getSizeInBits()-1, 9247 getShiftAmountTy(N0.getValueType()))); 9248 AddToWorkList(Shift.getNode()); 9249 9250 if (XType.bitsGT(AType)) { 9251 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9252 AddToWorkList(Shift.getNode()); 9253 } 9254 9255 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9256 } 9257 } 9258 9259 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 9260 // where y is has a single bit set. 9261 // A plaintext description would be, we can turn the SELECT_CC into an AND 9262 // when the condition can be materialized as an all-ones register. Any 9263 // single bit-test can be materialized as an all-ones register with 9264 // shift-left and shift-right-arith. 9265 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 9266 N0->getValueType(0) == VT && 9267 N1C && N1C->isNullValue() && 9268 N2C && N2C->isNullValue()) { 9269 SDValue AndLHS = N0->getOperand(0); 9270 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 9271 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 9272 // Shift the tested bit over the sign bit. 9273 APInt AndMask = ConstAndRHS->getAPIntValue(); 9274 SDValue ShlAmt = 9275 DAG.getConstant(AndMask.countLeadingZeros(), 9276 getShiftAmountTy(AndLHS.getValueType())); 9277 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 9278 9279 // Now arithmetic right shift it all the way over, so the result is either 9280 // all-ones, or zero. 9281 SDValue ShrAmt = 9282 DAG.getConstant(AndMask.getBitWidth()-1, 9283 getShiftAmountTy(Shl.getValueType())); 9284 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 9285 9286 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 9287 } 9288 } 9289 9290 // fold select C, 16, 0 -> shl C, 4 9291 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 9292 TLI.getBooleanContents(N0.getValueType().isVector()) == 9293 TargetLowering::ZeroOrOneBooleanContent) { 9294 9295 // If the caller doesn't want us to simplify this into a zext of a compare, 9296 // don't do it. 9297 if (NotExtCompare && N2C->getAPIntValue() == 1) 9298 return SDValue(); 9299 9300 // Get a SetCC of the condition 9301 // FIXME: Should probably make sure that setcc is legal if we ever have a 9302 // target where it isn't. 9303 SDValue Temp, SCC; 9304 // cast from setcc result type to select result type 9305 if (LegalTypes) { 9306 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 9307 N0, N1, CC); 9308 if (N2.getValueType().bitsLT(SCC.getValueType())) 9309 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 9310 else 9311 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9312 N2.getValueType(), SCC); 9313 } else { 9314 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 9315 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9316 N2.getValueType(), SCC); 9317 } 9318 9319 AddToWorkList(SCC.getNode()); 9320 AddToWorkList(Temp.getNode()); 9321 9322 if (N2C->getAPIntValue() == 1) 9323 return Temp; 9324 9325 // shl setcc result by log2 n2c 9326 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 9327 DAG.getConstant(N2C->getAPIntValue().logBase2(), 9328 getShiftAmountTy(Temp.getValueType()))); 9329 } 9330 9331 // Check to see if this is the equivalent of setcc 9332 // FIXME: Turn all of these into setcc if setcc if setcc is legal 9333 // otherwise, go ahead with the folds. 9334 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 9335 EVT XType = N0.getValueType(); 9336 if (!LegalOperations || 9337 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 9338 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 9339 if (Res.getValueType() != VT) 9340 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 9341 return Res; 9342 } 9343 9344 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 9345 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 9346 (!LegalOperations || 9347 TLI.isOperationLegal(ISD::CTLZ, XType))) { 9348 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 9349 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 9350 DAG.getConstant(Log2_32(XType.getSizeInBits()), 9351 getShiftAmountTy(Ctlz.getValueType()))); 9352 } 9353 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 9354 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 9355 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 9356 XType, DAG.getConstant(0, XType), N0); 9357 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 9358 return DAG.getNode(ISD::SRL, DL, XType, 9359 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 9360 DAG.getConstant(XType.getSizeInBits()-1, 9361 getShiftAmountTy(XType))); 9362 } 9363 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 9364 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 9365 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 9366 DAG.getConstant(XType.getSizeInBits()-1, 9367 getShiftAmountTy(N0.getValueType()))); 9368 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 9369 } 9370 } 9371 9372 // Check to see if this is an integer abs. 9373 // select_cc setg[te] X, 0, X, -X -> 9374 // select_cc setgt X, -1, X, -X -> 9375 // select_cc setl[te] X, 0, -X, X -> 9376 // select_cc setlt X, 1, -X, X -> 9377 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 9378 if (N1C) { 9379 ConstantSDNode *SubC = NULL; 9380 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 9381 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 9382 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 9383 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 9384 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 9385 (N1C->isOne() && CC == ISD::SETLT)) && 9386 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 9387 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 9388 9389 EVT XType = N0.getValueType(); 9390 if (SubC && SubC->isNullValue() && XType.isInteger()) { 9391 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 9392 N0, 9393 DAG.getConstant(XType.getSizeInBits()-1, 9394 getShiftAmountTy(N0.getValueType()))); 9395 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 9396 XType, N0, Shift); 9397 AddToWorkList(Shift.getNode()); 9398 AddToWorkList(Add.getNode()); 9399 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 9400 } 9401 } 9402 9403 return SDValue(); 9404} 9405 9406/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 9407SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 9408 SDValue N1, ISD::CondCode Cond, 9409 DebugLoc DL, bool foldBooleans) { 9410 TargetLowering::DAGCombinerInfo 9411 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 9412 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 9413} 9414 9415/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 9416/// return a DAG expression to select that will generate the same value by 9417/// multiplying by a magic number. See: 9418/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9419SDValue DAGCombiner::BuildSDIV(SDNode *N) { 9420 std::vector<SDNode*> Built; 9421 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 9422 9423 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9424 ii != ee; ++ii) 9425 AddToWorkList(*ii); 9426 return S; 9427} 9428 9429/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 9430/// return a DAG expression to select that will generate the same value by 9431/// multiplying by a magic number. See: 9432/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9433SDValue DAGCombiner::BuildUDIV(SDNode *N) { 9434 std::vector<SDNode*> Built; 9435 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 9436 9437 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9438 ii != ee; ++ii) 9439 AddToWorkList(*ii); 9440 return S; 9441} 9442 9443/// FindBaseOffset - Return true if base is a frame index, which is known not 9444// to alias with anything but itself. Provides base object and offset as 9445// results. 9446static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 9447 const GlobalValue *&GV, const void *&CV) { 9448 // Assume it is a primitive operation. 9449 Base = Ptr; Offset = 0; GV = 0; CV = 0; 9450 9451 // If it's an adding a simple constant then integrate the offset. 9452 if (Base.getOpcode() == ISD::ADD) { 9453 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 9454 Base = Base.getOperand(0); 9455 Offset += C->getZExtValue(); 9456 } 9457 } 9458 9459 // Return the underlying GlobalValue, and update the Offset. Return false 9460 // for GlobalAddressSDNode since the same GlobalAddress may be represented 9461 // by multiple nodes with different offsets. 9462 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 9463 GV = G->getGlobal(); 9464 Offset += G->getOffset(); 9465 return false; 9466 } 9467 9468 // Return the underlying Constant value, and update the Offset. Return false 9469 // for ConstantSDNodes since the same constant pool entry may be represented 9470 // by multiple nodes with different offsets. 9471 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 9472 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 9473 : (const void *)C->getConstVal(); 9474 Offset += C->getOffset(); 9475 return false; 9476 } 9477 // If it's any of the following then it can't alias with anything but itself. 9478 return isa<FrameIndexSDNode>(Base); 9479} 9480 9481/// isAlias - Return true if there is any possibility that the two addresses 9482/// overlap. 9483bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 9484 const Value *SrcValue1, int SrcValueOffset1, 9485 unsigned SrcValueAlign1, 9486 const MDNode *TBAAInfo1, 9487 SDValue Ptr2, int64_t Size2, 9488 const Value *SrcValue2, int SrcValueOffset2, 9489 unsigned SrcValueAlign2, 9490 const MDNode *TBAAInfo2) const { 9491 // If they are the same then they must be aliases. 9492 if (Ptr1 == Ptr2) return true; 9493 9494 // Gather base node and offset information. 9495 SDValue Base1, Base2; 9496 int64_t Offset1, Offset2; 9497 const GlobalValue *GV1, *GV2; 9498 const void *CV1, *CV2; 9499 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 9500 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 9501 9502 // If they have a same base address then check to see if they overlap. 9503 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 9504 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9505 9506 // It is possible for different frame indices to alias each other, mostly 9507 // when tail call optimization reuses return address slots for arguments. 9508 // To catch this case, look up the actual index of frame indices to compute 9509 // the real alias relationship. 9510 if (isFrameIndex1 && isFrameIndex2) { 9511 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9512 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 9513 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 9514 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9515 } 9516 9517 // Otherwise, if we know what the bases are, and they aren't identical, then 9518 // we know they cannot alias. 9519 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 9520 return false; 9521 9522 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 9523 // compared to the size and offset of the access, we may be able to prove they 9524 // do not alias. This check is conservative for now to catch cases created by 9525 // splitting vector types. 9526 if ((SrcValueAlign1 == SrcValueAlign2) && 9527 (SrcValueOffset1 != SrcValueOffset2) && 9528 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 9529 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 9530 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 9531 9532 // There is no overlap between these relatively aligned accesses of similar 9533 // size, return no alias. 9534 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 9535 return false; 9536 } 9537 9538 if (CombinerGlobalAA) { 9539 // Use alias analysis information. 9540 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 9541 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 9542 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 9543 AliasAnalysis::AliasResult AAResult = 9544 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 9545 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 9546 if (AAResult == AliasAnalysis::NoAlias) 9547 return false; 9548 } 9549 9550 // Otherwise we have to assume they alias. 9551 return true; 9552} 9553 9554/// FindAliasInfo - Extracts the relevant alias information from the memory 9555/// node. Returns true if the operand was a load. 9556bool DAGCombiner::FindAliasInfo(SDNode *N, 9557 SDValue &Ptr, int64_t &Size, 9558 const Value *&SrcValue, 9559 int &SrcValueOffset, 9560 unsigned &SrcValueAlign, 9561 const MDNode *&TBAAInfo) const { 9562 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 9563 9564 Ptr = LS->getBasePtr(); 9565 Size = LS->getMemoryVT().getSizeInBits() >> 3; 9566 SrcValue = LS->getSrcValue(); 9567 SrcValueOffset = LS->getSrcValueOffset(); 9568 SrcValueAlign = LS->getOriginalAlignment(); 9569 TBAAInfo = LS->getTBAAInfo(); 9570 return isa<LoadSDNode>(LS); 9571} 9572 9573/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 9574/// looking for aliasing nodes and adding them to the Aliases vector. 9575void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 9576 SmallVector<SDValue, 8> &Aliases) { 9577 SmallVector<SDValue, 8> Chains; // List of chains to visit. 9578 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 9579 9580 // Get alias information for node. 9581 SDValue Ptr; 9582 int64_t Size; 9583 const Value *SrcValue; 9584 int SrcValueOffset; 9585 unsigned SrcValueAlign; 9586 const MDNode *SrcTBAAInfo; 9587 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 9588 SrcValueAlign, SrcTBAAInfo); 9589 9590 // Starting off. 9591 Chains.push_back(OriginalChain); 9592 unsigned Depth = 0; 9593 9594 // Look at each chain and determine if it is an alias. If so, add it to the 9595 // aliases list. If not, then continue up the chain looking for the next 9596 // candidate. 9597 while (!Chains.empty()) { 9598 SDValue Chain = Chains.back(); 9599 Chains.pop_back(); 9600 9601 // For TokenFactor nodes, look at each operand and only continue up the 9602 // chain until we find two aliases. If we've seen two aliases, assume we'll 9603 // find more and revert to original chain since the xform is unlikely to be 9604 // profitable. 9605 // 9606 // FIXME: The depth check could be made to return the last non-aliasing 9607 // chain we found before we hit a tokenfactor rather than the original 9608 // chain. 9609 if (Depth > 6 || Aliases.size() == 2) { 9610 Aliases.clear(); 9611 Aliases.push_back(OriginalChain); 9612 break; 9613 } 9614 9615 // Don't bother if we've been before. 9616 if (!Visited.insert(Chain.getNode())) 9617 continue; 9618 9619 switch (Chain.getOpcode()) { 9620 case ISD::EntryToken: 9621 // Entry token is ideal chain operand, but handled in FindBetterChain. 9622 break; 9623 9624 case ISD::LOAD: 9625 case ISD::STORE: { 9626 // Get alias information for Chain. 9627 SDValue OpPtr; 9628 int64_t OpSize; 9629 const Value *OpSrcValue; 9630 int OpSrcValueOffset; 9631 unsigned OpSrcValueAlign; 9632 const MDNode *OpSrcTBAAInfo; 9633 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 9634 OpSrcValue, OpSrcValueOffset, 9635 OpSrcValueAlign, 9636 OpSrcTBAAInfo); 9637 9638 // If chain is alias then stop here. 9639 if (!(IsLoad && IsOpLoad) && 9640 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 9641 SrcTBAAInfo, 9642 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 9643 OpSrcValueAlign, OpSrcTBAAInfo)) { 9644 Aliases.push_back(Chain); 9645 } else { 9646 // Look further up the chain. 9647 Chains.push_back(Chain.getOperand(0)); 9648 ++Depth; 9649 } 9650 break; 9651 } 9652 9653 case ISD::TokenFactor: 9654 // We have to check each of the operands of the token factor for "small" 9655 // token factors, so we queue them up. Adding the operands to the queue 9656 // (stack) in reverse order maintains the original order and increases the 9657 // likelihood that getNode will find a matching token factor (CSE.) 9658 if (Chain.getNumOperands() > 16) { 9659 Aliases.push_back(Chain); 9660 break; 9661 } 9662 for (unsigned n = Chain.getNumOperands(); n;) 9663 Chains.push_back(Chain.getOperand(--n)); 9664 ++Depth; 9665 break; 9666 9667 default: 9668 // For all other instructions we will just have to take what we can get. 9669 Aliases.push_back(Chain); 9670 break; 9671 } 9672 } 9673} 9674 9675/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 9676/// for a better chain (aliasing node.) 9677SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 9678 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 9679 9680 // Accumulate all the aliases to this node. 9681 GatherAllAliases(N, OldChain, Aliases); 9682 9683 // If no operands then chain to entry token. 9684 if (Aliases.size() == 0) 9685 return DAG.getEntryNode(); 9686 9687 // If a single operand then chain to it. We don't need to revisit it. 9688 if (Aliases.size() == 1) 9689 return Aliases[0]; 9690 9691 // Construct a custom tailored token factor. 9692 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 9693 &Aliases[0], Aliases.size()); 9694} 9695 9696// SelectionDAG::Combine - This is the entry point for the file. 9697// 9698void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 9699 CodeGenOpt::Level OptLevel) { 9700 /// run - This is the main entry point to this class. 9701 /// 9702 DAGCombiner(*this, AA, OptLevel).Run(Level); 9703} 9704