DAGCombiner.cpp revision 29f60f359b59032108cdabcde91217b6784c4e13
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue visitSHL(SDNode *N); 198 SDValue visitSRA(SDNode *N); 199 SDValue visitSRL(SDNode *N); 200 SDValue visitCTLZ(SDNode *N); 201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 202 SDValue visitCTTZ(SDNode *N); 203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 204 SDValue visitCTPOP(SDNode *N); 205 SDValue visitSELECT(SDNode *N); 206 SDValue visitSELECT_CC(SDNode *N); 207 SDValue visitSETCC(SDNode *N); 208 SDValue visitSIGN_EXTEND(SDNode *N); 209 SDValue visitZERO_EXTEND(SDNode *N); 210 SDValue visitANY_EXTEND(SDNode *N); 211 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 212 SDValue visitTRUNCATE(SDNode *N); 213 SDValue visitBITCAST(SDNode *N); 214 SDValue visitBUILD_PAIR(SDNode *N); 215 SDValue visitFADD(SDNode *N); 216 SDValue visitFSUB(SDNode *N); 217 SDValue visitFMUL(SDNode *N); 218 SDValue visitFDIV(SDNode *N); 219 SDValue visitFREM(SDNode *N); 220 SDValue visitFCOPYSIGN(SDNode *N); 221 SDValue visitSINT_TO_FP(SDNode *N); 222 SDValue visitUINT_TO_FP(SDNode *N); 223 SDValue visitFP_TO_SINT(SDNode *N); 224 SDValue visitFP_TO_UINT(SDNode *N); 225 SDValue visitFP_ROUND(SDNode *N); 226 SDValue visitFP_ROUND_INREG(SDNode *N); 227 SDValue visitFP_EXTEND(SDNode *N); 228 SDValue visitFNEG(SDNode *N); 229 SDValue visitFABS(SDNode *N); 230 SDValue visitBRCOND(SDNode *N); 231 SDValue visitBR_CC(SDNode *N); 232 SDValue visitLOAD(SDNode *N); 233 SDValue visitSTORE(SDNode *N); 234 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 235 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 236 SDValue visitBUILD_VECTOR(SDNode *N); 237 SDValue visitCONCAT_VECTORS(SDNode *N); 238 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 239 SDValue visitVECTOR_SHUFFLE(SDNode *N); 240 SDValue visitMEMBARRIER(SDNode *N); 241 242 SDValue XformToShuffleWithZero(SDNode *N); 243 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 244 245 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 246 247 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 248 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 249 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 250 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 251 SDValue N3, ISD::CondCode CC, 252 bool NotExtCompare = false); 253 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 254 DebugLoc DL, bool foldBooleans = true); 255 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 256 unsigned HiOp); 257 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 258 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 259 SDValue BuildSDIV(SDNode *N); 260 SDValue BuildUDIV(SDNode *N); 261 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 262 bool DemandHighBits = true); 263 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 264 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 265 SDValue ReduceLoadWidth(SDNode *N); 266 SDValue ReduceLoadOpStoreWidth(SDNode *N); 267 SDValue TransformFPLoadStorePair(SDNode *N); 268 269 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 270 271 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 272 /// looking for aliasing nodes and adding them to the Aliases vector. 273 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 274 SmallVector<SDValue, 8> &Aliases); 275 276 /// isAlias - Return true if there is any possibility that the two addresses 277 /// overlap. 278 bool isAlias(SDValue Ptr1, int64_t Size1, 279 const Value *SrcValue1, int SrcValueOffset1, 280 unsigned SrcValueAlign1, 281 const MDNode *TBAAInfo1, 282 SDValue Ptr2, int64_t Size2, 283 const Value *SrcValue2, int SrcValueOffset2, 284 unsigned SrcValueAlign2, 285 const MDNode *TBAAInfo2) const; 286 287 /// FindAliasInfo - Extracts the relevant alias information from the memory 288 /// node. Returns true if the operand was a load. 289 bool FindAliasInfo(SDNode *N, 290 SDValue &Ptr, int64_t &Size, 291 const Value *&SrcValue, int &SrcValueOffset, 292 unsigned &SrcValueAlignment, 293 const MDNode *&TBAAInfo) const; 294 295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 296 /// looking for a better chain (aliasing node.) 297 SDValue FindBetterChain(SDNode *N, SDValue Chain); 298 299 public: 300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 301 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 302 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 303 304 /// Run - runs the dag combiner on all nodes in the work list 305 void Run(CombineLevel AtLevel); 306 307 SelectionDAG &getDAG() const { return DAG; } 308 309 /// getShiftAmountTy - Returns a type large enough to hold any valid 310 /// shift amount - before type legalization these can be huge. 311 EVT getShiftAmountTy(EVT LHSTy) { 312 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 313 } 314 315 /// isTypeLegal - This method returns true if we are running before type 316 /// legalization or if the specified VT is legal. 317 bool isTypeLegal(const EVT &VT) { 318 if (!LegalTypes) return true; 319 return TLI.isTypeLegal(VT); 320 } 321 }; 322} 323 324 325namespace { 326/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 327/// nodes from the worklist. 328class WorkListRemover : public SelectionDAG::DAGUpdateListener { 329 DAGCombiner &DC; 330public: 331 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 332 333 virtual void NodeDeleted(SDNode *N, SDNode *E) { 334 DC.removeFromWorkList(N); 335 } 336 337 virtual void NodeUpdated(SDNode *N) { 338 // Ignore updates. 339 } 340}; 341} 342 343//===----------------------------------------------------------------------===// 344// TargetLowering::DAGCombinerInfo implementation 345//===----------------------------------------------------------------------===// 346 347void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 348 ((DAGCombiner*)DC)->AddToWorkList(N); 349} 350 351void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 352 ((DAGCombiner*)DC)->removeFromWorkList(N); 353} 354 355SDValue TargetLowering::DAGCombinerInfo:: 356CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 357 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 358} 359 360SDValue TargetLowering::DAGCombinerInfo:: 361CombineTo(SDNode *N, SDValue Res, bool AddTo) { 362 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 363} 364 365 366SDValue TargetLowering::DAGCombinerInfo:: 367CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 368 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 369} 370 371void TargetLowering::DAGCombinerInfo:: 372CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 373 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 374} 375 376//===----------------------------------------------------------------------===// 377// Helper Functions 378//===----------------------------------------------------------------------===// 379 380/// isNegatibleForFree - Return 1 if we can compute the negated form of the 381/// specified expression for the same cost as the expression itself, or 2 if we 382/// can compute the negated form more cheaply than the expression itself. 383static char isNegatibleForFree(SDValue Op, bool LegalOperations, 384 const TargetLowering &TLI, 385 const TargetOptions *Options, 386 unsigned Depth = 0) { 387 // No compile time optimizations on this type. 388 if (Op.getValueType() == MVT::ppcf128) 389 return 0; 390 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return 2; 393 394 // Don't allow anything with multiple uses. 395 if (!Op.hasOneUse()) return 0; 396 397 // Don't recurse exponentially. 398 if (Depth > 6) return 0; 399 400 switch (Op.getOpcode()) { 401 default: return false; 402 case ISD::ConstantFP: 403 // Don't invert constant FP values after legalize. The negated constant 404 // isn't necessarily legal. 405 return LegalOperations ? 0 : 1; 406 case ISD::FADD: 407 // FIXME: determine better conditions for this xform. 408 if (!Options->UnsafeFPMath) return 0; 409 410 // After operation legalization, it might not be legal to create new FSUBs. 411 if (LegalOperations && 412 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 413 return 0; 414 415 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 416 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 417 Options, Depth + 1)) 418 return V; 419 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 420 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 421 Depth + 1); 422 case ISD::FSUB: 423 // We can't turn -(A-B) into B-A when we honor signed zeros. 424 if (!Options->UnsafeFPMath) return 0; 425 426 // fold (fneg (fsub A, B)) -> (fsub B, A) 427 return 1; 428 429 case ISD::FMUL: 430 case ISD::FDIV: 431 if (Options->HonorSignDependentRoundingFPMath()) return 0; 432 433 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 434 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 435 Options, Depth + 1)) 436 return V; 437 438 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 439 Depth + 1); 440 441 case ISD::FP_EXTEND: 442 case ISD::FP_ROUND: 443 case ISD::FSIN: 444 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 445 Depth + 1); 446 } 447} 448 449/// GetNegatedExpression - If isNegatibleForFree returns true, this function 450/// returns the newly negated expression. 451static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 452 bool LegalOperations, unsigned Depth = 0) { 453 // fneg is removable even if it has multiple uses. 454 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 455 456 // Don't allow anything with multiple uses. 457 assert(Op.hasOneUse() && "Unknown reuse!"); 458 459 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 460 switch (Op.getOpcode()) { 461 default: llvm_unreachable("Unknown code"); 462 case ISD::ConstantFP: { 463 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 464 V.changeSign(); 465 return DAG.getConstantFP(V, Op.getValueType()); 466 } 467 case ISD::FADD: 468 // FIXME: determine better conditions for this xform. 469 assert(DAG.getTarget().Options.UnsafeFPMath); 470 471 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 472 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 473 DAG.getTargetLoweringInfo(), 474 &DAG.getTarget().Options, Depth+1)) 475 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 476 GetNegatedExpression(Op.getOperand(0), DAG, 477 LegalOperations, Depth+1), 478 Op.getOperand(1)); 479 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 480 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 481 GetNegatedExpression(Op.getOperand(1), DAG, 482 LegalOperations, Depth+1), 483 Op.getOperand(0)); 484 case ISD::FSUB: 485 // We can't turn -(A-B) into B-A when we honor signed zeros. 486 assert(DAG.getTarget().Options.UnsafeFPMath); 487 488 // fold (fneg (fsub 0, B)) -> B 489 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 490 if (N0CFP->getValueAPF().isZero()) 491 return Op.getOperand(1); 492 493 // fold (fneg (fsub A, B)) -> (fsub B, A) 494 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 495 Op.getOperand(1), Op.getOperand(0)); 496 497 case ISD::FMUL: 498 case ISD::FDIV: 499 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 500 501 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 502 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 503 DAG.getTargetLoweringInfo(), 504 &DAG.getTarget().Options, Depth+1)) 505 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 506 GetNegatedExpression(Op.getOperand(0), DAG, 507 LegalOperations, Depth+1), 508 Op.getOperand(1)); 509 510 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 511 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 512 Op.getOperand(0), 513 GetNegatedExpression(Op.getOperand(1), DAG, 514 LegalOperations, Depth+1)); 515 516 case ISD::FP_EXTEND: 517 case ISD::FSIN: 518 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 519 GetNegatedExpression(Op.getOperand(0), DAG, 520 LegalOperations, Depth+1)); 521 case ISD::FP_ROUND: 522 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 523 GetNegatedExpression(Op.getOperand(0), DAG, 524 LegalOperations, Depth+1), 525 Op.getOperand(1)); 526 } 527} 528 529 530// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 531// that selects between the values 1 and 0, making it equivalent to a setcc. 532// Also, set the incoming LHS, RHS, and CC references to the appropriate 533// nodes based on the type of node we are checking. This simplifies life a 534// bit for the callers. 535static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 536 SDValue &CC) { 537 if (N.getOpcode() == ISD::SETCC) { 538 LHS = N.getOperand(0); 539 RHS = N.getOperand(1); 540 CC = N.getOperand(2); 541 return true; 542 } 543 if (N.getOpcode() == ISD::SELECT_CC && 544 N.getOperand(2).getOpcode() == ISD::Constant && 545 N.getOperand(3).getOpcode() == ISD::Constant && 546 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 547 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 548 LHS = N.getOperand(0); 549 RHS = N.getOperand(1); 550 CC = N.getOperand(4); 551 return true; 552 } 553 return false; 554} 555 556// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 557// one use. If this is true, it allows the users to invert the operation for 558// free when it is profitable to do so. 559static bool isOneUseSetCC(SDValue N) { 560 SDValue N0, N1, N2; 561 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 562 return true; 563 return false; 564} 565 566SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 567 SDValue N0, SDValue N1) { 568 EVT VT = N0.getValueType(); 569 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 570 if (isa<ConstantSDNode>(N1)) { 571 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 572 SDValue OpNode = 573 DAG.FoldConstantArithmetic(Opc, VT, 574 cast<ConstantSDNode>(N0.getOperand(1)), 575 cast<ConstantSDNode>(N1)); 576 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 577 } 578 if (N0.hasOneUse()) { 579 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 580 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 581 N0.getOperand(0), N1); 582 AddToWorkList(OpNode.getNode()); 583 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 584 } 585 } 586 587 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 588 if (isa<ConstantSDNode>(N0)) { 589 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 590 SDValue OpNode = 591 DAG.FoldConstantArithmetic(Opc, VT, 592 cast<ConstantSDNode>(N1.getOperand(1)), 593 cast<ConstantSDNode>(N0)); 594 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 595 } 596 if (N1.hasOneUse()) { 597 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 598 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 599 N1.getOperand(0), N0); 600 AddToWorkList(OpNode.getNode()); 601 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 602 } 603 } 604 605 return SDValue(); 606} 607 608SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 609 bool AddTo) { 610 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 611 ++NodesCombined; 612 DEBUG(dbgs() << "\nReplacing.1 "; 613 N->dump(&DAG); 614 dbgs() << "\nWith: "; 615 To[0].getNode()->dump(&DAG); 616 dbgs() << " and " << NumTo-1 << " other values\n"; 617 for (unsigned i = 0, e = NumTo; i != e; ++i) 618 assert((!To[i].getNode() || 619 N->getValueType(i) == To[i].getValueType()) && 620 "Cannot combine value to value of different type!")); 621 WorkListRemover DeadNodes(*this); 622 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 623 624 if (AddTo) { 625 // Push the new nodes and any users onto the worklist 626 for (unsigned i = 0, e = NumTo; i != e; ++i) { 627 if (To[i].getNode()) { 628 AddToWorkList(To[i].getNode()); 629 AddUsersToWorkList(To[i].getNode()); 630 } 631 } 632 } 633 634 // Finally, if the node is now dead, remove it from the graph. The node 635 // may not be dead if the replacement process recursively simplified to 636 // something else needing this node. 637 if (N->use_empty()) { 638 // Nodes can be reintroduced into the worklist. Make sure we do not 639 // process a node that has been replaced. 640 removeFromWorkList(N); 641 642 // Finally, since the node is now dead, remove it from the graph. 643 DAG.DeleteNode(N); 644 } 645 return SDValue(N, 0); 646} 647 648void DAGCombiner:: 649CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 650 // Replace all uses. If any nodes become isomorphic to other nodes and 651 // are deleted, make sure to remove them from our worklist. 652 WorkListRemover DeadNodes(*this); 653 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 654 655 // Push the new node and any (possibly new) users onto the worklist. 656 AddToWorkList(TLO.New.getNode()); 657 AddUsersToWorkList(TLO.New.getNode()); 658 659 // Finally, if the node is now dead, remove it from the graph. The node 660 // may not be dead if the replacement process recursively simplified to 661 // something else needing this node. 662 if (TLO.Old.getNode()->use_empty()) { 663 removeFromWorkList(TLO.Old.getNode()); 664 665 // If the operands of this node are only used by the node, they will now 666 // be dead. Make sure to visit them first to delete dead nodes early. 667 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 668 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 669 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 670 671 DAG.DeleteNode(TLO.Old.getNode()); 672 } 673} 674 675/// SimplifyDemandedBits - Check the specified integer node value to see if 676/// it can be simplified or if things it uses can be simplified by bit 677/// propagation. If so, return true. 678bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 679 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 680 APInt KnownZero, KnownOne; 681 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 682 return false; 683 684 // Revisit the node. 685 AddToWorkList(Op.getNode()); 686 687 // Replace the old value with the new one. 688 ++NodesCombined; 689 DEBUG(dbgs() << "\nReplacing.2 "; 690 TLO.Old.getNode()->dump(&DAG); 691 dbgs() << "\nWith: "; 692 TLO.New.getNode()->dump(&DAG); 693 dbgs() << '\n'); 694 695 CommitTargetLoweringOpt(TLO); 696 return true; 697} 698 699void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 700 DebugLoc dl = Load->getDebugLoc(); 701 EVT VT = Load->getValueType(0); 702 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 703 704 DEBUG(dbgs() << "\nReplacing.9 "; 705 Load->dump(&DAG); 706 dbgs() << "\nWith: "; 707 Trunc.getNode()->dump(&DAG); 708 dbgs() << '\n'); 709 WorkListRemover DeadNodes(*this); 710 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 711 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 712 &DeadNodes); 713 removeFromWorkList(Load); 714 DAG.DeleteNode(Load); 715 AddToWorkList(Trunc.getNode()); 716} 717 718SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 719 Replace = false; 720 DebugLoc dl = Op.getDebugLoc(); 721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 722 EVT MemVT = LD->getMemoryVT(); 723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 725 : ISD::EXTLOAD) 726 : LD->getExtensionType(); 727 Replace = true; 728 return DAG.getExtLoad(ExtType, dl, PVT, 729 LD->getChain(), LD->getBasePtr(), 730 LD->getPointerInfo(), 731 MemVT, LD->isVolatile(), 732 LD->isNonTemporal(), LD->getAlignment()); 733 } 734 735 unsigned Opc = Op.getOpcode(); 736 switch (Opc) { 737 default: break; 738 case ISD::AssertSext: 739 return DAG.getNode(ISD::AssertSext, dl, PVT, 740 SExtPromoteOperand(Op.getOperand(0), PVT), 741 Op.getOperand(1)); 742 case ISD::AssertZext: 743 return DAG.getNode(ISD::AssertZext, dl, PVT, 744 ZExtPromoteOperand(Op.getOperand(0), PVT), 745 Op.getOperand(1)); 746 case ISD::Constant: { 747 unsigned ExtOpc = 748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 749 return DAG.getNode(ExtOpc, dl, PVT, Op); 750 } 751 } 752 753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 754 return SDValue(); 755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 756} 757 758SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 760 return SDValue(); 761 EVT OldVT = Op.getValueType(); 762 DebugLoc dl = Op.getDebugLoc(); 763 bool Replace = false; 764 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 765 if (NewOp.getNode() == 0) 766 return SDValue(); 767 AddToWorkList(NewOp.getNode()); 768 769 if (Replace) 770 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 772 DAG.getValueType(OldVT)); 773} 774 775SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 776 EVT OldVT = Op.getValueType(); 777 DebugLoc dl = Op.getDebugLoc(); 778 bool Replace = false; 779 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 780 if (NewOp.getNode() == 0) 781 return SDValue(); 782 AddToWorkList(NewOp.getNode()); 783 784 if (Replace) 785 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 786 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 787} 788 789/// PromoteIntBinOp - Promote the specified integer binary operation if the 790/// target indicates it is beneficial. e.g. On x86, it's usually better to 791/// promote i16 operations to i32 since i16 instructions are longer. 792SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 793 if (!LegalOperations) 794 return SDValue(); 795 796 EVT VT = Op.getValueType(); 797 if (VT.isVector() || !VT.isInteger()) 798 return SDValue(); 799 800 // If operation type is 'undesirable', e.g. i16 on x86, consider 801 // promoting it. 802 unsigned Opc = Op.getOpcode(); 803 if (TLI.isTypeDesirableForOp(Opc, VT)) 804 return SDValue(); 805 806 EVT PVT = VT; 807 // Consult target whether it is a good idea to promote this operation and 808 // what's the right type to promote it to. 809 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 810 assert(PVT != VT && "Don't know what type to promote to!"); 811 812 bool Replace0 = false; 813 SDValue N0 = Op.getOperand(0); 814 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 815 if (NN0.getNode() == 0) 816 return SDValue(); 817 818 bool Replace1 = false; 819 SDValue N1 = Op.getOperand(1); 820 SDValue NN1; 821 if (N0 == N1) 822 NN1 = NN0; 823 else { 824 NN1 = PromoteOperand(N1, PVT, Replace1); 825 if (NN1.getNode() == 0) 826 return SDValue(); 827 } 828 829 AddToWorkList(NN0.getNode()); 830 if (NN1.getNode()) 831 AddToWorkList(NN1.getNode()); 832 833 if (Replace0) 834 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 835 if (Replace1) 836 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 837 838 DEBUG(dbgs() << "\nPromoting "; 839 Op.getNode()->dump(&DAG)); 840 DebugLoc dl = Op.getDebugLoc(); 841 return DAG.getNode(ISD::TRUNCATE, dl, VT, 842 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 843 } 844 return SDValue(); 845} 846 847/// PromoteIntShiftOp - Promote the specified integer shift operation if the 848/// target indicates it is beneficial. e.g. On x86, it's usually better to 849/// promote i16 operations to i32 since i16 instructions are longer. 850SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 851 if (!LegalOperations) 852 return SDValue(); 853 854 EVT VT = Op.getValueType(); 855 if (VT.isVector() || !VT.isInteger()) 856 return SDValue(); 857 858 // If operation type is 'undesirable', e.g. i16 on x86, consider 859 // promoting it. 860 unsigned Opc = Op.getOpcode(); 861 if (TLI.isTypeDesirableForOp(Opc, VT)) 862 return SDValue(); 863 864 EVT PVT = VT; 865 // Consult target whether it is a good idea to promote this operation and 866 // what's the right type to promote it to. 867 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 868 assert(PVT != VT && "Don't know what type to promote to!"); 869 870 bool Replace = false; 871 SDValue N0 = Op.getOperand(0); 872 if (Opc == ISD::SRA) 873 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 874 else if (Opc == ISD::SRL) 875 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 876 else 877 N0 = PromoteOperand(N0, PVT, Replace); 878 if (N0.getNode() == 0) 879 return SDValue(); 880 881 AddToWorkList(N0.getNode()); 882 if (Replace) 883 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 884 885 DEBUG(dbgs() << "\nPromoting "; 886 Op.getNode()->dump(&DAG)); 887 DebugLoc dl = Op.getDebugLoc(); 888 return DAG.getNode(ISD::TRUNCATE, dl, VT, 889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 890 } 891 return SDValue(); 892} 893 894SDValue DAGCombiner::PromoteExtend(SDValue Op) { 895 if (!LegalOperations) 896 return SDValue(); 897 898 EVT VT = Op.getValueType(); 899 if (VT.isVector() || !VT.isInteger()) 900 return SDValue(); 901 902 // If operation type is 'undesirable', e.g. i16 on x86, consider 903 // promoting it. 904 unsigned Opc = Op.getOpcode(); 905 if (TLI.isTypeDesirableForOp(Opc, VT)) 906 return SDValue(); 907 908 EVT PVT = VT; 909 // Consult target whether it is a good idea to promote this operation and 910 // what's the right type to promote it to. 911 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 912 assert(PVT != VT && "Don't know what type to promote to!"); 913 // fold (aext (aext x)) -> (aext x) 914 // fold (aext (zext x)) -> (zext x) 915 // fold (aext (sext x)) -> (sext x) 916 DEBUG(dbgs() << "\nPromoting "; 917 Op.getNode()->dump(&DAG)); 918 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 919 } 920 return SDValue(); 921} 922 923bool DAGCombiner::PromoteLoad(SDValue Op) { 924 if (!LegalOperations) 925 return false; 926 927 EVT VT = Op.getValueType(); 928 if (VT.isVector() || !VT.isInteger()) 929 return false; 930 931 // If operation type is 'undesirable', e.g. i16 on x86, consider 932 // promoting it. 933 unsigned Opc = Op.getOpcode(); 934 if (TLI.isTypeDesirableForOp(Opc, VT)) 935 return false; 936 937 EVT PVT = VT; 938 // Consult target whether it is a good idea to promote this operation and 939 // what's the right type to promote it to. 940 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 941 assert(PVT != VT && "Don't know what type to promote to!"); 942 943 DebugLoc dl = Op.getDebugLoc(); 944 SDNode *N = Op.getNode(); 945 LoadSDNode *LD = cast<LoadSDNode>(N); 946 EVT MemVT = LD->getMemoryVT(); 947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 949 : ISD::EXTLOAD) 950 : LD->getExtensionType(); 951 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 952 LD->getChain(), LD->getBasePtr(), 953 LD->getPointerInfo(), 954 MemVT, LD->isVolatile(), 955 LD->isNonTemporal(), LD->getAlignment()); 956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 957 958 DEBUG(dbgs() << "\nPromoting "; 959 N->dump(&DAG); 960 dbgs() << "\nTo: "; 961 Result.getNode()->dump(&DAG); 962 dbgs() << '\n'); 963 WorkListRemover DeadNodes(*this); 964 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 965 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 966 removeFromWorkList(N); 967 DAG.DeleteNode(N); 968 AddToWorkList(Result.getNode()); 969 return true; 970 } 971 return false; 972} 973 974 975//===----------------------------------------------------------------------===// 976// Main DAG Combiner implementation 977//===----------------------------------------------------------------------===// 978 979void DAGCombiner::Run(CombineLevel AtLevel) { 980 // set the instance variables, so that the various visit routines may use it. 981 Level = AtLevel; 982 LegalOperations = Level >= AfterLegalizeVectorOps; 983 LegalTypes = Level >= AfterLegalizeTypes; 984 985 // Add all the dag nodes to the worklist. 986 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 987 E = DAG.allnodes_end(); I != E; ++I) 988 AddToWorkList(I); 989 990 // Create a dummy node (which is not added to allnodes), that adds a reference 991 // to the root node, preventing it from being deleted, and tracking any 992 // changes of the root. 993 HandleSDNode Dummy(DAG.getRoot()); 994 995 // The root of the dag may dangle to deleted nodes until the dag combiner is 996 // done. Set it to null to avoid confusion. 997 DAG.setRoot(SDValue()); 998 999 // while the worklist isn't empty, find a node and 1000 // try and combine it. 1001 while (!WorkListContents.empty()) { 1002 SDNode *N; 1003 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1004 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1005 // worklist *should* contain, and check the node we want to visit is should 1006 // actually be visited. 1007 do { 1008 N = WorkListOrder.pop_back_val(); 1009 } while (!WorkListContents.erase(N)); 1010 1011 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1012 // N is deleted from the DAG, since they too may now be dead or may have a 1013 // reduced number of uses, allowing other xforms. 1014 if (N->use_empty() && N != &Dummy) { 1015 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1016 AddToWorkList(N->getOperand(i).getNode()); 1017 1018 DAG.DeleteNode(N); 1019 continue; 1020 } 1021 1022 SDValue RV = combine(N); 1023 1024 if (RV.getNode() == 0) 1025 continue; 1026 1027 ++NodesCombined; 1028 1029 // If we get back the same node we passed in, rather than a new node or 1030 // zero, we know that the node must have defined multiple values and 1031 // CombineTo was used. Since CombineTo takes care of the worklist 1032 // mechanics for us, we have no work to do in this case. 1033 if (RV.getNode() == N) 1034 continue; 1035 1036 assert(N->getOpcode() != ISD::DELETED_NODE && 1037 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1038 "Node was deleted but visit returned new node!"); 1039 1040 DEBUG(dbgs() << "\nReplacing.3 "; 1041 N->dump(&DAG); 1042 dbgs() << "\nWith: "; 1043 RV.getNode()->dump(&DAG); 1044 dbgs() << '\n'); 1045 1046 // Transfer debug value. 1047 DAG.TransferDbgValues(SDValue(N, 0), RV); 1048 WorkListRemover DeadNodes(*this); 1049 if (N->getNumValues() == RV.getNode()->getNumValues()) 1050 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 1051 else { 1052 assert(N->getValueType(0) == RV.getValueType() && 1053 N->getNumValues() == 1 && "Type mismatch"); 1054 SDValue OpV = RV; 1055 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1056 } 1057 1058 // Push the new node and any users onto the worklist 1059 AddToWorkList(RV.getNode()); 1060 AddUsersToWorkList(RV.getNode()); 1061 1062 // Add any uses of the old node to the worklist in case this node is the 1063 // last one that uses them. They may become dead after this node is 1064 // deleted. 1065 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1066 AddToWorkList(N->getOperand(i).getNode()); 1067 1068 // Finally, if the node is now dead, remove it from the graph. The node 1069 // may not be dead if the replacement process recursively simplified to 1070 // something else needing this node. 1071 if (N->use_empty()) { 1072 // Nodes can be reintroduced into the worklist. Make sure we do not 1073 // process a node that has been replaced. 1074 removeFromWorkList(N); 1075 1076 // Finally, since the node is now dead, remove it from the graph. 1077 DAG.DeleteNode(N); 1078 } 1079 } 1080 1081 // If the root changed (e.g. it was a dead load, update the root). 1082 DAG.setRoot(Dummy.getValue()); 1083} 1084 1085SDValue DAGCombiner::visit(SDNode *N) { 1086 switch (N->getOpcode()) { 1087 default: break; 1088 case ISD::TokenFactor: return visitTokenFactor(N); 1089 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1090 case ISD::ADD: return visitADD(N); 1091 case ISD::SUB: return visitSUB(N); 1092 case ISD::ADDC: return visitADDC(N); 1093 case ISD::SUBC: return visitSUBC(N); 1094 case ISD::ADDE: return visitADDE(N); 1095 case ISD::SUBE: return visitSUBE(N); 1096 case ISD::MUL: return visitMUL(N); 1097 case ISD::SDIV: return visitSDIV(N); 1098 case ISD::UDIV: return visitUDIV(N); 1099 case ISD::SREM: return visitSREM(N); 1100 case ISD::UREM: return visitUREM(N); 1101 case ISD::MULHU: return visitMULHU(N); 1102 case ISD::MULHS: return visitMULHS(N); 1103 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1104 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1105 case ISD::SMULO: return visitSMULO(N); 1106 case ISD::UMULO: return visitUMULO(N); 1107 case ISD::SDIVREM: return visitSDIVREM(N); 1108 case ISD::UDIVREM: return visitUDIVREM(N); 1109 case ISD::AND: return visitAND(N); 1110 case ISD::OR: return visitOR(N); 1111 case ISD::XOR: return visitXOR(N); 1112 case ISD::SHL: return visitSHL(N); 1113 case ISD::SRA: return visitSRA(N); 1114 case ISD::SRL: return visitSRL(N); 1115 case ISD::CTLZ: return visitCTLZ(N); 1116 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1117 case ISD::CTTZ: return visitCTTZ(N); 1118 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1119 case ISD::CTPOP: return visitCTPOP(N); 1120 case ISD::SELECT: return visitSELECT(N); 1121 case ISD::SELECT_CC: return visitSELECT_CC(N); 1122 case ISD::SETCC: return visitSETCC(N); 1123 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1124 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1125 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1126 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1127 case ISD::TRUNCATE: return visitTRUNCATE(N); 1128 case ISD::BITCAST: return visitBITCAST(N); 1129 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1130 case ISD::FADD: return visitFADD(N); 1131 case ISD::FSUB: return visitFSUB(N); 1132 case ISD::FMUL: return visitFMUL(N); 1133 case ISD::FDIV: return visitFDIV(N); 1134 case ISD::FREM: return visitFREM(N); 1135 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1136 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1137 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1138 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1139 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1140 case ISD::FP_ROUND: return visitFP_ROUND(N); 1141 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1142 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1143 case ISD::FNEG: return visitFNEG(N); 1144 case ISD::FABS: return visitFABS(N); 1145 case ISD::BRCOND: return visitBRCOND(N); 1146 case ISD::BR_CC: return visitBR_CC(N); 1147 case ISD::LOAD: return visitLOAD(N); 1148 case ISD::STORE: return visitSTORE(N); 1149 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1150 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1151 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1152 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1153 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1154 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1155 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1156 } 1157 return SDValue(); 1158} 1159 1160SDValue DAGCombiner::combine(SDNode *N) { 1161 SDValue RV = visit(N); 1162 1163 // If nothing happened, try a target-specific DAG combine. 1164 if (RV.getNode() == 0) { 1165 assert(N->getOpcode() != ISD::DELETED_NODE && 1166 "Node was deleted but visit returned NULL!"); 1167 1168 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1169 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1170 1171 // Expose the DAG combiner to the target combiner impls. 1172 TargetLowering::DAGCombinerInfo 1173 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1174 1175 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1176 } 1177 } 1178 1179 // If nothing happened still, try promoting the operation. 1180 if (RV.getNode() == 0) { 1181 switch (N->getOpcode()) { 1182 default: break; 1183 case ISD::ADD: 1184 case ISD::SUB: 1185 case ISD::MUL: 1186 case ISD::AND: 1187 case ISD::OR: 1188 case ISD::XOR: 1189 RV = PromoteIntBinOp(SDValue(N, 0)); 1190 break; 1191 case ISD::SHL: 1192 case ISD::SRA: 1193 case ISD::SRL: 1194 RV = PromoteIntShiftOp(SDValue(N, 0)); 1195 break; 1196 case ISD::SIGN_EXTEND: 1197 case ISD::ZERO_EXTEND: 1198 case ISD::ANY_EXTEND: 1199 RV = PromoteExtend(SDValue(N, 0)); 1200 break; 1201 case ISD::LOAD: 1202 if (PromoteLoad(SDValue(N, 0))) 1203 RV = SDValue(N, 0); 1204 break; 1205 } 1206 } 1207 1208 // If N is a commutative binary node, try commuting it to enable more 1209 // sdisel CSE. 1210 if (RV.getNode() == 0 && 1211 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1212 N->getNumValues() == 1) { 1213 SDValue N0 = N->getOperand(0); 1214 SDValue N1 = N->getOperand(1); 1215 1216 // Constant operands are canonicalized to RHS. 1217 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1218 SDValue Ops[] = { N1, N0 }; 1219 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1220 Ops, 2); 1221 if (CSENode) 1222 return SDValue(CSENode, 0); 1223 } 1224 } 1225 1226 return RV; 1227} 1228 1229/// getInputChainForNode - Given a node, return its input chain if it has one, 1230/// otherwise return a null sd operand. 1231static SDValue getInputChainForNode(SDNode *N) { 1232 if (unsigned NumOps = N->getNumOperands()) { 1233 if (N->getOperand(0).getValueType() == MVT::Other) 1234 return N->getOperand(0); 1235 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1236 return N->getOperand(NumOps-1); 1237 for (unsigned i = 1; i < NumOps-1; ++i) 1238 if (N->getOperand(i).getValueType() == MVT::Other) 1239 return N->getOperand(i); 1240 } 1241 return SDValue(); 1242} 1243 1244SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1245 // If N has two operands, where one has an input chain equal to the other, 1246 // the 'other' chain is redundant. 1247 if (N->getNumOperands() == 2) { 1248 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1249 return N->getOperand(0); 1250 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1251 return N->getOperand(1); 1252 } 1253 1254 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1255 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1256 SmallPtrSet<SDNode*, 16> SeenOps; 1257 bool Changed = false; // If we should replace this token factor. 1258 1259 // Start out with this token factor. 1260 TFs.push_back(N); 1261 1262 // Iterate through token factors. The TFs grows when new token factors are 1263 // encountered. 1264 for (unsigned i = 0; i < TFs.size(); ++i) { 1265 SDNode *TF = TFs[i]; 1266 1267 // Check each of the operands. 1268 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1269 SDValue Op = TF->getOperand(i); 1270 1271 switch (Op.getOpcode()) { 1272 case ISD::EntryToken: 1273 // Entry tokens don't need to be added to the list. They are 1274 // rededundant. 1275 Changed = true; 1276 break; 1277 1278 case ISD::TokenFactor: 1279 if (Op.hasOneUse() && 1280 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1281 // Queue up for processing. 1282 TFs.push_back(Op.getNode()); 1283 // Clean up in case the token factor is removed. 1284 AddToWorkList(Op.getNode()); 1285 Changed = true; 1286 break; 1287 } 1288 // Fall thru 1289 1290 default: 1291 // Only add if it isn't already in the list. 1292 if (SeenOps.insert(Op.getNode())) 1293 Ops.push_back(Op); 1294 else 1295 Changed = true; 1296 break; 1297 } 1298 } 1299 } 1300 1301 SDValue Result; 1302 1303 // If we've change things around then replace token factor. 1304 if (Changed) { 1305 if (Ops.empty()) { 1306 // The entry token is the only possible outcome. 1307 Result = DAG.getEntryNode(); 1308 } else { 1309 // New and improved token factor. 1310 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1311 MVT::Other, &Ops[0], Ops.size()); 1312 } 1313 1314 // Don't add users to work list. 1315 return CombineTo(N, Result, false); 1316 } 1317 1318 return Result; 1319} 1320 1321/// MERGE_VALUES can always be eliminated. 1322SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1323 WorkListRemover DeadNodes(*this); 1324 // Replacing results may cause a different MERGE_VALUES to suddenly 1325 // be CSE'd with N, and carry its uses with it. Iterate until no 1326 // uses remain, to ensure that the node can be safely deleted. 1327 do { 1328 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1329 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1330 &DeadNodes); 1331 } while (!N->use_empty()); 1332 removeFromWorkList(N); 1333 DAG.DeleteNode(N); 1334 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1335} 1336 1337static 1338SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1339 SelectionDAG &DAG) { 1340 EVT VT = N0.getValueType(); 1341 SDValue N00 = N0.getOperand(0); 1342 SDValue N01 = N0.getOperand(1); 1343 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1344 1345 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1346 isa<ConstantSDNode>(N00.getOperand(1))) { 1347 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1348 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1349 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1350 N00.getOperand(0), N01), 1351 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1352 N00.getOperand(1), N01)); 1353 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1354 } 1355 1356 return SDValue(); 1357} 1358 1359SDValue DAGCombiner::visitADD(SDNode *N) { 1360 SDValue N0 = N->getOperand(0); 1361 SDValue N1 = N->getOperand(1); 1362 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1364 EVT VT = N0.getValueType(); 1365 1366 // fold vector ops 1367 if (VT.isVector()) { 1368 SDValue FoldedVOp = SimplifyVBinOp(N); 1369 if (FoldedVOp.getNode()) return FoldedVOp; 1370 } 1371 1372 // fold (add x, undef) -> undef 1373 if (N0.getOpcode() == ISD::UNDEF) 1374 return N0; 1375 if (N1.getOpcode() == ISD::UNDEF) 1376 return N1; 1377 // fold (add c1, c2) -> c1+c2 1378 if (N0C && N1C) 1379 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1380 // canonicalize constant to RHS 1381 if (N0C && !N1C) 1382 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1383 // fold (add x, 0) -> x 1384 if (N1C && N1C->isNullValue()) 1385 return N0; 1386 // fold (add Sym, c) -> Sym+c 1387 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1388 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1389 GA->getOpcode() == ISD::GlobalAddress) 1390 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1391 GA->getOffset() + 1392 (uint64_t)N1C->getSExtValue()); 1393 // fold ((c1-A)+c2) -> (c1+c2)-A 1394 if (N1C && N0.getOpcode() == ISD::SUB) 1395 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1396 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1397 DAG.getConstant(N1C->getAPIntValue()+ 1398 N0C->getAPIntValue(), VT), 1399 N0.getOperand(1)); 1400 // reassociate add 1401 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1402 if (RADD.getNode() != 0) 1403 return RADD; 1404 // fold ((0-A) + B) -> B-A 1405 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1406 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1407 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1408 // fold (A + (0-B)) -> A-B 1409 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1410 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1411 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1412 // fold (A+(B-A)) -> B 1413 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1414 return N1.getOperand(0); 1415 // fold ((B-A)+A) -> B 1416 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1417 return N0.getOperand(0); 1418 // fold (A+(B-(A+C))) to (B-C) 1419 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1420 N0 == N1.getOperand(1).getOperand(0)) 1421 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1422 N1.getOperand(1).getOperand(1)); 1423 // fold (A+(B-(C+A))) to (B-C) 1424 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1425 N0 == N1.getOperand(1).getOperand(1)) 1426 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1427 N1.getOperand(1).getOperand(0)); 1428 // fold (A+((B-A)+or-C)) to (B+or-C) 1429 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1430 N1.getOperand(0).getOpcode() == ISD::SUB && 1431 N0 == N1.getOperand(0).getOperand(1)) 1432 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1433 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1434 1435 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1436 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1437 SDValue N00 = N0.getOperand(0); 1438 SDValue N01 = N0.getOperand(1); 1439 SDValue N10 = N1.getOperand(0); 1440 SDValue N11 = N1.getOperand(1); 1441 1442 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1443 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1444 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1445 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1446 } 1447 1448 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1449 return SDValue(N, 0); 1450 1451 // fold (a+b) -> (a|b) iff a and b share no bits. 1452 if (VT.isInteger() && !VT.isVector()) { 1453 APInt LHSZero, LHSOne; 1454 APInt RHSZero, RHSOne; 1455 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1456 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1457 1458 if (LHSZero.getBoolValue()) { 1459 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1460 1461 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1462 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1463 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1464 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1465 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1466 } 1467 } 1468 1469 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1470 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1471 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1472 if (Result.getNode()) return Result; 1473 } 1474 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1475 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1476 if (Result.getNode()) return Result; 1477 } 1478 1479 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1480 if (N1.getOpcode() == ISD::SHL && 1481 N1.getOperand(0).getOpcode() == ISD::SUB) 1482 if (ConstantSDNode *C = 1483 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1484 if (C->getAPIntValue() == 0) 1485 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1486 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1487 N1.getOperand(0).getOperand(1), 1488 N1.getOperand(1))); 1489 if (N0.getOpcode() == ISD::SHL && 1490 N0.getOperand(0).getOpcode() == ISD::SUB) 1491 if (ConstantSDNode *C = 1492 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1493 if (C->getAPIntValue() == 0) 1494 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1495 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1496 N0.getOperand(0).getOperand(1), 1497 N0.getOperand(1))); 1498 1499 if (N1.getOpcode() == ISD::AND) { 1500 SDValue AndOp0 = N1.getOperand(0); 1501 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1502 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1503 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1504 1505 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1506 // and similar xforms where the inner op is either ~0 or 0. 1507 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1508 DebugLoc DL = N->getDebugLoc(); 1509 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1510 } 1511 } 1512 1513 // add (sext i1), X -> sub X, (zext i1) 1514 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1515 N0.getOperand(0).getValueType() == MVT::i1 && 1516 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1517 DebugLoc DL = N->getDebugLoc(); 1518 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1519 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1520 } 1521 1522 return SDValue(); 1523} 1524 1525SDValue DAGCombiner::visitADDC(SDNode *N) { 1526 SDValue N0 = N->getOperand(0); 1527 SDValue N1 = N->getOperand(1); 1528 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1529 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1530 EVT VT = N0.getValueType(); 1531 1532 // If the flag result is dead, turn this into an ADD. 1533 if (!N->hasAnyUseOfValue(1)) 1534 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1535 DAG.getNode(ISD::CARRY_FALSE, 1536 N->getDebugLoc(), MVT::Glue)); 1537 1538 // canonicalize constant to RHS. 1539 if (N0C && !N1C) 1540 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1541 1542 // fold (addc x, 0) -> x + no carry out 1543 if (N1C && N1C->isNullValue()) 1544 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1545 N->getDebugLoc(), MVT::Glue)); 1546 1547 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1548 APInt LHSZero, LHSOne; 1549 APInt RHSZero, RHSOne; 1550 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1551 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1552 1553 if (LHSZero.getBoolValue()) { 1554 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1555 1556 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1557 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1558 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1559 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1560 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1561 DAG.getNode(ISD::CARRY_FALSE, 1562 N->getDebugLoc(), MVT::Glue)); 1563 } 1564 1565 return SDValue(); 1566} 1567 1568SDValue DAGCombiner::visitADDE(SDNode *N) { 1569 SDValue N0 = N->getOperand(0); 1570 SDValue N1 = N->getOperand(1); 1571 SDValue CarryIn = N->getOperand(2); 1572 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1573 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1574 1575 // canonicalize constant to RHS 1576 if (N0C && !N1C) 1577 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1578 N1, N0, CarryIn); 1579 1580 // fold (adde x, y, false) -> (addc x, y) 1581 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1582 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1583 1584 return SDValue(); 1585} 1586 1587// Since it may not be valid to emit a fold to zero for vector initializers 1588// check if we can before folding. 1589static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1590 SelectionDAG &DAG, bool LegalOperations) { 1591 if (!VT.isVector()) { 1592 return DAG.getConstant(0, VT); 1593 } 1594 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1595 // Produce a vector of zeros. 1596 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1597 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1598 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1599 &Ops[0], Ops.size()); 1600 } 1601 return SDValue(); 1602} 1603 1604SDValue DAGCombiner::visitSUB(SDNode *N) { 1605 SDValue N0 = N->getOperand(0); 1606 SDValue N1 = N->getOperand(1); 1607 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1608 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1609 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1610 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1611 EVT VT = N0.getValueType(); 1612 1613 // fold vector ops 1614 if (VT.isVector()) { 1615 SDValue FoldedVOp = SimplifyVBinOp(N); 1616 if (FoldedVOp.getNode()) return FoldedVOp; 1617 } 1618 1619 // fold (sub x, x) -> 0 1620 // FIXME: Refactor this and xor and other similar operations together. 1621 if (N0 == N1) 1622 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1623 // fold (sub c1, c2) -> c1-c2 1624 if (N0C && N1C) 1625 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1626 // fold (sub x, c) -> (add x, -c) 1627 if (N1C) 1628 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1629 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1630 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1631 if (N0C && N0C->isAllOnesValue()) 1632 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1633 // fold A-(A-B) -> B 1634 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1635 return N1.getOperand(1); 1636 // fold (A+B)-A -> B 1637 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1638 return N0.getOperand(1); 1639 // fold (A+B)-B -> A 1640 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1641 return N0.getOperand(0); 1642 // fold C2-(A+C1) -> (C2-C1)-A 1643 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1644 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT); 1645 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1646 N1.getOperand(0)); 1647 } 1648 // fold ((A+(B+or-C))-B) -> A+or-C 1649 if (N0.getOpcode() == ISD::ADD && 1650 (N0.getOperand(1).getOpcode() == ISD::SUB || 1651 N0.getOperand(1).getOpcode() == ISD::ADD) && 1652 N0.getOperand(1).getOperand(0) == N1) 1653 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1654 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1655 // fold ((A+(C+B))-B) -> A+C 1656 if (N0.getOpcode() == ISD::ADD && 1657 N0.getOperand(1).getOpcode() == ISD::ADD && 1658 N0.getOperand(1).getOperand(1) == N1) 1659 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1660 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1661 // fold ((A-(B-C))-C) -> A-B 1662 if (N0.getOpcode() == ISD::SUB && 1663 N0.getOperand(1).getOpcode() == ISD::SUB && 1664 N0.getOperand(1).getOperand(1) == N1) 1665 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1666 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1667 1668 // If either operand of a sub is undef, the result is undef 1669 if (N0.getOpcode() == ISD::UNDEF) 1670 return N0; 1671 if (N1.getOpcode() == ISD::UNDEF) 1672 return N1; 1673 1674 // If the relocation model supports it, consider symbol offsets. 1675 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1676 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1677 // fold (sub Sym, c) -> Sym-c 1678 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1679 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1680 GA->getOffset() - 1681 (uint64_t)N1C->getSExtValue()); 1682 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1683 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1684 if (GA->getGlobal() == GB->getGlobal()) 1685 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1686 VT); 1687 } 1688 1689 return SDValue(); 1690} 1691 1692SDValue DAGCombiner::visitSUBC(SDNode *N) { 1693 SDValue N0 = N->getOperand(0); 1694 SDValue N1 = N->getOperand(1); 1695 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1696 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1697 EVT VT = N0.getValueType(); 1698 1699 // If the flag result is dead, turn this into an SUB. 1700 if (!N->hasAnyUseOfValue(1)) 1701 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1702 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1703 MVT::Glue)); 1704 1705 // fold (subc x, x) -> 0 + no borrow 1706 if (N0 == N1) 1707 return CombineTo(N, DAG.getConstant(0, VT), 1708 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1709 MVT::Glue)); 1710 1711 // fold (subc x, 0) -> x + no borrow 1712 if (N1C && N1C->isNullValue()) 1713 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1714 MVT::Glue)); 1715 1716 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1717 if (N0C && N0C->isAllOnesValue()) 1718 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1719 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1720 MVT::Glue)); 1721 1722 return SDValue(); 1723} 1724 1725SDValue DAGCombiner::visitSUBE(SDNode *N) { 1726 SDValue N0 = N->getOperand(0); 1727 SDValue N1 = N->getOperand(1); 1728 SDValue CarryIn = N->getOperand(2); 1729 1730 // fold (sube x, y, false) -> (subc x, y) 1731 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1732 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1733 1734 return SDValue(); 1735} 1736 1737SDValue DAGCombiner::visitMUL(SDNode *N) { 1738 SDValue N0 = N->getOperand(0); 1739 SDValue N1 = N->getOperand(1); 1740 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1741 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1742 EVT VT = N0.getValueType(); 1743 1744 // fold vector ops 1745 if (VT.isVector()) { 1746 SDValue FoldedVOp = SimplifyVBinOp(N); 1747 if (FoldedVOp.getNode()) return FoldedVOp; 1748 } 1749 1750 // fold (mul x, undef) -> 0 1751 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1752 return DAG.getConstant(0, VT); 1753 // fold (mul c1, c2) -> c1*c2 1754 if (N0C && N1C) 1755 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1756 // canonicalize constant to RHS 1757 if (N0C && !N1C) 1758 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1759 // fold (mul x, 0) -> 0 1760 if (N1C && N1C->isNullValue()) 1761 return N1; 1762 // fold (mul x, -1) -> 0-x 1763 if (N1C && N1C->isAllOnesValue()) 1764 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1765 DAG.getConstant(0, VT), N0); 1766 // fold (mul x, (1 << c)) -> x << c 1767 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1768 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1769 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1770 getShiftAmountTy(N0.getValueType()))); 1771 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1772 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1773 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1774 // FIXME: If the input is something that is easily negated (e.g. a 1775 // single-use add), we should put the negate there. 1776 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1777 DAG.getConstant(0, VT), 1778 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1779 DAG.getConstant(Log2Val, 1780 getShiftAmountTy(N0.getValueType())))); 1781 } 1782 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1783 if (N1C && N0.getOpcode() == ISD::SHL && 1784 isa<ConstantSDNode>(N0.getOperand(1))) { 1785 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1786 N1, N0.getOperand(1)); 1787 AddToWorkList(C3.getNode()); 1788 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1789 N0.getOperand(0), C3); 1790 } 1791 1792 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1793 // use. 1794 { 1795 SDValue Sh(0,0), Y(0,0); 1796 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1797 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1798 N0.getNode()->hasOneUse()) { 1799 Sh = N0; Y = N1; 1800 } else if (N1.getOpcode() == ISD::SHL && 1801 isa<ConstantSDNode>(N1.getOperand(1)) && 1802 N1.getNode()->hasOneUse()) { 1803 Sh = N1; Y = N0; 1804 } 1805 1806 if (Sh.getNode()) { 1807 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1808 Sh.getOperand(0), Y); 1809 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1810 Mul, Sh.getOperand(1)); 1811 } 1812 } 1813 1814 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1815 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1816 isa<ConstantSDNode>(N0.getOperand(1))) 1817 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1818 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1819 N0.getOperand(0), N1), 1820 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1821 N0.getOperand(1), N1)); 1822 1823 // reassociate mul 1824 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1825 if (RMUL.getNode() != 0) 1826 return RMUL; 1827 1828 return SDValue(); 1829} 1830 1831SDValue DAGCombiner::visitSDIV(SDNode *N) { 1832 SDValue N0 = N->getOperand(0); 1833 SDValue N1 = N->getOperand(1); 1834 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1835 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1836 EVT VT = N->getValueType(0); 1837 1838 // fold vector ops 1839 if (VT.isVector()) { 1840 SDValue FoldedVOp = SimplifyVBinOp(N); 1841 if (FoldedVOp.getNode()) return FoldedVOp; 1842 } 1843 1844 // fold (sdiv c1, c2) -> c1/c2 1845 if (N0C && N1C && !N1C->isNullValue()) 1846 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1847 // fold (sdiv X, 1) -> X 1848 if (N1C && N1C->getAPIntValue() == 1LL) 1849 return N0; 1850 // fold (sdiv X, -1) -> 0-X 1851 if (N1C && N1C->isAllOnesValue()) 1852 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1853 DAG.getConstant(0, VT), N0); 1854 // If we know the sign bits of both operands are zero, strength reduce to a 1855 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1856 if (!VT.isVector()) { 1857 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1858 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1859 N0, N1); 1860 } 1861 // fold (sdiv X, pow2) -> simple ops after legalize 1862 if (N1C && !N1C->isNullValue() && 1863 (N1C->getAPIntValue().isPowerOf2() || 1864 (-N1C->getAPIntValue()).isPowerOf2())) { 1865 // If dividing by powers of two is cheap, then don't perform the following 1866 // fold. 1867 if (TLI.isPow2DivCheap()) 1868 return SDValue(); 1869 1870 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1871 1872 // Splat the sign bit into the register 1873 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1874 DAG.getConstant(VT.getSizeInBits()-1, 1875 getShiftAmountTy(N0.getValueType()))); 1876 AddToWorkList(SGN.getNode()); 1877 1878 // Add (N0 < 0) ? abs2 - 1 : 0; 1879 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1880 DAG.getConstant(VT.getSizeInBits() - lg2, 1881 getShiftAmountTy(SGN.getValueType()))); 1882 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1883 AddToWorkList(SRL.getNode()); 1884 AddToWorkList(ADD.getNode()); // Divide by pow2 1885 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1886 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1887 1888 // If we're dividing by a positive value, we're done. Otherwise, we must 1889 // negate the result. 1890 if (N1C->getAPIntValue().isNonNegative()) 1891 return SRA; 1892 1893 AddToWorkList(SRA.getNode()); 1894 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1895 DAG.getConstant(0, VT), SRA); 1896 } 1897 1898 // if integer divide is expensive and we satisfy the requirements, emit an 1899 // alternate sequence. 1900 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1901 SDValue Op = BuildSDIV(N); 1902 if (Op.getNode()) return Op; 1903 } 1904 1905 // undef / X -> 0 1906 if (N0.getOpcode() == ISD::UNDEF) 1907 return DAG.getConstant(0, VT); 1908 // X / undef -> undef 1909 if (N1.getOpcode() == ISD::UNDEF) 1910 return N1; 1911 1912 return SDValue(); 1913} 1914 1915SDValue DAGCombiner::visitUDIV(SDNode *N) { 1916 SDValue N0 = N->getOperand(0); 1917 SDValue N1 = N->getOperand(1); 1918 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1919 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1920 EVT VT = N->getValueType(0); 1921 1922 // fold vector ops 1923 if (VT.isVector()) { 1924 SDValue FoldedVOp = SimplifyVBinOp(N); 1925 if (FoldedVOp.getNode()) return FoldedVOp; 1926 } 1927 1928 // fold (udiv c1, c2) -> c1/c2 1929 if (N0C && N1C && !N1C->isNullValue()) 1930 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1931 // fold (udiv x, (1 << c)) -> x >>u c 1932 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1933 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1934 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1935 getShiftAmountTy(N0.getValueType()))); 1936 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1937 if (N1.getOpcode() == ISD::SHL) { 1938 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1939 if (SHC->getAPIntValue().isPowerOf2()) { 1940 EVT ADDVT = N1.getOperand(1).getValueType(); 1941 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1942 N1.getOperand(1), 1943 DAG.getConstant(SHC->getAPIntValue() 1944 .logBase2(), 1945 ADDVT)); 1946 AddToWorkList(Add.getNode()); 1947 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1948 } 1949 } 1950 } 1951 // fold (udiv x, c) -> alternate 1952 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1953 SDValue Op = BuildUDIV(N); 1954 if (Op.getNode()) return Op; 1955 } 1956 1957 // undef / X -> 0 1958 if (N0.getOpcode() == ISD::UNDEF) 1959 return DAG.getConstant(0, VT); 1960 // X / undef -> undef 1961 if (N1.getOpcode() == ISD::UNDEF) 1962 return N1; 1963 1964 return SDValue(); 1965} 1966 1967SDValue DAGCombiner::visitSREM(SDNode *N) { 1968 SDValue N0 = N->getOperand(0); 1969 SDValue N1 = N->getOperand(1); 1970 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1971 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1972 EVT VT = N->getValueType(0); 1973 1974 // fold (srem c1, c2) -> c1%c2 1975 if (N0C && N1C && !N1C->isNullValue()) 1976 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1977 // If we know the sign bits of both operands are zero, strength reduce to a 1978 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1979 if (!VT.isVector()) { 1980 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1981 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1982 } 1983 1984 // If X/C can be simplified by the division-by-constant logic, lower 1985 // X%C to the equivalent of X-X/C*C. 1986 if (N1C && !N1C->isNullValue()) { 1987 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1988 AddToWorkList(Div.getNode()); 1989 SDValue OptimizedDiv = combine(Div.getNode()); 1990 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1991 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1992 OptimizedDiv, N1); 1993 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1994 AddToWorkList(Mul.getNode()); 1995 return Sub; 1996 } 1997 } 1998 1999 // undef % X -> 0 2000 if (N0.getOpcode() == ISD::UNDEF) 2001 return DAG.getConstant(0, VT); 2002 // X % undef -> undef 2003 if (N1.getOpcode() == ISD::UNDEF) 2004 return N1; 2005 2006 return SDValue(); 2007} 2008 2009SDValue DAGCombiner::visitUREM(SDNode *N) { 2010 SDValue N0 = N->getOperand(0); 2011 SDValue N1 = N->getOperand(1); 2012 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2013 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2014 EVT VT = N->getValueType(0); 2015 2016 // fold (urem c1, c2) -> c1%c2 2017 if (N0C && N1C && !N1C->isNullValue()) 2018 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2019 // fold (urem x, pow2) -> (and x, pow2-1) 2020 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2021 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2022 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2023 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2024 if (N1.getOpcode() == ISD::SHL) { 2025 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2026 if (SHC->getAPIntValue().isPowerOf2()) { 2027 SDValue Add = 2028 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2029 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2030 VT)); 2031 AddToWorkList(Add.getNode()); 2032 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2033 } 2034 } 2035 } 2036 2037 // If X/C can be simplified by the division-by-constant logic, lower 2038 // X%C to the equivalent of X-X/C*C. 2039 if (N1C && !N1C->isNullValue()) { 2040 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2041 AddToWorkList(Div.getNode()); 2042 SDValue OptimizedDiv = combine(Div.getNode()); 2043 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2044 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2045 OptimizedDiv, N1); 2046 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2047 AddToWorkList(Mul.getNode()); 2048 return Sub; 2049 } 2050 } 2051 2052 // undef % X -> 0 2053 if (N0.getOpcode() == ISD::UNDEF) 2054 return DAG.getConstant(0, VT); 2055 // X % undef -> undef 2056 if (N1.getOpcode() == ISD::UNDEF) 2057 return N1; 2058 2059 return SDValue(); 2060} 2061 2062SDValue DAGCombiner::visitMULHS(SDNode *N) { 2063 SDValue N0 = N->getOperand(0); 2064 SDValue N1 = N->getOperand(1); 2065 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2066 EVT VT = N->getValueType(0); 2067 DebugLoc DL = N->getDebugLoc(); 2068 2069 // fold (mulhs x, 0) -> 0 2070 if (N1C && N1C->isNullValue()) 2071 return N1; 2072 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2073 if (N1C && N1C->getAPIntValue() == 1) 2074 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2075 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2076 getShiftAmountTy(N0.getValueType()))); 2077 // fold (mulhs x, undef) -> 0 2078 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2079 return DAG.getConstant(0, VT); 2080 2081 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2082 // plus a shift. 2083 if (VT.isSimple() && !VT.isVector()) { 2084 MVT Simple = VT.getSimpleVT(); 2085 unsigned SimpleSize = Simple.getSizeInBits(); 2086 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2087 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2088 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2089 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2090 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2091 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2092 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2093 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2094 } 2095 } 2096 2097 return SDValue(); 2098} 2099 2100SDValue DAGCombiner::visitMULHU(SDNode *N) { 2101 SDValue N0 = N->getOperand(0); 2102 SDValue N1 = N->getOperand(1); 2103 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2104 EVT VT = N->getValueType(0); 2105 DebugLoc DL = N->getDebugLoc(); 2106 2107 // fold (mulhu x, 0) -> 0 2108 if (N1C && N1C->isNullValue()) 2109 return N1; 2110 // fold (mulhu x, 1) -> 0 2111 if (N1C && N1C->getAPIntValue() == 1) 2112 return DAG.getConstant(0, N0.getValueType()); 2113 // fold (mulhu x, undef) -> 0 2114 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2115 return DAG.getConstant(0, VT); 2116 2117 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2118 // plus a shift. 2119 if (VT.isSimple() && !VT.isVector()) { 2120 MVT Simple = VT.getSimpleVT(); 2121 unsigned SimpleSize = Simple.getSizeInBits(); 2122 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2123 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2124 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2125 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2126 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2127 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2128 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2129 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2130 } 2131 } 2132 2133 return SDValue(); 2134} 2135 2136/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2137/// compute two values. LoOp and HiOp give the opcodes for the two computations 2138/// that are being performed. Return true if a simplification was made. 2139/// 2140SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2141 unsigned HiOp) { 2142 // If the high half is not needed, just compute the low half. 2143 bool HiExists = N->hasAnyUseOfValue(1); 2144 if (!HiExists && 2145 (!LegalOperations || 2146 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2147 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2148 N->op_begin(), N->getNumOperands()); 2149 return CombineTo(N, Res, Res); 2150 } 2151 2152 // If the low half is not needed, just compute the high half. 2153 bool LoExists = N->hasAnyUseOfValue(0); 2154 if (!LoExists && 2155 (!LegalOperations || 2156 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2157 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2158 N->op_begin(), N->getNumOperands()); 2159 return CombineTo(N, Res, Res); 2160 } 2161 2162 // If both halves are used, return as it is. 2163 if (LoExists && HiExists) 2164 return SDValue(); 2165 2166 // If the two computed results can be simplified separately, separate them. 2167 if (LoExists) { 2168 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2169 N->op_begin(), N->getNumOperands()); 2170 AddToWorkList(Lo.getNode()); 2171 SDValue LoOpt = combine(Lo.getNode()); 2172 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2173 (!LegalOperations || 2174 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2175 return CombineTo(N, LoOpt, LoOpt); 2176 } 2177 2178 if (HiExists) { 2179 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2180 N->op_begin(), N->getNumOperands()); 2181 AddToWorkList(Hi.getNode()); 2182 SDValue HiOpt = combine(Hi.getNode()); 2183 if (HiOpt.getNode() && HiOpt != Hi && 2184 (!LegalOperations || 2185 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2186 return CombineTo(N, HiOpt, HiOpt); 2187 } 2188 2189 return SDValue(); 2190} 2191 2192SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2193 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2194 if (Res.getNode()) return Res; 2195 2196 EVT VT = N->getValueType(0); 2197 DebugLoc DL = N->getDebugLoc(); 2198 2199 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2200 // plus a shift. 2201 if (VT.isSimple() && !VT.isVector()) { 2202 MVT Simple = VT.getSimpleVT(); 2203 unsigned SimpleSize = Simple.getSizeInBits(); 2204 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2205 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2206 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2207 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2208 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2209 // Compute the high part as N1. 2210 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2211 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2212 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2213 // Compute the low part as N0. 2214 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2215 return CombineTo(N, Lo, Hi); 2216 } 2217 } 2218 2219 return SDValue(); 2220} 2221 2222SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2223 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2224 if (Res.getNode()) return Res; 2225 2226 EVT VT = N->getValueType(0); 2227 DebugLoc DL = N->getDebugLoc(); 2228 2229 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2230 // plus a shift. 2231 if (VT.isSimple() && !VT.isVector()) { 2232 MVT Simple = VT.getSimpleVT(); 2233 unsigned SimpleSize = Simple.getSizeInBits(); 2234 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2235 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2236 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2237 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2238 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2239 // Compute the high part as N1. 2240 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2241 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2242 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2243 // Compute the low part as N0. 2244 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2245 return CombineTo(N, Lo, Hi); 2246 } 2247 } 2248 2249 return SDValue(); 2250} 2251 2252SDValue DAGCombiner::visitSMULO(SDNode *N) { 2253 // (smulo x, 2) -> (saddo x, x) 2254 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2255 if (C2->getAPIntValue() == 2) 2256 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2257 N->getOperand(0), N->getOperand(0)); 2258 2259 return SDValue(); 2260} 2261 2262SDValue DAGCombiner::visitUMULO(SDNode *N) { 2263 // (umulo x, 2) -> (uaddo x, x) 2264 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2265 if (C2->getAPIntValue() == 2) 2266 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2267 N->getOperand(0), N->getOperand(0)); 2268 2269 return SDValue(); 2270} 2271 2272SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2273 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2274 if (Res.getNode()) return Res; 2275 2276 return SDValue(); 2277} 2278 2279SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2280 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2281 if (Res.getNode()) return Res; 2282 2283 return SDValue(); 2284} 2285 2286/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2287/// two operands of the same opcode, try to simplify it. 2288SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2289 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2290 EVT VT = N0.getValueType(); 2291 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2292 2293 // Bail early if none of these transforms apply. 2294 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2295 2296 // For each of OP in AND/OR/XOR: 2297 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2298 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2299 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2300 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2301 // 2302 // do not sink logical op inside of a vector extend, since it may combine 2303 // into a vsetcc. 2304 EVT Op0VT = N0.getOperand(0).getValueType(); 2305 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2306 N0.getOpcode() == ISD::SIGN_EXTEND || 2307 // Avoid infinite looping with PromoteIntBinOp. 2308 (N0.getOpcode() == ISD::ANY_EXTEND && 2309 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2310 (N0.getOpcode() == ISD::TRUNCATE && 2311 (!TLI.isZExtFree(VT, Op0VT) || 2312 !TLI.isTruncateFree(Op0VT, VT)) && 2313 TLI.isTypeLegal(Op0VT))) && 2314 !VT.isVector() && 2315 Op0VT == N1.getOperand(0).getValueType() && 2316 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2317 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2318 N0.getOperand(0).getValueType(), 2319 N0.getOperand(0), N1.getOperand(0)); 2320 AddToWorkList(ORNode.getNode()); 2321 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2322 } 2323 2324 // For each of OP in SHL/SRL/SRA/AND... 2325 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2326 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2327 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2328 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2329 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2330 N0.getOperand(1) == N1.getOperand(1)) { 2331 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2332 N0.getOperand(0).getValueType(), 2333 N0.getOperand(0), N1.getOperand(0)); 2334 AddToWorkList(ORNode.getNode()); 2335 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2336 ORNode, N0.getOperand(1)); 2337 } 2338 2339 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2340 // Only perform this optimization after type legalization and before 2341 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2342 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2343 // we don't want to undo this promotion. 2344 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2345 // on scalars. 2346 if ((N0.getOpcode() == ISD::BITCAST || N0.getOpcode() == ISD::SCALAR_TO_VECTOR) 2347 && Level == AfterLegalizeVectorOps) { 2348 SDValue In0 = N0.getOperand(0); 2349 SDValue In1 = N1.getOperand(0); 2350 EVT In0Ty = In0.getValueType(); 2351 EVT In1Ty = In1.getValueType(); 2352 // If both incoming values are integers, and the original types are the same. 2353 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2354 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), In0Ty, In0, In1); 2355 SDValue BC = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, Op); 2356 AddToWorkList(Op.getNode()); 2357 return BC; 2358 } 2359 } 2360 2361 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2362 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2363 // If both shuffles use the same mask, and both shuffle within a single 2364 // vector, then it is worthwhile to move the swizzle after the operation. 2365 // The type-legalizer generates this pattern when loading illegal 2366 // vector types from memory. In many cases this allows additional shuffle 2367 // optimizations. 2368 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) { 2369 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2370 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2371 SDValue In0 = SVN0->getOperand(0); 2372 SDValue In1 = SVN1->getOperand(0); 2373 EVT In0Ty = In0.getValueType(); 2374 EVT In1Ty = In1.getValueType(); 2375 2376 unsigned NumElts = VT.getVectorNumElements(); 2377 // Check that both shuffles are swizzles. 2378 bool SingleVecShuff = (N0.getOperand(1).getOpcode() == ISD::UNDEF && 2379 N1.getOperand(1).getOpcode() == ISD::UNDEF); 2380 2381 // Check that both shuffles use the same mask. The masks are known to be of 2382 // the same length because the result vector type is the same. 2383 bool SameMask = true; 2384 for (unsigned i = 0; i != NumElts; ++i) { 2385 int Idx0 = SVN0->getMaskElt(i); 2386 int Idx1 = SVN1->getMaskElt(i); 2387 if (Idx0 != Idx1) { 2388 SameMask = false; 2389 break; 2390 } 2391 } 2392 2393 if (SameMask && SingleVecShuff && In0Ty == In1Ty) { 2394 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, In0, In1); 2395 SDValue Shuff = DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2396 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2397 AddToWorkList(Op.getNode()); 2398 return Shuff; 2399 } 2400 } 2401 return SDValue(); 2402} 2403 2404SDValue DAGCombiner::visitAND(SDNode *N) { 2405 SDValue N0 = N->getOperand(0); 2406 SDValue N1 = N->getOperand(1); 2407 SDValue LL, LR, RL, RR, CC0, CC1; 2408 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2409 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2410 EVT VT = N1.getValueType(); 2411 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2412 2413 // fold vector ops 2414 if (VT.isVector()) { 2415 SDValue FoldedVOp = SimplifyVBinOp(N); 2416 if (FoldedVOp.getNode()) return FoldedVOp; 2417 } 2418 2419 // fold (and x, undef) -> 0 2420 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2421 return DAG.getConstant(0, VT); 2422 // fold (and c1, c2) -> c1&c2 2423 if (N0C && N1C) 2424 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2425 // canonicalize constant to RHS 2426 if (N0C && !N1C) 2427 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2428 // fold (and x, -1) -> x 2429 if (N1C && N1C->isAllOnesValue()) 2430 return N0; 2431 // if (and x, c) is known to be zero, return 0 2432 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2433 APInt::getAllOnesValue(BitWidth))) 2434 return DAG.getConstant(0, VT); 2435 // reassociate and 2436 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2437 if (RAND.getNode() != 0) 2438 return RAND; 2439 // fold (and (or x, C), D) -> D if (C & D) == D 2440 if (N1C && N0.getOpcode() == ISD::OR) 2441 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2442 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2443 return N1; 2444 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2445 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2446 SDValue N0Op0 = N0.getOperand(0); 2447 APInt Mask = ~N1C->getAPIntValue(); 2448 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2449 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2450 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2451 N0.getValueType(), N0Op0); 2452 2453 // Replace uses of the AND with uses of the Zero extend node. 2454 CombineTo(N, Zext); 2455 2456 // We actually want to replace all uses of the any_extend with the 2457 // zero_extend, to avoid duplicating things. This will later cause this 2458 // AND to be folded. 2459 CombineTo(N0.getNode(), Zext); 2460 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2461 } 2462 } 2463 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2464 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2465 // already be zero by virtue of the width of the base type of the load. 2466 // 2467 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2468 // more cases. 2469 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2470 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2471 N0.getOpcode() == ISD::LOAD) { 2472 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2473 N0 : N0.getOperand(0) ); 2474 2475 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2476 // This can be a pure constant or a vector splat, in which case we treat the 2477 // vector as a scalar and use the splat value. 2478 APInt Constant = APInt::getNullValue(1); 2479 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2480 Constant = C->getAPIntValue(); 2481 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2482 APInt SplatValue, SplatUndef; 2483 unsigned SplatBitSize; 2484 bool HasAnyUndefs; 2485 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2486 SplatBitSize, HasAnyUndefs); 2487 if (IsSplat) { 2488 // Undef bits can contribute to a possible optimisation if set, so 2489 // set them. 2490 SplatValue |= SplatUndef; 2491 2492 // The splat value may be something like "0x00FFFFFF", which means 0 for 2493 // the first vector value and FF for the rest, repeating. We need a mask 2494 // that will apply equally to all members of the vector, so AND all the 2495 // lanes of the constant together. 2496 EVT VT = Vector->getValueType(0); 2497 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2498 Constant = APInt::getAllOnesValue(BitWidth); 2499 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i) 2500 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2501 } 2502 } 2503 2504 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2505 // actually legal and isn't going to get expanded, else this is a false 2506 // optimisation. 2507 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2508 Load->getMemoryVT()); 2509 2510 // Resize the constant to the same size as the original memory access before 2511 // extension. If it is still the AllOnesValue then this AND is completely 2512 // unneeded. 2513 Constant = 2514 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2515 2516 bool B; 2517 switch (Load->getExtensionType()) { 2518 default: B = false; break; 2519 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2520 case ISD::ZEXTLOAD: 2521 case ISD::NON_EXTLOAD: B = true; break; 2522 } 2523 2524 if (B && Constant.isAllOnesValue()) { 2525 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2526 // preserve semantics once we get rid of the AND. 2527 SDValue NewLoad(Load, 0); 2528 if (Load->getExtensionType() == ISD::EXTLOAD) { 2529 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2530 Load->getValueType(0), Load->getDebugLoc(), 2531 Load->getChain(), Load->getBasePtr(), 2532 Load->getOffset(), Load->getMemoryVT(), 2533 Load->getMemOperand()); 2534 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2535 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2536 } 2537 2538 // Fold the AND away, taking care not to fold to the old load node if we 2539 // replaced it. 2540 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2541 2542 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2543 } 2544 } 2545 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2546 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2547 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2548 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2549 2550 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2551 LL.getValueType().isInteger()) { 2552 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2553 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2554 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2555 LR.getValueType(), LL, RL); 2556 AddToWorkList(ORNode.getNode()); 2557 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2558 } 2559 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2560 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2561 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2562 LR.getValueType(), LL, RL); 2563 AddToWorkList(ANDNode.getNode()); 2564 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2565 } 2566 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2567 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2568 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2569 LR.getValueType(), LL, RL); 2570 AddToWorkList(ORNode.getNode()); 2571 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2572 } 2573 } 2574 // canonicalize equivalent to ll == rl 2575 if (LL == RR && LR == RL) { 2576 Op1 = ISD::getSetCCSwappedOperands(Op1); 2577 std::swap(RL, RR); 2578 } 2579 if (LL == RL && LR == RR) { 2580 bool isInteger = LL.getValueType().isInteger(); 2581 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2582 if (Result != ISD::SETCC_INVALID && 2583 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2584 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2585 LL, LR, Result); 2586 } 2587 } 2588 2589 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2590 if (N0.getOpcode() == N1.getOpcode()) { 2591 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2592 if (Tmp.getNode()) return Tmp; 2593 } 2594 2595 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2596 // fold (and (sra)) -> (and (srl)) when possible. 2597 if (!VT.isVector() && 2598 SimplifyDemandedBits(SDValue(N, 0))) 2599 return SDValue(N, 0); 2600 2601 // fold (zext_inreg (extload x)) -> (zextload x) 2602 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2603 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2604 EVT MemVT = LN0->getMemoryVT(); 2605 // If we zero all the possible extended bits, then we can turn this into 2606 // a zextload if we are running before legalize or the operation is legal. 2607 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2608 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2609 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2610 ((!LegalOperations && !LN0->isVolatile()) || 2611 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2612 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2613 LN0->getChain(), LN0->getBasePtr(), 2614 LN0->getPointerInfo(), MemVT, 2615 LN0->isVolatile(), LN0->isNonTemporal(), 2616 LN0->getAlignment()); 2617 AddToWorkList(N); 2618 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2619 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2620 } 2621 } 2622 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2623 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2624 N0.hasOneUse()) { 2625 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2626 EVT MemVT = LN0->getMemoryVT(); 2627 // If we zero all the possible extended bits, then we can turn this into 2628 // a zextload if we are running before legalize or the operation is legal. 2629 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2630 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2631 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2632 ((!LegalOperations && !LN0->isVolatile()) || 2633 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2634 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2635 LN0->getChain(), 2636 LN0->getBasePtr(), LN0->getPointerInfo(), 2637 MemVT, 2638 LN0->isVolatile(), LN0->isNonTemporal(), 2639 LN0->getAlignment()); 2640 AddToWorkList(N); 2641 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2642 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2643 } 2644 } 2645 2646 // fold (and (load x), 255) -> (zextload x, i8) 2647 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2648 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2649 if (N1C && (N0.getOpcode() == ISD::LOAD || 2650 (N0.getOpcode() == ISD::ANY_EXTEND && 2651 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2652 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2653 LoadSDNode *LN0 = HasAnyExt 2654 ? cast<LoadSDNode>(N0.getOperand(0)) 2655 : cast<LoadSDNode>(N0); 2656 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2657 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2658 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2659 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2660 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2661 EVT LoadedVT = LN0->getMemoryVT(); 2662 2663 if (ExtVT == LoadedVT && 2664 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2665 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2666 2667 SDValue NewLoad = 2668 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2669 LN0->getChain(), LN0->getBasePtr(), 2670 LN0->getPointerInfo(), 2671 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2672 LN0->getAlignment()); 2673 AddToWorkList(N); 2674 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2675 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2676 } 2677 2678 // Do not change the width of a volatile load. 2679 // Do not generate loads of non-round integer types since these can 2680 // be expensive (and would be wrong if the type is not byte sized). 2681 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2682 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2683 EVT PtrType = LN0->getOperand(1).getValueType(); 2684 2685 unsigned Alignment = LN0->getAlignment(); 2686 SDValue NewPtr = LN0->getBasePtr(); 2687 2688 // For big endian targets, we need to add an offset to the pointer 2689 // to load the correct bytes. For little endian systems, we merely 2690 // need to read fewer bytes from the same pointer. 2691 if (TLI.isBigEndian()) { 2692 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2693 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2694 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2695 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2696 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2697 Alignment = MinAlign(Alignment, PtrOff); 2698 } 2699 2700 AddToWorkList(NewPtr.getNode()); 2701 2702 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2703 SDValue Load = 2704 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2705 LN0->getChain(), NewPtr, 2706 LN0->getPointerInfo(), 2707 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2708 Alignment); 2709 AddToWorkList(N); 2710 CombineTo(LN0, Load, Load.getValue(1)); 2711 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2712 } 2713 } 2714 } 2715 } 2716 2717 return SDValue(); 2718} 2719 2720/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2721/// 2722SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2723 bool DemandHighBits) { 2724 if (!LegalOperations) 2725 return SDValue(); 2726 2727 EVT VT = N->getValueType(0); 2728 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2729 return SDValue(); 2730 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2731 return SDValue(); 2732 2733 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2734 bool LookPassAnd0 = false; 2735 bool LookPassAnd1 = false; 2736 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2737 std::swap(N0, N1); 2738 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2739 std::swap(N0, N1); 2740 if (N0.getOpcode() == ISD::AND) { 2741 if (!N0.getNode()->hasOneUse()) 2742 return SDValue(); 2743 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2744 if (!N01C || N01C->getZExtValue() != 0xFF00) 2745 return SDValue(); 2746 N0 = N0.getOperand(0); 2747 LookPassAnd0 = true; 2748 } 2749 2750 if (N1.getOpcode() == ISD::AND) { 2751 if (!N1.getNode()->hasOneUse()) 2752 return SDValue(); 2753 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2754 if (!N11C || N11C->getZExtValue() != 0xFF) 2755 return SDValue(); 2756 N1 = N1.getOperand(0); 2757 LookPassAnd1 = true; 2758 } 2759 2760 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2761 std::swap(N0, N1); 2762 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2763 return SDValue(); 2764 if (!N0.getNode()->hasOneUse() || 2765 !N1.getNode()->hasOneUse()) 2766 return SDValue(); 2767 2768 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2769 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2770 if (!N01C || !N11C) 2771 return SDValue(); 2772 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2773 return SDValue(); 2774 2775 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2776 SDValue N00 = N0->getOperand(0); 2777 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2778 if (!N00.getNode()->hasOneUse()) 2779 return SDValue(); 2780 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2781 if (!N001C || N001C->getZExtValue() != 0xFF) 2782 return SDValue(); 2783 N00 = N00.getOperand(0); 2784 LookPassAnd0 = true; 2785 } 2786 2787 SDValue N10 = N1->getOperand(0); 2788 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2789 if (!N10.getNode()->hasOneUse()) 2790 return SDValue(); 2791 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2792 if (!N101C || N101C->getZExtValue() != 0xFF00) 2793 return SDValue(); 2794 N10 = N10.getOperand(0); 2795 LookPassAnd1 = true; 2796 } 2797 2798 if (N00 != N10) 2799 return SDValue(); 2800 2801 // Make sure everything beyond the low halfword is zero since the SRL 16 2802 // will clear the top bits. 2803 unsigned OpSizeInBits = VT.getSizeInBits(); 2804 if (DemandHighBits && OpSizeInBits > 16 && 2805 (!LookPassAnd0 || !LookPassAnd1) && 2806 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2807 return SDValue(); 2808 2809 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2810 if (OpSizeInBits > 16) 2811 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2812 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2813 return Res; 2814} 2815 2816/// isBSwapHWordElement - Return true if the specified node is an element 2817/// that makes up a 32-bit packed halfword byteswap. i.e. 2818/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2819static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2820 if (!N.getNode()->hasOneUse()) 2821 return false; 2822 2823 unsigned Opc = N.getOpcode(); 2824 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2825 return false; 2826 2827 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2828 if (!N1C) 2829 return false; 2830 2831 unsigned Num; 2832 switch (N1C->getZExtValue()) { 2833 default: 2834 return false; 2835 case 0xFF: Num = 0; break; 2836 case 0xFF00: Num = 1; break; 2837 case 0xFF0000: Num = 2; break; 2838 case 0xFF000000: Num = 3; break; 2839 } 2840 2841 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2842 SDValue N0 = N.getOperand(0); 2843 if (Opc == ISD::AND) { 2844 if (Num == 0 || Num == 2) { 2845 // (x >> 8) & 0xff 2846 // (x >> 8) & 0xff0000 2847 if (N0.getOpcode() != ISD::SRL) 2848 return false; 2849 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2850 if (!C || C->getZExtValue() != 8) 2851 return false; 2852 } else { 2853 // (x << 8) & 0xff00 2854 // (x << 8) & 0xff000000 2855 if (N0.getOpcode() != ISD::SHL) 2856 return false; 2857 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2858 if (!C || C->getZExtValue() != 8) 2859 return false; 2860 } 2861 } else if (Opc == ISD::SHL) { 2862 // (x & 0xff) << 8 2863 // (x & 0xff0000) << 8 2864 if (Num != 0 && Num != 2) 2865 return false; 2866 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2867 if (!C || C->getZExtValue() != 8) 2868 return false; 2869 } else { // Opc == ISD::SRL 2870 // (x & 0xff00) >> 8 2871 // (x & 0xff000000) >> 8 2872 if (Num != 1 && Num != 3) 2873 return false; 2874 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2875 if (!C || C->getZExtValue() != 8) 2876 return false; 2877 } 2878 2879 if (Parts[Num]) 2880 return false; 2881 2882 Parts[Num] = N0.getOperand(0).getNode(); 2883 return true; 2884} 2885 2886/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2887/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2888/// => (rotl (bswap x), 16) 2889SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2890 if (!LegalOperations) 2891 return SDValue(); 2892 2893 EVT VT = N->getValueType(0); 2894 if (VT != MVT::i32) 2895 return SDValue(); 2896 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2897 return SDValue(); 2898 2899 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2900 // Look for either 2901 // (or (or (and), (and)), (or (and), (and))) 2902 // (or (or (or (and), (and)), (and)), (and)) 2903 if (N0.getOpcode() != ISD::OR) 2904 return SDValue(); 2905 SDValue N00 = N0.getOperand(0); 2906 SDValue N01 = N0.getOperand(1); 2907 2908 if (N1.getOpcode() == ISD::OR) { 2909 // (or (or (and), (and)), (or (and), (and))) 2910 SDValue N000 = N00.getOperand(0); 2911 if (!isBSwapHWordElement(N000, Parts)) 2912 return SDValue(); 2913 2914 SDValue N001 = N00.getOperand(1); 2915 if (!isBSwapHWordElement(N001, Parts)) 2916 return SDValue(); 2917 SDValue N010 = N01.getOperand(0); 2918 if (!isBSwapHWordElement(N010, Parts)) 2919 return SDValue(); 2920 SDValue N011 = N01.getOperand(1); 2921 if (!isBSwapHWordElement(N011, Parts)) 2922 return SDValue(); 2923 } else { 2924 // (or (or (or (and), (and)), (and)), (and)) 2925 if (!isBSwapHWordElement(N1, Parts)) 2926 return SDValue(); 2927 if (!isBSwapHWordElement(N01, Parts)) 2928 return SDValue(); 2929 if (N00.getOpcode() != ISD::OR) 2930 return SDValue(); 2931 SDValue N000 = N00.getOperand(0); 2932 if (!isBSwapHWordElement(N000, Parts)) 2933 return SDValue(); 2934 SDValue N001 = N00.getOperand(1); 2935 if (!isBSwapHWordElement(N001, Parts)) 2936 return SDValue(); 2937 } 2938 2939 // Make sure the parts are all coming from the same node. 2940 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2941 return SDValue(); 2942 2943 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2944 SDValue(Parts[0],0)); 2945 2946 // Result of the bswap should be rotated by 16. If it's not legal, than 2947 // do (x << 16) | (x >> 16). 2948 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2949 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2950 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2951 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2952 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 2953 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 2954 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 2955 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 2956} 2957 2958SDValue DAGCombiner::visitOR(SDNode *N) { 2959 SDValue N0 = N->getOperand(0); 2960 SDValue N1 = N->getOperand(1); 2961 SDValue LL, LR, RL, RR, CC0, CC1; 2962 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2963 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2964 EVT VT = N1.getValueType(); 2965 2966 // fold vector ops 2967 if (VT.isVector()) { 2968 SDValue FoldedVOp = SimplifyVBinOp(N); 2969 if (FoldedVOp.getNode()) return FoldedVOp; 2970 } 2971 2972 // fold (or x, undef) -> -1 2973 if (!LegalOperations && 2974 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2975 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2976 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2977 } 2978 // fold (or c1, c2) -> c1|c2 2979 if (N0C && N1C) 2980 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2981 // canonicalize constant to RHS 2982 if (N0C && !N1C) 2983 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2984 // fold (or x, 0) -> x 2985 if (N1C && N1C->isNullValue()) 2986 return N0; 2987 // fold (or x, -1) -> -1 2988 if (N1C && N1C->isAllOnesValue()) 2989 return N1; 2990 // fold (or x, c) -> c iff (x & ~c) == 0 2991 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2992 return N1; 2993 2994 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 2995 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 2996 if (BSwap.getNode() != 0) 2997 return BSwap; 2998 BSwap = MatchBSwapHWordLow(N, N0, N1); 2999 if (BSwap.getNode() != 0) 3000 return BSwap; 3001 3002 // reassociate or 3003 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3004 if (ROR.getNode() != 0) 3005 return ROR; 3006 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3007 // iff (c1 & c2) == 0. 3008 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3009 isa<ConstantSDNode>(N0.getOperand(1))) { 3010 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3011 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3012 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3013 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3014 N0.getOperand(0), N1), 3015 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3016 } 3017 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3018 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3019 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3020 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3021 3022 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3023 LL.getValueType().isInteger()) { 3024 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3025 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3026 if (cast<ConstantSDNode>(LR)->isNullValue() && 3027 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3028 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3029 LR.getValueType(), LL, RL); 3030 AddToWorkList(ORNode.getNode()); 3031 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3032 } 3033 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3034 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3035 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3036 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3037 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3038 LR.getValueType(), LL, RL); 3039 AddToWorkList(ANDNode.getNode()); 3040 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3041 } 3042 } 3043 // canonicalize equivalent to ll == rl 3044 if (LL == RR && LR == RL) { 3045 Op1 = ISD::getSetCCSwappedOperands(Op1); 3046 std::swap(RL, RR); 3047 } 3048 if (LL == RL && LR == RR) { 3049 bool isInteger = LL.getValueType().isInteger(); 3050 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3051 if (Result != ISD::SETCC_INVALID && 3052 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3053 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3054 LL, LR, Result); 3055 } 3056 } 3057 3058 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3059 if (N0.getOpcode() == N1.getOpcode()) { 3060 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3061 if (Tmp.getNode()) return Tmp; 3062 } 3063 3064 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3065 if (N0.getOpcode() == ISD::AND && 3066 N1.getOpcode() == ISD::AND && 3067 N0.getOperand(1).getOpcode() == ISD::Constant && 3068 N1.getOperand(1).getOpcode() == ISD::Constant && 3069 // Don't increase # computations. 3070 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3071 // We can only do this xform if we know that bits from X that are set in C2 3072 // but not in C1 are already zero. Likewise for Y. 3073 const APInt &LHSMask = 3074 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3075 const APInt &RHSMask = 3076 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3077 3078 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3079 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3080 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3081 N0.getOperand(0), N1.getOperand(0)); 3082 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3083 DAG.getConstant(LHSMask | RHSMask, VT)); 3084 } 3085 } 3086 3087 // See if this is some rotate idiom. 3088 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3089 return SDValue(Rot, 0); 3090 3091 // Simplify the operands using demanded-bits information. 3092 if (!VT.isVector() && 3093 SimplifyDemandedBits(SDValue(N, 0))) 3094 return SDValue(N, 0); 3095 3096 return SDValue(); 3097} 3098 3099/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3100static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3101 if (Op.getOpcode() == ISD::AND) { 3102 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3103 Mask = Op.getOperand(1); 3104 Op = Op.getOperand(0); 3105 } else { 3106 return false; 3107 } 3108 } 3109 3110 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3111 Shift = Op; 3112 return true; 3113 } 3114 3115 return false; 3116} 3117 3118// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3119// idioms for rotate, and if the target supports rotation instructions, generate 3120// a rot[lr]. 3121SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3122 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3123 EVT VT = LHS.getValueType(); 3124 if (!TLI.isTypeLegal(VT)) return 0; 3125 3126 // The target must have at least one rotate flavor. 3127 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3128 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3129 if (!HasROTL && !HasROTR) return 0; 3130 3131 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3132 SDValue LHSShift; // The shift. 3133 SDValue LHSMask; // AND value if any. 3134 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3135 return 0; // Not part of a rotate. 3136 3137 SDValue RHSShift; // The shift. 3138 SDValue RHSMask; // AND value if any. 3139 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3140 return 0; // Not part of a rotate. 3141 3142 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3143 return 0; // Not shifting the same value. 3144 3145 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3146 return 0; // Shifts must disagree. 3147 3148 // Canonicalize shl to left side in a shl/srl pair. 3149 if (RHSShift.getOpcode() == ISD::SHL) { 3150 std::swap(LHS, RHS); 3151 std::swap(LHSShift, RHSShift); 3152 std::swap(LHSMask , RHSMask ); 3153 } 3154 3155 unsigned OpSizeInBits = VT.getSizeInBits(); 3156 SDValue LHSShiftArg = LHSShift.getOperand(0); 3157 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3158 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3159 3160 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3161 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3162 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3163 RHSShiftAmt.getOpcode() == ISD::Constant) { 3164 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3165 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3166 if ((LShVal + RShVal) != OpSizeInBits) 3167 return 0; 3168 3169 SDValue Rot; 3170 if (HasROTL) 3171 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 3172 else 3173 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 3174 3175 // If there is an AND of either shifted operand, apply it to the result. 3176 if (LHSMask.getNode() || RHSMask.getNode()) { 3177 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3178 3179 if (LHSMask.getNode()) { 3180 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3181 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3182 } 3183 if (RHSMask.getNode()) { 3184 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3185 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3186 } 3187 3188 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3189 } 3190 3191 return Rot.getNode(); 3192 } 3193 3194 // If there is a mask here, and we have a variable shift, we can't be sure 3195 // that we're masking out the right stuff. 3196 if (LHSMask.getNode() || RHSMask.getNode()) 3197 return 0; 3198 3199 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3200 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3201 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3202 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3203 if (ConstantSDNode *SUBC = 3204 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3205 if (SUBC->getAPIntValue() == OpSizeInBits) { 3206 if (HasROTL) 3207 return DAG.getNode(ISD::ROTL, DL, VT, 3208 LHSShiftArg, LHSShiftAmt).getNode(); 3209 else 3210 return DAG.getNode(ISD::ROTR, DL, VT, 3211 LHSShiftArg, RHSShiftAmt).getNode(); 3212 } 3213 } 3214 } 3215 3216 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3217 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3218 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3219 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3220 if (ConstantSDNode *SUBC = 3221 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3222 if (SUBC->getAPIntValue() == OpSizeInBits) { 3223 if (HasROTR) 3224 return DAG.getNode(ISD::ROTR, DL, VT, 3225 LHSShiftArg, RHSShiftAmt).getNode(); 3226 else 3227 return DAG.getNode(ISD::ROTL, DL, VT, 3228 LHSShiftArg, LHSShiftAmt).getNode(); 3229 } 3230 } 3231 } 3232 3233 // Look for sign/zext/any-extended or truncate cases: 3234 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3235 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3236 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3237 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3238 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3239 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3240 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3241 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3242 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3243 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3244 if (RExtOp0.getOpcode() == ISD::SUB && 3245 RExtOp0.getOperand(1) == LExtOp0) { 3246 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3247 // (rotl x, y) 3248 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3249 // (rotr x, (sub 32, y)) 3250 if (ConstantSDNode *SUBC = 3251 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3252 if (SUBC->getAPIntValue() == OpSizeInBits) { 3253 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3254 LHSShiftArg, 3255 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3256 } 3257 } 3258 } else if (LExtOp0.getOpcode() == ISD::SUB && 3259 RExtOp0 == LExtOp0.getOperand(1)) { 3260 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3261 // (rotr x, y) 3262 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3263 // (rotl x, (sub 32, y)) 3264 if (ConstantSDNode *SUBC = 3265 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3266 if (SUBC->getAPIntValue() == OpSizeInBits) { 3267 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3268 LHSShiftArg, 3269 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3270 } 3271 } 3272 } 3273 } 3274 3275 return 0; 3276} 3277 3278SDValue DAGCombiner::visitXOR(SDNode *N) { 3279 SDValue N0 = N->getOperand(0); 3280 SDValue N1 = N->getOperand(1); 3281 SDValue LHS, RHS, CC; 3282 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3283 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3284 EVT VT = N0.getValueType(); 3285 3286 // fold vector ops 3287 if (VT.isVector()) { 3288 SDValue FoldedVOp = SimplifyVBinOp(N); 3289 if (FoldedVOp.getNode()) return FoldedVOp; 3290 } 3291 3292 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3293 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3294 return DAG.getConstant(0, VT); 3295 // fold (xor x, undef) -> undef 3296 if (N0.getOpcode() == ISD::UNDEF) 3297 return N0; 3298 if (N1.getOpcode() == ISD::UNDEF) 3299 return N1; 3300 // fold (xor c1, c2) -> c1^c2 3301 if (N0C && N1C) 3302 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3303 // canonicalize constant to RHS 3304 if (N0C && !N1C) 3305 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3306 // fold (xor x, 0) -> x 3307 if (N1C && N1C->isNullValue()) 3308 return N0; 3309 // reassociate xor 3310 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3311 if (RXOR.getNode() != 0) 3312 return RXOR; 3313 3314 // fold !(x cc y) -> (x !cc y) 3315 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3316 bool isInt = LHS.getValueType().isInteger(); 3317 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3318 isInt); 3319 3320 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3321 switch (N0.getOpcode()) { 3322 default: 3323 llvm_unreachable("Unhandled SetCC Equivalent!"); 3324 case ISD::SETCC: 3325 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3326 case ISD::SELECT_CC: 3327 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3328 N0.getOperand(3), NotCC); 3329 } 3330 } 3331 } 3332 3333 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3334 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3335 N0.getNode()->hasOneUse() && 3336 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3337 SDValue V = N0.getOperand(0); 3338 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3339 DAG.getConstant(1, V.getValueType())); 3340 AddToWorkList(V.getNode()); 3341 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3342 } 3343 3344 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3345 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3346 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3347 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3348 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3349 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3350 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3351 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3352 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3353 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3354 } 3355 } 3356 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3357 if (N1C && N1C->isAllOnesValue() && 3358 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3359 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3360 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3361 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3362 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3363 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3364 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3365 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3366 } 3367 } 3368 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3369 if (N1C && N0.getOpcode() == ISD::XOR) { 3370 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3371 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3372 if (N00C) 3373 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3374 DAG.getConstant(N1C->getAPIntValue() ^ 3375 N00C->getAPIntValue(), VT)); 3376 if (N01C) 3377 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3378 DAG.getConstant(N1C->getAPIntValue() ^ 3379 N01C->getAPIntValue(), VT)); 3380 } 3381 // fold (xor x, x) -> 0 3382 if (N0 == N1) 3383 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3384 3385 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3386 if (N0.getOpcode() == N1.getOpcode()) { 3387 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3388 if (Tmp.getNode()) return Tmp; 3389 } 3390 3391 // Simplify the expression using non-local knowledge. 3392 if (!VT.isVector() && 3393 SimplifyDemandedBits(SDValue(N, 0))) 3394 return SDValue(N, 0); 3395 3396 return SDValue(); 3397} 3398 3399/// visitShiftByConstant - Handle transforms common to the three shifts, when 3400/// the shift amount is a constant. 3401SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3402 SDNode *LHS = N->getOperand(0).getNode(); 3403 if (!LHS->hasOneUse()) return SDValue(); 3404 3405 // We want to pull some binops through shifts, so that we have (and (shift)) 3406 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3407 // thing happens with address calculations, so it's important to canonicalize 3408 // it. 3409 bool HighBitSet = false; // Can we transform this if the high bit is set? 3410 3411 switch (LHS->getOpcode()) { 3412 default: return SDValue(); 3413 case ISD::OR: 3414 case ISD::XOR: 3415 HighBitSet = false; // We can only transform sra if the high bit is clear. 3416 break; 3417 case ISD::AND: 3418 HighBitSet = true; // We can only transform sra if the high bit is set. 3419 break; 3420 case ISD::ADD: 3421 if (N->getOpcode() != ISD::SHL) 3422 return SDValue(); // only shl(add) not sr[al](add). 3423 HighBitSet = false; // We can only transform sra if the high bit is clear. 3424 break; 3425 } 3426 3427 // We require the RHS of the binop to be a constant as well. 3428 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3429 if (!BinOpCst) return SDValue(); 3430 3431 // FIXME: disable this unless the input to the binop is a shift by a constant. 3432 // If it is not a shift, it pessimizes some common cases like: 3433 // 3434 // void foo(int *X, int i) { X[i & 1235] = 1; } 3435 // int bar(int *X, int i) { return X[i & 255]; } 3436 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3437 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3438 BinOpLHSVal->getOpcode() != ISD::SRA && 3439 BinOpLHSVal->getOpcode() != ISD::SRL) || 3440 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3441 return SDValue(); 3442 3443 EVT VT = N->getValueType(0); 3444 3445 // If this is a signed shift right, and the high bit is modified by the 3446 // logical operation, do not perform the transformation. The highBitSet 3447 // boolean indicates the value of the high bit of the constant which would 3448 // cause it to be modified for this operation. 3449 if (N->getOpcode() == ISD::SRA) { 3450 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3451 if (BinOpRHSSignSet != HighBitSet) 3452 return SDValue(); 3453 } 3454 3455 // Fold the constants, shifting the binop RHS by the shift amount. 3456 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3457 N->getValueType(0), 3458 LHS->getOperand(1), N->getOperand(1)); 3459 3460 // Create the new shift. 3461 SDValue NewShift = DAG.getNode(N->getOpcode(), 3462 LHS->getOperand(0).getDebugLoc(), 3463 VT, LHS->getOperand(0), N->getOperand(1)); 3464 3465 // Create the new binop. 3466 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3467} 3468 3469SDValue DAGCombiner::visitSHL(SDNode *N) { 3470 SDValue N0 = N->getOperand(0); 3471 SDValue N1 = N->getOperand(1); 3472 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3473 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3474 EVT VT = N0.getValueType(); 3475 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3476 3477 // fold (shl c1, c2) -> c1<<c2 3478 if (N0C && N1C) 3479 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3480 // fold (shl 0, x) -> 0 3481 if (N0C && N0C->isNullValue()) 3482 return N0; 3483 // fold (shl x, c >= size(x)) -> undef 3484 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3485 return DAG.getUNDEF(VT); 3486 // fold (shl x, 0) -> x 3487 if (N1C && N1C->isNullValue()) 3488 return N0; 3489 // fold (shl undef, x) -> 0 3490 if (N0.getOpcode() == ISD::UNDEF) 3491 return DAG.getConstant(0, VT); 3492 // if (shl x, c) is known to be zero, return 0 3493 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3494 APInt::getAllOnesValue(OpSizeInBits))) 3495 return DAG.getConstant(0, VT); 3496 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3497 if (N1.getOpcode() == ISD::TRUNCATE && 3498 N1.getOperand(0).getOpcode() == ISD::AND && 3499 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3500 SDValue N101 = N1.getOperand(0).getOperand(1); 3501 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3502 EVT TruncVT = N1.getValueType(); 3503 SDValue N100 = N1.getOperand(0).getOperand(0); 3504 APInt TruncC = N101C->getAPIntValue(); 3505 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3506 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3507 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3508 DAG.getNode(ISD::TRUNCATE, 3509 N->getDebugLoc(), 3510 TruncVT, N100), 3511 DAG.getConstant(TruncC, TruncVT))); 3512 } 3513 } 3514 3515 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3516 return SDValue(N, 0); 3517 3518 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3519 if (N1C && N0.getOpcode() == ISD::SHL && 3520 N0.getOperand(1).getOpcode() == ISD::Constant) { 3521 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3522 uint64_t c2 = N1C->getZExtValue(); 3523 if (c1 + c2 >= OpSizeInBits) 3524 return DAG.getConstant(0, VT); 3525 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3526 DAG.getConstant(c1 + c2, N1.getValueType())); 3527 } 3528 3529 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3530 // For this to be valid, the second form must not preserve any of the bits 3531 // that are shifted out by the inner shift in the first form. This means 3532 // the outer shift size must be >= the number of bits added by the ext. 3533 // As a corollary, we don't care what kind of ext it is. 3534 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3535 N0.getOpcode() == ISD::ANY_EXTEND || 3536 N0.getOpcode() == ISD::SIGN_EXTEND) && 3537 N0.getOperand(0).getOpcode() == ISD::SHL && 3538 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3539 uint64_t c1 = 3540 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3541 uint64_t c2 = N1C->getZExtValue(); 3542 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3543 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3544 if (c2 >= OpSizeInBits - InnerShiftSize) { 3545 if (c1 + c2 >= OpSizeInBits) 3546 return DAG.getConstant(0, VT); 3547 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3548 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3549 N0.getOperand(0)->getOperand(0)), 3550 DAG.getConstant(c1 + c2, N1.getValueType())); 3551 } 3552 } 3553 3554 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3555 // (and (srl x, (sub c1, c2), MASK) 3556 // Only fold this if the inner shift has no other uses -- if it does, folding 3557 // this will increase the total number of instructions. 3558 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3559 N0.getOperand(1).getOpcode() == ISD::Constant) { 3560 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3561 if (c1 < VT.getSizeInBits()) { 3562 uint64_t c2 = N1C->getZExtValue(); 3563 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3564 VT.getSizeInBits() - c1); 3565 SDValue Shift; 3566 if (c2 > c1) { 3567 Mask = Mask.shl(c2-c1); 3568 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3569 DAG.getConstant(c2-c1, N1.getValueType())); 3570 } else { 3571 Mask = Mask.lshr(c1-c2); 3572 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3573 DAG.getConstant(c1-c2, N1.getValueType())); 3574 } 3575 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3576 DAG.getConstant(Mask, VT)); 3577 } 3578 } 3579 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3580 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3581 SDValue HiBitsMask = 3582 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3583 VT.getSizeInBits() - 3584 N1C->getZExtValue()), 3585 VT); 3586 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3587 HiBitsMask); 3588 } 3589 3590 if (N1C) { 3591 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3592 if (NewSHL.getNode()) 3593 return NewSHL; 3594 } 3595 3596 return SDValue(); 3597} 3598 3599SDValue DAGCombiner::visitSRA(SDNode *N) { 3600 SDValue N0 = N->getOperand(0); 3601 SDValue N1 = N->getOperand(1); 3602 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3603 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3604 EVT VT = N0.getValueType(); 3605 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3606 3607 // fold (sra c1, c2) -> (sra c1, c2) 3608 if (N0C && N1C) 3609 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3610 // fold (sra 0, x) -> 0 3611 if (N0C && N0C->isNullValue()) 3612 return N0; 3613 // fold (sra -1, x) -> -1 3614 if (N0C && N0C->isAllOnesValue()) 3615 return N0; 3616 // fold (sra x, (setge c, size(x))) -> undef 3617 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3618 return DAG.getUNDEF(VT); 3619 // fold (sra x, 0) -> x 3620 if (N1C && N1C->isNullValue()) 3621 return N0; 3622 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3623 // sext_inreg. 3624 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3625 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3626 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3627 if (VT.isVector()) 3628 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3629 ExtVT, VT.getVectorNumElements()); 3630 if ((!LegalOperations || 3631 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3632 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3633 N0.getOperand(0), DAG.getValueType(ExtVT)); 3634 } 3635 3636 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3637 if (N1C && N0.getOpcode() == ISD::SRA) { 3638 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3639 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3640 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3641 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3642 DAG.getConstant(Sum, N1C->getValueType(0))); 3643 } 3644 } 3645 3646 // fold (sra (shl X, m), (sub result_size, n)) 3647 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3648 // result_size - n != m. 3649 // If truncate is free for the target sext(shl) is likely to result in better 3650 // code. 3651 if (N0.getOpcode() == ISD::SHL) { 3652 // Get the two constanst of the shifts, CN0 = m, CN = n. 3653 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3654 if (N01C && N1C) { 3655 // Determine what the truncate's result bitsize and type would be. 3656 EVT TruncVT = 3657 EVT::getIntegerVT(*DAG.getContext(), 3658 OpSizeInBits - N1C->getZExtValue()); 3659 // Determine the residual right-shift amount. 3660 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3661 3662 // If the shift is not a no-op (in which case this should be just a sign 3663 // extend already), the truncated to type is legal, sign_extend is legal 3664 // on that type, and the truncate to that type is both legal and free, 3665 // perform the transform. 3666 if ((ShiftAmt > 0) && 3667 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3668 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3669 TLI.isTruncateFree(VT, TruncVT)) { 3670 3671 SDValue Amt = DAG.getConstant(ShiftAmt, 3672 getShiftAmountTy(N0.getOperand(0).getValueType())); 3673 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3674 N0.getOperand(0), Amt); 3675 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3676 Shift); 3677 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3678 N->getValueType(0), Trunc); 3679 } 3680 } 3681 } 3682 3683 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3684 if (N1.getOpcode() == ISD::TRUNCATE && 3685 N1.getOperand(0).getOpcode() == ISD::AND && 3686 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3687 SDValue N101 = N1.getOperand(0).getOperand(1); 3688 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3689 EVT TruncVT = N1.getValueType(); 3690 SDValue N100 = N1.getOperand(0).getOperand(0); 3691 APInt TruncC = N101C->getAPIntValue(); 3692 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3693 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3694 DAG.getNode(ISD::AND, N->getDebugLoc(), 3695 TruncVT, 3696 DAG.getNode(ISD::TRUNCATE, 3697 N->getDebugLoc(), 3698 TruncVT, N100), 3699 DAG.getConstant(TruncC, TruncVT))); 3700 } 3701 } 3702 3703 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3704 // if c1 is equal to the number of bits the trunc removes 3705 if (N0.getOpcode() == ISD::TRUNCATE && 3706 (N0.getOperand(0).getOpcode() == ISD::SRL || 3707 N0.getOperand(0).getOpcode() == ISD::SRA) && 3708 N0.getOperand(0).hasOneUse() && 3709 N0.getOperand(0).getOperand(1).hasOneUse() && 3710 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3711 EVT LargeVT = N0.getOperand(0).getValueType(); 3712 ConstantSDNode *LargeShiftAmt = 3713 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3714 3715 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3716 LargeShiftAmt->getZExtValue()) { 3717 SDValue Amt = 3718 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3719 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3720 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3721 N0.getOperand(0).getOperand(0), Amt); 3722 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3723 } 3724 } 3725 3726 // Simplify, based on bits shifted out of the LHS. 3727 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3728 return SDValue(N, 0); 3729 3730 3731 // If the sign bit is known to be zero, switch this to a SRL. 3732 if (DAG.SignBitIsZero(N0)) 3733 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3734 3735 if (N1C) { 3736 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3737 if (NewSRA.getNode()) 3738 return NewSRA; 3739 } 3740 3741 return SDValue(); 3742} 3743 3744SDValue DAGCombiner::visitSRL(SDNode *N) { 3745 SDValue N0 = N->getOperand(0); 3746 SDValue N1 = N->getOperand(1); 3747 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3748 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3749 EVT VT = N0.getValueType(); 3750 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3751 3752 // fold (srl c1, c2) -> c1 >>u c2 3753 if (N0C && N1C) 3754 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3755 // fold (srl 0, x) -> 0 3756 if (N0C && N0C->isNullValue()) 3757 return N0; 3758 // fold (srl x, c >= size(x)) -> undef 3759 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3760 return DAG.getUNDEF(VT); 3761 // fold (srl x, 0) -> x 3762 if (N1C && N1C->isNullValue()) 3763 return N0; 3764 // if (srl x, c) is known to be zero, return 0 3765 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3766 APInt::getAllOnesValue(OpSizeInBits))) 3767 return DAG.getConstant(0, VT); 3768 3769 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3770 if (N1C && N0.getOpcode() == ISD::SRL && 3771 N0.getOperand(1).getOpcode() == ISD::Constant) { 3772 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3773 uint64_t c2 = N1C->getZExtValue(); 3774 if (c1 + c2 >= OpSizeInBits) 3775 return DAG.getConstant(0, VT); 3776 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3777 DAG.getConstant(c1 + c2, N1.getValueType())); 3778 } 3779 3780 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3781 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3782 N0.getOperand(0).getOpcode() == ISD::SRL && 3783 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3784 uint64_t c1 = 3785 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3786 uint64_t c2 = N1C->getZExtValue(); 3787 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3788 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3789 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3790 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3791 if (c1 + OpSizeInBits == InnerShiftSize) { 3792 if (c1 + c2 >= InnerShiftSize) 3793 return DAG.getConstant(0, VT); 3794 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3795 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3796 N0.getOperand(0)->getOperand(0), 3797 DAG.getConstant(c1 + c2, ShiftCountVT))); 3798 } 3799 } 3800 3801 // fold (srl (shl x, c), c) -> (and x, cst2) 3802 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3803 N0.getValueSizeInBits() <= 64) { 3804 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3805 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3806 DAG.getConstant(~0ULL >> ShAmt, VT)); 3807 } 3808 3809 3810 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3811 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3812 // Shifting in all undef bits? 3813 EVT SmallVT = N0.getOperand(0).getValueType(); 3814 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3815 return DAG.getUNDEF(VT); 3816 3817 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3818 uint64_t ShiftAmt = N1C->getZExtValue(); 3819 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3820 N0.getOperand(0), 3821 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3822 AddToWorkList(SmallShift.getNode()); 3823 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3824 } 3825 } 3826 3827 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3828 // bit, which is unmodified by sra. 3829 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3830 if (N0.getOpcode() == ISD::SRA) 3831 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3832 } 3833 3834 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3835 if (N1C && N0.getOpcode() == ISD::CTLZ && 3836 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3837 APInt KnownZero, KnownOne; 3838 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3839 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3840 3841 // If any of the input bits are KnownOne, then the input couldn't be all 3842 // zeros, thus the result of the srl will always be zero. 3843 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3844 3845 // If all of the bits input the to ctlz node are known to be zero, then 3846 // the result of the ctlz is "32" and the result of the shift is one. 3847 APInt UnknownBits = ~KnownZero & Mask; 3848 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3849 3850 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3851 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3852 // Okay, we know that only that the single bit specified by UnknownBits 3853 // could be set on input to the CTLZ node. If this bit is set, the SRL 3854 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3855 // to an SRL/XOR pair, which is likely to simplify more. 3856 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3857 SDValue Op = N0.getOperand(0); 3858 3859 if (ShAmt) { 3860 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3861 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3862 AddToWorkList(Op.getNode()); 3863 } 3864 3865 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3866 Op, DAG.getConstant(1, VT)); 3867 } 3868 } 3869 3870 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3871 if (N1.getOpcode() == ISD::TRUNCATE && 3872 N1.getOperand(0).getOpcode() == ISD::AND && 3873 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3874 SDValue N101 = N1.getOperand(0).getOperand(1); 3875 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3876 EVT TruncVT = N1.getValueType(); 3877 SDValue N100 = N1.getOperand(0).getOperand(0); 3878 APInt TruncC = N101C->getAPIntValue(); 3879 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3880 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3881 DAG.getNode(ISD::AND, N->getDebugLoc(), 3882 TruncVT, 3883 DAG.getNode(ISD::TRUNCATE, 3884 N->getDebugLoc(), 3885 TruncVT, N100), 3886 DAG.getConstant(TruncC, TruncVT))); 3887 } 3888 } 3889 3890 // fold operands of srl based on knowledge that the low bits are not 3891 // demanded. 3892 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3893 return SDValue(N, 0); 3894 3895 if (N1C) { 3896 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3897 if (NewSRL.getNode()) 3898 return NewSRL; 3899 } 3900 3901 // Attempt to convert a srl of a load into a narrower zero-extending load. 3902 SDValue NarrowLoad = ReduceLoadWidth(N); 3903 if (NarrowLoad.getNode()) 3904 return NarrowLoad; 3905 3906 // Here is a common situation. We want to optimize: 3907 // 3908 // %a = ... 3909 // %b = and i32 %a, 2 3910 // %c = srl i32 %b, 1 3911 // brcond i32 %c ... 3912 // 3913 // into 3914 // 3915 // %a = ... 3916 // %b = and %a, 2 3917 // %c = setcc eq %b, 0 3918 // brcond %c ... 3919 // 3920 // However when after the source operand of SRL is optimized into AND, the SRL 3921 // itself may not be optimized further. Look for it and add the BRCOND into 3922 // the worklist. 3923 if (N->hasOneUse()) { 3924 SDNode *Use = *N->use_begin(); 3925 if (Use->getOpcode() == ISD::BRCOND) 3926 AddToWorkList(Use); 3927 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3928 // Also look pass the truncate. 3929 Use = *Use->use_begin(); 3930 if (Use->getOpcode() == ISD::BRCOND) 3931 AddToWorkList(Use); 3932 } 3933 } 3934 3935 return SDValue(); 3936} 3937 3938SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3939 SDValue N0 = N->getOperand(0); 3940 EVT VT = N->getValueType(0); 3941 3942 // fold (ctlz c1) -> c2 3943 if (isa<ConstantSDNode>(N0)) 3944 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3945 return SDValue(); 3946} 3947 3948SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3949 SDValue N0 = N->getOperand(0); 3950 EVT VT = N->getValueType(0); 3951 3952 // fold (ctlz_zero_undef c1) -> c2 3953 if (isa<ConstantSDNode>(N0)) 3954 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3955 return SDValue(); 3956} 3957 3958SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3959 SDValue N0 = N->getOperand(0); 3960 EVT VT = N->getValueType(0); 3961 3962 // fold (cttz c1) -> c2 3963 if (isa<ConstantSDNode>(N0)) 3964 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3965 return SDValue(); 3966} 3967 3968SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 3969 SDValue N0 = N->getOperand(0); 3970 EVT VT = N->getValueType(0); 3971 3972 // fold (cttz_zero_undef c1) -> c2 3973 if (isa<ConstantSDNode>(N0)) 3974 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3975 return SDValue(); 3976} 3977 3978SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3979 SDValue N0 = N->getOperand(0); 3980 EVT VT = N->getValueType(0); 3981 3982 // fold (ctpop c1) -> c2 3983 if (isa<ConstantSDNode>(N0)) 3984 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3985 return SDValue(); 3986} 3987 3988SDValue DAGCombiner::visitSELECT(SDNode *N) { 3989 SDValue N0 = N->getOperand(0); 3990 SDValue N1 = N->getOperand(1); 3991 SDValue N2 = N->getOperand(2); 3992 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3994 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3995 EVT VT = N->getValueType(0); 3996 EVT VT0 = N0.getValueType(); 3997 3998 // fold (select C, X, X) -> X 3999 if (N1 == N2) 4000 return N1; 4001 // fold (select true, X, Y) -> X 4002 if (N0C && !N0C->isNullValue()) 4003 return N1; 4004 // fold (select false, X, Y) -> Y 4005 if (N0C && N0C->isNullValue()) 4006 return N2; 4007 // fold (select C, 1, X) -> (or C, X) 4008 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4009 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4010 // fold (select C, 0, 1) -> (xor C, 1) 4011 if (VT.isInteger() && 4012 (VT0 == MVT::i1 || 4013 (VT0.isInteger() && 4014 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) && 4015 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4016 SDValue XORNode; 4017 if (VT == VT0) 4018 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4019 N0, DAG.getConstant(1, VT0)); 4020 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4021 N0, DAG.getConstant(1, VT0)); 4022 AddToWorkList(XORNode.getNode()); 4023 if (VT.bitsGT(VT0)) 4024 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4025 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4026 } 4027 // fold (select C, 0, X) -> (and (not C), X) 4028 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4029 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4030 AddToWorkList(NOTNode.getNode()); 4031 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4032 } 4033 // fold (select C, X, 1) -> (or (not C), X) 4034 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4035 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4036 AddToWorkList(NOTNode.getNode()); 4037 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4038 } 4039 // fold (select C, X, 0) -> (and C, X) 4040 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4041 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4042 // fold (select X, X, Y) -> (or X, Y) 4043 // fold (select X, 1, Y) -> (or X, Y) 4044 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4045 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4046 // fold (select X, Y, X) -> (and X, Y) 4047 // fold (select X, Y, 0) -> (and X, Y) 4048 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4049 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4050 4051 // If we can fold this based on the true/false value, do so. 4052 if (SimplifySelectOps(N, N1, N2)) 4053 return SDValue(N, 0); // Don't revisit N. 4054 4055 // fold selects based on a setcc into other things, such as min/max/abs 4056 if (N0.getOpcode() == ISD::SETCC) { 4057 // FIXME: 4058 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4059 // having to say they don't support SELECT_CC on every type the DAG knows 4060 // about, since there is no way to mark an opcode illegal at all value types 4061 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4062 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4063 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4064 N0.getOperand(0), N0.getOperand(1), 4065 N1, N2, N0.getOperand(2)); 4066 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4067 } 4068 4069 return SDValue(); 4070} 4071 4072SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4073 SDValue N0 = N->getOperand(0); 4074 SDValue N1 = N->getOperand(1); 4075 SDValue N2 = N->getOperand(2); 4076 SDValue N3 = N->getOperand(3); 4077 SDValue N4 = N->getOperand(4); 4078 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4079 4080 // fold select_cc lhs, rhs, x, x, cc -> x 4081 if (N2 == N3) 4082 return N2; 4083 4084 // Determine if the condition we're dealing with is constant 4085 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4086 N0, N1, CC, N->getDebugLoc(), false); 4087 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4088 4089 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4090 if (!SCCC->isNullValue()) 4091 return N2; // cond always true -> true val 4092 else 4093 return N3; // cond always false -> false val 4094 } 4095 4096 // Fold to a simpler select_cc 4097 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4098 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4099 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4100 SCC.getOperand(2)); 4101 4102 // If we can fold this based on the true/false value, do so. 4103 if (SimplifySelectOps(N, N2, N3)) 4104 return SDValue(N, 0); // Don't revisit N. 4105 4106 // fold select_cc into other things, such as min/max/abs 4107 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4108} 4109 4110SDValue DAGCombiner::visitSETCC(SDNode *N) { 4111 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4112 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4113 N->getDebugLoc()); 4114} 4115 4116// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4117// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4118// transformation. Returns true if extension are possible and the above 4119// mentioned transformation is profitable. 4120static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4121 unsigned ExtOpc, 4122 SmallVector<SDNode*, 4> &ExtendNodes, 4123 const TargetLowering &TLI) { 4124 bool HasCopyToRegUses = false; 4125 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4126 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4127 UE = N0.getNode()->use_end(); 4128 UI != UE; ++UI) { 4129 SDNode *User = *UI; 4130 if (User == N) 4131 continue; 4132 if (UI.getUse().getResNo() != N0.getResNo()) 4133 continue; 4134 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4135 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4136 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4137 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4138 // Sign bits will be lost after a zext. 4139 return false; 4140 bool Add = false; 4141 for (unsigned i = 0; i != 2; ++i) { 4142 SDValue UseOp = User->getOperand(i); 4143 if (UseOp == N0) 4144 continue; 4145 if (!isa<ConstantSDNode>(UseOp)) 4146 return false; 4147 Add = true; 4148 } 4149 if (Add) 4150 ExtendNodes.push_back(User); 4151 continue; 4152 } 4153 // If truncates aren't free and there are users we can't 4154 // extend, it isn't worthwhile. 4155 if (!isTruncFree) 4156 return false; 4157 // Remember if this value is live-out. 4158 if (User->getOpcode() == ISD::CopyToReg) 4159 HasCopyToRegUses = true; 4160 } 4161 4162 if (HasCopyToRegUses) { 4163 bool BothLiveOut = false; 4164 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4165 UI != UE; ++UI) { 4166 SDUse &Use = UI.getUse(); 4167 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4168 BothLiveOut = true; 4169 break; 4170 } 4171 } 4172 if (BothLiveOut) 4173 // Both unextended and extended values are live out. There had better be 4174 // a good reason for the transformation. 4175 return ExtendNodes.size(); 4176 } 4177 return true; 4178} 4179 4180void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4181 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4182 ISD::NodeType ExtType) { 4183 // Extend SetCC uses if necessary. 4184 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4185 SDNode *SetCC = SetCCs[i]; 4186 SmallVector<SDValue, 4> Ops; 4187 4188 for (unsigned j = 0; j != 2; ++j) { 4189 SDValue SOp = SetCC->getOperand(j); 4190 if (SOp == Trunc) 4191 Ops.push_back(ExtLoad); 4192 else 4193 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4194 } 4195 4196 Ops.push_back(SetCC->getOperand(2)); 4197 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4198 &Ops[0], Ops.size())); 4199 } 4200} 4201 4202SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4203 SDValue N0 = N->getOperand(0); 4204 EVT VT = N->getValueType(0); 4205 4206 // fold (sext c1) -> c1 4207 if (isa<ConstantSDNode>(N0)) 4208 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4209 4210 // fold (sext (sext x)) -> (sext x) 4211 // fold (sext (aext x)) -> (sext x) 4212 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4213 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4214 N0.getOperand(0)); 4215 4216 if (N0.getOpcode() == ISD::TRUNCATE) { 4217 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4218 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4219 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4220 if (NarrowLoad.getNode()) { 4221 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4222 if (NarrowLoad.getNode() != N0.getNode()) { 4223 CombineTo(N0.getNode(), NarrowLoad); 4224 // CombineTo deleted the truncate, if needed, but not what's under it. 4225 AddToWorkList(oye); 4226 } 4227 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4228 } 4229 4230 // See if the value being truncated is already sign extended. If so, just 4231 // eliminate the trunc/sext pair. 4232 SDValue Op = N0.getOperand(0); 4233 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4234 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4235 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4236 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4237 4238 if (OpBits == DestBits) { 4239 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4240 // bits, it is already ready. 4241 if (NumSignBits > DestBits-MidBits) 4242 return Op; 4243 } else if (OpBits < DestBits) { 4244 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4245 // bits, just sext from i32. 4246 if (NumSignBits > OpBits-MidBits) 4247 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4248 } else { 4249 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4250 // bits, just truncate to i32. 4251 if (NumSignBits > OpBits-MidBits) 4252 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4253 } 4254 4255 // fold (sext (truncate x)) -> (sextinreg x). 4256 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4257 N0.getValueType())) { 4258 if (OpBits < DestBits) 4259 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4260 else if (OpBits > DestBits) 4261 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4262 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4263 DAG.getValueType(N0.getValueType())); 4264 } 4265 } 4266 4267 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4268 // None of the supported targets knows how to perform load and sign extend 4269 // on vectors in one instruction. We only perform this transformation on 4270 // scalars. 4271 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4272 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4273 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4274 bool DoXform = true; 4275 SmallVector<SDNode*, 4> SetCCs; 4276 if (!N0.hasOneUse()) 4277 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4278 if (DoXform) { 4279 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4280 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4281 LN0->getChain(), 4282 LN0->getBasePtr(), LN0->getPointerInfo(), 4283 N0.getValueType(), 4284 LN0->isVolatile(), LN0->isNonTemporal(), 4285 LN0->getAlignment()); 4286 CombineTo(N, ExtLoad); 4287 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4288 N0.getValueType(), ExtLoad); 4289 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4290 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4291 ISD::SIGN_EXTEND); 4292 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4293 } 4294 } 4295 4296 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4297 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4298 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4299 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4300 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4301 EVT MemVT = LN0->getMemoryVT(); 4302 if ((!LegalOperations && !LN0->isVolatile()) || 4303 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4304 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4305 LN0->getChain(), 4306 LN0->getBasePtr(), LN0->getPointerInfo(), 4307 MemVT, 4308 LN0->isVolatile(), LN0->isNonTemporal(), 4309 LN0->getAlignment()); 4310 CombineTo(N, ExtLoad); 4311 CombineTo(N0.getNode(), 4312 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4313 N0.getValueType(), ExtLoad), 4314 ExtLoad.getValue(1)); 4315 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4316 } 4317 } 4318 4319 // fold (sext (and/or/xor (load x), cst)) -> 4320 // (and/or/xor (sextload x), (sext cst)) 4321 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4322 N0.getOpcode() == ISD::XOR) && 4323 isa<LoadSDNode>(N0.getOperand(0)) && 4324 N0.getOperand(1).getOpcode() == ISD::Constant && 4325 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4326 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4327 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4328 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4329 bool DoXform = true; 4330 SmallVector<SDNode*, 4> SetCCs; 4331 if (!N0.hasOneUse()) 4332 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4333 SetCCs, TLI); 4334 if (DoXform) { 4335 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4336 LN0->getChain(), LN0->getBasePtr(), 4337 LN0->getPointerInfo(), 4338 LN0->getMemoryVT(), 4339 LN0->isVolatile(), 4340 LN0->isNonTemporal(), 4341 LN0->getAlignment()); 4342 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4343 Mask = Mask.sext(VT.getSizeInBits()); 4344 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4345 ExtLoad, DAG.getConstant(Mask, VT)); 4346 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4347 N0.getOperand(0).getDebugLoc(), 4348 N0.getOperand(0).getValueType(), ExtLoad); 4349 CombineTo(N, And); 4350 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4351 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4352 ISD::SIGN_EXTEND); 4353 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4354 } 4355 } 4356 } 4357 4358 if (N0.getOpcode() == ISD::SETCC) { 4359 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4360 // Only do this before legalize for now. 4361 if (VT.isVector() && !LegalOperations) { 4362 EVT N0VT = N0.getOperand(0).getValueType(); 4363 // We know that the # elements of the results is the same as the 4364 // # elements of the compare (and the # elements of the compare result 4365 // for that matter). Check to see that they are the same size. If so, 4366 // we know that the element size of the sext'd result matches the 4367 // element size of the compare operands. 4368 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4369 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4370 N0.getOperand(1), 4371 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4372 // If the desired elements are smaller or larger than the source 4373 // elements we can use a matching integer vector type and then 4374 // truncate/sign extend 4375 else { 4376 EVT MatchingElementType = 4377 EVT::getIntegerVT(*DAG.getContext(), 4378 N0VT.getScalarType().getSizeInBits()); 4379 EVT MatchingVectorType = 4380 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4381 N0VT.getVectorNumElements()); 4382 SDValue VsetCC = 4383 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4384 N0.getOperand(1), 4385 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4386 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4387 } 4388 } 4389 4390 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4391 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4392 SDValue NegOne = 4393 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4394 SDValue SCC = 4395 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4396 NegOne, DAG.getConstant(0, VT), 4397 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4398 if (SCC.getNode()) return SCC; 4399 if (!LegalOperations || 4400 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4401 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4402 DAG.getSetCC(N->getDebugLoc(), 4403 TLI.getSetCCResultType(VT), 4404 N0.getOperand(0), N0.getOperand(1), 4405 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4406 NegOne, DAG.getConstant(0, VT)); 4407 } 4408 4409 // fold (sext x) -> (zext x) if the sign bit is known zero. 4410 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4411 DAG.SignBitIsZero(N0)) 4412 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4413 4414 return SDValue(); 4415} 4416 4417SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4418 SDValue N0 = N->getOperand(0); 4419 EVT VT = N->getValueType(0); 4420 4421 // fold (zext c1) -> c1 4422 if (isa<ConstantSDNode>(N0)) 4423 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4424 // fold (zext (zext x)) -> (zext x) 4425 // fold (zext (aext x)) -> (zext x) 4426 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4427 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4428 N0.getOperand(0)); 4429 4430 // fold (zext (truncate x)) -> (zext x) or 4431 // (zext (truncate x)) -> (truncate x) 4432 // This is valid when the truncated bits of x are already zero. 4433 // FIXME: We should extend this to work for vectors too. 4434 if (N0.getOpcode() == ISD::TRUNCATE && !VT.isVector()) { 4435 SDValue Op = N0.getOperand(0); 4436 APInt TruncatedBits 4437 = APInt::getBitsSet(Op.getValueSizeInBits(), 4438 N0.getValueSizeInBits(), 4439 std::min(Op.getValueSizeInBits(), 4440 VT.getSizeInBits())); 4441 APInt KnownZero, KnownOne; 4442 DAG.ComputeMaskedBits(Op, TruncatedBits, KnownZero, KnownOne); 4443 if (TruncatedBits == KnownZero) { 4444 if (VT.bitsGT(Op.getValueType())) 4445 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4446 if (VT.bitsLT(Op.getValueType())) 4447 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4448 4449 return Op; 4450 } 4451 } 4452 4453 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4454 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4455 if (N0.getOpcode() == ISD::TRUNCATE) { 4456 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4457 if (NarrowLoad.getNode()) { 4458 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4459 if (NarrowLoad.getNode() != N0.getNode()) { 4460 CombineTo(N0.getNode(), NarrowLoad); 4461 // CombineTo deleted the truncate, if needed, but not what's under it. 4462 AddToWorkList(oye); 4463 } 4464 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4465 } 4466 } 4467 4468 // fold (zext (truncate x)) -> (and x, mask) 4469 if (N0.getOpcode() == ISD::TRUNCATE && 4470 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4471 4472 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4473 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4474 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4475 if (NarrowLoad.getNode()) { 4476 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4477 if (NarrowLoad.getNode() != N0.getNode()) { 4478 CombineTo(N0.getNode(), NarrowLoad); 4479 // CombineTo deleted the truncate, if needed, but not what's under it. 4480 AddToWorkList(oye); 4481 } 4482 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4483 } 4484 4485 SDValue Op = N0.getOperand(0); 4486 if (Op.getValueType().bitsLT(VT)) { 4487 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4488 } else if (Op.getValueType().bitsGT(VT)) { 4489 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4490 } 4491 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4492 N0.getValueType().getScalarType()); 4493 } 4494 4495 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4496 // if either of the casts is not free. 4497 if (N0.getOpcode() == ISD::AND && 4498 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4499 N0.getOperand(1).getOpcode() == ISD::Constant && 4500 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4501 N0.getValueType()) || 4502 !TLI.isZExtFree(N0.getValueType(), VT))) { 4503 SDValue X = N0.getOperand(0).getOperand(0); 4504 if (X.getValueType().bitsLT(VT)) { 4505 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4506 } else if (X.getValueType().bitsGT(VT)) { 4507 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4508 } 4509 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4510 Mask = Mask.zext(VT.getSizeInBits()); 4511 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4512 X, DAG.getConstant(Mask, VT)); 4513 } 4514 4515 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4516 // None of the supported targets knows how to perform load and vector_zext 4517 // on vectors in one instruction. We only perform this transformation on 4518 // scalars. 4519 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4520 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4521 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4522 bool DoXform = true; 4523 SmallVector<SDNode*, 4> SetCCs; 4524 if (!N0.hasOneUse()) 4525 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4526 if (DoXform) { 4527 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4528 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4529 LN0->getChain(), 4530 LN0->getBasePtr(), LN0->getPointerInfo(), 4531 N0.getValueType(), 4532 LN0->isVolatile(), LN0->isNonTemporal(), 4533 LN0->getAlignment()); 4534 CombineTo(N, ExtLoad); 4535 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4536 N0.getValueType(), ExtLoad); 4537 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4538 4539 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4540 ISD::ZERO_EXTEND); 4541 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4542 } 4543 } 4544 4545 // fold (zext (and/or/xor (load x), cst)) -> 4546 // (and/or/xor (zextload x), (zext cst)) 4547 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4548 N0.getOpcode() == ISD::XOR) && 4549 isa<LoadSDNode>(N0.getOperand(0)) && 4550 N0.getOperand(1).getOpcode() == ISD::Constant && 4551 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4552 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4553 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4554 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4555 bool DoXform = true; 4556 SmallVector<SDNode*, 4> SetCCs; 4557 if (!N0.hasOneUse()) 4558 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4559 SetCCs, TLI); 4560 if (DoXform) { 4561 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4562 LN0->getChain(), LN0->getBasePtr(), 4563 LN0->getPointerInfo(), 4564 LN0->getMemoryVT(), 4565 LN0->isVolatile(), 4566 LN0->isNonTemporal(), 4567 LN0->getAlignment()); 4568 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4569 Mask = Mask.zext(VT.getSizeInBits()); 4570 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4571 ExtLoad, DAG.getConstant(Mask, VT)); 4572 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4573 N0.getOperand(0).getDebugLoc(), 4574 N0.getOperand(0).getValueType(), ExtLoad); 4575 CombineTo(N, And); 4576 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4577 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4578 ISD::ZERO_EXTEND); 4579 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4580 } 4581 } 4582 } 4583 4584 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4585 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4586 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4587 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4588 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4589 EVT MemVT = LN0->getMemoryVT(); 4590 if ((!LegalOperations && !LN0->isVolatile()) || 4591 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4592 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4593 LN0->getChain(), 4594 LN0->getBasePtr(), LN0->getPointerInfo(), 4595 MemVT, 4596 LN0->isVolatile(), LN0->isNonTemporal(), 4597 LN0->getAlignment()); 4598 CombineTo(N, ExtLoad); 4599 CombineTo(N0.getNode(), 4600 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4601 ExtLoad), 4602 ExtLoad.getValue(1)); 4603 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4604 } 4605 } 4606 4607 if (N0.getOpcode() == ISD::SETCC) { 4608 if (!LegalOperations && VT.isVector()) { 4609 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4610 // Only do this before legalize for now. 4611 EVT N0VT = N0.getOperand(0).getValueType(); 4612 EVT EltVT = VT.getVectorElementType(); 4613 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4614 DAG.getConstant(1, EltVT)); 4615 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4616 // We know that the # elements of the results is the same as the 4617 // # elements of the compare (and the # elements of the compare result 4618 // for that matter). Check to see that they are the same size. If so, 4619 // we know that the element size of the sext'd result matches the 4620 // element size of the compare operands. 4621 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4622 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4623 N0.getOperand(1), 4624 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4625 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4626 &OneOps[0], OneOps.size())); 4627 4628 // If the desired elements are smaller or larger than the source 4629 // elements we can use a matching integer vector type and then 4630 // truncate/sign extend 4631 EVT MatchingElementType = 4632 EVT::getIntegerVT(*DAG.getContext(), 4633 N0VT.getScalarType().getSizeInBits()); 4634 EVT MatchingVectorType = 4635 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4636 N0VT.getVectorNumElements()); 4637 SDValue VsetCC = 4638 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4639 N0.getOperand(1), 4640 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4641 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4642 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4643 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4644 &OneOps[0], OneOps.size())); 4645 } 4646 4647 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4648 SDValue SCC = 4649 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4650 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4651 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4652 if (SCC.getNode()) return SCC; 4653 } 4654 4655 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4656 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4657 isa<ConstantSDNode>(N0.getOperand(1)) && 4658 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4659 N0.hasOneUse()) { 4660 SDValue ShAmt = N0.getOperand(1); 4661 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4662 if (N0.getOpcode() == ISD::SHL) { 4663 SDValue InnerZExt = N0.getOperand(0); 4664 // If the original shl may be shifting out bits, do not perform this 4665 // transformation. 4666 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4667 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4668 if (ShAmtVal > KnownZeroBits) 4669 return SDValue(); 4670 } 4671 4672 DebugLoc DL = N->getDebugLoc(); 4673 4674 // Ensure that the shift amount is wide enough for the shifted value. 4675 if (VT.getSizeInBits() >= 256) 4676 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4677 4678 return DAG.getNode(N0.getOpcode(), DL, VT, 4679 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4680 ShAmt); 4681 } 4682 4683 return SDValue(); 4684} 4685 4686SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4687 SDValue N0 = N->getOperand(0); 4688 EVT VT = N->getValueType(0); 4689 4690 // fold (aext c1) -> c1 4691 if (isa<ConstantSDNode>(N0)) 4692 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4693 // fold (aext (aext x)) -> (aext x) 4694 // fold (aext (zext x)) -> (zext x) 4695 // fold (aext (sext x)) -> (sext x) 4696 if (N0.getOpcode() == ISD::ANY_EXTEND || 4697 N0.getOpcode() == ISD::ZERO_EXTEND || 4698 N0.getOpcode() == ISD::SIGN_EXTEND) 4699 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4700 4701 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4702 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4703 if (N0.getOpcode() == ISD::TRUNCATE) { 4704 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4705 if (NarrowLoad.getNode()) { 4706 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4707 if (NarrowLoad.getNode() != N0.getNode()) { 4708 CombineTo(N0.getNode(), NarrowLoad); 4709 // CombineTo deleted the truncate, if needed, but not what's under it. 4710 AddToWorkList(oye); 4711 } 4712 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4713 } 4714 } 4715 4716 // fold (aext (truncate x)) 4717 if (N0.getOpcode() == ISD::TRUNCATE) { 4718 SDValue TruncOp = N0.getOperand(0); 4719 if (TruncOp.getValueType() == VT) 4720 return TruncOp; // x iff x size == zext size. 4721 if (TruncOp.getValueType().bitsGT(VT)) 4722 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4723 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4724 } 4725 4726 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4727 // if the trunc is not free. 4728 if (N0.getOpcode() == ISD::AND && 4729 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4730 N0.getOperand(1).getOpcode() == ISD::Constant && 4731 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4732 N0.getValueType())) { 4733 SDValue X = N0.getOperand(0).getOperand(0); 4734 if (X.getValueType().bitsLT(VT)) { 4735 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4736 } else if (X.getValueType().bitsGT(VT)) { 4737 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4738 } 4739 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4740 Mask = Mask.zext(VT.getSizeInBits()); 4741 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4742 X, DAG.getConstant(Mask, VT)); 4743 } 4744 4745 // fold (aext (load x)) -> (aext (truncate (extload x))) 4746 // None of the supported targets knows how to perform load and any_ext 4747 // on vectors in one instruction. We only perform this transformation on 4748 // scalars. 4749 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4750 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4751 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4752 bool DoXform = true; 4753 SmallVector<SDNode*, 4> SetCCs; 4754 if (!N0.hasOneUse()) 4755 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4756 if (DoXform) { 4757 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4758 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4759 LN0->getChain(), 4760 LN0->getBasePtr(), LN0->getPointerInfo(), 4761 N0.getValueType(), 4762 LN0->isVolatile(), LN0->isNonTemporal(), 4763 LN0->getAlignment()); 4764 CombineTo(N, ExtLoad); 4765 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4766 N0.getValueType(), ExtLoad); 4767 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4768 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4769 ISD::ANY_EXTEND); 4770 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4771 } 4772 } 4773 4774 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4775 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4776 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4777 if (N0.getOpcode() == ISD::LOAD && 4778 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4779 N0.hasOneUse()) { 4780 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4781 EVT MemVT = LN0->getMemoryVT(); 4782 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4783 VT, LN0->getChain(), LN0->getBasePtr(), 4784 LN0->getPointerInfo(), MemVT, 4785 LN0->isVolatile(), LN0->isNonTemporal(), 4786 LN0->getAlignment()); 4787 CombineTo(N, ExtLoad); 4788 CombineTo(N0.getNode(), 4789 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4790 N0.getValueType(), ExtLoad), 4791 ExtLoad.getValue(1)); 4792 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4793 } 4794 4795 if (N0.getOpcode() == ISD::SETCC) { 4796 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4797 // Only do this before legalize for now. 4798 if (VT.isVector() && !LegalOperations) { 4799 EVT N0VT = N0.getOperand(0).getValueType(); 4800 // We know that the # elements of the results is the same as the 4801 // # elements of the compare (and the # elements of the compare result 4802 // for that matter). Check to see that they are the same size. If so, 4803 // we know that the element size of the sext'd result matches the 4804 // element size of the compare operands. 4805 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4806 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4807 N0.getOperand(1), 4808 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4809 // If the desired elements are smaller or larger than the source 4810 // elements we can use a matching integer vector type and then 4811 // truncate/sign extend 4812 else { 4813 EVT MatchingElementType = 4814 EVT::getIntegerVT(*DAG.getContext(), 4815 N0VT.getScalarType().getSizeInBits()); 4816 EVT MatchingVectorType = 4817 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4818 N0VT.getVectorNumElements()); 4819 SDValue VsetCC = 4820 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4821 N0.getOperand(1), 4822 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4823 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4824 } 4825 } 4826 4827 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4828 SDValue SCC = 4829 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4830 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4831 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4832 if (SCC.getNode()) 4833 return SCC; 4834 } 4835 4836 return SDValue(); 4837} 4838 4839/// GetDemandedBits - See if the specified operand can be simplified with the 4840/// knowledge that only the bits specified by Mask are used. If so, return the 4841/// simpler operand, otherwise return a null SDValue. 4842SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4843 switch (V.getOpcode()) { 4844 default: break; 4845 case ISD::Constant: { 4846 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4847 assert(CV != 0 && "Const value should be ConstSDNode."); 4848 const APInt &CVal = CV->getAPIntValue(); 4849 APInt NewVal = CVal & Mask; 4850 if (NewVal != CVal) { 4851 return DAG.getConstant(NewVal, V.getValueType()); 4852 } 4853 break; 4854 } 4855 case ISD::OR: 4856 case ISD::XOR: 4857 // If the LHS or RHS don't contribute bits to the or, drop them. 4858 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4859 return V.getOperand(1); 4860 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4861 return V.getOperand(0); 4862 break; 4863 case ISD::SRL: 4864 // Only look at single-use SRLs. 4865 if (!V.getNode()->hasOneUse()) 4866 break; 4867 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4868 // See if we can recursively simplify the LHS. 4869 unsigned Amt = RHSC->getZExtValue(); 4870 4871 // Watch out for shift count overflow though. 4872 if (Amt >= Mask.getBitWidth()) break; 4873 APInt NewMask = Mask << Amt; 4874 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4875 if (SimplifyLHS.getNode()) 4876 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4877 SimplifyLHS, V.getOperand(1)); 4878 } 4879 } 4880 return SDValue(); 4881} 4882 4883/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4884/// bits and then truncated to a narrower type and where N is a multiple 4885/// of number of bits of the narrower type, transform it to a narrower load 4886/// from address + N / num of bits of new type. If the result is to be 4887/// extended, also fold the extension to form a extending load. 4888SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4889 unsigned Opc = N->getOpcode(); 4890 4891 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4892 SDValue N0 = N->getOperand(0); 4893 EVT VT = N->getValueType(0); 4894 EVT ExtVT = VT; 4895 4896 // This transformation isn't valid for vector loads. 4897 if (VT.isVector()) 4898 return SDValue(); 4899 4900 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4901 // extended to VT. 4902 if (Opc == ISD::SIGN_EXTEND_INREG) { 4903 ExtType = ISD::SEXTLOAD; 4904 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4905 } else if (Opc == ISD::SRL) { 4906 // Another special-case: SRL is basically zero-extending a narrower value. 4907 ExtType = ISD::ZEXTLOAD; 4908 N0 = SDValue(N, 0); 4909 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4910 if (!N01) return SDValue(); 4911 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4912 VT.getSizeInBits() - N01->getZExtValue()); 4913 } 4914 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4915 return SDValue(); 4916 4917 unsigned EVTBits = ExtVT.getSizeInBits(); 4918 4919 // Do not generate loads of non-round integer types since these can 4920 // be expensive (and would be wrong if the type is not byte sized). 4921 if (!ExtVT.isRound()) 4922 return SDValue(); 4923 4924 unsigned ShAmt = 0; 4925 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4926 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4927 ShAmt = N01->getZExtValue(); 4928 // Is the shift amount a multiple of size of VT? 4929 if ((ShAmt & (EVTBits-1)) == 0) { 4930 N0 = N0.getOperand(0); 4931 // Is the load width a multiple of size of VT? 4932 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4933 return SDValue(); 4934 } 4935 4936 // At this point, we must have a load or else we can't do the transform. 4937 if (!isa<LoadSDNode>(N0)) return SDValue(); 4938 4939 // If the shift amount is larger than the input type then we're not 4940 // accessing any of the loaded bytes. If the load was a zextload/extload 4941 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4942 // If the load was a sextload then the result is a splat of the sign bit 4943 // of the extended byte. This is not worth optimizing for. 4944 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4945 return SDValue(); 4946 } 4947 } 4948 4949 // If the load is shifted left (and the result isn't shifted back right), 4950 // we can fold the truncate through the shift. 4951 unsigned ShLeftAmt = 0; 4952 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4953 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4954 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4955 ShLeftAmt = N01->getZExtValue(); 4956 N0 = N0.getOperand(0); 4957 } 4958 } 4959 4960 // If we haven't found a load, we can't narrow it. Don't transform one with 4961 // multiple uses, this would require adding a new load. 4962 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4963 // Don't change the width of a volatile load. 4964 cast<LoadSDNode>(N0)->isVolatile()) 4965 return SDValue(); 4966 4967 // Verify that we are actually reducing a load width here. 4968 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4969 return SDValue(); 4970 4971 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4972 EVT PtrType = N0.getOperand(1).getValueType(); 4973 4974 // For big endian targets, we need to adjust the offset to the pointer to 4975 // load the correct bytes. 4976 if (TLI.isBigEndian()) { 4977 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4978 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4979 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4980 } 4981 4982 uint64_t PtrOff = ShAmt / 8; 4983 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4984 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4985 PtrType, LN0->getBasePtr(), 4986 DAG.getConstant(PtrOff, PtrType)); 4987 AddToWorkList(NewPtr.getNode()); 4988 4989 SDValue Load; 4990 if (ExtType == ISD::NON_EXTLOAD) 4991 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4992 LN0->getPointerInfo().getWithOffset(PtrOff), 4993 LN0->isVolatile(), LN0->isNonTemporal(), 4994 LN0->isInvariant(), NewAlign); 4995 else 4996 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4997 LN0->getPointerInfo().getWithOffset(PtrOff), 4998 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4999 NewAlign); 5000 5001 // Replace the old load's chain with the new load's chain. 5002 WorkListRemover DeadNodes(*this); 5003 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 5004 &DeadNodes); 5005 5006 // Shift the result left, if we've swallowed a left shift. 5007 SDValue Result = Load; 5008 if (ShLeftAmt != 0) { 5009 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5010 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5011 ShImmTy = VT; 5012 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5013 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5014 } 5015 5016 // Return the new loaded value. 5017 return Result; 5018} 5019 5020SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5021 SDValue N0 = N->getOperand(0); 5022 SDValue N1 = N->getOperand(1); 5023 EVT VT = N->getValueType(0); 5024 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5025 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5026 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5027 5028 // fold (sext_in_reg c1) -> c1 5029 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5030 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5031 5032 // If the input is already sign extended, just drop the extension. 5033 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5034 return N0; 5035 5036 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5037 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5038 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5039 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5040 N0.getOperand(0), N1); 5041 } 5042 5043 // fold (sext_in_reg (sext x)) -> (sext x) 5044 // fold (sext_in_reg (aext x)) -> (sext x) 5045 // if x is small enough. 5046 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5047 SDValue N00 = N0.getOperand(0); 5048 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5049 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5050 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5051 } 5052 5053 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5054 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5055 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5056 5057 // fold operands of sext_in_reg based on knowledge that the top bits are not 5058 // demanded. 5059 if (SimplifyDemandedBits(SDValue(N, 0))) 5060 return SDValue(N, 0); 5061 5062 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5063 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5064 SDValue NarrowLoad = ReduceLoadWidth(N); 5065 if (NarrowLoad.getNode()) 5066 return NarrowLoad; 5067 5068 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5069 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5070 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5071 if (N0.getOpcode() == ISD::SRL) { 5072 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5073 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5074 // We can turn this into an SRA iff the input to the SRL is already sign 5075 // extended enough. 5076 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5077 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5078 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5079 N0.getOperand(0), N0.getOperand(1)); 5080 } 5081 } 5082 5083 // fold (sext_inreg (extload x)) -> (sextload x) 5084 if (ISD::isEXTLoad(N0.getNode()) && 5085 ISD::isUNINDEXEDLoad(N0.getNode()) && 5086 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5087 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5088 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5089 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5090 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5091 LN0->getChain(), 5092 LN0->getBasePtr(), LN0->getPointerInfo(), 5093 EVT, 5094 LN0->isVolatile(), LN0->isNonTemporal(), 5095 LN0->getAlignment()); 5096 CombineTo(N, ExtLoad); 5097 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5098 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5099 } 5100 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5101 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5102 N0.hasOneUse() && 5103 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5104 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5105 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5106 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5107 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5108 LN0->getChain(), 5109 LN0->getBasePtr(), LN0->getPointerInfo(), 5110 EVT, 5111 LN0->isVolatile(), LN0->isNonTemporal(), 5112 LN0->getAlignment()); 5113 CombineTo(N, ExtLoad); 5114 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5115 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5116 } 5117 5118 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5119 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5120 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5121 N0.getOperand(1), false); 5122 if (BSwap.getNode() != 0) 5123 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5124 BSwap, N1); 5125 } 5126 5127 return SDValue(); 5128} 5129 5130SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5131 SDValue N0 = N->getOperand(0); 5132 EVT VT = N->getValueType(0); 5133 bool isLE = TLI.isLittleEndian(); 5134 5135 // noop truncate 5136 if (N0.getValueType() == N->getValueType(0)) 5137 return N0; 5138 // fold (truncate c1) -> c1 5139 if (isa<ConstantSDNode>(N0)) 5140 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5141 // fold (truncate (truncate x)) -> (truncate x) 5142 if (N0.getOpcode() == ISD::TRUNCATE) 5143 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5144 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5145 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5146 N0.getOpcode() == ISD::SIGN_EXTEND || 5147 N0.getOpcode() == ISD::ANY_EXTEND) { 5148 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5149 // if the source is smaller than the dest, we still need an extend 5150 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5151 N0.getOperand(0)); 5152 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 5153 // if the source is larger than the dest, than we just need the truncate 5154 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5155 else 5156 // if the source and dest are the same type, we can drop both the extend 5157 // and the truncate. 5158 return N0.getOperand(0); 5159 } 5160 5161 // Fold extract-and-trunc into a narrow extract. For example: 5162 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5163 // i32 y = TRUNCATE(i64 x) 5164 // -- becomes -- 5165 // v16i8 b = BITCAST (v2i64 val) 5166 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5167 // 5168 // Note: We only run this optimization after type legalization (which often 5169 // creates this pattern) and before operation legalization after which 5170 // we need to be more careful about the vector instructions that we generate. 5171 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5172 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5173 5174 EVT VecTy = N0.getOperand(0).getValueType(); 5175 EVT ExTy = N0.getValueType(); 5176 EVT TrTy = N->getValueType(0); 5177 5178 unsigned NumElem = VecTy.getVectorNumElements(); 5179 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5180 5181 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5182 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5183 5184 SDValue EltNo = N0->getOperand(1); 5185 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5186 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5187 5188 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5189 5190 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5191 NVT, N0.getOperand(0)); 5192 5193 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5194 N->getDebugLoc(), TrTy, V, 5195 DAG.getConstant(Index, MVT::i32)); 5196 } 5197 } 5198 5199 // See if we can simplify the input to this truncate through knowledge that 5200 // only the low bits are being used. 5201 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5202 // Currently we only perform this optimization on scalars because vectors 5203 // may have different active low bits. 5204 if (!VT.isVector()) { 5205 SDValue Shorter = 5206 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5207 VT.getSizeInBits())); 5208 if (Shorter.getNode()) 5209 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5210 } 5211 // fold (truncate (load x)) -> (smaller load x) 5212 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5213 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5214 SDValue Reduced = ReduceLoadWidth(N); 5215 if (Reduced.getNode()) 5216 return Reduced; 5217 } 5218 5219 // Simplify the operands using demanded-bits information. 5220 if (!VT.isVector() && 5221 SimplifyDemandedBits(SDValue(N, 0))) 5222 return SDValue(N, 0); 5223 5224 return SDValue(); 5225} 5226 5227static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5228 SDValue Elt = N->getOperand(i); 5229 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5230 return Elt.getNode(); 5231 return Elt.getOperand(Elt.getResNo()).getNode(); 5232} 5233 5234/// CombineConsecutiveLoads - build_pair (load, load) -> load 5235/// if load locations are consecutive. 5236SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5237 assert(N->getOpcode() == ISD::BUILD_PAIR); 5238 5239 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5240 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5241 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5242 LD1->getPointerInfo().getAddrSpace() != 5243 LD2->getPointerInfo().getAddrSpace()) 5244 return SDValue(); 5245 EVT LD1VT = LD1->getValueType(0); 5246 5247 if (ISD::isNON_EXTLoad(LD2) && 5248 LD2->hasOneUse() && 5249 // If both are volatile this would reduce the number of volatile loads. 5250 // If one is volatile it might be ok, but play conservative and bail out. 5251 !LD1->isVolatile() && 5252 !LD2->isVolatile() && 5253 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5254 unsigned Align = LD1->getAlignment(); 5255 unsigned NewAlign = TLI.getTargetData()-> 5256 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5257 5258 if (NewAlign <= Align && 5259 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5260 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5261 LD1->getBasePtr(), LD1->getPointerInfo(), 5262 false, false, false, Align); 5263 } 5264 5265 return SDValue(); 5266} 5267 5268SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5269 SDValue N0 = N->getOperand(0); 5270 EVT VT = N->getValueType(0); 5271 5272 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5273 // Only do this before legalize, since afterward the target may be depending 5274 // on the bitconvert. 5275 // First check to see if this is all constant. 5276 if (!LegalTypes && 5277 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5278 VT.isVector()) { 5279 bool isSimple = true; 5280 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5281 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5282 N0.getOperand(i).getOpcode() != ISD::Constant && 5283 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5284 isSimple = false; 5285 break; 5286 } 5287 5288 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5289 assert(!DestEltVT.isVector() && 5290 "Element type of vector ValueType must not be vector!"); 5291 if (isSimple) 5292 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5293 } 5294 5295 // If the input is a constant, let getNode fold it. 5296 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5297 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5298 if (Res.getNode() != N) { 5299 if (!LegalOperations || 5300 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5301 return Res; 5302 5303 // Folding it resulted in an illegal node, and it's too late to 5304 // do that. Clean up the old node and forego the transformation. 5305 // Ideally this won't happen very often, because instcombine 5306 // and the earlier dagcombine runs (where illegal nodes are 5307 // permitted) should have folded most of them already. 5308 DAG.DeleteNode(Res.getNode()); 5309 } 5310 } 5311 5312 // (conv (conv x, t1), t2) -> (conv x, t2) 5313 if (N0.getOpcode() == ISD::BITCAST) 5314 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5315 N0.getOperand(0)); 5316 5317 // fold (conv (load x)) -> (load (conv*)x) 5318 // If the resultant load doesn't need a higher alignment than the original! 5319 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5320 // Do not change the width of a volatile load. 5321 !cast<LoadSDNode>(N0)->isVolatile() && 5322 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5323 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5324 unsigned Align = TLI.getTargetData()-> 5325 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5326 unsigned OrigAlign = LN0->getAlignment(); 5327 5328 if (Align <= OrigAlign) { 5329 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5330 LN0->getBasePtr(), LN0->getPointerInfo(), 5331 LN0->isVolatile(), LN0->isNonTemporal(), 5332 LN0->isInvariant(), OrigAlign); 5333 AddToWorkList(N); 5334 CombineTo(N0.getNode(), 5335 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5336 N0.getValueType(), Load), 5337 Load.getValue(1)); 5338 return Load; 5339 } 5340 } 5341 5342 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5343 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5344 // This often reduces constant pool loads. 5345 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5346 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5347 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5348 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5349 N0.getOperand(0)); 5350 AddToWorkList(NewConv.getNode()); 5351 5352 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5353 if (N0.getOpcode() == ISD::FNEG) 5354 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5355 NewConv, DAG.getConstant(SignBit, VT)); 5356 assert(N0.getOpcode() == ISD::FABS); 5357 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5358 NewConv, DAG.getConstant(~SignBit, VT)); 5359 } 5360 5361 // fold (bitconvert (fcopysign cst, x)) -> 5362 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5363 // Note that we don't handle (copysign x, cst) because this can always be 5364 // folded to an fneg or fabs. 5365 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5366 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5367 VT.isInteger() && !VT.isVector()) { 5368 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5369 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5370 if (isTypeLegal(IntXVT)) { 5371 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5372 IntXVT, N0.getOperand(1)); 5373 AddToWorkList(X.getNode()); 5374 5375 // If X has a different width than the result/lhs, sext it or truncate it. 5376 unsigned VTWidth = VT.getSizeInBits(); 5377 if (OrigXWidth < VTWidth) { 5378 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5379 AddToWorkList(X.getNode()); 5380 } else if (OrigXWidth > VTWidth) { 5381 // To get the sign bit in the right place, we have to shift it right 5382 // before truncating. 5383 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5384 X.getValueType(), X, 5385 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5386 AddToWorkList(X.getNode()); 5387 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5388 AddToWorkList(X.getNode()); 5389 } 5390 5391 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5392 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5393 X, DAG.getConstant(SignBit, VT)); 5394 AddToWorkList(X.getNode()); 5395 5396 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5397 VT, N0.getOperand(0)); 5398 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5399 Cst, DAG.getConstant(~SignBit, VT)); 5400 AddToWorkList(Cst.getNode()); 5401 5402 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5403 } 5404 } 5405 5406 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5407 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5408 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5409 if (CombineLD.getNode()) 5410 return CombineLD; 5411 } 5412 5413 return SDValue(); 5414} 5415 5416SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5417 EVT VT = N->getValueType(0); 5418 return CombineConsecutiveLoads(N, VT); 5419} 5420 5421/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5422/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5423/// destination element value type. 5424SDValue DAGCombiner:: 5425ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5426 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5427 5428 // If this is already the right type, we're done. 5429 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5430 5431 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5432 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5433 5434 // If this is a conversion of N elements of one type to N elements of another 5435 // type, convert each element. This handles FP<->INT cases. 5436 if (SrcBitSize == DstBitSize) { 5437 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5438 BV->getValueType(0).getVectorNumElements()); 5439 5440 // Due to the FP element handling below calling this routine recursively, 5441 // we can end up with a scalar-to-vector node here. 5442 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5443 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5444 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5445 DstEltVT, BV->getOperand(0))); 5446 5447 SmallVector<SDValue, 8> Ops; 5448 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5449 SDValue Op = BV->getOperand(i); 5450 // If the vector element type is not legal, the BUILD_VECTOR operands 5451 // are promoted and implicitly truncated. Make that explicit here. 5452 if (Op.getValueType() != SrcEltVT) 5453 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5454 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5455 DstEltVT, Op)); 5456 AddToWorkList(Ops.back().getNode()); 5457 } 5458 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5459 &Ops[0], Ops.size()); 5460 } 5461 5462 // Otherwise, we're growing or shrinking the elements. To avoid having to 5463 // handle annoying details of growing/shrinking FP values, we convert them to 5464 // int first. 5465 if (SrcEltVT.isFloatingPoint()) { 5466 // Convert the input float vector to a int vector where the elements are the 5467 // same sizes. 5468 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5469 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5470 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5471 SrcEltVT = IntVT; 5472 } 5473 5474 // Now we know the input is an integer vector. If the output is a FP type, 5475 // convert to integer first, then to FP of the right size. 5476 if (DstEltVT.isFloatingPoint()) { 5477 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5478 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5479 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5480 5481 // Next, convert to FP elements of the same size. 5482 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5483 } 5484 5485 // Okay, we know the src/dst types are both integers of differing types. 5486 // Handling growing first. 5487 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5488 if (SrcBitSize < DstBitSize) { 5489 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5490 5491 SmallVector<SDValue, 8> Ops; 5492 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5493 i += NumInputsPerOutput) { 5494 bool isLE = TLI.isLittleEndian(); 5495 APInt NewBits = APInt(DstBitSize, 0); 5496 bool EltIsUndef = true; 5497 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5498 // Shift the previously computed bits over. 5499 NewBits <<= SrcBitSize; 5500 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5501 if (Op.getOpcode() == ISD::UNDEF) continue; 5502 EltIsUndef = false; 5503 5504 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5505 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5506 } 5507 5508 if (EltIsUndef) 5509 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5510 else 5511 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5512 } 5513 5514 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5515 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5516 &Ops[0], Ops.size()); 5517 } 5518 5519 // Finally, this must be the case where we are shrinking elements: each input 5520 // turns into multiple outputs. 5521 bool isS2V = ISD::isScalarToVector(BV); 5522 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5523 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5524 NumOutputsPerInput*BV->getNumOperands()); 5525 SmallVector<SDValue, 8> Ops; 5526 5527 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5528 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5529 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5530 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5531 continue; 5532 } 5533 5534 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5535 getAPIntValue().zextOrTrunc(SrcBitSize); 5536 5537 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5538 APInt ThisVal = OpVal.trunc(DstBitSize); 5539 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5540 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5541 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5542 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5543 Ops[0]); 5544 OpVal = OpVal.lshr(DstBitSize); 5545 } 5546 5547 // For big endian targets, swap the order of the pieces of each element. 5548 if (TLI.isBigEndian()) 5549 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5550 } 5551 5552 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5553 &Ops[0], Ops.size()); 5554} 5555 5556SDValue DAGCombiner::visitFADD(SDNode *N) { 5557 SDValue N0 = N->getOperand(0); 5558 SDValue N1 = N->getOperand(1); 5559 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5560 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5561 EVT VT = N->getValueType(0); 5562 5563 // fold vector ops 5564 if (VT.isVector()) { 5565 SDValue FoldedVOp = SimplifyVBinOp(N); 5566 if (FoldedVOp.getNode()) return FoldedVOp; 5567 } 5568 5569 // fold (fadd c1, c2) -> (fadd c1, c2) 5570 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5571 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5572 // canonicalize constant to RHS 5573 if (N0CFP && !N1CFP) 5574 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5575 // fold (fadd A, 0) -> A 5576 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5577 N1CFP->getValueAPF().isZero()) 5578 return N0; 5579 // fold (fadd A, (fneg B)) -> (fsub A, B) 5580 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5581 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5582 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5583 GetNegatedExpression(N1, DAG, LegalOperations)); 5584 // fold (fadd (fneg A), B) -> (fsub B, A) 5585 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5586 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5587 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5588 GetNegatedExpression(N0, DAG, LegalOperations)); 5589 5590 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5591 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5592 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5593 isa<ConstantFPSDNode>(N0.getOperand(1))) 5594 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5595 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5596 N0.getOperand(1), N1)); 5597 5598 return SDValue(); 5599} 5600 5601SDValue DAGCombiner::visitFSUB(SDNode *N) { 5602 SDValue N0 = N->getOperand(0); 5603 SDValue N1 = N->getOperand(1); 5604 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5605 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5606 EVT VT = N->getValueType(0); 5607 5608 // fold vector ops 5609 if (VT.isVector()) { 5610 SDValue FoldedVOp = SimplifyVBinOp(N); 5611 if (FoldedVOp.getNode()) return FoldedVOp; 5612 } 5613 5614 // fold (fsub c1, c2) -> c1-c2 5615 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5616 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5617 // fold (fsub A, 0) -> A 5618 if (DAG.getTarget().Options.UnsafeFPMath && 5619 N1CFP && N1CFP->getValueAPF().isZero()) 5620 return N0; 5621 // fold (fsub 0, B) -> -B 5622 if (DAG.getTarget().Options.UnsafeFPMath && 5623 N0CFP && N0CFP->getValueAPF().isZero()) { 5624 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5625 return GetNegatedExpression(N1, DAG, LegalOperations); 5626 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5627 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5628 } 5629 // fold (fsub A, (fneg B)) -> (fadd A, B) 5630 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5631 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5632 GetNegatedExpression(N1, DAG, LegalOperations)); 5633 5634 // If 'unsafe math' is enabled, fold 5635 // (fsub x, (fadd x, y)) -> (fneg y) & 5636 // (fsub x, (fadd y, x)) -> (fneg y) 5637 if (DAG.getTarget().Options.UnsafeFPMath) { 5638 if (N1.getOpcode() == ISD::FADD) { 5639 SDValue N10 = N1->getOperand(0); 5640 SDValue N11 = N1->getOperand(1); 5641 5642 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5643 &DAG.getTarget().Options)) 5644 return GetNegatedExpression(N11, DAG, LegalOperations); 5645 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5646 &DAG.getTarget().Options)) 5647 return GetNegatedExpression(N10, DAG, LegalOperations); 5648 } 5649 } 5650 5651 return SDValue(); 5652} 5653 5654SDValue DAGCombiner::visitFMUL(SDNode *N) { 5655 SDValue N0 = N->getOperand(0); 5656 SDValue N1 = N->getOperand(1); 5657 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5658 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5659 EVT VT = N->getValueType(0); 5660 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5661 5662 // fold vector ops 5663 if (VT.isVector()) { 5664 SDValue FoldedVOp = SimplifyVBinOp(N); 5665 if (FoldedVOp.getNode()) return FoldedVOp; 5666 } 5667 5668 // fold (fmul c1, c2) -> c1*c2 5669 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5670 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5671 // canonicalize constant to RHS 5672 if (N0CFP && !N1CFP) 5673 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5674 // fold (fmul A, 0) -> 0 5675 if (DAG.getTarget().Options.UnsafeFPMath && 5676 N1CFP && N1CFP->getValueAPF().isZero()) 5677 return N1; 5678 // fold (fmul A, 0) -> 0, vector edition. 5679 if (DAG.getTarget().Options.UnsafeFPMath && 5680 ISD::isBuildVectorAllZeros(N1.getNode())) 5681 return N1; 5682 // fold (fmul X, 2.0) -> (fadd X, X) 5683 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5684 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5685 // fold (fmul X, -1.0) -> (fneg X) 5686 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5687 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5688 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5689 5690 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5691 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5692 &DAG.getTarget().Options)) { 5693 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5694 &DAG.getTarget().Options)) { 5695 // Both can be negated for free, check to see if at least one is cheaper 5696 // negated. 5697 if (LHSNeg == 2 || RHSNeg == 2) 5698 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5699 GetNegatedExpression(N0, DAG, LegalOperations), 5700 GetNegatedExpression(N1, DAG, LegalOperations)); 5701 } 5702 } 5703 5704 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5705 if (DAG.getTarget().Options.UnsafeFPMath && 5706 N1CFP && N0.getOpcode() == ISD::FMUL && 5707 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5708 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5709 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5710 N0.getOperand(1), N1)); 5711 5712 return SDValue(); 5713} 5714 5715SDValue DAGCombiner::visitFDIV(SDNode *N) { 5716 SDValue N0 = N->getOperand(0); 5717 SDValue N1 = N->getOperand(1); 5718 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5719 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5720 EVT VT = N->getValueType(0); 5721 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5722 5723 // fold vector ops 5724 if (VT.isVector()) { 5725 SDValue FoldedVOp = SimplifyVBinOp(N); 5726 if (FoldedVOp.getNode()) return FoldedVOp; 5727 } 5728 5729 // fold (fdiv c1, c2) -> c1/c2 5730 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5731 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5732 5733 5734 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5735 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5736 &DAG.getTarget().Options)) { 5737 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5738 &DAG.getTarget().Options)) { 5739 // Both can be negated for free, check to see if at least one is cheaper 5740 // negated. 5741 if (LHSNeg == 2 || RHSNeg == 2) 5742 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5743 GetNegatedExpression(N0, DAG, LegalOperations), 5744 GetNegatedExpression(N1, DAG, LegalOperations)); 5745 } 5746 } 5747 5748 return SDValue(); 5749} 5750 5751SDValue DAGCombiner::visitFREM(SDNode *N) { 5752 SDValue N0 = N->getOperand(0); 5753 SDValue N1 = N->getOperand(1); 5754 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5755 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5756 EVT VT = N->getValueType(0); 5757 5758 // fold (frem c1, c2) -> fmod(c1,c2) 5759 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5760 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5761 5762 return SDValue(); 5763} 5764 5765SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5766 SDValue N0 = N->getOperand(0); 5767 SDValue N1 = N->getOperand(1); 5768 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5769 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5770 EVT VT = N->getValueType(0); 5771 5772 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5773 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5774 5775 if (N1CFP) { 5776 const APFloat& V = N1CFP->getValueAPF(); 5777 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5778 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5779 if (!V.isNegative()) { 5780 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5781 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5782 } else { 5783 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5784 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5785 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5786 } 5787 } 5788 5789 // copysign(fabs(x), y) -> copysign(x, y) 5790 // copysign(fneg(x), y) -> copysign(x, y) 5791 // copysign(copysign(x,z), y) -> copysign(x, y) 5792 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5793 N0.getOpcode() == ISD::FCOPYSIGN) 5794 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5795 N0.getOperand(0), N1); 5796 5797 // copysign(x, abs(y)) -> abs(x) 5798 if (N1.getOpcode() == ISD::FABS) 5799 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5800 5801 // copysign(x, copysign(y,z)) -> copysign(x, z) 5802 if (N1.getOpcode() == ISD::FCOPYSIGN) 5803 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5804 N0, N1.getOperand(1)); 5805 5806 // copysign(x, fp_extend(y)) -> copysign(x, y) 5807 // copysign(x, fp_round(y)) -> copysign(x, y) 5808 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5809 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5810 N0, N1.getOperand(0)); 5811 5812 return SDValue(); 5813} 5814 5815SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5816 SDValue N0 = N->getOperand(0); 5817 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5818 EVT VT = N->getValueType(0); 5819 EVT OpVT = N0.getValueType(); 5820 5821 // fold (sint_to_fp c1) -> c1fp 5822 if (N0C && OpVT != MVT::ppcf128 && 5823 // ...but only if the target supports immediate floating-point values 5824 (!LegalOperations || 5825 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5826 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5827 5828 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5829 // but UINT_TO_FP is legal on this target, try to convert. 5830 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5831 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5832 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5833 if (DAG.SignBitIsZero(N0)) 5834 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5835 } 5836 5837 return SDValue(); 5838} 5839 5840SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5841 SDValue N0 = N->getOperand(0); 5842 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5843 EVT VT = N->getValueType(0); 5844 EVT OpVT = N0.getValueType(); 5845 5846 // fold (uint_to_fp c1) -> c1fp 5847 if (N0C && OpVT != MVT::ppcf128 && 5848 // ...but only if the target supports immediate floating-point values 5849 (!LegalOperations || 5850 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5851 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5852 5853 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5854 // but SINT_TO_FP is legal on this target, try to convert. 5855 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5856 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5857 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5858 if (DAG.SignBitIsZero(N0)) 5859 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5860 } 5861 5862 return SDValue(); 5863} 5864 5865SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5866 SDValue N0 = N->getOperand(0); 5867 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5868 EVT VT = N->getValueType(0); 5869 5870 // fold (fp_to_sint c1fp) -> c1 5871 if (N0CFP) 5872 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5873 5874 return SDValue(); 5875} 5876 5877SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5878 SDValue N0 = N->getOperand(0); 5879 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5880 EVT VT = N->getValueType(0); 5881 5882 // fold (fp_to_uint c1fp) -> c1 5883 if (N0CFP && VT != MVT::ppcf128) 5884 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5885 5886 return SDValue(); 5887} 5888 5889SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5890 SDValue N0 = N->getOperand(0); 5891 SDValue N1 = N->getOperand(1); 5892 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5893 EVT VT = N->getValueType(0); 5894 5895 // fold (fp_round c1fp) -> c1fp 5896 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5897 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5898 5899 // fold (fp_round (fp_extend x)) -> x 5900 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5901 return N0.getOperand(0); 5902 5903 // fold (fp_round (fp_round x)) -> (fp_round x) 5904 if (N0.getOpcode() == ISD::FP_ROUND) { 5905 // This is a value preserving truncation if both round's are. 5906 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5907 N0.getNode()->getConstantOperandVal(1) == 1; 5908 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5909 DAG.getIntPtrConstant(IsTrunc)); 5910 } 5911 5912 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5913 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5914 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5915 N0.getOperand(0), N1); 5916 AddToWorkList(Tmp.getNode()); 5917 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5918 Tmp, N0.getOperand(1)); 5919 } 5920 5921 return SDValue(); 5922} 5923 5924SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5925 SDValue N0 = N->getOperand(0); 5926 EVT VT = N->getValueType(0); 5927 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5928 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5929 5930 // fold (fp_round_inreg c1fp) -> c1fp 5931 if (N0CFP && isTypeLegal(EVT)) { 5932 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5933 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5934 } 5935 5936 return SDValue(); 5937} 5938 5939SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5940 SDValue N0 = N->getOperand(0); 5941 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5942 EVT VT = N->getValueType(0); 5943 5944 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5945 if (N->hasOneUse() && 5946 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5947 return SDValue(); 5948 5949 // fold (fp_extend c1fp) -> c1fp 5950 if (N0CFP && VT != MVT::ppcf128) 5951 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5952 5953 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5954 // value of X. 5955 if (N0.getOpcode() == ISD::FP_ROUND 5956 && N0.getNode()->getConstantOperandVal(1) == 1) { 5957 SDValue In = N0.getOperand(0); 5958 if (In.getValueType() == VT) return In; 5959 if (VT.bitsLT(In.getValueType())) 5960 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5961 In, N0.getOperand(1)); 5962 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5963 } 5964 5965 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5966 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5967 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5968 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5969 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5970 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5971 LN0->getChain(), 5972 LN0->getBasePtr(), LN0->getPointerInfo(), 5973 N0.getValueType(), 5974 LN0->isVolatile(), LN0->isNonTemporal(), 5975 LN0->getAlignment()); 5976 CombineTo(N, ExtLoad); 5977 CombineTo(N0.getNode(), 5978 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5979 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5980 ExtLoad.getValue(1)); 5981 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5982 } 5983 5984 return SDValue(); 5985} 5986 5987SDValue DAGCombiner::visitFNEG(SDNode *N) { 5988 SDValue N0 = N->getOperand(0); 5989 EVT VT = N->getValueType(0); 5990 5991 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 5992 &DAG.getTarget().Options)) 5993 return GetNegatedExpression(N0, DAG, LegalOperations); 5994 5995 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5996 // constant pool values. 5997 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 5998 !VT.isVector() && 5999 N0.getNode()->hasOneUse() && 6000 N0.getOperand(0).getValueType().isInteger()) { 6001 SDValue Int = N0.getOperand(0); 6002 EVT IntVT = Int.getValueType(); 6003 if (IntVT.isInteger() && !IntVT.isVector()) { 6004 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6005 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6006 AddToWorkList(Int.getNode()); 6007 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6008 VT, Int); 6009 } 6010 } 6011 6012 return SDValue(); 6013} 6014 6015SDValue DAGCombiner::visitFABS(SDNode *N) { 6016 SDValue N0 = N->getOperand(0); 6017 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6018 EVT VT = N->getValueType(0); 6019 6020 // fold (fabs c1) -> fabs(c1) 6021 if (N0CFP && VT != MVT::ppcf128) 6022 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6023 // fold (fabs (fabs x)) -> (fabs x) 6024 if (N0.getOpcode() == ISD::FABS) 6025 return N->getOperand(0); 6026 // fold (fabs (fneg x)) -> (fabs x) 6027 // fold (fabs (fcopysign x, y)) -> (fabs x) 6028 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6029 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6030 6031 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6032 // constant pool values. 6033 if (!TLI.isFAbsFree(VT) && 6034 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6035 N0.getOperand(0).getValueType().isInteger() && 6036 !N0.getOperand(0).getValueType().isVector()) { 6037 SDValue Int = N0.getOperand(0); 6038 EVT IntVT = Int.getValueType(); 6039 if (IntVT.isInteger() && !IntVT.isVector()) { 6040 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6041 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6042 AddToWorkList(Int.getNode()); 6043 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6044 N->getValueType(0), Int); 6045 } 6046 } 6047 6048 return SDValue(); 6049} 6050 6051SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6052 SDValue Chain = N->getOperand(0); 6053 SDValue N1 = N->getOperand(1); 6054 SDValue N2 = N->getOperand(2); 6055 6056 // If N is a constant we could fold this into a fallthrough or unconditional 6057 // branch. However that doesn't happen very often in normal code, because 6058 // Instcombine/SimplifyCFG should have handled the available opportunities. 6059 // If we did this folding here, it would be necessary to update the 6060 // MachineBasicBlock CFG, which is awkward. 6061 6062 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6063 // on the target. 6064 if (N1.getOpcode() == ISD::SETCC && 6065 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6066 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6067 Chain, N1.getOperand(2), 6068 N1.getOperand(0), N1.getOperand(1), N2); 6069 } 6070 6071 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6072 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6073 (N1.getOperand(0).hasOneUse() && 6074 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6075 SDNode *Trunc = 0; 6076 if (N1.getOpcode() == ISD::TRUNCATE) { 6077 // Look pass the truncate. 6078 Trunc = N1.getNode(); 6079 N1 = N1.getOperand(0); 6080 } 6081 6082 // Match this pattern so that we can generate simpler code: 6083 // 6084 // %a = ... 6085 // %b = and i32 %a, 2 6086 // %c = srl i32 %b, 1 6087 // brcond i32 %c ... 6088 // 6089 // into 6090 // 6091 // %a = ... 6092 // %b = and i32 %a, 2 6093 // %c = setcc eq %b, 0 6094 // brcond %c ... 6095 // 6096 // This applies only when the AND constant value has one bit set and the 6097 // SRL constant is equal to the log2 of the AND constant. The back-end is 6098 // smart enough to convert the result into a TEST/JMP sequence. 6099 SDValue Op0 = N1.getOperand(0); 6100 SDValue Op1 = N1.getOperand(1); 6101 6102 if (Op0.getOpcode() == ISD::AND && 6103 Op1.getOpcode() == ISD::Constant) { 6104 SDValue AndOp1 = Op0.getOperand(1); 6105 6106 if (AndOp1.getOpcode() == ISD::Constant) { 6107 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6108 6109 if (AndConst.isPowerOf2() && 6110 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6111 SDValue SetCC = 6112 DAG.getSetCC(N->getDebugLoc(), 6113 TLI.getSetCCResultType(Op0.getValueType()), 6114 Op0, DAG.getConstant(0, Op0.getValueType()), 6115 ISD::SETNE); 6116 6117 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6118 MVT::Other, Chain, SetCC, N2); 6119 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6120 // will convert it back to (X & C1) >> C2. 6121 CombineTo(N, NewBRCond, false); 6122 // Truncate is dead. 6123 if (Trunc) { 6124 removeFromWorkList(Trunc); 6125 DAG.DeleteNode(Trunc); 6126 } 6127 // Replace the uses of SRL with SETCC 6128 WorkListRemover DeadNodes(*this); 6129 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 6130 removeFromWorkList(N1.getNode()); 6131 DAG.DeleteNode(N1.getNode()); 6132 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6133 } 6134 } 6135 } 6136 6137 if (Trunc) 6138 // Restore N1 if the above transformation doesn't match. 6139 N1 = N->getOperand(1); 6140 } 6141 6142 // Transform br(xor(x, y)) -> br(x != y) 6143 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6144 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6145 SDNode *TheXor = N1.getNode(); 6146 SDValue Op0 = TheXor->getOperand(0); 6147 SDValue Op1 = TheXor->getOperand(1); 6148 if (Op0.getOpcode() == Op1.getOpcode()) { 6149 // Avoid missing important xor optimizations. 6150 SDValue Tmp = visitXOR(TheXor); 6151 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6152 DEBUG(dbgs() << "\nReplacing.8 "; 6153 TheXor->dump(&DAG); 6154 dbgs() << "\nWith: "; 6155 Tmp.getNode()->dump(&DAG); 6156 dbgs() << '\n'); 6157 WorkListRemover DeadNodes(*this); 6158 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 6159 removeFromWorkList(TheXor); 6160 DAG.DeleteNode(TheXor); 6161 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6162 MVT::Other, Chain, Tmp, N2); 6163 } 6164 } 6165 6166 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6167 bool Equal = false; 6168 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6169 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6170 Op0.getOpcode() == ISD::XOR) { 6171 TheXor = Op0.getNode(); 6172 Equal = true; 6173 } 6174 6175 EVT SetCCVT = N1.getValueType(); 6176 if (LegalTypes) 6177 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6178 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6179 SetCCVT, 6180 Op0, Op1, 6181 Equal ? ISD::SETEQ : ISD::SETNE); 6182 // Replace the uses of XOR with SETCC 6183 WorkListRemover DeadNodes(*this); 6184 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 6185 removeFromWorkList(N1.getNode()); 6186 DAG.DeleteNode(N1.getNode()); 6187 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6188 MVT::Other, Chain, SetCC, N2); 6189 } 6190 } 6191 6192 return SDValue(); 6193} 6194 6195// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6196// 6197SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6198 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6199 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6200 6201 // If N is a constant we could fold this into a fallthrough or unconditional 6202 // branch. However that doesn't happen very often in normal code, because 6203 // Instcombine/SimplifyCFG should have handled the available opportunities. 6204 // If we did this folding here, it would be necessary to update the 6205 // MachineBasicBlock CFG, which is awkward. 6206 6207 // Use SimplifySetCC to simplify SETCC's. 6208 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6209 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6210 false); 6211 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6212 6213 // fold to a simpler setcc 6214 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6215 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6216 N->getOperand(0), Simp.getOperand(2), 6217 Simp.getOperand(0), Simp.getOperand(1), 6218 N->getOperand(4)); 6219 6220 return SDValue(); 6221} 6222 6223/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6224/// uses N as its base pointer and that N may be folded in the load / store 6225/// addressing mode. 6226static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6227 SelectionDAG &DAG, 6228 const TargetLowering &TLI) { 6229 EVT VT; 6230 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6231 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6232 return false; 6233 VT = Use->getValueType(0); 6234 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6235 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6236 return false; 6237 VT = ST->getValue().getValueType(); 6238 } else 6239 return false; 6240 6241 TargetLowering::AddrMode AM; 6242 if (N->getOpcode() == ISD::ADD) { 6243 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6244 if (Offset) 6245 // [reg +/- imm] 6246 AM.BaseOffs = Offset->getSExtValue(); 6247 else 6248 // [reg +/- reg] 6249 AM.Scale = 1; 6250 } else if (N->getOpcode() == ISD::SUB) { 6251 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6252 if (Offset) 6253 // [reg +/- imm] 6254 AM.BaseOffs = -Offset->getSExtValue(); 6255 else 6256 // [reg +/- reg] 6257 AM.Scale = 1; 6258 } else 6259 return false; 6260 6261 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6262} 6263 6264/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6265/// pre-indexed load / store when the base pointer is an add or subtract 6266/// and it has other uses besides the load / store. After the 6267/// transformation, the new indexed load / store has effectively folded 6268/// the add / subtract in and all of its other uses are redirected to the 6269/// new load / store. 6270bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6271 if (Level < AfterLegalizeDAG) 6272 return false; 6273 6274 bool isLoad = true; 6275 SDValue Ptr; 6276 EVT VT; 6277 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6278 if (LD->isIndexed()) 6279 return false; 6280 VT = LD->getMemoryVT(); 6281 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6282 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6283 return false; 6284 Ptr = LD->getBasePtr(); 6285 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6286 if (ST->isIndexed()) 6287 return false; 6288 VT = ST->getMemoryVT(); 6289 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6290 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6291 return false; 6292 Ptr = ST->getBasePtr(); 6293 isLoad = false; 6294 } else { 6295 return false; 6296 } 6297 6298 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6299 // out. There is no reason to make this a preinc/predec. 6300 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6301 Ptr.getNode()->hasOneUse()) 6302 return false; 6303 6304 // Ask the target to do addressing mode selection. 6305 SDValue BasePtr; 6306 SDValue Offset; 6307 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6308 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6309 return false; 6310 // Don't create a indexed load / store with zero offset. 6311 if (isa<ConstantSDNode>(Offset) && 6312 cast<ConstantSDNode>(Offset)->isNullValue()) 6313 return false; 6314 6315 // Try turning it into a pre-indexed load / store except when: 6316 // 1) The new base ptr is a frame index. 6317 // 2) If N is a store and the new base ptr is either the same as or is a 6318 // predecessor of the value being stored. 6319 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6320 // that would create a cycle. 6321 // 4) All uses are load / store ops that use it as old base ptr. 6322 6323 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6324 // (plus the implicit offset) to a register to preinc anyway. 6325 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6326 return false; 6327 6328 // Check #2. 6329 if (!isLoad) { 6330 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6331 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6332 return false; 6333 } 6334 6335 // Now check for #3 and #4. 6336 bool RealUse = false; 6337 6338 // Caches for hasPredecessorHelper 6339 SmallPtrSet<const SDNode *, 32> Visited; 6340 SmallVector<const SDNode *, 16> Worklist; 6341 6342 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6343 E = Ptr.getNode()->use_end(); I != E; ++I) { 6344 SDNode *Use = *I; 6345 if (Use == N) 6346 continue; 6347 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6348 return false; 6349 6350 // If Ptr may be folded in addressing mode of other use, then it's 6351 // not profitable to do this transformation. 6352 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6353 RealUse = true; 6354 } 6355 6356 if (!RealUse) 6357 return false; 6358 6359 SDValue Result; 6360 if (isLoad) 6361 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6362 BasePtr, Offset, AM); 6363 else 6364 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6365 BasePtr, Offset, AM); 6366 ++PreIndexedNodes; 6367 ++NodesCombined; 6368 DEBUG(dbgs() << "\nReplacing.4 "; 6369 N->dump(&DAG); 6370 dbgs() << "\nWith: "; 6371 Result.getNode()->dump(&DAG); 6372 dbgs() << '\n'); 6373 WorkListRemover DeadNodes(*this); 6374 if (isLoad) { 6375 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6376 &DeadNodes); 6377 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6378 &DeadNodes); 6379 } else { 6380 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6381 &DeadNodes); 6382 } 6383 6384 // Finally, since the node is now dead, remove it from the graph. 6385 DAG.DeleteNode(N); 6386 6387 // Replace the uses of Ptr with uses of the updated base value. 6388 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 6389 &DeadNodes); 6390 removeFromWorkList(Ptr.getNode()); 6391 DAG.DeleteNode(Ptr.getNode()); 6392 6393 return true; 6394} 6395 6396/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6397/// add / sub of the base pointer node into a post-indexed load / store. 6398/// The transformation folded the add / subtract into the new indexed 6399/// load / store effectively and all of its uses are redirected to the 6400/// new load / store. 6401bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6402 if (Level < AfterLegalizeDAG) 6403 return false; 6404 6405 bool isLoad = true; 6406 SDValue Ptr; 6407 EVT VT; 6408 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6409 if (LD->isIndexed()) 6410 return false; 6411 VT = LD->getMemoryVT(); 6412 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6413 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6414 return false; 6415 Ptr = LD->getBasePtr(); 6416 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6417 if (ST->isIndexed()) 6418 return false; 6419 VT = ST->getMemoryVT(); 6420 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6421 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6422 return false; 6423 Ptr = ST->getBasePtr(); 6424 isLoad = false; 6425 } else { 6426 return false; 6427 } 6428 6429 if (Ptr.getNode()->hasOneUse()) 6430 return false; 6431 6432 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6433 E = Ptr.getNode()->use_end(); I != E; ++I) { 6434 SDNode *Op = *I; 6435 if (Op == N || 6436 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6437 continue; 6438 6439 SDValue BasePtr; 6440 SDValue Offset; 6441 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6442 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6443 // Don't create a indexed load / store with zero offset. 6444 if (isa<ConstantSDNode>(Offset) && 6445 cast<ConstantSDNode>(Offset)->isNullValue()) 6446 continue; 6447 6448 // Try turning it into a post-indexed load / store except when 6449 // 1) All uses are load / store ops that use it as base ptr (and 6450 // it may be folded as addressing mmode). 6451 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6452 // nor a successor of N. Otherwise, if Op is folded that would 6453 // create a cycle. 6454 6455 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6456 continue; 6457 6458 // Check for #1. 6459 bool TryNext = false; 6460 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6461 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6462 SDNode *Use = *II; 6463 if (Use == Ptr.getNode()) 6464 continue; 6465 6466 // If all the uses are load / store addresses, then don't do the 6467 // transformation. 6468 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6469 bool RealUse = false; 6470 for (SDNode::use_iterator III = Use->use_begin(), 6471 EEE = Use->use_end(); III != EEE; ++III) { 6472 SDNode *UseUse = *III; 6473 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6474 RealUse = true; 6475 } 6476 6477 if (!RealUse) { 6478 TryNext = true; 6479 break; 6480 } 6481 } 6482 } 6483 6484 if (TryNext) 6485 continue; 6486 6487 // Check for #2 6488 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6489 SDValue Result = isLoad 6490 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6491 BasePtr, Offset, AM) 6492 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6493 BasePtr, Offset, AM); 6494 ++PostIndexedNodes; 6495 ++NodesCombined; 6496 DEBUG(dbgs() << "\nReplacing.5 "; 6497 N->dump(&DAG); 6498 dbgs() << "\nWith: "; 6499 Result.getNode()->dump(&DAG); 6500 dbgs() << '\n'); 6501 WorkListRemover DeadNodes(*this); 6502 if (isLoad) { 6503 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6504 &DeadNodes); 6505 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6506 &DeadNodes); 6507 } else { 6508 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6509 &DeadNodes); 6510 } 6511 6512 // Finally, since the node is now dead, remove it from the graph. 6513 DAG.DeleteNode(N); 6514 6515 // Replace the uses of Use with uses of the updated base value. 6516 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6517 Result.getValue(isLoad ? 1 : 0), 6518 &DeadNodes); 6519 removeFromWorkList(Op); 6520 DAG.DeleteNode(Op); 6521 return true; 6522 } 6523 } 6524 } 6525 6526 return false; 6527} 6528 6529SDValue DAGCombiner::visitLOAD(SDNode *N) { 6530 LoadSDNode *LD = cast<LoadSDNode>(N); 6531 SDValue Chain = LD->getChain(); 6532 SDValue Ptr = LD->getBasePtr(); 6533 6534 // If load is not volatile and there are no uses of the loaded value (and 6535 // the updated indexed value in case of indexed loads), change uses of the 6536 // chain value into uses of the chain input (i.e. delete the dead load). 6537 if (!LD->isVolatile()) { 6538 if (N->getValueType(1) == MVT::Other) { 6539 // Unindexed loads. 6540 if (!N->hasAnyUseOfValue(0)) { 6541 // It's not safe to use the two value CombineTo variant here. e.g. 6542 // v1, chain2 = load chain1, loc 6543 // v2, chain3 = load chain2, loc 6544 // v3 = add v2, c 6545 // Now we replace use of chain2 with chain1. This makes the second load 6546 // isomorphic to the one we are deleting, and thus makes this load live. 6547 DEBUG(dbgs() << "\nReplacing.6 "; 6548 N->dump(&DAG); 6549 dbgs() << "\nWith chain: "; 6550 Chain.getNode()->dump(&DAG); 6551 dbgs() << "\n"); 6552 WorkListRemover DeadNodes(*this); 6553 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 6554 6555 if (N->use_empty()) { 6556 removeFromWorkList(N); 6557 DAG.DeleteNode(N); 6558 } 6559 6560 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6561 } 6562 } else { 6563 // Indexed loads. 6564 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 6565 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 6566 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 6567 DEBUG(dbgs() << "\nReplacing.7 "; 6568 N->dump(&DAG); 6569 dbgs() << "\nWith: "; 6570 Undef.getNode()->dump(&DAG); 6571 dbgs() << " and 2 other values\n"); 6572 WorkListRemover DeadNodes(*this); 6573 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 6574 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 6575 DAG.getUNDEF(N->getValueType(1)), 6576 &DeadNodes); 6577 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 6578 removeFromWorkList(N); 6579 DAG.DeleteNode(N); 6580 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6581 } 6582 } 6583 } 6584 6585 // If this load is directly stored, replace the load value with the stored 6586 // value. 6587 // TODO: Handle store large -> read small portion. 6588 // TODO: Handle TRUNCSTORE/LOADEXT 6589 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 6590 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 6591 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 6592 if (PrevST->getBasePtr() == Ptr && 6593 PrevST->getValue().getValueType() == N->getValueType(0)) 6594 return CombineTo(N, Chain.getOperand(1), Chain); 6595 } 6596 } 6597 6598 // Try to infer better alignment information than the load already has. 6599 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 6600 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6601 if (Align > LD->getAlignment()) 6602 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 6603 LD->getValueType(0), 6604 Chain, Ptr, LD->getPointerInfo(), 6605 LD->getMemoryVT(), 6606 LD->isVolatile(), LD->isNonTemporal(), Align); 6607 } 6608 } 6609 6610 if (CombinerAA) { 6611 // Walk up chain skipping non-aliasing memory nodes. 6612 SDValue BetterChain = FindBetterChain(N, Chain); 6613 6614 // If there is a better chain. 6615 if (Chain != BetterChain) { 6616 SDValue ReplLoad; 6617 6618 // Replace the chain to void dependency. 6619 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 6620 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 6621 BetterChain, Ptr, LD->getPointerInfo(), 6622 LD->isVolatile(), LD->isNonTemporal(), 6623 LD->isInvariant(), LD->getAlignment()); 6624 } else { 6625 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 6626 LD->getValueType(0), 6627 BetterChain, Ptr, LD->getPointerInfo(), 6628 LD->getMemoryVT(), 6629 LD->isVolatile(), 6630 LD->isNonTemporal(), 6631 LD->getAlignment()); 6632 } 6633 6634 // Create token factor to keep old chain connected. 6635 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6636 MVT::Other, Chain, ReplLoad.getValue(1)); 6637 6638 // Make sure the new and old chains are cleaned up. 6639 AddToWorkList(Token.getNode()); 6640 6641 // Replace uses with load result and token factor. Don't add users 6642 // to work list. 6643 return CombineTo(N, ReplLoad.getValue(0), Token, false); 6644 } 6645 } 6646 6647 // Try transforming N to an indexed load. 6648 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6649 return SDValue(N, 0); 6650 6651 return SDValue(); 6652} 6653 6654/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 6655/// load is having specific bytes cleared out. If so, return the byte size 6656/// being masked out and the shift amount. 6657static std::pair<unsigned, unsigned> 6658CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 6659 std::pair<unsigned, unsigned> Result(0, 0); 6660 6661 // Check for the structure we're looking for. 6662 if (V->getOpcode() != ISD::AND || 6663 !isa<ConstantSDNode>(V->getOperand(1)) || 6664 !ISD::isNormalLoad(V->getOperand(0).getNode())) 6665 return Result; 6666 6667 // Check the chain and pointer. 6668 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 6669 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 6670 6671 // The store should be chained directly to the load or be an operand of a 6672 // tokenfactor. 6673 if (LD == Chain.getNode()) 6674 ; // ok. 6675 else if (Chain->getOpcode() != ISD::TokenFactor) 6676 return Result; // Fail. 6677 else { 6678 bool isOk = false; 6679 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 6680 if (Chain->getOperand(i).getNode() == LD) { 6681 isOk = true; 6682 break; 6683 } 6684 if (!isOk) return Result; 6685 } 6686 6687 // This only handles simple types. 6688 if (V.getValueType() != MVT::i16 && 6689 V.getValueType() != MVT::i32 && 6690 V.getValueType() != MVT::i64) 6691 return Result; 6692 6693 // Check the constant mask. Invert it so that the bits being masked out are 6694 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6695 // follow the sign bit for uniformity. 6696 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6697 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6698 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6699 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6700 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6701 if (NotMaskLZ == 64) return Result; // All zero mask. 6702 6703 // See if we have a continuous run of bits. If so, we have 0*1+0* 6704 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6705 return Result; 6706 6707 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6708 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6709 NotMaskLZ -= 64-V.getValueSizeInBits(); 6710 6711 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6712 switch (MaskedBytes) { 6713 case 1: 6714 case 2: 6715 case 4: break; 6716 default: return Result; // All one mask, or 5-byte mask. 6717 } 6718 6719 // Verify that the first bit starts at a multiple of mask so that the access 6720 // is aligned the same as the access width. 6721 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6722 6723 Result.first = MaskedBytes; 6724 Result.second = NotMaskTZ/8; 6725 return Result; 6726} 6727 6728 6729/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6730/// provides a value as specified by MaskInfo. If so, replace the specified 6731/// store with a narrower store of truncated IVal. 6732static SDNode * 6733ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6734 SDValue IVal, StoreSDNode *St, 6735 DAGCombiner *DC) { 6736 unsigned NumBytes = MaskInfo.first; 6737 unsigned ByteShift = MaskInfo.second; 6738 SelectionDAG &DAG = DC->getDAG(); 6739 6740 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6741 // that uses this. If not, this is not a replacement. 6742 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6743 ByteShift*8, (ByteShift+NumBytes)*8); 6744 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6745 6746 // Check that it is legal on the target to do this. It is legal if the new 6747 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6748 // legalization. 6749 MVT VT = MVT::getIntegerVT(NumBytes*8); 6750 if (!DC->isTypeLegal(VT)) 6751 return 0; 6752 6753 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6754 // shifted by ByteShift and truncated down to NumBytes. 6755 if (ByteShift) 6756 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6757 DAG.getConstant(ByteShift*8, 6758 DC->getShiftAmountTy(IVal.getValueType()))); 6759 6760 // Figure out the offset for the store and the alignment of the access. 6761 unsigned StOffset; 6762 unsigned NewAlign = St->getAlignment(); 6763 6764 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6765 StOffset = ByteShift; 6766 else 6767 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6768 6769 SDValue Ptr = St->getBasePtr(); 6770 if (StOffset) { 6771 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6772 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6773 NewAlign = MinAlign(NewAlign, StOffset); 6774 } 6775 6776 // Truncate down to the new size. 6777 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6778 6779 ++OpsNarrowed; 6780 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6781 St->getPointerInfo().getWithOffset(StOffset), 6782 false, false, NewAlign).getNode(); 6783} 6784 6785 6786/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6787/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6788/// of the loaded bits, try narrowing the load and store if it would end up 6789/// being a win for performance or code size. 6790SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6791 StoreSDNode *ST = cast<StoreSDNode>(N); 6792 if (ST->isVolatile()) 6793 return SDValue(); 6794 6795 SDValue Chain = ST->getChain(); 6796 SDValue Value = ST->getValue(); 6797 SDValue Ptr = ST->getBasePtr(); 6798 EVT VT = Value.getValueType(); 6799 6800 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6801 return SDValue(); 6802 6803 unsigned Opc = Value.getOpcode(); 6804 6805 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6806 // is a byte mask indicating a consecutive number of bytes, check to see if 6807 // Y is known to provide just those bytes. If so, we try to replace the 6808 // load + replace + store sequence with a single (narrower) store, which makes 6809 // the load dead. 6810 if (Opc == ISD::OR) { 6811 std::pair<unsigned, unsigned> MaskedLoad; 6812 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6813 if (MaskedLoad.first) 6814 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6815 Value.getOperand(1), ST,this)) 6816 return SDValue(NewST, 0); 6817 6818 // Or is commutative, so try swapping X and Y. 6819 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6820 if (MaskedLoad.first) 6821 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6822 Value.getOperand(0), ST,this)) 6823 return SDValue(NewST, 0); 6824 } 6825 6826 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6827 Value.getOperand(1).getOpcode() != ISD::Constant) 6828 return SDValue(); 6829 6830 SDValue N0 = Value.getOperand(0); 6831 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6832 Chain == SDValue(N0.getNode(), 1)) { 6833 LoadSDNode *LD = cast<LoadSDNode>(N0); 6834 if (LD->getBasePtr() != Ptr || 6835 LD->getPointerInfo().getAddrSpace() != 6836 ST->getPointerInfo().getAddrSpace()) 6837 return SDValue(); 6838 6839 // Find the type to narrow it the load / op / store to. 6840 SDValue N1 = Value.getOperand(1); 6841 unsigned BitWidth = N1.getValueSizeInBits(); 6842 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6843 if (Opc == ISD::AND) 6844 Imm ^= APInt::getAllOnesValue(BitWidth); 6845 if (Imm == 0 || Imm.isAllOnesValue()) 6846 return SDValue(); 6847 unsigned ShAmt = Imm.countTrailingZeros(); 6848 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6849 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6850 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6851 while (NewBW < BitWidth && 6852 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6853 TLI.isNarrowingProfitable(VT, NewVT))) { 6854 NewBW = NextPowerOf2(NewBW); 6855 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6856 } 6857 if (NewBW >= BitWidth) 6858 return SDValue(); 6859 6860 // If the lsb changed does not start at the type bitwidth boundary, 6861 // start at the previous one. 6862 if (ShAmt % NewBW) 6863 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6864 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6865 if ((Imm & Mask) == Imm) { 6866 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6867 if (Opc == ISD::AND) 6868 NewImm ^= APInt::getAllOnesValue(NewBW); 6869 uint64_t PtrOff = ShAmt / 8; 6870 // For big endian targets, we need to adjust the offset to the pointer to 6871 // load the correct bytes. 6872 if (TLI.isBigEndian()) 6873 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6874 6875 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6876 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6877 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6878 return SDValue(); 6879 6880 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6881 Ptr.getValueType(), Ptr, 6882 DAG.getConstant(PtrOff, Ptr.getValueType())); 6883 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6884 LD->getChain(), NewPtr, 6885 LD->getPointerInfo().getWithOffset(PtrOff), 6886 LD->isVolatile(), LD->isNonTemporal(), 6887 LD->isInvariant(), NewAlign); 6888 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6889 DAG.getConstant(NewImm, NewVT)); 6890 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6891 NewVal, NewPtr, 6892 ST->getPointerInfo().getWithOffset(PtrOff), 6893 false, false, NewAlign); 6894 6895 AddToWorkList(NewPtr.getNode()); 6896 AddToWorkList(NewLD.getNode()); 6897 AddToWorkList(NewVal.getNode()); 6898 WorkListRemover DeadNodes(*this); 6899 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6900 &DeadNodes); 6901 ++OpsNarrowed; 6902 return NewST; 6903 } 6904 } 6905 6906 return SDValue(); 6907} 6908 6909/// TransformFPLoadStorePair - For a given floating point load / store pair, 6910/// if the load value isn't used by any other operations, then consider 6911/// transforming the pair to integer load / store operations if the target 6912/// deems the transformation profitable. 6913SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6914 StoreSDNode *ST = cast<StoreSDNode>(N); 6915 SDValue Chain = ST->getChain(); 6916 SDValue Value = ST->getValue(); 6917 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6918 Value.hasOneUse() && 6919 Chain == SDValue(Value.getNode(), 1)) { 6920 LoadSDNode *LD = cast<LoadSDNode>(Value); 6921 EVT VT = LD->getMemoryVT(); 6922 if (!VT.isFloatingPoint() || 6923 VT != ST->getMemoryVT() || 6924 LD->isNonTemporal() || 6925 ST->isNonTemporal() || 6926 LD->getPointerInfo().getAddrSpace() != 0 || 6927 ST->getPointerInfo().getAddrSpace() != 0) 6928 return SDValue(); 6929 6930 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6931 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6932 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6933 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6934 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6935 return SDValue(); 6936 6937 unsigned LDAlign = LD->getAlignment(); 6938 unsigned STAlign = ST->getAlignment(); 6939 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6940 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6941 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6942 return SDValue(); 6943 6944 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6945 LD->getChain(), LD->getBasePtr(), 6946 LD->getPointerInfo(), 6947 false, false, false, LDAlign); 6948 6949 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6950 NewLD, ST->getBasePtr(), 6951 ST->getPointerInfo(), 6952 false, false, STAlign); 6953 6954 AddToWorkList(NewLD.getNode()); 6955 AddToWorkList(NewST.getNode()); 6956 WorkListRemover DeadNodes(*this); 6957 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6958 &DeadNodes); 6959 ++LdStFP2Int; 6960 return NewST; 6961 } 6962 6963 return SDValue(); 6964} 6965 6966SDValue DAGCombiner::visitSTORE(SDNode *N) { 6967 StoreSDNode *ST = cast<StoreSDNode>(N); 6968 SDValue Chain = ST->getChain(); 6969 SDValue Value = ST->getValue(); 6970 SDValue Ptr = ST->getBasePtr(); 6971 6972 // If this is a store of a bit convert, store the input value if the 6973 // resultant store does not need a higher alignment than the original. 6974 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6975 ST->isUnindexed()) { 6976 unsigned OrigAlign = ST->getAlignment(); 6977 EVT SVT = Value.getOperand(0).getValueType(); 6978 unsigned Align = TLI.getTargetData()-> 6979 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6980 if (Align <= OrigAlign && 6981 ((!LegalOperations && !ST->isVolatile()) || 6982 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6983 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6984 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6985 ST->isNonTemporal(), OrigAlign); 6986 } 6987 6988 // Turn 'store undef, Ptr' -> nothing. 6989 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6990 return Chain; 6991 6992 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6993 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6994 // NOTE: If the original store is volatile, this transform must not increase 6995 // the number of stores. For example, on x86-32 an f64 can be stored in one 6996 // processor operation but an i64 (which is not legal) requires two. So the 6997 // transform should not be done in this case. 6998 if (Value.getOpcode() != ISD::TargetConstantFP) { 6999 SDValue Tmp; 7000 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 7001 default: llvm_unreachable("Unknown FP type"); 7002 case MVT::f80: // We don't do this for these yet. 7003 case MVT::f128: 7004 case MVT::ppcf128: 7005 break; 7006 case MVT::f32: 7007 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 7008 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7009 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 7010 bitcastToAPInt().getZExtValue(), MVT::i32); 7011 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7012 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7013 ST->isNonTemporal(), ST->getAlignment()); 7014 } 7015 break; 7016 case MVT::f64: 7017 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 7018 !ST->isVolatile()) || 7019 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 7020 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 7021 getZExtValue(), MVT::i64); 7022 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7023 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7024 ST->isNonTemporal(), ST->getAlignment()); 7025 } 7026 7027 if (!ST->isVolatile() && 7028 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7029 // Many FP stores are not made apparent until after legalize, e.g. for 7030 // argument passing. Since this is so common, custom legalize the 7031 // 64-bit integer store into two 32-bit stores. 7032 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 7033 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 7034 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 7035 if (TLI.isBigEndian()) std::swap(Lo, Hi); 7036 7037 unsigned Alignment = ST->getAlignment(); 7038 bool isVolatile = ST->isVolatile(); 7039 bool isNonTemporal = ST->isNonTemporal(); 7040 7041 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 7042 Ptr, ST->getPointerInfo(), 7043 isVolatile, isNonTemporal, 7044 ST->getAlignment()); 7045 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 7046 DAG.getConstant(4, Ptr.getValueType())); 7047 Alignment = MinAlign(Alignment, 4U); 7048 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 7049 Ptr, ST->getPointerInfo().getWithOffset(4), 7050 isVolatile, isNonTemporal, 7051 Alignment); 7052 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7053 St0, St1); 7054 } 7055 7056 break; 7057 } 7058 } 7059 } 7060 7061 // Try to infer better alignment information than the store already has. 7062 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 7063 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7064 if (Align > ST->getAlignment()) 7065 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 7066 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7067 ST->isVolatile(), ST->isNonTemporal(), Align); 7068 } 7069 } 7070 7071 // Try transforming a pair floating point load / store ops to integer 7072 // load / store ops. 7073 SDValue NewST = TransformFPLoadStorePair(N); 7074 if (NewST.getNode()) 7075 return NewST; 7076 7077 if (CombinerAA) { 7078 // Walk up chain skipping non-aliasing memory nodes. 7079 SDValue BetterChain = FindBetterChain(N, Chain); 7080 7081 // If there is a better chain. 7082 if (Chain != BetterChain) { 7083 SDValue ReplStore; 7084 7085 // Replace the chain to avoid dependency. 7086 if (ST->isTruncatingStore()) { 7087 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7088 ST->getPointerInfo(), 7089 ST->getMemoryVT(), ST->isVolatile(), 7090 ST->isNonTemporal(), ST->getAlignment()); 7091 } else { 7092 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7093 ST->getPointerInfo(), 7094 ST->isVolatile(), ST->isNonTemporal(), 7095 ST->getAlignment()); 7096 } 7097 7098 // Create token to keep both nodes around. 7099 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7100 MVT::Other, Chain, ReplStore); 7101 7102 // Make sure the new and old chains are cleaned up. 7103 AddToWorkList(Token.getNode()); 7104 7105 // Don't add users to work list. 7106 return CombineTo(N, Token, false); 7107 } 7108 } 7109 7110 // Try transforming N to an indexed store. 7111 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7112 return SDValue(N, 0); 7113 7114 // FIXME: is there such a thing as a truncating indexed store? 7115 if (ST->isTruncatingStore() && ST->isUnindexed() && 7116 Value.getValueType().isInteger()) { 7117 // See if we can simplify the input to this truncstore with knowledge that 7118 // only the low bits are being used. For example: 7119 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 7120 SDValue Shorter = 7121 GetDemandedBits(Value, 7122 APInt::getLowBitsSet( 7123 Value.getValueType().getScalarType().getSizeInBits(), 7124 ST->getMemoryVT().getScalarType().getSizeInBits())); 7125 AddToWorkList(Value.getNode()); 7126 if (Shorter.getNode()) 7127 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 7128 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7129 ST->isVolatile(), ST->isNonTemporal(), 7130 ST->getAlignment()); 7131 7132 // Otherwise, see if we can simplify the operation with 7133 // SimplifyDemandedBits, which only works if the value has a single use. 7134 if (SimplifyDemandedBits(Value, 7135 APInt::getLowBitsSet( 7136 Value.getValueType().getScalarType().getSizeInBits(), 7137 ST->getMemoryVT().getScalarType().getSizeInBits()))) 7138 return SDValue(N, 0); 7139 } 7140 7141 // If this is a load followed by a store to the same location, then the store 7142 // is dead/noop. 7143 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 7144 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 7145 ST->isUnindexed() && !ST->isVolatile() && 7146 // There can't be any side effects between the load and store, such as 7147 // a call or store. 7148 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 7149 // The store is dead, remove it. 7150 return Chain; 7151 } 7152 } 7153 7154 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 7155 // truncating store. We can do this even if this is already a truncstore. 7156 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 7157 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 7158 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 7159 ST->getMemoryVT())) { 7160 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7161 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7162 ST->isVolatile(), ST->isNonTemporal(), 7163 ST->getAlignment()); 7164 } 7165 7166 return ReduceLoadOpStoreWidth(N); 7167} 7168 7169SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 7170 SDValue InVec = N->getOperand(0); 7171 SDValue InVal = N->getOperand(1); 7172 SDValue EltNo = N->getOperand(2); 7173 DebugLoc dl = N->getDebugLoc(); 7174 7175 // If the inserted element is an UNDEF, just use the input vector. 7176 if (InVal.getOpcode() == ISD::UNDEF) 7177 return InVec; 7178 7179 EVT VT = InVec.getValueType(); 7180 7181 // If we can't generate a legal BUILD_VECTOR, exit 7182 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 7183 return SDValue(); 7184 7185 // Check that we know which element is being inserted 7186 if (!isa<ConstantSDNode>(EltNo)) 7187 return SDValue(); 7188 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7189 7190 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 7191 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 7192 // vector elements. 7193 SmallVector<SDValue, 8> Ops; 7194 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 7195 Ops.append(InVec.getNode()->op_begin(), 7196 InVec.getNode()->op_end()); 7197 } else if (InVec.getOpcode() == ISD::UNDEF) { 7198 unsigned NElts = VT.getVectorNumElements(); 7199 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 7200 } else { 7201 return SDValue(); 7202 } 7203 7204 // Insert the element 7205 if (Elt < Ops.size()) { 7206 // All the operands of BUILD_VECTOR must have the same type; 7207 // we enforce that here. 7208 EVT OpVT = Ops[0].getValueType(); 7209 if (InVal.getValueType() != OpVT) 7210 InVal = OpVT.bitsGT(InVal.getValueType()) ? 7211 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 7212 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 7213 Ops[Elt] = InVal; 7214 } 7215 7216 // Return the new vector 7217 return DAG.getNode(ISD::BUILD_VECTOR, dl, 7218 VT, &Ops[0], Ops.size()); 7219} 7220 7221SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 7222 // (vextract (scalar_to_vector val, 0) -> val 7223 SDValue InVec = N->getOperand(0); 7224 EVT VT = InVec.getValueType(); 7225 EVT NVT = N->getValueType(0); 7226 7227 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 7228 // Check if the result type doesn't match the inserted element type. A 7229 // SCALAR_TO_VECTOR may truncate the inserted element and the 7230 // EXTRACT_VECTOR_ELT may widen the extracted vector. 7231 SDValue InOp = InVec.getOperand(0); 7232 if (InOp.getValueType() != NVT) { 7233 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 7234 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 7235 } 7236 return InOp; 7237 } 7238 7239 SDValue EltNo = N->getOperand(1); 7240 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 7241 7242 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 7243 // We only perform this optimization before the op legalization phase because 7244 // we may introduce new vector instructions which are not backed by TD patterns. 7245 // For example on AVX, extracting elements from a wide vector without using 7246 // extract_subvector. 7247 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 7248 && ConstEltNo && !LegalOperations) { 7249 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7250 int NumElem = VT.getVectorNumElements(); 7251 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 7252 // Find the new index to extract from. 7253 int OrigElt = SVOp->getMaskElt(Elt); 7254 7255 // Extracting an undef index is undef. 7256 if (OrigElt == -1) 7257 return DAG.getUNDEF(NVT); 7258 7259 // Select the right vector half to extract from. 7260 if (OrigElt < NumElem) { 7261 InVec = InVec->getOperand(0); 7262 } else { 7263 InVec = InVec->getOperand(1); 7264 OrigElt -= NumElem; 7265 } 7266 7267 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 7268 InVec, DAG.getConstant(OrigElt, MVT::i32)); 7269 } 7270 7271 // Perform only after legalization to ensure build_vector / vector_shuffle 7272 // optimizations have already been done. 7273 if (!LegalOperations) return SDValue(); 7274 7275 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 7276 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 7277 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 7278 7279 if (ConstEltNo) { 7280 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7281 bool NewLoad = false; 7282 bool BCNumEltsChanged = false; 7283 EVT ExtVT = VT.getVectorElementType(); 7284 EVT LVT = ExtVT; 7285 7286 // If the result of load has to be truncated, then it's not necessarily 7287 // profitable. 7288 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 7289 return SDValue(); 7290 7291 if (InVec.getOpcode() == ISD::BITCAST) { 7292 // Don't duplicate a load with other uses. 7293 if (!InVec.hasOneUse()) 7294 return SDValue(); 7295 7296 EVT BCVT = InVec.getOperand(0).getValueType(); 7297 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 7298 return SDValue(); 7299 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 7300 BCNumEltsChanged = true; 7301 InVec = InVec.getOperand(0); 7302 ExtVT = BCVT.getVectorElementType(); 7303 NewLoad = true; 7304 } 7305 7306 LoadSDNode *LN0 = NULL; 7307 const ShuffleVectorSDNode *SVN = NULL; 7308 if (ISD::isNormalLoad(InVec.getNode())) { 7309 LN0 = cast<LoadSDNode>(InVec); 7310 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 7311 InVec.getOperand(0).getValueType() == ExtVT && 7312 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 7313 // Don't duplicate a load with other uses. 7314 if (!InVec.hasOneUse()) 7315 return SDValue(); 7316 7317 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 7318 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 7319 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 7320 // => 7321 // (load $addr+1*size) 7322 7323 // Don't duplicate a load with other uses. 7324 if (!InVec.hasOneUse()) 7325 return SDValue(); 7326 7327 // If the bit convert changed the number of elements, it is unsafe 7328 // to examine the mask. 7329 if (BCNumEltsChanged) 7330 return SDValue(); 7331 7332 // Select the input vector, guarding against out of range extract vector. 7333 unsigned NumElems = VT.getVectorNumElements(); 7334 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7335 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7336 7337 if (InVec.getOpcode() == ISD::BITCAST) { 7338 // Don't duplicate a load with other uses. 7339 if (!InVec.hasOneUse()) 7340 return SDValue(); 7341 7342 InVec = InVec.getOperand(0); 7343 } 7344 if (ISD::isNormalLoad(InVec.getNode())) { 7345 LN0 = cast<LoadSDNode>(InVec); 7346 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7347 } 7348 } 7349 7350 // Make sure we found a non-volatile load and the extractelement is 7351 // the only use. 7352 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7353 return SDValue(); 7354 7355 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7356 if (Elt == -1) 7357 return DAG.getUNDEF(LVT); 7358 7359 unsigned Align = LN0->getAlignment(); 7360 if (NewLoad) { 7361 // Check the resultant load doesn't need a higher alignment than the 7362 // original load. 7363 unsigned NewAlign = 7364 TLI.getTargetData() 7365 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7366 7367 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7368 return SDValue(); 7369 7370 Align = NewAlign; 7371 } 7372 7373 SDValue NewPtr = LN0->getBasePtr(); 7374 unsigned PtrOff = 0; 7375 7376 if (Elt) { 7377 PtrOff = LVT.getSizeInBits() * Elt / 8; 7378 EVT PtrType = NewPtr.getValueType(); 7379 if (TLI.isBigEndian()) 7380 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7381 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7382 DAG.getConstant(PtrOff, PtrType)); 7383 } 7384 7385 // The replacement we need to do here is a little tricky: we need to 7386 // replace an extractelement of a load with a load. 7387 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7388 // Note that this replacement assumes that the extractvalue is the only 7389 // use of the load; that's okay because we don't want to perform this 7390 // transformation in other cases anyway. 7391 SDValue Load; 7392 SDValue Chain; 7393 if (NVT.bitsGT(LVT)) { 7394 // If the result type of vextract is wider than the load, then issue an 7395 // extending load instead. 7396 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 7397 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 7398 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 7399 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 7400 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 7401 Chain = Load.getValue(1); 7402 } else { 7403 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7404 LN0->getPointerInfo().getWithOffset(PtrOff), 7405 LN0->isVolatile(), LN0->isNonTemporal(), 7406 LN0->isInvariant(), Align); 7407 Chain = Load.getValue(1); 7408 if (NVT.bitsLT(LVT)) 7409 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 7410 else 7411 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 7412 } 7413 WorkListRemover DeadNodes(*this); 7414 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7415 SDValue To[] = { Load, Chain }; 7416 DAG.ReplaceAllUsesOfValuesWith(From, To, 2, &DeadNodes); 7417 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7418 // worklist explicitly as well. 7419 AddToWorkList(Load.getNode()); 7420 AddUsersToWorkList(Load.getNode()); // Add users too 7421 // Make sure to revisit this node to clean it up; it will usually be dead. 7422 AddToWorkList(N); 7423 return SDValue(N, 0); 7424 } 7425 7426 return SDValue(); 7427} 7428 7429SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7430 unsigned NumInScalars = N->getNumOperands(); 7431 DebugLoc dl = N->getDebugLoc(); 7432 EVT VT = N->getValueType(0); 7433 // Check to see if this is a BUILD_VECTOR of a bunch of values 7434 // which come from any_extend or zero_extend nodes. If so, we can create 7435 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7436 // optimizations. We do not handle sign-extend because we can't fill the sign 7437 // using shuffles. 7438 EVT SourceType = MVT::Other; 7439 bool AllAnyExt = true; 7440 bool AllUndef = true; 7441 for (unsigned i = 0; i != NumInScalars; ++i) { 7442 SDValue In = N->getOperand(i); 7443 // Ignore undef inputs. 7444 if (In.getOpcode() == ISD::UNDEF) continue; 7445 AllUndef = false; 7446 7447 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7448 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7449 7450 // Abort if the element is not an extension. 7451 if (!ZeroExt && !AnyExt) { 7452 SourceType = MVT::Other; 7453 break; 7454 } 7455 7456 // The input is a ZeroExt or AnyExt. Check the original type. 7457 EVT InTy = In.getOperand(0).getValueType(); 7458 7459 // Check that all of the widened source types are the same. 7460 if (SourceType == MVT::Other) 7461 // First time. 7462 SourceType = InTy; 7463 else if (InTy != SourceType) { 7464 // Multiple income types. Abort. 7465 SourceType = MVT::Other; 7466 break; 7467 } 7468 7469 // Check if all of the extends are ANY_EXTENDs. 7470 AllAnyExt &= AnyExt; 7471 } 7472 7473 if (AllUndef) 7474 return DAG.getUNDEF(VT); 7475 7476 // In order to have valid types, all of the inputs must be extended from the 7477 // same source type and all of the inputs must be any or zero extend. 7478 // Scalar sizes must be a power of two. 7479 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7480 bool ValidTypes = SourceType != MVT::Other && 7481 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7482 isPowerOf2_32(SourceType.getSizeInBits()); 7483 7484 // We perform this optimization post type-legalization because 7485 // the type-legalizer often scalarizes integer-promoted vectors. 7486 // Performing this optimization before may create bit-casts which 7487 // will be type-legalized to complex code sequences. 7488 // We perform this optimization only before the operation legalizer because we 7489 // may introduce illegal operations. 7490 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 7491 // turn into a single shuffle instruction. 7492 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 7493 ValidTypes) { 7494 bool isLE = TLI.isLittleEndian(); 7495 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7496 assert(ElemRatio > 1 && "Invalid element size ratio"); 7497 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 7498 DAG.getConstant(0, SourceType); 7499 7500 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7501 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7502 7503 // Populate the new build_vector 7504 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7505 SDValue Cast = N->getOperand(i); 7506 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7507 Cast.getOpcode() == ISD::ZERO_EXTEND || 7508 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7509 SDValue In; 7510 if (Cast.getOpcode() == ISD::UNDEF) 7511 In = DAG.getUNDEF(SourceType); 7512 else 7513 In = Cast->getOperand(0); 7514 unsigned Index = isLE ? (i * ElemRatio) : 7515 (i * ElemRatio + (ElemRatio - 1)); 7516 7517 assert(Index < Ops.size() && "Invalid index"); 7518 Ops[Index] = In; 7519 } 7520 7521 // The type of the new BUILD_VECTOR node. 7522 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 7523 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 7524 "Invalid vector size"); 7525 // Check if the new vector type is legal. 7526 if (!isTypeLegal(VecVT)) return SDValue(); 7527 7528 // Make the new BUILD_VECTOR. 7529 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7530 VecVT, &Ops[0], Ops.size()); 7531 7532 // The new BUILD_VECTOR node has the potential to be further optimized. 7533 AddToWorkList(BV.getNode()); 7534 // Bitcast to the desired type. 7535 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 7536 } 7537 7538 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 7539 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 7540 // at most two distinct vectors, turn this into a shuffle node. 7541 7542 // May only combine to shuffle after legalize if shuffle is legal. 7543 if (LegalOperations && 7544 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 7545 return SDValue(); 7546 7547 SDValue VecIn1, VecIn2; 7548 for (unsigned i = 0; i != NumInScalars; ++i) { 7549 // Ignore undef inputs. 7550 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 7551 7552 // If this input is something other than a EXTRACT_VECTOR_ELT with a 7553 // constant index, bail out. 7554 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 7555 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 7556 VecIn1 = VecIn2 = SDValue(0, 0); 7557 break; 7558 } 7559 7560 // We allow up to two distinct input vectors. 7561 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 7562 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 7563 continue; 7564 7565 if (VecIn1.getNode() == 0) { 7566 VecIn1 = ExtractedFromVec; 7567 } else if (VecIn2.getNode() == 0) { 7568 VecIn2 = ExtractedFromVec; 7569 } else { 7570 // Too many inputs. 7571 VecIn1 = VecIn2 = SDValue(0, 0); 7572 break; 7573 } 7574 } 7575 7576 // If everything is good, we can make a shuffle operation. 7577 if (VecIn1.getNode()) { 7578 SmallVector<int, 8> Mask; 7579 for (unsigned i = 0; i != NumInScalars; ++i) { 7580 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 7581 Mask.push_back(-1); 7582 continue; 7583 } 7584 7585 // If extracting from the first vector, just use the index directly. 7586 SDValue Extract = N->getOperand(i); 7587 SDValue ExtVal = Extract.getOperand(1); 7588 if (Extract.getOperand(0) == VecIn1) { 7589 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7590 if (ExtIndex > VT.getVectorNumElements()) 7591 return SDValue(); 7592 7593 Mask.push_back(ExtIndex); 7594 continue; 7595 } 7596 7597 // Otherwise, use InIdx + VecSize 7598 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7599 Mask.push_back(Idx+NumInScalars); 7600 } 7601 7602 // We can't generate a shuffle node with mismatched input and output types. 7603 // Attempt to transform a single input vector to the correct type. 7604 if ((VT != VecIn1.getValueType())) { 7605 // We don't support shuffeling between TWO values of different types. 7606 if (VecIn2.getNode() != 0) 7607 return SDValue(); 7608 7609 // We only support widening of vectors which are half the size of the 7610 // output registers. For example XMM->YMM widening on X86 with AVX. 7611 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 7612 return SDValue(); 7613 7614 // Widen the input vector by adding undef values. 7615 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7616 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 7617 } 7618 7619 // If VecIn2 is unused then change it to undef. 7620 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 7621 7622 // Check that we were able to transform all incoming values to the same type. 7623 if (VecIn2.getValueType() != VecIn1.getValueType() || 7624 VecIn1.getValueType() != VT) 7625 return SDValue(); 7626 7627 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 7628 if (!isTypeLegal(VT)) 7629 return SDValue(); 7630 7631 // Return the new VECTOR_SHUFFLE node. 7632 SDValue Ops[2]; 7633 Ops[0] = VecIn1; 7634 Ops[1] = VecIn2; 7635 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 7636 } 7637 7638 return SDValue(); 7639} 7640 7641SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 7642 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 7643 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 7644 // inputs come from at most two distinct vectors, turn this into a shuffle 7645 // node. 7646 7647 // If we only have one input vector, we don't need to do any concatenation. 7648 if (N->getNumOperands() == 1) 7649 return N->getOperand(0); 7650 7651 return SDValue(); 7652} 7653 7654SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 7655 EVT NVT = N->getValueType(0); 7656 SDValue V = N->getOperand(0); 7657 7658 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 7659 // Handle only simple case where vector being inserted and vector 7660 // being extracted are of same type, and are half size of larger vectors. 7661 EVT BigVT = V->getOperand(0).getValueType(); 7662 EVT SmallVT = V->getOperand(1).getValueType(); 7663 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 7664 return SDValue(); 7665 7666 // Only handle cases where both indexes are constants with the same type. 7667 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7668 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 7669 7670 if (InsIdx && ExtIdx && 7671 InsIdx->getValueType(0).getSizeInBits() <= 64 && 7672 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 7673 // Combine: 7674 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 7675 // Into: 7676 // indices are equal => V1 7677 // otherwise => (extract_subvec V1, ExtIdx) 7678 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 7679 return V->getOperand(1); 7680 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 7681 V->getOperand(0), N->getOperand(1)); 7682 } 7683 } 7684 7685 return SDValue(); 7686} 7687 7688SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 7689 EVT VT = N->getValueType(0); 7690 unsigned NumElts = VT.getVectorNumElements(); 7691 7692 SDValue N0 = N->getOperand(0); 7693 SDValue N1 = N->getOperand(1); 7694 7695 assert(N0.getValueType().getVectorNumElements() == NumElts && 7696 "Vector shuffle must be normalized in DAG"); 7697 7698 // Canonicalize shuffle undef, undef -> undef 7699 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 7700 return DAG.getUNDEF(VT); 7701 7702 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7703 7704 // Canonicalize shuffle v, v -> v, undef 7705 if (N0 == N1) { 7706 SmallVector<int, 8> NewMask; 7707 for (unsigned i = 0; i != NumElts; ++i) { 7708 int Idx = SVN->getMaskElt(i); 7709 if (Idx >= (int)NumElts) Idx -= NumElts; 7710 NewMask.push_back(Idx); 7711 } 7712 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 7713 &NewMask[0]); 7714 } 7715 7716 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 7717 if (N0.getOpcode() == ISD::UNDEF) { 7718 SmallVector<int, 8> NewMask; 7719 for (unsigned i = 0; i != NumElts; ++i) { 7720 int Idx = SVN->getMaskElt(i); 7721 if (Idx < 0) 7722 NewMask.push_back(Idx); 7723 else if (Idx < (int)NumElts) 7724 NewMask.push_back(Idx + NumElts); 7725 else 7726 NewMask.push_back(Idx - NumElts); 7727 } 7728 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 7729 &NewMask[0]); 7730 } 7731 7732 // Remove references to rhs if it is undef 7733 if (N1.getOpcode() == ISD::UNDEF) { 7734 bool Changed = false; 7735 SmallVector<int, 8> NewMask; 7736 for (unsigned i = 0; i != NumElts; ++i) { 7737 int Idx = SVN->getMaskElt(i); 7738 if (Idx >= (int)NumElts) { 7739 Idx = -1; 7740 Changed = true; 7741 } 7742 NewMask.push_back(Idx); 7743 } 7744 if (Changed) 7745 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 7746 } 7747 7748 // If it is a splat, check if the argument vector is another splat or a 7749 // build_vector with all scalar elements the same. 7750 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 7751 SDNode *V = N0.getNode(); 7752 7753 // If this is a bit convert that changes the element type of the vector but 7754 // not the number of vector elements, look through it. Be careful not to 7755 // look though conversions that change things like v4f32 to v2f64. 7756 if (V->getOpcode() == ISD::BITCAST) { 7757 SDValue ConvInput = V->getOperand(0); 7758 if (ConvInput.getValueType().isVector() && 7759 ConvInput.getValueType().getVectorNumElements() == NumElts) 7760 V = ConvInput.getNode(); 7761 } 7762 7763 if (V->getOpcode() == ISD::BUILD_VECTOR) { 7764 assert(V->getNumOperands() == NumElts && 7765 "BUILD_VECTOR has wrong number of operands"); 7766 SDValue Base; 7767 bool AllSame = true; 7768 for (unsigned i = 0; i != NumElts; ++i) { 7769 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 7770 Base = V->getOperand(i); 7771 break; 7772 } 7773 } 7774 // Splat of <u, u, u, u>, return <u, u, u, u> 7775 if (!Base.getNode()) 7776 return N0; 7777 for (unsigned i = 0; i != NumElts; ++i) { 7778 if (V->getOperand(i) != Base) { 7779 AllSame = false; 7780 break; 7781 } 7782 } 7783 // Splat of <x, x, x, x>, return <x, x, x, x> 7784 if (AllSame) 7785 return N0; 7786 } 7787 } 7788 7789 // If this shuffle node is simply a swizzle of another shuffle node, 7790 // optimize shuffle(shuffle(x, y), undef) -> shuffle(x, y). 7791 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 7792 N1.getOpcode() == ISD::UNDEF) { 7793 7794 SmallVector<int, 8> NewMask; 7795 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 7796 7797 // If the source shuffle has more than one user then do not try to optimize 7798 // it because it may generate a more complex shuffle node. However, if the 7799 // source shuffle is also a swizzle (a single source shuffle), our 7800 // transformation is still likely to reduce the number of shuffles and only 7801 // generate a simple shuffle node. 7802 if (N0.getOperand(1).getOpcode() != ISD::UNDEF && !N0.hasOneUse()) 7803 return SDValue(); 7804 7805 EVT InVT = N0.getValueType(); 7806 int InNumElts = InVT.getVectorNumElements(); 7807 7808 for (unsigned i = 0; i != NumElts; ++i) { 7809 int Idx = SVN->getMaskElt(i); 7810 // If we access the second (undef) operand then this index can be 7811 // canonicalized to undef as well. 7812 if (Idx >= InNumElts) 7813 Idx = -1; 7814 // Next, this index comes from the first value, which is the incoming 7815 // shuffle. Adopt the incoming index. 7816 if (Idx >= 0) 7817 Idx = OtherSV->getMaskElt(Idx); 7818 7819 NewMask.push_back(Idx); 7820 } 7821 assert(NewMask.size() == VT.getVectorNumElements() && "Invalid mask size"); 7822 return DAG.getVectorShuffle(VT, N->getDebugLoc(), OtherSV->getOperand(0), 7823 OtherSV->getOperand(1), &NewMask[0]); 7824 } 7825 7826 return SDValue(); 7827} 7828 7829SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 7830 if (!TLI.getShouldFoldAtomicFences()) 7831 return SDValue(); 7832 7833 SDValue atomic = N->getOperand(0); 7834 switch (atomic.getOpcode()) { 7835 case ISD::ATOMIC_CMP_SWAP: 7836 case ISD::ATOMIC_SWAP: 7837 case ISD::ATOMIC_LOAD_ADD: 7838 case ISD::ATOMIC_LOAD_SUB: 7839 case ISD::ATOMIC_LOAD_AND: 7840 case ISD::ATOMIC_LOAD_OR: 7841 case ISD::ATOMIC_LOAD_XOR: 7842 case ISD::ATOMIC_LOAD_NAND: 7843 case ISD::ATOMIC_LOAD_MIN: 7844 case ISD::ATOMIC_LOAD_MAX: 7845 case ISD::ATOMIC_LOAD_UMIN: 7846 case ISD::ATOMIC_LOAD_UMAX: 7847 break; 7848 default: 7849 return SDValue(); 7850 } 7851 7852 SDValue fence = atomic.getOperand(0); 7853 if (fence.getOpcode() != ISD::MEMBARRIER) 7854 return SDValue(); 7855 7856 switch (atomic.getOpcode()) { 7857 case ISD::ATOMIC_CMP_SWAP: 7858 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7859 fence.getOperand(0), 7860 atomic.getOperand(1), atomic.getOperand(2), 7861 atomic.getOperand(3)), atomic.getResNo()); 7862 case ISD::ATOMIC_SWAP: 7863 case ISD::ATOMIC_LOAD_ADD: 7864 case ISD::ATOMIC_LOAD_SUB: 7865 case ISD::ATOMIC_LOAD_AND: 7866 case ISD::ATOMIC_LOAD_OR: 7867 case ISD::ATOMIC_LOAD_XOR: 7868 case ISD::ATOMIC_LOAD_NAND: 7869 case ISD::ATOMIC_LOAD_MIN: 7870 case ISD::ATOMIC_LOAD_MAX: 7871 case ISD::ATOMIC_LOAD_UMIN: 7872 case ISD::ATOMIC_LOAD_UMAX: 7873 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7874 fence.getOperand(0), 7875 atomic.getOperand(1), atomic.getOperand(2)), 7876 atomic.getResNo()); 7877 default: 7878 return SDValue(); 7879 } 7880} 7881 7882/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 7883/// an AND to a vector_shuffle with the destination vector and a zero vector. 7884/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 7885/// vector_shuffle V, Zero, <0, 4, 2, 4> 7886SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 7887 EVT VT = N->getValueType(0); 7888 DebugLoc dl = N->getDebugLoc(); 7889 SDValue LHS = N->getOperand(0); 7890 SDValue RHS = N->getOperand(1); 7891 if (N->getOpcode() == ISD::AND) { 7892 if (RHS.getOpcode() == ISD::BITCAST) 7893 RHS = RHS.getOperand(0); 7894 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 7895 SmallVector<int, 8> Indices; 7896 unsigned NumElts = RHS.getNumOperands(); 7897 for (unsigned i = 0; i != NumElts; ++i) { 7898 SDValue Elt = RHS.getOperand(i); 7899 if (!isa<ConstantSDNode>(Elt)) 7900 return SDValue(); 7901 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 7902 Indices.push_back(i); 7903 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 7904 Indices.push_back(NumElts); 7905 else 7906 return SDValue(); 7907 } 7908 7909 // Let's see if the target supports this vector_shuffle. 7910 EVT RVT = RHS.getValueType(); 7911 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 7912 return SDValue(); 7913 7914 // Return the new VECTOR_SHUFFLE node. 7915 EVT EltVT = RVT.getVectorElementType(); 7916 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 7917 DAG.getConstant(0, EltVT)); 7918 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7919 RVT, &ZeroOps[0], ZeroOps.size()); 7920 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 7921 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 7922 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 7923 } 7924 } 7925 7926 return SDValue(); 7927} 7928 7929/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 7930SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 7931 // After legalize, the target may be depending on adds and other 7932 // binary ops to provide legal ways to construct constants or other 7933 // things. Simplifying them may result in a loss of legality. 7934 if (LegalOperations) return SDValue(); 7935 7936 assert(N->getValueType(0).isVector() && 7937 "SimplifyVBinOp only works on vectors!"); 7938 7939 SDValue LHS = N->getOperand(0); 7940 SDValue RHS = N->getOperand(1); 7941 SDValue Shuffle = XformToShuffleWithZero(N); 7942 if (Shuffle.getNode()) return Shuffle; 7943 7944 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 7945 // this operation. 7946 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 7947 RHS.getOpcode() == ISD::BUILD_VECTOR) { 7948 SmallVector<SDValue, 8> Ops; 7949 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 7950 SDValue LHSOp = LHS.getOperand(i); 7951 SDValue RHSOp = RHS.getOperand(i); 7952 // If these two elements can't be folded, bail out. 7953 if ((LHSOp.getOpcode() != ISD::UNDEF && 7954 LHSOp.getOpcode() != ISD::Constant && 7955 LHSOp.getOpcode() != ISD::ConstantFP) || 7956 (RHSOp.getOpcode() != ISD::UNDEF && 7957 RHSOp.getOpcode() != ISD::Constant && 7958 RHSOp.getOpcode() != ISD::ConstantFP)) 7959 break; 7960 7961 // Can't fold divide by zero. 7962 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 7963 N->getOpcode() == ISD::FDIV) { 7964 if ((RHSOp.getOpcode() == ISD::Constant && 7965 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 7966 (RHSOp.getOpcode() == ISD::ConstantFP && 7967 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 7968 break; 7969 } 7970 7971 EVT VT = LHSOp.getValueType(); 7972 EVT RVT = RHSOp.getValueType(); 7973 if (RVT != VT) { 7974 // Integer BUILD_VECTOR operands may have types larger than the element 7975 // size (e.g., when the element type is not legal). Prior to type 7976 // legalization, the types may not match between the two BUILD_VECTORS. 7977 // Truncate one of the operands to make them match. 7978 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 7979 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 7980 } else { 7981 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 7982 VT = RVT; 7983 } 7984 } 7985 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 7986 LHSOp, RHSOp); 7987 if (FoldOp.getOpcode() != ISD::UNDEF && 7988 FoldOp.getOpcode() != ISD::Constant && 7989 FoldOp.getOpcode() != ISD::ConstantFP) 7990 break; 7991 Ops.push_back(FoldOp); 7992 AddToWorkList(FoldOp.getNode()); 7993 } 7994 7995 if (Ops.size() == LHS.getNumOperands()) 7996 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7997 LHS.getValueType(), &Ops[0], Ops.size()); 7998 } 7999 8000 return SDValue(); 8001} 8002 8003SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 8004 SDValue N1, SDValue N2){ 8005 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 8006 8007 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 8008 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 8009 8010 // If we got a simplified select_cc node back from SimplifySelectCC, then 8011 // break it down into a new SETCC node, and a new SELECT node, and then return 8012 // the SELECT node, since we were called with a SELECT node. 8013 if (SCC.getNode()) { 8014 // Check to see if we got a select_cc back (to turn into setcc/select). 8015 // Otherwise, just return whatever node we got back, like fabs. 8016 if (SCC.getOpcode() == ISD::SELECT_CC) { 8017 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 8018 N0.getValueType(), 8019 SCC.getOperand(0), SCC.getOperand(1), 8020 SCC.getOperand(4)); 8021 AddToWorkList(SETCC.getNode()); 8022 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 8023 SCC.getOperand(2), SCC.getOperand(3), SETCC); 8024 } 8025 8026 return SCC; 8027 } 8028 return SDValue(); 8029} 8030 8031/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 8032/// are the two values being selected between, see if we can simplify the 8033/// select. Callers of this should assume that TheSelect is deleted if this 8034/// returns true. As such, they should return the appropriate thing (e.g. the 8035/// node) back to the top-level of the DAG combiner loop to avoid it being 8036/// looked at. 8037bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 8038 SDValue RHS) { 8039 8040 // Cannot simplify select with vector condition 8041 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 8042 8043 // If this is a select from two identical things, try to pull the operation 8044 // through the select. 8045 if (LHS.getOpcode() != RHS.getOpcode() || 8046 !LHS.hasOneUse() || !RHS.hasOneUse()) 8047 return false; 8048 8049 // If this is a load and the token chain is identical, replace the select 8050 // of two loads with a load through a select of the address to load from. 8051 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 8052 // constants have been dropped into the constant pool. 8053 if (LHS.getOpcode() == ISD::LOAD) { 8054 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 8055 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 8056 8057 // Token chains must be identical. 8058 if (LHS.getOperand(0) != RHS.getOperand(0) || 8059 // Do not let this transformation reduce the number of volatile loads. 8060 LLD->isVolatile() || RLD->isVolatile() || 8061 // If this is an EXTLOAD, the VT's must match. 8062 LLD->getMemoryVT() != RLD->getMemoryVT() || 8063 // If this is an EXTLOAD, the kind of extension must match. 8064 (LLD->getExtensionType() != RLD->getExtensionType() && 8065 // The only exception is if one of the extensions is anyext. 8066 LLD->getExtensionType() != ISD::EXTLOAD && 8067 RLD->getExtensionType() != ISD::EXTLOAD) || 8068 // FIXME: this discards src value information. This is 8069 // over-conservative. It would be beneficial to be able to remember 8070 // both potential memory locations. Since we are discarding 8071 // src value info, don't do the transformation if the memory 8072 // locations are not in the default address space. 8073 LLD->getPointerInfo().getAddrSpace() != 0 || 8074 RLD->getPointerInfo().getAddrSpace() != 0) 8075 return false; 8076 8077 // Check that the select condition doesn't reach either load. If so, 8078 // folding this will induce a cycle into the DAG. If not, this is safe to 8079 // xform, so create a select of the addresses. 8080 SDValue Addr; 8081 if (TheSelect->getOpcode() == ISD::SELECT) { 8082 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 8083 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 8084 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 8085 return false; 8086 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 8087 LLD->getBasePtr().getValueType(), 8088 TheSelect->getOperand(0), LLD->getBasePtr(), 8089 RLD->getBasePtr()); 8090 } else { // Otherwise SELECT_CC 8091 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 8092 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 8093 8094 if ((LLD->hasAnyUseOfValue(1) && 8095 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 8096 (RLD->hasAnyUseOfValue(1) && 8097 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 8098 return false; 8099 8100 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 8101 LLD->getBasePtr().getValueType(), 8102 TheSelect->getOperand(0), 8103 TheSelect->getOperand(1), 8104 LLD->getBasePtr(), RLD->getBasePtr(), 8105 TheSelect->getOperand(4)); 8106 } 8107 8108 SDValue Load; 8109 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 8110 Load = DAG.getLoad(TheSelect->getValueType(0), 8111 TheSelect->getDebugLoc(), 8112 // FIXME: Discards pointer info. 8113 LLD->getChain(), Addr, MachinePointerInfo(), 8114 LLD->isVolatile(), LLD->isNonTemporal(), 8115 LLD->isInvariant(), LLD->getAlignment()); 8116 } else { 8117 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 8118 RLD->getExtensionType() : LLD->getExtensionType(), 8119 TheSelect->getDebugLoc(), 8120 TheSelect->getValueType(0), 8121 // FIXME: Discards pointer info. 8122 LLD->getChain(), Addr, MachinePointerInfo(), 8123 LLD->getMemoryVT(), LLD->isVolatile(), 8124 LLD->isNonTemporal(), LLD->getAlignment()); 8125 } 8126 8127 // Users of the select now use the result of the load. 8128 CombineTo(TheSelect, Load); 8129 8130 // Users of the old loads now use the new load's chain. We know the 8131 // old-load value is dead now. 8132 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 8133 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 8134 return true; 8135 } 8136 8137 return false; 8138} 8139 8140/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 8141/// where 'cond' is the comparison specified by CC. 8142SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 8143 SDValue N2, SDValue N3, 8144 ISD::CondCode CC, bool NotExtCompare) { 8145 // (x ? y : y) -> y. 8146 if (N2 == N3) return N2; 8147 8148 EVT VT = N2.getValueType(); 8149 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 8150 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 8151 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 8152 8153 // Determine if the condition we're dealing with is constant 8154 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 8155 N0, N1, CC, DL, false); 8156 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 8157 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 8158 8159 // fold select_cc true, x, y -> x 8160 if (SCCC && !SCCC->isNullValue()) 8161 return N2; 8162 // fold select_cc false, x, y -> y 8163 if (SCCC && SCCC->isNullValue()) 8164 return N3; 8165 8166 // Check to see if we can simplify the select into an fabs node 8167 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 8168 // Allow either -0.0 or 0.0 8169 if (CFP->getValueAPF().isZero()) { 8170 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 8171 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 8172 N0 == N2 && N3.getOpcode() == ISD::FNEG && 8173 N2 == N3.getOperand(0)) 8174 return DAG.getNode(ISD::FABS, DL, VT, N0); 8175 8176 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 8177 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 8178 N0 == N3 && N2.getOpcode() == ISD::FNEG && 8179 N2.getOperand(0) == N3) 8180 return DAG.getNode(ISD::FABS, DL, VT, N3); 8181 } 8182 } 8183 8184 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 8185 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 8186 // in it. This is a win when the constant is not otherwise available because 8187 // it replaces two constant pool loads with one. We only do this if the FP 8188 // type is known to be legal, because if it isn't, then we are before legalize 8189 // types an we want the other legalization to happen first (e.g. to avoid 8190 // messing with soft float) and if the ConstantFP is not legal, because if 8191 // it is legal, we may not need to store the FP constant in a constant pool. 8192 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 8193 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 8194 if (TLI.isTypeLegal(N2.getValueType()) && 8195 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 8196 TargetLowering::Legal) && 8197 // If both constants have multiple uses, then we won't need to do an 8198 // extra load, they are likely around in registers for other users. 8199 (TV->hasOneUse() || FV->hasOneUse())) { 8200 Constant *Elts[] = { 8201 const_cast<ConstantFP*>(FV->getConstantFPValue()), 8202 const_cast<ConstantFP*>(TV->getConstantFPValue()) 8203 }; 8204 Type *FPTy = Elts[0]->getType(); 8205 const TargetData &TD = *TLI.getTargetData(); 8206 8207 // Create a ConstantArray of the two constants. 8208 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 8209 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 8210 TD.getPrefTypeAlignment(FPTy)); 8211 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8212 8213 // Get the offsets to the 0 and 1 element of the array so that we can 8214 // select between them. 8215 SDValue Zero = DAG.getIntPtrConstant(0); 8216 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 8217 SDValue One = DAG.getIntPtrConstant(EltSize); 8218 8219 SDValue Cond = DAG.getSetCC(DL, 8220 TLI.getSetCCResultType(N0.getValueType()), 8221 N0, N1, CC); 8222 AddToWorkList(Cond.getNode()); 8223 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 8224 Cond, One, Zero); 8225 AddToWorkList(CstOffset.getNode()); 8226 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 8227 CstOffset); 8228 AddToWorkList(CPIdx.getNode()); 8229 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 8230 MachinePointerInfo::getConstantPool(), false, 8231 false, false, Alignment); 8232 8233 } 8234 } 8235 8236 // Check to see if we can perform the "gzip trick", transforming 8237 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 8238 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 8239 (N1C->isNullValue() || // (a < 0) ? b : 0 8240 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 8241 EVT XType = N0.getValueType(); 8242 EVT AType = N2.getValueType(); 8243 if (XType.bitsGE(AType)) { 8244 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 8245 // single-bit constant. 8246 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 8247 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 8248 ShCtV = XType.getSizeInBits()-ShCtV-1; 8249 SDValue ShCt = DAG.getConstant(ShCtV, 8250 getShiftAmountTy(N0.getValueType())); 8251 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 8252 XType, N0, ShCt); 8253 AddToWorkList(Shift.getNode()); 8254 8255 if (XType.bitsGT(AType)) { 8256 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8257 AddToWorkList(Shift.getNode()); 8258 } 8259 8260 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8261 } 8262 8263 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 8264 XType, N0, 8265 DAG.getConstant(XType.getSizeInBits()-1, 8266 getShiftAmountTy(N0.getValueType()))); 8267 AddToWorkList(Shift.getNode()); 8268 8269 if (XType.bitsGT(AType)) { 8270 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8271 AddToWorkList(Shift.getNode()); 8272 } 8273 8274 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8275 } 8276 } 8277 8278 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 8279 // where y is has a single bit set. 8280 // A plaintext description would be, we can turn the SELECT_CC into an AND 8281 // when the condition can be materialized as an all-ones register. Any 8282 // single bit-test can be materialized as an all-ones register with 8283 // shift-left and shift-right-arith. 8284 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 8285 N0->getValueType(0) == VT && 8286 N1C && N1C->isNullValue() && 8287 N2C && N2C->isNullValue()) { 8288 SDValue AndLHS = N0->getOperand(0); 8289 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 8290 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 8291 // Shift the tested bit over the sign bit. 8292 APInt AndMask = ConstAndRHS->getAPIntValue(); 8293 SDValue ShlAmt = 8294 DAG.getConstant(AndMask.countLeadingZeros(), 8295 getShiftAmountTy(AndLHS.getValueType())); 8296 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 8297 8298 // Now arithmetic right shift it all the way over, so the result is either 8299 // all-ones, or zero. 8300 SDValue ShrAmt = 8301 DAG.getConstant(AndMask.getBitWidth()-1, 8302 getShiftAmountTy(Shl.getValueType())); 8303 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 8304 8305 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 8306 } 8307 } 8308 8309 // fold select C, 16, 0 -> shl C, 4 8310 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 8311 TLI.getBooleanContents(N0.getValueType().isVector()) == 8312 TargetLowering::ZeroOrOneBooleanContent) { 8313 8314 // If the caller doesn't want us to simplify this into a zext of a compare, 8315 // don't do it. 8316 if (NotExtCompare && N2C->getAPIntValue() == 1) 8317 return SDValue(); 8318 8319 // Get a SetCC of the condition 8320 // FIXME: Should probably make sure that setcc is legal if we ever have a 8321 // target where it isn't. 8322 SDValue Temp, SCC; 8323 // cast from setcc result type to select result type 8324 if (LegalTypes) { 8325 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 8326 N0, N1, CC); 8327 if (N2.getValueType().bitsLT(SCC.getValueType())) 8328 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 8329 else 8330 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8331 N2.getValueType(), SCC); 8332 } else { 8333 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 8334 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8335 N2.getValueType(), SCC); 8336 } 8337 8338 AddToWorkList(SCC.getNode()); 8339 AddToWorkList(Temp.getNode()); 8340 8341 if (N2C->getAPIntValue() == 1) 8342 return Temp; 8343 8344 // shl setcc result by log2 n2c 8345 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 8346 DAG.getConstant(N2C->getAPIntValue().logBase2(), 8347 getShiftAmountTy(Temp.getValueType()))); 8348 } 8349 8350 // Check to see if this is the equivalent of setcc 8351 // FIXME: Turn all of these into setcc if setcc if setcc is legal 8352 // otherwise, go ahead with the folds. 8353 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 8354 EVT XType = N0.getValueType(); 8355 if (!LegalOperations || 8356 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 8357 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 8358 if (Res.getValueType() != VT) 8359 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 8360 return Res; 8361 } 8362 8363 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 8364 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 8365 (!LegalOperations || 8366 TLI.isOperationLegal(ISD::CTLZ, XType))) { 8367 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 8368 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 8369 DAG.getConstant(Log2_32(XType.getSizeInBits()), 8370 getShiftAmountTy(Ctlz.getValueType()))); 8371 } 8372 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 8373 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 8374 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 8375 XType, DAG.getConstant(0, XType), N0); 8376 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 8377 return DAG.getNode(ISD::SRL, DL, XType, 8378 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 8379 DAG.getConstant(XType.getSizeInBits()-1, 8380 getShiftAmountTy(XType))); 8381 } 8382 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 8383 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 8384 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 8385 DAG.getConstant(XType.getSizeInBits()-1, 8386 getShiftAmountTy(N0.getValueType()))); 8387 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 8388 } 8389 } 8390 8391 // Check to see if this is an integer abs. 8392 // select_cc setg[te] X, 0, X, -X -> 8393 // select_cc setgt X, -1, X, -X -> 8394 // select_cc setl[te] X, 0, -X, X -> 8395 // select_cc setlt X, 1, -X, X -> 8396 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 8397 if (N1C) { 8398 ConstantSDNode *SubC = NULL; 8399 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8400 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 8401 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 8402 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 8403 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 8404 (N1C->isOne() && CC == ISD::SETLT)) && 8405 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 8406 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 8407 8408 EVT XType = N0.getValueType(); 8409 if (SubC && SubC->isNullValue() && XType.isInteger()) { 8410 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 8411 N0, 8412 DAG.getConstant(XType.getSizeInBits()-1, 8413 getShiftAmountTy(N0.getValueType()))); 8414 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 8415 XType, N0, Shift); 8416 AddToWorkList(Shift.getNode()); 8417 AddToWorkList(Add.getNode()); 8418 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 8419 } 8420 } 8421 8422 return SDValue(); 8423} 8424 8425/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8426SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8427 SDValue N1, ISD::CondCode Cond, 8428 DebugLoc DL, bool foldBooleans) { 8429 TargetLowering::DAGCombinerInfo 8430 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8431 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8432} 8433 8434/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8435/// return a DAG expression to select that will generate the same value by 8436/// multiplying by a magic number. See: 8437/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8438SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8439 std::vector<SDNode*> Built; 8440 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8441 8442 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8443 ii != ee; ++ii) 8444 AddToWorkList(*ii); 8445 return S; 8446} 8447 8448/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8449/// return a DAG expression to select that will generate the same value by 8450/// multiplying by a magic number. See: 8451/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8452SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8453 std::vector<SDNode*> Built; 8454 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8455 8456 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8457 ii != ee; ++ii) 8458 AddToWorkList(*ii); 8459 return S; 8460} 8461 8462/// FindBaseOffset - Return true if base is a frame index, which is known not 8463// to alias with anything but itself. Provides base object and offset as 8464// results. 8465static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8466 const GlobalValue *&GV, void *&CV) { 8467 // Assume it is a primitive operation. 8468 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8469 8470 // If it's an adding a simple constant then integrate the offset. 8471 if (Base.getOpcode() == ISD::ADD) { 8472 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8473 Base = Base.getOperand(0); 8474 Offset += C->getZExtValue(); 8475 } 8476 } 8477 8478 // Return the underlying GlobalValue, and update the Offset. Return false 8479 // for GlobalAddressSDNode since the same GlobalAddress may be represented 8480 // by multiple nodes with different offsets. 8481 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 8482 GV = G->getGlobal(); 8483 Offset += G->getOffset(); 8484 return false; 8485 } 8486 8487 // Return the underlying Constant value, and update the Offset. Return false 8488 // for ConstantSDNodes since the same constant pool entry may be represented 8489 // by multiple nodes with different offsets. 8490 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 8491 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 8492 : (void *)C->getConstVal(); 8493 Offset += C->getOffset(); 8494 return false; 8495 } 8496 // If it's any of the following then it can't alias with anything but itself. 8497 return isa<FrameIndexSDNode>(Base); 8498} 8499 8500/// isAlias - Return true if there is any possibility that the two addresses 8501/// overlap. 8502bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 8503 const Value *SrcValue1, int SrcValueOffset1, 8504 unsigned SrcValueAlign1, 8505 const MDNode *TBAAInfo1, 8506 SDValue Ptr2, int64_t Size2, 8507 const Value *SrcValue2, int SrcValueOffset2, 8508 unsigned SrcValueAlign2, 8509 const MDNode *TBAAInfo2) const { 8510 // If they are the same then they must be aliases. 8511 if (Ptr1 == Ptr2) return true; 8512 8513 // Gather base node and offset information. 8514 SDValue Base1, Base2; 8515 int64_t Offset1, Offset2; 8516 const GlobalValue *GV1, *GV2; 8517 void *CV1, *CV2; 8518 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 8519 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 8520 8521 // If they have a same base address then check to see if they overlap. 8522 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 8523 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8524 8525 // It is possible for different frame indices to alias each other, mostly 8526 // when tail call optimization reuses return address slots for arguments. 8527 // To catch this case, look up the actual index of frame indices to compute 8528 // the real alias relationship. 8529 if (isFrameIndex1 && isFrameIndex2) { 8530 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8531 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 8532 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 8533 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8534 } 8535 8536 // Otherwise, if we know what the bases are, and they aren't identical, then 8537 // we know they cannot alias. 8538 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 8539 return false; 8540 8541 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 8542 // compared to the size and offset of the access, we may be able to prove they 8543 // do not alias. This check is conservative for now to catch cases created by 8544 // splitting vector types. 8545 if ((SrcValueAlign1 == SrcValueAlign2) && 8546 (SrcValueOffset1 != SrcValueOffset2) && 8547 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 8548 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 8549 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 8550 8551 // There is no overlap between these relatively aligned accesses of similar 8552 // size, return no alias. 8553 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 8554 return false; 8555 } 8556 8557 if (CombinerGlobalAA) { 8558 // Use alias analysis information. 8559 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 8560 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 8561 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 8562 AliasAnalysis::AliasResult AAResult = 8563 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 8564 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 8565 if (AAResult == AliasAnalysis::NoAlias) 8566 return false; 8567 } 8568 8569 // Otherwise we have to assume they alias. 8570 return true; 8571} 8572 8573/// FindAliasInfo - Extracts the relevant alias information from the memory 8574/// node. Returns true if the operand was a load. 8575bool DAGCombiner::FindAliasInfo(SDNode *N, 8576 SDValue &Ptr, int64_t &Size, 8577 const Value *&SrcValue, 8578 int &SrcValueOffset, 8579 unsigned &SrcValueAlign, 8580 const MDNode *&TBAAInfo) const { 8581 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 8582 8583 Ptr = LS->getBasePtr(); 8584 Size = LS->getMemoryVT().getSizeInBits() >> 3; 8585 SrcValue = LS->getSrcValue(); 8586 SrcValueOffset = LS->getSrcValueOffset(); 8587 SrcValueAlign = LS->getOriginalAlignment(); 8588 TBAAInfo = LS->getTBAAInfo(); 8589 return isa<LoadSDNode>(LS); 8590} 8591 8592/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 8593/// looking for aliasing nodes and adding them to the Aliases vector. 8594void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 8595 SmallVector<SDValue, 8> &Aliases) { 8596 SmallVector<SDValue, 8> Chains; // List of chains to visit. 8597 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 8598 8599 // Get alias information for node. 8600 SDValue Ptr; 8601 int64_t Size; 8602 const Value *SrcValue; 8603 int SrcValueOffset; 8604 unsigned SrcValueAlign; 8605 const MDNode *SrcTBAAInfo; 8606 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 8607 SrcValueAlign, SrcTBAAInfo); 8608 8609 // Starting off. 8610 Chains.push_back(OriginalChain); 8611 unsigned Depth = 0; 8612 8613 // Look at each chain and determine if it is an alias. If so, add it to the 8614 // aliases list. If not, then continue up the chain looking for the next 8615 // candidate. 8616 while (!Chains.empty()) { 8617 SDValue Chain = Chains.back(); 8618 Chains.pop_back(); 8619 8620 // For TokenFactor nodes, look at each operand and only continue up the 8621 // chain until we find two aliases. If we've seen two aliases, assume we'll 8622 // find more and revert to original chain since the xform is unlikely to be 8623 // profitable. 8624 // 8625 // FIXME: The depth check could be made to return the last non-aliasing 8626 // chain we found before we hit a tokenfactor rather than the original 8627 // chain. 8628 if (Depth > 6 || Aliases.size() == 2) { 8629 Aliases.clear(); 8630 Aliases.push_back(OriginalChain); 8631 break; 8632 } 8633 8634 // Don't bother if we've been before. 8635 if (!Visited.insert(Chain.getNode())) 8636 continue; 8637 8638 switch (Chain.getOpcode()) { 8639 case ISD::EntryToken: 8640 // Entry token is ideal chain operand, but handled in FindBetterChain. 8641 break; 8642 8643 case ISD::LOAD: 8644 case ISD::STORE: { 8645 // Get alias information for Chain. 8646 SDValue OpPtr; 8647 int64_t OpSize; 8648 const Value *OpSrcValue; 8649 int OpSrcValueOffset; 8650 unsigned OpSrcValueAlign; 8651 const MDNode *OpSrcTBAAInfo; 8652 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 8653 OpSrcValue, OpSrcValueOffset, 8654 OpSrcValueAlign, 8655 OpSrcTBAAInfo); 8656 8657 // If chain is alias then stop here. 8658 if (!(IsLoad && IsOpLoad) && 8659 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 8660 SrcTBAAInfo, 8661 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 8662 OpSrcValueAlign, OpSrcTBAAInfo)) { 8663 Aliases.push_back(Chain); 8664 } else { 8665 // Look further up the chain. 8666 Chains.push_back(Chain.getOperand(0)); 8667 ++Depth; 8668 } 8669 break; 8670 } 8671 8672 case ISD::TokenFactor: 8673 // We have to check each of the operands of the token factor for "small" 8674 // token factors, so we queue them up. Adding the operands to the queue 8675 // (stack) in reverse order maintains the original order and increases the 8676 // likelihood that getNode will find a matching token factor (CSE.) 8677 if (Chain.getNumOperands() > 16) { 8678 Aliases.push_back(Chain); 8679 break; 8680 } 8681 for (unsigned n = Chain.getNumOperands(); n;) 8682 Chains.push_back(Chain.getOperand(--n)); 8683 ++Depth; 8684 break; 8685 8686 default: 8687 // For all other instructions we will just have to take what we can get. 8688 Aliases.push_back(Chain); 8689 break; 8690 } 8691 } 8692} 8693 8694/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 8695/// for a better chain (aliasing node.) 8696SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 8697 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 8698 8699 // Accumulate all the aliases to this node. 8700 GatherAllAliases(N, OldChain, Aliases); 8701 8702 // If no operands then chain to entry token. 8703 if (Aliases.size() == 0) 8704 return DAG.getEntryNode(); 8705 8706 // If a single operand then chain to it. We don't need to revisit it. 8707 if (Aliases.size() == 1) 8708 return Aliases[0]; 8709 8710 // Construct a custom tailored token factor. 8711 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8712 &Aliases[0], Aliases.size()); 8713} 8714 8715// SelectionDAG::Combine - This is the entry point for the file. 8716// 8717void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 8718 CodeGenOpt::Level OptLevel) { 8719 /// run - This is the main entry point to this class. 8720 /// 8721 DAGCombiner(*this, AA, OptLevel).Run(Level); 8722} 8723