DAGCombiner.cpp revision 2d2536c9d7669c1ba809664dd164be50222183dd
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: make truncate see through SIGN_EXTEND and AND 26// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 27// FIXME: verify that getNode can't return extends with an operand whose type 28// is >= to that of the extend. 29// FIXME: divide by zero is currently left unfolded. do we want to turn this 30// into an undef? 31// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 32// 33//===----------------------------------------------------------------------===// 34 35#define DEBUG_TYPE "dagcombine" 36#include "llvm/ADT/Statistic.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Support/Debug.h" 39#include "llvm/Support/MathExtras.h" 40#include "llvm/Target/TargetLowering.h" 41#include <algorithm> 42#include <cmath> 43#include <iostream> 44using namespace llvm; 45 46namespace { 47 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 48 49 class DAGCombiner { 50 SelectionDAG &DAG; 51 TargetLowering &TLI; 52 bool AfterLegalize; 53 54 // Worklist of all of the nodes that need to be simplified. 55 std::vector<SDNode*> WorkList; 56 57 /// AddUsersToWorkList - When an instruction is simplified, add all users of 58 /// the instruction to the work lists because they might get more simplified 59 /// now. 60 /// 61 void AddUsersToWorkList(SDNode *N) { 62 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 63 UI != UE; ++UI) 64 WorkList.push_back(*UI); 65 } 66 67 /// removeFromWorkList - remove all instances of N from the worklist. 68 void removeFromWorkList(SDNode *N) { 69 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 70 WorkList.end()); 71 } 72 73 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 74 ++NodesCombined; 75 DEBUG(std::cerr << "\nReplacing "; N->dump(); 76 std::cerr << "\nWith: "; To[0].Val->dump(); 77 std::cerr << " and " << To.size()-1 << " other values\n"); 78 std::vector<SDNode*> NowDead; 79 DAG.ReplaceAllUsesWith(N, To, &NowDead); 80 81 // Push the new nodes and any users onto the worklist 82 for (unsigned i = 0, e = To.size(); i != e; ++i) { 83 WorkList.push_back(To[i].Val); 84 AddUsersToWorkList(To[i].Val); 85 } 86 87 // Nodes can end up on the worklist more than once. Make sure we do 88 // not process a node that has been replaced. 89 removeFromWorkList(N); 90 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 91 removeFromWorkList(NowDead[i]); 92 93 // Finally, since the node is now dead, remove it from the graph. 94 DAG.DeleteNode(N); 95 return SDOperand(N, 0); 96 } 97 98 /// SimplifyDemandedBits - Check the specified integer node value to see if 99 /// it can be simplified or if things is uses can be simplified by bit 100 /// propagation. If so, return true. 101 bool SimplifyDemandedBits(SDOperand Op) { 102 TargetLowering::TargetLoweringOpt TLO(DAG); 103 uint64_t KnownZero, KnownOne; 104 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 105 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 106 return false; 107 108 // Revisit the node. 109 WorkList.push_back(Op.Val); 110 111 // Replace the old value with the new one. 112 ++NodesCombined; 113 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 114 std::cerr << "\nWith: "; TLO.New.Val->dump()); 115 116 std::vector<SDNode*> NowDead; 117 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 118 119 // Push the new node and any (possibly new) users onto the worklist. 120 WorkList.push_back(TLO.New.Val); 121 AddUsersToWorkList(TLO.New.Val); 122 123 // Nodes can end up on the worklist more than once. Make sure we do 124 // not process a node that has been replaced. 125 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 126 removeFromWorkList(NowDead[i]); 127 128 // Finally, if the node is now dead, remove it from the graph. The node 129 // may not be dead if the replacement process recursively simplified to 130 // something else needing this node. 131 if (TLO.Old.Val->use_empty()) { 132 removeFromWorkList(TLO.Old.Val); 133 DAG.DeleteNode(TLO.Old.Val); 134 } 135 return true; 136 } 137 138 SDOperand CombineTo(SDNode *N, SDOperand Res) { 139 std::vector<SDOperand> To; 140 To.push_back(Res); 141 return CombineTo(N, To); 142 } 143 144 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 145 std::vector<SDOperand> To; 146 To.push_back(Res0); 147 To.push_back(Res1); 148 return CombineTo(N, To); 149 } 150 151 /// visit - call the node-specific routine that knows how to fold each 152 /// particular type of node. 153 SDOperand visit(SDNode *N); 154 155 // Visitation implementation - Implement dag node combining for different 156 // node types. The semantics are as follows: 157 // Return Value: 158 // SDOperand.Val == 0 - No change was made 159 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 160 // otherwise - N should be replaced by the returned Operand. 161 // 162 SDOperand visitTokenFactor(SDNode *N); 163 SDOperand visitADD(SDNode *N); 164 SDOperand visitSUB(SDNode *N); 165 SDOperand visitMUL(SDNode *N); 166 SDOperand visitSDIV(SDNode *N); 167 SDOperand visitUDIV(SDNode *N); 168 SDOperand visitSREM(SDNode *N); 169 SDOperand visitUREM(SDNode *N); 170 SDOperand visitMULHU(SDNode *N); 171 SDOperand visitMULHS(SDNode *N); 172 SDOperand visitAND(SDNode *N); 173 SDOperand visitOR(SDNode *N); 174 SDOperand visitXOR(SDNode *N); 175 SDOperand visitSHL(SDNode *N); 176 SDOperand visitSRA(SDNode *N); 177 SDOperand visitSRL(SDNode *N); 178 SDOperand visitCTLZ(SDNode *N); 179 SDOperand visitCTTZ(SDNode *N); 180 SDOperand visitCTPOP(SDNode *N); 181 SDOperand visitSELECT(SDNode *N); 182 SDOperand visitSELECT_CC(SDNode *N); 183 SDOperand visitSETCC(SDNode *N); 184 SDOperand visitSIGN_EXTEND(SDNode *N); 185 SDOperand visitZERO_EXTEND(SDNode *N); 186 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 187 SDOperand visitTRUNCATE(SDNode *N); 188 SDOperand visitBIT_CONVERT(SDNode *N); 189 SDOperand visitFADD(SDNode *N); 190 SDOperand visitFSUB(SDNode *N); 191 SDOperand visitFMUL(SDNode *N); 192 SDOperand visitFDIV(SDNode *N); 193 SDOperand visitFREM(SDNode *N); 194 SDOperand visitSINT_TO_FP(SDNode *N); 195 SDOperand visitUINT_TO_FP(SDNode *N); 196 SDOperand visitFP_TO_SINT(SDNode *N); 197 SDOperand visitFP_TO_UINT(SDNode *N); 198 SDOperand visitFP_ROUND(SDNode *N); 199 SDOperand visitFP_ROUND_INREG(SDNode *N); 200 SDOperand visitFP_EXTEND(SDNode *N); 201 SDOperand visitFNEG(SDNode *N); 202 SDOperand visitFABS(SDNode *N); 203 SDOperand visitBRCOND(SDNode *N); 204 SDOperand visitBRCONDTWOWAY(SDNode *N); 205 SDOperand visitBR_CC(SDNode *N); 206 SDOperand visitBRTWOWAY_CC(SDNode *N); 207 SDOperand visitLOAD(SDNode *N); 208 SDOperand visitSTORE(SDNode *N); 209 210 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 213 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 214 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 215 SDOperand N3, ISD::CondCode CC); 216 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 217 ISD::CondCode Cond, bool foldBooleans = true); 218 219 SDOperand BuildSDIV(SDNode *N); 220 SDOperand BuildUDIV(SDNode *N); 221public: 222 DAGCombiner(SelectionDAG &D) 223 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 224 225 /// Run - runs the dag combiner on all nodes in the work list 226 void Run(bool RunningAfterLegalize); 227 }; 228} 229 230struct ms { 231 int64_t m; // magic number 232 int64_t s; // shift amount 233}; 234 235struct mu { 236 uint64_t m; // magic number 237 int64_t a; // add indicator 238 int64_t s; // shift amount 239}; 240 241/// magic - calculate the magic numbers required to codegen an integer sdiv as 242/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 243/// or -1. 244static ms magic32(int32_t d) { 245 int32_t p; 246 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 247 const uint32_t two31 = 0x80000000U; 248 struct ms mag; 249 250 ad = abs(d); 251 t = two31 + ((uint32_t)d >> 31); 252 anc = t - 1 - t%ad; // absolute value of nc 253 p = 31; // initialize p 254 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 255 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 256 q2 = two31/ad; // initialize q2 = 2p/abs(d) 257 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 258 do { 259 p = p + 1; 260 q1 = 2*q1; // update q1 = 2p/abs(nc) 261 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 262 if (r1 >= anc) { // must be unsigned comparison 263 q1 = q1 + 1; 264 r1 = r1 - anc; 265 } 266 q2 = 2*q2; // update q2 = 2p/abs(d) 267 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 268 if (r2 >= ad) { // must be unsigned comparison 269 q2 = q2 + 1; 270 r2 = r2 - ad; 271 } 272 delta = ad - r2; 273 } while (q1 < delta || (q1 == delta && r1 == 0)); 274 275 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 276 if (d < 0) mag.m = -mag.m; // resulting magic number 277 mag.s = p - 32; // resulting shift 278 return mag; 279} 280 281/// magicu - calculate the magic numbers required to codegen an integer udiv as 282/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 283static mu magicu32(uint32_t d) { 284 int32_t p; 285 uint32_t nc, delta, q1, r1, q2, r2; 286 struct mu magu; 287 magu.a = 0; // initialize "add" indicator 288 nc = - 1 - (-d)%d; 289 p = 31; // initialize p 290 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 291 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 292 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 293 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 294 do { 295 p = p + 1; 296 if (r1 >= nc - r1 ) { 297 q1 = 2*q1 + 1; // update q1 298 r1 = 2*r1 - nc; // update r1 299 } 300 else { 301 q1 = 2*q1; // update q1 302 r1 = 2*r1; // update r1 303 } 304 if (r2 + 1 >= d - r2) { 305 if (q2 >= 0x7FFFFFFF) magu.a = 1; 306 q2 = 2*q2 + 1; // update q2 307 r2 = 2*r2 + 1 - d; // update r2 308 } 309 else { 310 if (q2 >= 0x80000000) magu.a = 1; 311 q2 = 2*q2; // update q2 312 r2 = 2*r2 + 1; // update r2 313 } 314 delta = d - 1 - r2; 315 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 316 magu.m = q2 + 1; // resulting magic number 317 magu.s = p - 32; // resulting shift 318 return magu; 319} 320 321/// magic - calculate the magic numbers required to codegen an integer sdiv as 322/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 323/// or -1. 324static ms magic64(int64_t d) { 325 int64_t p; 326 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 327 const uint64_t two63 = 9223372036854775808ULL; // 2^63 328 struct ms mag; 329 330 ad = d >= 0 ? d : -d; 331 t = two63 + ((uint64_t)d >> 63); 332 anc = t - 1 - t%ad; // absolute value of nc 333 p = 63; // initialize p 334 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 335 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 336 q2 = two63/ad; // initialize q2 = 2p/abs(d) 337 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 338 do { 339 p = p + 1; 340 q1 = 2*q1; // update q1 = 2p/abs(nc) 341 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 342 if (r1 >= anc) { // must be unsigned comparison 343 q1 = q1 + 1; 344 r1 = r1 - anc; 345 } 346 q2 = 2*q2; // update q2 = 2p/abs(d) 347 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 348 if (r2 >= ad) { // must be unsigned comparison 349 q2 = q2 + 1; 350 r2 = r2 - ad; 351 } 352 delta = ad - r2; 353 } while (q1 < delta || (q1 == delta && r1 == 0)); 354 355 mag.m = q2 + 1; 356 if (d < 0) mag.m = -mag.m; // resulting magic number 357 mag.s = p - 64; // resulting shift 358 return mag; 359} 360 361/// magicu - calculate the magic numbers required to codegen an integer udiv as 362/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 363static mu magicu64(uint64_t d) 364{ 365 int64_t p; 366 uint64_t nc, delta, q1, r1, q2, r2; 367 struct mu magu; 368 magu.a = 0; // initialize "add" indicator 369 nc = - 1 - (-d)%d; 370 p = 63; // initialize p 371 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 372 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 373 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 374 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 375 do { 376 p = p + 1; 377 if (r1 >= nc - r1 ) { 378 q1 = 2*q1 + 1; // update q1 379 r1 = 2*r1 - nc; // update r1 380 } 381 else { 382 q1 = 2*q1; // update q1 383 r1 = 2*r1; // update r1 384 } 385 if (r2 + 1 >= d - r2) { 386 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 387 q2 = 2*q2 + 1; // update q2 388 r2 = 2*r2 + 1 - d; // update r2 389 } 390 else { 391 if (q2 >= 0x8000000000000000ull) magu.a = 1; 392 q2 = 2*q2; // update q2 393 r2 = 2*r2 + 1; // update r2 394 } 395 delta = d - 1 - r2; 396 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 397 magu.m = q2 + 1; // resulting magic number 398 magu.s = p - 64; // resulting shift 399 return magu; 400} 401 402// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 403// that selects between the values 1 and 0, making it equivalent to a setcc. 404// Also, set the incoming LHS, RHS, and CC references to the appropriate 405// nodes based on the type of node we are checking. This simplifies life a 406// bit for the callers. 407static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 408 SDOperand &CC) { 409 if (N.getOpcode() == ISD::SETCC) { 410 LHS = N.getOperand(0); 411 RHS = N.getOperand(1); 412 CC = N.getOperand(2); 413 return true; 414 } 415 if (N.getOpcode() == ISD::SELECT_CC && 416 N.getOperand(2).getOpcode() == ISD::Constant && 417 N.getOperand(3).getOpcode() == ISD::Constant && 418 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 419 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 420 LHS = N.getOperand(0); 421 RHS = N.getOperand(1); 422 CC = N.getOperand(4); 423 return true; 424 } 425 return false; 426} 427 428// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 429// one use. If this is true, it allows the users to invert the operation for 430// free when it is profitable to do so. 431static bool isOneUseSetCC(SDOperand N) { 432 SDOperand N0, N1, N2; 433 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 434 return true; 435 return false; 436} 437 438// FIXME: This should probably go in the ISD class rather than being duplicated 439// in several files. 440static bool isCommutativeBinOp(unsigned Opcode) { 441 switch (Opcode) { 442 case ISD::ADD: 443 case ISD::MUL: 444 case ISD::AND: 445 case ISD::OR: 446 case ISD::XOR: return true; 447 default: return false; // FIXME: Need commutative info for user ops! 448 } 449} 450 451SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 452 MVT::ValueType VT = N0.getValueType(); 453 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 454 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 455 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 456 if (isa<ConstantSDNode>(N1)) { 457 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 458 WorkList.push_back(OpNode.Val); 459 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 460 } else if (N0.hasOneUse()) { 461 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 462 WorkList.push_back(OpNode.Val); 463 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 464 } 465 } 466 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 467 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 468 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 469 if (isa<ConstantSDNode>(N0)) { 470 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 471 WorkList.push_back(OpNode.Val); 472 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 473 } else if (N1.hasOneUse()) { 474 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 475 WorkList.push_back(OpNode.Val); 476 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 477 } 478 } 479 return SDOperand(); 480} 481 482void DAGCombiner::Run(bool RunningAfterLegalize) { 483 // set the instance variable, so that the various visit routines may use it. 484 AfterLegalize = RunningAfterLegalize; 485 486 // Add all the dag nodes to the worklist. 487 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 488 E = DAG.allnodes_end(); I != E; ++I) 489 WorkList.push_back(I); 490 491 // Create a dummy node (which is not added to allnodes), that adds a reference 492 // to the root node, preventing it from being deleted, and tracking any 493 // changes of the root. 494 HandleSDNode Dummy(DAG.getRoot()); 495 496 // while the worklist isn't empty, inspect the node on the end of it and 497 // try and combine it. 498 while (!WorkList.empty()) { 499 SDNode *N = WorkList.back(); 500 WorkList.pop_back(); 501 502 // If N has no uses, it is dead. Make sure to revisit all N's operands once 503 // N is deleted from the DAG, since they too may now be dead or may have a 504 // reduced number of uses, allowing other xforms. 505 if (N->use_empty() && N != &Dummy) { 506 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 507 WorkList.push_back(N->getOperand(i).Val); 508 509 removeFromWorkList(N); 510 DAG.DeleteNode(N); 511 continue; 512 } 513 514 SDOperand RV = visit(N); 515 if (RV.Val) { 516 ++NodesCombined; 517 // If we get back the same node we passed in, rather than a new node or 518 // zero, we know that the node must have defined multiple values and 519 // CombineTo was used. Since CombineTo takes care of the worklist 520 // mechanics for us, we have no work to do in this case. 521 if (RV.Val != N) { 522 DEBUG(std::cerr << "\nReplacing "; N->dump(); 523 std::cerr << "\nWith: "; RV.Val->dump(); 524 std::cerr << '\n'); 525 std::vector<SDNode*> NowDead; 526 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 527 528 // Push the new node and any users onto the worklist 529 WorkList.push_back(RV.Val); 530 AddUsersToWorkList(RV.Val); 531 532 // Nodes can end up on the worklist more than once. Make sure we do 533 // not process a node that has been replaced. 534 removeFromWorkList(N); 535 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 536 removeFromWorkList(NowDead[i]); 537 538 // Finally, since the node is now dead, remove it from the graph. 539 DAG.DeleteNode(N); 540 } 541 } 542 } 543 544 // If the root changed (e.g. it was a dead load, update the root). 545 DAG.setRoot(Dummy.getValue()); 546} 547 548SDOperand DAGCombiner::visit(SDNode *N) { 549 switch(N->getOpcode()) { 550 default: break; 551 case ISD::TokenFactor: return visitTokenFactor(N); 552 case ISD::ADD: return visitADD(N); 553 case ISD::SUB: return visitSUB(N); 554 case ISD::MUL: return visitMUL(N); 555 case ISD::SDIV: return visitSDIV(N); 556 case ISD::UDIV: return visitUDIV(N); 557 case ISD::SREM: return visitSREM(N); 558 case ISD::UREM: return visitUREM(N); 559 case ISD::MULHU: return visitMULHU(N); 560 case ISD::MULHS: return visitMULHS(N); 561 case ISD::AND: return visitAND(N); 562 case ISD::OR: return visitOR(N); 563 case ISD::XOR: return visitXOR(N); 564 case ISD::SHL: return visitSHL(N); 565 case ISD::SRA: return visitSRA(N); 566 case ISD::SRL: return visitSRL(N); 567 case ISD::CTLZ: return visitCTLZ(N); 568 case ISD::CTTZ: return visitCTTZ(N); 569 case ISD::CTPOP: return visitCTPOP(N); 570 case ISD::SELECT: return visitSELECT(N); 571 case ISD::SELECT_CC: return visitSELECT_CC(N); 572 case ISD::SETCC: return visitSETCC(N); 573 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 574 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 575 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 576 case ISD::TRUNCATE: return visitTRUNCATE(N); 577 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 578 case ISD::FADD: return visitFADD(N); 579 case ISD::FSUB: return visitFSUB(N); 580 case ISD::FMUL: return visitFMUL(N); 581 case ISD::FDIV: return visitFDIV(N); 582 case ISD::FREM: return visitFREM(N); 583 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 584 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 585 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 586 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 587 case ISD::FP_ROUND: return visitFP_ROUND(N); 588 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 589 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 590 case ISD::FNEG: return visitFNEG(N); 591 case ISD::FABS: return visitFABS(N); 592 case ISD::BRCOND: return visitBRCOND(N); 593 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 594 case ISD::BR_CC: return visitBR_CC(N); 595 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 596 case ISD::LOAD: return visitLOAD(N); 597 case ISD::STORE: return visitSTORE(N); 598 } 599 return SDOperand(); 600} 601 602SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 603 std::vector<SDOperand> Ops; 604 bool Changed = false; 605 606 // If the token factor has two operands and one is the entry token, replace 607 // the token factor with the other operand. 608 if (N->getNumOperands() == 2) { 609 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 610 return N->getOperand(1); 611 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 612 return N->getOperand(0); 613 } 614 615 // fold (tokenfactor (tokenfactor)) -> tokenfactor 616 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 617 SDOperand Op = N->getOperand(i); 618 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 619 Changed = true; 620 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 621 Ops.push_back(Op.getOperand(j)); 622 } else { 623 Ops.push_back(Op); 624 } 625 } 626 if (Changed) 627 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 628 return SDOperand(); 629} 630 631SDOperand DAGCombiner::visitADD(SDNode *N) { 632 SDOperand N0 = N->getOperand(0); 633 SDOperand N1 = N->getOperand(1); 634 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 635 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 636 MVT::ValueType VT = N0.getValueType(); 637 638 // fold (add c1, c2) -> c1+c2 639 if (N0C && N1C) 640 return DAG.getNode(ISD::ADD, VT, N0, N1); 641 // canonicalize constant to RHS 642 if (N0C && !N1C) 643 return DAG.getNode(ISD::ADD, VT, N1, N0); 644 // fold (add x, 0) -> x 645 if (N1C && N1C->isNullValue()) 646 return N0; 647 // fold ((c1-A)+c2) -> (c1+c2)-A 648 if (N1C && N0.getOpcode() == ISD::SUB) 649 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 650 return DAG.getNode(ISD::SUB, VT, 651 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 652 N0.getOperand(1)); 653 // reassociate add 654 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 655 if (RADD.Val != 0) 656 return RADD; 657 // fold ((0-A) + B) -> B-A 658 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 659 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 660 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 661 // fold (A + (0-B)) -> A-B 662 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 663 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 664 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 665 // fold (A+(B-A)) -> B 666 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 667 return N1.getOperand(0); 668 // 669 if (SimplifyDemandedBits(SDOperand(N, 0))) 670 return SDOperand(); 671 return SDOperand(); 672} 673 674SDOperand DAGCombiner::visitSUB(SDNode *N) { 675 SDOperand N0 = N->getOperand(0); 676 SDOperand N1 = N->getOperand(1); 677 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 678 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 679 MVT::ValueType VT = N0.getValueType(); 680 681 // fold (sub x, x) -> 0 682 if (N0 == N1) 683 return DAG.getConstant(0, N->getValueType(0)); 684 // fold (sub c1, c2) -> c1-c2 685 if (N0C && N1C) 686 return DAG.getNode(ISD::SUB, VT, N0, N1); 687 // fold (sub x, c) -> (add x, -c) 688 if (N1C) 689 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 690 // fold (A+B)-A -> B 691 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 692 return N0.getOperand(1); 693 // fold (A+B)-B -> A 694 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 695 return N0.getOperand(0); 696 return SDOperand(); 697} 698 699SDOperand DAGCombiner::visitMUL(SDNode *N) { 700 SDOperand N0 = N->getOperand(0); 701 SDOperand N1 = N->getOperand(1); 702 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 703 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 704 MVT::ValueType VT = N0.getValueType(); 705 706 // fold (mul c1, c2) -> c1*c2 707 if (N0C && N1C) 708 return DAG.getNode(ISD::MUL, VT, N0, N1); 709 // canonicalize constant to RHS 710 if (N0C && !N1C) 711 return DAG.getNode(ISD::MUL, VT, N1, N0); 712 // fold (mul x, 0) -> 0 713 if (N1C && N1C->isNullValue()) 714 return N1; 715 // fold (mul x, -1) -> 0-x 716 if (N1C && N1C->isAllOnesValue()) 717 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 718 // fold (mul x, (1 << c)) -> x << c 719 if (N1C && isPowerOf2_64(N1C->getValue())) 720 return DAG.getNode(ISD::SHL, VT, N0, 721 DAG.getConstant(Log2_64(N1C->getValue()), 722 TLI.getShiftAmountTy())); 723 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 724 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 725 // FIXME: If the input is something that is easily negated (e.g. a 726 // single-use add), we should put the negate there. 727 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 728 DAG.getNode(ISD::SHL, VT, N0, 729 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 730 TLI.getShiftAmountTy()))); 731 } 732 // reassociate mul 733 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 734 if (RMUL.Val != 0) 735 return RMUL; 736 return SDOperand(); 737} 738 739SDOperand DAGCombiner::visitSDIV(SDNode *N) { 740 SDOperand N0 = N->getOperand(0); 741 SDOperand N1 = N->getOperand(1); 742 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 743 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 744 MVT::ValueType VT = N->getValueType(0); 745 746 // fold (sdiv c1, c2) -> c1/c2 747 if (N0C && N1C && !N1C->isNullValue()) 748 return DAG.getNode(ISD::SDIV, VT, N0, N1); 749 // fold (sdiv X, 1) -> X 750 if (N1C && N1C->getSignExtended() == 1LL) 751 return N0; 752 // fold (sdiv X, -1) -> 0-X 753 if (N1C && N1C->isAllOnesValue()) 754 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 755 // If we know the sign bits of both operands are zero, strength reduce to a 756 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 757 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 758 if (TLI.MaskedValueIsZero(N1, SignBit) && 759 TLI.MaskedValueIsZero(N0, SignBit)) 760 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 761 // fold (sdiv X, pow2) -> simple ops after legalize 762 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 763 (isPowerOf2_64(N1C->getSignExtended()) || 764 isPowerOf2_64(-N1C->getSignExtended()))) { 765 // If dividing by powers of two is cheap, then don't perform the following 766 // fold. 767 if (TLI.isPow2DivCheap()) 768 return SDOperand(); 769 int64_t pow2 = N1C->getSignExtended(); 770 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 771 unsigned lg2 = Log2_64(abs2); 772 // Splat the sign bit into the register 773 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 774 DAG.getConstant(MVT::getSizeInBits(VT)-1, 775 TLI.getShiftAmountTy())); 776 WorkList.push_back(SGN.Val); 777 // Add (N0 < 0) ? abs2 - 1 : 0; 778 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 779 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 780 TLI.getShiftAmountTy())); 781 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 782 WorkList.push_back(SRL.Val); 783 WorkList.push_back(ADD.Val); // Divide by pow2 784 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 785 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 786 // If we're dividing by a positive value, we're done. Otherwise, we must 787 // negate the result. 788 if (pow2 > 0) 789 return SRA; 790 WorkList.push_back(SRA.Val); 791 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 792 } 793 // if integer divide is expensive and we satisfy the requirements, emit an 794 // alternate sequence. 795 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 796 !TLI.isIntDivCheap()) { 797 SDOperand Op = BuildSDIV(N); 798 if (Op.Val) return Op; 799 } 800 return SDOperand(); 801} 802 803SDOperand DAGCombiner::visitUDIV(SDNode *N) { 804 SDOperand N0 = N->getOperand(0); 805 SDOperand N1 = N->getOperand(1); 806 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 807 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 808 MVT::ValueType VT = N->getValueType(0); 809 810 // fold (udiv c1, c2) -> c1/c2 811 if (N0C && N1C && !N1C->isNullValue()) 812 return DAG.getNode(ISD::UDIV, VT, N0, N1); 813 // fold (udiv x, (1 << c)) -> x >>u c 814 if (N1C && isPowerOf2_64(N1C->getValue())) 815 return DAG.getNode(ISD::SRL, VT, N0, 816 DAG.getConstant(Log2_64(N1C->getValue()), 817 TLI.getShiftAmountTy())); 818 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 819 if (N1.getOpcode() == ISD::SHL) { 820 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 821 if (isPowerOf2_64(SHC->getValue())) { 822 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 823 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 824 DAG.getConstant(Log2_64(SHC->getValue()), 825 ADDVT)); 826 WorkList.push_back(Add.Val); 827 return DAG.getNode(ISD::SRL, VT, N0, Add); 828 } 829 } 830 } 831 // fold (udiv x, c) -> alternate 832 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 833 SDOperand Op = BuildUDIV(N); 834 if (Op.Val) return Op; 835 } 836 return SDOperand(); 837} 838 839SDOperand DAGCombiner::visitSREM(SDNode *N) { 840 SDOperand N0 = N->getOperand(0); 841 SDOperand N1 = N->getOperand(1); 842 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 843 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 844 MVT::ValueType VT = N->getValueType(0); 845 846 // fold (srem c1, c2) -> c1%c2 847 if (N0C && N1C && !N1C->isNullValue()) 848 return DAG.getNode(ISD::SREM, VT, N0, N1); 849 // If we know the sign bits of both operands are zero, strength reduce to a 850 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 851 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 852 if (TLI.MaskedValueIsZero(N1, SignBit) && 853 TLI.MaskedValueIsZero(N0, SignBit)) 854 return DAG.getNode(ISD::UREM, VT, N0, N1); 855 return SDOperand(); 856} 857 858SDOperand DAGCombiner::visitUREM(SDNode *N) { 859 SDOperand N0 = N->getOperand(0); 860 SDOperand N1 = N->getOperand(1); 861 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 862 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 863 MVT::ValueType VT = N->getValueType(0); 864 865 // fold (urem c1, c2) -> c1%c2 866 if (N0C && N1C && !N1C->isNullValue()) 867 return DAG.getNode(ISD::UREM, VT, N0, N1); 868 // fold (urem x, pow2) -> (and x, pow2-1) 869 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 870 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 871 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 872 if (N1.getOpcode() == ISD::SHL) { 873 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 874 if (isPowerOf2_64(SHC->getValue())) { 875 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 876 WorkList.push_back(Add.Val); 877 return DAG.getNode(ISD::AND, VT, N0, Add); 878 } 879 } 880 } 881 return SDOperand(); 882} 883 884SDOperand DAGCombiner::visitMULHS(SDNode *N) { 885 SDOperand N0 = N->getOperand(0); 886 SDOperand N1 = N->getOperand(1); 887 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 888 889 // fold (mulhs x, 0) -> 0 890 if (N1C && N1C->isNullValue()) 891 return N1; 892 // fold (mulhs x, 1) -> (sra x, size(x)-1) 893 if (N1C && N1C->getValue() == 1) 894 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 895 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 896 TLI.getShiftAmountTy())); 897 return SDOperand(); 898} 899 900SDOperand DAGCombiner::visitMULHU(SDNode *N) { 901 SDOperand N0 = N->getOperand(0); 902 SDOperand N1 = N->getOperand(1); 903 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 904 905 // fold (mulhu x, 0) -> 0 906 if (N1C && N1C->isNullValue()) 907 return N1; 908 // fold (mulhu x, 1) -> 0 909 if (N1C && N1C->getValue() == 1) 910 return DAG.getConstant(0, N0.getValueType()); 911 return SDOperand(); 912} 913 914SDOperand DAGCombiner::visitAND(SDNode *N) { 915 SDOperand N0 = N->getOperand(0); 916 SDOperand N1 = N->getOperand(1); 917 SDOperand LL, LR, RL, RR, CC0, CC1; 918 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 919 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 920 MVT::ValueType VT = N1.getValueType(); 921 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 922 923 // fold (and c1, c2) -> c1&c2 924 if (N0C && N1C) 925 return DAG.getNode(ISD::AND, VT, N0, N1); 926 // canonicalize constant to RHS 927 if (N0C && !N1C) 928 return DAG.getNode(ISD::AND, VT, N1, N0); 929 // fold (and x, -1) -> x 930 if (N1C && N1C->isAllOnesValue()) 931 return N0; 932 // if (and x, c) is known to be zero, return 0 933 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 934 return DAG.getConstant(0, VT); 935 // reassociate and 936 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 937 if (RAND.Val != 0) 938 return RAND; 939 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 940 if (N1C && N0.getOpcode() == ISD::OR) 941 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 942 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 943 return N1; 944 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 945 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 946 unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 947 if (TLI.MaskedValueIsZero(N0.getOperand(0), 948 ~N1C->getValue() & ((1ULL << InBits)-1))) { 949 // We actually want to replace all uses of the any_extend with the 950 // zero_extend, to avoid duplicating things. This will later cause this 951 // AND to be folded. 952 CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 953 N0.getOperand(0))); 954 return SDOperand(); 955 } 956 } 957 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 958 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 959 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 960 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 961 962 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 963 MVT::isInteger(LL.getValueType())) { 964 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 965 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 966 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 967 WorkList.push_back(ORNode.Val); 968 return DAG.getSetCC(VT, ORNode, LR, Op1); 969 } 970 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 971 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 972 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 973 WorkList.push_back(ANDNode.Val); 974 return DAG.getSetCC(VT, ANDNode, LR, Op1); 975 } 976 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 977 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 978 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 979 WorkList.push_back(ORNode.Val); 980 return DAG.getSetCC(VT, ORNode, LR, Op1); 981 } 982 } 983 // canonicalize equivalent to ll == rl 984 if (LL == RR && LR == RL) { 985 Op1 = ISD::getSetCCSwappedOperands(Op1); 986 std::swap(RL, RR); 987 } 988 if (LL == RL && LR == RR) { 989 bool isInteger = MVT::isInteger(LL.getValueType()); 990 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 991 if (Result != ISD::SETCC_INVALID) 992 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 993 } 994 } 995 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 996 if (N0.getOpcode() == ISD::ZERO_EXTEND && 997 N1.getOpcode() == ISD::ZERO_EXTEND && 998 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 999 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1000 N0.getOperand(0), N1.getOperand(0)); 1001 WorkList.push_back(ANDNode.Val); 1002 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 1003 } 1004 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y)) 1005 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1006 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1007 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1008 N0.getOperand(1) == N1.getOperand(1)) { 1009 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1010 N0.getOperand(0), N1.getOperand(0)); 1011 WorkList.push_back(ANDNode.Val); 1012 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 1013 } 1014 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1015 // fold (and (sra)) -> (and (srl)) when possible. 1016 if (SimplifyDemandedBits(SDOperand(N, 0))) 1017 return SDOperand(); 1018 // fold (zext_inreg (extload x)) -> (zextload x) 1019 if (N0.getOpcode() == ISD::EXTLOAD) { 1020 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1021 // If we zero all the possible extended bits, then we can turn this into 1022 // a zextload if we are running before legalize or the operation is legal. 1023 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1024 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1025 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1026 N0.getOperand(1), N0.getOperand(2), 1027 EVT); 1028 WorkList.push_back(N); 1029 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1030 return SDOperand(); 1031 } 1032 } 1033 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1034 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1035 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1036 // If we zero all the possible extended bits, then we can turn this into 1037 // a zextload if we are running before legalize or the operation is legal. 1038 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1039 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1040 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1041 N0.getOperand(1), N0.getOperand(2), 1042 EVT); 1043 WorkList.push_back(N); 1044 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1045 return SDOperand(); 1046 } 1047 } 1048 return SDOperand(); 1049} 1050 1051SDOperand DAGCombiner::visitOR(SDNode *N) { 1052 SDOperand N0 = N->getOperand(0); 1053 SDOperand N1 = N->getOperand(1); 1054 SDOperand LL, LR, RL, RR, CC0, CC1; 1055 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1056 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1057 MVT::ValueType VT = N1.getValueType(); 1058 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1059 1060 // fold (or c1, c2) -> c1|c2 1061 if (N0C && N1C) 1062 return DAG.getNode(ISD::OR, VT, N0, N1); 1063 // canonicalize constant to RHS 1064 if (N0C && !N1C) 1065 return DAG.getNode(ISD::OR, VT, N1, N0); 1066 // fold (or x, 0) -> x 1067 if (N1C && N1C->isNullValue()) 1068 return N0; 1069 // fold (or x, -1) -> -1 1070 if (N1C && N1C->isAllOnesValue()) 1071 return N1; 1072 // fold (or x, c) -> c iff (x & ~c) == 0 1073 if (N1C && 1074 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1075 return N1; 1076 // reassociate or 1077 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1078 if (ROR.Val != 0) 1079 return ROR; 1080 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1081 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1082 isa<ConstantSDNode>(N0.getOperand(1))) { 1083 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1084 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1085 N1), 1086 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1087 } 1088 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1089 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1090 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1091 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1092 1093 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1094 MVT::isInteger(LL.getValueType())) { 1095 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1096 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1097 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1098 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1099 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1100 WorkList.push_back(ORNode.Val); 1101 return DAG.getSetCC(VT, ORNode, LR, Op1); 1102 } 1103 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1104 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1105 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1106 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1107 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1108 WorkList.push_back(ANDNode.Val); 1109 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1110 } 1111 } 1112 // canonicalize equivalent to ll == rl 1113 if (LL == RR && LR == RL) { 1114 Op1 = ISD::getSetCCSwappedOperands(Op1); 1115 std::swap(RL, RR); 1116 } 1117 if (LL == RL && LR == RR) { 1118 bool isInteger = MVT::isInteger(LL.getValueType()); 1119 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1120 if (Result != ISD::SETCC_INVALID) 1121 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1122 } 1123 } 1124 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 1125 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1126 N1.getOpcode() == ISD::ZERO_EXTEND && 1127 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1128 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1129 N0.getOperand(0), N1.getOperand(0)); 1130 WorkList.push_back(ORNode.Val); 1131 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 1132 } 1133 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y)) 1134 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1135 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1136 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1137 N0.getOperand(1) == N1.getOperand(1)) { 1138 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1139 N0.getOperand(0), N1.getOperand(0)); 1140 WorkList.push_back(ORNode.Val); 1141 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1142 } 1143 // canonicalize shl to left side in a shl/srl pair, to match rotate 1144 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 1145 std::swap(N0, N1); 1146 // check for rotl, rotr 1147 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 1148 N0.getOperand(0) == N1.getOperand(0) && 1149 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 1150 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1151 if (N0.getOperand(1).getOpcode() == ISD::Constant && 1152 N1.getOperand(1).getOpcode() == ISD::Constant) { 1153 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1154 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1155 if ((c1val + c2val) == OpSizeInBits) 1156 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1157 } 1158 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1159 if (N1.getOperand(1).getOpcode() == ISD::SUB && 1160 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 1161 if (ConstantSDNode *SUBC = 1162 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 1163 if (SUBC->getValue() == OpSizeInBits) 1164 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1165 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1166 if (N0.getOperand(1).getOpcode() == ISD::SUB && 1167 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 1168 if (ConstantSDNode *SUBC = 1169 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 1170 if (SUBC->getValue() == OpSizeInBits) { 1171 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 1172 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 1173 N1.getOperand(1)); 1174 else 1175 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 1176 N0.getOperand(1)); 1177 } 1178 } 1179 return SDOperand(); 1180} 1181 1182SDOperand DAGCombiner::visitXOR(SDNode *N) { 1183 SDOperand N0 = N->getOperand(0); 1184 SDOperand N1 = N->getOperand(1); 1185 SDOperand LHS, RHS, CC; 1186 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1187 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1188 MVT::ValueType VT = N0.getValueType(); 1189 1190 // fold (xor c1, c2) -> c1^c2 1191 if (N0C && N1C) 1192 return DAG.getNode(ISD::XOR, VT, N0, N1); 1193 // canonicalize constant to RHS 1194 if (N0C && !N1C) 1195 return DAG.getNode(ISD::XOR, VT, N1, N0); 1196 // fold (xor x, 0) -> x 1197 if (N1C && N1C->isNullValue()) 1198 return N0; 1199 // reassociate xor 1200 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1201 if (RXOR.Val != 0) 1202 return RXOR; 1203 // fold !(x cc y) -> (x !cc y) 1204 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1205 bool isInt = MVT::isInteger(LHS.getValueType()); 1206 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1207 isInt); 1208 if (N0.getOpcode() == ISD::SETCC) 1209 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1210 if (N0.getOpcode() == ISD::SELECT_CC) 1211 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1212 assert(0 && "Unhandled SetCC Equivalent!"); 1213 abort(); 1214 } 1215 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1216 if (N1C && N1C->getValue() == 1 && 1217 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1218 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1219 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1220 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1221 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1222 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1223 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1224 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1225 } 1226 } 1227 // fold !(x or y) -> (!x and !y) iff x or y are constants 1228 if (N1C && N1C->isAllOnesValue() && 1229 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1230 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1231 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1232 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1233 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1234 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1235 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1236 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1237 } 1238 } 1239 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1240 if (N1C && N0.getOpcode() == ISD::XOR) { 1241 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1242 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1243 if (N00C) 1244 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1245 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1246 if (N01C) 1247 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1248 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1249 } 1250 // fold (xor x, x) -> 0 1251 if (N0 == N1) 1252 return DAG.getConstant(0, VT); 1253 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1254 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1255 N1.getOpcode() == ISD::ZERO_EXTEND && 1256 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1257 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1258 N0.getOperand(0), N1.getOperand(0)); 1259 WorkList.push_back(XORNode.Val); 1260 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1261 } 1262 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y)) 1263 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1264 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1265 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1266 N0.getOperand(1) == N1.getOperand(1)) { 1267 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1268 N0.getOperand(0), N1.getOperand(0)); 1269 WorkList.push_back(XORNode.Val); 1270 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1)); 1271 } 1272 return SDOperand(); 1273} 1274 1275SDOperand DAGCombiner::visitSHL(SDNode *N) { 1276 SDOperand N0 = N->getOperand(0); 1277 SDOperand N1 = N->getOperand(1); 1278 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1279 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1280 MVT::ValueType VT = N0.getValueType(); 1281 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1282 1283 // fold (shl c1, c2) -> c1<<c2 1284 if (N0C && N1C) 1285 return DAG.getNode(ISD::SHL, VT, N0, N1); 1286 // fold (shl 0, x) -> 0 1287 if (N0C && N0C->isNullValue()) 1288 return N0; 1289 // fold (shl x, c >= size(x)) -> undef 1290 if (N1C && N1C->getValue() >= OpSizeInBits) 1291 return DAG.getNode(ISD::UNDEF, VT); 1292 // fold (shl x, 0) -> x 1293 if (N1C && N1C->isNullValue()) 1294 return N0; 1295 // if (shl x, c) is known to be zero, return 0 1296 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1297 return DAG.getConstant(0, VT); 1298 if (SimplifyDemandedBits(SDOperand(N, 0))) 1299 return SDOperand(); 1300 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1301 if (N1C && N0.getOpcode() == ISD::SHL && 1302 N0.getOperand(1).getOpcode() == ISD::Constant) { 1303 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1304 uint64_t c2 = N1C->getValue(); 1305 if (c1 + c2 > OpSizeInBits) 1306 return DAG.getConstant(0, VT); 1307 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1308 DAG.getConstant(c1 + c2, N1.getValueType())); 1309 } 1310 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1311 // (srl (and x, -1 << c1), c1-c2) 1312 if (N1C && N0.getOpcode() == ISD::SRL && 1313 N0.getOperand(1).getOpcode() == ISD::Constant) { 1314 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1315 uint64_t c2 = N1C->getValue(); 1316 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1317 DAG.getConstant(~0ULL << c1, VT)); 1318 if (c2 > c1) 1319 return DAG.getNode(ISD::SHL, VT, Mask, 1320 DAG.getConstant(c2-c1, N1.getValueType())); 1321 else 1322 return DAG.getNode(ISD::SRL, VT, Mask, 1323 DAG.getConstant(c1-c2, N1.getValueType())); 1324 } 1325 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1326 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1327 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1328 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1329 return SDOperand(); 1330} 1331 1332SDOperand DAGCombiner::visitSRA(SDNode *N) { 1333 SDOperand N0 = N->getOperand(0); 1334 SDOperand N1 = N->getOperand(1); 1335 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1336 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1337 MVT::ValueType VT = N0.getValueType(); 1338 1339 // fold (sra c1, c2) -> c1>>c2 1340 if (N0C && N1C) 1341 return DAG.getNode(ISD::SRA, VT, N0, N1); 1342 // fold (sra 0, x) -> 0 1343 if (N0C && N0C->isNullValue()) 1344 return N0; 1345 // fold (sra -1, x) -> -1 1346 if (N0C && N0C->isAllOnesValue()) 1347 return N0; 1348 // fold (sra x, c >= size(x)) -> undef 1349 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1350 return DAG.getNode(ISD::UNDEF, VT); 1351 // fold (sra x, 0) -> x 1352 if (N1C && N1C->isNullValue()) 1353 return N0; 1354 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1355 // sext_inreg. 1356 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1357 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1358 MVT::ValueType EVT; 1359 switch (LowBits) { 1360 default: EVT = MVT::Other; break; 1361 case 1: EVT = MVT::i1; break; 1362 case 8: EVT = MVT::i8; break; 1363 case 16: EVT = MVT::i16; break; 1364 case 32: EVT = MVT::i32; break; 1365 } 1366 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1367 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1368 DAG.getValueType(EVT)); 1369 } 1370 // If the sign bit is known to be zero, switch this to a SRL. 1371 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1372 return DAG.getNode(ISD::SRL, VT, N0, N1); 1373 return SDOperand(); 1374} 1375 1376SDOperand DAGCombiner::visitSRL(SDNode *N) { 1377 SDOperand N0 = N->getOperand(0); 1378 SDOperand N1 = N->getOperand(1); 1379 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1380 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1381 MVT::ValueType VT = N0.getValueType(); 1382 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1383 1384 // fold (srl c1, c2) -> c1 >>u c2 1385 if (N0C && N1C) 1386 return DAG.getNode(ISD::SRL, VT, N0, N1); 1387 // fold (srl 0, x) -> 0 1388 if (N0C && N0C->isNullValue()) 1389 return N0; 1390 // fold (srl x, c >= size(x)) -> undef 1391 if (N1C && N1C->getValue() >= OpSizeInBits) 1392 return DAG.getNode(ISD::UNDEF, VT); 1393 // fold (srl x, 0) -> x 1394 if (N1C && N1C->isNullValue()) 1395 return N0; 1396 // if (srl x, c) is known to be zero, return 0 1397 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1398 return DAG.getConstant(0, VT); 1399 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1400 if (N1C && N0.getOpcode() == ISD::SRL && 1401 N0.getOperand(1).getOpcode() == ISD::Constant) { 1402 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1403 uint64_t c2 = N1C->getValue(); 1404 if (c1 + c2 > OpSizeInBits) 1405 return DAG.getConstant(0, VT); 1406 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1407 DAG.getConstant(c1 + c2, N1.getValueType())); 1408 } 1409 return SDOperand(); 1410} 1411 1412SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1413 SDOperand N0 = N->getOperand(0); 1414 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1415 MVT::ValueType VT = N->getValueType(0); 1416 1417 // fold (ctlz c1) -> c2 1418 if (N0C) 1419 return DAG.getNode(ISD::CTLZ, VT, N0); 1420 return SDOperand(); 1421} 1422 1423SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1424 SDOperand N0 = N->getOperand(0); 1425 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1426 MVT::ValueType VT = N->getValueType(0); 1427 1428 // fold (cttz c1) -> c2 1429 if (N0C) 1430 return DAG.getNode(ISD::CTTZ, VT, N0); 1431 return SDOperand(); 1432} 1433 1434SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1435 SDOperand N0 = N->getOperand(0); 1436 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1437 MVT::ValueType VT = N->getValueType(0); 1438 1439 // fold (ctpop c1) -> c2 1440 if (N0C) 1441 return DAG.getNode(ISD::CTPOP, VT, N0); 1442 return SDOperand(); 1443} 1444 1445SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1446 SDOperand N0 = N->getOperand(0); 1447 SDOperand N1 = N->getOperand(1); 1448 SDOperand N2 = N->getOperand(2); 1449 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1450 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1451 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1452 MVT::ValueType VT = N->getValueType(0); 1453 1454 // fold select C, X, X -> X 1455 if (N1 == N2) 1456 return N1; 1457 // fold select true, X, Y -> X 1458 if (N0C && !N0C->isNullValue()) 1459 return N1; 1460 // fold select false, X, Y -> Y 1461 if (N0C && N0C->isNullValue()) 1462 return N2; 1463 // fold select C, 1, X -> C | X 1464 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1465 return DAG.getNode(ISD::OR, VT, N0, N2); 1466 // fold select C, 0, X -> ~C & X 1467 // FIXME: this should check for C type == X type, not i1? 1468 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1469 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1470 WorkList.push_back(XORNode.Val); 1471 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1472 } 1473 // fold select C, X, 1 -> ~C | X 1474 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1475 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1476 WorkList.push_back(XORNode.Val); 1477 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1478 } 1479 // fold select C, X, 0 -> C & X 1480 // FIXME: this should check for C type == X type, not i1? 1481 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1482 return DAG.getNode(ISD::AND, VT, N0, N1); 1483 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1484 if (MVT::i1 == VT && N0 == N1) 1485 return DAG.getNode(ISD::OR, VT, N0, N2); 1486 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1487 if (MVT::i1 == VT && N0 == N2) 1488 return DAG.getNode(ISD::AND, VT, N0, N1); 1489 // If we can fold this based on the true/false value, do so. 1490 if (SimplifySelectOps(N, N1, N2)) 1491 return SDOperand(); 1492 // fold selects based on a setcc into other things, such as min/max/abs 1493 if (N0.getOpcode() == ISD::SETCC) 1494 // FIXME: 1495 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1496 // having to say they don't support SELECT_CC on every type the DAG knows 1497 // about, since there is no way to mark an opcode illegal at all value types 1498 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1499 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1500 N1, N2, N0.getOperand(2)); 1501 else 1502 return SimplifySelect(N0, N1, N2); 1503 return SDOperand(); 1504} 1505 1506SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1507 SDOperand N0 = N->getOperand(0); 1508 SDOperand N1 = N->getOperand(1); 1509 SDOperand N2 = N->getOperand(2); 1510 SDOperand N3 = N->getOperand(3); 1511 SDOperand N4 = N->getOperand(4); 1512 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1513 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1514 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1515 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1516 1517 // Determine if the condition we're dealing with is constant 1518 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1519 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1520 1521 // fold select_cc lhs, rhs, x, x, cc -> x 1522 if (N2 == N3) 1523 return N2; 1524 1525 // If we can fold this based on the true/false value, do so. 1526 if (SimplifySelectOps(N, N2, N3)) 1527 return SDOperand(); 1528 1529 // fold select_cc into other things, such as min/max/abs 1530 return SimplifySelectCC(N0, N1, N2, N3, CC); 1531} 1532 1533SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1534 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1535 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1536} 1537 1538SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1539 SDOperand N0 = N->getOperand(0); 1540 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1541 MVT::ValueType VT = N->getValueType(0); 1542 1543 // fold (sext c1) -> c1 1544 if (N0C) 1545 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1546 // fold (sext (sext x)) -> (sext x) 1547 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1548 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1549 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1550 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1551 (!AfterLegalize || 1552 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1553 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1554 DAG.getValueType(N0.getValueType())); 1555 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1556 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1557 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1558 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1559 N0.getOperand(1), N0.getOperand(2), 1560 N0.getValueType()); 1561 CombineTo(N, ExtLoad); 1562 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1563 ExtLoad.getValue(1)); 1564 return SDOperand(); 1565 } 1566 1567 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1568 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1569 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1570 N0.hasOneUse()) { 1571 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0), 1572 N0.getOperand(1), N0.getOperand(2), 1573 N0.getOperand(3)); 1574 CombineTo(N, ExtLoad); 1575 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1576 ExtLoad.getValue(1)); 1577 return SDOperand(); 1578 } 1579 1580 return SDOperand(); 1581} 1582 1583SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1584 SDOperand N0 = N->getOperand(0); 1585 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1586 MVT::ValueType VT = N->getValueType(0); 1587 1588 // fold (zext c1) -> c1 1589 if (N0C) 1590 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1591 // fold (zext (zext x)) -> (zext x) 1592 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1593 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1594 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1595 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1596 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1597 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1598 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1599 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1600 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1601 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1602 N0.getOperand(1), N0.getOperand(2), 1603 N0.getValueType()); 1604 CombineTo(N, ExtLoad); 1605 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1606 ExtLoad.getValue(1)); 1607 return SDOperand(); 1608 } 1609 1610 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1611 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1612 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1613 N0.hasOneUse()) { 1614 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1615 N0.getOperand(1), N0.getOperand(2), 1616 N0.getOperand(3)); 1617 CombineTo(N, ExtLoad); 1618 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1619 ExtLoad.getValue(1)); 1620 return SDOperand(); 1621 } 1622 return SDOperand(); 1623} 1624 1625SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1626 SDOperand N0 = N->getOperand(0); 1627 SDOperand N1 = N->getOperand(1); 1628 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1629 MVT::ValueType VT = N->getValueType(0); 1630 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1631 unsigned EVTBits = MVT::getSizeInBits(EVT); 1632 1633 // fold (sext_in_reg c1) -> c1 1634 if (N0C) { 1635 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1636 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1637 } 1638 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1639 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1640 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1641 return N0; 1642 } 1643 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1644 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1645 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1646 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1647 } 1648 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1649 if (N0.getOpcode() == ISD::AssertSext && 1650 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1651 return N0; 1652 } 1653 // fold (sext_in_reg (sextload x)) -> (sextload x) 1654 if (N0.getOpcode() == ISD::SEXTLOAD && 1655 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1656 return N0; 1657 } 1658 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1659 if (N0.getOpcode() == ISD::SETCC && 1660 TLI.getSetCCResultContents() == 1661 TargetLowering::ZeroOrNegativeOneSetCCResult) 1662 return N0; 1663 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1664 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1665 return DAG.getZeroExtendInReg(N0, EVT); 1666 // fold (sext_in_reg (srl x)) -> sra x 1667 if (N0.getOpcode() == ISD::SRL && 1668 N0.getOperand(1).getOpcode() == ISD::Constant && 1669 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1670 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1671 N0.getOperand(1)); 1672 } 1673 // fold (sext_inreg (extload x)) -> (sextload x) 1674 if (N0.getOpcode() == ISD::EXTLOAD && 1675 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1676 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1677 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1678 N0.getOperand(1), N0.getOperand(2), 1679 EVT); 1680 CombineTo(N, ExtLoad); 1681 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1682 return SDOperand(); 1683 } 1684 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1685 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1686 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1687 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1688 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1689 N0.getOperand(1), N0.getOperand(2), 1690 EVT); 1691 CombineTo(N, ExtLoad); 1692 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1693 return SDOperand(); 1694 } 1695 return SDOperand(); 1696} 1697 1698SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1699 SDOperand N0 = N->getOperand(0); 1700 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1701 MVT::ValueType VT = N->getValueType(0); 1702 1703 // noop truncate 1704 if (N0.getValueType() == N->getValueType(0)) 1705 return N0; 1706 // fold (truncate c1) -> c1 1707 if (N0C) 1708 return DAG.getNode(ISD::TRUNCATE, VT, N0); 1709 // fold (truncate (truncate x)) -> (truncate x) 1710 if (N0.getOpcode() == ISD::TRUNCATE) 1711 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1712 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1713 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1714 if (N0.getValueType() < VT) 1715 // if the source is smaller than the dest, we still need an extend 1716 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1717 else if (N0.getValueType() > VT) 1718 // if the source is larger than the dest, than we just need the truncate 1719 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1720 else 1721 // if the source and dest are the same type, we can drop both the extend 1722 // and the truncate 1723 return N0.getOperand(0); 1724 } 1725 // fold (truncate (load x)) -> (smaller load x) 1726 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1727 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1728 "Cannot truncate to larger type!"); 1729 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1730 // For big endian targets, we need to add an offset to the pointer to load 1731 // the correct bytes. For little endian systems, we merely need to read 1732 // fewer bytes from the same pointer. 1733 uint64_t PtrOff = 1734 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1735 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1736 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1737 DAG.getConstant(PtrOff, PtrType)); 1738 WorkList.push_back(NewPtr.Val); 1739 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1740 WorkList.push_back(N); 1741 CombineTo(N0.Val, Load, Load.getValue(1)); 1742 return SDOperand(); 1743 } 1744 return SDOperand(); 1745} 1746 1747SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 1748 SDOperand N0 = N->getOperand(0); 1749 MVT::ValueType VT = N->getValueType(0); 1750 1751 // If the input is a constant, let getNode() fold it. 1752 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 1753 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 1754 if (Res.Val != N) return Res; 1755 } 1756 1757 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 1758 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 1759 1760 // fold (conv (load x)) -> (load (conv*)x) 1761 // FIXME: These xforms need to know that the resultant load doesn't need a 1762 // higher alignment than the original! 1763 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1764 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 1765 N0.getOperand(2)); 1766 WorkList.push_back(N); 1767 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 1768 Load.getValue(1)); 1769 return Load; 1770 } 1771 1772 return SDOperand(); 1773} 1774 1775SDOperand DAGCombiner::visitFADD(SDNode *N) { 1776 SDOperand N0 = N->getOperand(0); 1777 SDOperand N1 = N->getOperand(1); 1778 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1779 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1780 MVT::ValueType VT = N->getValueType(0); 1781 1782 // fold (fadd c1, c2) -> c1+c2 1783 if (N0CFP && N1CFP) 1784 return DAG.getNode(ISD::FADD, VT, N0, N1); 1785 // canonicalize constant to RHS 1786 if (N0CFP && !N1CFP) 1787 return DAG.getNode(ISD::FADD, VT, N1, N0); 1788 // fold (A + (-B)) -> A-B 1789 if (N1.getOpcode() == ISD::FNEG) 1790 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1791 // fold ((-A) + B) -> B-A 1792 if (N0.getOpcode() == ISD::FNEG) 1793 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1794 return SDOperand(); 1795} 1796 1797SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1798 SDOperand N0 = N->getOperand(0); 1799 SDOperand N1 = N->getOperand(1); 1800 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1801 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1802 MVT::ValueType VT = N->getValueType(0); 1803 1804 // fold (fsub c1, c2) -> c1-c2 1805 if (N0CFP && N1CFP) 1806 return DAG.getNode(ISD::FSUB, VT, N0, N1); 1807 // fold (A-(-B)) -> A+B 1808 if (N1.getOpcode() == ISD::FNEG) 1809 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 1810 return SDOperand(); 1811} 1812 1813SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1814 SDOperand N0 = N->getOperand(0); 1815 SDOperand N1 = N->getOperand(1); 1816 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1817 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1818 MVT::ValueType VT = N->getValueType(0); 1819 1820 // fold (fmul c1, c2) -> c1*c2 1821 if (N0CFP && N1CFP) 1822 return DAG.getNode(ISD::FMUL, VT, N0, N1); 1823 // canonicalize constant to RHS 1824 if (N0CFP && !N1CFP) 1825 return DAG.getNode(ISD::FMUL, VT, N1, N0); 1826 // fold (fmul X, 2.0) -> (fadd X, X) 1827 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 1828 return DAG.getNode(ISD::FADD, VT, N0, N0); 1829 return SDOperand(); 1830} 1831 1832SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1833 SDOperand N0 = N->getOperand(0); 1834 SDOperand N1 = N->getOperand(1); 1835 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1836 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1837 MVT::ValueType VT = N->getValueType(0); 1838 1839 // fold (fdiv c1, c2) -> c1/c2 1840 if (N0CFP && N1CFP) 1841 return DAG.getNode(ISD::FDIV, VT, N0, N1); 1842 return SDOperand(); 1843} 1844 1845SDOperand DAGCombiner::visitFREM(SDNode *N) { 1846 SDOperand N0 = N->getOperand(0); 1847 SDOperand N1 = N->getOperand(1); 1848 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1849 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1850 MVT::ValueType VT = N->getValueType(0); 1851 1852 // fold (frem c1, c2) -> fmod(c1,c2) 1853 if (N0CFP && N1CFP) 1854 return DAG.getNode(ISD::FREM, VT, N0, N1); 1855 return SDOperand(); 1856} 1857 1858 1859SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1860 SDOperand N0 = N->getOperand(0); 1861 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1862 MVT::ValueType VT = N->getValueType(0); 1863 1864 // fold (sint_to_fp c1) -> c1fp 1865 if (N0C) 1866 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 1867 return SDOperand(); 1868} 1869 1870SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1871 SDOperand N0 = N->getOperand(0); 1872 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1873 MVT::ValueType VT = N->getValueType(0); 1874 1875 // fold (uint_to_fp c1) -> c1fp 1876 if (N0C) 1877 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 1878 return SDOperand(); 1879} 1880 1881SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1882 SDOperand N0 = N->getOperand(0); 1883 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1884 MVT::ValueType VT = N->getValueType(0); 1885 1886 // fold (fp_to_sint c1fp) -> c1 1887 if (N0CFP) 1888 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 1889 return SDOperand(); 1890} 1891 1892SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1893 SDOperand N0 = N->getOperand(0); 1894 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1895 MVT::ValueType VT = N->getValueType(0); 1896 1897 // fold (fp_to_uint c1fp) -> c1 1898 if (N0CFP) 1899 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 1900 return SDOperand(); 1901} 1902 1903SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1904 SDOperand N0 = N->getOperand(0); 1905 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1906 MVT::ValueType VT = N->getValueType(0); 1907 1908 // fold (fp_round c1fp) -> c1fp 1909 if (N0CFP) 1910 return DAG.getNode(ISD::FP_ROUND, VT, N0); 1911 return SDOperand(); 1912} 1913 1914SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1915 SDOperand N0 = N->getOperand(0); 1916 MVT::ValueType VT = N->getValueType(0); 1917 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1918 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1919 1920 // fold (fp_round_inreg c1fp) -> c1fp 1921 if (N0CFP) { 1922 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1923 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1924 } 1925 return SDOperand(); 1926} 1927 1928SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1929 SDOperand N0 = N->getOperand(0); 1930 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1931 MVT::ValueType VT = N->getValueType(0); 1932 1933 // fold (fp_extend c1fp) -> c1fp 1934 if (N0CFP) 1935 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 1936 return SDOperand(); 1937} 1938 1939SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1940 SDOperand N0 = N->getOperand(0); 1941 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1942 MVT::ValueType VT = N->getValueType(0); 1943 1944 // fold (fneg c1) -> -c1 1945 if (N0CFP) 1946 return DAG.getNode(ISD::FNEG, VT, N0); 1947 // fold (fneg (sub x, y)) -> (sub y, x) 1948 if (N->getOperand(0).getOpcode() == ISD::SUB) 1949 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0)); 1950 // fold (fneg (fneg x)) -> x 1951 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1952 return N->getOperand(0).getOperand(0); 1953 return SDOperand(); 1954} 1955 1956SDOperand DAGCombiner::visitFABS(SDNode *N) { 1957 SDOperand N0 = N->getOperand(0); 1958 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1959 MVT::ValueType VT = N->getValueType(0); 1960 1961 // fold (fabs c1) -> fabs(c1) 1962 if (N0CFP) 1963 return DAG.getNode(ISD::FABS, VT, N0); 1964 // fold (fabs (fabs x)) -> (fabs x) 1965 if (N->getOperand(0).getOpcode() == ISD::FABS) 1966 return N->getOperand(0); 1967 // fold (fabs (fneg x)) -> (fabs x) 1968 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1969 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0)); 1970 return SDOperand(); 1971} 1972 1973SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 1974 SDOperand Chain = N->getOperand(0); 1975 SDOperand N1 = N->getOperand(1); 1976 SDOperand N2 = N->getOperand(2); 1977 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1978 1979 // never taken branch, fold to chain 1980 if (N1C && N1C->isNullValue()) 1981 return Chain; 1982 // unconditional branch 1983 if (N1C && N1C->getValue() == 1) 1984 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1985 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 1986 // on the target. 1987 if (N1.getOpcode() == ISD::SETCC && 1988 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 1989 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 1990 N1.getOperand(0), N1.getOperand(1), N2); 1991 } 1992 return SDOperand(); 1993} 1994 1995SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 1996 SDOperand Chain = N->getOperand(0); 1997 SDOperand N1 = N->getOperand(1); 1998 SDOperand N2 = N->getOperand(2); 1999 SDOperand N3 = N->getOperand(3); 2000 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2001 2002 // unconditional branch to true mbb 2003 if (N1C && N1C->getValue() == 1) 2004 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2005 // unconditional branch to false mbb 2006 if (N1C && N1C->isNullValue()) 2007 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 2008 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if 2009 // BRTWOWAY_CC is legal on the target. 2010 if (N1.getOpcode() == ISD::SETCC && 2011 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 2012 std::vector<SDOperand> Ops; 2013 Ops.push_back(Chain); 2014 Ops.push_back(N1.getOperand(2)); 2015 Ops.push_back(N1.getOperand(0)); 2016 Ops.push_back(N1.getOperand(1)); 2017 Ops.push_back(N2); 2018 Ops.push_back(N3); 2019 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2020 } 2021 return SDOperand(); 2022} 2023 2024// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2025// 2026SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2027 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2028 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2029 2030 // Use SimplifySetCC to simplify SETCC's. 2031 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2032 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2033 2034 // fold br_cc true, dest -> br dest (unconditional branch) 2035 if (SCCC && SCCC->getValue()) 2036 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2037 N->getOperand(4)); 2038 // fold br_cc false, dest -> unconditional fall through 2039 if (SCCC && SCCC->isNullValue()) 2040 return N->getOperand(0); 2041 // fold to a simpler setcc 2042 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2043 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2044 Simp.getOperand(2), Simp.getOperand(0), 2045 Simp.getOperand(1), N->getOperand(4)); 2046 return SDOperand(); 2047} 2048 2049SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 2050 SDOperand Chain = N->getOperand(0); 2051 SDOperand CCN = N->getOperand(1); 2052 SDOperand LHS = N->getOperand(2); 2053 SDOperand RHS = N->getOperand(3); 2054 SDOperand N4 = N->getOperand(4); 2055 SDOperand N5 = N->getOperand(5); 2056 2057 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 2058 cast<CondCodeSDNode>(CCN)->get(), false); 2059 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2060 2061 // fold select_cc lhs, rhs, x, x, cc -> x 2062 if (N4 == N5) 2063 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2064 // fold select_cc true, x, y -> x 2065 if (SCCC && SCCC->getValue()) 2066 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2067 // fold select_cc false, x, y -> y 2068 if (SCCC && SCCC->isNullValue()) 2069 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 2070 // fold to a simpler setcc 2071 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) { 2072 std::vector<SDOperand> Ops; 2073 Ops.push_back(Chain); 2074 Ops.push_back(SCC.getOperand(2)); 2075 Ops.push_back(SCC.getOperand(0)); 2076 Ops.push_back(SCC.getOperand(1)); 2077 Ops.push_back(N4); 2078 Ops.push_back(N5); 2079 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2080 } 2081 return SDOperand(); 2082} 2083 2084SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2085 SDOperand Chain = N->getOperand(0); 2086 SDOperand Ptr = N->getOperand(1); 2087 SDOperand SrcValue = N->getOperand(2); 2088 2089 // If this load is directly stored, replace the load value with the stored 2090 // value. 2091 // TODO: Handle store large -> read small portion. 2092 // TODO: Handle TRUNCSTORE/EXTLOAD 2093 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2094 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2095 return CombineTo(N, Chain.getOperand(1), Chain); 2096 2097 return SDOperand(); 2098} 2099 2100SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2101 SDOperand Chain = N->getOperand(0); 2102 SDOperand Value = N->getOperand(1); 2103 SDOperand Ptr = N->getOperand(2); 2104 SDOperand SrcValue = N->getOperand(3); 2105 2106 // If this is a store that kills a previous store, remove the previous store. 2107 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2108 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2109 // Make sure that these stores are the same value type: 2110 // FIXME: we really care that the second store is >= size of the first. 2111 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2112 // Create a new store of Value that replaces both stores. 2113 SDNode *PrevStore = Chain.Val; 2114 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2115 return Chain; 2116 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2117 PrevStore->getOperand(0), Value, Ptr, 2118 SrcValue); 2119 CombineTo(N, NewStore); // Nuke this store. 2120 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2121 return SDOperand(N, 0); 2122 } 2123 2124 // If this is a store of a bit convert, store the input value. 2125 // FIXME: This needs to know that the resultant store does not need a 2126 // higher alignment than the original. 2127 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2128 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2129 Ptr, SrcValue); 2130 2131 return SDOperand(); 2132} 2133 2134SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2135 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2136 2137 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2138 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2139 // If we got a simplified select_cc node back from SimplifySelectCC, then 2140 // break it down into a new SETCC node, and a new SELECT node, and then return 2141 // the SELECT node, since we were called with a SELECT node. 2142 if (SCC.Val) { 2143 // Check to see if we got a select_cc back (to turn into setcc/select). 2144 // Otherwise, just return whatever node we got back, like fabs. 2145 if (SCC.getOpcode() == ISD::SELECT_CC) { 2146 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2147 SCC.getOperand(0), SCC.getOperand(1), 2148 SCC.getOperand(4)); 2149 WorkList.push_back(SETCC.Val); 2150 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2151 SCC.getOperand(3), SETCC); 2152 } 2153 return SCC; 2154 } 2155 return SDOperand(); 2156} 2157 2158/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2159/// are the two values being selected between, see if we can simplify the 2160/// select. 2161/// 2162bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2163 SDOperand RHS) { 2164 2165 // If this is a select from two identical things, try to pull the operation 2166 // through the select. 2167 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2168#if 0 2169 std::cerr << "SELECT: ["; LHS.Val->dump(); 2170 std::cerr << "] ["; RHS.Val->dump(); 2171 std::cerr << "]\n"; 2172#endif 2173 2174 // If this is a load and the token chain is identical, replace the select 2175 // of two loads with a load through a select of the address to load from. 2176 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2177 // constants have been dropped into the constant pool. 2178 if ((LHS.getOpcode() == ISD::LOAD || 2179 LHS.getOpcode() == ISD::EXTLOAD || 2180 LHS.getOpcode() == ISD::ZEXTLOAD || 2181 LHS.getOpcode() == ISD::SEXTLOAD) && 2182 // Token chains must be identical. 2183 LHS.getOperand(0) == RHS.getOperand(0) && 2184 // If this is an EXTLOAD, the VT's must match. 2185 (LHS.getOpcode() == ISD::LOAD || 2186 LHS.getOperand(3) == RHS.getOperand(3))) { 2187 // FIXME: this conflates two src values, discarding one. This is not 2188 // the right thing to do, but nothing uses srcvalues now. When they do, 2189 // turn SrcValue into a list of locations. 2190 SDOperand Addr; 2191 if (TheSelect->getOpcode() == ISD::SELECT) 2192 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2193 TheSelect->getOperand(0), LHS.getOperand(1), 2194 RHS.getOperand(1)); 2195 else 2196 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2197 TheSelect->getOperand(0), 2198 TheSelect->getOperand(1), 2199 LHS.getOperand(1), RHS.getOperand(1), 2200 TheSelect->getOperand(4)); 2201 2202 SDOperand Load; 2203 if (LHS.getOpcode() == ISD::LOAD) 2204 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2205 Addr, LHS.getOperand(2)); 2206 else 2207 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2208 LHS.getOperand(0), Addr, LHS.getOperand(2), 2209 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2210 // Users of the select now use the result of the load. 2211 CombineTo(TheSelect, Load); 2212 2213 // Users of the old loads now use the new load's chain. We know the 2214 // old-load value is dead now. 2215 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2216 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2217 return true; 2218 } 2219 } 2220 2221 return false; 2222} 2223 2224SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2225 SDOperand N2, SDOperand N3, 2226 ISD::CondCode CC) { 2227 2228 MVT::ValueType VT = N2.getValueType(); 2229 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2230 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2231 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2232 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2233 2234 // Determine if the condition we're dealing with is constant 2235 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2236 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2237 2238 // fold select_cc true, x, y -> x 2239 if (SCCC && SCCC->getValue()) 2240 return N2; 2241 // fold select_cc false, x, y -> y 2242 if (SCCC && SCCC->getValue() == 0) 2243 return N3; 2244 2245 // Check to see if we can simplify the select into an fabs node 2246 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2247 // Allow either -0.0 or 0.0 2248 if (CFP->getValue() == 0.0) { 2249 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2250 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2251 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2252 N2 == N3.getOperand(0)) 2253 return DAG.getNode(ISD::FABS, VT, N0); 2254 2255 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2256 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2257 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2258 N2.getOperand(0) == N3) 2259 return DAG.getNode(ISD::FABS, VT, N3); 2260 } 2261 } 2262 2263 // Check to see if we can perform the "gzip trick", transforming 2264 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2265 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2266 MVT::isInteger(N0.getValueType()) && 2267 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2268 MVT::ValueType XType = N0.getValueType(); 2269 MVT::ValueType AType = N2.getValueType(); 2270 if (XType >= AType) { 2271 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2272 // single-bit constant. 2273 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2274 unsigned ShCtV = Log2_64(N2C->getValue()); 2275 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 2276 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 2277 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 2278 WorkList.push_back(Shift.Val); 2279 if (XType > AType) { 2280 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2281 WorkList.push_back(Shift.Val); 2282 } 2283 return DAG.getNode(ISD::AND, AType, Shift, N2); 2284 } 2285 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2286 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2287 TLI.getShiftAmountTy())); 2288 WorkList.push_back(Shift.Val); 2289 if (XType > AType) { 2290 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2291 WorkList.push_back(Shift.Val); 2292 } 2293 return DAG.getNode(ISD::AND, AType, Shift, N2); 2294 } 2295 } 2296 2297 // fold select C, 16, 0 -> shl C, 4 2298 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 2299 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 2300 // Get a SetCC of the condition 2301 // FIXME: Should probably make sure that setcc is legal if we ever have a 2302 // target where it isn't. 2303 SDOperand Temp, SCC; 2304 // cast from setcc result type to select result type 2305 if (AfterLegalize) { 2306 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2307 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 2308 } else { 2309 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 2310 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 2311 } 2312 WorkList.push_back(SCC.Val); 2313 WorkList.push_back(Temp.Val); 2314 // shl setcc result by log2 n2c 2315 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 2316 DAG.getConstant(Log2_64(N2C->getValue()), 2317 TLI.getShiftAmountTy())); 2318 } 2319 2320 // Check to see if this is the equivalent of setcc 2321 // FIXME: Turn all of these into setcc if setcc if setcc is legal 2322 // otherwise, go ahead with the folds. 2323 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 2324 MVT::ValueType XType = N0.getValueType(); 2325 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 2326 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2327 if (Res.getValueType() != VT) 2328 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 2329 return Res; 2330 } 2331 2332 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 2333 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 2334 TLI.isOperationLegal(ISD::CTLZ, XType)) { 2335 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 2336 return DAG.getNode(ISD::SRL, XType, Ctlz, 2337 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 2338 TLI.getShiftAmountTy())); 2339 } 2340 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 2341 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 2342 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 2343 N0); 2344 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 2345 DAG.getConstant(~0ULL, XType)); 2346 return DAG.getNode(ISD::SRL, XType, 2347 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 2348 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2349 TLI.getShiftAmountTy())); 2350 } 2351 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 2352 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 2353 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 2354 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2355 TLI.getShiftAmountTy())); 2356 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 2357 } 2358 } 2359 2360 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 2361 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2362 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 2363 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 2364 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 2365 MVT::ValueType XType = N0.getValueType(); 2366 if (SubC->isNullValue() && MVT::isInteger(XType)) { 2367 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2368 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2369 TLI.getShiftAmountTy())); 2370 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 2371 WorkList.push_back(Shift.Val); 2372 WorkList.push_back(Add.Val); 2373 return DAG.getNode(ISD::XOR, XType, Add, Shift); 2374 } 2375 } 2376 } 2377 2378 return SDOperand(); 2379} 2380 2381SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 2382 SDOperand N1, ISD::CondCode Cond, 2383 bool foldBooleans) { 2384 // These setcc operations always fold. 2385 switch (Cond) { 2386 default: break; 2387 case ISD::SETFALSE: 2388 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 2389 case ISD::SETTRUE: 2390 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 2391 } 2392 2393 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 2394 uint64_t C1 = N1C->getValue(); 2395 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 2396 uint64_t C0 = N0C->getValue(); 2397 2398 // Sign extend the operands if required 2399 if (ISD::isSignedIntSetCC(Cond)) { 2400 C0 = N0C->getSignExtended(); 2401 C1 = N1C->getSignExtended(); 2402 } 2403 2404 switch (Cond) { 2405 default: assert(0 && "Unknown integer setcc!"); 2406 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2407 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2408 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 2409 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 2410 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 2411 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 2412 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 2413 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 2414 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 2415 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 2416 } 2417 } else { 2418 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2419 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2420 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 2421 2422 // If the comparison constant has bits in the upper part, the 2423 // zero-extended value could never match. 2424 if (C1 & (~0ULL << InSize)) { 2425 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 2426 switch (Cond) { 2427 case ISD::SETUGT: 2428 case ISD::SETUGE: 2429 case ISD::SETEQ: return DAG.getConstant(0, VT); 2430 case ISD::SETULT: 2431 case ISD::SETULE: 2432 case ISD::SETNE: return DAG.getConstant(1, VT); 2433 case ISD::SETGT: 2434 case ISD::SETGE: 2435 // True if the sign bit of C1 is set. 2436 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 2437 case ISD::SETLT: 2438 case ISD::SETLE: 2439 // True if the sign bit of C1 isn't set. 2440 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 2441 default: 2442 break; 2443 } 2444 } 2445 2446 // Otherwise, we can perform the comparison with the low bits. 2447 switch (Cond) { 2448 case ISD::SETEQ: 2449 case ISD::SETNE: 2450 case ISD::SETUGT: 2451 case ISD::SETUGE: 2452 case ISD::SETULT: 2453 case ISD::SETULE: 2454 return DAG.getSetCC(VT, N0.getOperand(0), 2455 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 2456 Cond); 2457 default: 2458 break; // todo, be more careful with signed comparisons 2459 } 2460 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2461 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2462 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2463 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 2464 MVT::ValueType ExtDstTy = N0.getValueType(); 2465 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 2466 2467 // If the extended part has any inconsistent bits, it cannot ever 2468 // compare equal. In other words, they have to be all ones or all 2469 // zeros. 2470 uint64_t ExtBits = 2471 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 2472 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 2473 return DAG.getConstant(Cond == ISD::SETNE, VT); 2474 2475 SDOperand ZextOp; 2476 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 2477 if (Op0Ty == ExtSrcTy) { 2478 ZextOp = N0.getOperand(0); 2479 } else { 2480 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 2481 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 2482 DAG.getConstant(Imm, Op0Ty)); 2483 } 2484 WorkList.push_back(ZextOp.Val); 2485 // Otherwise, make this a use of a zext. 2486 return DAG.getSetCC(VT, ZextOp, 2487 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 2488 ExtDstTy), 2489 Cond); 2490 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 2491 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2492 (N0.getOpcode() == ISD::XOR || 2493 (N0.getOpcode() == ISD::AND && 2494 N0.getOperand(0).getOpcode() == ISD::XOR && 2495 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2496 isa<ConstantSDNode>(N0.getOperand(1)) && 2497 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 2498 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 2499 // only do this if the top bits are known zero. 2500 if (TLI.MaskedValueIsZero(N1, 2501 MVT::getIntVTBitMask(N0.getValueType())-1)) { 2502 // Okay, get the un-inverted input value. 2503 SDOperand Val; 2504 if (N0.getOpcode() == ISD::XOR) 2505 Val = N0.getOperand(0); 2506 else { 2507 assert(N0.getOpcode() == ISD::AND && 2508 N0.getOperand(0).getOpcode() == ISD::XOR); 2509 // ((X^1)&1)^1 -> X & 1 2510 Val = DAG.getNode(ISD::AND, N0.getValueType(), 2511 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 2512 } 2513 return DAG.getSetCC(VT, Val, N1, 2514 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2515 } 2516 } 2517 2518 uint64_t MinVal, MaxVal; 2519 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 2520 if (ISD::isSignedIntSetCC(Cond)) { 2521 MinVal = 1ULL << (OperandBitSize-1); 2522 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2523 MaxVal = ~0ULL >> (65-OperandBitSize); 2524 else 2525 MaxVal = 0; 2526 } else { 2527 MinVal = 0; 2528 MaxVal = ~0ULL >> (64-OperandBitSize); 2529 } 2530 2531 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2532 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2533 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2534 --C1; // X >= C0 --> X > (C0-1) 2535 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2536 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2537 } 2538 2539 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2540 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2541 ++C1; // X <= C0 --> X < (C0+1) 2542 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2543 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2544 } 2545 2546 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2547 return DAG.getConstant(0, VT); // X < MIN --> false 2548 2549 // Canonicalize setgt X, Min --> setne X, Min 2550 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2551 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2552 // Canonicalize setlt X, Max --> setne X, Max 2553 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2554 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2555 2556 // If we have setult X, 1, turn it into seteq X, 0 2557 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2558 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2559 ISD::SETEQ); 2560 // If we have setugt X, Max-1, turn it into seteq X, Max 2561 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2562 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2563 ISD::SETEQ); 2564 2565 // If we have "setcc X, C0", check to see if we can shrink the immediate 2566 // by changing cc. 2567 2568 // SETUGT X, SINTMAX -> SETLT X, 0 2569 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2570 C1 == (~0ULL >> (65-OperandBitSize))) 2571 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2572 ISD::SETLT); 2573 2574 // FIXME: Implement the rest of these. 2575 2576 // Fold bit comparisons when we can. 2577 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2578 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2579 if (ConstantSDNode *AndRHS = 2580 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2581 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2582 // Perform the xform if the AND RHS is a single bit. 2583 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2584 return DAG.getNode(ISD::SRL, VT, N0, 2585 DAG.getConstant(Log2_64(AndRHS->getValue()), 2586 TLI.getShiftAmountTy())); 2587 } 2588 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2589 // (X & 8) == 8 --> (X & 8) >> 3 2590 // Perform the xform if C1 is a single bit. 2591 if ((C1 & (C1-1)) == 0) { 2592 return DAG.getNode(ISD::SRL, VT, N0, 2593 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2594 } 2595 } 2596 } 2597 } 2598 } else if (isa<ConstantSDNode>(N0.Val)) { 2599 // Ensure that the constant occurs on the RHS. 2600 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2601 } 2602 2603 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2604 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2605 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2606 2607 switch (Cond) { 2608 default: break; // FIXME: Implement the rest of these! 2609 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2610 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2611 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2612 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2613 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2614 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2615 } 2616 } else { 2617 // Ensure that the constant occurs on the RHS. 2618 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2619 } 2620 2621 if (N0 == N1) { 2622 // We can always fold X == Y for integer setcc's. 2623 if (MVT::isInteger(N0.getValueType())) 2624 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2625 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2626 if (UOF == 2) // FP operators that are undefined on NaNs. 2627 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2628 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2629 return DAG.getConstant(UOF, VT); 2630 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2631 // if it is not already. 2632 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2633 if (NewCond != Cond) 2634 return DAG.getSetCC(VT, N0, N1, NewCond); 2635 } 2636 2637 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2638 MVT::isInteger(N0.getValueType())) { 2639 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2640 N0.getOpcode() == ISD::XOR) { 2641 // Simplify (X+Y) == (X+Z) --> Y == Z 2642 if (N0.getOpcode() == N1.getOpcode()) { 2643 if (N0.getOperand(0) == N1.getOperand(0)) 2644 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2645 if (N0.getOperand(1) == N1.getOperand(1)) 2646 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2647 if (isCommutativeBinOp(N0.getOpcode())) { 2648 // If X op Y == Y op X, try other combinations. 2649 if (N0.getOperand(0) == N1.getOperand(1)) 2650 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2651 if (N0.getOperand(1) == N1.getOperand(0)) 2652 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 2653 } 2654 } 2655 2656 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2657 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2658 // Turn (X+C1) == C2 --> X == C2-C1 2659 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 2660 return DAG.getSetCC(VT, N0.getOperand(0), 2661 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 2662 N0.getValueType()), Cond); 2663 } 2664 2665 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2666 if (N0.getOpcode() == ISD::XOR) 2667 // If we know that all of the inverted bits are zero, don't bother 2668 // performing the inversion. 2669 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 2670 return DAG.getSetCC(VT, N0.getOperand(0), 2671 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 2672 N0.getValueType()), Cond); 2673 } 2674 2675 // Turn (C1-X) == C2 --> X == C1-C2 2676 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2677 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 2678 return DAG.getSetCC(VT, N0.getOperand(1), 2679 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 2680 N0.getValueType()), Cond); 2681 } 2682 } 2683 } 2684 2685 // Simplify (X+Z) == X --> Z == 0 2686 if (N0.getOperand(0) == N1) 2687 return DAG.getSetCC(VT, N0.getOperand(1), 2688 DAG.getConstant(0, N0.getValueType()), Cond); 2689 if (N0.getOperand(1) == N1) { 2690 if (isCommutativeBinOp(N0.getOpcode())) 2691 return DAG.getSetCC(VT, N0.getOperand(0), 2692 DAG.getConstant(0, N0.getValueType()), Cond); 2693 else { 2694 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2695 // (Z-X) == X --> Z == X<<1 2696 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2697 N1, 2698 DAG.getConstant(1,TLI.getShiftAmountTy())); 2699 WorkList.push_back(SH.Val); 2700 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2701 } 2702 } 2703 } 2704 2705 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2706 N1.getOpcode() == ISD::XOR) { 2707 // Simplify X == (X+Z) --> Z == 0 2708 if (N1.getOperand(0) == N0) { 2709 return DAG.getSetCC(VT, N1.getOperand(1), 2710 DAG.getConstant(0, N1.getValueType()), Cond); 2711 } else if (N1.getOperand(1) == N0) { 2712 if (isCommutativeBinOp(N1.getOpcode())) { 2713 return DAG.getSetCC(VT, N1.getOperand(0), 2714 DAG.getConstant(0, N1.getValueType()), Cond); 2715 } else { 2716 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2717 // X == (Z-X) --> X<<1 == Z 2718 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2719 DAG.getConstant(1,TLI.getShiftAmountTy())); 2720 WorkList.push_back(SH.Val); 2721 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2722 } 2723 } 2724 } 2725 } 2726 2727 // Fold away ALL boolean setcc's. 2728 SDOperand Temp; 2729 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2730 switch (Cond) { 2731 default: assert(0 && "Unknown integer setcc!"); 2732 case ISD::SETEQ: // X == Y -> (X^Y)^1 2733 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2734 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2735 WorkList.push_back(Temp.Val); 2736 break; 2737 case ISD::SETNE: // X != Y --> (X^Y) 2738 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2739 break; 2740 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2741 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2742 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2743 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2744 WorkList.push_back(Temp.Val); 2745 break; 2746 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2747 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2748 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2749 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2750 WorkList.push_back(Temp.Val); 2751 break; 2752 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2753 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2754 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2755 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2756 WorkList.push_back(Temp.Val); 2757 break; 2758 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2759 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2760 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2761 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2762 break; 2763 } 2764 if (VT != MVT::i1) { 2765 WorkList.push_back(N0.Val); 2766 // FIXME: If running after legalize, we probably can't do this. 2767 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2768 } 2769 return N0; 2770 } 2771 2772 // Could not fold it. 2773 return SDOperand(); 2774} 2775 2776/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2777/// return a DAG expression to select that will generate the same value by 2778/// multiplying by a magic number. See: 2779/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2780SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 2781 MVT::ValueType VT = N->getValueType(0); 2782 2783 // Check to see if we can do this. 2784 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2785 return SDOperand(); // BuildSDIV only operates on i32 or i64 2786 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 2787 return SDOperand(); // Make sure the target supports MULHS. 2788 2789 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2790 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2791 2792 // Multiply the numerator (operand 0) by the magic value 2793 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2794 DAG.getConstant(magics.m, VT)); 2795 // If d > 0 and m < 0, add the numerator 2796 if (d > 0 && magics.m < 0) { 2797 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2798 WorkList.push_back(Q.Val); 2799 } 2800 // If d < 0 and m > 0, subtract the numerator. 2801 if (d < 0 && magics.m > 0) { 2802 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2803 WorkList.push_back(Q.Val); 2804 } 2805 // Shift right algebraic if shift value is nonzero 2806 if (magics.s > 0) { 2807 Q = DAG.getNode(ISD::SRA, VT, Q, 2808 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2809 WorkList.push_back(Q.Val); 2810 } 2811 // Extract the sign bit and add it to the quotient 2812 SDOperand T = 2813 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 2814 TLI.getShiftAmountTy())); 2815 WorkList.push_back(T.Val); 2816 return DAG.getNode(ISD::ADD, VT, Q, T); 2817} 2818 2819/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2820/// return a DAG expression to select that will generate the same value by 2821/// multiplying by a magic number. See: 2822/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2823SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 2824 MVT::ValueType VT = N->getValueType(0); 2825 2826 // Check to see if we can do this. 2827 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2828 return SDOperand(); // BuildUDIV only operates on i32 or i64 2829 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 2830 return SDOperand(); // Make sure the target supports MULHU. 2831 2832 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2833 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2834 2835 // Multiply the numerator (operand 0) by the magic value 2836 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2837 DAG.getConstant(magics.m, VT)); 2838 WorkList.push_back(Q.Val); 2839 2840 if (magics.a == 0) { 2841 return DAG.getNode(ISD::SRL, VT, Q, 2842 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2843 } else { 2844 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2845 WorkList.push_back(NPQ.Val); 2846 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2847 DAG.getConstant(1, TLI.getShiftAmountTy())); 2848 WorkList.push_back(NPQ.Val); 2849 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2850 WorkList.push_back(NPQ.Val); 2851 return DAG.getNode(ISD::SRL, VT, NPQ, 2852 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 2853 } 2854} 2855 2856// SelectionDAG::Combine - This is the entry point for the file. 2857// 2858void SelectionDAG::Combine(bool RunningAfterLegalize) { 2859 /// run - This is the main entry point to this class. 2860 /// 2861 DAGCombiner(*this).Run(RunningAfterLegalize); 2862} 2863