DAGCombiner.cpp revision 301f405ef34539e7f287513bd7df0cbcf4f71d07
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32using namespace llvm; 33 34STATISTIC(NodesCombined , "Number of dag nodes combined"); 35STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 36STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 37 38namespace { 39#ifndef NDEBUG 40 static cl::opt<bool> 41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 42 cl::desc("Pop up a window to show dags before the first " 43 "dag combine pass")); 44 static cl::opt<bool> 45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 46 cl::desc("Pop up a window to show dags before the second " 47 "dag combine pass")); 48#else 49 static const bool ViewDAGCombine1 = false; 50 static const bool ViewDAGCombine2 = false; 51#endif 52 53 static cl::opt<bool> 54 CombinerAA("combiner-alias-analysis", cl::Hidden, 55 cl::desc("Turn on alias analysis during testing")); 56 57 static cl::opt<bool> 58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 59 cl::desc("Include global information in alias analysis")); 60 61//------------------------------ DAGCombiner ---------------------------------// 62 63 class VISIBILITY_HIDDEN DAGCombiner { 64 SelectionDAG &DAG; 65 TargetLowering &TLI; 66 bool AfterLegalize; 67 68 // Worklist of all of the nodes that need to be simplified. 69 std::vector<SDNode*> WorkList; 70 71 // AA - Used for DAG load/store alias analysis. 72 AliasAnalysis &AA; 73 74 /// AddUsersToWorkList - When an instruction is simplified, add all users of 75 /// the instruction to the work lists because they might get more simplified 76 /// now. 77 /// 78 void AddUsersToWorkList(SDNode *N) { 79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 80 UI != UE; ++UI) 81 AddToWorkList(*UI); 82 } 83 84 /// removeFromWorkList - remove all instances of N from the worklist. 85 /// 86 void removeFromWorkList(SDNode *N) { 87 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 88 WorkList.end()); 89 } 90 91 /// visit - call the node-specific routine that knows how to fold each 92 /// particular type of node. 93 SDOperand visit(SDNode *N); 94 95 public: 96 /// AddToWorkList - Add to the work list making sure it's instance is at the 97 /// the back (next to be processed.) 98 void AddToWorkList(SDNode *N) { 99 removeFromWorkList(N); 100 WorkList.push_back(N); 101 } 102 103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 104 bool AddTo = true) { 105 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 106 ++NodesCombined; 107 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 108 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 109 DOUT << " and " << NumTo-1 << " other values\n"; 110 std::vector<SDNode*> NowDead; 111 DAG.ReplaceAllUsesWith(N, To, &NowDead); 112 113 if (AddTo) { 114 // Push the new nodes and any users onto the worklist 115 for (unsigned i = 0, e = NumTo; i != e; ++i) { 116 AddToWorkList(To[i].Val); 117 AddUsersToWorkList(To[i].Val); 118 } 119 } 120 121 // Nodes can be reintroduced into the worklist. Make sure we do not 122 // process a node that has been replaced. 123 removeFromWorkList(N); 124 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 125 removeFromWorkList(NowDead[i]); 126 127 // Finally, since the node is now dead, remove it from the graph. 128 DAG.DeleteNode(N); 129 return SDOperand(N, 0); 130 } 131 132 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 133 return CombineTo(N, &Res, 1, AddTo); 134 } 135 136 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 137 bool AddTo = true) { 138 SDOperand To[] = { Res0, Res1 }; 139 return CombineTo(N, To, 2, AddTo); 140 } 141 142 private: 143 144 /// SimplifyDemandedBits - Check the specified integer node value to see if 145 /// it can be simplified or if things it uses can be simplified by bit 146 /// propagation. If so, return true. 147 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) { 148 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 149 uint64_t KnownZero, KnownOne; 150 Demanded &= MVT::getIntVTBitMask(Op.getValueType()); 151 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 152 return false; 153 154 // Revisit the node. 155 AddToWorkList(Op.Val); 156 157 // Replace the old value with the new one. 158 ++NodesCombined; 159 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 160 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 161 DOUT << '\n'; 162 163 std::vector<SDNode*> NowDead; 164 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead); 165 166 // Push the new node and any (possibly new) users onto the worklist. 167 AddToWorkList(TLO.New.Val); 168 AddUsersToWorkList(TLO.New.Val); 169 170 // Nodes can end up on the worklist more than once. Make sure we do 171 // not process a node that has been replaced. 172 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 173 removeFromWorkList(NowDead[i]); 174 175 // Finally, if the node is now dead, remove it from the graph. The node 176 // may not be dead if the replacement process recursively simplified to 177 // something else needing this node. 178 if (TLO.Old.Val->use_empty()) { 179 removeFromWorkList(TLO.Old.Val); 180 181 // If the operands of this node are only used by the node, they will now 182 // be dead. Make sure to visit them first to delete dead nodes early. 183 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 184 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 185 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 186 187 DAG.DeleteNode(TLO.Old.Val); 188 } 189 return true; 190 } 191 192 bool CombineToPreIndexedLoadStore(SDNode *N); 193 bool CombineToPostIndexedLoadStore(SDNode *N); 194 195 196 /// combine - call the node-specific routine that knows how to fold each 197 /// particular type of node. If that doesn't do anything, try the 198 /// target-specific DAG combines. 199 SDOperand combine(SDNode *N); 200 201 // Visitation implementation - Implement dag node combining for different 202 // node types. The semantics are as follows: 203 // Return Value: 204 // SDOperand.Val == 0 - No change was made 205 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 206 // otherwise - N should be replaced by the returned Operand. 207 // 208 SDOperand visitTokenFactor(SDNode *N); 209 SDOperand visitADD(SDNode *N); 210 SDOperand visitSUB(SDNode *N); 211 SDOperand visitADDC(SDNode *N); 212 SDOperand visitADDE(SDNode *N); 213 SDOperand visitMUL(SDNode *N); 214 SDOperand visitSDIV(SDNode *N); 215 SDOperand visitUDIV(SDNode *N); 216 SDOperand visitSREM(SDNode *N); 217 SDOperand visitUREM(SDNode *N); 218 SDOperand visitMULHU(SDNode *N); 219 SDOperand visitMULHS(SDNode *N); 220 SDOperand visitSMUL_LOHI(SDNode *N); 221 SDOperand visitUMUL_LOHI(SDNode *N); 222 SDOperand visitSDIVREM(SDNode *N); 223 SDOperand visitUDIVREM(SDNode *N); 224 SDOperand visitAND(SDNode *N); 225 SDOperand visitOR(SDNode *N); 226 SDOperand visitXOR(SDNode *N); 227 SDOperand SimplifyVBinOp(SDNode *N); 228 SDOperand visitSHL(SDNode *N); 229 SDOperand visitSRA(SDNode *N); 230 SDOperand visitSRL(SDNode *N); 231 SDOperand visitCTLZ(SDNode *N); 232 SDOperand visitCTTZ(SDNode *N); 233 SDOperand visitCTPOP(SDNode *N); 234 SDOperand visitSELECT(SDNode *N); 235 SDOperand visitSELECT_CC(SDNode *N); 236 SDOperand visitSETCC(SDNode *N); 237 SDOperand visitSIGN_EXTEND(SDNode *N); 238 SDOperand visitZERO_EXTEND(SDNode *N); 239 SDOperand visitANY_EXTEND(SDNode *N); 240 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 241 SDOperand visitTRUNCATE(SDNode *N); 242 SDOperand visitBIT_CONVERT(SDNode *N); 243 SDOperand visitFADD(SDNode *N); 244 SDOperand visitFSUB(SDNode *N); 245 SDOperand visitFMUL(SDNode *N); 246 SDOperand visitFDIV(SDNode *N); 247 SDOperand visitFREM(SDNode *N); 248 SDOperand visitFCOPYSIGN(SDNode *N); 249 SDOperand visitSINT_TO_FP(SDNode *N); 250 SDOperand visitUINT_TO_FP(SDNode *N); 251 SDOperand visitFP_TO_SINT(SDNode *N); 252 SDOperand visitFP_TO_UINT(SDNode *N); 253 SDOperand visitFP_ROUND(SDNode *N); 254 SDOperand visitFP_ROUND_INREG(SDNode *N); 255 SDOperand visitFP_EXTEND(SDNode *N); 256 SDOperand visitFNEG(SDNode *N); 257 SDOperand visitFABS(SDNode *N); 258 SDOperand visitBRCOND(SDNode *N); 259 SDOperand visitBR_CC(SDNode *N); 260 SDOperand visitLOAD(SDNode *N); 261 SDOperand visitSTORE(SDNode *N); 262 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 263 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 264 SDOperand visitBUILD_VECTOR(SDNode *N); 265 SDOperand visitCONCAT_VECTORS(SDNode *N); 266 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 267 268 SDOperand XformToShuffleWithZero(SDNode *N); 269 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 270 271 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 272 273 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 274 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 275 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 276 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 277 SDOperand N3, ISD::CondCode CC, 278 bool NotExtCompare = false); 279 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 280 ISD::CondCode Cond, bool foldBooleans = true); 281 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 282 unsigned HiOp); 283 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 284 SDOperand BuildSDIV(SDNode *N); 285 SDOperand BuildUDIV(SDNode *N); 286 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 287 SDOperand ReduceLoadWidth(SDNode *N); 288 289 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask); 290 291 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 292 /// looking for aliasing nodes and adding them to the Aliases vector. 293 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 294 SmallVector<SDOperand, 8> &Aliases); 295 296 /// isAlias - Return true if there is any possibility that the two addresses 297 /// overlap. 298 bool isAlias(SDOperand Ptr1, int64_t Size1, 299 const Value *SrcValue1, int SrcValueOffset1, 300 SDOperand Ptr2, int64_t Size2, 301 const Value *SrcValue2, int SrcValueOffset2); 302 303 /// FindAliasInfo - Extracts the relevant alias information from the memory 304 /// node. Returns true if the operand was a load. 305 bool FindAliasInfo(SDNode *N, 306 SDOperand &Ptr, int64_t &Size, 307 const Value *&SrcValue, int &SrcValueOffset); 308 309 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 310 /// looking for a better chain (aliasing node.) 311 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 312 313public: 314 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 315 : DAG(D), 316 TLI(D.getTargetLoweringInfo()), 317 AfterLegalize(false), 318 AA(A) {} 319 320 /// Run - runs the dag combiner on all nodes in the work list 321 void Run(bool RunningAfterLegalize); 322 }; 323} 324 325//===----------------------------------------------------------------------===// 326// TargetLowering::DAGCombinerInfo implementation 327//===----------------------------------------------------------------------===// 328 329void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 330 ((DAGCombiner*)DC)->AddToWorkList(N); 331} 332 333SDOperand TargetLowering::DAGCombinerInfo:: 334CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 335 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 336} 337 338SDOperand TargetLowering::DAGCombinerInfo:: 339CombineTo(SDNode *N, SDOperand Res) { 340 return ((DAGCombiner*)DC)->CombineTo(N, Res); 341} 342 343 344SDOperand TargetLowering::DAGCombinerInfo:: 345CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 346 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 347} 348 349 350//===----------------------------------------------------------------------===// 351// Helper Functions 352//===----------------------------------------------------------------------===// 353 354/// isNegatibleForFree - Return 1 if we can compute the negated form of the 355/// specified expression for the same cost as the expression itself, or 2 if we 356/// can compute the negated form more cheaply than the expression itself. 357static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 358 // No compile time optimizations on this type. 359 if (Op.getValueType() == MVT::ppcf128) 360 return 0; 361 362 // fneg is removable even if it has multiple uses. 363 if (Op.getOpcode() == ISD::FNEG) return 2; 364 365 // Don't allow anything with multiple uses. 366 if (!Op.hasOneUse()) return 0; 367 368 // Don't recurse exponentially. 369 if (Depth > 6) return 0; 370 371 switch (Op.getOpcode()) { 372 default: return false; 373 case ISD::ConstantFP: 374 return 1; 375 case ISD::FADD: 376 // FIXME: determine better conditions for this xform. 377 if (!UnsafeFPMath) return 0; 378 379 // -(A+B) -> -A - B 380 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 381 return V; 382 // -(A+B) -> -B - A 383 return isNegatibleForFree(Op.getOperand(1), Depth+1); 384 case ISD::FSUB: 385 // We can't turn -(A-B) into B-A when we honor signed zeros. 386 if (!UnsafeFPMath) return 0; 387 388 // -(A-B) -> B-A 389 return 1; 390 391 case ISD::FMUL: 392 case ISD::FDIV: 393 if (HonorSignDependentRoundingFPMath()) return 0; 394 395 // -(X*Y) -> (-X * Y) or (X*-Y) 396 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 397 return V; 398 399 return isNegatibleForFree(Op.getOperand(1), Depth+1); 400 401 case ISD::FP_EXTEND: 402 case ISD::FP_ROUND: 403 case ISD::FSIN: 404 return isNegatibleForFree(Op.getOperand(0), Depth+1); 405 } 406} 407 408/// GetNegatedExpression - If isNegatibleForFree returns true, this function 409/// returns the newly negated expression. 410static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 411 unsigned Depth = 0) { 412 // fneg is removable even if it has multiple uses. 413 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 414 415 // Don't allow anything with multiple uses. 416 assert(Op.hasOneUse() && "Unknown reuse!"); 417 418 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 419 switch (Op.getOpcode()) { 420 default: assert(0 && "Unknown code"); 421 case ISD::ConstantFP: { 422 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 423 V.changeSign(); 424 return DAG.getConstantFP(V, Op.getValueType()); 425 } 426 case ISD::FADD: 427 // FIXME: determine better conditions for this xform. 428 assert(UnsafeFPMath); 429 430 // -(A+B) -> -A - B 431 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 432 return DAG.getNode(ISD::FSUB, Op.getValueType(), 433 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 434 Op.getOperand(1)); 435 // -(A+B) -> -B - A 436 return DAG.getNode(ISD::FSUB, Op.getValueType(), 437 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 438 Op.getOperand(0)); 439 case ISD::FSUB: 440 // We can't turn -(A-B) into B-A when we honor signed zeros. 441 assert(UnsafeFPMath); 442 443 // -(0-B) -> B 444 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 445 if (N0CFP->getValueAPF().isZero()) 446 return Op.getOperand(1); 447 448 // -(A-B) -> B-A 449 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 450 Op.getOperand(0)); 451 452 case ISD::FMUL: 453 case ISD::FDIV: 454 assert(!HonorSignDependentRoundingFPMath()); 455 456 // -(X*Y) -> -X * Y 457 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 458 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 459 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 460 Op.getOperand(1)); 461 462 // -(X*Y) -> X * -Y 463 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 464 Op.getOperand(0), 465 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 466 467 case ISD::FP_EXTEND: 468 case ISD::FSIN: 469 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 470 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 471 case ISD::FP_ROUND: 472 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 473 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 474 Op.getOperand(1)); 475 } 476} 477 478 479// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 480// that selects between the values 1 and 0, making it equivalent to a setcc. 481// Also, set the incoming LHS, RHS, and CC references to the appropriate 482// nodes based on the type of node we are checking. This simplifies life a 483// bit for the callers. 484static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 485 SDOperand &CC) { 486 if (N.getOpcode() == ISD::SETCC) { 487 LHS = N.getOperand(0); 488 RHS = N.getOperand(1); 489 CC = N.getOperand(2); 490 return true; 491 } 492 if (N.getOpcode() == ISD::SELECT_CC && 493 N.getOperand(2).getOpcode() == ISD::Constant && 494 N.getOperand(3).getOpcode() == ISD::Constant && 495 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 496 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 497 LHS = N.getOperand(0); 498 RHS = N.getOperand(1); 499 CC = N.getOperand(4); 500 return true; 501 } 502 return false; 503} 504 505// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 506// one use. If this is true, it allows the users to invert the operation for 507// free when it is profitable to do so. 508static bool isOneUseSetCC(SDOperand N) { 509 SDOperand N0, N1, N2; 510 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 511 return true; 512 return false; 513} 514 515SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 516 MVT::ValueType VT = N0.getValueType(); 517 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 518 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 519 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 520 if (isa<ConstantSDNode>(N1)) { 521 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 522 AddToWorkList(OpNode.Val); 523 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 524 } else if (N0.hasOneUse()) { 525 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 526 AddToWorkList(OpNode.Val); 527 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 528 } 529 } 530 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 531 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 532 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 533 if (isa<ConstantSDNode>(N0)) { 534 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 535 AddToWorkList(OpNode.Val); 536 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 537 } else if (N1.hasOneUse()) { 538 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 539 AddToWorkList(OpNode.Val); 540 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 541 } 542 } 543 return SDOperand(); 544} 545 546//===----------------------------------------------------------------------===// 547// Main DAG Combiner implementation 548//===----------------------------------------------------------------------===// 549 550void DAGCombiner::Run(bool RunningAfterLegalize) { 551 // set the instance variable, so that the various visit routines may use it. 552 AfterLegalize = RunningAfterLegalize; 553 554 // Add all the dag nodes to the worklist. 555 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 556 E = DAG.allnodes_end(); I != E; ++I) 557 WorkList.push_back(I); 558 559 // Create a dummy node (which is not added to allnodes), that adds a reference 560 // to the root node, preventing it from being deleted, and tracking any 561 // changes of the root. 562 HandleSDNode Dummy(DAG.getRoot()); 563 564 // The root of the dag may dangle to deleted nodes until the dag combiner is 565 // done. Set it to null to avoid confusion. 566 DAG.setRoot(SDOperand()); 567 568 // while the worklist isn't empty, inspect the node on the end of it and 569 // try and combine it. 570 while (!WorkList.empty()) { 571 SDNode *N = WorkList.back(); 572 WorkList.pop_back(); 573 574 // If N has no uses, it is dead. Make sure to revisit all N's operands once 575 // N is deleted from the DAG, since they too may now be dead or may have a 576 // reduced number of uses, allowing other xforms. 577 if (N->use_empty() && N != &Dummy) { 578 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 579 AddToWorkList(N->getOperand(i).Val); 580 581 DAG.DeleteNode(N); 582 continue; 583 } 584 585 SDOperand RV = combine(N); 586 587 if (RV.Val == 0) 588 continue; 589 590 ++NodesCombined; 591 592 // If we get back the same node we passed in, rather than a new node or 593 // zero, we know that the node must have defined multiple values and 594 // CombineTo was used. Since CombineTo takes care of the worklist 595 // mechanics for us, we have no work to do in this case. 596 if (RV.Val == N) 597 continue; 598 599 assert(N->getOpcode() != ISD::DELETED_NODE && 600 RV.Val->getOpcode() != ISD::DELETED_NODE && 601 "Node was deleted but visit returned new node!"); 602 603 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 604 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 605 DOUT << '\n'; 606 std::vector<SDNode*> NowDead; 607 if (N->getNumValues() == RV.Val->getNumValues()) 608 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 609 else { 610 assert(N->getValueType(0) == RV.getValueType() && 611 N->getNumValues() == 1 && "Type mismatch"); 612 SDOperand OpV = RV; 613 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 614 } 615 616 // Push the new node and any users onto the worklist 617 AddToWorkList(RV.Val); 618 AddUsersToWorkList(RV.Val); 619 620 // Add any uses of the old node to the worklist in case this node is the 621 // last one that uses them. They may become dead after this node is 622 // deleted. 623 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 624 AddToWorkList(N->getOperand(i).Val); 625 626 // Nodes can be reintroduced into the worklist. Make sure we do not 627 // process a node that has been replaced. 628 removeFromWorkList(N); 629 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 630 removeFromWorkList(NowDead[i]); 631 632 // Finally, since the node is now dead, remove it from the graph. 633 DAG.DeleteNode(N); 634 } 635 636 // If the root changed (e.g. it was a dead load, update the root). 637 DAG.setRoot(Dummy.getValue()); 638} 639 640SDOperand DAGCombiner::visit(SDNode *N) { 641 switch(N->getOpcode()) { 642 default: break; 643 case ISD::TokenFactor: return visitTokenFactor(N); 644 case ISD::ADD: return visitADD(N); 645 case ISD::SUB: return visitSUB(N); 646 case ISD::ADDC: return visitADDC(N); 647 case ISD::ADDE: return visitADDE(N); 648 case ISD::MUL: return visitMUL(N); 649 case ISD::SDIV: return visitSDIV(N); 650 case ISD::UDIV: return visitUDIV(N); 651 case ISD::SREM: return visitSREM(N); 652 case ISD::UREM: return visitUREM(N); 653 case ISD::MULHU: return visitMULHU(N); 654 case ISD::MULHS: return visitMULHS(N); 655 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 656 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 657 case ISD::SDIVREM: return visitSDIVREM(N); 658 case ISD::UDIVREM: return visitUDIVREM(N); 659 case ISD::AND: return visitAND(N); 660 case ISD::OR: return visitOR(N); 661 case ISD::XOR: return visitXOR(N); 662 case ISD::SHL: return visitSHL(N); 663 case ISD::SRA: return visitSRA(N); 664 case ISD::SRL: return visitSRL(N); 665 case ISD::CTLZ: return visitCTLZ(N); 666 case ISD::CTTZ: return visitCTTZ(N); 667 case ISD::CTPOP: return visitCTPOP(N); 668 case ISD::SELECT: return visitSELECT(N); 669 case ISD::SELECT_CC: return visitSELECT_CC(N); 670 case ISD::SETCC: return visitSETCC(N); 671 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 672 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 673 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 674 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 675 case ISD::TRUNCATE: return visitTRUNCATE(N); 676 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 677 case ISD::FADD: return visitFADD(N); 678 case ISD::FSUB: return visitFSUB(N); 679 case ISD::FMUL: return visitFMUL(N); 680 case ISD::FDIV: return visitFDIV(N); 681 case ISD::FREM: return visitFREM(N); 682 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 683 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 684 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 685 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 686 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 687 case ISD::FP_ROUND: return visitFP_ROUND(N); 688 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 689 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 690 case ISD::FNEG: return visitFNEG(N); 691 case ISD::FABS: return visitFABS(N); 692 case ISD::BRCOND: return visitBRCOND(N); 693 case ISD::BR_CC: return visitBR_CC(N); 694 case ISD::LOAD: return visitLOAD(N); 695 case ISD::STORE: return visitSTORE(N); 696 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 697 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 698 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 699 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 700 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 701 } 702 return SDOperand(); 703} 704 705SDOperand DAGCombiner::combine(SDNode *N) { 706 707 SDOperand RV = visit(N); 708 709 // If nothing happened, try a target-specific DAG combine. 710 if (RV.Val == 0) { 711 assert(N->getOpcode() != ISD::DELETED_NODE && 712 "Node was deleted but visit returned NULL!"); 713 714 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 715 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 716 717 // Expose the DAG combiner to the target combiner impls. 718 TargetLowering::DAGCombinerInfo 719 DagCombineInfo(DAG, !AfterLegalize, false, this); 720 721 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 722 } 723 } 724 725 return RV; 726} 727 728/// getInputChainForNode - Given a node, return its input chain if it has one, 729/// otherwise return a null sd operand. 730static SDOperand getInputChainForNode(SDNode *N) { 731 if (unsigned NumOps = N->getNumOperands()) { 732 if (N->getOperand(0).getValueType() == MVT::Other) 733 return N->getOperand(0); 734 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 735 return N->getOperand(NumOps-1); 736 for (unsigned i = 1; i < NumOps-1; ++i) 737 if (N->getOperand(i).getValueType() == MVT::Other) 738 return N->getOperand(i); 739 } 740 return SDOperand(0, 0); 741} 742 743SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 744 // If N has two operands, where one has an input chain equal to the other, 745 // the 'other' chain is redundant. 746 if (N->getNumOperands() == 2) { 747 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 748 return N->getOperand(0); 749 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 750 return N->getOperand(1); 751 } 752 753 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 754 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 755 SmallPtrSet<SDNode*, 16> SeenOps; 756 bool Changed = false; // If we should replace this token factor. 757 758 // Start out with this token factor. 759 TFs.push_back(N); 760 761 // Iterate through token factors. The TFs grows when new token factors are 762 // encountered. 763 for (unsigned i = 0; i < TFs.size(); ++i) { 764 SDNode *TF = TFs[i]; 765 766 // Check each of the operands. 767 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 768 SDOperand Op = TF->getOperand(i); 769 770 switch (Op.getOpcode()) { 771 case ISD::EntryToken: 772 // Entry tokens don't need to be added to the list. They are 773 // rededundant. 774 Changed = true; 775 break; 776 777 case ISD::TokenFactor: 778 if ((CombinerAA || Op.hasOneUse()) && 779 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 780 // Queue up for processing. 781 TFs.push_back(Op.Val); 782 // Clean up in case the token factor is removed. 783 AddToWorkList(Op.Val); 784 Changed = true; 785 break; 786 } 787 // Fall thru 788 789 default: 790 // Only add if it isn't already in the list. 791 if (SeenOps.insert(Op.Val)) 792 Ops.push_back(Op); 793 else 794 Changed = true; 795 break; 796 } 797 } 798 } 799 800 SDOperand Result; 801 802 // If we've change things around then replace token factor. 803 if (Changed) { 804 if (Ops.empty()) { 805 // The entry token is the only possible outcome. 806 Result = DAG.getEntryNode(); 807 } else { 808 // New and improved token factor. 809 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 810 } 811 812 // Don't add users to work list. 813 return CombineTo(N, Result, false); 814 } 815 816 return Result; 817} 818 819static 820SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 821 MVT::ValueType VT = N0.getValueType(); 822 SDOperand N00 = N0.getOperand(0); 823 SDOperand N01 = N0.getOperand(1); 824 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 825 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 826 isa<ConstantSDNode>(N00.getOperand(1))) { 827 N0 = DAG.getNode(ISD::ADD, VT, 828 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 829 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 830 return DAG.getNode(ISD::ADD, VT, N0, N1); 831 } 832 return SDOperand(); 833} 834 835static 836SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 837 SelectionDAG &DAG) { 838 MVT::ValueType VT = N->getValueType(0); 839 unsigned Opc = N->getOpcode(); 840 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 841 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 842 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 843 ISD::CondCode CC = ISD::SETCC_INVALID; 844 if (isSlctCC) 845 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 846 else { 847 SDOperand CCOp = Slct.getOperand(0); 848 if (CCOp.getOpcode() == ISD::SETCC) 849 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 850 } 851 852 bool DoXform = false; 853 bool InvCC = false; 854 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 855 "Bad input!"); 856 if (LHS.getOpcode() == ISD::Constant && 857 cast<ConstantSDNode>(LHS)->isNullValue()) 858 DoXform = true; 859 else if (CC != ISD::SETCC_INVALID && 860 RHS.getOpcode() == ISD::Constant && 861 cast<ConstantSDNode>(RHS)->isNullValue()) { 862 std::swap(LHS, RHS); 863 SDOperand Op0 = Slct.getOperand(0); 864 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() 865 : Op0.getOperand(0).getValueType()); 866 CC = ISD::getSetCCInverse(CC, isInt); 867 DoXform = true; 868 InvCC = true; 869 } 870 871 if (DoXform) { 872 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 873 if (isSlctCC) 874 return DAG.getSelectCC(OtherOp, Result, 875 Slct.getOperand(0), Slct.getOperand(1), CC); 876 SDOperand CCOp = Slct.getOperand(0); 877 if (InvCC) 878 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 879 CCOp.getOperand(1), CC); 880 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 881 } 882 return SDOperand(); 883} 884 885SDOperand DAGCombiner::visitADD(SDNode *N) { 886 SDOperand N0 = N->getOperand(0); 887 SDOperand N1 = N->getOperand(1); 888 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 889 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 890 MVT::ValueType VT = N0.getValueType(); 891 892 // fold vector ops 893 if (MVT::isVector(VT)) { 894 SDOperand FoldedVOp = SimplifyVBinOp(N); 895 if (FoldedVOp.Val) return FoldedVOp; 896 } 897 898 // fold (add x, undef) -> undef 899 if (N0.getOpcode() == ISD::UNDEF) 900 return N0; 901 if (N1.getOpcode() == ISD::UNDEF) 902 return N1; 903 // fold (add c1, c2) -> c1+c2 904 if (N0C && N1C) 905 return DAG.getNode(ISD::ADD, VT, N0, N1); 906 // canonicalize constant to RHS 907 if (N0C && !N1C) 908 return DAG.getNode(ISD::ADD, VT, N1, N0); 909 // fold (add x, 0) -> x 910 if (N1C && N1C->isNullValue()) 911 return N0; 912 // fold ((c1-A)+c2) -> (c1+c2)-A 913 if (N1C && N0.getOpcode() == ISD::SUB) 914 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 915 return DAG.getNode(ISD::SUB, VT, 916 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 917 N0.getOperand(1)); 918 // reassociate add 919 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 920 if (RADD.Val != 0) 921 return RADD; 922 // fold ((0-A) + B) -> B-A 923 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 924 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 925 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 926 // fold (A + (0-B)) -> A-B 927 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 928 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 929 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 930 // fold (A+(B-A)) -> B 931 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 932 return N1.getOperand(0); 933 934 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 935 return SDOperand(N, 0); 936 937 // fold (a+b) -> (a|b) iff a and b share no bits. 938 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 939 uint64_t LHSZero, LHSOne; 940 uint64_t RHSZero, RHSOne; 941 uint64_t Mask = MVT::getIntVTBitMask(VT); 942 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 943 if (LHSZero) { 944 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 945 946 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 947 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 948 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 949 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 950 return DAG.getNode(ISD::OR, VT, N0, N1); 951 } 952 } 953 954 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 955 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 956 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 957 if (Result.Val) return Result; 958 } 959 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 960 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 961 if (Result.Val) return Result; 962 } 963 964 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 965 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 966 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 967 if (Result.Val) return Result; 968 } 969 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 970 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 971 if (Result.Val) return Result; 972 } 973 974 return SDOperand(); 975} 976 977SDOperand DAGCombiner::visitADDC(SDNode *N) { 978 SDOperand N0 = N->getOperand(0); 979 SDOperand N1 = N->getOperand(1); 980 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 981 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 982 MVT::ValueType VT = N0.getValueType(); 983 984 // If the flag result is dead, turn this into an ADD. 985 if (N->hasNUsesOfValue(0, 1)) 986 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 987 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 988 989 // canonicalize constant to RHS. 990 if (N0C && !N1C) { 991 SDOperand Ops[] = { N1, N0 }; 992 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 993 } 994 995 // fold (addc x, 0) -> x + no carry out 996 if (N1C && N1C->isNullValue()) 997 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 998 999 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1000 uint64_t LHSZero, LHSOne; 1001 uint64_t RHSZero, RHSOne; 1002 uint64_t Mask = MVT::getIntVTBitMask(VT); 1003 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1004 if (LHSZero) { 1005 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1006 1007 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1008 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1009 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1010 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1011 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1012 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1013 } 1014 1015 return SDOperand(); 1016} 1017 1018SDOperand DAGCombiner::visitADDE(SDNode *N) { 1019 SDOperand N0 = N->getOperand(0); 1020 SDOperand N1 = N->getOperand(1); 1021 SDOperand CarryIn = N->getOperand(2); 1022 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1023 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1024 //MVT::ValueType VT = N0.getValueType(); 1025 1026 // canonicalize constant to RHS 1027 if (N0C && !N1C) { 1028 SDOperand Ops[] = { N1, N0, CarryIn }; 1029 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1030 } 1031 1032 // fold (adde x, y, false) -> (addc x, y) 1033 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1034 SDOperand Ops[] = { N1, N0 }; 1035 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1036 } 1037 1038 return SDOperand(); 1039} 1040 1041 1042 1043SDOperand DAGCombiner::visitSUB(SDNode *N) { 1044 SDOperand N0 = N->getOperand(0); 1045 SDOperand N1 = N->getOperand(1); 1046 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1048 MVT::ValueType VT = N0.getValueType(); 1049 1050 // fold vector ops 1051 if (MVT::isVector(VT)) { 1052 SDOperand FoldedVOp = SimplifyVBinOp(N); 1053 if (FoldedVOp.Val) return FoldedVOp; 1054 } 1055 1056 // fold (sub x, x) -> 0 1057 if (N0 == N1) 1058 return DAG.getConstant(0, N->getValueType(0)); 1059 // fold (sub c1, c2) -> c1-c2 1060 if (N0C && N1C) 1061 return DAG.getNode(ISD::SUB, VT, N0, N1); 1062 // fold (sub x, c) -> (add x, -c) 1063 if (N1C) 1064 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1065 // fold (A+B)-A -> B 1066 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1067 return N0.getOperand(1); 1068 // fold (A+B)-B -> A 1069 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1070 return N0.getOperand(0); 1071 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1072 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1073 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1074 if (Result.Val) return Result; 1075 } 1076 // If either operand of a sub is undef, the result is undef 1077 if (N0.getOpcode() == ISD::UNDEF) 1078 return N0; 1079 if (N1.getOpcode() == ISD::UNDEF) 1080 return N1; 1081 1082 return SDOperand(); 1083} 1084 1085SDOperand DAGCombiner::visitMUL(SDNode *N) { 1086 SDOperand N0 = N->getOperand(0); 1087 SDOperand N1 = N->getOperand(1); 1088 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1090 MVT::ValueType VT = N0.getValueType(); 1091 1092 // fold vector ops 1093 if (MVT::isVector(VT)) { 1094 SDOperand FoldedVOp = SimplifyVBinOp(N); 1095 if (FoldedVOp.Val) return FoldedVOp; 1096 } 1097 1098 // fold (mul x, undef) -> 0 1099 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1100 return DAG.getConstant(0, VT); 1101 // fold (mul c1, c2) -> c1*c2 1102 if (N0C && N1C) 1103 return DAG.getNode(ISD::MUL, VT, N0, N1); 1104 // canonicalize constant to RHS 1105 if (N0C && !N1C) 1106 return DAG.getNode(ISD::MUL, VT, N1, N0); 1107 // fold (mul x, 0) -> 0 1108 if (N1C && N1C->isNullValue()) 1109 return N1; 1110 // fold (mul x, -1) -> 0-x 1111 if (N1C && N1C->isAllOnesValue()) 1112 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1113 // fold (mul x, (1 << c)) -> x << c 1114 if (N1C && isPowerOf2_64(N1C->getValue())) 1115 return DAG.getNode(ISD::SHL, VT, N0, 1116 DAG.getConstant(Log2_64(N1C->getValue()), 1117 TLI.getShiftAmountTy())); 1118 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1119 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1120 // FIXME: If the input is something that is easily negated (e.g. a 1121 // single-use add), we should put the negate there. 1122 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1123 DAG.getNode(ISD::SHL, VT, N0, 1124 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1125 TLI.getShiftAmountTy()))); 1126 } 1127 1128 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1129 if (N1C && N0.getOpcode() == ISD::SHL && 1130 isa<ConstantSDNode>(N0.getOperand(1))) { 1131 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1132 AddToWorkList(C3.Val); 1133 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1134 } 1135 1136 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1137 // use. 1138 { 1139 SDOperand Sh(0,0), Y(0,0); 1140 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1141 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1142 N0.Val->hasOneUse()) { 1143 Sh = N0; Y = N1; 1144 } else if (N1.getOpcode() == ISD::SHL && 1145 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1146 Sh = N1; Y = N0; 1147 } 1148 if (Sh.Val) { 1149 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1150 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1151 } 1152 } 1153 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1154 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1155 isa<ConstantSDNode>(N0.getOperand(1))) { 1156 return DAG.getNode(ISD::ADD, VT, 1157 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1158 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1159 } 1160 1161 // reassociate mul 1162 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1163 if (RMUL.Val != 0) 1164 return RMUL; 1165 1166 return SDOperand(); 1167} 1168 1169SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1170 SDOperand N0 = N->getOperand(0); 1171 SDOperand N1 = N->getOperand(1); 1172 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1173 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1174 MVT::ValueType VT = N->getValueType(0); 1175 1176 // fold vector ops 1177 if (MVT::isVector(VT)) { 1178 SDOperand FoldedVOp = SimplifyVBinOp(N); 1179 if (FoldedVOp.Val) return FoldedVOp; 1180 } 1181 1182 // fold (sdiv c1, c2) -> c1/c2 1183 if (N0C && N1C && !N1C->isNullValue()) 1184 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1185 // fold (sdiv X, 1) -> X 1186 if (N1C && N1C->getSignExtended() == 1LL) 1187 return N0; 1188 // fold (sdiv X, -1) -> 0-X 1189 if (N1C && N1C->isAllOnesValue()) 1190 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1191 // If we know the sign bits of both operands are zero, strength reduce to a 1192 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1193 if (!MVT::isVector(VT)) { 1194 uint64_t SignBit = MVT::getIntVTSignBit(VT); 1195 if (DAG.MaskedValueIsZero(N1, SignBit) && 1196 DAG.MaskedValueIsZero(N0, SignBit)) 1197 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1198 } 1199 // fold (sdiv X, pow2) -> simple ops after legalize 1200 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1201 (isPowerOf2_64(N1C->getSignExtended()) || 1202 isPowerOf2_64(-N1C->getSignExtended()))) { 1203 // If dividing by powers of two is cheap, then don't perform the following 1204 // fold. 1205 if (TLI.isPow2DivCheap()) 1206 return SDOperand(); 1207 int64_t pow2 = N1C->getSignExtended(); 1208 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1209 unsigned lg2 = Log2_64(abs2); 1210 // Splat the sign bit into the register 1211 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1212 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1213 TLI.getShiftAmountTy())); 1214 AddToWorkList(SGN.Val); 1215 // Add (N0 < 0) ? abs2 - 1 : 0; 1216 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1217 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1218 TLI.getShiftAmountTy())); 1219 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1220 AddToWorkList(SRL.Val); 1221 AddToWorkList(ADD.Val); // Divide by pow2 1222 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1223 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1224 // If we're dividing by a positive value, we're done. Otherwise, we must 1225 // negate the result. 1226 if (pow2 > 0) 1227 return SRA; 1228 AddToWorkList(SRA.Val); 1229 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1230 } 1231 // if integer divide is expensive and we satisfy the requirements, emit an 1232 // alternate sequence. 1233 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1234 !TLI.isIntDivCheap()) { 1235 SDOperand Op = BuildSDIV(N); 1236 if (Op.Val) return Op; 1237 } 1238 1239 // undef / X -> 0 1240 if (N0.getOpcode() == ISD::UNDEF) 1241 return DAG.getConstant(0, VT); 1242 // X / undef -> undef 1243 if (N1.getOpcode() == ISD::UNDEF) 1244 return N1; 1245 1246 return SDOperand(); 1247} 1248 1249SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1250 SDOperand N0 = N->getOperand(0); 1251 SDOperand N1 = N->getOperand(1); 1252 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1253 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1254 MVT::ValueType VT = N->getValueType(0); 1255 1256 // fold vector ops 1257 if (MVT::isVector(VT)) { 1258 SDOperand FoldedVOp = SimplifyVBinOp(N); 1259 if (FoldedVOp.Val) return FoldedVOp; 1260 } 1261 1262 // fold (udiv c1, c2) -> c1/c2 1263 if (N0C && N1C && !N1C->isNullValue()) 1264 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1265 // fold (udiv x, (1 << c)) -> x >>u c 1266 if (N1C && isPowerOf2_64(N1C->getValue())) 1267 return DAG.getNode(ISD::SRL, VT, N0, 1268 DAG.getConstant(Log2_64(N1C->getValue()), 1269 TLI.getShiftAmountTy())); 1270 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1271 if (N1.getOpcode() == ISD::SHL) { 1272 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1273 if (isPowerOf2_64(SHC->getValue())) { 1274 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1275 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1276 DAG.getConstant(Log2_64(SHC->getValue()), 1277 ADDVT)); 1278 AddToWorkList(Add.Val); 1279 return DAG.getNode(ISD::SRL, VT, N0, Add); 1280 } 1281 } 1282 } 1283 // fold (udiv x, c) -> alternate 1284 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1285 SDOperand Op = BuildUDIV(N); 1286 if (Op.Val) return Op; 1287 } 1288 1289 // undef / X -> 0 1290 if (N0.getOpcode() == ISD::UNDEF) 1291 return DAG.getConstant(0, VT); 1292 // X / undef -> undef 1293 if (N1.getOpcode() == ISD::UNDEF) 1294 return N1; 1295 1296 return SDOperand(); 1297} 1298 1299SDOperand DAGCombiner::visitSREM(SDNode *N) { 1300 SDOperand N0 = N->getOperand(0); 1301 SDOperand N1 = N->getOperand(1); 1302 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1303 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1304 MVT::ValueType VT = N->getValueType(0); 1305 1306 // fold (srem c1, c2) -> c1%c2 1307 if (N0C && N1C && !N1C->isNullValue()) 1308 return DAG.getNode(ISD::SREM, VT, N0, N1); 1309 // If we know the sign bits of both operands are zero, strength reduce to a 1310 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1311 if (!MVT::isVector(VT)) { 1312 uint64_t SignBit = MVT::getIntVTSignBit(VT); 1313 if (DAG.MaskedValueIsZero(N1, SignBit) && 1314 DAG.MaskedValueIsZero(N0, SignBit)) 1315 return DAG.getNode(ISD::UREM, VT, N0, N1); 1316 } 1317 1318 // If X/C can be simplified by the division-by-constant logic, lower 1319 // X%C to the equivalent of X-X/C*C. 1320 if (N1C && !N1C->isNullValue()) { 1321 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1322 AddToWorkList(Div.Val); 1323 SDOperand OptimizedDiv = combine(Div.Val); 1324 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1325 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1326 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1327 AddToWorkList(Mul.Val); 1328 return Sub; 1329 } 1330 } 1331 1332 // undef % X -> 0 1333 if (N0.getOpcode() == ISD::UNDEF) 1334 return DAG.getConstant(0, VT); 1335 // X % undef -> undef 1336 if (N1.getOpcode() == ISD::UNDEF) 1337 return N1; 1338 1339 return SDOperand(); 1340} 1341 1342SDOperand DAGCombiner::visitUREM(SDNode *N) { 1343 SDOperand N0 = N->getOperand(0); 1344 SDOperand N1 = N->getOperand(1); 1345 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1346 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1347 MVT::ValueType VT = N->getValueType(0); 1348 1349 // fold (urem c1, c2) -> c1%c2 1350 if (N0C && N1C && !N1C->isNullValue()) 1351 return DAG.getNode(ISD::UREM, VT, N0, N1); 1352 // fold (urem x, pow2) -> (and x, pow2-1) 1353 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1354 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1355 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1356 if (N1.getOpcode() == ISD::SHL) { 1357 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1358 if (isPowerOf2_64(SHC->getValue())) { 1359 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1360 AddToWorkList(Add.Val); 1361 return DAG.getNode(ISD::AND, VT, N0, Add); 1362 } 1363 } 1364 } 1365 1366 // If X/C can be simplified by the division-by-constant logic, lower 1367 // X%C to the equivalent of X-X/C*C. 1368 if (N1C && !N1C->isNullValue()) { 1369 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1370 SDOperand OptimizedDiv = combine(Div.Val); 1371 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1372 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1373 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1374 AddToWorkList(Mul.Val); 1375 return Sub; 1376 } 1377 } 1378 1379 // undef % X -> 0 1380 if (N0.getOpcode() == ISD::UNDEF) 1381 return DAG.getConstant(0, VT); 1382 // X % undef -> undef 1383 if (N1.getOpcode() == ISD::UNDEF) 1384 return N1; 1385 1386 return SDOperand(); 1387} 1388 1389SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1390 SDOperand N0 = N->getOperand(0); 1391 SDOperand N1 = N->getOperand(1); 1392 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1393 MVT::ValueType VT = N->getValueType(0); 1394 1395 // fold (mulhs x, 0) -> 0 1396 if (N1C && N1C->isNullValue()) 1397 return N1; 1398 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1399 if (N1C && N1C->getValue() == 1) 1400 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1401 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1402 TLI.getShiftAmountTy())); 1403 // fold (mulhs x, undef) -> 0 1404 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1405 return DAG.getConstant(0, VT); 1406 1407 return SDOperand(); 1408} 1409 1410SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1411 SDOperand N0 = N->getOperand(0); 1412 SDOperand N1 = N->getOperand(1); 1413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1414 MVT::ValueType VT = N->getValueType(0); 1415 1416 // fold (mulhu x, 0) -> 0 1417 if (N1C && N1C->isNullValue()) 1418 return N1; 1419 // fold (mulhu x, 1) -> 0 1420 if (N1C && N1C->getValue() == 1) 1421 return DAG.getConstant(0, N0.getValueType()); 1422 // fold (mulhu x, undef) -> 0 1423 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1424 return DAG.getConstant(0, VT); 1425 1426 return SDOperand(); 1427} 1428 1429/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1430/// compute two values. LoOp and HiOp give the opcodes for the two computations 1431/// that are being performed. Return true if a simplification was made. 1432/// 1433SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1434 unsigned HiOp) { 1435 // If the high half is not needed, just compute the low half. 1436 bool HiExists = N->hasAnyUseOfValue(1); 1437 if (!HiExists && 1438 (!AfterLegalize || 1439 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1440 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1441 N->getNumOperands()); 1442 return CombineTo(N, Res, Res); 1443 } 1444 1445 // If the low half is not needed, just compute the high half. 1446 bool LoExists = N->hasAnyUseOfValue(0); 1447 if (!LoExists && 1448 (!AfterLegalize || 1449 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1450 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1451 N->getNumOperands()); 1452 return CombineTo(N, Res, Res); 1453 } 1454 1455 // If both halves are used, return as it is. 1456 if (LoExists && HiExists) 1457 return SDOperand(); 1458 1459 // If the two computed results can be simplified separately, separate them. 1460 if (LoExists) { 1461 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1462 N->op_begin(), N->getNumOperands()); 1463 AddToWorkList(Lo.Val); 1464 SDOperand LoOpt = combine(Lo.Val); 1465 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1466 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) 1467 return CombineTo(N, LoOpt, LoOpt); 1468 } 1469 1470 if (HiExists) { 1471 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1472 N->op_begin(), N->getNumOperands()); 1473 AddToWorkList(Hi.Val); 1474 SDOperand HiOpt = combine(Hi.Val); 1475 if (HiOpt.Val && HiOpt != Hi && 1476 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) 1477 return CombineTo(N, HiOpt, HiOpt); 1478 } 1479 return SDOperand(); 1480} 1481 1482SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1483 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1484 if (Res.Val) return Res; 1485 1486 return SDOperand(); 1487} 1488 1489SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1490 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1491 if (Res.Val) return Res; 1492 1493 return SDOperand(); 1494} 1495 1496SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1497 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1498 if (Res.Val) return Res; 1499 1500 return SDOperand(); 1501} 1502 1503SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1504 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1505 if (Res.Val) return Res; 1506 1507 return SDOperand(); 1508} 1509 1510/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1511/// two operands of the same opcode, try to simplify it. 1512SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1513 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1514 MVT::ValueType VT = N0.getValueType(); 1515 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1516 1517 // For each of OP in AND/OR/XOR: 1518 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1519 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1520 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1521 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1522 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1523 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1524 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1525 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1526 N0.getOperand(0).getValueType(), 1527 N0.getOperand(0), N1.getOperand(0)); 1528 AddToWorkList(ORNode.Val); 1529 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1530 } 1531 1532 // For each of OP in SHL/SRL/SRA/AND... 1533 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1534 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1535 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1536 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1537 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1538 N0.getOperand(1) == N1.getOperand(1)) { 1539 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1540 N0.getOperand(0).getValueType(), 1541 N0.getOperand(0), N1.getOperand(0)); 1542 AddToWorkList(ORNode.Val); 1543 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1544 } 1545 1546 return SDOperand(); 1547} 1548 1549SDOperand DAGCombiner::visitAND(SDNode *N) { 1550 SDOperand N0 = N->getOperand(0); 1551 SDOperand N1 = N->getOperand(1); 1552 SDOperand LL, LR, RL, RR, CC0, CC1; 1553 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1554 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1555 MVT::ValueType VT = N1.getValueType(); 1556 1557 // fold vector ops 1558 if (MVT::isVector(VT)) { 1559 SDOperand FoldedVOp = SimplifyVBinOp(N); 1560 if (FoldedVOp.Val) return FoldedVOp; 1561 } 1562 1563 // fold (and x, undef) -> 0 1564 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1565 return DAG.getConstant(0, VT); 1566 // fold (and c1, c2) -> c1&c2 1567 if (N0C && N1C) 1568 return DAG.getNode(ISD::AND, VT, N0, N1); 1569 // canonicalize constant to RHS 1570 if (N0C && !N1C) 1571 return DAG.getNode(ISD::AND, VT, N1, N0); 1572 // fold (and x, -1) -> x 1573 if (N1C && N1C->isAllOnesValue()) 1574 return N0; 1575 // if (and x, c) is known to be zero, return 0 1576 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1577 return DAG.getConstant(0, VT); 1578 // reassociate and 1579 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1580 if (RAND.Val != 0) 1581 return RAND; 1582 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1583 if (N1C && N0.getOpcode() == ISD::OR) 1584 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1585 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1586 return N1; 1587 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1588 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1589 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1590 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1591 ~N1C->getValue() & InMask)) { 1592 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1593 N0.getOperand(0)); 1594 1595 // Replace uses of the AND with uses of the Zero extend node. 1596 CombineTo(N, Zext); 1597 1598 // We actually want to replace all uses of the any_extend with the 1599 // zero_extend, to avoid duplicating things. This will later cause this 1600 // AND to be folded. 1601 CombineTo(N0.Val, Zext); 1602 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1603 } 1604 } 1605 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1606 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1607 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1608 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1609 1610 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1611 MVT::isInteger(LL.getValueType())) { 1612 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1613 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1614 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1615 AddToWorkList(ORNode.Val); 1616 return DAG.getSetCC(VT, ORNode, LR, Op1); 1617 } 1618 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1619 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1620 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1621 AddToWorkList(ANDNode.Val); 1622 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1623 } 1624 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1625 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1626 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1627 AddToWorkList(ORNode.Val); 1628 return DAG.getSetCC(VT, ORNode, LR, Op1); 1629 } 1630 } 1631 // canonicalize equivalent to ll == rl 1632 if (LL == RR && LR == RL) { 1633 Op1 = ISD::getSetCCSwappedOperands(Op1); 1634 std::swap(RL, RR); 1635 } 1636 if (LL == RL && LR == RR) { 1637 bool isInteger = MVT::isInteger(LL.getValueType()); 1638 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1639 if (Result != ISD::SETCC_INVALID) 1640 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1641 } 1642 } 1643 1644 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1645 if (N0.getOpcode() == N1.getOpcode()) { 1646 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1647 if (Tmp.Val) return Tmp; 1648 } 1649 1650 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1651 // fold (and (sra)) -> (and (srl)) when possible. 1652 if (!MVT::isVector(VT) && 1653 SimplifyDemandedBits(SDOperand(N, 0))) 1654 return SDOperand(N, 0); 1655 // fold (zext_inreg (extload x)) -> (zextload x) 1656 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1657 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1658 MVT::ValueType EVT = LN0->getLoadedVT(); 1659 // If we zero all the possible extended bits, then we can turn this into 1660 // a zextload if we are running before legalize or the operation is legal. 1661 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1662 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1663 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1664 LN0->getBasePtr(), LN0->getSrcValue(), 1665 LN0->getSrcValueOffset(), EVT, 1666 LN0->isVolatile(), 1667 LN0->getAlignment()); 1668 AddToWorkList(N); 1669 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1670 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1671 } 1672 } 1673 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1674 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1675 N0.hasOneUse()) { 1676 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1677 MVT::ValueType EVT = LN0->getLoadedVT(); 1678 // If we zero all the possible extended bits, then we can turn this into 1679 // a zextload if we are running before legalize or the operation is legal. 1680 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1681 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1682 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1683 LN0->getBasePtr(), LN0->getSrcValue(), 1684 LN0->getSrcValueOffset(), EVT, 1685 LN0->isVolatile(), 1686 LN0->getAlignment()); 1687 AddToWorkList(N); 1688 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1689 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1690 } 1691 } 1692 1693 // fold (and (load x), 255) -> (zextload x, i8) 1694 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1695 if (N1C && N0.getOpcode() == ISD::LOAD) { 1696 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1697 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1698 LN0->isUnindexed() && N0.hasOneUse()) { 1699 MVT::ValueType EVT, LoadedVT; 1700 if (N1C->getValue() == 255) 1701 EVT = MVT::i8; 1702 else if (N1C->getValue() == 65535) 1703 EVT = MVT::i16; 1704 else if (N1C->getValue() == ~0U) 1705 EVT = MVT::i32; 1706 else 1707 EVT = MVT::Other; 1708 1709 LoadedVT = LN0->getLoadedVT(); 1710 if (EVT != MVT::Other && LoadedVT > EVT && 1711 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1712 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1713 // For big endian targets, we need to add an offset to the pointer to 1714 // load the correct bytes. For little endian systems, we merely need to 1715 // read fewer bytes from the same pointer. 1716 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1717 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1718 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1719 unsigned Alignment = LN0->getAlignment(); 1720 SDOperand NewPtr = LN0->getBasePtr(); 1721 if (!TLI.isLittleEndian()) { 1722 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1723 DAG.getConstant(PtrOff, PtrType)); 1724 Alignment = MinAlign(Alignment, PtrOff); 1725 } 1726 AddToWorkList(NewPtr.Val); 1727 SDOperand Load = 1728 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1729 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1730 LN0->isVolatile(), Alignment); 1731 AddToWorkList(N); 1732 CombineTo(N0.Val, Load, Load.getValue(1)); 1733 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1734 } 1735 } 1736 } 1737 1738 return SDOperand(); 1739} 1740 1741SDOperand DAGCombiner::visitOR(SDNode *N) { 1742 SDOperand N0 = N->getOperand(0); 1743 SDOperand N1 = N->getOperand(1); 1744 SDOperand LL, LR, RL, RR, CC0, CC1; 1745 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1746 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1747 MVT::ValueType VT = N1.getValueType(); 1748 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1749 1750 // fold vector ops 1751 if (MVT::isVector(VT)) { 1752 SDOperand FoldedVOp = SimplifyVBinOp(N); 1753 if (FoldedVOp.Val) return FoldedVOp; 1754 } 1755 1756 // fold (or x, undef) -> -1 1757 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1758 return DAG.getConstant(~0ULL, VT); 1759 // fold (or c1, c2) -> c1|c2 1760 if (N0C && N1C) 1761 return DAG.getNode(ISD::OR, VT, N0, N1); 1762 // canonicalize constant to RHS 1763 if (N0C && !N1C) 1764 return DAG.getNode(ISD::OR, VT, N1, N0); 1765 // fold (or x, 0) -> x 1766 if (N1C && N1C->isNullValue()) 1767 return N0; 1768 // fold (or x, -1) -> -1 1769 if (N1C && N1C->isAllOnesValue()) 1770 return N1; 1771 // fold (or x, c) -> c iff (x & ~c) == 0 1772 if (N1C && 1773 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1774 return N1; 1775 // reassociate or 1776 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1777 if (ROR.Val != 0) 1778 return ROR; 1779 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1780 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1781 isa<ConstantSDNode>(N0.getOperand(1))) { 1782 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1783 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1784 N1), 1785 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1786 } 1787 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1788 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1789 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1790 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1791 1792 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1793 MVT::isInteger(LL.getValueType())) { 1794 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1795 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1796 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1797 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1798 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1799 AddToWorkList(ORNode.Val); 1800 return DAG.getSetCC(VT, ORNode, LR, Op1); 1801 } 1802 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1803 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1804 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1805 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1806 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1807 AddToWorkList(ANDNode.Val); 1808 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1809 } 1810 } 1811 // canonicalize equivalent to ll == rl 1812 if (LL == RR && LR == RL) { 1813 Op1 = ISD::getSetCCSwappedOperands(Op1); 1814 std::swap(RL, RR); 1815 } 1816 if (LL == RL && LR == RR) { 1817 bool isInteger = MVT::isInteger(LL.getValueType()); 1818 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1819 if (Result != ISD::SETCC_INVALID) 1820 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1821 } 1822 } 1823 1824 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1825 if (N0.getOpcode() == N1.getOpcode()) { 1826 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1827 if (Tmp.Val) return Tmp; 1828 } 1829 1830 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1831 if (N0.getOpcode() == ISD::AND && 1832 N1.getOpcode() == ISD::AND && 1833 N0.getOperand(1).getOpcode() == ISD::Constant && 1834 N1.getOperand(1).getOpcode() == ISD::Constant && 1835 // Don't increase # computations. 1836 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1837 // We can only do this xform if we know that bits from X that are set in C2 1838 // but not in C1 are already zero. Likewise for Y. 1839 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1840 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1841 1842 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1843 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1844 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1845 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1846 } 1847 } 1848 1849 1850 // See if this is some rotate idiom. 1851 if (SDNode *Rot = MatchRotate(N0, N1)) 1852 return SDOperand(Rot, 0); 1853 1854 return SDOperand(); 1855} 1856 1857 1858/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1859static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1860 if (Op.getOpcode() == ISD::AND) { 1861 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1862 Mask = Op.getOperand(1); 1863 Op = Op.getOperand(0); 1864 } else { 1865 return false; 1866 } 1867 } 1868 1869 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1870 Shift = Op; 1871 return true; 1872 } 1873 return false; 1874} 1875 1876 1877// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1878// idioms for rotate, and if the target supports rotation instructions, generate 1879// a rot[lr]. 1880SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1881 // Must be a legal type. Expanded an promoted things won't work with rotates. 1882 MVT::ValueType VT = LHS.getValueType(); 1883 if (!TLI.isTypeLegal(VT)) return 0; 1884 1885 // The target must have at least one rotate flavor. 1886 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1887 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1888 if (!HasROTL && !HasROTR) return 0; 1889 1890 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1891 SDOperand LHSShift; // The shift. 1892 SDOperand LHSMask; // AND value if any. 1893 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1894 return 0; // Not part of a rotate. 1895 1896 SDOperand RHSShift; // The shift. 1897 SDOperand RHSMask; // AND value if any. 1898 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1899 return 0; // Not part of a rotate. 1900 1901 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1902 return 0; // Not shifting the same value. 1903 1904 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1905 return 0; // Shifts must disagree. 1906 1907 // Canonicalize shl to left side in a shl/srl pair. 1908 if (RHSShift.getOpcode() == ISD::SHL) { 1909 std::swap(LHS, RHS); 1910 std::swap(LHSShift, RHSShift); 1911 std::swap(LHSMask , RHSMask ); 1912 } 1913 1914 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1915 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1916 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1917 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1918 1919 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1920 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1921 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1922 RHSShiftAmt.getOpcode() == ISD::Constant) { 1923 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1924 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1925 if ((LShVal + RShVal) != OpSizeInBits) 1926 return 0; 1927 1928 SDOperand Rot; 1929 if (HasROTL) 1930 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1931 else 1932 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1933 1934 // If there is an AND of either shifted operand, apply it to the result. 1935 if (LHSMask.Val || RHSMask.Val) { 1936 uint64_t Mask = MVT::getIntVTBitMask(VT); 1937 1938 if (LHSMask.Val) { 1939 uint64_t RHSBits = (1ULL << LShVal)-1; 1940 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1941 } 1942 if (RHSMask.Val) { 1943 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1944 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1945 } 1946 1947 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1948 } 1949 1950 return Rot.Val; 1951 } 1952 1953 // If there is a mask here, and we have a variable shift, we can't be sure 1954 // that we're masking out the right stuff. 1955 if (LHSMask.Val || RHSMask.Val) 1956 return 0; 1957 1958 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1959 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1960 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1961 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1962 if (ConstantSDNode *SUBC = 1963 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1964 if (SUBC->getValue() == OpSizeInBits) 1965 if (HasROTL) 1966 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1967 else 1968 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1969 } 1970 } 1971 1972 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1973 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1974 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1975 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1976 if (ConstantSDNode *SUBC = 1977 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1978 if (SUBC->getValue() == OpSizeInBits) 1979 if (HasROTL) 1980 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1981 else 1982 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1983 } 1984 } 1985 1986 // Look for sign/zext/any-extended cases: 1987 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1988 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1989 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1990 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1991 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1992 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1993 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1994 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1995 if (RExtOp0.getOpcode() == ISD::SUB && 1996 RExtOp0.getOperand(1) == LExtOp0) { 1997 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1998 // (rotr x, y) 1999 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2000 // (rotl x, (sub 32, y)) 2001 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2002 if (SUBC->getValue() == OpSizeInBits) { 2003 if (HasROTL) 2004 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2005 else 2006 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2007 } 2008 } 2009 } else if (LExtOp0.getOpcode() == ISD::SUB && 2010 RExtOp0 == LExtOp0.getOperand(1)) { 2011 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2012 // (rotl x, y) 2013 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2014 // (rotr x, (sub 32, y)) 2015 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2016 if (SUBC->getValue() == OpSizeInBits) { 2017 if (HasROTL) 2018 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2019 else 2020 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2021 } 2022 } 2023 } 2024 } 2025 2026 return 0; 2027} 2028 2029 2030SDOperand DAGCombiner::visitXOR(SDNode *N) { 2031 SDOperand N0 = N->getOperand(0); 2032 SDOperand N1 = N->getOperand(1); 2033 SDOperand LHS, RHS, CC; 2034 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2035 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2036 MVT::ValueType VT = N0.getValueType(); 2037 2038 // fold vector ops 2039 if (MVT::isVector(VT)) { 2040 SDOperand FoldedVOp = SimplifyVBinOp(N); 2041 if (FoldedVOp.Val) return FoldedVOp; 2042 } 2043 2044 // fold (xor x, undef) -> undef 2045 if (N0.getOpcode() == ISD::UNDEF) 2046 return N0; 2047 if (N1.getOpcode() == ISD::UNDEF) 2048 return N1; 2049 // fold (xor c1, c2) -> c1^c2 2050 if (N0C && N1C) 2051 return DAG.getNode(ISD::XOR, VT, N0, N1); 2052 // canonicalize constant to RHS 2053 if (N0C && !N1C) 2054 return DAG.getNode(ISD::XOR, VT, N1, N0); 2055 // fold (xor x, 0) -> x 2056 if (N1C && N1C->isNullValue()) 2057 return N0; 2058 // reassociate xor 2059 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2060 if (RXOR.Val != 0) 2061 return RXOR; 2062 // fold !(x cc y) -> (x !cc y) 2063 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2064 bool isInt = MVT::isInteger(LHS.getValueType()); 2065 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2066 isInt); 2067 if (N0.getOpcode() == ISD::SETCC) 2068 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2069 if (N0.getOpcode() == ISD::SELECT_CC) 2070 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2071 assert(0 && "Unhandled SetCC Equivalent!"); 2072 abort(); 2073 } 2074 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2075 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2076 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2077 SDOperand V = N0.getOperand(0); 2078 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2079 DAG.getConstant(1, V.getValueType())); 2080 AddToWorkList(V.Val); 2081 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2082 } 2083 2084 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2085 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2086 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2087 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2088 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2089 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2090 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2091 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2092 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2093 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2094 } 2095 } 2096 // fold !(x or y) -> (!x and !y) iff x or y are constants 2097 if (N1C && N1C->isAllOnesValue() && 2098 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2099 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2100 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2101 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2102 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2103 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2104 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2105 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2106 } 2107 } 2108 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2109 if (N1C && N0.getOpcode() == ISD::XOR) { 2110 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2111 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2112 if (N00C) 2113 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2114 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2115 if (N01C) 2116 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2117 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2118 } 2119 // fold (xor x, x) -> 0 2120 if (N0 == N1) { 2121 if (!MVT::isVector(VT)) { 2122 return DAG.getConstant(0, VT); 2123 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2124 // Produce a vector of zeros. 2125 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2126 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2127 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2128 } 2129 } 2130 2131 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2132 if (N0.getOpcode() == N1.getOpcode()) { 2133 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2134 if (Tmp.Val) return Tmp; 2135 } 2136 2137 // Simplify the expression using non-local knowledge. 2138 if (!MVT::isVector(VT) && 2139 SimplifyDemandedBits(SDOperand(N, 0))) 2140 return SDOperand(N, 0); 2141 2142 return SDOperand(); 2143} 2144 2145/// visitShiftByConstant - Handle transforms common to the three shifts, when 2146/// the shift amount is a constant. 2147SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2148 SDNode *LHS = N->getOperand(0).Val; 2149 if (!LHS->hasOneUse()) return SDOperand(); 2150 2151 // We want to pull some binops through shifts, so that we have (and (shift)) 2152 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2153 // thing happens with address calculations, so it's important to canonicalize 2154 // it. 2155 bool HighBitSet = false; // Can we transform this if the high bit is set? 2156 2157 switch (LHS->getOpcode()) { 2158 default: return SDOperand(); 2159 case ISD::OR: 2160 case ISD::XOR: 2161 HighBitSet = false; // We can only transform sra if the high bit is clear. 2162 break; 2163 case ISD::AND: 2164 HighBitSet = true; // We can only transform sra if the high bit is set. 2165 break; 2166 case ISD::ADD: 2167 if (N->getOpcode() != ISD::SHL) 2168 return SDOperand(); // only shl(add) not sr[al](add). 2169 HighBitSet = false; // We can only transform sra if the high bit is clear. 2170 break; 2171 } 2172 2173 // We require the RHS of the binop to be a constant as well. 2174 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2175 if (!BinOpCst) return SDOperand(); 2176 2177 2178 // FIXME: disable this for unless the input to the binop is a shift by a 2179 // constant. If it is not a shift, it pessimizes some common cases like: 2180 // 2181 //void foo(int *X, int i) { X[i & 1235] = 1; } 2182 //int bar(int *X, int i) { return X[i & 255]; } 2183 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2184 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2185 BinOpLHSVal->getOpcode() != ISD::SRA && 2186 BinOpLHSVal->getOpcode() != ISD::SRL) || 2187 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2188 return SDOperand(); 2189 2190 MVT::ValueType VT = N->getValueType(0); 2191 2192 // If this is a signed shift right, and the high bit is modified 2193 // by the logical operation, do not perform the transformation. 2194 // The highBitSet boolean indicates the value of the high bit of 2195 // the constant which would cause it to be modified for this 2196 // operation. 2197 if (N->getOpcode() == ISD::SRA) { 2198 uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1; 2199 if ((bool)BinOpRHSSign != HighBitSet) 2200 return SDOperand(); 2201 } 2202 2203 // Fold the constants, shifting the binop RHS by the shift amount. 2204 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2205 LHS->getOperand(1), N->getOperand(1)); 2206 2207 // Create the new shift. 2208 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2209 N->getOperand(1)); 2210 2211 // Create the new binop. 2212 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2213} 2214 2215 2216SDOperand DAGCombiner::visitSHL(SDNode *N) { 2217 SDOperand N0 = N->getOperand(0); 2218 SDOperand N1 = N->getOperand(1); 2219 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2220 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2221 MVT::ValueType VT = N0.getValueType(); 2222 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2223 2224 // fold (shl c1, c2) -> c1<<c2 2225 if (N0C && N1C) 2226 return DAG.getNode(ISD::SHL, VT, N0, N1); 2227 // fold (shl 0, x) -> 0 2228 if (N0C && N0C->isNullValue()) 2229 return N0; 2230 // fold (shl x, c >= size(x)) -> undef 2231 if (N1C && N1C->getValue() >= OpSizeInBits) 2232 return DAG.getNode(ISD::UNDEF, VT); 2233 // fold (shl x, 0) -> x 2234 if (N1C && N1C->isNullValue()) 2235 return N0; 2236 // if (shl x, c) is known to be zero, return 0 2237 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2238 return DAG.getConstant(0, VT); 2239 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2240 return SDOperand(N, 0); 2241 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2242 if (N1C && N0.getOpcode() == ISD::SHL && 2243 N0.getOperand(1).getOpcode() == ISD::Constant) { 2244 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2245 uint64_t c2 = N1C->getValue(); 2246 if (c1 + c2 > OpSizeInBits) 2247 return DAG.getConstant(0, VT); 2248 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2249 DAG.getConstant(c1 + c2, N1.getValueType())); 2250 } 2251 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2252 // (srl (and x, -1 << c1), c1-c2) 2253 if (N1C && N0.getOpcode() == ISD::SRL && 2254 N0.getOperand(1).getOpcode() == ISD::Constant) { 2255 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2256 uint64_t c2 = N1C->getValue(); 2257 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2258 DAG.getConstant(~0ULL << c1, VT)); 2259 if (c2 > c1) 2260 return DAG.getNode(ISD::SHL, VT, Mask, 2261 DAG.getConstant(c2-c1, N1.getValueType())); 2262 else 2263 return DAG.getNode(ISD::SRL, VT, Mask, 2264 DAG.getConstant(c1-c2, N1.getValueType())); 2265 } 2266 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2267 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2268 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2269 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2270 2271 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2272} 2273 2274SDOperand DAGCombiner::visitSRA(SDNode *N) { 2275 SDOperand N0 = N->getOperand(0); 2276 SDOperand N1 = N->getOperand(1); 2277 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2278 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2279 MVT::ValueType VT = N0.getValueType(); 2280 2281 // fold (sra c1, c2) -> c1>>c2 2282 if (N0C && N1C) 2283 return DAG.getNode(ISD::SRA, VT, N0, N1); 2284 // fold (sra 0, x) -> 0 2285 if (N0C && N0C->isNullValue()) 2286 return N0; 2287 // fold (sra -1, x) -> -1 2288 if (N0C && N0C->isAllOnesValue()) 2289 return N0; 2290 // fold (sra x, c >= size(x)) -> undef 2291 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2292 return DAG.getNode(ISD::UNDEF, VT); 2293 // fold (sra x, 0) -> x 2294 if (N1C && N1C->isNullValue()) 2295 return N0; 2296 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2297 // sext_inreg. 2298 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2299 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2300 MVT::ValueType EVT; 2301 switch (LowBits) { 2302 default: EVT = MVT::Other; break; 2303 case 1: EVT = MVT::i1; break; 2304 case 8: EVT = MVT::i8; break; 2305 case 16: EVT = MVT::i16; break; 2306 case 32: EVT = MVT::i32; break; 2307 } 2308 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2309 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2310 DAG.getValueType(EVT)); 2311 } 2312 2313 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2314 if (N1C && N0.getOpcode() == ISD::SRA) { 2315 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2316 unsigned Sum = N1C->getValue() + C1->getValue(); 2317 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2318 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2319 DAG.getConstant(Sum, N1C->getValueType(0))); 2320 } 2321 } 2322 2323 // Simplify, based on bits shifted out of the LHS. 2324 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2325 return SDOperand(N, 0); 2326 2327 2328 // If the sign bit is known to be zero, switch this to a SRL. 2329 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2330 return DAG.getNode(ISD::SRL, VT, N0, N1); 2331 2332 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2333} 2334 2335SDOperand DAGCombiner::visitSRL(SDNode *N) { 2336 SDOperand N0 = N->getOperand(0); 2337 SDOperand N1 = N->getOperand(1); 2338 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2339 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2340 MVT::ValueType VT = N0.getValueType(); 2341 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2342 2343 // fold (srl c1, c2) -> c1 >>u c2 2344 if (N0C && N1C) 2345 return DAG.getNode(ISD::SRL, VT, N0, N1); 2346 // fold (srl 0, x) -> 0 2347 if (N0C && N0C->isNullValue()) 2348 return N0; 2349 // fold (srl x, c >= size(x)) -> undef 2350 if (N1C && N1C->getValue() >= OpSizeInBits) 2351 return DAG.getNode(ISD::UNDEF, VT); 2352 // fold (srl x, 0) -> x 2353 if (N1C && N1C->isNullValue()) 2354 return N0; 2355 // if (srl x, c) is known to be zero, return 0 2356 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2357 return DAG.getConstant(0, VT); 2358 2359 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2360 if (N1C && N0.getOpcode() == ISD::SRL && 2361 N0.getOperand(1).getOpcode() == ISD::Constant) { 2362 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2363 uint64_t c2 = N1C->getValue(); 2364 if (c1 + c2 > OpSizeInBits) 2365 return DAG.getConstant(0, VT); 2366 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2367 DAG.getConstant(c1 + c2, N1.getValueType())); 2368 } 2369 2370 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2371 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2372 // Shifting in all undef bits? 2373 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2374 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2375 return DAG.getNode(ISD::UNDEF, VT); 2376 2377 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2378 AddToWorkList(SmallShift.Val); 2379 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2380 } 2381 2382 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2383 // bit, which is unmodified by sra. 2384 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2385 if (N0.getOpcode() == ISD::SRA) 2386 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2387 } 2388 2389 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2390 if (N1C && N0.getOpcode() == ISD::CTLZ && 2391 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2392 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2393 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2394 2395 // If any of the input bits are KnownOne, then the input couldn't be all 2396 // zeros, thus the result of the srl will always be zero. 2397 if (KnownOne) return DAG.getConstant(0, VT); 2398 2399 // If all of the bits input the to ctlz node are known to be zero, then 2400 // the result of the ctlz is "32" and the result of the shift is one. 2401 uint64_t UnknownBits = ~KnownZero & Mask; 2402 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2403 2404 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2405 if ((UnknownBits & (UnknownBits-1)) == 0) { 2406 // Okay, we know that only that the single bit specified by UnknownBits 2407 // could be set on input to the CTLZ node. If this bit is set, the SRL 2408 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2409 // to an SRL,XOR pair, which is likely to simplify more. 2410 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2411 SDOperand Op = N0.getOperand(0); 2412 if (ShAmt) { 2413 Op = DAG.getNode(ISD::SRL, VT, Op, 2414 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2415 AddToWorkList(Op.Val); 2416 } 2417 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2418 } 2419 } 2420 2421 // fold operands of srl based on knowledge that the low bits are not 2422 // demanded. 2423 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2424 return SDOperand(N, 0); 2425 2426 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2427} 2428 2429SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2430 SDOperand N0 = N->getOperand(0); 2431 MVT::ValueType VT = N->getValueType(0); 2432 2433 // fold (ctlz c1) -> c2 2434 if (isa<ConstantSDNode>(N0)) 2435 return DAG.getNode(ISD::CTLZ, VT, N0); 2436 return SDOperand(); 2437} 2438 2439SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2440 SDOperand N0 = N->getOperand(0); 2441 MVT::ValueType VT = N->getValueType(0); 2442 2443 // fold (cttz c1) -> c2 2444 if (isa<ConstantSDNode>(N0)) 2445 return DAG.getNode(ISD::CTTZ, VT, N0); 2446 return SDOperand(); 2447} 2448 2449SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2450 SDOperand N0 = N->getOperand(0); 2451 MVT::ValueType VT = N->getValueType(0); 2452 2453 // fold (ctpop c1) -> c2 2454 if (isa<ConstantSDNode>(N0)) 2455 return DAG.getNode(ISD::CTPOP, VT, N0); 2456 return SDOperand(); 2457} 2458 2459SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2460 SDOperand N0 = N->getOperand(0); 2461 SDOperand N1 = N->getOperand(1); 2462 SDOperand N2 = N->getOperand(2); 2463 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2464 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2465 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2466 MVT::ValueType VT = N->getValueType(0); 2467 MVT::ValueType VT0 = N0.getValueType(); 2468 2469 // fold select C, X, X -> X 2470 if (N1 == N2) 2471 return N1; 2472 // fold select true, X, Y -> X 2473 if (N0C && !N0C->isNullValue()) 2474 return N1; 2475 // fold select false, X, Y -> Y 2476 if (N0C && N0C->isNullValue()) 2477 return N2; 2478 // fold select C, 1, X -> C | X 2479 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2480 return DAG.getNode(ISD::OR, VT, N0, N2); 2481 // fold select C, 0, 1 -> ~C 2482 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2483 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2484 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2485 if (VT == VT0) 2486 return XORNode; 2487 AddToWorkList(XORNode.Val); 2488 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2489 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2490 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2491 } 2492 // fold select C, 0, X -> ~C & X 2493 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2494 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2495 AddToWorkList(XORNode.Val); 2496 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2497 } 2498 // fold select C, X, 1 -> ~C | X 2499 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) { 2500 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2501 AddToWorkList(XORNode.Val); 2502 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2503 } 2504 // fold select C, X, 0 -> C & X 2505 // FIXME: this should check for C type == X type, not i1? 2506 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2507 return DAG.getNode(ISD::AND, VT, N0, N1); 2508 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2509 if (MVT::i1 == VT && N0 == N1) 2510 return DAG.getNode(ISD::OR, VT, N0, N2); 2511 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2512 if (MVT::i1 == VT && N0 == N2) 2513 return DAG.getNode(ISD::AND, VT, N0, N1); 2514 2515 // If we can fold this based on the true/false value, do so. 2516 if (SimplifySelectOps(N, N1, N2)) 2517 return SDOperand(N, 0); // Don't revisit N. 2518 2519 // fold selects based on a setcc into other things, such as min/max/abs 2520 if (N0.getOpcode() == ISD::SETCC) 2521 // FIXME: 2522 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2523 // having to say they don't support SELECT_CC on every type the DAG knows 2524 // about, since there is no way to mark an opcode illegal at all value types 2525 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2526 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2527 N1, N2, N0.getOperand(2)); 2528 else 2529 return SimplifySelect(N0, N1, N2); 2530 return SDOperand(); 2531} 2532 2533SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2534 SDOperand N0 = N->getOperand(0); 2535 SDOperand N1 = N->getOperand(1); 2536 SDOperand N2 = N->getOperand(2); 2537 SDOperand N3 = N->getOperand(3); 2538 SDOperand N4 = N->getOperand(4); 2539 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2540 2541 // fold select_cc lhs, rhs, x, x, cc -> x 2542 if (N2 == N3) 2543 return N2; 2544 2545 // Determine if the condition we're dealing with is constant 2546 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2547 if (SCC.Val) AddToWorkList(SCC.Val); 2548 2549 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2550 if (SCCC->getValue()) 2551 return N2; // cond always true -> true val 2552 else 2553 return N3; // cond always false -> false val 2554 } 2555 2556 // Fold to a simpler select_cc 2557 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2558 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2559 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2560 SCC.getOperand(2)); 2561 2562 // If we can fold this based on the true/false value, do so. 2563 if (SimplifySelectOps(N, N2, N3)) 2564 return SDOperand(N, 0); // Don't revisit N. 2565 2566 // fold select_cc into other things, such as min/max/abs 2567 return SimplifySelectCC(N0, N1, N2, N3, CC); 2568} 2569 2570SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2571 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2572 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2573} 2574 2575// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2576// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2577// transformation. Returns true if extension are possible and the above 2578// mentioned transformation is profitable. 2579static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2580 unsigned ExtOpc, 2581 SmallVector<SDNode*, 4> &ExtendNodes, 2582 TargetLowering &TLI) { 2583 bool HasCopyToRegUses = false; 2584 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2585 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2586 UI != UE; ++UI) { 2587 SDNode *User = *UI; 2588 if (User == N) 2589 continue; 2590 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2591 if (User->getOpcode() == ISD::SETCC) { 2592 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2593 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2594 // Sign bits will be lost after a zext. 2595 return false; 2596 bool Add = false; 2597 for (unsigned i = 0; i != 2; ++i) { 2598 SDOperand UseOp = User->getOperand(i); 2599 if (UseOp == N0) 2600 continue; 2601 if (!isa<ConstantSDNode>(UseOp)) 2602 return false; 2603 Add = true; 2604 } 2605 if (Add) 2606 ExtendNodes.push_back(User); 2607 } else { 2608 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2609 SDOperand UseOp = User->getOperand(i); 2610 if (UseOp == N0) { 2611 // If truncate from extended type to original load type is free 2612 // on this target, then it's ok to extend a CopyToReg. 2613 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2614 HasCopyToRegUses = true; 2615 else 2616 return false; 2617 } 2618 } 2619 } 2620 } 2621 2622 if (HasCopyToRegUses) { 2623 bool BothLiveOut = false; 2624 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2625 UI != UE; ++UI) { 2626 SDNode *User = *UI; 2627 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2628 SDOperand UseOp = User->getOperand(i); 2629 if (UseOp.Val == N && UseOp.ResNo == 0) { 2630 BothLiveOut = true; 2631 break; 2632 } 2633 } 2634 } 2635 if (BothLiveOut) 2636 // Both unextended and extended values are live out. There had better be 2637 // good a reason for the transformation. 2638 return ExtendNodes.size(); 2639 } 2640 return true; 2641} 2642 2643SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2644 SDOperand N0 = N->getOperand(0); 2645 MVT::ValueType VT = N->getValueType(0); 2646 2647 // fold (sext c1) -> c1 2648 if (isa<ConstantSDNode>(N0)) 2649 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2650 2651 // fold (sext (sext x)) -> (sext x) 2652 // fold (sext (aext x)) -> (sext x) 2653 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2654 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2655 2656 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2657 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2658 if (N0.getOpcode() == ISD::TRUNCATE) { 2659 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2660 if (NarrowLoad.Val) { 2661 if (NarrowLoad.Val != N0.Val) 2662 CombineTo(N0.Val, NarrowLoad); 2663 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2664 } 2665 } 2666 2667 // See if the value being truncated is already sign extended. If so, just 2668 // eliminate the trunc/sext pair. 2669 if (N0.getOpcode() == ISD::TRUNCATE) { 2670 SDOperand Op = N0.getOperand(0); 2671 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2672 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2673 unsigned DestBits = MVT::getSizeInBits(VT); 2674 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2675 2676 if (OpBits == DestBits) { 2677 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2678 // bits, it is already ready. 2679 if (NumSignBits > DestBits-MidBits) 2680 return Op; 2681 } else if (OpBits < DestBits) { 2682 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2683 // bits, just sext from i32. 2684 if (NumSignBits > OpBits-MidBits) 2685 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2686 } else { 2687 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2688 // bits, just truncate to i32. 2689 if (NumSignBits > OpBits-MidBits) 2690 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2691 } 2692 2693 // fold (sext (truncate x)) -> (sextinreg x). 2694 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2695 N0.getValueType())) { 2696 if (Op.getValueType() < VT) 2697 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2698 else if (Op.getValueType() > VT) 2699 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2700 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2701 DAG.getValueType(N0.getValueType())); 2702 } 2703 } 2704 2705 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2706 if (ISD::isNON_EXTLoad(N0.Val) && 2707 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2708 bool DoXform = true; 2709 SmallVector<SDNode*, 4> SetCCs; 2710 if (!N0.hasOneUse()) 2711 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2712 if (DoXform) { 2713 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2714 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2715 LN0->getBasePtr(), LN0->getSrcValue(), 2716 LN0->getSrcValueOffset(), 2717 N0.getValueType(), 2718 LN0->isVolatile(), 2719 LN0->getAlignment()); 2720 CombineTo(N, ExtLoad); 2721 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2722 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2723 // Extend SetCC uses if necessary. 2724 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2725 SDNode *SetCC = SetCCs[i]; 2726 SmallVector<SDOperand, 4> Ops; 2727 for (unsigned j = 0; j != 2; ++j) { 2728 SDOperand SOp = SetCC->getOperand(j); 2729 if (SOp == Trunc) 2730 Ops.push_back(ExtLoad); 2731 else 2732 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2733 } 2734 Ops.push_back(SetCC->getOperand(2)); 2735 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2736 &Ops[0], Ops.size())); 2737 } 2738 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2739 } 2740 } 2741 2742 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2743 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2744 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2745 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2746 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2747 MVT::ValueType EVT = LN0->getLoadedVT(); 2748 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2749 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2750 LN0->getBasePtr(), LN0->getSrcValue(), 2751 LN0->getSrcValueOffset(), EVT, 2752 LN0->isVolatile(), 2753 LN0->getAlignment()); 2754 CombineTo(N, ExtLoad); 2755 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2756 ExtLoad.getValue(1)); 2757 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2758 } 2759 } 2760 2761 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2762 if (N0.getOpcode() == ISD::SETCC) { 2763 SDOperand SCC = 2764 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2765 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2766 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2767 if (SCC.Val) return SCC; 2768 } 2769 2770 return SDOperand(); 2771} 2772 2773SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2774 SDOperand N0 = N->getOperand(0); 2775 MVT::ValueType VT = N->getValueType(0); 2776 2777 // fold (zext c1) -> c1 2778 if (isa<ConstantSDNode>(N0)) 2779 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2780 // fold (zext (zext x)) -> (zext x) 2781 // fold (zext (aext x)) -> (zext x) 2782 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2783 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2784 2785 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2786 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2787 if (N0.getOpcode() == ISD::TRUNCATE) { 2788 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2789 if (NarrowLoad.Val) { 2790 if (NarrowLoad.Val != N0.Val) 2791 CombineTo(N0.Val, NarrowLoad); 2792 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2793 } 2794 } 2795 2796 // fold (zext (truncate x)) -> (and x, mask) 2797 if (N0.getOpcode() == ISD::TRUNCATE && 2798 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2799 SDOperand Op = N0.getOperand(0); 2800 if (Op.getValueType() < VT) { 2801 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2802 } else if (Op.getValueType() > VT) { 2803 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2804 } 2805 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2806 } 2807 2808 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2809 if (N0.getOpcode() == ISD::AND && 2810 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2811 N0.getOperand(1).getOpcode() == ISD::Constant) { 2812 SDOperand X = N0.getOperand(0).getOperand(0); 2813 if (X.getValueType() < VT) { 2814 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2815 } else if (X.getValueType() > VT) { 2816 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2817 } 2818 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2819 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2820 } 2821 2822 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2823 if (ISD::isNON_EXTLoad(N0.Val) && 2824 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2825 bool DoXform = true; 2826 SmallVector<SDNode*, 4> SetCCs; 2827 if (!N0.hasOneUse()) 2828 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2829 if (DoXform) { 2830 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2831 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2832 LN0->getBasePtr(), LN0->getSrcValue(), 2833 LN0->getSrcValueOffset(), 2834 N0.getValueType(), 2835 LN0->isVolatile(), 2836 LN0->getAlignment()); 2837 CombineTo(N, ExtLoad); 2838 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2839 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2840 // Extend SetCC uses if necessary. 2841 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2842 SDNode *SetCC = SetCCs[i]; 2843 SmallVector<SDOperand, 4> Ops; 2844 for (unsigned j = 0; j != 2; ++j) { 2845 SDOperand SOp = SetCC->getOperand(j); 2846 if (SOp == Trunc) 2847 Ops.push_back(ExtLoad); 2848 else 2849 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2850 } 2851 Ops.push_back(SetCC->getOperand(2)); 2852 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2853 &Ops[0], Ops.size())); 2854 } 2855 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2856 } 2857 } 2858 2859 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2860 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2861 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2862 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2863 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2864 MVT::ValueType EVT = LN0->getLoadedVT(); 2865 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2866 LN0->getBasePtr(), LN0->getSrcValue(), 2867 LN0->getSrcValueOffset(), EVT, 2868 LN0->isVolatile(), 2869 LN0->getAlignment()); 2870 CombineTo(N, ExtLoad); 2871 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2872 ExtLoad.getValue(1)); 2873 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2874 } 2875 2876 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2877 if (N0.getOpcode() == ISD::SETCC) { 2878 SDOperand SCC = 2879 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2880 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2881 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2882 if (SCC.Val) return SCC; 2883 } 2884 2885 return SDOperand(); 2886} 2887 2888SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2889 SDOperand N0 = N->getOperand(0); 2890 MVT::ValueType VT = N->getValueType(0); 2891 2892 // fold (aext c1) -> c1 2893 if (isa<ConstantSDNode>(N0)) 2894 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2895 // fold (aext (aext x)) -> (aext x) 2896 // fold (aext (zext x)) -> (zext x) 2897 // fold (aext (sext x)) -> (sext x) 2898 if (N0.getOpcode() == ISD::ANY_EXTEND || 2899 N0.getOpcode() == ISD::ZERO_EXTEND || 2900 N0.getOpcode() == ISD::SIGN_EXTEND) 2901 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2902 2903 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2904 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2905 if (N0.getOpcode() == ISD::TRUNCATE) { 2906 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2907 if (NarrowLoad.Val) { 2908 if (NarrowLoad.Val != N0.Val) 2909 CombineTo(N0.Val, NarrowLoad); 2910 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2911 } 2912 } 2913 2914 // fold (aext (truncate x)) 2915 if (N0.getOpcode() == ISD::TRUNCATE) { 2916 SDOperand TruncOp = N0.getOperand(0); 2917 if (TruncOp.getValueType() == VT) 2918 return TruncOp; // x iff x size == zext size. 2919 if (TruncOp.getValueType() > VT) 2920 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2921 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2922 } 2923 2924 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2925 if (N0.getOpcode() == ISD::AND && 2926 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2927 N0.getOperand(1).getOpcode() == ISD::Constant) { 2928 SDOperand X = N0.getOperand(0).getOperand(0); 2929 if (X.getValueType() < VT) { 2930 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2931 } else if (X.getValueType() > VT) { 2932 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2933 } 2934 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2935 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2936 } 2937 2938 // fold (aext (load x)) -> (aext (truncate (extload x))) 2939 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2940 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2941 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2942 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2943 LN0->getBasePtr(), LN0->getSrcValue(), 2944 LN0->getSrcValueOffset(), 2945 N0.getValueType(), 2946 LN0->isVolatile(), 2947 LN0->getAlignment()); 2948 CombineTo(N, ExtLoad); 2949 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2950 ExtLoad.getValue(1)); 2951 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2952 } 2953 2954 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2955 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2956 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2957 if (N0.getOpcode() == ISD::LOAD && 2958 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2959 N0.hasOneUse()) { 2960 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2961 MVT::ValueType EVT = LN0->getLoadedVT(); 2962 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2963 LN0->getChain(), LN0->getBasePtr(), 2964 LN0->getSrcValue(), 2965 LN0->getSrcValueOffset(), EVT, 2966 LN0->isVolatile(), 2967 LN0->getAlignment()); 2968 CombineTo(N, ExtLoad); 2969 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2970 ExtLoad.getValue(1)); 2971 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2972 } 2973 2974 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2975 if (N0.getOpcode() == ISD::SETCC) { 2976 SDOperand SCC = 2977 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2978 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2979 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2980 if (SCC.Val) 2981 return SCC; 2982 } 2983 2984 return SDOperand(); 2985} 2986 2987/// GetDemandedBits - See if the specified operand can be simplified with the 2988/// knowledge that only the bits specified by Mask are used. If so, return the 2989/// simpler operand, otherwise return a null SDOperand. 2990SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) { 2991 switch (V.getOpcode()) { 2992 default: break; 2993 case ISD::OR: 2994 case ISD::XOR: 2995 // If the LHS or RHS don't contribute bits to the or, drop them. 2996 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 2997 return V.getOperand(1); 2998 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 2999 return V.getOperand(0); 3000 break; 3001 case ISD::SRL: 3002 // Only look at single-use SRLs. 3003 if (!V.Val->hasOneUse()) 3004 break; 3005 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3006 // See if we can recursively simplify the LHS. 3007 unsigned Amt = RHSC->getValue(); 3008 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType()); 3009 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask); 3010 if (SimplifyLHS.Val) { 3011 return DAG.getNode(ISD::SRL, V.getValueType(), 3012 SimplifyLHS, V.getOperand(1)); 3013 } 3014 } 3015 } 3016 return SDOperand(); 3017} 3018 3019/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3020/// bits and then truncated to a narrower type and where N is a multiple 3021/// of number of bits of the narrower type, transform it to a narrower load 3022/// from address + N / num of bits of new type. If the result is to be 3023/// extended, also fold the extension to form a extending load. 3024SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3025 unsigned Opc = N->getOpcode(); 3026 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3027 SDOperand N0 = N->getOperand(0); 3028 MVT::ValueType VT = N->getValueType(0); 3029 MVT::ValueType EVT = N->getValueType(0); 3030 3031 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3032 // extended to VT. 3033 if (Opc == ISD::SIGN_EXTEND_INREG) { 3034 ExtType = ISD::SEXTLOAD; 3035 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3036 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3037 return SDOperand(); 3038 } 3039 3040 unsigned EVTBits = MVT::getSizeInBits(EVT); 3041 unsigned ShAmt = 0; 3042 bool CombineSRL = false; 3043 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3044 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3045 ShAmt = N01->getValue(); 3046 // Is the shift amount a multiple of size of VT? 3047 if ((ShAmt & (EVTBits-1)) == 0) { 3048 N0 = N0.getOperand(0); 3049 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3050 return SDOperand(); 3051 CombineSRL = true; 3052 } 3053 } 3054 } 3055 3056 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3057 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3058 // zero extended form: by shrinking the load, we lose track of the fact 3059 // that it is already zero extended. 3060 // FIXME: This should be reevaluated. 3061 VT != MVT::i1) { 3062 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3063 "Cannot truncate to larger type!"); 3064 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3065 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3066 // For big endian targets, we need to adjust the offset to the pointer to 3067 // load the correct bytes. 3068 if (!TLI.isLittleEndian()) { 3069 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3070 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3071 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3072 } 3073 uint64_t PtrOff = ShAmt / 8; 3074 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3075 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3076 DAG.getConstant(PtrOff, PtrType)); 3077 AddToWorkList(NewPtr.Val); 3078 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3079 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3080 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3081 LN0->isVolatile(), NewAlign) 3082 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3083 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3084 LN0->isVolatile(), NewAlign); 3085 AddToWorkList(N); 3086 if (CombineSRL) { 3087 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 3088 CombineTo(N->getOperand(0).Val, Load); 3089 } else 3090 CombineTo(N0.Val, Load, Load.getValue(1)); 3091 if (ShAmt) { 3092 if (Opc == ISD::SIGN_EXTEND_INREG) 3093 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3094 else 3095 return DAG.getNode(Opc, VT, Load); 3096 } 3097 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3098 } 3099 3100 return SDOperand(); 3101} 3102 3103 3104SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3105 SDOperand N0 = N->getOperand(0); 3106 SDOperand N1 = N->getOperand(1); 3107 MVT::ValueType VT = N->getValueType(0); 3108 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3109 unsigned EVTBits = MVT::getSizeInBits(EVT); 3110 3111 // fold (sext_in_reg c1) -> c1 3112 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3113 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3114 3115 // If the input is already sign extended, just drop the extension. 3116 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3117 return N0; 3118 3119 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3120 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3121 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3122 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3123 } 3124 3125 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3126 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 3127 return DAG.getZeroExtendInReg(N0, EVT); 3128 3129 // fold operands of sext_in_reg based on knowledge that the top bits are not 3130 // demanded. 3131 if (SimplifyDemandedBits(SDOperand(N, 0))) 3132 return SDOperand(N, 0); 3133 3134 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3135 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3136 SDOperand NarrowLoad = ReduceLoadWidth(N); 3137 if (NarrowLoad.Val) 3138 return NarrowLoad; 3139 3140 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3141 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3142 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3143 if (N0.getOpcode() == ISD::SRL) { 3144 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3145 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3146 // We can turn this into an SRA iff the input to the SRL is already sign 3147 // extended enough. 3148 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3149 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3150 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3151 } 3152 } 3153 3154 // fold (sext_inreg (extload x)) -> (sextload x) 3155 if (ISD::isEXTLoad(N0.Val) && 3156 ISD::isUNINDEXEDLoad(N0.Val) && 3157 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3158 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3159 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3160 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3161 LN0->getBasePtr(), LN0->getSrcValue(), 3162 LN0->getSrcValueOffset(), EVT, 3163 LN0->isVolatile(), 3164 LN0->getAlignment()); 3165 CombineTo(N, ExtLoad); 3166 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3167 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3168 } 3169 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3170 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3171 N0.hasOneUse() && 3172 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3173 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3174 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3175 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3176 LN0->getBasePtr(), LN0->getSrcValue(), 3177 LN0->getSrcValueOffset(), EVT, 3178 LN0->isVolatile(), 3179 LN0->getAlignment()); 3180 CombineTo(N, ExtLoad); 3181 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3182 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3183 } 3184 return SDOperand(); 3185} 3186 3187SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3188 SDOperand N0 = N->getOperand(0); 3189 MVT::ValueType VT = N->getValueType(0); 3190 3191 // noop truncate 3192 if (N0.getValueType() == N->getValueType(0)) 3193 return N0; 3194 // fold (truncate c1) -> c1 3195 if (isa<ConstantSDNode>(N0)) 3196 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3197 // fold (truncate (truncate x)) -> (truncate x) 3198 if (N0.getOpcode() == ISD::TRUNCATE) 3199 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3200 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3201 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3202 N0.getOpcode() == ISD::ANY_EXTEND) { 3203 if (N0.getOperand(0).getValueType() < VT) 3204 // if the source is smaller than the dest, we still need an extend 3205 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3206 else if (N0.getOperand(0).getValueType() > VT) 3207 // if the source is larger than the dest, than we just need the truncate 3208 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3209 else 3210 // if the source and dest are the same type, we can drop both the extend 3211 // and the truncate 3212 return N0.getOperand(0); 3213 } 3214 3215 // See if we can simplify the input to this truncate through knowledge that 3216 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3217 // -> trunc y 3218 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT)); 3219 if (Shorter.Val) 3220 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3221 3222 // fold (truncate (load x)) -> (smaller load x) 3223 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3224 return ReduceLoadWidth(N); 3225} 3226 3227SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3228 SDOperand N0 = N->getOperand(0); 3229 MVT::ValueType VT = N->getValueType(0); 3230 3231 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3232 // Only do this before legalize, since afterward the target may be depending 3233 // on the bitconvert. 3234 // First check to see if this is all constant. 3235 if (!AfterLegalize && 3236 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3237 MVT::isVector(VT)) { 3238 bool isSimple = true; 3239 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3240 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3241 N0.getOperand(i).getOpcode() != ISD::Constant && 3242 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3243 isSimple = false; 3244 break; 3245 } 3246 3247 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3248 assert(!MVT::isVector(DestEltVT) && 3249 "Element type of vector ValueType must not be vector!"); 3250 if (isSimple) { 3251 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3252 } 3253 } 3254 3255 // If the input is a constant, let getNode() fold it. 3256 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3257 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3258 if (Res.Val != N) return Res; 3259 } 3260 3261 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3262 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3263 3264 // fold (conv (load x)) -> (load (conv*)x) 3265 // If the resultant load doesn't need a higher alignment than the original! 3266 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3267 TLI.isOperationLegal(ISD::LOAD, VT)) { 3268 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3269 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3270 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3271 unsigned OrigAlign = LN0->getAlignment(); 3272 if (Align <= OrigAlign) { 3273 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3274 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3275 LN0->isVolatile(), Align); 3276 AddToWorkList(N); 3277 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3278 Load.getValue(1)); 3279 return Load; 3280 } 3281 } 3282 3283 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3284 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3285 // This often reduces constant pool loads. 3286 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3287 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) { 3288 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3289 AddToWorkList(NewConv.Val); 3290 3291 uint64_t SignBit = MVT::getIntVTSignBit(VT); 3292 if (N0.getOpcode() == ISD::FNEG) 3293 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3294 assert(N0.getOpcode() == ISD::FABS); 3295 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3296 } 3297 3298 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3299 // Note that we don't handle copysign(x,cst) because this can always be folded 3300 // to an fneg or fabs. 3301 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3302 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3303 MVT::isInteger(VT) && !MVT::isVector(VT)) { 3304 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType()); 3305 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth), 3306 N0.getOperand(1)); 3307 AddToWorkList(X.Val); 3308 3309 // If X has a different width than the result/lhs, sext it or truncate it. 3310 unsigned VTWidth = MVT::getSizeInBits(VT); 3311 if (OrigXWidth < VTWidth) { 3312 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3313 AddToWorkList(X.Val); 3314 } else if (OrigXWidth > VTWidth) { 3315 // To get the sign bit in the right place, we have to shift it right 3316 // before truncating. 3317 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3318 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3319 AddToWorkList(X.Val); 3320 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3321 AddToWorkList(X.Val); 3322 } 3323 3324 uint64_t SignBit = MVT::getIntVTSignBit(VT); 3325 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3326 AddToWorkList(X.Val); 3327 3328 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3329 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3330 AddToWorkList(Cst.Val); 3331 3332 return DAG.getNode(ISD::OR, VT, X, Cst); 3333 } 3334 3335 return SDOperand(); 3336} 3337 3338/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3339/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3340/// destination element value type. 3341SDOperand DAGCombiner:: 3342ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3343 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3344 3345 // If this is already the right type, we're done. 3346 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3347 3348 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3349 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3350 3351 // If this is a conversion of N elements of one type to N elements of another 3352 // type, convert each element. This handles FP<->INT cases. 3353 if (SrcBitSize == DstBitSize) { 3354 SmallVector<SDOperand, 8> Ops; 3355 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3356 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3357 AddToWorkList(Ops.back().Val); 3358 } 3359 MVT::ValueType VT = 3360 MVT::getVectorType(DstEltVT, 3361 MVT::getVectorNumElements(BV->getValueType(0))); 3362 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3363 } 3364 3365 // Otherwise, we're growing or shrinking the elements. To avoid having to 3366 // handle annoying details of growing/shrinking FP values, we convert them to 3367 // int first. 3368 if (MVT::isFloatingPoint(SrcEltVT)) { 3369 // Convert the input float vector to a int vector where the elements are the 3370 // same sizes. 3371 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3372 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3373 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3374 SrcEltVT = IntVT; 3375 } 3376 3377 // Now we know the input is an integer vector. If the output is a FP type, 3378 // convert to integer first, then to FP of the right size. 3379 if (MVT::isFloatingPoint(DstEltVT)) { 3380 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3381 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3382 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3383 3384 // Next, convert to FP elements of the same size. 3385 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3386 } 3387 3388 // Okay, we know the src/dst types are both integers of differing types. 3389 // Handling growing first. 3390 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3391 if (SrcBitSize < DstBitSize) { 3392 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3393 3394 SmallVector<SDOperand, 8> Ops; 3395 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3396 i += NumInputsPerOutput) { 3397 bool isLE = TLI.isLittleEndian(); 3398 uint64_t NewBits = 0; 3399 bool EltIsUndef = true; 3400 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3401 // Shift the previously computed bits over. 3402 NewBits <<= SrcBitSize; 3403 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3404 if (Op.getOpcode() == ISD::UNDEF) continue; 3405 EltIsUndef = false; 3406 3407 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3408 } 3409 3410 if (EltIsUndef) 3411 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3412 else 3413 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3414 } 3415 3416 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3417 Ops.size()); 3418 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3419 } 3420 3421 // Finally, this must be the case where we are shrinking elements: each input 3422 // turns into multiple outputs. 3423 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3424 SmallVector<SDOperand, 8> Ops; 3425 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3426 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3427 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3428 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3429 continue; 3430 } 3431 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3432 3433 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3434 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3435 OpVal >>= DstBitSize; 3436 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3437 } 3438 3439 // For big endian targets, swap the order of the pieces of each element. 3440 if (!TLI.isLittleEndian()) 3441 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3442 } 3443 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3444 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3445} 3446 3447 3448 3449SDOperand DAGCombiner::visitFADD(SDNode *N) { 3450 SDOperand N0 = N->getOperand(0); 3451 SDOperand N1 = N->getOperand(1); 3452 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3453 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3454 MVT::ValueType VT = N->getValueType(0); 3455 3456 // fold vector ops 3457 if (MVT::isVector(VT)) { 3458 SDOperand FoldedVOp = SimplifyVBinOp(N); 3459 if (FoldedVOp.Val) return FoldedVOp; 3460 } 3461 3462 // fold (fadd c1, c2) -> c1+c2 3463 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3464 return DAG.getNode(ISD::FADD, VT, N0, N1); 3465 // canonicalize constant to RHS 3466 if (N0CFP && !N1CFP) 3467 return DAG.getNode(ISD::FADD, VT, N1, N0); 3468 // fold (A + (-B)) -> A-B 3469 if (isNegatibleForFree(N1) == 2) 3470 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3471 // fold ((-A) + B) -> B-A 3472 if (isNegatibleForFree(N0) == 2) 3473 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3474 3475 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3476 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3477 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3478 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3479 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3480 3481 return SDOperand(); 3482} 3483 3484SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3485 SDOperand N0 = N->getOperand(0); 3486 SDOperand N1 = N->getOperand(1); 3487 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3488 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3489 MVT::ValueType VT = N->getValueType(0); 3490 3491 // fold vector ops 3492 if (MVT::isVector(VT)) { 3493 SDOperand FoldedVOp = SimplifyVBinOp(N); 3494 if (FoldedVOp.Val) return FoldedVOp; 3495 } 3496 3497 // fold (fsub c1, c2) -> c1-c2 3498 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3499 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3500 // fold (0-B) -> -B 3501 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3502 if (isNegatibleForFree(N1)) 3503 return GetNegatedExpression(N1, DAG); 3504 return DAG.getNode(ISD::FNEG, VT, N1); 3505 } 3506 // fold (A-(-B)) -> A+B 3507 if (isNegatibleForFree(N1)) 3508 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3509 3510 return SDOperand(); 3511} 3512 3513SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3514 SDOperand N0 = N->getOperand(0); 3515 SDOperand N1 = N->getOperand(1); 3516 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3517 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3518 MVT::ValueType VT = N->getValueType(0); 3519 3520 // fold vector ops 3521 if (MVT::isVector(VT)) { 3522 SDOperand FoldedVOp = SimplifyVBinOp(N); 3523 if (FoldedVOp.Val) return FoldedVOp; 3524 } 3525 3526 // fold (fmul c1, c2) -> c1*c2 3527 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3528 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3529 // canonicalize constant to RHS 3530 if (N0CFP && !N1CFP) 3531 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3532 // fold (fmul X, 2.0) -> (fadd X, X) 3533 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3534 return DAG.getNode(ISD::FADD, VT, N0, N0); 3535 // fold (fmul X, -1.0) -> (fneg X) 3536 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3537 return DAG.getNode(ISD::FNEG, VT, N0); 3538 3539 // -X * -Y -> X*Y 3540 if (char LHSNeg = isNegatibleForFree(N0)) { 3541 if (char RHSNeg = isNegatibleForFree(N1)) { 3542 // Both can be negated for free, check to see if at least one is cheaper 3543 // negated. 3544 if (LHSNeg == 2 || RHSNeg == 2) 3545 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3546 GetNegatedExpression(N1, DAG)); 3547 } 3548 } 3549 3550 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3551 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3552 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3553 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3554 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3555 3556 return SDOperand(); 3557} 3558 3559SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3560 SDOperand N0 = N->getOperand(0); 3561 SDOperand N1 = N->getOperand(1); 3562 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3563 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3564 MVT::ValueType VT = N->getValueType(0); 3565 3566 // fold vector ops 3567 if (MVT::isVector(VT)) { 3568 SDOperand FoldedVOp = SimplifyVBinOp(N); 3569 if (FoldedVOp.Val) return FoldedVOp; 3570 } 3571 3572 // fold (fdiv c1, c2) -> c1/c2 3573 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3574 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3575 3576 3577 // -X / -Y -> X*Y 3578 if (char LHSNeg = isNegatibleForFree(N0)) { 3579 if (char RHSNeg = isNegatibleForFree(N1)) { 3580 // Both can be negated for free, check to see if at least one is cheaper 3581 // negated. 3582 if (LHSNeg == 2 || RHSNeg == 2) 3583 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3584 GetNegatedExpression(N1, DAG)); 3585 } 3586 } 3587 3588 return SDOperand(); 3589} 3590 3591SDOperand DAGCombiner::visitFREM(SDNode *N) { 3592 SDOperand N0 = N->getOperand(0); 3593 SDOperand N1 = N->getOperand(1); 3594 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3595 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3596 MVT::ValueType VT = N->getValueType(0); 3597 3598 // fold (frem c1, c2) -> fmod(c1,c2) 3599 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3600 return DAG.getNode(ISD::FREM, VT, N0, N1); 3601 3602 return SDOperand(); 3603} 3604 3605SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3606 SDOperand N0 = N->getOperand(0); 3607 SDOperand N1 = N->getOperand(1); 3608 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3609 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3610 MVT::ValueType VT = N->getValueType(0); 3611 3612 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3613 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3614 3615 if (N1CFP) { 3616 const APFloat& V = N1CFP->getValueAPF(); 3617 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3618 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3619 if (!V.isNegative()) 3620 return DAG.getNode(ISD::FABS, VT, N0); 3621 else 3622 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3623 } 3624 3625 // copysign(fabs(x), y) -> copysign(x, y) 3626 // copysign(fneg(x), y) -> copysign(x, y) 3627 // copysign(copysign(x,z), y) -> copysign(x, y) 3628 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3629 N0.getOpcode() == ISD::FCOPYSIGN) 3630 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3631 3632 // copysign(x, abs(y)) -> abs(x) 3633 if (N1.getOpcode() == ISD::FABS) 3634 return DAG.getNode(ISD::FABS, VT, N0); 3635 3636 // copysign(x, copysign(y,z)) -> copysign(x, z) 3637 if (N1.getOpcode() == ISD::FCOPYSIGN) 3638 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3639 3640 // copysign(x, fp_extend(y)) -> copysign(x, y) 3641 // copysign(x, fp_round(y)) -> copysign(x, y) 3642 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3643 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3644 3645 return SDOperand(); 3646} 3647 3648 3649 3650SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3651 SDOperand N0 = N->getOperand(0); 3652 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3653 MVT::ValueType VT = N->getValueType(0); 3654 3655 // fold (sint_to_fp c1) -> c1fp 3656 if (N0C && N0.getValueType() != MVT::ppcf128) 3657 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3658 return SDOperand(); 3659} 3660 3661SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3662 SDOperand N0 = N->getOperand(0); 3663 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3664 MVT::ValueType VT = N->getValueType(0); 3665 3666 // fold (uint_to_fp c1) -> c1fp 3667 if (N0C && N0.getValueType() != MVT::ppcf128) 3668 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3669 return SDOperand(); 3670} 3671 3672SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3673 SDOperand N0 = N->getOperand(0); 3674 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3675 MVT::ValueType VT = N->getValueType(0); 3676 3677 // fold (fp_to_sint c1fp) -> c1 3678 if (N0CFP) 3679 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3680 return SDOperand(); 3681} 3682 3683SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3684 SDOperand N0 = N->getOperand(0); 3685 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3686 MVT::ValueType VT = N->getValueType(0); 3687 3688 // fold (fp_to_uint c1fp) -> c1 3689 if (N0CFP && VT != MVT::ppcf128) 3690 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3691 return SDOperand(); 3692} 3693 3694SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3695 SDOperand N0 = N->getOperand(0); 3696 SDOperand N1 = N->getOperand(1); 3697 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3698 MVT::ValueType VT = N->getValueType(0); 3699 3700 // fold (fp_round c1fp) -> c1fp 3701 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3702 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3703 3704 // fold (fp_round (fp_extend x)) -> x 3705 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3706 return N0.getOperand(0); 3707 3708 // fold (fp_round (fp_round x)) -> (fp_round x) 3709 if (N0.getOpcode() == ISD::FP_ROUND) { 3710 // This is a value preserving truncation if both round's are. 3711 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3712 N0.Val->getConstantOperandVal(1) == 1; 3713 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3714 DAG.getIntPtrConstant(IsTrunc)); 3715 } 3716 3717 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3718 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3719 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3720 AddToWorkList(Tmp.Val); 3721 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3722 } 3723 3724 return SDOperand(); 3725} 3726 3727SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3728 SDOperand N0 = N->getOperand(0); 3729 MVT::ValueType VT = N->getValueType(0); 3730 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3731 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3732 3733 // fold (fp_round_inreg c1fp) -> c1fp 3734 if (N0CFP) { 3735 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3736 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3737 } 3738 return SDOperand(); 3739} 3740 3741SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3742 SDOperand N0 = N->getOperand(0); 3743 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3744 MVT::ValueType VT = N->getValueType(0); 3745 3746 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3747 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND) 3748 return SDOperand(); 3749 3750 // fold (fp_extend c1fp) -> c1fp 3751 if (N0CFP && VT != MVT::ppcf128) 3752 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3753 3754 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3755 // value of X. 3756 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3757 SDOperand In = N0.getOperand(0); 3758 if (In.getValueType() == VT) return In; 3759 if (VT < In.getValueType()) 3760 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3761 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3762 } 3763 3764 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3765 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3766 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3767 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3768 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3769 LN0->getBasePtr(), LN0->getSrcValue(), 3770 LN0->getSrcValueOffset(), 3771 N0.getValueType(), 3772 LN0->isVolatile(), 3773 LN0->getAlignment()); 3774 CombineTo(N, ExtLoad); 3775 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3776 DAG.getIntPtrConstant(1)), 3777 ExtLoad.getValue(1)); 3778 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3779 } 3780 3781 3782 return SDOperand(); 3783} 3784 3785SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3786 SDOperand N0 = N->getOperand(0); 3787 3788 if (isNegatibleForFree(N0)) 3789 return GetNegatedExpression(N0, DAG); 3790 3791 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 3792 // constant pool values. 3793 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3794 MVT::isInteger(N0.getOperand(0).getValueType()) && 3795 !MVT::isVector(N0.getOperand(0).getValueType())) { 3796 SDOperand Int = N0.getOperand(0); 3797 MVT::ValueType IntVT = Int.getValueType(); 3798 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3799 Int = DAG.getNode(ISD::XOR, IntVT, Int, 3800 DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT)); 3801 AddToWorkList(Int.Val); 3802 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3803 } 3804 } 3805 3806 return SDOperand(); 3807} 3808 3809SDOperand DAGCombiner::visitFABS(SDNode *N) { 3810 SDOperand N0 = N->getOperand(0); 3811 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3812 MVT::ValueType VT = N->getValueType(0); 3813 3814 // fold (fabs c1) -> fabs(c1) 3815 if (N0CFP && VT != MVT::ppcf128) 3816 return DAG.getNode(ISD::FABS, VT, N0); 3817 // fold (fabs (fabs x)) -> (fabs x) 3818 if (N0.getOpcode() == ISD::FABS) 3819 return N->getOperand(0); 3820 // fold (fabs (fneg x)) -> (fabs x) 3821 // fold (fabs (fcopysign x, y)) -> (fabs x) 3822 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3823 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3824 3825 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 3826 // constant pool values. 3827 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3828 MVT::isInteger(N0.getOperand(0).getValueType()) && 3829 !MVT::isVector(N0.getOperand(0).getValueType())) { 3830 SDOperand Int = N0.getOperand(0); 3831 MVT::ValueType IntVT = Int.getValueType(); 3832 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3833 Int = DAG.getNode(ISD::AND, IntVT, Int, 3834 DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT)); 3835 AddToWorkList(Int.Val); 3836 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3837 } 3838 } 3839 3840 return SDOperand(); 3841} 3842 3843SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3844 SDOperand Chain = N->getOperand(0); 3845 SDOperand N1 = N->getOperand(1); 3846 SDOperand N2 = N->getOperand(2); 3847 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3848 3849 // never taken branch, fold to chain 3850 if (N1C && N1C->isNullValue()) 3851 return Chain; 3852 // unconditional branch 3853 if (N1C && N1C->getValue() == 1) 3854 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3855 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3856 // on the target. 3857 if (N1.getOpcode() == ISD::SETCC && 3858 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3859 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3860 N1.getOperand(0), N1.getOperand(1), N2); 3861 } 3862 return SDOperand(); 3863} 3864 3865// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3866// 3867SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3868 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3869 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3870 3871 // Use SimplifySetCC to simplify SETCC's. 3872 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3873 if (Simp.Val) AddToWorkList(Simp.Val); 3874 3875 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3876 3877 // fold br_cc true, dest -> br dest (unconditional branch) 3878 if (SCCC && SCCC->getValue()) 3879 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3880 N->getOperand(4)); 3881 // fold br_cc false, dest -> unconditional fall through 3882 if (SCCC && SCCC->isNullValue()) 3883 return N->getOperand(0); 3884 3885 // fold to a simpler setcc 3886 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3887 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3888 Simp.getOperand(2), Simp.getOperand(0), 3889 Simp.getOperand(1), N->getOperand(4)); 3890 return SDOperand(); 3891} 3892 3893 3894/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3895/// pre-indexed load / store when the base pointer is a add or subtract 3896/// and it has other uses besides the load / store. After the 3897/// transformation, the new indexed load / store has effectively folded 3898/// the add / subtract in and all of its other uses are redirected to the 3899/// new load / store. 3900bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3901 if (!AfterLegalize) 3902 return false; 3903 3904 bool isLoad = true; 3905 SDOperand Ptr; 3906 MVT::ValueType VT; 3907 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3908 if (LD->isIndexed()) 3909 return false; 3910 VT = LD->getLoadedVT(); 3911 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3912 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3913 return false; 3914 Ptr = LD->getBasePtr(); 3915 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3916 if (ST->isIndexed()) 3917 return false; 3918 VT = ST->getStoredVT(); 3919 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3920 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3921 return false; 3922 Ptr = ST->getBasePtr(); 3923 isLoad = false; 3924 } else 3925 return false; 3926 3927 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3928 // out. There is no reason to make this a preinc/predec. 3929 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3930 Ptr.Val->hasOneUse()) 3931 return false; 3932 3933 // Ask the target to do addressing mode selection. 3934 SDOperand BasePtr; 3935 SDOperand Offset; 3936 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3937 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3938 return false; 3939 // Don't create a indexed load / store with zero offset. 3940 if (isa<ConstantSDNode>(Offset) && 3941 cast<ConstantSDNode>(Offset)->getValue() == 0) 3942 return false; 3943 3944 // Try turning it into a pre-indexed load / store except when: 3945 // 1) The new base ptr is a frame index. 3946 // 2) If N is a store and the new base ptr is either the same as or is a 3947 // predecessor of the value being stored. 3948 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3949 // that would create a cycle. 3950 // 4) All uses are load / store ops that use it as old base ptr. 3951 3952 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3953 // (plus the implicit offset) to a register to preinc anyway. 3954 if (isa<FrameIndexSDNode>(BasePtr)) 3955 return false; 3956 3957 // Check #2. 3958 if (!isLoad) { 3959 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3960 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3961 return false; 3962 } 3963 3964 // Now check for #3 and #4. 3965 bool RealUse = false; 3966 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3967 E = Ptr.Val->use_end(); I != E; ++I) { 3968 SDNode *Use = *I; 3969 if (Use == N) 3970 continue; 3971 if (Use->isPredecessor(N)) 3972 return false; 3973 3974 if (!((Use->getOpcode() == ISD::LOAD && 3975 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3976 (Use->getOpcode() == ISD::STORE) && 3977 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3978 RealUse = true; 3979 } 3980 if (!RealUse) 3981 return false; 3982 3983 SDOperand Result; 3984 if (isLoad) 3985 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3986 else 3987 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3988 ++PreIndexedNodes; 3989 ++NodesCombined; 3990 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 3991 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3992 DOUT << '\n'; 3993 std::vector<SDNode*> NowDead; 3994 if (isLoad) { 3995 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3996 &NowDead); 3997 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3998 &NowDead); 3999 } else { 4000 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4001 &NowDead); 4002 } 4003 4004 // Nodes can end up on the worklist more than once. Make sure we do 4005 // not process a node that has been replaced. 4006 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4007 removeFromWorkList(NowDead[i]); 4008 // Finally, since the node is now dead, remove it from the graph. 4009 DAG.DeleteNode(N); 4010 4011 // Replace the uses of Ptr with uses of the updated base value. 4012 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4013 &NowDead); 4014 removeFromWorkList(Ptr.Val); 4015 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4016 removeFromWorkList(NowDead[i]); 4017 DAG.DeleteNode(Ptr.Val); 4018 4019 return true; 4020} 4021 4022/// CombineToPostIndexedLoadStore - Try combine a load / store with a 4023/// add / sub of the base pointer node into a post-indexed load / store. 4024/// The transformation folded the add / subtract into the new indexed 4025/// load / store effectively and all of its uses are redirected to the 4026/// new load / store. 4027bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4028 if (!AfterLegalize) 4029 return false; 4030 4031 bool isLoad = true; 4032 SDOperand Ptr; 4033 MVT::ValueType VT; 4034 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4035 if (LD->isIndexed()) 4036 return false; 4037 VT = LD->getLoadedVT(); 4038 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4039 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4040 return false; 4041 Ptr = LD->getBasePtr(); 4042 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4043 if (ST->isIndexed()) 4044 return false; 4045 VT = ST->getStoredVT(); 4046 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4047 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4048 return false; 4049 Ptr = ST->getBasePtr(); 4050 isLoad = false; 4051 } else 4052 return false; 4053 4054 if (Ptr.Val->hasOneUse()) 4055 return false; 4056 4057 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4058 E = Ptr.Val->use_end(); I != E; ++I) { 4059 SDNode *Op = *I; 4060 if (Op == N || 4061 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4062 continue; 4063 4064 SDOperand BasePtr; 4065 SDOperand Offset; 4066 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4067 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4068 if (Ptr == Offset) 4069 std::swap(BasePtr, Offset); 4070 if (Ptr != BasePtr) 4071 continue; 4072 // Don't create a indexed load / store with zero offset. 4073 if (isa<ConstantSDNode>(Offset) && 4074 cast<ConstantSDNode>(Offset)->getValue() == 0) 4075 continue; 4076 4077 // Try turning it into a post-indexed load / store except when 4078 // 1) All uses are load / store ops that use it as base ptr. 4079 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4080 // nor a successor of N. Otherwise, if Op is folded that would 4081 // create a cycle. 4082 4083 // Check for #1. 4084 bool TryNext = false; 4085 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4086 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4087 SDNode *Use = *II; 4088 if (Use == Ptr.Val) 4089 continue; 4090 4091 // If all the uses are load / store addresses, then don't do the 4092 // transformation. 4093 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4094 bool RealUse = false; 4095 for (SDNode::use_iterator III = Use->use_begin(), 4096 EEE = Use->use_end(); III != EEE; ++III) { 4097 SDNode *UseUse = *III; 4098 if (!((UseUse->getOpcode() == ISD::LOAD && 4099 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4100 (UseUse->getOpcode() == ISD::STORE) && 4101 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 4102 RealUse = true; 4103 } 4104 4105 if (!RealUse) { 4106 TryNext = true; 4107 break; 4108 } 4109 } 4110 } 4111 if (TryNext) 4112 continue; 4113 4114 // Check for #2 4115 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 4116 SDOperand Result = isLoad 4117 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4118 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4119 ++PostIndexedNodes; 4120 ++NodesCombined; 4121 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4122 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4123 DOUT << '\n'; 4124 std::vector<SDNode*> NowDead; 4125 if (isLoad) { 4126 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4127 &NowDead); 4128 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4129 &NowDead); 4130 } else { 4131 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4132 &NowDead); 4133 } 4134 4135 // Nodes can end up on the worklist more than once. Make sure we do 4136 // not process a node that has been replaced. 4137 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4138 removeFromWorkList(NowDead[i]); 4139 // Finally, since the node is now dead, remove it from the graph. 4140 DAG.DeleteNode(N); 4141 4142 // Replace the uses of Use with uses of the updated base value. 4143 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4144 Result.getValue(isLoad ? 1 : 0), 4145 &NowDead); 4146 removeFromWorkList(Op); 4147 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4148 removeFromWorkList(NowDead[i]); 4149 DAG.DeleteNode(Op); 4150 4151 return true; 4152 } 4153 } 4154 } 4155 return false; 4156} 4157 4158/// InferAlignment - If we can infer some alignment information from this 4159/// pointer, return it. 4160static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4161 // If this is a direct reference to a stack slot, use information about the 4162 // stack slot's alignment. 4163 int FrameIdx = 1 << 31; 4164 int64_t FrameOffset = 0; 4165 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4166 FrameIdx = FI->getIndex(); 4167 } else if (Ptr.getOpcode() == ISD::ADD && 4168 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4169 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4170 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4171 FrameOffset = Ptr.getConstantOperandVal(1); 4172 } 4173 4174 if (FrameIdx != (1 << 31)) { 4175 // FIXME: Handle FI+CST. 4176 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4177 if (MFI.isFixedObjectIndex(FrameIdx)) { 4178 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4179 4180 // The alignment of the frame index can be determined from its offset from 4181 // the incoming frame position. If the frame object is at offset 32 and 4182 // the stack is guaranteed to be 16-byte aligned, then we know that the 4183 // object is 16-byte aligned. 4184 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4185 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4186 4187 // Finally, the frame object itself may have a known alignment. Factor 4188 // the alignment + offset into a new alignment. For example, if we know 4189 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4190 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4191 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4192 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4193 FrameOffset); 4194 return std::max(Align, FIInfoAlign); 4195 } 4196 } 4197 4198 return 0; 4199} 4200 4201SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4202 LoadSDNode *LD = cast<LoadSDNode>(N); 4203 SDOperand Chain = LD->getChain(); 4204 SDOperand Ptr = LD->getBasePtr(); 4205 4206 // Try to infer better alignment information than the load already has. 4207 if (LD->isUnindexed()) { 4208 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4209 if (Align > LD->getAlignment()) 4210 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4211 Chain, Ptr, LD->getSrcValue(), 4212 LD->getSrcValueOffset(), LD->getLoadedVT(), 4213 LD->isVolatile(), Align); 4214 } 4215 } 4216 4217 4218 // If load is not volatile and there are no uses of the loaded value (and 4219 // the updated indexed value in case of indexed loads), change uses of the 4220 // chain value into uses of the chain input (i.e. delete the dead load). 4221 if (!LD->isVolatile()) { 4222 if (N->getValueType(1) == MVT::Other) { 4223 // Unindexed loads. 4224 if (N->hasNUsesOfValue(0, 0)) { 4225 // It's not safe to use the two value CombineTo variant here. e.g. 4226 // v1, chain2 = load chain1, loc 4227 // v2, chain3 = load chain2, loc 4228 // v3 = add v2, c 4229 // Now we replace use of chain2 with chain1. This makes the second load 4230 // isomorphic to the one we are deleting, and thus makes this load live. 4231 std::vector<SDNode*> NowDead; 4232 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4233 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4234 DOUT << "\n"; 4235 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &NowDead); 4236 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4237 removeFromWorkList(NowDead[i]); 4238 if (N->use_empty()) { 4239 removeFromWorkList(N); 4240 DAG.DeleteNode(N); 4241 } 4242 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4243 } 4244 } else { 4245 // Indexed loads. 4246 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4247 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4248 std::vector<SDNode*> NowDead; 4249 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4250 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4251 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4252 DOUT << " and 2 other values\n"; 4253 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &NowDead); 4254 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4255 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4256 &NowDead); 4257 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &NowDead); 4258 removeFromWorkList(N); 4259 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 4260 removeFromWorkList(NowDead[i]); 4261 DAG.DeleteNode(N); 4262 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4263 } 4264 } 4265 } 4266 4267 // If this load is directly stored, replace the load value with the stored 4268 // value. 4269 // TODO: Handle store large -> read small portion. 4270 // TODO: Handle TRUNCSTORE/LOADEXT 4271 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4272 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4273 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4274 if (PrevST->getBasePtr() == Ptr && 4275 PrevST->getValue().getValueType() == N->getValueType(0)) 4276 return CombineTo(N, Chain.getOperand(1), Chain); 4277 } 4278 } 4279 4280 if (CombinerAA) { 4281 // Walk up chain skipping non-aliasing memory nodes. 4282 SDOperand BetterChain = FindBetterChain(N, Chain); 4283 4284 // If there is a better chain. 4285 if (Chain != BetterChain) { 4286 SDOperand ReplLoad; 4287 4288 // Replace the chain to void dependency. 4289 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4290 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4291 LD->getSrcValue(), LD->getSrcValueOffset(), 4292 LD->isVolatile(), LD->getAlignment()); 4293 } else { 4294 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4295 LD->getValueType(0), 4296 BetterChain, Ptr, LD->getSrcValue(), 4297 LD->getSrcValueOffset(), 4298 LD->getLoadedVT(), 4299 LD->isVolatile(), 4300 LD->getAlignment()); 4301 } 4302 4303 // Create token factor to keep old chain connected. 4304 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4305 Chain, ReplLoad.getValue(1)); 4306 4307 // Replace uses with load result and token factor. Don't add users 4308 // to work list. 4309 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4310 } 4311 } 4312 4313 // Try transforming N to an indexed load. 4314 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4315 return SDOperand(N, 0); 4316 4317 return SDOperand(); 4318} 4319 4320 4321SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4322 StoreSDNode *ST = cast<StoreSDNode>(N); 4323 SDOperand Chain = ST->getChain(); 4324 SDOperand Value = ST->getValue(); 4325 SDOperand Ptr = ST->getBasePtr(); 4326 4327 // Try to infer better alignment information than the store already has. 4328 if (ST->isUnindexed()) { 4329 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4330 if (Align > ST->getAlignment()) 4331 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4332 ST->getSrcValueOffset(), ST->getStoredVT(), 4333 ST->isVolatile(), Align); 4334 } 4335 } 4336 4337 // If this is a store of a bit convert, store the input value if the 4338 // resultant store does not need a higher alignment than the original. 4339 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4340 ST->isUnindexed()) { 4341 unsigned Align = ST->getAlignment(); 4342 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4343 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4344 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4345 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4346 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4347 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4348 } 4349 4350 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4351 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4352 if (Value.getOpcode() != ISD::TargetConstantFP) { 4353 SDOperand Tmp; 4354 switch (CFP->getValueType(0)) { 4355 default: assert(0 && "Unknown FP type"); 4356 case MVT::f80: // We don't do this for these yet. 4357 case MVT::f128: 4358 case MVT::ppcf128: 4359 break; 4360 case MVT::f32: 4361 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4362 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4363 convertToAPInt().getZExtValue(), MVT::i32); 4364 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4365 ST->getSrcValueOffset(), ST->isVolatile(), 4366 ST->getAlignment()); 4367 } 4368 break; 4369 case MVT::f64: 4370 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4371 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4372 getZExtValue(), MVT::i64); 4373 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4374 ST->getSrcValueOffset(), ST->isVolatile(), 4375 ST->getAlignment()); 4376 } else if (TLI.isTypeLegal(MVT::i32)) { 4377 // Many FP stores are not made apparent until after legalize, e.g. for 4378 // argument passing. Since this is so common, custom legalize the 4379 // 64-bit integer store into two 32-bit stores. 4380 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4381 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4382 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4383 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 4384 4385 int SVOffset = ST->getSrcValueOffset(); 4386 unsigned Alignment = ST->getAlignment(); 4387 bool isVolatile = ST->isVolatile(); 4388 4389 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4390 ST->getSrcValueOffset(), 4391 isVolatile, ST->getAlignment()); 4392 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4393 DAG.getConstant(4, Ptr.getValueType())); 4394 SVOffset += 4; 4395 Alignment = MinAlign(Alignment, 4U); 4396 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4397 SVOffset, isVolatile, Alignment); 4398 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4399 } 4400 break; 4401 } 4402 } 4403 } 4404 4405 if (CombinerAA) { 4406 // Walk up chain skipping non-aliasing memory nodes. 4407 SDOperand BetterChain = FindBetterChain(N, Chain); 4408 4409 // If there is a better chain. 4410 if (Chain != BetterChain) { 4411 // Replace the chain to avoid dependency. 4412 SDOperand ReplStore; 4413 if (ST->isTruncatingStore()) { 4414 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4415 ST->getSrcValue(),ST->getSrcValueOffset(), 4416 ST->getStoredVT(), 4417 ST->isVolatile(), ST->getAlignment()); 4418 } else { 4419 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4420 ST->getSrcValue(), ST->getSrcValueOffset(), 4421 ST->isVolatile(), ST->getAlignment()); 4422 } 4423 4424 // Create token to keep both nodes around. 4425 SDOperand Token = 4426 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4427 4428 // Don't add users to work list. 4429 return CombineTo(N, Token, false); 4430 } 4431 } 4432 4433 // Try transforming N to an indexed store. 4434 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4435 return SDOperand(N, 0); 4436 4437 // FIXME: is there such a thing as a truncating indexed store? 4438 if (ST->isTruncatingStore() && ST->isUnindexed() && 4439 MVT::isInteger(Value.getValueType())) { 4440 // See if we can simplify the input to this truncstore with knowledge that 4441 // only the low bits are being used. For example: 4442 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4443 SDOperand Shorter = 4444 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())); 4445 AddToWorkList(Value.Val); 4446 if (Shorter.Val) 4447 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4448 ST->getSrcValueOffset(), ST->getStoredVT(), 4449 ST->isVolatile(), ST->getAlignment()); 4450 4451 // Otherwise, see if we can simplify the operation with 4452 // SimplifyDemandedBits, which only works if the value has a single use. 4453 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()))) 4454 return SDOperand(N, 0); 4455 } 4456 4457 // If this is a load followed by a store to the same location, then the store 4458 // is dead/noop. 4459 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4460 if (Ld->getBasePtr() == Ptr && ST->getStoredVT() == Ld->getLoadedVT() && 4461 ST->isUnindexed() && !ST->isVolatile() && 4462 // There can't be any side effects between the load and store, such as 4463 // a call or store. 4464 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4465 // The store is dead, remove it. 4466 return Chain; 4467 } 4468 } 4469 4470 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4471 // truncating store. We can do this even if this is already a truncstore. 4472 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4473 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) && 4474 Value.Val->hasOneUse() && ST->isUnindexed() && 4475 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4476 ST->getStoredVT())) { 4477 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4478 ST->getSrcValueOffset(), ST->getStoredVT(), 4479 ST->isVolatile(), ST->getAlignment()); 4480 } 4481 4482 return SDOperand(); 4483} 4484 4485SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4486 SDOperand InVec = N->getOperand(0); 4487 SDOperand InVal = N->getOperand(1); 4488 SDOperand EltNo = N->getOperand(2); 4489 4490 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4491 // vector with the inserted element. 4492 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4493 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4494 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4495 if (Elt < Ops.size()) 4496 Ops[Elt] = InVal; 4497 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4498 &Ops[0], Ops.size()); 4499 } 4500 4501 return SDOperand(); 4502} 4503 4504SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4505 SDOperand InVec = N->getOperand(0); 4506 SDOperand EltNo = N->getOperand(1); 4507 4508 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4509 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4510 if (isa<ConstantSDNode>(EltNo)) { 4511 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4512 bool NewLoad = false; 4513 if (Elt == 0) { 4514 MVT::ValueType VT = InVec.getValueType(); 4515 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4516 MVT::ValueType LVT = EVT; 4517 unsigned NumElts = MVT::getVectorNumElements(VT); 4518 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4519 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4520 if (!MVT::isVector(BCVT) || 4521 NumElts != MVT::getVectorNumElements(BCVT)) 4522 return SDOperand(); 4523 InVec = InVec.getOperand(0); 4524 EVT = MVT::getVectorElementType(BCVT); 4525 NewLoad = true; 4526 } 4527 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4528 InVec.getOperand(0).getValueType() == EVT && 4529 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4530 InVec.getOperand(0).hasOneUse()) { 4531 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4532 unsigned Align = LN0->getAlignment(); 4533 if (NewLoad) { 4534 // Check the resultant load doesn't need a higher alignment than the 4535 // original load. 4536 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4537 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4538 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4539 return SDOperand(); 4540 Align = NewAlign; 4541 } 4542 4543 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4544 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4545 LN0->isVolatile(), Align); 4546 } 4547 } 4548 } 4549 return SDOperand(); 4550} 4551 4552 4553SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4554 unsigned NumInScalars = N->getNumOperands(); 4555 MVT::ValueType VT = N->getValueType(0); 4556 unsigned NumElts = MVT::getVectorNumElements(VT); 4557 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4558 4559 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4560 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4561 // at most two distinct vectors, turn this into a shuffle node. 4562 SDOperand VecIn1, VecIn2; 4563 for (unsigned i = 0; i != NumInScalars; ++i) { 4564 // Ignore undef inputs. 4565 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4566 4567 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4568 // constant index, bail out. 4569 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4570 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4571 VecIn1 = VecIn2 = SDOperand(0, 0); 4572 break; 4573 } 4574 4575 // If the input vector type disagrees with the result of the build_vector, 4576 // we can't make a shuffle. 4577 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4578 if (ExtractedFromVec.getValueType() != VT) { 4579 VecIn1 = VecIn2 = SDOperand(0, 0); 4580 break; 4581 } 4582 4583 // Otherwise, remember this. We allow up to two distinct input vectors. 4584 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4585 continue; 4586 4587 if (VecIn1.Val == 0) { 4588 VecIn1 = ExtractedFromVec; 4589 } else if (VecIn2.Val == 0) { 4590 VecIn2 = ExtractedFromVec; 4591 } else { 4592 // Too many inputs. 4593 VecIn1 = VecIn2 = SDOperand(0, 0); 4594 break; 4595 } 4596 } 4597 4598 // If everything is good, we can make a shuffle operation. 4599 if (VecIn1.Val) { 4600 SmallVector<SDOperand, 8> BuildVecIndices; 4601 for (unsigned i = 0; i != NumInScalars; ++i) { 4602 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4603 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4604 continue; 4605 } 4606 4607 SDOperand Extract = N->getOperand(i); 4608 4609 // If extracting from the first vector, just use the index directly. 4610 if (Extract.getOperand(0) == VecIn1) { 4611 BuildVecIndices.push_back(Extract.getOperand(1)); 4612 continue; 4613 } 4614 4615 // Otherwise, use InIdx + VecSize 4616 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4617 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4618 } 4619 4620 // Add count and size info. 4621 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); 4622 4623 // Return the new VECTOR_SHUFFLE node. 4624 SDOperand Ops[5]; 4625 Ops[0] = VecIn1; 4626 if (VecIn2.Val) { 4627 Ops[1] = VecIn2; 4628 } else { 4629 // Use an undef build_vector as input for the second operand. 4630 std::vector<SDOperand> UnOps(NumInScalars, 4631 DAG.getNode(ISD::UNDEF, 4632 EltType)); 4633 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4634 &UnOps[0], UnOps.size()); 4635 AddToWorkList(Ops[1].Val); 4636 } 4637 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4638 &BuildVecIndices[0], BuildVecIndices.size()); 4639 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4640 } 4641 4642 return SDOperand(); 4643} 4644 4645SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4646 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4647 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4648 // inputs come from at most two distinct vectors, turn this into a shuffle 4649 // node. 4650 4651 // If we only have one input vector, we don't need to do any concatenation. 4652 if (N->getNumOperands() == 1) { 4653 return N->getOperand(0); 4654 } 4655 4656 return SDOperand(); 4657} 4658 4659SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4660 SDOperand ShufMask = N->getOperand(2); 4661 unsigned NumElts = ShufMask.getNumOperands(); 4662 4663 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4664 bool isIdentity = true; 4665 for (unsigned i = 0; i != NumElts; ++i) { 4666 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4667 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4668 isIdentity = false; 4669 break; 4670 } 4671 } 4672 if (isIdentity) return N->getOperand(0); 4673 4674 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4675 isIdentity = true; 4676 for (unsigned i = 0; i != NumElts; ++i) { 4677 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4678 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4679 isIdentity = false; 4680 break; 4681 } 4682 } 4683 if (isIdentity) return N->getOperand(1); 4684 4685 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4686 // needed at all. 4687 bool isUnary = true; 4688 bool isSplat = true; 4689 int VecNum = -1; 4690 unsigned BaseIdx = 0; 4691 for (unsigned i = 0; i != NumElts; ++i) 4692 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4693 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4694 int V = (Idx < NumElts) ? 0 : 1; 4695 if (VecNum == -1) { 4696 VecNum = V; 4697 BaseIdx = Idx; 4698 } else { 4699 if (BaseIdx != Idx) 4700 isSplat = false; 4701 if (VecNum != V) { 4702 isUnary = false; 4703 break; 4704 } 4705 } 4706 } 4707 4708 SDOperand N0 = N->getOperand(0); 4709 SDOperand N1 = N->getOperand(1); 4710 // Normalize unary shuffle so the RHS is undef. 4711 if (isUnary && VecNum == 1) 4712 std::swap(N0, N1); 4713 4714 // If it is a splat, check if the argument vector is a build_vector with 4715 // all scalar elements the same. 4716 if (isSplat) { 4717 SDNode *V = N0.Val; 4718 4719 // If this is a bit convert that changes the element type of the vector but 4720 // not the number of vector elements, look through it. Be careful not to 4721 // look though conversions that change things like v4f32 to v2f64. 4722 if (V->getOpcode() == ISD::BIT_CONVERT) { 4723 SDOperand ConvInput = V->getOperand(0); 4724 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4725 V = ConvInput.Val; 4726 } 4727 4728 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4729 unsigned NumElems = V->getNumOperands(); 4730 if (NumElems > BaseIdx) { 4731 SDOperand Base; 4732 bool AllSame = true; 4733 for (unsigned i = 0; i != NumElems; ++i) { 4734 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4735 Base = V->getOperand(i); 4736 break; 4737 } 4738 } 4739 // Splat of <u, u, u, u>, return <u, u, u, u> 4740 if (!Base.Val) 4741 return N0; 4742 for (unsigned i = 0; i != NumElems; ++i) { 4743 if (V->getOperand(i) != Base) { 4744 AllSame = false; 4745 break; 4746 } 4747 } 4748 // Splat of <x, x, x, x>, return <x, x, x, x> 4749 if (AllSame) 4750 return N0; 4751 } 4752 } 4753 } 4754 4755 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4756 // into an undef. 4757 if (isUnary || N0 == N1) { 4758 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4759 // first operand. 4760 SmallVector<SDOperand, 8> MappedOps; 4761 for (unsigned i = 0; i != NumElts; ++i) { 4762 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4763 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4764 MappedOps.push_back(ShufMask.getOperand(i)); 4765 } else { 4766 unsigned NewIdx = 4767 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4768 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4769 } 4770 } 4771 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4772 &MappedOps[0], MappedOps.size()); 4773 AddToWorkList(ShufMask.Val); 4774 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4775 N0, 4776 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4777 ShufMask); 4778 } 4779 4780 return SDOperand(); 4781} 4782 4783/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4784/// an AND to a vector_shuffle with the destination vector and a zero vector. 4785/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4786/// vector_shuffle V, Zero, <0, 4, 2, 4> 4787SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4788 SDOperand LHS = N->getOperand(0); 4789 SDOperand RHS = N->getOperand(1); 4790 if (N->getOpcode() == ISD::AND) { 4791 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4792 RHS = RHS.getOperand(0); 4793 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4794 std::vector<SDOperand> IdxOps; 4795 unsigned NumOps = RHS.getNumOperands(); 4796 unsigned NumElts = NumOps; 4797 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4798 for (unsigned i = 0; i != NumElts; ++i) { 4799 SDOperand Elt = RHS.getOperand(i); 4800 if (!isa<ConstantSDNode>(Elt)) 4801 return SDOperand(); 4802 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4803 IdxOps.push_back(DAG.getConstant(i, EVT)); 4804 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4805 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4806 else 4807 return SDOperand(); 4808 } 4809 4810 // Let's see if the target supports this vector_shuffle. 4811 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4812 return SDOperand(); 4813 4814 // Return the new VECTOR_SHUFFLE node. 4815 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4816 std::vector<SDOperand> Ops; 4817 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4818 Ops.push_back(LHS); 4819 AddToWorkList(LHS.Val); 4820 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4821 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4822 &ZeroOps[0], ZeroOps.size())); 4823 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4824 &IdxOps[0], IdxOps.size())); 4825 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4826 &Ops[0], Ops.size()); 4827 if (VT != LHS.getValueType()) { 4828 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4829 } 4830 return Result; 4831 } 4832 } 4833 return SDOperand(); 4834} 4835 4836/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4837SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4838 // After legalize, the target may be depending on adds and other 4839 // binary ops to provide legal ways to construct constants or other 4840 // things. Simplifying them may result in a loss of legality. 4841 if (AfterLegalize) return SDOperand(); 4842 4843 MVT::ValueType VT = N->getValueType(0); 4844 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4845 4846 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4847 SDOperand LHS = N->getOperand(0); 4848 SDOperand RHS = N->getOperand(1); 4849 SDOperand Shuffle = XformToShuffleWithZero(N); 4850 if (Shuffle.Val) return Shuffle; 4851 4852 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4853 // this operation. 4854 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4855 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4856 SmallVector<SDOperand, 8> Ops; 4857 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4858 SDOperand LHSOp = LHS.getOperand(i); 4859 SDOperand RHSOp = RHS.getOperand(i); 4860 // If these two elements can't be folded, bail out. 4861 if ((LHSOp.getOpcode() != ISD::UNDEF && 4862 LHSOp.getOpcode() != ISD::Constant && 4863 LHSOp.getOpcode() != ISD::ConstantFP) || 4864 (RHSOp.getOpcode() != ISD::UNDEF && 4865 RHSOp.getOpcode() != ISD::Constant && 4866 RHSOp.getOpcode() != ISD::ConstantFP)) 4867 break; 4868 // Can't fold divide by zero. 4869 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4870 N->getOpcode() == ISD::FDIV) { 4871 if ((RHSOp.getOpcode() == ISD::Constant && 4872 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4873 (RHSOp.getOpcode() == ISD::ConstantFP && 4874 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4875 break; 4876 } 4877 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4878 AddToWorkList(Ops.back().Val); 4879 assert((Ops.back().getOpcode() == ISD::UNDEF || 4880 Ops.back().getOpcode() == ISD::Constant || 4881 Ops.back().getOpcode() == ISD::ConstantFP) && 4882 "Scalar binop didn't fold!"); 4883 } 4884 4885 if (Ops.size() == LHS.getNumOperands()) { 4886 MVT::ValueType VT = LHS.getValueType(); 4887 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4888 } 4889 } 4890 4891 return SDOperand(); 4892} 4893 4894SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4895 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4896 4897 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4898 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4899 // If we got a simplified select_cc node back from SimplifySelectCC, then 4900 // break it down into a new SETCC node, and a new SELECT node, and then return 4901 // the SELECT node, since we were called with a SELECT node. 4902 if (SCC.Val) { 4903 // Check to see if we got a select_cc back (to turn into setcc/select). 4904 // Otherwise, just return whatever node we got back, like fabs. 4905 if (SCC.getOpcode() == ISD::SELECT_CC) { 4906 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4907 SCC.getOperand(0), SCC.getOperand(1), 4908 SCC.getOperand(4)); 4909 AddToWorkList(SETCC.Val); 4910 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4911 SCC.getOperand(3), SETCC); 4912 } 4913 return SCC; 4914 } 4915 return SDOperand(); 4916} 4917 4918/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4919/// are the two values being selected between, see if we can simplify the 4920/// select. Callers of this should assume that TheSelect is deleted if this 4921/// returns true. As such, they should return the appropriate thing (e.g. the 4922/// node) back to the top-level of the DAG combiner loop to avoid it being 4923/// looked at. 4924/// 4925bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4926 SDOperand RHS) { 4927 4928 // If this is a select from two identical things, try to pull the operation 4929 // through the select. 4930 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4931 // If this is a load and the token chain is identical, replace the select 4932 // of two loads with a load through a select of the address to load from. 4933 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4934 // constants have been dropped into the constant pool. 4935 if (LHS.getOpcode() == ISD::LOAD && 4936 // Token chains must be identical. 4937 LHS.getOperand(0) == RHS.getOperand(0)) { 4938 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4939 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4940 4941 // If this is an EXTLOAD, the VT's must match. 4942 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4943 // FIXME: this conflates two src values, discarding one. This is not 4944 // the right thing to do, but nothing uses srcvalues now. When they do, 4945 // turn SrcValue into a list of locations. 4946 SDOperand Addr; 4947 if (TheSelect->getOpcode() == ISD::SELECT) { 4948 // Check that the condition doesn't reach either load. If so, folding 4949 // this will induce a cycle into the DAG. 4950 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4951 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4952 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4953 TheSelect->getOperand(0), LLD->getBasePtr(), 4954 RLD->getBasePtr()); 4955 } 4956 } else { 4957 // Check that the condition doesn't reach either load. If so, folding 4958 // this will induce a cycle into the DAG. 4959 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4960 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4961 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4962 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4963 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4964 TheSelect->getOperand(0), 4965 TheSelect->getOperand(1), 4966 LLD->getBasePtr(), RLD->getBasePtr(), 4967 TheSelect->getOperand(4)); 4968 } 4969 } 4970 4971 if (Addr.Val) { 4972 SDOperand Load; 4973 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4974 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4975 Addr,LLD->getSrcValue(), 4976 LLD->getSrcValueOffset(), 4977 LLD->isVolatile(), 4978 LLD->getAlignment()); 4979 else { 4980 Load = DAG.getExtLoad(LLD->getExtensionType(), 4981 TheSelect->getValueType(0), 4982 LLD->getChain(), Addr, LLD->getSrcValue(), 4983 LLD->getSrcValueOffset(), 4984 LLD->getLoadedVT(), 4985 LLD->isVolatile(), 4986 LLD->getAlignment()); 4987 } 4988 // Users of the select now use the result of the load. 4989 CombineTo(TheSelect, Load); 4990 4991 // Users of the old loads now use the new load's chain. We know the 4992 // old-load value is dead now. 4993 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4994 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4995 return true; 4996 } 4997 } 4998 } 4999 } 5000 5001 return false; 5002} 5003 5004SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 5005 SDOperand N2, SDOperand N3, 5006 ISD::CondCode CC, bool NotExtCompare) { 5007 5008 MVT::ValueType VT = N2.getValueType(); 5009 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5010 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5011 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5012 5013 // Determine if the condition we're dealing with is constant 5014 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 5015 if (SCC.Val) AddToWorkList(SCC.Val); 5016 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5017 5018 // fold select_cc true, x, y -> x 5019 if (SCCC && SCCC->getValue()) 5020 return N2; 5021 // fold select_cc false, x, y -> y 5022 if (SCCC && SCCC->getValue() == 0) 5023 return N3; 5024 5025 // Check to see if we can simplify the select into an fabs node 5026 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5027 // Allow either -0.0 or 0.0 5028 if (CFP->getValueAPF().isZero()) { 5029 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5030 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5031 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5032 N2 == N3.getOperand(0)) 5033 return DAG.getNode(ISD::FABS, VT, N0); 5034 5035 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5036 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5037 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5038 N2.getOperand(0) == N3) 5039 return DAG.getNode(ISD::FABS, VT, N3); 5040 } 5041 } 5042 5043 // Check to see if we can perform the "gzip trick", transforming 5044 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5045 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5046 MVT::isInteger(N0.getValueType()) && 5047 MVT::isInteger(N2.getValueType()) && 5048 (N1C->isNullValue() || // (a < 0) ? b : 0 5049 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5050 MVT::ValueType XType = N0.getValueType(); 5051 MVT::ValueType AType = N2.getValueType(); 5052 if (XType >= AType) { 5053 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5054 // single-bit constant. 5055 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 5056 unsigned ShCtV = Log2_64(N2C->getValue()); 5057 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 5058 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5059 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5060 AddToWorkList(Shift.Val); 5061 if (XType > AType) { 5062 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5063 AddToWorkList(Shift.Val); 5064 } 5065 return DAG.getNode(ISD::AND, AType, Shift, N2); 5066 } 5067 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5068 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5069 TLI.getShiftAmountTy())); 5070 AddToWorkList(Shift.Val); 5071 if (XType > AType) { 5072 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5073 AddToWorkList(Shift.Val); 5074 } 5075 return DAG.getNode(ISD::AND, AType, Shift, N2); 5076 } 5077 } 5078 5079 // fold select C, 16, 0 -> shl C, 4 5080 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 5081 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5082 5083 // If the caller doesn't want us to simplify this into a zext of a compare, 5084 // don't do it. 5085 if (NotExtCompare && N2C->getValue() == 1) 5086 return SDOperand(); 5087 5088 // Get a SetCC of the condition 5089 // FIXME: Should probably make sure that setcc is legal if we ever have a 5090 // target where it isn't. 5091 SDOperand Temp, SCC; 5092 // cast from setcc result type to select result type 5093 if (AfterLegalize) { 5094 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 5095 if (N2.getValueType() < SCC.getValueType()) 5096 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5097 else 5098 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5099 } else { 5100 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5101 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5102 } 5103 AddToWorkList(SCC.Val); 5104 AddToWorkList(Temp.Val); 5105 5106 if (N2C->getValue() == 1) 5107 return Temp; 5108 // shl setcc result by log2 n2c 5109 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5110 DAG.getConstant(Log2_64(N2C->getValue()), 5111 TLI.getShiftAmountTy())); 5112 } 5113 5114 // Check to see if this is the equivalent of setcc 5115 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5116 // otherwise, go ahead with the folds. 5117 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 5118 MVT::ValueType XType = N0.getValueType(); 5119 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 5120 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 5121 if (Res.getValueType() != VT) 5122 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5123 return Res; 5124 } 5125 5126 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5127 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5128 TLI.isOperationLegal(ISD::CTLZ, XType)) { 5129 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5130 return DAG.getNode(ISD::SRL, XType, Ctlz, 5131 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 5132 TLI.getShiftAmountTy())); 5133 } 5134 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5135 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5136 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5137 N0); 5138 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5139 DAG.getConstant(~0ULL, XType)); 5140 return DAG.getNode(ISD::SRL, XType, 5141 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5142 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5143 TLI.getShiftAmountTy())); 5144 } 5145 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5146 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5147 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5148 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5149 TLI.getShiftAmountTy())); 5150 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5151 } 5152 } 5153 5154 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5155 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5156 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5157 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5158 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 5159 MVT::ValueType XType = N0.getValueType(); 5160 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5161 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5162 TLI.getShiftAmountTy())); 5163 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5164 AddToWorkList(Shift.Val); 5165 AddToWorkList(Add.Val); 5166 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5167 } 5168 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5169 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5170 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5171 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5172 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5173 MVT::ValueType XType = N0.getValueType(); 5174 if (SubC->isNullValue() && MVT::isInteger(XType)) { 5175 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5176 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5177 TLI.getShiftAmountTy())); 5178 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5179 AddToWorkList(Shift.Val); 5180 AddToWorkList(Add.Val); 5181 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5182 } 5183 } 5184 } 5185 5186 return SDOperand(); 5187} 5188 5189/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5190SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 5191 SDOperand N1, ISD::CondCode Cond, 5192 bool foldBooleans) { 5193 TargetLowering::DAGCombinerInfo 5194 DagCombineInfo(DAG, !AfterLegalize, false, this); 5195 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5196} 5197 5198/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5199/// return a DAG expression to select that will generate the same value by 5200/// multiplying by a magic number. See: 5201/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5202SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5203 std::vector<SDNode*> Built; 5204 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5205 5206 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5207 ii != ee; ++ii) 5208 AddToWorkList(*ii); 5209 return S; 5210} 5211 5212/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5213/// return a DAG expression to select that will generate the same value by 5214/// multiplying by a magic number. See: 5215/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5216SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5217 std::vector<SDNode*> Built; 5218 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5219 5220 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5221 ii != ee; ++ii) 5222 AddToWorkList(*ii); 5223 return S; 5224} 5225 5226/// FindBaseOffset - Return true if base is known not to alias with anything 5227/// but itself. Provides base object and offset as results. 5228static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5229 // Assume it is a primitive operation. 5230 Base = Ptr; Offset = 0; 5231 5232 // If it's an adding a simple constant then integrate the offset. 5233 if (Base.getOpcode() == ISD::ADD) { 5234 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5235 Base = Base.getOperand(0); 5236 Offset += C->getValue(); 5237 } 5238 } 5239 5240 // If it's any of the following then it can't alias with anything but itself. 5241 return isa<FrameIndexSDNode>(Base) || 5242 isa<ConstantPoolSDNode>(Base) || 5243 isa<GlobalAddressSDNode>(Base); 5244} 5245 5246/// isAlias - Return true if there is any possibility that the two addresses 5247/// overlap. 5248bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5249 const Value *SrcValue1, int SrcValueOffset1, 5250 SDOperand Ptr2, int64_t Size2, 5251 const Value *SrcValue2, int SrcValueOffset2) 5252{ 5253 // If they are the same then they must be aliases. 5254 if (Ptr1 == Ptr2) return true; 5255 5256 // Gather base node and offset information. 5257 SDOperand Base1, Base2; 5258 int64_t Offset1, Offset2; 5259 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5260 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5261 5262 // If they have a same base address then... 5263 if (Base1 == Base2) { 5264 // Check to see if the addresses overlap. 5265 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5266 } 5267 5268 // If we know both bases then they can't alias. 5269 if (KnownBase1 && KnownBase2) return false; 5270 5271 if (CombinerGlobalAA) { 5272 // Use alias analysis information. 5273 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5274 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5275 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5276 AliasAnalysis::AliasResult AAResult = 5277 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5278 if (AAResult == AliasAnalysis::NoAlias) 5279 return false; 5280 } 5281 5282 // Otherwise we have to assume they alias. 5283 return true; 5284} 5285 5286/// FindAliasInfo - Extracts the relevant alias information from the memory 5287/// node. Returns true if the operand was a load. 5288bool DAGCombiner::FindAliasInfo(SDNode *N, 5289 SDOperand &Ptr, int64_t &Size, 5290 const Value *&SrcValue, int &SrcValueOffset) { 5291 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5292 Ptr = LD->getBasePtr(); 5293 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 5294 SrcValue = LD->getSrcValue(); 5295 SrcValueOffset = LD->getSrcValueOffset(); 5296 return true; 5297 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5298 Ptr = ST->getBasePtr(); 5299 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 5300 SrcValue = ST->getSrcValue(); 5301 SrcValueOffset = ST->getSrcValueOffset(); 5302 } else { 5303 assert(0 && "FindAliasInfo expected a memory operand"); 5304 } 5305 5306 return false; 5307} 5308 5309/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5310/// looking for aliasing nodes and adding them to the Aliases vector. 5311void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5312 SmallVector<SDOperand, 8> &Aliases) { 5313 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5314 std::set<SDNode *> Visited; // Visited node set. 5315 5316 // Get alias information for node. 5317 SDOperand Ptr; 5318 int64_t Size; 5319 const Value *SrcValue; 5320 int SrcValueOffset; 5321 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5322 5323 // Starting off. 5324 Chains.push_back(OriginalChain); 5325 5326 // Look at each chain and determine if it is an alias. If so, add it to the 5327 // aliases list. If not, then continue up the chain looking for the next 5328 // candidate. 5329 while (!Chains.empty()) { 5330 SDOperand Chain = Chains.back(); 5331 Chains.pop_back(); 5332 5333 // Don't bother if we've been before. 5334 if (Visited.find(Chain.Val) != Visited.end()) continue; 5335 Visited.insert(Chain.Val); 5336 5337 switch (Chain.getOpcode()) { 5338 case ISD::EntryToken: 5339 // Entry token is ideal chain operand, but handled in FindBetterChain. 5340 break; 5341 5342 case ISD::LOAD: 5343 case ISD::STORE: { 5344 // Get alias information for Chain. 5345 SDOperand OpPtr; 5346 int64_t OpSize; 5347 const Value *OpSrcValue; 5348 int OpSrcValueOffset; 5349 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5350 OpSrcValue, OpSrcValueOffset); 5351 5352 // If chain is alias then stop here. 5353 if (!(IsLoad && IsOpLoad) && 5354 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5355 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5356 Aliases.push_back(Chain); 5357 } else { 5358 // Look further up the chain. 5359 Chains.push_back(Chain.getOperand(0)); 5360 // Clean up old chain. 5361 AddToWorkList(Chain.Val); 5362 } 5363 break; 5364 } 5365 5366 case ISD::TokenFactor: 5367 // We have to check each of the operands of the token factor, so we queue 5368 // then up. Adding the operands to the queue (stack) in reverse order 5369 // maintains the original order and increases the likelihood that getNode 5370 // will find a matching token factor (CSE.) 5371 for (unsigned n = Chain.getNumOperands(); n;) 5372 Chains.push_back(Chain.getOperand(--n)); 5373 // Eliminate the token factor if we can. 5374 AddToWorkList(Chain.Val); 5375 break; 5376 5377 default: 5378 // For all other instructions we will just have to take what we can get. 5379 Aliases.push_back(Chain); 5380 break; 5381 } 5382 } 5383} 5384 5385/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5386/// for a better chain (aliasing node.) 5387SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5388 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5389 5390 // Accumulate all the aliases to this node. 5391 GatherAllAliases(N, OldChain, Aliases); 5392 5393 if (Aliases.size() == 0) { 5394 // If no operands then chain to entry token. 5395 return DAG.getEntryNode(); 5396 } else if (Aliases.size() == 1) { 5397 // If a single operand then chain to it. We don't need to revisit it. 5398 return Aliases[0]; 5399 } 5400 5401 // Construct a custom tailored token factor. 5402 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5403 &Aliases[0], Aliases.size()); 5404 5405 // Make sure the old chain gets cleaned up. 5406 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5407 5408 return NewChain; 5409} 5410 5411// SelectionDAG::Combine - This is the entry point for the file. 5412// 5413void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5414 if (!RunningAfterLegalize && ViewDAGCombine1) 5415 viewGraph(); 5416 if (RunningAfterLegalize && ViewDAGCombine2) 5417 viewGraph(); 5418 /// run - This is the main entry point to this class. 5419 /// 5420 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5421} 5422