DAGCombiner.cpp revision 35247c35136232bb30aa17543dbcf9c92fa24d29
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 const TargetLowering &TLI; 53 CombineLevel Level; 54 bool LegalOperations; 55 bool LegalTypes; 56 bool Fast; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 // AA - Used for DAG load/store alias analysis. 62 AliasAnalysis &AA; 63 64 /// AddUsersToWorkList - When an instruction is simplified, add all users of 65 /// the instruction to the work lists because they might get more simplified 66 /// now. 67 /// 68 void AddUsersToWorkList(SDNode *N) { 69 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 70 UI != UE; ++UI) 71 AddToWorkList(*UI); 72 } 73 74 /// visit - call the node-specific routine that knows how to fold each 75 /// particular type of node. 76 SDValue visit(SDNode *N); 77 78 public: 79 /// AddToWorkList - Add to the work list making sure it's instance is at the 80 /// the back (next to be processed.) 81 void AddToWorkList(SDNode *N) { 82 removeFromWorkList(N); 83 WorkList.push_back(N); 84 } 85 86 /// removeFromWorkList - remove all instances of N from the worklist. 87 /// 88 void removeFromWorkList(SDNode *N) { 89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 90 WorkList.end()); 91 } 92 93 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 94 bool AddTo = true); 95 96 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 97 return CombineTo(N, &Res, 1, AddTo); 98 } 99 100 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 101 bool AddTo = true) { 102 SDValue To[] = { Res0, Res1 }; 103 return CombineTo(N, To, 2, AddTo); 104 } 105 106 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 107 108 private: 109 110 /// SimplifyDemandedBits - Check the specified integer node value to see if 111 /// it can be simplified or if things it uses can be simplified by bit 112 /// propagation. If so, return true. 113 bool SimplifyDemandedBits(SDValue Op) { 114 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 115 return SimplifyDemandedBits(Op, Demanded); 116 } 117 118 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 119 120 bool CombineToPreIndexedLoadStore(SDNode *N); 121 bool CombineToPostIndexedLoadStore(SDNode *N); 122 123 124 /// combine - call the node-specific routine that knows how to fold each 125 /// particular type of node. If that doesn't do anything, try the 126 /// target-specific DAG combines. 127 SDValue combine(SDNode *N); 128 129 // Visitation implementation - Implement dag node combining for different 130 // node types. The semantics are as follows: 131 // Return Value: 132 // SDValue.getNode() == 0 - No change was made 133 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 134 // otherwise - N should be replaced by the returned Operand. 135 // 136 SDValue visitTokenFactor(SDNode *N); 137 SDValue visitMERGE_VALUES(SDNode *N); 138 SDValue visitADD(SDNode *N); 139 SDValue visitSUB(SDNode *N); 140 SDValue visitADDC(SDNode *N); 141 SDValue visitADDE(SDNode *N); 142 SDValue visitMUL(SDNode *N); 143 SDValue visitSDIV(SDNode *N); 144 SDValue visitUDIV(SDNode *N); 145 SDValue visitSREM(SDNode *N); 146 SDValue visitUREM(SDNode *N); 147 SDValue visitMULHU(SDNode *N); 148 SDValue visitMULHS(SDNode *N); 149 SDValue visitSMUL_LOHI(SDNode *N); 150 SDValue visitUMUL_LOHI(SDNode *N); 151 SDValue visitSDIVREM(SDNode *N); 152 SDValue visitUDIVREM(SDNode *N); 153 SDValue visitAND(SDNode *N); 154 SDValue visitOR(SDNode *N); 155 SDValue visitXOR(SDNode *N); 156 SDValue SimplifyVBinOp(SDNode *N); 157 SDValue visitSHL(SDNode *N); 158 SDValue visitSRA(SDNode *N); 159 SDValue visitSRL(SDNode *N); 160 SDValue visitCTLZ(SDNode *N); 161 SDValue visitCTTZ(SDNode *N); 162 SDValue visitCTPOP(SDNode *N); 163 SDValue visitSELECT(SDNode *N); 164 SDValue visitSELECT_CC(SDNode *N); 165 SDValue visitSETCC(SDNode *N); 166 SDValue visitSIGN_EXTEND(SDNode *N); 167 SDValue visitZERO_EXTEND(SDNode *N); 168 SDValue visitANY_EXTEND(SDNode *N); 169 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 170 SDValue visitTRUNCATE(SDNode *N); 171 SDValue visitBIT_CONVERT(SDNode *N); 172 SDValue visitBUILD_PAIR(SDNode *N); 173 SDValue visitFADD(SDNode *N); 174 SDValue visitFSUB(SDNode *N); 175 SDValue visitFMUL(SDNode *N); 176 SDValue visitFDIV(SDNode *N); 177 SDValue visitFREM(SDNode *N); 178 SDValue visitFCOPYSIGN(SDNode *N); 179 SDValue visitSINT_TO_FP(SDNode *N); 180 SDValue visitUINT_TO_FP(SDNode *N); 181 SDValue visitFP_TO_SINT(SDNode *N); 182 SDValue visitFP_TO_UINT(SDNode *N); 183 SDValue visitFP_ROUND(SDNode *N); 184 SDValue visitFP_ROUND_INREG(SDNode *N); 185 SDValue visitFP_EXTEND(SDNode *N); 186 SDValue visitFNEG(SDNode *N); 187 SDValue visitFABS(SDNode *N); 188 SDValue visitBRCOND(SDNode *N); 189 SDValue visitBR_CC(SDNode *N); 190 SDValue visitLOAD(SDNode *N); 191 SDValue visitSTORE(SDNode *N); 192 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 193 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 194 SDValue visitBUILD_VECTOR(SDNode *N); 195 SDValue visitCONCAT_VECTORS(SDNode *N); 196 SDValue visitVECTOR_SHUFFLE(SDNode *N); 197 198 SDValue XformToShuffleWithZero(SDNode *N); 199 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 200 201 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 202 203 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 204 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 205 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 206 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 207 SDValue N3, ISD::CondCode CC, 208 bool NotExtCompare = false); 209 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 210 bool foldBooleans = true); 211 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 212 unsigned HiOp); 213 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 214 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 215 SDValue BuildSDIV(SDNode *N); 216 SDValue BuildUDIV(SDNode *N); 217 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 218 SDValue ReduceLoadWidth(SDNode *N); 219 220 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 221 222 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 223 /// looking for aliasing nodes and adding them to the Aliases vector. 224 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 225 SmallVector<SDValue, 8> &Aliases); 226 227 /// isAlias - Return true if there is any possibility that the two addresses 228 /// overlap. 229 bool isAlias(SDValue Ptr1, int64_t Size1, 230 const Value *SrcValue1, int SrcValueOffset1, 231 SDValue Ptr2, int64_t Size2, 232 const Value *SrcValue2, int SrcValueOffset2); 233 234 /// FindAliasInfo - Extracts the relevant alias information from the memory 235 /// node. Returns true if the operand was a load. 236 bool FindAliasInfo(SDNode *N, 237 SDValue &Ptr, int64_t &Size, 238 const Value *&SrcValue, int &SrcValueOffset); 239 240 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 241 /// looking for a better chain (aliasing node.) 242 SDValue FindBetterChain(SDNode *N, SDValue Chain); 243 244public: 245 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 246 : DAG(D), 247 TLI(D.getTargetLoweringInfo()), 248 Level(Unrestricted), 249 LegalOperations(false), 250 LegalTypes(false), 251 Fast(fast), 252 AA(A) {} 253 254 /// Run - runs the dag combiner on all nodes in the work list 255 void Run(CombineLevel AtLevel); 256 }; 257} 258 259 260namespace { 261/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 262/// nodes from the worklist. 263class VISIBILITY_HIDDEN WorkListRemover : 264 public SelectionDAG::DAGUpdateListener { 265 DAGCombiner &DC; 266public: 267 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 268 269 virtual void NodeDeleted(SDNode *N, SDNode *E) { 270 DC.removeFromWorkList(N); 271 } 272 273 virtual void NodeUpdated(SDNode *N) { 274 // Ignore updates. 275 } 276}; 277} 278 279//===----------------------------------------------------------------------===// 280// TargetLowering::DAGCombinerInfo implementation 281//===----------------------------------------------------------------------===// 282 283void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 284 ((DAGCombiner*)DC)->AddToWorkList(N); 285} 286 287SDValue TargetLowering::DAGCombinerInfo:: 288CombineTo(SDNode *N, const std::vector<SDValue> &To) { 289 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 290} 291 292SDValue TargetLowering::DAGCombinerInfo:: 293CombineTo(SDNode *N, SDValue Res) { 294 return ((DAGCombiner*)DC)->CombineTo(N, Res); 295} 296 297 298SDValue TargetLowering::DAGCombinerInfo:: 299CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 300 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 301} 302 303void TargetLowering::DAGCombinerInfo:: 304CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 305 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 306} 307 308//===----------------------------------------------------------------------===// 309// Helper Functions 310//===----------------------------------------------------------------------===// 311 312/// isNegatibleForFree - Return 1 if we can compute the negated form of the 313/// specified expression for the same cost as the expression itself, or 2 if we 314/// can compute the negated form more cheaply than the expression itself. 315static char isNegatibleForFree(SDValue Op, bool LegalOperations, 316 unsigned Depth = 0) { 317 // No compile time optimizations on this type. 318 if (Op.getValueType() == MVT::ppcf128) 319 return 0; 320 321 // fneg is removable even if it has multiple uses. 322 if (Op.getOpcode() == ISD::FNEG) return 2; 323 324 // Don't allow anything with multiple uses. 325 if (!Op.hasOneUse()) return 0; 326 327 // Don't recurse exponentially. 328 if (Depth > 6) return 0; 329 330 switch (Op.getOpcode()) { 331 default: return false; 332 case ISD::ConstantFP: 333 // Don't invert constant FP values after legalize. The negated constant 334 // isn't necessarily legal. 335 return LegalOperations ? 0 : 1; 336 case ISD::FADD: 337 // FIXME: determine better conditions for this xform. 338 if (!UnsafeFPMath) return 0; 339 340 // -(A+B) -> -A - B 341 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 342 return V; 343 // -(A+B) -> -B - A 344 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 345 case ISD::FSUB: 346 // We can't turn -(A-B) into B-A when we honor signed zeros. 347 if (!UnsafeFPMath) return 0; 348 349 // -(A-B) -> B-A 350 return 1; 351 352 case ISD::FMUL: 353 case ISD::FDIV: 354 if (HonorSignDependentRoundingFPMath()) return 0; 355 356 // -(X*Y) -> (-X * Y) or (X*-Y) 357 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 358 return V; 359 360 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 361 362 case ISD::FP_EXTEND: 363 case ISD::FP_ROUND: 364 case ISD::FSIN: 365 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 366 } 367} 368 369/// GetNegatedExpression - If isNegatibleForFree returns true, this function 370/// returns the newly negated expression. 371static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 372 bool LegalOperations, unsigned Depth = 0) { 373 // fneg is removable even if it has multiple uses. 374 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 375 376 // Don't allow anything with multiple uses. 377 assert(Op.hasOneUse() && "Unknown reuse!"); 378 379 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 380 switch (Op.getOpcode()) { 381 default: assert(0 && "Unknown code"); 382 case ISD::ConstantFP: { 383 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 384 V.changeSign(); 385 return DAG.getConstantFP(V, Op.getValueType()); 386 } 387 case ISD::FADD: 388 // FIXME: determine better conditions for this xform. 389 assert(UnsafeFPMath); 390 391 // -(A+B) -> -A - B 392 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 393 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 394 GetNegatedExpression(Op.getOperand(0), DAG, 395 LegalOperations, Depth+1), 396 Op.getOperand(1)); 397 // -(A+B) -> -B - A 398 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 399 GetNegatedExpression(Op.getOperand(1), DAG, 400 LegalOperations, Depth+1), 401 Op.getOperand(0)); 402 case ISD::FSUB: 403 // We can't turn -(A-B) into B-A when we honor signed zeros. 404 assert(UnsafeFPMath); 405 406 // -(0-B) -> B 407 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 408 if (N0CFP->getValueAPF().isZero()) 409 return Op.getOperand(1); 410 411 // -(A-B) -> B-A 412 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 413 Op.getOperand(1), Op.getOperand(0)); 414 415 case ISD::FMUL: 416 case ISD::FDIV: 417 assert(!HonorSignDependentRoundingFPMath()); 418 419 // -(X*Y) -> -X * Y 420 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 421 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 422 GetNegatedExpression(Op.getOperand(0), DAG, 423 LegalOperations, Depth+1), 424 Op.getOperand(1)); 425 426 // -(X*Y) -> X * -Y 427 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 428 Op.getOperand(0), 429 GetNegatedExpression(Op.getOperand(1), DAG, 430 LegalOperations, Depth+1)); 431 432 case ISD::FP_EXTEND: 433 case ISD::FSIN: 434 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 435 GetNegatedExpression(Op.getOperand(0), DAG, 436 LegalOperations, Depth+1)); 437 case ISD::FP_ROUND: 438 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 439 GetNegatedExpression(Op.getOperand(0), DAG, 440 LegalOperations, Depth+1), 441 Op.getOperand(1)); 442 } 443} 444 445 446// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 447// that selects between the values 1 and 0, making it equivalent to a setcc. 448// Also, set the incoming LHS, RHS, and CC references to the appropriate 449// nodes based on the type of node we are checking. This simplifies life a 450// bit for the callers. 451static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 452 SDValue &CC) { 453 if (N.getOpcode() == ISD::SETCC) { 454 LHS = N.getOperand(0); 455 RHS = N.getOperand(1); 456 CC = N.getOperand(2); 457 return true; 458 } 459 if (N.getOpcode() == ISD::SELECT_CC && 460 N.getOperand(2).getOpcode() == ISD::Constant && 461 N.getOperand(3).getOpcode() == ISD::Constant && 462 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 463 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 464 LHS = N.getOperand(0); 465 RHS = N.getOperand(1); 466 CC = N.getOperand(4); 467 return true; 468 } 469 return false; 470} 471 472// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 473// one use. If this is true, it allows the users to invert the operation for 474// free when it is profitable to do so. 475static bool isOneUseSetCC(SDValue N) { 476 SDValue N0, N1, N2; 477 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 478 return true; 479 return false; 480} 481 482SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 483 SDValue N0, SDValue N1) { 484 MVT VT = N0.getValueType(); 485 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 486 if (isa<ConstantSDNode>(N1)) { 487 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 488 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 489 N0.getOperand(1), N1); 490 AddToWorkList(OpNode.getNode()); 491 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(0)); 492 } else if (N0.hasOneUse()) { 493 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 494 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 495 N0.getOperand(0), N1); 496 AddToWorkList(OpNode.getNode()); 497 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 498 } 499 } 500 501 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 502 if (isa<ConstantSDNode>(N0)) { 503 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 504 SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT, 505 N1.getOperand(1), N0); 506 AddToWorkList(OpNode.getNode()); 507 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(0)); 508 } else if (N1.hasOneUse()) { 509 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 510 SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT, 511 N1.getOperand(0), N0); 512 AddToWorkList(OpNode.getNode()); 513 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 514 } 515 } 516 517 return SDValue(); 518} 519 520SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 521 bool AddTo) { 522 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 523 ++NodesCombined; 524 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 525 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 526 DOUT << " and " << NumTo-1 << " other values\n"; 527 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 528 assert(N->getValueType(i) == To[i].getValueType() && 529 "Cannot combine value to value of different type!")); 530 WorkListRemover DeadNodes(*this); 531 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 532 533 if (AddTo) { 534 // Push the new nodes and any users onto the worklist 535 for (unsigned i = 0, e = NumTo; i != e; ++i) { 536 AddToWorkList(To[i].getNode()); 537 AddUsersToWorkList(To[i].getNode()); 538 } 539 } 540 541 // Finally, if the node is now dead, remove it from the graph. The node 542 // may not be dead if the replacement process recursively simplified to 543 // something else needing this node. 544 if (N->use_empty()) { 545 // Nodes can be reintroduced into the worklist. Make sure we do not 546 // process a node that has been replaced. 547 removeFromWorkList(N); 548 549 // Finally, since the node is now dead, remove it from the graph. 550 DAG.DeleteNode(N); 551 } 552 return SDValue(N, 0); 553} 554 555void 556DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 557 TLO) { 558 // Replace all uses. If any nodes become isomorphic to other nodes and 559 // are deleted, make sure to remove them from our worklist. 560 WorkListRemover DeadNodes(*this); 561 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 562 563 // Push the new node and any (possibly new) users onto the worklist. 564 AddToWorkList(TLO.New.getNode()); 565 AddUsersToWorkList(TLO.New.getNode()); 566 567 // Finally, if the node is now dead, remove it from the graph. The node 568 // may not be dead if the replacement process recursively simplified to 569 // something else needing this node. 570 if (TLO.Old.getNode()->use_empty()) { 571 removeFromWorkList(TLO.Old.getNode()); 572 573 // If the operands of this node are only used by the node, they will now 574 // be dead. Make sure to visit them first to delete dead nodes early. 575 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 576 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 577 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 578 579 DAG.DeleteNode(TLO.Old.getNode()); 580 } 581} 582 583/// SimplifyDemandedBits - Check the specified integer node value to see if 584/// it can be simplified or if things it uses can be simplified by bit 585/// propagation. If so, return true. 586bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 587 TargetLowering::TargetLoweringOpt TLO(DAG); 588 APInt KnownZero, KnownOne; 589 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 590 return false; 591 592 // Revisit the node. 593 AddToWorkList(Op.getNode()); 594 595 // Replace the old value with the new one. 596 ++NodesCombined; 597 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 598 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 599 DOUT << '\n'; 600 601 CommitTargetLoweringOpt(TLO); 602 return true; 603} 604 605//===----------------------------------------------------------------------===// 606// Main DAG Combiner implementation 607//===----------------------------------------------------------------------===// 608 609void DAGCombiner::Run(CombineLevel AtLevel) { 610 // set the instance variables, so that the various visit routines may use it. 611 Level = AtLevel; 612 LegalOperations = Level >= NoIllegalOperations; 613 LegalTypes = Level >= NoIllegalTypes; 614 615 // Add all the dag nodes to the worklist. 616 WorkList.reserve(DAG.allnodes_size()); 617 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 618 E = DAG.allnodes_end(); I != E; ++I) 619 WorkList.push_back(I); 620 621 // Create a dummy node (which is not added to allnodes), that adds a reference 622 // to the root node, preventing it from being deleted, and tracking any 623 // changes of the root. 624 HandleSDNode Dummy(DAG.getRoot()); 625 626 // The root of the dag may dangle to deleted nodes until the dag combiner is 627 // done. Set it to null to avoid confusion. 628 DAG.setRoot(SDValue()); 629 630 // while the worklist isn't empty, inspect the node on the end of it and 631 // try and combine it. 632 while (!WorkList.empty()) { 633 SDNode *N = WorkList.back(); 634 WorkList.pop_back(); 635 636 // If N has no uses, it is dead. Make sure to revisit all N's operands once 637 // N is deleted from the DAG, since they too may now be dead or may have a 638 // reduced number of uses, allowing other xforms. 639 if (N->use_empty() && N != &Dummy) { 640 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 641 AddToWorkList(N->getOperand(i).getNode()); 642 643 DAG.DeleteNode(N); 644 continue; 645 } 646 647 SDValue RV = combine(N); 648 649 if (RV.getNode() == 0) 650 continue; 651 652 ++NodesCombined; 653 654 // If we get back the same node we passed in, rather than a new node or 655 // zero, we know that the node must have defined multiple values and 656 // CombineTo was used. Since CombineTo takes care of the worklist 657 // mechanics for us, we have no work to do in this case. 658 if (RV.getNode() == N) 659 continue; 660 661 assert(N->getOpcode() != ISD::DELETED_NODE && 662 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 663 "Node was deleted but visit returned new node!"); 664 665 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 666 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 667 DOUT << '\n'; 668 WorkListRemover DeadNodes(*this); 669 if (N->getNumValues() == RV.getNode()->getNumValues()) 670 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 671 else { 672 assert(N->getValueType(0) == RV.getValueType() && 673 N->getNumValues() == 1 && "Type mismatch"); 674 SDValue OpV = RV; 675 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 676 } 677 678 // Push the new node and any users onto the worklist 679 AddToWorkList(RV.getNode()); 680 AddUsersToWorkList(RV.getNode()); 681 682 // Add any uses of the old node to the worklist in case this node is the 683 // last one that uses them. They may become dead after this node is 684 // deleted. 685 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 686 AddToWorkList(N->getOperand(i).getNode()); 687 688 // Finally, if the node is now dead, remove it from the graph. The node 689 // may not be dead if the replacement process recursively simplified to 690 // something else needing this node. 691 if (N->use_empty()) { 692 // Nodes can be reintroduced into the worklist. Make sure we do not 693 // process a node that has been replaced. 694 removeFromWorkList(N); 695 696 // Finally, since the node is now dead, remove it from the graph. 697 DAG.DeleteNode(N); 698 } 699 } 700 701 // If the root changed (e.g. it was a dead load, update the root). 702 DAG.setRoot(Dummy.getValue()); 703} 704 705SDValue DAGCombiner::visit(SDNode *N) { 706 switch(N->getOpcode()) { 707 default: break; 708 case ISD::TokenFactor: return visitTokenFactor(N); 709 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 710 case ISD::ADD: return visitADD(N); 711 case ISD::SUB: return visitSUB(N); 712 case ISD::ADDC: return visitADDC(N); 713 case ISD::ADDE: return visitADDE(N); 714 case ISD::MUL: return visitMUL(N); 715 case ISD::SDIV: return visitSDIV(N); 716 case ISD::UDIV: return visitUDIV(N); 717 case ISD::SREM: return visitSREM(N); 718 case ISD::UREM: return visitUREM(N); 719 case ISD::MULHU: return visitMULHU(N); 720 case ISD::MULHS: return visitMULHS(N); 721 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 722 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 723 case ISD::SDIVREM: return visitSDIVREM(N); 724 case ISD::UDIVREM: return visitUDIVREM(N); 725 case ISD::AND: return visitAND(N); 726 case ISD::OR: return visitOR(N); 727 case ISD::XOR: return visitXOR(N); 728 case ISD::SHL: return visitSHL(N); 729 case ISD::SRA: return visitSRA(N); 730 case ISD::SRL: return visitSRL(N); 731 case ISD::CTLZ: return visitCTLZ(N); 732 case ISD::CTTZ: return visitCTTZ(N); 733 case ISD::CTPOP: return visitCTPOP(N); 734 case ISD::SELECT: return visitSELECT(N); 735 case ISD::SELECT_CC: return visitSELECT_CC(N); 736 case ISD::SETCC: return visitSETCC(N); 737 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 738 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 739 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 740 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 741 case ISD::TRUNCATE: return visitTRUNCATE(N); 742 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 743 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 744 case ISD::FADD: return visitFADD(N); 745 case ISD::FSUB: return visitFSUB(N); 746 case ISD::FMUL: return visitFMUL(N); 747 case ISD::FDIV: return visitFDIV(N); 748 case ISD::FREM: return visitFREM(N); 749 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 750 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 751 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 752 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 753 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 754 case ISD::FP_ROUND: return visitFP_ROUND(N); 755 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 756 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 757 case ISD::FNEG: return visitFNEG(N); 758 case ISD::FABS: return visitFABS(N); 759 case ISD::BRCOND: return visitBRCOND(N); 760 case ISD::BR_CC: return visitBR_CC(N); 761 case ISD::LOAD: return visitLOAD(N); 762 case ISD::STORE: return visitSTORE(N); 763 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 764 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 765 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 766 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 767 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 768 } 769 return SDValue(); 770} 771 772SDValue DAGCombiner::combine(SDNode *N) { 773 774 SDValue RV = visit(N); 775 776 // If nothing happened, try a target-specific DAG combine. 777 if (RV.getNode() == 0) { 778 assert(N->getOpcode() != ISD::DELETED_NODE && 779 "Node was deleted but visit returned NULL!"); 780 781 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 782 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 783 784 // Expose the DAG combiner to the target combiner impls. 785 TargetLowering::DAGCombinerInfo 786 DagCombineInfo(DAG, Level == Unrestricted, false, this); 787 788 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 789 } 790 } 791 792 // If N is a commutative binary node, try commuting it to enable more 793 // sdisel CSE. 794 if (RV.getNode() == 0 && 795 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 796 N->getNumValues() == 1) { 797 SDValue N0 = N->getOperand(0); 798 SDValue N1 = N->getOperand(1); 799 // Constant operands are canonicalized to RHS. 800 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 801 SDValue Ops[] = { N1, N0 }; 802 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 803 Ops, 2); 804 if (CSENode) 805 return SDValue(CSENode, 0); 806 } 807 } 808 809 return RV; 810} 811 812/// getInputChainForNode - Given a node, return its input chain if it has one, 813/// otherwise return a null sd operand. 814static SDValue getInputChainForNode(SDNode *N) { 815 if (unsigned NumOps = N->getNumOperands()) { 816 if (N->getOperand(0).getValueType() == MVT::Other) 817 return N->getOperand(0); 818 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 819 return N->getOperand(NumOps-1); 820 for (unsigned i = 1; i < NumOps-1; ++i) 821 if (N->getOperand(i).getValueType() == MVT::Other) 822 return N->getOperand(i); 823 } 824 return SDValue(0, 0); 825} 826 827SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 828 // If N has two operands, where one has an input chain equal to the other, 829 // the 'other' chain is redundant. 830 if (N->getNumOperands() == 2) { 831 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 832 return N->getOperand(0); 833 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 834 return N->getOperand(1); 835 } 836 837 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 838 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 839 SmallPtrSet<SDNode*, 16> SeenOps; 840 bool Changed = false; // If we should replace this token factor. 841 842 // Start out with this token factor. 843 TFs.push_back(N); 844 845 // Iterate through token factors. The TFs grows when new token factors are 846 // encountered. 847 for (unsigned i = 0; i < TFs.size(); ++i) { 848 SDNode *TF = TFs[i]; 849 850 // Check each of the operands. 851 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 852 SDValue Op = TF->getOperand(i); 853 854 switch (Op.getOpcode()) { 855 case ISD::EntryToken: 856 // Entry tokens don't need to be added to the list. They are 857 // rededundant. 858 Changed = true; 859 break; 860 861 case ISD::TokenFactor: 862 if ((CombinerAA || Op.hasOneUse()) && 863 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 864 // Queue up for processing. 865 TFs.push_back(Op.getNode()); 866 // Clean up in case the token factor is removed. 867 AddToWorkList(Op.getNode()); 868 Changed = true; 869 break; 870 } 871 // Fall thru 872 873 default: 874 // Only add if it isn't already in the list. 875 if (SeenOps.insert(Op.getNode())) 876 Ops.push_back(Op); 877 else 878 Changed = true; 879 break; 880 } 881 } 882 } 883 884 SDValue Result; 885 886 // If we've change things around then replace token factor. 887 if (Changed) { 888 if (Ops.empty()) { 889 // The entry token is the only possible outcome. 890 Result = DAG.getEntryNode(); 891 } else { 892 // New and improved token factor. 893 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 894 } 895 896 // Don't add users to work list. 897 return CombineTo(N, Result, false); 898 } 899 900 return Result; 901} 902 903/// MERGE_VALUES can always be eliminated. 904SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 905 WorkListRemover DeadNodes(*this); 906 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 907 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 908 &DeadNodes); 909 removeFromWorkList(N); 910 DAG.DeleteNode(N); 911 return SDValue(N, 0); // Return N so it doesn't get rechecked! 912} 913 914 915static 916SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) { 917 MVT VT = N0.getValueType(); 918 SDValue N00 = N0.getOperand(0); 919 SDValue N01 = N0.getOperand(1); 920 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 921 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 922 isa<ConstantSDNode>(N00.getOperand(1))) { 923 N0 = DAG.getNode(ISD::ADD, VT, 924 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 925 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 926 return DAG.getNode(ISD::ADD, VT, N0, N1); 927 } 928 return SDValue(); 929} 930 931static 932SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 933 SelectionDAG &DAG, const TargetLowering &TLI, 934 bool LegalOperations) { 935 MVT VT = N->getValueType(0); 936 unsigned Opc = N->getOpcode(); 937 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 938 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 939 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 940 ISD::CondCode CC = ISD::SETCC_INVALID; 941 942 if (isSlctCC) { 943 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 944 } else { 945 SDValue CCOp = Slct.getOperand(0); 946 if (CCOp.getOpcode() == ISD::SETCC) 947 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 948 } 949 950 bool DoXform = false; 951 bool InvCC = false; 952 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 953 "Bad input!"); 954 955 if (LHS.getOpcode() == ISD::Constant && 956 cast<ConstantSDNode>(LHS)->isNullValue()) { 957 DoXform = true; 958 } else if (CC != ISD::SETCC_INVALID && 959 RHS.getOpcode() == ISD::Constant && 960 cast<ConstantSDNode>(RHS)->isNullValue()) { 961 std::swap(LHS, RHS); 962 SDValue Op0 = Slct.getOperand(0); 963 MVT OpVT = isSlctCC ? Op0.getValueType() : 964 Op0.getOperand(0).getValueType(); 965 bool isInt = OpVT.isInteger(); 966 CC = ISD::getSetCCInverse(CC, isInt); 967 968 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT)) 969 return SDValue(); // Inverse operator isn't legal. 970 971 DoXform = true; 972 InvCC = true; 973 } 974 975 if (DoXform) { 976 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS); 977 if (isSlctCC) 978 return DAG.getSelectCC(OtherOp, Result, 979 Slct.getOperand(0), Slct.getOperand(1), CC); 980 SDValue CCOp = Slct.getOperand(0); 981 if (InvCC) 982 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 983 CCOp.getOperand(1), CC); 984 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 985 } 986 return SDValue(); 987} 988 989SDValue DAGCombiner::visitADD(SDNode *N) { 990 SDValue N0 = N->getOperand(0); 991 SDValue N1 = N->getOperand(1); 992 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 994 MVT VT = N0.getValueType(); 995 996 // fold vector ops 997 if (VT.isVector()) { 998 SDValue FoldedVOp = SimplifyVBinOp(N); 999 if (FoldedVOp.getNode()) return FoldedVOp; 1000 } 1001 1002 // fold (add x, undef) -> undef 1003 if (N0.getOpcode() == ISD::UNDEF) 1004 return N0; 1005 if (N1.getOpcode() == ISD::UNDEF) 1006 return N1; 1007 // fold (add c1, c2) -> c1+c2 1008 if (N0C && N1C) 1009 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1010 // canonicalize constant to RHS 1011 if (N0C && !N1C) 1012 return DAG.getNode(ISD::ADD, VT, N1, N0); 1013 // fold (add x, 0) -> x 1014 if (N1C && N1C->isNullValue()) 1015 return N0; 1016 // fold (add Sym, c) -> Sym+c 1017 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1018 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1019 GA->getOpcode() == ISD::GlobalAddress) 1020 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1021 GA->getOffset() + 1022 (uint64_t)N1C->getSExtValue()); 1023 // fold ((c1-A)+c2) -> (c1+c2)-A 1024 if (N1C && N0.getOpcode() == ISD::SUB) 1025 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1026 return DAG.getNode(ISD::SUB, VT, 1027 DAG.getConstant(N1C->getAPIntValue()+ 1028 N0C->getAPIntValue(), VT), 1029 N0.getOperand(1)); 1030 // reassociate add 1031 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1032 if (RADD.getNode() != 0) 1033 return RADD; 1034 // fold ((0-A) + B) -> B-A 1035 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1036 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1037 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 1038 // fold (A + (0-B)) -> A-B 1039 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1040 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1041 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 1042 // fold (A+(B-A)) -> B 1043 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1044 return N1.getOperand(0); 1045 // fold ((B-A)+A) -> B 1046 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1047 return N0.getOperand(0); 1048 // fold (A+(B-(A+C))) to (B-C) 1049 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1050 N0 == N1.getOperand(1).getOperand(0)) { 1051 return DAG.getNode(ISD::SUB, VT, N1.getOperand(0), 1052 N1.getOperand(1).getOperand(1)); 1053 } 1054 // fold (A+(B-(C+A))) to (B-C) 1055 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1056 N0 == N1.getOperand(1).getOperand(1)) { 1057 return DAG.getNode(ISD::SUB, VT, N1.getOperand(0), 1058 N1.getOperand(1).getOperand(0)); 1059 } 1060 // fold (A+((B-A)+or-C)) to (B+or-C) 1061 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1062 N1.getOperand(0).getOpcode() == ISD::SUB && 1063 N0 == N1.getOperand(0).getOperand(1)) { 1064 return DAG.getNode(N1.getOpcode(), VT, N1.getOperand(0).getOperand(0), 1065 N1.getOperand(1)); 1066 } 1067 1068 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1069 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1070 SDValue N00 = N0.getOperand(0); 1071 SDValue N01 = N0.getOperand(1); 1072 SDValue N10 = N1.getOperand(0); 1073 SDValue N11 = N1.getOperand(1); 1074 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) { 1075 return DAG.getNode(ISD::SUB, VT, 1076 DAG.getNode(ISD::ADD, VT, N00, N10), 1077 DAG.getNode(ISD::ADD, VT, N01, N11)); 1078 } 1079 } 1080 1081 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1082 return SDValue(N, 0); 1083 1084 // fold (a+b) -> (a|b) iff a and b share no bits. 1085 if (VT.isInteger() && !VT.isVector()) { 1086 APInt LHSZero, LHSOne; 1087 APInt RHSZero, RHSOne; 1088 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1089 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1090 if (LHSZero.getBoolValue()) { 1091 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1092 1093 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1094 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1095 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1096 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1097 return DAG.getNode(ISD::OR, VT, N0, N1); 1098 } 1099 } 1100 1101 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1102 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1103 SDValue Result = combineShlAddConstant(N0, N1, DAG); 1104 if (Result.getNode()) return Result; 1105 } 1106 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1107 SDValue Result = combineShlAddConstant(N1, N0, DAG); 1108 if (Result.getNode()) return Result; 1109 } 1110 1111 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1112 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1113 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations); 1114 if (Result.getNode()) return Result; 1115 } 1116 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1117 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1118 if (Result.getNode()) return Result; 1119 } 1120 1121 return SDValue(); 1122} 1123 1124SDValue DAGCombiner::visitADDC(SDNode *N) { 1125 SDValue N0 = N->getOperand(0); 1126 SDValue N1 = N->getOperand(1); 1127 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1128 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1129 MVT VT = N0.getValueType(); 1130 1131 // If the flag result is dead, turn this into an ADD. 1132 if (N->hasNUsesOfValue(0, 1)) 1133 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1134 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1135 1136 // canonicalize constant to RHS. 1137 if (N0C && !N1C) 1138 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1139 1140 // fold (addc x, 0) -> x + no carry out 1141 if (N1C && N1C->isNullValue()) 1142 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1143 1144 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1145 APInt LHSZero, LHSOne; 1146 APInt RHSZero, RHSOne; 1147 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1148 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1149 if (LHSZero.getBoolValue()) { 1150 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1151 1152 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1153 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1154 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1155 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1156 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1157 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1158 } 1159 1160 return SDValue(); 1161} 1162 1163SDValue DAGCombiner::visitADDE(SDNode *N) { 1164 SDValue N0 = N->getOperand(0); 1165 SDValue N1 = N->getOperand(1); 1166 SDValue CarryIn = N->getOperand(2); 1167 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1168 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1169 //MVT VT = N0.getValueType(); 1170 1171 // canonicalize constant to RHS 1172 if (N0C && !N1C) 1173 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1174 1175 // fold (adde x, y, false) -> (addc x, y) 1176 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1177 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1178 1179 return SDValue(); 1180} 1181 1182 1183 1184SDValue DAGCombiner::visitSUB(SDNode *N) { 1185 SDValue N0 = N->getOperand(0); 1186 SDValue N1 = N->getOperand(1); 1187 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1188 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1189 MVT VT = N0.getValueType(); 1190 1191 // fold vector ops 1192 if (VT.isVector()) { 1193 SDValue FoldedVOp = SimplifyVBinOp(N); 1194 if (FoldedVOp.getNode()) return FoldedVOp; 1195 } 1196 1197 // fold (sub x, x) -> 0 1198 if (N0 == N1) 1199 return DAG.getConstant(0, N->getValueType(0)); 1200 // fold (sub c1, c2) -> c1-c2 1201 if (N0C && N1C) 1202 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1203 // fold (sub x, c) -> (add x, -c) 1204 if (N1C) 1205 return DAG.getNode(ISD::ADD, VT, N0, 1206 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1207 // fold (A+B)-A -> B 1208 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1209 return N0.getOperand(1); 1210 // fold (A+B)-B -> A 1211 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1212 return N0.getOperand(0); 1213 // fold ((A+(B+or-C))-B) -> A+or-C 1214 if (N0.getOpcode() == ISD::ADD && 1215 (N0.getOperand(1).getOpcode() == ISD::SUB || 1216 N0.getOperand(1).getOpcode() == ISD::ADD) && 1217 N0.getOperand(1).getOperand(0) == N1) 1218 return DAG.getNode(N0.getOperand(1).getOpcode(), VT, N0.getOperand(0), 1219 N0.getOperand(1).getOperand(1)); 1220 // fold ((A+(C+B))-B) -> A+C 1221 if (N0.getOpcode() == ISD::ADD && 1222 N0.getOperand(1).getOpcode() == ISD::ADD && 1223 N0.getOperand(1).getOperand(1) == N1) 1224 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0), 1225 N0.getOperand(1).getOperand(0)); 1226 // fold ((A-(B-C))-C) -> A-B 1227 if (N0.getOpcode() == ISD::SUB && 1228 N0.getOperand(1).getOpcode() == ISD::SUB && 1229 N0.getOperand(1).getOperand(1) == N1) 1230 return DAG.getNode(ISD::SUB, VT, N0.getOperand(0), 1231 N0.getOperand(1).getOperand(0)); 1232 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1233 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1234 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1235 if (Result.getNode()) return Result; 1236 } 1237 // If either operand of a sub is undef, the result is undef 1238 if (N0.getOpcode() == ISD::UNDEF) 1239 return N0; 1240 if (N1.getOpcode() == ISD::UNDEF) 1241 return N1; 1242 1243 // If the relocation model supports it, consider symbol offsets. 1244 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1245 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1246 // fold (sub Sym, c) -> Sym-c 1247 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1248 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1249 GA->getOffset() - 1250 (uint64_t)N1C->getSExtValue()); 1251 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1252 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1253 if (GA->getGlobal() == GB->getGlobal()) 1254 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1255 VT); 1256 } 1257 1258 return SDValue(); 1259} 1260 1261SDValue DAGCombiner::visitMUL(SDNode *N) { 1262 SDValue N0 = N->getOperand(0); 1263 SDValue N1 = N->getOperand(1); 1264 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1265 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1266 MVT VT = N0.getValueType(); 1267 1268 // fold vector ops 1269 if (VT.isVector()) { 1270 SDValue FoldedVOp = SimplifyVBinOp(N); 1271 if (FoldedVOp.getNode()) return FoldedVOp; 1272 } 1273 1274 // fold (mul x, undef) -> 0 1275 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1276 return DAG.getConstant(0, VT); 1277 // fold (mul c1, c2) -> c1*c2 1278 if (N0C && N1C) 1279 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1280 // canonicalize constant to RHS 1281 if (N0C && !N1C) 1282 return DAG.getNode(ISD::MUL, VT, N1, N0); 1283 // fold (mul x, 0) -> 0 1284 if (N1C && N1C->isNullValue()) 1285 return N1; 1286 // fold (mul x, -1) -> 0-x 1287 if (N1C && N1C->isAllOnesValue()) 1288 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1289 // fold (mul x, (1 << c)) -> x << c 1290 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1291 return DAG.getNode(ISD::SHL, VT, N0, 1292 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1293 TLI.getShiftAmountTy())); 1294 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1295 if (N1C && isPowerOf2_64(-N1C->getSExtValue())) { 1296 // FIXME: If the input is something that is easily negated (e.g. a 1297 // single-use add), we should put the negate there. 1298 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1299 DAG.getNode(ISD::SHL, VT, N0, 1300 DAG.getConstant(Log2_64(-N1C->getSExtValue()), 1301 TLI.getShiftAmountTy()))); 1302 } 1303 1304 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1305 if (N1C && N0.getOpcode() == ISD::SHL && 1306 isa<ConstantSDNode>(N0.getOperand(1))) { 1307 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1308 AddToWorkList(C3.getNode()); 1309 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1310 } 1311 1312 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1313 // use. 1314 { 1315 SDValue Sh(0,0), Y(0,0); 1316 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1317 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1318 N0.getNode()->hasOneUse()) { 1319 Sh = N0; Y = N1; 1320 } else if (N1.getOpcode() == ISD::SHL && 1321 isa<ConstantSDNode>(N1.getOperand(1)) && 1322 N1.getNode()->hasOneUse()) { 1323 Sh = N1; Y = N0; 1324 } 1325 if (Sh.getNode()) { 1326 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1327 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1328 } 1329 } 1330 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1331 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1332 isa<ConstantSDNode>(N0.getOperand(1))) { 1333 return DAG.getNode(ISD::ADD, VT, 1334 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1335 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1336 } 1337 1338 // reassociate mul 1339 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1340 if (RMUL.getNode() != 0) 1341 return RMUL; 1342 1343 return SDValue(); 1344} 1345 1346SDValue DAGCombiner::visitSDIV(SDNode *N) { 1347 SDValue N0 = N->getOperand(0); 1348 SDValue N1 = N->getOperand(1); 1349 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1350 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1351 MVT VT = N->getValueType(0); 1352 1353 // fold vector ops 1354 if (VT.isVector()) { 1355 SDValue FoldedVOp = SimplifyVBinOp(N); 1356 if (FoldedVOp.getNode()) return FoldedVOp; 1357 } 1358 1359 // fold (sdiv c1, c2) -> c1/c2 1360 if (N0C && N1C && !N1C->isNullValue()) 1361 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1362 // fold (sdiv X, 1) -> X 1363 if (N1C && N1C->getSExtValue() == 1LL) 1364 return N0; 1365 // fold (sdiv X, -1) -> 0-X 1366 if (N1C && N1C->isAllOnesValue()) 1367 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1368 // If we know the sign bits of both operands are zero, strength reduce to a 1369 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1370 if (!VT.isVector()) { 1371 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1372 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1373 } 1374 // fold (sdiv X, pow2) -> simple ops after legalize 1375 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1376 (isPowerOf2_64(N1C->getSExtValue()) || 1377 isPowerOf2_64(-N1C->getSExtValue()))) { 1378 // If dividing by powers of two is cheap, then don't perform the following 1379 // fold. 1380 if (TLI.isPow2DivCheap()) 1381 return SDValue(); 1382 int64_t pow2 = N1C->getSExtValue(); 1383 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1384 unsigned lg2 = Log2_64(abs2); 1385 // Splat the sign bit into the register 1386 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1387 DAG.getConstant(VT.getSizeInBits()-1, 1388 TLI.getShiftAmountTy())); 1389 AddToWorkList(SGN.getNode()); 1390 // Add (N0 < 0) ? abs2 - 1 : 0; 1391 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1392 DAG.getConstant(VT.getSizeInBits()-lg2, 1393 TLI.getShiftAmountTy())); 1394 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1395 AddToWorkList(SRL.getNode()); 1396 AddToWorkList(ADD.getNode()); // Divide by pow2 1397 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1398 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1399 // If we're dividing by a positive value, we're done. Otherwise, we must 1400 // negate the result. 1401 if (pow2 > 0) 1402 return SRA; 1403 AddToWorkList(SRA.getNode()); 1404 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1405 } 1406 // if integer divide is expensive and we satisfy the requirements, emit an 1407 // alternate sequence. 1408 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1409 !TLI.isIntDivCheap()) { 1410 SDValue Op = BuildSDIV(N); 1411 if (Op.getNode()) return Op; 1412 } 1413 1414 // undef / X -> 0 1415 if (N0.getOpcode() == ISD::UNDEF) 1416 return DAG.getConstant(0, VT); 1417 // X / undef -> undef 1418 if (N1.getOpcode() == ISD::UNDEF) 1419 return N1; 1420 1421 return SDValue(); 1422} 1423 1424SDValue DAGCombiner::visitUDIV(SDNode *N) { 1425 SDValue N0 = N->getOperand(0); 1426 SDValue N1 = N->getOperand(1); 1427 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1428 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1429 MVT VT = N->getValueType(0); 1430 1431 // fold vector ops 1432 if (VT.isVector()) { 1433 SDValue FoldedVOp = SimplifyVBinOp(N); 1434 if (FoldedVOp.getNode()) return FoldedVOp; 1435 } 1436 1437 // fold (udiv c1, c2) -> c1/c2 1438 if (N0C && N1C && !N1C->isNullValue()) 1439 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1440 // fold (udiv x, (1 << c)) -> x >>u c 1441 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1442 return DAG.getNode(ISD::SRL, VT, N0, 1443 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1444 TLI.getShiftAmountTy())); 1445 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1446 if (N1.getOpcode() == ISD::SHL) { 1447 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1448 if (SHC->getAPIntValue().isPowerOf2()) { 1449 MVT ADDVT = N1.getOperand(1).getValueType(); 1450 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1451 DAG.getConstant(SHC->getAPIntValue() 1452 .logBase2(), 1453 ADDVT)); 1454 AddToWorkList(Add.getNode()); 1455 return DAG.getNode(ISD::SRL, VT, N0, Add); 1456 } 1457 } 1458 } 1459 // fold (udiv x, c) -> alternate 1460 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1461 SDValue Op = BuildUDIV(N); 1462 if (Op.getNode()) return Op; 1463 } 1464 1465 // undef / X -> 0 1466 if (N0.getOpcode() == ISD::UNDEF) 1467 return DAG.getConstant(0, VT); 1468 // X / undef -> undef 1469 if (N1.getOpcode() == ISD::UNDEF) 1470 return N1; 1471 1472 return SDValue(); 1473} 1474 1475SDValue DAGCombiner::visitSREM(SDNode *N) { 1476 SDValue N0 = N->getOperand(0); 1477 SDValue N1 = N->getOperand(1); 1478 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1479 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1480 MVT VT = N->getValueType(0); 1481 1482 // fold (srem c1, c2) -> c1%c2 1483 if (N0C && N1C && !N1C->isNullValue()) 1484 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1485 // If we know the sign bits of both operands are zero, strength reduce to a 1486 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1487 if (!VT.isVector()) { 1488 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1489 return DAG.getNode(ISD::UREM, VT, N0, N1); 1490 } 1491 1492 // If X/C can be simplified by the division-by-constant logic, lower 1493 // X%C to the equivalent of X-X/C*C. 1494 if (N1C && !N1C->isNullValue()) { 1495 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1496 AddToWorkList(Div.getNode()); 1497 SDValue OptimizedDiv = combine(Div.getNode()); 1498 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1499 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1500 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1501 AddToWorkList(Mul.getNode()); 1502 return Sub; 1503 } 1504 } 1505 1506 // undef % X -> 0 1507 if (N0.getOpcode() == ISD::UNDEF) 1508 return DAG.getConstant(0, VT); 1509 // X % undef -> undef 1510 if (N1.getOpcode() == ISD::UNDEF) 1511 return N1; 1512 1513 return SDValue(); 1514} 1515 1516SDValue DAGCombiner::visitUREM(SDNode *N) { 1517 SDValue N0 = N->getOperand(0); 1518 SDValue N1 = N->getOperand(1); 1519 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1521 MVT VT = N->getValueType(0); 1522 1523 // fold (urem c1, c2) -> c1%c2 1524 if (N0C && N1C && !N1C->isNullValue()) 1525 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1526 // fold (urem x, pow2) -> (and x, pow2-1) 1527 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1528 return DAG.getNode(ISD::AND, VT, N0, 1529 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1530 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1531 if (N1.getOpcode() == ISD::SHL) { 1532 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1533 if (SHC->getAPIntValue().isPowerOf2()) { 1534 SDValue Add = 1535 DAG.getNode(ISD::ADD, VT, N1, 1536 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1537 VT)); 1538 AddToWorkList(Add.getNode()); 1539 return DAG.getNode(ISD::AND, VT, N0, Add); 1540 } 1541 } 1542 } 1543 1544 // If X/C can be simplified by the division-by-constant logic, lower 1545 // X%C to the equivalent of X-X/C*C. 1546 if (N1C && !N1C->isNullValue()) { 1547 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1548 AddToWorkList(Div.getNode()); 1549 SDValue OptimizedDiv = combine(Div.getNode()); 1550 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1551 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1552 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1553 AddToWorkList(Mul.getNode()); 1554 return Sub; 1555 } 1556 } 1557 1558 // undef % X -> 0 1559 if (N0.getOpcode() == ISD::UNDEF) 1560 return DAG.getConstant(0, VT); 1561 // X % undef -> undef 1562 if (N1.getOpcode() == ISD::UNDEF) 1563 return N1; 1564 1565 return SDValue(); 1566} 1567 1568SDValue DAGCombiner::visitMULHS(SDNode *N) { 1569 SDValue N0 = N->getOperand(0); 1570 SDValue N1 = N->getOperand(1); 1571 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1572 MVT VT = N->getValueType(0); 1573 1574 // fold (mulhs x, 0) -> 0 1575 if (N1C && N1C->isNullValue()) 1576 return N1; 1577 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1578 if (N1C && N1C->getAPIntValue() == 1) 1579 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1580 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1581 TLI.getShiftAmountTy())); 1582 // fold (mulhs x, undef) -> 0 1583 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1584 return DAG.getConstant(0, VT); 1585 1586 return SDValue(); 1587} 1588 1589SDValue DAGCombiner::visitMULHU(SDNode *N) { 1590 SDValue N0 = N->getOperand(0); 1591 SDValue N1 = N->getOperand(1); 1592 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1593 MVT VT = N->getValueType(0); 1594 1595 // fold (mulhu x, 0) -> 0 1596 if (N1C && N1C->isNullValue()) 1597 return N1; 1598 // fold (mulhu x, 1) -> 0 1599 if (N1C && N1C->getAPIntValue() == 1) 1600 return DAG.getConstant(0, N0.getValueType()); 1601 // fold (mulhu x, undef) -> 0 1602 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1603 return DAG.getConstant(0, VT); 1604 1605 return SDValue(); 1606} 1607 1608/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1609/// compute two values. LoOp and HiOp give the opcodes for the two computations 1610/// that are being performed. Return true if a simplification was made. 1611/// 1612SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1613 unsigned HiOp) { 1614 // If the high half is not needed, just compute the low half. 1615 bool HiExists = N->hasAnyUseOfValue(1); 1616 if (!HiExists && 1617 (!LegalOperations || 1618 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1619 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1620 N->getNumOperands()); 1621 return CombineTo(N, Res, Res); 1622 } 1623 1624 // If the low half is not needed, just compute the high half. 1625 bool LoExists = N->hasAnyUseOfValue(0); 1626 if (!LoExists && 1627 (!LegalOperations || 1628 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1629 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1630 N->getNumOperands()); 1631 return CombineTo(N, Res, Res); 1632 } 1633 1634 // If both halves are used, return as it is. 1635 if (LoExists && HiExists) 1636 return SDValue(); 1637 1638 // If the two computed results can be simplified separately, separate them. 1639 if (LoExists) { 1640 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1641 N->op_begin(), N->getNumOperands()); 1642 AddToWorkList(Lo.getNode()); 1643 SDValue LoOpt = combine(Lo.getNode()); 1644 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1645 (!LegalOperations || 1646 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1647 return CombineTo(N, LoOpt, LoOpt); 1648 } 1649 1650 if (HiExists) { 1651 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1652 N->op_begin(), N->getNumOperands()); 1653 AddToWorkList(Hi.getNode()); 1654 SDValue HiOpt = combine(Hi.getNode()); 1655 if (HiOpt.getNode() && HiOpt != Hi && 1656 (!LegalOperations || 1657 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1658 return CombineTo(N, HiOpt, HiOpt); 1659 } 1660 return SDValue(); 1661} 1662 1663SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1664 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1665 if (Res.getNode()) return Res; 1666 1667 return SDValue(); 1668} 1669 1670SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1671 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1672 if (Res.getNode()) return Res; 1673 1674 return SDValue(); 1675} 1676 1677SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1678 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1679 if (Res.getNode()) return Res; 1680 1681 return SDValue(); 1682} 1683 1684SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1685 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1686 if (Res.getNode()) return Res; 1687 1688 return SDValue(); 1689} 1690 1691/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1692/// two operands of the same opcode, try to simplify it. 1693SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1694 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1695 MVT VT = N0.getValueType(); 1696 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1697 1698 // For each of OP in AND/OR/XOR: 1699 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1700 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1701 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1702 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1703 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1704 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1705 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1706 SDValue ORNode = DAG.getNode(N->getOpcode(), 1707 N0.getOperand(0).getValueType(), 1708 N0.getOperand(0), N1.getOperand(0)); 1709 AddToWorkList(ORNode.getNode()); 1710 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1711 } 1712 1713 // For each of OP in SHL/SRL/SRA/AND... 1714 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1715 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1716 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1717 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1718 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1719 N0.getOperand(1) == N1.getOperand(1)) { 1720 SDValue ORNode = DAG.getNode(N->getOpcode(), 1721 N0.getOperand(0).getValueType(), 1722 N0.getOperand(0), N1.getOperand(0)); 1723 AddToWorkList(ORNode.getNode()); 1724 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1725 } 1726 1727 return SDValue(); 1728} 1729 1730SDValue DAGCombiner::visitAND(SDNode *N) { 1731 SDValue N0 = N->getOperand(0); 1732 SDValue N1 = N->getOperand(1); 1733 SDValue LL, LR, RL, RR, CC0, CC1; 1734 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1735 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1736 MVT VT = N1.getValueType(); 1737 unsigned BitWidth = VT.getSizeInBits(); 1738 1739 // fold vector ops 1740 if (VT.isVector()) { 1741 SDValue FoldedVOp = SimplifyVBinOp(N); 1742 if (FoldedVOp.getNode()) return FoldedVOp; 1743 } 1744 1745 // fold (and x, undef) -> 0 1746 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1747 return DAG.getConstant(0, VT); 1748 // fold (and c1, c2) -> c1&c2 1749 if (N0C && N1C) 1750 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1751 // canonicalize constant to RHS 1752 if (N0C && !N1C) 1753 return DAG.getNode(ISD::AND, VT, N1, N0); 1754 // fold (and x, -1) -> x 1755 if (N1C && N1C->isAllOnesValue()) 1756 return N0; 1757 // if (and x, c) is known to be zero, return 0 1758 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1759 APInt::getAllOnesValue(BitWidth))) 1760 return DAG.getConstant(0, VT); 1761 // reassociate and 1762 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1763 if (RAND.getNode() != 0) 1764 return RAND; 1765 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1766 if (N1C && N0.getOpcode() == ISD::OR) 1767 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1768 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1769 return N1; 1770 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1771 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1772 SDValue N0Op0 = N0.getOperand(0); 1773 APInt Mask = ~N1C->getAPIntValue(); 1774 Mask.trunc(N0Op0.getValueSizeInBits()); 1775 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1776 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1777 N0Op0); 1778 1779 // Replace uses of the AND with uses of the Zero extend node. 1780 CombineTo(N, Zext); 1781 1782 // We actually want to replace all uses of the any_extend with the 1783 // zero_extend, to avoid duplicating things. This will later cause this 1784 // AND to be folded. 1785 CombineTo(N0.getNode(), Zext); 1786 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1787 } 1788 } 1789 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1790 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1791 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1792 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1793 1794 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1795 LL.getValueType().isInteger()) { 1796 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1797 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1798 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1799 AddToWorkList(ORNode.getNode()); 1800 return DAG.getSetCC(VT, ORNode, LR, Op1); 1801 } 1802 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1803 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1804 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1805 AddToWorkList(ANDNode.getNode()); 1806 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1807 } 1808 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1809 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1810 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1811 AddToWorkList(ORNode.getNode()); 1812 return DAG.getSetCC(VT, ORNode, LR, Op1); 1813 } 1814 } 1815 // canonicalize equivalent to ll == rl 1816 if (LL == RR && LR == RL) { 1817 Op1 = ISD::getSetCCSwappedOperands(Op1); 1818 std::swap(RL, RR); 1819 } 1820 if (LL == RL && LR == RR) { 1821 bool isInteger = LL.getValueType().isInteger(); 1822 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1823 if (Result != ISD::SETCC_INVALID && 1824 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1825 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1826 } 1827 } 1828 1829 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1830 if (N0.getOpcode() == N1.getOpcode()) { 1831 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1832 if (Tmp.getNode()) return Tmp; 1833 } 1834 1835 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1836 // fold (and (sra)) -> (and (srl)) when possible. 1837 if (!VT.isVector() && 1838 SimplifyDemandedBits(SDValue(N, 0))) 1839 return SDValue(N, 0); 1840 // fold (zext_inreg (extload x)) -> (zextload x) 1841 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1842 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1843 MVT EVT = LN0->getMemoryVT(); 1844 // If we zero all the possible extended bits, then we can turn this into 1845 // a zextload if we are running before legalize or the operation is legal. 1846 unsigned BitWidth = N1.getValueSizeInBits(); 1847 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1848 BitWidth - EVT.getSizeInBits())) && 1849 ((!LegalOperations && !LN0->isVolatile()) || 1850 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1851 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1852 LN0->getBasePtr(), LN0->getSrcValue(), 1853 LN0->getSrcValueOffset(), EVT, 1854 LN0->isVolatile(), LN0->getAlignment()); 1855 AddToWorkList(N); 1856 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1857 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1858 } 1859 } 1860 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1861 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1862 N0.hasOneUse()) { 1863 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1864 MVT EVT = LN0->getMemoryVT(); 1865 // If we zero all the possible extended bits, then we can turn this into 1866 // a zextload if we are running before legalize or the operation is legal. 1867 unsigned BitWidth = N1.getValueSizeInBits(); 1868 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1869 BitWidth - EVT.getSizeInBits())) && 1870 ((!LegalOperations && !LN0->isVolatile()) || 1871 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1872 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1873 LN0->getBasePtr(), LN0->getSrcValue(), 1874 LN0->getSrcValueOffset(), EVT, 1875 LN0->isVolatile(), LN0->getAlignment()); 1876 AddToWorkList(N); 1877 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1878 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1879 } 1880 } 1881 1882 // fold (and (load x), 255) -> (zextload x, i8) 1883 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1884 if (N1C && N0.getOpcode() == ISD::LOAD) { 1885 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1886 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1887 LN0->isUnindexed() && N0.hasOneUse() && 1888 // Do not change the width of a volatile load. 1889 !LN0->isVolatile()) { 1890 MVT EVT = MVT::Other; 1891 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1892 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1893 EVT = MVT::getIntegerVT(ActiveBits); 1894 1895 MVT LoadedVT = LN0->getMemoryVT(); 1896 // Do not generate loads of non-round integer types since these can 1897 // be expensive (and would be wrong if the type is not byte sized). 1898 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1899 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1900 MVT PtrType = N0.getOperand(1).getValueType(); 1901 // For big endian targets, we need to add an offset to the pointer to 1902 // load the correct bytes. For little endian systems, we merely need to 1903 // read fewer bytes from the same pointer. 1904 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1905 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1906 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1907 unsigned Alignment = LN0->getAlignment(); 1908 SDValue NewPtr = LN0->getBasePtr(); 1909 if (TLI.isBigEndian()) { 1910 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1911 DAG.getConstant(PtrOff, PtrType)); 1912 Alignment = MinAlign(Alignment, PtrOff); 1913 } 1914 AddToWorkList(NewPtr.getNode()); 1915 SDValue Load = 1916 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1917 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1918 LN0->isVolatile(), Alignment); 1919 AddToWorkList(N); 1920 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1921 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1922 } 1923 } 1924 } 1925 1926 return SDValue(); 1927} 1928 1929SDValue DAGCombiner::visitOR(SDNode *N) { 1930 SDValue N0 = N->getOperand(0); 1931 SDValue N1 = N->getOperand(1); 1932 SDValue LL, LR, RL, RR, CC0, CC1; 1933 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1934 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1935 MVT VT = N1.getValueType(); 1936 1937 // fold vector ops 1938 if (VT.isVector()) { 1939 SDValue FoldedVOp = SimplifyVBinOp(N); 1940 if (FoldedVOp.getNode()) return FoldedVOp; 1941 } 1942 1943 // fold (or x, undef) -> -1 1944 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1945 return DAG.getConstant(~0ULL, VT); 1946 // fold (or c1, c2) -> c1|c2 1947 if (N0C && N1C) 1948 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1949 // canonicalize constant to RHS 1950 if (N0C && !N1C) 1951 return DAG.getNode(ISD::OR, VT, N1, N0); 1952 // fold (or x, 0) -> x 1953 if (N1C && N1C->isNullValue()) 1954 return N0; 1955 // fold (or x, -1) -> -1 1956 if (N1C && N1C->isAllOnesValue()) 1957 return N1; 1958 // fold (or x, c) -> c iff (x & ~c) == 0 1959 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1960 return N1; 1961 // reassociate or 1962 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1963 if (ROR.getNode() != 0) 1964 return ROR; 1965 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1966 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1967 isa<ConstantSDNode>(N0.getOperand(1))) { 1968 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1969 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1970 N1), 1971 DAG.getConstant(N1C->getAPIntValue() | 1972 C1->getAPIntValue(), VT)); 1973 } 1974 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1975 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1976 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1977 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1978 1979 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1980 LL.getValueType().isInteger()) { 1981 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1982 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1983 if (cast<ConstantSDNode>(LR)->isNullValue() && 1984 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1985 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1986 AddToWorkList(ORNode.getNode()); 1987 return DAG.getSetCC(VT, ORNode, LR, Op1); 1988 } 1989 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1990 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1991 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1992 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1993 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1994 AddToWorkList(ANDNode.getNode()); 1995 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1996 } 1997 } 1998 // canonicalize equivalent to ll == rl 1999 if (LL == RR && LR == RL) { 2000 Op1 = ISD::getSetCCSwappedOperands(Op1); 2001 std::swap(RL, RR); 2002 } 2003 if (LL == RL && LR == RR) { 2004 bool isInteger = LL.getValueType().isInteger(); 2005 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2006 if (Result != ISD::SETCC_INVALID && 2007 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2008 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 2009 } 2010 } 2011 2012 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 2013 if (N0.getOpcode() == N1.getOpcode()) { 2014 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2015 if (Tmp.getNode()) return Tmp; 2016 } 2017 2018 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 2019 if (N0.getOpcode() == ISD::AND && 2020 N1.getOpcode() == ISD::AND && 2021 N0.getOperand(1).getOpcode() == ISD::Constant && 2022 N1.getOperand(1).getOpcode() == ISD::Constant && 2023 // Don't increase # computations. 2024 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2025 // We can only do this xform if we know that bits from X that are set in C2 2026 // but not in C1 are already zero. Likewise for Y. 2027 const APInt &LHSMask = 2028 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2029 const APInt &RHSMask = 2030 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2031 2032 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2033 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2034 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 2035 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 2036 } 2037 } 2038 2039 2040 // See if this is some rotate idiom. 2041 if (SDNode *Rot = MatchRotate(N0, N1)) 2042 return SDValue(Rot, 0); 2043 2044 return SDValue(); 2045} 2046 2047 2048/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2049static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2050 if (Op.getOpcode() == ISD::AND) { 2051 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2052 Mask = Op.getOperand(1); 2053 Op = Op.getOperand(0); 2054 } else { 2055 return false; 2056 } 2057 } 2058 2059 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2060 Shift = Op; 2061 return true; 2062 } 2063 return false; 2064} 2065 2066 2067// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2068// idioms for rotate, and if the target supports rotation instructions, generate 2069// a rot[lr]. 2070SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 2071 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2072 MVT VT = LHS.getValueType(); 2073 if (!TLI.isTypeLegal(VT)) return 0; 2074 2075 // The target must have at least one rotate flavor. 2076 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2077 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2078 if (!HasROTL && !HasROTR) return 0; 2079 2080 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2081 SDValue LHSShift; // The shift. 2082 SDValue LHSMask; // AND value if any. 2083 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2084 return 0; // Not part of a rotate. 2085 2086 SDValue RHSShift; // The shift. 2087 SDValue RHSMask; // AND value if any. 2088 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2089 return 0; // Not part of a rotate. 2090 2091 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2092 return 0; // Not shifting the same value. 2093 2094 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2095 return 0; // Shifts must disagree. 2096 2097 // Canonicalize shl to left side in a shl/srl pair. 2098 if (RHSShift.getOpcode() == ISD::SHL) { 2099 std::swap(LHS, RHS); 2100 std::swap(LHSShift, RHSShift); 2101 std::swap(LHSMask , RHSMask ); 2102 } 2103 2104 unsigned OpSizeInBits = VT.getSizeInBits(); 2105 SDValue LHSShiftArg = LHSShift.getOperand(0); 2106 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2107 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2108 2109 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2110 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2111 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2112 RHSShiftAmt.getOpcode() == ISD::Constant) { 2113 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2114 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2115 if ((LShVal + RShVal) != OpSizeInBits) 2116 return 0; 2117 2118 SDValue Rot; 2119 if (HasROTL) 2120 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2121 else 2122 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2123 2124 // If there is an AND of either shifted operand, apply it to the result. 2125 if (LHSMask.getNode() || RHSMask.getNode()) { 2126 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2127 2128 if (LHSMask.getNode()) { 2129 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2130 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2131 } 2132 if (RHSMask.getNode()) { 2133 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2134 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2135 } 2136 2137 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2138 } 2139 2140 return Rot.getNode(); 2141 } 2142 2143 // If there is a mask here, and we have a variable shift, we can't be sure 2144 // that we're masking out the right stuff. 2145 if (LHSMask.getNode() || RHSMask.getNode()) 2146 return 0; 2147 2148 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2149 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2150 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2151 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2152 if (ConstantSDNode *SUBC = 2153 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2154 if (SUBC->getAPIntValue() == OpSizeInBits) { 2155 if (HasROTL) 2156 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2157 else 2158 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2159 } 2160 } 2161 } 2162 2163 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2164 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2165 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2166 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2167 if (ConstantSDNode *SUBC = 2168 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2169 if (SUBC->getAPIntValue() == OpSizeInBits) { 2170 if (HasROTR) 2171 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2172 else 2173 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2174 } 2175 } 2176 } 2177 2178 // Look for sign/zext/any-extended or truncate cases: 2179 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2180 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2181 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2182 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2183 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2184 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2185 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2186 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2187 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2188 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2189 if (RExtOp0.getOpcode() == ISD::SUB && 2190 RExtOp0.getOperand(1) == LExtOp0) { 2191 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2192 // (rotl x, y) 2193 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2194 // (rotr x, (sub 32, y)) 2195 if (ConstantSDNode *SUBC = 2196 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2197 if (SUBC->getAPIntValue() == OpSizeInBits) { 2198 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, 2199 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2200 } 2201 } 2202 } else if (LExtOp0.getOpcode() == ISD::SUB && 2203 RExtOp0 == LExtOp0.getOperand(1)) { 2204 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2205 // (rotr x, y) 2206 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2207 // (rotl x, (sub 32, y)) 2208 if (ConstantSDNode *SUBC = 2209 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2210 if (SUBC->getAPIntValue() == OpSizeInBits) { 2211 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, 2212 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2213 } 2214 } 2215 } 2216 } 2217 2218 return 0; 2219} 2220 2221 2222SDValue DAGCombiner::visitXOR(SDNode *N) { 2223 SDValue N0 = N->getOperand(0); 2224 SDValue N1 = N->getOperand(1); 2225 SDValue LHS, RHS, CC; 2226 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2227 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2228 MVT VT = N0.getValueType(); 2229 2230 // fold vector ops 2231 if (VT.isVector()) { 2232 SDValue FoldedVOp = SimplifyVBinOp(N); 2233 if (FoldedVOp.getNode()) return FoldedVOp; 2234 } 2235 2236 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2237 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2238 return DAG.getConstant(0, VT); 2239 // fold (xor x, undef) -> undef 2240 if (N0.getOpcode() == ISD::UNDEF) 2241 return N0; 2242 if (N1.getOpcode() == ISD::UNDEF) 2243 return N1; 2244 // fold (xor c1, c2) -> c1^c2 2245 if (N0C && N1C) 2246 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2247 // canonicalize constant to RHS 2248 if (N0C && !N1C) 2249 return DAG.getNode(ISD::XOR, VT, N1, N0); 2250 // fold (xor x, 0) -> x 2251 if (N1C && N1C->isNullValue()) 2252 return N0; 2253 // reassociate xor 2254 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2255 if (RXOR.getNode() != 0) 2256 return RXOR; 2257 2258 // fold !(x cc y) -> (x !cc y) 2259 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2260 bool isInt = LHS.getValueType().isInteger(); 2261 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2262 isInt); 2263 2264 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2265 switch (N0.getOpcode()) { 2266 default: 2267 assert(0 && "Unhandled SetCC Equivalent!"); 2268 abort(); 2269 case ISD::SETCC: 2270 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2271 case ISD::SELECT_CC: 2272 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2), 2273 N0.getOperand(3), NotCC); 2274 } 2275 } 2276 } 2277 2278 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2279 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2280 N0.getNode()->hasOneUse() && 2281 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2282 SDValue V = N0.getOperand(0); 2283 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2284 DAG.getConstant(1, V.getValueType())); 2285 AddToWorkList(V.getNode()); 2286 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2287 } 2288 2289 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2290 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2291 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2292 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2293 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2294 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2295 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2296 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2297 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2298 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2299 } 2300 } 2301 // fold !(x or y) -> (!x and !y) iff x or y are constants 2302 if (N1C && N1C->isAllOnesValue() && 2303 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2304 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2305 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2306 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2307 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2308 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2309 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2310 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2311 } 2312 } 2313 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2314 if (N1C && N0.getOpcode() == ISD::XOR) { 2315 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2316 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2317 if (N00C) 2318 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2319 DAG.getConstant(N1C->getAPIntValue()^ 2320 N00C->getAPIntValue(), VT)); 2321 if (N01C) 2322 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2323 DAG.getConstant(N1C->getAPIntValue()^ 2324 N01C->getAPIntValue(), VT)); 2325 } 2326 // fold (xor x, x) -> 0 2327 if (N0 == N1) { 2328 if (!VT.isVector()) { 2329 return DAG.getConstant(0, VT); 2330 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2331 // Produce a vector of zeros. 2332 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2333 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2334 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2335 } 2336 } 2337 2338 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2339 if (N0.getOpcode() == N1.getOpcode()) { 2340 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2341 if (Tmp.getNode()) return Tmp; 2342 } 2343 2344 // Simplify the expression using non-local knowledge. 2345 if (!VT.isVector() && 2346 SimplifyDemandedBits(SDValue(N, 0))) 2347 return SDValue(N, 0); 2348 2349 return SDValue(); 2350} 2351 2352/// visitShiftByConstant - Handle transforms common to the three shifts, when 2353/// the shift amount is a constant. 2354SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2355 SDNode *LHS = N->getOperand(0).getNode(); 2356 if (!LHS->hasOneUse()) return SDValue(); 2357 2358 // We want to pull some binops through shifts, so that we have (and (shift)) 2359 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2360 // thing happens with address calculations, so it's important to canonicalize 2361 // it. 2362 bool HighBitSet = false; // Can we transform this if the high bit is set? 2363 2364 switch (LHS->getOpcode()) { 2365 default: return SDValue(); 2366 case ISD::OR: 2367 case ISD::XOR: 2368 HighBitSet = false; // We can only transform sra if the high bit is clear. 2369 break; 2370 case ISD::AND: 2371 HighBitSet = true; // We can only transform sra if the high bit is set. 2372 break; 2373 case ISD::ADD: 2374 if (N->getOpcode() != ISD::SHL) 2375 return SDValue(); // only shl(add) not sr[al](add). 2376 HighBitSet = false; // We can only transform sra if the high bit is clear. 2377 break; 2378 } 2379 2380 // We require the RHS of the binop to be a constant as well. 2381 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2382 if (!BinOpCst) return SDValue(); 2383 2384 2385 // FIXME: disable this for unless the input to the binop is a shift by a 2386 // constant. If it is not a shift, it pessimizes some common cases like: 2387 // 2388 //void foo(int *X, int i) { X[i & 1235] = 1; } 2389 //int bar(int *X, int i) { return X[i & 255]; } 2390 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2391 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2392 BinOpLHSVal->getOpcode() != ISD::SRA && 2393 BinOpLHSVal->getOpcode() != ISD::SRL) || 2394 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2395 return SDValue(); 2396 2397 MVT VT = N->getValueType(0); 2398 2399 // If this is a signed shift right, and the high bit is modified 2400 // by the logical operation, do not perform the transformation. 2401 // The highBitSet boolean indicates the value of the high bit of 2402 // the constant which would cause it to be modified for this 2403 // operation. 2404 if (N->getOpcode() == ISD::SRA) { 2405 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2406 if (BinOpRHSSignSet != HighBitSet) 2407 return SDValue(); 2408 } 2409 2410 // Fold the constants, shifting the binop RHS by the shift amount. 2411 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2412 LHS->getOperand(1), N->getOperand(1)); 2413 2414 // Create the new shift. 2415 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2416 N->getOperand(1)); 2417 2418 // Create the new binop. 2419 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2420} 2421 2422 2423SDValue DAGCombiner::visitSHL(SDNode *N) { 2424 SDValue N0 = N->getOperand(0); 2425 SDValue N1 = N->getOperand(1); 2426 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2427 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2428 MVT VT = N0.getValueType(); 2429 unsigned OpSizeInBits = VT.getSizeInBits(); 2430 2431 // fold (shl c1, c2) -> c1<<c2 2432 if (N0C && N1C) 2433 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2434 // fold (shl 0, x) -> 0 2435 if (N0C && N0C->isNullValue()) 2436 return N0; 2437 // fold (shl x, c >= size(x)) -> undef 2438 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2439 return DAG.getNode(ISD::UNDEF, VT); 2440 // fold (shl x, 0) -> x 2441 if (N1C && N1C->isNullValue()) 2442 return N0; 2443 // if (shl x, c) is known to be zero, return 0 2444 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2445 APInt::getAllOnesValue(VT.getSizeInBits()))) 2446 return DAG.getConstant(0, VT); 2447 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2448 // iff (trunc c) == c 2449 if (N1.getOpcode() == ISD::TRUNCATE && 2450 N1.getOperand(0).getOpcode() == ISD::AND && 2451 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2452 SDValue N101 = N1.getOperand(0).getOperand(1); 2453 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2454 MVT TruncVT = N1.getValueType(); 2455 SDValue N100 = N1.getOperand(0).getOperand(0); 2456 uint64_t TruncC = TruncVT.getIntegerVTBitMask() & 2457 N101C->getZExtValue(); 2458 return DAG.getNode(ISD::SHL, VT, N0, 2459 DAG.getNode(ISD::AND, TruncVT, 2460 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2461 DAG.getConstant(TruncC, TruncVT))); 2462 } 2463 } 2464 2465 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2466 return SDValue(N, 0); 2467 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2468 if (N1C && N0.getOpcode() == ISD::SHL && 2469 N0.getOperand(1).getOpcode() == ISD::Constant) { 2470 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2471 uint64_t c2 = N1C->getZExtValue(); 2472 if (c1 + c2 > OpSizeInBits) 2473 return DAG.getConstant(0, VT); 2474 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2475 DAG.getConstant(c1 + c2, N1.getValueType())); 2476 } 2477 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2478 // (srl (and x, -1 << c1), c1-c2) 2479 if (N1C && N0.getOpcode() == ISD::SRL && 2480 N0.getOperand(1).getOpcode() == ISD::Constant) { 2481 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2482 uint64_t c2 = N1C->getZExtValue(); 2483 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2484 DAG.getConstant(~0ULL << c1, VT)); 2485 if (c2 > c1) 2486 return DAG.getNode(ISD::SHL, VT, Mask, 2487 DAG.getConstant(c2-c1, N1.getValueType())); 2488 else 2489 return DAG.getNode(ISD::SRL, VT, Mask, 2490 DAG.getConstant(c1-c2, N1.getValueType())); 2491 } 2492 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2493 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2494 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2495 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2496 2497 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2498} 2499 2500SDValue DAGCombiner::visitSRA(SDNode *N) { 2501 SDValue N0 = N->getOperand(0); 2502 SDValue N1 = N->getOperand(1); 2503 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2504 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2505 MVT VT = N0.getValueType(); 2506 2507 // fold (sra c1, c2) -> c1>>c2 2508 if (N0C && N1C) 2509 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2510 // fold (sra 0, x) -> 0 2511 if (N0C && N0C->isNullValue()) 2512 return N0; 2513 // fold (sra -1, x) -> -1 2514 if (N0C && N0C->isAllOnesValue()) 2515 return N0; 2516 // fold (sra x, c >= size(x)) -> undef 2517 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2518 return DAG.getNode(ISD::UNDEF, VT); 2519 // fold (sra x, 0) -> x 2520 if (N1C && N1C->isNullValue()) 2521 return N0; 2522 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2523 // sext_inreg. 2524 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2525 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2526 MVT EVT = MVT::getIntegerVT(LowBits); 2527 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2528 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2529 DAG.getValueType(EVT)); 2530 } 2531 2532 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2533 if (N1C && N0.getOpcode() == ISD::SRA) { 2534 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2535 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2536 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2537 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2538 DAG.getConstant(Sum, N1C->getValueType(0))); 2539 } 2540 } 2541 2542 // fold sra (shl X, m), result_size - n 2543 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2544 // result_size - n != m. 2545 // If truncate is free for the target sext(shl) is likely to result in better 2546 // code. 2547 if (N0.getOpcode() == ISD::SHL) { 2548 // Get the two constanst of the shifts, CN0 = m, CN = n. 2549 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2550 if (N01C && N1C) { 2551 // Determine what the truncate's result bitsize and type would be. 2552 unsigned VTValSize = VT.getSizeInBits(); 2553 MVT TruncVT = 2554 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2555 // Determine the residual right-shift amount. 2556 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2557 2558 // If the shift is not a no-op (in which case this should be just a sign 2559 // extend already), the truncated to type is legal, sign_extend is legal 2560 // on that type, and the the truncate to that type is both legal and free, 2561 // perform the transform. 2562 if (ShiftAmt && 2563 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2564 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2565 TLI.isTruncateFree(VT, TruncVT)) { 2566 2567 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2568 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2569 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2570 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2571 } 2572 } 2573 } 2574 2575 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2576 // iff (trunc c) == c 2577 if (N1.getOpcode() == ISD::TRUNCATE && 2578 N1.getOperand(0).getOpcode() == ISD::AND && 2579 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2580 SDValue N101 = N1.getOperand(0).getOperand(1); 2581 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2582 MVT TruncVT = N1.getValueType(); 2583 SDValue N100 = N1.getOperand(0).getOperand(0); 2584 uint64_t TruncC = TruncVT.getIntegerVTBitMask() & 2585 N101C->getZExtValue(); 2586 return DAG.getNode(ISD::SRA, VT, N0, 2587 DAG.getNode(ISD::AND, TruncVT, 2588 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2589 DAG.getConstant(TruncC, TruncVT))); 2590 } 2591 } 2592 2593 // Simplify, based on bits shifted out of the LHS. 2594 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2595 return SDValue(N, 0); 2596 2597 2598 // If the sign bit is known to be zero, switch this to a SRL. 2599 if (DAG.SignBitIsZero(N0)) 2600 return DAG.getNode(ISD::SRL, VT, N0, N1); 2601 2602 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2603} 2604 2605SDValue DAGCombiner::visitSRL(SDNode *N) { 2606 SDValue N0 = N->getOperand(0); 2607 SDValue N1 = N->getOperand(1); 2608 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2609 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2610 MVT VT = N0.getValueType(); 2611 unsigned OpSizeInBits = VT.getSizeInBits(); 2612 2613 // fold (srl c1, c2) -> c1 >>u c2 2614 if (N0C && N1C) 2615 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2616 // fold (srl 0, x) -> 0 2617 if (N0C && N0C->isNullValue()) 2618 return N0; 2619 // fold (srl x, c >= size(x)) -> undef 2620 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2621 return DAG.getNode(ISD::UNDEF, VT); 2622 // fold (srl x, 0) -> x 2623 if (N1C && N1C->isNullValue()) 2624 return N0; 2625 // if (srl x, c) is known to be zero, return 0 2626 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2627 APInt::getAllOnesValue(OpSizeInBits))) 2628 return DAG.getConstant(0, VT); 2629 2630 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2631 if (N1C && N0.getOpcode() == ISD::SRL && 2632 N0.getOperand(1).getOpcode() == ISD::Constant) { 2633 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2634 uint64_t c2 = N1C->getZExtValue(); 2635 if (c1 + c2 > OpSizeInBits) 2636 return DAG.getConstant(0, VT); 2637 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2638 DAG.getConstant(c1 + c2, N1.getValueType())); 2639 } 2640 2641 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2642 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2643 // Shifting in all undef bits? 2644 MVT SmallVT = N0.getOperand(0).getValueType(); 2645 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2646 return DAG.getNode(ISD::UNDEF, VT); 2647 2648 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2649 AddToWorkList(SmallShift.getNode()); 2650 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2651 } 2652 2653 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2654 // bit, which is unmodified by sra. 2655 if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { 2656 if (N0.getOpcode() == ISD::SRA) 2657 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2658 } 2659 2660 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2661 if (N1C && N0.getOpcode() == ISD::CTLZ && 2662 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2663 APInt KnownZero, KnownOne; 2664 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2665 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2666 2667 // If any of the input bits are KnownOne, then the input couldn't be all 2668 // zeros, thus the result of the srl will always be zero. 2669 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2670 2671 // If all of the bits input the to ctlz node are known to be zero, then 2672 // the result of the ctlz is "32" and the result of the shift is one. 2673 APInt UnknownBits = ~KnownZero & Mask; 2674 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2675 2676 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2677 if ((UnknownBits & (UnknownBits-1)) == 0) { 2678 // Okay, we know that only that the single bit specified by UnknownBits 2679 // could be set on input to the CTLZ node. If this bit is set, the SRL 2680 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2681 // to an SRL,XOR pair, which is likely to simplify more. 2682 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2683 SDValue Op = N0.getOperand(0); 2684 if (ShAmt) { 2685 Op = DAG.getNode(ISD::SRL, VT, Op, 2686 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2687 AddToWorkList(Op.getNode()); 2688 } 2689 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2690 } 2691 } 2692 2693 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2694 // iff (trunc c) == c 2695 if (N1.getOpcode() == ISD::TRUNCATE && 2696 N1.getOperand(0).getOpcode() == ISD::AND && 2697 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2698 SDValue N101 = N1.getOperand(0).getOperand(1); 2699 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2700 MVT TruncVT = N1.getValueType(); 2701 SDValue N100 = N1.getOperand(0).getOperand(0); 2702 uint64_t TruncC = TruncVT.getIntegerVTBitMask() & 2703 N101C->getZExtValue(); 2704 return DAG.getNode(ISD::SRL, VT, N0, 2705 DAG.getNode(ISD::AND, TruncVT, 2706 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2707 DAG.getConstant(TruncC, TruncVT))); 2708 } 2709 } 2710 2711 // fold operands of srl based on knowledge that the low bits are not 2712 // demanded. 2713 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2714 return SDValue(N, 0); 2715 2716 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2717} 2718 2719SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2720 SDValue N0 = N->getOperand(0); 2721 MVT VT = N->getValueType(0); 2722 2723 // fold (ctlz c1) -> c2 2724 if (isa<ConstantSDNode>(N0)) 2725 return DAG.getNode(ISD::CTLZ, VT, N0); 2726 return SDValue(); 2727} 2728 2729SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2730 SDValue N0 = N->getOperand(0); 2731 MVT VT = N->getValueType(0); 2732 2733 // fold (cttz c1) -> c2 2734 if (isa<ConstantSDNode>(N0)) 2735 return DAG.getNode(ISD::CTTZ, VT, N0); 2736 return SDValue(); 2737} 2738 2739SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2740 SDValue N0 = N->getOperand(0); 2741 MVT VT = N->getValueType(0); 2742 2743 // fold (ctpop c1) -> c2 2744 if (isa<ConstantSDNode>(N0)) 2745 return DAG.getNode(ISD::CTPOP, VT, N0); 2746 return SDValue(); 2747} 2748 2749SDValue DAGCombiner::visitSELECT(SDNode *N) { 2750 SDValue N0 = N->getOperand(0); 2751 SDValue N1 = N->getOperand(1); 2752 SDValue N2 = N->getOperand(2); 2753 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2754 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2755 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2756 MVT VT = N->getValueType(0); 2757 MVT VT0 = N0.getValueType(); 2758 2759 // fold select C, X, X -> X 2760 if (N1 == N2) 2761 return N1; 2762 // fold select true, X, Y -> X 2763 if (N0C && !N0C->isNullValue()) 2764 return N1; 2765 // fold select false, X, Y -> Y 2766 if (N0C && N0C->isNullValue()) 2767 return N2; 2768 // fold select C, 1, X -> C | X 2769 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2770 return DAG.getNode(ISD::OR, VT, N0, N2); 2771 // fold select C, 0, 1 -> C ^ 1 2772 if (VT.isInteger() && 2773 (VT0 == MVT::i1 || 2774 (VT0.isInteger() && 2775 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2776 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2777 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2778 if (VT == VT0) 2779 return XORNode; 2780 AddToWorkList(XORNode.getNode()); 2781 if (VT.bitsGT(VT0)) 2782 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2783 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2784 } 2785 // fold select C, 0, X -> ~C & X 2786 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2787 SDValue NOTNode = DAG.getNOT(N0, VT); 2788 AddToWorkList(NOTNode.getNode()); 2789 return DAG.getNode(ISD::AND, VT, NOTNode, N2); 2790 } 2791 // fold select C, X, 1 -> ~C | X 2792 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2793 SDValue NOTNode = DAG.getNOT(N0, VT); 2794 AddToWorkList(NOTNode.getNode()); 2795 return DAG.getNode(ISD::OR, VT, NOTNode, N1); 2796 } 2797 // fold select C, X, 0 -> C & X 2798 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2799 return DAG.getNode(ISD::AND, VT, N0, N1); 2800 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2801 if (VT == MVT::i1 && N0 == N1) 2802 return DAG.getNode(ISD::OR, VT, N0, N2); 2803 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2804 if (VT == MVT::i1 && N0 == N2) 2805 return DAG.getNode(ISD::AND, VT, N0, N1); 2806 2807 // If we can fold this based on the true/false value, do so. 2808 if (SimplifySelectOps(N, N1, N2)) 2809 return SDValue(N, 0); // Don't revisit N. 2810 2811 // fold selects based on a setcc into other things, such as min/max/abs 2812 if (N0.getOpcode() == ISD::SETCC) { 2813 // FIXME: 2814 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2815 // having to say they don't support SELECT_CC on every type the DAG knows 2816 // about, since there is no way to mark an opcode illegal at all value types 2817 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2818 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2819 N1, N2, N0.getOperand(2)); 2820 else 2821 return SimplifySelect(N0, N1, N2); 2822 } 2823 return SDValue(); 2824} 2825 2826SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2827 SDValue N0 = N->getOperand(0); 2828 SDValue N1 = N->getOperand(1); 2829 SDValue N2 = N->getOperand(2); 2830 SDValue N3 = N->getOperand(3); 2831 SDValue N4 = N->getOperand(4); 2832 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2833 2834 // fold select_cc lhs, rhs, x, x, cc -> x 2835 if (N2 == N3) 2836 return N2; 2837 2838 // Determine if the condition we're dealing with is constant 2839 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2840 N0, N1, CC, false); 2841 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2842 2843 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2844 if (!SCCC->isNullValue()) 2845 return N2; // cond always true -> true val 2846 else 2847 return N3; // cond always false -> false val 2848 } 2849 2850 // Fold to a simpler select_cc 2851 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2852 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2853 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2854 SCC.getOperand(2)); 2855 2856 // If we can fold this based on the true/false value, do so. 2857 if (SimplifySelectOps(N, N2, N3)) 2858 return SDValue(N, 0); // Don't revisit N. 2859 2860 // fold select_cc into other things, such as min/max/abs 2861 return SimplifySelectCC(N0, N1, N2, N3, CC); 2862} 2863 2864SDValue DAGCombiner::visitSETCC(SDNode *N) { 2865 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2866 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2867} 2868 2869// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2870// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2871// transformation. Returns true if extension are possible and the above 2872// mentioned transformation is profitable. 2873static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2874 unsigned ExtOpc, 2875 SmallVector<SDNode*, 4> &ExtendNodes, 2876 const TargetLowering &TLI) { 2877 bool HasCopyToRegUses = false; 2878 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2879 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2880 UE = N0.getNode()->use_end(); 2881 UI != UE; ++UI) { 2882 SDNode *User = *UI; 2883 if (User == N) 2884 continue; 2885 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2886 if (User->getOpcode() == ISD::SETCC) { 2887 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2888 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2889 // Sign bits will be lost after a zext. 2890 return false; 2891 bool Add = false; 2892 for (unsigned i = 0; i != 2; ++i) { 2893 SDValue UseOp = User->getOperand(i); 2894 if (UseOp == N0) 2895 continue; 2896 if (!isa<ConstantSDNode>(UseOp)) 2897 return false; 2898 Add = true; 2899 } 2900 if (Add) 2901 ExtendNodes.push_back(User); 2902 } else { 2903 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2904 SDValue UseOp = User->getOperand(i); 2905 if (UseOp == N0) { 2906 // If truncate from extended type to original load type is free 2907 // on this target, then it's ok to extend a CopyToReg. 2908 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2909 HasCopyToRegUses = true; 2910 else 2911 return false; 2912 } 2913 } 2914 } 2915 } 2916 2917 if (HasCopyToRegUses) { 2918 bool BothLiveOut = false; 2919 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2920 UI != UE; ++UI) { 2921 SDNode *User = *UI; 2922 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2923 SDValue UseOp = User->getOperand(i); 2924 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2925 BothLiveOut = true; 2926 break; 2927 } 2928 } 2929 } 2930 if (BothLiveOut) 2931 // Both unextended and extended values are live out. There had better be 2932 // good a reason for the transformation. 2933 return ExtendNodes.size(); 2934 } 2935 return true; 2936} 2937 2938SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2939 SDValue N0 = N->getOperand(0); 2940 MVT VT = N->getValueType(0); 2941 2942 // fold (sext c1) -> c1 2943 if (isa<ConstantSDNode>(N0)) 2944 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2945 2946 // fold (sext (sext x)) -> (sext x) 2947 // fold (sext (aext x)) -> (sext x) 2948 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2949 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2950 2951 if (N0.getOpcode() == ISD::TRUNCATE) { 2952 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2953 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2954 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2955 if (NarrowLoad.getNode()) { 2956 if (NarrowLoad.getNode() != N0.getNode()) 2957 CombineTo(N0.getNode(), NarrowLoad); 2958 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2959 } 2960 2961 // See if the value being truncated is already sign extended. If so, just 2962 // eliminate the trunc/sext pair. 2963 SDValue Op = N0.getOperand(0); 2964 unsigned OpBits = Op.getValueType().getSizeInBits(); 2965 unsigned MidBits = N0.getValueType().getSizeInBits(); 2966 unsigned DestBits = VT.getSizeInBits(); 2967 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2968 2969 if (OpBits == DestBits) { 2970 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2971 // bits, it is already ready. 2972 if (NumSignBits > DestBits-MidBits) 2973 return Op; 2974 } else if (OpBits < DestBits) { 2975 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2976 // bits, just sext from i32. 2977 if (NumSignBits > OpBits-MidBits) 2978 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2979 } else { 2980 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2981 // bits, just truncate to i32. 2982 if (NumSignBits > OpBits-MidBits) 2983 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2984 } 2985 2986 // fold (sext (truncate x)) -> (sextinreg x). 2987 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2988 N0.getValueType())) { 2989 if (Op.getValueType().bitsLT(VT)) 2990 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2991 else if (Op.getValueType().bitsGT(VT)) 2992 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2993 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2994 DAG.getValueType(N0.getValueType())); 2995 } 2996 } 2997 2998 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2999 if (ISD::isNON_EXTLoad(N0.getNode()) && 3000 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3001 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3002 bool DoXform = true; 3003 SmallVector<SDNode*, 4> SetCCs; 3004 if (!N0.hasOneUse()) 3005 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3006 if (DoXform) { 3007 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3008 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3009 LN0->getBasePtr(), LN0->getSrcValue(), 3010 LN0->getSrcValueOffset(), 3011 N0.getValueType(), 3012 LN0->isVolatile(), LN0->getAlignment()); 3013 CombineTo(N, ExtLoad); 3014 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3015 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3016 // Extend SetCC uses if necessary. 3017 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3018 SDNode *SetCC = SetCCs[i]; 3019 SmallVector<SDValue, 4> Ops; 3020 for (unsigned j = 0; j != 2; ++j) { 3021 SDValue SOp = SetCC->getOperand(j); 3022 if (SOp == Trunc) 3023 Ops.push_back(ExtLoad); 3024 else 3025 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 3026 } 3027 Ops.push_back(SetCC->getOperand(2)); 3028 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3029 &Ops[0], Ops.size())); 3030 } 3031 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3032 } 3033 } 3034 3035 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3036 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3037 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3038 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3039 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3040 MVT EVT = LN0->getMemoryVT(); 3041 if ((!LegalOperations && !LN0->isVolatile()) || 3042 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3043 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3044 LN0->getBasePtr(), LN0->getSrcValue(), 3045 LN0->getSrcValueOffset(), EVT, 3046 LN0->isVolatile(), LN0->getAlignment()); 3047 CombineTo(N, ExtLoad); 3048 CombineTo(N0.getNode(), 3049 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3050 ExtLoad.getValue(1)); 3051 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3052 } 3053 } 3054 3055 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 3056 if (N0.getOpcode() == ISD::SETCC) { 3057 SDValue SCC = 3058 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3059 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3060 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3061 if (SCC.getNode()) return SCC; 3062 } 3063 3064 // fold (sext x) -> (zext x) if the sign bit is known zero. 3065 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3066 DAG.SignBitIsZero(N0)) 3067 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3068 3069 return SDValue(); 3070} 3071 3072SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3073 SDValue N0 = N->getOperand(0); 3074 MVT VT = N->getValueType(0); 3075 3076 // fold (zext c1) -> c1 3077 if (isa<ConstantSDNode>(N0)) 3078 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3079 // fold (zext (zext x)) -> (zext x) 3080 // fold (zext (aext x)) -> (zext x) 3081 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3082 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 3083 3084 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3085 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3086 if (N0.getOpcode() == ISD::TRUNCATE) { 3087 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3088 if (NarrowLoad.getNode()) { 3089 if (NarrowLoad.getNode() != N0.getNode()) 3090 CombineTo(N0.getNode(), NarrowLoad); 3091 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 3092 } 3093 } 3094 3095 // fold (zext (truncate x)) -> (and x, mask) 3096 if (N0.getOpcode() == ISD::TRUNCATE && 3097 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3098 SDValue Op = N0.getOperand(0); 3099 if (Op.getValueType().bitsLT(VT)) { 3100 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 3101 } else if (Op.getValueType().bitsGT(VT)) { 3102 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3103 } 3104 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 3105 } 3106 3107 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3108 if (N0.getOpcode() == ISD::AND && 3109 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3110 N0.getOperand(1).getOpcode() == ISD::Constant) { 3111 SDValue X = N0.getOperand(0).getOperand(0); 3112 if (X.getValueType().bitsLT(VT)) { 3113 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3114 } else if (X.getValueType().bitsGT(VT)) { 3115 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3116 } 3117 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3118 Mask.zext(VT.getSizeInBits()); 3119 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3120 } 3121 3122 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3123 if (ISD::isNON_EXTLoad(N0.getNode()) && 3124 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3125 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3126 bool DoXform = true; 3127 SmallVector<SDNode*, 4> SetCCs; 3128 if (!N0.hasOneUse()) 3129 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3130 if (DoXform) { 3131 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3132 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3133 LN0->getBasePtr(), LN0->getSrcValue(), 3134 LN0->getSrcValueOffset(), 3135 N0.getValueType(), 3136 LN0->isVolatile(), LN0->getAlignment()); 3137 CombineTo(N, ExtLoad); 3138 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3139 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3140 // Extend SetCC uses if necessary. 3141 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3142 SDNode *SetCC = SetCCs[i]; 3143 SmallVector<SDValue, 4> Ops; 3144 for (unsigned j = 0; j != 2; ++j) { 3145 SDValue SOp = SetCC->getOperand(j); 3146 if (SOp == Trunc) 3147 Ops.push_back(ExtLoad); 3148 else 3149 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3150 } 3151 Ops.push_back(SetCC->getOperand(2)); 3152 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3153 &Ops[0], Ops.size())); 3154 } 3155 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3156 } 3157 } 3158 3159 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3160 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3161 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3162 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3163 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3164 MVT EVT = LN0->getMemoryVT(); 3165 if ((!LegalOperations && !LN0->isVolatile()) || 3166 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3167 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3168 LN0->getBasePtr(), LN0->getSrcValue(), 3169 LN0->getSrcValueOffset(), EVT, 3170 LN0->isVolatile(), LN0->getAlignment()); 3171 CombineTo(N, ExtLoad); 3172 CombineTo(N0.getNode(), 3173 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3174 ExtLoad.getValue(1)); 3175 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3176 } 3177 } 3178 3179 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3180 if (N0.getOpcode() == ISD::SETCC) { 3181 SDValue SCC = 3182 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3183 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3184 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3185 if (SCC.getNode()) return SCC; 3186 } 3187 3188 return SDValue(); 3189} 3190 3191SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3192 SDValue N0 = N->getOperand(0); 3193 MVT VT = N->getValueType(0); 3194 3195 // fold (aext c1) -> c1 3196 if (isa<ConstantSDNode>(N0)) 3197 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3198 // fold (aext (aext x)) -> (aext x) 3199 // fold (aext (zext x)) -> (zext x) 3200 // fold (aext (sext x)) -> (sext x) 3201 if (N0.getOpcode() == ISD::ANY_EXTEND || 3202 N0.getOpcode() == ISD::ZERO_EXTEND || 3203 N0.getOpcode() == ISD::SIGN_EXTEND) 3204 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3205 3206 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3207 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3208 if (N0.getOpcode() == ISD::TRUNCATE) { 3209 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3210 if (NarrowLoad.getNode()) { 3211 if (NarrowLoad.getNode() != N0.getNode()) 3212 CombineTo(N0.getNode(), NarrowLoad); 3213 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3214 } 3215 } 3216 3217 // fold (aext (truncate x)) 3218 if (N0.getOpcode() == ISD::TRUNCATE) { 3219 SDValue TruncOp = N0.getOperand(0); 3220 if (TruncOp.getValueType() == VT) 3221 return TruncOp; // x iff x size == zext size. 3222 if (TruncOp.getValueType().bitsGT(VT)) 3223 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3224 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3225 } 3226 3227 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3228 if (N0.getOpcode() == ISD::AND && 3229 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3230 N0.getOperand(1).getOpcode() == ISD::Constant) { 3231 SDValue X = N0.getOperand(0).getOperand(0); 3232 if (X.getValueType().bitsLT(VT)) { 3233 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3234 } else if (X.getValueType().bitsGT(VT)) { 3235 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3236 } 3237 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3238 Mask.zext(VT.getSizeInBits()); 3239 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3240 } 3241 3242 // fold (aext (load x)) -> (aext (truncate (extload x))) 3243 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3244 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3245 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3246 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3247 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3248 LN0->getBasePtr(), LN0->getSrcValue(), 3249 LN0->getSrcValueOffset(), 3250 N0.getValueType(), 3251 LN0->isVolatile(), LN0->getAlignment()); 3252 CombineTo(N, ExtLoad); 3253 // Redirect any chain users to the new load. 3254 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3255 SDValue(ExtLoad.getNode(), 1)); 3256 // If any node needs the original loaded value, recompute it. 3257 if (!LN0->use_empty()) 3258 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3259 ExtLoad.getValue(1)); 3260 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3261 } 3262 3263 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3264 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3265 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3266 if (N0.getOpcode() == ISD::LOAD && 3267 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3268 N0.hasOneUse()) { 3269 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3270 MVT EVT = LN0->getMemoryVT(); 3271 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3272 LN0->getChain(), LN0->getBasePtr(), 3273 LN0->getSrcValue(), 3274 LN0->getSrcValueOffset(), EVT, 3275 LN0->isVolatile(), LN0->getAlignment()); 3276 CombineTo(N, ExtLoad); 3277 CombineTo(N0.getNode(), 3278 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3279 ExtLoad.getValue(1)); 3280 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3281 } 3282 3283 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3284 if (N0.getOpcode() == ISD::SETCC) { 3285 SDValue SCC = 3286 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3287 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3288 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3289 if (SCC.getNode()) 3290 return SCC; 3291 } 3292 3293 return SDValue(); 3294} 3295 3296/// GetDemandedBits - See if the specified operand can be simplified with the 3297/// knowledge that only the bits specified by Mask are used. If so, return the 3298/// simpler operand, otherwise return a null SDValue. 3299SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3300 switch (V.getOpcode()) { 3301 default: break; 3302 case ISD::OR: 3303 case ISD::XOR: 3304 // If the LHS or RHS don't contribute bits to the or, drop them. 3305 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3306 return V.getOperand(1); 3307 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3308 return V.getOperand(0); 3309 break; 3310 case ISD::SRL: 3311 // Only look at single-use SRLs. 3312 if (!V.getNode()->hasOneUse()) 3313 break; 3314 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3315 // See if we can recursively simplify the LHS. 3316 unsigned Amt = RHSC->getZExtValue(); 3317 // Watch out for shift count overflow though. 3318 if (Amt >= Mask.getBitWidth()) break; 3319 APInt NewMask = Mask << Amt; 3320 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3321 if (SimplifyLHS.getNode()) { 3322 return DAG.getNode(ISD::SRL, V.getValueType(), 3323 SimplifyLHS, V.getOperand(1)); 3324 } 3325 } 3326 } 3327 return SDValue(); 3328} 3329 3330/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3331/// bits and then truncated to a narrower type and where N is a multiple 3332/// of number of bits of the narrower type, transform it to a narrower load 3333/// from address + N / num of bits of new type. If the result is to be 3334/// extended, also fold the extension to form a extending load. 3335SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3336 unsigned Opc = N->getOpcode(); 3337 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3338 SDValue N0 = N->getOperand(0); 3339 MVT VT = N->getValueType(0); 3340 MVT EVT = VT; 3341 3342 // This transformation isn't valid for vector loads. 3343 if (VT.isVector()) 3344 return SDValue(); 3345 3346 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3347 // extended to VT. 3348 if (Opc == ISD::SIGN_EXTEND_INREG) { 3349 ExtType = ISD::SEXTLOAD; 3350 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3351 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3352 return SDValue(); 3353 } 3354 3355 unsigned EVTBits = EVT.getSizeInBits(); 3356 unsigned ShAmt = 0; 3357 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3358 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3359 ShAmt = N01->getZExtValue(); 3360 // Is the shift amount a multiple of size of VT? 3361 if ((ShAmt & (EVTBits-1)) == 0) { 3362 N0 = N0.getOperand(0); 3363 if (N0.getValueType().getSizeInBits() <= EVTBits) 3364 return SDValue(); 3365 } 3366 } 3367 } 3368 3369 // Do not generate loads of non-round integer types since these can 3370 // be expensive (and would be wrong if the type is not byte sized). 3371 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3372 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3373 // Do not change the width of a volatile load. 3374 !cast<LoadSDNode>(N0)->isVolatile()) { 3375 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3376 MVT PtrType = N0.getOperand(1).getValueType(); 3377 // For big endian targets, we need to adjust the offset to the pointer to 3378 // load the correct bytes. 3379 if (TLI.isBigEndian()) { 3380 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3381 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3382 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3383 } 3384 uint64_t PtrOff = ShAmt / 8; 3385 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3386 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3387 DAG.getConstant(PtrOff, PtrType)); 3388 AddToWorkList(NewPtr.getNode()); 3389 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3390 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3391 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3392 LN0->isVolatile(), NewAlign) 3393 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3394 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3395 EVT, LN0->isVolatile(), NewAlign); 3396 // Replace the old load's chain with the new load's chain. 3397 WorkListRemover DeadNodes(*this); 3398 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3399 &DeadNodes); 3400 // Return the new loaded value. 3401 return Load; 3402 } 3403 3404 return SDValue(); 3405} 3406 3407 3408SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3409 SDValue N0 = N->getOperand(0); 3410 SDValue N1 = N->getOperand(1); 3411 MVT VT = N->getValueType(0); 3412 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3413 unsigned VTBits = VT.getSizeInBits(); 3414 unsigned EVTBits = EVT.getSizeInBits(); 3415 3416 // fold (sext_in_reg c1) -> c1 3417 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3418 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3419 3420 // If the input is already sign extended, just drop the extension. 3421 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3422 return N0; 3423 3424 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3425 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3426 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3427 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3428 } 3429 3430 // fold (sext_in_reg (sext x)) -> (sext x) 3431 // fold (sext_in_reg (aext x)) -> (sext x) 3432 // if x is small enough. 3433 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3434 SDValue N00 = N0.getOperand(0); 3435 if (N00.getValueType().getSizeInBits() < EVTBits) 3436 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3437 } 3438 3439 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3440 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3441 return DAG.getZeroExtendInReg(N0, EVT); 3442 3443 // fold operands of sext_in_reg based on knowledge that the top bits are not 3444 // demanded. 3445 if (SimplifyDemandedBits(SDValue(N, 0))) 3446 return SDValue(N, 0); 3447 3448 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3449 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3450 SDValue NarrowLoad = ReduceLoadWidth(N); 3451 if (NarrowLoad.getNode()) 3452 return NarrowLoad; 3453 3454 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3455 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3456 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3457 if (N0.getOpcode() == ISD::SRL) { 3458 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3459 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3460 // We can turn this into an SRA iff the input to the SRL is already sign 3461 // extended enough. 3462 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3463 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3464 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3465 } 3466 } 3467 3468 // fold (sext_inreg (extload x)) -> (sextload x) 3469 if (ISD::isEXTLoad(N0.getNode()) && 3470 ISD::isUNINDEXEDLoad(N0.getNode()) && 3471 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3472 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3473 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3474 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3475 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3476 LN0->getBasePtr(), LN0->getSrcValue(), 3477 LN0->getSrcValueOffset(), EVT, 3478 LN0->isVolatile(), LN0->getAlignment()); 3479 CombineTo(N, ExtLoad); 3480 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3481 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3482 } 3483 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3484 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3485 N0.hasOneUse() && 3486 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3487 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3488 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3489 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3490 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3491 LN0->getBasePtr(), LN0->getSrcValue(), 3492 LN0->getSrcValueOffset(), EVT, 3493 LN0->isVolatile(), LN0->getAlignment()); 3494 CombineTo(N, ExtLoad); 3495 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3496 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3497 } 3498 return SDValue(); 3499} 3500 3501SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3502 SDValue N0 = N->getOperand(0); 3503 MVT VT = N->getValueType(0); 3504 3505 // noop truncate 3506 if (N0.getValueType() == N->getValueType(0)) 3507 return N0; 3508 // fold (truncate c1) -> c1 3509 if (isa<ConstantSDNode>(N0)) 3510 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3511 // fold (truncate (truncate x)) -> (truncate x) 3512 if (N0.getOpcode() == ISD::TRUNCATE) 3513 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3514 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3515 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3516 N0.getOpcode() == ISD::ANY_EXTEND) { 3517 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3518 // if the source is smaller than the dest, we still need an extend 3519 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3520 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3521 // if the source is larger than the dest, than we just need the truncate 3522 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3523 else 3524 // if the source and dest are the same type, we can drop both the extend 3525 // and the truncate 3526 return N0.getOperand(0); 3527 } 3528 3529 // See if we can simplify the input to this truncate through knowledge that 3530 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3531 // -> trunc y 3532 SDValue Shorter = 3533 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3534 VT.getSizeInBits())); 3535 if (Shorter.getNode()) 3536 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3537 3538 // fold (truncate (load x)) -> (smaller load x) 3539 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3540 return ReduceLoadWidth(N); 3541} 3542 3543static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3544 SDValue Elt = N->getOperand(i); 3545 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3546 return Elt.getNode(); 3547 return Elt.getOperand(Elt.getResNo()).getNode(); 3548} 3549 3550/// CombineConsecutiveLoads - build_pair (load, load) -> load 3551/// if load locations are consecutive. 3552SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3553 assert(N->getOpcode() == ISD::BUILD_PAIR); 3554 3555 SDNode *LD1 = getBuildPairElt(N, 0); 3556 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3557 return SDValue(); 3558 MVT LD1VT = LD1->getValueType(0); 3559 SDNode *LD2 = getBuildPairElt(N, 1); 3560 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3561 if (ISD::isNON_EXTLoad(LD2) && 3562 LD2->hasOneUse() && 3563 // If both are volatile this would reduce the number of volatile loads. 3564 // If one is volatile it might be ok, but play conservative and bail out. 3565 !cast<LoadSDNode>(LD1)->isVolatile() && 3566 !cast<LoadSDNode>(LD2)->isVolatile() && 3567 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3568 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3569 unsigned Align = LD->getAlignment(); 3570 unsigned NewAlign = TLI.getTargetData()-> 3571 getABITypeAlignment(VT.getTypeForMVT()); 3572 if (NewAlign <= Align && 3573 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3574 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3575 LD->getSrcValue(), LD->getSrcValueOffset(), 3576 false, Align); 3577 } 3578 return SDValue(); 3579} 3580 3581SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3582 SDValue N0 = N->getOperand(0); 3583 MVT VT = N->getValueType(0); 3584 3585 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3586 // Only do this before legalize, since afterward the target may be depending 3587 // on the bitconvert. 3588 // First check to see if this is all constant. 3589 if (!LegalTypes && 3590 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3591 VT.isVector()) { 3592 bool isSimple = true; 3593 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3594 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3595 N0.getOperand(i).getOpcode() != ISD::Constant && 3596 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3597 isSimple = false; 3598 break; 3599 } 3600 3601 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3602 assert(!DestEltVT.isVector() && 3603 "Element type of vector ValueType must not be vector!"); 3604 if (isSimple) { 3605 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3606 } 3607 } 3608 3609 // If the input is a constant, let getNode fold it. 3610 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3611 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3612 if (Res.getNode() != N) return Res; 3613 } 3614 3615 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3616 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3617 3618 // fold (conv (load x)) -> (load (conv*)x) 3619 // If the resultant load doesn't need a higher alignment than the original! 3620 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3621 // Do not change the width of a volatile load. 3622 !cast<LoadSDNode>(N0)->isVolatile() && 3623 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3624 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3625 unsigned Align = TLI.getTargetData()-> 3626 getABITypeAlignment(VT.getTypeForMVT()); 3627 unsigned OrigAlign = LN0->getAlignment(); 3628 if (Align <= OrigAlign) { 3629 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3630 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3631 LN0->isVolatile(), OrigAlign); 3632 AddToWorkList(N); 3633 CombineTo(N0.getNode(), 3634 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3635 Load.getValue(1)); 3636 return Load; 3637 } 3638 } 3639 3640 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3641 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3642 // This often reduces constant pool loads. 3643 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3644 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3645 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3646 AddToWorkList(NewConv.getNode()); 3647 3648 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3649 if (N0.getOpcode() == ISD::FNEG) 3650 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3651 assert(N0.getOpcode() == ISD::FABS); 3652 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3653 } 3654 3655 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3656 // Note that we don't handle copysign(x,cst) because this can always be folded 3657 // to an fneg or fabs. 3658 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3659 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3660 VT.isInteger() && !VT.isVector()) { 3661 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3662 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3663 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3664 SDValue X = DAG.getNode(ISD::BIT_CONVERT, IntXVT, N0.getOperand(1)); 3665 AddToWorkList(X.getNode()); 3666 3667 // If X has a different width than the result/lhs, sext it or truncate it. 3668 unsigned VTWidth = VT.getSizeInBits(); 3669 if (OrigXWidth < VTWidth) { 3670 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3671 AddToWorkList(X.getNode()); 3672 } else if (OrigXWidth > VTWidth) { 3673 // To get the sign bit in the right place, we have to shift it right 3674 // before truncating. 3675 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3676 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3677 AddToWorkList(X.getNode()); 3678 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3679 AddToWorkList(X.getNode()); 3680 } 3681 3682 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3683 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3684 AddToWorkList(X.getNode()); 3685 3686 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3687 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3688 AddToWorkList(Cst.getNode()); 3689 3690 return DAG.getNode(ISD::OR, VT, X, Cst); 3691 } 3692 } 3693 3694 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3695 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3696 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3697 if (CombineLD.getNode()) 3698 return CombineLD; 3699 } 3700 3701 return SDValue(); 3702} 3703 3704SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3705 MVT VT = N->getValueType(0); 3706 return CombineConsecutiveLoads(N, VT); 3707} 3708 3709/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3710/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3711/// destination element value type. 3712SDValue DAGCombiner:: 3713ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3714 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3715 3716 // If this is already the right type, we're done. 3717 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3718 3719 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3720 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3721 3722 // If this is a conversion of N elements of one type to N elements of another 3723 // type, convert each element. This handles FP<->INT cases. 3724 if (SrcBitSize == DstBitSize) { 3725 SmallVector<SDValue, 8> Ops; 3726 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3727 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3728 AddToWorkList(Ops.back().getNode()); 3729 } 3730 MVT VT = MVT::getVectorVT(DstEltVT, 3731 BV->getValueType(0).getVectorNumElements()); 3732 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3733 } 3734 3735 // Otherwise, we're growing or shrinking the elements. To avoid having to 3736 // handle annoying details of growing/shrinking FP values, we convert them to 3737 // int first. 3738 if (SrcEltVT.isFloatingPoint()) { 3739 // Convert the input float vector to a int vector where the elements are the 3740 // same sizes. 3741 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3742 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3743 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3744 SrcEltVT = IntVT; 3745 } 3746 3747 // Now we know the input is an integer vector. If the output is a FP type, 3748 // convert to integer first, then to FP of the right size. 3749 if (DstEltVT.isFloatingPoint()) { 3750 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3751 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3752 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3753 3754 // Next, convert to FP elements of the same size. 3755 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3756 } 3757 3758 // Okay, we know the src/dst types are both integers of differing types. 3759 // Handling growing first. 3760 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3761 if (SrcBitSize < DstBitSize) { 3762 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3763 3764 SmallVector<SDValue, 8> Ops; 3765 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3766 i += NumInputsPerOutput) { 3767 bool isLE = TLI.isLittleEndian(); 3768 APInt NewBits = APInt(DstBitSize, 0); 3769 bool EltIsUndef = true; 3770 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3771 // Shift the previously computed bits over. 3772 NewBits <<= SrcBitSize; 3773 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3774 if (Op.getOpcode() == ISD::UNDEF) continue; 3775 EltIsUndef = false; 3776 3777 NewBits |= 3778 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3779 } 3780 3781 if (EltIsUndef) 3782 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3783 else 3784 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3785 } 3786 3787 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3788 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3789 } 3790 3791 // Finally, this must be the case where we are shrinking elements: each input 3792 // turns into multiple outputs. 3793 bool isS2V = ISD::isScalarToVector(BV); 3794 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3795 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3796 SmallVector<SDValue, 8> Ops; 3797 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3798 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3799 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3800 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3801 continue; 3802 } 3803 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3804 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3805 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3806 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3807 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3808 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3809 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3810 OpVal = OpVal.lshr(DstBitSize); 3811 } 3812 3813 // For big endian targets, swap the order of the pieces of each element. 3814 if (TLI.isBigEndian()) 3815 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3816 } 3817 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3818} 3819 3820 3821 3822SDValue DAGCombiner::visitFADD(SDNode *N) { 3823 SDValue N0 = N->getOperand(0); 3824 SDValue N1 = N->getOperand(1); 3825 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3826 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3827 MVT VT = N->getValueType(0); 3828 3829 // fold vector ops 3830 if (VT.isVector()) { 3831 SDValue FoldedVOp = SimplifyVBinOp(N); 3832 if (FoldedVOp.getNode()) return FoldedVOp; 3833 } 3834 3835 // fold (fadd c1, c2) -> c1+c2 3836 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3837 return DAG.getNode(ISD::FADD, VT, N0, N1); 3838 // canonicalize constant to RHS 3839 if (N0CFP && !N1CFP) 3840 return DAG.getNode(ISD::FADD, VT, N1, N0); 3841 // fold (A + 0) -> A 3842 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3843 return N0; 3844 // fold (A + (-B)) -> A-B 3845 if (isNegatibleForFree(N1, LegalOperations) == 2) 3846 return DAG.getNode(ISD::FSUB, VT, N0, 3847 GetNegatedExpression(N1, DAG, LegalOperations)); 3848 // fold ((-A) + B) -> B-A 3849 if (isNegatibleForFree(N0, LegalOperations) == 2) 3850 return DAG.getNode(ISD::FSUB, VT, N1, 3851 GetNegatedExpression(N0, DAG, LegalOperations)); 3852 3853 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3854 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3855 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3856 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3857 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3858 3859 return SDValue(); 3860} 3861 3862SDValue DAGCombiner::visitFSUB(SDNode *N) { 3863 SDValue N0 = N->getOperand(0); 3864 SDValue N1 = N->getOperand(1); 3865 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3866 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3867 MVT VT = N->getValueType(0); 3868 3869 // fold vector ops 3870 if (VT.isVector()) { 3871 SDValue FoldedVOp = SimplifyVBinOp(N); 3872 if (FoldedVOp.getNode()) return FoldedVOp; 3873 } 3874 3875 // fold (fsub c1, c2) -> c1-c2 3876 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3877 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3878 // fold (A-0) -> A 3879 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3880 return N0; 3881 // fold (0-B) -> -B 3882 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3883 if (isNegatibleForFree(N1, LegalOperations)) 3884 return GetNegatedExpression(N1, DAG, LegalOperations); 3885 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3886 return DAG.getNode(ISD::FNEG, VT, N1); 3887 } 3888 // fold (A-(-B)) -> A+B 3889 if (isNegatibleForFree(N1, LegalOperations)) 3890 return DAG.getNode(ISD::FADD, VT, N0, 3891 GetNegatedExpression(N1, DAG, LegalOperations)); 3892 3893 return SDValue(); 3894} 3895 3896SDValue DAGCombiner::visitFMUL(SDNode *N) { 3897 SDValue N0 = N->getOperand(0); 3898 SDValue N1 = N->getOperand(1); 3899 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3900 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3901 MVT VT = N->getValueType(0); 3902 3903 // fold vector ops 3904 if (VT.isVector()) { 3905 SDValue FoldedVOp = SimplifyVBinOp(N); 3906 if (FoldedVOp.getNode()) return FoldedVOp; 3907 } 3908 3909 // fold (fmul c1, c2) -> c1*c2 3910 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3911 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3912 // canonicalize constant to RHS 3913 if (N0CFP && !N1CFP) 3914 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3915 // fold (A * 0) -> 0 3916 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3917 return N1; 3918 // fold (fmul X, 2.0) -> (fadd X, X) 3919 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3920 return DAG.getNode(ISD::FADD, VT, N0, N0); 3921 // fold (fmul X, -1.0) -> (fneg X) 3922 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3923 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3924 return DAG.getNode(ISD::FNEG, VT, N0); 3925 3926 // -X * -Y -> X*Y 3927 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3928 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3929 // Both can be negated for free, check to see if at least one is cheaper 3930 // negated. 3931 if (LHSNeg == 2 || RHSNeg == 2) 3932 return DAG.getNode(ISD::FMUL, VT, 3933 GetNegatedExpression(N0, DAG, LegalOperations), 3934 GetNegatedExpression(N1, DAG, LegalOperations)); 3935 } 3936 } 3937 3938 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3939 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3940 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3941 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3942 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3943 3944 return SDValue(); 3945} 3946 3947SDValue DAGCombiner::visitFDIV(SDNode *N) { 3948 SDValue N0 = N->getOperand(0); 3949 SDValue N1 = N->getOperand(1); 3950 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3951 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3952 MVT VT = N->getValueType(0); 3953 3954 // fold vector ops 3955 if (VT.isVector()) { 3956 SDValue FoldedVOp = SimplifyVBinOp(N); 3957 if (FoldedVOp.getNode()) return FoldedVOp; 3958 } 3959 3960 // fold (fdiv c1, c2) -> c1/c2 3961 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3962 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3963 3964 3965 // -X / -Y -> X*Y 3966 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3967 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3968 // Both can be negated for free, check to see if at least one is cheaper 3969 // negated. 3970 if (LHSNeg == 2 || RHSNeg == 2) 3971 return DAG.getNode(ISD::FDIV, VT, 3972 GetNegatedExpression(N0, DAG, LegalOperations), 3973 GetNegatedExpression(N1, DAG, LegalOperations)); 3974 } 3975 } 3976 3977 return SDValue(); 3978} 3979 3980SDValue DAGCombiner::visitFREM(SDNode *N) { 3981 SDValue N0 = N->getOperand(0); 3982 SDValue N1 = N->getOperand(1); 3983 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3984 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3985 MVT VT = N->getValueType(0); 3986 3987 // fold (frem c1, c2) -> fmod(c1,c2) 3988 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3989 return DAG.getNode(ISD::FREM, VT, N0, N1); 3990 3991 return SDValue(); 3992} 3993 3994SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3995 SDValue N0 = N->getOperand(0); 3996 SDValue N1 = N->getOperand(1); 3997 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3998 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3999 MVT VT = N->getValueType(0); 4000 4001 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4002 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 4003 4004 if (N1CFP) { 4005 const APFloat& V = N1CFP->getValueAPF(); 4006 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4007 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4008 if (!V.isNegative()) { 4009 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4010 return DAG.getNode(ISD::FABS, VT, N0); 4011 } else { 4012 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4013 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 4014 } 4015 } 4016 4017 // copysign(fabs(x), y) -> copysign(x, y) 4018 // copysign(fneg(x), y) -> copysign(x, y) 4019 // copysign(copysign(x,z), y) -> copysign(x, y) 4020 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4021 N0.getOpcode() == ISD::FCOPYSIGN) 4022 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 4023 4024 // copysign(x, abs(y)) -> abs(x) 4025 if (N1.getOpcode() == ISD::FABS) 4026 return DAG.getNode(ISD::FABS, VT, N0); 4027 4028 // copysign(x, copysign(y,z)) -> copysign(x, z) 4029 if (N1.getOpcode() == ISD::FCOPYSIGN) 4030 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 4031 4032 // copysign(x, fp_extend(y)) -> copysign(x, y) 4033 // copysign(x, fp_round(y)) -> copysign(x, y) 4034 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4035 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 4036 4037 return SDValue(); 4038} 4039 4040 4041 4042SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4043 SDValue N0 = N->getOperand(0); 4044 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4045 MVT VT = N->getValueType(0); 4046 MVT OpVT = N0.getValueType(); 4047 4048 // fold (sint_to_fp c1) -> c1fp 4049 if (N0C && OpVT != MVT::ppcf128) 4050 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 4051 4052 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4053 // but UINT_TO_FP is legal on this target, try to convert. 4054 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4055 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4056 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4057 if (DAG.SignBitIsZero(N0)) 4058 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4059 } 4060 4061 4062 return SDValue(); 4063} 4064 4065SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4066 SDValue N0 = N->getOperand(0); 4067 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4068 MVT VT = N->getValueType(0); 4069 MVT OpVT = N0.getValueType(); 4070 4071 // fold (uint_to_fp c1) -> c1fp 4072 if (N0C && OpVT != MVT::ppcf128) 4073 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4074 4075 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4076 // but SINT_TO_FP is legal on this target, try to convert. 4077 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4078 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4079 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4080 if (DAG.SignBitIsZero(N0)) 4081 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 4082 } 4083 4084 return SDValue(); 4085} 4086 4087SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4088 SDValue N0 = N->getOperand(0); 4089 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4090 MVT VT = N->getValueType(0); 4091 4092 // fold (fp_to_sint c1fp) -> c1 4093 if (N0CFP) 4094 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 4095 return SDValue(); 4096} 4097 4098SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4099 SDValue N0 = N->getOperand(0); 4100 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4101 MVT VT = N->getValueType(0); 4102 4103 // fold (fp_to_uint c1fp) -> c1 4104 if (N0CFP && VT != MVT::ppcf128) 4105 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 4106 return SDValue(); 4107} 4108 4109SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4110 SDValue N0 = N->getOperand(0); 4111 SDValue N1 = N->getOperand(1); 4112 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4113 MVT VT = N->getValueType(0); 4114 4115 // fold (fp_round c1fp) -> c1fp 4116 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4117 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 4118 4119 // fold (fp_round (fp_extend x)) -> x 4120 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4121 return N0.getOperand(0); 4122 4123 // fold (fp_round (fp_round x)) -> (fp_round x) 4124 if (N0.getOpcode() == ISD::FP_ROUND) { 4125 // This is a value preserving truncation if both round's are. 4126 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4127 N0.getNode()->getConstantOperandVal(1) == 1; 4128 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 4129 DAG.getIntPtrConstant(IsTrunc)); 4130 } 4131 4132 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4133 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4134 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 4135 AddToWorkList(Tmp.getNode()); 4136 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 4137 } 4138 4139 return SDValue(); 4140} 4141 4142SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4143 SDValue N0 = N->getOperand(0); 4144 MVT VT = N->getValueType(0); 4145 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4146 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4147 4148 // fold (fp_round_inreg c1fp) -> c1fp 4149 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4150 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4151 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4152 } 4153 return SDValue(); 4154} 4155 4156SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4157 SDValue N0 = N->getOperand(0); 4158 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4159 MVT VT = N->getValueType(0); 4160 4161 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4162 if (N->hasOneUse() && 4163 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4164 return SDValue(); 4165 4166 // fold (fp_extend c1fp) -> c1fp 4167 if (N0CFP && VT != MVT::ppcf128) 4168 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4169 4170 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4171 // value of X. 4172 if (N0.getOpcode() == ISD::FP_ROUND 4173 && N0.getNode()->getConstantOperandVal(1) == 1) { 4174 SDValue In = N0.getOperand(0); 4175 if (In.getValueType() == VT) return In; 4176 if (VT.bitsLT(In.getValueType())) 4177 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4178 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4179 } 4180 4181 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4182 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4183 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4184 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4185 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4186 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4187 LN0->getBasePtr(), LN0->getSrcValue(), 4188 LN0->getSrcValueOffset(), 4189 N0.getValueType(), 4190 LN0->isVolatile(), LN0->getAlignment()); 4191 CombineTo(N, ExtLoad); 4192 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4193 ExtLoad, DAG.getIntPtrConstant(1)), 4194 ExtLoad.getValue(1)); 4195 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4196 } 4197 4198 return SDValue(); 4199} 4200 4201SDValue DAGCombiner::visitFNEG(SDNode *N) { 4202 SDValue N0 = N->getOperand(0); 4203 4204 if (isNegatibleForFree(N0, LegalOperations)) 4205 return GetNegatedExpression(N0, DAG, LegalOperations); 4206 4207 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4208 // constant pool values. 4209 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4210 N0.getOperand(0).getValueType().isInteger() && 4211 !N0.getOperand(0).getValueType().isVector()) { 4212 SDValue Int = N0.getOperand(0); 4213 MVT IntVT = Int.getValueType(); 4214 if (IntVT.isInteger() && !IntVT.isVector()) { 4215 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4216 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4217 AddToWorkList(Int.getNode()); 4218 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4219 } 4220 } 4221 4222 return SDValue(); 4223} 4224 4225SDValue DAGCombiner::visitFABS(SDNode *N) { 4226 SDValue N0 = N->getOperand(0); 4227 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4228 MVT VT = N->getValueType(0); 4229 4230 // fold (fabs c1) -> fabs(c1) 4231 if (N0CFP && VT != MVT::ppcf128) 4232 return DAG.getNode(ISD::FABS, VT, N0); 4233 // fold (fabs (fabs x)) -> (fabs x) 4234 if (N0.getOpcode() == ISD::FABS) 4235 return N->getOperand(0); 4236 // fold (fabs (fneg x)) -> (fabs x) 4237 // fold (fabs (fcopysign x, y)) -> (fabs x) 4238 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4239 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4240 4241 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4242 // constant pool values. 4243 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4244 N0.getOperand(0).getValueType().isInteger() && 4245 !N0.getOperand(0).getValueType().isVector()) { 4246 SDValue Int = N0.getOperand(0); 4247 MVT IntVT = Int.getValueType(); 4248 if (IntVT.isInteger() && !IntVT.isVector()) { 4249 Int = DAG.getNode(ISD::AND, IntVT, Int, 4250 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4251 AddToWorkList(Int.getNode()); 4252 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4253 } 4254 } 4255 4256 return SDValue(); 4257} 4258 4259SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4260 SDValue Chain = N->getOperand(0); 4261 SDValue N1 = N->getOperand(1); 4262 SDValue N2 = N->getOperand(2); 4263 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4264 4265 // never taken branch, fold to chain 4266 if (N1C && N1C->isNullValue()) 4267 return Chain; 4268 // unconditional branch 4269 if (N1C && N1C->getAPIntValue() == 1) 4270 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4271 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4272 // on the target. 4273 if (N1.getOpcode() == ISD::SETCC && 4274 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4275 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4276 N1.getOperand(0), N1.getOperand(1), N2); 4277 } 4278 return SDValue(); 4279} 4280 4281// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4282// 4283SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4284 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4285 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4286 4287 // Use SimplifySetCC to simplify SETCC's. 4288 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4289 CondLHS, CondRHS, CC->get(), false); 4290 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4291 4292 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4293 4294 // fold br_cc true, dest -> br dest (unconditional branch) 4295 if (SCCC && !SCCC->isNullValue()) 4296 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4297 N->getOperand(4)); 4298 // fold br_cc false, dest -> unconditional fall through 4299 if (SCCC && SCCC->isNullValue()) 4300 return N->getOperand(0); 4301 4302 // fold to a simpler setcc 4303 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4304 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4305 Simp.getOperand(2), Simp.getOperand(0), 4306 Simp.getOperand(1), N->getOperand(4)); 4307 return SDValue(); 4308} 4309 4310 4311/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4312/// pre-indexed load / store when the base pointer is an add or subtract 4313/// and it has other uses besides the load / store. After the 4314/// transformation, the new indexed load / store has effectively folded 4315/// the add / subtract in and all of its other uses are redirected to the 4316/// new load / store. 4317bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4318 if (!LegalOperations) 4319 return false; 4320 4321 bool isLoad = true; 4322 SDValue Ptr; 4323 MVT VT; 4324 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4325 if (LD->isIndexed()) 4326 return false; 4327 VT = LD->getMemoryVT(); 4328 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4329 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4330 return false; 4331 Ptr = LD->getBasePtr(); 4332 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4333 if (ST->isIndexed()) 4334 return false; 4335 VT = ST->getMemoryVT(); 4336 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4337 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4338 return false; 4339 Ptr = ST->getBasePtr(); 4340 isLoad = false; 4341 } else 4342 return false; 4343 4344 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4345 // out. There is no reason to make this a preinc/predec. 4346 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4347 Ptr.getNode()->hasOneUse()) 4348 return false; 4349 4350 // Ask the target to do addressing mode selection. 4351 SDValue BasePtr; 4352 SDValue Offset; 4353 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4354 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4355 return false; 4356 // Don't create a indexed load / store with zero offset. 4357 if (isa<ConstantSDNode>(Offset) && 4358 cast<ConstantSDNode>(Offset)->isNullValue()) 4359 return false; 4360 4361 // Try turning it into a pre-indexed load / store except when: 4362 // 1) The new base ptr is a frame index. 4363 // 2) If N is a store and the new base ptr is either the same as or is a 4364 // predecessor of the value being stored. 4365 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4366 // that would create a cycle. 4367 // 4) All uses are load / store ops that use it as old base ptr. 4368 4369 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4370 // (plus the implicit offset) to a register to preinc anyway. 4371 if (isa<FrameIndexSDNode>(BasePtr)) 4372 return false; 4373 4374 // Check #2. 4375 if (!isLoad) { 4376 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4377 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4378 return false; 4379 } 4380 4381 // Now check for #3 and #4. 4382 bool RealUse = false; 4383 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4384 E = Ptr.getNode()->use_end(); I != E; ++I) { 4385 SDNode *Use = *I; 4386 if (Use == N) 4387 continue; 4388 if (Use->isPredecessorOf(N)) 4389 return false; 4390 4391 if (!((Use->getOpcode() == ISD::LOAD && 4392 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4393 (Use->getOpcode() == ISD::STORE && 4394 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4395 RealUse = true; 4396 } 4397 if (!RealUse) 4398 return false; 4399 4400 SDValue Result; 4401 if (isLoad) 4402 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4403 else 4404 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4405 ++PreIndexedNodes; 4406 ++NodesCombined; 4407 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4408 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4409 DOUT << '\n'; 4410 WorkListRemover DeadNodes(*this); 4411 if (isLoad) { 4412 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4413 &DeadNodes); 4414 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4415 &DeadNodes); 4416 } else { 4417 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4418 &DeadNodes); 4419 } 4420 4421 // Finally, since the node is now dead, remove it from the graph. 4422 DAG.DeleteNode(N); 4423 4424 // Replace the uses of Ptr with uses of the updated base value. 4425 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4426 &DeadNodes); 4427 removeFromWorkList(Ptr.getNode()); 4428 DAG.DeleteNode(Ptr.getNode()); 4429 4430 return true; 4431} 4432 4433/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4434/// add / sub of the base pointer node into a post-indexed load / store. 4435/// The transformation folded the add / subtract into the new indexed 4436/// load / store effectively and all of its uses are redirected to the 4437/// new load / store. 4438bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4439 if (!LegalOperations) 4440 return false; 4441 4442 bool isLoad = true; 4443 SDValue Ptr; 4444 MVT VT; 4445 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4446 if (LD->isIndexed()) 4447 return false; 4448 VT = LD->getMemoryVT(); 4449 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4450 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4451 return false; 4452 Ptr = LD->getBasePtr(); 4453 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4454 if (ST->isIndexed()) 4455 return false; 4456 VT = ST->getMemoryVT(); 4457 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4458 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4459 return false; 4460 Ptr = ST->getBasePtr(); 4461 isLoad = false; 4462 } else 4463 return false; 4464 4465 if (Ptr.getNode()->hasOneUse()) 4466 return false; 4467 4468 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4469 E = Ptr.getNode()->use_end(); I != E; ++I) { 4470 SDNode *Op = *I; 4471 if (Op == N || 4472 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4473 continue; 4474 4475 SDValue BasePtr; 4476 SDValue Offset; 4477 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4478 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4479 if (Ptr == Offset) 4480 std::swap(BasePtr, Offset); 4481 if (Ptr != BasePtr) 4482 continue; 4483 // Don't create a indexed load / store with zero offset. 4484 if (isa<ConstantSDNode>(Offset) && 4485 cast<ConstantSDNode>(Offset)->isNullValue()) 4486 continue; 4487 4488 // Try turning it into a post-indexed load / store except when 4489 // 1) All uses are load / store ops that use it as base ptr. 4490 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4491 // nor a successor of N. Otherwise, if Op is folded that would 4492 // create a cycle. 4493 4494 // Check for #1. 4495 bool TryNext = false; 4496 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4497 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4498 SDNode *Use = *II; 4499 if (Use == Ptr.getNode()) 4500 continue; 4501 4502 // If all the uses are load / store addresses, then don't do the 4503 // transformation. 4504 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4505 bool RealUse = false; 4506 for (SDNode::use_iterator III = Use->use_begin(), 4507 EEE = Use->use_end(); III != EEE; ++III) { 4508 SDNode *UseUse = *III; 4509 if (!((UseUse->getOpcode() == ISD::LOAD && 4510 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4511 (UseUse->getOpcode() == ISD::STORE && 4512 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4513 RealUse = true; 4514 } 4515 4516 if (!RealUse) { 4517 TryNext = true; 4518 break; 4519 } 4520 } 4521 } 4522 if (TryNext) 4523 continue; 4524 4525 // Check for #2 4526 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4527 SDValue Result = isLoad 4528 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4529 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4530 ++PostIndexedNodes; 4531 ++NodesCombined; 4532 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4533 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4534 DOUT << '\n'; 4535 WorkListRemover DeadNodes(*this); 4536 if (isLoad) { 4537 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4538 &DeadNodes); 4539 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4540 &DeadNodes); 4541 } else { 4542 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4543 &DeadNodes); 4544 } 4545 4546 // Finally, since the node is now dead, remove it from the graph. 4547 DAG.DeleteNode(N); 4548 4549 // Replace the uses of Use with uses of the updated base value. 4550 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4551 Result.getValue(isLoad ? 1 : 0), 4552 &DeadNodes); 4553 removeFromWorkList(Op); 4554 DAG.DeleteNode(Op); 4555 return true; 4556 } 4557 } 4558 } 4559 return false; 4560} 4561 4562/// InferAlignment - If we can infer some alignment information from this 4563/// pointer, return it. 4564static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4565 // If this is a direct reference to a stack slot, use information about the 4566 // stack slot's alignment. 4567 int FrameIdx = 1 << 31; 4568 int64_t FrameOffset = 0; 4569 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4570 FrameIdx = FI->getIndex(); 4571 } else if (Ptr.getOpcode() == ISD::ADD && 4572 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4573 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4574 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4575 FrameOffset = Ptr.getConstantOperandVal(1); 4576 } 4577 4578 if (FrameIdx != (1 << 31)) { 4579 // FIXME: Handle FI+CST. 4580 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4581 if (MFI.isFixedObjectIndex(FrameIdx)) { 4582 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4583 4584 // The alignment of the frame index can be determined from its offset from 4585 // the incoming frame position. If the frame object is at offset 32 and 4586 // the stack is guaranteed to be 16-byte aligned, then we know that the 4587 // object is 16-byte aligned. 4588 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4589 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4590 4591 // Finally, the frame object itself may have a known alignment. Factor 4592 // the alignment + offset into a new alignment. For example, if we know 4593 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4594 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4595 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4596 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4597 FrameOffset); 4598 return std::max(Align, FIInfoAlign); 4599 } 4600 } 4601 4602 return 0; 4603} 4604 4605SDValue DAGCombiner::visitLOAD(SDNode *N) { 4606 LoadSDNode *LD = cast<LoadSDNode>(N); 4607 SDValue Chain = LD->getChain(); 4608 SDValue Ptr = LD->getBasePtr(); 4609 4610 // Try to infer better alignment information than the load already has. 4611 if (!Fast && LD->isUnindexed()) { 4612 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4613 if (Align > LD->getAlignment()) 4614 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4615 Chain, Ptr, LD->getSrcValue(), 4616 LD->getSrcValueOffset(), LD->getMemoryVT(), 4617 LD->isVolatile(), Align); 4618 } 4619 } 4620 4621 4622 // If load is not volatile and there are no uses of the loaded value (and 4623 // the updated indexed value in case of indexed loads), change uses of the 4624 // chain value into uses of the chain input (i.e. delete the dead load). 4625 if (!LD->isVolatile()) { 4626 if (N->getValueType(1) == MVT::Other) { 4627 // Unindexed loads. 4628 if (N->hasNUsesOfValue(0, 0)) { 4629 // It's not safe to use the two value CombineTo variant here. e.g. 4630 // v1, chain2 = load chain1, loc 4631 // v2, chain3 = load chain2, loc 4632 // v3 = add v2, c 4633 // Now we replace use of chain2 with chain1. This makes the second load 4634 // isomorphic to the one we are deleting, and thus makes this load live. 4635 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4636 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4637 DOUT << "\n"; 4638 WorkListRemover DeadNodes(*this); 4639 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4640 if (N->use_empty()) { 4641 removeFromWorkList(N); 4642 DAG.DeleteNode(N); 4643 } 4644 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4645 } 4646 } else { 4647 // Indexed loads. 4648 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4649 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4650 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4651 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4652 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4653 DOUT << " and 2 other values\n"; 4654 WorkListRemover DeadNodes(*this); 4655 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4656 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4657 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4658 &DeadNodes); 4659 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4660 removeFromWorkList(N); 4661 DAG.DeleteNode(N); 4662 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4663 } 4664 } 4665 } 4666 4667 // If this load is directly stored, replace the load value with the stored 4668 // value. 4669 // TODO: Handle store large -> read small portion. 4670 // TODO: Handle TRUNCSTORE/LOADEXT 4671 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4672 !LD->isVolatile()) { 4673 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4674 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4675 if (PrevST->getBasePtr() == Ptr && 4676 PrevST->getValue().getValueType() == N->getValueType(0)) 4677 return CombineTo(N, Chain.getOperand(1), Chain); 4678 } 4679 } 4680 4681 if (CombinerAA) { 4682 // Walk up chain skipping non-aliasing memory nodes. 4683 SDValue BetterChain = FindBetterChain(N, Chain); 4684 4685 // If there is a better chain. 4686 if (Chain != BetterChain) { 4687 SDValue ReplLoad; 4688 4689 // Replace the chain to void dependency. 4690 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4691 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4692 LD->getSrcValue(), LD->getSrcValueOffset(), 4693 LD->isVolatile(), LD->getAlignment()); 4694 } else { 4695 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4696 LD->getValueType(0), 4697 BetterChain, Ptr, LD->getSrcValue(), 4698 LD->getSrcValueOffset(), 4699 LD->getMemoryVT(), 4700 LD->isVolatile(), 4701 LD->getAlignment()); 4702 } 4703 4704 // Create token factor to keep old chain connected. 4705 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4706 Chain, ReplLoad.getValue(1)); 4707 4708 // Replace uses with load result and token factor. Don't add users 4709 // to work list. 4710 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4711 } 4712 } 4713 4714 // Try transforming N to an indexed load. 4715 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4716 return SDValue(N, 0); 4717 4718 return SDValue(); 4719} 4720 4721 4722SDValue DAGCombiner::visitSTORE(SDNode *N) { 4723 StoreSDNode *ST = cast<StoreSDNode>(N); 4724 SDValue Chain = ST->getChain(); 4725 SDValue Value = ST->getValue(); 4726 SDValue Ptr = ST->getBasePtr(); 4727 4728 // Try to infer better alignment information than the store already has. 4729 if (!Fast && ST->isUnindexed()) { 4730 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4731 if (Align > ST->getAlignment()) 4732 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4733 ST->getSrcValueOffset(), ST->getMemoryVT(), 4734 ST->isVolatile(), Align); 4735 } 4736 } 4737 4738 // If this is a store of a bit convert, store the input value if the 4739 // resultant store does not need a higher alignment than the original. 4740 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4741 ST->isUnindexed()) { 4742 unsigned Align = ST->getAlignment(); 4743 MVT SVT = Value.getOperand(0).getValueType(); 4744 unsigned OrigAlign = TLI.getTargetData()-> 4745 getABITypeAlignment(SVT.getTypeForMVT()); 4746 if (Align <= OrigAlign && 4747 ((!LegalOperations && !ST->isVolatile()) || 4748 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 4749 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4750 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4751 } 4752 4753 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4754 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4755 // NOTE: If the original store is volatile, this transform must not increase 4756 // the number of stores. For example, on x86-32 an f64 can be stored in one 4757 // processor operation but an i64 (which is not legal) requires two. So the 4758 // transform should not be done in this case. 4759 if (Value.getOpcode() != ISD::TargetConstantFP) { 4760 SDValue Tmp; 4761 switch (CFP->getValueType(0).getSimpleVT()) { 4762 default: assert(0 && "Unknown FP type"); 4763 case MVT::f80: // We don't do this for these yet. 4764 case MVT::f128: 4765 case MVT::ppcf128: 4766 break; 4767 case MVT::f32: 4768 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 4769 !ST->isVolatile()) || 4770 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4771 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4772 bitcastToAPInt().getZExtValue(), MVT::i32); 4773 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4774 ST->getSrcValueOffset(), ST->isVolatile(), 4775 ST->getAlignment()); 4776 } 4777 break; 4778 case MVT::f64: 4779 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 4780 !ST->isVolatile()) || 4781 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 4782 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4783 getZExtValue(), MVT::i64); 4784 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4785 ST->getSrcValueOffset(), ST->isVolatile(), 4786 ST->getAlignment()); 4787 } else if (!ST->isVolatile() && 4788 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4789 // Many FP stores are not made apparent until after legalize, e.g. for 4790 // argument passing. Since this is so common, custom legalize the 4791 // 64-bit integer store into two 32-bit stores. 4792 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4793 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4794 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4795 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4796 4797 int SVOffset = ST->getSrcValueOffset(); 4798 unsigned Alignment = ST->getAlignment(); 4799 bool isVolatile = ST->isVolatile(); 4800 4801 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4802 ST->getSrcValueOffset(), 4803 isVolatile, ST->getAlignment()); 4804 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4805 DAG.getConstant(4, Ptr.getValueType())); 4806 SVOffset += 4; 4807 Alignment = MinAlign(Alignment, 4U); 4808 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4809 SVOffset, isVolatile, Alignment); 4810 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4811 } 4812 break; 4813 } 4814 } 4815 } 4816 4817 if (CombinerAA) { 4818 // Walk up chain skipping non-aliasing memory nodes. 4819 SDValue BetterChain = FindBetterChain(N, Chain); 4820 4821 // If there is a better chain. 4822 if (Chain != BetterChain) { 4823 // Replace the chain to avoid dependency. 4824 SDValue ReplStore; 4825 if (ST->isTruncatingStore()) { 4826 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4827 ST->getSrcValue(),ST->getSrcValueOffset(), 4828 ST->getMemoryVT(), 4829 ST->isVolatile(), ST->getAlignment()); 4830 } else { 4831 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4832 ST->getSrcValue(), ST->getSrcValueOffset(), 4833 ST->isVolatile(), ST->getAlignment()); 4834 } 4835 4836 // Create token to keep both nodes around. 4837 SDValue Token = 4838 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4839 4840 // Don't add users to work list. 4841 return CombineTo(N, Token, false); 4842 } 4843 } 4844 4845 // Try transforming N to an indexed store. 4846 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4847 return SDValue(N, 0); 4848 4849 // FIXME: is there such a thing as a truncating indexed store? 4850 if (ST->isTruncatingStore() && ST->isUnindexed() && 4851 Value.getValueType().isInteger()) { 4852 // See if we can simplify the input to this truncstore with knowledge that 4853 // only the low bits are being used. For example: 4854 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4855 SDValue Shorter = 4856 GetDemandedBits(Value, 4857 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4858 ST->getMemoryVT().getSizeInBits())); 4859 AddToWorkList(Value.getNode()); 4860 if (Shorter.getNode()) 4861 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4862 ST->getSrcValueOffset(), ST->getMemoryVT(), 4863 ST->isVolatile(), ST->getAlignment()); 4864 4865 // Otherwise, see if we can simplify the operation with 4866 // SimplifyDemandedBits, which only works if the value has a single use. 4867 if (SimplifyDemandedBits(Value, 4868 APInt::getLowBitsSet( 4869 Value.getValueSizeInBits(), 4870 ST->getMemoryVT().getSizeInBits()))) 4871 return SDValue(N, 0); 4872 } 4873 4874 // If this is a load followed by a store to the same location, then the store 4875 // is dead/noop. 4876 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4877 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4878 ST->isUnindexed() && !ST->isVolatile() && 4879 // There can't be any side effects between the load and store, such as 4880 // a call or store. 4881 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4882 // The store is dead, remove it. 4883 return Chain; 4884 } 4885 } 4886 4887 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4888 // truncating store. We can do this even if this is already a truncstore. 4889 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4890 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4891 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4892 ST->getMemoryVT())) { 4893 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4894 ST->getSrcValueOffset(), ST->getMemoryVT(), 4895 ST->isVolatile(), ST->getAlignment()); 4896 } 4897 4898 return SDValue(); 4899} 4900 4901SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4902 SDValue InVec = N->getOperand(0); 4903 SDValue InVal = N->getOperand(1); 4904 SDValue EltNo = N->getOperand(2); 4905 4906 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4907 // vector with the inserted element. 4908 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4909 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4910 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 4911 InVec.getNode()->op_end()); 4912 if (Elt < Ops.size()) 4913 Ops[Elt] = InVal; 4914 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4915 &Ops[0], Ops.size()); 4916 } 4917 4918 return SDValue(); 4919} 4920 4921SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4922 // (vextract (scalar_to_vector val, 0) -> val 4923 SDValue InVec = N->getOperand(0); 4924 4925 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) 4926 return InVec.getOperand(0); 4927 4928 // Perform only after legalization to ensure build_vector / vector_shuffle 4929 // optimizations have already been done. 4930 if (!LegalOperations) return SDValue(); 4931 4932 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4933 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4934 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4935 SDValue EltNo = N->getOperand(1); 4936 4937 if (isa<ConstantSDNode>(EltNo)) { 4938 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4939 bool NewLoad = false; 4940 bool BCNumEltsChanged = false; 4941 MVT VT = InVec.getValueType(); 4942 MVT EVT = VT.getVectorElementType(); 4943 MVT LVT = EVT; 4944 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4945 MVT BCVT = InVec.getOperand(0).getValueType(); 4946 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4947 return SDValue(); 4948 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 4949 BCNumEltsChanged = true; 4950 InVec = InVec.getOperand(0); 4951 EVT = BCVT.getVectorElementType(); 4952 NewLoad = true; 4953 } 4954 4955 LoadSDNode *LN0 = NULL; 4956 if (ISD::isNormalLoad(InVec.getNode())) 4957 LN0 = cast<LoadSDNode>(InVec); 4958 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4959 InVec.getOperand(0).getValueType() == EVT && 4960 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 4961 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4962 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4963 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4964 // => 4965 // (load $addr+1*size) 4966 4967 // If the bit convert changed the number of elements, it is unsafe 4968 // to examine the mask. 4969 if (BCNumEltsChanged) 4970 return SDValue(); 4971 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4972 getOperand(Elt))->getZExtValue(); 4973 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4974 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4975 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4976 InVec = InVec.getOperand(0); 4977 if (ISD::isNormalLoad(InVec.getNode())) { 4978 LN0 = cast<LoadSDNode>(InVec); 4979 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4980 } 4981 } 4982 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4983 return SDValue(); 4984 4985 unsigned Align = LN0->getAlignment(); 4986 if (NewLoad) { 4987 // Check the resultant load doesn't need a higher alignment than the 4988 // original load. 4989 unsigned NewAlign = TLI.getTargetData()-> 4990 getABITypeAlignment(LVT.getTypeForMVT()); 4991 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 4992 return SDValue(); 4993 Align = NewAlign; 4994 } 4995 4996 SDValue NewPtr = LN0->getBasePtr(); 4997 if (Elt) { 4998 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4999 MVT PtrType = NewPtr.getValueType(); 5000 if (TLI.isBigEndian()) 5001 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5002 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 5003 DAG.getConstant(PtrOff, PtrType)); 5004 } 5005 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 5006 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5007 LN0->isVolatile(), Align); 5008 } 5009 return SDValue(); 5010} 5011 5012 5013SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5014 unsigned NumInScalars = N->getNumOperands(); 5015 MVT VT = N->getValueType(0); 5016 unsigned NumElts = VT.getVectorNumElements(); 5017 MVT EltType = VT.getVectorElementType(); 5018 5019 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5020 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5021 // at most two distinct vectors, turn this into a shuffle node. 5022 SDValue VecIn1, VecIn2; 5023 for (unsigned i = 0; i != NumInScalars; ++i) { 5024 // Ignore undef inputs. 5025 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5026 5027 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5028 // constant index, bail out. 5029 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5030 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5031 VecIn1 = VecIn2 = SDValue(0, 0); 5032 break; 5033 } 5034 5035 // If the input vector type disagrees with the result of the build_vector, 5036 // we can't make a shuffle. 5037 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5038 if (ExtractedFromVec.getValueType() != VT) { 5039 VecIn1 = VecIn2 = SDValue(0, 0); 5040 break; 5041 } 5042 5043 // Otherwise, remember this. We allow up to two distinct input vectors. 5044 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5045 continue; 5046 5047 if (VecIn1.getNode() == 0) { 5048 VecIn1 = ExtractedFromVec; 5049 } else if (VecIn2.getNode() == 0) { 5050 VecIn2 = ExtractedFromVec; 5051 } else { 5052 // Too many inputs. 5053 VecIn1 = VecIn2 = SDValue(0, 0); 5054 break; 5055 } 5056 } 5057 5058 // If everything is good, we can make a shuffle operation. 5059 if (VecIn1.getNode()) { 5060 SmallVector<SDValue, 8> BuildVecIndices; 5061 for (unsigned i = 0; i != NumInScalars; ++i) { 5062 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5063 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 5064 continue; 5065 } 5066 5067 SDValue Extract = N->getOperand(i); 5068 5069 // If extracting from the first vector, just use the index directly. 5070 if (Extract.getOperand(0) == VecIn1) { 5071 BuildVecIndices.push_back(Extract.getOperand(1)); 5072 continue; 5073 } 5074 5075 // Otherwise, use InIdx + VecSize 5076 unsigned Idx = 5077 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 5078 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 5079 } 5080 5081 // Add count and size info. 5082 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5083 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes) 5084 return SDValue(); 5085 5086 // Return the new VECTOR_SHUFFLE node. 5087 SDValue Ops[5]; 5088 Ops[0] = VecIn1; 5089 if (VecIn2.getNode()) { 5090 Ops[1] = VecIn2; 5091 } else { 5092 // Use an undef build_vector as input for the second operand. 5093 std::vector<SDValue> UnOps(NumInScalars, 5094 DAG.getNode(ISD::UNDEF, 5095 EltType)); 5096 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 5097 &UnOps[0], UnOps.size()); 5098 AddToWorkList(Ops[1].getNode()); 5099 } 5100 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 5101 &BuildVecIndices[0], BuildVecIndices.size()); 5102 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 5103 } 5104 5105 return SDValue(); 5106} 5107 5108SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5109 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5110 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5111 // inputs come from at most two distinct vectors, turn this into a shuffle 5112 // node. 5113 5114 // If we only have one input vector, we don't need to do any concatenation. 5115 if (N->getNumOperands() == 1) { 5116 return N->getOperand(0); 5117 } 5118 5119 return SDValue(); 5120} 5121 5122SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5123 SDValue ShufMask = N->getOperand(2); 5124 unsigned NumElts = ShufMask.getNumOperands(); 5125 5126 SDValue N0 = N->getOperand(0); 5127 SDValue N1 = N->getOperand(1); 5128 5129 assert(N0.getValueType().getVectorNumElements() == NumElts && 5130 "Vector shuffle must be normalized in DAG"); 5131 5132 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5133 bool isIdentity = true; 5134 for (unsigned i = 0; i != NumElts; ++i) { 5135 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5136 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5137 isIdentity = false; 5138 break; 5139 } 5140 } 5141 if (isIdentity) return N->getOperand(0); 5142 5143 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5144 isIdentity = true; 5145 for (unsigned i = 0; i != NumElts; ++i) { 5146 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5147 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5148 i+NumElts) { 5149 isIdentity = false; 5150 break; 5151 } 5152 } 5153 if (isIdentity) return N->getOperand(1); 5154 5155 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5156 // needed at all. 5157 bool isUnary = true; 5158 bool isSplat = true; 5159 int VecNum = -1; 5160 unsigned BaseIdx = 0; 5161 for (unsigned i = 0; i != NumElts; ++i) 5162 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5163 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5164 int V = (Idx < NumElts) ? 0 : 1; 5165 if (VecNum == -1) { 5166 VecNum = V; 5167 BaseIdx = Idx; 5168 } else { 5169 if (BaseIdx != Idx) 5170 isSplat = false; 5171 if (VecNum != V) { 5172 isUnary = false; 5173 break; 5174 } 5175 } 5176 } 5177 5178 // Normalize unary shuffle so the RHS is undef. 5179 if (isUnary && VecNum == 1) 5180 std::swap(N0, N1); 5181 5182 // If it is a splat, check if the argument vector is a build_vector with 5183 // all scalar elements the same. 5184 if (isSplat) { 5185 SDNode *V = N0.getNode(); 5186 5187 // If this is a bit convert that changes the element type of the vector but 5188 // not the number of vector elements, look through it. Be careful not to 5189 // look though conversions that change things like v4f32 to v2f64. 5190 if (V->getOpcode() == ISD::BIT_CONVERT) { 5191 SDValue ConvInput = V->getOperand(0); 5192 if (ConvInput.getValueType().isVector() && 5193 ConvInput.getValueType().getVectorNumElements() == NumElts) 5194 V = ConvInput.getNode(); 5195 } 5196 5197 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5198 unsigned NumElems = V->getNumOperands(); 5199 if (NumElems > BaseIdx) { 5200 SDValue Base; 5201 bool AllSame = true; 5202 for (unsigned i = 0; i != NumElems; ++i) { 5203 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5204 Base = V->getOperand(i); 5205 break; 5206 } 5207 } 5208 // Splat of <u, u, u, u>, return <u, u, u, u> 5209 if (!Base.getNode()) 5210 return N0; 5211 for (unsigned i = 0; i != NumElems; ++i) { 5212 if (V->getOperand(i) != Base) { 5213 AllSame = false; 5214 break; 5215 } 5216 } 5217 // Splat of <x, x, x, x>, return <x, x, x, x> 5218 if (AllSame) 5219 return N0; 5220 } 5221 } 5222 } 5223 5224 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5225 // into an undef. 5226 if (isUnary || N0 == N1) { 5227 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5228 // first operand. 5229 SmallVector<SDValue, 8> MappedOps; 5230 for (unsigned i = 0; i != NumElts; ++i) { 5231 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5232 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5233 NumElts) { 5234 MappedOps.push_back(ShufMask.getOperand(i)); 5235 } else { 5236 unsigned NewIdx = 5237 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5238 NumElts; 5239 MappedOps.push_back(DAG.getConstant(NewIdx, 5240 ShufMask.getOperand(i).getValueType())); 5241 } 5242 } 5243 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5244 &MappedOps[0], MappedOps.size()); 5245 AddToWorkList(ShufMask.getNode()); 5246 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5247 N0, 5248 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5249 ShufMask); 5250 } 5251 5252 return SDValue(); 5253} 5254 5255/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5256/// an AND to a vector_shuffle with the destination vector and a zero vector. 5257/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5258/// vector_shuffle V, Zero, <0, 4, 2, 4> 5259SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5260 SDValue LHS = N->getOperand(0); 5261 SDValue RHS = N->getOperand(1); 5262 if (N->getOpcode() == ISD::AND) { 5263 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5264 RHS = RHS.getOperand(0); 5265 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5266 std::vector<SDValue> IdxOps; 5267 unsigned NumOps = RHS.getNumOperands(); 5268 unsigned NumElts = NumOps; 5269 for (unsigned i = 0; i != NumElts; ++i) { 5270 SDValue Elt = RHS.getOperand(i); 5271 if (!isa<ConstantSDNode>(Elt)) 5272 return SDValue(); 5273 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5274 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5275 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5276 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5277 else 5278 return SDValue(); 5279 } 5280 5281 // Let's see if the target supports this vector_shuffle. 5282 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5283 return SDValue(); 5284 5285 // Return the new VECTOR_SHUFFLE node. 5286 MVT EVT = RHS.getValueType().getVectorElementType(); 5287 MVT VT = MVT::getVectorVT(EVT, NumElts); 5288 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5289 std::vector<SDValue> Ops; 5290 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5291 Ops.push_back(LHS); 5292 AddToWorkList(LHS.getNode()); 5293 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5294 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5295 &ZeroOps[0], ZeroOps.size())); 5296 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5297 &IdxOps[0], IdxOps.size())); 5298 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5299 &Ops[0], Ops.size()); 5300 if (VT != N->getValueType(0)) 5301 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5302 return Result; 5303 } 5304 } 5305 return SDValue(); 5306} 5307 5308/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5309SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5310 // After legalize, the target may be depending on adds and other 5311 // binary ops to provide legal ways to construct constants or other 5312 // things. Simplifying them may result in a loss of legality. 5313 if (LegalOperations) return SDValue(); 5314 5315 MVT VT = N->getValueType(0); 5316 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5317 5318 MVT EltType = VT.getVectorElementType(); 5319 SDValue LHS = N->getOperand(0); 5320 SDValue RHS = N->getOperand(1); 5321 SDValue Shuffle = XformToShuffleWithZero(N); 5322 if (Shuffle.getNode()) return Shuffle; 5323 5324 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5325 // this operation. 5326 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5327 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5328 SmallVector<SDValue, 8> Ops; 5329 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5330 SDValue LHSOp = LHS.getOperand(i); 5331 SDValue RHSOp = RHS.getOperand(i); 5332 // If these two elements can't be folded, bail out. 5333 if ((LHSOp.getOpcode() != ISD::UNDEF && 5334 LHSOp.getOpcode() != ISD::Constant && 5335 LHSOp.getOpcode() != ISD::ConstantFP) || 5336 (RHSOp.getOpcode() != ISD::UNDEF && 5337 RHSOp.getOpcode() != ISD::Constant && 5338 RHSOp.getOpcode() != ISD::ConstantFP)) 5339 break; 5340 // Can't fold divide by zero. 5341 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5342 N->getOpcode() == ISD::FDIV) { 5343 if ((RHSOp.getOpcode() == ISD::Constant && 5344 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5345 (RHSOp.getOpcode() == ISD::ConstantFP && 5346 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5347 break; 5348 } 5349 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5350 AddToWorkList(Ops.back().getNode()); 5351 assert((Ops.back().getOpcode() == ISD::UNDEF || 5352 Ops.back().getOpcode() == ISD::Constant || 5353 Ops.back().getOpcode() == ISD::ConstantFP) && 5354 "Scalar binop didn't fold!"); 5355 } 5356 5357 if (Ops.size() == LHS.getNumOperands()) { 5358 MVT VT = LHS.getValueType(); 5359 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5360 } 5361 } 5362 5363 return SDValue(); 5364} 5365 5366SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5367 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5368 5369 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5370 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5371 // If we got a simplified select_cc node back from SimplifySelectCC, then 5372 // break it down into a new SETCC node, and a new SELECT node, and then return 5373 // the SELECT node, since we were called with a SELECT node. 5374 if (SCC.getNode()) { 5375 // Check to see if we got a select_cc back (to turn into setcc/select). 5376 // Otherwise, just return whatever node we got back, like fabs. 5377 if (SCC.getOpcode() == ISD::SELECT_CC) { 5378 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5379 SCC.getOperand(0), SCC.getOperand(1), 5380 SCC.getOperand(4)); 5381 AddToWorkList(SETCC.getNode()); 5382 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5383 SCC.getOperand(3), SETCC); 5384 } 5385 return SCC; 5386 } 5387 return SDValue(); 5388} 5389 5390/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5391/// are the two values being selected between, see if we can simplify the 5392/// select. Callers of this should assume that TheSelect is deleted if this 5393/// returns true. As such, they should return the appropriate thing (e.g. the 5394/// node) back to the top-level of the DAG combiner loop to avoid it being 5395/// looked at. 5396/// 5397bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5398 SDValue RHS) { 5399 5400 // If this is a select from two identical things, try to pull the operation 5401 // through the select. 5402 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5403 // If this is a load and the token chain is identical, replace the select 5404 // of two loads with a load through a select of the address to load from. 5405 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5406 // constants have been dropped into the constant pool. 5407 if (LHS.getOpcode() == ISD::LOAD && 5408 // Do not let this transformation reduce the number of volatile loads. 5409 !cast<LoadSDNode>(LHS)->isVolatile() && 5410 !cast<LoadSDNode>(RHS)->isVolatile() && 5411 // Token chains must be identical. 5412 LHS.getOperand(0) == RHS.getOperand(0)) { 5413 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5414 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5415 5416 // If this is an EXTLOAD, the VT's must match. 5417 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5418 // FIXME: this conflates two src values, discarding one. This is not 5419 // the right thing to do, but nothing uses srcvalues now. When they do, 5420 // turn SrcValue into a list of locations. 5421 SDValue Addr; 5422 if (TheSelect->getOpcode() == ISD::SELECT) { 5423 // Check that the condition doesn't reach either load. If so, folding 5424 // this will induce a cycle into the DAG. 5425 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5426 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5427 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5428 TheSelect->getOperand(0), LLD->getBasePtr(), 5429 RLD->getBasePtr()); 5430 } 5431 } else { 5432 // Check that the condition doesn't reach either load. If so, folding 5433 // this will induce a cycle into the DAG. 5434 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5435 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5436 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5437 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5438 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5439 TheSelect->getOperand(0), 5440 TheSelect->getOperand(1), 5441 LLD->getBasePtr(), RLD->getBasePtr(), 5442 TheSelect->getOperand(4)); 5443 } 5444 } 5445 5446 if (Addr.getNode()) { 5447 SDValue Load; 5448 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5449 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5450 Addr,LLD->getSrcValue(), 5451 LLD->getSrcValueOffset(), 5452 LLD->isVolatile(), 5453 LLD->getAlignment()); 5454 else { 5455 Load = DAG.getExtLoad(LLD->getExtensionType(), 5456 TheSelect->getValueType(0), 5457 LLD->getChain(), Addr, LLD->getSrcValue(), 5458 LLD->getSrcValueOffset(), 5459 LLD->getMemoryVT(), 5460 LLD->isVolatile(), 5461 LLD->getAlignment()); 5462 } 5463 // Users of the select now use the result of the load. 5464 CombineTo(TheSelect, Load); 5465 5466 // Users of the old loads now use the new load's chain. We know the 5467 // old-load value is dead now. 5468 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5469 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5470 return true; 5471 } 5472 } 5473 } 5474 } 5475 5476 return false; 5477} 5478 5479SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5480 SDValue N2, SDValue N3, 5481 ISD::CondCode CC, bool NotExtCompare) { 5482 5483 MVT VT = N2.getValueType(); 5484 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5485 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5486 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5487 5488 // Determine if the condition we're dealing with is constant 5489 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5490 N0, N1, CC, false); 5491 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5492 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5493 5494 // fold select_cc true, x, y -> x 5495 if (SCCC && !SCCC->isNullValue()) 5496 return N2; 5497 // fold select_cc false, x, y -> y 5498 if (SCCC && SCCC->isNullValue()) 5499 return N3; 5500 5501 // Check to see if we can simplify the select into an fabs node 5502 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5503 // Allow either -0.0 or 0.0 5504 if (CFP->getValueAPF().isZero()) { 5505 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5506 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5507 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5508 N2 == N3.getOperand(0)) 5509 return DAG.getNode(ISD::FABS, VT, N0); 5510 5511 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5512 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5513 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5514 N2.getOperand(0) == N3) 5515 return DAG.getNode(ISD::FABS, VT, N3); 5516 } 5517 } 5518 5519 // Check to see if we can perform the "gzip trick", transforming 5520 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5521 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5522 N0.getValueType().isInteger() && 5523 N2.getValueType().isInteger() && 5524 (N1C->isNullValue() || // (a < 0) ? b : 0 5525 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5526 MVT XType = N0.getValueType(); 5527 MVT AType = N2.getValueType(); 5528 if (XType.bitsGE(AType)) { 5529 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5530 // single-bit constant. 5531 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5532 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5533 ShCtV = XType.getSizeInBits()-ShCtV-1; 5534 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5535 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5536 AddToWorkList(Shift.getNode()); 5537 if (XType.bitsGT(AType)) { 5538 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5539 AddToWorkList(Shift.getNode()); 5540 } 5541 return DAG.getNode(ISD::AND, AType, Shift, N2); 5542 } 5543 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5544 DAG.getConstant(XType.getSizeInBits()-1, 5545 TLI.getShiftAmountTy())); 5546 AddToWorkList(Shift.getNode()); 5547 if (XType.bitsGT(AType)) { 5548 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5549 AddToWorkList(Shift.getNode()); 5550 } 5551 return DAG.getNode(ISD::AND, AType, Shift, N2); 5552 } 5553 } 5554 5555 // fold select C, 16, 0 -> shl C, 4 5556 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5557 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5558 5559 // If the caller doesn't want us to simplify this into a zext of a compare, 5560 // don't do it. 5561 if (NotExtCompare && N2C->getAPIntValue() == 1) 5562 return SDValue(); 5563 5564 // Get a SetCC of the condition 5565 // FIXME: Should probably make sure that setcc is legal if we ever have a 5566 // target where it isn't. 5567 SDValue Temp, SCC; 5568 // cast from setcc result type to select result type 5569 if (LegalTypes) { 5570 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0.getValueType()), 5571 N0, N1, CC); 5572 if (N2.getValueType().bitsLT(SCC.getValueType())) 5573 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5574 else 5575 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5576 } else { 5577 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5578 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5579 } 5580 AddToWorkList(SCC.getNode()); 5581 AddToWorkList(Temp.getNode()); 5582 5583 if (N2C->getAPIntValue() == 1) 5584 return Temp; 5585 // shl setcc result by log2 n2c 5586 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5587 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5588 TLI.getShiftAmountTy())); 5589 } 5590 5591 // Check to see if this is the equivalent of setcc 5592 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5593 // otherwise, go ahead with the folds. 5594 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5595 MVT XType = N0.getValueType(); 5596 if (!LegalOperations || 5597 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5598 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(XType), N0, N1, CC); 5599 if (Res.getValueType() != VT) 5600 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5601 return Res; 5602 } 5603 5604 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5605 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5606 (!LegalOperations || 5607 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5608 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5609 return DAG.getNode(ISD::SRL, XType, Ctlz, 5610 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5611 TLI.getShiftAmountTy())); 5612 } 5613 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5614 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5615 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5616 N0); 5617 SDValue NotN0 = DAG.getNOT(N0, XType); 5618 return DAG.getNode(ISD::SRL, XType, 5619 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5620 DAG.getConstant(XType.getSizeInBits()-1, 5621 TLI.getShiftAmountTy())); 5622 } 5623 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5624 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5625 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5626 DAG.getConstant(XType.getSizeInBits()-1, 5627 TLI.getShiftAmountTy())); 5628 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5629 } 5630 } 5631 5632 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5633 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5634 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5635 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5636 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5637 MVT XType = N0.getValueType(); 5638 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5639 DAG.getConstant(XType.getSizeInBits()-1, 5640 TLI.getShiftAmountTy())); 5641 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5642 AddToWorkList(Shift.getNode()); 5643 AddToWorkList(Add.getNode()); 5644 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5645 } 5646 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5647 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5648 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5649 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5650 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5651 MVT XType = N0.getValueType(); 5652 if (SubC->isNullValue() && XType.isInteger()) { 5653 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5654 DAG.getConstant(XType.getSizeInBits()-1, 5655 TLI.getShiftAmountTy())); 5656 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5657 AddToWorkList(Shift.getNode()); 5658 AddToWorkList(Add.getNode()); 5659 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5660 } 5661 } 5662 } 5663 5664 return SDValue(); 5665} 5666 5667/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5668SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5669 SDValue N1, ISD::CondCode Cond, 5670 bool foldBooleans) { 5671 TargetLowering::DAGCombinerInfo 5672 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5673 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5674} 5675 5676/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5677/// return a DAG expression to select that will generate the same value by 5678/// multiplying by a magic number. See: 5679/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5680SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5681 std::vector<SDNode*> Built; 5682 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5683 5684 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5685 ii != ee; ++ii) 5686 AddToWorkList(*ii); 5687 return S; 5688} 5689 5690/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5691/// return a DAG expression to select that will generate the same value by 5692/// multiplying by a magic number. See: 5693/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5694SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5695 std::vector<SDNode*> Built; 5696 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5697 5698 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5699 ii != ee; ++ii) 5700 AddToWorkList(*ii); 5701 return S; 5702} 5703 5704/// FindBaseOffset - Return true if base is known not to alias with anything 5705/// but itself. Provides base object and offset as results. 5706static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5707 // Assume it is a primitive operation. 5708 Base = Ptr; Offset = 0; 5709 5710 // If it's an adding a simple constant then integrate the offset. 5711 if (Base.getOpcode() == ISD::ADD) { 5712 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5713 Base = Base.getOperand(0); 5714 Offset += C->getZExtValue(); 5715 } 5716 } 5717 5718 // If it's any of the following then it can't alias with anything but itself. 5719 return isa<FrameIndexSDNode>(Base) || 5720 isa<ConstantPoolSDNode>(Base) || 5721 isa<GlobalAddressSDNode>(Base); 5722} 5723 5724/// isAlias - Return true if there is any possibility that the two addresses 5725/// overlap. 5726bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5727 const Value *SrcValue1, int SrcValueOffset1, 5728 SDValue Ptr2, int64_t Size2, 5729 const Value *SrcValue2, int SrcValueOffset2) 5730{ 5731 // If they are the same then they must be aliases. 5732 if (Ptr1 == Ptr2) return true; 5733 5734 // Gather base node and offset information. 5735 SDValue Base1, Base2; 5736 int64_t Offset1, Offset2; 5737 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5738 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5739 5740 // If they have a same base address then... 5741 if (Base1 == Base2) { 5742 // Check to see if the addresses overlap. 5743 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5744 } 5745 5746 // If we know both bases then they can't alias. 5747 if (KnownBase1 && KnownBase2) return false; 5748 5749 if (CombinerGlobalAA) { 5750 // Use alias analysis information. 5751 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5752 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5753 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5754 AliasAnalysis::AliasResult AAResult = 5755 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5756 if (AAResult == AliasAnalysis::NoAlias) 5757 return false; 5758 } 5759 5760 // Otherwise we have to assume they alias. 5761 return true; 5762} 5763 5764/// FindAliasInfo - Extracts the relevant alias information from the memory 5765/// node. Returns true if the operand was a load. 5766bool DAGCombiner::FindAliasInfo(SDNode *N, 5767 SDValue &Ptr, int64_t &Size, 5768 const Value *&SrcValue, int &SrcValueOffset) { 5769 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5770 Ptr = LD->getBasePtr(); 5771 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5772 SrcValue = LD->getSrcValue(); 5773 SrcValueOffset = LD->getSrcValueOffset(); 5774 return true; 5775 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5776 Ptr = ST->getBasePtr(); 5777 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5778 SrcValue = ST->getSrcValue(); 5779 SrcValueOffset = ST->getSrcValueOffset(); 5780 } else { 5781 assert(0 && "FindAliasInfo expected a memory operand"); 5782 } 5783 5784 return false; 5785} 5786 5787/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5788/// looking for aliasing nodes and adding them to the Aliases vector. 5789void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5790 SmallVector<SDValue, 8> &Aliases) { 5791 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5792 std::set<SDNode *> Visited; // Visited node set. 5793 5794 // Get alias information for node. 5795 SDValue Ptr; 5796 int64_t Size; 5797 const Value *SrcValue; 5798 int SrcValueOffset; 5799 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5800 5801 // Starting off. 5802 Chains.push_back(OriginalChain); 5803 5804 // Look at each chain and determine if it is an alias. If so, add it to the 5805 // aliases list. If not, then continue up the chain looking for the next 5806 // candidate. 5807 while (!Chains.empty()) { 5808 SDValue Chain = Chains.back(); 5809 Chains.pop_back(); 5810 5811 // Don't bother if we've been before. 5812 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5813 Visited.insert(Chain.getNode()); 5814 5815 switch (Chain.getOpcode()) { 5816 case ISD::EntryToken: 5817 // Entry token is ideal chain operand, but handled in FindBetterChain. 5818 break; 5819 5820 case ISD::LOAD: 5821 case ISD::STORE: { 5822 // Get alias information for Chain. 5823 SDValue OpPtr; 5824 int64_t OpSize; 5825 const Value *OpSrcValue; 5826 int OpSrcValueOffset; 5827 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5828 OpSrcValue, OpSrcValueOffset); 5829 5830 // If chain is alias then stop here. 5831 if (!(IsLoad && IsOpLoad) && 5832 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5833 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5834 Aliases.push_back(Chain); 5835 } else { 5836 // Look further up the chain. 5837 Chains.push_back(Chain.getOperand(0)); 5838 // Clean up old chain. 5839 AddToWorkList(Chain.getNode()); 5840 } 5841 break; 5842 } 5843 5844 case ISD::TokenFactor: 5845 // We have to check each of the operands of the token factor, so we queue 5846 // then up. Adding the operands to the queue (stack) in reverse order 5847 // maintains the original order and increases the likelihood that getNode 5848 // will find a matching token factor (CSE.) 5849 for (unsigned n = Chain.getNumOperands(); n;) 5850 Chains.push_back(Chain.getOperand(--n)); 5851 // Eliminate the token factor if we can. 5852 AddToWorkList(Chain.getNode()); 5853 break; 5854 5855 default: 5856 // For all other instructions we will just have to take what we can get. 5857 Aliases.push_back(Chain); 5858 break; 5859 } 5860 } 5861} 5862 5863/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5864/// for a better chain (aliasing node.) 5865SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5866 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5867 5868 // Accumulate all the aliases to this node. 5869 GatherAllAliases(N, OldChain, Aliases); 5870 5871 if (Aliases.size() == 0) { 5872 // If no operands then chain to entry token. 5873 return DAG.getEntryNode(); 5874 } else if (Aliases.size() == 1) { 5875 // If a single operand then chain to it. We don't need to revisit it. 5876 return Aliases[0]; 5877 } 5878 5879 // Construct a custom tailored token factor. 5880 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5881 &Aliases[0], Aliases.size()); 5882 5883 // Make sure the old chain gets cleaned up. 5884 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5885 5886 return NewChain; 5887} 5888 5889// SelectionDAG::Combine - This is the entry point for the file. 5890// 5891void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { 5892 /// run - This is the main entry point to this class. 5893 /// 5894 DAGCombiner(*this, AA, Fast).Run(Level); 5895} 5896