DAGCombiner.cpp revision 363e4b90c0a8dfca87ac847001158c743491c06f
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue visitSHL(SDNode *N); 198 SDValue visitSRA(SDNode *N); 199 SDValue visitSRL(SDNode *N); 200 SDValue visitCTLZ(SDNode *N); 201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 202 SDValue visitCTTZ(SDNode *N); 203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 204 SDValue visitCTPOP(SDNode *N); 205 SDValue visitSELECT(SDNode *N); 206 SDValue visitSELECT_CC(SDNode *N); 207 SDValue visitSETCC(SDNode *N); 208 SDValue visitSIGN_EXTEND(SDNode *N); 209 SDValue visitZERO_EXTEND(SDNode *N); 210 SDValue visitANY_EXTEND(SDNode *N); 211 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 212 SDValue visitTRUNCATE(SDNode *N); 213 SDValue visitBITCAST(SDNode *N); 214 SDValue visitBUILD_PAIR(SDNode *N); 215 SDValue visitFADD(SDNode *N); 216 SDValue visitFSUB(SDNode *N); 217 SDValue visitFMUL(SDNode *N); 218 SDValue visitFDIV(SDNode *N); 219 SDValue visitFREM(SDNode *N); 220 SDValue visitFCOPYSIGN(SDNode *N); 221 SDValue visitSINT_TO_FP(SDNode *N); 222 SDValue visitUINT_TO_FP(SDNode *N); 223 SDValue visitFP_TO_SINT(SDNode *N); 224 SDValue visitFP_TO_UINT(SDNode *N); 225 SDValue visitFP_ROUND(SDNode *N); 226 SDValue visitFP_ROUND_INREG(SDNode *N); 227 SDValue visitFP_EXTEND(SDNode *N); 228 SDValue visitFNEG(SDNode *N); 229 SDValue visitFABS(SDNode *N); 230 SDValue visitBRCOND(SDNode *N); 231 SDValue visitBR_CC(SDNode *N); 232 SDValue visitLOAD(SDNode *N); 233 SDValue visitSTORE(SDNode *N); 234 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 235 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 236 SDValue visitBUILD_VECTOR(SDNode *N); 237 SDValue visitCONCAT_VECTORS(SDNode *N); 238 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 239 SDValue visitVECTOR_SHUFFLE(SDNode *N); 240 SDValue visitMEMBARRIER(SDNode *N); 241 242 SDValue XformToShuffleWithZero(SDNode *N); 243 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 244 245 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 246 247 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 248 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 249 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 250 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 251 SDValue N3, ISD::CondCode CC, 252 bool NotExtCompare = false); 253 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 254 DebugLoc DL, bool foldBooleans = true); 255 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 256 unsigned HiOp); 257 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 258 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 259 SDValue BuildSDIV(SDNode *N); 260 SDValue BuildUDIV(SDNode *N); 261 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 262 bool DemandHighBits = true); 263 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 264 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 265 SDValue ReduceLoadWidth(SDNode *N); 266 SDValue ReduceLoadOpStoreWidth(SDNode *N); 267 SDValue TransformFPLoadStorePair(SDNode *N); 268 269 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 270 271 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 272 /// looking for aliasing nodes and adding them to the Aliases vector. 273 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 274 SmallVector<SDValue, 8> &Aliases); 275 276 /// isAlias - Return true if there is any possibility that the two addresses 277 /// overlap. 278 bool isAlias(SDValue Ptr1, int64_t Size1, 279 const Value *SrcValue1, int SrcValueOffset1, 280 unsigned SrcValueAlign1, 281 const MDNode *TBAAInfo1, 282 SDValue Ptr2, int64_t Size2, 283 const Value *SrcValue2, int SrcValueOffset2, 284 unsigned SrcValueAlign2, 285 const MDNode *TBAAInfo2) const; 286 287 /// FindAliasInfo - Extracts the relevant alias information from the memory 288 /// node. Returns true if the operand was a load. 289 bool FindAliasInfo(SDNode *N, 290 SDValue &Ptr, int64_t &Size, 291 const Value *&SrcValue, int &SrcValueOffset, 292 unsigned &SrcValueAlignment, 293 const MDNode *&TBAAInfo) const; 294 295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 296 /// looking for a better chain (aliasing node.) 297 SDValue FindBetterChain(SDNode *N, SDValue Chain); 298 299 public: 300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 301 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 302 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 303 304 /// Run - runs the dag combiner on all nodes in the work list 305 void Run(CombineLevel AtLevel); 306 307 SelectionDAG &getDAG() const { return DAG; } 308 309 /// getShiftAmountTy - Returns a type large enough to hold any valid 310 /// shift amount - before type legalization these can be huge. 311 EVT getShiftAmountTy(EVT LHSTy) { 312 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 313 } 314 315 /// isTypeLegal - This method returns true if we are running before type 316 /// legalization or if the specified VT is legal. 317 bool isTypeLegal(const EVT &VT) { 318 if (!LegalTypes) return true; 319 return TLI.isTypeLegal(VT); 320 } 321 }; 322} 323 324 325namespace { 326/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 327/// nodes from the worklist. 328class WorkListRemover : public SelectionDAG::DAGUpdateListener { 329 DAGCombiner &DC; 330public: 331 explicit WorkListRemover(DAGCombiner &dc) 332 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 333 334 virtual void NodeDeleted(SDNode *N, SDNode *E) { 335 DC.removeFromWorkList(N); 336 } 337}; 338} 339 340//===----------------------------------------------------------------------===// 341// TargetLowering::DAGCombinerInfo implementation 342//===----------------------------------------------------------------------===// 343 344void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 345 ((DAGCombiner*)DC)->AddToWorkList(N); 346} 347 348void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 349 ((DAGCombiner*)DC)->removeFromWorkList(N); 350} 351 352SDValue TargetLowering::DAGCombinerInfo:: 353CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 354 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 355} 356 357SDValue TargetLowering::DAGCombinerInfo:: 358CombineTo(SDNode *N, SDValue Res, bool AddTo) { 359 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 360} 361 362 363SDValue TargetLowering::DAGCombinerInfo:: 364CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 365 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 366} 367 368void TargetLowering::DAGCombinerInfo:: 369CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 370 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 371} 372 373//===----------------------------------------------------------------------===// 374// Helper Functions 375//===----------------------------------------------------------------------===// 376 377/// isNegatibleForFree - Return 1 if we can compute the negated form of the 378/// specified expression for the same cost as the expression itself, or 2 if we 379/// can compute the negated form more cheaply than the expression itself. 380static char isNegatibleForFree(SDValue Op, bool LegalOperations, 381 const TargetLowering &TLI, 382 const TargetOptions *Options, 383 unsigned Depth = 0) { 384 // No compile time optimizations on this type. 385 if (Op.getValueType() == MVT::ppcf128) 386 return 0; 387 388 // fneg is removable even if it has multiple uses. 389 if (Op.getOpcode() == ISD::FNEG) return 2; 390 391 // Don't allow anything with multiple uses. 392 if (!Op.hasOneUse()) return 0; 393 394 // Don't recurse exponentially. 395 if (Depth > 6) return 0; 396 397 switch (Op.getOpcode()) { 398 default: return false; 399 case ISD::ConstantFP: 400 // Don't invert constant FP values after legalize. The negated constant 401 // isn't necessarily legal. 402 return LegalOperations ? 0 : 1; 403 case ISD::FADD: 404 // FIXME: determine better conditions for this xform. 405 if (!Options->UnsafeFPMath) return 0; 406 407 // After operation legalization, it might not be legal to create new FSUBs. 408 if (LegalOperations && 409 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 410 return 0; 411 412 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 413 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 414 Options, Depth + 1)) 415 return V; 416 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 417 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 418 Depth + 1); 419 case ISD::FSUB: 420 // We can't turn -(A-B) into B-A when we honor signed zeros. 421 if (!Options->UnsafeFPMath) return 0; 422 423 // fold (fneg (fsub A, B)) -> (fsub B, A) 424 return 1; 425 426 case ISD::FMUL: 427 case ISD::FDIV: 428 if (Options->HonorSignDependentRoundingFPMath()) return 0; 429 430 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 431 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 432 Options, Depth + 1)) 433 return V; 434 435 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 436 Depth + 1); 437 438 case ISD::FP_EXTEND: 439 case ISD::FP_ROUND: 440 case ISD::FSIN: 441 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 442 Depth + 1); 443 } 444} 445 446/// GetNegatedExpression - If isNegatibleForFree returns true, this function 447/// returns the newly negated expression. 448static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 449 bool LegalOperations, unsigned Depth = 0) { 450 // fneg is removable even if it has multiple uses. 451 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 452 453 // Don't allow anything with multiple uses. 454 assert(Op.hasOneUse() && "Unknown reuse!"); 455 456 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 457 switch (Op.getOpcode()) { 458 default: llvm_unreachable("Unknown code"); 459 case ISD::ConstantFP: { 460 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 461 V.changeSign(); 462 return DAG.getConstantFP(V, Op.getValueType()); 463 } 464 case ISD::FADD: 465 // FIXME: determine better conditions for this xform. 466 assert(DAG.getTarget().Options.UnsafeFPMath); 467 468 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 469 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 470 DAG.getTargetLoweringInfo(), 471 &DAG.getTarget().Options, Depth+1)) 472 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 473 GetNegatedExpression(Op.getOperand(0), DAG, 474 LegalOperations, Depth+1), 475 Op.getOperand(1)); 476 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 477 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 478 GetNegatedExpression(Op.getOperand(1), DAG, 479 LegalOperations, Depth+1), 480 Op.getOperand(0)); 481 case ISD::FSUB: 482 // We can't turn -(A-B) into B-A when we honor signed zeros. 483 assert(DAG.getTarget().Options.UnsafeFPMath); 484 485 // fold (fneg (fsub 0, B)) -> B 486 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 487 if (N0CFP->getValueAPF().isZero()) 488 return Op.getOperand(1); 489 490 // fold (fneg (fsub A, B)) -> (fsub B, A) 491 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 492 Op.getOperand(1), Op.getOperand(0)); 493 494 case ISD::FMUL: 495 case ISD::FDIV: 496 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 497 498 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 499 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 500 DAG.getTargetLoweringInfo(), 501 &DAG.getTarget().Options, Depth+1)) 502 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 503 GetNegatedExpression(Op.getOperand(0), DAG, 504 LegalOperations, Depth+1), 505 Op.getOperand(1)); 506 507 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 508 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 509 Op.getOperand(0), 510 GetNegatedExpression(Op.getOperand(1), DAG, 511 LegalOperations, Depth+1)); 512 513 case ISD::FP_EXTEND: 514 case ISD::FSIN: 515 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 516 GetNegatedExpression(Op.getOperand(0), DAG, 517 LegalOperations, Depth+1)); 518 case ISD::FP_ROUND: 519 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 520 GetNegatedExpression(Op.getOperand(0), DAG, 521 LegalOperations, Depth+1), 522 Op.getOperand(1)); 523 } 524} 525 526 527// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 528// that selects between the values 1 and 0, making it equivalent to a setcc. 529// Also, set the incoming LHS, RHS, and CC references to the appropriate 530// nodes based on the type of node we are checking. This simplifies life a 531// bit for the callers. 532static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 533 SDValue &CC) { 534 if (N.getOpcode() == ISD::SETCC) { 535 LHS = N.getOperand(0); 536 RHS = N.getOperand(1); 537 CC = N.getOperand(2); 538 return true; 539 } 540 if (N.getOpcode() == ISD::SELECT_CC && 541 N.getOperand(2).getOpcode() == ISD::Constant && 542 N.getOperand(3).getOpcode() == ISD::Constant && 543 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 544 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 545 LHS = N.getOperand(0); 546 RHS = N.getOperand(1); 547 CC = N.getOperand(4); 548 return true; 549 } 550 return false; 551} 552 553// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 554// one use. If this is true, it allows the users to invert the operation for 555// free when it is profitable to do so. 556static bool isOneUseSetCC(SDValue N) { 557 SDValue N0, N1, N2; 558 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 559 return true; 560 return false; 561} 562 563SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 564 SDValue N0, SDValue N1) { 565 EVT VT = N0.getValueType(); 566 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 567 if (isa<ConstantSDNode>(N1)) { 568 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 569 SDValue OpNode = 570 DAG.FoldConstantArithmetic(Opc, VT, 571 cast<ConstantSDNode>(N0.getOperand(1)), 572 cast<ConstantSDNode>(N1)); 573 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 574 } 575 if (N0.hasOneUse()) { 576 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 577 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 578 N0.getOperand(0), N1); 579 AddToWorkList(OpNode.getNode()); 580 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 581 } 582 } 583 584 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 585 if (isa<ConstantSDNode>(N0)) { 586 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 587 SDValue OpNode = 588 DAG.FoldConstantArithmetic(Opc, VT, 589 cast<ConstantSDNode>(N1.getOperand(1)), 590 cast<ConstantSDNode>(N0)); 591 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 592 } 593 if (N1.hasOneUse()) { 594 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 595 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 596 N1.getOperand(0), N0); 597 AddToWorkList(OpNode.getNode()); 598 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 599 } 600 } 601 602 return SDValue(); 603} 604 605SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 606 bool AddTo) { 607 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 608 ++NodesCombined; 609 DEBUG(dbgs() << "\nReplacing.1 "; 610 N->dump(&DAG); 611 dbgs() << "\nWith: "; 612 To[0].getNode()->dump(&DAG); 613 dbgs() << " and " << NumTo-1 << " other values\n"; 614 for (unsigned i = 0, e = NumTo; i != e; ++i) 615 assert((!To[i].getNode() || 616 N->getValueType(i) == To[i].getValueType()) && 617 "Cannot combine value to value of different type!")); 618 WorkListRemover DeadNodes(*this); 619 DAG.ReplaceAllUsesWith(N, To); 620 if (AddTo) { 621 // Push the new nodes and any users onto the worklist 622 for (unsigned i = 0, e = NumTo; i != e; ++i) { 623 if (To[i].getNode()) { 624 AddToWorkList(To[i].getNode()); 625 AddUsersToWorkList(To[i].getNode()); 626 } 627 } 628 } 629 630 // Finally, if the node is now dead, remove it from the graph. The node 631 // may not be dead if the replacement process recursively simplified to 632 // something else needing this node. 633 if (N->use_empty()) { 634 // Nodes can be reintroduced into the worklist. Make sure we do not 635 // process a node that has been replaced. 636 removeFromWorkList(N); 637 638 // Finally, since the node is now dead, remove it from the graph. 639 DAG.DeleteNode(N); 640 } 641 return SDValue(N, 0); 642} 643 644void DAGCombiner:: 645CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 646 // Replace all uses. If any nodes become isomorphic to other nodes and 647 // are deleted, make sure to remove them from our worklist. 648 WorkListRemover DeadNodes(*this); 649 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 650 651 // Push the new node and any (possibly new) users onto the worklist. 652 AddToWorkList(TLO.New.getNode()); 653 AddUsersToWorkList(TLO.New.getNode()); 654 655 // Finally, if the node is now dead, remove it from the graph. The node 656 // may not be dead if the replacement process recursively simplified to 657 // something else needing this node. 658 if (TLO.Old.getNode()->use_empty()) { 659 removeFromWorkList(TLO.Old.getNode()); 660 661 // If the operands of this node are only used by the node, they will now 662 // be dead. Make sure to visit them first to delete dead nodes early. 663 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 664 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 665 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 666 667 DAG.DeleteNode(TLO.Old.getNode()); 668 } 669} 670 671/// SimplifyDemandedBits - Check the specified integer node value to see if 672/// it can be simplified or if things it uses can be simplified by bit 673/// propagation. If so, return true. 674bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 675 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 676 APInt KnownZero, KnownOne; 677 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 678 return false; 679 680 // Revisit the node. 681 AddToWorkList(Op.getNode()); 682 683 // Replace the old value with the new one. 684 ++NodesCombined; 685 DEBUG(dbgs() << "\nReplacing.2 "; 686 TLO.Old.getNode()->dump(&DAG); 687 dbgs() << "\nWith: "; 688 TLO.New.getNode()->dump(&DAG); 689 dbgs() << '\n'); 690 691 CommitTargetLoweringOpt(TLO); 692 return true; 693} 694 695void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 696 DebugLoc dl = Load->getDebugLoc(); 697 EVT VT = Load->getValueType(0); 698 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 699 700 DEBUG(dbgs() << "\nReplacing.9 "; 701 Load->dump(&DAG); 702 dbgs() << "\nWith: "; 703 Trunc.getNode()->dump(&DAG); 704 dbgs() << '\n'); 705 WorkListRemover DeadNodes(*this); 706 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 707 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 708 removeFromWorkList(Load); 709 DAG.DeleteNode(Load); 710 AddToWorkList(Trunc.getNode()); 711} 712 713SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 714 Replace = false; 715 DebugLoc dl = Op.getDebugLoc(); 716 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 717 EVT MemVT = LD->getMemoryVT(); 718 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 719 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 720 : ISD::EXTLOAD) 721 : LD->getExtensionType(); 722 Replace = true; 723 return DAG.getExtLoad(ExtType, dl, PVT, 724 LD->getChain(), LD->getBasePtr(), 725 LD->getPointerInfo(), 726 MemVT, LD->isVolatile(), 727 LD->isNonTemporal(), LD->getAlignment()); 728 } 729 730 unsigned Opc = Op.getOpcode(); 731 switch (Opc) { 732 default: break; 733 case ISD::AssertSext: 734 return DAG.getNode(ISD::AssertSext, dl, PVT, 735 SExtPromoteOperand(Op.getOperand(0), PVT), 736 Op.getOperand(1)); 737 case ISD::AssertZext: 738 return DAG.getNode(ISD::AssertZext, dl, PVT, 739 ZExtPromoteOperand(Op.getOperand(0), PVT), 740 Op.getOperand(1)); 741 case ISD::Constant: { 742 unsigned ExtOpc = 743 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 744 return DAG.getNode(ExtOpc, dl, PVT, Op); 745 } 746 } 747 748 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 749 return SDValue(); 750 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 751} 752 753SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 754 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 755 return SDValue(); 756 EVT OldVT = Op.getValueType(); 757 DebugLoc dl = Op.getDebugLoc(); 758 bool Replace = false; 759 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 760 if (NewOp.getNode() == 0) 761 return SDValue(); 762 AddToWorkList(NewOp.getNode()); 763 764 if (Replace) 765 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 766 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 767 DAG.getValueType(OldVT)); 768} 769 770SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 771 EVT OldVT = Op.getValueType(); 772 DebugLoc dl = Op.getDebugLoc(); 773 bool Replace = false; 774 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 775 if (NewOp.getNode() == 0) 776 return SDValue(); 777 AddToWorkList(NewOp.getNode()); 778 779 if (Replace) 780 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 781 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 782} 783 784/// PromoteIntBinOp - Promote the specified integer binary operation if the 785/// target indicates it is beneficial. e.g. On x86, it's usually better to 786/// promote i16 operations to i32 since i16 instructions are longer. 787SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 788 if (!LegalOperations) 789 return SDValue(); 790 791 EVT VT = Op.getValueType(); 792 if (VT.isVector() || !VT.isInteger()) 793 return SDValue(); 794 795 // If operation type is 'undesirable', e.g. i16 on x86, consider 796 // promoting it. 797 unsigned Opc = Op.getOpcode(); 798 if (TLI.isTypeDesirableForOp(Opc, VT)) 799 return SDValue(); 800 801 EVT PVT = VT; 802 // Consult target whether it is a good idea to promote this operation and 803 // what's the right type to promote it to. 804 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 805 assert(PVT != VT && "Don't know what type to promote to!"); 806 807 bool Replace0 = false; 808 SDValue N0 = Op.getOperand(0); 809 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 810 if (NN0.getNode() == 0) 811 return SDValue(); 812 813 bool Replace1 = false; 814 SDValue N1 = Op.getOperand(1); 815 SDValue NN1; 816 if (N0 == N1) 817 NN1 = NN0; 818 else { 819 NN1 = PromoteOperand(N1, PVT, Replace1); 820 if (NN1.getNode() == 0) 821 return SDValue(); 822 } 823 824 AddToWorkList(NN0.getNode()); 825 if (NN1.getNode()) 826 AddToWorkList(NN1.getNode()); 827 828 if (Replace0) 829 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 830 if (Replace1) 831 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 832 833 DEBUG(dbgs() << "\nPromoting "; 834 Op.getNode()->dump(&DAG)); 835 DebugLoc dl = Op.getDebugLoc(); 836 return DAG.getNode(ISD::TRUNCATE, dl, VT, 837 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 838 } 839 return SDValue(); 840} 841 842/// PromoteIntShiftOp - Promote the specified integer shift operation if the 843/// target indicates it is beneficial. e.g. On x86, it's usually better to 844/// promote i16 operations to i32 since i16 instructions are longer. 845SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 846 if (!LegalOperations) 847 return SDValue(); 848 849 EVT VT = Op.getValueType(); 850 if (VT.isVector() || !VT.isInteger()) 851 return SDValue(); 852 853 // If operation type is 'undesirable', e.g. i16 on x86, consider 854 // promoting it. 855 unsigned Opc = Op.getOpcode(); 856 if (TLI.isTypeDesirableForOp(Opc, VT)) 857 return SDValue(); 858 859 EVT PVT = VT; 860 // Consult target whether it is a good idea to promote this operation and 861 // what's the right type to promote it to. 862 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 863 assert(PVT != VT && "Don't know what type to promote to!"); 864 865 bool Replace = false; 866 SDValue N0 = Op.getOperand(0); 867 if (Opc == ISD::SRA) 868 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 869 else if (Opc == ISD::SRL) 870 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 871 else 872 N0 = PromoteOperand(N0, PVT, Replace); 873 if (N0.getNode() == 0) 874 return SDValue(); 875 876 AddToWorkList(N0.getNode()); 877 if (Replace) 878 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 879 880 DEBUG(dbgs() << "\nPromoting "; 881 Op.getNode()->dump(&DAG)); 882 DebugLoc dl = Op.getDebugLoc(); 883 return DAG.getNode(ISD::TRUNCATE, dl, VT, 884 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 885 } 886 return SDValue(); 887} 888 889SDValue DAGCombiner::PromoteExtend(SDValue Op) { 890 if (!LegalOperations) 891 return SDValue(); 892 893 EVT VT = Op.getValueType(); 894 if (VT.isVector() || !VT.isInteger()) 895 return SDValue(); 896 897 // If operation type is 'undesirable', e.g. i16 on x86, consider 898 // promoting it. 899 unsigned Opc = Op.getOpcode(); 900 if (TLI.isTypeDesirableForOp(Opc, VT)) 901 return SDValue(); 902 903 EVT PVT = VT; 904 // Consult target whether it is a good idea to promote this operation and 905 // what's the right type to promote it to. 906 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 907 assert(PVT != VT && "Don't know what type to promote to!"); 908 // fold (aext (aext x)) -> (aext x) 909 // fold (aext (zext x)) -> (zext x) 910 // fold (aext (sext x)) -> (sext x) 911 DEBUG(dbgs() << "\nPromoting "; 912 Op.getNode()->dump(&DAG)); 913 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 914 } 915 return SDValue(); 916} 917 918bool DAGCombiner::PromoteLoad(SDValue Op) { 919 if (!LegalOperations) 920 return false; 921 922 EVT VT = Op.getValueType(); 923 if (VT.isVector() || !VT.isInteger()) 924 return false; 925 926 // If operation type is 'undesirable', e.g. i16 on x86, consider 927 // promoting it. 928 unsigned Opc = Op.getOpcode(); 929 if (TLI.isTypeDesirableForOp(Opc, VT)) 930 return false; 931 932 EVT PVT = VT; 933 // Consult target whether it is a good idea to promote this operation and 934 // what's the right type to promote it to. 935 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 936 assert(PVT != VT && "Don't know what type to promote to!"); 937 938 DebugLoc dl = Op.getDebugLoc(); 939 SDNode *N = Op.getNode(); 940 LoadSDNode *LD = cast<LoadSDNode>(N); 941 EVT MemVT = LD->getMemoryVT(); 942 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 943 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 944 : ISD::EXTLOAD) 945 : LD->getExtensionType(); 946 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 947 LD->getChain(), LD->getBasePtr(), 948 LD->getPointerInfo(), 949 MemVT, LD->isVolatile(), 950 LD->isNonTemporal(), LD->getAlignment()); 951 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 952 953 DEBUG(dbgs() << "\nPromoting "; 954 N->dump(&DAG); 955 dbgs() << "\nTo: "; 956 Result.getNode()->dump(&DAG); 957 dbgs() << '\n'); 958 WorkListRemover DeadNodes(*this); 959 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 960 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 961 removeFromWorkList(N); 962 DAG.DeleteNode(N); 963 AddToWorkList(Result.getNode()); 964 return true; 965 } 966 return false; 967} 968 969 970//===----------------------------------------------------------------------===// 971// Main DAG Combiner implementation 972//===----------------------------------------------------------------------===// 973 974void DAGCombiner::Run(CombineLevel AtLevel) { 975 // set the instance variables, so that the various visit routines may use it. 976 Level = AtLevel; 977 LegalOperations = Level >= AfterLegalizeVectorOps; 978 LegalTypes = Level >= AfterLegalizeTypes; 979 980 // Add all the dag nodes to the worklist. 981 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 982 E = DAG.allnodes_end(); I != E; ++I) 983 AddToWorkList(I); 984 985 // Create a dummy node (which is not added to allnodes), that adds a reference 986 // to the root node, preventing it from being deleted, and tracking any 987 // changes of the root. 988 HandleSDNode Dummy(DAG.getRoot()); 989 990 // The root of the dag may dangle to deleted nodes until the dag combiner is 991 // done. Set it to null to avoid confusion. 992 DAG.setRoot(SDValue()); 993 994 // while the worklist isn't empty, find a node and 995 // try and combine it. 996 while (!WorkListContents.empty()) { 997 SDNode *N; 998 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 999 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1000 // worklist *should* contain, and check the node we want to visit is should 1001 // actually be visited. 1002 do { 1003 N = WorkListOrder.pop_back_val(); 1004 } while (!WorkListContents.erase(N)); 1005 1006 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1007 // N is deleted from the DAG, since they too may now be dead or may have a 1008 // reduced number of uses, allowing other xforms. 1009 if (N->use_empty() && N != &Dummy) { 1010 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1011 AddToWorkList(N->getOperand(i).getNode()); 1012 1013 DAG.DeleteNode(N); 1014 continue; 1015 } 1016 1017 SDValue RV = combine(N); 1018 1019 if (RV.getNode() == 0) 1020 continue; 1021 1022 ++NodesCombined; 1023 1024 // If we get back the same node we passed in, rather than a new node or 1025 // zero, we know that the node must have defined multiple values and 1026 // CombineTo was used. Since CombineTo takes care of the worklist 1027 // mechanics for us, we have no work to do in this case. 1028 if (RV.getNode() == N) 1029 continue; 1030 1031 assert(N->getOpcode() != ISD::DELETED_NODE && 1032 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1033 "Node was deleted but visit returned new node!"); 1034 1035 DEBUG(dbgs() << "\nReplacing.3 "; 1036 N->dump(&DAG); 1037 dbgs() << "\nWith: "; 1038 RV.getNode()->dump(&DAG); 1039 dbgs() << '\n'); 1040 1041 // Transfer debug value. 1042 DAG.TransferDbgValues(SDValue(N, 0), RV); 1043 WorkListRemover DeadNodes(*this); 1044 if (N->getNumValues() == RV.getNode()->getNumValues()) 1045 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1046 else { 1047 assert(N->getValueType(0) == RV.getValueType() && 1048 N->getNumValues() == 1 && "Type mismatch"); 1049 SDValue OpV = RV; 1050 DAG.ReplaceAllUsesWith(N, &OpV); 1051 } 1052 1053 // Push the new node and any users onto the worklist 1054 AddToWorkList(RV.getNode()); 1055 AddUsersToWorkList(RV.getNode()); 1056 1057 // Add any uses of the old node to the worklist in case this node is the 1058 // last one that uses them. They may become dead after this node is 1059 // deleted. 1060 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1061 AddToWorkList(N->getOperand(i).getNode()); 1062 1063 // Finally, if the node is now dead, remove it from the graph. The node 1064 // may not be dead if the replacement process recursively simplified to 1065 // something else needing this node. 1066 if (N->use_empty()) { 1067 // Nodes can be reintroduced into the worklist. Make sure we do not 1068 // process a node that has been replaced. 1069 removeFromWorkList(N); 1070 1071 // Finally, since the node is now dead, remove it from the graph. 1072 DAG.DeleteNode(N); 1073 } 1074 } 1075 1076 // If the root changed (e.g. it was a dead load, update the root). 1077 DAG.setRoot(Dummy.getValue()); 1078 DAG.RemoveDeadNodes(); 1079} 1080 1081SDValue DAGCombiner::visit(SDNode *N) { 1082 switch (N->getOpcode()) { 1083 default: break; 1084 case ISD::TokenFactor: return visitTokenFactor(N); 1085 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1086 case ISD::ADD: return visitADD(N); 1087 case ISD::SUB: return visitSUB(N); 1088 case ISD::ADDC: return visitADDC(N); 1089 case ISD::SUBC: return visitSUBC(N); 1090 case ISD::ADDE: return visitADDE(N); 1091 case ISD::SUBE: return visitSUBE(N); 1092 case ISD::MUL: return visitMUL(N); 1093 case ISD::SDIV: return visitSDIV(N); 1094 case ISD::UDIV: return visitUDIV(N); 1095 case ISD::SREM: return visitSREM(N); 1096 case ISD::UREM: return visitUREM(N); 1097 case ISD::MULHU: return visitMULHU(N); 1098 case ISD::MULHS: return visitMULHS(N); 1099 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1100 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1101 case ISD::SMULO: return visitSMULO(N); 1102 case ISD::UMULO: return visitUMULO(N); 1103 case ISD::SDIVREM: return visitSDIVREM(N); 1104 case ISD::UDIVREM: return visitUDIVREM(N); 1105 case ISD::AND: return visitAND(N); 1106 case ISD::OR: return visitOR(N); 1107 case ISD::XOR: return visitXOR(N); 1108 case ISD::SHL: return visitSHL(N); 1109 case ISD::SRA: return visitSRA(N); 1110 case ISD::SRL: return visitSRL(N); 1111 case ISD::CTLZ: return visitCTLZ(N); 1112 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1113 case ISD::CTTZ: return visitCTTZ(N); 1114 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1115 case ISD::CTPOP: return visitCTPOP(N); 1116 case ISD::SELECT: return visitSELECT(N); 1117 case ISD::SELECT_CC: return visitSELECT_CC(N); 1118 case ISD::SETCC: return visitSETCC(N); 1119 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1120 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1121 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1122 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1123 case ISD::TRUNCATE: return visitTRUNCATE(N); 1124 case ISD::BITCAST: return visitBITCAST(N); 1125 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1126 case ISD::FADD: return visitFADD(N); 1127 case ISD::FSUB: return visitFSUB(N); 1128 case ISD::FMUL: return visitFMUL(N); 1129 case ISD::FDIV: return visitFDIV(N); 1130 case ISD::FREM: return visitFREM(N); 1131 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1132 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1133 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1134 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1135 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1136 case ISD::FP_ROUND: return visitFP_ROUND(N); 1137 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1138 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1139 case ISD::FNEG: return visitFNEG(N); 1140 case ISD::FABS: return visitFABS(N); 1141 case ISD::BRCOND: return visitBRCOND(N); 1142 case ISD::BR_CC: return visitBR_CC(N); 1143 case ISD::LOAD: return visitLOAD(N); 1144 case ISD::STORE: return visitSTORE(N); 1145 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1146 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1147 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1148 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1149 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1150 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1151 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1152 } 1153 return SDValue(); 1154} 1155 1156SDValue DAGCombiner::combine(SDNode *N) { 1157 SDValue RV = visit(N); 1158 1159 // If nothing happened, try a target-specific DAG combine. 1160 if (RV.getNode() == 0) { 1161 assert(N->getOpcode() != ISD::DELETED_NODE && 1162 "Node was deleted but visit returned NULL!"); 1163 1164 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1165 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1166 1167 // Expose the DAG combiner to the target combiner impls. 1168 TargetLowering::DAGCombinerInfo 1169 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1170 1171 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1172 } 1173 } 1174 1175 // If nothing happened still, try promoting the operation. 1176 if (RV.getNode() == 0) { 1177 switch (N->getOpcode()) { 1178 default: break; 1179 case ISD::ADD: 1180 case ISD::SUB: 1181 case ISD::MUL: 1182 case ISD::AND: 1183 case ISD::OR: 1184 case ISD::XOR: 1185 RV = PromoteIntBinOp(SDValue(N, 0)); 1186 break; 1187 case ISD::SHL: 1188 case ISD::SRA: 1189 case ISD::SRL: 1190 RV = PromoteIntShiftOp(SDValue(N, 0)); 1191 break; 1192 case ISD::SIGN_EXTEND: 1193 case ISD::ZERO_EXTEND: 1194 case ISD::ANY_EXTEND: 1195 RV = PromoteExtend(SDValue(N, 0)); 1196 break; 1197 case ISD::LOAD: 1198 if (PromoteLoad(SDValue(N, 0))) 1199 RV = SDValue(N, 0); 1200 break; 1201 } 1202 } 1203 1204 // If N is a commutative binary node, try commuting it to enable more 1205 // sdisel CSE. 1206 if (RV.getNode() == 0 && 1207 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1208 N->getNumValues() == 1) { 1209 SDValue N0 = N->getOperand(0); 1210 SDValue N1 = N->getOperand(1); 1211 1212 // Constant operands are canonicalized to RHS. 1213 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1214 SDValue Ops[] = { N1, N0 }; 1215 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1216 Ops, 2); 1217 if (CSENode) 1218 return SDValue(CSENode, 0); 1219 } 1220 } 1221 1222 return RV; 1223} 1224 1225/// getInputChainForNode - Given a node, return its input chain if it has one, 1226/// otherwise return a null sd operand. 1227static SDValue getInputChainForNode(SDNode *N) { 1228 if (unsigned NumOps = N->getNumOperands()) { 1229 if (N->getOperand(0).getValueType() == MVT::Other) 1230 return N->getOperand(0); 1231 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1232 return N->getOperand(NumOps-1); 1233 for (unsigned i = 1; i < NumOps-1; ++i) 1234 if (N->getOperand(i).getValueType() == MVT::Other) 1235 return N->getOperand(i); 1236 } 1237 return SDValue(); 1238} 1239 1240SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1241 // If N has two operands, where one has an input chain equal to the other, 1242 // the 'other' chain is redundant. 1243 if (N->getNumOperands() == 2) { 1244 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1245 return N->getOperand(0); 1246 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1247 return N->getOperand(1); 1248 } 1249 1250 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1251 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1252 SmallPtrSet<SDNode*, 16> SeenOps; 1253 bool Changed = false; // If we should replace this token factor. 1254 1255 // Start out with this token factor. 1256 TFs.push_back(N); 1257 1258 // Iterate through token factors. The TFs grows when new token factors are 1259 // encountered. 1260 for (unsigned i = 0; i < TFs.size(); ++i) { 1261 SDNode *TF = TFs[i]; 1262 1263 // Check each of the operands. 1264 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1265 SDValue Op = TF->getOperand(i); 1266 1267 switch (Op.getOpcode()) { 1268 case ISD::EntryToken: 1269 // Entry tokens don't need to be added to the list. They are 1270 // rededundant. 1271 Changed = true; 1272 break; 1273 1274 case ISD::TokenFactor: 1275 if (Op.hasOneUse() && 1276 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1277 // Queue up for processing. 1278 TFs.push_back(Op.getNode()); 1279 // Clean up in case the token factor is removed. 1280 AddToWorkList(Op.getNode()); 1281 Changed = true; 1282 break; 1283 } 1284 // Fall thru 1285 1286 default: 1287 // Only add if it isn't already in the list. 1288 if (SeenOps.insert(Op.getNode())) 1289 Ops.push_back(Op); 1290 else 1291 Changed = true; 1292 break; 1293 } 1294 } 1295 } 1296 1297 SDValue Result; 1298 1299 // If we've change things around then replace token factor. 1300 if (Changed) { 1301 if (Ops.empty()) { 1302 // The entry token is the only possible outcome. 1303 Result = DAG.getEntryNode(); 1304 } else { 1305 // New and improved token factor. 1306 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1307 MVT::Other, &Ops[0], Ops.size()); 1308 } 1309 1310 // Don't add users to work list. 1311 return CombineTo(N, Result, false); 1312 } 1313 1314 return Result; 1315} 1316 1317/// MERGE_VALUES can always be eliminated. 1318SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1319 WorkListRemover DeadNodes(*this); 1320 // Replacing results may cause a different MERGE_VALUES to suddenly 1321 // be CSE'd with N, and carry its uses with it. Iterate until no 1322 // uses remain, to ensure that the node can be safely deleted. 1323 do { 1324 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1325 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1326 } while (!N->use_empty()); 1327 removeFromWorkList(N); 1328 DAG.DeleteNode(N); 1329 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1330} 1331 1332static 1333SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1334 SelectionDAG &DAG) { 1335 EVT VT = N0.getValueType(); 1336 SDValue N00 = N0.getOperand(0); 1337 SDValue N01 = N0.getOperand(1); 1338 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1339 1340 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1341 isa<ConstantSDNode>(N00.getOperand(1))) { 1342 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1343 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1344 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1345 N00.getOperand(0), N01), 1346 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1347 N00.getOperand(1), N01)); 1348 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1349 } 1350 1351 return SDValue(); 1352} 1353 1354SDValue DAGCombiner::visitADD(SDNode *N) { 1355 SDValue N0 = N->getOperand(0); 1356 SDValue N1 = N->getOperand(1); 1357 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1358 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1359 EVT VT = N0.getValueType(); 1360 1361 // fold vector ops 1362 if (VT.isVector()) { 1363 SDValue FoldedVOp = SimplifyVBinOp(N); 1364 if (FoldedVOp.getNode()) return FoldedVOp; 1365 } 1366 1367 // fold (add x, undef) -> undef 1368 if (N0.getOpcode() == ISD::UNDEF) 1369 return N0; 1370 if (N1.getOpcode() == ISD::UNDEF) 1371 return N1; 1372 // fold (add c1, c2) -> c1+c2 1373 if (N0C && N1C) 1374 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1375 // canonicalize constant to RHS 1376 if (N0C && !N1C) 1377 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1378 // fold (add x, 0) -> x 1379 if (N1C && N1C->isNullValue()) 1380 return N0; 1381 // fold (add Sym, c) -> Sym+c 1382 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1383 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1384 GA->getOpcode() == ISD::GlobalAddress) 1385 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1386 GA->getOffset() + 1387 (uint64_t)N1C->getSExtValue()); 1388 // fold ((c1-A)+c2) -> (c1+c2)-A 1389 if (N1C && N0.getOpcode() == ISD::SUB) 1390 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1391 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1392 DAG.getConstant(N1C->getAPIntValue()+ 1393 N0C->getAPIntValue(), VT), 1394 N0.getOperand(1)); 1395 // reassociate add 1396 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1397 if (RADD.getNode() != 0) 1398 return RADD; 1399 // fold ((0-A) + B) -> B-A 1400 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1401 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1402 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1403 // fold (A + (0-B)) -> A-B 1404 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1405 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1406 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1407 // fold (A+(B-A)) -> B 1408 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1409 return N1.getOperand(0); 1410 // fold ((B-A)+A) -> B 1411 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1412 return N0.getOperand(0); 1413 // fold (A+(B-(A+C))) to (B-C) 1414 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1415 N0 == N1.getOperand(1).getOperand(0)) 1416 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1417 N1.getOperand(1).getOperand(1)); 1418 // fold (A+(B-(C+A))) to (B-C) 1419 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1420 N0 == N1.getOperand(1).getOperand(1)) 1421 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1422 N1.getOperand(1).getOperand(0)); 1423 // fold (A+((B-A)+or-C)) to (B+or-C) 1424 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1425 N1.getOperand(0).getOpcode() == ISD::SUB && 1426 N0 == N1.getOperand(0).getOperand(1)) 1427 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1428 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1429 1430 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1431 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1432 SDValue N00 = N0.getOperand(0); 1433 SDValue N01 = N0.getOperand(1); 1434 SDValue N10 = N1.getOperand(0); 1435 SDValue N11 = N1.getOperand(1); 1436 1437 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1438 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1439 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1440 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1441 } 1442 1443 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1444 return SDValue(N, 0); 1445 1446 // fold (a+b) -> (a|b) iff a and b share no bits. 1447 if (VT.isInteger() && !VT.isVector()) { 1448 APInt LHSZero, LHSOne; 1449 APInt RHSZero, RHSOne; 1450 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1451 1452 if (LHSZero.getBoolValue()) { 1453 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1454 1455 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1456 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1457 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1458 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1459 } 1460 } 1461 1462 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1463 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1464 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1465 if (Result.getNode()) return Result; 1466 } 1467 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1468 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1469 if (Result.getNode()) return Result; 1470 } 1471 1472 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1473 if (N1.getOpcode() == ISD::SHL && 1474 N1.getOperand(0).getOpcode() == ISD::SUB) 1475 if (ConstantSDNode *C = 1476 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1477 if (C->getAPIntValue() == 0) 1478 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1479 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1480 N1.getOperand(0).getOperand(1), 1481 N1.getOperand(1))); 1482 if (N0.getOpcode() == ISD::SHL && 1483 N0.getOperand(0).getOpcode() == ISD::SUB) 1484 if (ConstantSDNode *C = 1485 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1486 if (C->getAPIntValue() == 0) 1487 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1488 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1489 N0.getOperand(0).getOperand(1), 1490 N0.getOperand(1))); 1491 1492 if (N1.getOpcode() == ISD::AND) { 1493 SDValue AndOp0 = N1.getOperand(0); 1494 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1495 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1496 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1497 1498 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1499 // and similar xforms where the inner op is either ~0 or 0. 1500 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1501 DebugLoc DL = N->getDebugLoc(); 1502 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1503 } 1504 } 1505 1506 // add (sext i1), X -> sub X, (zext i1) 1507 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1508 N0.getOperand(0).getValueType() == MVT::i1 && 1509 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1510 DebugLoc DL = N->getDebugLoc(); 1511 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1512 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1513 } 1514 1515 return SDValue(); 1516} 1517 1518SDValue DAGCombiner::visitADDC(SDNode *N) { 1519 SDValue N0 = N->getOperand(0); 1520 SDValue N1 = N->getOperand(1); 1521 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1522 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1523 EVT VT = N0.getValueType(); 1524 1525 // If the flag result is dead, turn this into an ADD. 1526 if (!N->hasAnyUseOfValue(1)) 1527 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1528 DAG.getNode(ISD::CARRY_FALSE, 1529 N->getDebugLoc(), MVT::Glue)); 1530 1531 // canonicalize constant to RHS. 1532 if (N0C && !N1C) 1533 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1534 1535 // fold (addc x, 0) -> x + no carry out 1536 if (N1C && N1C->isNullValue()) 1537 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1538 N->getDebugLoc(), MVT::Glue)); 1539 1540 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1541 APInt LHSZero, LHSOne; 1542 APInt RHSZero, RHSOne; 1543 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1544 1545 if (LHSZero.getBoolValue()) { 1546 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1547 1548 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1549 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1550 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1551 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1552 DAG.getNode(ISD::CARRY_FALSE, 1553 N->getDebugLoc(), MVT::Glue)); 1554 } 1555 1556 return SDValue(); 1557} 1558 1559SDValue DAGCombiner::visitADDE(SDNode *N) { 1560 SDValue N0 = N->getOperand(0); 1561 SDValue N1 = N->getOperand(1); 1562 SDValue CarryIn = N->getOperand(2); 1563 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1564 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1565 1566 // canonicalize constant to RHS 1567 if (N0C && !N1C) 1568 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1569 N1, N0, CarryIn); 1570 1571 // fold (adde x, y, false) -> (addc x, y) 1572 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1573 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1574 1575 return SDValue(); 1576} 1577 1578// Since it may not be valid to emit a fold to zero for vector initializers 1579// check if we can before folding. 1580static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1581 SelectionDAG &DAG, bool LegalOperations) { 1582 if (!VT.isVector()) { 1583 return DAG.getConstant(0, VT); 1584 } 1585 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1586 // Produce a vector of zeros. 1587 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1588 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1589 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1590 &Ops[0], Ops.size()); 1591 } 1592 return SDValue(); 1593} 1594 1595SDValue DAGCombiner::visitSUB(SDNode *N) { 1596 SDValue N0 = N->getOperand(0); 1597 SDValue N1 = N->getOperand(1); 1598 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1599 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1600 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1601 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1602 EVT VT = N0.getValueType(); 1603 1604 // fold vector ops 1605 if (VT.isVector()) { 1606 SDValue FoldedVOp = SimplifyVBinOp(N); 1607 if (FoldedVOp.getNode()) return FoldedVOp; 1608 } 1609 1610 // fold (sub x, x) -> 0 1611 // FIXME: Refactor this and xor and other similar operations together. 1612 if (N0 == N1) 1613 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1614 // fold (sub c1, c2) -> c1-c2 1615 if (N0C && N1C) 1616 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1617 // fold (sub x, c) -> (add x, -c) 1618 if (N1C) 1619 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1620 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1621 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1622 if (N0C && N0C->isAllOnesValue()) 1623 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1624 // fold A-(A-B) -> B 1625 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1626 return N1.getOperand(1); 1627 // fold (A+B)-A -> B 1628 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1629 return N0.getOperand(1); 1630 // fold (A+B)-B -> A 1631 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1632 return N0.getOperand(0); 1633 // fold C2-(A+C1) -> (C2-C1)-A 1634 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1635 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT); 1636 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1637 N1.getOperand(0)); 1638 } 1639 // fold ((A+(B+or-C))-B) -> A+or-C 1640 if (N0.getOpcode() == ISD::ADD && 1641 (N0.getOperand(1).getOpcode() == ISD::SUB || 1642 N0.getOperand(1).getOpcode() == ISD::ADD) && 1643 N0.getOperand(1).getOperand(0) == N1) 1644 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1645 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1646 // fold ((A+(C+B))-B) -> A+C 1647 if (N0.getOpcode() == ISD::ADD && 1648 N0.getOperand(1).getOpcode() == ISD::ADD && 1649 N0.getOperand(1).getOperand(1) == N1) 1650 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1651 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1652 // fold ((A-(B-C))-C) -> A-B 1653 if (N0.getOpcode() == ISD::SUB && 1654 N0.getOperand(1).getOpcode() == ISD::SUB && 1655 N0.getOperand(1).getOperand(1) == N1) 1656 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1657 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1658 1659 // If either operand of a sub is undef, the result is undef 1660 if (N0.getOpcode() == ISD::UNDEF) 1661 return N0; 1662 if (N1.getOpcode() == ISD::UNDEF) 1663 return N1; 1664 1665 // If the relocation model supports it, consider symbol offsets. 1666 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1667 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1668 // fold (sub Sym, c) -> Sym-c 1669 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1670 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1671 GA->getOffset() - 1672 (uint64_t)N1C->getSExtValue()); 1673 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1674 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1675 if (GA->getGlobal() == GB->getGlobal()) 1676 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1677 VT); 1678 } 1679 1680 return SDValue(); 1681} 1682 1683SDValue DAGCombiner::visitSUBC(SDNode *N) { 1684 SDValue N0 = N->getOperand(0); 1685 SDValue N1 = N->getOperand(1); 1686 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1687 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1688 EVT VT = N0.getValueType(); 1689 1690 // If the flag result is dead, turn this into an SUB. 1691 if (!N->hasAnyUseOfValue(1)) 1692 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1693 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1694 MVT::Glue)); 1695 1696 // fold (subc x, x) -> 0 + no borrow 1697 if (N0 == N1) 1698 return CombineTo(N, DAG.getConstant(0, VT), 1699 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1700 MVT::Glue)); 1701 1702 // fold (subc x, 0) -> x + no borrow 1703 if (N1C && N1C->isNullValue()) 1704 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1705 MVT::Glue)); 1706 1707 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1708 if (N0C && N0C->isAllOnesValue()) 1709 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1710 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1711 MVT::Glue)); 1712 1713 return SDValue(); 1714} 1715 1716SDValue DAGCombiner::visitSUBE(SDNode *N) { 1717 SDValue N0 = N->getOperand(0); 1718 SDValue N1 = N->getOperand(1); 1719 SDValue CarryIn = N->getOperand(2); 1720 1721 // fold (sube x, y, false) -> (subc x, y) 1722 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1723 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1724 1725 return SDValue(); 1726} 1727 1728SDValue DAGCombiner::visitMUL(SDNode *N) { 1729 SDValue N0 = N->getOperand(0); 1730 SDValue N1 = N->getOperand(1); 1731 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1732 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1733 EVT VT = N0.getValueType(); 1734 1735 // fold vector ops 1736 if (VT.isVector()) { 1737 SDValue FoldedVOp = SimplifyVBinOp(N); 1738 if (FoldedVOp.getNode()) return FoldedVOp; 1739 } 1740 1741 // fold (mul x, undef) -> 0 1742 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1743 return DAG.getConstant(0, VT); 1744 // fold (mul c1, c2) -> c1*c2 1745 if (N0C && N1C) 1746 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1747 // canonicalize constant to RHS 1748 if (N0C && !N1C) 1749 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1750 // fold (mul x, 0) -> 0 1751 if (N1C && N1C->isNullValue()) 1752 return N1; 1753 // fold (mul x, -1) -> 0-x 1754 if (N1C && N1C->isAllOnesValue()) 1755 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1756 DAG.getConstant(0, VT), N0); 1757 // fold (mul x, (1 << c)) -> x << c 1758 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1759 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1760 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1761 getShiftAmountTy(N0.getValueType()))); 1762 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1763 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1764 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1765 // FIXME: If the input is something that is easily negated (e.g. a 1766 // single-use add), we should put the negate there. 1767 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1768 DAG.getConstant(0, VT), 1769 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1770 DAG.getConstant(Log2Val, 1771 getShiftAmountTy(N0.getValueType())))); 1772 } 1773 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1774 if (N1C && N0.getOpcode() == ISD::SHL && 1775 isa<ConstantSDNode>(N0.getOperand(1))) { 1776 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1777 N1, N0.getOperand(1)); 1778 AddToWorkList(C3.getNode()); 1779 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1780 N0.getOperand(0), C3); 1781 } 1782 1783 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1784 // use. 1785 { 1786 SDValue Sh(0,0), Y(0,0); 1787 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1788 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1789 N0.getNode()->hasOneUse()) { 1790 Sh = N0; Y = N1; 1791 } else if (N1.getOpcode() == ISD::SHL && 1792 isa<ConstantSDNode>(N1.getOperand(1)) && 1793 N1.getNode()->hasOneUse()) { 1794 Sh = N1; Y = N0; 1795 } 1796 1797 if (Sh.getNode()) { 1798 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1799 Sh.getOperand(0), Y); 1800 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1801 Mul, Sh.getOperand(1)); 1802 } 1803 } 1804 1805 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1806 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1807 isa<ConstantSDNode>(N0.getOperand(1))) 1808 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1809 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1810 N0.getOperand(0), N1), 1811 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1812 N0.getOperand(1), N1)); 1813 1814 // reassociate mul 1815 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1816 if (RMUL.getNode() != 0) 1817 return RMUL; 1818 1819 return SDValue(); 1820} 1821 1822SDValue DAGCombiner::visitSDIV(SDNode *N) { 1823 SDValue N0 = N->getOperand(0); 1824 SDValue N1 = N->getOperand(1); 1825 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1826 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1827 EVT VT = N->getValueType(0); 1828 1829 // fold vector ops 1830 if (VT.isVector()) { 1831 SDValue FoldedVOp = SimplifyVBinOp(N); 1832 if (FoldedVOp.getNode()) return FoldedVOp; 1833 } 1834 1835 // fold (sdiv c1, c2) -> c1/c2 1836 if (N0C && N1C && !N1C->isNullValue()) 1837 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1838 // fold (sdiv X, 1) -> X 1839 if (N1C && N1C->getAPIntValue() == 1LL) 1840 return N0; 1841 // fold (sdiv X, -1) -> 0-X 1842 if (N1C && N1C->isAllOnesValue()) 1843 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1844 DAG.getConstant(0, VT), N0); 1845 // If we know the sign bits of both operands are zero, strength reduce to a 1846 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1847 if (!VT.isVector()) { 1848 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1849 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1850 N0, N1); 1851 } 1852 // fold (sdiv X, pow2) -> simple ops after legalize 1853 if (N1C && !N1C->isNullValue() && 1854 (N1C->getAPIntValue().isPowerOf2() || 1855 (-N1C->getAPIntValue()).isPowerOf2())) { 1856 // If dividing by powers of two is cheap, then don't perform the following 1857 // fold. 1858 if (TLI.isPow2DivCheap()) 1859 return SDValue(); 1860 1861 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1862 1863 // Splat the sign bit into the register 1864 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1865 DAG.getConstant(VT.getSizeInBits()-1, 1866 getShiftAmountTy(N0.getValueType()))); 1867 AddToWorkList(SGN.getNode()); 1868 1869 // Add (N0 < 0) ? abs2 - 1 : 0; 1870 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1871 DAG.getConstant(VT.getSizeInBits() - lg2, 1872 getShiftAmountTy(SGN.getValueType()))); 1873 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1874 AddToWorkList(SRL.getNode()); 1875 AddToWorkList(ADD.getNode()); // Divide by pow2 1876 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1877 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1878 1879 // If we're dividing by a positive value, we're done. Otherwise, we must 1880 // negate the result. 1881 if (N1C->getAPIntValue().isNonNegative()) 1882 return SRA; 1883 1884 AddToWorkList(SRA.getNode()); 1885 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1886 DAG.getConstant(0, VT), SRA); 1887 } 1888 1889 // if integer divide is expensive and we satisfy the requirements, emit an 1890 // alternate sequence. 1891 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1892 SDValue Op = BuildSDIV(N); 1893 if (Op.getNode()) return Op; 1894 } 1895 1896 // undef / X -> 0 1897 if (N0.getOpcode() == ISD::UNDEF) 1898 return DAG.getConstant(0, VT); 1899 // X / undef -> undef 1900 if (N1.getOpcode() == ISD::UNDEF) 1901 return N1; 1902 1903 return SDValue(); 1904} 1905 1906SDValue DAGCombiner::visitUDIV(SDNode *N) { 1907 SDValue N0 = N->getOperand(0); 1908 SDValue N1 = N->getOperand(1); 1909 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1910 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1911 EVT VT = N->getValueType(0); 1912 1913 // fold vector ops 1914 if (VT.isVector()) { 1915 SDValue FoldedVOp = SimplifyVBinOp(N); 1916 if (FoldedVOp.getNode()) return FoldedVOp; 1917 } 1918 1919 // fold (udiv c1, c2) -> c1/c2 1920 if (N0C && N1C && !N1C->isNullValue()) 1921 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1922 // fold (udiv x, (1 << c)) -> x >>u c 1923 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1924 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1925 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1926 getShiftAmountTy(N0.getValueType()))); 1927 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1928 if (N1.getOpcode() == ISD::SHL) { 1929 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1930 if (SHC->getAPIntValue().isPowerOf2()) { 1931 EVT ADDVT = N1.getOperand(1).getValueType(); 1932 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1933 N1.getOperand(1), 1934 DAG.getConstant(SHC->getAPIntValue() 1935 .logBase2(), 1936 ADDVT)); 1937 AddToWorkList(Add.getNode()); 1938 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1939 } 1940 } 1941 } 1942 // fold (udiv x, c) -> alternate 1943 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1944 SDValue Op = BuildUDIV(N); 1945 if (Op.getNode()) return Op; 1946 } 1947 1948 // undef / X -> 0 1949 if (N0.getOpcode() == ISD::UNDEF) 1950 return DAG.getConstant(0, VT); 1951 // X / undef -> undef 1952 if (N1.getOpcode() == ISD::UNDEF) 1953 return N1; 1954 1955 return SDValue(); 1956} 1957 1958SDValue DAGCombiner::visitSREM(SDNode *N) { 1959 SDValue N0 = N->getOperand(0); 1960 SDValue N1 = N->getOperand(1); 1961 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1962 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1963 EVT VT = N->getValueType(0); 1964 1965 // fold (srem c1, c2) -> c1%c2 1966 if (N0C && N1C && !N1C->isNullValue()) 1967 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1968 // If we know the sign bits of both operands are zero, strength reduce to a 1969 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1970 if (!VT.isVector()) { 1971 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1972 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1973 } 1974 1975 // If X/C can be simplified by the division-by-constant logic, lower 1976 // X%C to the equivalent of X-X/C*C. 1977 if (N1C && !N1C->isNullValue()) { 1978 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1979 AddToWorkList(Div.getNode()); 1980 SDValue OptimizedDiv = combine(Div.getNode()); 1981 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1982 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1983 OptimizedDiv, N1); 1984 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1985 AddToWorkList(Mul.getNode()); 1986 return Sub; 1987 } 1988 } 1989 1990 // undef % X -> 0 1991 if (N0.getOpcode() == ISD::UNDEF) 1992 return DAG.getConstant(0, VT); 1993 // X % undef -> undef 1994 if (N1.getOpcode() == ISD::UNDEF) 1995 return N1; 1996 1997 return SDValue(); 1998} 1999 2000SDValue DAGCombiner::visitUREM(SDNode *N) { 2001 SDValue N0 = N->getOperand(0); 2002 SDValue N1 = N->getOperand(1); 2003 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2004 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2005 EVT VT = N->getValueType(0); 2006 2007 // fold (urem c1, c2) -> c1%c2 2008 if (N0C && N1C && !N1C->isNullValue()) 2009 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2010 // fold (urem x, pow2) -> (and x, pow2-1) 2011 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2012 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2013 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2014 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2015 if (N1.getOpcode() == ISD::SHL) { 2016 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2017 if (SHC->getAPIntValue().isPowerOf2()) { 2018 SDValue Add = 2019 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2020 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2021 VT)); 2022 AddToWorkList(Add.getNode()); 2023 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2024 } 2025 } 2026 } 2027 2028 // If X/C can be simplified by the division-by-constant logic, lower 2029 // X%C to the equivalent of X-X/C*C. 2030 if (N1C && !N1C->isNullValue()) { 2031 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2032 AddToWorkList(Div.getNode()); 2033 SDValue OptimizedDiv = combine(Div.getNode()); 2034 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2035 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2036 OptimizedDiv, N1); 2037 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2038 AddToWorkList(Mul.getNode()); 2039 return Sub; 2040 } 2041 } 2042 2043 // undef % X -> 0 2044 if (N0.getOpcode() == ISD::UNDEF) 2045 return DAG.getConstant(0, VT); 2046 // X % undef -> undef 2047 if (N1.getOpcode() == ISD::UNDEF) 2048 return N1; 2049 2050 return SDValue(); 2051} 2052 2053SDValue DAGCombiner::visitMULHS(SDNode *N) { 2054 SDValue N0 = N->getOperand(0); 2055 SDValue N1 = N->getOperand(1); 2056 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2057 EVT VT = N->getValueType(0); 2058 DebugLoc DL = N->getDebugLoc(); 2059 2060 // fold (mulhs x, 0) -> 0 2061 if (N1C && N1C->isNullValue()) 2062 return N1; 2063 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2064 if (N1C && N1C->getAPIntValue() == 1) 2065 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2066 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2067 getShiftAmountTy(N0.getValueType()))); 2068 // fold (mulhs x, undef) -> 0 2069 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2070 return DAG.getConstant(0, VT); 2071 2072 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2073 // plus a shift. 2074 if (VT.isSimple() && !VT.isVector()) { 2075 MVT Simple = VT.getSimpleVT(); 2076 unsigned SimpleSize = Simple.getSizeInBits(); 2077 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2078 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2079 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2080 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2081 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2082 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2083 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2084 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2085 } 2086 } 2087 2088 return SDValue(); 2089} 2090 2091SDValue DAGCombiner::visitMULHU(SDNode *N) { 2092 SDValue N0 = N->getOperand(0); 2093 SDValue N1 = N->getOperand(1); 2094 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2095 EVT VT = N->getValueType(0); 2096 DebugLoc DL = N->getDebugLoc(); 2097 2098 // fold (mulhu x, 0) -> 0 2099 if (N1C && N1C->isNullValue()) 2100 return N1; 2101 // fold (mulhu x, 1) -> 0 2102 if (N1C && N1C->getAPIntValue() == 1) 2103 return DAG.getConstant(0, N0.getValueType()); 2104 // fold (mulhu x, undef) -> 0 2105 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2106 return DAG.getConstant(0, VT); 2107 2108 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2109 // plus a shift. 2110 if (VT.isSimple() && !VT.isVector()) { 2111 MVT Simple = VT.getSimpleVT(); 2112 unsigned SimpleSize = Simple.getSizeInBits(); 2113 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2114 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2115 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2116 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2117 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2118 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2119 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2120 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2121 } 2122 } 2123 2124 return SDValue(); 2125} 2126 2127/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2128/// compute two values. LoOp and HiOp give the opcodes for the two computations 2129/// that are being performed. Return true if a simplification was made. 2130/// 2131SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2132 unsigned HiOp) { 2133 // If the high half is not needed, just compute the low half. 2134 bool HiExists = N->hasAnyUseOfValue(1); 2135 if (!HiExists && 2136 (!LegalOperations || 2137 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2138 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2139 N->op_begin(), N->getNumOperands()); 2140 return CombineTo(N, Res, Res); 2141 } 2142 2143 // If the low half is not needed, just compute the high half. 2144 bool LoExists = N->hasAnyUseOfValue(0); 2145 if (!LoExists && 2146 (!LegalOperations || 2147 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2148 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2149 N->op_begin(), N->getNumOperands()); 2150 return CombineTo(N, Res, Res); 2151 } 2152 2153 // If both halves are used, return as it is. 2154 if (LoExists && HiExists) 2155 return SDValue(); 2156 2157 // If the two computed results can be simplified separately, separate them. 2158 if (LoExists) { 2159 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2160 N->op_begin(), N->getNumOperands()); 2161 AddToWorkList(Lo.getNode()); 2162 SDValue LoOpt = combine(Lo.getNode()); 2163 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2164 (!LegalOperations || 2165 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2166 return CombineTo(N, LoOpt, LoOpt); 2167 } 2168 2169 if (HiExists) { 2170 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2171 N->op_begin(), N->getNumOperands()); 2172 AddToWorkList(Hi.getNode()); 2173 SDValue HiOpt = combine(Hi.getNode()); 2174 if (HiOpt.getNode() && HiOpt != Hi && 2175 (!LegalOperations || 2176 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2177 return CombineTo(N, HiOpt, HiOpt); 2178 } 2179 2180 return SDValue(); 2181} 2182 2183SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2184 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2185 if (Res.getNode()) return Res; 2186 2187 EVT VT = N->getValueType(0); 2188 DebugLoc DL = N->getDebugLoc(); 2189 2190 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2191 // plus a shift. 2192 if (VT.isSimple() && !VT.isVector()) { 2193 MVT Simple = VT.getSimpleVT(); 2194 unsigned SimpleSize = Simple.getSizeInBits(); 2195 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2196 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2197 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2198 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2199 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2200 // Compute the high part as N1. 2201 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2202 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2203 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2204 // Compute the low part as N0. 2205 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2206 return CombineTo(N, Lo, Hi); 2207 } 2208 } 2209 2210 return SDValue(); 2211} 2212 2213SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2214 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2215 if (Res.getNode()) return Res; 2216 2217 EVT VT = N->getValueType(0); 2218 DebugLoc DL = N->getDebugLoc(); 2219 2220 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2221 // plus a shift. 2222 if (VT.isSimple() && !VT.isVector()) { 2223 MVT Simple = VT.getSimpleVT(); 2224 unsigned SimpleSize = Simple.getSizeInBits(); 2225 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2226 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2227 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2228 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2229 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2230 // Compute the high part as N1. 2231 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2232 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2233 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2234 // Compute the low part as N0. 2235 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2236 return CombineTo(N, Lo, Hi); 2237 } 2238 } 2239 2240 return SDValue(); 2241} 2242 2243SDValue DAGCombiner::visitSMULO(SDNode *N) { 2244 // (smulo x, 2) -> (saddo x, x) 2245 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2246 if (C2->getAPIntValue() == 2) 2247 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2248 N->getOperand(0), N->getOperand(0)); 2249 2250 return SDValue(); 2251} 2252 2253SDValue DAGCombiner::visitUMULO(SDNode *N) { 2254 // (umulo x, 2) -> (uaddo x, x) 2255 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2256 if (C2->getAPIntValue() == 2) 2257 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2258 N->getOperand(0), N->getOperand(0)); 2259 2260 return SDValue(); 2261} 2262 2263SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2264 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2265 if (Res.getNode()) return Res; 2266 2267 return SDValue(); 2268} 2269 2270SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2271 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2272 if (Res.getNode()) return Res; 2273 2274 return SDValue(); 2275} 2276 2277/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2278/// two operands of the same opcode, try to simplify it. 2279SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2280 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2281 EVT VT = N0.getValueType(); 2282 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2283 2284 // Bail early if none of these transforms apply. 2285 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2286 2287 // For each of OP in AND/OR/XOR: 2288 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2289 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2290 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2291 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2292 // 2293 // do not sink logical op inside of a vector extend, since it may combine 2294 // into a vsetcc. 2295 EVT Op0VT = N0.getOperand(0).getValueType(); 2296 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2297 N0.getOpcode() == ISD::SIGN_EXTEND || 2298 // Avoid infinite looping with PromoteIntBinOp. 2299 (N0.getOpcode() == ISD::ANY_EXTEND && 2300 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2301 (N0.getOpcode() == ISD::TRUNCATE && 2302 (!TLI.isZExtFree(VT, Op0VT) || 2303 !TLI.isTruncateFree(Op0VT, VT)) && 2304 TLI.isTypeLegal(Op0VT))) && 2305 !VT.isVector() && 2306 Op0VT == N1.getOperand(0).getValueType() && 2307 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2308 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2309 N0.getOperand(0).getValueType(), 2310 N0.getOperand(0), N1.getOperand(0)); 2311 AddToWorkList(ORNode.getNode()); 2312 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2313 } 2314 2315 // For each of OP in SHL/SRL/SRA/AND... 2316 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2317 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2318 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2319 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2320 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2321 N0.getOperand(1) == N1.getOperand(1)) { 2322 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2323 N0.getOperand(0).getValueType(), 2324 N0.getOperand(0), N1.getOperand(0)); 2325 AddToWorkList(ORNode.getNode()); 2326 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2327 ORNode, N0.getOperand(1)); 2328 } 2329 2330 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2331 // Only perform this optimization after type legalization and before 2332 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2333 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2334 // we don't want to undo this promotion. 2335 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2336 // on scalars. 2337 if ((N0.getOpcode() == ISD::BITCAST || N0.getOpcode() == ISD::SCALAR_TO_VECTOR) 2338 && Level == AfterLegalizeVectorOps) { 2339 SDValue In0 = N0.getOperand(0); 2340 SDValue In1 = N1.getOperand(0); 2341 EVT In0Ty = In0.getValueType(); 2342 EVT In1Ty = In1.getValueType(); 2343 // If both incoming values are integers, and the original types are the same. 2344 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2345 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), In0Ty, In0, In1); 2346 SDValue BC = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, Op); 2347 AddToWorkList(Op.getNode()); 2348 return BC; 2349 } 2350 } 2351 2352 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2353 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2354 // If both shuffles use the same mask, and both shuffle within a single 2355 // vector, then it is worthwhile to move the swizzle after the operation. 2356 // The type-legalizer generates this pattern when loading illegal 2357 // vector types from memory. In many cases this allows additional shuffle 2358 // optimizations. 2359 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2360 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2361 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2362 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2363 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2364 2365 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2366 "Inputs to shuffles are not the same type"); 2367 2368 unsigned NumElts = VT.getVectorNumElements(); 2369 2370 // Check that both shuffles use the same mask. The masks are known to be of 2371 // the same length because the result vector type is the same. 2372 bool SameMask = true; 2373 for (unsigned i = 0; i != NumElts; ++i) { 2374 int Idx0 = SVN0->getMaskElt(i); 2375 int Idx1 = SVN1->getMaskElt(i); 2376 if (Idx0 != Idx1) { 2377 SameMask = false; 2378 break; 2379 } 2380 } 2381 2382 if (SameMask) { 2383 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2384 N0.getOperand(0), N1.getOperand(0)); 2385 AddToWorkList(Op.getNode()); 2386 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2387 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2388 } 2389 } 2390 2391 return SDValue(); 2392} 2393 2394SDValue DAGCombiner::visitAND(SDNode *N) { 2395 SDValue N0 = N->getOperand(0); 2396 SDValue N1 = N->getOperand(1); 2397 SDValue LL, LR, RL, RR, CC0, CC1; 2398 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2400 EVT VT = N1.getValueType(); 2401 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2402 2403 // fold vector ops 2404 if (VT.isVector()) { 2405 SDValue FoldedVOp = SimplifyVBinOp(N); 2406 if (FoldedVOp.getNode()) return FoldedVOp; 2407 } 2408 2409 // fold (and x, undef) -> 0 2410 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2411 return DAG.getConstant(0, VT); 2412 // fold (and c1, c2) -> c1&c2 2413 if (N0C && N1C) 2414 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2415 // canonicalize constant to RHS 2416 if (N0C && !N1C) 2417 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2418 // fold (and x, -1) -> x 2419 if (N1C && N1C->isAllOnesValue()) 2420 return N0; 2421 // if (and x, c) is known to be zero, return 0 2422 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2423 APInt::getAllOnesValue(BitWidth))) 2424 return DAG.getConstant(0, VT); 2425 // reassociate and 2426 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2427 if (RAND.getNode() != 0) 2428 return RAND; 2429 // fold (and (or x, C), D) -> D if (C & D) == D 2430 if (N1C && N0.getOpcode() == ISD::OR) 2431 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2432 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2433 return N1; 2434 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2435 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2436 SDValue N0Op0 = N0.getOperand(0); 2437 APInt Mask = ~N1C->getAPIntValue(); 2438 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2439 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2440 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2441 N0.getValueType(), N0Op0); 2442 2443 // Replace uses of the AND with uses of the Zero extend node. 2444 CombineTo(N, Zext); 2445 2446 // We actually want to replace all uses of the any_extend with the 2447 // zero_extend, to avoid duplicating things. This will later cause this 2448 // AND to be folded. 2449 CombineTo(N0.getNode(), Zext); 2450 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2451 } 2452 } 2453 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2454 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2455 // already be zero by virtue of the width of the base type of the load. 2456 // 2457 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2458 // more cases. 2459 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2460 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2461 N0.getOpcode() == ISD::LOAD) { 2462 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2463 N0 : N0.getOperand(0) ); 2464 2465 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2466 // This can be a pure constant or a vector splat, in which case we treat the 2467 // vector as a scalar and use the splat value. 2468 APInt Constant = APInt::getNullValue(1); 2469 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2470 Constant = C->getAPIntValue(); 2471 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2472 APInt SplatValue, SplatUndef; 2473 unsigned SplatBitSize; 2474 bool HasAnyUndefs; 2475 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2476 SplatBitSize, HasAnyUndefs); 2477 if (IsSplat) { 2478 // Undef bits can contribute to a possible optimisation if set, so 2479 // set them. 2480 SplatValue |= SplatUndef; 2481 2482 // The splat value may be something like "0x00FFFFFF", which means 0 for 2483 // the first vector value and FF for the rest, repeating. We need a mask 2484 // that will apply equally to all members of the vector, so AND all the 2485 // lanes of the constant together. 2486 EVT VT = Vector->getValueType(0); 2487 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2488 Constant = APInt::getAllOnesValue(BitWidth); 2489 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i) 2490 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2491 } 2492 } 2493 2494 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2495 // actually legal and isn't going to get expanded, else this is a false 2496 // optimisation. 2497 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2498 Load->getMemoryVT()); 2499 2500 // Resize the constant to the same size as the original memory access before 2501 // extension. If it is still the AllOnesValue then this AND is completely 2502 // unneeded. 2503 Constant = 2504 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2505 2506 bool B; 2507 switch (Load->getExtensionType()) { 2508 default: B = false; break; 2509 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2510 case ISD::ZEXTLOAD: 2511 case ISD::NON_EXTLOAD: B = true; break; 2512 } 2513 2514 if (B && Constant.isAllOnesValue()) { 2515 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2516 // preserve semantics once we get rid of the AND. 2517 SDValue NewLoad(Load, 0); 2518 if (Load->getExtensionType() == ISD::EXTLOAD) { 2519 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2520 Load->getValueType(0), Load->getDebugLoc(), 2521 Load->getChain(), Load->getBasePtr(), 2522 Load->getOffset(), Load->getMemoryVT(), 2523 Load->getMemOperand()); 2524 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2525 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2526 } 2527 2528 // Fold the AND away, taking care not to fold to the old load node if we 2529 // replaced it. 2530 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2531 2532 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2533 } 2534 } 2535 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2536 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2537 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2538 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2539 2540 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2541 LL.getValueType().isInteger()) { 2542 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2543 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2544 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2545 LR.getValueType(), LL, RL); 2546 AddToWorkList(ORNode.getNode()); 2547 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2548 } 2549 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2550 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2551 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2552 LR.getValueType(), LL, RL); 2553 AddToWorkList(ANDNode.getNode()); 2554 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2555 } 2556 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2557 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2558 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2559 LR.getValueType(), LL, RL); 2560 AddToWorkList(ORNode.getNode()); 2561 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2562 } 2563 } 2564 // canonicalize equivalent to ll == rl 2565 if (LL == RR && LR == RL) { 2566 Op1 = ISD::getSetCCSwappedOperands(Op1); 2567 std::swap(RL, RR); 2568 } 2569 if (LL == RL && LR == RR) { 2570 bool isInteger = LL.getValueType().isInteger(); 2571 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2572 if (Result != ISD::SETCC_INVALID && 2573 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2574 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2575 LL, LR, Result); 2576 } 2577 } 2578 2579 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2580 if (N0.getOpcode() == N1.getOpcode()) { 2581 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2582 if (Tmp.getNode()) return Tmp; 2583 } 2584 2585 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2586 // fold (and (sra)) -> (and (srl)) when possible. 2587 if (!VT.isVector() && 2588 SimplifyDemandedBits(SDValue(N, 0))) 2589 return SDValue(N, 0); 2590 2591 // fold (zext_inreg (extload x)) -> (zextload x) 2592 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2593 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2594 EVT MemVT = LN0->getMemoryVT(); 2595 // If we zero all the possible extended bits, then we can turn this into 2596 // a zextload if we are running before legalize or the operation is legal. 2597 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2598 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2599 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2600 ((!LegalOperations && !LN0->isVolatile()) || 2601 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2602 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2603 LN0->getChain(), LN0->getBasePtr(), 2604 LN0->getPointerInfo(), MemVT, 2605 LN0->isVolatile(), LN0->isNonTemporal(), 2606 LN0->getAlignment()); 2607 AddToWorkList(N); 2608 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2609 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2610 } 2611 } 2612 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2613 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2614 N0.hasOneUse()) { 2615 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2616 EVT MemVT = LN0->getMemoryVT(); 2617 // If we zero all the possible extended bits, then we can turn this into 2618 // a zextload if we are running before legalize or the operation is legal. 2619 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2620 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2621 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2622 ((!LegalOperations && !LN0->isVolatile()) || 2623 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2624 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2625 LN0->getChain(), 2626 LN0->getBasePtr(), LN0->getPointerInfo(), 2627 MemVT, 2628 LN0->isVolatile(), LN0->isNonTemporal(), 2629 LN0->getAlignment()); 2630 AddToWorkList(N); 2631 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2632 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2633 } 2634 } 2635 2636 // fold (and (load x), 255) -> (zextload x, i8) 2637 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2638 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2639 if (N1C && (N0.getOpcode() == ISD::LOAD || 2640 (N0.getOpcode() == ISD::ANY_EXTEND && 2641 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2642 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2643 LoadSDNode *LN0 = HasAnyExt 2644 ? cast<LoadSDNode>(N0.getOperand(0)) 2645 : cast<LoadSDNode>(N0); 2646 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2647 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2648 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2649 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2650 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2651 EVT LoadedVT = LN0->getMemoryVT(); 2652 2653 if (ExtVT == LoadedVT && 2654 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2655 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2656 2657 SDValue NewLoad = 2658 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2659 LN0->getChain(), LN0->getBasePtr(), 2660 LN0->getPointerInfo(), 2661 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2662 LN0->getAlignment()); 2663 AddToWorkList(N); 2664 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2665 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2666 } 2667 2668 // Do not change the width of a volatile load. 2669 // Do not generate loads of non-round integer types since these can 2670 // be expensive (and would be wrong if the type is not byte sized). 2671 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2672 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2673 EVT PtrType = LN0->getOperand(1).getValueType(); 2674 2675 unsigned Alignment = LN0->getAlignment(); 2676 SDValue NewPtr = LN0->getBasePtr(); 2677 2678 // For big endian targets, we need to add an offset to the pointer 2679 // to load the correct bytes. For little endian systems, we merely 2680 // need to read fewer bytes from the same pointer. 2681 if (TLI.isBigEndian()) { 2682 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2683 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2684 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2685 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2686 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2687 Alignment = MinAlign(Alignment, PtrOff); 2688 } 2689 2690 AddToWorkList(NewPtr.getNode()); 2691 2692 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2693 SDValue Load = 2694 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2695 LN0->getChain(), NewPtr, 2696 LN0->getPointerInfo(), 2697 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2698 Alignment); 2699 AddToWorkList(N); 2700 CombineTo(LN0, Load, Load.getValue(1)); 2701 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2702 } 2703 } 2704 } 2705 } 2706 2707 return SDValue(); 2708} 2709 2710/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2711/// 2712SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2713 bool DemandHighBits) { 2714 if (!LegalOperations) 2715 return SDValue(); 2716 2717 EVT VT = N->getValueType(0); 2718 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2719 return SDValue(); 2720 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2721 return SDValue(); 2722 2723 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2724 bool LookPassAnd0 = false; 2725 bool LookPassAnd1 = false; 2726 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2727 std::swap(N0, N1); 2728 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2729 std::swap(N0, N1); 2730 if (N0.getOpcode() == ISD::AND) { 2731 if (!N0.getNode()->hasOneUse()) 2732 return SDValue(); 2733 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2734 if (!N01C || N01C->getZExtValue() != 0xFF00) 2735 return SDValue(); 2736 N0 = N0.getOperand(0); 2737 LookPassAnd0 = true; 2738 } 2739 2740 if (N1.getOpcode() == ISD::AND) { 2741 if (!N1.getNode()->hasOneUse()) 2742 return SDValue(); 2743 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2744 if (!N11C || N11C->getZExtValue() != 0xFF) 2745 return SDValue(); 2746 N1 = N1.getOperand(0); 2747 LookPassAnd1 = true; 2748 } 2749 2750 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2751 std::swap(N0, N1); 2752 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2753 return SDValue(); 2754 if (!N0.getNode()->hasOneUse() || 2755 !N1.getNode()->hasOneUse()) 2756 return SDValue(); 2757 2758 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2759 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2760 if (!N01C || !N11C) 2761 return SDValue(); 2762 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2763 return SDValue(); 2764 2765 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2766 SDValue N00 = N0->getOperand(0); 2767 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2768 if (!N00.getNode()->hasOneUse()) 2769 return SDValue(); 2770 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2771 if (!N001C || N001C->getZExtValue() != 0xFF) 2772 return SDValue(); 2773 N00 = N00.getOperand(0); 2774 LookPassAnd0 = true; 2775 } 2776 2777 SDValue N10 = N1->getOperand(0); 2778 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2779 if (!N10.getNode()->hasOneUse()) 2780 return SDValue(); 2781 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2782 if (!N101C || N101C->getZExtValue() != 0xFF00) 2783 return SDValue(); 2784 N10 = N10.getOperand(0); 2785 LookPassAnd1 = true; 2786 } 2787 2788 if (N00 != N10) 2789 return SDValue(); 2790 2791 // Make sure everything beyond the low halfword is zero since the SRL 16 2792 // will clear the top bits. 2793 unsigned OpSizeInBits = VT.getSizeInBits(); 2794 if (DemandHighBits && OpSizeInBits > 16 && 2795 (!LookPassAnd0 || !LookPassAnd1) && 2796 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2797 return SDValue(); 2798 2799 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2800 if (OpSizeInBits > 16) 2801 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2802 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2803 return Res; 2804} 2805 2806/// isBSwapHWordElement - Return true if the specified node is an element 2807/// that makes up a 32-bit packed halfword byteswap. i.e. 2808/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2809static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2810 if (!N.getNode()->hasOneUse()) 2811 return false; 2812 2813 unsigned Opc = N.getOpcode(); 2814 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2815 return false; 2816 2817 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2818 if (!N1C) 2819 return false; 2820 2821 unsigned Num; 2822 switch (N1C->getZExtValue()) { 2823 default: 2824 return false; 2825 case 0xFF: Num = 0; break; 2826 case 0xFF00: Num = 1; break; 2827 case 0xFF0000: Num = 2; break; 2828 case 0xFF000000: Num = 3; break; 2829 } 2830 2831 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2832 SDValue N0 = N.getOperand(0); 2833 if (Opc == ISD::AND) { 2834 if (Num == 0 || Num == 2) { 2835 // (x >> 8) & 0xff 2836 // (x >> 8) & 0xff0000 2837 if (N0.getOpcode() != ISD::SRL) 2838 return false; 2839 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2840 if (!C || C->getZExtValue() != 8) 2841 return false; 2842 } else { 2843 // (x << 8) & 0xff00 2844 // (x << 8) & 0xff000000 2845 if (N0.getOpcode() != ISD::SHL) 2846 return false; 2847 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2848 if (!C || C->getZExtValue() != 8) 2849 return false; 2850 } 2851 } else if (Opc == ISD::SHL) { 2852 // (x & 0xff) << 8 2853 // (x & 0xff0000) << 8 2854 if (Num != 0 && Num != 2) 2855 return false; 2856 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2857 if (!C || C->getZExtValue() != 8) 2858 return false; 2859 } else { // Opc == ISD::SRL 2860 // (x & 0xff00) >> 8 2861 // (x & 0xff000000) >> 8 2862 if (Num != 1 && Num != 3) 2863 return false; 2864 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2865 if (!C || C->getZExtValue() != 8) 2866 return false; 2867 } 2868 2869 if (Parts[Num]) 2870 return false; 2871 2872 Parts[Num] = N0.getOperand(0).getNode(); 2873 return true; 2874} 2875 2876/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2877/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2878/// => (rotl (bswap x), 16) 2879SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2880 if (!LegalOperations) 2881 return SDValue(); 2882 2883 EVT VT = N->getValueType(0); 2884 if (VT != MVT::i32) 2885 return SDValue(); 2886 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2887 return SDValue(); 2888 2889 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2890 // Look for either 2891 // (or (or (and), (and)), (or (and), (and))) 2892 // (or (or (or (and), (and)), (and)), (and)) 2893 if (N0.getOpcode() != ISD::OR) 2894 return SDValue(); 2895 SDValue N00 = N0.getOperand(0); 2896 SDValue N01 = N0.getOperand(1); 2897 2898 if (N1.getOpcode() == ISD::OR) { 2899 // (or (or (and), (and)), (or (and), (and))) 2900 SDValue N000 = N00.getOperand(0); 2901 if (!isBSwapHWordElement(N000, Parts)) 2902 return SDValue(); 2903 2904 SDValue N001 = N00.getOperand(1); 2905 if (!isBSwapHWordElement(N001, Parts)) 2906 return SDValue(); 2907 SDValue N010 = N01.getOperand(0); 2908 if (!isBSwapHWordElement(N010, Parts)) 2909 return SDValue(); 2910 SDValue N011 = N01.getOperand(1); 2911 if (!isBSwapHWordElement(N011, Parts)) 2912 return SDValue(); 2913 } else { 2914 // (or (or (or (and), (and)), (and)), (and)) 2915 if (!isBSwapHWordElement(N1, Parts)) 2916 return SDValue(); 2917 if (!isBSwapHWordElement(N01, Parts)) 2918 return SDValue(); 2919 if (N00.getOpcode() != ISD::OR) 2920 return SDValue(); 2921 SDValue N000 = N00.getOperand(0); 2922 if (!isBSwapHWordElement(N000, Parts)) 2923 return SDValue(); 2924 SDValue N001 = N00.getOperand(1); 2925 if (!isBSwapHWordElement(N001, Parts)) 2926 return SDValue(); 2927 } 2928 2929 // Make sure the parts are all coming from the same node. 2930 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2931 return SDValue(); 2932 2933 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2934 SDValue(Parts[0],0)); 2935 2936 // Result of the bswap should be rotated by 16. If it's not legal, than 2937 // do (x << 16) | (x >> 16). 2938 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2939 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2940 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2941 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2942 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 2943 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 2944 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 2945 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 2946} 2947 2948SDValue DAGCombiner::visitOR(SDNode *N) { 2949 SDValue N0 = N->getOperand(0); 2950 SDValue N1 = N->getOperand(1); 2951 SDValue LL, LR, RL, RR, CC0, CC1; 2952 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2953 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2954 EVT VT = N1.getValueType(); 2955 2956 // fold vector ops 2957 if (VT.isVector()) { 2958 SDValue FoldedVOp = SimplifyVBinOp(N); 2959 if (FoldedVOp.getNode()) return FoldedVOp; 2960 } 2961 2962 // fold (or x, undef) -> -1 2963 if (!LegalOperations && 2964 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2965 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2966 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2967 } 2968 // fold (or c1, c2) -> c1|c2 2969 if (N0C && N1C) 2970 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2971 // canonicalize constant to RHS 2972 if (N0C && !N1C) 2973 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2974 // fold (or x, 0) -> x 2975 if (N1C && N1C->isNullValue()) 2976 return N0; 2977 // fold (or x, -1) -> -1 2978 if (N1C && N1C->isAllOnesValue()) 2979 return N1; 2980 // fold (or x, c) -> c iff (x & ~c) == 0 2981 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2982 return N1; 2983 2984 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 2985 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 2986 if (BSwap.getNode() != 0) 2987 return BSwap; 2988 BSwap = MatchBSwapHWordLow(N, N0, N1); 2989 if (BSwap.getNode() != 0) 2990 return BSwap; 2991 2992 // reassociate or 2993 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2994 if (ROR.getNode() != 0) 2995 return ROR; 2996 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2997 // iff (c1 & c2) == 0. 2998 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2999 isa<ConstantSDNode>(N0.getOperand(1))) { 3000 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3001 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3002 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3003 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3004 N0.getOperand(0), N1), 3005 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3006 } 3007 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3008 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3009 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3010 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3011 3012 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3013 LL.getValueType().isInteger()) { 3014 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3015 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3016 if (cast<ConstantSDNode>(LR)->isNullValue() && 3017 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3018 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3019 LR.getValueType(), LL, RL); 3020 AddToWorkList(ORNode.getNode()); 3021 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3022 } 3023 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3024 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3025 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3026 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3027 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3028 LR.getValueType(), LL, RL); 3029 AddToWorkList(ANDNode.getNode()); 3030 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3031 } 3032 } 3033 // canonicalize equivalent to ll == rl 3034 if (LL == RR && LR == RL) { 3035 Op1 = ISD::getSetCCSwappedOperands(Op1); 3036 std::swap(RL, RR); 3037 } 3038 if (LL == RL && LR == RR) { 3039 bool isInteger = LL.getValueType().isInteger(); 3040 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3041 if (Result != ISD::SETCC_INVALID && 3042 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3043 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3044 LL, LR, Result); 3045 } 3046 } 3047 3048 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3049 if (N0.getOpcode() == N1.getOpcode()) { 3050 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3051 if (Tmp.getNode()) return Tmp; 3052 } 3053 3054 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3055 if (N0.getOpcode() == ISD::AND && 3056 N1.getOpcode() == ISD::AND && 3057 N0.getOperand(1).getOpcode() == ISD::Constant && 3058 N1.getOperand(1).getOpcode() == ISD::Constant && 3059 // Don't increase # computations. 3060 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3061 // We can only do this xform if we know that bits from X that are set in C2 3062 // but not in C1 are already zero. Likewise for Y. 3063 const APInt &LHSMask = 3064 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3065 const APInt &RHSMask = 3066 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3067 3068 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3069 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3070 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3071 N0.getOperand(0), N1.getOperand(0)); 3072 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3073 DAG.getConstant(LHSMask | RHSMask, VT)); 3074 } 3075 } 3076 3077 // See if this is some rotate idiom. 3078 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3079 return SDValue(Rot, 0); 3080 3081 // Simplify the operands using demanded-bits information. 3082 if (!VT.isVector() && 3083 SimplifyDemandedBits(SDValue(N, 0))) 3084 return SDValue(N, 0); 3085 3086 return SDValue(); 3087} 3088 3089/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3090static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3091 if (Op.getOpcode() == ISD::AND) { 3092 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3093 Mask = Op.getOperand(1); 3094 Op = Op.getOperand(0); 3095 } else { 3096 return false; 3097 } 3098 } 3099 3100 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3101 Shift = Op; 3102 return true; 3103 } 3104 3105 return false; 3106} 3107 3108// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3109// idioms for rotate, and if the target supports rotation instructions, generate 3110// a rot[lr]. 3111SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3112 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3113 EVT VT = LHS.getValueType(); 3114 if (!TLI.isTypeLegal(VT)) return 0; 3115 3116 // The target must have at least one rotate flavor. 3117 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3118 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3119 if (!HasROTL && !HasROTR) return 0; 3120 3121 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3122 SDValue LHSShift; // The shift. 3123 SDValue LHSMask; // AND value if any. 3124 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3125 return 0; // Not part of a rotate. 3126 3127 SDValue RHSShift; // The shift. 3128 SDValue RHSMask; // AND value if any. 3129 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3130 return 0; // Not part of a rotate. 3131 3132 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3133 return 0; // Not shifting the same value. 3134 3135 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3136 return 0; // Shifts must disagree. 3137 3138 // Canonicalize shl to left side in a shl/srl pair. 3139 if (RHSShift.getOpcode() == ISD::SHL) { 3140 std::swap(LHS, RHS); 3141 std::swap(LHSShift, RHSShift); 3142 std::swap(LHSMask , RHSMask ); 3143 } 3144 3145 unsigned OpSizeInBits = VT.getSizeInBits(); 3146 SDValue LHSShiftArg = LHSShift.getOperand(0); 3147 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3148 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3149 3150 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3151 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3152 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3153 RHSShiftAmt.getOpcode() == ISD::Constant) { 3154 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3155 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3156 if ((LShVal + RShVal) != OpSizeInBits) 3157 return 0; 3158 3159 SDValue Rot; 3160 if (HasROTL) 3161 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 3162 else 3163 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 3164 3165 // If there is an AND of either shifted operand, apply it to the result. 3166 if (LHSMask.getNode() || RHSMask.getNode()) { 3167 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3168 3169 if (LHSMask.getNode()) { 3170 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3171 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3172 } 3173 if (RHSMask.getNode()) { 3174 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3175 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3176 } 3177 3178 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3179 } 3180 3181 return Rot.getNode(); 3182 } 3183 3184 // If there is a mask here, and we have a variable shift, we can't be sure 3185 // that we're masking out the right stuff. 3186 if (LHSMask.getNode() || RHSMask.getNode()) 3187 return 0; 3188 3189 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3190 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3191 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3192 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3193 if (ConstantSDNode *SUBC = 3194 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3195 if (SUBC->getAPIntValue() == OpSizeInBits) { 3196 if (HasROTL) 3197 return DAG.getNode(ISD::ROTL, DL, VT, 3198 LHSShiftArg, LHSShiftAmt).getNode(); 3199 else 3200 return DAG.getNode(ISD::ROTR, DL, VT, 3201 LHSShiftArg, RHSShiftAmt).getNode(); 3202 } 3203 } 3204 } 3205 3206 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3207 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3208 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3209 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3210 if (ConstantSDNode *SUBC = 3211 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3212 if (SUBC->getAPIntValue() == OpSizeInBits) { 3213 if (HasROTR) 3214 return DAG.getNode(ISD::ROTR, DL, VT, 3215 LHSShiftArg, RHSShiftAmt).getNode(); 3216 else 3217 return DAG.getNode(ISD::ROTL, DL, VT, 3218 LHSShiftArg, LHSShiftAmt).getNode(); 3219 } 3220 } 3221 } 3222 3223 // Look for sign/zext/any-extended or truncate cases: 3224 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3225 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3226 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3227 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3228 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3229 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3230 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3231 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3232 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3233 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3234 if (RExtOp0.getOpcode() == ISD::SUB && 3235 RExtOp0.getOperand(1) == LExtOp0) { 3236 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3237 // (rotl x, y) 3238 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3239 // (rotr x, (sub 32, y)) 3240 if (ConstantSDNode *SUBC = 3241 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3242 if (SUBC->getAPIntValue() == OpSizeInBits) { 3243 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3244 LHSShiftArg, 3245 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3246 } 3247 } 3248 } else if (LExtOp0.getOpcode() == ISD::SUB && 3249 RExtOp0 == LExtOp0.getOperand(1)) { 3250 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3251 // (rotr x, y) 3252 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3253 // (rotl x, (sub 32, y)) 3254 if (ConstantSDNode *SUBC = 3255 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3256 if (SUBC->getAPIntValue() == OpSizeInBits) { 3257 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3258 LHSShiftArg, 3259 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3260 } 3261 } 3262 } 3263 } 3264 3265 return 0; 3266} 3267 3268SDValue DAGCombiner::visitXOR(SDNode *N) { 3269 SDValue N0 = N->getOperand(0); 3270 SDValue N1 = N->getOperand(1); 3271 SDValue LHS, RHS, CC; 3272 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3273 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3274 EVT VT = N0.getValueType(); 3275 3276 // fold vector ops 3277 if (VT.isVector()) { 3278 SDValue FoldedVOp = SimplifyVBinOp(N); 3279 if (FoldedVOp.getNode()) return FoldedVOp; 3280 } 3281 3282 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3283 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3284 return DAG.getConstant(0, VT); 3285 // fold (xor x, undef) -> undef 3286 if (N0.getOpcode() == ISD::UNDEF) 3287 return N0; 3288 if (N1.getOpcode() == ISD::UNDEF) 3289 return N1; 3290 // fold (xor c1, c2) -> c1^c2 3291 if (N0C && N1C) 3292 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3293 // canonicalize constant to RHS 3294 if (N0C && !N1C) 3295 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3296 // fold (xor x, 0) -> x 3297 if (N1C && N1C->isNullValue()) 3298 return N0; 3299 // reassociate xor 3300 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3301 if (RXOR.getNode() != 0) 3302 return RXOR; 3303 3304 // fold !(x cc y) -> (x !cc y) 3305 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3306 bool isInt = LHS.getValueType().isInteger(); 3307 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3308 isInt); 3309 3310 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3311 switch (N0.getOpcode()) { 3312 default: 3313 llvm_unreachable("Unhandled SetCC Equivalent!"); 3314 case ISD::SETCC: 3315 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3316 case ISD::SELECT_CC: 3317 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3318 N0.getOperand(3), NotCC); 3319 } 3320 } 3321 } 3322 3323 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3324 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3325 N0.getNode()->hasOneUse() && 3326 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3327 SDValue V = N0.getOperand(0); 3328 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3329 DAG.getConstant(1, V.getValueType())); 3330 AddToWorkList(V.getNode()); 3331 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3332 } 3333 3334 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3335 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3336 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3337 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3338 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3339 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3340 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3341 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3342 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3343 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3344 } 3345 } 3346 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3347 if (N1C && N1C->isAllOnesValue() && 3348 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3349 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3350 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3351 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3352 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3353 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3354 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3355 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3356 } 3357 } 3358 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3359 if (N1C && N0.getOpcode() == ISD::XOR) { 3360 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3361 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3362 if (N00C) 3363 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3364 DAG.getConstant(N1C->getAPIntValue() ^ 3365 N00C->getAPIntValue(), VT)); 3366 if (N01C) 3367 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3368 DAG.getConstant(N1C->getAPIntValue() ^ 3369 N01C->getAPIntValue(), VT)); 3370 } 3371 // fold (xor x, x) -> 0 3372 if (N0 == N1) 3373 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3374 3375 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3376 if (N0.getOpcode() == N1.getOpcode()) { 3377 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3378 if (Tmp.getNode()) return Tmp; 3379 } 3380 3381 // Simplify the expression using non-local knowledge. 3382 if (!VT.isVector() && 3383 SimplifyDemandedBits(SDValue(N, 0))) 3384 return SDValue(N, 0); 3385 3386 return SDValue(); 3387} 3388 3389/// visitShiftByConstant - Handle transforms common to the three shifts, when 3390/// the shift amount is a constant. 3391SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3392 SDNode *LHS = N->getOperand(0).getNode(); 3393 if (!LHS->hasOneUse()) return SDValue(); 3394 3395 // We want to pull some binops through shifts, so that we have (and (shift)) 3396 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3397 // thing happens with address calculations, so it's important to canonicalize 3398 // it. 3399 bool HighBitSet = false; // Can we transform this if the high bit is set? 3400 3401 switch (LHS->getOpcode()) { 3402 default: return SDValue(); 3403 case ISD::OR: 3404 case ISD::XOR: 3405 HighBitSet = false; // We can only transform sra if the high bit is clear. 3406 break; 3407 case ISD::AND: 3408 HighBitSet = true; // We can only transform sra if the high bit is set. 3409 break; 3410 case ISD::ADD: 3411 if (N->getOpcode() != ISD::SHL) 3412 return SDValue(); // only shl(add) not sr[al](add). 3413 HighBitSet = false; // We can only transform sra if the high bit is clear. 3414 break; 3415 } 3416 3417 // We require the RHS of the binop to be a constant as well. 3418 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3419 if (!BinOpCst) return SDValue(); 3420 3421 // FIXME: disable this unless the input to the binop is a shift by a constant. 3422 // If it is not a shift, it pessimizes some common cases like: 3423 // 3424 // void foo(int *X, int i) { X[i & 1235] = 1; } 3425 // int bar(int *X, int i) { return X[i & 255]; } 3426 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3427 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3428 BinOpLHSVal->getOpcode() != ISD::SRA && 3429 BinOpLHSVal->getOpcode() != ISD::SRL) || 3430 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3431 return SDValue(); 3432 3433 EVT VT = N->getValueType(0); 3434 3435 // If this is a signed shift right, and the high bit is modified by the 3436 // logical operation, do not perform the transformation. The highBitSet 3437 // boolean indicates the value of the high bit of the constant which would 3438 // cause it to be modified for this operation. 3439 if (N->getOpcode() == ISD::SRA) { 3440 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3441 if (BinOpRHSSignSet != HighBitSet) 3442 return SDValue(); 3443 } 3444 3445 // Fold the constants, shifting the binop RHS by the shift amount. 3446 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3447 N->getValueType(0), 3448 LHS->getOperand(1), N->getOperand(1)); 3449 3450 // Create the new shift. 3451 SDValue NewShift = DAG.getNode(N->getOpcode(), 3452 LHS->getOperand(0).getDebugLoc(), 3453 VT, LHS->getOperand(0), N->getOperand(1)); 3454 3455 // Create the new binop. 3456 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3457} 3458 3459SDValue DAGCombiner::visitSHL(SDNode *N) { 3460 SDValue N0 = N->getOperand(0); 3461 SDValue N1 = N->getOperand(1); 3462 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3463 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3464 EVT VT = N0.getValueType(); 3465 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3466 3467 // fold (shl c1, c2) -> c1<<c2 3468 if (N0C && N1C) 3469 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3470 // fold (shl 0, x) -> 0 3471 if (N0C && N0C->isNullValue()) 3472 return N0; 3473 // fold (shl x, c >= size(x)) -> undef 3474 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3475 return DAG.getUNDEF(VT); 3476 // fold (shl x, 0) -> x 3477 if (N1C && N1C->isNullValue()) 3478 return N0; 3479 // fold (shl undef, x) -> 0 3480 if (N0.getOpcode() == ISD::UNDEF) 3481 return DAG.getConstant(0, VT); 3482 // if (shl x, c) is known to be zero, return 0 3483 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3484 APInt::getAllOnesValue(OpSizeInBits))) 3485 return DAG.getConstant(0, VT); 3486 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3487 if (N1.getOpcode() == ISD::TRUNCATE && 3488 N1.getOperand(0).getOpcode() == ISD::AND && 3489 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3490 SDValue N101 = N1.getOperand(0).getOperand(1); 3491 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3492 EVT TruncVT = N1.getValueType(); 3493 SDValue N100 = N1.getOperand(0).getOperand(0); 3494 APInt TruncC = N101C->getAPIntValue(); 3495 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3496 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3497 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3498 DAG.getNode(ISD::TRUNCATE, 3499 N->getDebugLoc(), 3500 TruncVT, N100), 3501 DAG.getConstant(TruncC, TruncVT))); 3502 } 3503 } 3504 3505 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3506 return SDValue(N, 0); 3507 3508 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3509 if (N1C && N0.getOpcode() == ISD::SHL && 3510 N0.getOperand(1).getOpcode() == ISD::Constant) { 3511 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3512 uint64_t c2 = N1C->getZExtValue(); 3513 if (c1 + c2 >= OpSizeInBits) 3514 return DAG.getConstant(0, VT); 3515 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3516 DAG.getConstant(c1 + c2, N1.getValueType())); 3517 } 3518 3519 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3520 // For this to be valid, the second form must not preserve any of the bits 3521 // that are shifted out by the inner shift in the first form. This means 3522 // the outer shift size must be >= the number of bits added by the ext. 3523 // As a corollary, we don't care what kind of ext it is. 3524 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3525 N0.getOpcode() == ISD::ANY_EXTEND || 3526 N0.getOpcode() == ISD::SIGN_EXTEND) && 3527 N0.getOperand(0).getOpcode() == ISD::SHL && 3528 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3529 uint64_t c1 = 3530 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3531 uint64_t c2 = N1C->getZExtValue(); 3532 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3533 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3534 if (c2 >= OpSizeInBits - InnerShiftSize) { 3535 if (c1 + c2 >= OpSizeInBits) 3536 return DAG.getConstant(0, VT); 3537 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3538 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3539 N0.getOperand(0)->getOperand(0)), 3540 DAG.getConstant(c1 + c2, N1.getValueType())); 3541 } 3542 } 3543 3544 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3545 // (and (srl x, (sub c1, c2), MASK) 3546 // Only fold this if the inner shift has no other uses -- if it does, folding 3547 // this will increase the total number of instructions. 3548 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3549 N0.getOperand(1).getOpcode() == ISD::Constant) { 3550 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3551 if (c1 < VT.getSizeInBits()) { 3552 uint64_t c2 = N1C->getZExtValue(); 3553 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3554 VT.getSizeInBits() - c1); 3555 SDValue Shift; 3556 if (c2 > c1) { 3557 Mask = Mask.shl(c2-c1); 3558 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3559 DAG.getConstant(c2-c1, N1.getValueType())); 3560 } else { 3561 Mask = Mask.lshr(c1-c2); 3562 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3563 DAG.getConstant(c1-c2, N1.getValueType())); 3564 } 3565 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3566 DAG.getConstant(Mask, VT)); 3567 } 3568 } 3569 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3570 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3571 SDValue HiBitsMask = 3572 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3573 VT.getSizeInBits() - 3574 N1C->getZExtValue()), 3575 VT); 3576 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3577 HiBitsMask); 3578 } 3579 3580 if (N1C) { 3581 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3582 if (NewSHL.getNode()) 3583 return NewSHL; 3584 } 3585 3586 return SDValue(); 3587} 3588 3589SDValue DAGCombiner::visitSRA(SDNode *N) { 3590 SDValue N0 = N->getOperand(0); 3591 SDValue N1 = N->getOperand(1); 3592 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3593 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3594 EVT VT = N0.getValueType(); 3595 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3596 3597 // fold (sra c1, c2) -> (sra c1, c2) 3598 if (N0C && N1C) 3599 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3600 // fold (sra 0, x) -> 0 3601 if (N0C && N0C->isNullValue()) 3602 return N0; 3603 // fold (sra -1, x) -> -1 3604 if (N0C && N0C->isAllOnesValue()) 3605 return N0; 3606 // fold (sra x, (setge c, size(x))) -> undef 3607 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3608 return DAG.getUNDEF(VT); 3609 // fold (sra x, 0) -> x 3610 if (N1C && N1C->isNullValue()) 3611 return N0; 3612 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3613 // sext_inreg. 3614 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3615 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3616 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3617 if (VT.isVector()) 3618 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3619 ExtVT, VT.getVectorNumElements()); 3620 if ((!LegalOperations || 3621 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3622 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3623 N0.getOperand(0), DAG.getValueType(ExtVT)); 3624 } 3625 3626 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3627 if (N1C && N0.getOpcode() == ISD::SRA) { 3628 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3629 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3630 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3631 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3632 DAG.getConstant(Sum, N1C->getValueType(0))); 3633 } 3634 } 3635 3636 // fold (sra (shl X, m), (sub result_size, n)) 3637 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3638 // result_size - n != m. 3639 // If truncate is free for the target sext(shl) is likely to result in better 3640 // code. 3641 if (N0.getOpcode() == ISD::SHL) { 3642 // Get the two constanst of the shifts, CN0 = m, CN = n. 3643 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3644 if (N01C && N1C) { 3645 // Determine what the truncate's result bitsize and type would be. 3646 EVT TruncVT = 3647 EVT::getIntegerVT(*DAG.getContext(), 3648 OpSizeInBits - N1C->getZExtValue()); 3649 // Determine the residual right-shift amount. 3650 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3651 3652 // If the shift is not a no-op (in which case this should be just a sign 3653 // extend already), the truncated to type is legal, sign_extend is legal 3654 // on that type, and the truncate to that type is both legal and free, 3655 // perform the transform. 3656 if ((ShiftAmt > 0) && 3657 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3658 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3659 TLI.isTruncateFree(VT, TruncVT)) { 3660 3661 SDValue Amt = DAG.getConstant(ShiftAmt, 3662 getShiftAmountTy(N0.getOperand(0).getValueType())); 3663 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3664 N0.getOperand(0), Amt); 3665 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3666 Shift); 3667 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3668 N->getValueType(0), Trunc); 3669 } 3670 } 3671 } 3672 3673 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3674 if (N1.getOpcode() == ISD::TRUNCATE && 3675 N1.getOperand(0).getOpcode() == ISD::AND && 3676 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3677 SDValue N101 = N1.getOperand(0).getOperand(1); 3678 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3679 EVT TruncVT = N1.getValueType(); 3680 SDValue N100 = N1.getOperand(0).getOperand(0); 3681 APInt TruncC = N101C->getAPIntValue(); 3682 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3683 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3684 DAG.getNode(ISD::AND, N->getDebugLoc(), 3685 TruncVT, 3686 DAG.getNode(ISD::TRUNCATE, 3687 N->getDebugLoc(), 3688 TruncVT, N100), 3689 DAG.getConstant(TruncC, TruncVT))); 3690 } 3691 } 3692 3693 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3694 // if c1 is equal to the number of bits the trunc removes 3695 if (N0.getOpcode() == ISD::TRUNCATE && 3696 (N0.getOperand(0).getOpcode() == ISD::SRL || 3697 N0.getOperand(0).getOpcode() == ISD::SRA) && 3698 N0.getOperand(0).hasOneUse() && 3699 N0.getOperand(0).getOperand(1).hasOneUse() && 3700 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3701 EVT LargeVT = N0.getOperand(0).getValueType(); 3702 ConstantSDNode *LargeShiftAmt = 3703 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3704 3705 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3706 LargeShiftAmt->getZExtValue()) { 3707 SDValue Amt = 3708 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3709 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3710 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3711 N0.getOperand(0).getOperand(0), Amt); 3712 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3713 } 3714 } 3715 3716 // Simplify, based on bits shifted out of the LHS. 3717 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3718 return SDValue(N, 0); 3719 3720 3721 // If the sign bit is known to be zero, switch this to a SRL. 3722 if (DAG.SignBitIsZero(N0)) 3723 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3724 3725 if (N1C) { 3726 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3727 if (NewSRA.getNode()) 3728 return NewSRA; 3729 } 3730 3731 return SDValue(); 3732} 3733 3734SDValue DAGCombiner::visitSRL(SDNode *N) { 3735 SDValue N0 = N->getOperand(0); 3736 SDValue N1 = N->getOperand(1); 3737 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3738 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3739 EVT VT = N0.getValueType(); 3740 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3741 3742 // fold (srl c1, c2) -> c1 >>u c2 3743 if (N0C && N1C) 3744 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3745 // fold (srl 0, x) -> 0 3746 if (N0C && N0C->isNullValue()) 3747 return N0; 3748 // fold (srl x, c >= size(x)) -> undef 3749 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3750 return DAG.getUNDEF(VT); 3751 // fold (srl x, 0) -> x 3752 if (N1C && N1C->isNullValue()) 3753 return N0; 3754 // if (srl x, c) is known to be zero, return 0 3755 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3756 APInt::getAllOnesValue(OpSizeInBits))) 3757 return DAG.getConstant(0, VT); 3758 3759 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3760 if (N1C && N0.getOpcode() == ISD::SRL && 3761 N0.getOperand(1).getOpcode() == ISD::Constant) { 3762 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3763 uint64_t c2 = N1C->getZExtValue(); 3764 if (c1 + c2 >= OpSizeInBits) 3765 return DAG.getConstant(0, VT); 3766 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3767 DAG.getConstant(c1 + c2, N1.getValueType())); 3768 } 3769 3770 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3771 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3772 N0.getOperand(0).getOpcode() == ISD::SRL && 3773 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3774 uint64_t c1 = 3775 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3776 uint64_t c2 = N1C->getZExtValue(); 3777 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3778 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3779 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3780 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3781 if (c1 + OpSizeInBits == InnerShiftSize) { 3782 if (c1 + c2 >= InnerShiftSize) 3783 return DAG.getConstant(0, VT); 3784 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3785 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3786 N0.getOperand(0)->getOperand(0), 3787 DAG.getConstant(c1 + c2, ShiftCountVT))); 3788 } 3789 } 3790 3791 // fold (srl (shl x, c), c) -> (and x, cst2) 3792 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3793 N0.getValueSizeInBits() <= 64) { 3794 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3795 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3796 DAG.getConstant(~0ULL >> ShAmt, VT)); 3797 } 3798 3799 3800 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3801 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3802 // Shifting in all undef bits? 3803 EVT SmallVT = N0.getOperand(0).getValueType(); 3804 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3805 return DAG.getUNDEF(VT); 3806 3807 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3808 uint64_t ShiftAmt = N1C->getZExtValue(); 3809 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3810 N0.getOperand(0), 3811 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3812 AddToWorkList(SmallShift.getNode()); 3813 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3814 } 3815 } 3816 3817 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3818 // bit, which is unmodified by sra. 3819 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3820 if (N0.getOpcode() == ISD::SRA) 3821 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3822 } 3823 3824 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3825 if (N1C && N0.getOpcode() == ISD::CTLZ && 3826 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3827 APInt KnownZero, KnownOne; 3828 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3829 3830 // If any of the input bits are KnownOne, then the input couldn't be all 3831 // zeros, thus the result of the srl will always be zero. 3832 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3833 3834 // If all of the bits input the to ctlz node are known to be zero, then 3835 // the result of the ctlz is "32" and the result of the shift is one. 3836 APInt UnknownBits = ~KnownZero; 3837 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3838 3839 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3840 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3841 // Okay, we know that only that the single bit specified by UnknownBits 3842 // could be set on input to the CTLZ node. If this bit is set, the SRL 3843 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3844 // to an SRL/XOR pair, which is likely to simplify more. 3845 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3846 SDValue Op = N0.getOperand(0); 3847 3848 if (ShAmt) { 3849 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3850 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3851 AddToWorkList(Op.getNode()); 3852 } 3853 3854 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3855 Op, DAG.getConstant(1, VT)); 3856 } 3857 } 3858 3859 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3860 if (N1.getOpcode() == ISD::TRUNCATE && 3861 N1.getOperand(0).getOpcode() == ISD::AND && 3862 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3863 SDValue N101 = N1.getOperand(0).getOperand(1); 3864 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3865 EVT TruncVT = N1.getValueType(); 3866 SDValue N100 = N1.getOperand(0).getOperand(0); 3867 APInt TruncC = N101C->getAPIntValue(); 3868 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3869 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3870 DAG.getNode(ISD::AND, N->getDebugLoc(), 3871 TruncVT, 3872 DAG.getNode(ISD::TRUNCATE, 3873 N->getDebugLoc(), 3874 TruncVT, N100), 3875 DAG.getConstant(TruncC, TruncVT))); 3876 } 3877 } 3878 3879 // fold operands of srl based on knowledge that the low bits are not 3880 // demanded. 3881 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3882 return SDValue(N, 0); 3883 3884 if (N1C) { 3885 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3886 if (NewSRL.getNode()) 3887 return NewSRL; 3888 } 3889 3890 // Attempt to convert a srl of a load into a narrower zero-extending load. 3891 SDValue NarrowLoad = ReduceLoadWidth(N); 3892 if (NarrowLoad.getNode()) 3893 return NarrowLoad; 3894 3895 // Here is a common situation. We want to optimize: 3896 // 3897 // %a = ... 3898 // %b = and i32 %a, 2 3899 // %c = srl i32 %b, 1 3900 // brcond i32 %c ... 3901 // 3902 // into 3903 // 3904 // %a = ... 3905 // %b = and %a, 2 3906 // %c = setcc eq %b, 0 3907 // brcond %c ... 3908 // 3909 // However when after the source operand of SRL is optimized into AND, the SRL 3910 // itself may not be optimized further. Look for it and add the BRCOND into 3911 // the worklist. 3912 if (N->hasOneUse()) { 3913 SDNode *Use = *N->use_begin(); 3914 if (Use->getOpcode() == ISD::BRCOND) 3915 AddToWorkList(Use); 3916 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3917 // Also look pass the truncate. 3918 Use = *Use->use_begin(); 3919 if (Use->getOpcode() == ISD::BRCOND) 3920 AddToWorkList(Use); 3921 } 3922 } 3923 3924 return SDValue(); 3925} 3926 3927SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3928 SDValue N0 = N->getOperand(0); 3929 EVT VT = N->getValueType(0); 3930 3931 // fold (ctlz c1) -> c2 3932 if (isa<ConstantSDNode>(N0)) 3933 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3934 return SDValue(); 3935} 3936 3937SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3938 SDValue N0 = N->getOperand(0); 3939 EVT VT = N->getValueType(0); 3940 3941 // fold (ctlz_zero_undef c1) -> c2 3942 if (isa<ConstantSDNode>(N0)) 3943 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3944 return SDValue(); 3945} 3946 3947SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3948 SDValue N0 = N->getOperand(0); 3949 EVT VT = N->getValueType(0); 3950 3951 // fold (cttz c1) -> c2 3952 if (isa<ConstantSDNode>(N0)) 3953 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3954 return SDValue(); 3955} 3956 3957SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 3958 SDValue N0 = N->getOperand(0); 3959 EVT VT = N->getValueType(0); 3960 3961 // fold (cttz_zero_undef c1) -> c2 3962 if (isa<ConstantSDNode>(N0)) 3963 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3964 return SDValue(); 3965} 3966 3967SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3968 SDValue N0 = N->getOperand(0); 3969 EVT VT = N->getValueType(0); 3970 3971 // fold (ctpop c1) -> c2 3972 if (isa<ConstantSDNode>(N0)) 3973 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3974 return SDValue(); 3975} 3976 3977SDValue DAGCombiner::visitSELECT(SDNode *N) { 3978 SDValue N0 = N->getOperand(0); 3979 SDValue N1 = N->getOperand(1); 3980 SDValue N2 = N->getOperand(2); 3981 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3982 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3983 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3984 EVT VT = N->getValueType(0); 3985 EVT VT0 = N0.getValueType(); 3986 3987 // fold (select C, X, X) -> X 3988 if (N1 == N2) 3989 return N1; 3990 // fold (select true, X, Y) -> X 3991 if (N0C && !N0C->isNullValue()) 3992 return N1; 3993 // fold (select false, X, Y) -> Y 3994 if (N0C && N0C->isNullValue()) 3995 return N2; 3996 // fold (select C, 1, X) -> (or C, X) 3997 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3998 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3999 // fold (select C, 0, 1) -> (xor C, 1) 4000 if (VT.isInteger() && 4001 (VT0 == MVT::i1 || 4002 (VT0.isInteger() && 4003 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) && 4004 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4005 SDValue XORNode; 4006 if (VT == VT0) 4007 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4008 N0, DAG.getConstant(1, VT0)); 4009 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4010 N0, DAG.getConstant(1, VT0)); 4011 AddToWorkList(XORNode.getNode()); 4012 if (VT.bitsGT(VT0)) 4013 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4014 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4015 } 4016 // fold (select C, 0, X) -> (and (not C), X) 4017 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4018 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4019 AddToWorkList(NOTNode.getNode()); 4020 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4021 } 4022 // fold (select C, X, 1) -> (or (not C), X) 4023 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4024 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4025 AddToWorkList(NOTNode.getNode()); 4026 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4027 } 4028 // fold (select C, X, 0) -> (and C, X) 4029 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4030 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4031 // fold (select X, X, Y) -> (or X, Y) 4032 // fold (select X, 1, Y) -> (or X, Y) 4033 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4034 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4035 // fold (select X, Y, X) -> (and X, Y) 4036 // fold (select X, Y, 0) -> (and X, Y) 4037 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4038 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4039 4040 // If we can fold this based on the true/false value, do so. 4041 if (SimplifySelectOps(N, N1, N2)) 4042 return SDValue(N, 0); // Don't revisit N. 4043 4044 // fold selects based on a setcc into other things, such as min/max/abs 4045 if (N0.getOpcode() == ISD::SETCC) { 4046 // FIXME: 4047 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4048 // having to say they don't support SELECT_CC on every type the DAG knows 4049 // about, since there is no way to mark an opcode illegal at all value types 4050 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4051 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4052 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4053 N0.getOperand(0), N0.getOperand(1), 4054 N1, N2, N0.getOperand(2)); 4055 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4056 } 4057 4058 return SDValue(); 4059} 4060 4061SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4062 SDValue N0 = N->getOperand(0); 4063 SDValue N1 = N->getOperand(1); 4064 SDValue N2 = N->getOperand(2); 4065 SDValue N3 = N->getOperand(3); 4066 SDValue N4 = N->getOperand(4); 4067 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4068 4069 // fold select_cc lhs, rhs, x, x, cc -> x 4070 if (N2 == N3) 4071 return N2; 4072 4073 // Determine if the condition we're dealing with is constant 4074 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4075 N0, N1, CC, N->getDebugLoc(), false); 4076 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4077 4078 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4079 if (!SCCC->isNullValue()) 4080 return N2; // cond always true -> true val 4081 else 4082 return N3; // cond always false -> false val 4083 } 4084 4085 // Fold to a simpler select_cc 4086 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4087 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4088 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4089 SCC.getOperand(2)); 4090 4091 // If we can fold this based on the true/false value, do so. 4092 if (SimplifySelectOps(N, N2, N3)) 4093 return SDValue(N, 0); // Don't revisit N. 4094 4095 // fold select_cc into other things, such as min/max/abs 4096 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4097} 4098 4099SDValue DAGCombiner::visitSETCC(SDNode *N) { 4100 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4101 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4102 N->getDebugLoc()); 4103} 4104 4105// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4106// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4107// transformation. Returns true if extension are possible and the above 4108// mentioned transformation is profitable. 4109static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4110 unsigned ExtOpc, 4111 SmallVector<SDNode*, 4> &ExtendNodes, 4112 const TargetLowering &TLI) { 4113 bool HasCopyToRegUses = false; 4114 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4115 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4116 UE = N0.getNode()->use_end(); 4117 UI != UE; ++UI) { 4118 SDNode *User = *UI; 4119 if (User == N) 4120 continue; 4121 if (UI.getUse().getResNo() != N0.getResNo()) 4122 continue; 4123 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4124 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4125 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4126 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4127 // Sign bits will be lost after a zext. 4128 return false; 4129 bool Add = false; 4130 for (unsigned i = 0; i != 2; ++i) { 4131 SDValue UseOp = User->getOperand(i); 4132 if (UseOp == N0) 4133 continue; 4134 if (!isa<ConstantSDNode>(UseOp)) 4135 return false; 4136 Add = true; 4137 } 4138 if (Add) 4139 ExtendNodes.push_back(User); 4140 continue; 4141 } 4142 // If truncates aren't free and there are users we can't 4143 // extend, it isn't worthwhile. 4144 if (!isTruncFree) 4145 return false; 4146 // Remember if this value is live-out. 4147 if (User->getOpcode() == ISD::CopyToReg) 4148 HasCopyToRegUses = true; 4149 } 4150 4151 if (HasCopyToRegUses) { 4152 bool BothLiveOut = false; 4153 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4154 UI != UE; ++UI) { 4155 SDUse &Use = UI.getUse(); 4156 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4157 BothLiveOut = true; 4158 break; 4159 } 4160 } 4161 if (BothLiveOut) 4162 // Both unextended and extended values are live out. There had better be 4163 // a good reason for the transformation. 4164 return ExtendNodes.size(); 4165 } 4166 return true; 4167} 4168 4169void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4170 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4171 ISD::NodeType ExtType) { 4172 // Extend SetCC uses if necessary. 4173 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4174 SDNode *SetCC = SetCCs[i]; 4175 SmallVector<SDValue, 4> Ops; 4176 4177 for (unsigned j = 0; j != 2; ++j) { 4178 SDValue SOp = SetCC->getOperand(j); 4179 if (SOp == Trunc) 4180 Ops.push_back(ExtLoad); 4181 else 4182 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4183 } 4184 4185 Ops.push_back(SetCC->getOperand(2)); 4186 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4187 &Ops[0], Ops.size())); 4188 } 4189} 4190 4191SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4192 SDValue N0 = N->getOperand(0); 4193 EVT VT = N->getValueType(0); 4194 4195 // fold (sext c1) -> c1 4196 if (isa<ConstantSDNode>(N0)) 4197 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4198 4199 // fold (sext (sext x)) -> (sext x) 4200 // fold (sext (aext x)) -> (sext x) 4201 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4202 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4203 N0.getOperand(0)); 4204 4205 if (N0.getOpcode() == ISD::TRUNCATE) { 4206 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4207 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4208 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4209 if (NarrowLoad.getNode()) { 4210 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4211 if (NarrowLoad.getNode() != N0.getNode()) { 4212 CombineTo(N0.getNode(), NarrowLoad); 4213 // CombineTo deleted the truncate, if needed, but not what's under it. 4214 AddToWorkList(oye); 4215 } 4216 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4217 } 4218 4219 // See if the value being truncated is already sign extended. If so, just 4220 // eliminate the trunc/sext pair. 4221 SDValue Op = N0.getOperand(0); 4222 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4223 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4224 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4225 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4226 4227 if (OpBits == DestBits) { 4228 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4229 // bits, it is already ready. 4230 if (NumSignBits > DestBits-MidBits) 4231 return Op; 4232 } else if (OpBits < DestBits) { 4233 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4234 // bits, just sext from i32. 4235 if (NumSignBits > OpBits-MidBits) 4236 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4237 } else { 4238 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4239 // bits, just truncate to i32. 4240 if (NumSignBits > OpBits-MidBits) 4241 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4242 } 4243 4244 // fold (sext (truncate x)) -> (sextinreg x). 4245 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4246 N0.getValueType())) { 4247 if (OpBits < DestBits) 4248 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4249 else if (OpBits > DestBits) 4250 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4251 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4252 DAG.getValueType(N0.getValueType())); 4253 } 4254 } 4255 4256 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4257 // None of the supported targets knows how to perform load and sign extend 4258 // on vectors in one instruction. We only perform this transformation on 4259 // scalars. 4260 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4261 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4262 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4263 bool DoXform = true; 4264 SmallVector<SDNode*, 4> SetCCs; 4265 if (!N0.hasOneUse()) 4266 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4267 if (DoXform) { 4268 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4269 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4270 LN0->getChain(), 4271 LN0->getBasePtr(), LN0->getPointerInfo(), 4272 N0.getValueType(), 4273 LN0->isVolatile(), LN0->isNonTemporal(), 4274 LN0->getAlignment()); 4275 CombineTo(N, ExtLoad); 4276 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4277 N0.getValueType(), ExtLoad); 4278 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4279 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4280 ISD::SIGN_EXTEND); 4281 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4282 } 4283 } 4284 4285 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4286 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4287 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4288 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4289 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4290 EVT MemVT = LN0->getMemoryVT(); 4291 if ((!LegalOperations && !LN0->isVolatile()) || 4292 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4293 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4294 LN0->getChain(), 4295 LN0->getBasePtr(), LN0->getPointerInfo(), 4296 MemVT, 4297 LN0->isVolatile(), LN0->isNonTemporal(), 4298 LN0->getAlignment()); 4299 CombineTo(N, ExtLoad); 4300 CombineTo(N0.getNode(), 4301 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4302 N0.getValueType(), ExtLoad), 4303 ExtLoad.getValue(1)); 4304 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4305 } 4306 } 4307 4308 // fold (sext (and/or/xor (load x), cst)) -> 4309 // (and/or/xor (sextload x), (sext cst)) 4310 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4311 N0.getOpcode() == ISD::XOR) && 4312 isa<LoadSDNode>(N0.getOperand(0)) && 4313 N0.getOperand(1).getOpcode() == ISD::Constant && 4314 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4315 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4316 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4317 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4318 bool DoXform = true; 4319 SmallVector<SDNode*, 4> SetCCs; 4320 if (!N0.hasOneUse()) 4321 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4322 SetCCs, TLI); 4323 if (DoXform) { 4324 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4325 LN0->getChain(), LN0->getBasePtr(), 4326 LN0->getPointerInfo(), 4327 LN0->getMemoryVT(), 4328 LN0->isVolatile(), 4329 LN0->isNonTemporal(), 4330 LN0->getAlignment()); 4331 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4332 Mask = Mask.sext(VT.getSizeInBits()); 4333 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4334 ExtLoad, DAG.getConstant(Mask, VT)); 4335 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4336 N0.getOperand(0).getDebugLoc(), 4337 N0.getOperand(0).getValueType(), ExtLoad); 4338 CombineTo(N, And); 4339 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4340 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4341 ISD::SIGN_EXTEND); 4342 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4343 } 4344 } 4345 } 4346 4347 if (N0.getOpcode() == ISD::SETCC) { 4348 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4349 // Only do this before legalize for now. 4350 if (VT.isVector() && !LegalOperations) { 4351 EVT N0VT = N0.getOperand(0).getValueType(); 4352 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4353 // of the same size as the compared operands. Only optimize sext(setcc()) 4354 // if this is the case. 4355 EVT SVT = TLI.getSetCCResultType(N0VT); 4356 4357 // We know that the # elements of the results is the same as the 4358 // # elements of the compare (and the # elements of the compare result 4359 // for that matter). Check to see that they are the same size. If so, 4360 // we know that the element size of the sext'd result matches the 4361 // element size of the compare operands. 4362 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4363 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4364 N0.getOperand(1), 4365 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4366 // If the desired elements are smaller or larger than the source 4367 // elements we can use a matching integer vector type and then 4368 // truncate/sign extend 4369 else { 4370 EVT MatchingElementType = 4371 EVT::getIntegerVT(*DAG.getContext(), 4372 N0VT.getScalarType().getSizeInBits()); 4373 EVT MatchingVectorType = 4374 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4375 N0VT.getVectorNumElements()); 4376 4377 if (SVT == MatchingVectorType) { 4378 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4379 N0.getOperand(0), N0.getOperand(1), 4380 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4381 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4382 } 4383 } 4384 } 4385 4386 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4387 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4388 SDValue NegOne = 4389 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4390 SDValue SCC = 4391 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4392 NegOne, DAG.getConstant(0, VT), 4393 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4394 if (SCC.getNode()) return SCC; 4395 if (!LegalOperations || 4396 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4397 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4398 DAG.getSetCC(N->getDebugLoc(), 4399 TLI.getSetCCResultType(VT), 4400 N0.getOperand(0), N0.getOperand(1), 4401 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4402 NegOne, DAG.getConstant(0, VT)); 4403 } 4404 4405 // fold (sext x) -> (zext x) if the sign bit is known zero. 4406 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4407 DAG.SignBitIsZero(N0)) 4408 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4409 4410 return SDValue(); 4411} 4412 4413// isTruncateOf - If N is a truncate of some other value, return true, record 4414// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4415// This function computes KnownZero to avoid a duplicated call to 4416// ComputeMaskedBits in the caller. 4417static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4418 APInt &KnownZero) { 4419 APInt KnownOne; 4420 if (N->getOpcode() == ISD::TRUNCATE) { 4421 Op = N->getOperand(0); 4422 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4423 return true; 4424 } 4425 4426 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4427 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4428 return false; 4429 4430 SDValue Op0 = N->getOperand(0); 4431 SDValue Op1 = N->getOperand(1); 4432 assert(Op0.getValueType() == Op1.getValueType()); 4433 4434 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4435 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4436 if (COp0 && COp0->isNullValue()) 4437 Op = Op1; 4438 else if (COp1 && COp1->isNullValue()) 4439 Op = Op0; 4440 else 4441 return false; 4442 4443 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4444 4445 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4446 return false; 4447 4448 return true; 4449} 4450 4451SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4452 SDValue N0 = N->getOperand(0); 4453 EVT VT = N->getValueType(0); 4454 4455 // fold (zext c1) -> c1 4456 if (isa<ConstantSDNode>(N0)) 4457 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4458 // fold (zext (zext x)) -> (zext x) 4459 // fold (zext (aext x)) -> (zext x) 4460 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4461 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4462 N0.getOperand(0)); 4463 4464 // fold (zext (truncate x)) -> (zext x) or 4465 // (zext (truncate x)) -> (truncate x) 4466 // This is valid when the truncated bits of x are already zero. 4467 // FIXME: We should extend this to work for vectors too. 4468 SDValue Op; 4469 APInt KnownZero; 4470 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4471 APInt TruncatedBits = 4472 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4473 APInt(Op.getValueSizeInBits(), 0) : 4474 APInt::getBitsSet(Op.getValueSizeInBits(), 4475 N0.getValueSizeInBits(), 4476 std::min(Op.getValueSizeInBits(), 4477 VT.getSizeInBits())); 4478 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4479 if (VT.bitsGT(Op.getValueType())) 4480 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4481 if (VT.bitsLT(Op.getValueType())) 4482 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4483 4484 return Op; 4485 } 4486 } 4487 4488 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4489 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4490 if (N0.getOpcode() == ISD::TRUNCATE) { 4491 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4492 if (NarrowLoad.getNode()) { 4493 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4494 if (NarrowLoad.getNode() != N0.getNode()) { 4495 CombineTo(N0.getNode(), NarrowLoad); 4496 // CombineTo deleted the truncate, if needed, but not what's under it. 4497 AddToWorkList(oye); 4498 } 4499 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4500 } 4501 } 4502 4503 // fold (zext (truncate x)) -> (and x, mask) 4504 if (N0.getOpcode() == ISD::TRUNCATE && 4505 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4506 4507 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4508 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4509 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4510 if (NarrowLoad.getNode()) { 4511 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4512 if (NarrowLoad.getNode() != N0.getNode()) { 4513 CombineTo(N0.getNode(), NarrowLoad); 4514 // CombineTo deleted the truncate, if needed, but not what's under it. 4515 AddToWorkList(oye); 4516 } 4517 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4518 } 4519 4520 SDValue Op = N0.getOperand(0); 4521 if (Op.getValueType().bitsLT(VT)) { 4522 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4523 AddToWorkList(Op.getNode()); 4524 } else if (Op.getValueType().bitsGT(VT)) { 4525 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4526 AddToWorkList(Op.getNode()); 4527 } 4528 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4529 N0.getValueType().getScalarType()); 4530 } 4531 4532 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4533 // if either of the casts is not free. 4534 if (N0.getOpcode() == ISD::AND && 4535 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4536 N0.getOperand(1).getOpcode() == ISD::Constant && 4537 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4538 N0.getValueType()) || 4539 !TLI.isZExtFree(N0.getValueType(), VT))) { 4540 SDValue X = N0.getOperand(0).getOperand(0); 4541 if (X.getValueType().bitsLT(VT)) { 4542 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4543 } else if (X.getValueType().bitsGT(VT)) { 4544 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4545 } 4546 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4547 Mask = Mask.zext(VT.getSizeInBits()); 4548 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4549 X, DAG.getConstant(Mask, VT)); 4550 } 4551 4552 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4553 // None of the supported targets knows how to perform load and vector_zext 4554 // on vectors in one instruction. We only perform this transformation on 4555 // scalars. 4556 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4557 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4558 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4559 bool DoXform = true; 4560 SmallVector<SDNode*, 4> SetCCs; 4561 if (!N0.hasOneUse()) 4562 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4563 if (DoXform) { 4564 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4565 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4566 LN0->getChain(), 4567 LN0->getBasePtr(), LN0->getPointerInfo(), 4568 N0.getValueType(), 4569 LN0->isVolatile(), LN0->isNonTemporal(), 4570 LN0->getAlignment()); 4571 CombineTo(N, ExtLoad); 4572 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4573 N0.getValueType(), ExtLoad); 4574 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4575 4576 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4577 ISD::ZERO_EXTEND); 4578 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4579 } 4580 } 4581 4582 // fold (zext (and/or/xor (load x), cst)) -> 4583 // (and/or/xor (zextload x), (zext cst)) 4584 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4585 N0.getOpcode() == ISD::XOR) && 4586 isa<LoadSDNode>(N0.getOperand(0)) && 4587 N0.getOperand(1).getOpcode() == ISD::Constant && 4588 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4589 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4590 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4591 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4592 bool DoXform = true; 4593 SmallVector<SDNode*, 4> SetCCs; 4594 if (!N0.hasOneUse()) 4595 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4596 SetCCs, TLI); 4597 if (DoXform) { 4598 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4599 LN0->getChain(), LN0->getBasePtr(), 4600 LN0->getPointerInfo(), 4601 LN0->getMemoryVT(), 4602 LN0->isVolatile(), 4603 LN0->isNonTemporal(), 4604 LN0->getAlignment()); 4605 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4606 Mask = Mask.zext(VT.getSizeInBits()); 4607 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4608 ExtLoad, DAG.getConstant(Mask, VT)); 4609 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4610 N0.getOperand(0).getDebugLoc(), 4611 N0.getOperand(0).getValueType(), ExtLoad); 4612 CombineTo(N, And); 4613 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4614 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4615 ISD::ZERO_EXTEND); 4616 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4617 } 4618 } 4619 } 4620 4621 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4622 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4623 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4624 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4625 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4626 EVT MemVT = LN0->getMemoryVT(); 4627 if ((!LegalOperations && !LN0->isVolatile()) || 4628 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4629 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4630 LN0->getChain(), 4631 LN0->getBasePtr(), LN0->getPointerInfo(), 4632 MemVT, 4633 LN0->isVolatile(), LN0->isNonTemporal(), 4634 LN0->getAlignment()); 4635 CombineTo(N, ExtLoad); 4636 CombineTo(N0.getNode(), 4637 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4638 ExtLoad), 4639 ExtLoad.getValue(1)); 4640 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4641 } 4642 } 4643 4644 if (N0.getOpcode() == ISD::SETCC) { 4645 if (!LegalOperations && VT.isVector()) { 4646 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4647 // Only do this before legalize for now. 4648 EVT N0VT = N0.getOperand(0).getValueType(); 4649 EVT EltVT = VT.getVectorElementType(); 4650 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4651 DAG.getConstant(1, EltVT)); 4652 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4653 // We know that the # elements of the results is the same as the 4654 // # elements of the compare (and the # elements of the compare result 4655 // for that matter). Check to see that they are the same size. If so, 4656 // we know that the element size of the sext'd result matches the 4657 // element size of the compare operands. 4658 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4659 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4660 N0.getOperand(1), 4661 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4662 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4663 &OneOps[0], OneOps.size())); 4664 4665 // If the desired elements are smaller or larger than the source 4666 // elements we can use a matching integer vector type and then 4667 // truncate/sign extend 4668 EVT MatchingElementType = 4669 EVT::getIntegerVT(*DAG.getContext(), 4670 N0VT.getScalarType().getSizeInBits()); 4671 EVT MatchingVectorType = 4672 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4673 N0VT.getVectorNumElements()); 4674 SDValue VsetCC = 4675 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4676 N0.getOperand(1), 4677 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4678 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4679 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4680 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4681 &OneOps[0], OneOps.size())); 4682 } 4683 4684 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4685 SDValue SCC = 4686 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4687 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4688 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4689 if (SCC.getNode()) return SCC; 4690 } 4691 4692 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4693 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4694 isa<ConstantSDNode>(N0.getOperand(1)) && 4695 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4696 N0.hasOneUse()) { 4697 SDValue ShAmt = N0.getOperand(1); 4698 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4699 if (N0.getOpcode() == ISD::SHL) { 4700 SDValue InnerZExt = N0.getOperand(0); 4701 // If the original shl may be shifting out bits, do not perform this 4702 // transformation. 4703 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4704 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4705 if (ShAmtVal > KnownZeroBits) 4706 return SDValue(); 4707 } 4708 4709 DebugLoc DL = N->getDebugLoc(); 4710 4711 // Ensure that the shift amount is wide enough for the shifted value. 4712 if (VT.getSizeInBits() >= 256) 4713 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4714 4715 return DAG.getNode(N0.getOpcode(), DL, VT, 4716 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4717 ShAmt); 4718 } 4719 4720 return SDValue(); 4721} 4722 4723SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4724 SDValue N0 = N->getOperand(0); 4725 EVT VT = N->getValueType(0); 4726 4727 // fold (aext c1) -> c1 4728 if (isa<ConstantSDNode>(N0)) 4729 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4730 // fold (aext (aext x)) -> (aext x) 4731 // fold (aext (zext x)) -> (zext x) 4732 // fold (aext (sext x)) -> (sext x) 4733 if (N0.getOpcode() == ISD::ANY_EXTEND || 4734 N0.getOpcode() == ISD::ZERO_EXTEND || 4735 N0.getOpcode() == ISD::SIGN_EXTEND) 4736 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4737 4738 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4739 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4740 if (N0.getOpcode() == ISD::TRUNCATE) { 4741 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4742 if (NarrowLoad.getNode()) { 4743 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4744 if (NarrowLoad.getNode() != N0.getNode()) { 4745 CombineTo(N0.getNode(), NarrowLoad); 4746 // CombineTo deleted the truncate, if needed, but not what's under it. 4747 AddToWorkList(oye); 4748 } 4749 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4750 } 4751 } 4752 4753 // fold (aext (truncate x)) 4754 if (N0.getOpcode() == ISD::TRUNCATE) { 4755 SDValue TruncOp = N0.getOperand(0); 4756 if (TruncOp.getValueType() == VT) 4757 return TruncOp; // x iff x size == zext size. 4758 if (TruncOp.getValueType().bitsGT(VT)) 4759 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4760 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4761 } 4762 4763 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4764 // if the trunc is not free. 4765 if (N0.getOpcode() == ISD::AND && 4766 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4767 N0.getOperand(1).getOpcode() == ISD::Constant && 4768 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4769 N0.getValueType())) { 4770 SDValue X = N0.getOperand(0).getOperand(0); 4771 if (X.getValueType().bitsLT(VT)) { 4772 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4773 } else if (X.getValueType().bitsGT(VT)) { 4774 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4775 } 4776 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4777 Mask = Mask.zext(VT.getSizeInBits()); 4778 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4779 X, DAG.getConstant(Mask, VT)); 4780 } 4781 4782 // fold (aext (load x)) -> (aext (truncate (extload x))) 4783 // None of the supported targets knows how to perform load and any_ext 4784 // on vectors in one instruction. We only perform this transformation on 4785 // scalars. 4786 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4787 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4788 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4789 bool DoXform = true; 4790 SmallVector<SDNode*, 4> SetCCs; 4791 if (!N0.hasOneUse()) 4792 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4793 if (DoXform) { 4794 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4795 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4796 LN0->getChain(), 4797 LN0->getBasePtr(), LN0->getPointerInfo(), 4798 N0.getValueType(), 4799 LN0->isVolatile(), LN0->isNonTemporal(), 4800 LN0->getAlignment()); 4801 CombineTo(N, ExtLoad); 4802 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4803 N0.getValueType(), ExtLoad); 4804 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4805 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4806 ISD::ANY_EXTEND); 4807 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4808 } 4809 } 4810 4811 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4812 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4813 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4814 if (N0.getOpcode() == ISD::LOAD && 4815 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4816 N0.hasOneUse()) { 4817 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4818 EVT MemVT = LN0->getMemoryVT(); 4819 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4820 VT, LN0->getChain(), LN0->getBasePtr(), 4821 LN0->getPointerInfo(), MemVT, 4822 LN0->isVolatile(), LN0->isNonTemporal(), 4823 LN0->getAlignment()); 4824 CombineTo(N, ExtLoad); 4825 CombineTo(N0.getNode(), 4826 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4827 N0.getValueType(), ExtLoad), 4828 ExtLoad.getValue(1)); 4829 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4830 } 4831 4832 if (N0.getOpcode() == ISD::SETCC) { 4833 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4834 // Only do this before legalize for now. 4835 if (VT.isVector() && !LegalOperations) { 4836 EVT N0VT = N0.getOperand(0).getValueType(); 4837 // We know that the # elements of the results is the same as the 4838 // # elements of the compare (and the # elements of the compare result 4839 // for that matter). Check to see that they are the same size. If so, 4840 // we know that the element size of the sext'd result matches the 4841 // element size of the compare operands. 4842 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4843 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4844 N0.getOperand(1), 4845 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4846 // If the desired elements are smaller or larger than the source 4847 // elements we can use a matching integer vector type and then 4848 // truncate/sign extend 4849 else { 4850 EVT MatchingElementType = 4851 EVT::getIntegerVT(*DAG.getContext(), 4852 N0VT.getScalarType().getSizeInBits()); 4853 EVT MatchingVectorType = 4854 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4855 N0VT.getVectorNumElements()); 4856 SDValue VsetCC = 4857 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4858 N0.getOperand(1), 4859 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4860 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4861 } 4862 } 4863 4864 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4865 SDValue SCC = 4866 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4867 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4868 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4869 if (SCC.getNode()) 4870 return SCC; 4871 } 4872 4873 return SDValue(); 4874} 4875 4876/// GetDemandedBits - See if the specified operand can be simplified with the 4877/// knowledge that only the bits specified by Mask are used. If so, return the 4878/// simpler operand, otherwise return a null SDValue. 4879SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4880 switch (V.getOpcode()) { 4881 default: break; 4882 case ISD::Constant: { 4883 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4884 assert(CV != 0 && "Const value should be ConstSDNode."); 4885 const APInt &CVal = CV->getAPIntValue(); 4886 APInt NewVal = CVal & Mask; 4887 if (NewVal != CVal) { 4888 return DAG.getConstant(NewVal, V.getValueType()); 4889 } 4890 break; 4891 } 4892 case ISD::OR: 4893 case ISD::XOR: 4894 // If the LHS or RHS don't contribute bits to the or, drop them. 4895 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4896 return V.getOperand(1); 4897 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4898 return V.getOperand(0); 4899 break; 4900 case ISD::SRL: 4901 // Only look at single-use SRLs. 4902 if (!V.getNode()->hasOneUse()) 4903 break; 4904 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4905 // See if we can recursively simplify the LHS. 4906 unsigned Amt = RHSC->getZExtValue(); 4907 4908 // Watch out for shift count overflow though. 4909 if (Amt >= Mask.getBitWidth()) break; 4910 APInt NewMask = Mask << Amt; 4911 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4912 if (SimplifyLHS.getNode()) 4913 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4914 SimplifyLHS, V.getOperand(1)); 4915 } 4916 } 4917 return SDValue(); 4918} 4919 4920/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4921/// bits and then truncated to a narrower type and where N is a multiple 4922/// of number of bits of the narrower type, transform it to a narrower load 4923/// from address + N / num of bits of new type. If the result is to be 4924/// extended, also fold the extension to form a extending load. 4925SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4926 unsigned Opc = N->getOpcode(); 4927 4928 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4929 SDValue N0 = N->getOperand(0); 4930 EVT VT = N->getValueType(0); 4931 EVT ExtVT = VT; 4932 4933 // This transformation isn't valid for vector loads. 4934 if (VT.isVector()) 4935 return SDValue(); 4936 4937 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4938 // extended to VT. 4939 if (Opc == ISD::SIGN_EXTEND_INREG) { 4940 ExtType = ISD::SEXTLOAD; 4941 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4942 } else if (Opc == ISD::SRL) { 4943 // Another special-case: SRL is basically zero-extending a narrower value. 4944 ExtType = ISD::ZEXTLOAD; 4945 N0 = SDValue(N, 0); 4946 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4947 if (!N01) return SDValue(); 4948 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4949 VT.getSizeInBits() - N01->getZExtValue()); 4950 } 4951 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4952 return SDValue(); 4953 4954 unsigned EVTBits = ExtVT.getSizeInBits(); 4955 4956 // Do not generate loads of non-round integer types since these can 4957 // be expensive (and would be wrong if the type is not byte sized). 4958 if (!ExtVT.isRound()) 4959 return SDValue(); 4960 4961 unsigned ShAmt = 0; 4962 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4963 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4964 ShAmt = N01->getZExtValue(); 4965 // Is the shift amount a multiple of size of VT? 4966 if ((ShAmt & (EVTBits-1)) == 0) { 4967 N0 = N0.getOperand(0); 4968 // Is the load width a multiple of size of VT? 4969 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4970 return SDValue(); 4971 } 4972 4973 // At this point, we must have a load or else we can't do the transform. 4974 if (!isa<LoadSDNode>(N0)) return SDValue(); 4975 4976 // If the shift amount is larger than the input type then we're not 4977 // accessing any of the loaded bytes. If the load was a zextload/extload 4978 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4979 // If the load was a sextload then the result is a splat of the sign bit 4980 // of the extended byte. This is not worth optimizing for. 4981 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4982 return SDValue(); 4983 } 4984 } 4985 4986 // If the load is shifted left (and the result isn't shifted back right), 4987 // we can fold the truncate through the shift. 4988 unsigned ShLeftAmt = 0; 4989 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4990 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4991 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4992 ShLeftAmt = N01->getZExtValue(); 4993 N0 = N0.getOperand(0); 4994 } 4995 } 4996 4997 // If we haven't found a load, we can't narrow it. Don't transform one with 4998 // multiple uses, this would require adding a new load. 4999 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 5000 // Don't change the width of a volatile load. 5001 cast<LoadSDNode>(N0)->isVolatile()) 5002 return SDValue(); 5003 5004 // Verify that we are actually reducing a load width here. 5005 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 5006 return SDValue(); 5007 5008 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5009 EVT PtrType = N0.getOperand(1).getValueType(); 5010 5011 // For big endian targets, we need to adjust the offset to the pointer to 5012 // load the correct bytes. 5013 if (TLI.isBigEndian()) { 5014 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5015 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5016 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5017 } 5018 5019 uint64_t PtrOff = ShAmt / 8; 5020 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5021 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5022 PtrType, LN0->getBasePtr(), 5023 DAG.getConstant(PtrOff, PtrType)); 5024 AddToWorkList(NewPtr.getNode()); 5025 5026 SDValue Load; 5027 if (ExtType == ISD::NON_EXTLOAD) 5028 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5029 LN0->getPointerInfo().getWithOffset(PtrOff), 5030 LN0->isVolatile(), LN0->isNonTemporal(), 5031 LN0->isInvariant(), NewAlign); 5032 else 5033 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5034 LN0->getPointerInfo().getWithOffset(PtrOff), 5035 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5036 NewAlign); 5037 5038 // Replace the old load's chain with the new load's chain. 5039 WorkListRemover DeadNodes(*this); 5040 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5041 5042 // Shift the result left, if we've swallowed a left shift. 5043 SDValue Result = Load; 5044 if (ShLeftAmt != 0) { 5045 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5046 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5047 ShImmTy = VT; 5048 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5049 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5050 } 5051 5052 // Return the new loaded value. 5053 return Result; 5054} 5055 5056SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5057 SDValue N0 = N->getOperand(0); 5058 SDValue N1 = N->getOperand(1); 5059 EVT VT = N->getValueType(0); 5060 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5061 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5062 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5063 5064 // fold (sext_in_reg c1) -> c1 5065 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5066 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5067 5068 // If the input is already sign extended, just drop the extension. 5069 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5070 return N0; 5071 5072 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5073 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5074 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5075 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5076 N0.getOperand(0), N1); 5077 } 5078 5079 // fold (sext_in_reg (sext x)) -> (sext x) 5080 // fold (sext_in_reg (aext x)) -> (sext x) 5081 // if x is small enough. 5082 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5083 SDValue N00 = N0.getOperand(0); 5084 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5085 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5086 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5087 } 5088 5089 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5090 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5091 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5092 5093 // fold operands of sext_in_reg based on knowledge that the top bits are not 5094 // demanded. 5095 if (SimplifyDemandedBits(SDValue(N, 0))) 5096 return SDValue(N, 0); 5097 5098 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5099 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5100 SDValue NarrowLoad = ReduceLoadWidth(N); 5101 if (NarrowLoad.getNode()) 5102 return NarrowLoad; 5103 5104 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5105 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5106 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5107 if (N0.getOpcode() == ISD::SRL) { 5108 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5109 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5110 // We can turn this into an SRA iff the input to the SRL is already sign 5111 // extended enough. 5112 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5113 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5114 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5115 N0.getOperand(0), N0.getOperand(1)); 5116 } 5117 } 5118 5119 // fold (sext_inreg (extload x)) -> (sextload x) 5120 if (ISD::isEXTLoad(N0.getNode()) && 5121 ISD::isUNINDEXEDLoad(N0.getNode()) && 5122 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5123 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5124 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5125 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5126 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5127 LN0->getChain(), 5128 LN0->getBasePtr(), LN0->getPointerInfo(), 5129 EVT, 5130 LN0->isVolatile(), LN0->isNonTemporal(), 5131 LN0->getAlignment()); 5132 CombineTo(N, ExtLoad); 5133 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5134 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5135 } 5136 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5137 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5138 N0.hasOneUse() && 5139 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5140 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5141 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5142 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5143 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5144 LN0->getChain(), 5145 LN0->getBasePtr(), LN0->getPointerInfo(), 5146 EVT, 5147 LN0->isVolatile(), LN0->isNonTemporal(), 5148 LN0->getAlignment()); 5149 CombineTo(N, ExtLoad); 5150 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5151 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5152 } 5153 5154 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5155 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5156 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5157 N0.getOperand(1), false); 5158 if (BSwap.getNode() != 0) 5159 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5160 BSwap, N1); 5161 } 5162 5163 return SDValue(); 5164} 5165 5166SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5167 SDValue N0 = N->getOperand(0); 5168 EVT VT = N->getValueType(0); 5169 bool isLE = TLI.isLittleEndian(); 5170 5171 // noop truncate 5172 if (N0.getValueType() == N->getValueType(0)) 5173 return N0; 5174 // fold (truncate c1) -> c1 5175 if (isa<ConstantSDNode>(N0)) 5176 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5177 // fold (truncate (truncate x)) -> (truncate x) 5178 if (N0.getOpcode() == ISD::TRUNCATE) 5179 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5180 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5181 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5182 N0.getOpcode() == ISD::SIGN_EXTEND || 5183 N0.getOpcode() == ISD::ANY_EXTEND) { 5184 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5185 // if the source is smaller than the dest, we still need an extend 5186 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5187 N0.getOperand(0)); 5188 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 5189 // if the source is larger than the dest, than we just need the truncate 5190 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5191 else 5192 // if the source and dest are the same type, we can drop both the extend 5193 // and the truncate. 5194 return N0.getOperand(0); 5195 } 5196 5197 // Fold extract-and-trunc into a narrow extract. For example: 5198 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5199 // i32 y = TRUNCATE(i64 x) 5200 // -- becomes -- 5201 // v16i8 b = BITCAST (v2i64 val) 5202 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5203 // 5204 // Note: We only run this optimization after type legalization (which often 5205 // creates this pattern) and before operation legalization after which 5206 // we need to be more careful about the vector instructions that we generate. 5207 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5208 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5209 5210 EVT VecTy = N0.getOperand(0).getValueType(); 5211 EVT ExTy = N0.getValueType(); 5212 EVT TrTy = N->getValueType(0); 5213 5214 unsigned NumElem = VecTy.getVectorNumElements(); 5215 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5216 5217 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5218 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5219 5220 SDValue EltNo = N0->getOperand(1); 5221 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5222 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5223 5224 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5225 5226 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5227 NVT, N0.getOperand(0)); 5228 5229 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5230 N->getDebugLoc(), TrTy, V, 5231 DAG.getConstant(Index, MVT::i32)); 5232 } 5233 } 5234 5235 // See if we can simplify the input to this truncate through knowledge that 5236 // only the low bits are being used. 5237 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5238 // Currently we only perform this optimization on scalars because vectors 5239 // may have different active low bits. 5240 if (!VT.isVector()) { 5241 SDValue Shorter = 5242 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5243 VT.getSizeInBits())); 5244 if (Shorter.getNode()) 5245 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5246 } 5247 // fold (truncate (load x)) -> (smaller load x) 5248 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5249 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5250 SDValue Reduced = ReduceLoadWidth(N); 5251 if (Reduced.getNode()) 5252 return Reduced; 5253 } 5254 5255 // Simplify the operands using demanded-bits information. 5256 if (!VT.isVector() && 5257 SimplifyDemandedBits(SDValue(N, 0))) 5258 return SDValue(N, 0); 5259 5260 return SDValue(); 5261} 5262 5263static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5264 SDValue Elt = N->getOperand(i); 5265 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5266 return Elt.getNode(); 5267 return Elt.getOperand(Elt.getResNo()).getNode(); 5268} 5269 5270/// CombineConsecutiveLoads - build_pair (load, load) -> load 5271/// if load locations are consecutive. 5272SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5273 assert(N->getOpcode() == ISD::BUILD_PAIR); 5274 5275 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5276 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5277 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5278 LD1->getPointerInfo().getAddrSpace() != 5279 LD2->getPointerInfo().getAddrSpace()) 5280 return SDValue(); 5281 EVT LD1VT = LD1->getValueType(0); 5282 5283 if (ISD::isNON_EXTLoad(LD2) && 5284 LD2->hasOneUse() && 5285 // If both are volatile this would reduce the number of volatile loads. 5286 // If one is volatile it might be ok, but play conservative and bail out. 5287 !LD1->isVolatile() && 5288 !LD2->isVolatile() && 5289 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5290 unsigned Align = LD1->getAlignment(); 5291 unsigned NewAlign = TLI.getTargetData()-> 5292 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5293 5294 if (NewAlign <= Align && 5295 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5296 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5297 LD1->getBasePtr(), LD1->getPointerInfo(), 5298 false, false, false, Align); 5299 } 5300 5301 return SDValue(); 5302} 5303 5304SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5305 SDValue N0 = N->getOperand(0); 5306 EVT VT = N->getValueType(0); 5307 5308 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5309 // Only do this before legalize, since afterward the target may be depending 5310 // on the bitconvert. 5311 // First check to see if this is all constant. 5312 if (!LegalTypes && 5313 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5314 VT.isVector()) { 5315 bool isSimple = true; 5316 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5317 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5318 N0.getOperand(i).getOpcode() != ISD::Constant && 5319 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5320 isSimple = false; 5321 break; 5322 } 5323 5324 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5325 assert(!DestEltVT.isVector() && 5326 "Element type of vector ValueType must not be vector!"); 5327 if (isSimple) 5328 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5329 } 5330 5331 // If the input is a constant, let getNode fold it. 5332 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5333 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5334 if (Res.getNode() != N) { 5335 if (!LegalOperations || 5336 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5337 return Res; 5338 5339 // Folding it resulted in an illegal node, and it's too late to 5340 // do that. Clean up the old node and forego the transformation. 5341 // Ideally this won't happen very often, because instcombine 5342 // and the earlier dagcombine runs (where illegal nodes are 5343 // permitted) should have folded most of them already. 5344 DAG.DeleteNode(Res.getNode()); 5345 } 5346 } 5347 5348 // (conv (conv x, t1), t2) -> (conv x, t2) 5349 if (N0.getOpcode() == ISD::BITCAST) 5350 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5351 N0.getOperand(0)); 5352 5353 // fold (conv (load x)) -> (load (conv*)x) 5354 // If the resultant load doesn't need a higher alignment than the original! 5355 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5356 // Do not change the width of a volatile load. 5357 !cast<LoadSDNode>(N0)->isVolatile() && 5358 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5359 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5360 unsigned Align = TLI.getTargetData()-> 5361 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5362 unsigned OrigAlign = LN0->getAlignment(); 5363 5364 if (Align <= OrigAlign) { 5365 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5366 LN0->getBasePtr(), LN0->getPointerInfo(), 5367 LN0->isVolatile(), LN0->isNonTemporal(), 5368 LN0->isInvariant(), OrigAlign); 5369 AddToWorkList(N); 5370 CombineTo(N0.getNode(), 5371 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5372 N0.getValueType(), Load), 5373 Load.getValue(1)); 5374 return Load; 5375 } 5376 } 5377 5378 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5379 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5380 // This often reduces constant pool loads. 5381 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5382 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5383 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5384 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5385 N0.getOperand(0)); 5386 AddToWorkList(NewConv.getNode()); 5387 5388 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5389 if (N0.getOpcode() == ISD::FNEG) 5390 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5391 NewConv, DAG.getConstant(SignBit, VT)); 5392 assert(N0.getOpcode() == ISD::FABS); 5393 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5394 NewConv, DAG.getConstant(~SignBit, VT)); 5395 } 5396 5397 // fold (bitconvert (fcopysign cst, x)) -> 5398 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5399 // Note that we don't handle (copysign x, cst) because this can always be 5400 // folded to an fneg or fabs. 5401 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5402 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5403 VT.isInteger() && !VT.isVector()) { 5404 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5405 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5406 if (isTypeLegal(IntXVT)) { 5407 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5408 IntXVT, N0.getOperand(1)); 5409 AddToWorkList(X.getNode()); 5410 5411 // If X has a different width than the result/lhs, sext it or truncate it. 5412 unsigned VTWidth = VT.getSizeInBits(); 5413 if (OrigXWidth < VTWidth) { 5414 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5415 AddToWorkList(X.getNode()); 5416 } else if (OrigXWidth > VTWidth) { 5417 // To get the sign bit in the right place, we have to shift it right 5418 // before truncating. 5419 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5420 X.getValueType(), X, 5421 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5422 AddToWorkList(X.getNode()); 5423 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5424 AddToWorkList(X.getNode()); 5425 } 5426 5427 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5428 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5429 X, DAG.getConstant(SignBit, VT)); 5430 AddToWorkList(X.getNode()); 5431 5432 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5433 VT, N0.getOperand(0)); 5434 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5435 Cst, DAG.getConstant(~SignBit, VT)); 5436 AddToWorkList(Cst.getNode()); 5437 5438 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5439 } 5440 } 5441 5442 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5443 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5444 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5445 if (CombineLD.getNode()) 5446 return CombineLD; 5447 } 5448 5449 return SDValue(); 5450} 5451 5452SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5453 EVT VT = N->getValueType(0); 5454 return CombineConsecutiveLoads(N, VT); 5455} 5456 5457/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5458/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5459/// destination element value type. 5460SDValue DAGCombiner:: 5461ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5462 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5463 5464 // If this is already the right type, we're done. 5465 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5466 5467 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5468 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5469 5470 // If this is a conversion of N elements of one type to N elements of another 5471 // type, convert each element. This handles FP<->INT cases. 5472 if (SrcBitSize == DstBitSize) { 5473 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5474 BV->getValueType(0).getVectorNumElements()); 5475 5476 // Due to the FP element handling below calling this routine recursively, 5477 // we can end up with a scalar-to-vector node here. 5478 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5479 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5480 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5481 DstEltVT, BV->getOperand(0))); 5482 5483 SmallVector<SDValue, 8> Ops; 5484 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5485 SDValue Op = BV->getOperand(i); 5486 // If the vector element type is not legal, the BUILD_VECTOR operands 5487 // are promoted and implicitly truncated. Make that explicit here. 5488 if (Op.getValueType() != SrcEltVT) 5489 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5490 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5491 DstEltVT, Op)); 5492 AddToWorkList(Ops.back().getNode()); 5493 } 5494 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5495 &Ops[0], Ops.size()); 5496 } 5497 5498 // Otherwise, we're growing or shrinking the elements. To avoid having to 5499 // handle annoying details of growing/shrinking FP values, we convert them to 5500 // int first. 5501 if (SrcEltVT.isFloatingPoint()) { 5502 // Convert the input float vector to a int vector where the elements are the 5503 // same sizes. 5504 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5505 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5506 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5507 SrcEltVT = IntVT; 5508 } 5509 5510 // Now we know the input is an integer vector. If the output is a FP type, 5511 // convert to integer first, then to FP of the right size. 5512 if (DstEltVT.isFloatingPoint()) { 5513 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5514 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5515 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5516 5517 // Next, convert to FP elements of the same size. 5518 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5519 } 5520 5521 // Okay, we know the src/dst types are both integers of differing types. 5522 // Handling growing first. 5523 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5524 if (SrcBitSize < DstBitSize) { 5525 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5526 5527 SmallVector<SDValue, 8> Ops; 5528 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5529 i += NumInputsPerOutput) { 5530 bool isLE = TLI.isLittleEndian(); 5531 APInt NewBits = APInt(DstBitSize, 0); 5532 bool EltIsUndef = true; 5533 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5534 // Shift the previously computed bits over. 5535 NewBits <<= SrcBitSize; 5536 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5537 if (Op.getOpcode() == ISD::UNDEF) continue; 5538 EltIsUndef = false; 5539 5540 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5541 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5542 } 5543 5544 if (EltIsUndef) 5545 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5546 else 5547 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5548 } 5549 5550 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5551 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5552 &Ops[0], Ops.size()); 5553 } 5554 5555 // Finally, this must be the case where we are shrinking elements: each input 5556 // turns into multiple outputs. 5557 bool isS2V = ISD::isScalarToVector(BV); 5558 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5559 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5560 NumOutputsPerInput*BV->getNumOperands()); 5561 SmallVector<SDValue, 8> Ops; 5562 5563 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5564 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5565 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5566 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5567 continue; 5568 } 5569 5570 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5571 getAPIntValue().zextOrTrunc(SrcBitSize); 5572 5573 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5574 APInt ThisVal = OpVal.trunc(DstBitSize); 5575 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5576 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5577 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5578 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5579 Ops[0]); 5580 OpVal = OpVal.lshr(DstBitSize); 5581 } 5582 5583 // For big endian targets, swap the order of the pieces of each element. 5584 if (TLI.isBigEndian()) 5585 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5586 } 5587 5588 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5589 &Ops[0], Ops.size()); 5590} 5591 5592SDValue DAGCombiner::visitFADD(SDNode *N) { 5593 SDValue N0 = N->getOperand(0); 5594 SDValue N1 = N->getOperand(1); 5595 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5596 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5597 EVT VT = N->getValueType(0); 5598 5599 // fold vector ops 5600 if (VT.isVector()) { 5601 SDValue FoldedVOp = SimplifyVBinOp(N); 5602 if (FoldedVOp.getNode()) return FoldedVOp; 5603 } 5604 5605 // fold (fadd c1, c2) -> (fadd c1, c2) 5606 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5607 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5608 // canonicalize constant to RHS 5609 if (N0CFP && !N1CFP) 5610 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5611 // fold (fadd A, 0) -> A 5612 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5613 N1CFP->getValueAPF().isZero()) 5614 return N0; 5615 // fold (fadd A, (fneg B)) -> (fsub A, B) 5616 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5617 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5618 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5619 GetNegatedExpression(N1, DAG, LegalOperations)); 5620 // fold (fadd (fneg A), B) -> (fsub B, A) 5621 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5622 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5623 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5624 GetNegatedExpression(N0, DAG, LegalOperations)); 5625 5626 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5627 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5628 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5629 isa<ConstantFPSDNode>(N0.getOperand(1))) 5630 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5631 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5632 N0.getOperand(1), N1)); 5633 5634 return SDValue(); 5635} 5636 5637SDValue DAGCombiner::visitFSUB(SDNode *N) { 5638 SDValue N0 = N->getOperand(0); 5639 SDValue N1 = N->getOperand(1); 5640 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5641 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5642 EVT VT = N->getValueType(0); 5643 5644 // fold vector ops 5645 if (VT.isVector()) { 5646 SDValue FoldedVOp = SimplifyVBinOp(N); 5647 if (FoldedVOp.getNode()) return FoldedVOp; 5648 } 5649 5650 // fold (fsub c1, c2) -> c1-c2 5651 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5652 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5653 // fold (fsub A, 0) -> A 5654 if (DAG.getTarget().Options.UnsafeFPMath && 5655 N1CFP && N1CFP->getValueAPF().isZero()) 5656 return N0; 5657 // fold (fsub 0, B) -> -B 5658 if (DAG.getTarget().Options.UnsafeFPMath && 5659 N0CFP && N0CFP->getValueAPF().isZero()) { 5660 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5661 return GetNegatedExpression(N1, DAG, LegalOperations); 5662 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5663 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5664 } 5665 // fold (fsub A, (fneg B)) -> (fadd A, B) 5666 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5667 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5668 GetNegatedExpression(N1, DAG, LegalOperations)); 5669 5670 // If 'unsafe math' is enabled, fold 5671 // (fsub x, (fadd x, y)) -> (fneg y) & 5672 // (fsub x, (fadd y, x)) -> (fneg y) 5673 if (DAG.getTarget().Options.UnsafeFPMath) { 5674 if (N1.getOpcode() == ISD::FADD) { 5675 SDValue N10 = N1->getOperand(0); 5676 SDValue N11 = N1->getOperand(1); 5677 5678 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5679 &DAG.getTarget().Options)) 5680 return GetNegatedExpression(N11, DAG, LegalOperations); 5681 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5682 &DAG.getTarget().Options)) 5683 return GetNegatedExpression(N10, DAG, LegalOperations); 5684 } 5685 } 5686 5687 return SDValue(); 5688} 5689 5690SDValue DAGCombiner::visitFMUL(SDNode *N) { 5691 SDValue N0 = N->getOperand(0); 5692 SDValue N1 = N->getOperand(1); 5693 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5694 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5695 EVT VT = N->getValueType(0); 5696 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5697 5698 // fold vector ops 5699 if (VT.isVector()) { 5700 SDValue FoldedVOp = SimplifyVBinOp(N); 5701 if (FoldedVOp.getNode()) return FoldedVOp; 5702 } 5703 5704 // fold (fmul c1, c2) -> c1*c2 5705 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5706 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5707 // canonicalize constant to RHS 5708 if (N0CFP && !N1CFP) 5709 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5710 // fold (fmul A, 0) -> 0 5711 if (DAG.getTarget().Options.UnsafeFPMath && 5712 N1CFP && N1CFP->getValueAPF().isZero()) 5713 return N1; 5714 // fold (fmul A, 0) -> 0, vector edition. 5715 if (DAG.getTarget().Options.UnsafeFPMath && 5716 ISD::isBuildVectorAllZeros(N1.getNode())) 5717 return N1; 5718 // fold (fmul A, 1.0) -> A 5719 if (N1CFP && N1CFP->isExactlyValue(1.0)) 5720 return N0; 5721 // fold (fmul X, 2.0) -> (fadd X, X) 5722 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5723 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5724 // fold (fmul X, -1.0) -> (fneg X) 5725 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5726 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5727 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5728 5729 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5730 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5731 &DAG.getTarget().Options)) { 5732 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5733 &DAG.getTarget().Options)) { 5734 // Both can be negated for free, check to see if at least one is cheaper 5735 // negated. 5736 if (LHSNeg == 2 || RHSNeg == 2) 5737 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5738 GetNegatedExpression(N0, DAG, LegalOperations), 5739 GetNegatedExpression(N1, DAG, LegalOperations)); 5740 } 5741 } 5742 5743 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5744 if (DAG.getTarget().Options.UnsafeFPMath && 5745 N1CFP && N0.getOpcode() == ISD::FMUL && 5746 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5747 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5748 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5749 N0.getOperand(1), N1)); 5750 5751 return SDValue(); 5752} 5753 5754SDValue DAGCombiner::visitFDIV(SDNode *N) { 5755 SDValue N0 = N->getOperand(0); 5756 SDValue N1 = N->getOperand(1); 5757 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5758 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5759 EVT VT = N->getValueType(0); 5760 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5761 5762 // fold vector ops 5763 if (VT.isVector()) { 5764 SDValue FoldedVOp = SimplifyVBinOp(N); 5765 if (FoldedVOp.getNode()) return FoldedVOp; 5766 } 5767 5768 // fold (fdiv c1, c2) -> c1/c2 5769 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5770 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5771 5772 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 5773 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) { 5774 // Compute the reciprocal 1.0 / c2. 5775 APFloat N1APF = N1CFP->getValueAPF(); 5776 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 5777 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 5778 // Only do the transform if the reciprocal is a legal fp immediate that 5779 // isn't too nasty (eg NaN, denormal, ...). 5780 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 5781 (!LegalOperations || 5782 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 5783 // backend)... we should handle this gracefully after Legalize. 5784 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 5785 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 5786 TLI.isFPImmLegal(Recip, VT))) 5787 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 5788 DAG.getConstantFP(Recip, VT)); 5789 } 5790 5791 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5792 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5793 &DAG.getTarget().Options)) { 5794 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5795 &DAG.getTarget().Options)) { 5796 // Both can be negated for free, check to see if at least one is cheaper 5797 // negated. 5798 if (LHSNeg == 2 || RHSNeg == 2) 5799 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5800 GetNegatedExpression(N0, DAG, LegalOperations), 5801 GetNegatedExpression(N1, DAG, LegalOperations)); 5802 } 5803 } 5804 5805 return SDValue(); 5806} 5807 5808SDValue DAGCombiner::visitFREM(SDNode *N) { 5809 SDValue N0 = N->getOperand(0); 5810 SDValue N1 = N->getOperand(1); 5811 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5812 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5813 EVT VT = N->getValueType(0); 5814 5815 // fold (frem c1, c2) -> fmod(c1,c2) 5816 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5817 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5818 5819 return SDValue(); 5820} 5821 5822SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5823 SDValue N0 = N->getOperand(0); 5824 SDValue N1 = N->getOperand(1); 5825 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5826 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5827 EVT VT = N->getValueType(0); 5828 5829 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5830 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5831 5832 if (N1CFP) { 5833 const APFloat& V = N1CFP->getValueAPF(); 5834 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5835 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5836 if (!V.isNegative()) { 5837 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5838 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5839 } else { 5840 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5841 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5842 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5843 } 5844 } 5845 5846 // copysign(fabs(x), y) -> copysign(x, y) 5847 // copysign(fneg(x), y) -> copysign(x, y) 5848 // copysign(copysign(x,z), y) -> copysign(x, y) 5849 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5850 N0.getOpcode() == ISD::FCOPYSIGN) 5851 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5852 N0.getOperand(0), N1); 5853 5854 // copysign(x, abs(y)) -> abs(x) 5855 if (N1.getOpcode() == ISD::FABS) 5856 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5857 5858 // copysign(x, copysign(y,z)) -> copysign(x, z) 5859 if (N1.getOpcode() == ISD::FCOPYSIGN) 5860 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5861 N0, N1.getOperand(1)); 5862 5863 // copysign(x, fp_extend(y)) -> copysign(x, y) 5864 // copysign(x, fp_round(y)) -> copysign(x, y) 5865 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5866 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5867 N0, N1.getOperand(0)); 5868 5869 return SDValue(); 5870} 5871 5872SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5873 SDValue N0 = N->getOperand(0); 5874 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5875 EVT VT = N->getValueType(0); 5876 EVT OpVT = N0.getValueType(); 5877 5878 // fold (sint_to_fp c1) -> c1fp 5879 if (N0C && OpVT != MVT::ppcf128 && 5880 // ...but only if the target supports immediate floating-point values 5881 (!LegalOperations || 5882 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5883 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5884 5885 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5886 // but UINT_TO_FP is legal on this target, try to convert. 5887 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5888 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5889 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5890 if (DAG.SignBitIsZero(N0)) 5891 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5892 } 5893 5894 return SDValue(); 5895} 5896 5897SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5898 SDValue N0 = N->getOperand(0); 5899 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5900 EVT VT = N->getValueType(0); 5901 EVT OpVT = N0.getValueType(); 5902 5903 // fold (uint_to_fp c1) -> c1fp 5904 if (N0C && OpVT != MVT::ppcf128 && 5905 // ...but only if the target supports immediate floating-point values 5906 (!LegalOperations || 5907 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5908 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5909 5910 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5911 // but SINT_TO_FP is legal on this target, try to convert. 5912 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5913 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5914 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5915 if (DAG.SignBitIsZero(N0)) 5916 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5917 } 5918 5919 return SDValue(); 5920} 5921 5922SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5923 SDValue N0 = N->getOperand(0); 5924 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5925 EVT VT = N->getValueType(0); 5926 5927 // fold (fp_to_sint c1fp) -> c1 5928 if (N0CFP) 5929 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5930 5931 return SDValue(); 5932} 5933 5934SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5935 SDValue N0 = N->getOperand(0); 5936 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5937 EVT VT = N->getValueType(0); 5938 5939 // fold (fp_to_uint c1fp) -> c1 5940 if (N0CFP && VT != MVT::ppcf128) 5941 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5942 5943 return SDValue(); 5944} 5945 5946SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5947 SDValue N0 = N->getOperand(0); 5948 SDValue N1 = N->getOperand(1); 5949 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5950 EVT VT = N->getValueType(0); 5951 5952 // fold (fp_round c1fp) -> c1fp 5953 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5954 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5955 5956 // fold (fp_round (fp_extend x)) -> x 5957 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5958 return N0.getOperand(0); 5959 5960 // fold (fp_round (fp_round x)) -> (fp_round x) 5961 if (N0.getOpcode() == ISD::FP_ROUND) { 5962 // This is a value preserving truncation if both round's are. 5963 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5964 N0.getNode()->getConstantOperandVal(1) == 1; 5965 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5966 DAG.getIntPtrConstant(IsTrunc)); 5967 } 5968 5969 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5970 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5971 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5972 N0.getOperand(0), N1); 5973 AddToWorkList(Tmp.getNode()); 5974 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5975 Tmp, N0.getOperand(1)); 5976 } 5977 5978 return SDValue(); 5979} 5980 5981SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5982 SDValue N0 = N->getOperand(0); 5983 EVT VT = N->getValueType(0); 5984 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5985 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5986 5987 // fold (fp_round_inreg c1fp) -> c1fp 5988 if (N0CFP && isTypeLegal(EVT)) { 5989 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5990 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5991 } 5992 5993 return SDValue(); 5994} 5995 5996SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5997 SDValue N0 = N->getOperand(0); 5998 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5999 EVT VT = N->getValueType(0); 6000 6001 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6002 if (N->hasOneUse() && 6003 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6004 return SDValue(); 6005 6006 // fold (fp_extend c1fp) -> c1fp 6007 if (N0CFP && VT != MVT::ppcf128) 6008 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6009 6010 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6011 // value of X. 6012 if (N0.getOpcode() == ISD::FP_ROUND 6013 && N0.getNode()->getConstantOperandVal(1) == 1) { 6014 SDValue In = N0.getOperand(0); 6015 if (In.getValueType() == VT) return In; 6016 if (VT.bitsLT(In.getValueType())) 6017 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6018 In, N0.getOperand(1)); 6019 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6020 } 6021 6022 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6023 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6024 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6025 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6026 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6027 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6028 LN0->getChain(), 6029 LN0->getBasePtr(), LN0->getPointerInfo(), 6030 N0.getValueType(), 6031 LN0->isVolatile(), LN0->isNonTemporal(), 6032 LN0->getAlignment()); 6033 CombineTo(N, ExtLoad); 6034 CombineTo(N0.getNode(), 6035 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6036 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6037 ExtLoad.getValue(1)); 6038 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6039 } 6040 6041 return SDValue(); 6042} 6043 6044SDValue DAGCombiner::visitFNEG(SDNode *N) { 6045 SDValue N0 = N->getOperand(0); 6046 EVT VT = N->getValueType(0); 6047 6048 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6049 &DAG.getTarget().Options)) 6050 return GetNegatedExpression(N0, DAG, LegalOperations); 6051 6052 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6053 // constant pool values. 6054 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6055 !VT.isVector() && 6056 N0.getNode()->hasOneUse() && 6057 N0.getOperand(0).getValueType().isInteger()) { 6058 SDValue Int = N0.getOperand(0); 6059 EVT IntVT = Int.getValueType(); 6060 if (IntVT.isInteger() && !IntVT.isVector()) { 6061 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6062 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6063 AddToWorkList(Int.getNode()); 6064 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6065 VT, Int); 6066 } 6067 } 6068 6069 return SDValue(); 6070} 6071 6072SDValue DAGCombiner::visitFABS(SDNode *N) { 6073 SDValue N0 = N->getOperand(0); 6074 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6075 EVT VT = N->getValueType(0); 6076 6077 // fold (fabs c1) -> fabs(c1) 6078 if (N0CFP && VT != MVT::ppcf128) 6079 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6080 // fold (fabs (fabs x)) -> (fabs x) 6081 if (N0.getOpcode() == ISD::FABS) 6082 return N->getOperand(0); 6083 // fold (fabs (fneg x)) -> (fabs x) 6084 // fold (fabs (fcopysign x, y)) -> (fabs x) 6085 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6086 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6087 6088 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6089 // constant pool values. 6090 if (!TLI.isFAbsFree(VT) && 6091 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6092 N0.getOperand(0).getValueType().isInteger() && 6093 !N0.getOperand(0).getValueType().isVector()) { 6094 SDValue Int = N0.getOperand(0); 6095 EVT IntVT = Int.getValueType(); 6096 if (IntVT.isInteger() && !IntVT.isVector()) { 6097 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6098 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6099 AddToWorkList(Int.getNode()); 6100 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6101 N->getValueType(0), Int); 6102 } 6103 } 6104 6105 return SDValue(); 6106} 6107 6108SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6109 SDValue Chain = N->getOperand(0); 6110 SDValue N1 = N->getOperand(1); 6111 SDValue N2 = N->getOperand(2); 6112 6113 // If N is a constant we could fold this into a fallthrough or unconditional 6114 // branch. However that doesn't happen very often in normal code, because 6115 // Instcombine/SimplifyCFG should have handled the available opportunities. 6116 // If we did this folding here, it would be necessary to update the 6117 // MachineBasicBlock CFG, which is awkward. 6118 6119 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6120 // on the target. 6121 if (N1.getOpcode() == ISD::SETCC && 6122 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6123 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6124 Chain, N1.getOperand(2), 6125 N1.getOperand(0), N1.getOperand(1), N2); 6126 } 6127 6128 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6129 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6130 (N1.getOperand(0).hasOneUse() && 6131 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6132 SDNode *Trunc = 0; 6133 if (N1.getOpcode() == ISD::TRUNCATE) { 6134 // Look pass the truncate. 6135 Trunc = N1.getNode(); 6136 N1 = N1.getOperand(0); 6137 } 6138 6139 // Match this pattern so that we can generate simpler code: 6140 // 6141 // %a = ... 6142 // %b = and i32 %a, 2 6143 // %c = srl i32 %b, 1 6144 // brcond i32 %c ... 6145 // 6146 // into 6147 // 6148 // %a = ... 6149 // %b = and i32 %a, 2 6150 // %c = setcc eq %b, 0 6151 // brcond %c ... 6152 // 6153 // This applies only when the AND constant value has one bit set and the 6154 // SRL constant is equal to the log2 of the AND constant. The back-end is 6155 // smart enough to convert the result into a TEST/JMP sequence. 6156 SDValue Op0 = N1.getOperand(0); 6157 SDValue Op1 = N1.getOperand(1); 6158 6159 if (Op0.getOpcode() == ISD::AND && 6160 Op1.getOpcode() == ISD::Constant) { 6161 SDValue AndOp1 = Op0.getOperand(1); 6162 6163 if (AndOp1.getOpcode() == ISD::Constant) { 6164 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6165 6166 if (AndConst.isPowerOf2() && 6167 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6168 SDValue SetCC = 6169 DAG.getSetCC(N->getDebugLoc(), 6170 TLI.getSetCCResultType(Op0.getValueType()), 6171 Op0, DAG.getConstant(0, Op0.getValueType()), 6172 ISD::SETNE); 6173 6174 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6175 MVT::Other, Chain, SetCC, N2); 6176 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6177 // will convert it back to (X & C1) >> C2. 6178 CombineTo(N, NewBRCond, false); 6179 // Truncate is dead. 6180 if (Trunc) { 6181 removeFromWorkList(Trunc); 6182 DAG.DeleteNode(Trunc); 6183 } 6184 // Replace the uses of SRL with SETCC 6185 WorkListRemover DeadNodes(*this); 6186 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6187 removeFromWorkList(N1.getNode()); 6188 DAG.DeleteNode(N1.getNode()); 6189 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6190 } 6191 } 6192 } 6193 6194 if (Trunc) 6195 // Restore N1 if the above transformation doesn't match. 6196 N1 = N->getOperand(1); 6197 } 6198 6199 // Transform br(xor(x, y)) -> br(x != y) 6200 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6201 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6202 SDNode *TheXor = N1.getNode(); 6203 SDValue Op0 = TheXor->getOperand(0); 6204 SDValue Op1 = TheXor->getOperand(1); 6205 if (Op0.getOpcode() == Op1.getOpcode()) { 6206 // Avoid missing important xor optimizations. 6207 SDValue Tmp = visitXOR(TheXor); 6208 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6209 DEBUG(dbgs() << "\nReplacing.8 "; 6210 TheXor->dump(&DAG); 6211 dbgs() << "\nWith: "; 6212 Tmp.getNode()->dump(&DAG); 6213 dbgs() << '\n'); 6214 WorkListRemover DeadNodes(*this); 6215 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6216 removeFromWorkList(TheXor); 6217 DAG.DeleteNode(TheXor); 6218 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6219 MVT::Other, Chain, Tmp, N2); 6220 } 6221 } 6222 6223 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6224 bool Equal = false; 6225 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6226 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6227 Op0.getOpcode() == ISD::XOR) { 6228 TheXor = Op0.getNode(); 6229 Equal = true; 6230 } 6231 6232 EVT SetCCVT = N1.getValueType(); 6233 if (LegalTypes) 6234 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6235 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6236 SetCCVT, 6237 Op0, Op1, 6238 Equal ? ISD::SETEQ : ISD::SETNE); 6239 // Replace the uses of XOR with SETCC 6240 WorkListRemover DeadNodes(*this); 6241 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6242 removeFromWorkList(N1.getNode()); 6243 DAG.DeleteNode(N1.getNode()); 6244 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6245 MVT::Other, Chain, SetCC, N2); 6246 } 6247 } 6248 6249 return SDValue(); 6250} 6251 6252// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6253// 6254SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6255 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6256 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6257 6258 // If N is a constant we could fold this into a fallthrough or unconditional 6259 // branch. However that doesn't happen very often in normal code, because 6260 // Instcombine/SimplifyCFG should have handled the available opportunities. 6261 // If we did this folding here, it would be necessary to update the 6262 // MachineBasicBlock CFG, which is awkward. 6263 6264 // Use SimplifySetCC to simplify SETCC's. 6265 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6266 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6267 false); 6268 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6269 6270 // fold to a simpler setcc 6271 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6272 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6273 N->getOperand(0), Simp.getOperand(2), 6274 Simp.getOperand(0), Simp.getOperand(1), 6275 N->getOperand(4)); 6276 6277 return SDValue(); 6278} 6279 6280/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6281/// uses N as its base pointer and that N may be folded in the load / store 6282/// addressing mode. 6283static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6284 SelectionDAG &DAG, 6285 const TargetLowering &TLI) { 6286 EVT VT; 6287 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6288 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6289 return false; 6290 VT = Use->getValueType(0); 6291 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6292 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6293 return false; 6294 VT = ST->getValue().getValueType(); 6295 } else 6296 return false; 6297 6298 TargetLowering::AddrMode AM; 6299 if (N->getOpcode() == ISD::ADD) { 6300 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6301 if (Offset) 6302 // [reg +/- imm] 6303 AM.BaseOffs = Offset->getSExtValue(); 6304 else 6305 // [reg +/- reg] 6306 AM.Scale = 1; 6307 } else if (N->getOpcode() == ISD::SUB) { 6308 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6309 if (Offset) 6310 // [reg +/- imm] 6311 AM.BaseOffs = -Offset->getSExtValue(); 6312 else 6313 // [reg +/- reg] 6314 AM.Scale = 1; 6315 } else 6316 return false; 6317 6318 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6319} 6320 6321/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6322/// pre-indexed load / store when the base pointer is an add or subtract 6323/// and it has other uses besides the load / store. After the 6324/// transformation, the new indexed load / store has effectively folded 6325/// the add / subtract in and all of its other uses are redirected to the 6326/// new load / store. 6327bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6328 if (Level < AfterLegalizeDAG) 6329 return false; 6330 6331 bool isLoad = true; 6332 SDValue Ptr; 6333 EVT VT; 6334 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6335 if (LD->isIndexed()) 6336 return false; 6337 VT = LD->getMemoryVT(); 6338 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6339 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6340 return false; 6341 Ptr = LD->getBasePtr(); 6342 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6343 if (ST->isIndexed()) 6344 return false; 6345 VT = ST->getMemoryVT(); 6346 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6347 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6348 return false; 6349 Ptr = ST->getBasePtr(); 6350 isLoad = false; 6351 } else { 6352 return false; 6353 } 6354 6355 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6356 // out. There is no reason to make this a preinc/predec. 6357 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6358 Ptr.getNode()->hasOneUse()) 6359 return false; 6360 6361 // Ask the target to do addressing mode selection. 6362 SDValue BasePtr; 6363 SDValue Offset; 6364 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6365 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6366 return false; 6367 // Don't create a indexed load / store with zero offset. 6368 if (isa<ConstantSDNode>(Offset) && 6369 cast<ConstantSDNode>(Offset)->isNullValue()) 6370 return false; 6371 6372 // Try turning it into a pre-indexed load / store except when: 6373 // 1) The new base ptr is a frame index. 6374 // 2) If N is a store and the new base ptr is either the same as or is a 6375 // predecessor of the value being stored. 6376 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6377 // that would create a cycle. 6378 // 4) All uses are load / store ops that use it as old base ptr. 6379 6380 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6381 // (plus the implicit offset) to a register to preinc anyway. 6382 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6383 return false; 6384 6385 // Check #2. 6386 if (!isLoad) { 6387 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6388 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6389 return false; 6390 } 6391 6392 // Now check for #3 and #4. 6393 bool RealUse = false; 6394 6395 // Caches for hasPredecessorHelper 6396 SmallPtrSet<const SDNode *, 32> Visited; 6397 SmallVector<const SDNode *, 16> Worklist; 6398 6399 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6400 E = Ptr.getNode()->use_end(); I != E; ++I) { 6401 SDNode *Use = *I; 6402 if (Use == N) 6403 continue; 6404 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6405 return false; 6406 6407 // If Ptr may be folded in addressing mode of other use, then it's 6408 // not profitable to do this transformation. 6409 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6410 RealUse = true; 6411 } 6412 6413 if (!RealUse) 6414 return false; 6415 6416 SDValue Result; 6417 if (isLoad) 6418 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6419 BasePtr, Offset, AM); 6420 else 6421 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6422 BasePtr, Offset, AM); 6423 ++PreIndexedNodes; 6424 ++NodesCombined; 6425 DEBUG(dbgs() << "\nReplacing.4 "; 6426 N->dump(&DAG); 6427 dbgs() << "\nWith: "; 6428 Result.getNode()->dump(&DAG); 6429 dbgs() << '\n'); 6430 WorkListRemover DeadNodes(*this); 6431 if (isLoad) { 6432 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6433 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6434 } else { 6435 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6436 } 6437 6438 // Finally, since the node is now dead, remove it from the graph. 6439 DAG.DeleteNode(N); 6440 6441 // Replace the uses of Ptr with uses of the updated base value. 6442 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 6443 removeFromWorkList(Ptr.getNode()); 6444 DAG.DeleteNode(Ptr.getNode()); 6445 6446 return true; 6447} 6448 6449/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6450/// add / sub of the base pointer node into a post-indexed load / store. 6451/// The transformation folded the add / subtract into the new indexed 6452/// load / store effectively and all of its uses are redirected to the 6453/// new load / store. 6454bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6455 if (Level < AfterLegalizeDAG) 6456 return false; 6457 6458 bool isLoad = true; 6459 SDValue Ptr; 6460 EVT VT; 6461 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6462 if (LD->isIndexed()) 6463 return false; 6464 VT = LD->getMemoryVT(); 6465 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6466 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6467 return false; 6468 Ptr = LD->getBasePtr(); 6469 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6470 if (ST->isIndexed()) 6471 return false; 6472 VT = ST->getMemoryVT(); 6473 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6474 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6475 return false; 6476 Ptr = ST->getBasePtr(); 6477 isLoad = false; 6478 } else { 6479 return false; 6480 } 6481 6482 if (Ptr.getNode()->hasOneUse()) 6483 return false; 6484 6485 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6486 E = Ptr.getNode()->use_end(); I != E; ++I) { 6487 SDNode *Op = *I; 6488 if (Op == N || 6489 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6490 continue; 6491 6492 SDValue BasePtr; 6493 SDValue Offset; 6494 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6495 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6496 // Don't create a indexed load / store with zero offset. 6497 if (isa<ConstantSDNode>(Offset) && 6498 cast<ConstantSDNode>(Offset)->isNullValue()) 6499 continue; 6500 6501 // Try turning it into a post-indexed load / store except when 6502 // 1) All uses are load / store ops that use it as base ptr (and 6503 // it may be folded as addressing mmode). 6504 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6505 // nor a successor of N. Otherwise, if Op is folded that would 6506 // create a cycle. 6507 6508 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6509 continue; 6510 6511 // Check for #1. 6512 bool TryNext = false; 6513 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6514 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6515 SDNode *Use = *II; 6516 if (Use == Ptr.getNode()) 6517 continue; 6518 6519 // If all the uses are load / store addresses, then don't do the 6520 // transformation. 6521 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6522 bool RealUse = false; 6523 for (SDNode::use_iterator III = Use->use_begin(), 6524 EEE = Use->use_end(); III != EEE; ++III) { 6525 SDNode *UseUse = *III; 6526 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6527 RealUse = true; 6528 } 6529 6530 if (!RealUse) { 6531 TryNext = true; 6532 break; 6533 } 6534 } 6535 } 6536 6537 if (TryNext) 6538 continue; 6539 6540 // Check for #2 6541 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6542 SDValue Result = isLoad 6543 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6544 BasePtr, Offset, AM) 6545 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6546 BasePtr, Offset, AM); 6547 ++PostIndexedNodes; 6548 ++NodesCombined; 6549 DEBUG(dbgs() << "\nReplacing.5 "; 6550 N->dump(&DAG); 6551 dbgs() << "\nWith: "; 6552 Result.getNode()->dump(&DAG); 6553 dbgs() << '\n'); 6554 WorkListRemover DeadNodes(*this); 6555 if (isLoad) { 6556 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6557 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6558 } else { 6559 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6560 } 6561 6562 // Finally, since the node is now dead, remove it from the graph. 6563 DAG.DeleteNode(N); 6564 6565 // Replace the uses of Use with uses of the updated base value. 6566 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6567 Result.getValue(isLoad ? 1 : 0)); 6568 removeFromWorkList(Op); 6569 DAG.DeleteNode(Op); 6570 return true; 6571 } 6572 } 6573 } 6574 6575 return false; 6576} 6577 6578SDValue DAGCombiner::visitLOAD(SDNode *N) { 6579 LoadSDNode *LD = cast<LoadSDNode>(N); 6580 SDValue Chain = LD->getChain(); 6581 SDValue Ptr = LD->getBasePtr(); 6582 6583 // If load is not volatile and there are no uses of the loaded value (and 6584 // the updated indexed value in case of indexed loads), change uses of the 6585 // chain value into uses of the chain input (i.e. delete the dead load). 6586 if (!LD->isVolatile()) { 6587 if (N->getValueType(1) == MVT::Other) { 6588 // Unindexed loads. 6589 if (!N->hasAnyUseOfValue(0)) { 6590 // It's not safe to use the two value CombineTo variant here. e.g. 6591 // v1, chain2 = load chain1, loc 6592 // v2, chain3 = load chain2, loc 6593 // v3 = add v2, c 6594 // Now we replace use of chain2 with chain1. This makes the second load 6595 // isomorphic to the one we are deleting, and thus makes this load live. 6596 DEBUG(dbgs() << "\nReplacing.6 "; 6597 N->dump(&DAG); 6598 dbgs() << "\nWith chain: "; 6599 Chain.getNode()->dump(&DAG); 6600 dbgs() << "\n"); 6601 WorkListRemover DeadNodes(*this); 6602 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 6603 6604 if (N->use_empty()) { 6605 removeFromWorkList(N); 6606 DAG.DeleteNode(N); 6607 } 6608 6609 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6610 } 6611 } else { 6612 // Indexed loads. 6613 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 6614 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 6615 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 6616 DEBUG(dbgs() << "\nReplacing.7 "; 6617 N->dump(&DAG); 6618 dbgs() << "\nWith: "; 6619 Undef.getNode()->dump(&DAG); 6620 dbgs() << " and 2 other values\n"); 6621 WorkListRemover DeadNodes(*this); 6622 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 6623 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 6624 DAG.getUNDEF(N->getValueType(1))); 6625 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 6626 removeFromWorkList(N); 6627 DAG.DeleteNode(N); 6628 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6629 } 6630 } 6631 } 6632 6633 // If this load is directly stored, replace the load value with the stored 6634 // value. 6635 // TODO: Handle store large -> read small portion. 6636 // TODO: Handle TRUNCSTORE/LOADEXT 6637 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 6638 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 6639 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 6640 if (PrevST->getBasePtr() == Ptr && 6641 PrevST->getValue().getValueType() == N->getValueType(0)) 6642 return CombineTo(N, Chain.getOperand(1), Chain); 6643 } 6644 } 6645 6646 // Try to infer better alignment information than the load already has. 6647 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 6648 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6649 if (Align > LD->getAlignment()) 6650 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 6651 LD->getValueType(0), 6652 Chain, Ptr, LD->getPointerInfo(), 6653 LD->getMemoryVT(), 6654 LD->isVolatile(), LD->isNonTemporal(), Align); 6655 } 6656 } 6657 6658 if (CombinerAA) { 6659 // Walk up chain skipping non-aliasing memory nodes. 6660 SDValue BetterChain = FindBetterChain(N, Chain); 6661 6662 // If there is a better chain. 6663 if (Chain != BetterChain) { 6664 SDValue ReplLoad; 6665 6666 // Replace the chain to void dependency. 6667 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 6668 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 6669 BetterChain, Ptr, LD->getPointerInfo(), 6670 LD->isVolatile(), LD->isNonTemporal(), 6671 LD->isInvariant(), LD->getAlignment()); 6672 } else { 6673 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 6674 LD->getValueType(0), 6675 BetterChain, Ptr, LD->getPointerInfo(), 6676 LD->getMemoryVT(), 6677 LD->isVolatile(), 6678 LD->isNonTemporal(), 6679 LD->getAlignment()); 6680 } 6681 6682 // Create token factor to keep old chain connected. 6683 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6684 MVT::Other, Chain, ReplLoad.getValue(1)); 6685 6686 // Make sure the new and old chains are cleaned up. 6687 AddToWorkList(Token.getNode()); 6688 6689 // Replace uses with load result and token factor. Don't add users 6690 // to work list. 6691 return CombineTo(N, ReplLoad.getValue(0), Token, false); 6692 } 6693 } 6694 6695 // Try transforming N to an indexed load. 6696 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6697 return SDValue(N, 0); 6698 6699 return SDValue(); 6700} 6701 6702/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 6703/// load is having specific bytes cleared out. If so, return the byte size 6704/// being masked out and the shift amount. 6705static std::pair<unsigned, unsigned> 6706CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 6707 std::pair<unsigned, unsigned> Result(0, 0); 6708 6709 // Check for the structure we're looking for. 6710 if (V->getOpcode() != ISD::AND || 6711 !isa<ConstantSDNode>(V->getOperand(1)) || 6712 !ISD::isNormalLoad(V->getOperand(0).getNode())) 6713 return Result; 6714 6715 // Check the chain and pointer. 6716 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 6717 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 6718 6719 // The store should be chained directly to the load or be an operand of a 6720 // tokenfactor. 6721 if (LD == Chain.getNode()) 6722 ; // ok. 6723 else if (Chain->getOpcode() != ISD::TokenFactor) 6724 return Result; // Fail. 6725 else { 6726 bool isOk = false; 6727 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 6728 if (Chain->getOperand(i).getNode() == LD) { 6729 isOk = true; 6730 break; 6731 } 6732 if (!isOk) return Result; 6733 } 6734 6735 // This only handles simple types. 6736 if (V.getValueType() != MVT::i16 && 6737 V.getValueType() != MVT::i32 && 6738 V.getValueType() != MVT::i64) 6739 return Result; 6740 6741 // Check the constant mask. Invert it so that the bits being masked out are 6742 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6743 // follow the sign bit for uniformity. 6744 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6745 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6746 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6747 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6748 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6749 if (NotMaskLZ == 64) return Result; // All zero mask. 6750 6751 // See if we have a continuous run of bits. If so, we have 0*1+0* 6752 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6753 return Result; 6754 6755 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6756 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6757 NotMaskLZ -= 64-V.getValueSizeInBits(); 6758 6759 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6760 switch (MaskedBytes) { 6761 case 1: 6762 case 2: 6763 case 4: break; 6764 default: return Result; // All one mask, or 5-byte mask. 6765 } 6766 6767 // Verify that the first bit starts at a multiple of mask so that the access 6768 // is aligned the same as the access width. 6769 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6770 6771 Result.first = MaskedBytes; 6772 Result.second = NotMaskTZ/8; 6773 return Result; 6774} 6775 6776 6777/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6778/// provides a value as specified by MaskInfo. If so, replace the specified 6779/// store with a narrower store of truncated IVal. 6780static SDNode * 6781ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6782 SDValue IVal, StoreSDNode *St, 6783 DAGCombiner *DC) { 6784 unsigned NumBytes = MaskInfo.first; 6785 unsigned ByteShift = MaskInfo.second; 6786 SelectionDAG &DAG = DC->getDAG(); 6787 6788 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6789 // that uses this. If not, this is not a replacement. 6790 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6791 ByteShift*8, (ByteShift+NumBytes)*8); 6792 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6793 6794 // Check that it is legal on the target to do this. It is legal if the new 6795 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6796 // legalization. 6797 MVT VT = MVT::getIntegerVT(NumBytes*8); 6798 if (!DC->isTypeLegal(VT)) 6799 return 0; 6800 6801 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6802 // shifted by ByteShift and truncated down to NumBytes. 6803 if (ByteShift) 6804 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6805 DAG.getConstant(ByteShift*8, 6806 DC->getShiftAmountTy(IVal.getValueType()))); 6807 6808 // Figure out the offset for the store and the alignment of the access. 6809 unsigned StOffset; 6810 unsigned NewAlign = St->getAlignment(); 6811 6812 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6813 StOffset = ByteShift; 6814 else 6815 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6816 6817 SDValue Ptr = St->getBasePtr(); 6818 if (StOffset) { 6819 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6820 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6821 NewAlign = MinAlign(NewAlign, StOffset); 6822 } 6823 6824 // Truncate down to the new size. 6825 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6826 6827 ++OpsNarrowed; 6828 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6829 St->getPointerInfo().getWithOffset(StOffset), 6830 false, false, NewAlign).getNode(); 6831} 6832 6833 6834/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6835/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6836/// of the loaded bits, try narrowing the load and store if it would end up 6837/// being a win for performance or code size. 6838SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6839 StoreSDNode *ST = cast<StoreSDNode>(N); 6840 if (ST->isVolatile()) 6841 return SDValue(); 6842 6843 SDValue Chain = ST->getChain(); 6844 SDValue Value = ST->getValue(); 6845 SDValue Ptr = ST->getBasePtr(); 6846 EVT VT = Value.getValueType(); 6847 6848 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6849 return SDValue(); 6850 6851 unsigned Opc = Value.getOpcode(); 6852 6853 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6854 // is a byte mask indicating a consecutive number of bytes, check to see if 6855 // Y is known to provide just those bytes. If so, we try to replace the 6856 // load + replace + store sequence with a single (narrower) store, which makes 6857 // the load dead. 6858 if (Opc == ISD::OR) { 6859 std::pair<unsigned, unsigned> MaskedLoad; 6860 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6861 if (MaskedLoad.first) 6862 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6863 Value.getOperand(1), ST,this)) 6864 return SDValue(NewST, 0); 6865 6866 // Or is commutative, so try swapping X and Y. 6867 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6868 if (MaskedLoad.first) 6869 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6870 Value.getOperand(0), ST,this)) 6871 return SDValue(NewST, 0); 6872 } 6873 6874 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6875 Value.getOperand(1).getOpcode() != ISD::Constant) 6876 return SDValue(); 6877 6878 SDValue N0 = Value.getOperand(0); 6879 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6880 Chain == SDValue(N0.getNode(), 1)) { 6881 LoadSDNode *LD = cast<LoadSDNode>(N0); 6882 if (LD->getBasePtr() != Ptr || 6883 LD->getPointerInfo().getAddrSpace() != 6884 ST->getPointerInfo().getAddrSpace()) 6885 return SDValue(); 6886 6887 // Find the type to narrow it the load / op / store to. 6888 SDValue N1 = Value.getOperand(1); 6889 unsigned BitWidth = N1.getValueSizeInBits(); 6890 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6891 if (Opc == ISD::AND) 6892 Imm ^= APInt::getAllOnesValue(BitWidth); 6893 if (Imm == 0 || Imm.isAllOnesValue()) 6894 return SDValue(); 6895 unsigned ShAmt = Imm.countTrailingZeros(); 6896 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6897 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6898 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6899 while (NewBW < BitWidth && 6900 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6901 TLI.isNarrowingProfitable(VT, NewVT))) { 6902 NewBW = NextPowerOf2(NewBW); 6903 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6904 } 6905 if (NewBW >= BitWidth) 6906 return SDValue(); 6907 6908 // If the lsb changed does not start at the type bitwidth boundary, 6909 // start at the previous one. 6910 if (ShAmt % NewBW) 6911 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6912 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6913 if ((Imm & Mask) == Imm) { 6914 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6915 if (Opc == ISD::AND) 6916 NewImm ^= APInt::getAllOnesValue(NewBW); 6917 uint64_t PtrOff = ShAmt / 8; 6918 // For big endian targets, we need to adjust the offset to the pointer to 6919 // load the correct bytes. 6920 if (TLI.isBigEndian()) 6921 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6922 6923 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6924 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6925 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6926 return SDValue(); 6927 6928 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6929 Ptr.getValueType(), Ptr, 6930 DAG.getConstant(PtrOff, Ptr.getValueType())); 6931 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6932 LD->getChain(), NewPtr, 6933 LD->getPointerInfo().getWithOffset(PtrOff), 6934 LD->isVolatile(), LD->isNonTemporal(), 6935 LD->isInvariant(), NewAlign); 6936 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6937 DAG.getConstant(NewImm, NewVT)); 6938 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6939 NewVal, NewPtr, 6940 ST->getPointerInfo().getWithOffset(PtrOff), 6941 false, false, NewAlign); 6942 6943 AddToWorkList(NewPtr.getNode()); 6944 AddToWorkList(NewLD.getNode()); 6945 AddToWorkList(NewVal.getNode()); 6946 WorkListRemover DeadNodes(*this); 6947 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 6948 ++OpsNarrowed; 6949 return NewST; 6950 } 6951 } 6952 6953 return SDValue(); 6954} 6955 6956/// TransformFPLoadStorePair - For a given floating point load / store pair, 6957/// if the load value isn't used by any other operations, then consider 6958/// transforming the pair to integer load / store operations if the target 6959/// deems the transformation profitable. 6960SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6961 StoreSDNode *ST = cast<StoreSDNode>(N); 6962 SDValue Chain = ST->getChain(); 6963 SDValue Value = ST->getValue(); 6964 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6965 Value.hasOneUse() && 6966 Chain == SDValue(Value.getNode(), 1)) { 6967 LoadSDNode *LD = cast<LoadSDNode>(Value); 6968 EVT VT = LD->getMemoryVT(); 6969 if (!VT.isFloatingPoint() || 6970 VT != ST->getMemoryVT() || 6971 LD->isNonTemporal() || 6972 ST->isNonTemporal() || 6973 LD->getPointerInfo().getAddrSpace() != 0 || 6974 ST->getPointerInfo().getAddrSpace() != 0) 6975 return SDValue(); 6976 6977 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6978 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6979 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6980 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6981 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6982 return SDValue(); 6983 6984 unsigned LDAlign = LD->getAlignment(); 6985 unsigned STAlign = ST->getAlignment(); 6986 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6987 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6988 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6989 return SDValue(); 6990 6991 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6992 LD->getChain(), LD->getBasePtr(), 6993 LD->getPointerInfo(), 6994 false, false, false, LDAlign); 6995 6996 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6997 NewLD, ST->getBasePtr(), 6998 ST->getPointerInfo(), 6999 false, false, STAlign); 7000 7001 AddToWorkList(NewLD.getNode()); 7002 AddToWorkList(NewST.getNode()); 7003 WorkListRemover DeadNodes(*this); 7004 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7005 ++LdStFP2Int; 7006 return NewST; 7007 } 7008 7009 return SDValue(); 7010} 7011 7012SDValue DAGCombiner::visitSTORE(SDNode *N) { 7013 StoreSDNode *ST = cast<StoreSDNode>(N); 7014 SDValue Chain = ST->getChain(); 7015 SDValue Value = ST->getValue(); 7016 SDValue Ptr = ST->getBasePtr(); 7017 7018 // If this is a store of a bit convert, store the input value if the 7019 // resultant store does not need a higher alignment than the original. 7020 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 7021 ST->isUnindexed()) { 7022 unsigned OrigAlign = ST->getAlignment(); 7023 EVT SVT = Value.getOperand(0).getValueType(); 7024 unsigned Align = TLI.getTargetData()-> 7025 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 7026 if (Align <= OrigAlign && 7027 ((!LegalOperations && !ST->isVolatile()) || 7028 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 7029 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7030 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7031 ST->isNonTemporal(), OrigAlign); 7032 } 7033 7034 // Turn 'store undef, Ptr' -> nothing. 7035 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 7036 return Chain; 7037 7038 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 7039 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 7040 // NOTE: If the original store is volatile, this transform must not increase 7041 // the number of stores. For example, on x86-32 an f64 can be stored in one 7042 // processor operation but an i64 (which is not legal) requires two. So the 7043 // transform should not be done in this case. 7044 if (Value.getOpcode() != ISD::TargetConstantFP) { 7045 SDValue Tmp; 7046 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 7047 default: llvm_unreachable("Unknown FP type"); 7048 case MVT::f80: // We don't do this for these yet. 7049 case MVT::f128: 7050 case MVT::ppcf128: 7051 break; 7052 case MVT::f32: 7053 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 7054 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7055 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 7056 bitcastToAPInt().getZExtValue(), MVT::i32); 7057 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7058 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7059 ST->isNonTemporal(), ST->getAlignment()); 7060 } 7061 break; 7062 case MVT::f64: 7063 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 7064 !ST->isVolatile()) || 7065 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 7066 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 7067 getZExtValue(), MVT::i64); 7068 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7069 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7070 ST->isNonTemporal(), ST->getAlignment()); 7071 } 7072 7073 if (!ST->isVolatile() && 7074 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7075 // Many FP stores are not made apparent until after legalize, e.g. for 7076 // argument passing. Since this is so common, custom legalize the 7077 // 64-bit integer store into two 32-bit stores. 7078 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 7079 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 7080 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 7081 if (TLI.isBigEndian()) std::swap(Lo, Hi); 7082 7083 unsigned Alignment = ST->getAlignment(); 7084 bool isVolatile = ST->isVolatile(); 7085 bool isNonTemporal = ST->isNonTemporal(); 7086 7087 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 7088 Ptr, ST->getPointerInfo(), 7089 isVolatile, isNonTemporal, 7090 ST->getAlignment()); 7091 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 7092 DAG.getConstant(4, Ptr.getValueType())); 7093 Alignment = MinAlign(Alignment, 4U); 7094 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 7095 Ptr, ST->getPointerInfo().getWithOffset(4), 7096 isVolatile, isNonTemporal, 7097 Alignment); 7098 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7099 St0, St1); 7100 } 7101 7102 break; 7103 } 7104 } 7105 } 7106 7107 // Try to infer better alignment information than the store already has. 7108 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 7109 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7110 if (Align > ST->getAlignment()) 7111 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 7112 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7113 ST->isVolatile(), ST->isNonTemporal(), Align); 7114 } 7115 } 7116 7117 // Try transforming a pair floating point load / store ops to integer 7118 // load / store ops. 7119 SDValue NewST = TransformFPLoadStorePair(N); 7120 if (NewST.getNode()) 7121 return NewST; 7122 7123 if (CombinerAA) { 7124 // Walk up chain skipping non-aliasing memory nodes. 7125 SDValue BetterChain = FindBetterChain(N, Chain); 7126 7127 // If there is a better chain. 7128 if (Chain != BetterChain) { 7129 SDValue ReplStore; 7130 7131 // Replace the chain to avoid dependency. 7132 if (ST->isTruncatingStore()) { 7133 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7134 ST->getPointerInfo(), 7135 ST->getMemoryVT(), ST->isVolatile(), 7136 ST->isNonTemporal(), ST->getAlignment()); 7137 } else { 7138 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7139 ST->getPointerInfo(), 7140 ST->isVolatile(), ST->isNonTemporal(), 7141 ST->getAlignment()); 7142 } 7143 7144 // Create token to keep both nodes around. 7145 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7146 MVT::Other, Chain, ReplStore); 7147 7148 // Make sure the new and old chains are cleaned up. 7149 AddToWorkList(Token.getNode()); 7150 7151 // Don't add users to work list. 7152 return CombineTo(N, Token, false); 7153 } 7154 } 7155 7156 // Try transforming N to an indexed store. 7157 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7158 return SDValue(N, 0); 7159 7160 // FIXME: is there such a thing as a truncating indexed store? 7161 if (ST->isTruncatingStore() && ST->isUnindexed() && 7162 Value.getValueType().isInteger()) { 7163 // See if we can simplify the input to this truncstore with knowledge that 7164 // only the low bits are being used. For example: 7165 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 7166 SDValue Shorter = 7167 GetDemandedBits(Value, 7168 APInt::getLowBitsSet( 7169 Value.getValueType().getScalarType().getSizeInBits(), 7170 ST->getMemoryVT().getScalarType().getSizeInBits())); 7171 AddToWorkList(Value.getNode()); 7172 if (Shorter.getNode()) 7173 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 7174 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7175 ST->isVolatile(), ST->isNonTemporal(), 7176 ST->getAlignment()); 7177 7178 // Otherwise, see if we can simplify the operation with 7179 // SimplifyDemandedBits, which only works if the value has a single use. 7180 if (SimplifyDemandedBits(Value, 7181 APInt::getLowBitsSet( 7182 Value.getValueType().getScalarType().getSizeInBits(), 7183 ST->getMemoryVT().getScalarType().getSizeInBits()))) 7184 return SDValue(N, 0); 7185 } 7186 7187 // If this is a load followed by a store to the same location, then the store 7188 // is dead/noop. 7189 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 7190 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 7191 ST->isUnindexed() && !ST->isVolatile() && 7192 // There can't be any side effects between the load and store, such as 7193 // a call or store. 7194 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 7195 // The store is dead, remove it. 7196 return Chain; 7197 } 7198 } 7199 7200 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 7201 // truncating store. We can do this even if this is already a truncstore. 7202 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 7203 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 7204 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 7205 ST->getMemoryVT())) { 7206 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7207 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7208 ST->isVolatile(), ST->isNonTemporal(), 7209 ST->getAlignment()); 7210 } 7211 7212 return ReduceLoadOpStoreWidth(N); 7213} 7214 7215SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 7216 SDValue InVec = N->getOperand(0); 7217 SDValue InVal = N->getOperand(1); 7218 SDValue EltNo = N->getOperand(2); 7219 DebugLoc dl = N->getDebugLoc(); 7220 7221 // If the inserted element is an UNDEF, just use the input vector. 7222 if (InVal.getOpcode() == ISD::UNDEF) 7223 return InVec; 7224 7225 EVT VT = InVec.getValueType(); 7226 7227 // If we can't generate a legal BUILD_VECTOR, exit 7228 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 7229 return SDValue(); 7230 7231 // Check that we know which element is being inserted 7232 if (!isa<ConstantSDNode>(EltNo)) 7233 return SDValue(); 7234 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7235 7236 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 7237 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 7238 // vector elements. 7239 SmallVector<SDValue, 8> Ops; 7240 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 7241 Ops.append(InVec.getNode()->op_begin(), 7242 InVec.getNode()->op_end()); 7243 } else if (InVec.getOpcode() == ISD::UNDEF) { 7244 unsigned NElts = VT.getVectorNumElements(); 7245 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 7246 } else { 7247 return SDValue(); 7248 } 7249 7250 // Insert the element 7251 if (Elt < Ops.size()) { 7252 // All the operands of BUILD_VECTOR must have the same type; 7253 // we enforce that here. 7254 EVT OpVT = Ops[0].getValueType(); 7255 if (InVal.getValueType() != OpVT) 7256 InVal = OpVT.bitsGT(InVal.getValueType()) ? 7257 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 7258 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 7259 Ops[Elt] = InVal; 7260 } 7261 7262 // Return the new vector 7263 return DAG.getNode(ISD::BUILD_VECTOR, dl, 7264 VT, &Ops[0], Ops.size()); 7265} 7266 7267SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 7268 // (vextract (scalar_to_vector val, 0) -> val 7269 SDValue InVec = N->getOperand(0); 7270 EVT VT = InVec.getValueType(); 7271 EVT NVT = N->getValueType(0); 7272 7273 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 7274 // Check if the result type doesn't match the inserted element type. A 7275 // SCALAR_TO_VECTOR may truncate the inserted element and the 7276 // EXTRACT_VECTOR_ELT may widen the extracted vector. 7277 SDValue InOp = InVec.getOperand(0); 7278 if (InOp.getValueType() != NVT) { 7279 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 7280 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 7281 } 7282 return InOp; 7283 } 7284 7285 SDValue EltNo = N->getOperand(1); 7286 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 7287 7288 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 7289 // We only perform this optimization before the op legalization phase because 7290 // we may introduce new vector instructions which are not backed by TD patterns. 7291 // For example on AVX, extracting elements from a wide vector without using 7292 // extract_subvector. 7293 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 7294 && ConstEltNo && !LegalOperations) { 7295 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7296 int NumElem = VT.getVectorNumElements(); 7297 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 7298 // Find the new index to extract from. 7299 int OrigElt = SVOp->getMaskElt(Elt); 7300 7301 // Extracting an undef index is undef. 7302 if (OrigElt == -1) 7303 return DAG.getUNDEF(NVT); 7304 7305 // Select the right vector half to extract from. 7306 if (OrigElt < NumElem) { 7307 InVec = InVec->getOperand(0); 7308 } else { 7309 InVec = InVec->getOperand(1); 7310 OrigElt -= NumElem; 7311 } 7312 7313 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 7314 InVec, DAG.getConstant(OrigElt, MVT::i32)); 7315 } 7316 7317 // Perform only after legalization to ensure build_vector / vector_shuffle 7318 // optimizations have already been done. 7319 if (!LegalOperations) return SDValue(); 7320 7321 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 7322 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 7323 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 7324 7325 if (ConstEltNo) { 7326 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7327 bool NewLoad = false; 7328 bool BCNumEltsChanged = false; 7329 EVT ExtVT = VT.getVectorElementType(); 7330 EVT LVT = ExtVT; 7331 7332 // If the result of load has to be truncated, then it's not necessarily 7333 // profitable. 7334 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 7335 return SDValue(); 7336 7337 if (InVec.getOpcode() == ISD::BITCAST) { 7338 // Don't duplicate a load with other uses. 7339 if (!InVec.hasOneUse()) 7340 return SDValue(); 7341 7342 EVT BCVT = InVec.getOperand(0).getValueType(); 7343 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 7344 return SDValue(); 7345 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 7346 BCNumEltsChanged = true; 7347 InVec = InVec.getOperand(0); 7348 ExtVT = BCVT.getVectorElementType(); 7349 NewLoad = true; 7350 } 7351 7352 LoadSDNode *LN0 = NULL; 7353 const ShuffleVectorSDNode *SVN = NULL; 7354 if (ISD::isNormalLoad(InVec.getNode())) { 7355 LN0 = cast<LoadSDNode>(InVec); 7356 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 7357 InVec.getOperand(0).getValueType() == ExtVT && 7358 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 7359 // Don't duplicate a load with other uses. 7360 if (!InVec.hasOneUse()) 7361 return SDValue(); 7362 7363 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 7364 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 7365 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 7366 // => 7367 // (load $addr+1*size) 7368 7369 // Don't duplicate a load with other uses. 7370 if (!InVec.hasOneUse()) 7371 return SDValue(); 7372 7373 // If the bit convert changed the number of elements, it is unsafe 7374 // to examine the mask. 7375 if (BCNumEltsChanged) 7376 return SDValue(); 7377 7378 // Select the input vector, guarding against out of range extract vector. 7379 unsigned NumElems = VT.getVectorNumElements(); 7380 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7381 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7382 7383 if (InVec.getOpcode() == ISD::BITCAST) { 7384 // Don't duplicate a load with other uses. 7385 if (!InVec.hasOneUse()) 7386 return SDValue(); 7387 7388 InVec = InVec.getOperand(0); 7389 } 7390 if (ISD::isNormalLoad(InVec.getNode())) { 7391 LN0 = cast<LoadSDNode>(InVec); 7392 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7393 } 7394 } 7395 7396 // Make sure we found a non-volatile load and the extractelement is 7397 // the only use. 7398 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7399 return SDValue(); 7400 7401 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7402 if (Elt == -1) 7403 return DAG.getUNDEF(LVT); 7404 7405 unsigned Align = LN0->getAlignment(); 7406 if (NewLoad) { 7407 // Check the resultant load doesn't need a higher alignment than the 7408 // original load. 7409 unsigned NewAlign = 7410 TLI.getTargetData() 7411 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7412 7413 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7414 return SDValue(); 7415 7416 Align = NewAlign; 7417 } 7418 7419 SDValue NewPtr = LN0->getBasePtr(); 7420 unsigned PtrOff = 0; 7421 7422 if (Elt) { 7423 PtrOff = LVT.getSizeInBits() * Elt / 8; 7424 EVT PtrType = NewPtr.getValueType(); 7425 if (TLI.isBigEndian()) 7426 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7427 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7428 DAG.getConstant(PtrOff, PtrType)); 7429 } 7430 7431 // The replacement we need to do here is a little tricky: we need to 7432 // replace an extractelement of a load with a load. 7433 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7434 // Note that this replacement assumes that the extractvalue is the only 7435 // use of the load; that's okay because we don't want to perform this 7436 // transformation in other cases anyway. 7437 SDValue Load; 7438 SDValue Chain; 7439 if (NVT.bitsGT(LVT)) { 7440 // If the result type of vextract is wider than the load, then issue an 7441 // extending load instead. 7442 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 7443 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 7444 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 7445 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 7446 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 7447 Chain = Load.getValue(1); 7448 } else { 7449 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7450 LN0->getPointerInfo().getWithOffset(PtrOff), 7451 LN0->isVolatile(), LN0->isNonTemporal(), 7452 LN0->isInvariant(), Align); 7453 Chain = Load.getValue(1); 7454 if (NVT.bitsLT(LVT)) 7455 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 7456 else 7457 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 7458 } 7459 WorkListRemover DeadNodes(*this); 7460 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7461 SDValue To[] = { Load, Chain }; 7462 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 7463 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7464 // worklist explicitly as well. 7465 AddToWorkList(Load.getNode()); 7466 AddUsersToWorkList(Load.getNode()); // Add users too 7467 // Make sure to revisit this node to clean it up; it will usually be dead. 7468 AddToWorkList(N); 7469 return SDValue(N, 0); 7470 } 7471 7472 return SDValue(); 7473} 7474 7475SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7476 unsigned NumInScalars = N->getNumOperands(); 7477 DebugLoc dl = N->getDebugLoc(); 7478 EVT VT = N->getValueType(0); 7479 // Check to see if this is a BUILD_VECTOR of a bunch of values 7480 // which come from any_extend or zero_extend nodes. If so, we can create 7481 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7482 // optimizations. We do not handle sign-extend because we can't fill the sign 7483 // using shuffles. 7484 EVT SourceType = MVT::Other; 7485 bool AllAnyExt = true; 7486 bool AllUndef = true; 7487 for (unsigned i = 0; i != NumInScalars; ++i) { 7488 SDValue In = N->getOperand(i); 7489 // Ignore undef inputs. 7490 if (In.getOpcode() == ISD::UNDEF) continue; 7491 AllUndef = false; 7492 7493 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7494 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7495 7496 // Abort if the element is not an extension. 7497 if (!ZeroExt && !AnyExt) { 7498 SourceType = MVT::Other; 7499 break; 7500 } 7501 7502 // The input is a ZeroExt or AnyExt. Check the original type. 7503 EVT InTy = In.getOperand(0).getValueType(); 7504 7505 // Check that all of the widened source types are the same. 7506 if (SourceType == MVT::Other) 7507 // First time. 7508 SourceType = InTy; 7509 else if (InTy != SourceType) { 7510 // Multiple income types. Abort. 7511 SourceType = MVT::Other; 7512 break; 7513 } 7514 7515 // Check if all of the extends are ANY_EXTENDs. 7516 AllAnyExt &= AnyExt; 7517 } 7518 7519 if (AllUndef) 7520 return DAG.getUNDEF(VT); 7521 7522 // In order to have valid types, all of the inputs must be extended from the 7523 // same source type and all of the inputs must be any or zero extend. 7524 // Scalar sizes must be a power of two. 7525 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7526 bool ValidTypes = SourceType != MVT::Other && 7527 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7528 isPowerOf2_32(SourceType.getSizeInBits()); 7529 7530 // We perform this optimization post type-legalization because 7531 // the type-legalizer often scalarizes integer-promoted vectors. 7532 // Performing this optimization before may create bit-casts which 7533 // will be type-legalized to complex code sequences. 7534 // We perform this optimization only before the operation legalizer because we 7535 // may introduce illegal operations. 7536 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 7537 // turn into a single shuffle instruction. 7538 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 7539 ValidTypes) { 7540 bool isLE = TLI.isLittleEndian(); 7541 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7542 assert(ElemRatio > 1 && "Invalid element size ratio"); 7543 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 7544 DAG.getConstant(0, SourceType); 7545 7546 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7547 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7548 7549 // Populate the new build_vector 7550 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7551 SDValue Cast = N->getOperand(i); 7552 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7553 Cast.getOpcode() == ISD::ZERO_EXTEND || 7554 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7555 SDValue In; 7556 if (Cast.getOpcode() == ISD::UNDEF) 7557 In = DAG.getUNDEF(SourceType); 7558 else 7559 In = Cast->getOperand(0); 7560 unsigned Index = isLE ? (i * ElemRatio) : 7561 (i * ElemRatio + (ElemRatio - 1)); 7562 7563 assert(Index < Ops.size() && "Invalid index"); 7564 Ops[Index] = In; 7565 } 7566 7567 // The type of the new BUILD_VECTOR node. 7568 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 7569 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 7570 "Invalid vector size"); 7571 // Check if the new vector type is legal. 7572 if (!isTypeLegal(VecVT)) return SDValue(); 7573 7574 // Make the new BUILD_VECTOR. 7575 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7576 VecVT, &Ops[0], Ops.size()); 7577 7578 // The new BUILD_VECTOR node has the potential to be further optimized. 7579 AddToWorkList(BV.getNode()); 7580 // Bitcast to the desired type. 7581 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 7582 } 7583 7584 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 7585 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 7586 // at most two distinct vectors, turn this into a shuffle node. 7587 7588 // May only combine to shuffle after legalize if shuffle is legal. 7589 if (LegalOperations && 7590 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 7591 return SDValue(); 7592 7593 SDValue VecIn1, VecIn2; 7594 for (unsigned i = 0; i != NumInScalars; ++i) { 7595 // Ignore undef inputs. 7596 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 7597 7598 // If this input is something other than a EXTRACT_VECTOR_ELT with a 7599 // constant index, bail out. 7600 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 7601 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 7602 VecIn1 = VecIn2 = SDValue(0, 0); 7603 break; 7604 } 7605 7606 // We allow up to two distinct input vectors. 7607 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 7608 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 7609 continue; 7610 7611 if (VecIn1.getNode() == 0) { 7612 VecIn1 = ExtractedFromVec; 7613 } else if (VecIn2.getNode() == 0) { 7614 VecIn2 = ExtractedFromVec; 7615 } else { 7616 // Too many inputs. 7617 VecIn1 = VecIn2 = SDValue(0, 0); 7618 break; 7619 } 7620 } 7621 7622 // If everything is good, we can make a shuffle operation. 7623 if (VecIn1.getNode()) { 7624 SmallVector<int, 8> Mask; 7625 for (unsigned i = 0; i != NumInScalars; ++i) { 7626 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 7627 Mask.push_back(-1); 7628 continue; 7629 } 7630 7631 // If extracting from the first vector, just use the index directly. 7632 SDValue Extract = N->getOperand(i); 7633 SDValue ExtVal = Extract.getOperand(1); 7634 if (Extract.getOperand(0) == VecIn1) { 7635 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7636 if (ExtIndex > VT.getVectorNumElements()) 7637 return SDValue(); 7638 7639 Mask.push_back(ExtIndex); 7640 continue; 7641 } 7642 7643 // Otherwise, use InIdx + VecSize 7644 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7645 Mask.push_back(Idx+NumInScalars); 7646 } 7647 7648 // We can't generate a shuffle node with mismatched input and output types. 7649 // Attempt to transform a single input vector to the correct type. 7650 if ((VT != VecIn1.getValueType())) { 7651 // We don't support shuffeling between TWO values of different types. 7652 if (VecIn2.getNode() != 0) 7653 return SDValue(); 7654 7655 // We only support widening of vectors which are half the size of the 7656 // output registers. For example XMM->YMM widening on X86 with AVX. 7657 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 7658 return SDValue(); 7659 7660 // Widen the input vector by adding undef values. 7661 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7662 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 7663 } 7664 7665 // If VecIn2 is unused then change it to undef. 7666 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 7667 7668 // Check that we were able to transform all incoming values to the same type. 7669 if (VecIn2.getValueType() != VecIn1.getValueType() || 7670 VecIn1.getValueType() != VT) 7671 return SDValue(); 7672 7673 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 7674 if (!isTypeLegal(VT)) 7675 return SDValue(); 7676 7677 // Return the new VECTOR_SHUFFLE node. 7678 SDValue Ops[2]; 7679 Ops[0] = VecIn1; 7680 Ops[1] = VecIn2; 7681 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 7682 } 7683 7684 return SDValue(); 7685} 7686 7687SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 7688 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 7689 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 7690 // inputs come from at most two distinct vectors, turn this into a shuffle 7691 // node. 7692 7693 // If we only have one input vector, we don't need to do any concatenation. 7694 if (N->getNumOperands() == 1) 7695 return N->getOperand(0); 7696 7697 return SDValue(); 7698} 7699 7700SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 7701 EVT NVT = N->getValueType(0); 7702 SDValue V = N->getOperand(0); 7703 7704 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 7705 // Handle only simple case where vector being inserted and vector 7706 // being extracted are of same type, and are half size of larger vectors. 7707 EVT BigVT = V->getOperand(0).getValueType(); 7708 EVT SmallVT = V->getOperand(1).getValueType(); 7709 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 7710 return SDValue(); 7711 7712 // Only handle cases where both indexes are constants with the same type. 7713 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7714 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 7715 7716 if (InsIdx && ExtIdx && 7717 InsIdx->getValueType(0).getSizeInBits() <= 64 && 7718 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 7719 // Combine: 7720 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 7721 // Into: 7722 // indices are equal => V1 7723 // otherwise => (extract_subvec V1, ExtIdx) 7724 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 7725 return V->getOperand(1); 7726 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 7727 V->getOperand(0), N->getOperand(1)); 7728 } 7729 } 7730 7731 return SDValue(); 7732} 7733 7734SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 7735 EVT VT = N->getValueType(0); 7736 unsigned NumElts = VT.getVectorNumElements(); 7737 7738 SDValue N0 = N->getOperand(0); 7739 SDValue N1 = N->getOperand(1); 7740 7741 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 7742 7743 // Canonicalize shuffle undef, undef -> undef 7744 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 7745 return DAG.getUNDEF(VT); 7746 7747 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7748 7749 // Canonicalize shuffle v, v -> v, undef 7750 if (N0 == N1) { 7751 SmallVector<int, 8> NewMask; 7752 for (unsigned i = 0; i != NumElts; ++i) { 7753 int Idx = SVN->getMaskElt(i); 7754 if (Idx >= (int)NumElts) Idx -= NumElts; 7755 NewMask.push_back(Idx); 7756 } 7757 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 7758 &NewMask[0]); 7759 } 7760 7761 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 7762 if (N0.getOpcode() == ISD::UNDEF) { 7763 SmallVector<int, 8> NewMask; 7764 for (unsigned i = 0; i != NumElts; ++i) { 7765 int Idx = SVN->getMaskElt(i); 7766 if (Idx >= 0) { 7767 if (Idx < (int)NumElts) 7768 Idx += NumElts; 7769 else 7770 Idx -= NumElts; 7771 } 7772 NewMask.push_back(Idx); 7773 } 7774 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 7775 &NewMask[0]); 7776 } 7777 7778 // Remove references to rhs if it is undef 7779 if (N1.getOpcode() == ISD::UNDEF) { 7780 bool Changed = false; 7781 SmallVector<int, 8> NewMask; 7782 for (unsigned i = 0; i != NumElts; ++i) { 7783 int Idx = SVN->getMaskElt(i); 7784 if (Idx >= (int)NumElts) { 7785 Idx = -1; 7786 Changed = true; 7787 } 7788 NewMask.push_back(Idx); 7789 } 7790 if (Changed) 7791 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 7792 } 7793 7794 // If it is a splat, check if the argument vector is another splat or a 7795 // build_vector with all scalar elements the same. 7796 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 7797 SDNode *V = N0.getNode(); 7798 7799 // If this is a bit convert that changes the element type of the vector but 7800 // not the number of vector elements, look through it. Be careful not to 7801 // look though conversions that change things like v4f32 to v2f64. 7802 if (V->getOpcode() == ISD::BITCAST) { 7803 SDValue ConvInput = V->getOperand(0); 7804 if (ConvInput.getValueType().isVector() && 7805 ConvInput.getValueType().getVectorNumElements() == NumElts) 7806 V = ConvInput.getNode(); 7807 } 7808 7809 if (V->getOpcode() == ISD::BUILD_VECTOR) { 7810 assert(V->getNumOperands() == NumElts && 7811 "BUILD_VECTOR has wrong number of operands"); 7812 SDValue Base; 7813 bool AllSame = true; 7814 for (unsigned i = 0; i != NumElts; ++i) { 7815 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 7816 Base = V->getOperand(i); 7817 break; 7818 } 7819 } 7820 // Splat of <u, u, u, u>, return <u, u, u, u> 7821 if (!Base.getNode()) 7822 return N0; 7823 for (unsigned i = 0; i != NumElts; ++i) { 7824 if (V->getOperand(i) != Base) { 7825 AllSame = false; 7826 break; 7827 } 7828 } 7829 // Splat of <x, x, x, x>, return <x, x, x, x> 7830 if (AllSame) 7831 return N0; 7832 } 7833 } 7834 7835 // If this shuffle node is simply a swizzle of another shuffle node, 7836 // and it reverses the swizzle of the previous shuffle then we can 7837 // optimize shuffle(shuffle(x, undef), undef) -> x. 7838 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 7839 N1.getOpcode() == ISD::UNDEF) { 7840 7841 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 7842 7843 // Shuffle nodes can only reverse shuffles with a single non-undef value. 7844 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 7845 return SDValue(); 7846 7847 // The incoming shuffle must be of the same type as the result of the 7848 // current shuffle. 7849 assert(OtherSV->getOperand(0).getValueType() == VT && 7850 "Shuffle types don't match"); 7851 7852 for (unsigned i = 0; i != NumElts; ++i) { 7853 int Idx = SVN->getMaskElt(i); 7854 assert(Idx < (int)NumElts && "Index references undef operand"); 7855 // Next, this index comes from the first value, which is the incoming 7856 // shuffle. Adopt the incoming index. 7857 if (Idx >= 0) 7858 Idx = OtherSV->getMaskElt(Idx); 7859 7860 // The combined shuffle must map each index to itself. 7861 if (Idx >= 0 && (unsigned)Idx != i) 7862 return SDValue(); 7863 } 7864 7865 return OtherSV->getOperand(0); 7866 } 7867 7868 return SDValue(); 7869} 7870 7871SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 7872 if (!TLI.getShouldFoldAtomicFences()) 7873 return SDValue(); 7874 7875 SDValue atomic = N->getOperand(0); 7876 switch (atomic.getOpcode()) { 7877 case ISD::ATOMIC_CMP_SWAP: 7878 case ISD::ATOMIC_SWAP: 7879 case ISD::ATOMIC_LOAD_ADD: 7880 case ISD::ATOMIC_LOAD_SUB: 7881 case ISD::ATOMIC_LOAD_AND: 7882 case ISD::ATOMIC_LOAD_OR: 7883 case ISD::ATOMIC_LOAD_XOR: 7884 case ISD::ATOMIC_LOAD_NAND: 7885 case ISD::ATOMIC_LOAD_MIN: 7886 case ISD::ATOMIC_LOAD_MAX: 7887 case ISD::ATOMIC_LOAD_UMIN: 7888 case ISD::ATOMIC_LOAD_UMAX: 7889 break; 7890 default: 7891 return SDValue(); 7892 } 7893 7894 SDValue fence = atomic.getOperand(0); 7895 if (fence.getOpcode() != ISD::MEMBARRIER) 7896 return SDValue(); 7897 7898 switch (atomic.getOpcode()) { 7899 case ISD::ATOMIC_CMP_SWAP: 7900 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7901 fence.getOperand(0), 7902 atomic.getOperand(1), atomic.getOperand(2), 7903 atomic.getOperand(3)), atomic.getResNo()); 7904 case ISD::ATOMIC_SWAP: 7905 case ISD::ATOMIC_LOAD_ADD: 7906 case ISD::ATOMIC_LOAD_SUB: 7907 case ISD::ATOMIC_LOAD_AND: 7908 case ISD::ATOMIC_LOAD_OR: 7909 case ISD::ATOMIC_LOAD_XOR: 7910 case ISD::ATOMIC_LOAD_NAND: 7911 case ISD::ATOMIC_LOAD_MIN: 7912 case ISD::ATOMIC_LOAD_MAX: 7913 case ISD::ATOMIC_LOAD_UMIN: 7914 case ISD::ATOMIC_LOAD_UMAX: 7915 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7916 fence.getOperand(0), 7917 atomic.getOperand(1), atomic.getOperand(2)), 7918 atomic.getResNo()); 7919 default: 7920 return SDValue(); 7921 } 7922} 7923 7924/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 7925/// an AND to a vector_shuffle with the destination vector and a zero vector. 7926/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 7927/// vector_shuffle V, Zero, <0, 4, 2, 4> 7928SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 7929 EVT VT = N->getValueType(0); 7930 DebugLoc dl = N->getDebugLoc(); 7931 SDValue LHS = N->getOperand(0); 7932 SDValue RHS = N->getOperand(1); 7933 if (N->getOpcode() == ISD::AND) { 7934 if (RHS.getOpcode() == ISD::BITCAST) 7935 RHS = RHS.getOperand(0); 7936 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 7937 SmallVector<int, 8> Indices; 7938 unsigned NumElts = RHS.getNumOperands(); 7939 for (unsigned i = 0; i != NumElts; ++i) { 7940 SDValue Elt = RHS.getOperand(i); 7941 if (!isa<ConstantSDNode>(Elt)) 7942 return SDValue(); 7943 7944 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 7945 Indices.push_back(i); 7946 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 7947 Indices.push_back(NumElts); 7948 else 7949 return SDValue(); 7950 } 7951 7952 // Let's see if the target supports this vector_shuffle. 7953 EVT RVT = RHS.getValueType(); 7954 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 7955 return SDValue(); 7956 7957 // Return the new VECTOR_SHUFFLE node. 7958 EVT EltVT = RVT.getVectorElementType(); 7959 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 7960 DAG.getConstant(0, EltVT)); 7961 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7962 RVT, &ZeroOps[0], ZeroOps.size()); 7963 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 7964 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 7965 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 7966 } 7967 } 7968 7969 return SDValue(); 7970} 7971 7972/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 7973SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 7974 // After legalize, the target may be depending on adds and other 7975 // binary ops to provide legal ways to construct constants or other 7976 // things. Simplifying them may result in a loss of legality. 7977 if (LegalOperations) return SDValue(); 7978 7979 assert(N->getValueType(0).isVector() && 7980 "SimplifyVBinOp only works on vectors!"); 7981 7982 SDValue LHS = N->getOperand(0); 7983 SDValue RHS = N->getOperand(1); 7984 SDValue Shuffle = XformToShuffleWithZero(N); 7985 if (Shuffle.getNode()) return Shuffle; 7986 7987 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 7988 // this operation. 7989 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 7990 RHS.getOpcode() == ISD::BUILD_VECTOR) { 7991 SmallVector<SDValue, 8> Ops; 7992 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 7993 SDValue LHSOp = LHS.getOperand(i); 7994 SDValue RHSOp = RHS.getOperand(i); 7995 // If these two elements can't be folded, bail out. 7996 if ((LHSOp.getOpcode() != ISD::UNDEF && 7997 LHSOp.getOpcode() != ISD::Constant && 7998 LHSOp.getOpcode() != ISD::ConstantFP) || 7999 (RHSOp.getOpcode() != ISD::UNDEF && 8000 RHSOp.getOpcode() != ISD::Constant && 8001 RHSOp.getOpcode() != ISD::ConstantFP)) 8002 break; 8003 8004 // Can't fold divide by zero. 8005 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 8006 N->getOpcode() == ISD::FDIV) { 8007 if ((RHSOp.getOpcode() == ISD::Constant && 8008 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 8009 (RHSOp.getOpcode() == ISD::ConstantFP && 8010 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 8011 break; 8012 } 8013 8014 EVT VT = LHSOp.getValueType(); 8015 EVT RVT = RHSOp.getValueType(); 8016 if (RVT != VT) { 8017 // Integer BUILD_VECTOR operands may have types larger than the element 8018 // size (e.g., when the element type is not legal). Prior to type 8019 // legalization, the types may not match between the two BUILD_VECTORS. 8020 // Truncate one of the operands to make them match. 8021 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 8022 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 8023 } else { 8024 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 8025 VT = RVT; 8026 } 8027 } 8028 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 8029 LHSOp, RHSOp); 8030 if (FoldOp.getOpcode() != ISD::UNDEF && 8031 FoldOp.getOpcode() != ISD::Constant && 8032 FoldOp.getOpcode() != ISD::ConstantFP) 8033 break; 8034 Ops.push_back(FoldOp); 8035 AddToWorkList(FoldOp.getNode()); 8036 } 8037 8038 if (Ops.size() == LHS.getNumOperands()) 8039 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8040 LHS.getValueType(), &Ops[0], Ops.size()); 8041 } 8042 8043 return SDValue(); 8044} 8045 8046SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 8047 SDValue N1, SDValue N2){ 8048 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 8049 8050 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 8051 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 8052 8053 // If we got a simplified select_cc node back from SimplifySelectCC, then 8054 // break it down into a new SETCC node, and a new SELECT node, and then return 8055 // the SELECT node, since we were called with a SELECT node. 8056 if (SCC.getNode()) { 8057 // Check to see if we got a select_cc back (to turn into setcc/select). 8058 // Otherwise, just return whatever node we got back, like fabs. 8059 if (SCC.getOpcode() == ISD::SELECT_CC) { 8060 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 8061 N0.getValueType(), 8062 SCC.getOperand(0), SCC.getOperand(1), 8063 SCC.getOperand(4)); 8064 AddToWorkList(SETCC.getNode()); 8065 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 8066 SCC.getOperand(2), SCC.getOperand(3), SETCC); 8067 } 8068 8069 return SCC; 8070 } 8071 return SDValue(); 8072} 8073 8074/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 8075/// are the two values being selected between, see if we can simplify the 8076/// select. Callers of this should assume that TheSelect is deleted if this 8077/// returns true. As such, they should return the appropriate thing (e.g. the 8078/// node) back to the top-level of the DAG combiner loop to avoid it being 8079/// looked at. 8080bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 8081 SDValue RHS) { 8082 8083 // Cannot simplify select with vector condition 8084 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 8085 8086 // If this is a select from two identical things, try to pull the operation 8087 // through the select. 8088 if (LHS.getOpcode() != RHS.getOpcode() || 8089 !LHS.hasOneUse() || !RHS.hasOneUse()) 8090 return false; 8091 8092 // If this is a load and the token chain is identical, replace the select 8093 // of two loads with a load through a select of the address to load from. 8094 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 8095 // constants have been dropped into the constant pool. 8096 if (LHS.getOpcode() == ISD::LOAD) { 8097 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 8098 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 8099 8100 // Token chains must be identical. 8101 if (LHS.getOperand(0) != RHS.getOperand(0) || 8102 // Do not let this transformation reduce the number of volatile loads. 8103 LLD->isVolatile() || RLD->isVolatile() || 8104 // If this is an EXTLOAD, the VT's must match. 8105 LLD->getMemoryVT() != RLD->getMemoryVT() || 8106 // If this is an EXTLOAD, the kind of extension must match. 8107 (LLD->getExtensionType() != RLD->getExtensionType() && 8108 // The only exception is if one of the extensions is anyext. 8109 LLD->getExtensionType() != ISD::EXTLOAD && 8110 RLD->getExtensionType() != ISD::EXTLOAD) || 8111 // FIXME: this discards src value information. This is 8112 // over-conservative. It would be beneficial to be able to remember 8113 // both potential memory locations. Since we are discarding 8114 // src value info, don't do the transformation if the memory 8115 // locations are not in the default address space. 8116 LLD->getPointerInfo().getAddrSpace() != 0 || 8117 RLD->getPointerInfo().getAddrSpace() != 0) 8118 return false; 8119 8120 // Check that the select condition doesn't reach either load. If so, 8121 // folding this will induce a cycle into the DAG. If not, this is safe to 8122 // xform, so create a select of the addresses. 8123 SDValue Addr; 8124 if (TheSelect->getOpcode() == ISD::SELECT) { 8125 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 8126 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 8127 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 8128 return false; 8129 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 8130 LLD->getBasePtr().getValueType(), 8131 TheSelect->getOperand(0), LLD->getBasePtr(), 8132 RLD->getBasePtr()); 8133 } else { // Otherwise SELECT_CC 8134 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 8135 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 8136 8137 if ((LLD->hasAnyUseOfValue(1) && 8138 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 8139 (RLD->hasAnyUseOfValue(1) && 8140 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 8141 return false; 8142 8143 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 8144 LLD->getBasePtr().getValueType(), 8145 TheSelect->getOperand(0), 8146 TheSelect->getOperand(1), 8147 LLD->getBasePtr(), RLD->getBasePtr(), 8148 TheSelect->getOperand(4)); 8149 } 8150 8151 SDValue Load; 8152 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 8153 Load = DAG.getLoad(TheSelect->getValueType(0), 8154 TheSelect->getDebugLoc(), 8155 // FIXME: Discards pointer info. 8156 LLD->getChain(), Addr, MachinePointerInfo(), 8157 LLD->isVolatile(), LLD->isNonTemporal(), 8158 LLD->isInvariant(), LLD->getAlignment()); 8159 } else { 8160 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 8161 RLD->getExtensionType() : LLD->getExtensionType(), 8162 TheSelect->getDebugLoc(), 8163 TheSelect->getValueType(0), 8164 // FIXME: Discards pointer info. 8165 LLD->getChain(), Addr, MachinePointerInfo(), 8166 LLD->getMemoryVT(), LLD->isVolatile(), 8167 LLD->isNonTemporal(), LLD->getAlignment()); 8168 } 8169 8170 // Users of the select now use the result of the load. 8171 CombineTo(TheSelect, Load); 8172 8173 // Users of the old loads now use the new load's chain. We know the 8174 // old-load value is dead now. 8175 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 8176 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 8177 return true; 8178 } 8179 8180 return false; 8181} 8182 8183/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 8184/// where 'cond' is the comparison specified by CC. 8185SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 8186 SDValue N2, SDValue N3, 8187 ISD::CondCode CC, bool NotExtCompare) { 8188 // (x ? y : y) -> y. 8189 if (N2 == N3) return N2; 8190 8191 EVT VT = N2.getValueType(); 8192 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 8193 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 8194 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 8195 8196 // Determine if the condition we're dealing with is constant 8197 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 8198 N0, N1, CC, DL, false); 8199 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 8200 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 8201 8202 // fold select_cc true, x, y -> x 8203 if (SCCC && !SCCC->isNullValue()) 8204 return N2; 8205 // fold select_cc false, x, y -> y 8206 if (SCCC && SCCC->isNullValue()) 8207 return N3; 8208 8209 // Check to see if we can simplify the select into an fabs node 8210 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 8211 // Allow either -0.0 or 0.0 8212 if (CFP->getValueAPF().isZero()) { 8213 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 8214 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 8215 N0 == N2 && N3.getOpcode() == ISD::FNEG && 8216 N2 == N3.getOperand(0)) 8217 return DAG.getNode(ISD::FABS, DL, VT, N0); 8218 8219 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 8220 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 8221 N0 == N3 && N2.getOpcode() == ISD::FNEG && 8222 N2.getOperand(0) == N3) 8223 return DAG.getNode(ISD::FABS, DL, VT, N3); 8224 } 8225 } 8226 8227 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 8228 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 8229 // in it. This is a win when the constant is not otherwise available because 8230 // it replaces two constant pool loads with one. We only do this if the FP 8231 // type is known to be legal, because if it isn't, then we are before legalize 8232 // types an we want the other legalization to happen first (e.g. to avoid 8233 // messing with soft float) and if the ConstantFP is not legal, because if 8234 // it is legal, we may not need to store the FP constant in a constant pool. 8235 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 8236 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 8237 if (TLI.isTypeLegal(N2.getValueType()) && 8238 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 8239 TargetLowering::Legal) && 8240 // If both constants have multiple uses, then we won't need to do an 8241 // extra load, they are likely around in registers for other users. 8242 (TV->hasOneUse() || FV->hasOneUse())) { 8243 Constant *Elts[] = { 8244 const_cast<ConstantFP*>(FV->getConstantFPValue()), 8245 const_cast<ConstantFP*>(TV->getConstantFPValue()) 8246 }; 8247 Type *FPTy = Elts[0]->getType(); 8248 const TargetData &TD = *TLI.getTargetData(); 8249 8250 // Create a ConstantArray of the two constants. 8251 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 8252 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 8253 TD.getPrefTypeAlignment(FPTy)); 8254 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8255 8256 // Get the offsets to the 0 and 1 element of the array so that we can 8257 // select between them. 8258 SDValue Zero = DAG.getIntPtrConstant(0); 8259 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 8260 SDValue One = DAG.getIntPtrConstant(EltSize); 8261 8262 SDValue Cond = DAG.getSetCC(DL, 8263 TLI.getSetCCResultType(N0.getValueType()), 8264 N0, N1, CC); 8265 AddToWorkList(Cond.getNode()); 8266 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 8267 Cond, One, Zero); 8268 AddToWorkList(CstOffset.getNode()); 8269 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 8270 CstOffset); 8271 AddToWorkList(CPIdx.getNode()); 8272 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 8273 MachinePointerInfo::getConstantPool(), false, 8274 false, false, Alignment); 8275 8276 } 8277 } 8278 8279 // Check to see if we can perform the "gzip trick", transforming 8280 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 8281 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 8282 (N1C->isNullValue() || // (a < 0) ? b : 0 8283 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 8284 EVT XType = N0.getValueType(); 8285 EVT AType = N2.getValueType(); 8286 if (XType.bitsGE(AType)) { 8287 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 8288 // single-bit constant. 8289 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 8290 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 8291 ShCtV = XType.getSizeInBits()-ShCtV-1; 8292 SDValue ShCt = DAG.getConstant(ShCtV, 8293 getShiftAmountTy(N0.getValueType())); 8294 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 8295 XType, N0, ShCt); 8296 AddToWorkList(Shift.getNode()); 8297 8298 if (XType.bitsGT(AType)) { 8299 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8300 AddToWorkList(Shift.getNode()); 8301 } 8302 8303 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8304 } 8305 8306 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 8307 XType, N0, 8308 DAG.getConstant(XType.getSizeInBits()-1, 8309 getShiftAmountTy(N0.getValueType()))); 8310 AddToWorkList(Shift.getNode()); 8311 8312 if (XType.bitsGT(AType)) { 8313 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8314 AddToWorkList(Shift.getNode()); 8315 } 8316 8317 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8318 } 8319 } 8320 8321 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 8322 // where y is has a single bit set. 8323 // A plaintext description would be, we can turn the SELECT_CC into an AND 8324 // when the condition can be materialized as an all-ones register. Any 8325 // single bit-test can be materialized as an all-ones register with 8326 // shift-left and shift-right-arith. 8327 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 8328 N0->getValueType(0) == VT && 8329 N1C && N1C->isNullValue() && 8330 N2C && N2C->isNullValue()) { 8331 SDValue AndLHS = N0->getOperand(0); 8332 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 8333 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 8334 // Shift the tested bit over the sign bit. 8335 APInt AndMask = ConstAndRHS->getAPIntValue(); 8336 SDValue ShlAmt = 8337 DAG.getConstant(AndMask.countLeadingZeros(), 8338 getShiftAmountTy(AndLHS.getValueType())); 8339 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 8340 8341 // Now arithmetic right shift it all the way over, so the result is either 8342 // all-ones, or zero. 8343 SDValue ShrAmt = 8344 DAG.getConstant(AndMask.getBitWidth()-1, 8345 getShiftAmountTy(Shl.getValueType())); 8346 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 8347 8348 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 8349 } 8350 } 8351 8352 // fold select C, 16, 0 -> shl C, 4 8353 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 8354 TLI.getBooleanContents(N0.getValueType().isVector()) == 8355 TargetLowering::ZeroOrOneBooleanContent) { 8356 8357 // If the caller doesn't want us to simplify this into a zext of a compare, 8358 // don't do it. 8359 if (NotExtCompare && N2C->getAPIntValue() == 1) 8360 return SDValue(); 8361 8362 // Get a SetCC of the condition 8363 // FIXME: Should probably make sure that setcc is legal if we ever have a 8364 // target where it isn't. 8365 SDValue Temp, SCC; 8366 // cast from setcc result type to select result type 8367 if (LegalTypes) { 8368 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 8369 N0, N1, CC); 8370 if (N2.getValueType().bitsLT(SCC.getValueType())) 8371 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 8372 else 8373 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8374 N2.getValueType(), SCC); 8375 } else { 8376 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 8377 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8378 N2.getValueType(), SCC); 8379 } 8380 8381 AddToWorkList(SCC.getNode()); 8382 AddToWorkList(Temp.getNode()); 8383 8384 if (N2C->getAPIntValue() == 1) 8385 return Temp; 8386 8387 // shl setcc result by log2 n2c 8388 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 8389 DAG.getConstant(N2C->getAPIntValue().logBase2(), 8390 getShiftAmountTy(Temp.getValueType()))); 8391 } 8392 8393 // Check to see if this is the equivalent of setcc 8394 // FIXME: Turn all of these into setcc if setcc if setcc is legal 8395 // otherwise, go ahead with the folds. 8396 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 8397 EVT XType = N0.getValueType(); 8398 if (!LegalOperations || 8399 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 8400 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 8401 if (Res.getValueType() != VT) 8402 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 8403 return Res; 8404 } 8405 8406 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 8407 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 8408 (!LegalOperations || 8409 TLI.isOperationLegal(ISD::CTLZ, XType))) { 8410 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 8411 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 8412 DAG.getConstant(Log2_32(XType.getSizeInBits()), 8413 getShiftAmountTy(Ctlz.getValueType()))); 8414 } 8415 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 8416 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 8417 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 8418 XType, DAG.getConstant(0, XType), N0); 8419 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 8420 return DAG.getNode(ISD::SRL, DL, XType, 8421 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 8422 DAG.getConstant(XType.getSizeInBits()-1, 8423 getShiftAmountTy(XType))); 8424 } 8425 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 8426 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 8427 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 8428 DAG.getConstant(XType.getSizeInBits()-1, 8429 getShiftAmountTy(N0.getValueType()))); 8430 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 8431 } 8432 } 8433 8434 // Check to see if this is an integer abs. 8435 // select_cc setg[te] X, 0, X, -X -> 8436 // select_cc setgt X, -1, X, -X -> 8437 // select_cc setl[te] X, 0, -X, X -> 8438 // select_cc setlt X, 1, -X, X -> 8439 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 8440 if (N1C) { 8441 ConstantSDNode *SubC = NULL; 8442 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8443 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 8444 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 8445 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 8446 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 8447 (N1C->isOne() && CC == ISD::SETLT)) && 8448 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 8449 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 8450 8451 EVT XType = N0.getValueType(); 8452 if (SubC && SubC->isNullValue() && XType.isInteger()) { 8453 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 8454 N0, 8455 DAG.getConstant(XType.getSizeInBits()-1, 8456 getShiftAmountTy(N0.getValueType()))); 8457 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 8458 XType, N0, Shift); 8459 AddToWorkList(Shift.getNode()); 8460 AddToWorkList(Add.getNode()); 8461 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 8462 } 8463 } 8464 8465 return SDValue(); 8466} 8467 8468/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8469SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8470 SDValue N1, ISD::CondCode Cond, 8471 DebugLoc DL, bool foldBooleans) { 8472 TargetLowering::DAGCombinerInfo 8473 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8474 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8475} 8476 8477/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8478/// return a DAG expression to select that will generate the same value by 8479/// multiplying by a magic number. See: 8480/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8481SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8482 std::vector<SDNode*> Built; 8483 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8484 8485 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8486 ii != ee; ++ii) 8487 AddToWorkList(*ii); 8488 return S; 8489} 8490 8491/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8492/// return a DAG expression to select that will generate the same value by 8493/// multiplying by a magic number. See: 8494/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8495SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8496 std::vector<SDNode*> Built; 8497 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8498 8499 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8500 ii != ee; ++ii) 8501 AddToWorkList(*ii); 8502 return S; 8503} 8504 8505/// FindBaseOffset - Return true if base is a frame index, which is known not 8506// to alias with anything but itself. Provides base object and offset as 8507// results. 8508static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8509 const GlobalValue *&GV, void *&CV) { 8510 // Assume it is a primitive operation. 8511 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8512 8513 // If it's an adding a simple constant then integrate the offset. 8514 if (Base.getOpcode() == ISD::ADD) { 8515 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8516 Base = Base.getOperand(0); 8517 Offset += C->getZExtValue(); 8518 } 8519 } 8520 8521 // Return the underlying GlobalValue, and update the Offset. Return false 8522 // for GlobalAddressSDNode since the same GlobalAddress may be represented 8523 // by multiple nodes with different offsets. 8524 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 8525 GV = G->getGlobal(); 8526 Offset += G->getOffset(); 8527 return false; 8528 } 8529 8530 // Return the underlying Constant value, and update the Offset. Return false 8531 // for ConstantSDNodes since the same constant pool entry may be represented 8532 // by multiple nodes with different offsets. 8533 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 8534 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 8535 : (void *)C->getConstVal(); 8536 Offset += C->getOffset(); 8537 return false; 8538 } 8539 // If it's any of the following then it can't alias with anything but itself. 8540 return isa<FrameIndexSDNode>(Base); 8541} 8542 8543/// isAlias - Return true if there is any possibility that the two addresses 8544/// overlap. 8545bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 8546 const Value *SrcValue1, int SrcValueOffset1, 8547 unsigned SrcValueAlign1, 8548 const MDNode *TBAAInfo1, 8549 SDValue Ptr2, int64_t Size2, 8550 const Value *SrcValue2, int SrcValueOffset2, 8551 unsigned SrcValueAlign2, 8552 const MDNode *TBAAInfo2) const { 8553 // If they are the same then they must be aliases. 8554 if (Ptr1 == Ptr2) return true; 8555 8556 // Gather base node and offset information. 8557 SDValue Base1, Base2; 8558 int64_t Offset1, Offset2; 8559 const GlobalValue *GV1, *GV2; 8560 void *CV1, *CV2; 8561 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 8562 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 8563 8564 // If they have a same base address then check to see if they overlap. 8565 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 8566 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8567 8568 // It is possible for different frame indices to alias each other, mostly 8569 // when tail call optimization reuses return address slots for arguments. 8570 // To catch this case, look up the actual index of frame indices to compute 8571 // the real alias relationship. 8572 if (isFrameIndex1 && isFrameIndex2) { 8573 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8574 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 8575 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 8576 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8577 } 8578 8579 // Otherwise, if we know what the bases are, and they aren't identical, then 8580 // we know they cannot alias. 8581 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 8582 return false; 8583 8584 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 8585 // compared to the size and offset of the access, we may be able to prove they 8586 // do not alias. This check is conservative for now to catch cases created by 8587 // splitting vector types. 8588 if ((SrcValueAlign1 == SrcValueAlign2) && 8589 (SrcValueOffset1 != SrcValueOffset2) && 8590 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 8591 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 8592 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 8593 8594 // There is no overlap between these relatively aligned accesses of similar 8595 // size, return no alias. 8596 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 8597 return false; 8598 } 8599 8600 if (CombinerGlobalAA) { 8601 // Use alias analysis information. 8602 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 8603 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 8604 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 8605 AliasAnalysis::AliasResult AAResult = 8606 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 8607 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 8608 if (AAResult == AliasAnalysis::NoAlias) 8609 return false; 8610 } 8611 8612 // Otherwise we have to assume they alias. 8613 return true; 8614} 8615 8616/// FindAliasInfo - Extracts the relevant alias information from the memory 8617/// node. Returns true if the operand was a load. 8618bool DAGCombiner::FindAliasInfo(SDNode *N, 8619 SDValue &Ptr, int64_t &Size, 8620 const Value *&SrcValue, 8621 int &SrcValueOffset, 8622 unsigned &SrcValueAlign, 8623 const MDNode *&TBAAInfo) const { 8624 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 8625 8626 Ptr = LS->getBasePtr(); 8627 Size = LS->getMemoryVT().getSizeInBits() >> 3; 8628 SrcValue = LS->getSrcValue(); 8629 SrcValueOffset = LS->getSrcValueOffset(); 8630 SrcValueAlign = LS->getOriginalAlignment(); 8631 TBAAInfo = LS->getTBAAInfo(); 8632 return isa<LoadSDNode>(LS); 8633} 8634 8635/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 8636/// looking for aliasing nodes and adding them to the Aliases vector. 8637void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 8638 SmallVector<SDValue, 8> &Aliases) { 8639 SmallVector<SDValue, 8> Chains; // List of chains to visit. 8640 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 8641 8642 // Get alias information for node. 8643 SDValue Ptr; 8644 int64_t Size; 8645 const Value *SrcValue; 8646 int SrcValueOffset; 8647 unsigned SrcValueAlign; 8648 const MDNode *SrcTBAAInfo; 8649 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 8650 SrcValueAlign, SrcTBAAInfo); 8651 8652 // Starting off. 8653 Chains.push_back(OriginalChain); 8654 unsigned Depth = 0; 8655 8656 // Look at each chain and determine if it is an alias. If so, add it to the 8657 // aliases list. If not, then continue up the chain looking for the next 8658 // candidate. 8659 while (!Chains.empty()) { 8660 SDValue Chain = Chains.back(); 8661 Chains.pop_back(); 8662 8663 // For TokenFactor nodes, look at each operand and only continue up the 8664 // chain until we find two aliases. If we've seen two aliases, assume we'll 8665 // find more and revert to original chain since the xform is unlikely to be 8666 // profitable. 8667 // 8668 // FIXME: The depth check could be made to return the last non-aliasing 8669 // chain we found before we hit a tokenfactor rather than the original 8670 // chain. 8671 if (Depth > 6 || Aliases.size() == 2) { 8672 Aliases.clear(); 8673 Aliases.push_back(OriginalChain); 8674 break; 8675 } 8676 8677 // Don't bother if we've been before. 8678 if (!Visited.insert(Chain.getNode())) 8679 continue; 8680 8681 switch (Chain.getOpcode()) { 8682 case ISD::EntryToken: 8683 // Entry token is ideal chain operand, but handled in FindBetterChain. 8684 break; 8685 8686 case ISD::LOAD: 8687 case ISD::STORE: { 8688 // Get alias information for Chain. 8689 SDValue OpPtr; 8690 int64_t OpSize; 8691 const Value *OpSrcValue; 8692 int OpSrcValueOffset; 8693 unsigned OpSrcValueAlign; 8694 const MDNode *OpSrcTBAAInfo; 8695 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 8696 OpSrcValue, OpSrcValueOffset, 8697 OpSrcValueAlign, 8698 OpSrcTBAAInfo); 8699 8700 // If chain is alias then stop here. 8701 if (!(IsLoad && IsOpLoad) && 8702 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 8703 SrcTBAAInfo, 8704 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 8705 OpSrcValueAlign, OpSrcTBAAInfo)) { 8706 Aliases.push_back(Chain); 8707 } else { 8708 // Look further up the chain. 8709 Chains.push_back(Chain.getOperand(0)); 8710 ++Depth; 8711 } 8712 break; 8713 } 8714 8715 case ISD::TokenFactor: 8716 // We have to check each of the operands of the token factor for "small" 8717 // token factors, so we queue them up. Adding the operands to the queue 8718 // (stack) in reverse order maintains the original order and increases the 8719 // likelihood that getNode will find a matching token factor (CSE.) 8720 if (Chain.getNumOperands() > 16) { 8721 Aliases.push_back(Chain); 8722 break; 8723 } 8724 for (unsigned n = Chain.getNumOperands(); n;) 8725 Chains.push_back(Chain.getOperand(--n)); 8726 ++Depth; 8727 break; 8728 8729 default: 8730 // For all other instructions we will just have to take what we can get. 8731 Aliases.push_back(Chain); 8732 break; 8733 } 8734 } 8735} 8736 8737/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 8738/// for a better chain (aliasing node.) 8739SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 8740 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 8741 8742 // Accumulate all the aliases to this node. 8743 GatherAllAliases(N, OldChain, Aliases); 8744 8745 // If no operands then chain to entry token. 8746 if (Aliases.size() == 0) 8747 return DAG.getEntryNode(); 8748 8749 // If a single operand then chain to it. We don't need to revisit it. 8750 if (Aliases.size() == 1) 8751 return Aliases[0]; 8752 8753 // Construct a custom tailored token factor. 8754 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8755 &Aliases[0], Aliases.size()); 8756} 8757 8758// SelectionDAG::Combine - This is the entry point for the file. 8759// 8760void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 8761 CodeGenOpt::Level OptLevel) { 8762 /// run - This is the main entry point to this class. 8763 /// 8764 DAGCombiner(*this, AA, OptLevel).Run(Level); 8765} 8766