DAGCombiner.cpp revision 36c56d0353f1a9c4e878f509aff85a62e5087dd4
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 unsigned SrcValueAlign1, 242 SDValue Ptr2, int64_t Size2, 243 const Value *SrcValue2, int SrcValueOffset2, 244 unsigned SrcValueAlign2) const; 245 246 /// FindAliasInfo - Extracts the relevant alias information from the memory 247 /// node. Returns true if the operand was a load. 248 bool FindAliasInfo(SDNode *N, 249 SDValue &Ptr, int64_t &Size, 250 const Value *&SrcValue, int &SrcValueOffset, 251 unsigned &SrcValueAlignment) const; 252 253 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 254 /// looking for a better chain (aliasing node.) 255 SDValue FindBetterChain(SDNode *N, SDValue Chain); 256 257 /// getShiftAmountTy - Returns a type large enough to hold any valid 258 /// shift amount - before type legalization these can be huge. 259 EVT getShiftAmountTy() { 260 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 261 } 262 263public: 264 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 265 : DAG(D), 266 TLI(D.getTargetLoweringInfo()), 267 Level(Unrestricted), 268 OptLevel(OL), 269 LegalOperations(false), 270 LegalTypes(false), 271 AA(A) {} 272 273 /// Run - runs the dag combiner on all nodes in the work list 274 void Run(CombineLevel AtLevel); 275 }; 276} 277 278 279namespace { 280/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 281/// nodes from the worklist. 282class WorkListRemover : public SelectionDAG::DAGUpdateListener { 283 DAGCombiner &DC; 284public: 285 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 286 287 virtual void NodeDeleted(SDNode *N, SDNode *E) { 288 DC.removeFromWorkList(N); 289 } 290 291 virtual void NodeUpdated(SDNode *N) { 292 // Ignore updates. 293 } 294}; 295} 296 297//===----------------------------------------------------------------------===// 298// TargetLowering::DAGCombinerInfo implementation 299//===----------------------------------------------------------------------===// 300 301void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 302 ((DAGCombiner*)DC)->AddToWorkList(N); 303} 304 305SDValue TargetLowering::DAGCombinerInfo:: 306CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 307 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 308} 309 310SDValue TargetLowering::DAGCombinerInfo:: 311CombineTo(SDNode *N, SDValue Res, bool AddTo) { 312 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 313} 314 315 316SDValue TargetLowering::DAGCombinerInfo:: 317CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 318 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 319} 320 321void TargetLowering::DAGCombinerInfo:: 322CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 323 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 324} 325 326//===----------------------------------------------------------------------===// 327// Helper Functions 328//===----------------------------------------------------------------------===// 329 330/// isNegatibleForFree - Return 1 if we can compute the negated form of the 331/// specified expression for the same cost as the expression itself, or 2 if we 332/// can compute the negated form more cheaply than the expression itself. 333static char isNegatibleForFree(SDValue Op, bool LegalOperations, 334 unsigned Depth = 0) { 335 // No compile time optimizations on this type. 336 if (Op.getValueType() == MVT::ppcf128) 337 return 0; 338 339 // fneg is removable even if it has multiple uses. 340 if (Op.getOpcode() == ISD::FNEG) return 2; 341 342 // Don't allow anything with multiple uses. 343 if (!Op.hasOneUse()) return 0; 344 345 // Don't recurse exponentially. 346 if (Depth > 6) return 0; 347 348 switch (Op.getOpcode()) { 349 default: return false; 350 case ISD::ConstantFP: 351 // Don't invert constant FP values after legalize. The negated constant 352 // isn't necessarily legal. 353 return LegalOperations ? 0 : 1; 354 case ISD::FADD: 355 // FIXME: determine better conditions for this xform. 356 if (!UnsafeFPMath) return 0; 357 358 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 359 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 360 return V; 361 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 362 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 363 case ISD::FSUB: 364 // We can't turn -(A-B) into B-A when we honor signed zeros. 365 if (!UnsafeFPMath) return 0; 366 367 // fold (fneg (fsub A, B)) -> (fsub B, A) 368 return 1; 369 370 case ISD::FMUL: 371 case ISD::FDIV: 372 if (HonorSignDependentRoundingFPMath()) return 0; 373 374 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 376 return V; 377 378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 379 380 case ISD::FP_EXTEND: 381 case ISD::FP_ROUND: 382 case ISD::FSIN: 383 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 384 } 385} 386 387/// GetNegatedExpression - If isNegatibleForFree returns true, this function 388/// returns the newly negated expression. 389static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 390 bool LegalOperations, unsigned Depth = 0) { 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 393 394 // Don't allow anything with multiple uses. 395 assert(Op.hasOneUse() && "Unknown reuse!"); 396 397 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 398 switch (Op.getOpcode()) { 399 default: llvm_unreachable("Unknown code"); 400 case ISD::ConstantFP: { 401 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 402 V.changeSign(); 403 return DAG.getConstantFP(V, Op.getValueType()); 404 } 405 case ISD::FADD: 406 // FIXME: determine better conditions for this xform. 407 assert(UnsafeFPMath); 408 409 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 410 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 411 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 LegalOperations, Depth+1), 414 Op.getOperand(1)); 415 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 416 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 417 GetNegatedExpression(Op.getOperand(1), DAG, 418 LegalOperations, Depth+1), 419 Op.getOperand(0)); 420 case ISD::FSUB: 421 // We can't turn -(A-B) into B-A when we honor signed zeros. 422 assert(UnsafeFPMath); 423 424 // fold (fneg (fsub 0, B)) -> B 425 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 426 if (N0CFP->getValueAPF().isZero()) 427 return Op.getOperand(1); 428 429 // fold (fneg (fsub A, B)) -> (fsub B, A) 430 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 431 Op.getOperand(1), Op.getOperand(0)); 432 433 case ISD::FMUL: 434 case ISD::FDIV: 435 assert(!HonorSignDependentRoundingFPMath()); 436 437 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 438 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 439 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 440 GetNegatedExpression(Op.getOperand(0), DAG, 441 LegalOperations, Depth+1), 442 Op.getOperand(1)); 443 444 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 445 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 446 Op.getOperand(0), 447 GetNegatedExpression(Op.getOperand(1), DAG, 448 LegalOperations, Depth+1)); 449 450 case ISD::FP_EXTEND: 451 case ISD::FSIN: 452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1)); 455 case ISD::FP_ROUND: 456 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 457 GetNegatedExpression(Op.getOperand(0), DAG, 458 LegalOperations, Depth+1), 459 Op.getOperand(1)); 460 } 461} 462 463 464// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 465// that selects between the values 1 and 0, making it equivalent to a setcc. 466// Also, set the incoming LHS, RHS, and CC references to the appropriate 467// nodes based on the type of node we are checking. This simplifies life a 468// bit for the callers. 469static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 470 SDValue &CC) { 471 if (N.getOpcode() == ISD::SETCC) { 472 LHS = N.getOperand(0); 473 RHS = N.getOperand(1); 474 CC = N.getOperand(2); 475 return true; 476 } 477 if (N.getOpcode() == ISD::SELECT_CC && 478 N.getOperand(2).getOpcode() == ISD::Constant && 479 N.getOperand(3).getOpcode() == ISD::Constant && 480 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 481 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 482 LHS = N.getOperand(0); 483 RHS = N.getOperand(1); 484 CC = N.getOperand(4); 485 return true; 486 } 487 return false; 488} 489 490// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 491// one use. If this is true, it allows the users to invert the operation for 492// free when it is profitable to do so. 493static bool isOneUseSetCC(SDValue N) { 494 SDValue N0, N1, N2; 495 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 496 return true; 497 return false; 498} 499 500SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 501 SDValue N0, SDValue N1) { 502 EVT VT = N0.getValueType(); 503 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 504 if (isa<ConstantSDNode>(N1)) { 505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 506 SDValue OpNode = 507 DAG.FoldConstantArithmetic(Opc, VT, 508 cast<ConstantSDNode>(N0.getOperand(1)), 509 cast<ConstantSDNode>(N1)); 510 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 511 } else if (N0.hasOneUse()) { 512 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 513 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 514 N0.getOperand(0), N1); 515 AddToWorkList(OpNode.getNode()); 516 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 517 } 518 } 519 520 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 521 if (isa<ConstantSDNode>(N0)) { 522 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 523 SDValue OpNode = 524 DAG.FoldConstantArithmetic(Opc, VT, 525 cast<ConstantSDNode>(N1.getOperand(1)), 526 cast<ConstantSDNode>(N0)); 527 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 528 } else if (N1.hasOneUse()) { 529 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 530 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 531 N1.getOperand(0), N0); 532 AddToWorkList(OpNode.getNode()); 533 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 534 } 535 } 536 537 return SDValue(); 538} 539 540SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 541 bool AddTo) { 542 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 543 ++NodesCombined; 544 DEBUG(dbgs() << "\nReplacing.1 "; 545 N->dump(&DAG); 546 dbgs() << "\nWith: "; 547 To[0].getNode()->dump(&DAG); 548 dbgs() << " and " << NumTo-1 << " other values\n"; 549 for (unsigned i = 0, e = NumTo; i != e; ++i) 550 assert((!To[i].getNode() || 551 N->getValueType(i) == To[i].getValueType()) && 552 "Cannot combine value to value of different type!")); 553 WorkListRemover DeadNodes(*this); 554 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 555 556 if (AddTo) { 557 // Push the new nodes and any users onto the worklist 558 for (unsigned i = 0, e = NumTo; i != e; ++i) { 559 if (To[i].getNode()) { 560 AddToWorkList(To[i].getNode()); 561 AddUsersToWorkList(To[i].getNode()); 562 } 563 } 564 } 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (N->use_empty()) { 570 // Nodes can be reintroduced into the worklist. Make sure we do not 571 // process a node that has been replaced. 572 removeFromWorkList(N); 573 574 // Finally, since the node is now dead, remove it from the graph. 575 DAG.DeleteNode(N); 576 } 577 return SDValue(N, 0); 578} 579 580void 581DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 582 TLO) { 583 // Replace all uses. If any nodes become isomorphic to other nodes and 584 // are deleted, make sure to remove them from our worklist. 585 WorkListRemover DeadNodes(*this); 586 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 587 588 // Push the new node and any (possibly new) users onto the worklist. 589 AddToWorkList(TLO.New.getNode()); 590 AddUsersToWorkList(TLO.New.getNode()); 591 592 // Finally, if the node is now dead, remove it from the graph. The node 593 // may not be dead if the replacement process recursively simplified to 594 // something else needing this node. 595 if (TLO.Old.getNode()->use_empty()) { 596 removeFromWorkList(TLO.Old.getNode()); 597 598 // If the operands of this node are only used by the node, they will now 599 // be dead. Make sure to visit them first to delete dead nodes early. 600 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 601 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 602 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 603 604 DAG.DeleteNode(TLO.Old.getNode()); 605 } 606} 607 608/// SimplifyDemandedBits - Check the specified integer node value to see if 609/// it can be simplified or if things it uses can be simplified by bit 610/// propagation. If so, return true. 611bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 612 TargetLowering::TargetLoweringOpt TLO(DAG); 613 APInt KnownZero, KnownOne; 614 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 615 return false; 616 617 // Revisit the node. 618 AddToWorkList(Op.getNode()); 619 620 // Replace the old value with the new one. 621 ++NodesCombined; 622 DEBUG(dbgs() << "\nReplacing.2 "; 623 TLO.Old.getNode()->dump(&DAG); 624 dbgs() << "\nWith: "; 625 TLO.New.getNode()->dump(&DAG); 626 dbgs() << '\n'); 627 628 CommitTargetLoweringOpt(TLO); 629 return true; 630} 631 632//===----------------------------------------------------------------------===// 633// Main DAG Combiner implementation 634//===----------------------------------------------------------------------===// 635 636void DAGCombiner::Run(CombineLevel AtLevel) { 637 // set the instance variables, so that the various visit routines may use it. 638 Level = AtLevel; 639 LegalOperations = Level >= NoIllegalOperations; 640 LegalTypes = Level >= NoIllegalTypes; 641 642 // Add all the dag nodes to the worklist. 643 WorkList.reserve(DAG.allnodes_size()); 644 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 645 E = DAG.allnodes_end(); I != E; ++I) 646 WorkList.push_back(I); 647 648 // Create a dummy node (which is not added to allnodes), that adds a reference 649 // to the root node, preventing it from being deleted, and tracking any 650 // changes of the root. 651 HandleSDNode Dummy(DAG.getRoot()); 652 653 // The root of the dag may dangle to deleted nodes until the dag combiner is 654 // done. Set it to null to avoid confusion. 655 DAG.setRoot(SDValue()); 656 657 // while the worklist isn't empty, inspect the node on the end of it and 658 // try and combine it. 659 while (!WorkList.empty()) { 660 SDNode *N = WorkList.back(); 661 WorkList.pop_back(); 662 663 // If N has no uses, it is dead. Make sure to revisit all N's operands once 664 // N is deleted from the DAG, since they too may now be dead or may have a 665 // reduced number of uses, allowing other xforms. 666 if (N->use_empty() && N != &Dummy) { 667 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 668 AddToWorkList(N->getOperand(i).getNode()); 669 670 DAG.DeleteNode(N); 671 continue; 672 } 673 674 SDValue RV = combine(N); 675 676 if (RV.getNode() == 0) 677 continue; 678 679 ++NodesCombined; 680 681 // If we get back the same node we passed in, rather than a new node or 682 // zero, we know that the node must have defined multiple values and 683 // CombineTo was used. Since CombineTo takes care of the worklist 684 // mechanics for us, we have no work to do in this case. 685 if (RV.getNode() == N) 686 continue; 687 688 assert(N->getOpcode() != ISD::DELETED_NODE && 689 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 690 "Node was deleted but visit returned new node!"); 691 692 DEBUG(dbgs() << "\nReplacing.3 "; 693 N->dump(&DAG); 694 dbgs() << "\nWith: "; 695 RV.getNode()->dump(&DAG); 696 dbgs() << '\n'); 697 WorkListRemover DeadNodes(*this); 698 if (N->getNumValues() == RV.getNode()->getNumValues()) 699 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 700 else { 701 assert(N->getValueType(0) == RV.getValueType() && 702 N->getNumValues() == 1 && "Type mismatch"); 703 SDValue OpV = RV; 704 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 705 } 706 707 // Push the new node and any users onto the worklist 708 AddToWorkList(RV.getNode()); 709 AddUsersToWorkList(RV.getNode()); 710 711 // Add any uses of the old node to the worklist in case this node is the 712 // last one that uses them. They may become dead after this node is 713 // deleted. 714 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 715 AddToWorkList(N->getOperand(i).getNode()); 716 717 // Finally, if the node is now dead, remove it from the graph. The node 718 // may not be dead if the replacement process recursively simplified to 719 // something else needing this node. 720 if (N->use_empty()) { 721 // Nodes can be reintroduced into the worklist. Make sure we do not 722 // process a node that has been replaced. 723 removeFromWorkList(N); 724 725 // Finally, since the node is now dead, remove it from the graph. 726 DAG.DeleteNode(N); 727 } 728 } 729 730 // If the root changed (e.g. it was a dead load, update the root). 731 DAG.setRoot(Dummy.getValue()); 732} 733 734SDValue DAGCombiner::visit(SDNode *N) { 735 switch(N->getOpcode()) { 736 default: break; 737 case ISD::TokenFactor: return visitTokenFactor(N); 738 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 739 case ISD::ADD: return visitADD(N); 740 case ISD::SUB: return visitSUB(N); 741 case ISD::ADDC: return visitADDC(N); 742 case ISD::ADDE: return visitADDE(N); 743 case ISD::MUL: return visitMUL(N); 744 case ISD::SDIV: return visitSDIV(N); 745 case ISD::UDIV: return visitUDIV(N); 746 case ISD::SREM: return visitSREM(N); 747 case ISD::UREM: return visitUREM(N); 748 case ISD::MULHU: return visitMULHU(N); 749 case ISD::MULHS: return visitMULHS(N); 750 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 751 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 752 case ISD::SDIVREM: return visitSDIVREM(N); 753 case ISD::UDIVREM: return visitUDIVREM(N); 754 case ISD::AND: return visitAND(N); 755 case ISD::OR: return visitOR(N); 756 case ISD::XOR: return visitXOR(N); 757 case ISD::SHL: return visitSHL(N); 758 case ISD::SRA: return visitSRA(N); 759 case ISD::SRL: return visitSRL(N); 760 case ISD::CTLZ: return visitCTLZ(N); 761 case ISD::CTTZ: return visitCTTZ(N); 762 case ISD::CTPOP: return visitCTPOP(N); 763 case ISD::SELECT: return visitSELECT(N); 764 case ISD::SELECT_CC: return visitSELECT_CC(N); 765 case ISD::SETCC: return visitSETCC(N); 766 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 767 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 768 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 769 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 770 case ISD::TRUNCATE: return visitTRUNCATE(N); 771 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 772 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 773 case ISD::FADD: return visitFADD(N); 774 case ISD::FSUB: return visitFSUB(N); 775 case ISD::FMUL: return visitFMUL(N); 776 case ISD::FDIV: return visitFDIV(N); 777 case ISD::FREM: return visitFREM(N); 778 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 779 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 780 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 781 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 782 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 783 case ISD::FP_ROUND: return visitFP_ROUND(N); 784 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 785 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 786 case ISD::FNEG: return visitFNEG(N); 787 case ISD::FABS: return visitFABS(N); 788 case ISD::BRCOND: return visitBRCOND(N); 789 case ISD::BR_CC: return visitBR_CC(N); 790 case ISD::LOAD: return visitLOAD(N); 791 case ISD::STORE: return visitSTORE(N); 792 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 793 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 794 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 795 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 796 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 797 } 798 return SDValue(); 799} 800 801SDValue DAGCombiner::combine(SDNode *N) { 802 SDValue RV = visit(N); 803 804 // If nothing happened, try a target-specific DAG combine. 805 if (RV.getNode() == 0) { 806 assert(N->getOpcode() != ISD::DELETED_NODE && 807 "Node was deleted but visit returned NULL!"); 808 809 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 810 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 811 812 // Expose the DAG combiner to the target combiner impls. 813 TargetLowering::DAGCombinerInfo 814 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 815 816 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 817 } 818 } 819 820 // If N is a commutative binary node, try commuting it to enable more 821 // sdisel CSE. 822 if (RV.getNode() == 0 && 823 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 824 N->getNumValues() == 1) { 825 SDValue N0 = N->getOperand(0); 826 SDValue N1 = N->getOperand(1); 827 828 // Constant operands are canonicalized to RHS. 829 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 830 SDValue Ops[] = { N1, N0 }; 831 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 832 Ops, 2); 833 if (CSENode) 834 return SDValue(CSENode, 0); 835 } 836 } 837 838 return RV; 839} 840 841/// getInputChainForNode - Given a node, return its input chain if it has one, 842/// otherwise return a null sd operand. 843static SDValue getInputChainForNode(SDNode *N) { 844 if (unsigned NumOps = N->getNumOperands()) { 845 if (N->getOperand(0).getValueType() == MVT::Other) 846 return N->getOperand(0); 847 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 848 return N->getOperand(NumOps-1); 849 for (unsigned i = 1; i < NumOps-1; ++i) 850 if (N->getOperand(i).getValueType() == MVT::Other) 851 return N->getOperand(i); 852 } 853 return SDValue(); 854} 855 856SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 857 // If N has two operands, where one has an input chain equal to the other, 858 // the 'other' chain is redundant. 859 if (N->getNumOperands() == 2) { 860 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 861 return N->getOperand(0); 862 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 863 return N->getOperand(1); 864 } 865 866 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 867 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 868 SmallPtrSet<SDNode*, 16> SeenOps; 869 bool Changed = false; // If we should replace this token factor. 870 871 // Start out with this token factor. 872 TFs.push_back(N); 873 874 // Iterate through token factors. The TFs grows when new token factors are 875 // encountered. 876 for (unsigned i = 0; i < TFs.size(); ++i) { 877 SDNode *TF = TFs[i]; 878 879 // Check each of the operands. 880 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 881 SDValue Op = TF->getOperand(i); 882 883 switch (Op.getOpcode()) { 884 case ISD::EntryToken: 885 // Entry tokens don't need to be added to the list. They are 886 // rededundant. 887 Changed = true; 888 break; 889 890 case ISD::TokenFactor: 891 if (Op.hasOneUse() && 892 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 893 // Queue up for processing. 894 TFs.push_back(Op.getNode()); 895 // Clean up in case the token factor is removed. 896 AddToWorkList(Op.getNode()); 897 Changed = true; 898 break; 899 } 900 // Fall thru 901 902 default: 903 // Only add if it isn't already in the list. 904 if (SeenOps.insert(Op.getNode())) 905 Ops.push_back(Op); 906 else 907 Changed = true; 908 break; 909 } 910 } 911 } 912 913 SDValue Result; 914 915 // If we've change things around then replace token factor. 916 if (Changed) { 917 if (Ops.empty()) { 918 // The entry token is the only possible outcome. 919 Result = DAG.getEntryNode(); 920 } else { 921 // New and improved token factor. 922 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 923 MVT::Other, &Ops[0], Ops.size()); 924 } 925 926 // Don't add users to work list. 927 return CombineTo(N, Result, false); 928 } 929 930 return Result; 931} 932 933/// MERGE_VALUES can always be eliminated. 934SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 935 WorkListRemover DeadNodes(*this); 936 // Replacing results may cause a different MERGE_VALUES to suddenly 937 // be CSE'd with N, and carry its uses with it. Iterate until no 938 // uses remain, to ensure that the node can be safely deleted. 939 do { 940 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 942 &DeadNodes); 943 } while (!N->use_empty()); 944 removeFromWorkList(N); 945 DAG.DeleteNode(N); 946 return SDValue(N, 0); // Return N so it doesn't get rechecked! 947} 948 949static 950SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 951 SelectionDAG &DAG) { 952 EVT VT = N0.getValueType(); 953 SDValue N00 = N0.getOperand(0); 954 SDValue N01 = N0.getOperand(1); 955 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 956 957 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 958 isa<ConstantSDNode>(N00.getOperand(1))) { 959 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 960 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 961 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 962 N00.getOperand(0), N01), 963 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 964 N00.getOperand(1), N01)); 965 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 966 } 967 968 return SDValue(); 969} 970 971SDValue DAGCombiner::visitADD(SDNode *N) { 972 SDValue N0 = N->getOperand(0); 973 SDValue N1 = N->getOperand(1); 974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 976 EVT VT = N0.getValueType(); 977 978 // fold vector ops 979 if (VT.isVector()) { 980 SDValue FoldedVOp = SimplifyVBinOp(N); 981 if (FoldedVOp.getNode()) return FoldedVOp; 982 } 983 984 // fold (add x, undef) -> undef 985 if (N0.getOpcode() == ISD::UNDEF) 986 return N0; 987 if (N1.getOpcode() == ISD::UNDEF) 988 return N1; 989 // fold (add c1, c2) -> c1+c2 990 if (N0C && N1C) 991 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 992 // canonicalize constant to RHS 993 if (N0C && !N1C) 994 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 995 // fold (add x, 0) -> x 996 if (N1C && N1C->isNullValue()) 997 return N0; 998 // fold (add Sym, c) -> Sym+c 999 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1000 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1001 GA->getOpcode() == ISD::GlobalAddress) 1002 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1003 GA->getOffset() + 1004 (uint64_t)N1C->getSExtValue()); 1005 // fold ((c1-A)+c2) -> (c1+c2)-A 1006 if (N1C && N0.getOpcode() == ISD::SUB) 1007 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1008 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1009 DAG.getConstant(N1C->getAPIntValue()+ 1010 N0C->getAPIntValue(), VT), 1011 N0.getOperand(1)); 1012 // reassociate add 1013 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1014 if (RADD.getNode() != 0) 1015 return RADD; 1016 // fold ((0-A) + B) -> B-A 1017 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1018 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1020 // fold (A + (0-B)) -> A-B 1021 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1022 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1023 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1024 // fold (A+(B-A)) -> B 1025 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1026 return N1.getOperand(0); 1027 // fold ((B-A)+A) -> B 1028 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1029 return N0.getOperand(0); 1030 // fold (A+(B-(A+C))) to (B-C) 1031 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1032 N0 == N1.getOperand(1).getOperand(0)) 1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1034 N1.getOperand(1).getOperand(1)); 1035 // fold (A+(B-(C+A))) to (B-C) 1036 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1037 N0 == N1.getOperand(1).getOperand(1)) 1038 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1039 N1.getOperand(1).getOperand(0)); 1040 // fold (A+((B-A)+or-C)) to (B+or-C) 1041 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1042 N1.getOperand(0).getOpcode() == ISD::SUB && 1043 N0 == N1.getOperand(0).getOperand(1)) 1044 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1045 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1046 1047 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1048 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1049 SDValue N00 = N0.getOperand(0); 1050 SDValue N01 = N0.getOperand(1); 1051 SDValue N10 = N1.getOperand(0); 1052 SDValue N11 = N1.getOperand(1); 1053 1054 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1055 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1056 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1057 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1058 } 1059 1060 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1061 return SDValue(N, 0); 1062 1063 // fold (a+b) -> (a|b) iff a and b share no bits. 1064 if (VT.isInteger() && !VT.isVector()) { 1065 APInt LHSZero, LHSOne; 1066 APInt RHSZero, RHSOne; 1067 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1068 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1069 1070 if (LHSZero.getBoolValue()) { 1071 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1072 1073 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1074 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1075 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1076 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1078 } 1079 } 1080 1081 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1082 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1083 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1084 if (Result.getNode()) return Result; 1085 } 1086 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1087 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1088 if (Result.getNode()) return Result; 1089 } 1090 1091 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1092 if (N1.getOpcode() == ISD::SHL && 1093 N1.getOperand(0).getOpcode() == ISD::SUB) 1094 if (ConstantSDNode *C = 1095 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1096 if (C->getAPIntValue() == 0) 1097 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1098 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1099 N1.getOperand(0).getOperand(1), 1100 N1.getOperand(1))); 1101 if (N0.getOpcode() == ISD::SHL && 1102 N0.getOperand(0).getOpcode() == ISD::SUB) 1103 if (ConstantSDNode *C = 1104 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1105 if (C->getAPIntValue() == 0) 1106 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1107 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1108 N0.getOperand(0).getOperand(1), 1109 N0.getOperand(1))); 1110 1111 return SDValue(); 1112} 1113 1114SDValue DAGCombiner::visitADDC(SDNode *N) { 1115 SDValue N0 = N->getOperand(0); 1116 SDValue N1 = N->getOperand(1); 1117 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1118 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1119 EVT VT = N0.getValueType(); 1120 1121 // If the flag result is dead, turn this into an ADD. 1122 if (N->hasNUsesOfValue(0, 1)) 1123 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1124 DAG.getNode(ISD::CARRY_FALSE, 1125 N->getDebugLoc(), MVT::Flag)); 1126 1127 // canonicalize constant to RHS. 1128 if (N0C && !N1C) 1129 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1130 1131 // fold (addc x, 0) -> x + no carry out 1132 if (N1C && N1C->isNullValue()) 1133 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1134 N->getDebugLoc(), MVT::Flag)); 1135 1136 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1137 APInt LHSZero, LHSOne; 1138 APInt RHSZero, RHSOne; 1139 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1140 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1141 1142 if (LHSZero.getBoolValue()) { 1143 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1144 1145 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1146 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1147 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1148 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1149 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1150 DAG.getNode(ISD::CARRY_FALSE, 1151 N->getDebugLoc(), MVT::Flag)); 1152 } 1153 1154 return SDValue(); 1155} 1156 1157SDValue DAGCombiner::visitADDE(SDNode *N) { 1158 SDValue N0 = N->getOperand(0); 1159 SDValue N1 = N->getOperand(1); 1160 SDValue CarryIn = N->getOperand(2); 1161 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1162 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1163 1164 // canonicalize constant to RHS 1165 if (N0C && !N1C) 1166 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1167 N1, N0, CarryIn); 1168 1169 // fold (adde x, y, false) -> (addc x, y) 1170 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1171 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1172 1173 return SDValue(); 1174} 1175 1176SDValue DAGCombiner::visitSUB(SDNode *N) { 1177 SDValue N0 = N->getOperand(0); 1178 SDValue N1 = N->getOperand(1); 1179 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1180 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1181 EVT VT = N0.getValueType(); 1182 1183 // fold vector ops 1184 if (VT.isVector()) { 1185 SDValue FoldedVOp = SimplifyVBinOp(N); 1186 if (FoldedVOp.getNode()) return FoldedVOp; 1187 } 1188 1189 // fold (sub x, x) -> 0 1190 if (N0 == N1) 1191 return DAG.getConstant(0, N->getValueType(0)); 1192 // fold (sub c1, c2) -> c1-c2 1193 if (N0C && N1C) 1194 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1195 // fold (sub x, c) -> (add x, -c) 1196 if (N1C) 1197 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1198 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1199 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1200 if (N0C && N0C->isAllOnesValue()) 1201 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1202 // fold (A+B)-A -> B 1203 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1204 return N0.getOperand(1); 1205 // fold (A+B)-B -> A 1206 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1207 return N0.getOperand(0); 1208 // fold ((A+(B+or-C))-B) -> A+or-C 1209 if (N0.getOpcode() == ISD::ADD && 1210 (N0.getOperand(1).getOpcode() == ISD::SUB || 1211 N0.getOperand(1).getOpcode() == ISD::ADD) && 1212 N0.getOperand(1).getOperand(0) == N1) 1213 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1214 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1215 // fold ((A+(C+B))-B) -> A+C 1216 if (N0.getOpcode() == ISD::ADD && 1217 N0.getOperand(1).getOpcode() == ISD::ADD && 1218 N0.getOperand(1).getOperand(1) == N1) 1219 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1220 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1221 // fold ((A-(B-C))-C) -> A-B 1222 if (N0.getOpcode() == ISD::SUB && 1223 N0.getOperand(1).getOpcode() == ISD::SUB && 1224 N0.getOperand(1).getOperand(1) == N1) 1225 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1226 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1227 1228 // If either operand of a sub is undef, the result is undef 1229 if (N0.getOpcode() == ISD::UNDEF) 1230 return N0; 1231 if (N1.getOpcode() == ISD::UNDEF) 1232 return N1; 1233 1234 // If the relocation model supports it, consider symbol offsets. 1235 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1236 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1237 // fold (sub Sym, c) -> Sym-c 1238 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1239 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1240 GA->getOffset() - 1241 (uint64_t)N1C->getSExtValue()); 1242 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1243 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1244 if (GA->getGlobal() == GB->getGlobal()) 1245 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1246 VT); 1247 } 1248 1249 return SDValue(); 1250} 1251 1252SDValue DAGCombiner::visitMUL(SDNode *N) { 1253 SDValue N0 = N->getOperand(0); 1254 SDValue N1 = N->getOperand(1); 1255 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1256 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1257 EVT VT = N0.getValueType(); 1258 1259 // fold vector ops 1260 if (VT.isVector()) { 1261 SDValue FoldedVOp = SimplifyVBinOp(N); 1262 if (FoldedVOp.getNode()) return FoldedVOp; 1263 } 1264 1265 // fold (mul x, undef) -> 0 1266 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1267 return DAG.getConstant(0, VT); 1268 // fold (mul c1, c2) -> c1*c2 1269 if (N0C && N1C) 1270 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1271 // canonicalize constant to RHS 1272 if (N0C && !N1C) 1273 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1274 // fold (mul x, 0) -> 0 1275 if (N1C && N1C->isNullValue()) 1276 return N1; 1277 // fold (mul x, -1) -> 0-x 1278 if (N1C && N1C->isAllOnesValue()) 1279 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1280 DAG.getConstant(0, VT), N0); 1281 // fold (mul x, (1 << c)) -> x << c 1282 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1283 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1284 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1285 getShiftAmountTy())); 1286 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1287 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1288 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1289 // FIXME: If the input is something that is easily negated (e.g. a 1290 // single-use add), we should put the negate there. 1291 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1292 DAG.getConstant(0, VT), 1293 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1294 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1295 } 1296 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1297 if (N1C && N0.getOpcode() == ISD::SHL && 1298 isa<ConstantSDNode>(N0.getOperand(1))) { 1299 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1300 N1, N0.getOperand(1)); 1301 AddToWorkList(C3.getNode()); 1302 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1303 N0.getOperand(0), C3); 1304 } 1305 1306 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1307 // use. 1308 { 1309 SDValue Sh(0,0), Y(0,0); 1310 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1311 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1312 N0.getNode()->hasOneUse()) { 1313 Sh = N0; Y = N1; 1314 } else if (N1.getOpcode() == ISD::SHL && 1315 isa<ConstantSDNode>(N1.getOperand(1)) && 1316 N1.getNode()->hasOneUse()) { 1317 Sh = N1; Y = N0; 1318 } 1319 1320 if (Sh.getNode()) { 1321 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1322 Sh.getOperand(0), Y); 1323 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1324 Mul, Sh.getOperand(1)); 1325 } 1326 } 1327 1328 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1329 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1330 isa<ConstantSDNode>(N0.getOperand(1))) 1331 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1332 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1333 N0.getOperand(0), N1), 1334 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1335 N0.getOperand(1), N1)); 1336 1337 // reassociate mul 1338 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1339 if (RMUL.getNode() != 0) 1340 return RMUL; 1341 1342 return SDValue(); 1343} 1344 1345SDValue DAGCombiner::visitSDIV(SDNode *N) { 1346 SDValue N0 = N->getOperand(0); 1347 SDValue N1 = N->getOperand(1); 1348 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1349 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1350 EVT VT = N->getValueType(0); 1351 1352 // fold vector ops 1353 if (VT.isVector()) { 1354 SDValue FoldedVOp = SimplifyVBinOp(N); 1355 if (FoldedVOp.getNode()) return FoldedVOp; 1356 } 1357 1358 // fold (sdiv c1, c2) -> c1/c2 1359 if (N0C && N1C && !N1C->isNullValue()) 1360 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1361 // fold (sdiv X, 1) -> X 1362 if (N1C && N1C->getSExtValue() == 1LL) 1363 return N0; 1364 // fold (sdiv X, -1) -> 0-X 1365 if (N1C && N1C->isAllOnesValue()) 1366 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1367 DAG.getConstant(0, VT), N0); 1368 // If we know the sign bits of both operands are zero, strength reduce to a 1369 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1370 if (!VT.isVector()) { 1371 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1372 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1373 N0, N1); 1374 } 1375 // fold (sdiv X, pow2) -> simple ops after legalize 1376 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1377 (isPowerOf2_64(N1C->getSExtValue()) || 1378 isPowerOf2_64(-N1C->getSExtValue()))) { 1379 // If dividing by powers of two is cheap, then don't perform the following 1380 // fold. 1381 if (TLI.isPow2DivCheap()) 1382 return SDValue(); 1383 1384 int64_t pow2 = N1C->getSExtValue(); 1385 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1386 unsigned lg2 = Log2_64(abs2); 1387 1388 // Splat the sign bit into the register 1389 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1390 DAG.getConstant(VT.getSizeInBits()-1, 1391 getShiftAmountTy())); 1392 AddToWorkList(SGN.getNode()); 1393 1394 // Add (N0 < 0) ? abs2 - 1 : 0; 1395 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1396 DAG.getConstant(VT.getSizeInBits() - lg2, 1397 getShiftAmountTy())); 1398 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1399 AddToWorkList(SRL.getNode()); 1400 AddToWorkList(ADD.getNode()); // Divide by pow2 1401 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1402 DAG.getConstant(lg2, getShiftAmountTy())); 1403 1404 // If we're dividing by a positive value, we're done. Otherwise, we must 1405 // negate the result. 1406 if (pow2 > 0) 1407 return SRA; 1408 1409 AddToWorkList(SRA.getNode()); 1410 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1411 DAG.getConstant(0, VT), SRA); 1412 } 1413 1414 // if integer divide is expensive and we satisfy the requirements, emit an 1415 // alternate sequence. 1416 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1417 !TLI.isIntDivCheap()) { 1418 SDValue Op = BuildSDIV(N); 1419 if (Op.getNode()) return Op; 1420 } 1421 1422 // undef / X -> 0 1423 if (N0.getOpcode() == ISD::UNDEF) 1424 return DAG.getConstant(0, VT); 1425 // X / undef -> undef 1426 if (N1.getOpcode() == ISD::UNDEF) 1427 return N1; 1428 1429 return SDValue(); 1430} 1431 1432SDValue DAGCombiner::visitUDIV(SDNode *N) { 1433 SDValue N0 = N->getOperand(0); 1434 SDValue N1 = N->getOperand(1); 1435 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1436 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1437 EVT VT = N->getValueType(0); 1438 1439 // fold vector ops 1440 if (VT.isVector()) { 1441 SDValue FoldedVOp = SimplifyVBinOp(N); 1442 if (FoldedVOp.getNode()) return FoldedVOp; 1443 } 1444 1445 // fold (udiv c1, c2) -> c1/c2 1446 if (N0C && N1C && !N1C->isNullValue()) 1447 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1448 // fold (udiv x, (1 << c)) -> x >>u c 1449 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1450 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1451 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1452 getShiftAmountTy())); 1453 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1454 if (N1.getOpcode() == ISD::SHL) { 1455 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1456 if (SHC->getAPIntValue().isPowerOf2()) { 1457 EVT ADDVT = N1.getOperand(1).getValueType(); 1458 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1459 N1.getOperand(1), 1460 DAG.getConstant(SHC->getAPIntValue() 1461 .logBase2(), 1462 ADDVT)); 1463 AddToWorkList(Add.getNode()); 1464 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1465 } 1466 } 1467 } 1468 // fold (udiv x, c) -> alternate 1469 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1470 SDValue Op = BuildUDIV(N); 1471 if (Op.getNode()) return Op; 1472 } 1473 1474 // undef / X -> 0 1475 if (N0.getOpcode() == ISD::UNDEF) 1476 return DAG.getConstant(0, VT); 1477 // X / undef -> undef 1478 if (N1.getOpcode() == ISD::UNDEF) 1479 return N1; 1480 1481 return SDValue(); 1482} 1483 1484SDValue DAGCombiner::visitSREM(SDNode *N) { 1485 SDValue N0 = N->getOperand(0); 1486 SDValue N1 = N->getOperand(1); 1487 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1488 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1489 EVT VT = N->getValueType(0); 1490 1491 // fold (srem c1, c2) -> c1%c2 1492 if (N0C && N1C && !N1C->isNullValue()) 1493 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1494 // If we know the sign bits of both operands are zero, strength reduce to a 1495 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1496 if (!VT.isVector()) { 1497 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1498 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1499 } 1500 1501 // If X/C can be simplified by the division-by-constant logic, lower 1502 // X%C to the equivalent of X-X/C*C. 1503 if (N1C && !N1C->isNullValue()) { 1504 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1505 AddToWorkList(Div.getNode()); 1506 SDValue OptimizedDiv = combine(Div.getNode()); 1507 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1508 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1509 OptimizedDiv, N1); 1510 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1511 AddToWorkList(Mul.getNode()); 1512 return Sub; 1513 } 1514 } 1515 1516 // undef % X -> 0 1517 if (N0.getOpcode() == ISD::UNDEF) 1518 return DAG.getConstant(0, VT); 1519 // X % undef -> undef 1520 if (N1.getOpcode() == ISD::UNDEF) 1521 return N1; 1522 1523 return SDValue(); 1524} 1525 1526SDValue DAGCombiner::visitUREM(SDNode *N) { 1527 SDValue N0 = N->getOperand(0); 1528 SDValue N1 = N->getOperand(1); 1529 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1531 EVT VT = N->getValueType(0); 1532 1533 // fold (urem c1, c2) -> c1%c2 1534 if (N0C && N1C && !N1C->isNullValue()) 1535 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1536 // fold (urem x, pow2) -> (and x, pow2-1) 1537 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1538 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1539 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1540 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1541 if (N1.getOpcode() == ISD::SHL) { 1542 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1543 if (SHC->getAPIntValue().isPowerOf2()) { 1544 SDValue Add = 1545 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1546 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1547 VT)); 1548 AddToWorkList(Add.getNode()); 1549 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1550 } 1551 } 1552 } 1553 1554 // If X/C can be simplified by the division-by-constant logic, lower 1555 // X%C to the equivalent of X-X/C*C. 1556 if (N1C && !N1C->isNullValue()) { 1557 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1558 AddToWorkList(Div.getNode()); 1559 SDValue OptimizedDiv = combine(Div.getNode()); 1560 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1561 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1562 OptimizedDiv, N1); 1563 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1564 AddToWorkList(Mul.getNode()); 1565 return Sub; 1566 } 1567 } 1568 1569 // undef % X -> 0 1570 if (N0.getOpcode() == ISD::UNDEF) 1571 return DAG.getConstant(0, VT); 1572 // X % undef -> undef 1573 if (N1.getOpcode() == ISD::UNDEF) 1574 return N1; 1575 1576 return SDValue(); 1577} 1578 1579SDValue DAGCombiner::visitMULHS(SDNode *N) { 1580 SDValue N0 = N->getOperand(0); 1581 SDValue N1 = N->getOperand(1); 1582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1583 EVT VT = N->getValueType(0); 1584 1585 // fold (mulhs x, 0) -> 0 1586 if (N1C && N1C->isNullValue()) 1587 return N1; 1588 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1589 if (N1C && N1C->getAPIntValue() == 1) 1590 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1591 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1592 getShiftAmountTy())); 1593 // fold (mulhs x, undef) -> 0 1594 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1595 return DAG.getConstant(0, VT); 1596 1597 return SDValue(); 1598} 1599 1600SDValue DAGCombiner::visitMULHU(SDNode *N) { 1601 SDValue N0 = N->getOperand(0); 1602 SDValue N1 = N->getOperand(1); 1603 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1604 EVT VT = N->getValueType(0); 1605 1606 // fold (mulhu x, 0) -> 0 1607 if (N1C && N1C->isNullValue()) 1608 return N1; 1609 // fold (mulhu x, 1) -> 0 1610 if (N1C && N1C->getAPIntValue() == 1) 1611 return DAG.getConstant(0, N0.getValueType()); 1612 // fold (mulhu x, undef) -> 0 1613 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1614 return DAG.getConstant(0, VT); 1615 1616 return SDValue(); 1617} 1618 1619/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1620/// compute two values. LoOp and HiOp give the opcodes for the two computations 1621/// that are being performed. Return true if a simplification was made. 1622/// 1623SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1624 unsigned HiOp) { 1625 // If the high half is not needed, just compute the low half. 1626 bool HiExists = N->hasAnyUseOfValue(1); 1627 if (!HiExists && 1628 (!LegalOperations || 1629 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1630 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1631 N->op_begin(), N->getNumOperands()); 1632 return CombineTo(N, Res, Res); 1633 } 1634 1635 // If the low half is not needed, just compute the high half. 1636 bool LoExists = N->hasAnyUseOfValue(0); 1637 if (!LoExists && 1638 (!LegalOperations || 1639 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1640 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1641 N->op_begin(), N->getNumOperands()); 1642 return CombineTo(N, Res, Res); 1643 } 1644 1645 // If both halves are used, return as it is. 1646 if (LoExists && HiExists) 1647 return SDValue(); 1648 1649 // If the two computed results can be simplified separately, separate them. 1650 if (LoExists) { 1651 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1652 N->op_begin(), N->getNumOperands()); 1653 AddToWorkList(Lo.getNode()); 1654 SDValue LoOpt = combine(Lo.getNode()); 1655 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1656 (!LegalOperations || 1657 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1658 return CombineTo(N, LoOpt, LoOpt); 1659 } 1660 1661 if (HiExists) { 1662 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1663 N->op_begin(), N->getNumOperands()); 1664 AddToWorkList(Hi.getNode()); 1665 SDValue HiOpt = combine(Hi.getNode()); 1666 if (HiOpt.getNode() && HiOpt != Hi && 1667 (!LegalOperations || 1668 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1669 return CombineTo(N, HiOpt, HiOpt); 1670 } 1671 1672 return SDValue(); 1673} 1674 1675SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1676 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1677 if (Res.getNode()) return Res; 1678 1679 return SDValue(); 1680} 1681 1682SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1683 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1684 if (Res.getNode()) return Res; 1685 1686 return SDValue(); 1687} 1688 1689SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1690 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1691 if (Res.getNode()) return Res; 1692 1693 return SDValue(); 1694} 1695 1696SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1697 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1698 if (Res.getNode()) return Res; 1699 1700 return SDValue(); 1701} 1702 1703/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1704/// two operands of the same opcode, try to simplify it. 1705SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1706 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1707 EVT VT = N0.getValueType(); 1708 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1709 1710 // Bail early if none of these transforms apply. 1711 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 1712 1713 // For each of OP in AND/OR/XOR: 1714 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1715 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1716 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1717 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1718 // 1719 // do not sink logical op inside of a vector extend, since it may combine 1720 // into a vsetcc. 1721 EVT Op0VT = N0.getOperand(0).getValueType(); 1722 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 1723 N0.getOpcode() == ISD::ANY_EXTEND || 1724 N0.getOpcode() == ISD::SIGN_EXTEND || 1725 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) && 1726 !VT.isVector() && 1727 Op0VT == N1.getOperand(0).getValueType() && 1728 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 1729 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1730 N0.getOperand(0).getValueType(), 1731 N0.getOperand(0), N1.getOperand(0)); 1732 AddToWorkList(ORNode.getNode()); 1733 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1734 } 1735 1736 // For each of OP in SHL/SRL/SRA/AND... 1737 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1738 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1739 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1740 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1741 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1742 N0.getOperand(1) == N1.getOperand(1)) { 1743 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1744 N0.getOperand(0).getValueType(), 1745 N0.getOperand(0), N1.getOperand(0)); 1746 AddToWorkList(ORNode.getNode()); 1747 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1748 ORNode, N0.getOperand(1)); 1749 } 1750 1751 return SDValue(); 1752} 1753 1754SDValue DAGCombiner::visitAND(SDNode *N) { 1755 SDValue N0 = N->getOperand(0); 1756 SDValue N1 = N->getOperand(1); 1757 SDValue LL, LR, RL, RR, CC0, CC1; 1758 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1759 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1760 EVT VT = N1.getValueType(); 1761 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 1762 1763 // fold vector ops 1764 if (VT.isVector()) { 1765 SDValue FoldedVOp = SimplifyVBinOp(N); 1766 if (FoldedVOp.getNode()) return FoldedVOp; 1767 } 1768 1769 // fold (and x, undef) -> 0 1770 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1771 return DAG.getConstant(0, VT); 1772 // fold (and c1, c2) -> c1&c2 1773 if (N0C && N1C) 1774 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1775 // canonicalize constant to RHS 1776 if (N0C && !N1C) 1777 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1778 // fold (and x, -1) -> x 1779 if (N1C && N1C->isAllOnesValue()) 1780 return N0; 1781 // if (and x, c) is known to be zero, return 0 1782 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1783 APInt::getAllOnesValue(BitWidth))) 1784 return DAG.getConstant(0, VT); 1785 // reassociate and 1786 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1787 if (RAND.getNode() != 0) 1788 return RAND; 1789 // fold (and (or x, C), D) -> D if (C & D) == D 1790 if (N1C && N0.getOpcode() == ISD::OR) 1791 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1792 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1793 return N1; 1794 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1795 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1796 SDValue N0Op0 = N0.getOperand(0); 1797 APInt Mask = ~N1C->getAPIntValue(); 1798 Mask.trunc(N0Op0.getValueSizeInBits()); 1799 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1800 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1801 N0.getValueType(), N0Op0); 1802 1803 // Replace uses of the AND with uses of the Zero extend node. 1804 CombineTo(N, Zext); 1805 1806 // We actually want to replace all uses of the any_extend with the 1807 // zero_extend, to avoid duplicating things. This will later cause this 1808 // AND to be folded. 1809 CombineTo(N0.getNode(), Zext); 1810 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1811 } 1812 } 1813 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1814 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1815 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1816 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1817 1818 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1819 LL.getValueType().isInteger()) { 1820 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1821 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1822 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1823 LR.getValueType(), LL, RL); 1824 AddToWorkList(ORNode.getNode()); 1825 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1826 } 1827 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1828 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1829 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1830 LR.getValueType(), LL, RL); 1831 AddToWorkList(ANDNode.getNode()); 1832 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1833 } 1834 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1835 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1836 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1837 LR.getValueType(), LL, RL); 1838 AddToWorkList(ORNode.getNode()); 1839 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1840 } 1841 } 1842 // canonicalize equivalent to ll == rl 1843 if (LL == RR && LR == RL) { 1844 Op1 = ISD::getSetCCSwappedOperands(Op1); 1845 std::swap(RL, RR); 1846 } 1847 if (LL == RL && LR == RR) { 1848 bool isInteger = LL.getValueType().isInteger(); 1849 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1850 if (Result != ISD::SETCC_INVALID && 1851 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1852 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1853 LL, LR, Result); 1854 } 1855 } 1856 1857 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1858 if (N0.getOpcode() == N1.getOpcode()) { 1859 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1860 if (Tmp.getNode()) return Tmp; 1861 } 1862 1863 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1864 // fold (and (sra)) -> (and (srl)) when possible. 1865 if (!VT.isVector() && 1866 SimplifyDemandedBits(SDValue(N, 0))) 1867 return SDValue(N, 0); 1868 1869 // fold (zext_inreg (extload x)) -> (zextload x) 1870 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1871 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1872 EVT MemVT = LN0->getMemoryVT(); 1873 // If we zero all the possible extended bits, then we can turn this into 1874 // a zextload if we are running before legalize or the operation is legal. 1875 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 1876 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1877 BitWidth - MemVT.getScalarType().getSizeInBits())) && 1878 ((!LegalOperations && !LN0->isVolatile()) || 1879 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1880 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1881 LN0->getChain(), LN0->getBasePtr(), 1882 LN0->getSrcValue(), 1883 LN0->getSrcValueOffset(), MemVT, 1884 LN0->isVolatile(), LN0->isNonTemporal(), 1885 LN0->getAlignment()); 1886 AddToWorkList(N); 1887 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1888 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1889 } 1890 } 1891 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1892 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1893 N0.hasOneUse()) { 1894 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1895 EVT MemVT = LN0->getMemoryVT(); 1896 // If we zero all the possible extended bits, then we can turn this into 1897 // a zextload if we are running before legalize or the operation is legal. 1898 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 1899 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1900 BitWidth - MemVT.getScalarType().getSizeInBits())) && 1901 ((!LegalOperations && !LN0->isVolatile()) || 1902 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1903 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1904 LN0->getChain(), 1905 LN0->getBasePtr(), LN0->getSrcValue(), 1906 LN0->getSrcValueOffset(), MemVT, 1907 LN0->isVolatile(), LN0->isNonTemporal(), 1908 LN0->getAlignment()); 1909 AddToWorkList(N); 1910 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1911 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1912 } 1913 } 1914 1915 // fold (and (load x), 255) -> (zextload x, i8) 1916 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1917 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 1918 if (N1C && (N0.getOpcode() == ISD::LOAD || 1919 (N0.getOpcode() == ISD::ANY_EXTEND && 1920 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 1921 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 1922 LoadSDNode *LN0 = HasAnyExt 1923 ? cast<LoadSDNode>(N0.getOperand(0)) 1924 : cast<LoadSDNode>(N0); 1925 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1926 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 1927 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1928 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 1929 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 1930 EVT LoadedVT = LN0->getMemoryVT(); 1931 1932 if (ExtVT == LoadedVT && 1933 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1934 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1935 1936 SDValue NewLoad = 1937 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1938 LN0->getChain(), LN0->getBasePtr(), 1939 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1940 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 1941 LN0->getAlignment()); 1942 AddToWorkList(N); 1943 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 1944 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1945 } 1946 1947 // Do not change the width of a volatile load. 1948 // Do not generate loads of non-round integer types since these can 1949 // be expensive (and would be wrong if the type is not byte sized). 1950 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 1951 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1952 EVT PtrType = LN0->getOperand(1).getValueType(); 1953 1954 unsigned Alignment = LN0->getAlignment(); 1955 SDValue NewPtr = LN0->getBasePtr(); 1956 1957 // For big endian targets, we need to add an offset to the pointer 1958 // to load the correct bytes. For little endian systems, we merely 1959 // need to read fewer bytes from the same pointer. 1960 if (TLI.isBigEndian()) { 1961 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 1962 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 1963 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1964 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1965 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1966 Alignment = MinAlign(Alignment, PtrOff); 1967 } 1968 1969 AddToWorkList(NewPtr.getNode()); 1970 1971 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1972 SDValue Load = 1973 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1974 LN0->getChain(), NewPtr, 1975 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1976 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 1977 Alignment); 1978 AddToWorkList(N); 1979 CombineTo(LN0, Load, Load.getValue(1)); 1980 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1981 } 1982 } 1983 } 1984 } 1985 1986 return SDValue(); 1987} 1988 1989SDValue DAGCombiner::visitOR(SDNode *N) { 1990 SDValue N0 = N->getOperand(0); 1991 SDValue N1 = N->getOperand(1); 1992 SDValue LL, LR, RL, RR, CC0, CC1; 1993 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1994 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1995 EVT VT = N1.getValueType(); 1996 1997 // fold vector ops 1998 if (VT.isVector()) { 1999 SDValue FoldedVOp = SimplifyVBinOp(N); 2000 if (FoldedVOp.getNode()) return FoldedVOp; 2001 } 2002 2003 // fold (or x, undef) -> -1 2004 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 2005 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2006 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2007 } 2008 // fold (or c1, c2) -> c1|c2 2009 if (N0C && N1C) 2010 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2011 // canonicalize constant to RHS 2012 if (N0C && !N1C) 2013 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2014 // fold (or x, 0) -> x 2015 if (N1C && N1C->isNullValue()) 2016 return N0; 2017 // fold (or x, -1) -> -1 2018 if (N1C && N1C->isAllOnesValue()) 2019 return N1; 2020 // fold (or x, c) -> c iff (x & ~c) == 0 2021 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2022 return N1; 2023 // reassociate or 2024 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2025 if (ROR.getNode() != 0) 2026 return ROR; 2027 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2028 // iff (c1 & c2) == 0. 2029 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2030 isa<ConstantSDNode>(N0.getOperand(1))) { 2031 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2032 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2033 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2034 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2035 N0.getOperand(0), N1), 2036 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2037 } 2038 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2039 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2040 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2041 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2042 2043 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2044 LL.getValueType().isInteger()) { 2045 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2046 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2047 if (cast<ConstantSDNode>(LR)->isNullValue() && 2048 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2049 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2050 LR.getValueType(), LL, RL); 2051 AddToWorkList(ORNode.getNode()); 2052 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2053 } 2054 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2055 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2056 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2057 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2058 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2059 LR.getValueType(), LL, RL); 2060 AddToWorkList(ANDNode.getNode()); 2061 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2062 } 2063 } 2064 // canonicalize equivalent to ll == rl 2065 if (LL == RR && LR == RL) { 2066 Op1 = ISD::getSetCCSwappedOperands(Op1); 2067 std::swap(RL, RR); 2068 } 2069 if (LL == RL && LR == RR) { 2070 bool isInteger = LL.getValueType().isInteger(); 2071 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2072 if (Result != ISD::SETCC_INVALID && 2073 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2074 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2075 LL, LR, Result); 2076 } 2077 } 2078 2079 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2080 if (N0.getOpcode() == N1.getOpcode()) { 2081 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2082 if (Tmp.getNode()) return Tmp; 2083 } 2084 2085 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2086 if (N0.getOpcode() == ISD::AND && 2087 N1.getOpcode() == ISD::AND && 2088 N0.getOperand(1).getOpcode() == ISD::Constant && 2089 N1.getOperand(1).getOpcode() == ISD::Constant && 2090 // Don't increase # computations. 2091 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2092 // We can only do this xform if we know that bits from X that are set in C2 2093 // but not in C1 are already zero. Likewise for Y. 2094 const APInt &LHSMask = 2095 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2096 const APInt &RHSMask = 2097 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2098 2099 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2100 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2101 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2102 N0.getOperand(0), N1.getOperand(0)); 2103 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2104 DAG.getConstant(LHSMask | RHSMask, VT)); 2105 } 2106 } 2107 2108 // See if this is some rotate idiom. 2109 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2110 return SDValue(Rot, 0); 2111 2112 return SDValue(); 2113} 2114 2115/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2116static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2117 if (Op.getOpcode() == ISD::AND) { 2118 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2119 Mask = Op.getOperand(1); 2120 Op = Op.getOperand(0); 2121 } else { 2122 return false; 2123 } 2124 } 2125 2126 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2127 Shift = Op; 2128 return true; 2129 } 2130 2131 return false; 2132} 2133 2134// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2135// idioms for rotate, and if the target supports rotation instructions, generate 2136// a rot[lr]. 2137SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2138 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2139 EVT VT = LHS.getValueType(); 2140 if (!TLI.isTypeLegal(VT)) return 0; 2141 2142 // The target must have at least one rotate flavor. 2143 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2144 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2145 if (!HasROTL && !HasROTR) return 0; 2146 2147 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2148 SDValue LHSShift; // The shift. 2149 SDValue LHSMask; // AND value if any. 2150 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2151 return 0; // Not part of a rotate. 2152 2153 SDValue RHSShift; // The shift. 2154 SDValue RHSMask; // AND value if any. 2155 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2156 return 0; // Not part of a rotate. 2157 2158 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2159 return 0; // Not shifting the same value. 2160 2161 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2162 return 0; // Shifts must disagree. 2163 2164 // Canonicalize shl to left side in a shl/srl pair. 2165 if (RHSShift.getOpcode() == ISD::SHL) { 2166 std::swap(LHS, RHS); 2167 std::swap(LHSShift, RHSShift); 2168 std::swap(LHSMask , RHSMask ); 2169 } 2170 2171 unsigned OpSizeInBits = VT.getSizeInBits(); 2172 SDValue LHSShiftArg = LHSShift.getOperand(0); 2173 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2174 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2175 2176 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2177 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2178 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2179 RHSShiftAmt.getOpcode() == ISD::Constant) { 2180 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2181 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2182 if ((LShVal + RShVal) != OpSizeInBits) 2183 return 0; 2184 2185 SDValue Rot; 2186 if (HasROTL) 2187 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2188 else 2189 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2190 2191 // If there is an AND of either shifted operand, apply it to the result. 2192 if (LHSMask.getNode() || RHSMask.getNode()) { 2193 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2194 2195 if (LHSMask.getNode()) { 2196 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2197 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2198 } 2199 if (RHSMask.getNode()) { 2200 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2201 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2202 } 2203 2204 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2205 } 2206 2207 return Rot.getNode(); 2208 } 2209 2210 // If there is a mask here, and we have a variable shift, we can't be sure 2211 // that we're masking out the right stuff. 2212 if (LHSMask.getNode() || RHSMask.getNode()) 2213 return 0; 2214 2215 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2216 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2217 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2218 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2219 if (ConstantSDNode *SUBC = 2220 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2221 if (SUBC->getAPIntValue() == OpSizeInBits) { 2222 if (HasROTL) 2223 return DAG.getNode(ISD::ROTL, DL, VT, 2224 LHSShiftArg, LHSShiftAmt).getNode(); 2225 else 2226 return DAG.getNode(ISD::ROTR, DL, VT, 2227 LHSShiftArg, RHSShiftAmt).getNode(); 2228 } 2229 } 2230 } 2231 2232 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2233 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2234 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2235 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2236 if (ConstantSDNode *SUBC = 2237 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2238 if (SUBC->getAPIntValue() == OpSizeInBits) { 2239 if (HasROTR) 2240 return DAG.getNode(ISD::ROTR, DL, VT, 2241 LHSShiftArg, RHSShiftAmt).getNode(); 2242 else 2243 return DAG.getNode(ISD::ROTL, DL, VT, 2244 LHSShiftArg, LHSShiftAmt).getNode(); 2245 } 2246 } 2247 } 2248 2249 // Look for sign/zext/any-extended or truncate cases: 2250 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2251 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2252 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2253 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2254 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2255 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2256 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2257 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2258 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2259 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2260 if (RExtOp0.getOpcode() == ISD::SUB && 2261 RExtOp0.getOperand(1) == LExtOp0) { 2262 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2263 // (rotl x, y) 2264 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2265 // (rotr x, (sub 32, y)) 2266 if (ConstantSDNode *SUBC = 2267 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2268 if (SUBC->getAPIntValue() == OpSizeInBits) { 2269 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2270 LHSShiftArg, 2271 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2272 } 2273 } 2274 } else if (LExtOp0.getOpcode() == ISD::SUB && 2275 RExtOp0 == LExtOp0.getOperand(1)) { 2276 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2277 // (rotr x, y) 2278 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2279 // (rotl x, (sub 32, y)) 2280 if (ConstantSDNode *SUBC = 2281 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2282 if (SUBC->getAPIntValue() == OpSizeInBits) { 2283 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2284 LHSShiftArg, 2285 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2286 } 2287 } 2288 } 2289 } 2290 2291 return 0; 2292} 2293 2294SDValue DAGCombiner::visitXOR(SDNode *N) { 2295 SDValue N0 = N->getOperand(0); 2296 SDValue N1 = N->getOperand(1); 2297 SDValue LHS, RHS, CC; 2298 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2299 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2300 EVT VT = N0.getValueType(); 2301 2302 // fold vector ops 2303 if (VT.isVector()) { 2304 SDValue FoldedVOp = SimplifyVBinOp(N); 2305 if (FoldedVOp.getNode()) return FoldedVOp; 2306 } 2307 2308 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2309 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2310 return DAG.getConstant(0, VT); 2311 // fold (xor x, undef) -> undef 2312 if (N0.getOpcode() == ISD::UNDEF) 2313 return N0; 2314 if (N1.getOpcode() == ISD::UNDEF) 2315 return N1; 2316 // fold (xor c1, c2) -> c1^c2 2317 if (N0C && N1C) 2318 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2319 // canonicalize constant to RHS 2320 if (N0C && !N1C) 2321 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2322 // fold (xor x, 0) -> x 2323 if (N1C && N1C->isNullValue()) 2324 return N0; 2325 // reassociate xor 2326 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2327 if (RXOR.getNode() != 0) 2328 return RXOR; 2329 2330 // fold !(x cc y) -> (x !cc y) 2331 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2332 bool isInt = LHS.getValueType().isInteger(); 2333 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2334 isInt); 2335 2336 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2337 switch (N0.getOpcode()) { 2338 default: 2339 llvm_unreachable("Unhandled SetCC Equivalent!"); 2340 case ISD::SETCC: 2341 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2342 case ISD::SELECT_CC: 2343 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2344 N0.getOperand(3), NotCC); 2345 } 2346 } 2347 } 2348 2349 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2350 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2351 N0.getNode()->hasOneUse() && 2352 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2353 SDValue V = N0.getOperand(0); 2354 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2355 DAG.getConstant(1, V.getValueType())); 2356 AddToWorkList(V.getNode()); 2357 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2358 } 2359 2360 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2361 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2362 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2363 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2364 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2365 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2366 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2367 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2368 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2369 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2370 } 2371 } 2372 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2373 if (N1C && N1C->isAllOnesValue() && 2374 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2375 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2376 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2377 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2378 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2379 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2380 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2381 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2382 } 2383 } 2384 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2385 if (N1C && N0.getOpcode() == ISD::XOR) { 2386 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2387 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2388 if (N00C) 2389 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2390 DAG.getConstant(N1C->getAPIntValue() ^ 2391 N00C->getAPIntValue(), VT)); 2392 if (N01C) 2393 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2394 DAG.getConstant(N1C->getAPIntValue() ^ 2395 N01C->getAPIntValue(), VT)); 2396 } 2397 // fold (xor x, x) -> 0 2398 if (N0 == N1) { 2399 if (!VT.isVector()) { 2400 return DAG.getConstant(0, VT); 2401 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2402 // Produce a vector of zeros. 2403 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2404 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2405 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2406 &Ops[0], Ops.size()); 2407 } 2408 } 2409 2410 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2411 if (N0.getOpcode() == N1.getOpcode()) { 2412 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2413 if (Tmp.getNode()) return Tmp; 2414 } 2415 2416 // Simplify the expression using non-local knowledge. 2417 if (!VT.isVector() && 2418 SimplifyDemandedBits(SDValue(N, 0))) 2419 return SDValue(N, 0); 2420 2421 return SDValue(); 2422} 2423 2424/// visitShiftByConstant - Handle transforms common to the three shifts, when 2425/// the shift amount is a constant. 2426SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2427 SDNode *LHS = N->getOperand(0).getNode(); 2428 if (!LHS->hasOneUse()) return SDValue(); 2429 2430 // We want to pull some binops through shifts, so that we have (and (shift)) 2431 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2432 // thing happens with address calculations, so it's important to canonicalize 2433 // it. 2434 bool HighBitSet = false; // Can we transform this if the high bit is set? 2435 2436 switch (LHS->getOpcode()) { 2437 default: return SDValue(); 2438 case ISD::OR: 2439 case ISD::XOR: 2440 HighBitSet = false; // We can only transform sra if the high bit is clear. 2441 break; 2442 case ISD::AND: 2443 HighBitSet = true; // We can only transform sra if the high bit is set. 2444 break; 2445 case ISD::ADD: 2446 if (N->getOpcode() != ISD::SHL) 2447 return SDValue(); // only shl(add) not sr[al](add). 2448 HighBitSet = false; // We can only transform sra if the high bit is clear. 2449 break; 2450 } 2451 2452 // We require the RHS of the binop to be a constant as well. 2453 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2454 if (!BinOpCst) return SDValue(); 2455 2456 // FIXME: disable this unless the input to the binop is a shift by a constant. 2457 // If it is not a shift, it pessimizes some common cases like: 2458 // 2459 // void foo(int *X, int i) { X[i & 1235] = 1; } 2460 // int bar(int *X, int i) { return X[i & 255]; } 2461 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2462 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2463 BinOpLHSVal->getOpcode() != ISD::SRA && 2464 BinOpLHSVal->getOpcode() != ISD::SRL) || 2465 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2466 return SDValue(); 2467 2468 EVT VT = N->getValueType(0); 2469 2470 // If this is a signed shift right, and the high bit is modified by the 2471 // logical operation, do not perform the transformation. The highBitSet 2472 // boolean indicates the value of the high bit of the constant which would 2473 // cause it to be modified for this operation. 2474 if (N->getOpcode() == ISD::SRA) { 2475 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2476 if (BinOpRHSSignSet != HighBitSet) 2477 return SDValue(); 2478 } 2479 2480 // Fold the constants, shifting the binop RHS by the shift amount. 2481 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2482 N->getValueType(0), 2483 LHS->getOperand(1), N->getOperand(1)); 2484 2485 // Create the new shift. 2486 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2487 VT, LHS->getOperand(0), N->getOperand(1)); 2488 2489 // Create the new binop. 2490 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2491} 2492 2493SDValue DAGCombiner::visitSHL(SDNode *N) { 2494 SDValue N0 = N->getOperand(0); 2495 SDValue N1 = N->getOperand(1); 2496 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2498 EVT VT = N0.getValueType(); 2499 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2500 2501 // fold (shl c1, c2) -> c1<<c2 2502 if (N0C && N1C) 2503 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2504 // fold (shl 0, x) -> 0 2505 if (N0C && N0C->isNullValue()) 2506 return N0; 2507 // fold (shl x, c >= size(x)) -> undef 2508 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2509 return DAG.getUNDEF(VT); 2510 // fold (shl x, 0) -> x 2511 if (N1C && N1C->isNullValue()) 2512 return N0; 2513 // if (shl x, c) is known to be zero, return 0 2514 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2515 APInt::getAllOnesValue(OpSizeInBits))) 2516 return DAG.getConstant(0, VT); 2517 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2518 if (N1.getOpcode() == ISD::TRUNCATE && 2519 N1.getOperand(0).getOpcode() == ISD::AND && 2520 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2521 SDValue N101 = N1.getOperand(0).getOperand(1); 2522 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2523 EVT TruncVT = N1.getValueType(); 2524 SDValue N100 = N1.getOperand(0).getOperand(0); 2525 APInt TruncC = N101C->getAPIntValue(); 2526 TruncC.trunc(TruncVT.getSizeInBits()); 2527 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2528 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2529 DAG.getNode(ISD::TRUNCATE, 2530 N->getDebugLoc(), 2531 TruncVT, N100), 2532 DAG.getConstant(TruncC, TruncVT))); 2533 } 2534 } 2535 2536 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2537 return SDValue(N, 0); 2538 2539 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2540 if (N1C && N0.getOpcode() == ISD::SHL && 2541 N0.getOperand(1).getOpcode() == ISD::Constant) { 2542 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2543 uint64_t c2 = N1C->getZExtValue(); 2544 if (c1 + c2 > OpSizeInBits) 2545 return DAG.getConstant(0, VT); 2546 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2547 DAG.getConstant(c1 + c2, N1.getValueType())); 2548 } 2549 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2550 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2551 if (N1C && N0.getOpcode() == ISD::SRL && 2552 N0.getOperand(1).getOpcode() == ISD::Constant) { 2553 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2554 if (c1 < VT.getSizeInBits()) { 2555 uint64_t c2 = N1C->getZExtValue(); 2556 SDValue HiBitsMask = 2557 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2558 VT.getSizeInBits() - c1), 2559 VT); 2560 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2561 N0.getOperand(0), 2562 HiBitsMask); 2563 if (c2 > c1) 2564 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2565 DAG.getConstant(c2-c1, N1.getValueType())); 2566 else 2567 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2568 DAG.getConstant(c1-c2, N1.getValueType())); 2569 } 2570 } 2571 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2572 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2573 SDValue HiBitsMask = 2574 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2575 VT.getSizeInBits() - 2576 N1C->getZExtValue()), 2577 VT); 2578 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2579 HiBitsMask); 2580 } 2581 2582 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2583} 2584 2585SDValue DAGCombiner::visitSRA(SDNode *N) { 2586 SDValue N0 = N->getOperand(0); 2587 SDValue N1 = N->getOperand(1); 2588 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2589 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2590 EVT VT = N0.getValueType(); 2591 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2592 2593 // fold (sra c1, c2) -> (sra c1, c2) 2594 if (N0C && N1C) 2595 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2596 // fold (sra 0, x) -> 0 2597 if (N0C && N0C->isNullValue()) 2598 return N0; 2599 // fold (sra -1, x) -> -1 2600 if (N0C && N0C->isAllOnesValue()) 2601 return N0; 2602 // fold (sra x, (setge c, size(x))) -> undef 2603 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2604 return DAG.getUNDEF(VT); 2605 // fold (sra x, 0) -> x 2606 if (N1C && N1C->isNullValue()) 2607 return N0; 2608 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2609 // sext_inreg. 2610 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2611 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2612 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2613 if (VT.isVector()) 2614 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2615 ExtVT, VT.getVectorNumElements()); 2616 if ((!LegalOperations || 2617 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2618 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2619 N0.getOperand(0), DAG.getValueType(ExtVT)); 2620 } 2621 2622 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2623 if (N1C && N0.getOpcode() == ISD::SRA) { 2624 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2625 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2626 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2627 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2628 DAG.getConstant(Sum, N1C->getValueType(0))); 2629 } 2630 } 2631 2632 // fold (sra (shl X, m), (sub result_size, n)) 2633 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2634 // result_size - n != m. 2635 // If truncate is free for the target sext(shl) is likely to result in better 2636 // code. 2637 if (N0.getOpcode() == ISD::SHL) { 2638 // Get the two constanst of the shifts, CN0 = m, CN = n. 2639 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2640 if (N01C && N1C) { 2641 // Determine what the truncate's result bitsize and type would be. 2642 EVT TruncVT = 2643 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2644 // Determine the residual right-shift amount. 2645 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2646 2647 // If the shift is not a no-op (in which case this should be just a sign 2648 // extend already), the truncated to type is legal, sign_extend is legal 2649 // on that type, and the truncate to that type is both legal and free, 2650 // perform the transform. 2651 if ((ShiftAmt > 0) && 2652 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2653 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2654 TLI.isTruncateFree(VT, TruncVT)) { 2655 2656 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2657 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2658 N0.getOperand(0), Amt); 2659 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2660 Shift); 2661 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2662 N->getValueType(0), Trunc); 2663 } 2664 } 2665 } 2666 2667 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2668 if (N1.getOpcode() == ISD::TRUNCATE && 2669 N1.getOperand(0).getOpcode() == ISD::AND && 2670 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2671 SDValue N101 = N1.getOperand(0).getOperand(1); 2672 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2673 EVT TruncVT = N1.getValueType(); 2674 SDValue N100 = N1.getOperand(0).getOperand(0); 2675 APInt TruncC = N101C->getAPIntValue(); 2676 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 2677 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2678 DAG.getNode(ISD::AND, N->getDebugLoc(), 2679 TruncVT, 2680 DAG.getNode(ISD::TRUNCATE, 2681 N->getDebugLoc(), 2682 TruncVT, N100), 2683 DAG.getConstant(TruncC, TruncVT))); 2684 } 2685 } 2686 2687 // Simplify, based on bits shifted out of the LHS. 2688 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2689 return SDValue(N, 0); 2690 2691 2692 // If the sign bit is known to be zero, switch this to a SRL. 2693 if (DAG.SignBitIsZero(N0)) 2694 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2695 2696 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2697} 2698 2699SDValue DAGCombiner::visitSRL(SDNode *N) { 2700 SDValue N0 = N->getOperand(0); 2701 SDValue N1 = N->getOperand(1); 2702 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2703 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2704 EVT VT = N0.getValueType(); 2705 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2706 2707 // fold (srl c1, c2) -> c1 >>u c2 2708 if (N0C && N1C) 2709 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2710 // fold (srl 0, x) -> 0 2711 if (N0C && N0C->isNullValue()) 2712 return N0; 2713 // fold (srl x, c >= size(x)) -> undef 2714 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2715 return DAG.getUNDEF(VT); 2716 // fold (srl x, 0) -> x 2717 if (N1C && N1C->isNullValue()) 2718 return N0; 2719 // if (srl x, c) is known to be zero, return 0 2720 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2721 APInt::getAllOnesValue(OpSizeInBits))) 2722 return DAG.getConstant(0, VT); 2723 2724 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2725 if (N1C && N0.getOpcode() == ISD::SRL && 2726 N0.getOperand(1).getOpcode() == ISD::Constant) { 2727 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2728 uint64_t c2 = N1C->getZExtValue(); 2729 if (c1 + c2 > OpSizeInBits) 2730 return DAG.getConstant(0, VT); 2731 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2732 DAG.getConstant(c1 + c2, N1.getValueType())); 2733 } 2734 2735 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2736 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2737 // Shifting in all undef bits? 2738 EVT SmallVT = N0.getOperand(0).getValueType(); 2739 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2740 return DAG.getUNDEF(VT); 2741 2742 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2743 N0.getOperand(0), N1); 2744 AddToWorkList(SmallShift.getNode()); 2745 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2746 } 2747 2748 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2749 // bit, which is unmodified by sra. 2750 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2751 if (N0.getOpcode() == ISD::SRA) 2752 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2753 } 2754 2755 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2756 if (N1C && N0.getOpcode() == ISD::CTLZ && 2757 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2758 APInt KnownZero, KnownOne; 2759 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 2760 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2761 2762 // If any of the input bits are KnownOne, then the input couldn't be all 2763 // zeros, thus the result of the srl will always be zero. 2764 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2765 2766 // If all of the bits input the to ctlz node are known to be zero, then 2767 // the result of the ctlz is "32" and the result of the shift is one. 2768 APInt UnknownBits = ~KnownZero & Mask; 2769 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2770 2771 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2772 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2773 // Okay, we know that only that the single bit specified by UnknownBits 2774 // could be set on input to the CTLZ node. If this bit is set, the SRL 2775 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2776 // to an SRL/XOR pair, which is likely to simplify more. 2777 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2778 SDValue Op = N0.getOperand(0); 2779 2780 if (ShAmt) { 2781 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2782 DAG.getConstant(ShAmt, getShiftAmountTy())); 2783 AddToWorkList(Op.getNode()); 2784 } 2785 2786 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2787 Op, DAG.getConstant(1, VT)); 2788 } 2789 } 2790 2791 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2792 if (N1.getOpcode() == ISD::TRUNCATE && 2793 N1.getOperand(0).getOpcode() == ISD::AND && 2794 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2795 SDValue N101 = N1.getOperand(0).getOperand(1); 2796 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2797 EVT TruncVT = N1.getValueType(); 2798 SDValue N100 = N1.getOperand(0).getOperand(0); 2799 APInt TruncC = N101C->getAPIntValue(); 2800 TruncC.trunc(TruncVT.getSizeInBits()); 2801 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2802 DAG.getNode(ISD::AND, N->getDebugLoc(), 2803 TruncVT, 2804 DAG.getNode(ISD::TRUNCATE, 2805 N->getDebugLoc(), 2806 TruncVT, N100), 2807 DAG.getConstant(TruncC, TruncVT))); 2808 } 2809 } 2810 2811 // fold operands of srl based on knowledge that the low bits are not 2812 // demanded. 2813 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2814 return SDValue(N, 0); 2815 2816 if (N1C) { 2817 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 2818 if (NewSRL.getNode()) 2819 return NewSRL; 2820 } 2821 2822 // Here is a common situation. We want to optimize: 2823 // 2824 // %a = ... 2825 // %b = and i32 %a, 2 2826 // %c = srl i32 %b, 1 2827 // brcond i32 %c ... 2828 // 2829 // into 2830 // 2831 // %a = ... 2832 // %b = and %a, 2 2833 // %c = setcc eq %b, 0 2834 // brcond %c ... 2835 // 2836 // However when after the source operand of SRL is optimized into AND, the SRL 2837 // itself may not be optimized further. Look for it and add the BRCOND into 2838 // the worklist. 2839 if (N->hasOneUse()) { 2840 SDNode *Use = *N->use_begin(); 2841 if (Use->getOpcode() == ISD::BRCOND) 2842 AddToWorkList(Use); 2843 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 2844 // Also look pass the truncate. 2845 Use = *Use->use_begin(); 2846 if (Use->getOpcode() == ISD::BRCOND) 2847 AddToWorkList(Use); 2848 } 2849 } 2850 2851 return SDValue(); 2852} 2853 2854SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2855 SDValue N0 = N->getOperand(0); 2856 EVT VT = N->getValueType(0); 2857 2858 // fold (ctlz c1) -> c2 2859 if (isa<ConstantSDNode>(N0)) 2860 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2861 return SDValue(); 2862} 2863 2864SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2865 SDValue N0 = N->getOperand(0); 2866 EVT VT = N->getValueType(0); 2867 2868 // fold (cttz c1) -> c2 2869 if (isa<ConstantSDNode>(N0)) 2870 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2871 return SDValue(); 2872} 2873 2874SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2875 SDValue N0 = N->getOperand(0); 2876 EVT VT = N->getValueType(0); 2877 2878 // fold (ctpop c1) -> c2 2879 if (isa<ConstantSDNode>(N0)) 2880 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2881 return SDValue(); 2882} 2883 2884SDValue DAGCombiner::visitSELECT(SDNode *N) { 2885 SDValue N0 = N->getOperand(0); 2886 SDValue N1 = N->getOperand(1); 2887 SDValue N2 = N->getOperand(2); 2888 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2889 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2890 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2891 EVT VT = N->getValueType(0); 2892 EVT VT0 = N0.getValueType(); 2893 2894 // fold (select C, X, X) -> X 2895 if (N1 == N2) 2896 return N1; 2897 // fold (select true, X, Y) -> X 2898 if (N0C && !N0C->isNullValue()) 2899 return N1; 2900 // fold (select false, X, Y) -> Y 2901 if (N0C && N0C->isNullValue()) 2902 return N2; 2903 // fold (select C, 1, X) -> (or C, X) 2904 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2905 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2906 // fold (select C, 0, 1) -> (xor C, 1) 2907 if (VT.isInteger() && 2908 (VT0 == MVT::i1 || 2909 (VT0.isInteger() && 2910 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2911 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2912 SDValue XORNode; 2913 if (VT == VT0) 2914 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2915 N0, DAG.getConstant(1, VT0)); 2916 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2917 N0, DAG.getConstant(1, VT0)); 2918 AddToWorkList(XORNode.getNode()); 2919 if (VT.bitsGT(VT0)) 2920 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2921 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2922 } 2923 // fold (select C, 0, X) -> (and (not C), X) 2924 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2925 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2926 AddToWorkList(NOTNode.getNode()); 2927 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2928 } 2929 // fold (select C, X, 1) -> (or (not C), X) 2930 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2931 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2932 AddToWorkList(NOTNode.getNode()); 2933 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2934 } 2935 // fold (select C, X, 0) -> (and C, X) 2936 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2937 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2938 // fold (select X, X, Y) -> (or X, Y) 2939 // fold (select X, 1, Y) -> (or X, Y) 2940 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2941 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2942 // fold (select X, Y, X) -> (and X, Y) 2943 // fold (select X, Y, 0) -> (and X, Y) 2944 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2945 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2946 2947 // If we can fold this based on the true/false value, do so. 2948 if (SimplifySelectOps(N, N1, N2)) 2949 return SDValue(N, 0); // Don't revisit N. 2950 2951 // fold selects based on a setcc into other things, such as min/max/abs 2952 if (N0.getOpcode() == ISD::SETCC) { 2953 // FIXME: 2954 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2955 // having to say they don't support SELECT_CC on every type the DAG knows 2956 // about, since there is no way to mark an opcode illegal at all value types 2957 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2958 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2959 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2960 N0.getOperand(0), N0.getOperand(1), 2961 N1, N2, N0.getOperand(2)); 2962 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2963 } 2964 2965 return SDValue(); 2966} 2967 2968SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2969 SDValue N0 = N->getOperand(0); 2970 SDValue N1 = N->getOperand(1); 2971 SDValue N2 = N->getOperand(2); 2972 SDValue N3 = N->getOperand(3); 2973 SDValue N4 = N->getOperand(4); 2974 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2975 2976 // fold select_cc lhs, rhs, x, x, cc -> x 2977 if (N2 == N3) 2978 return N2; 2979 2980 // Determine if the condition we're dealing with is constant 2981 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2982 N0, N1, CC, N->getDebugLoc(), false); 2983 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2984 2985 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2986 if (!SCCC->isNullValue()) 2987 return N2; // cond always true -> true val 2988 else 2989 return N3; // cond always false -> false val 2990 } 2991 2992 // Fold to a simpler select_cc 2993 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2994 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2995 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2996 SCC.getOperand(2)); 2997 2998 // If we can fold this based on the true/false value, do so. 2999 if (SimplifySelectOps(N, N2, N3)) 3000 return SDValue(N, 0); // Don't revisit N. 3001 3002 // fold select_cc into other things, such as min/max/abs 3003 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3004} 3005 3006SDValue DAGCombiner::visitSETCC(SDNode *N) { 3007 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3008 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3009 N->getDebugLoc()); 3010} 3011 3012// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3013// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3014// transformation. Returns true if extension are possible and the above 3015// mentioned transformation is profitable. 3016static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3017 unsigned ExtOpc, 3018 SmallVector<SDNode*, 4> &ExtendNodes, 3019 const TargetLowering &TLI) { 3020 bool HasCopyToRegUses = false; 3021 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3022 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3023 UE = N0.getNode()->use_end(); 3024 UI != UE; ++UI) { 3025 SDNode *User = *UI; 3026 if (User == N) 3027 continue; 3028 if (UI.getUse().getResNo() != N0.getResNo()) 3029 continue; 3030 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3031 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3032 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3033 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3034 // Sign bits will be lost after a zext. 3035 return false; 3036 bool Add = false; 3037 for (unsigned i = 0; i != 2; ++i) { 3038 SDValue UseOp = User->getOperand(i); 3039 if (UseOp == N0) 3040 continue; 3041 if (!isa<ConstantSDNode>(UseOp)) 3042 return false; 3043 Add = true; 3044 } 3045 if (Add) 3046 ExtendNodes.push_back(User); 3047 continue; 3048 } 3049 // If truncates aren't free and there are users we can't 3050 // extend, it isn't worthwhile. 3051 if (!isTruncFree) 3052 return false; 3053 // Remember if this value is live-out. 3054 if (User->getOpcode() == ISD::CopyToReg) 3055 HasCopyToRegUses = true; 3056 } 3057 3058 if (HasCopyToRegUses) { 3059 bool BothLiveOut = false; 3060 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3061 UI != UE; ++UI) { 3062 SDUse &Use = UI.getUse(); 3063 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3064 BothLiveOut = true; 3065 break; 3066 } 3067 } 3068 if (BothLiveOut) 3069 // Both unextended and extended values are live out. There had better be 3070 // good a reason for the transformation. 3071 return ExtendNodes.size(); 3072 } 3073 return true; 3074} 3075 3076SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3077 SDValue N0 = N->getOperand(0); 3078 EVT VT = N->getValueType(0); 3079 3080 // fold (sext c1) -> c1 3081 if (isa<ConstantSDNode>(N0)) 3082 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3083 3084 // fold (sext (sext x)) -> (sext x) 3085 // fold (sext (aext x)) -> (sext x) 3086 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3087 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3088 N0.getOperand(0)); 3089 3090 if (N0.getOpcode() == ISD::TRUNCATE) { 3091 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3092 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3093 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3094 if (NarrowLoad.getNode()) { 3095 if (NarrowLoad.getNode() != N0.getNode()) 3096 CombineTo(N0.getNode(), NarrowLoad); 3097 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3098 } 3099 3100 // See if the value being truncated is already sign extended. If so, just 3101 // eliminate the trunc/sext pair. 3102 SDValue Op = N0.getOperand(0); 3103 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3104 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3105 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3106 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3107 3108 if (OpBits == DestBits) { 3109 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3110 // bits, it is already ready. 3111 if (NumSignBits > DestBits-MidBits) 3112 return Op; 3113 } else if (OpBits < DestBits) { 3114 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3115 // bits, just sext from i32. 3116 if (NumSignBits > OpBits-MidBits) 3117 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3118 } else { 3119 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3120 // bits, just truncate to i32. 3121 if (NumSignBits > OpBits-MidBits) 3122 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3123 } 3124 3125 // fold (sext (truncate x)) -> (sextinreg x). 3126 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3127 N0.getValueType())) { 3128 if (OpBits < DestBits) 3129 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3130 else if (OpBits > DestBits) 3131 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3132 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3133 DAG.getValueType(N0.getValueType())); 3134 } 3135 } 3136 3137 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3138 if (ISD::isNON_EXTLoad(N0.getNode()) && 3139 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3140 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3141 bool DoXform = true; 3142 SmallVector<SDNode*, 4> SetCCs; 3143 if (!N0.hasOneUse()) 3144 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3145 if (DoXform) { 3146 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3147 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3148 LN0->getChain(), 3149 LN0->getBasePtr(), LN0->getSrcValue(), 3150 LN0->getSrcValueOffset(), 3151 N0.getValueType(), 3152 LN0->isVolatile(), LN0->isNonTemporal(), 3153 LN0->getAlignment()); 3154 CombineTo(N, ExtLoad); 3155 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3156 N0.getValueType(), ExtLoad); 3157 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3158 3159 // Extend SetCC uses if necessary. 3160 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3161 SDNode *SetCC = SetCCs[i]; 3162 SmallVector<SDValue, 4> Ops; 3163 3164 for (unsigned j = 0; j != 2; ++j) { 3165 SDValue SOp = SetCC->getOperand(j); 3166 if (SOp == Trunc) 3167 Ops.push_back(ExtLoad); 3168 else 3169 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3170 N->getDebugLoc(), VT, SOp)); 3171 } 3172 3173 Ops.push_back(SetCC->getOperand(2)); 3174 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3175 SetCC->getValueType(0), 3176 &Ops[0], Ops.size())); 3177 } 3178 3179 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3180 } 3181 } 3182 3183 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3184 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3185 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3186 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3187 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3188 EVT MemVT = LN0->getMemoryVT(); 3189 if ((!LegalOperations && !LN0->isVolatile()) || 3190 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3191 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3192 LN0->getChain(), 3193 LN0->getBasePtr(), LN0->getSrcValue(), 3194 LN0->getSrcValueOffset(), MemVT, 3195 LN0->isVolatile(), LN0->isNonTemporal(), 3196 LN0->getAlignment()); 3197 CombineTo(N, ExtLoad); 3198 CombineTo(N0.getNode(), 3199 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3200 N0.getValueType(), ExtLoad), 3201 ExtLoad.getValue(1)); 3202 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3203 } 3204 } 3205 3206 if (N0.getOpcode() == ISD::SETCC) { 3207 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3208 if (VT.isVector() && 3209 // We know that the # elements of the results is the same as the 3210 // # elements of the compare (and the # elements of the compare result 3211 // for that matter). Check to see that they are the same size. If so, 3212 // we know that the element size of the sext'd result matches the 3213 // element size of the compare operands. 3214 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3215 3216 // Only do this before legalize for now. 3217 !LegalOperations) { 3218 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3219 N0.getOperand(1), 3220 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3221 } 3222 3223 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3224 SDValue NegOne = 3225 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3226 SDValue SCC = 3227 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3228 NegOne, DAG.getConstant(0, VT), 3229 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3230 if (SCC.getNode()) return SCC; 3231 if (!LegalOperations || 3232 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3233 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3234 DAG.getSetCC(N->getDebugLoc(), 3235 TLI.getSetCCResultType(VT), 3236 N0.getOperand(0), N0.getOperand(1), 3237 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3238 NegOne, DAG.getConstant(0, VT)); 3239 } 3240 3241 3242 3243 // fold (sext x) -> (zext x) if the sign bit is known zero. 3244 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3245 DAG.SignBitIsZero(N0)) 3246 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3247 3248 return SDValue(); 3249} 3250 3251SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3252 SDValue N0 = N->getOperand(0); 3253 EVT VT = N->getValueType(0); 3254 3255 // fold (zext c1) -> c1 3256 if (isa<ConstantSDNode>(N0)) 3257 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3258 // fold (zext (zext x)) -> (zext x) 3259 // fold (zext (aext x)) -> (zext x) 3260 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3261 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3262 N0.getOperand(0)); 3263 3264 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3265 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3266 if (N0.getOpcode() == ISD::TRUNCATE) { 3267 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3268 if (NarrowLoad.getNode()) { 3269 if (NarrowLoad.getNode() != N0.getNode()) 3270 CombineTo(N0.getNode(), NarrowLoad); 3271 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3272 } 3273 } 3274 3275 // fold (zext (truncate x)) -> (and x, mask) 3276 if (N0.getOpcode() == ISD::TRUNCATE && 3277 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) && 3278 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(), 3279 N0.getValueType()) || 3280 !TLI.isZExtFree(N0.getValueType(), VT))) { 3281 SDValue Op = N0.getOperand(0); 3282 if (Op.getValueType().bitsLT(VT)) { 3283 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3284 } else if (Op.getValueType().bitsGT(VT)) { 3285 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3286 } 3287 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3288 N0.getValueType().getScalarType()); 3289 } 3290 3291 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3292 // if either of the casts is not free. 3293 if (N0.getOpcode() == ISD::AND && 3294 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3295 N0.getOperand(1).getOpcode() == ISD::Constant && 3296 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3297 N0.getValueType()) || 3298 !TLI.isZExtFree(N0.getValueType(), VT))) { 3299 SDValue X = N0.getOperand(0).getOperand(0); 3300 if (X.getValueType().bitsLT(VT)) { 3301 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3302 } else if (X.getValueType().bitsGT(VT)) { 3303 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3304 } 3305 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3306 Mask.zext(VT.getSizeInBits()); 3307 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3308 X, DAG.getConstant(Mask, VT)); 3309 } 3310 3311 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3312 if (ISD::isNON_EXTLoad(N0.getNode()) && 3313 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3314 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3315 bool DoXform = true; 3316 SmallVector<SDNode*, 4> SetCCs; 3317 if (!N0.hasOneUse()) 3318 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3319 if (DoXform) { 3320 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3321 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3322 LN0->getChain(), 3323 LN0->getBasePtr(), LN0->getSrcValue(), 3324 LN0->getSrcValueOffset(), 3325 N0.getValueType(), 3326 LN0->isVolatile(), LN0->isNonTemporal(), 3327 LN0->getAlignment()); 3328 CombineTo(N, ExtLoad); 3329 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3330 N0.getValueType(), ExtLoad); 3331 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3332 3333 // Extend SetCC uses if necessary. 3334 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3335 SDNode *SetCC = SetCCs[i]; 3336 SmallVector<SDValue, 4> Ops; 3337 3338 for (unsigned j = 0; j != 2; ++j) { 3339 SDValue SOp = SetCC->getOperand(j); 3340 if (SOp == Trunc) 3341 Ops.push_back(ExtLoad); 3342 else 3343 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3344 N->getDebugLoc(), VT, SOp)); 3345 } 3346 3347 Ops.push_back(SetCC->getOperand(2)); 3348 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3349 SetCC->getValueType(0), 3350 &Ops[0], Ops.size())); 3351 } 3352 3353 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3354 } 3355 } 3356 3357 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3358 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3359 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3360 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3361 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3362 EVT MemVT = LN0->getMemoryVT(); 3363 if ((!LegalOperations && !LN0->isVolatile()) || 3364 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3365 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3366 LN0->getChain(), 3367 LN0->getBasePtr(), LN0->getSrcValue(), 3368 LN0->getSrcValueOffset(), MemVT, 3369 LN0->isVolatile(), LN0->isNonTemporal(), 3370 LN0->getAlignment()); 3371 CombineTo(N, ExtLoad); 3372 CombineTo(N0.getNode(), 3373 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3374 ExtLoad), 3375 ExtLoad.getValue(1)); 3376 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3377 } 3378 } 3379 3380 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3381 if (N0.getOpcode() == ISD::SETCC) { 3382 SDValue SCC = 3383 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3384 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3385 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3386 if (SCC.getNode()) return SCC; 3387 } 3388 3389 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3390 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3391 isa<ConstantSDNode>(N0.getOperand(1)) && 3392 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3393 N0.hasOneUse()) { 3394 if (N0.getOpcode() == ISD::SHL) { 3395 // If the original shl may be shifting out bits, do not perform this 3396 // transformation. 3397 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3398 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3399 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3400 if (ShAmt > KnownZeroBits) 3401 return SDValue(); 3402 } 3403 DebugLoc dl = N->getDebugLoc(); 3404 return DAG.getNode(N0.getOpcode(), dl, VT, 3405 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3406 DAG.getNode(ISD::ZERO_EXTEND, dl, 3407 N0.getOperand(1).getValueType(), 3408 N0.getOperand(1))); 3409 } 3410 3411 return SDValue(); 3412} 3413 3414SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3415 SDValue N0 = N->getOperand(0); 3416 EVT VT = N->getValueType(0); 3417 3418 // fold (aext c1) -> c1 3419 if (isa<ConstantSDNode>(N0)) 3420 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3421 // fold (aext (aext x)) -> (aext x) 3422 // fold (aext (zext x)) -> (zext x) 3423 // fold (aext (sext x)) -> (sext x) 3424 if (N0.getOpcode() == ISD::ANY_EXTEND || 3425 N0.getOpcode() == ISD::ZERO_EXTEND || 3426 N0.getOpcode() == ISD::SIGN_EXTEND) 3427 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3428 3429 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3430 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3431 if (N0.getOpcode() == ISD::TRUNCATE) { 3432 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3433 if (NarrowLoad.getNode()) { 3434 if (NarrowLoad.getNode() != N0.getNode()) 3435 CombineTo(N0.getNode(), NarrowLoad); 3436 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3437 } 3438 } 3439 3440 // fold (aext (truncate x)) 3441 if (N0.getOpcode() == ISD::TRUNCATE) { 3442 SDValue TruncOp = N0.getOperand(0); 3443 if (TruncOp.getValueType() == VT) 3444 return TruncOp; // x iff x size == zext size. 3445 if (TruncOp.getValueType().bitsGT(VT)) 3446 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3447 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3448 } 3449 3450 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3451 // if the trunc is not free. 3452 if (N0.getOpcode() == ISD::AND && 3453 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3454 N0.getOperand(1).getOpcode() == ISD::Constant && 3455 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3456 N0.getValueType())) { 3457 SDValue X = N0.getOperand(0).getOperand(0); 3458 if (X.getValueType().bitsLT(VT)) { 3459 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3460 } else if (X.getValueType().bitsGT(VT)) { 3461 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3462 } 3463 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3464 Mask.zext(VT.getSizeInBits()); 3465 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3466 X, DAG.getConstant(Mask, VT)); 3467 } 3468 3469 // fold (aext (load x)) -> (aext (truncate (extload x))) 3470 if (ISD::isNON_EXTLoad(N0.getNode()) && 3471 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3472 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3473 bool DoXform = true; 3474 SmallVector<SDNode*, 4> SetCCs; 3475 if (!N0.hasOneUse()) 3476 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3477 if (DoXform) { 3478 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3479 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3480 LN0->getChain(), 3481 LN0->getBasePtr(), LN0->getSrcValue(), 3482 LN0->getSrcValueOffset(), 3483 N0.getValueType(), 3484 LN0->isVolatile(), LN0->isNonTemporal(), 3485 LN0->getAlignment()); 3486 CombineTo(N, ExtLoad); 3487 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3488 N0.getValueType(), ExtLoad); 3489 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3490 3491 // Extend SetCC uses if necessary. 3492 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3493 SDNode *SetCC = SetCCs[i]; 3494 SmallVector<SDValue, 4> Ops; 3495 3496 for (unsigned j = 0; j != 2; ++j) { 3497 SDValue SOp = SetCC->getOperand(j); 3498 if (SOp == Trunc) 3499 Ops.push_back(ExtLoad); 3500 else 3501 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3502 N->getDebugLoc(), VT, SOp)); 3503 } 3504 3505 Ops.push_back(SetCC->getOperand(2)); 3506 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3507 SetCC->getValueType(0), 3508 &Ops[0], Ops.size())); 3509 } 3510 3511 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3512 } 3513 } 3514 3515 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3516 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3517 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3518 if (N0.getOpcode() == ISD::LOAD && 3519 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3520 N0.hasOneUse()) { 3521 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3522 EVT MemVT = LN0->getMemoryVT(); 3523 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3524 VT, LN0->getChain(), LN0->getBasePtr(), 3525 LN0->getSrcValue(), 3526 LN0->getSrcValueOffset(), MemVT, 3527 LN0->isVolatile(), LN0->isNonTemporal(), 3528 LN0->getAlignment()); 3529 CombineTo(N, ExtLoad); 3530 CombineTo(N0.getNode(), 3531 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3532 N0.getValueType(), ExtLoad), 3533 ExtLoad.getValue(1)); 3534 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3535 } 3536 3537 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3538 if (N0.getOpcode() == ISD::SETCC) { 3539 SDValue SCC = 3540 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3541 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3542 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3543 if (SCC.getNode()) 3544 return SCC; 3545 } 3546 3547 return SDValue(); 3548} 3549 3550/// GetDemandedBits - See if the specified operand can be simplified with the 3551/// knowledge that only the bits specified by Mask are used. If so, return the 3552/// simpler operand, otherwise return a null SDValue. 3553SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3554 switch (V.getOpcode()) { 3555 default: break; 3556 case ISD::OR: 3557 case ISD::XOR: 3558 // If the LHS or RHS don't contribute bits to the or, drop them. 3559 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3560 return V.getOperand(1); 3561 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3562 return V.getOperand(0); 3563 break; 3564 case ISD::SRL: 3565 // Only look at single-use SRLs. 3566 if (!V.getNode()->hasOneUse()) 3567 break; 3568 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3569 // See if we can recursively simplify the LHS. 3570 unsigned Amt = RHSC->getZExtValue(); 3571 3572 // Watch out for shift count overflow though. 3573 if (Amt >= Mask.getBitWidth()) break; 3574 APInt NewMask = Mask << Amt; 3575 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3576 if (SimplifyLHS.getNode()) 3577 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3578 SimplifyLHS, V.getOperand(1)); 3579 } 3580 } 3581 return SDValue(); 3582} 3583 3584/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3585/// bits and then truncated to a narrower type and where N is a multiple 3586/// of number of bits of the narrower type, transform it to a narrower load 3587/// from address + N / num of bits of new type. If the result is to be 3588/// extended, also fold the extension to form a extending load. 3589SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3590 unsigned Opc = N->getOpcode(); 3591 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3592 SDValue N0 = N->getOperand(0); 3593 EVT VT = N->getValueType(0); 3594 EVT ExtVT = VT; 3595 3596 // This transformation isn't valid for vector loads. 3597 if (VT.isVector()) 3598 return SDValue(); 3599 3600 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 3601 // extended to VT. 3602 if (Opc == ISD::SIGN_EXTEND_INREG) { 3603 ExtType = ISD::SEXTLOAD; 3604 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3605 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 3606 return SDValue(); 3607 } 3608 3609 unsigned EVTBits = ExtVT.getSizeInBits(); 3610 unsigned ShAmt = 0; 3611 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 3612 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3613 ShAmt = N01->getZExtValue(); 3614 // Is the shift amount a multiple of size of VT? 3615 if ((ShAmt & (EVTBits-1)) == 0) { 3616 N0 = N0.getOperand(0); 3617 // Is the load width a multiple of size of VT? 3618 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 3619 return SDValue(); 3620 } 3621 } 3622 } 3623 3624 // Do not generate loads of non-round integer types since these can 3625 // be expensive (and would be wrong if the type is not byte sized). 3626 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 3627 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3628 // Do not change the width of a volatile load. 3629 !cast<LoadSDNode>(N0)->isVolatile()) { 3630 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3631 EVT PtrType = N0.getOperand(1).getValueType(); 3632 3633 // For big endian targets, we need to adjust the offset to the pointer to 3634 // load the correct bytes. 3635 if (TLI.isBigEndian()) { 3636 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3637 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 3638 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3639 } 3640 3641 uint64_t PtrOff = ShAmt / 8; 3642 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3643 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3644 PtrType, LN0->getBasePtr(), 3645 DAG.getConstant(PtrOff, PtrType)); 3646 AddToWorkList(NewPtr.getNode()); 3647 3648 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3649 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3650 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3651 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign) 3652 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3653 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3654 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 3655 NewAlign); 3656 3657 // Replace the old load's chain with the new load's chain. 3658 WorkListRemover DeadNodes(*this); 3659 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3660 &DeadNodes); 3661 3662 // Return the new loaded value. 3663 return Load; 3664 } 3665 3666 return SDValue(); 3667} 3668 3669SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3670 SDValue N0 = N->getOperand(0); 3671 SDValue N1 = N->getOperand(1); 3672 EVT VT = N->getValueType(0); 3673 EVT EVT = cast<VTSDNode>(N1)->getVT(); 3674 unsigned VTBits = VT.getScalarType().getSizeInBits(); 3675 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 3676 3677 // fold (sext_in_reg c1) -> c1 3678 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3679 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3680 3681 // If the input is already sign extended, just drop the extension. 3682 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 3683 return N0; 3684 3685 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3686 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3687 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3688 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3689 N0.getOperand(0), N1); 3690 } 3691 3692 // fold (sext_in_reg (sext x)) -> (sext x) 3693 // fold (sext_in_reg (aext x)) -> (sext x) 3694 // if x is small enough. 3695 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3696 SDValue N00 = N0.getOperand(0); 3697 if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits) 3698 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3699 } 3700 3701 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3702 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3703 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3704 3705 // fold operands of sext_in_reg based on knowledge that the top bits are not 3706 // demanded. 3707 if (SimplifyDemandedBits(SDValue(N, 0))) 3708 return SDValue(N, 0); 3709 3710 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3711 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3712 SDValue NarrowLoad = ReduceLoadWidth(N); 3713 if (NarrowLoad.getNode()) 3714 return NarrowLoad; 3715 3716 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3717 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3718 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3719 if (N0.getOpcode() == ISD::SRL) { 3720 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3721 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 3722 // We can turn this into an SRA iff the input to the SRL is already sign 3723 // extended enough. 3724 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3725 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3726 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3727 N0.getOperand(0), N0.getOperand(1)); 3728 } 3729 } 3730 3731 // fold (sext_inreg (extload x)) -> (sextload x) 3732 if (ISD::isEXTLoad(N0.getNode()) && 3733 ISD::isUNINDEXEDLoad(N0.getNode()) && 3734 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3735 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3736 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3737 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3738 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3739 LN0->getChain(), 3740 LN0->getBasePtr(), LN0->getSrcValue(), 3741 LN0->getSrcValueOffset(), EVT, 3742 LN0->isVolatile(), LN0->isNonTemporal(), 3743 LN0->getAlignment()); 3744 CombineTo(N, ExtLoad); 3745 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3746 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3747 } 3748 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3749 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3750 N0.hasOneUse() && 3751 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3752 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3753 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3754 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3755 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3756 LN0->getChain(), 3757 LN0->getBasePtr(), LN0->getSrcValue(), 3758 LN0->getSrcValueOffset(), EVT, 3759 LN0->isVolatile(), LN0->isNonTemporal(), 3760 LN0->getAlignment()); 3761 CombineTo(N, ExtLoad); 3762 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3763 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3764 } 3765 return SDValue(); 3766} 3767 3768SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3769 SDValue N0 = N->getOperand(0); 3770 EVT VT = N->getValueType(0); 3771 3772 // noop truncate 3773 if (N0.getValueType() == N->getValueType(0)) 3774 return N0; 3775 // fold (truncate c1) -> c1 3776 if (isa<ConstantSDNode>(N0)) 3777 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3778 // fold (truncate (truncate x)) -> (truncate x) 3779 if (N0.getOpcode() == ISD::TRUNCATE) 3780 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3781 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3782 if (N0.getOpcode() == ISD::ZERO_EXTEND || 3783 N0.getOpcode() == ISD::SIGN_EXTEND || 3784 N0.getOpcode() == ISD::ANY_EXTEND) { 3785 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3786 // if the source is smaller than the dest, we still need an extend 3787 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3788 N0.getOperand(0)); 3789 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3790 // if the source is larger than the dest, than we just need the truncate 3791 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3792 else 3793 // if the source and dest are the same type, we can drop both the extend 3794 // and the truncate. 3795 return N0.getOperand(0); 3796 } 3797 3798 // See if we can simplify the input to this truncate through knowledge that 3799 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3800 // -> trunc y 3801 SDValue Shorter = 3802 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3803 VT.getSizeInBits())); 3804 if (Shorter.getNode()) 3805 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3806 3807 // fold (truncate (load x)) -> (smaller load x) 3808 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3809 return ReduceLoadWidth(N); 3810} 3811 3812static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3813 SDValue Elt = N->getOperand(i); 3814 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3815 return Elt.getNode(); 3816 return Elt.getOperand(Elt.getResNo()).getNode(); 3817} 3818 3819/// CombineConsecutiveLoads - build_pair (load, load) -> load 3820/// if load locations are consecutive. 3821SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 3822 assert(N->getOpcode() == ISD::BUILD_PAIR); 3823 3824 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3825 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3826 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3827 return SDValue(); 3828 EVT LD1VT = LD1->getValueType(0); 3829 3830 if (ISD::isNON_EXTLoad(LD2) && 3831 LD2->hasOneUse() && 3832 // If both are volatile this would reduce the number of volatile loads. 3833 // If one is volatile it might be ok, but play conservative and bail out. 3834 !LD1->isVolatile() && 3835 !LD2->isVolatile() && 3836 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 3837 unsigned Align = LD1->getAlignment(); 3838 unsigned NewAlign = TLI.getTargetData()-> 3839 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3840 3841 if (NewAlign <= Align && 3842 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3843 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3844 LD1->getBasePtr(), LD1->getSrcValue(), 3845 LD1->getSrcValueOffset(), false, false, Align); 3846 } 3847 3848 return SDValue(); 3849} 3850 3851SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3852 SDValue N0 = N->getOperand(0); 3853 EVT VT = N->getValueType(0); 3854 3855 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3856 // Only do this before legalize, since afterward the target may be depending 3857 // on the bitconvert. 3858 // First check to see if this is all constant. 3859 if (!LegalTypes && 3860 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3861 VT.isVector()) { 3862 bool isSimple = true; 3863 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3864 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3865 N0.getOperand(i).getOpcode() != ISD::Constant && 3866 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3867 isSimple = false; 3868 break; 3869 } 3870 3871 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 3872 assert(!DestEltVT.isVector() && 3873 "Element type of vector ValueType must not be vector!"); 3874 if (isSimple) 3875 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3876 } 3877 3878 // If the input is a constant, let getNode fold it. 3879 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3880 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3881 if (Res.getNode() != N) { 3882 if (!LegalOperations || 3883 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 3884 return Res; 3885 3886 // Folding it resulted in an illegal node, and it's too late to 3887 // do that. Clean up the old node and forego the transformation. 3888 // Ideally this won't happen very often, because instcombine 3889 // and the earlier dagcombine runs (where illegal nodes are 3890 // permitted) should have folded most of them already. 3891 DAG.DeleteNode(Res.getNode()); 3892 } 3893 } 3894 3895 // (conv (conv x, t1), t2) -> (conv x, t2) 3896 if (N0.getOpcode() == ISD::BIT_CONVERT) 3897 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3898 N0.getOperand(0)); 3899 3900 // fold (conv (load x)) -> (load (conv*)x) 3901 // If the resultant load doesn't need a higher alignment than the original! 3902 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3903 // Do not change the width of a volatile load. 3904 !cast<LoadSDNode>(N0)->isVolatile() && 3905 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3906 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3907 unsigned Align = TLI.getTargetData()-> 3908 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3909 unsigned OrigAlign = LN0->getAlignment(); 3910 3911 if (Align <= OrigAlign) { 3912 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3913 LN0->getBasePtr(), 3914 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3915 LN0->isVolatile(), LN0->isNonTemporal(), 3916 OrigAlign); 3917 AddToWorkList(N); 3918 CombineTo(N0.getNode(), 3919 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3920 N0.getValueType(), Load), 3921 Load.getValue(1)); 3922 return Load; 3923 } 3924 } 3925 3926 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3927 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3928 // This often reduces constant pool loads. 3929 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3930 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3931 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3932 N0.getOperand(0)); 3933 AddToWorkList(NewConv.getNode()); 3934 3935 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3936 if (N0.getOpcode() == ISD::FNEG) 3937 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3938 NewConv, DAG.getConstant(SignBit, VT)); 3939 assert(N0.getOpcode() == ISD::FABS); 3940 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3941 NewConv, DAG.getConstant(~SignBit, VT)); 3942 } 3943 3944 // fold (bitconvert (fcopysign cst, x)) -> 3945 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3946 // Note that we don't handle (copysign x, cst) because this can always be 3947 // folded to an fneg or fabs. 3948 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3949 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3950 VT.isInteger() && !VT.isVector()) { 3951 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3952 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 3953 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3954 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3955 IntXVT, N0.getOperand(1)); 3956 AddToWorkList(X.getNode()); 3957 3958 // If X has a different width than the result/lhs, sext it or truncate it. 3959 unsigned VTWidth = VT.getSizeInBits(); 3960 if (OrigXWidth < VTWidth) { 3961 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3962 AddToWorkList(X.getNode()); 3963 } else if (OrigXWidth > VTWidth) { 3964 // To get the sign bit in the right place, we have to shift it right 3965 // before truncating. 3966 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3967 X.getValueType(), X, 3968 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3969 AddToWorkList(X.getNode()); 3970 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3971 AddToWorkList(X.getNode()); 3972 } 3973 3974 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3975 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3976 X, DAG.getConstant(SignBit, VT)); 3977 AddToWorkList(X.getNode()); 3978 3979 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3980 VT, N0.getOperand(0)); 3981 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3982 Cst, DAG.getConstant(~SignBit, VT)); 3983 AddToWorkList(Cst.getNode()); 3984 3985 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3986 } 3987 } 3988 3989 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3990 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3991 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3992 if (CombineLD.getNode()) 3993 return CombineLD; 3994 } 3995 3996 return SDValue(); 3997} 3998 3999SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4000 EVT VT = N->getValueType(0); 4001 return CombineConsecutiveLoads(N, VT); 4002} 4003 4004/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 4005/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4006/// destination element value type. 4007SDValue DAGCombiner:: 4008ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4009 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4010 4011 // If this is already the right type, we're done. 4012 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4013 4014 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4015 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4016 4017 // If this is a conversion of N elements of one type to N elements of another 4018 // type, convert each element. This handles FP<->INT cases. 4019 if (SrcBitSize == DstBitSize) { 4020 SmallVector<SDValue, 8> Ops; 4021 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4022 SDValue Op = BV->getOperand(i); 4023 // If the vector element type is not legal, the BUILD_VECTOR operands 4024 // are promoted and implicitly truncated. Make that explicit here. 4025 if (Op.getValueType() != SrcEltVT) 4026 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4027 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 4028 DstEltVT, Op)); 4029 AddToWorkList(Ops.back().getNode()); 4030 } 4031 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4032 BV->getValueType(0).getVectorNumElements()); 4033 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4034 &Ops[0], Ops.size()); 4035 } 4036 4037 // Otherwise, we're growing or shrinking the elements. To avoid having to 4038 // handle annoying details of growing/shrinking FP values, we convert them to 4039 // int first. 4040 if (SrcEltVT.isFloatingPoint()) { 4041 // Convert the input float vector to a int vector where the elements are the 4042 // same sizes. 4043 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4044 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4045 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 4046 SrcEltVT = IntVT; 4047 } 4048 4049 // Now we know the input is an integer vector. If the output is a FP type, 4050 // convert to integer first, then to FP of the right size. 4051 if (DstEltVT.isFloatingPoint()) { 4052 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4053 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4054 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4055 4056 // Next, convert to FP elements of the same size. 4057 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4058 } 4059 4060 // Okay, we know the src/dst types are both integers of differing types. 4061 // Handling growing first. 4062 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4063 if (SrcBitSize < DstBitSize) { 4064 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4065 4066 SmallVector<SDValue, 8> Ops; 4067 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4068 i += NumInputsPerOutput) { 4069 bool isLE = TLI.isLittleEndian(); 4070 APInt NewBits = APInt(DstBitSize, 0); 4071 bool EltIsUndef = true; 4072 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4073 // Shift the previously computed bits over. 4074 NewBits <<= SrcBitSize; 4075 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4076 if (Op.getOpcode() == ISD::UNDEF) continue; 4077 EltIsUndef = false; 4078 4079 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4080 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4081 } 4082 4083 if (EltIsUndef) 4084 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4085 else 4086 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4087 } 4088 4089 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4090 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4091 &Ops[0], Ops.size()); 4092 } 4093 4094 // Finally, this must be the case where we are shrinking elements: each input 4095 // turns into multiple outputs. 4096 bool isS2V = ISD::isScalarToVector(BV); 4097 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4098 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4099 NumOutputsPerInput*BV->getNumOperands()); 4100 SmallVector<SDValue, 8> Ops; 4101 4102 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4103 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4104 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4105 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4106 continue; 4107 } 4108 4109 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4110 getAPIntValue()).zextOrTrunc(SrcBitSize); 4111 4112 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4113 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4114 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4115 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4116 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4117 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4118 Ops[0]); 4119 OpVal = OpVal.lshr(DstBitSize); 4120 } 4121 4122 // For big endian targets, swap the order of the pieces of each element. 4123 if (TLI.isBigEndian()) 4124 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4125 } 4126 4127 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4128 &Ops[0], Ops.size()); 4129} 4130 4131SDValue DAGCombiner::visitFADD(SDNode *N) { 4132 SDValue N0 = N->getOperand(0); 4133 SDValue N1 = N->getOperand(1); 4134 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4135 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4136 EVT VT = N->getValueType(0); 4137 4138 // fold vector ops 4139 if (VT.isVector()) { 4140 SDValue FoldedVOp = SimplifyVBinOp(N); 4141 if (FoldedVOp.getNode()) return FoldedVOp; 4142 } 4143 4144 // fold (fadd c1, c2) -> (fadd c1, c2) 4145 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4146 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4147 // canonicalize constant to RHS 4148 if (N0CFP && !N1CFP) 4149 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4150 // fold (fadd A, 0) -> A 4151 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4152 return N0; 4153 // fold (fadd A, (fneg B)) -> (fsub A, B) 4154 if (isNegatibleForFree(N1, LegalOperations) == 2) 4155 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4156 GetNegatedExpression(N1, DAG, LegalOperations)); 4157 // fold (fadd (fneg A), B) -> (fsub B, A) 4158 if (isNegatibleForFree(N0, LegalOperations) == 2) 4159 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4160 GetNegatedExpression(N0, DAG, LegalOperations)); 4161 4162 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4163 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4164 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4165 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4166 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4167 N0.getOperand(1), N1)); 4168 4169 return SDValue(); 4170} 4171 4172SDValue DAGCombiner::visitFSUB(SDNode *N) { 4173 SDValue N0 = N->getOperand(0); 4174 SDValue N1 = N->getOperand(1); 4175 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4176 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4177 EVT VT = N->getValueType(0); 4178 4179 // fold vector ops 4180 if (VT.isVector()) { 4181 SDValue FoldedVOp = SimplifyVBinOp(N); 4182 if (FoldedVOp.getNode()) return FoldedVOp; 4183 } 4184 4185 // fold (fsub c1, c2) -> c1-c2 4186 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4187 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4188 // fold (fsub A, 0) -> A 4189 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4190 return N0; 4191 // fold (fsub 0, B) -> -B 4192 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4193 if (isNegatibleForFree(N1, LegalOperations)) 4194 return GetNegatedExpression(N1, DAG, LegalOperations); 4195 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4196 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4197 } 4198 // fold (fsub A, (fneg B)) -> (fadd A, B) 4199 if (isNegatibleForFree(N1, LegalOperations)) 4200 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4201 GetNegatedExpression(N1, DAG, LegalOperations)); 4202 4203 return SDValue(); 4204} 4205 4206SDValue DAGCombiner::visitFMUL(SDNode *N) { 4207 SDValue N0 = N->getOperand(0); 4208 SDValue N1 = N->getOperand(1); 4209 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4210 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4211 EVT VT = N->getValueType(0); 4212 4213 // fold vector ops 4214 if (VT.isVector()) { 4215 SDValue FoldedVOp = SimplifyVBinOp(N); 4216 if (FoldedVOp.getNode()) return FoldedVOp; 4217 } 4218 4219 // fold (fmul c1, c2) -> c1*c2 4220 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4221 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4222 // canonicalize constant to RHS 4223 if (N0CFP && !N1CFP) 4224 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4225 // fold (fmul A, 0) -> 0 4226 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4227 return N1; 4228 // fold (fmul A, 0) -> 0, vector edition. 4229 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4230 return N1; 4231 // fold (fmul X, 2.0) -> (fadd X, X) 4232 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4233 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4234 // fold (fmul X, -1.0) -> (fneg X) 4235 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4236 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4237 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4238 4239 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4240 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4241 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4242 // Both can be negated for free, check to see if at least one is cheaper 4243 // negated. 4244 if (LHSNeg == 2 || RHSNeg == 2) 4245 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4246 GetNegatedExpression(N0, DAG, LegalOperations), 4247 GetNegatedExpression(N1, DAG, LegalOperations)); 4248 } 4249 } 4250 4251 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4252 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4253 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4254 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4255 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4256 N0.getOperand(1), N1)); 4257 4258 return SDValue(); 4259} 4260 4261SDValue DAGCombiner::visitFDIV(SDNode *N) { 4262 SDValue N0 = N->getOperand(0); 4263 SDValue N1 = N->getOperand(1); 4264 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4265 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4266 EVT VT = N->getValueType(0); 4267 4268 // fold vector ops 4269 if (VT.isVector()) { 4270 SDValue FoldedVOp = SimplifyVBinOp(N); 4271 if (FoldedVOp.getNode()) return FoldedVOp; 4272 } 4273 4274 // fold (fdiv c1, c2) -> c1/c2 4275 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4276 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4277 4278 4279 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4280 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4281 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4282 // Both can be negated for free, check to see if at least one is cheaper 4283 // negated. 4284 if (LHSNeg == 2 || RHSNeg == 2) 4285 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4286 GetNegatedExpression(N0, DAG, LegalOperations), 4287 GetNegatedExpression(N1, DAG, LegalOperations)); 4288 } 4289 } 4290 4291 return SDValue(); 4292} 4293 4294SDValue DAGCombiner::visitFREM(SDNode *N) { 4295 SDValue N0 = N->getOperand(0); 4296 SDValue N1 = N->getOperand(1); 4297 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4298 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4299 EVT VT = N->getValueType(0); 4300 4301 // fold (frem c1, c2) -> fmod(c1,c2) 4302 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4303 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4304 4305 return SDValue(); 4306} 4307 4308SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4309 SDValue N0 = N->getOperand(0); 4310 SDValue N1 = N->getOperand(1); 4311 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4312 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4313 EVT VT = N->getValueType(0); 4314 4315 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4316 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4317 4318 if (N1CFP) { 4319 const APFloat& V = N1CFP->getValueAPF(); 4320 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4321 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4322 if (!V.isNegative()) { 4323 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4324 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4325 } else { 4326 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4327 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4328 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4329 } 4330 } 4331 4332 // copysign(fabs(x), y) -> copysign(x, y) 4333 // copysign(fneg(x), y) -> copysign(x, y) 4334 // copysign(copysign(x,z), y) -> copysign(x, y) 4335 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4336 N0.getOpcode() == ISD::FCOPYSIGN) 4337 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4338 N0.getOperand(0), N1); 4339 4340 // copysign(x, abs(y)) -> abs(x) 4341 if (N1.getOpcode() == ISD::FABS) 4342 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4343 4344 // copysign(x, copysign(y,z)) -> copysign(x, z) 4345 if (N1.getOpcode() == ISD::FCOPYSIGN) 4346 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4347 N0, N1.getOperand(1)); 4348 4349 // copysign(x, fp_extend(y)) -> copysign(x, y) 4350 // copysign(x, fp_round(y)) -> copysign(x, y) 4351 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4352 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4353 N0, N1.getOperand(0)); 4354 4355 return SDValue(); 4356} 4357 4358SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4359 SDValue N0 = N->getOperand(0); 4360 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4361 EVT VT = N->getValueType(0); 4362 EVT OpVT = N0.getValueType(); 4363 4364 // fold (sint_to_fp c1) -> c1fp 4365 if (N0C && OpVT != MVT::ppcf128) 4366 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4367 4368 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4369 // but UINT_TO_FP is legal on this target, try to convert. 4370 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4371 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4372 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4373 if (DAG.SignBitIsZero(N0)) 4374 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4375 } 4376 4377 return SDValue(); 4378} 4379 4380SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4381 SDValue N0 = N->getOperand(0); 4382 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4383 EVT VT = N->getValueType(0); 4384 EVT OpVT = N0.getValueType(); 4385 4386 // fold (uint_to_fp c1) -> c1fp 4387 if (N0C && OpVT != MVT::ppcf128) 4388 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4389 4390 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4391 // but SINT_TO_FP is legal on this target, try to convert. 4392 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4393 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4394 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4395 if (DAG.SignBitIsZero(N0)) 4396 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4397 } 4398 4399 return SDValue(); 4400} 4401 4402SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4403 SDValue N0 = N->getOperand(0); 4404 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4405 EVT VT = N->getValueType(0); 4406 4407 // fold (fp_to_sint c1fp) -> c1 4408 if (N0CFP) 4409 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4410 4411 return SDValue(); 4412} 4413 4414SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4415 SDValue N0 = N->getOperand(0); 4416 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4417 EVT VT = N->getValueType(0); 4418 4419 // fold (fp_to_uint c1fp) -> c1 4420 if (N0CFP && VT != MVT::ppcf128) 4421 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4422 4423 return SDValue(); 4424} 4425 4426SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4427 SDValue N0 = N->getOperand(0); 4428 SDValue N1 = N->getOperand(1); 4429 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4430 EVT VT = N->getValueType(0); 4431 4432 // fold (fp_round c1fp) -> c1fp 4433 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4434 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4435 4436 // fold (fp_round (fp_extend x)) -> x 4437 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4438 return N0.getOperand(0); 4439 4440 // fold (fp_round (fp_round x)) -> (fp_round x) 4441 if (N0.getOpcode() == ISD::FP_ROUND) { 4442 // This is a value preserving truncation if both round's are. 4443 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4444 N0.getNode()->getConstantOperandVal(1) == 1; 4445 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4446 DAG.getIntPtrConstant(IsTrunc)); 4447 } 4448 4449 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4450 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4451 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4452 N0.getOperand(0), N1); 4453 AddToWorkList(Tmp.getNode()); 4454 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4455 Tmp, N0.getOperand(1)); 4456 } 4457 4458 return SDValue(); 4459} 4460 4461SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4462 SDValue N0 = N->getOperand(0); 4463 EVT VT = N->getValueType(0); 4464 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4465 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4466 4467 // fold (fp_round_inreg c1fp) -> c1fp 4468 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4469 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4470 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4471 } 4472 4473 return SDValue(); 4474} 4475 4476SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4477 SDValue N0 = N->getOperand(0); 4478 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4479 EVT VT = N->getValueType(0); 4480 4481 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4482 if (N->hasOneUse() && 4483 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4484 return SDValue(); 4485 4486 // fold (fp_extend c1fp) -> c1fp 4487 if (N0CFP && VT != MVT::ppcf128) 4488 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4489 4490 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4491 // value of X. 4492 if (N0.getOpcode() == ISD::FP_ROUND 4493 && N0.getNode()->getConstantOperandVal(1) == 1) { 4494 SDValue In = N0.getOperand(0); 4495 if (In.getValueType() == VT) return In; 4496 if (VT.bitsLT(In.getValueType())) 4497 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4498 In, N0.getOperand(1)); 4499 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4500 } 4501 4502 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4503 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4504 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4505 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4506 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4507 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4508 LN0->getChain(), 4509 LN0->getBasePtr(), LN0->getSrcValue(), 4510 LN0->getSrcValueOffset(), 4511 N0.getValueType(), 4512 LN0->isVolatile(), LN0->isNonTemporal(), 4513 LN0->getAlignment()); 4514 CombineTo(N, ExtLoad); 4515 CombineTo(N0.getNode(), 4516 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4517 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4518 ExtLoad.getValue(1)); 4519 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4520 } 4521 4522 return SDValue(); 4523} 4524 4525SDValue DAGCombiner::visitFNEG(SDNode *N) { 4526 SDValue N0 = N->getOperand(0); 4527 EVT VT = N->getValueType(0); 4528 4529 if (isNegatibleForFree(N0, LegalOperations)) 4530 return GetNegatedExpression(N0, DAG, LegalOperations); 4531 4532 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4533 // constant pool values. 4534 if (N0.getOpcode() == ISD::BIT_CONVERT && 4535 !VT.isVector() && 4536 N0.getNode()->hasOneUse() && 4537 N0.getOperand(0).getValueType().isInteger()) { 4538 SDValue Int = N0.getOperand(0); 4539 EVT IntVT = Int.getValueType(); 4540 if (IntVT.isInteger() && !IntVT.isVector()) { 4541 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4542 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4543 AddToWorkList(Int.getNode()); 4544 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4545 VT, Int); 4546 } 4547 } 4548 4549 return SDValue(); 4550} 4551 4552SDValue DAGCombiner::visitFABS(SDNode *N) { 4553 SDValue N0 = N->getOperand(0); 4554 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4555 EVT VT = N->getValueType(0); 4556 4557 // fold (fabs c1) -> fabs(c1) 4558 if (N0CFP && VT != MVT::ppcf128) 4559 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4560 // fold (fabs (fabs x)) -> (fabs x) 4561 if (N0.getOpcode() == ISD::FABS) 4562 return N->getOperand(0); 4563 // fold (fabs (fneg x)) -> (fabs x) 4564 // fold (fabs (fcopysign x, y)) -> (fabs x) 4565 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4566 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4567 4568 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4569 // constant pool values. 4570 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4571 N0.getOperand(0).getValueType().isInteger() && 4572 !N0.getOperand(0).getValueType().isVector()) { 4573 SDValue Int = N0.getOperand(0); 4574 EVT IntVT = Int.getValueType(); 4575 if (IntVT.isInteger() && !IntVT.isVector()) { 4576 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4577 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4578 AddToWorkList(Int.getNode()); 4579 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4580 N->getValueType(0), Int); 4581 } 4582 } 4583 4584 return SDValue(); 4585} 4586 4587SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4588 SDValue Chain = N->getOperand(0); 4589 SDValue N1 = N->getOperand(1); 4590 SDValue N2 = N->getOperand(2); 4591 4592 // If N is a constant we could fold this into a fallthrough or unconditional 4593 // branch. However that doesn't happen very often in normal code, because 4594 // Instcombine/SimplifyCFG should have handled the available opportunities. 4595 // If we did this folding here, it would be necessary to update the 4596 // MachineBasicBlock CFG, which is awkward. 4597 4598 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4599 // on the target. 4600 if (N1.getOpcode() == ISD::SETCC && 4601 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4602 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4603 Chain, N1.getOperand(2), 4604 N1.getOperand(0), N1.getOperand(1), N2); 4605 } 4606 4607 SDNode *Trunc = 0; 4608 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 4609 // Look past truncate. 4610 Trunc = N1.getNode(); 4611 N1 = N1.getOperand(0); 4612 } 4613 4614 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4615 // Match this pattern so that we can generate simpler code: 4616 // 4617 // %a = ... 4618 // %b = and i32 %a, 2 4619 // %c = srl i32 %b, 1 4620 // brcond i32 %c ... 4621 // 4622 // into 4623 // 4624 // %a = ... 4625 // %b = and i32 %a, 2 4626 // %c = setcc eq %b, 0 4627 // brcond %c ... 4628 // 4629 // This applies only when the AND constant value has one bit set and the 4630 // SRL constant is equal to the log2 of the AND constant. The back-end is 4631 // smart enough to convert the result into a TEST/JMP sequence. 4632 SDValue Op0 = N1.getOperand(0); 4633 SDValue Op1 = N1.getOperand(1); 4634 4635 if (Op0.getOpcode() == ISD::AND && 4636 Op1.getOpcode() == ISD::Constant) { 4637 SDValue AndOp1 = Op0.getOperand(1); 4638 4639 if (AndOp1.getOpcode() == ISD::Constant) { 4640 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4641 4642 if (AndConst.isPowerOf2() && 4643 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4644 SDValue SetCC = 4645 DAG.getSetCC(N->getDebugLoc(), 4646 TLI.getSetCCResultType(Op0.getValueType()), 4647 Op0, DAG.getConstant(0, Op0.getValueType()), 4648 ISD::SETNE); 4649 4650 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4651 MVT::Other, Chain, SetCC, N2); 4652 // Don't add the new BRCond into the worklist or else SimplifySelectCC 4653 // will convert it back to (X & C1) >> C2. 4654 CombineTo(N, NewBRCond, false); 4655 // Truncate is dead. 4656 if (Trunc) { 4657 removeFromWorkList(Trunc); 4658 DAG.DeleteNode(Trunc); 4659 } 4660 // Replace the uses of SRL with SETCC 4661 WorkListRemover DeadNodes(*this); 4662 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 4663 removeFromWorkList(N1.getNode()); 4664 DAG.DeleteNode(N1.getNode()); 4665 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4666 } 4667 } 4668 } 4669 } 4670 4671 // Transform br(xor(x, y)) -> br(x != y) 4672 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 4673 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 4674 SDNode *TheXor = N1.getNode(); 4675 SDValue Op0 = TheXor->getOperand(0); 4676 SDValue Op1 = TheXor->getOperand(1); 4677 if (Op0.getOpcode() == Op1.getOpcode()) { 4678 // Avoid missing important xor optimizations. 4679 SDValue Tmp = visitXOR(TheXor); 4680 if (Tmp.getNode()) { 4681 DEBUG(dbgs() << "\nReplacing.8 "; 4682 TheXor->dump(&DAG); 4683 dbgs() << "\nWith: "; 4684 Tmp.getNode()->dump(&DAG); 4685 dbgs() << '\n'); 4686 WorkListRemover DeadNodes(*this); 4687 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 4688 removeFromWorkList(TheXor); 4689 DAG.DeleteNode(TheXor); 4690 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4691 MVT::Other, Chain, Tmp, N2); 4692 } 4693 } 4694 4695 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 4696 bool Equal = false; 4697 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 4698 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 4699 Op0.getOpcode() == ISD::XOR) { 4700 TheXor = Op0.getNode(); 4701 Equal = true; 4702 } 4703 4704 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; 4705 4706 EVT SetCCVT = NodeToReplace.getValueType(); 4707 if (LegalTypes) 4708 SetCCVT = TLI.getSetCCResultType(SetCCVT); 4709 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 4710 SetCCVT, 4711 Op0, Op1, 4712 Equal ? ISD::SETEQ : ISD::SETNE); 4713 // Replace the uses of XOR with SETCC 4714 WorkListRemover DeadNodes(*this); 4715 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes); 4716 removeFromWorkList(NodeToReplace.getNode()); 4717 DAG.DeleteNode(NodeToReplace.getNode()); 4718 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4719 MVT::Other, Chain, SetCC, N2); 4720 } 4721 } 4722 4723 return SDValue(); 4724} 4725 4726// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4727// 4728SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4729 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4730 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4731 4732 // If N is a constant we could fold this into a fallthrough or unconditional 4733 // branch. However that doesn't happen very often in normal code, because 4734 // Instcombine/SimplifyCFG should have handled the available opportunities. 4735 // If we did this folding here, it would be necessary to update the 4736 // MachineBasicBlock CFG, which is awkward. 4737 4738 // Use SimplifySetCC to simplify SETCC's. 4739 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4740 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4741 false); 4742 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4743 4744 // fold to a simpler setcc 4745 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4746 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4747 N->getOperand(0), Simp.getOperand(2), 4748 Simp.getOperand(0), Simp.getOperand(1), 4749 N->getOperand(4)); 4750 4751 return SDValue(); 4752} 4753 4754/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4755/// pre-indexed load / store when the base pointer is an add or subtract 4756/// and it has other uses besides the load / store. After the 4757/// transformation, the new indexed load / store has effectively folded 4758/// the add / subtract in and all of its other uses are redirected to the 4759/// new load / store. 4760bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4761 if (!LegalOperations) 4762 return false; 4763 4764 bool isLoad = true; 4765 SDValue Ptr; 4766 EVT VT; 4767 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4768 if (LD->isIndexed()) 4769 return false; 4770 VT = LD->getMemoryVT(); 4771 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4772 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4773 return false; 4774 Ptr = LD->getBasePtr(); 4775 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4776 if (ST->isIndexed()) 4777 return false; 4778 VT = ST->getMemoryVT(); 4779 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4780 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4781 return false; 4782 Ptr = ST->getBasePtr(); 4783 isLoad = false; 4784 } else { 4785 return false; 4786 } 4787 4788 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4789 // out. There is no reason to make this a preinc/predec. 4790 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4791 Ptr.getNode()->hasOneUse()) 4792 return false; 4793 4794 // Ask the target to do addressing mode selection. 4795 SDValue BasePtr; 4796 SDValue Offset; 4797 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4798 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4799 return false; 4800 // Don't create a indexed load / store with zero offset. 4801 if (isa<ConstantSDNode>(Offset) && 4802 cast<ConstantSDNode>(Offset)->isNullValue()) 4803 return false; 4804 4805 // Try turning it into a pre-indexed load / store except when: 4806 // 1) The new base ptr is a frame index. 4807 // 2) If N is a store and the new base ptr is either the same as or is a 4808 // predecessor of the value being stored. 4809 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4810 // that would create a cycle. 4811 // 4) All uses are load / store ops that use it as old base ptr. 4812 4813 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4814 // (plus the implicit offset) to a register to preinc anyway. 4815 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4816 return false; 4817 4818 // Check #2. 4819 if (!isLoad) { 4820 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4821 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4822 return false; 4823 } 4824 4825 // Now check for #3 and #4. 4826 bool RealUse = false; 4827 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4828 E = Ptr.getNode()->use_end(); I != E; ++I) { 4829 SDNode *Use = *I; 4830 if (Use == N) 4831 continue; 4832 if (Use->isPredecessorOf(N)) 4833 return false; 4834 4835 if (!((Use->getOpcode() == ISD::LOAD && 4836 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4837 (Use->getOpcode() == ISD::STORE && 4838 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4839 RealUse = true; 4840 } 4841 4842 if (!RealUse) 4843 return false; 4844 4845 SDValue Result; 4846 if (isLoad) 4847 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4848 BasePtr, Offset, AM); 4849 else 4850 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4851 BasePtr, Offset, AM); 4852 ++PreIndexedNodes; 4853 ++NodesCombined; 4854 DEBUG(dbgs() << "\nReplacing.4 "; 4855 N->dump(&DAG); 4856 dbgs() << "\nWith: "; 4857 Result.getNode()->dump(&DAG); 4858 dbgs() << '\n'); 4859 WorkListRemover DeadNodes(*this); 4860 if (isLoad) { 4861 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4862 &DeadNodes); 4863 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4864 &DeadNodes); 4865 } else { 4866 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4867 &DeadNodes); 4868 } 4869 4870 // Finally, since the node is now dead, remove it from the graph. 4871 DAG.DeleteNode(N); 4872 4873 // Replace the uses of Ptr with uses of the updated base value. 4874 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4875 &DeadNodes); 4876 removeFromWorkList(Ptr.getNode()); 4877 DAG.DeleteNode(Ptr.getNode()); 4878 4879 return true; 4880} 4881 4882/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4883/// add / sub of the base pointer node into a post-indexed load / store. 4884/// The transformation folded the add / subtract into the new indexed 4885/// load / store effectively and all of its uses are redirected to the 4886/// new load / store. 4887bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4888 if (!LegalOperations) 4889 return false; 4890 4891 bool isLoad = true; 4892 SDValue Ptr; 4893 EVT VT; 4894 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4895 if (LD->isIndexed()) 4896 return false; 4897 VT = LD->getMemoryVT(); 4898 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4899 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4900 return false; 4901 Ptr = LD->getBasePtr(); 4902 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4903 if (ST->isIndexed()) 4904 return false; 4905 VT = ST->getMemoryVT(); 4906 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4907 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4908 return false; 4909 Ptr = ST->getBasePtr(); 4910 isLoad = false; 4911 } else { 4912 return false; 4913 } 4914 4915 if (Ptr.getNode()->hasOneUse()) 4916 return false; 4917 4918 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4919 E = Ptr.getNode()->use_end(); I != E; ++I) { 4920 SDNode *Op = *I; 4921 if (Op == N || 4922 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4923 continue; 4924 4925 SDValue BasePtr; 4926 SDValue Offset; 4927 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4928 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4929 if (Ptr == Offset && Op->getOpcode() == ISD::ADD) 4930 std::swap(BasePtr, Offset); 4931 if (Ptr != BasePtr) 4932 continue; 4933 // Don't create a indexed load / store with zero offset. 4934 if (isa<ConstantSDNode>(Offset) && 4935 cast<ConstantSDNode>(Offset)->isNullValue()) 4936 continue; 4937 4938 // Try turning it into a post-indexed load / store except when 4939 // 1) All uses are load / store ops that use it as base ptr. 4940 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4941 // nor a successor of N. Otherwise, if Op is folded that would 4942 // create a cycle. 4943 4944 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4945 continue; 4946 4947 // Check for #1. 4948 bool TryNext = false; 4949 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4950 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4951 SDNode *Use = *II; 4952 if (Use == Ptr.getNode()) 4953 continue; 4954 4955 // If all the uses are load / store addresses, then don't do the 4956 // transformation. 4957 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4958 bool RealUse = false; 4959 for (SDNode::use_iterator III = Use->use_begin(), 4960 EEE = Use->use_end(); III != EEE; ++III) { 4961 SDNode *UseUse = *III; 4962 if (!((UseUse->getOpcode() == ISD::LOAD && 4963 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4964 (UseUse->getOpcode() == ISD::STORE && 4965 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4966 RealUse = true; 4967 } 4968 4969 if (!RealUse) { 4970 TryNext = true; 4971 break; 4972 } 4973 } 4974 } 4975 4976 if (TryNext) 4977 continue; 4978 4979 // Check for #2 4980 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4981 SDValue Result = isLoad 4982 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4983 BasePtr, Offset, AM) 4984 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4985 BasePtr, Offset, AM); 4986 ++PostIndexedNodes; 4987 ++NodesCombined; 4988 DEBUG(dbgs() << "\nReplacing.5 "; 4989 N->dump(&DAG); 4990 dbgs() << "\nWith: "; 4991 Result.getNode()->dump(&DAG); 4992 dbgs() << '\n'); 4993 WorkListRemover DeadNodes(*this); 4994 if (isLoad) { 4995 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4996 &DeadNodes); 4997 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4998 &DeadNodes); 4999 } else { 5000 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5001 &DeadNodes); 5002 } 5003 5004 // Finally, since the node is now dead, remove it from the graph. 5005 DAG.DeleteNode(N); 5006 5007 // Replace the uses of Use with uses of the updated base value. 5008 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5009 Result.getValue(isLoad ? 1 : 0), 5010 &DeadNodes); 5011 removeFromWorkList(Op); 5012 DAG.DeleteNode(Op); 5013 return true; 5014 } 5015 } 5016 } 5017 5018 return false; 5019} 5020 5021SDValue DAGCombiner::visitLOAD(SDNode *N) { 5022 LoadSDNode *LD = cast<LoadSDNode>(N); 5023 SDValue Chain = LD->getChain(); 5024 SDValue Ptr = LD->getBasePtr(); 5025 5026 // If load is not volatile and there are no uses of the loaded value (and 5027 // the updated indexed value in case of indexed loads), change uses of the 5028 // chain value into uses of the chain input (i.e. delete the dead load). 5029 if (!LD->isVolatile()) { 5030 if (N->getValueType(1) == MVT::Other) { 5031 // Unindexed loads. 5032 if (N->hasNUsesOfValue(0, 0)) { 5033 // It's not safe to use the two value CombineTo variant here. e.g. 5034 // v1, chain2 = load chain1, loc 5035 // v2, chain3 = load chain2, loc 5036 // v3 = add v2, c 5037 // Now we replace use of chain2 with chain1. This makes the second load 5038 // isomorphic to the one we are deleting, and thus makes this load live. 5039 DEBUG(dbgs() << "\nReplacing.6 "; 5040 N->dump(&DAG); 5041 dbgs() << "\nWith chain: "; 5042 Chain.getNode()->dump(&DAG); 5043 dbgs() << "\n"); 5044 WorkListRemover DeadNodes(*this); 5045 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5046 5047 if (N->use_empty()) { 5048 removeFromWorkList(N); 5049 DAG.DeleteNode(N); 5050 } 5051 5052 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5053 } 5054 } else { 5055 // Indexed loads. 5056 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5057 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5058 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5059 DEBUG(dbgs() << "\nReplacing.7 "; 5060 N->dump(&DAG); 5061 dbgs() << "\nWith: "; 5062 Undef.getNode()->dump(&DAG); 5063 dbgs() << " and 2 other values\n"); 5064 WorkListRemover DeadNodes(*this); 5065 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5066 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5067 DAG.getUNDEF(N->getValueType(1)), 5068 &DeadNodes); 5069 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5070 removeFromWorkList(N); 5071 DAG.DeleteNode(N); 5072 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5073 } 5074 } 5075 } 5076 5077 // If this load is directly stored, replace the load value with the stored 5078 // value. 5079 // TODO: Handle store large -> read small portion. 5080 // TODO: Handle TRUNCSTORE/LOADEXT 5081 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5082 !LD->isVolatile()) { 5083 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5084 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5085 if (PrevST->getBasePtr() == Ptr && 5086 PrevST->getValue().getValueType() == N->getValueType(0)) 5087 return CombineTo(N, Chain.getOperand(1), Chain); 5088 } 5089 } 5090 5091 // Try to infer better alignment information than the load already has. 5092 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5093 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5094 if (Align > LD->getAlignment()) 5095 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5096 LD->getValueType(0), 5097 Chain, Ptr, LD->getSrcValue(), 5098 LD->getSrcValueOffset(), LD->getMemoryVT(), 5099 LD->isVolatile(), LD->isNonTemporal(), Align); 5100 } 5101 } 5102 5103 if (CombinerAA) { 5104 // Walk up chain skipping non-aliasing memory nodes. 5105 SDValue BetterChain = FindBetterChain(N, Chain); 5106 5107 // If there is a better chain. 5108 if (Chain != BetterChain) { 5109 SDValue ReplLoad; 5110 5111 // Replace the chain to void dependency. 5112 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5113 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5114 BetterChain, Ptr, 5115 LD->getSrcValue(), LD->getSrcValueOffset(), 5116 LD->isVolatile(), LD->isNonTemporal(), 5117 LD->getAlignment()); 5118 } else { 5119 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5120 LD->getValueType(0), 5121 BetterChain, Ptr, LD->getSrcValue(), 5122 LD->getSrcValueOffset(), 5123 LD->getMemoryVT(), 5124 LD->isVolatile(), 5125 LD->isNonTemporal(), 5126 LD->getAlignment()); 5127 } 5128 5129 // Create token factor to keep old chain connected. 5130 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5131 MVT::Other, Chain, ReplLoad.getValue(1)); 5132 5133 // Make sure the new and old chains are cleaned up. 5134 AddToWorkList(Token.getNode()); 5135 5136 // Replace uses with load result and token factor. Don't add users 5137 // to work list. 5138 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5139 } 5140 } 5141 5142 // Try transforming N to an indexed load. 5143 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5144 return SDValue(N, 0); 5145 5146 return SDValue(); 5147} 5148 5149 5150/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5151/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5152/// of the loaded bits, try narrowing the load and store if it would end up 5153/// being a win for performance or code size. 5154SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5155 StoreSDNode *ST = cast<StoreSDNode>(N); 5156 if (ST->isVolatile()) 5157 return SDValue(); 5158 5159 SDValue Chain = ST->getChain(); 5160 SDValue Value = ST->getValue(); 5161 SDValue Ptr = ST->getBasePtr(); 5162 EVT VT = Value.getValueType(); 5163 5164 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5165 return SDValue(); 5166 5167 unsigned Opc = Value.getOpcode(); 5168 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5169 Value.getOperand(1).getOpcode() != ISD::Constant) 5170 return SDValue(); 5171 5172 SDValue N0 = Value.getOperand(0); 5173 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5174 LoadSDNode *LD = cast<LoadSDNode>(N0); 5175 if (LD->getBasePtr() != Ptr) 5176 return SDValue(); 5177 5178 // Find the type to narrow it the load / op / store to. 5179 SDValue N1 = Value.getOperand(1); 5180 unsigned BitWidth = N1.getValueSizeInBits(); 5181 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5182 if (Opc == ISD::AND) 5183 Imm ^= APInt::getAllOnesValue(BitWidth); 5184 if (Imm == 0 || Imm.isAllOnesValue()) 5185 return SDValue(); 5186 unsigned ShAmt = Imm.countTrailingZeros(); 5187 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5188 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5189 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5190 while (NewBW < BitWidth && 5191 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5192 TLI.isNarrowingProfitable(VT, NewVT))) { 5193 NewBW = NextPowerOf2(NewBW); 5194 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5195 } 5196 if (NewBW >= BitWidth) 5197 return SDValue(); 5198 5199 // If the lsb changed does not start at the type bitwidth boundary, 5200 // start at the previous one. 5201 if (ShAmt % NewBW) 5202 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5203 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5204 if ((Imm & Mask) == Imm) { 5205 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5206 if (Opc == ISD::AND) 5207 NewImm ^= APInt::getAllOnesValue(NewBW); 5208 uint64_t PtrOff = ShAmt / 8; 5209 // For big endian targets, we need to adjust the offset to the pointer to 5210 // load the correct bytes. 5211 if (TLI.isBigEndian()) 5212 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5213 5214 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5215 if (NewAlign < 5216 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext()))) 5217 return SDValue(); 5218 5219 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5220 Ptr.getValueType(), Ptr, 5221 DAG.getConstant(PtrOff, Ptr.getValueType())); 5222 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5223 LD->getChain(), NewPtr, 5224 LD->getSrcValue(), LD->getSrcValueOffset(), 5225 LD->isVolatile(), LD->isNonTemporal(), 5226 NewAlign); 5227 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5228 DAG.getConstant(NewImm, NewVT)); 5229 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5230 NewVal, NewPtr, 5231 ST->getSrcValue(), ST->getSrcValueOffset(), 5232 false, false, NewAlign); 5233 5234 AddToWorkList(NewPtr.getNode()); 5235 AddToWorkList(NewLD.getNode()); 5236 AddToWorkList(NewVal.getNode()); 5237 WorkListRemover DeadNodes(*this); 5238 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5239 &DeadNodes); 5240 ++OpsNarrowed; 5241 return NewST; 5242 } 5243 } 5244 5245 return SDValue(); 5246} 5247 5248SDValue DAGCombiner::visitSTORE(SDNode *N) { 5249 StoreSDNode *ST = cast<StoreSDNode>(N); 5250 SDValue Chain = ST->getChain(); 5251 SDValue Value = ST->getValue(); 5252 SDValue Ptr = ST->getBasePtr(); 5253 5254 // If this is a store of a bit convert, store the input value if the 5255 // resultant store does not need a higher alignment than the original. 5256 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5257 ST->isUnindexed()) { 5258 unsigned OrigAlign = ST->getAlignment(); 5259 EVT SVT = Value.getOperand(0).getValueType(); 5260 unsigned Align = TLI.getTargetData()-> 5261 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5262 if (Align <= OrigAlign && 5263 ((!LegalOperations && !ST->isVolatile()) || 5264 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5265 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5266 Ptr, ST->getSrcValue(), 5267 ST->getSrcValueOffset(), ST->isVolatile(), 5268 ST->isNonTemporal(), OrigAlign); 5269 } 5270 5271 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5272 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5273 // NOTE: If the original store is volatile, this transform must not increase 5274 // the number of stores. For example, on x86-32 an f64 can be stored in one 5275 // processor operation but an i64 (which is not legal) requires two. So the 5276 // transform should not be done in this case. 5277 if (Value.getOpcode() != ISD::TargetConstantFP) { 5278 SDValue Tmp; 5279 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5280 default: llvm_unreachable("Unknown FP type"); 5281 case MVT::f80: // We don't do this for these yet. 5282 case MVT::f128: 5283 case MVT::ppcf128: 5284 break; 5285 case MVT::f32: 5286 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5287 !ST->isVolatile()) || 5288 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5289 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5290 bitcastToAPInt().getZExtValue(), MVT::i32); 5291 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5292 Ptr, ST->getSrcValue(), 5293 ST->getSrcValueOffset(), ST->isVolatile(), 5294 ST->isNonTemporal(), ST->getAlignment()); 5295 } 5296 break; 5297 case MVT::f64: 5298 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5299 !ST->isVolatile()) || 5300 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5301 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5302 getZExtValue(), MVT::i64); 5303 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5304 Ptr, ST->getSrcValue(), 5305 ST->getSrcValueOffset(), ST->isVolatile(), 5306 ST->isNonTemporal(), ST->getAlignment()); 5307 } else if (!ST->isVolatile() && 5308 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5309 // Many FP stores are not made apparent until after legalize, e.g. for 5310 // argument passing. Since this is so common, custom legalize the 5311 // 64-bit integer store into two 32-bit stores. 5312 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5313 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5314 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5315 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5316 5317 int SVOffset = ST->getSrcValueOffset(); 5318 unsigned Alignment = ST->getAlignment(); 5319 bool isVolatile = ST->isVolatile(); 5320 bool isNonTemporal = ST->isNonTemporal(); 5321 5322 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5323 Ptr, ST->getSrcValue(), 5324 ST->getSrcValueOffset(), 5325 isVolatile, isNonTemporal, 5326 ST->getAlignment()); 5327 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5328 DAG.getConstant(4, Ptr.getValueType())); 5329 SVOffset += 4; 5330 Alignment = MinAlign(Alignment, 4U); 5331 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5332 Ptr, ST->getSrcValue(), 5333 SVOffset, isVolatile, isNonTemporal, 5334 Alignment); 5335 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5336 St0, St1); 5337 } 5338 5339 break; 5340 } 5341 } 5342 } 5343 5344 // Try to infer better alignment information than the store already has. 5345 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5346 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5347 if (Align > ST->getAlignment()) 5348 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5349 Ptr, ST->getSrcValue(), 5350 ST->getSrcValueOffset(), ST->getMemoryVT(), 5351 ST->isVolatile(), ST->isNonTemporal(), Align); 5352 } 5353 } 5354 5355 if (CombinerAA) { 5356 // Walk up chain skipping non-aliasing memory nodes. 5357 SDValue BetterChain = FindBetterChain(N, Chain); 5358 5359 // If there is a better chain. 5360 if (Chain != BetterChain) { 5361 SDValue ReplStore; 5362 5363 // Replace the chain to avoid dependency. 5364 if (ST->isTruncatingStore()) { 5365 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5366 ST->getSrcValue(),ST->getSrcValueOffset(), 5367 ST->getMemoryVT(), ST->isVolatile(), 5368 ST->isNonTemporal(), ST->getAlignment()); 5369 } else { 5370 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5371 ST->getSrcValue(), ST->getSrcValueOffset(), 5372 ST->isVolatile(), ST->isNonTemporal(), 5373 ST->getAlignment()); 5374 } 5375 5376 // Create token to keep both nodes around. 5377 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5378 MVT::Other, Chain, ReplStore); 5379 5380 // Make sure the new and old chains are cleaned up. 5381 AddToWorkList(Token.getNode()); 5382 5383 // Don't add users to work list. 5384 return CombineTo(N, Token, false); 5385 } 5386 } 5387 5388 // Try transforming N to an indexed store. 5389 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5390 return SDValue(N, 0); 5391 5392 // FIXME: is there such a thing as a truncating indexed store? 5393 if (ST->isTruncatingStore() && ST->isUnindexed() && 5394 Value.getValueType().isInteger()) { 5395 // See if we can simplify the input to this truncstore with knowledge that 5396 // only the low bits are being used. For example: 5397 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5398 SDValue Shorter = 5399 GetDemandedBits(Value, 5400 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5401 ST->getMemoryVT().getSizeInBits())); 5402 AddToWorkList(Value.getNode()); 5403 if (Shorter.getNode()) 5404 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5405 Ptr, ST->getSrcValue(), 5406 ST->getSrcValueOffset(), ST->getMemoryVT(), 5407 ST->isVolatile(), ST->isNonTemporal(), 5408 ST->getAlignment()); 5409 5410 // Otherwise, see if we can simplify the operation with 5411 // SimplifyDemandedBits, which only works if the value has a single use. 5412 if (SimplifyDemandedBits(Value, 5413 APInt::getLowBitsSet( 5414 Value.getValueType().getScalarType().getSizeInBits(), 5415 ST->getMemoryVT().getScalarType().getSizeInBits()))) 5416 return SDValue(N, 0); 5417 } 5418 5419 // If this is a load followed by a store to the same location, then the store 5420 // is dead/noop. 5421 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5422 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5423 ST->isUnindexed() && !ST->isVolatile() && 5424 // There can't be any side effects between the load and store, such as 5425 // a call or store. 5426 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5427 // The store is dead, remove it. 5428 return Chain; 5429 } 5430 } 5431 5432 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5433 // truncating store. We can do this even if this is already a truncstore. 5434 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5435 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5436 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5437 ST->getMemoryVT())) { 5438 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5439 Ptr, ST->getSrcValue(), 5440 ST->getSrcValueOffset(), ST->getMemoryVT(), 5441 ST->isVolatile(), ST->isNonTemporal(), 5442 ST->getAlignment()); 5443 } 5444 5445 return ReduceLoadOpStoreWidth(N); 5446} 5447 5448SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5449 SDValue InVec = N->getOperand(0); 5450 SDValue InVal = N->getOperand(1); 5451 SDValue EltNo = N->getOperand(2); 5452 5453 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5454 // vector with the inserted element. 5455 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5456 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5457 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5458 InVec.getNode()->op_end()); 5459 if (Elt < Ops.size()) 5460 Ops[Elt] = InVal; 5461 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5462 InVec.getValueType(), &Ops[0], Ops.size()); 5463 } 5464 // If the invec is an UNDEF and if EltNo is a constant, create a new 5465 // BUILD_VECTOR with undef elements and the inserted element. 5466 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5467 isa<ConstantSDNode>(EltNo)) { 5468 EVT VT = InVec.getValueType(); 5469 EVT EltVT = VT.getVectorElementType(); 5470 unsigned NElts = VT.getVectorNumElements(); 5471 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 5472 5473 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5474 if (Elt < Ops.size()) 5475 Ops[Elt] = InVal; 5476 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5477 InVec.getValueType(), &Ops[0], Ops.size()); 5478 } 5479 return SDValue(); 5480} 5481 5482SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5483 // (vextract (scalar_to_vector val, 0) -> val 5484 SDValue InVec = N->getOperand(0); 5485 5486 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5487 // Check if the result type doesn't match the inserted element type. A 5488 // SCALAR_TO_VECTOR may truncate the inserted element and the 5489 // EXTRACT_VECTOR_ELT may widen the extracted vector. 5490 EVT EltVT = InVec.getValueType().getVectorElementType(); 5491 SDValue InOp = InVec.getOperand(0); 5492 EVT NVT = N->getValueType(0); 5493 if (InOp.getValueType() != NVT) { 5494 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 5495 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 5496 } 5497 return InOp; 5498 } 5499 5500 // Perform only after legalization to ensure build_vector / vector_shuffle 5501 // optimizations have already been done. 5502 if (!LegalOperations) return SDValue(); 5503 5504 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5505 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5506 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5507 SDValue EltNo = N->getOperand(1); 5508 5509 if (isa<ConstantSDNode>(EltNo)) { 5510 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5511 bool NewLoad = false; 5512 bool BCNumEltsChanged = false; 5513 EVT VT = InVec.getValueType(); 5514 EVT ExtVT = VT.getVectorElementType(); 5515 EVT LVT = ExtVT; 5516 5517 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5518 EVT BCVT = InVec.getOperand(0).getValueType(); 5519 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 5520 return SDValue(); 5521 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5522 BCNumEltsChanged = true; 5523 InVec = InVec.getOperand(0); 5524 ExtVT = BCVT.getVectorElementType(); 5525 NewLoad = true; 5526 } 5527 5528 LoadSDNode *LN0 = NULL; 5529 const ShuffleVectorSDNode *SVN = NULL; 5530 if (ISD::isNormalLoad(InVec.getNode())) { 5531 LN0 = cast<LoadSDNode>(InVec); 5532 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5533 InVec.getOperand(0).getValueType() == ExtVT && 5534 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5535 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5536 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5537 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5538 // => 5539 // (load $addr+1*size) 5540 5541 // If the bit convert changed the number of elements, it is unsafe 5542 // to examine the mask. 5543 if (BCNumEltsChanged) 5544 return SDValue(); 5545 5546 // Select the input vector, guarding against out of range extract vector. 5547 unsigned NumElems = VT.getVectorNumElements(); 5548 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5549 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5550 5551 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5552 InVec = InVec.getOperand(0); 5553 if (ISD::isNormalLoad(InVec.getNode())) { 5554 LN0 = cast<LoadSDNode>(InVec); 5555 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 5556 } 5557 } 5558 5559 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5560 return SDValue(); 5561 5562 unsigned Align = LN0->getAlignment(); 5563 if (NewLoad) { 5564 // Check the resultant load doesn't need a higher alignment than the 5565 // original load. 5566 unsigned NewAlign = 5567 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 5568 5569 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5570 return SDValue(); 5571 5572 Align = NewAlign; 5573 } 5574 5575 SDValue NewPtr = LN0->getBasePtr(); 5576 if (Elt) { 5577 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5578 EVT PtrType = NewPtr.getValueType(); 5579 if (TLI.isBigEndian()) 5580 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5581 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5582 DAG.getConstant(PtrOff, PtrType)); 5583 } 5584 5585 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5586 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5587 LN0->isVolatile(), LN0->isNonTemporal(), Align); 5588 } 5589 5590 return SDValue(); 5591} 5592 5593SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5594 unsigned NumInScalars = N->getNumOperands(); 5595 EVT VT = N->getValueType(0); 5596 5597 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5598 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5599 // at most two distinct vectors, turn this into a shuffle node. 5600 SDValue VecIn1, VecIn2; 5601 for (unsigned i = 0; i != NumInScalars; ++i) { 5602 // Ignore undef inputs. 5603 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5604 5605 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5606 // constant index, bail out. 5607 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5608 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5609 VecIn1 = VecIn2 = SDValue(0, 0); 5610 break; 5611 } 5612 5613 // If the input vector type disagrees with the result of the build_vector, 5614 // we can't make a shuffle. 5615 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5616 if (ExtractedFromVec.getValueType() != VT) { 5617 VecIn1 = VecIn2 = SDValue(0, 0); 5618 break; 5619 } 5620 5621 // Otherwise, remember this. We allow up to two distinct input vectors. 5622 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5623 continue; 5624 5625 if (VecIn1.getNode() == 0) { 5626 VecIn1 = ExtractedFromVec; 5627 } else if (VecIn2.getNode() == 0) { 5628 VecIn2 = ExtractedFromVec; 5629 } else { 5630 // Too many inputs. 5631 VecIn1 = VecIn2 = SDValue(0, 0); 5632 break; 5633 } 5634 } 5635 5636 // If everything is good, we can make a shuffle operation. 5637 if (VecIn1.getNode()) { 5638 SmallVector<int, 8> Mask; 5639 for (unsigned i = 0; i != NumInScalars; ++i) { 5640 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5641 Mask.push_back(-1); 5642 continue; 5643 } 5644 5645 // If extracting from the first vector, just use the index directly. 5646 SDValue Extract = N->getOperand(i); 5647 SDValue ExtVal = Extract.getOperand(1); 5648 if (Extract.getOperand(0) == VecIn1) { 5649 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5650 if (ExtIndex > VT.getVectorNumElements()) 5651 return SDValue(); 5652 5653 Mask.push_back(ExtIndex); 5654 continue; 5655 } 5656 5657 // Otherwise, use InIdx + VecSize 5658 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5659 Mask.push_back(Idx+NumInScalars); 5660 } 5661 5662 // Add count and size info. 5663 if (!TLI.isTypeLegal(VT) && LegalTypes) 5664 return SDValue(); 5665 5666 // Return the new VECTOR_SHUFFLE node. 5667 SDValue Ops[2]; 5668 Ops[0] = VecIn1; 5669 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5670 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5671 } 5672 5673 return SDValue(); 5674} 5675 5676SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5677 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5678 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5679 // inputs come from at most two distinct vectors, turn this into a shuffle 5680 // node. 5681 5682 // If we only have one input vector, we don't need to do any concatenation. 5683 if (N->getNumOperands() == 1) 5684 return N->getOperand(0); 5685 5686 return SDValue(); 5687} 5688 5689SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5690 return SDValue(); 5691 5692 EVT VT = N->getValueType(0); 5693 unsigned NumElts = VT.getVectorNumElements(); 5694 5695 SDValue N0 = N->getOperand(0); 5696 5697 assert(N0.getValueType().getVectorNumElements() == NumElts && 5698 "Vector shuffle must be normalized in DAG"); 5699 5700 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5701 5702 // If it is a splat, check if the argument vector is a build_vector with 5703 // all scalar elements the same. 5704 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5705 SDNode *V = N0.getNode(); 5706 5707 5708 // If this is a bit convert that changes the element type of the vector but 5709 // not the number of vector elements, look through it. Be careful not to 5710 // look though conversions that change things like v4f32 to v2f64. 5711 if (V->getOpcode() == ISD::BIT_CONVERT) { 5712 SDValue ConvInput = V->getOperand(0); 5713 if (ConvInput.getValueType().isVector() && 5714 ConvInput.getValueType().getVectorNumElements() == NumElts) 5715 V = ConvInput.getNode(); 5716 } 5717 5718 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5719 unsigned NumElems = V->getNumOperands(); 5720 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5721 if (NumElems > BaseIdx) { 5722 SDValue Base; 5723 bool AllSame = true; 5724 for (unsigned i = 0; i != NumElems; ++i) { 5725 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5726 Base = V->getOperand(i); 5727 break; 5728 } 5729 } 5730 // Splat of <u, u, u, u>, return <u, u, u, u> 5731 if (!Base.getNode()) 5732 return N0; 5733 for (unsigned i = 0; i != NumElems; ++i) { 5734 if (V->getOperand(i) != Base) { 5735 AllSame = false; 5736 break; 5737 } 5738 } 5739 // Splat of <x, x, x, x>, return <x, x, x, x> 5740 if (AllSame) 5741 return N0; 5742 } 5743 } 5744 } 5745 return SDValue(); 5746} 5747 5748/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5749/// an AND to a vector_shuffle with the destination vector and a zero vector. 5750/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5751/// vector_shuffle V, Zero, <0, 4, 2, 4> 5752SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5753 EVT VT = N->getValueType(0); 5754 DebugLoc dl = N->getDebugLoc(); 5755 SDValue LHS = N->getOperand(0); 5756 SDValue RHS = N->getOperand(1); 5757 if (N->getOpcode() == ISD::AND) { 5758 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5759 RHS = RHS.getOperand(0); 5760 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5761 SmallVector<int, 8> Indices; 5762 unsigned NumElts = RHS.getNumOperands(); 5763 for (unsigned i = 0; i != NumElts; ++i) { 5764 SDValue Elt = RHS.getOperand(i); 5765 if (!isa<ConstantSDNode>(Elt)) 5766 return SDValue(); 5767 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5768 Indices.push_back(i); 5769 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5770 Indices.push_back(NumElts); 5771 else 5772 return SDValue(); 5773 } 5774 5775 // Let's see if the target supports this vector_shuffle. 5776 EVT RVT = RHS.getValueType(); 5777 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5778 return SDValue(); 5779 5780 // Return the new VECTOR_SHUFFLE node. 5781 EVT EltVT = RVT.getVectorElementType(); 5782 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5783 DAG.getConstant(0, EltVT)); 5784 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5785 RVT, &ZeroOps[0], ZeroOps.size()); 5786 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5787 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5788 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5789 } 5790 } 5791 5792 return SDValue(); 5793} 5794 5795/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5796SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5797 // After legalize, the target may be depending on adds and other 5798 // binary ops to provide legal ways to construct constants or other 5799 // things. Simplifying them may result in a loss of legality. 5800 if (LegalOperations) return SDValue(); 5801 5802 EVT VT = N->getValueType(0); 5803 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5804 5805 EVT EltType = VT.getVectorElementType(); 5806 SDValue LHS = N->getOperand(0); 5807 SDValue RHS = N->getOperand(1); 5808 SDValue Shuffle = XformToShuffleWithZero(N); 5809 if (Shuffle.getNode()) return Shuffle; 5810 5811 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5812 // this operation. 5813 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5814 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5815 SmallVector<SDValue, 8> Ops; 5816 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5817 SDValue LHSOp = LHS.getOperand(i); 5818 SDValue RHSOp = RHS.getOperand(i); 5819 // If these two elements can't be folded, bail out. 5820 if ((LHSOp.getOpcode() != ISD::UNDEF && 5821 LHSOp.getOpcode() != ISD::Constant && 5822 LHSOp.getOpcode() != ISD::ConstantFP) || 5823 (RHSOp.getOpcode() != ISD::UNDEF && 5824 RHSOp.getOpcode() != ISD::Constant && 5825 RHSOp.getOpcode() != ISD::ConstantFP)) 5826 break; 5827 5828 // Can't fold divide by zero. 5829 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5830 N->getOpcode() == ISD::FDIV) { 5831 if ((RHSOp.getOpcode() == ISD::Constant && 5832 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5833 (RHSOp.getOpcode() == ISD::ConstantFP && 5834 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5835 break; 5836 } 5837 5838 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5839 EltType, LHSOp, RHSOp)); 5840 AddToWorkList(Ops.back().getNode()); 5841 assert((Ops.back().getOpcode() == ISD::UNDEF || 5842 Ops.back().getOpcode() == ISD::Constant || 5843 Ops.back().getOpcode() == ISD::ConstantFP) && 5844 "Scalar binop didn't fold!"); 5845 } 5846 5847 if (Ops.size() == LHS.getNumOperands()) { 5848 EVT VT = LHS.getValueType(); 5849 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5850 &Ops[0], Ops.size()); 5851 } 5852 } 5853 5854 return SDValue(); 5855} 5856 5857SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5858 SDValue N1, SDValue N2){ 5859 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5860 5861 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5862 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5863 5864 // If we got a simplified select_cc node back from SimplifySelectCC, then 5865 // break it down into a new SETCC node, and a new SELECT node, and then return 5866 // the SELECT node, since we were called with a SELECT node. 5867 if (SCC.getNode()) { 5868 // Check to see if we got a select_cc back (to turn into setcc/select). 5869 // Otherwise, just return whatever node we got back, like fabs. 5870 if (SCC.getOpcode() == ISD::SELECT_CC) { 5871 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5872 N0.getValueType(), 5873 SCC.getOperand(0), SCC.getOperand(1), 5874 SCC.getOperand(4)); 5875 AddToWorkList(SETCC.getNode()); 5876 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5877 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5878 } 5879 5880 return SCC; 5881 } 5882 return SDValue(); 5883} 5884 5885/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5886/// are the two values being selected between, see if we can simplify the 5887/// select. Callers of this should assume that TheSelect is deleted if this 5888/// returns true. As such, they should return the appropriate thing (e.g. the 5889/// node) back to the top-level of the DAG combiner loop to avoid it being 5890/// looked at. 5891bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5892 SDValue RHS) { 5893 5894 // If this is a select from two identical things, try to pull the operation 5895 // through the select. 5896 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5897 // If this is a load and the token chain is identical, replace the select 5898 // of two loads with a load through a select of the address to load from. 5899 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5900 // constants have been dropped into the constant pool. 5901 if (LHS.getOpcode() == ISD::LOAD && 5902 // Do not let this transformation reduce the number of volatile loads. 5903 !cast<LoadSDNode>(LHS)->isVolatile() && 5904 !cast<LoadSDNode>(RHS)->isVolatile() && 5905 // Token chains must be identical. 5906 LHS.getOperand(0) == RHS.getOperand(0)) { 5907 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5908 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5909 5910 // If this is an EXTLOAD, the VT's must match. 5911 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5912 // FIXME: this discards src value information. This is 5913 // over-conservative. It would be beneficial to be able to remember 5914 // both potential memory locations. Since we are discarding 5915 // src value info, don't do the transformation if the memory 5916 // locations are not in the default address space. 5917 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0; 5918 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) { 5919 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType())) 5920 LLDAddrSpace = PT->getAddressSpace(); 5921 } 5922 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) { 5923 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType())) 5924 RLDAddrSpace = PT->getAddressSpace(); 5925 } 5926 SDValue Addr; 5927 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) { 5928 if (TheSelect->getOpcode() == ISD::SELECT) { 5929 // Check that the condition doesn't reach either load. If so, folding 5930 // this will induce a cycle into the DAG. 5931 if ((!LLD->hasAnyUseOfValue(1) || 5932 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 5933 (!RLD->hasAnyUseOfValue(1) || 5934 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 5935 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5936 LLD->getBasePtr().getValueType(), 5937 TheSelect->getOperand(0), LLD->getBasePtr(), 5938 RLD->getBasePtr()); 5939 } 5940 } else { 5941 // Check that the condition doesn't reach either load. If so, folding 5942 // this will induce a cycle into the DAG. 5943 if ((!LLD->hasAnyUseOfValue(1) || 5944 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5945 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 5946 (!RLD->hasAnyUseOfValue(1) || 5947 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5948 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 5949 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5950 LLD->getBasePtr().getValueType(), 5951 TheSelect->getOperand(0), 5952 TheSelect->getOperand(1), 5953 LLD->getBasePtr(), RLD->getBasePtr(), 5954 TheSelect->getOperand(4)); 5955 } 5956 } 5957 } 5958 5959 if (Addr.getNode()) { 5960 SDValue Load; 5961 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5962 Load = DAG.getLoad(TheSelect->getValueType(0), 5963 TheSelect->getDebugLoc(), 5964 LLD->getChain(), 5965 Addr, 0, 0, 5966 LLD->isVolatile(), 5967 LLD->isNonTemporal(), 5968 LLD->getAlignment()); 5969 } else { 5970 Load = DAG.getExtLoad(LLD->getExtensionType(), 5971 TheSelect->getDebugLoc(), 5972 TheSelect->getValueType(0), 5973 LLD->getChain(), Addr, 0, 0, 5974 LLD->getMemoryVT(), 5975 LLD->isVolatile(), 5976 LLD->isNonTemporal(), 5977 LLD->getAlignment()); 5978 } 5979 5980 // Users of the select now use the result of the load. 5981 CombineTo(TheSelect, Load); 5982 5983 // Users of the old loads now use the new load's chain. We know the 5984 // old-load value is dead now. 5985 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5986 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5987 return true; 5988 } 5989 } 5990 } 5991 } 5992 5993 return false; 5994} 5995 5996/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5997/// where 'cond' is the comparison specified by CC. 5998SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5999 SDValue N2, SDValue N3, 6000 ISD::CondCode CC, bool NotExtCompare) { 6001 // (x ? y : y) -> y. 6002 if (N2 == N3) return N2; 6003 6004 EVT VT = N2.getValueType(); 6005 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 6006 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 6007 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 6008 6009 // Determine if the condition we're dealing with is constant 6010 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 6011 N0, N1, CC, DL, false); 6012 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 6013 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 6014 6015 // fold select_cc true, x, y -> x 6016 if (SCCC && !SCCC->isNullValue()) 6017 return N2; 6018 // fold select_cc false, x, y -> y 6019 if (SCCC && SCCC->isNullValue()) 6020 return N3; 6021 6022 // Check to see if we can simplify the select into an fabs node 6023 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 6024 // Allow either -0.0 or 0.0 6025 if (CFP->getValueAPF().isZero()) { 6026 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 6027 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 6028 N0 == N2 && N3.getOpcode() == ISD::FNEG && 6029 N2 == N3.getOperand(0)) 6030 return DAG.getNode(ISD::FABS, DL, VT, N0); 6031 6032 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 6033 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 6034 N0 == N3 && N2.getOpcode() == ISD::FNEG && 6035 N2.getOperand(0) == N3) 6036 return DAG.getNode(ISD::FABS, DL, VT, N3); 6037 } 6038 } 6039 6040 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 6041 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 6042 // in it. This is a win when the constant is not otherwise available because 6043 // it replaces two constant pool loads with one. We only do this if the FP 6044 // type is known to be legal, because if it isn't, then we are before legalize 6045 // types an we want the other legalization to happen first (e.g. to avoid 6046 // messing with soft float) and if the ConstantFP is not legal, because if 6047 // it is legal, we may not need to store the FP constant in a constant pool. 6048 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 6049 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 6050 if (TLI.isTypeLegal(N2.getValueType()) && 6051 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 6052 TargetLowering::Legal) && 6053 // If both constants have multiple uses, then we won't need to do an 6054 // extra load, they are likely around in registers for other users. 6055 (TV->hasOneUse() || FV->hasOneUse())) { 6056 Constant *Elts[] = { 6057 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6058 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6059 }; 6060 const Type *FPTy = Elts[0]->getType(); 6061 const TargetData &TD = *TLI.getTargetData(); 6062 6063 // Create a ConstantArray of the two constants. 6064 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6065 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6066 TD.getPrefTypeAlignment(FPTy)); 6067 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6068 6069 // Get the offsets to the 0 and 1 element of the array so that we can 6070 // select between them. 6071 SDValue Zero = DAG.getIntPtrConstant(0); 6072 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6073 SDValue One = DAG.getIntPtrConstant(EltSize); 6074 6075 SDValue Cond = DAG.getSetCC(DL, 6076 TLI.getSetCCResultType(N0.getValueType()), 6077 N0, N1, CC); 6078 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6079 Cond, One, Zero); 6080 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6081 CstOffset); 6082 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6083 PseudoSourceValue::getConstantPool(), 0, false, 6084 false, Alignment); 6085 6086 } 6087 } 6088 6089 // Check to see if we can perform the "gzip trick", transforming 6090 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6091 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6092 N0.getValueType().isInteger() && 6093 N2.getValueType().isInteger() && 6094 (N1C->isNullValue() || // (a < 0) ? b : 0 6095 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6096 EVT XType = N0.getValueType(); 6097 EVT AType = N2.getValueType(); 6098 if (XType.bitsGE(AType)) { 6099 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6100 // single-bit constant. 6101 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6102 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6103 ShCtV = XType.getSizeInBits()-ShCtV-1; 6104 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6105 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6106 XType, N0, ShCt); 6107 AddToWorkList(Shift.getNode()); 6108 6109 if (XType.bitsGT(AType)) { 6110 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6111 AddToWorkList(Shift.getNode()); 6112 } 6113 6114 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6115 } 6116 6117 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6118 XType, N0, 6119 DAG.getConstant(XType.getSizeInBits()-1, 6120 getShiftAmountTy())); 6121 AddToWorkList(Shift.getNode()); 6122 6123 if (XType.bitsGT(AType)) { 6124 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6125 AddToWorkList(Shift.getNode()); 6126 } 6127 6128 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6129 } 6130 } 6131 6132 // fold select C, 16, 0 -> shl C, 4 6133 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6134 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6135 6136 // If the caller doesn't want us to simplify this into a zext of a compare, 6137 // don't do it. 6138 if (NotExtCompare && N2C->getAPIntValue() == 1) 6139 return SDValue(); 6140 6141 // Get a SetCC of the condition 6142 // FIXME: Should probably make sure that setcc is legal if we ever have a 6143 // target where it isn't. 6144 SDValue Temp, SCC; 6145 // cast from setcc result type to select result type 6146 if (LegalTypes) { 6147 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6148 N0, N1, CC); 6149 if (N2.getValueType().bitsLT(SCC.getValueType())) 6150 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6151 else 6152 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6153 N2.getValueType(), SCC); 6154 } else { 6155 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6156 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6157 N2.getValueType(), SCC); 6158 } 6159 6160 AddToWorkList(SCC.getNode()); 6161 AddToWorkList(Temp.getNode()); 6162 6163 if (N2C->getAPIntValue() == 1) 6164 return Temp; 6165 6166 // shl setcc result by log2 n2c 6167 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6168 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6169 getShiftAmountTy())); 6170 } 6171 6172 // Check to see if this is the equivalent of setcc 6173 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6174 // otherwise, go ahead with the folds. 6175 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6176 EVT XType = N0.getValueType(); 6177 if (!LegalOperations || 6178 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6179 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6180 if (Res.getValueType() != VT) 6181 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6182 return Res; 6183 } 6184 6185 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6186 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6187 (!LegalOperations || 6188 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6189 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6190 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6191 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6192 getShiftAmountTy())); 6193 } 6194 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6195 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6196 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6197 XType, DAG.getConstant(0, XType), N0); 6198 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6199 return DAG.getNode(ISD::SRL, DL, XType, 6200 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6201 DAG.getConstant(XType.getSizeInBits()-1, 6202 getShiftAmountTy())); 6203 } 6204 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6205 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6206 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6207 DAG.getConstant(XType.getSizeInBits()-1, 6208 getShiftAmountTy())); 6209 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6210 } 6211 } 6212 6213 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6214 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6215 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6216 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6217 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6218 EVT XType = N0.getValueType(); 6219 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6220 DAG.getConstant(XType.getSizeInBits()-1, 6221 getShiftAmountTy())); 6222 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6223 N0, Shift); 6224 AddToWorkList(Shift.getNode()); 6225 AddToWorkList(Add.getNode()); 6226 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6227 } 6228 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6229 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6230 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6231 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6232 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6233 EVT XType = N0.getValueType(); 6234 if (SubC->isNullValue() && XType.isInteger()) { 6235 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6236 N0, 6237 DAG.getConstant(XType.getSizeInBits()-1, 6238 getShiftAmountTy())); 6239 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6240 XType, N0, Shift); 6241 AddToWorkList(Shift.getNode()); 6242 AddToWorkList(Add.getNode()); 6243 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6244 } 6245 } 6246 } 6247 6248 return SDValue(); 6249} 6250 6251/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6252SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6253 SDValue N1, ISD::CondCode Cond, 6254 DebugLoc DL, bool foldBooleans) { 6255 TargetLowering::DAGCombinerInfo 6256 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6257 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6258} 6259 6260/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6261/// return a DAG expression to select that will generate the same value by 6262/// multiplying by a magic number. See: 6263/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6264SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6265 std::vector<SDNode*> Built; 6266 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6267 6268 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6269 ii != ee; ++ii) 6270 AddToWorkList(*ii); 6271 return S; 6272} 6273 6274/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6275/// return a DAG expression to select that will generate the same value by 6276/// multiplying by a magic number. See: 6277/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6278SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6279 std::vector<SDNode*> Built; 6280 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6281 6282 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6283 ii != ee; ++ii) 6284 AddToWorkList(*ii); 6285 return S; 6286} 6287 6288/// FindBaseOffset - Return true if base is a frame index, which is known not 6289// to alias with anything but itself. Provides base object and offset as results. 6290static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6291 const GlobalValue *&GV, void *&CV) { 6292 // Assume it is a primitive operation. 6293 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6294 6295 // If it's an adding a simple constant then integrate the offset. 6296 if (Base.getOpcode() == ISD::ADD) { 6297 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6298 Base = Base.getOperand(0); 6299 Offset += C->getZExtValue(); 6300 } 6301 } 6302 6303 // Return the underlying GlobalValue, and update the Offset. Return false 6304 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6305 // by multiple nodes with different offsets. 6306 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6307 GV = G->getGlobal(); 6308 Offset += G->getOffset(); 6309 return false; 6310 } 6311 6312 // Return the underlying Constant value, and update the Offset. Return false 6313 // for ConstantSDNodes since the same constant pool entry may be represented 6314 // by multiple nodes with different offsets. 6315 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6316 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6317 : (void *)C->getConstVal(); 6318 Offset += C->getOffset(); 6319 return false; 6320 } 6321 // If it's any of the following then it can't alias with anything but itself. 6322 return isa<FrameIndexSDNode>(Base); 6323} 6324 6325/// isAlias - Return true if there is any possibility that the two addresses 6326/// overlap. 6327bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6328 const Value *SrcValue1, int SrcValueOffset1, 6329 unsigned SrcValueAlign1, 6330 SDValue Ptr2, int64_t Size2, 6331 const Value *SrcValue2, int SrcValueOffset2, 6332 unsigned SrcValueAlign2) const { 6333 // If they are the same then they must be aliases. 6334 if (Ptr1 == Ptr2) return true; 6335 6336 // Gather base node and offset information. 6337 SDValue Base1, Base2; 6338 int64_t Offset1, Offset2; 6339 const GlobalValue *GV1, *GV2; 6340 void *CV1, *CV2; 6341 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6342 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6343 6344 // If they have a same base address then check to see if they overlap. 6345 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6346 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6347 6348 // If we know what the bases are, and they aren't identical, then we know they 6349 // cannot alias. 6350 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6351 return false; 6352 6353 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6354 // compared to the size and offset of the access, we may be able to prove they 6355 // do not alias. This check is conservative for now to catch cases created by 6356 // splitting vector types. 6357 if ((SrcValueAlign1 == SrcValueAlign2) && 6358 (SrcValueOffset1 != SrcValueOffset2) && 6359 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6360 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6361 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6362 6363 // There is no overlap between these relatively aligned accesses of similar 6364 // size, return no alias. 6365 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6366 return false; 6367 } 6368 6369 if (CombinerGlobalAA) { 6370 // Use alias analysis information. 6371 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6372 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6373 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6374 AliasAnalysis::AliasResult AAResult = 6375 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6376 if (AAResult == AliasAnalysis::NoAlias) 6377 return false; 6378 } 6379 6380 // Otherwise we have to assume they alias. 6381 return true; 6382} 6383 6384/// FindAliasInfo - Extracts the relevant alias information from the memory 6385/// node. Returns true if the operand was a load. 6386bool DAGCombiner::FindAliasInfo(SDNode *N, 6387 SDValue &Ptr, int64_t &Size, 6388 const Value *&SrcValue, 6389 int &SrcValueOffset, 6390 unsigned &SrcValueAlign) const { 6391 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6392 Ptr = LD->getBasePtr(); 6393 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6394 SrcValue = LD->getSrcValue(); 6395 SrcValueOffset = LD->getSrcValueOffset(); 6396 SrcValueAlign = LD->getOriginalAlignment(); 6397 return true; 6398 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6399 Ptr = ST->getBasePtr(); 6400 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6401 SrcValue = ST->getSrcValue(); 6402 SrcValueOffset = ST->getSrcValueOffset(); 6403 SrcValueAlign = ST->getOriginalAlignment(); 6404 } else { 6405 llvm_unreachable("FindAliasInfo expected a memory operand"); 6406 } 6407 6408 return false; 6409} 6410 6411/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6412/// looking for aliasing nodes and adding them to the Aliases vector. 6413void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6414 SmallVector<SDValue, 8> &Aliases) { 6415 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6416 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 6417 6418 // Get alias information for node. 6419 SDValue Ptr; 6420 int64_t Size; 6421 const Value *SrcValue; 6422 int SrcValueOffset; 6423 unsigned SrcValueAlign; 6424 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 6425 SrcValueAlign); 6426 6427 // Starting off. 6428 Chains.push_back(OriginalChain); 6429 unsigned Depth = 0; 6430 6431 // Look at each chain and determine if it is an alias. If so, add it to the 6432 // aliases list. If not, then continue up the chain looking for the next 6433 // candidate. 6434 while (!Chains.empty()) { 6435 SDValue Chain = Chains.back(); 6436 Chains.pop_back(); 6437 6438 // For TokenFactor nodes, look at each operand and only continue up the 6439 // chain until we find two aliases. If we've seen two aliases, assume we'll 6440 // find more and revert to original chain since the xform is unlikely to be 6441 // profitable. 6442 // 6443 // FIXME: The depth check could be made to return the last non-aliasing 6444 // chain we found before we hit a tokenfactor rather than the original 6445 // chain. 6446 if (Depth > 6 || Aliases.size() == 2) { 6447 Aliases.clear(); 6448 Aliases.push_back(OriginalChain); 6449 break; 6450 } 6451 6452 // Don't bother if we've been before. 6453 if (!Visited.insert(Chain.getNode())) 6454 continue; 6455 6456 switch (Chain.getOpcode()) { 6457 case ISD::EntryToken: 6458 // Entry token is ideal chain operand, but handled in FindBetterChain. 6459 break; 6460 6461 case ISD::LOAD: 6462 case ISD::STORE: { 6463 // Get alias information for Chain. 6464 SDValue OpPtr; 6465 int64_t OpSize; 6466 const Value *OpSrcValue; 6467 int OpSrcValueOffset; 6468 unsigned OpSrcValueAlign; 6469 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6470 OpSrcValue, OpSrcValueOffset, 6471 OpSrcValueAlign); 6472 6473 // If chain is alias then stop here. 6474 if (!(IsLoad && IsOpLoad) && 6475 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 6476 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 6477 OpSrcValueAlign)) { 6478 Aliases.push_back(Chain); 6479 } else { 6480 // Look further up the chain. 6481 Chains.push_back(Chain.getOperand(0)); 6482 ++Depth; 6483 } 6484 break; 6485 } 6486 6487 case ISD::TokenFactor: 6488 // We have to check each of the operands of the token factor for "small" 6489 // token factors, so we queue them up. Adding the operands to the queue 6490 // (stack) in reverse order maintains the original order and increases the 6491 // likelihood that getNode will find a matching token factor (CSE.) 6492 if (Chain.getNumOperands() > 16) { 6493 Aliases.push_back(Chain); 6494 break; 6495 } 6496 for (unsigned n = Chain.getNumOperands(); n;) 6497 Chains.push_back(Chain.getOperand(--n)); 6498 ++Depth; 6499 break; 6500 6501 default: 6502 // For all other instructions we will just have to take what we can get. 6503 Aliases.push_back(Chain); 6504 break; 6505 } 6506 } 6507} 6508 6509/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6510/// for a better chain (aliasing node.) 6511SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6512 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6513 6514 // Accumulate all the aliases to this node. 6515 GatherAllAliases(N, OldChain, Aliases); 6516 6517 if (Aliases.size() == 0) { 6518 // If no operands then chain to entry token. 6519 return DAG.getEntryNode(); 6520 } else if (Aliases.size() == 1) { 6521 // If a single operand then chain to it. We don't need to revisit it. 6522 return Aliases[0]; 6523 } 6524 6525 // Construct a custom tailored token factor. 6526 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6527 &Aliases[0], Aliases.size()); 6528} 6529 6530// SelectionDAG::Combine - This is the entry point for the file. 6531// 6532void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6533 CodeGenOpt::Level OptLevel) { 6534 /// run - This is the main entry point to this class. 6535 /// 6536 DAGCombiner(*this, AA, OptLevel).Run(Level); 6537} 6538