DAGCombiner.cpp revision 3eba667081cb63761861e4543715c90f8fc47b18
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 unsigned SrcValueAlign1, 242 SDValue Ptr2, int64_t Size2, 243 const Value *SrcValue2, int SrcValueOffset2, 244 unsigned SrcValueAlign2) const; 245 246 /// FindAliasInfo - Extracts the relevant alias information from the memory 247 /// node. Returns true if the operand was a load. 248 bool FindAliasInfo(SDNode *N, 249 SDValue &Ptr, int64_t &Size, 250 const Value *&SrcValue, int &SrcValueOffset, 251 unsigned &SrcValueAlignment) const; 252 253 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 254 /// looking for a better chain (aliasing node.) 255 SDValue FindBetterChain(SDNode *N, SDValue Chain); 256 257 /// getShiftAmountTy - Returns a type large enough to hold any valid 258 /// shift amount - before type legalization these can be huge. 259 EVT getShiftAmountTy() { 260 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 261 } 262 263public: 264 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 265 : DAG(D), 266 TLI(D.getTargetLoweringInfo()), 267 Level(Unrestricted), 268 OptLevel(OL), 269 LegalOperations(false), 270 LegalTypes(false), 271 AA(A) {} 272 273 /// Run - runs the dag combiner on all nodes in the work list 274 void Run(CombineLevel AtLevel); 275 }; 276} 277 278 279namespace { 280/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 281/// nodes from the worklist. 282class WorkListRemover : public SelectionDAG::DAGUpdateListener { 283 DAGCombiner &DC; 284public: 285 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 286 287 virtual void NodeDeleted(SDNode *N, SDNode *E) { 288 DC.removeFromWorkList(N); 289 } 290 291 virtual void NodeUpdated(SDNode *N) { 292 // Ignore updates. 293 } 294}; 295} 296 297//===----------------------------------------------------------------------===// 298// TargetLowering::DAGCombinerInfo implementation 299//===----------------------------------------------------------------------===// 300 301void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 302 ((DAGCombiner*)DC)->AddToWorkList(N); 303} 304 305SDValue TargetLowering::DAGCombinerInfo:: 306CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 307 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 308} 309 310SDValue TargetLowering::DAGCombinerInfo:: 311CombineTo(SDNode *N, SDValue Res, bool AddTo) { 312 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 313} 314 315 316SDValue TargetLowering::DAGCombinerInfo:: 317CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 318 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 319} 320 321void TargetLowering::DAGCombinerInfo:: 322CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 323 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 324} 325 326//===----------------------------------------------------------------------===// 327// Helper Functions 328//===----------------------------------------------------------------------===// 329 330/// isNegatibleForFree - Return 1 if we can compute the negated form of the 331/// specified expression for the same cost as the expression itself, or 2 if we 332/// can compute the negated form more cheaply than the expression itself. 333static char isNegatibleForFree(SDValue Op, bool LegalOperations, 334 unsigned Depth = 0) { 335 // No compile time optimizations on this type. 336 if (Op.getValueType() == MVT::ppcf128) 337 return 0; 338 339 // fneg is removable even if it has multiple uses. 340 if (Op.getOpcode() == ISD::FNEG) return 2; 341 342 // Don't allow anything with multiple uses. 343 if (!Op.hasOneUse()) return 0; 344 345 // Don't recurse exponentially. 346 if (Depth > 6) return 0; 347 348 switch (Op.getOpcode()) { 349 default: return false; 350 case ISD::ConstantFP: 351 // Don't invert constant FP values after legalize. The negated constant 352 // isn't necessarily legal. 353 return LegalOperations ? 0 : 1; 354 case ISD::FADD: 355 // FIXME: determine better conditions for this xform. 356 if (!UnsafeFPMath) return 0; 357 358 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 359 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 360 return V; 361 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 362 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 363 case ISD::FSUB: 364 // We can't turn -(A-B) into B-A when we honor signed zeros. 365 if (!UnsafeFPMath) return 0; 366 367 // fold (fneg (fsub A, B)) -> (fsub B, A) 368 return 1; 369 370 case ISD::FMUL: 371 case ISD::FDIV: 372 if (HonorSignDependentRoundingFPMath()) return 0; 373 374 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 376 return V; 377 378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 379 380 case ISD::FP_EXTEND: 381 case ISD::FP_ROUND: 382 case ISD::FSIN: 383 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 384 } 385} 386 387/// GetNegatedExpression - If isNegatibleForFree returns true, this function 388/// returns the newly negated expression. 389static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 390 bool LegalOperations, unsigned Depth = 0) { 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 393 394 // Don't allow anything with multiple uses. 395 assert(Op.hasOneUse() && "Unknown reuse!"); 396 397 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 398 switch (Op.getOpcode()) { 399 default: llvm_unreachable("Unknown code"); 400 case ISD::ConstantFP: { 401 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 402 V.changeSign(); 403 return DAG.getConstantFP(V, Op.getValueType()); 404 } 405 case ISD::FADD: 406 // FIXME: determine better conditions for this xform. 407 assert(UnsafeFPMath); 408 409 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 410 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 411 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 LegalOperations, Depth+1), 414 Op.getOperand(1)); 415 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 416 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 417 GetNegatedExpression(Op.getOperand(1), DAG, 418 LegalOperations, Depth+1), 419 Op.getOperand(0)); 420 case ISD::FSUB: 421 // We can't turn -(A-B) into B-A when we honor signed zeros. 422 assert(UnsafeFPMath); 423 424 // fold (fneg (fsub 0, B)) -> B 425 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 426 if (N0CFP->getValueAPF().isZero()) 427 return Op.getOperand(1); 428 429 // fold (fneg (fsub A, B)) -> (fsub B, A) 430 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 431 Op.getOperand(1), Op.getOperand(0)); 432 433 case ISD::FMUL: 434 case ISD::FDIV: 435 assert(!HonorSignDependentRoundingFPMath()); 436 437 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 438 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 439 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 440 GetNegatedExpression(Op.getOperand(0), DAG, 441 LegalOperations, Depth+1), 442 Op.getOperand(1)); 443 444 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 445 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 446 Op.getOperand(0), 447 GetNegatedExpression(Op.getOperand(1), DAG, 448 LegalOperations, Depth+1)); 449 450 case ISD::FP_EXTEND: 451 case ISD::FSIN: 452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1)); 455 case ISD::FP_ROUND: 456 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 457 GetNegatedExpression(Op.getOperand(0), DAG, 458 LegalOperations, Depth+1), 459 Op.getOperand(1)); 460 } 461} 462 463 464// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 465// that selects between the values 1 and 0, making it equivalent to a setcc. 466// Also, set the incoming LHS, RHS, and CC references to the appropriate 467// nodes based on the type of node we are checking. This simplifies life a 468// bit for the callers. 469static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 470 SDValue &CC) { 471 if (N.getOpcode() == ISD::SETCC) { 472 LHS = N.getOperand(0); 473 RHS = N.getOperand(1); 474 CC = N.getOperand(2); 475 return true; 476 } 477 if (N.getOpcode() == ISD::SELECT_CC && 478 N.getOperand(2).getOpcode() == ISD::Constant && 479 N.getOperand(3).getOpcode() == ISD::Constant && 480 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 481 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 482 LHS = N.getOperand(0); 483 RHS = N.getOperand(1); 484 CC = N.getOperand(4); 485 return true; 486 } 487 return false; 488} 489 490// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 491// one use. If this is true, it allows the users to invert the operation for 492// free when it is profitable to do so. 493static bool isOneUseSetCC(SDValue N) { 494 SDValue N0, N1, N2; 495 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 496 return true; 497 return false; 498} 499 500SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 501 SDValue N0, SDValue N1) { 502 EVT VT = N0.getValueType(); 503 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 504 if (isa<ConstantSDNode>(N1)) { 505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 506 SDValue OpNode = 507 DAG.FoldConstantArithmetic(Opc, VT, 508 cast<ConstantSDNode>(N0.getOperand(1)), 509 cast<ConstantSDNode>(N1)); 510 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 511 } else if (N0.hasOneUse()) { 512 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 513 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 514 N0.getOperand(0), N1); 515 AddToWorkList(OpNode.getNode()); 516 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 517 } 518 } 519 520 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 521 if (isa<ConstantSDNode>(N0)) { 522 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 523 SDValue OpNode = 524 DAG.FoldConstantArithmetic(Opc, VT, 525 cast<ConstantSDNode>(N1.getOperand(1)), 526 cast<ConstantSDNode>(N0)); 527 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 528 } else if (N1.hasOneUse()) { 529 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 530 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 531 N1.getOperand(0), N0); 532 AddToWorkList(OpNode.getNode()); 533 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 534 } 535 } 536 537 return SDValue(); 538} 539 540SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 541 bool AddTo) { 542 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 543 ++NodesCombined; 544 DEBUG(dbgs() << "\nReplacing.1 "; 545 N->dump(&DAG); 546 dbgs() << "\nWith: "; 547 To[0].getNode()->dump(&DAG); 548 dbgs() << " and " << NumTo-1 << " other values\n"; 549 for (unsigned i = 0, e = NumTo; i != e; ++i) 550 assert((!To[i].getNode() || 551 N->getValueType(i) == To[i].getValueType()) && 552 "Cannot combine value to value of different type!")); 553 WorkListRemover DeadNodes(*this); 554 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 555 556 if (AddTo) { 557 // Push the new nodes and any users onto the worklist 558 for (unsigned i = 0, e = NumTo; i != e; ++i) { 559 if (To[i].getNode()) { 560 AddToWorkList(To[i].getNode()); 561 AddUsersToWorkList(To[i].getNode()); 562 } 563 } 564 } 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (N->use_empty()) { 570 // Nodes can be reintroduced into the worklist. Make sure we do not 571 // process a node that has been replaced. 572 removeFromWorkList(N); 573 574 // Finally, since the node is now dead, remove it from the graph. 575 DAG.DeleteNode(N); 576 } 577 return SDValue(N, 0); 578} 579 580void 581DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 582 TLO) { 583 // Replace all uses. If any nodes become isomorphic to other nodes and 584 // are deleted, make sure to remove them from our worklist. 585 WorkListRemover DeadNodes(*this); 586 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 587 588 // Push the new node and any (possibly new) users onto the worklist. 589 AddToWorkList(TLO.New.getNode()); 590 AddUsersToWorkList(TLO.New.getNode()); 591 592 // Finally, if the node is now dead, remove it from the graph. The node 593 // may not be dead if the replacement process recursively simplified to 594 // something else needing this node. 595 if (TLO.Old.getNode()->use_empty()) { 596 removeFromWorkList(TLO.Old.getNode()); 597 598 // If the operands of this node are only used by the node, they will now 599 // be dead. Make sure to visit them first to delete dead nodes early. 600 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 601 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 602 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 603 604 DAG.DeleteNode(TLO.Old.getNode()); 605 } 606} 607 608/// SimplifyDemandedBits - Check the specified integer node value to see if 609/// it can be simplified or if things it uses can be simplified by bit 610/// propagation. If so, return true. 611bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 612 TargetLowering::TargetLoweringOpt TLO(DAG); 613 APInt KnownZero, KnownOne; 614 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 615 return false; 616 617 // Revisit the node. 618 AddToWorkList(Op.getNode()); 619 620 // Replace the old value with the new one. 621 ++NodesCombined; 622 DEBUG(dbgs() << "\nReplacing.2 "; 623 TLO.Old.getNode()->dump(&DAG); 624 dbgs() << "\nWith: "; 625 TLO.New.getNode()->dump(&DAG); 626 dbgs() << '\n'); 627 628 CommitTargetLoweringOpt(TLO); 629 return true; 630} 631 632//===----------------------------------------------------------------------===// 633// Main DAG Combiner implementation 634//===----------------------------------------------------------------------===// 635 636void DAGCombiner::Run(CombineLevel AtLevel) { 637 // set the instance variables, so that the various visit routines may use it. 638 Level = AtLevel; 639 LegalOperations = Level >= NoIllegalOperations; 640 LegalTypes = Level >= NoIllegalTypes; 641 642 // Add all the dag nodes to the worklist. 643 WorkList.reserve(DAG.allnodes_size()); 644 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 645 E = DAG.allnodes_end(); I != E; ++I) 646 WorkList.push_back(I); 647 648 // Create a dummy node (which is not added to allnodes), that adds a reference 649 // to the root node, preventing it from being deleted, and tracking any 650 // changes of the root. 651 HandleSDNode Dummy(DAG.getRoot()); 652 653 // The root of the dag may dangle to deleted nodes until the dag combiner is 654 // done. Set it to null to avoid confusion. 655 DAG.setRoot(SDValue()); 656 657 // while the worklist isn't empty, inspect the node on the end of it and 658 // try and combine it. 659 while (!WorkList.empty()) { 660 SDNode *N = WorkList.back(); 661 WorkList.pop_back(); 662 663 // If N has no uses, it is dead. Make sure to revisit all N's operands once 664 // N is deleted from the DAG, since they too may now be dead or may have a 665 // reduced number of uses, allowing other xforms. 666 if (N->use_empty() && N != &Dummy) { 667 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 668 AddToWorkList(N->getOperand(i).getNode()); 669 670 DAG.DeleteNode(N); 671 continue; 672 } 673 674 SDValue RV = combine(N); 675 676 if (RV.getNode() == 0) 677 continue; 678 679 ++NodesCombined; 680 681 // If we get back the same node we passed in, rather than a new node or 682 // zero, we know that the node must have defined multiple values and 683 // CombineTo was used. Since CombineTo takes care of the worklist 684 // mechanics for us, we have no work to do in this case. 685 if (RV.getNode() == N) 686 continue; 687 688 assert(N->getOpcode() != ISD::DELETED_NODE && 689 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 690 "Node was deleted but visit returned new node!"); 691 692 DEBUG(dbgs() << "\nReplacing.3 "; 693 N->dump(&DAG); 694 dbgs() << "\nWith: "; 695 RV.getNode()->dump(&DAG); 696 dbgs() << '\n'); 697 WorkListRemover DeadNodes(*this); 698 if (N->getNumValues() == RV.getNode()->getNumValues()) 699 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 700 else { 701 assert(N->getValueType(0) == RV.getValueType() && 702 N->getNumValues() == 1 && "Type mismatch"); 703 SDValue OpV = RV; 704 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 705 } 706 707 // Push the new node and any users onto the worklist 708 AddToWorkList(RV.getNode()); 709 AddUsersToWorkList(RV.getNode()); 710 711 // Add any uses of the old node to the worklist in case this node is the 712 // last one that uses them. They may become dead after this node is 713 // deleted. 714 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 715 AddToWorkList(N->getOperand(i).getNode()); 716 717 // Finally, if the node is now dead, remove it from the graph. The node 718 // may not be dead if the replacement process recursively simplified to 719 // something else needing this node. 720 if (N->use_empty()) { 721 // Nodes can be reintroduced into the worklist. Make sure we do not 722 // process a node that has been replaced. 723 removeFromWorkList(N); 724 725 // Finally, since the node is now dead, remove it from the graph. 726 DAG.DeleteNode(N); 727 } 728 } 729 730 // If the root changed (e.g. it was a dead load, update the root). 731 DAG.setRoot(Dummy.getValue()); 732} 733 734SDValue DAGCombiner::visit(SDNode *N) { 735 switch(N->getOpcode()) { 736 default: break; 737 case ISD::TokenFactor: return visitTokenFactor(N); 738 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 739 case ISD::ADD: return visitADD(N); 740 case ISD::SUB: return visitSUB(N); 741 case ISD::ADDC: return visitADDC(N); 742 case ISD::ADDE: return visitADDE(N); 743 case ISD::MUL: return visitMUL(N); 744 case ISD::SDIV: return visitSDIV(N); 745 case ISD::UDIV: return visitUDIV(N); 746 case ISD::SREM: return visitSREM(N); 747 case ISD::UREM: return visitUREM(N); 748 case ISD::MULHU: return visitMULHU(N); 749 case ISD::MULHS: return visitMULHS(N); 750 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 751 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 752 case ISD::SDIVREM: return visitSDIVREM(N); 753 case ISD::UDIVREM: return visitUDIVREM(N); 754 case ISD::AND: return visitAND(N); 755 case ISD::OR: return visitOR(N); 756 case ISD::XOR: return visitXOR(N); 757 case ISD::SHL: return visitSHL(N); 758 case ISD::SRA: return visitSRA(N); 759 case ISD::SRL: return visitSRL(N); 760 case ISD::CTLZ: return visitCTLZ(N); 761 case ISD::CTTZ: return visitCTTZ(N); 762 case ISD::CTPOP: return visitCTPOP(N); 763 case ISD::SELECT: return visitSELECT(N); 764 case ISD::SELECT_CC: return visitSELECT_CC(N); 765 case ISD::SETCC: return visitSETCC(N); 766 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 767 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 768 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 769 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 770 case ISD::TRUNCATE: return visitTRUNCATE(N); 771 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 772 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 773 case ISD::FADD: return visitFADD(N); 774 case ISD::FSUB: return visitFSUB(N); 775 case ISD::FMUL: return visitFMUL(N); 776 case ISD::FDIV: return visitFDIV(N); 777 case ISD::FREM: return visitFREM(N); 778 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 779 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 780 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 781 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 782 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 783 case ISD::FP_ROUND: return visitFP_ROUND(N); 784 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 785 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 786 case ISD::FNEG: return visitFNEG(N); 787 case ISD::FABS: return visitFABS(N); 788 case ISD::BRCOND: return visitBRCOND(N); 789 case ISD::BR_CC: return visitBR_CC(N); 790 case ISD::LOAD: return visitLOAD(N); 791 case ISD::STORE: return visitSTORE(N); 792 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 793 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 794 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 795 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 796 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 797 } 798 return SDValue(); 799} 800 801SDValue DAGCombiner::combine(SDNode *N) { 802 SDValue RV = visit(N); 803 804 // If nothing happened, try a target-specific DAG combine. 805 if (RV.getNode() == 0) { 806 assert(N->getOpcode() != ISD::DELETED_NODE && 807 "Node was deleted but visit returned NULL!"); 808 809 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 810 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 811 812 // Expose the DAG combiner to the target combiner impls. 813 TargetLowering::DAGCombinerInfo 814 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 815 816 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 817 } 818 } 819 820 // If N is a commutative binary node, try commuting it to enable more 821 // sdisel CSE. 822 if (RV.getNode() == 0 && 823 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 824 N->getNumValues() == 1) { 825 SDValue N0 = N->getOperand(0); 826 SDValue N1 = N->getOperand(1); 827 828 // Constant operands are canonicalized to RHS. 829 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 830 SDValue Ops[] = { N1, N0 }; 831 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 832 Ops, 2); 833 if (CSENode) 834 return SDValue(CSENode, 0); 835 } 836 } 837 838 return RV; 839} 840 841/// getInputChainForNode - Given a node, return its input chain if it has one, 842/// otherwise return a null sd operand. 843static SDValue getInputChainForNode(SDNode *N) { 844 if (unsigned NumOps = N->getNumOperands()) { 845 if (N->getOperand(0).getValueType() == MVT::Other) 846 return N->getOperand(0); 847 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 848 return N->getOperand(NumOps-1); 849 for (unsigned i = 1; i < NumOps-1; ++i) 850 if (N->getOperand(i).getValueType() == MVT::Other) 851 return N->getOperand(i); 852 } 853 return SDValue(); 854} 855 856SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 857 // If N has two operands, where one has an input chain equal to the other, 858 // the 'other' chain is redundant. 859 if (N->getNumOperands() == 2) { 860 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 861 return N->getOperand(0); 862 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 863 return N->getOperand(1); 864 } 865 866 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 867 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 868 SmallPtrSet<SDNode*, 16> SeenOps; 869 bool Changed = false; // If we should replace this token factor. 870 871 // Start out with this token factor. 872 TFs.push_back(N); 873 874 // Iterate through token factors. The TFs grows when new token factors are 875 // encountered. 876 for (unsigned i = 0; i < TFs.size(); ++i) { 877 SDNode *TF = TFs[i]; 878 879 // Check each of the operands. 880 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 881 SDValue Op = TF->getOperand(i); 882 883 switch (Op.getOpcode()) { 884 case ISD::EntryToken: 885 // Entry tokens don't need to be added to the list. They are 886 // rededundant. 887 Changed = true; 888 break; 889 890 case ISD::TokenFactor: 891 if (Op.hasOneUse() && 892 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 893 // Queue up for processing. 894 TFs.push_back(Op.getNode()); 895 // Clean up in case the token factor is removed. 896 AddToWorkList(Op.getNode()); 897 Changed = true; 898 break; 899 } 900 // Fall thru 901 902 default: 903 // Only add if it isn't already in the list. 904 if (SeenOps.insert(Op.getNode())) 905 Ops.push_back(Op); 906 else 907 Changed = true; 908 break; 909 } 910 } 911 } 912 913 SDValue Result; 914 915 // If we've change things around then replace token factor. 916 if (Changed) { 917 if (Ops.empty()) { 918 // The entry token is the only possible outcome. 919 Result = DAG.getEntryNode(); 920 } else { 921 // New and improved token factor. 922 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 923 MVT::Other, &Ops[0], Ops.size()); 924 } 925 926 // Don't add users to work list. 927 return CombineTo(N, Result, false); 928 } 929 930 return Result; 931} 932 933/// MERGE_VALUES can always be eliminated. 934SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 935 WorkListRemover DeadNodes(*this); 936 // Replacing results may cause a different MERGE_VALUES to suddenly 937 // be CSE'd with N, and carry its uses with it. Iterate until no 938 // uses remain, to ensure that the node can be safely deleted. 939 do { 940 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 942 &DeadNodes); 943 } while (!N->use_empty()); 944 removeFromWorkList(N); 945 DAG.DeleteNode(N); 946 return SDValue(N, 0); // Return N so it doesn't get rechecked! 947} 948 949static 950SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 951 SelectionDAG &DAG) { 952 EVT VT = N0.getValueType(); 953 SDValue N00 = N0.getOperand(0); 954 SDValue N01 = N0.getOperand(1); 955 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 956 957 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 958 isa<ConstantSDNode>(N00.getOperand(1))) { 959 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 960 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 961 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 962 N00.getOperand(0), N01), 963 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 964 N00.getOperand(1), N01)); 965 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 966 } 967 968 return SDValue(); 969} 970 971SDValue DAGCombiner::visitADD(SDNode *N) { 972 SDValue N0 = N->getOperand(0); 973 SDValue N1 = N->getOperand(1); 974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 976 EVT VT = N0.getValueType(); 977 978 // fold vector ops 979 if (VT.isVector()) { 980 SDValue FoldedVOp = SimplifyVBinOp(N); 981 if (FoldedVOp.getNode()) return FoldedVOp; 982 } 983 984 // fold (add x, undef) -> undef 985 if (N0.getOpcode() == ISD::UNDEF) 986 return N0; 987 if (N1.getOpcode() == ISD::UNDEF) 988 return N1; 989 // fold (add c1, c2) -> c1+c2 990 if (N0C && N1C) 991 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 992 // canonicalize constant to RHS 993 if (N0C && !N1C) 994 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 995 // fold (add x, 0) -> x 996 if (N1C && N1C->isNullValue()) 997 return N0; 998 // fold (add Sym, c) -> Sym+c 999 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1000 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1001 GA->getOpcode() == ISD::GlobalAddress) 1002 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1003 GA->getOffset() + 1004 (uint64_t)N1C->getSExtValue()); 1005 // fold ((c1-A)+c2) -> (c1+c2)-A 1006 if (N1C && N0.getOpcode() == ISD::SUB) 1007 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1008 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1009 DAG.getConstant(N1C->getAPIntValue()+ 1010 N0C->getAPIntValue(), VT), 1011 N0.getOperand(1)); 1012 // reassociate add 1013 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1014 if (RADD.getNode() != 0) 1015 return RADD; 1016 // fold ((0-A) + B) -> B-A 1017 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1018 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1020 // fold (A + (0-B)) -> A-B 1021 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1022 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1023 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1024 // fold (A+(B-A)) -> B 1025 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1026 return N1.getOperand(0); 1027 // fold ((B-A)+A) -> B 1028 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1029 return N0.getOperand(0); 1030 // fold (A+(B-(A+C))) to (B-C) 1031 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1032 N0 == N1.getOperand(1).getOperand(0)) 1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1034 N1.getOperand(1).getOperand(1)); 1035 // fold (A+(B-(C+A))) to (B-C) 1036 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1037 N0 == N1.getOperand(1).getOperand(1)) 1038 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1039 N1.getOperand(1).getOperand(0)); 1040 // fold (A+((B-A)+or-C)) to (B+or-C) 1041 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1042 N1.getOperand(0).getOpcode() == ISD::SUB && 1043 N0 == N1.getOperand(0).getOperand(1)) 1044 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1045 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1046 1047 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1048 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1049 SDValue N00 = N0.getOperand(0); 1050 SDValue N01 = N0.getOperand(1); 1051 SDValue N10 = N1.getOperand(0); 1052 SDValue N11 = N1.getOperand(1); 1053 1054 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1055 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1056 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1057 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1058 } 1059 1060 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1061 return SDValue(N, 0); 1062 1063 // fold (a+b) -> (a|b) iff a and b share no bits. 1064 if (VT.isInteger() && !VT.isVector()) { 1065 APInt LHSZero, LHSOne; 1066 APInt RHSZero, RHSOne; 1067 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1068 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1069 1070 if (LHSZero.getBoolValue()) { 1071 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1072 1073 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1074 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1075 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1076 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1078 } 1079 } 1080 1081 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1082 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1083 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1084 if (Result.getNode()) return Result; 1085 } 1086 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1087 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1088 if (Result.getNode()) return Result; 1089 } 1090 1091 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1092 if (N1.getOpcode() == ISD::SHL && 1093 N1.getOperand(0).getOpcode() == ISD::SUB) 1094 if (ConstantSDNode *C = 1095 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1096 if (C->getAPIntValue() == 0) 1097 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1098 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1099 N1.getOperand(0).getOperand(1), 1100 N1.getOperand(1))); 1101 if (N0.getOpcode() == ISD::SHL && 1102 N0.getOperand(0).getOpcode() == ISD::SUB) 1103 if (ConstantSDNode *C = 1104 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1105 if (C->getAPIntValue() == 0) 1106 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1107 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1108 N0.getOperand(0).getOperand(1), 1109 N0.getOperand(1))); 1110 1111 return SDValue(); 1112} 1113 1114SDValue DAGCombiner::visitADDC(SDNode *N) { 1115 SDValue N0 = N->getOperand(0); 1116 SDValue N1 = N->getOperand(1); 1117 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1118 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1119 EVT VT = N0.getValueType(); 1120 1121 // If the flag result is dead, turn this into an ADD. 1122 if (N->hasNUsesOfValue(0, 1)) 1123 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1124 DAG.getNode(ISD::CARRY_FALSE, 1125 N->getDebugLoc(), MVT::Flag)); 1126 1127 // canonicalize constant to RHS. 1128 if (N0C && !N1C) 1129 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1130 1131 // fold (addc x, 0) -> x + no carry out 1132 if (N1C && N1C->isNullValue()) 1133 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1134 N->getDebugLoc(), MVT::Flag)); 1135 1136 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1137 APInt LHSZero, LHSOne; 1138 APInt RHSZero, RHSOne; 1139 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1140 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1141 1142 if (LHSZero.getBoolValue()) { 1143 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1144 1145 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1146 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1147 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1148 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1149 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1150 DAG.getNode(ISD::CARRY_FALSE, 1151 N->getDebugLoc(), MVT::Flag)); 1152 } 1153 1154 return SDValue(); 1155} 1156 1157SDValue DAGCombiner::visitADDE(SDNode *N) { 1158 SDValue N0 = N->getOperand(0); 1159 SDValue N1 = N->getOperand(1); 1160 SDValue CarryIn = N->getOperand(2); 1161 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1162 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1163 1164 // canonicalize constant to RHS 1165 if (N0C && !N1C) 1166 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1167 N1, N0, CarryIn); 1168 1169 // fold (adde x, y, false) -> (addc x, y) 1170 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1171 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1172 1173 return SDValue(); 1174} 1175 1176SDValue DAGCombiner::visitSUB(SDNode *N) { 1177 SDValue N0 = N->getOperand(0); 1178 SDValue N1 = N->getOperand(1); 1179 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1180 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1181 EVT VT = N0.getValueType(); 1182 1183 // fold vector ops 1184 if (VT.isVector()) { 1185 SDValue FoldedVOp = SimplifyVBinOp(N); 1186 if (FoldedVOp.getNode()) return FoldedVOp; 1187 } 1188 1189 // fold (sub x, x) -> 0 1190 if (N0 == N1) 1191 return DAG.getConstant(0, N->getValueType(0)); 1192 // fold (sub c1, c2) -> c1-c2 1193 if (N0C && N1C) 1194 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1195 // fold (sub x, c) -> (add x, -c) 1196 if (N1C) 1197 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1198 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1199 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1200 if (N0C && N0C->isAllOnesValue()) 1201 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1202 // fold (A+B)-A -> B 1203 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1204 return N0.getOperand(1); 1205 // fold (A+B)-B -> A 1206 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1207 return N0.getOperand(0); 1208 // fold ((A+(B+or-C))-B) -> A+or-C 1209 if (N0.getOpcode() == ISD::ADD && 1210 (N0.getOperand(1).getOpcode() == ISD::SUB || 1211 N0.getOperand(1).getOpcode() == ISD::ADD) && 1212 N0.getOperand(1).getOperand(0) == N1) 1213 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1214 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1215 // fold ((A+(C+B))-B) -> A+C 1216 if (N0.getOpcode() == ISD::ADD && 1217 N0.getOperand(1).getOpcode() == ISD::ADD && 1218 N0.getOperand(1).getOperand(1) == N1) 1219 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1220 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1221 // fold ((A-(B-C))-C) -> A-B 1222 if (N0.getOpcode() == ISD::SUB && 1223 N0.getOperand(1).getOpcode() == ISD::SUB && 1224 N0.getOperand(1).getOperand(1) == N1) 1225 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1226 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1227 1228 // If either operand of a sub is undef, the result is undef 1229 if (N0.getOpcode() == ISD::UNDEF) 1230 return N0; 1231 if (N1.getOpcode() == ISD::UNDEF) 1232 return N1; 1233 1234 // If the relocation model supports it, consider symbol offsets. 1235 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1236 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1237 // fold (sub Sym, c) -> Sym-c 1238 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1239 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1240 GA->getOffset() - 1241 (uint64_t)N1C->getSExtValue()); 1242 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1243 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1244 if (GA->getGlobal() == GB->getGlobal()) 1245 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1246 VT); 1247 } 1248 1249 return SDValue(); 1250} 1251 1252SDValue DAGCombiner::visitMUL(SDNode *N) { 1253 SDValue N0 = N->getOperand(0); 1254 SDValue N1 = N->getOperand(1); 1255 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1256 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1257 EVT VT = N0.getValueType(); 1258 1259 // fold vector ops 1260 if (VT.isVector()) { 1261 SDValue FoldedVOp = SimplifyVBinOp(N); 1262 if (FoldedVOp.getNode()) return FoldedVOp; 1263 } 1264 1265 // fold (mul x, undef) -> 0 1266 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1267 return DAG.getConstant(0, VT); 1268 // fold (mul c1, c2) -> c1*c2 1269 if (N0C && N1C) 1270 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1271 // canonicalize constant to RHS 1272 if (N0C && !N1C) 1273 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1274 // fold (mul x, 0) -> 0 1275 if (N1C && N1C->isNullValue()) 1276 return N1; 1277 // fold (mul x, -1) -> 0-x 1278 if (N1C && N1C->isAllOnesValue()) 1279 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1280 DAG.getConstant(0, VT), N0); 1281 // fold (mul x, (1 << c)) -> x << c 1282 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1283 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1284 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1285 getShiftAmountTy())); 1286 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1287 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1288 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1289 // FIXME: If the input is something that is easily negated (e.g. a 1290 // single-use add), we should put the negate there. 1291 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1292 DAG.getConstant(0, VT), 1293 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1294 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1295 } 1296 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1297 if (N1C && N0.getOpcode() == ISD::SHL && 1298 isa<ConstantSDNode>(N0.getOperand(1))) { 1299 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1300 N1, N0.getOperand(1)); 1301 AddToWorkList(C3.getNode()); 1302 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1303 N0.getOperand(0), C3); 1304 } 1305 1306 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1307 // use. 1308 { 1309 SDValue Sh(0,0), Y(0,0); 1310 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1311 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1312 N0.getNode()->hasOneUse()) { 1313 Sh = N0; Y = N1; 1314 } else if (N1.getOpcode() == ISD::SHL && 1315 isa<ConstantSDNode>(N1.getOperand(1)) && 1316 N1.getNode()->hasOneUse()) { 1317 Sh = N1; Y = N0; 1318 } 1319 1320 if (Sh.getNode()) { 1321 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1322 Sh.getOperand(0), Y); 1323 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1324 Mul, Sh.getOperand(1)); 1325 } 1326 } 1327 1328 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1329 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1330 isa<ConstantSDNode>(N0.getOperand(1))) 1331 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1332 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1333 N0.getOperand(0), N1), 1334 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1335 N0.getOperand(1), N1)); 1336 1337 // reassociate mul 1338 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1339 if (RMUL.getNode() != 0) 1340 return RMUL; 1341 1342 return SDValue(); 1343} 1344 1345SDValue DAGCombiner::visitSDIV(SDNode *N) { 1346 SDValue N0 = N->getOperand(0); 1347 SDValue N1 = N->getOperand(1); 1348 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1349 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1350 EVT VT = N->getValueType(0); 1351 1352 // fold vector ops 1353 if (VT.isVector()) { 1354 SDValue FoldedVOp = SimplifyVBinOp(N); 1355 if (FoldedVOp.getNode()) return FoldedVOp; 1356 } 1357 1358 // fold (sdiv c1, c2) -> c1/c2 1359 if (N0C && N1C && !N1C->isNullValue()) 1360 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1361 // fold (sdiv X, 1) -> X 1362 if (N1C && N1C->getSExtValue() == 1LL) 1363 return N0; 1364 // fold (sdiv X, -1) -> 0-X 1365 if (N1C && N1C->isAllOnesValue()) 1366 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1367 DAG.getConstant(0, VT), N0); 1368 // If we know the sign bits of both operands are zero, strength reduce to a 1369 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1370 if (!VT.isVector()) { 1371 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1372 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1373 N0, N1); 1374 } 1375 // fold (sdiv X, pow2) -> simple ops after legalize 1376 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1377 (isPowerOf2_64(N1C->getSExtValue()) || 1378 isPowerOf2_64(-N1C->getSExtValue()))) { 1379 // If dividing by powers of two is cheap, then don't perform the following 1380 // fold. 1381 if (TLI.isPow2DivCheap()) 1382 return SDValue(); 1383 1384 int64_t pow2 = N1C->getSExtValue(); 1385 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1386 unsigned lg2 = Log2_64(abs2); 1387 1388 // Splat the sign bit into the register 1389 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1390 DAG.getConstant(VT.getSizeInBits()-1, 1391 getShiftAmountTy())); 1392 AddToWorkList(SGN.getNode()); 1393 1394 // Add (N0 < 0) ? abs2 - 1 : 0; 1395 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1396 DAG.getConstant(VT.getSizeInBits() - lg2, 1397 getShiftAmountTy())); 1398 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1399 AddToWorkList(SRL.getNode()); 1400 AddToWorkList(ADD.getNode()); // Divide by pow2 1401 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1402 DAG.getConstant(lg2, getShiftAmountTy())); 1403 1404 // If we're dividing by a positive value, we're done. Otherwise, we must 1405 // negate the result. 1406 if (pow2 > 0) 1407 return SRA; 1408 1409 AddToWorkList(SRA.getNode()); 1410 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1411 DAG.getConstant(0, VT), SRA); 1412 } 1413 1414 // if integer divide is expensive and we satisfy the requirements, emit an 1415 // alternate sequence. 1416 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1417 !TLI.isIntDivCheap()) { 1418 SDValue Op = BuildSDIV(N); 1419 if (Op.getNode()) return Op; 1420 } 1421 1422 // undef / X -> 0 1423 if (N0.getOpcode() == ISD::UNDEF) 1424 return DAG.getConstant(0, VT); 1425 // X / undef -> undef 1426 if (N1.getOpcode() == ISD::UNDEF) 1427 return N1; 1428 1429 return SDValue(); 1430} 1431 1432SDValue DAGCombiner::visitUDIV(SDNode *N) { 1433 SDValue N0 = N->getOperand(0); 1434 SDValue N1 = N->getOperand(1); 1435 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1436 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1437 EVT VT = N->getValueType(0); 1438 1439 // fold vector ops 1440 if (VT.isVector()) { 1441 SDValue FoldedVOp = SimplifyVBinOp(N); 1442 if (FoldedVOp.getNode()) return FoldedVOp; 1443 } 1444 1445 // fold (udiv c1, c2) -> c1/c2 1446 if (N0C && N1C && !N1C->isNullValue()) 1447 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1448 // fold (udiv x, (1 << c)) -> x >>u c 1449 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1450 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1451 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1452 getShiftAmountTy())); 1453 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1454 if (N1.getOpcode() == ISD::SHL) { 1455 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1456 if (SHC->getAPIntValue().isPowerOf2()) { 1457 EVT ADDVT = N1.getOperand(1).getValueType(); 1458 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1459 N1.getOperand(1), 1460 DAG.getConstant(SHC->getAPIntValue() 1461 .logBase2(), 1462 ADDVT)); 1463 AddToWorkList(Add.getNode()); 1464 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1465 } 1466 } 1467 } 1468 // fold (udiv x, c) -> alternate 1469 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1470 SDValue Op = BuildUDIV(N); 1471 if (Op.getNode()) return Op; 1472 } 1473 1474 // undef / X -> 0 1475 if (N0.getOpcode() == ISD::UNDEF) 1476 return DAG.getConstant(0, VT); 1477 // X / undef -> undef 1478 if (N1.getOpcode() == ISD::UNDEF) 1479 return N1; 1480 1481 return SDValue(); 1482} 1483 1484SDValue DAGCombiner::visitSREM(SDNode *N) { 1485 SDValue N0 = N->getOperand(0); 1486 SDValue N1 = N->getOperand(1); 1487 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1488 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1489 EVT VT = N->getValueType(0); 1490 1491 // fold (srem c1, c2) -> c1%c2 1492 if (N0C && N1C && !N1C->isNullValue()) 1493 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1494 // If we know the sign bits of both operands are zero, strength reduce to a 1495 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1496 if (!VT.isVector()) { 1497 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1498 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1499 } 1500 1501 // If X/C can be simplified by the division-by-constant logic, lower 1502 // X%C to the equivalent of X-X/C*C. 1503 if (N1C && !N1C->isNullValue()) { 1504 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1505 AddToWorkList(Div.getNode()); 1506 SDValue OptimizedDiv = combine(Div.getNode()); 1507 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1508 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1509 OptimizedDiv, N1); 1510 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1511 AddToWorkList(Mul.getNode()); 1512 return Sub; 1513 } 1514 } 1515 1516 // undef % X -> 0 1517 if (N0.getOpcode() == ISD::UNDEF) 1518 return DAG.getConstant(0, VT); 1519 // X % undef -> undef 1520 if (N1.getOpcode() == ISD::UNDEF) 1521 return N1; 1522 1523 return SDValue(); 1524} 1525 1526SDValue DAGCombiner::visitUREM(SDNode *N) { 1527 SDValue N0 = N->getOperand(0); 1528 SDValue N1 = N->getOperand(1); 1529 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1531 EVT VT = N->getValueType(0); 1532 1533 // fold (urem c1, c2) -> c1%c2 1534 if (N0C && N1C && !N1C->isNullValue()) 1535 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1536 // fold (urem x, pow2) -> (and x, pow2-1) 1537 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1538 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1539 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1540 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1541 if (N1.getOpcode() == ISD::SHL) { 1542 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1543 if (SHC->getAPIntValue().isPowerOf2()) { 1544 SDValue Add = 1545 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1546 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1547 VT)); 1548 AddToWorkList(Add.getNode()); 1549 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1550 } 1551 } 1552 } 1553 1554 // If X/C can be simplified by the division-by-constant logic, lower 1555 // X%C to the equivalent of X-X/C*C. 1556 if (N1C && !N1C->isNullValue()) { 1557 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1558 AddToWorkList(Div.getNode()); 1559 SDValue OptimizedDiv = combine(Div.getNode()); 1560 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1561 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1562 OptimizedDiv, N1); 1563 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1564 AddToWorkList(Mul.getNode()); 1565 return Sub; 1566 } 1567 } 1568 1569 // undef % X -> 0 1570 if (N0.getOpcode() == ISD::UNDEF) 1571 return DAG.getConstant(0, VT); 1572 // X % undef -> undef 1573 if (N1.getOpcode() == ISD::UNDEF) 1574 return N1; 1575 1576 return SDValue(); 1577} 1578 1579SDValue DAGCombiner::visitMULHS(SDNode *N) { 1580 SDValue N0 = N->getOperand(0); 1581 SDValue N1 = N->getOperand(1); 1582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1583 EVT VT = N->getValueType(0); 1584 1585 // fold (mulhs x, 0) -> 0 1586 if (N1C && N1C->isNullValue()) 1587 return N1; 1588 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1589 if (N1C && N1C->getAPIntValue() == 1) 1590 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1591 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1592 getShiftAmountTy())); 1593 // fold (mulhs x, undef) -> 0 1594 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1595 return DAG.getConstant(0, VT); 1596 1597 return SDValue(); 1598} 1599 1600SDValue DAGCombiner::visitMULHU(SDNode *N) { 1601 SDValue N0 = N->getOperand(0); 1602 SDValue N1 = N->getOperand(1); 1603 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1604 EVT VT = N->getValueType(0); 1605 1606 // fold (mulhu x, 0) -> 0 1607 if (N1C && N1C->isNullValue()) 1608 return N1; 1609 // fold (mulhu x, 1) -> 0 1610 if (N1C && N1C->getAPIntValue() == 1) 1611 return DAG.getConstant(0, N0.getValueType()); 1612 // fold (mulhu x, undef) -> 0 1613 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1614 return DAG.getConstant(0, VT); 1615 1616 return SDValue(); 1617} 1618 1619/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1620/// compute two values. LoOp and HiOp give the opcodes for the two computations 1621/// that are being performed. Return true if a simplification was made. 1622/// 1623SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1624 unsigned HiOp) { 1625 // If the high half is not needed, just compute the low half. 1626 bool HiExists = N->hasAnyUseOfValue(1); 1627 if (!HiExists && 1628 (!LegalOperations || 1629 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1630 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1631 N->op_begin(), N->getNumOperands()); 1632 return CombineTo(N, Res, Res); 1633 } 1634 1635 // If the low half is not needed, just compute the high half. 1636 bool LoExists = N->hasAnyUseOfValue(0); 1637 if (!LoExists && 1638 (!LegalOperations || 1639 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1640 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1641 N->op_begin(), N->getNumOperands()); 1642 return CombineTo(N, Res, Res); 1643 } 1644 1645 // If both halves are used, return as it is. 1646 if (LoExists && HiExists) 1647 return SDValue(); 1648 1649 // If the two computed results can be simplified separately, separate them. 1650 if (LoExists) { 1651 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1652 N->op_begin(), N->getNumOperands()); 1653 AddToWorkList(Lo.getNode()); 1654 SDValue LoOpt = combine(Lo.getNode()); 1655 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1656 (!LegalOperations || 1657 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1658 return CombineTo(N, LoOpt, LoOpt); 1659 } 1660 1661 if (HiExists) { 1662 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1663 N->op_begin(), N->getNumOperands()); 1664 AddToWorkList(Hi.getNode()); 1665 SDValue HiOpt = combine(Hi.getNode()); 1666 if (HiOpt.getNode() && HiOpt != Hi && 1667 (!LegalOperations || 1668 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1669 return CombineTo(N, HiOpt, HiOpt); 1670 } 1671 1672 return SDValue(); 1673} 1674 1675SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1676 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1677 if (Res.getNode()) return Res; 1678 1679 return SDValue(); 1680} 1681 1682SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1683 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1684 if (Res.getNode()) return Res; 1685 1686 return SDValue(); 1687} 1688 1689SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1690 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1691 if (Res.getNode()) return Res; 1692 1693 return SDValue(); 1694} 1695 1696SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1697 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1698 if (Res.getNode()) return Res; 1699 1700 return SDValue(); 1701} 1702 1703/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1704/// two operands of the same opcode, try to simplify it. 1705SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1706 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1707 EVT VT = N0.getValueType(); 1708 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1709 1710 // Bail early if none of these transforms apply. 1711 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 1712 1713 // For each of OP in AND/OR/XOR: 1714 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1715 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1716 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1717 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1718 // 1719 // do not sink logical op inside of a vector extend, since it may combine 1720 // into a vsetcc. 1721 EVT Op0VT = N0.getOperand(0).getValueType(); 1722 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 1723 N0.getOpcode() == ISD::ANY_EXTEND || 1724 N0.getOpcode() == ISD::SIGN_EXTEND || 1725 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) && 1726 !VT.isVector() && 1727 Op0VT == N1.getOperand(0).getValueType() && 1728 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 1729 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1730 N0.getOperand(0).getValueType(), 1731 N0.getOperand(0), N1.getOperand(0)); 1732 AddToWorkList(ORNode.getNode()); 1733 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1734 } 1735 1736 // For each of OP in SHL/SRL/SRA/AND... 1737 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1738 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1739 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1740 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1741 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1742 N0.getOperand(1) == N1.getOperand(1)) { 1743 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1744 N0.getOperand(0).getValueType(), 1745 N0.getOperand(0), N1.getOperand(0)); 1746 AddToWorkList(ORNode.getNode()); 1747 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1748 ORNode, N0.getOperand(1)); 1749 } 1750 1751 return SDValue(); 1752} 1753 1754SDValue DAGCombiner::visitAND(SDNode *N) { 1755 SDValue N0 = N->getOperand(0); 1756 SDValue N1 = N->getOperand(1); 1757 SDValue LL, LR, RL, RR, CC0, CC1; 1758 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1759 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1760 EVT VT = N1.getValueType(); 1761 unsigned BitWidth = VT.getSizeInBits(); 1762 1763 // fold vector ops 1764 if (VT.isVector()) { 1765 SDValue FoldedVOp = SimplifyVBinOp(N); 1766 if (FoldedVOp.getNode()) return FoldedVOp; 1767 } 1768 1769 // fold (and x, undef) -> 0 1770 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1771 return DAG.getConstant(0, VT); 1772 // fold (and c1, c2) -> c1&c2 1773 if (N0C && N1C) 1774 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1775 // canonicalize constant to RHS 1776 if (N0C && !N1C) 1777 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1778 // fold (and x, -1) -> x 1779 if (N1C && N1C->isAllOnesValue()) 1780 return N0; 1781 // if (and x, c) is known to be zero, return 0 1782 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1783 APInt::getAllOnesValue(BitWidth))) 1784 return DAG.getConstant(0, VT); 1785 // reassociate and 1786 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1787 if (RAND.getNode() != 0) 1788 return RAND; 1789 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1790 if (N1C && N0.getOpcode() == ISD::OR) 1791 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1792 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1793 return N1; 1794 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1795 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1796 SDValue N0Op0 = N0.getOperand(0); 1797 APInt Mask = ~N1C->getAPIntValue(); 1798 Mask.trunc(N0Op0.getValueSizeInBits()); 1799 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1800 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1801 N0.getValueType(), N0Op0); 1802 1803 // Replace uses of the AND with uses of the Zero extend node. 1804 CombineTo(N, Zext); 1805 1806 // We actually want to replace all uses of the any_extend with the 1807 // zero_extend, to avoid duplicating things. This will later cause this 1808 // AND to be folded. 1809 CombineTo(N0.getNode(), Zext); 1810 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1811 } 1812 } 1813 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1814 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1815 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1816 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1817 1818 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1819 LL.getValueType().isInteger()) { 1820 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1821 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1822 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1823 LR.getValueType(), LL, RL); 1824 AddToWorkList(ORNode.getNode()); 1825 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1826 } 1827 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1828 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1829 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1830 LR.getValueType(), LL, RL); 1831 AddToWorkList(ANDNode.getNode()); 1832 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1833 } 1834 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1835 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1836 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1837 LR.getValueType(), LL, RL); 1838 AddToWorkList(ORNode.getNode()); 1839 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1840 } 1841 } 1842 // canonicalize equivalent to ll == rl 1843 if (LL == RR && LR == RL) { 1844 Op1 = ISD::getSetCCSwappedOperands(Op1); 1845 std::swap(RL, RR); 1846 } 1847 if (LL == RL && LR == RR) { 1848 bool isInteger = LL.getValueType().isInteger(); 1849 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1850 if (Result != ISD::SETCC_INVALID && 1851 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1852 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1853 LL, LR, Result); 1854 } 1855 } 1856 1857 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1858 if (N0.getOpcode() == N1.getOpcode()) { 1859 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1860 if (Tmp.getNode()) return Tmp; 1861 } 1862 1863 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1864 // fold (and (sra)) -> (and (srl)) when possible. 1865 if (!VT.isVector() && 1866 SimplifyDemandedBits(SDValue(N, 0))) 1867 return SDValue(N, 0); 1868 1869 // fold (zext_inreg (extload x)) -> (zextload x) 1870 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1871 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1872 EVT MemVT = LN0->getMemoryVT(); 1873 // If we zero all the possible extended bits, then we can turn this into 1874 // a zextload if we are running before legalize or the operation is legal. 1875 unsigned BitWidth = N1.getValueSizeInBits(); 1876 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1877 BitWidth - MemVT.getSizeInBits())) && 1878 ((!LegalOperations && !LN0->isVolatile()) || 1879 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1880 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1881 LN0->getChain(), LN0->getBasePtr(), 1882 LN0->getSrcValue(), 1883 LN0->getSrcValueOffset(), MemVT, 1884 LN0->isVolatile(), LN0->isNonTemporal(), 1885 LN0->getAlignment()); 1886 AddToWorkList(N); 1887 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1888 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1889 } 1890 } 1891 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1892 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1893 N0.hasOneUse()) { 1894 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1895 EVT MemVT = LN0->getMemoryVT(); 1896 // If we zero all the possible extended bits, then we can turn this into 1897 // a zextload if we are running before legalize or the operation is legal. 1898 unsigned BitWidth = N1.getValueSizeInBits(); 1899 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1900 BitWidth - MemVT.getSizeInBits())) && 1901 ((!LegalOperations && !LN0->isVolatile()) || 1902 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1903 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1904 LN0->getChain(), 1905 LN0->getBasePtr(), LN0->getSrcValue(), 1906 LN0->getSrcValueOffset(), MemVT, 1907 LN0->isVolatile(), LN0->isNonTemporal(), 1908 LN0->getAlignment()); 1909 AddToWorkList(N); 1910 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1911 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1912 } 1913 } 1914 1915 // fold (and (load x), 255) -> (zextload x, i8) 1916 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1917 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 1918 if (N1C && (N0.getOpcode() == ISD::LOAD || 1919 (N0.getOpcode() == ISD::ANY_EXTEND && 1920 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 1921 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 1922 LoadSDNode *LN0 = HasAnyExt 1923 ? cast<LoadSDNode>(N0.getOperand(0)) 1924 : cast<LoadSDNode>(N0); 1925 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1926 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 1927 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1928 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 1929 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 1930 EVT LoadedVT = LN0->getMemoryVT(); 1931 1932 if (ExtVT == LoadedVT && 1933 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1934 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1935 1936 SDValue NewLoad = 1937 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1938 LN0->getChain(), LN0->getBasePtr(), 1939 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1940 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 1941 LN0->getAlignment()); 1942 AddToWorkList(N); 1943 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 1944 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1945 } 1946 1947 // Do not change the width of a volatile load. 1948 // Do not generate loads of non-round integer types since these can 1949 // be expensive (and would be wrong if the type is not byte sized). 1950 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 1951 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1952 EVT PtrType = LN0->getOperand(1).getValueType(); 1953 1954 unsigned Alignment = LN0->getAlignment(); 1955 SDValue NewPtr = LN0->getBasePtr(); 1956 1957 // For big endian targets, we need to add an offset to the pointer 1958 // to load the correct bytes. For little endian systems, we merely 1959 // need to read fewer bytes from the same pointer. 1960 if (TLI.isBigEndian()) { 1961 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 1962 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 1963 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1964 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1965 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1966 Alignment = MinAlign(Alignment, PtrOff); 1967 } 1968 1969 AddToWorkList(NewPtr.getNode()); 1970 1971 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1972 SDValue Load = 1973 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1974 LN0->getChain(), NewPtr, 1975 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1976 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 1977 Alignment); 1978 AddToWorkList(N); 1979 CombineTo(LN0, Load, Load.getValue(1)); 1980 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1981 } 1982 } 1983 } 1984 } 1985 1986 return SDValue(); 1987} 1988 1989SDValue DAGCombiner::visitOR(SDNode *N) { 1990 SDValue N0 = N->getOperand(0); 1991 SDValue N1 = N->getOperand(1); 1992 SDValue LL, LR, RL, RR, CC0, CC1; 1993 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1994 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1995 EVT VT = N1.getValueType(); 1996 1997 // fold vector ops 1998 if (VT.isVector()) { 1999 SDValue FoldedVOp = SimplifyVBinOp(N); 2000 if (FoldedVOp.getNode()) return FoldedVOp; 2001 } 2002 2003 // fold (or x, undef) -> -1 2004 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 2005 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2006 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2007 } 2008 // fold (or c1, c2) -> c1|c2 2009 if (N0C && N1C) 2010 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2011 // canonicalize constant to RHS 2012 if (N0C && !N1C) 2013 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2014 // fold (or x, 0) -> x 2015 if (N1C && N1C->isNullValue()) 2016 return N0; 2017 // fold (or x, -1) -> -1 2018 if (N1C && N1C->isAllOnesValue()) 2019 return N1; 2020 // fold (or x, c) -> c iff (x & ~c) == 0 2021 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2022 return N1; 2023 // reassociate or 2024 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2025 if (ROR.getNode() != 0) 2026 return ROR; 2027 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2028 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2029 isa<ConstantSDNode>(N0.getOperand(1))) { 2030 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2031 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2032 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2033 N0.getOperand(0), N1), 2034 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2035 } 2036 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2037 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2038 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2039 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2040 2041 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2042 LL.getValueType().isInteger()) { 2043 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2044 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2045 if (cast<ConstantSDNode>(LR)->isNullValue() && 2046 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2047 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2048 LR.getValueType(), LL, RL); 2049 AddToWorkList(ORNode.getNode()); 2050 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2051 } 2052 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2053 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2054 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2055 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2056 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2057 LR.getValueType(), LL, RL); 2058 AddToWorkList(ANDNode.getNode()); 2059 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2060 } 2061 } 2062 // canonicalize equivalent to ll == rl 2063 if (LL == RR && LR == RL) { 2064 Op1 = ISD::getSetCCSwappedOperands(Op1); 2065 std::swap(RL, RR); 2066 } 2067 if (LL == RL && LR == RR) { 2068 bool isInteger = LL.getValueType().isInteger(); 2069 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2070 if (Result != ISD::SETCC_INVALID && 2071 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2072 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2073 LL, LR, Result); 2074 } 2075 } 2076 2077 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2078 if (N0.getOpcode() == N1.getOpcode()) { 2079 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2080 if (Tmp.getNode()) return Tmp; 2081 } 2082 2083 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2084 if (N0.getOpcode() == ISD::AND && 2085 N1.getOpcode() == ISD::AND && 2086 N0.getOperand(1).getOpcode() == ISD::Constant && 2087 N1.getOperand(1).getOpcode() == ISD::Constant && 2088 // Don't increase # computations. 2089 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2090 // We can only do this xform if we know that bits from X that are set in C2 2091 // but not in C1 are already zero. Likewise for Y. 2092 const APInt &LHSMask = 2093 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2094 const APInt &RHSMask = 2095 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2096 2097 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2098 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2099 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2100 N0.getOperand(0), N1.getOperand(0)); 2101 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2102 DAG.getConstant(LHSMask | RHSMask, VT)); 2103 } 2104 } 2105 2106 // See if this is some rotate idiom. 2107 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2108 return SDValue(Rot, 0); 2109 2110 return SDValue(); 2111} 2112 2113/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2114static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2115 if (Op.getOpcode() == ISD::AND) { 2116 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2117 Mask = Op.getOperand(1); 2118 Op = Op.getOperand(0); 2119 } else { 2120 return false; 2121 } 2122 } 2123 2124 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2125 Shift = Op; 2126 return true; 2127 } 2128 2129 return false; 2130} 2131 2132// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2133// idioms for rotate, and if the target supports rotation instructions, generate 2134// a rot[lr]. 2135SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2136 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2137 EVT VT = LHS.getValueType(); 2138 if (!TLI.isTypeLegal(VT)) return 0; 2139 2140 // The target must have at least one rotate flavor. 2141 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2142 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2143 if (!HasROTL && !HasROTR) return 0; 2144 2145 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2146 SDValue LHSShift; // The shift. 2147 SDValue LHSMask; // AND value if any. 2148 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2149 return 0; // Not part of a rotate. 2150 2151 SDValue RHSShift; // The shift. 2152 SDValue RHSMask; // AND value if any. 2153 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2154 return 0; // Not part of a rotate. 2155 2156 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2157 return 0; // Not shifting the same value. 2158 2159 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2160 return 0; // Shifts must disagree. 2161 2162 // Canonicalize shl to left side in a shl/srl pair. 2163 if (RHSShift.getOpcode() == ISD::SHL) { 2164 std::swap(LHS, RHS); 2165 std::swap(LHSShift, RHSShift); 2166 std::swap(LHSMask , RHSMask ); 2167 } 2168 2169 unsigned OpSizeInBits = VT.getSizeInBits(); 2170 SDValue LHSShiftArg = LHSShift.getOperand(0); 2171 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2172 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2173 2174 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2175 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2176 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2177 RHSShiftAmt.getOpcode() == ISD::Constant) { 2178 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2179 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2180 if ((LShVal + RShVal) != OpSizeInBits) 2181 return 0; 2182 2183 SDValue Rot; 2184 if (HasROTL) 2185 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2186 else 2187 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2188 2189 // If there is an AND of either shifted operand, apply it to the result. 2190 if (LHSMask.getNode() || RHSMask.getNode()) { 2191 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2192 2193 if (LHSMask.getNode()) { 2194 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2195 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2196 } 2197 if (RHSMask.getNode()) { 2198 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2199 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2200 } 2201 2202 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2203 } 2204 2205 return Rot.getNode(); 2206 } 2207 2208 // If there is a mask here, and we have a variable shift, we can't be sure 2209 // that we're masking out the right stuff. 2210 if (LHSMask.getNode() || RHSMask.getNode()) 2211 return 0; 2212 2213 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2214 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2215 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2216 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2217 if (ConstantSDNode *SUBC = 2218 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2219 if (SUBC->getAPIntValue() == OpSizeInBits) { 2220 if (HasROTL) 2221 return DAG.getNode(ISD::ROTL, DL, VT, 2222 LHSShiftArg, LHSShiftAmt).getNode(); 2223 else 2224 return DAG.getNode(ISD::ROTR, DL, VT, 2225 LHSShiftArg, RHSShiftAmt).getNode(); 2226 } 2227 } 2228 } 2229 2230 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2231 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2232 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2233 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2234 if (ConstantSDNode *SUBC = 2235 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2236 if (SUBC->getAPIntValue() == OpSizeInBits) { 2237 if (HasROTR) 2238 return DAG.getNode(ISD::ROTR, DL, VT, 2239 LHSShiftArg, RHSShiftAmt).getNode(); 2240 else 2241 return DAG.getNode(ISD::ROTL, DL, VT, 2242 LHSShiftArg, LHSShiftAmt).getNode(); 2243 } 2244 } 2245 } 2246 2247 // Look for sign/zext/any-extended or truncate cases: 2248 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2249 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2250 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2251 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2252 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2253 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2254 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2255 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2256 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2257 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2258 if (RExtOp0.getOpcode() == ISD::SUB && 2259 RExtOp0.getOperand(1) == LExtOp0) { 2260 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2261 // (rotl x, y) 2262 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2263 // (rotr x, (sub 32, y)) 2264 if (ConstantSDNode *SUBC = 2265 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2266 if (SUBC->getAPIntValue() == OpSizeInBits) { 2267 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2268 LHSShiftArg, 2269 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2270 } 2271 } 2272 } else if (LExtOp0.getOpcode() == ISD::SUB && 2273 RExtOp0 == LExtOp0.getOperand(1)) { 2274 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2275 // (rotr x, y) 2276 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2277 // (rotl x, (sub 32, y)) 2278 if (ConstantSDNode *SUBC = 2279 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2280 if (SUBC->getAPIntValue() == OpSizeInBits) { 2281 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2282 LHSShiftArg, 2283 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2284 } 2285 } 2286 } 2287 } 2288 2289 return 0; 2290} 2291 2292SDValue DAGCombiner::visitXOR(SDNode *N) { 2293 SDValue N0 = N->getOperand(0); 2294 SDValue N1 = N->getOperand(1); 2295 SDValue LHS, RHS, CC; 2296 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2297 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2298 EVT VT = N0.getValueType(); 2299 2300 // fold vector ops 2301 if (VT.isVector()) { 2302 SDValue FoldedVOp = SimplifyVBinOp(N); 2303 if (FoldedVOp.getNode()) return FoldedVOp; 2304 } 2305 2306 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2307 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2308 return DAG.getConstant(0, VT); 2309 // fold (xor x, undef) -> undef 2310 if (N0.getOpcode() == ISD::UNDEF) 2311 return N0; 2312 if (N1.getOpcode() == ISD::UNDEF) 2313 return N1; 2314 // fold (xor c1, c2) -> c1^c2 2315 if (N0C && N1C) 2316 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2317 // canonicalize constant to RHS 2318 if (N0C && !N1C) 2319 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2320 // fold (xor x, 0) -> x 2321 if (N1C && N1C->isNullValue()) 2322 return N0; 2323 // reassociate xor 2324 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2325 if (RXOR.getNode() != 0) 2326 return RXOR; 2327 2328 // fold !(x cc y) -> (x !cc y) 2329 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2330 bool isInt = LHS.getValueType().isInteger(); 2331 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2332 isInt); 2333 2334 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2335 switch (N0.getOpcode()) { 2336 default: 2337 llvm_unreachable("Unhandled SetCC Equivalent!"); 2338 case ISD::SETCC: 2339 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2340 case ISD::SELECT_CC: 2341 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2342 N0.getOperand(3), NotCC); 2343 } 2344 } 2345 } 2346 2347 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2348 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2349 N0.getNode()->hasOneUse() && 2350 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2351 SDValue V = N0.getOperand(0); 2352 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2353 DAG.getConstant(1, V.getValueType())); 2354 AddToWorkList(V.getNode()); 2355 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2356 } 2357 2358 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2359 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2360 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2361 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2362 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2363 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2364 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2365 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2366 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2367 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2368 } 2369 } 2370 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2371 if (N1C && N1C->isAllOnesValue() && 2372 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2373 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2374 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2375 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2376 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2377 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2378 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2379 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2380 } 2381 } 2382 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2383 if (N1C && N0.getOpcode() == ISD::XOR) { 2384 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2385 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2386 if (N00C) 2387 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2388 DAG.getConstant(N1C->getAPIntValue() ^ 2389 N00C->getAPIntValue(), VT)); 2390 if (N01C) 2391 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2392 DAG.getConstant(N1C->getAPIntValue() ^ 2393 N01C->getAPIntValue(), VT)); 2394 } 2395 // fold (xor x, x) -> 0 2396 if (N0 == N1) { 2397 if (!VT.isVector()) { 2398 return DAG.getConstant(0, VT); 2399 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2400 // Produce a vector of zeros. 2401 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2402 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2403 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2404 &Ops[0], Ops.size()); 2405 } 2406 } 2407 2408 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2409 if (N0.getOpcode() == N1.getOpcode()) { 2410 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2411 if (Tmp.getNode()) return Tmp; 2412 } 2413 2414 // Simplify the expression using non-local knowledge. 2415 if (!VT.isVector() && 2416 SimplifyDemandedBits(SDValue(N, 0))) 2417 return SDValue(N, 0); 2418 2419 return SDValue(); 2420} 2421 2422/// visitShiftByConstant - Handle transforms common to the three shifts, when 2423/// the shift amount is a constant. 2424SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2425 SDNode *LHS = N->getOperand(0).getNode(); 2426 if (!LHS->hasOneUse()) return SDValue(); 2427 2428 // We want to pull some binops through shifts, so that we have (and (shift)) 2429 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2430 // thing happens with address calculations, so it's important to canonicalize 2431 // it. 2432 bool HighBitSet = false; // Can we transform this if the high bit is set? 2433 2434 switch (LHS->getOpcode()) { 2435 default: return SDValue(); 2436 case ISD::OR: 2437 case ISD::XOR: 2438 HighBitSet = false; // We can only transform sra if the high bit is clear. 2439 break; 2440 case ISD::AND: 2441 HighBitSet = true; // We can only transform sra if the high bit is set. 2442 break; 2443 case ISD::ADD: 2444 if (N->getOpcode() != ISD::SHL) 2445 return SDValue(); // only shl(add) not sr[al](add). 2446 HighBitSet = false; // We can only transform sra if the high bit is clear. 2447 break; 2448 } 2449 2450 // We require the RHS of the binop to be a constant as well. 2451 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2452 if (!BinOpCst) return SDValue(); 2453 2454 // FIXME: disable this unless the input to the binop is a shift by a constant. 2455 // If it is not a shift, it pessimizes some common cases like: 2456 // 2457 // void foo(int *X, int i) { X[i & 1235] = 1; } 2458 // int bar(int *X, int i) { return X[i & 255]; } 2459 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2460 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2461 BinOpLHSVal->getOpcode() != ISD::SRA && 2462 BinOpLHSVal->getOpcode() != ISD::SRL) || 2463 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2464 return SDValue(); 2465 2466 EVT VT = N->getValueType(0); 2467 2468 // If this is a signed shift right, and the high bit is modified by the 2469 // logical operation, do not perform the transformation. The highBitSet 2470 // boolean indicates the value of the high bit of the constant which would 2471 // cause it to be modified for this operation. 2472 if (N->getOpcode() == ISD::SRA) { 2473 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2474 if (BinOpRHSSignSet != HighBitSet) 2475 return SDValue(); 2476 } 2477 2478 // Fold the constants, shifting the binop RHS by the shift amount. 2479 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2480 N->getValueType(0), 2481 LHS->getOperand(1), N->getOperand(1)); 2482 2483 // Create the new shift. 2484 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2485 VT, LHS->getOperand(0), N->getOperand(1)); 2486 2487 // Create the new binop. 2488 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2489} 2490 2491SDValue DAGCombiner::visitSHL(SDNode *N) { 2492 SDValue N0 = N->getOperand(0); 2493 SDValue N1 = N->getOperand(1); 2494 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2495 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2496 EVT VT = N0.getValueType(); 2497 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2498 2499 // fold (shl c1, c2) -> c1<<c2 2500 if (N0C && N1C) 2501 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2502 // fold (shl 0, x) -> 0 2503 if (N0C && N0C->isNullValue()) 2504 return N0; 2505 // fold (shl x, c >= size(x)) -> undef 2506 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2507 return DAG.getUNDEF(VT); 2508 // fold (shl x, 0) -> x 2509 if (N1C && N1C->isNullValue()) 2510 return N0; 2511 // if (shl x, c) is known to be zero, return 0 2512 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2513 APInt::getAllOnesValue(OpSizeInBits))) 2514 return DAG.getConstant(0, VT); 2515 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2516 if (N1.getOpcode() == ISD::TRUNCATE && 2517 N1.getOperand(0).getOpcode() == ISD::AND && 2518 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2519 SDValue N101 = N1.getOperand(0).getOperand(1); 2520 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2521 EVT TruncVT = N1.getValueType(); 2522 SDValue N100 = N1.getOperand(0).getOperand(0); 2523 APInt TruncC = N101C->getAPIntValue(); 2524 TruncC.trunc(TruncVT.getSizeInBits()); 2525 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2526 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2527 DAG.getNode(ISD::TRUNCATE, 2528 N->getDebugLoc(), 2529 TruncVT, N100), 2530 DAG.getConstant(TruncC, TruncVT))); 2531 } 2532 } 2533 2534 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2535 return SDValue(N, 0); 2536 2537 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2538 if (N1C && N0.getOpcode() == ISD::SHL && 2539 N0.getOperand(1).getOpcode() == ISD::Constant) { 2540 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2541 uint64_t c2 = N1C->getZExtValue(); 2542 if (c1 + c2 > OpSizeInBits) 2543 return DAG.getConstant(0, VT); 2544 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2545 DAG.getConstant(c1 + c2, N1.getValueType())); 2546 } 2547 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2548 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2549 if (N1C && N0.getOpcode() == ISD::SRL && 2550 N0.getOperand(1).getOpcode() == ISD::Constant) { 2551 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2552 if (c1 < VT.getSizeInBits()) { 2553 uint64_t c2 = N1C->getZExtValue(); 2554 SDValue HiBitsMask = 2555 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2556 VT.getSizeInBits() - c1), 2557 VT); 2558 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2559 N0.getOperand(0), 2560 HiBitsMask); 2561 if (c2 > c1) 2562 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2563 DAG.getConstant(c2-c1, N1.getValueType())); 2564 else 2565 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2566 DAG.getConstant(c1-c2, N1.getValueType())); 2567 } 2568 } 2569 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2570 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2571 SDValue HiBitsMask = 2572 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2573 VT.getSizeInBits() - 2574 N1C->getZExtValue()), 2575 VT); 2576 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2577 HiBitsMask); 2578 } 2579 2580 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2581} 2582 2583SDValue DAGCombiner::visitSRA(SDNode *N) { 2584 SDValue N0 = N->getOperand(0); 2585 SDValue N1 = N->getOperand(1); 2586 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2587 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2588 EVT VT = N0.getValueType(); 2589 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2590 2591 // fold (sra c1, c2) -> (sra c1, c2) 2592 if (N0C && N1C) 2593 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2594 // fold (sra 0, x) -> 0 2595 if (N0C && N0C->isNullValue()) 2596 return N0; 2597 // fold (sra -1, x) -> -1 2598 if (N0C && N0C->isAllOnesValue()) 2599 return N0; 2600 // fold (sra x, (setge c, size(x))) -> undef 2601 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2602 return DAG.getUNDEF(VT); 2603 // fold (sra x, 0) -> x 2604 if (N1C && N1C->isNullValue()) 2605 return N0; 2606 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2607 // sext_inreg. 2608 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2609 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2610 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2611 if (VT.isVector()) 2612 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2613 ExtVT, VT.getVectorNumElements()); 2614 if ((!LegalOperations || 2615 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2616 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2617 N0.getOperand(0), DAG.getValueType(ExtVT)); 2618 } 2619 2620 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2621 if (N1C && N0.getOpcode() == ISD::SRA) { 2622 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2623 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2624 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2625 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2626 DAG.getConstant(Sum, N1C->getValueType(0))); 2627 } 2628 } 2629 2630 // fold (sra (shl X, m), (sub result_size, n)) 2631 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2632 // result_size - n != m. 2633 // If truncate is free for the target sext(shl) is likely to result in better 2634 // code. 2635 if (N0.getOpcode() == ISD::SHL) { 2636 // Get the two constanst of the shifts, CN0 = m, CN = n. 2637 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2638 if (N01C && N1C) { 2639 // Determine what the truncate's result bitsize and type would be. 2640 EVT TruncVT = 2641 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2642 // Determine the residual right-shift amount. 2643 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2644 2645 // If the shift is not a no-op (in which case this should be just a sign 2646 // extend already), the truncated to type is legal, sign_extend is legal 2647 // on that type, and the truncate to that type is both legal and free, 2648 // perform the transform. 2649 if ((ShiftAmt > 0) && 2650 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2651 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2652 TLI.isTruncateFree(VT, TruncVT)) { 2653 2654 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2655 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2656 N0.getOperand(0), Amt); 2657 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2658 Shift); 2659 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2660 N->getValueType(0), Trunc); 2661 } 2662 } 2663 } 2664 2665 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2666 if (N1.getOpcode() == ISD::TRUNCATE && 2667 N1.getOperand(0).getOpcode() == ISD::AND && 2668 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2669 SDValue N101 = N1.getOperand(0).getOperand(1); 2670 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2671 EVT TruncVT = N1.getValueType(); 2672 SDValue N100 = N1.getOperand(0).getOperand(0); 2673 APInt TruncC = N101C->getAPIntValue(); 2674 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 2675 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2676 DAG.getNode(ISD::AND, N->getDebugLoc(), 2677 TruncVT, 2678 DAG.getNode(ISD::TRUNCATE, 2679 N->getDebugLoc(), 2680 TruncVT, N100), 2681 DAG.getConstant(TruncC, TruncVT))); 2682 } 2683 } 2684 2685 // Simplify, based on bits shifted out of the LHS. 2686 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2687 return SDValue(N, 0); 2688 2689 2690 // If the sign bit is known to be zero, switch this to a SRL. 2691 if (DAG.SignBitIsZero(N0)) 2692 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2693 2694 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2695} 2696 2697SDValue DAGCombiner::visitSRL(SDNode *N) { 2698 SDValue N0 = N->getOperand(0); 2699 SDValue N1 = N->getOperand(1); 2700 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2701 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2702 EVT VT = N0.getValueType(); 2703 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2704 2705 // fold (srl c1, c2) -> c1 >>u c2 2706 if (N0C && N1C) 2707 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2708 // fold (srl 0, x) -> 0 2709 if (N0C && N0C->isNullValue()) 2710 return N0; 2711 // fold (srl x, c >= size(x)) -> undef 2712 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2713 return DAG.getUNDEF(VT); 2714 // fold (srl x, 0) -> x 2715 if (N1C && N1C->isNullValue()) 2716 return N0; 2717 // if (srl x, c) is known to be zero, return 0 2718 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2719 APInt::getAllOnesValue(OpSizeInBits))) 2720 return DAG.getConstant(0, VT); 2721 2722 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2723 if (N1C && N0.getOpcode() == ISD::SRL && 2724 N0.getOperand(1).getOpcode() == ISD::Constant) { 2725 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2726 uint64_t c2 = N1C->getZExtValue(); 2727 if (c1 + c2 > OpSizeInBits) 2728 return DAG.getConstant(0, VT); 2729 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2730 DAG.getConstant(c1 + c2, N1.getValueType())); 2731 } 2732 2733 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2734 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2735 // Shifting in all undef bits? 2736 EVT SmallVT = N0.getOperand(0).getValueType(); 2737 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2738 return DAG.getUNDEF(VT); 2739 2740 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2741 N0.getOperand(0), N1); 2742 AddToWorkList(SmallShift.getNode()); 2743 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2744 } 2745 2746 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2747 // bit, which is unmodified by sra. 2748 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2749 if (N0.getOpcode() == ISD::SRA) 2750 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2751 } 2752 2753 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2754 if (N1C && N0.getOpcode() == ISD::CTLZ && 2755 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2756 APInt KnownZero, KnownOne; 2757 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2758 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2759 2760 // If any of the input bits are KnownOne, then the input couldn't be all 2761 // zeros, thus the result of the srl will always be zero. 2762 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2763 2764 // If all of the bits input the to ctlz node are known to be zero, then 2765 // the result of the ctlz is "32" and the result of the shift is one. 2766 APInt UnknownBits = ~KnownZero & Mask; 2767 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2768 2769 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2770 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2771 // Okay, we know that only that the single bit specified by UnknownBits 2772 // could be set on input to the CTLZ node. If this bit is set, the SRL 2773 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2774 // to an SRL/XOR pair, which is likely to simplify more. 2775 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2776 SDValue Op = N0.getOperand(0); 2777 2778 if (ShAmt) { 2779 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2780 DAG.getConstant(ShAmt, getShiftAmountTy())); 2781 AddToWorkList(Op.getNode()); 2782 } 2783 2784 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2785 Op, DAG.getConstant(1, VT)); 2786 } 2787 } 2788 2789 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2790 if (N1.getOpcode() == ISD::TRUNCATE && 2791 N1.getOperand(0).getOpcode() == ISD::AND && 2792 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2793 SDValue N101 = N1.getOperand(0).getOperand(1); 2794 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2795 EVT TruncVT = N1.getValueType(); 2796 SDValue N100 = N1.getOperand(0).getOperand(0); 2797 APInt TruncC = N101C->getAPIntValue(); 2798 TruncC.trunc(TruncVT.getSizeInBits()); 2799 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2800 DAG.getNode(ISD::AND, N->getDebugLoc(), 2801 TruncVT, 2802 DAG.getNode(ISD::TRUNCATE, 2803 N->getDebugLoc(), 2804 TruncVT, N100), 2805 DAG.getConstant(TruncC, TruncVT))); 2806 } 2807 } 2808 2809 // fold operands of srl based on knowledge that the low bits are not 2810 // demanded. 2811 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2812 return SDValue(N, 0); 2813 2814 if (N1C) { 2815 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 2816 if (NewSRL.getNode()) 2817 return NewSRL; 2818 } 2819 2820 // Here is a common situation. We want to optimize: 2821 // 2822 // %a = ... 2823 // %b = and i32 %a, 2 2824 // %c = srl i32 %b, 1 2825 // brcond i32 %c ... 2826 // 2827 // into 2828 // 2829 // %a = ... 2830 // %b = and %a, 2 2831 // %c = setcc eq %b, 0 2832 // brcond %c ... 2833 // 2834 // However when after the source operand of SRL is optimized into AND, the SRL 2835 // itself may not be optimized further. Look for it and add the BRCOND into 2836 // the worklist. 2837 if (N->hasOneUse()) { 2838 SDNode *Use = *N->use_begin(); 2839 if (Use->getOpcode() == ISD::BRCOND) 2840 AddToWorkList(Use); 2841 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 2842 // Also look pass the truncate. 2843 Use = *Use->use_begin(); 2844 if (Use->getOpcode() == ISD::BRCOND) 2845 AddToWorkList(Use); 2846 } 2847 } 2848 2849 return SDValue(); 2850} 2851 2852SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2853 SDValue N0 = N->getOperand(0); 2854 EVT VT = N->getValueType(0); 2855 2856 // fold (ctlz c1) -> c2 2857 if (isa<ConstantSDNode>(N0)) 2858 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2859 return SDValue(); 2860} 2861 2862SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2863 SDValue N0 = N->getOperand(0); 2864 EVT VT = N->getValueType(0); 2865 2866 // fold (cttz c1) -> c2 2867 if (isa<ConstantSDNode>(N0)) 2868 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2869 return SDValue(); 2870} 2871 2872SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2873 SDValue N0 = N->getOperand(0); 2874 EVT VT = N->getValueType(0); 2875 2876 // fold (ctpop c1) -> c2 2877 if (isa<ConstantSDNode>(N0)) 2878 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2879 return SDValue(); 2880} 2881 2882SDValue DAGCombiner::visitSELECT(SDNode *N) { 2883 SDValue N0 = N->getOperand(0); 2884 SDValue N1 = N->getOperand(1); 2885 SDValue N2 = N->getOperand(2); 2886 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2887 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2888 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2889 EVT VT = N->getValueType(0); 2890 EVT VT0 = N0.getValueType(); 2891 2892 // fold (select C, X, X) -> X 2893 if (N1 == N2) 2894 return N1; 2895 // fold (select true, X, Y) -> X 2896 if (N0C && !N0C->isNullValue()) 2897 return N1; 2898 // fold (select false, X, Y) -> Y 2899 if (N0C && N0C->isNullValue()) 2900 return N2; 2901 // fold (select C, 1, X) -> (or C, X) 2902 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2903 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2904 // fold (select C, 0, 1) -> (xor C, 1) 2905 if (VT.isInteger() && 2906 (VT0 == MVT::i1 || 2907 (VT0.isInteger() && 2908 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2909 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2910 SDValue XORNode; 2911 if (VT == VT0) 2912 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2913 N0, DAG.getConstant(1, VT0)); 2914 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2915 N0, DAG.getConstant(1, VT0)); 2916 AddToWorkList(XORNode.getNode()); 2917 if (VT.bitsGT(VT0)) 2918 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2919 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2920 } 2921 // fold (select C, 0, X) -> (and (not C), X) 2922 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2923 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2924 AddToWorkList(NOTNode.getNode()); 2925 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2926 } 2927 // fold (select C, X, 1) -> (or (not C), X) 2928 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2929 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2930 AddToWorkList(NOTNode.getNode()); 2931 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2932 } 2933 // fold (select C, X, 0) -> (and C, X) 2934 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2935 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2936 // fold (select X, X, Y) -> (or X, Y) 2937 // fold (select X, 1, Y) -> (or X, Y) 2938 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2939 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2940 // fold (select X, Y, X) -> (and X, Y) 2941 // fold (select X, Y, 0) -> (and X, Y) 2942 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2943 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2944 2945 // If we can fold this based on the true/false value, do so. 2946 if (SimplifySelectOps(N, N1, N2)) 2947 return SDValue(N, 0); // Don't revisit N. 2948 2949 // fold selects based on a setcc into other things, such as min/max/abs 2950 if (N0.getOpcode() == ISD::SETCC) { 2951 // FIXME: 2952 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2953 // having to say they don't support SELECT_CC on every type the DAG knows 2954 // about, since there is no way to mark an opcode illegal at all value types 2955 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2956 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2957 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2958 N0.getOperand(0), N0.getOperand(1), 2959 N1, N2, N0.getOperand(2)); 2960 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2961 } 2962 2963 return SDValue(); 2964} 2965 2966SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2967 SDValue N0 = N->getOperand(0); 2968 SDValue N1 = N->getOperand(1); 2969 SDValue N2 = N->getOperand(2); 2970 SDValue N3 = N->getOperand(3); 2971 SDValue N4 = N->getOperand(4); 2972 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2973 2974 // fold select_cc lhs, rhs, x, x, cc -> x 2975 if (N2 == N3) 2976 return N2; 2977 2978 // Determine if the condition we're dealing with is constant 2979 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2980 N0, N1, CC, N->getDebugLoc(), false); 2981 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2982 2983 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2984 if (!SCCC->isNullValue()) 2985 return N2; // cond always true -> true val 2986 else 2987 return N3; // cond always false -> false val 2988 } 2989 2990 // Fold to a simpler select_cc 2991 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2992 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2993 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2994 SCC.getOperand(2)); 2995 2996 // If we can fold this based on the true/false value, do so. 2997 if (SimplifySelectOps(N, N2, N3)) 2998 return SDValue(N, 0); // Don't revisit N. 2999 3000 // fold select_cc into other things, such as min/max/abs 3001 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3002} 3003 3004SDValue DAGCombiner::visitSETCC(SDNode *N) { 3005 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3006 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3007 N->getDebugLoc()); 3008} 3009 3010// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3011// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3012// transformation. Returns true if extension are possible and the above 3013// mentioned transformation is profitable. 3014static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3015 unsigned ExtOpc, 3016 SmallVector<SDNode*, 4> &ExtendNodes, 3017 const TargetLowering &TLI) { 3018 bool HasCopyToRegUses = false; 3019 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3020 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3021 UE = N0.getNode()->use_end(); 3022 UI != UE; ++UI) { 3023 SDNode *User = *UI; 3024 if (User == N) 3025 continue; 3026 if (UI.getUse().getResNo() != N0.getResNo()) 3027 continue; 3028 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3029 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3030 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3031 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3032 // Sign bits will be lost after a zext. 3033 return false; 3034 bool Add = false; 3035 for (unsigned i = 0; i != 2; ++i) { 3036 SDValue UseOp = User->getOperand(i); 3037 if (UseOp == N0) 3038 continue; 3039 if (!isa<ConstantSDNode>(UseOp)) 3040 return false; 3041 Add = true; 3042 } 3043 if (Add) 3044 ExtendNodes.push_back(User); 3045 continue; 3046 } 3047 // If truncates aren't free and there are users we can't 3048 // extend, it isn't worthwhile. 3049 if (!isTruncFree) 3050 return false; 3051 // Remember if this value is live-out. 3052 if (User->getOpcode() == ISD::CopyToReg) 3053 HasCopyToRegUses = true; 3054 } 3055 3056 if (HasCopyToRegUses) { 3057 bool BothLiveOut = false; 3058 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3059 UI != UE; ++UI) { 3060 SDUse &Use = UI.getUse(); 3061 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3062 BothLiveOut = true; 3063 break; 3064 } 3065 } 3066 if (BothLiveOut) 3067 // Both unextended and extended values are live out. There had better be 3068 // good a reason for the transformation. 3069 return ExtendNodes.size(); 3070 } 3071 return true; 3072} 3073 3074SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3075 SDValue N0 = N->getOperand(0); 3076 EVT VT = N->getValueType(0); 3077 3078 // fold (sext c1) -> c1 3079 if (isa<ConstantSDNode>(N0)) 3080 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3081 3082 // fold (sext (sext x)) -> (sext x) 3083 // fold (sext (aext x)) -> (sext x) 3084 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3085 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3086 N0.getOperand(0)); 3087 3088 if (N0.getOpcode() == ISD::TRUNCATE) { 3089 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3090 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3091 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3092 if (NarrowLoad.getNode()) { 3093 if (NarrowLoad.getNode() != N0.getNode()) 3094 CombineTo(N0.getNode(), NarrowLoad); 3095 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3096 } 3097 3098 // See if the value being truncated is already sign extended. If so, just 3099 // eliminate the trunc/sext pair. 3100 SDValue Op = N0.getOperand(0); 3101 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3102 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3103 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3104 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3105 3106 if (OpBits == DestBits) { 3107 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3108 // bits, it is already ready. 3109 if (NumSignBits > DestBits-MidBits) 3110 return Op; 3111 } else if (OpBits < DestBits) { 3112 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3113 // bits, just sext from i32. 3114 if (NumSignBits > OpBits-MidBits) 3115 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3116 } else { 3117 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3118 // bits, just truncate to i32. 3119 if (NumSignBits > OpBits-MidBits) 3120 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3121 } 3122 3123 // fold (sext (truncate x)) -> (sextinreg x). 3124 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3125 N0.getValueType())) { 3126 if (OpBits < DestBits) 3127 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3128 else if (OpBits > DestBits) 3129 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3130 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3131 DAG.getValueType(N0.getValueType())); 3132 } 3133 } 3134 3135 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3136 if (ISD::isNON_EXTLoad(N0.getNode()) && 3137 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3138 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3139 bool DoXform = true; 3140 SmallVector<SDNode*, 4> SetCCs; 3141 if (!N0.hasOneUse()) 3142 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3143 if (DoXform) { 3144 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3145 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3146 LN0->getChain(), 3147 LN0->getBasePtr(), LN0->getSrcValue(), 3148 LN0->getSrcValueOffset(), 3149 N0.getValueType(), 3150 LN0->isVolatile(), LN0->isNonTemporal(), 3151 LN0->getAlignment()); 3152 CombineTo(N, ExtLoad); 3153 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3154 N0.getValueType(), ExtLoad); 3155 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3156 3157 // Extend SetCC uses if necessary. 3158 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3159 SDNode *SetCC = SetCCs[i]; 3160 SmallVector<SDValue, 4> Ops; 3161 3162 for (unsigned j = 0; j != 2; ++j) { 3163 SDValue SOp = SetCC->getOperand(j); 3164 if (SOp == Trunc) 3165 Ops.push_back(ExtLoad); 3166 else 3167 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3168 N->getDebugLoc(), VT, SOp)); 3169 } 3170 3171 Ops.push_back(SetCC->getOperand(2)); 3172 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3173 SetCC->getValueType(0), 3174 &Ops[0], Ops.size())); 3175 } 3176 3177 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3178 } 3179 } 3180 3181 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3182 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3183 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3184 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3185 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3186 EVT MemVT = LN0->getMemoryVT(); 3187 if ((!LegalOperations && !LN0->isVolatile()) || 3188 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3189 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3190 LN0->getChain(), 3191 LN0->getBasePtr(), LN0->getSrcValue(), 3192 LN0->getSrcValueOffset(), MemVT, 3193 LN0->isVolatile(), LN0->isNonTemporal(), 3194 LN0->getAlignment()); 3195 CombineTo(N, ExtLoad); 3196 CombineTo(N0.getNode(), 3197 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3198 N0.getValueType(), ExtLoad), 3199 ExtLoad.getValue(1)); 3200 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3201 } 3202 } 3203 3204 if (N0.getOpcode() == ISD::SETCC) { 3205 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3206 if (VT.isVector() && 3207 // We know that the # elements of the results is the same as the 3208 // # elements of the compare (and the # elements of the compare result 3209 // for that matter). Check to see that they are the same size. If so, 3210 // we know that the element size of the sext'd result matches the 3211 // element size of the compare operands. 3212 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3213 3214 // Only do this before legalize for now. 3215 !LegalOperations) { 3216 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3217 N0.getOperand(1), 3218 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3219 } 3220 3221 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3222 SDValue NegOne = 3223 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3224 SDValue SCC = 3225 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3226 NegOne, DAG.getConstant(0, VT), 3227 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3228 if (SCC.getNode()) return SCC; 3229 if (!LegalOperations || 3230 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3231 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3232 DAG.getSetCC(N->getDebugLoc(), 3233 TLI.getSetCCResultType(VT), 3234 N0.getOperand(0), N0.getOperand(1), 3235 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3236 NegOne, DAG.getConstant(0, VT)); 3237 } 3238 3239 3240 3241 // fold (sext x) -> (zext x) if the sign bit is known zero. 3242 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3243 DAG.SignBitIsZero(N0)) 3244 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3245 3246 return SDValue(); 3247} 3248 3249SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3250 SDValue N0 = N->getOperand(0); 3251 EVT VT = N->getValueType(0); 3252 3253 // fold (zext c1) -> c1 3254 if (isa<ConstantSDNode>(N0)) 3255 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3256 // fold (zext (zext x)) -> (zext x) 3257 // fold (zext (aext x)) -> (zext x) 3258 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3259 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3260 N0.getOperand(0)); 3261 3262 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3263 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3264 if (N0.getOpcode() == ISD::TRUNCATE) { 3265 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3266 if (NarrowLoad.getNode()) { 3267 if (NarrowLoad.getNode() != N0.getNode()) 3268 CombineTo(N0.getNode(), NarrowLoad); 3269 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3270 } 3271 } 3272 3273 // fold (zext (truncate x)) -> (and x, mask) 3274 if (N0.getOpcode() == ISD::TRUNCATE && 3275 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) && 3276 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(), 3277 N0.getValueType()) || 3278 !TLI.isZExtFree(N0.getValueType(), VT))) { 3279 SDValue Op = N0.getOperand(0); 3280 if (Op.getValueType().bitsLT(VT)) { 3281 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3282 } else if (Op.getValueType().bitsGT(VT)) { 3283 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3284 } 3285 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3286 N0.getValueType().getScalarType()); 3287 } 3288 3289 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3290 // if either of the casts is not free. 3291 if (N0.getOpcode() == ISD::AND && 3292 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3293 N0.getOperand(1).getOpcode() == ISD::Constant && 3294 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3295 N0.getValueType()) || 3296 !TLI.isZExtFree(N0.getValueType(), VT))) { 3297 SDValue X = N0.getOperand(0).getOperand(0); 3298 if (X.getValueType().bitsLT(VT)) { 3299 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3300 } else if (X.getValueType().bitsGT(VT)) { 3301 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3302 } 3303 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3304 Mask.zext(VT.getSizeInBits()); 3305 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3306 X, DAG.getConstant(Mask, VT)); 3307 } 3308 3309 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3310 if (ISD::isNON_EXTLoad(N0.getNode()) && 3311 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3312 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3313 bool DoXform = true; 3314 SmallVector<SDNode*, 4> SetCCs; 3315 if (!N0.hasOneUse()) 3316 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3317 if (DoXform) { 3318 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3319 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3320 LN0->getChain(), 3321 LN0->getBasePtr(), LN0->getSrcValue(), 3322 LN0->getSrcValueOffset(), 3323 N0.getValueType(), 3324 LN0->isVolatile(), LN0->isNonTemporal(), 3325 LN0->getAlignment()); 3326 CombineTo(N, ExtLoad); 3327 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3328 N0.getValueType(), ExtLoad); 3329 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3330 3331 // Extend SetCC uses if necessary. 3332 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3333 SDNode *SetCC = SetCCs[i]; 3334 SmallVector<SDValue, 4> Ops; 3335 3336 for (unsigned j = 0; j != 2; ++j) { 3337 SDValue SOp = SetCC->getOperand(j); 3338 if (SOp == Trunc) 3339 Ops.push_back(ExtLoad); 3340 else 3341 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3342 N->getDebugLoc(), VT, SOp)); 3343 } 3344 3345 Ops.push_back(SetCC->getOperand(2)); 3346 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3347 SetCC->getValueType(0), 3348 &Ops[0], Ops.size())); 3349 } 3350 3351 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3352 } 3353 } 3354 3355 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3356 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3357 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3358 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3359 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3360 EVT MemVT = LN0->getMemoryVT(); 3361 if ((!LegalOperations && !LN0->isVolatile()) || 3362 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3363 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3364 LN0->getChain(), 3365 LN0->getBasePtr(), LN0->getSrcValue(), 3366 LN0->getSrcValueOffset(), MemVT, 3367 LN0->isVolatile(), LN0->isNonTemporal(), 3368 LN0->getAlignment()); 3369 CombineTo(N, ExtLoad); 3370 CombineTo(N0.getNode(), 3371 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3372 ExtLoad), 3373 ExtLoad.getValue(1)); 3374 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3375 } 3376 } 3377 3378 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3379 if (N0.getOpcode() == ISD::SETCC) { 3380 SDValue SCC = 3381 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3382 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3383 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3384 if (SCC.getNode()) return SCC; 3385 } 3386 3387 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3388 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3389 isa<ConstantSDNode>(N0.getOperand(1)) && 3390 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3391 N0.hasOneUse()) { 3392 if (N0.getOpcode() == ISD::SHL) { 3393 // If the original shl may be shifting out bits, do not perform this 3394 // transformation. 3395 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3396 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3397 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3398 if (ShAmt > KnownZeroBits) 3399 return SDValue(); 3400 } 3401 DebugLoc dl = N->getDebugLoc(); 3402 return DAG.getNode(N0.getOpcode(), dl, VT, 3403 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3404 DAG.getNode(ISD::ZERO_EXTEND, dl, 3405 N0.getOperand(1).getValueType(), 3406 N0.getOperand(1))); 3407 } 3408 3409 return SDValue(); 3410} 3411 3412SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3413 SDValue N0 = N->getOperand(0); 3414 EVT VT = N->getValueType(0); 3415 3416 // fold (aext c1) -> c1 3417 if (isa<ConstantSDNode>(N0)) 3418 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3419 // fold (aext (aext x)) -> (aext x) 3420 // fold (aext (zext x)) -> (zext x) 3421 // fold (aext (sext x)) -> (sext x) 3422 if (N0.getOpcode() == ISD::ANY_EXTEND || 3423 N0.getOpcode() == ISD::ZERO_EXTEND || 3424 N0.getOpcode() == ISD::SIGN_EXTEND) 3425 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3426 3427 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3428 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3429 if (N0.getOpcode() == ISD::TRUNCATE) { 3430 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3431 if (NarrowLoad.getNode()) { 3432 if (NarrowLoad.getNode() != N0.getNode()) 3433 CombineTo(N0.getNode(), NarrowLoad); 3434 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3435 } 3436 } 3437 3438 // fold (aext (truncate x)) 3439 if (N0.getOpcode() == ISD::TRUNCATE) { 3440 SDValue TruncOp = N0.getOperand(0); 3441 if (TruncOp.getValueType() == VT) 3442 return TruncOp; // x iff x size == zext size. 3443 if (TruncOp.getValueType().bitsGT(VT)) 3444 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3445 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3446 } 3447 3448 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3449 // if the trunc is not free. 3450 if (N0.getOpcode() == ISD::AND && 3451 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3452 N0.getOperand(1).getOpcode() == ISD::Constant && 3453 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3454 N0.getValueType())) { 3455 SDValue X = N0.getOperand(0).getOperand(0); 3456 if (X.getValueType().bitsLT(VT)) { 3457 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3458 } else if (X.getValueType().bitsGT(VT)) { 3459 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3460 } 3461 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3462 Mask.zext(VT.getSizeInBits()); 3463 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3464 X, DAG.getConstant(Mask, VT)); 3465 } 3466 3467 // fold (aext (load x)) -> (aext (truncate (extload x))) 3468 if (ISD::isNON_EXTLoad(N0.getNode()) && 3469 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3470 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3471 bool DoXform = true; 3472 SmallVector<SDNode*, 4> SetCCs; 3473 if (!N0.hasOneUse()) 3474 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3475 if (DoXform) { 3476 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3477 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3478 LN0->getChain(), 3479 LN0->getBasePtr(), LN0->getSrcValue(), 3480 LN0->getSrcValueOffset(), 3481 N0.getValueType(), 3482 LN0->isVolatile(), LN0->isNonTemporal(), 3483 LN0->getAlignment()); 3484 CombineTo(N, ExtLoad); 3485 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3486 N0.getValueType(), ExtLoad); 3487 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3488 3489 // Extend SetCC uses if necessary. 3490 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3491 SDNode *SetCC = SetCCs[i]; 3492 SmallVector<SDValue, 4> Ops; 3493 3494 for (unsigned j = 0; j != 2; ++j) { 3495 SDValue SOp = SetCC->getOperand(j); 3496 if (SOp == Trunc) 3497 Ops.push_back(ExtLoad); 3498 else 3499 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3500 N->getDebugLoc(), VT, SOp)); 3501 } 3502 3503 Ops.push_back(SetCC->getOperand(2)); 3504 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3505 SetCC->getValueType(0), 3506 &Ops[0], Ops.size())); 3507 } 3508 3509 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3510 } 3511 } 3512 3513 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3514 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3515 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3516 if (N0.getOpcode() == ISD::LOAD && 3517 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3518 N0.hasOneUse()) { 3519 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3520 EVT MemVT = LN0->getMemoryVT(); 3521 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3522 VT, LN0->getChain(), LN0->getBasePtr(), 3523 LN0->getSrcValue(), 3524 LN0->getSrcValueOffset(), MemVT, 3525 LN0->isVolatile(), LN0->isNonTemporal(), 3526 LN0->getAlignment()); 3527 CombineTo(N, ExtLoad); 3528 CombineTo(N0.getNode(), 3529 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3530 N0.getValueType(), ExtLoad), 3531 ExtLoad.getValue(1)); 3532 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3533 } 3534 3535 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3536 if (N0.getOpcode() == ISD::SETCC) { 3537 SDValue SCC = 3538 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3539 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3540 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3541 if (SCC.getNode()) 3542 return SCC; 3543 } 3544 3545 return SDValue(); 3546} 3547 3548/// GetDemandedBits - See if the specified operand can be simplified with the 3549/// knowledge that only the bits specified by Mask are used. If so, return the 3550/// simpler operand, otherwise return a null SDValue. 3551SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3552 switch (V.getOpcode()) { 3553 default: break; 3554 case ISD::OR: 3555 case ISD::XOR: 3556 // If the LHS or RHS don't contribute bits to the or, drop them. 3557 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3558 return V.getOperand(1); 3559 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3560 return V.getOperand(0); 3561 break; 3562 case ISD::SRL: 3563 // Only look at single-use SRLs. 3564 if (!V.getNode()->hasOneUse()) 3565 break; 3566 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3567 // See if we can recursively simplify the LHS. 3568 unsigned Amt = RHSC->getZExtValue(); 3569 3570 // Watch out for shift count overflow though. 3571 if (Amt >= Mask.getBitWidth()) break; 3572 APInt NewMask = Mask << Amt; 3573 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3574 if (SimplifyLHS.getNode()) 3575 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3576 SimplifyLHS, V.getOperand(1)); 3577 } 3578 } 3579 return SDValue(); 3580} 3581 3582/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3583/// bits and then truncated to a narrower type and where N is a multiple 3584/// of number of bits of the narrower type, transform it to a narrower load 3585/// from address + N / num of bits of new type. If the result is to be 3586/// extended, also fold the extension to form a extending load. 3587SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3588 unsigned Opc = N->getOpcode(); 3589 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3590 SDValue N0 = N->getOperand(0); 3591 EVT VT = N->getValueType(0); 3592 EVT ExtVT = VT; 3593 3594 // This transformation isn't valid for vector loads. 3595 if (VT.isVector()) 3596 return SDValue(); 3597 3598 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 3599 // extended to VT. 3600 if (Opc == ISD::SIGN_EXTEND_INREG) { 3601 ExtType = ISD::SEXTLOAD; 3602 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3603 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 3604 return SDValue(); 3605 } 3606 3607 unsigned EVTBits = ExtVT.getSizeInBits(); 3608 unsigned ShAmt = 0; 3609 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 3610 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3611 ShAmt = N01->getZExtValue(); 3612 // Is the shift amount a multiple of size of VT? 3613 if ((ShAmt & (EVTBits-1)) == 0) { 3614 N0 = N0.getOperand(0); 3615 // Is the load width a multiple of size of VT? 3616 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 3617 return SDValue(); 3618 } 3619 } 3620 } 3621 3622 // Do not generate loads of non-round integer types since these can 3623 // be expensive (and would be wrong if the type is not byte sized). 3624 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 3625 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3626 // Do not change the width of a volatile load. 3627 !cast<LoadSDNode>(N0)->isVolatile()) { 3628 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3629 EVT PtrType = N0.getOperand(1).getValueType(); 3630 3631 // For big endian targets, we need to adjust the offset to the pointer to 3632 // load the correct bytes. 3633 if (TLI.isBigEndian()) { 3634 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3635 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 3636 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3637 } 3638 3639 uint64_t PtrOff = ShAmt / 8; 3640 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3641 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3642 PtrType, LN0->getBasePtr(), 3643 DAG.getConstant(PtrOff, PtrType)); 3644 AddToWorkList(NewPtr.getNode()); 3645 3646 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3647 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3648 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3649 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign) 3650 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3651 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3652 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 3653 NewAlign); 3654 3655 // Replace the old load's chain with the new load's chain. 3656 WorkListRemover DeadNodes(*this); 3657 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3658 &DeadNodes); 3659 3660 // Return the new loaded value. 3661 return Load; 3662 } 3663 3664 return SDValue(); 3665} 3666 3667SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3668 SDValue N0 = N->getOperand(0); 3669 SDValue N1 = N->getOperand(1); 3670 EVT VT = N->getValueType(0); 3671 EVT EVT = cast<VTSDNode>(N1)->getVT(); 3672 unsigned VTBits = VT.getScalarType().getSizeInBits(); 3673 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 3674 3675 // fold (sext_in_reg c1) -> c1 3676 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3677 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3678 3679 // If the input is already sign extended, just drop the extension. 3680 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 3681 return N0; 3682 3683 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3684 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3685 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3686 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3687 N0.getOperand(0), N1); 3688 } 3689 3690 // fold (sext_in_reg (sext x)) -> (sext x) 3691 // fold (sext_in_reg (aext x)) -> (sext x) 3692 // if x is small enough. 3693 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3694 SDValue N00 = N0.getOperand(0); 3695 if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits) 3696 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3697 } 3698 3699 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3700 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3701 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3702 3703 // fold operands of sext_in_reg based on knowledge that the top bits are not 3704 // demanded. 3705 if (SimplifyDemandedBits(SDValue(N, 0))) 3706 return SDValue(N, 0); 3707 3708 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3709 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3710 SDValue NarrowLoad = ReduceLoadWidth(N); 3711 if (NarrowLoad.getNode()) 3712 return NarrowLoad; 3713 3714 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3715 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3716 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3717 if (N0.getOpcode() == ISD::SRL) { 3718 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3719 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 3720 // We can turn this into an SRA iff the input to the SRL is already sign 3721 // extended enough. 3722 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3723 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3724 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3725 N0.getOperand(0), N0.getOperand(1)); 3726 } 3727 } 3728 3729 // fold (sext_inreg (extload x)) -> (sextload x) 3730 if (ISD::isEXTLoad(N0.getNode()) && 3731 ISD::isUNINDEXEDLoad(N0.getNode()) && 3732 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3733 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3734 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3735 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3736 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3737 LN0->getChain(), 3738 LN0->getBasePtr(), LN0->getSrcValue(), 3739 LN0->getSrcValueOffset(), EVT, 3740 LN0->isVolatile(), LN0->isNonTemporal(), 3741 LN0->getAlignment()); 3742 CombineTo(N, ExtLoad); 3743 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3744 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3745 } 3746 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3747 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3748 N0.hasOneUse() && 3749 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3750 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3751 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3752 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3753 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3754 LN0->getChain(), 3755 LN0->getBasePtr(), LN0->getSrcValue(), 3756 LN0->getSrcValueOffset(), EVT, 3757 LN0->isVolatile(), LN0->isNonTemporal(), 3758 LN0->getAlignment()); 3759 CombineTo(N, ExtLoad); 3760 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3761 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3762 } 3763 return SDValue(); 3764} 3765 3766SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3767 SDValue N0 = N->getOperand(0); 3768 EVT VT = N->getValueType(0); 3769 3770 // noop truncate 3771 if (N0.getValueType() == N->getValueType(0)) 3772 return N0; 3773 // fold (truncate c1) -> c1 3774 if (isa<ConstantSDNode>(N0)) 3775 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3776 // fold (truncate (truncate x)) -> (truncate x) 3777 if (N0.getOpcode() == ISD::TRUNCATE) 3778 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3779 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3780 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3781 N0.getOpcode() == ISD::ANY_EXTEND) { 3782 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3783 // if the source is smaller than the dest, we still need an extend 3784 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3785 N0.getOperand(0)); 3786 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3787 // if the source is larger than the dest, than we just need the truncate 3788 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3789 else 3790 // if the source and dest are the same type, we can drop both the extend 3791 // and the truncate. 3792 return N0.getOperand(0); 3793 } 3794 3795 // See if we can simplify the input to this truncate through knowledge that 3796 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3797 // -> trunc y 3798 SDValue Shorter = 3799 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3800 VT.getSizeInBits())); 3801 if (Shorter.getNode()) 3802 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3803 3804 // fold (truncate (load x)) -> (smaller load x) 3805 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3806 return ReduceLoadWidth(N); 3807} 3808 3809static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3810 SDValue Elt = N->getOperand(i); 3811 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3812 return Elt.getNode(); 3813 return Elt.getOperand(Elt.getResNo()).getNode(); 3814} 3815 3816/// CombineConsecutiveLoads - build_pair (load, load) -> load 3817/// if load locations are consecutive. 3818SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 3819 assert(N->getOpcode() == ISD::BUILD_PAIR); 3820 3821 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3822 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3823 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3824 return SDValue(); 3825 EVT LD1VT = LD1->getValueType(0); 3826 3827 if (ISD::isNON_EXTLoad(LD2) && 3828 LD2->hasOneUse() && 3829 // If both are volatile this would reduce the number of volatile loads. 3830 // If one is volatile it might be ok, but play conservative and bail out. 3831 !LD1->isVolatile() && 3832 !LD2->isVolatile() && 3833 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 3834 unsigned Align = LD1->getAlignment(); 3835 unsigned NewAlign = TLI.getTargetData()-> 3836 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3837 3838 if (NewAlign <= Align && 3839 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3840 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3841 LD1->getBasePtr(), LD1->getSrcValue(), 3842 LD1->getSrcValueOffset(), false, false, Align); 3843 } 3844 3845 return SDValue(); 3846} 3847 3848SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3849 SDValue N0 = N->getOperand(0); 3850 EVT VT = N->getValueType(0); 3851 3852 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3853 // Only do this before legalize, since afterward the target may be depending 3854 // on the bitconvert. 3855 // First check to see if this is all constant. 3856 if (!LegalTypes && 3857 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3858 VT.isVector()) { 3859 bool isSimple = true; 3860 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3861 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3862 N0.getOperand(i).getOpcode() != ISD::Constant && 3863 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3864 isSimple = false; 3865 break; 3866 } 3867 3868 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 3869 assert(!DestEltVT.isVector() && 3870 "Element type of vector ValueType must not be vector!"); 3871 if (isSimple) 3872 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3873 } 3874 3875 // If the input is a constant, let getNode fold it. 3876 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3877 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3878 if (Res.getNode() != N) { 3879 if (!LegalOperations || 3880 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 3881 return Res; 3882 3883 // Folding it resulted in an illegal node, and it's too late to 3884 // do that. Clean up the old node and forego the transformation. 3885 // Ideally this won't happen very often, because instcombine 3886 // and the earlier dagcombine runs (where illegal nodes are 3887 // permitted) should have folded most of them already. 3888 DAG.DeleteNode(Res.getNode()); 3889 } 3890 } 3891 3892 // (conv (conv x, t1), t2) -> (conv x, t2) 3893 if (N0.getOpcode() == ISD::BIT_CONVERT) 3894 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3895 N0.getOperand(0)); 3896 3897 // fold (conv (load x)) -> (load (conv*)x) 3898 // If the resultant load doesn't need a higher alignment than the original! 3899 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3900 // Do not change the width of a volatile load. 3901 !cast<LoadSDNode>(N0)->isVolatile() && 3902 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3903 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3904 unsigned Align = TLI.getTargetData()-> 3905 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3906 unsigned OrigAlign = LN0->getAlignment(); 3907 3908 if (Align <= OrigAlign) { 3909 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3910 LN0->getBasePtr(), 3911 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3912 LN0->isVolatile(), LN0->isNonTemporal(), 3913 OrigAlign); 3914 AddToWorkList(N); 3915 CombineTo(N0.getNode(), 3916 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3917 N0.getValueType(), Load), 3918 Load.getValue(1)); 3919 return Load; 3920 } 3921 } 3922 3923 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3924 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3925 // This often reduces constant pool loads. 3926 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3927 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3928 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3929 N0.getOperand(0)); 3930 AddToWorkList(NewConv.getNode()); 3931 3932 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3933 if (N0.getOpcode() == ISD::FNEG) 3934 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3935 NewConv, DAG.getConstant(SignBit, VT)); 3936 assert(N0.getOpcode() == ISD::FABS); 3937 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3938 NewConv, DAG.getConstant(~SignBit, VT)); 3939 } 3940 3941 // fold (bitconvert (fcopysign cst, x)) -> 3942 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3943 // Note that we don't handle (copysign x, cst) because this can always be 3944 // folded to an fneg or fabs. 3945 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3946 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3947 VT.isInteger() && !VT.isVector()) { 3948 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3949 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 3950 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3951 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3952 IntXVT, N0.getOperand(1)); 3953 AddToWorkList(X.getNode()); 3954 3955 // If X has a different width than the result/lhs, sext it or truncate it. 3956 unsigned VTWidth = VT.getSizeInBits(); 3957 if (OrigXWidth < VTWidth) { 3958 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3959 AddToWorkList(X.getNode()); 3960 } else if (OrigXWidth > VTWidth) { 3961 // To get the sign bit in the right place, we have to shift it right 3962 // before truncating. 3963 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3964 X.getValueType(), X, 3965 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3966 AddToWorkList(X.getNode()); 3967 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3968 AddToWorkList(X.getNode()); 3969 } 3970 3971 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3972 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3973 X, DAG.getConstant(SignBit, VT)); 3974 AddToWorkList(X.getNode()); 3975 3976 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3977 VT, N0.getOperand(0)); 3978 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3979 Cst, DAG.getConstant(~SignBit, VT)); 3980 AddToWorkList(Cst.getNode()); 3981 3982 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3983 } 3984 } 3985 3986 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3987 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3988 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3989 if (CombineLD.getNode()) 3990 return CombineLD; 3991 } 3992 3993 return SDValue(); 3994} 3995 3996SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3997 EVT VT = N->getValueType(0); 3998 return CombineConsecutiveLoads(N, VT); 3999} 4000 4001/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 4002/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4003/// destination element value type. 4004SDValue DAGCombiner:: 4005ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4006 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4007 4008 // If this is already the right type, we're done. 4009 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4010 4011 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4012 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4013 4014 // If this is a conversion of N elements of one type to N elements of another 4015 // type, convert each element. This handles FP<->INT cases. 4016 if (SrcBitSize == DstBitSize) { 4017 SmallVector<SDValue, 8> Ops; 4018 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4019 SDValue Op = BV->getOperand(i); 4020 // If the vector element type is not legal, the BUILD_VECTOR operands 4021 // are promoted and implicitly truncated. Make that explicit here. 4022 if (Op.getValueType() != SrcEltVT) 4023 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4024 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 4025 DstEltVT, Op)); 4026 AddToWorkList(Ops.back().getNode()); 4027 } 4028 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4029 BV->getValueType(0).getVectorNumElements()); 4030 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4031 &Ops[0], Ops.size()); 4032 } 4033 4034 // Otherwise, we're growing or shrinking the elements. To avoid having to 4035 // handle annoying details of growing/shrinking FP values, we convert them to 4036 // int first. 4037 if (SrcEltVT.isFloatingPoint()) { 4038 // Convert the input float vector to a int vector where the elements are the 4039 // same sizes. 4040 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4041 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4042 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 4043 SrcEltVT = IntVT; 4044 } 4045 4046 // Now we know the input is an integer vector. If the output is a FP type, 4047 // convert to integer first, then to FP of the right size. 4048 if (DstEltVT.isFloatingPoint()) { 4049 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4050 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4051 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4052 4053 // Next, convert to FP elements of the same size. 4054 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4055 } 4056 4057 // Okay, we know the src/dst types are both integers of differing types. 4058 // Handling growing first. 4059 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4060 if (SrcBitSize < DstBitSize) { 4061 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4062 4063 SmallVector<SDValue, 8> Ops; 4064 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4065 i += NumInputsPerOutput) { 4066 bool isLE = TLI.isLittleEndian(); 4067 APInt NewBits = APInt(DstBitSize, 0); 4068 bool EltIsUndef = true; 4069 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4070 // Shift the previously computed bits over. 4071 NewBits <<= SrcBitSize; 4072 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4073 if (Op.getOpcode() == ISD::UNDEF) continue; 4074 EltIsUndef = false; 4075 4076 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4077 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 4078 } 4079 4080 if (EltIsUndef) 4081 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4082 else 4083 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4084 } 4085 4086 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4087 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4088 &Ops[0], Ops.size()); 4089 } 4090 4091 // Finally, this must be the case where we are shrinking elements: each input 4092 // turns into multiple outputs. 4093 bool isS2V = ISD::isScalarToVector(BV); 4094 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4095 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4096 NumOutputsPerInput*BV->getNumOperands()); 4097 SmallVector<SDValue, 8> Ops; 4098 4099 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4100 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4101 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4102 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4103 continue; 4104 } 4105 4106 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4107 getAPIntValue()).zextOrTrunc(SrcBitSize); 4108 4109 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4110 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4111 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4112 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4113 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4114 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4115 Ops[0]); 4116 OpVal = OpVal.lshr(DstBitSize); 4117 } 4118 4119 // For big endian targets, swap the order of the pieces of each element. 4120 if (TLI.isBigEndian()) 4121 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4122 } 4123 4124 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4125 &Ops[0], Ops.size()); 4126} 4127 4128SDValue DAGCombiner::visitFADD(SDNode *N) { 4129 SDValue N0 = N->getOperand(0); 4130 SDValue N1 = N->getOperand(1); 4131 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4132 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4133 EVT VT = N->getValueType(0); 4134 4135 // fold vector ops 4136 if (VT.isVector()) { 4137 SDValue FoldedVOp = SimplifyVBinOp(N); 4138 if (FoldedVOp.getNode()) return FoldedVOp; 4139 } 4140 4141 // fold (fadd c1, c2) -> (fadd c1, c2) 4142 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4143 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4144 // canonicalize constant to RHS 4145 if (N0CFP && !N1CFP) 4146 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4147 // fold (fadd A, 0) -> A 4148 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4149 return N0; 4150 // fold (fadd A, (fneg B)) -> (fsub A, B) 4151 if (isNegatibleForFree(N1, LegalOperations) == 2) 4152 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4153 GetNegatedExpression(N1, DAG, LegalOperations)); 4154 // fold (fadd (fneg A), B) -> (fsub B, A) 4155 if (isNegatibleForFree(N0, LegalOperations) == 2) 4156 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4157 GetNegatedExpression(N0, DAG, LegalOperations)); 4158 4159 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4160 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4161 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4162 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4163 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4164 N0.getOperand(1), N1)); 4165 4166 return SDValue(); 4167} 4168 4169SDValue DAGCombiner::visitFSUB(SDNode *N) { 4170 SDValue N0 = N->getOperand(0); 4171 SDValue N1 = N->getOperand(1); 4172 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4173 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4174 EVT VT = N->getValueType(0); 4175 4176 // fold vector ops 4177 if (VT.isVector()) { 4178 SDValue FoldedVOp = SimplifyVBinOp(N); 4179 if (FoldedVOp.getNode()) return FoldedVOp; 4180 } 4181 4182 // fold (fsub c1, c2) -> c1-c2 4183 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4184 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4185 // fold (fsub A, 0) -> A 4186 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4187 return N0; 4188 // fold (fsub 0, B) -> -B 4189 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4190 if (isNegatibleForFree(N1, LegalOperations)) 4191 return GetNegatedExpression(N1, DAG, LegalOperations); 4192 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4193 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4194 } 4195 // fold (fsub A, (fneg B)) -> (fadd A, B) 4196 if (isNegatibleForFree(N1, LegalOperations)) 4197 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4198 GetNegatedExpression(N1, DAG, LegalOperations)); 4199 4200 return SDValue(); 4201} 4202 4203SDValue DAGCombiner::visitFMUL(SDNode *N) { 4204 SDValue N0 = N->getOperand(0); 4205 SDValue N1 = N->getOperand(1); 4206 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4207 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4208 EVT VT = N->getValueType(0); 4209 4210 // fold vector ops 4211 if (VT.isVector()) { 4212 SDValue FoldedVOp = SimplifyVBinOp(N); 4213 if (FoldedVOp.getNode()) return FoldedVOp; 4214 } 4215 4216 // fold (fmul c1, c2) -> c1*c2 4217 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4218 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4219 // canonicalize constant to RHS 4220 if (N0CFP && !N1CFP) 4221 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4222 // fold (fmul A, 0) -> 0 4223 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4224 return N1; 4225 // fold (fmul A, 0) -> 0, vector edition. 4226 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4227 return N1; 4228 // fold (fmul X, 2.0) -> (fadd X, X) 4229 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4230 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4231 // fold (fmul X, -1.0) -> (fneg X) 4232 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4233 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4234 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4235 4236 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4237 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4238 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4239 // Both can be negated for free, check to see if at least one is cheaper 4240 // negated. 4241 if (LHSNeg == 2 || RHSNeg == 2) 4242 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4243 GetNegatedExpression(N0, DAG, LegalOperations), 4244 GetNegatedExpression(N1, DAG, LegalOperations)); 4245 } 4246 } 4247 4248 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4249 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4250 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4251 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4252 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4253 N0.getOperand(1), N1)); 4254 4255 return SDValue(); 4256} 4257 4258SDValue DAGCombiner::visitFDIV(SDNode *N) { 4259 SDValue N0 = N->getOperand(0); 4260 SDValue N1 = N->getOperand(1); 4261 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4262 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4263 EVT VT = N->getValueType(0); 4264 4265 // fold vector ops 4266 if (VT.isVector()) { 4267 SDValue FoldedVOp = SimplifyVBinOp(N); 4268 if (FoldedVOp.getNode()) return FoldedVOp; 4269 } 4270 4271 // fold (fdiv c1, c2) -> c1/c2 4272 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4273 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4274 4275 4276 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4277 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4278 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4279 // Both can be negated for free, check to see if at least one is cheaper 4280 // negated. 4281 if (LHSNeg == 2 || RHSNeg == 2) 4282 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4283 GetNegatedExpression(N0, DAG, LegalOperations), 4284 GetNegatedExpression(N1, DAG, LegalOperations)); 4285 } 4286 } 4287 4288 return SDValue(); 4289} 4290 4291SDValue DAGCombiner::visitFREM(SDNode *N) { 4292 SDValue N0 = N->getOperand(0); 4293 SDValue N1 = N->getOperand(1); 4294 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4295 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4296 EVT VT = N->getValueType(0); 4297 4298 // fold (frem c1, c2) -> fmod(c1,c2) 4299 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4300 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4301 4302 return SDValue(); 4303} 4304 4305SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4306 SDValue N0 = N->getOperand(0); 4307 SDValue N1 = N->getOperand(1); 4308 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4309 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4310 EVT VT = N->getValueType(0); 4311 4312 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4313 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4314 4315 if (N1CFP) { 4316 const APFloat& V = N1CFP->getValueAPF(); 4317 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4318 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4319 if (!V.isNegative()) { 4320 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4321 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4322 } else { 4323 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4324 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4325 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4326 } 4327 } 4328 4329 // copysign(fabs(x), y) -> copysign(x, y) 4330 // copysign(fneg(x), y) -> copysign(x, y) 4331 // copysign(copysign(x,z), y) -> copysign(x, y) 4332 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4333 N0.getOpcode() == ISD::FCOPYSIGN) 4334 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4335 N0.getOperand(0), N1); 4336 4337 // copysign(x, abs(y)) -> abs(x) 4338 if (N1.getOpcode() == ISD::FABS) 4339 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4340 4341 // copysign(x, copysign(y,z)) -> copysign(x, z) 4342 if (N1.getOpcode() == ISD::FCOPYSIGN) 4343 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4344 N0, N1.getOperand(1)); 4345 4346 // copysign(x, fp_extend(y)) -> copysign(x, y) 4347 // copysign(x, fp_round(y)) -> copysign(x, y) 4348 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4349 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4350 N0, N1.getOperand(0)); 4351 4352 return SDValue(); 4353} 4354 4355SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4356 SDValue N0 = N->getOperand(0); 4357 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4358 EVT VT = N->getValueType(0); 4359 EVT OpVT = N0.getValueType(); 4360 4361 // fold (sint_to_fp c1) -> c1fp 4362 if (N0C && OpVT != MVT::ppcf128) 4363 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4364 4365 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4366 // but UINT_TO_FP is legal on this target, try to convert. 4367 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4368 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4369 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4370 if (DAG.SignBitIsZero(N0)) 4371 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4372 } 4373 4374 return SDValue(); 4375} 4376 4377SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4378 SDValue N0 = N->getOperand(0); 4379 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4380 EVT VT = N->getValueType(0); 4381 EVT OpVT = N0.getValueType(); 4382 4383 // fold (uint_to_fp c1) -> c1fp 4384 if (N0C && OpVT != MVT::ppcf128) 4385 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4386 4387 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4388 // but SINT_TO_FP is legal on this target, try to convert. 4389 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4390 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4391 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4392 if (DAG.SignBitIsZero(N0)) 4393 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4394 } 4395 4396 return SDValue(); 4397} 4398 4399SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4400 SDValue N0 = N->getOperand(0); 4401 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4402 EVT VT = N->getValueType(0); 4403 4404 // fold (fp_to_sint c1fp) -> c1 4405 if (N0CFP) 4406 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4407 4408 return SDValue(); 4409} 4410 4411SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4412 SDValue N0 = N->getOperand(0); 4413 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4414 EVT VT = N->getValueType(0); 4415 4416 // fold (fp_to_uint c1fp) -> c1 4417 if (N0CFP && VT != MVT::ppcf128) 4418 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4419 4420 return SDValue(); 4421} 4422 4423SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4424 SDValue N0 = N->getOperand(0); 4425 SDValue N1 = N->getOperand(1); 4426 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4427 EVT VT = N->getValueType(0); 4428 4429 // fold (fp_round c1fp) -> c1fp 4430 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4431 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4432 4433 // fold (fp_round (fp_extend x)) -> x 4434 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4435 return N0.getOperand(0); 4436 4437 // fold (fp_round (fp_round x)) -> (fp_round x) 4438 if (N0.getOpcode() == ISD::FP_ROUND) { 4439 // This is a value preserving truncation if both round's are. 4440 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4441 N0.getNode()->getConstantOperandVal(1) == 1; 4442 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4443 DAG.getIntPtrConstant(IsTrunc)); 4444 } 4445 4446 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4447 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4448 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4449 N0.getOperand(0), N1); 4450 AddToWorkList(Tmp.getNode()); 4451 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4452 Tmp, N0.getOperand(1)); 4453 } 4454 4455 return SDValue(); 4456} 4457 4458SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4459 SDValue N0 = N->getOperand(0); 4460 EVT VT = N->getValueType(0); 4461 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4462 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4463 4464 // fold (fp_round_inreg c1fp) -> c1fp 4465 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4466 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4467 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4468 } 4469 4470 return SDValue(); 4471} 4472 4473SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4474 SDValue N0 = N->getOperand(0); 4475 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4476 EVT VT = N->getValueType(0); 4477 4478 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4479 if (N->hasOneUse() && 4480 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4481 return SDValue(); 4482 4483 // fold (fp_extend c1fp) -> c1fp 4484 if (N0CFP && VT != MVT::ppcf128) 4485 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4486 4487 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4488 // value of X. 4489 if (N0.getOpcode() == ISD::FP_ROUND 4490 && N0.getNode()->getConstantOperandVal(1) == 1) { 4491 SDValue In = N0.getOperand(0); 4492 if (In.getValueType() == VT) return In; 4493 if (VT.bitsLT(In.getValueType())) 4494 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4495 In, N0.getOperand(1)); 4496 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4497 } 4498 4499 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4500 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4501 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4502 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4503 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4504 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4505 LN0->getChain(), 4506 LN0->getBasePtr(), LN0->getSrcValue(), 4507 LN0->getSrcValueOffset(), 4508 N0.getValueType(), 4509 LN0->isVolatile(), LN0->isNonTemporal(), 4510 LN0->getAlignment()); 4511 CombineTo(N, ExtLoad); 4512 CombineTo(N0.getNode(), 4513 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4514 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4515 ExtLoad.getValue(1)); 4516 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4517 } 4518 4519 return SDValue(); 4520} 4521 4522SDValue DAGCombiner::visitFNEG(SDNode *N) { 4523 SDValue N0 = N->getOperand(0); 4524 EVT VT = N->getValueType(0); 4525 4526 if (isNegatibleForFree(N0, LegalOperations)) 4527 return GetNegatedExpression(N0, DAG, LegalOperations); 4528 4529 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4530 // constant pool values. 4531 if (N0.getOpcode() == ISD::BIT_CONVERT && 4532 !VT.isVector() && 4533 N0.getNode()->hasOneUse() && 4534 N0.getOperand(0).getValueType().isInteger()) { 4535 SDValue Int = N0.getOperand(0); 4536 EVT IntVT = Int.getValueType(); 4537 if (IntVT.isInteger() && !IntVT.isVector()) { 4538 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4539 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4540 AddToWorkList(Int.getNode()); 4541 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4542 VT, Int); 4543 } 4544 } 4545 4546 return SDValue(); 4547} 4548 4549SDValue DAGCombiner::visitFABS(SDNode *N) { 4550 SDValue N0 = N->getOperand(0); 4551 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4552 EVT VT = N->getValueType(0); 4553 4554 // fold (fabs c1) -> fabs(c1) 4555 if (N0CFP && VT != MVT::ppcf128) 4556 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4557 // fold (fabs (fabs x)) -> (fabs x) 4558 if (N0.getOpcode() == ISD::FABS) 4559 return N->getOperand(0); 4560 // fold (fabs (fneg x)) -> (fabs x) 4561 // fold (fabs (fcopysign x, y)) -> (fabs x) 4562 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4563 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4564 4565 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4566 // constant pool values. 4567 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4568 N0.getOperand(0).getValueType().isInteger() && 4569 !N0.getOperand(0).getValueType().isVector()) { 4570 SDValue Int = N0.getOperand(0); 4571 EVT IntVT = Int.getValueType(); 4572 if (IntVT.isInteger() && !IntVT.isVector()) { 4573 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4574 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4575 AddToWorkList(Int.getNode()); 4576 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4577 N->getValueType(0), Int); 4578 } 4579 } 4580 4581 return SDValue(); 4582} 4583 4584SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4585 SDValue Chain = N->getOperand(0); 4586 SDValue N1 = N->getOperand(1); 4587 SDValue N2 = N->getOperand(2); 4588 4589 // If N is a constant we could fold this into a fallthrough or unconditional 4590 // branch. However that doesn't happen very often in normal code, because 4591 // Instcombine/SimplifyCFG should have handled the available opportunities. 4592 // If we did this folding here, it would be necessary to update the 4593 // MachineBasicBlock CFG, which is awkward. 4594 4595 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4596 // on the target. 4597 if (N1.getOpcode() == ISD::SETCC && 4598 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4599 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4600 Chain, N1.getOperand(2), 4601 N1.getOperand(0), N1.getOperand(1), N2); 4602 } 4603 4604 SDNode *Trunc = 0; 4605 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 4606 // Look pass truncate. 4607 Trunc = N1.getNode(); 4608 N1 = N1.getOperand(0); 4609 } 4610 4611 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4612 // Match this pattern so that we can generate simpler code: 4613 // 4614 // %a = ... 4615 // %b = and i32 %a, 2 4616 // %c = srl i32 %b, 1 4617 // brcond i32 %c ... 4618 // 4619 // into 4620 // 4621 // %a = ... 4622 // %b = and i32 %a, 2 4623 // %c = setcc eq %b, 0 4624 // brcond %c ... 4625 // 4626 // This applies only when the AND constant value has one bit set and the 4627 // SRL constant is equal to the log2 of the AND constant. The back-end is 4628 // smart enough to convert the result into a TEST/JMP sequence. 4629 SDValue Op0 = N1.getOperand(0); 4630 SDValue Op1 = N1.getOperand(1); 4631 4632 if (Op0.getOpcode() == ISD::AND && 4633 Op1.getOpcode() == ISD::Constant) { 4634 SDValue AndOp1 = Op0.getOperand(1); 4635 4636 if (AndOp1.getOpcode() == ISD::Constant) { 4637 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4638 4639 if (AndConst.isPowerOf2() && 4640 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4641 SDValue SetCC = 4642 DAG.getSetCC(N->getDebugLoc(), 4643 TLI.getSetCCResultType(Op0.getValueType()), 4644 Op0, DAG.getConstant(0, Op0.getValueType()), 4645 ISD::SETNE); 4646 4647 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4648 MVT::Other, Chain, SetCC, N2); 4649 // Don't add the new BRCond into the worklist or else SimplifySelectCC 4650 // will convert it back to (X & C1) >> C2. 4651 CombineTo(N, NewBRCond, false); 4652 // Truncate is dead. 4653 if (Trunc) { 4654 removeFromWorkList(Trunc); 4655 DAG.DeleteNode(Trunc); 4656 } 4657 // Replace the uses of SRL with SETCC 4658 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4659 removeFromWorkList(N1.getNode()); 4660 DAG.DeleteNode(N1.getNode()); 4661 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4662 } 4663 } 4664 } 4665 } 4666 4667 return SDValue(); 4668} 4669 4670// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4671// 4672SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4673 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4674 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4675 4676 // If N is a constant we could fold this into a fallthrough or unconditional 4677 // branch. However that doesn't happen very often in normal code, because 4678 // Instcombine/SimplifyCFG should have handled the available opportunities. 4679 // If we did this folding here, it would be necessary to update the 4680 // MachineBasicBlock CFG, which is awkward. 4681 4682 // Use SimplifySetCC to simplify SETCC's. 4683 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4684 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4685 false); 4686 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4687 4688 // fold to a simpler setcc 4689 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4690 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4691 N->getOperand(0), Simp.getOperand(2), 4692 Simp.getOperand(0), Simp.getOperand(1), 4693 N->getOperand(4)); 4694 4695 return SDValue(); 4696} 4697 4698/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4699/// pre-indexed load / store when the base pointer is an add or subtract 4700/// and it has other uses besides the load / store. After the 4701/// transformation, the new indexed load / store has effectively folded 4702/// the add / subtract in and all of its other uses are redirected to the 4703/// new load / store. 4704bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4705 if (!LegalOperations) 4706 return false; 4707 4708 bool isLoad = true; 4709 SDValue Ptr; 4710 EVT VT; 4711 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4712 if (LD->isIndexed()) 4713 return false; 4714 VT = LD->getMemoryVT(); 4715 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4716 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4717 return false; 4718 Ptr = LD->getBasePtr(); 4719 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4720 if (ST->isIndexed()) 4721 return false; 4722 VT = ST->getMemoryVT(); 4723 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4724 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4725 return false; 4726 Ptr = ST->getBasePtr(); 4727 isLoad = false; 4728 } else { 4729 return false; 4730 } 4731 4732 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4733 // out. There is no reason to make this a preinc/predec. 4734 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4735 Ptr.getNode()->hasOneUse()) 4736 return false; 4737 4738 // Ask the target to do addressing mode selection. 4739 SDValue BasePtr; 4740 SDValue Offset; 4741 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4742 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4743 return false; 4744 // Don't create a indexed load / store with zero offset. 4745 if (isa<ConstantSDNode>(Offset) && 4746 cast<ConstantSDNode>(Offset)->isNullValue()) 4747 return false; 4748 4749 // Try turning it into a pre-indexed load / store except when: 4750 // 1) The new base ptr is a frame index. 4751 // 2) If N is a store and the new base ptr is either the same as or is a 4752 // predecessor of the value being stored. 4753 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4754 // that would create a cycle. 4755 // 4) All uses are load / store ops that use it as old base ptr. 4756 4757 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4758 // (plus the implicit offset) to a register to preinc anyway. 4759 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4760 return false; 4761 4762 // Check #2. 4763 if (!isLoad) { 4764 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4765 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4766 return false; 4767 } 4768 4769 // Now check for #3 and #4. 4770 bool RealUse = false; 4771 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4772 E = Ptr.getNode()->use_end(); I != E; ++I) { 4773 SDNode *Use = *I; 4774 if (Use == N) 4775 continue; 4776 if (Use->isPredecessorOf(N)) 4777 return false; 4778 4779 if (!((Use->getOpcode() == ISD::LOAD && 4780 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4781 (Use->getOpcode() == ISD::STORE && 4782 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4783 RealUse = true; 4784 } 4785 4786 if (!RealUse) 4787 return false; 4788 4789 SDValue Result; 4790 if (isLoad) 4791 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4792 BasePtr, Offset, AM); 4793 else 4794 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4795 BasePtr, Offset, AM); 4796 ++PreIndexedNodes; 4797 ++NodesCombined; 4798 DEBUG(dbgs() << "\nReplacing.4 "; 4799 N->dump(&DAG); 4800 dbgs() << "\nWith: "; 4801 Result.getNode()->dump(&DAG); 4802 dbgs() << '\n'); 4803 WorkListRemover DeadNodes(*this); 4804 if (isLoad) { 4805 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4806 &DeadNodes); 4807 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4808 &DeadNodes); 4809 } else { 4810 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4811 &DeadNodes); 4812 } 4813 4814 // Finally, since the node is now dead, remove it from the graph. 4815 DAG.DeleteNode(N); 4816 4817 // Replace the uses of Ptr with uses of the updated base value. 4818 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4819 &DeadNodes); 4820 removeFromWorkList(Ptr.getNode()); 4821 DAG.DeleteNode(Ptr.getNode()); 4822 4823 return true; 4824} 4825 4826/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4827/// add / sub of the base pointer node into a post-indexed load / store. 4828/// The transformation folded the add / subtract into the new indexed 4829/// load / store effectively and all of its uses are redirected to the 4830/// new load / store. 4831bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4832 if (!LegalOperations) 4833 return false; 4834 4835 bool isLoad = true; 4836 SDValue Ptr; 4837 EVT VT; 4838 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4839 if (LD->isIndexed()) 4840 return false; 4841 VT = LD->getMemoryVT(); 4842 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4843 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4844 return false; 4845 Ptr = LD->getBasePtr(); 4846 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4847 if (ST->isIndexed()) 4848 return false; 4849 VT = ST->getMemoryVT(); 4850 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4851 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4852 return false; 4853 Ptr = ST->getBasePtr(); 4854 isLoad = false; 4855 } else { 4856 return false; 4857 } 4858 4859 if (Ptr.getNode()->hasOneUse()) 4860 return false; 4861 4862 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4863 E = Ptr.getNode()->use_end(); I != E; ++I) { 4864 SDNode *Op = *I; 4865 if (Op == N || 4866 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4867 continue; 4868 4869 SDValue BasePtr; 4870 SDValue Offset; 4871 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4872 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4873 if (Ptr == Offset && Op->getOpcode() == ISD::ADD) 4874 std::swap(BasePtr, Offset); 4875 if (Ptr != BasePtr) 4876 continue; 4877 // Don't create a indexed load / store with zero offset. 4878 if (isa<ConstantSDNode>(Offset) && 4879 cast<ConstantSDNode>(Offset)->isNullValue()) 4880 continue; 4881 4882 // Try turning it into a post-indexed load / store except when 4883 // 1) All uses are load / store ops that use it as base ptr. 4884 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4885 // nor a successor of N. Otherwise, if Op is folded that would 4886 // create a cycle. 4887 4888 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4889 continue; 4890 4891 // Check for #1. 4892 bool TryNext = false; 4893 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4894 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4895 SDNode *Use = *II; 4896 if (Use == Ptr.getNode()) 4897 continue; 4898 4899 // If all the uses are load / store addresses, then don't do the 4900 // transformation. 4901 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4902 bool RealUse = false; 4903 for (SDNode::use_iterator III = Use->use_begin(), 4904 EEE = Use->use_end(); III != EEE; ++III) { 4905 SDNode *UseUse = *III; 4906 if (!((UseUse->getOpcode() == ISD::LOAD && 4907 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4908 (UseUse->getOpcode() == ISD::STORE && 4909 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4910 RealUse = true; 4911 } 4912 4913 if (!RealUse) { 4914 TryNext = true; 4915 break; 4916 } 4917 } 4918 } 4919 4920 if (TryNext) 4921 continue; 4922 4923 // Check for #2 4924 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4925 SDValue Result = isLoad 4926 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4927 BasePtr, Offset, AM) 4928 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4929 BasePtr, Offset, AM); 4930 ++PostIndexedNodes; 4931 ++NodesCombined; 4932 DEBUG(dbgs() << "\nReplacing.5 "; 4933 N->dump(&DAG); 4934 dbgs() << "\nWith: "; 4935 Result.getNode()->dump(&DAG); 4936 dbgs() << '\n'); 4937 WorkListRemover DeadNodes(*this); 4938 if (isLoad) { 4939 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4940 &DeadNodes); 4941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4942 &DeadNodes); 4943 } else { 4944 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4945 &DeadNodes); 4946 } 4947 4948 // Finally, since the node is now dead, remove it from the graph. 4949 DAG.DeleteNode(N); 4950 4951 // Replace the uses of Use with uses of the updated base value. 4952 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4953 Result.getValue(isLoad ? 1 : 0), 4954 &DeadNodes); 4955 removeFromWorkList(Op); 4956 DAG.DeleteNode(Op); 4957 return true; 4958 } 4959 } 4960 } 4961 4962 return false; 4963} 4964 4965SDValue DAGCombiner::visitLOAD(SDNode *N) { 4966 LoadSDNode *LD = cast<LoadSDNode>(N); 4967 SDValue Chain = LD->getChain(); 4968 SDValue Ptr = LD->getBasePtr(); 4969 4970 // Try to infer better alignment information than the load already has. 4971 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4972 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 4973 if (Align > LD->getAlignment()) 4974 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4975 LD->getValueType(0), 4976 Chain, Ptr, LD->getSrcValue(), 4977 LD->getSrcValueOffset(), LD->getMemoryVT(), 4978 LD->isVolatile(), LD->isNonTemporal(), Align); 4979 } 4980 } 4981 4982 // If load is not volatile and there are no uses of the loaded value (and 4983 // the updated indexed value in case of indexed loads), change uses of the 4984 // chain value into uses of the chain input (i.e. delete the dead load). 4985 if (!LD->isVolatile()) { 4986 if (N->getValueType(1) == MVT::Other) { 4987 // Unindexed loads. 4988 if (N->hasNUsesOfValue(0, 0)) { 4989 // It's not safe to use the two value CombineTo variant here. e.g. 4990 // v1, chain2 = load chain1, loc 4991 // v2, chain3 = load chain2, loc 4992 // v3 = add v2, c 4993 // Now we replace use of chain2 with chain1. This makes the second load 4994 // isomorphic to the one we are deleting, and thus makes this load live. 4995 DEBUG(dbgs() << "\nReplacing.6 "; 4996 N->dump(&DAG); 4997 dbgs() << "\nWith chain: "; 4998 Chain.getNode()->dump(&DAG); 4999 dbgs() << "\n"); 5000 WorkListRemover DeadNodes(*this); 5001 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5002 5003 if (N->use_empty()) { 5004 removeFromWorkList(N); 5005 DAG.DeleteNode(N); 5006 } 5007 5008 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5009 } 5010 } else { 5011 // Indexed loads. 5012 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5013 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5014 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5015 DEBUG(dbgs() << "\nReplacing.6 "; 5016 N->dump(&DAG); 5017 dbgs() << "\nWith: "; 5018 Undef.getNode()->dump(&DAG); 5019 dbgs() << " and 2 other values\n"); 5020 WorkListRemover DeadNodes(*this); 5021 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5022 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5023 DAG.getUNDEF(N->getValueType(1)), 5024 &DeadNodes); 5025 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5026 removeFromWorkList(N); 5027 DAG.DeleteNode(N); 5028 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5029 } 5030 } 5031 } 5032 5033 // If this load is directly stored, replace the load value with the stored 5034 // value. 5035 // TODO: Handle store large -> read small portion. 5036 // TODO: Handle TRUNCSTORE/LOADEXT 5037 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5038 !LD->isVolatile()) { 5039 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5040 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5041 if (PrevST->getBasePtr() == Ptr && 5042 PrevST->getValue().getValueType() == N->getValueType(0)) 5043 return CombineTo(N, Chain.getOperand(1), Chain); 5044 } 5045 } 5046 5047 if (CombinerAA) { 5048 // Walk up chain skipping non-aliasing memory nodes. 5049 SDValue BetterChain = FindBetterChain(N, Chain); 5050 5051 // If there is a better chain. 5052 if (Chain != BetterChain) { 5053 SDValue ReplLoad; 5054 5055 // Replace the chain to void dependency. 5056 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5057 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5058 BetterChain, Ptr, 5059 LD->getSrcValue(), LD->getSrcValueOffset(), 5060 LD->isVolatile(), LD->isNonTemporal(), 5061 LD->getAlignment()); 5062 } else { 5063 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5064 LD->getValueType(0), 5065 BetterChain, Ptr, LD->getSrcValue(), 5066 LD->getSrcValueOffset(), 5067 LD->getMemoryVT(), 5068 LD->isVolatile(), 5069 LD->isNonTemporal(), 5070 LD->getAlignment()); 5071 } 5072 5073 // Create token factor to keep old chain connected. 5074 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5075 MVT::Other, Chain, ReplLoad.getValue(1)); 5076 5077 // Make sure the new and old chains are cleaned up. 5078 AddToWorkList(Token.getNode()); 5079 5080 // Replace uses with load result and token factor. Don't add users 5081 // to work list. 5082 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5083 } 5084 } 5085 5086 // Try transforming N to an indexed load. 5087 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5088 return SDValue(N, 0); 5089 5090 return SDValue(); 5091} 5092 5093 5094/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5095/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5096/// of the loaded bits, try narrowing the load and store if it would end up 5097/// being a win for performance or code size. 5098SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5099 StoreSDNode *ST = cast<StoreSDNode>(N); 5100 if (ST->isVolatile()) 5101 return SDValue(); 5102 5103 SDValue Chain = ST->getChain(); 5104 SDValue Value = ST->getValue(); 5105 SDValue Ptr = ST->getBasePtr(); 5106 EVT VT = Value.getValueType(); 5107 5108 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5109 return SDValue(); 5110 5111 unsigned Opc = Value.getOpcode(); 5112 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5113 Value.getOperand(1).getOpcode() != ISD::Constant) 5114 return SDValue(); 5115 5116 SDValue N0 = Value.getOperand(0); 5117 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5118 LoadSDNode *LD = cast<LoadSDNode>(N0); 5119 if (LD->getBasePtr() != Ptr) 5120 return SDValue(); 5121 5122 // Find the type to narrow it the load / op / store to. 5123 SDValue N1 = Value.getOperand(1); 5124 unsigned BitWidth = N1.getValueSizeInBits(); 5125 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5126 if (Opc == ISD::AND) 5127 Imm ^= APInt::getAllOnesValue(BitWidth); 5128 if (Imm == 0 || Imm.isAllOnesValue()) 5129 return SDValue(); 5130 unsigned ShAmt = Imm.countTrailingZeros(); 5131 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5132 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5133 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5134 while (NewBW < BitWidth && 5135 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5136 TLI.isNarrowingProfitable(VT, NewVT))) { 5137 NewBW = NextPowerOf2(NewBW); 5138 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5139 } 5140 if (NewBW >= BitWidth) 5141 return SDValue(); 5142 5143 // If the lsb changed does not start at the type bitwidth boundary, 5144 // start at the previous one. 5145 if (ShAmt % NewBW) 5146 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5147 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5148 if ((Imm & Mask) == Imm) { 5149 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5150 if (Opc == ISD::AND) 5151 NewImm ^= APInt::getAllOnesValue(NewBW); 5152 uint64_t PtrOff = ShAmt / 8; 5153 // For big endian targets, we need to adjust the offset to the pointer to 5154 // load the correct bytes. 5155 if (TLI.isBigEndian()) 5156 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5157 5158 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5159 if (NewAlign < 5160 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext()))) 5161 return SDValue(); 5162 5163 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5164 Ptr.getValueType(), Ptr, 5165 DAG.getConstant(PtrOff, Ptr.getValueType())); 5166 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5167 LD->getChain(), NewPtr, 5168 LD->getSrcValue(), LD->getSrcValueOffset(), 5169 LD->isVolatile(), LD->isNonTemporal(), 5170 NewAlign); 5171 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5172 DAG.getConstant(NewImm, NewVT)); 5173 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5174 NewVal, NewPtr, 5175 ST->getSrcValue(), ST->getSrcValueOffset(), 5176 false, false, NewAlign); 5177 5178 AddToWorkList(NewPtr.getNode()); 5179 AddToWorkList(NewLD.getNode()); 5180 AddToWorkList(NewVal.getNode()); 5181 WorkListRemover DeadNodes(*this); 5182 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5183 &DeadNodes); 5184 ++OpsNarrowed; 5185 return NewST; 5186 } 5187 } 5188 5189 return SDValue(); 5190} 5191 5192SDValue DAGCombiner::visitSTORE(SDNode *N) { 5193 StoreSDNode *ST = cast<StoreSDNode>(N); 5194 SDValue Chain = ST->getChain(); 5195 SDValue Value = ST->getValue(); 5196 SDValue Ptr = ST->getBasePtr(); 5197 5198 // Try to infer better alignment information than the store already has. 5199 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5200 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5201 if (Align > ST->getAlignment()) 5202 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5203 Ptr, ST->getSrcValue(), 5204 ST->getSrcValueOffset(), ST->getMemoryVT(), 5205 ST->isVolatile(), ST->isNonTemporal(), Align); 5206 } 5207 } 5208 5209 // If this is a store of a bit convert, store the input value if the 5210 // resultant store does not need a higher alignment than the original. 5211 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5212 ST->isUnindexed()) { 5213 unsigned OrigAlign = ST->getAlignment(); 5214 EVT SVT = Value.getOperand(0).getValueType(); 5215 unsigned Align = TLI.getTargetData()-> 5216 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5217 if (Align <= OrigAlign && 5218 ((!LegalOperations && !ST->isVolatile()) || 5219 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5220 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5221 Ptr, ST->getSrcValue(), 5222 ST->getSrcValueOffset(), ST->isVolatile(), 5223 ST->isNonTemporal(), OrigAlign); 5224 } 5225 5226 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5227 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5228 // NOTE: If the original store is volatile, this transform must not increase 5229 // the number of stores. For example, on x86-32 an f64 can be stored in one 5230 // processor operation but an i64 (which is not legal) requires two. So the 5231 // transform should not be done in this case. 5232 if (Value.getOpcode() != ISD::TargetConstantFP) { 5233 SDValue Tmp; 5234 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5235 default: llvm_unreachable("Unknown FP type"); 5236 case MVT::f80: // We don't do this for these yet. 5237 case MVT::f128: 5238 case MVT::ppcf128: 5239 break; 5240 case MVT::f32: 5241 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5242 !ST->isVolatile()) || 5243 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5244 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5245 bitcastToAPInt().getZExtValue(), MVT::i32); 5246 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5247 Ptr, ST->getSrcValue(), 5248 ST->getSrcValueOffset(), ST->isVolatile(), 5249 ST->isNonTemporal(), ST->getAlignment()); 5250 } 5251 break; 5252 case MVT::f64: 5253 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5254 !ST->isVolatile()) || 5255 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5256 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5257 getZExtValue(), MVT::i64); 5258 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5259 Ptr, ST->getSrcValue(), 5260 ST->getSrcValueOffset(), ST->isVolatile(), 5261 ST->isNonTemporal(), ST->getAlignment()); 5262 } else if (!ST->isVolatile() && 5263 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5264 // Many FP stores are not made apparent until after legalize, e.g. for 5265 // argument passing. Since this is so common, custom legalize the 5266 // 64-bit integer store into two 32-bit stores. 5267 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5268 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5269 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5270 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5271 5272 int SVOffset = ST->getSrcValueOffset(); 5273 unsigned Alignment = ST->getAlignment(); 5274 bool isVolatile = ST->isVolatile(); 5275 bool isNonTemporal = ST->isNonTemporal(); 5276 5277 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5278 Ptr, ST->getSrcValue(), 5279 ST->getSrcValueOffset(), 5280 isVolatile, isNonTemporal, 5281 ST->getAlignment()); 5282 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5283 DAG.getConstant(4, Ptr.getValueType())); 5284 SVOffset += 4; 5285 Alignment = MinAlign(Alignment, 4U); 5286 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5287 Ptr, ST->getSrcValue(), 5288 SVOffset, isVolatile, isNonTemporal, 5289 Alignment); 5290 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5291 St0, St1); 5292 } 5293 5294 break; 5295 } 5296 } 5297 } 5298 5299 if (CombinerAA) { 5300 // Walk up chain skipping non-aliasing memory nodes. 5301 SDValue BetterChain = FindBetterChain(N, Chain); 5302 5303 // If there is a better chain. 5304 if (Chain != BetterChain) { 5305 SDValue ReplStore; 5306 5307 // Replace the chain to avoid dependency. 5308 if (ST->isTruncatingStore()) { 5309 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5310 ST->getSrcValue(),ST->getSrcValueOffset(), 5311 ST->getMemoryVT(), ST->isVolatile(), 5312 ST->isNonTemporal(), ST->getAlignment()); 5313 } else { 5314 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5315 ST->getSrcValue(), ST->getSrcValueOffset(), 5316 ST->isVolatile(), ST->isNonTemporal(), 5317 ST->getAlignment()); 5318 } 5319 5320 // Create token to keep both nodes around. 5321 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5322 MVT::Other, Chain, ReplStore); 5323 5324 // Make sure the new and old chains are cleaned up. 5325 AddToWorkList(Token.getNode()); 5326 5327 // Don't add users to work list. 5328 return CombineTo(N, Token, false); 5329 } 5330 } 5331 5332 // Try transforming N to an indexed store. 5333 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5334 return SDValue(N, 0); 5335 5336 // FIXME: is there such a thing as a truncating indexed store? 5337 if (ST->isTruncatingStore() && ST->isUnindexed() && 5338 Value.getValueType().isInteger()) { 5339 // See if we can simplify the input to this truncstore with knowledge that 5340 // only the low bits are being used. For example: 5341 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5342 SDValue Shorter = 5343 GetDemandedBits(Value, 5344 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5345 ST->getMemoryVT().getSizeInBits())); 5346 AddToWorkList(Value.getNode()); 5347 if (Shorter.getNode()) 5348 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5349 Ptr, ST->getSrcValue(), 5350 ST->getSrcValueOffset(), ST->getMemoryVT(), 5351 ST->isVolatile(), ST->isNonTemporal(), 5352 ST->getAlignment()); 5353 5354 // Otherwise, see if we can simplify the operation with 5355 // SimplifyDemandedBits, which only works if the value has a single use. 5356 if (SimplifyDemandedBits(Value, 5357 APInt::getLowBitsSet( 5358 Value.getValueType().getScalarType().getSizeInBits(), 5359 ST->getMemoryVT().getSizeInBits()))) 5360 return SDValue(N, 0); 5361 } 5362 5363 // If this is a load followed by a store to the same location, then the store 5364 // is dead/noop. 5365 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5366 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5367 ST->isUnindexed() && !ST->isVolatile() && 5368 // There can't be any side effects between the load and store, such as 5369 // a call or store. 5370 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5371 // The store is dead, remove it. 5372 return Chain; 5373 } 5374 } 5375 5376 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5377 // truncating store. We can do this even if this is already a truncstore. 5378 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5379 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5380 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5381 ST->getMemoryVT())) { 5382 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5383 Ptr, ST->getSrcValue(), 5384 ST->getSrcValueOffset(), ST->getMemoryVT(), 5385 ST->isVolatile(), ST->isNonTemporal(), 5386 ST->getAlignment()); 5387 } 5388 5389 return ReduceLoadOpStoreWidth(N); 5390} 5391 5392SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5393 SDValue InVec = N->getOperand(0); 5394 SDValue InVal = N->getOperand(1); 5395 SDValue EltNo = N->getOperand(2); 5396 5397 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5398 // vector with the inserted element. 5399 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5400 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5401 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5402 InVec.getNode()->op_end()); 5403 if (Elt < Ops.size()) 5404 Ops[Elt] = InVal; 5405 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5406 InVec.getValueType(), &Ops[0], Ops.size()); 5407 } 5408 // If the invec is an UNDEF and if EltNo is a constant, create a new 5409 // BUILD_VECTOR with undef elements and the inserted element. 5410 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5411 isa<ConstantSDNode>(EltNo)) { 5412 EVT VT = InVec.getValueType(); 5413 EVT EltVT = VT.getVectorElementType(); 5414 unsigned NElts = VT.getVectorNumElements(); 5415 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 5416 5417 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5418 if (Elt < Ops.size()) 5419 Ops[Elt] = InVal; 5420 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5421 InVec.getValueType(), &Ops[0], Ops.size()); 5422 } 5423 return SDValue(); 5424} 5425 5426SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5427 // (vextract (scalar_to_vector val, 0) -> val 5428 SDValue InVec = N->getOperand(0); 5429 5430 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5431 // Check if the result type doesn't match the inserted element type. A 5432 // SCALAR_TO_VECTOR may truncate the inserted element and the 5433 // EXTRACT_VECTOR_ELT may widen the extracted vector. 5434 EVT EltVT = InVec.getValueType().getVectorElementType(); 5435 SDValue InOp = InVec.getOperand(0); 5436 EVT NVT = N->getValueType(0); 5437 if (InOp.getValueType() != NVT) { 5438 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 5439 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 5440 } 5441 return InOp; 5442 } 5443 5444 // Perform only after legalization to ensure build_vector / vector_shuffle 5445 // optimizations have already been done. 5446 if (!LegalOperations) return SDValue(); 5447 5448 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5449 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5450 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5451 SDValue EltNo = N->getOperand(1); 5452 5453 if (isa<ConstantSDNode>(EltNo)) { 5454 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5455 bool NewLoad = false; 5456 bool BCNumEltsChanged = false; 5457 EVT VT = InVec.getValueType(); 5458 EVT ExtVT = VT.getVectorElementType(); 5459 EVT LVT = ExtVT; 5460 5461 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5462 EVT BCVT = InVec.getOperand(0).getValueType(); 5463 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 5464 return SDValue(); 5465 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5466 BCNumEltsChanged = true; 5467 InVec = InVec.getOperand(0); 5468 ExtVT = BCVT.getVectorElementType(); 5469 NewLoad = true; 5470 } 5471 5472 LoadSDNode *LN0 = NULL; 5473 const ShuffleVectorSDNode *SVN = NULL; 5474 if (ISD::isNormalLoad(InVec.getNode())) { 5475 LN0 = cast<LoadSDNode>(InVec); 5476 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5477 InVec.getOperand(0).getValueType() == ExtVT && 5478 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5479 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5480 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5481 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5482 // => 5483 // (load $addr+1*size) 5484 5485 // If the bit convert changed the number of elements, it is unsafe 5486 // to examine the mask. 5487 if (BCNumEltsChanged) 5488 return SDValue(); 5489 5490 // Select the input vector, guarding against out of range extract vector. 5491 unsigned NumElems = VT.getVectorNumElements(); 5492 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5493 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5494 5495 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5496 InVec = InVec.getOperand(0); 5497 if (ISD::isNormalLoad(InVec.getNode())) { 5498 LN0 = cast<LoadSDNode>(InVec); 5499 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5500 } 5501 } 5502 5503 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5504 return SDValue(); 5505 5506 unsigned Align = LN0->getAlignment(); 5507 if (NewLoad) { 5508 // Check the resultant load doesn't need a higher alignment than the 5509 // original load. 5510 unsigned NewAlign = 5511 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 5512 5513 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5514 return SDValue(); 5515 5516 Align = NewAlign; 5517 } 5518 5519 SDValue NewPtr = LN0->getBasePtr(); 5520 if (Elt) { 5521 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5522 EVT PtrType = NewPtr.getValueType(); 5523 if (TLI.isBigEndian()) 5524 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5525 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5526 DAG.getConstant(PtrOff, PtrType)); 5527 } 5528 5529 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5530 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5531 LN0->isVolatile(), LN0->isNonTemporal(), Align); 5532 } 5533 5534 return SDValue(); 5535} 5536 5537SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5538 unsigned NumInScalars = N->getNumOperands(); 5539 EVT VT = N->getValueType(0); 5540 5541 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5542 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5543 // at most two distinct vectors, turn this into a shuffle node. 5544 SDValue VecIn1, VecIn2; 5545 for (unsigned i = 0; i != NumInScalars; ++i) { 5546 // Ignore undef inputs. 5547 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5548 5549 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5550 // constant index, bail out. 5551 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5552 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5553 VecIn1 = VecIn2 = SDValue(0, 0); 5554 break; 5555 } 5556 5557 // If the input vector type disagrees with the result of the build_vector, 5558 // we can't make a shuffle. 5559 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5560 if (ExtractedFromVec.getValueType() != VT) { 5561 VecIn1 = VecIn2 = SDValue(0, 0); 5562 break; 5563 } 5564 5565 // Otherwise, remember this. We allow up to two distinct input vectors. 5566 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5567 continue; 5568 5569 if (VecIn1.getNode() == 0) { 5570 VecIn1 = ExtractedFromVec; 5571 } else if (VecIn2.getNode() == 0) { 5572 VecIn2 = ExtractedFromVec; 5573 } else { 5574 // Too many inputs. 5575 VecIn1 = VecIn2 = SDValue(0, 0); 5576 break; 5577 } 5578 } 5579 5580 // If everything is good, we can make a shuffle operation. 5581 if (VecIn1.getNode()) { 5582 SmallVector<int, 8> Mask; 5583 for (unsigned i = 0; i != NumInScalars; ++i) { 5584 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5585 Mask.push_back(-1); 5586 continue; 5587 } 5588 5589 // If extracting from the first vector, just use the index directly. 5590 SDValue Extract = N->getOperand(i); 5591 SDValue ExtVal = Extract.getOperand(1); 5592 if (Extract.getOperand(0) == VecIn1) { 5593 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5594 if (ExtIndex > VT.getVectorNumElements()) 5595 return SDValue(); 5596 5597 Mask.push_back(ExtIndex); 5598 continue; 5599 } 5600 5601 // Otherwise, use InIdx + VecSize 5602 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5603 Mask.push_back(Idx+NumInScalars); 5604 } 5605 5606 // Add count and size info. 5607 if (!TLI.isTypeLegal(VT) && LegalTypes) 5608 return SDValue(); 5609 5610 // Return the new VECTOR_SHUFFLE node. 5611 SDValue Ops[2]; 5612 Ops[0] = VecIn1; 5613 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5614 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5615 } 5616 5617 return SDValue(); 5618} 5619 5620SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5621 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5622 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5623 // inputs come from at most two distinct vectors, turn this into a shuffle 5624 // node. 5625 5626 // If we only have one input vector, we don't need to do any concatenation. 5627 if (N->getNumOperands() == 1) 5628 return N->getOperand(0); 5629 5630 return SDValue(); 5631} 5632 5633SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5634 return SDValue(); 5635 5636 EVT VT = N->getValueType(0); 5637 unsigned NumElts = VT.getVectorNumElements(); 5638 5639 SDValue N0 = N->getOperand(0); 5640 5641 assert(N0.getValueType().getVectorNumElements() == NumElts && 5642 "Vector shuffle must be normalized in DAG"); 5643 5644 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5645 5646 // If it is a splat, check if the argument vector is a build_vector with 5647 // all scalar elements the same. 5648 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5649 SDNode *V = N0.getNode(); 5650 5651 5652 // If this is a bit convert that changes the element type of the vector but 5653 // not the number of vector elements, look through it. Be careful not to 5654 // look though conversions that change things like v4f32 to v2f64. 5655 if (V->getOpcode() == ISD::BIT_CONVERT) { 5656 SDValue ConvInput = V->getOperand(0); 5657 if (ConvInput.getValueType().isVector() && 5658 ConvInput.getValueType().getVectorNumElements() == NumElts) 5659 V = ConvInput.getNode(); 5660 } 5661 5662 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5663 unsigned NumElems = V->getNumOperands(); 5664 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5665 if (NumElems > BaseIdx) { 5666 SDValue Base; 5667 bool AllSame = true; 5668 for (unsigned i = 0; i != NumElems; ++i) { 5669 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5670 Base = V->getOperand(i); 5671 break; 5672 } 5673 } 5674 // Splat of <u, u, u, u>, return <u, u, u, u> 5675 if (!Base.getNode()) 5676 return N0; 5677 for (unsigned i = 0; i != NumElems; ++i) { 5678 if (V->getOperand(i) != Base) { 5679 AllSame = false; 5680 break; 5681 } 5682 } 5683 // Splat of <x, x, x, x>, return <x, x, x, x> 5684 if (AllSame) 5685 return N0; 5686 } 5687 } 5688 } 5689 return SDValue(); 5690} 5691 5692/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5693/// an AND to a vector_shuffle with the destination vector and a zero vector. 5694/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5695/// vector_shuffle V, Zero, <0, 4, 2, 4> 5696SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5697 EVT VT = N->getValueType(0); 5698 DebugLoc dl = N->getDebugLoc(); 5699 SDValue LHS = N->getOperand(0); 5700 SDValue RHS = N->getOperand(1); 5701 if (N->getOpcode() == ISD::AND) { 5702 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5703 RHS = RHS.getOperand(0); 5704 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5705 SmallVector<int, 8> Indices; 5706 unsigned NumElts = RHS.getNumOperands(); 5707 for (unsigned i = 0; i != NumElts; ++i) { 5708 SDValue Elt = RHS.getOperand(i); 5709 if (!isa<ConstantSDNode>(Elt)) 5710 return SDValue(); 5711 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5712 Indices.push_back(i); 5713 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5714 Indices.push_back(NumElts); 5715 else 5716 return SDValue(); 5717 } 5718 5719 // Let's see if the target supports this vector_shuffle. 5720 EVT RVT = RHS.getValueType(); 5721 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5722 return SDValue(); 5723 5724 // Return the new VECTOR_SHUFFLE node. 5725 EVT EltVT = RVT.getVectorElementType(); 5726 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5727 DAG.getConstant(0, EltVT)); 5728 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5729 RVT, &ZeroOps[0], ZeroOps.size()); 5730 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5731 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5732 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5733 } 5734 } 5735 5736 return SDValue(); 5737} 5738 5739/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5740SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5741 // After legalize, the target may be depending on adds and other 5742 // binary ops to provide legal ways to construct constants or other 5743 // things. Simplifying them may result in a loss of legality. 5744 if (LegalOperations) return SDValue(); 5745 5746 EVT VT = N->getValueType(0); 5747 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5748 5749 EVT EltType = VT.getVectorElementType(); 5750 SDValue LHS = N->getOperand(0); 5751 SDValue RHS = N->getOperand(1); 5752 SDValue Shuffle = XformToShuffleWithZero(N); 5753 if (Shuffle.getNode()) return Shuffle; 5754 5755 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5756 // this operation. 5757 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5758 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5759 SmallVector<SDValue, 8> Ops; 5760 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5761 SDValue LHSOp = LHS.getOperand(i); 5762 SDValue RHSOp = RHS.getOperand(i); 5763 // If these two elements can't be folded, bail out. 5764 if ((LHSOp.getOpcode() != ISD::UNDEF && 5765 LHSOp.getOpcode() != ISD::Constant && 5766 LHSOp.getOpcode() != ISD::ConstantFP) || 5767 (RHSOp.getOpcode() != ISD::UNDEF && 5768 RHSOp.getOpcode() != ISD::Constant && 5769 RHSOp.getOpcode() != ISD::ConstantFP)) 5770 break; 5771 5772 // Can't fold divide by zero. 5773 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5774 N->getOpcode() == ISD::FDIV) { 5775 if ((RHSOp.getOpcode() == ISD::Constant && 5776 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5777 (RHSOp.getOpcode() == ISD::ConstantFP && 5778 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5779 break; 5780 } 5781 5782 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5783 EltType, LHSOp, RHSOp)); 5784 AddToWorkList(Ops.back().getNode()); 5785 assert((Ops.back().getOpcode() == ISD::UNDEF || 5786 Ops.back().getOpcode() == ISD::Constant || 5787 Ops.back().getOpcode() == ISD::ConstantFP) && 5788 "Scalar binop didn't fold!"); 5789 } 5790 5791 if (Ops.size() == LHS.getNumOperands()) { 5792 EVT VT = LHS.getValueType(); 5793 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5794 &Ops[0], Ops.size()); 5795 } 5796 } 5797 5798 return SDValue(); 5799} 5800 5801SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5802 SDValue N1, SDValue N2){ 5803 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5804 5805 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5806 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5807 5808 // If we got a simplified select_cc node back from SimplifySelectCC, then 5809 // break it down into a new SETCC node, and a new SELECT node, and then return 5810 // the SELECT node, since we were called with a SELECT node. 5811 if (SCC.getNode()) { 5812 // Check to see if we got a select_cc back (to turn into setcc/select). 5813 // Otherwise, just return whatever node we got back, like fabs. 5814 if (SCC.getOpcode() == ISD::SELECT_CC) { 5815 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5816 N0.getValueType(), 5817 SCC.getOperand(0), SCC.getOperand(1), 5818 SCC.getOperand(4)); 5819 AddToWorkList(SETCC.getNode()); 5820 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5821 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5822 } 5823 5824 return SCC; 5825 } 5826 return SDValue(); 5827} 5828 5829/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5830/// are the two values being selected between, see if we can simplify the 5831/// select. Callers of this should assume that TheSelect is deleted if this 5832/// returns true. As such, they should return the appropriate thing (e.g. the 5833/// node) back to the top-level of the DAG combiner loop to avoid it being 5834/// looked at. 5835bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5836 SDValue RHS) { 5837 5838 // If this is a select from two identical things, try to pull the operation 5839 // through the select. 5840 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5841 // If this is a load and the token chain is identical, replace the select 5842 // of two loads with a load through a select of the address to load from. 5843 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5844 // constants have been dropped into the constant pool. 5845 if (LHS.getOpcode() == ISD::LOAD && 5846 // Do not let this transformation reduce the number of volatile loads. 5847 !cast<LoadSDNode>(LHS)->isVolatile() && 5848 !cast<LoadSDNode>(RHS)->isVolatile() && 5849 // Token chains must be identical. 5850 LHS.getOperand(0) == RHS.getOperand(0)) { 5851 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5852 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5853 5854 // If this is an EXTLOAD, the VT's must match. 5855 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5856 // FIXME: this discards src value information. This is 5857 // over-conservative. It would be beneficial to be able to remember 5858 // both potential memory locations. Since we are discarding 5859 // src value info, don't do the transformation if the memory 5860 // locations are not in the default address space. 5861 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0; 5862 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) { 5863 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType())) 5864 LLDAddrSpace = PT->getAddressSpace(); 5865 } 5866 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) { 5867 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType())) 5868 RLDAddrSpace = PT->getAddressSpace(); 5869 } 5870 SDValue Addr; 5871 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) { 5872 if (TheSelect->getOpcode() == ISD::SELECT) { 5873 // Check that the condition doesn't reach either load. If so, folding 5874 // this will induce a cycle into the DAG. 5875 if ((!LLD->hasAnyUseOfValue(1) || 5876 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 5877 (!RLD->hasAnyUseOfValue(1) || 5878 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 5879 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5880 LLD->getBasePtr().getValueType(), 5881 TheSelect->getOperand(0), LLD->getBasePtr(), 5882 RLD->getBasePtr()); 5883 } 5884 } else { 5885 // Check that the condition doesn't reach either load. If so, folding 5886 // this will induce a cycle into the DAG. 5887 if ((!LLD->hasAnyUseOfValue(1) || 5888 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5889 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 5890 (!RLD->hasAnyUseOfValue(1) || 5891 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5892 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 5893 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5894 LLD->getBasePtr().getValueType(), 5895 TheSelect->getOperand(0), 5896 TheSelect->getOperand(1), 5897 LLD->getBasePtr(), RLD->getBasePtr(), 5898 TheSelect->getOperand(4)); 5899 } 5900 } 5901 } 5902 5903 if (Addr.getNode()) { 5904 SDValue Load; 5905 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5906 Load = DAG.getLoad(TheSelect->getValueType(0), 5907 TheSelect->getDebugLoc(), 5908 LLD->getChain(), 5909 Addr, 0, 0, 5910 LLD->isVolatile(), 5911 LLD->isNonTemporal(), 5912 LLD->getAlignment()); 5913 } else { 5914 Load = DAG.getExtLoad(LLD->getExtensionType(), 5915 TheSelect->getDebugLoc(), 5916 TheSelect->getValueType(0), 5917 LLD->getChain(), Addr, 0, 0, 5918 LLD->getMemoryVT(), 5919 LLD->isVolatile(), 5920 LLD->isNonTemporal(), 5921 LLD->getAlignment()); 5922 } 5923 5924 // Users of the select now use the result of the load. 5925 CombineTo(TheSelect, Load); 5926 5927 // Users of the old loads now use the new load's chain. We know the 5928 // old-load value is dead now. 5929 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5930 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5931 return true; 5932 } 5933 } 5934 } 5935 } 5936 5937 return false; 5938} 5939 5940/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5941/// where 'cond' is the comparison specified by CC. 5942SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5943 SDValue N2, SDValue N3, 5944 ISD::CondCode CC, bool NotExtCompare) { 5945 // (x ? y : y) -> y. 5946 if (N2 == N3) return N2; 5947 5948 EVT VT = N2.getValueType(); 5949 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5950 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5951 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5952 5953 // Determine if the condition we're dealing with is constant 5954 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5955 N0, N1, CC, DL, false); 5956 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5957 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5958 5959 // fold select_cc true, x, y -> x 5960 if (SCCC && !SCCC->isNullValue()) 5961 return N2; 5962 // fold select_cc false, x, y -> y 5963 if (SCCC && SCCC->isNullValue()) 5964 return N3; 5965 5966 // Check to see if we can simplify the select into an fabs node 5967 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5968 // Allow either -0.0 or 0.0 5969 if (CFP->getValueAPF().isZero()) { 5970 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5971 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5972 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5973 N2 == N3.getOperand(0)) 5974 return DAG.getNode(ISD::FABS, DL, VT, N0); 5975 5976 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5977 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5978 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5979 N2.getOperand(0) == N3) 5980 return DAG.getNode(ISD::FABS, DL, VT, N3); 5981 } 5982 } 5983 5984 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5985 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5986 // in it. This is a win when the constant is not otherwise available because 5987 // it replaces two constant pool loads with one. We only do this if the FP 5988 // type is known to be legal, because if it isn't, then we are before legalize 5989 // types an we want the other legalization to happen first (e.g. to avoid 5990 // messing with soft float) and if the ConstantFP is not legal, because if 5991 // it is legal, we may not need to store the FP constant in a constant pool. 5992 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5993 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5994 if (TLI.isTypeLegal(N2.getValueType()) && 5995 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5996 TargetLowering::Legal) && 5997 // If both constants have multiple uses, then we won't need to do an 5998 // extra load, they are likely around in registers for other users. 5999 (TV->hasOneUse() || FV->hasOneUse())) { 6000 Constant *Elts[] = { 6001 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6002 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6003 }; 6004 const Type *FPTy = Elts[0]->getType(); 6005 const TargetData &TD = *TLI.getTargetData(); 6006 6007 // Create a ConstantArray of the two constants. 6008 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6009 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6010 TD.getPrefTypeAlignment(FPTy)); 6011 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6012 6013 // Get the offsets to the 0 and 1 element of the array so that we can 6014 // select between them. 6015 SDValue Zero = DAG.getIntPtrConstant(0); 6016 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6017 SDValue One = DAG.getIntPtrConstant(EltSize); 6018 6019 SDValue Cond = DAG.getSetCC(DL, 6020 TLI.getSetCCResultType(N0.getValueType()), 6021 N0, N1, CC); 6022 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6023 Cond, One, Zero); 6024 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6025 CstOffset); 6026 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6027 PseudoSourceValue::getConstantPool(), 0, false, 6028 false, Alignment); 6029 6030 } 6031 } 6032 6033 // Check to see if we can perform the "gzip trick", transforming 6034 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6035 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6036 N0.getValueType().isInteger() && 6037 N2.getValueType().isInteger() && 6038 (N1C->isNullValue() || // (a < 0) ? b : 0 6039 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6040 EVT XType = N0.getValueType(); 6041 EVT AType = N2.getValueType(); 6042 if (XType.bitsGE(AType)) { 6043 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6044 // single-bit constant. 6045 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6046 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6047 ShCtV = XType.getSizeInBits()-ShCtV-1; 6048 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6049 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6050 XType, N0, ShCt); 6051 AddToWorkList(Shift.getNode()); 6052 6053 if (XType.bitsGT(AType)) { 6054 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6055 AddToWorkList(Shift.getNode()); 6056 } 6057 6058 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6059 } 6060 6061 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6062 XType, N0, 6063 DAG.getConstant(XType.getSizeInBits()-1, 6064 getShiftAmountTy())); 6065 AddToWorkList(Shift.getNode()); 6066 6067 if (XType.bitsGT(AType)) { 6068 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6069 AddToWorkList(Shift.getNode()); 6070 } 6071 6072 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6073 } 6074 } 6075 6076 // fold select C, 16, 0 -> shl C, 4 6077 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6078 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6079 6080 // If the caller doesn't want us to simplify this into a zext of a compare, 6081 // don't do it. 6082 if (NotExtCompare && N2C->getAPIntValue() == 1) 6083 return SDValue(); 6084 6085 // Get a SetCC of the condition 6086 // FIXME: Should probably make sure that setcc is legal if we ever have a 6087 // target where it isn't. 6088 SDValue Temp, SCC; 6089 // cast from setcc result type to select result type 6090 if (LegalTypes) { 6091 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6092 N0, N1, CC); 6093 if (N2.getValueType().bitsLT(SCC.getValueType())) 6094 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6095 else 6096 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6097 N2.getValueType(), SCC); 6098 } else { 6099 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6100 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6101 N2.getValueType(), SCC); 6102 } 6103 6104 AddToWorkList(SCC.getNode()); 6105 AddToWorkList(Temp.getNode()); 6106 6107 if (N2C->getAPIntValue() == 1) 6108 return Temp; 6109 6110 // shl setcc result by log2 n2c 6111 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6112 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6113 getShiftAmountTy())); 6114 } 6115 6116 // Check to see if this is the equivalent of setcc 6117 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6118 // otherwise, go ahead with the folds. 6119 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6120 EVT XType = N0.getValueType(); 6121 if (!LegalOperations || 6122 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6123 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6124 if (Res.getValueType() != VT) 6125 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6126 return Res; 6127 } 6128 6129 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6130 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6131 (!LegalOperations || 6132 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6133 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6134 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6135 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6136 getShiftAmountTy())); 6137 } 6138 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6139 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6140 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6141 XType, DAG.getConstant(0, XType), N0); 6142 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6143 return DAG.getNode(ISD::SRL, DL, XType, 6144 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6145 DAG.getConstant(XType.getSizeInBits()-1, 6146 getShiftAmountTy())); 6147 } 6148 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6149 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6150 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6151 DAG.getConstant(XType.getSizeInBits()-1, 6152 getShiftAmountTy())); 6153 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6154 } 6155 } 6156 6157 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6158 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6159 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6160 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6161 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6162 EVT XType = N0.getValueType(); 6163 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6164 DAG.getConstant(XType.getSizeInBits()-1, 6165 getShiftAmountTy())); 6166 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6167 N0, Shift); 6168 AddToWorkList(Shift.getNode()); 6169 AddToWorkList(Add.getNode()); 6170 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6171 } 6172 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6173 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6174 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6175 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6176 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6177 EVT XType = N0.getValueType(); 6178 if (SubC->isNullValue() && XType.isInteger()) { 6179 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6180 N0, 6181 DAG.getConstant(XType.getSizeInBits()-1, 6182 getShiftAmountTy())); 6183 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6184 XType, N0, Shift); 6185 AddToWorkList(Shift.getNode()); 6186 AddToWorkList(Add.getNode()); 6187 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6188 } 6189 } 6190 } 6191 6192 return SDValue(); 6193} 6194 6195/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6196SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6197 SDValue N1, ISD::CondCode Cond, 6198 DebugLoc DL, bool foldBooleans) { 6199 TargetLowering::DAGCombinerInfo 6200 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6201 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6202} 6203 6204/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6205/// return a DAG expression to select that will generate the same value by 6206/// multiplying by a magic number. See: 6207/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6208SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6209 std::vector<SDNode*> Built; 6210 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6211 6212 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6213 ii != ee; ++ii) 6214 AddToWorkList(*ii); 6215 return S; 6216} 6217 6218/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6219/// return a DAG expression to select that will generate the same value by 6220/// multiplying by a magic number. See: 6221/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6222SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6223 std::vector<SDNode*> Built; 6224 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6225 6226 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6227 ii != ee; ++ii) 6228 AddToWorkList(*ii); 6229 return S; 6230} 6231 6232/// FindBaseOffset - Return true if base is a frame index, which is known not 6233// to alias with anything but itself. Provides base object and offset as results. 6234static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6235 GlobalValue *&GV, void *&CV) { 6236 // Assume it is a primitive operation. 6237 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6238 6239 // If it's an adding a simple constant then integrate the offset. 6240 if (Base.getOpcode() == ISD::ADD) { 6241 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6242 Base = Base.getOperand(0); 6243 Offset += C->getZExtValue(); 6244 } 6245 } 6246 6247 // Return the underlying GlobalValue, and update the Offset. Return false 6248 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6249 // by multiple nodes with different offsets. 6250 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6251 GV = G->getGlobal(); 6252 Offset += G->getOffset(); 6253 return false; 6254 } 6255 6256 // Return the underlying Constant value, and update the Offset. Return false 6257 // for ConstantSDNodes since the same constant pool entry may be represented 6258 // by multiple nodes with different offsets. 6259 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6260 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6261 : (void *)C->getConstVal(); 6262 Offset += C->getOffset(); 6263 return false; 6264 } 6265 // If it's any of the following then it can't alias with anything but itself. 6266 return isa<FrameIndexSDNode>(Base); 6267} 6268 6269/// isAlias - Return true if there is any possibility that the two addresses 6270/// overlap. 6271bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6272 const Value *SrcValue1, int SrcValueOffset1, 6273 unsigned SrcValueAlign1, 6274 SDValue Ptr2, int64_t Size2, 6275 const Value *SrcValue2, int SrcValueOffset2, 6276 unsigned SrcValueAlign2) const { 6277 // If they are the same then they must be aliases. 6278 if (Ptr1 == Ptr2) return true; 6279 6280 // Gather base node and offset information. 6281 SDValue Base1, Base2; 6282 int64_t Offset1, Offset2; 6283 GlobalValue *GV1, *GV2; 6284 void *CV1, *CV2; 6285 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6286 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6287 6288 // If they have a same base address then check to see if they overlap. 6289 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6290 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6291 6292 // If we know what the bases are, and they aren't identical, then we know they 6293 // cannot alias. 6294 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6295 return false; 6296 6297 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6298 // compared to the size and offset of the access, we may be able to prove they 6299 // do not alias. This check is conservative for now to catch cases created by 6300 // splitting vector types. 6301 if ((SrcValueAlign1 == SrcValueAlign2) && 6302 (SrcValueOffset1 != SrcValueOffset2) && 6303 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6304 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6305 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6306 6307 // There is no overlap between these relatively aligned accesses of similar 6308 // size, return no alias. 6309 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6310 return false; 6311 } 6312 6313 if (CombinerGlobalAA) { 6314 // Use alias analysis information. 6315 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6316 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6317 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6318 AliasAnalysis::AliasResult AAResult = 6319 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6320 if (AAResult == AliasAnalysis::NoAlias) 6321 return false; 6322 } 6323 6324 // Otherwise we have to assume they alias. 6325 return true; 6326} 6327 6328/// FindAliasInfo - Extracts the relevant alias information from the memory 6329/// node. Returns true if the operand was a load. 6330bool DAGCombiner::FindAliasInfo(SDNode *N, 6331 SDValue &Ptr, int64_t &Size, 6332 const Value *&SrcValue, 6333 int &SrcValueOffset, 6334 unsigned &SrcValueAlign) const { 6335 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6336 Ptr = LD->getBasePtr(); 6337 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6338 SrcValue = LD->getSrcValue(); 6339 SrcValueOffset = LD->getSrcValueOffset(); 6340 SrcValueAlign = LD->getOriginalAlignment(); 6341 return true; 6342 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6343 Ptr = ST->getBasePtr(); 6344 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6345 SrcValue = ST->getSrcValue(); 6346 SrcValueOffset = ST->getSrcValueOffset(); 6347 SrcValueAlign = ST->getOriginalAlignment(); 6348 } else { 6349 llvm_unreachable("FindAliasInfo expected a memory operand"); 6350 } 6351 6352 return false; 6353} 6354 6355/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6356/// looking for aliasing nodes and adding them to the Aliases vector. 6357void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6358 SmallVector<SDValue, 8> &Aliases) { 6359 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6360 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 6361 6362 // Get alias information for node. 6363 SDValue Ptr; 6364 int64_t Size; 6365 const Value *SrcValue; 6366 int SrcValueOffset; 6367 unsigned SrcValueAlign; 6368 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 6369 SrcValueAlign); 6370 6371 // Starting off. 6372 Chains.push_back(OriginalChain); 6373 unsigned Depth = 0; 6374 6375 // Look at each chain and determine if it is an alias. If so, add it to the 6376 // aliases list. If not, then continue up the chain looking for the next 6377 // candidate. 6378 while (!Chains.empty()) { 6379 SDValue Chain = Chains.back(); 6380 Chains.pop_back(); 6381 6382 // For TokenFactor nodes, look at each operand and only continue up the 6383 // chain until we find two aliases. If we've seen two aliases, assume we'll 6384 // find more and revert to original chain since the xform is unlikely to be 6385 // profitable. 6386 // 6387 // FIXME: The depth check could be made to return the last non-aliasing 6388 // chain we found before we hit a tokenfactor rather than the original 6389 // chain. 6390 if (Depth > 6 || Aliases.size() == 2) { 6391 Aliases.clear(); 6392 Aliases.push_back(OriginalChain); 6393 break; 6394 } 6395 6396 // Don't bother if we've been before. 6397 if (!Visited.insert(Chain.getNode())) 6398 continue; 6399 6400 switch (Chain.getOpcode()) { 6401 case ISD::EntryToken: 6402 // Entry token is ideal chain operand, but handled in FindBetterChain. 6403 break; 6404 6405 case ISD::LOAD: 6406 case ISD::STORE: { 6407 // Get alias information for Chain. 6408 SDValue OpPtr; 6409 int64_t OpSize; 6410 const Value *OpSrcValue; 6411 int OpSrcValueOffset; 6412 unsigned OpSrcValueAlign; 6413 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6414 OpSrcValue, OpSrcValueOffset, 6415 OpSrcValueAlign); 6416 6417 // If chain is alias then stop here. 6418 if (!(IsLoad && IsOpLoad) && 6419 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 6420 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 6421 OpSrcValueAlign)) { 6422 Aliases.push_back(Chain); 6423 } else { 6424 // Look further up the chain. 6425 Chains.push_back(Chain.getOperand(0)); 6426 ++Depth; 6427 } 6428 break; 6429 } 6430 6431 case ISD::TokenFactor: 6432 // We have to check each of the operands of the token factor for "small" 6433 // token factors, so we queue them up. Adding the operands to the queue 6434 // (stack) in reverse order maintains the original order and increases the 6435 // likelihood that getNode will find a matching token factor (CSE.) 6436 if (Chain.getNumOperands() > 16) { 6437 Aliases.push_back(Chain); 6438 break; 6439 } 6440 for (unsigned n = Chain.getNumOperands(); n;) 6441 Chains.push_back(Chain.getOperand(--n)); 6442 ++Depth; 6443 break; 6444 6445 default: 6446 // For all other instructions we will just have to take what we can get. 6447 Aliases.push_back(Chain); 6448 break; 6449 } 6450 } 6451} 6452 6453/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6454/// for a better chain (aliasing node.) 6455SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6456 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6457 6458 // Accumulate all the aliases to this node. 6459 GatherAllAliases(N, OldChain, Aliases); 6460 6461 if (Aliases.size() == 0) { 6462 // If no operands then chain to entry token. 6463 return DAG.getEntryNode(); 6464 } else if (Aliases.size() == 1) { 6465 // If a single operand then chain to it. We don't need to revisit it. 6466 return Aliases[0]; 6467 } 6468 6469 // Construct a custom tailored token factor. 6470 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6471 &Aliases[0], Aliases.size()); 6472} 6473 6474// SelectionDAG::Combine - This is the entry point for the file. 6475// 6476void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6477 CodeGenOpt::Level OptLevel) { 6478 /// run - This is the main entry point to this class. 6479 /// 6480 DAGCombiner(*this, AA, OptLevel).Run(Level); 6481} 6482