DAGCombiner.cpp revision 4150d83abe90a5da4ddf86433b7bf4329acfa57c
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetFrameInfo.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Support/Compiler.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include <algorithm> 38#include <set> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class VISIBILITY_HIDDEN DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 std::vector<SDNode*> WorkList; 67 68 // AA - Used for DAG load/store alias analysis. 69 AliasAnalysis &AA; 70 71 /// AddUsersToWorkList - When an instruction is simplified, add all users of 72 /// the instruction to the work lists because they might get more simplified 73 /// now. 74 /// 75 void AddUsersToWorkList(SDNode *N) { 76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 77 UI != UE; ++UI) 78 AddToWorkList(*UI); 79 } 80 81 /// visit - call the node-specific routine that knows how to fold each 82 /// particular type of node. 83 SDValue visit(SDNode *N); 84 85 public: 86 /// AddToWorkList - Add to the work list making sure it's instance is at the 87 /// the back (next to be processed.) 88 void AddToWorkList(SDNode *N) { 89 removeFromWorkList(N); 90 WorkList.push_back(N); 91 } 92 93 /// removeFromWorkList - remove all instances of N from the worklist. 94 /// 95 void removeFromWorkList(SDNode *N) { 96 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 97 WorkList.end()); 98 } 99 100 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 101 bool AddTo = true); 102 103 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 104 return CombineTo(N, &Res, 1, AddTo); 105 } 106 107 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 108 bool AddTo = true) { 109 SDValue To[] = { Res0, Res1 }; 110 return CombineTo(N, To, 2, AddTo); 111 } 112 113 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 114 115 private: 116 117 /// SimplifyDemandedBits - Check the specified integer node value to see if 118 /// it can be simplified or if things it uses can be simplified by bit 119 /// propagation. If so, return true. 120 bool SimplifyDemandedBits(SDValue Op) { 121 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 122 return SimplifyDemandedBits(Op, Demanded); 123 } 124 125 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 126 127 bool CombineToPreIndexedLoadStore(SDNode *N); 128 bool CombineToPostIndexedLoadStore(SDNode *N); 129 130 131 /// combine - call the node-specific routine that knows how to fold each 132 /// particular type of node. If that doesn't do anything, try the 133 /// target-specific DAG combines. 134 SDValue combine(SDNode *N); 135 136 // Visitation implementation - Implement dag node combining for different 137 // node types. The semantics are as follows: 138 // Return Value: 139 // SDValue.getNode() == 0 - No change was made 140 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 141 // otherwise - N should be replaced by the returned Operand. 142 // 143 SDValue visitTokenFactor(SDNode *N); 144 SDValue visitMERGE_VALUES(SDNode *N); 145 SDValue visitADD(SDNode *N); 146 SDValue visitSUB(SDNode *N); 147 SDValue visitADDC(SDNode *N); 148 SDValue visitADDE(SDNode *N); 149 SDValue visitMUL(SDNode *N); 150 SDValue visitSDIV(SDNode *N); 151 SDValue visitUDIV(SDNode *N); 152 SDValue visitSREM(SDNode *N); 153 SDValue visitUREM(SDNode *N); 154 SDValue visitMULHU(SDNode *N); 155 SDValue visitMULHS(SDNode *N); 156 SDValue visitSMUL_LOHI(SDNode *N); 157 SDValue visitUMUL_LOHI(SDNode *N); 158 SDValue visitSDIVREM(SDNode *N); 159 SDValue visitUDIVREM(SDNode *N); 160 SDValue visitAND(SDNode *N); 161 SDValue visitOR(SDNode *N); 162 SDValue visitXOR(SDNode *N); 163 SDValue SimplifyVBinOp(SDNode *N); 164 SDValue visitSHL(SDNode *N); 165 SDValue visitSRA(SDNode *N); 166 SDValue visitSRL(SDNode *N); 167 SDValue visitCTLZ(SDNode *N); 168 SDValue visitCTTZ(SDNode *N); 169 SDValue visitCTPOP(SDNode *N); 170 SDValue visitSELECT(SDNode *N); 171 SDValue visitSELECT_CC(SDNode *N); 172 SDValue visitSETCC(SDNode *N); 173 SDValue visitSIGN_EXTEND(SDNode *N); 174 SDValue visitZERO_EXTEND(SDNode *N); 175 SDValue visitANY_EXTEND(SDNode *N); 176 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 177 SDValue visitTRUNCATE(SDNode *N); 178 SDValue visitBIT_CONVERT(SDNode *N); 179 SDValue visitBUILD_PAIR(SDNode *N); 180 SDValue visitFADD(SDNode *N); 181 SDValue visitFSUB(SDNode *N); 182 SDValue visitFMUL(SDNode *N); 183 SDValue visitFDIV(SDNode *N); 184 SDValue visitFREM(SDNode *N); 185 SDValue visitFCOPYSIGN(SDNode *N); 186 SDValue visitSINT_TO_FP(SDNode *N); 187 SDValue visitUINT_TO_FP(SDNode *N); 188 SDValue visitFP_TO_SINT(SDNode *N); 189 SDValue visitFP_TO_UINT(SDNode *N); 190 SDValue visitFP_ROUND(SDNode *N); 191 SDValue visitFP_ROUND_INREG(SDNode *N); 192 SDValue visitFP_EXTEND(SDNode *N); 193 SDValue visitFNEG(SDNode *N); 194 SDValue visitFABS(SDNode *N); 195 SDValue visitBRCOND(SDNode *N); 196 SDValue visitBR_CC(SDNode *N); 197 SDValue visitLOAD(SDNode *N); 198 SDValue visitSTORE(SDNode *N); 199 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 200 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 201 SDValue visitBUILD_VECTOR(SDNode *N); 202 SDValue visitCONCAT_VECTORS(SDNode *N); 203 SDValue visitVECTOR_SHUFFLE(SDNode *N); 204 205 SDValue XformToShuffleWithZero(SDNode *N); 206 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 207 208 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 209 210 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 211 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 212 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 213 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 214 SDValue N3, ISD::CondCode CC, 215 bool NotExtCompare = false); 216 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 217 DebugLoc DL, bool foldBooleans = true); 218 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 219 unsigned HiOp); 220 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 221 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 222 SDValue BuildSDIV(SDNode *N); 223 SDValue BuildUDIV(SDNode *N); 224 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 225 SDValue ReduceLoadWidth(SDNode *N); 226 SDValue ReduceLoadOpStoreWidth(SDNode *N); 227 228 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 229 230 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 231 /// looking for aliasing nodes and adding them to the Aliases vector. 232 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 233 SmallVector<SDValue, 8> &Aliases); 234 235 /// isAlias - Return true if there is any possibility that the two addresses 236 /// overlap. 237 bool isAlias(SDValue Ptr1, int64_t Size1, 238 const Value *SrcValue1, int SrcValueOffset1, 239 SDValue Ptr2, int64_t Size2, 240 const Value *SrcValue2, int SrcValueOffset2) const; 241 242 /// FindAliasInfo - Extracts the relevant alias information from the memory 243 /// node. Returns true if the operand was a load. 244 bool FindAliasInfo(SDNode *N, 245 SDValue &Ptr, int64_t &Size, 246 const Value *&SrcValue, int &SrcValueOffset) const; 247 248 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 249 /// looking for a better chain (aliasing node.) 250 SDValue FindBetterChain(SDNode *N, SDValue Chain); 251 252 /// getShiftAmountTy - Returns a type large enough to hold any valid 253 /// shift amount - before type legalization these can be huge. 254 MVT getShiftAmountTy() { 255 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 256 } 257 258public: 259 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 260 : DAG(D), 261 TLI(D.getTargetLoweringInfo()), 262 Level(Unrestricted), 263 OptLevel(OL), 264 LegalOperations(false), 265 LegalTypes(false), 266 AA(A) {} 267 268 /// Run - runs the dag combiner on all nodes in the work list 269 void Run(CombineLevel AtLevel); 270 }; 271} 272 273 274namespace { 275/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 276/// nodes from the worklist. 277class VISIBILITY_HIDDEN WorkListRemover : 278 public SelectionDAG::DAGUpdateListener { 279 DAGCombiner &DC; 280public: 281 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 282 283 virtual void NodeDeleted(SDNode *N, SDNode *E) { 284 DC.removeFromWorkList(N); 285 } 286 287 virtual void NodeUpdated(SDNode *N) { 288 // Ignore updates. 289 } 290}; 291} 292 293//===----------------------------------------------------------------------===// 294// TargetLowering::DAGCombinerInfo implementation 295//===----------------------------------------------------------------------===// 296 297void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 298 ((DAGCombiner*)DC)->AddToWorkList(N); 299} 300 301SDValue TargetLowering::DAGCombinerInfo:: 302CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 303 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 304} 305 306SDValue TargetLowering::DAGCombinerInfo:: 307CombineTo(SDNode *N, SDValue Res, bool AddTo) { 308 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 309} 310 311 312SDValue TargetLowering::DAGCombinerInfo:: 313CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 314 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 315} 316 317void TargetLowering::DAGCombinerInfo:: 318CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 319 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 320} 321 322//===----------------------------------------------------------------------===// 323// Helper Functions 324//===----------------------------------------------------------------------===// 325 326/// isNegatibleForFree - Return 1 if we can compute the negated form of the 327/// specified expression for the same cost as the expression itself, or 2 if we 328/// can compute the negated form more cheaply than the expression itself. 329static char isNegatibleForFree(SDValue Op, bool LegalOperations, 330 unsigned Depth = 0) { 331 // No compile time optimizations on this type. 332 if (Op.getValueType() == MVT::ppcf128) 333 return 0; 334 335 // fneg is removable even if it has multiple uses. 336 if (Op.getOpcode() == ISD::FNEG) return 2; 337 338 // Don't allow anything with multiple uses. 339 if (!Op.hasOneUse()) return 0; 340 341 // Don't recurse exponentially. 342 if (Depth > 6) return 0; 343 344 switch (Op.getOpcode()) { 345 default: return false; 346 case ISD::ConstantFP: 347 // Don't invert constant FP values after legalize. The negated constant 348 // isn't necessarily legal. 349 return LegalOperations ? 0 : 1; 350 case ISD::FADD: 351 // FIXME: determine better conditions for this xform. 352 if (!UnsafeFPMath) return 0; 353 354 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 355 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 356 return V; 357 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 358 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 359 case ISD::FSUB: 360 // We can't turn -(A-B) into B-A when we honor signed zeros. 361 if (!UnsafeFPMath) return 0; 362 363 // fold (fneg (fsub A, B)) -> (fsub B, A) 364 return 1; 365 366 case ISD::FMUL: 367 case ISD::FDIV: 368 if (HonorSignDependentRoundingFPMath()) return 0; 369 370 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 371 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 372 return V; 373 374 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 375 376 case ISD::FP_EXTEND: 377 case ISD::FP_ROUND: 378 case ISD::FSIN: 379 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 380 } 381} 382 383/// GetNegatedExpression - If isNegatibleForFree returns true, this function 384/// returns the newly negated expression. 385static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 386 bool LegalOperations, unsigned Depth = 0) { 387 // fneg is removable even if it has multiple uses. 388 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 389 390 // Don't allow anything with multiple uses. 391 assert(Op.hasOneUse() && "Unknown reuse!"); 392 393 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 394 switch (Op.getOpcode()) { 395 default: assert(0 && "Unknown code"); 396 case ISD::ConstantFP: { 397 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 398 V.changeSign(); 399 return DAG.getConstantFP(V, Op.getValueType()); 400 } 401 case ISD::FADD: 402 // FIXME: determine better conditions for this xform. 403 assert(UnsafeFPMath); 404 405 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 406 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 407 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 408 GetNegatedExpression(Op.getOperand(0), DAG, 409 LegalOperations, Depth+1), 410 Op.getOperand(1)); 411 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 412 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 413 GetNegatedExpression(Op.getOperand(1), DAG, 414 LegalOperations, Depth+1), 415 Op.getOperand(0)); 416 case ISD::FSUB: 417 // We can't turn -(A-B) into B-A when we honor signed zeros. 418 assert(UnsafeFPMath); 419 420 // fold (fneg (fsub 0, B)) -> B 421 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 422 if (N0CFP->getValueAPF().isZero()) 423 return Op.getOperand(1); 424 425 // fold (fneg (fsub A, B)) -> (fsub B, A) 426 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 427 Op.getOperand(1), Op.getOperand(0)); 428 429 case ISD::FMUL: 430 case ISD::FDIV: 431 assert(!HonorSignDependentRoundingFPMath()); 432 433 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 434 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 435 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 436 GetNegatedExpression(Op.getOperand(0), DAG, 437 LegalOperations, Depth+1), 438 Op.getOperand(1)); 439 440 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 441 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 442 Op.getOperand(0), 443 GetNegatedExpression(Op.getOperand(1), DAG, 444 LegalOperations, Depth+1)); 445 446 case ISD::FP_EXTEND: 447 case ISD::FSIN: 448 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 449 GetNegatedExpression(Op.getOperand(0), DAG, 450 LegalOperations, Depth+1)); 451 case ISD::FP_ROUND: 452 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1), 455 Op.getOperand(1)); 456 } 457} 458 459 460// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 461// that selects between the values 1 and 0, making it equivalent to a setcc. 462// Also, set the incoming LHS, RHS, and CC references to the appropriate 463// nodes based on the type of node we are checking. This simplifies life a 464// bit for the callers. 465static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 466 SDValue &CC) { 467 if (N.getOpcode() == ISD::SETCC) { 468 LHS = N.getOperand(0); 469 RHS = N.getOperand(1); 470 CC = N.getOperand(2); 471 return true; 472 } 473 if (N.getOpcode() == ISD::SELECT_CC && 474 N.getOperand(2).getOpcode() == ISD::Constant && 475 N.getOperand(3).getOpcode() == ISD::Constant && 476 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 477 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 478 LHS = N.getOperand(0); 479 RHS = N.getOperand(1); 480 CC = N.getOperand(4); 481 return true; 482 } 483 return false; 484} 485 486// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 487// one use. If this is true, it allows the users to invert the operation for 488// free when it is profitable to do so. 489static bool isOneUseSetCC(SDValue N) { 490 SDValue N0, N1, N2; 491 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 492 return true; 493 return false; 494} 495 496SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 497 SDValue N0, SDValue N1) { 498 MVT VT = N0.getValueType(); 499 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 500 if (isa<ConstantSDNode>(N1)) { 501 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 502 SDValue OpNode = 503 DAG.FoldConstantArithmetic(Opc, VT, 504 cast<ConstantSDNode>(N0.getOperand(1)), 505 cast<ConstantSDNode>(N1)); 506 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 507 } else if (N0.hasOneUse()) { 508 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 509 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 510 N0.getOperand(0), N1); 511 AddToWorkList(OpNode.getNode()); 512 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 513 } 514 } 515 516 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 517 if (isa<ConstantSDNode>(N0)) { 518 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 519 SDValue OpNode = 520 DAG.FoldConstantArithmetic(Opc, VT, 521 cast<ConstantSDNode>(N1.getOperand(1)), 522 cast<ConstantSDNode>(N0)); 523 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 524 } else if (N1.hasOneUse()) { 525 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 526 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 527 N1.getOperand(0), N0); 528 AddToWorkList(OpNode.getNode()); 529 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 530 } 531 } 532 533 return SDValue(); 534} 535 536SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 537 bool AddTo) { 538 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 539 ++NodesCombined; 540 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 541 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 542 DOUT << " and " << NumTo-1 << " other values\n"; 543 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 544 assert(N->getValueType(i) == To[i].getValueType() && 545 "Cannot combine value to value of different type!")); 546 WorkListRemover DeadNodes(*this); 547 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 548 549 if (AddTo) { 550 // Push the new nodes and any users onto the worklist 551 for (unsigned i = 0, e = NumTo; i != e; ++i) { 552 if (To[i].getNode()) { 553 AddToWorkList(To[i].getNode()); 554 AddUsersToWorkList(To[i].getNode()); 555 } 556 } 557 } 558 559 // Finally, if the node is now dead, remove it from the graph. The node 560 // may not be dead if the replacement process recursively simplified to 561 // something else needing this node. 562 if (N->use_empty()) { 563 // Nodes can be reintroduced into the worklist. Make sure we do not 564 // process a node that has been replaced. 565 removeFromWorkList(N); 566 567 // Finally, since the node is now dead, remove it from the graph. 568 DAG.DeleteNode(N); 569 } 570 return SDValue(N, 0); 571} 572 573void 574DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 575 TLO) { 576 // Replace all uses. If any nodes become isomorphic to other nodes and 577 // are deleted, make sure to remove them from our worklist. 578 WorkListRemover DeadNodes(*this); 579 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 580 581 // Push the new node and any (possibly new) users onto the worklist. 582 AddToWorkList(TLO.New.getNode()); 583 AddUsersToWorkList(TLO.New.getNode()); 584 585 // Finally, if the node is now dead, remove it from the graph. The node 586 // may not be dead if the replacement process recursively simplified to 587 // something else needing this node. 588 if (TLO.Old.getNode()->use_empty()) { 589 removeFromWorkList(TLO.Old.getNode()); 590 591 // If the operands of this node are only used by the node, they will now 592 // be dead. Make sure to visit them first to delete dead nodes early. 593 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 594 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 595 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 596 597 DAG.DeleteNode(TLO.Old.getNode()); 598 } 599} 600 601/// SimplifyDemandedBits - Check the specified integer node value to see if 602/// it can be simplified or if things it uses can be simplified by bit 603/// propagation. If so, return true. 604bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 605 TargetLowering::TargetLoweringOpt TLO(DAG); 606 APInt KnownZero, KnownOne; 607 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 608 return false; 609 610 // Revisit the node. 611 AddToWorkList(Op.getNode()); 612 613 // Replace the old value with the new one. 614 ++NodesCombined; 615 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 616 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 617 DOUT << '\n'; 618 619 CommitTargetLoweringOpt(TLO); 620 return true; 621} 622 623//===----------------------------------------------------------------------===// 624// Main DAG Combiner implementation 625//===----------------------------------------------------------------------===// 626 627void DAGCombiner::Run(CombineLevel AtLevel) { 628 // set the instance variables, so that the various visit routines may use it. 629 Level = AtLevel; 630 LegalOperations = Level >= NoIllegalOperations; 631 LegalTypes = Level >= NoIllegalTypes; 632 633 // Add all the dag nodes to the worklist. 634 WorkList.reserve(DAG.allnodes_size()); 635 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 636 E = DAG.allnodes_end(); I != E; ++I) 637 WorkList.push_back(I); 638 639 // Create a dummy node (which is not added to allnodes), that adds a reference 640 // to the root node, preventing it from being deleted, and tracking any 641 // changes of the root. 642 HandleSDNode Dummy(DAG.getRoot()); 643 644 // The root of the dag may dangle to deleted nodes until the dag combiner is 645 // done. Set it to null to avoid confusion. 646 DAG.setRoot(SDValue()); 647 648 // while the worklist isn't empty, inspect the node on the end of it and 649 // try and combine it. 650 while (!WorkList.empty()) { 651 SDNode *N = WorkList.back(); 652 WorkList.pop_back(); 653 654 // If N has no uses, it is dead. Make sure to revisit all N's operands once 655 // N is deleted from the DAG, since they too may now be dead or may have a 656 // reduced number of uses, allowing other xforms. 657 if (N->use_empty() && N != &Dummy) { 658 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 659 AddToWorkList(N->getOperand(i).getNode()); 660 661 DAG.DeleteNode(N); 662 continue; 663 } 664 665 SDValue RV = combine(N); 666 667 if (RV.getNode() == 0) 668 continue; 669 670 ++NodesCombined; 671 672 // If we get back the same node we passed in, rather than a new node or 673 // zero, we know that the node must have defined multiple values and 674 // CombineTo was used. Since CombineTo takes care of the worklist 675 // mechanics for us, we have no work to do in this case. 676 if (RV.getNode() == N) 677 continue; 678 679 assert(N->getOpcode() != ISD::DELETED_NODE && 680 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 681 "Node was deleted but visit returned new node!"); 682 683 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 684 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 685 DOUT << '\n'; 686 WorkListRemover DeadNodes(*this); 687 if (N->getNumValues() == RV.getNode()->getNumValues()) 688 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 689 else { 690 assert(N->getValueType(0) == RV.getValueType() && 691 N->getNumValues() == 1 && "Type mismatch"); 692 SDValue OpV = RV; 693 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 694 } 695 696 // Push the new node and any users onto the worklist 697 AddToWorkList(RV.getNode()); 698 AddUsersToWorkList(RV.getNode()); 699 700 // Add any uses of the old node to the worklist in case this node is the 701 // last one that uses them. They may become dead after this node is 702 // deleted. 703 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 704 AddToWorkList(N->getOperand(i).getNode()); 705 706 // Finally, if the node is now dead, remove it from the graph. The node 707 // may not be dead if the replacement process recursively simplified to 708 // something else needing this node. 709 if (N->use_empty()) { 710 // Nodes can be reintroduced into the worklist. Make sure we do not 711 // process a node that has been replaced. 712 removeFromWorkList(N); 713 714 // Finally, since the node is now dead, remove it from the graph. 715 DAG.DeleteNode(N); 716 } 717 } 718 719 // If the root changed (e.g. it was a dead load, update the root). 720 DAG.setRoot(Dummy.getValue()); 721} 722 723SDValue DAGCombiner::visit(SDNode *N) { 724 switch(N->getOpcode()) { 725 default: break; 726 case ISD::TokenFactor: return visitTokenFactor(N); 727 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 728 case ISD::ADD: return visitADD(N); 729 case ISD::SUB: return visitSUB(N); 730 case ISD::ADDC: return visitADDC(N); 731 case ISD::ADDE: return visitADDE(N); 732 case ISD::MUL: return visitMUL(N); 733 case ISD::SDIV: return visitSDIV(N); 734 case ISD::UDIV: return visitUDIV(N); 735 case ISD::SREM: return visitSREM(N); 736 case ISD::UREM: return visitUREM(N); 737 case ISD::MULHU: return visitMULHU(N); 738 case ISD::MULHS: return visitMULHS(N); 739 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 740 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 741 case ISD::SDIVREM: return visitSDIVREM(N); 742 case ISD::UDIVREM: return visitUDIVREM(N); 743 case ISD::AND: return visitAND(N); 744 case ISD::OR: return visitOR(N); 745 case ISD::XOR: return visitXOR(N); 746 case ISD::SHL: return visitSHL(N); 747 case ISD::SRA: return visitSRA(N); 748 case ISD::SRL: return visitSRL(N); 749 case ISD::CTLZ: return visitCTLZ(N); 750 case ISD::CTTZ: return visitCTTZ(N); 751 case ISD::CTPOP: return visitCTPOP(N); 752 case ISD::SELECT: return visitSELECT(N); 753 case ISD::SELECT_CC: return visitSELECT_CC(N); 754 case ISD::SETCC: return visitSETCC(N); 755 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 756 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 757 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 758 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 759 case ISD::TRUNCATE: return visitTRUNCATE(N); 760 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 761 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 762 case ISD::FADD: return visitFADD(N); 763 case ISD::FSUB: return visitFSUB(N); 764 case ISD::FMUL: return visitFMUL(N); 765 case ISD::FDIV: return visitFDIV(N); 766 case ISD::FREM: return visitFREM(N); 767 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 768 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 769 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 770 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 771 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 772 case ISD::FP_ROUND: return visitFP_ROUND(N); 773 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 774 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 775 case ISD::FNEG: return visitFNEG(N); 776 case ISD::FABS: return visitFABS(N); 777 case ISD::BRCOND: return visitBRCOND(N); 778 case ISD::BR_CC: return visitBR_CC(N); 779 case ISD::LOAD: return visitLOAD(N); 780 case ISD::STORE: return visitSTORE(N); 781 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 782 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 783 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 784 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 785 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 786 } 787 return SDValue(); 788} 789 790SDValue DAGCombiner::combine(SDNode *N) { 791 SDValue RV = visit(N); 792 793 // If nothing happened, try a target-specific DAG combine. 794 if (RV.getNode() == 0) { 795 assert(N->getOpcode() != ISD::DELETED_NODE && 796 "Node was deleted but visit returned NULL!"); 797 798 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 799 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 800 801 // Expose the DAG combiner to the target combiner impls. 802 TargetLowering::DAGCombinerInfo 803 DagCombineInfo(DAG, Level == Unrestricted, false, this); 804 805 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 806 } 807 } 808 809 // If N is a commutative binary node, try commuting it to enable more 810 // sdisel CSE. 811 if (RV.getNode() == 0 && 812 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 813 N->getNumValues() == 1) { 814 SDValue N0 = N->getOperand(0); 815 SDValue N1 = N->getOperand(1); 816 817 // Constant operands are canonicalized to RHS. 818 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 819 SDValue Ops[] = { N1, N0 }; 820 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 821 Ops, 2); 822 if (CSENode) 823 return SDValue(CSENode, 0); 824 } 825 } 826 827 return RV; 828} 829 830/// getInputChainForNode - Given a node, return its input chain if it has one, 831/// otherwise return a null sd operand. 832static SDValue getInputChainForNode(SDNode *N) { 833 if (unsigned NumOps = N->getNumOperands()) { 834 if (N->getOperand(0).getValueType() == MVT::Other) 835 return N->getOperand(0); 836 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 837 return N->getOperand(NumOps-1); 838 for (unsigned i = 1; i < NumOps-1; ++i) 839 if (N->getOperand(i).getValueType() == MVT::Other) 840 return N->getOperand(i); 841 } 842 return SDValue(); 843} 844 845SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 846 // If N has two operands, where one has an input chain equal to the other, 847 // the 'other' chain is redundant. 848 if (N->getNumOperands() == 2) { 849 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 850 return N->getOperand(0); 851 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 852 return N->getOperand(1); 853 } 854 855 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 856 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 857 SmallPtrSet<SDNode*, 16> SeenOps; 858 bool Changed = false; // If we should replace this token factor. 859 860 // Start out with this token factor. 861 TFs.push_back(N); 862 863 // Iterate through token factors. The TFs grows when new token factors are 864 // encountered. 865 for (unsigned i = 0; i < TFs.size(); ++i) { 866 SDNode *TF = TFs[i]; 867 868 // Check each of the operands. 869 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 870 SDValue Op = TF->getOperand(i); 871 872 switch (Op.getOpcode()) { 873 case ISD::EntryToken: 874 // Entry tokens don't need to be added to the list. They are 875 // rededundant. 876 Changed = true; 877 break; 878 879 case ISD::TokenFactor: 880 if ((CombinerAA || Op.hasOneUse()) && 881 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 882 // Queue up for processing. 883 TFs.push_back(Op.getNode()); 884 // Clean up in case the token factor is removed. 885 AddToWorkList(Op.getNode()); 886 Changed = true; 887 break; 888 } 889 // Fall thru 890 891 default: 892 // Only add if it isn't already in the list. 893 if (SeenOps.insert(Op.getNode())) 894 Ops.push_back(Op); 895 else 896 Changed = true; 897 break; 898 } 899 } 900 } 901 902 SDValue Result; 903 904 // If we've change things around then replace token factor. 905 if (Changed) { 906 if (Ops.empty()) { 907 // The entry token is the only possible outcome. 908 Result = DAG.getEntryNode(); 909 } else { 910 // New and improved token factor. 911 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 912 MVT::Other, &Ops[0], Ops.size()); 913 } 914 915 // Don't add users to work list. 916 return CombineTo(N, Result, false); 917 } 918 919 return Result; 920} 921 922/// MERGE_VALUES can always be eliminated. 923SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 924 WorkListRemover DeadNodes(*this); 925 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 926 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 927 &DeadNodes); 928 removeFromWorkList(N); 929 DAG.DeleteNode(N); 930 return SDValue(N, 0); // Return N so it doesn't get rechecked! 931} 932 933static 934SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 935 SelectionDAG &DAG) { 936 MVT VT = N0.getValueType(); 937 SDValue N00 = N0.getOperand(0); 938 SDValue N01 = N0.getOperand(1); 939 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 940 941 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 942 isa<ConstantSDNode>(N00.getOperand(1))) { 943 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 944 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 945 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 946 N00.getOperand(0), N01), 947 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 948 N00.getOperand(1), N01)); 949 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 950 } 951 952 return SDValue(); 953} 954 955SDValue DAGCombiner::visitADD(SDNode *N) { 956 SDValue N0 = N->getOperand(0); 957 SDValue N1 = N->getOperand(1); 958 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 959 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 960 MVT VT = N0.getValueType(); 961 962 // fold vector ops 963 if (VT.isVector()) { 964 SDValue FoldedVOp = SimplifyVBinOp(N); 965 if (FoldedVOp.getNode()) return FoldedVOp; 966 } 967 968 // fold (add x, undef) -> undef 969 if (N0.getOpcode() == ISD::UNDEF) 970 return N0; 971 if (N1.getOpcode() == ISD::UNDEF) 972 return N1; 973 // fold (add c1, c2) -> c1+c2 974 if (N0C && N1C) 975 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 976 // canonicalize constant to RHS 977 if (N0C && !N1C) 978 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 979 // fold (add x, 0) -> x 980 if (N1C && N1C->isNullValue()) 981 return N0; 982 // fold (add Sym, c) -> Sym+c 983 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 984 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 985 GA->getOpcode() == ISD::GlobalAddress) 986 return DAG.getGlobalAddress(GA->getGlobal(), VT, 987 GA->getOffset() + 988 (uint64_t)N1C->getSExtValue()); 989 // fold ((c1-A)+c2) -> (c1+c2)-A 990 if (N1C && N0.getOpcode() == ISD::SUB) 991 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 992 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 993 DAG.getConstant(N1C->getAPIntValue()+ 994 N0C->getAPIntValue(), VT), 995 N0.getOperand(1)); 996 // reassociate add 997 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 998 if (RADD.getNode() != 0) 999 return RADD; 1000 // fold ((0-A) + B) -> B-A 1001 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1002 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1003 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1004 // fold (A + (0-B)) -> A-B 1005 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1006 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1007 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1008 // fold (A+(B-A)) -> B 1009 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1010 return N1.getOperand(0); 1011 // fold ((B-A)+A) -> B 1012 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1013 return N0.getOperand(0); 1014 // fold (A+(B-(A+C))) to (B-C) 1015 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1016 N0 == N1.getOperand(1).getOperand(0)) 1017 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1018 N1.getOperand(1).getOperand(1)); 1019 // fold (A+(B-(C+A))) to (B-C) 1020 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1021 N0 == N1.getOperand(1).getOperand(1)) 1022 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1023 N1.getOperand(1).getOperand(0)); 1024 // fold (A+((B-A)+or-C)) to (B+or-C) 1025 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1026 N1.getOperand(0).getOpcode() == ISD::SUB && 1027 N0 == N1.getOperand(0).getOperand(1)) 1028 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1029 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1030 1031 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1032 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1033 SDValue N00 = N0.getOperand(0); 1034 SDValue N01 = N0.getOperand(1); 1035 SDValue N10 = N1.getOperand(0); 1036 SDValue N11 = N1.getOperand(1); 1037 1038 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1039 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1040 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1041 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1042 } 1043 1044 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1045 return SDValue(N, 0); 1046 1047 // fold (a+b) -> (a|b) iff a and b share no bits. 1048 if (VT.isInteger() && !VT.isVector()) { 1049 APInt LHSZero, LHSOne; 1050 APInt RHSZero, RHSOne; 1051 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1052 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1053 1054 if (LHSZero.getBoolValue()) { 1055 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1056 1057 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1058 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1059 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1060 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1061 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1062 } 1063 } 1064 1065 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1066 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1067 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1068 if (Result.getNode()) return Result; 1069 } 1070 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1071 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1072 if (Result.getNode()) return Result; 1073 } 1074 1075 return SDValue(); 1076} 1077 1078SDValue DAGCombiner::visitADDC(SDNode *N) { 1079 SDValue N0 = N->getOperand(0); 1080 SDValue N1 = N->getOperand(1); 1081 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1082 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1083 MVT VT = N0.getValueType(); 1084 1085 // If the flag result is dead, turn this into an ADD. 1086 if (N->hasNUsesOfValue(0, 1)) 1087 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1088 DAG.getConstant(0, N->getValueType(1))); 1089 1090 // canonicalize constant to RHS. 1091 if (N0C && !N1C) 1092 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1093 1094 // fold (addc x, 0) -> x + no carry out 1095 if (N1C && N1C->isNullValue()) 1096 return CombineTo(N, N0, DAG.getConstant(0, N1.getValueType())); 1097 1098 // fold (addc a, b) -> (or a, b), 0 iff a and b share no bits. 1099 APInt LHSZero, LHSOne; 1100 APInt RHSZero, RHSOne; 1101 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1102 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1103 1104 if (LHSZero.getBoolValue()) { 1105 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1106 1107 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1108 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1109 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1110 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1111 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1112 DAG.getConstant(0, N1.getValueType())); 1113 } 1114 1115 return SDValue(); 1116} 1117 1118SDValue DAGCombiner::visitADDE(SDNode *N) { 1119 SDValue N0 = N->getOperand(0); 1120 SDValue N1 = N->getOperand(1); 1121 SDValue CarryIn = N->getOperand(2); 1122 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1123 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1124 1125 // canonicalize constant to RHS 1126 if (N0C && !N1C) 1127 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1128 N1, N0, CarryIn); 1129 1130 // fold (adde x, y, false) -> (addc x, y) 1131 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(CarryIn)) 1132 if (N2C->getAPIntValue()==0) 1133 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1134 1135 return SDValue(); 1136} 1137 1138SDValue DAGCombiner::visitSUB(SDNode *N) { 1139 SDValue N0 = N->getOperand(0); 1140 SDValue N1 = N->getOperand(1); 1141 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1142 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1143 MVT VT = N0.getValueType(); 1144 1145 // fold vector ops 1146 if (VT.isVector()) { 1147 SDValue FoldedVOp = SimplifyVBinOp(N); 1148 if (FoldedVOp.getNode()) return FoldedVOp; 1149 } 1150 1151 // fold (sub x, x) -> 0 1152 if (N0 == N1) 1153 return DAG.getConstant(0, N->getValueType(0)); 1154 // fold (sub c1, c2) -> c1-c2 1155 if (N0C && N1C) 1156 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1157 // fold (sub x, c) -> (add x, -c) 1158 if (N1C) 1159 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1160 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1161 // fold (A+B)-A -> B 1162 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1163 return N0.getOperand(1); 1164 // fold (A+B)-B -> A 1165 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1166 return N0.getOperand(0); 1167 // fold ((A+(B+or-C))-B) -> A+or-C 1168 if (N0.getOpcode() == ISD::ADD && 1169 (N0.getOperand(1).getOpcode() == ISD::SUB || 1170 N0.getOperand(1).getOpcode() == ISD::ADD) && 1171 N0.getOperand(1).getOperand(0) == N1) 1172 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1173 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1174 // fold ((A+(C+B))-B) -> A+C 1175 if (N0.getOpcode() == ISD::ADD && 1176 N0.getOperand(1).getOpcode() == ISD::ADD && 1177 N0.getOperand(1).getOperand(1) == N1) 1178 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1179 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1180 // fold ((A-(B-C))-C) -> A-B 1181 if (N0.getOpcode() == ISD::SUB && 1182 N0.getOperand(1).getOpcode() == ISD::SUB && 1183 N0.getOperand(1).getOperand(1) == N1) 1184 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1185 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1186 1187 // If either operand of a sub is undef, the result is undef 1188 if (N0.getOpcode() == ISD::UNDEF) 1189 return N0; 1190 if (N1.getOpcode() == ISD::UNDEF) 1191 return N1; 1192 1193 // If the relocation model supports it, consider symbol offsets. 1194 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1195 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1196 // fold (sub Sym, c) -> Sym-c 1197 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1198 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1199 GA->getOffset() - 1200 (uint64_t)N1C->getSExtValue()); 1201 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1202 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1203 if (GA->getGlobal() == GB->getGlobal()) 1204 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1205 VT); 1206 } 1207 1208 return SDValue(); 1209} 1210 1211SDValue DAGCombiner::visitMUL(SDNode *N) { 1212 SDValue N0 = N->getOperand(0); 1213 SDValue N1 = N->getOperand(1); 1214 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1215 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1216 MVT VT = N0.getValueType(); 1217 1218 // fold vector ops 1219 if (VT.isVector()) { 1220 SDValue FoldedVOp = SimplifyVBinOp(N); 1221 if (FoldedVOp.getNode()) return FoldedVOp; 1222 } 1223 1224 // fold (mul x, undef) -> 0 1225 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1226 return DAG.getConstant(0, VT); 1227 // fold (mul c1, c2) -> c1*c2 1228 if (N0C && N1C) 1229 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1230 // canonicalize constant to RHS 1231 if (N0C && !N1C) 1232 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1233 // fold (mul x, 0) -> 0 1234 if (N1C && N1C->isNullValue()) 1235 return N1; 1236 // fold (mul x, -1) -> 0-x 1237 if (N1C && N1C->isAllOnesValue()) 1238 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1239 DAG.getConstant(0, VT), N0); 1240 // fold (mul x, (1 << c)) -> x << c 1241 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1242 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1243 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1244 getShiftAmountTy())); 1245 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1246 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1247 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1248 // FIXME: If the input is something that is easily negated (e.g. a 1249 // single-use add), we should put the negate there. 1250 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1251 DAG.getConstant(0, VT), 1252 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1253 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1254 } 1255 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1256 if (N1C && N0.getOpcode() == ISD::SHL && 1257 isa<ConstantSDNode>(N0.getOperand(1))) { 1258 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1259 N1, N0.getOperand(1)); 1260 AddToWorkList(C3.getNode()); 1261 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1262 N0.getOperand(0), C3); 1263 } 1264 1265 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1266 // use. 1267 { 1268 SDValue Sh(0,0), Y(0,0); 1269 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1270 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1271 N0.getNode()->hasOneUse()) { 1272 Sh = N0; Y = N1; 1273 } else if (N1.getOpcode() == ISD::SHL && 1274 isa<ConstantSDNode>(N1.getOperand(1)) && 1275 N1.getNode()->hasOneUse()) { 1276 Sh = N1; Y = N0; 1277 } 1278 1279 if (Sh.getNode()) { 1280 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1281 Sh.getOperand(0), Y); 1282 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1283 Mul, Sh.getOperand(1)); 1284 } 1285 } 1286 1287 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1288 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1289 isa<ConstantSDNode>(N0.getOperand(1))) 1290 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1291 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1292 N0.getOperand(0), N1), 1293 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1294 N0.getOperand(1), N1)); 1295 1296 // reassociate mul 1297 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1298 if (RMUL.getNode() != 0) 1299 return RMUL; 1300 1301 return SDValue(); 1302} 1303 1304SDValue DAGCombiner::visitSDIV(SDNode *N) { 1305 SDValue N0 = N->getOperand(0); 1306 SDValue N1 = N->getOperand(1); 1307 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1308 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1309 MVT VT = N->getValueType(0); 1310 1311 // fold vector ops 1312 if (VT.isVector()) { 1313 SDValue FoldedVOp = SimplifyVBinOp(N); 1314 if (FoldedVOp.getNode()) return FoldedVOp; 1315 } 1316 1317 // fold (sdiv c1, c2) -> c1/c2 1318 if (N0C && N1C && !N1C->isNullValue()) 1319 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1320 // fold (sdiv X, 1) -> X 1321 if (N1C && N1C->getSExtValue() == 1LL) 1322 return N0; 1323 // fold (sdiv X, -1) -> 0-X 1324 if (N1C && N1C->isAllOnesValue()) 1325 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1326 DAG.getConstant(0, VT), N0); 1327 // If we know the sign bits of both operands are zero, strength reduce to a 1328 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1329 if (!VT.isVector()) { 1330 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1331 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1332 N0, N1); 1333 } 1334 // fold (sdiv X, pow2) -> simple ops after legalize 1335 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1336 (isPowerOf2_64(N1C->getSExtValue()) || 1337 isPowerOf2_64(-N1C->getSExtValue()))) { 1338 // If dividing by powers of two is cheap, then don't perform the following 1339 // fold. 1340 if (TLI.isPow2DivCheap()) 1341 return SDValue(); 1342 1343 int64_t pow2 = N1C->getSExtValue(); 1344 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1345 unsigned lg2 = Log2_64(abs2); 1346 1347 // Splat the sign bit into the register 1348 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1349 DAG.getConstant(VT.getSizeInBits()-1, 1350 getShiftAmountTy())); 1351 AddToWorkList(SGN.getNode()); 1352 1353 // Add (N0 < 0) ? abs2 - 1 : 0; 1354 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1355 DAG.getConstant(VT.getSizeInBits() - lg2, 1356 getShiftAmountTy())); 1357 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1358 AddToWorkList(SRL.getNode()); 1359 AddToWorkList(ADD.getNode()); // Divide by pow2 1360 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1361 DAG.getConstant(lg2, getShiftAmountTy())); 1362 1363 // If we're dividing by a positive value, we're done. Otherwise, we must 1364 // negate the result. 1365 if (pow2 > 0) 1366 return SRA; 1367 1368 AddToWorkList(SRA.getNode()); 1369 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1370 DAG.getConstant(0, VT), SRA); 1371 } 1372 1373 // if integer divide is expensive and we satisfy the requirements, emit an 1374 // alternate sequence. 1375 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1376 !TLI.isIntDivCheap()) { 1377 SDValue Op = BuildSDIV(N); 1378 if (Op.getNode()) return Op; 1379 } 1380 1381 // undef / X -> 0 1382 if (N0.getOpcode() == ISD::UNDEF) 1383 return DAG.getConstant(0, VT); 1384 // X / undef -> undef 1385 if (N1.getOpcode() == ISD::UNDEF) 1386 return N1; 1387 1388 return SDValue(); 1389} 1390 1391SDValue DAGCombiner::visitUDIV(SDNode *N) { 1392 SDValue N0 = N->getOperand(0); 1393 SDValue N1 = N->getOperand(1); 1394 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1395 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1396 MVT VT = N->getValueType(0); 1397 1398 // fold vector ops 1399 if (VT.isVector()) { 1400 SDValue FoldedVOp = SimplifyVBinOp(N); 1401 if (FoldedVOp.getNode()) return FoldedVOp; 1402 } 1403 1404 // fold (udiv c1, c2) -> c1/c2 1405 if (N0C && N1C && !N1C->isNullValue()) 1406 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1407 // fold (udiv x, (1 << c)) -> x >>u c 1408 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1409 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1410 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1411 getShiftAmountTy())); 1412 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1413 if (N1.getOpcode() == ISD::SHL) { 1414 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1415 if (SHC->getAPIntValue().isPowerOf2()) { 1416 MVT ADDVT = N1.getOperand(1).getValueType(); 1417 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1418 N1.getOperand(1), 1419 DAG.getConstant(SHC->getAPIntValue() 1420 .logBase2(), 1421 ADDVT)); 1422 AddToWorkList(Add.getNode()); 1423 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1424 } 1425 } 1426 } 1427 // fold (udiv x, c) -> alternate 1428 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1429 SDValue Op = BuildUDIV(N); 1430 if (Op.getNode()) return Op; 1431 } 1432 1433 // undef / X -> 0 1434 if (N0.getOpcode() == ISD::UNDEF) 1435 return DAG.getConstant(0, VT); 1436 // X / undef -> undef 1437 if (N1.getOpcode() == ISD::UNDEF) 1438 return N1; 1439 1440 return SDValue(); 1441} 1442 1443SDValue DAGCombiner::visitSREM(SDNode *N) { 1444 SDValue N0 = N->getOperand(0); 1445 SDValue N1 = N->getOperand(1); 1446 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1447 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1448 MVT VT = N->getValueType(0); 1449 1450 // fold (srem c1, c2) -> c1%c2 1451 if (N0C && N1C && !N1C->isNullValue()) 1452 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1453 // If we know the sign bits of both operands are zero, strength reduce to a 1454 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1455 if (!VT.isVector()) { 1456 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1457 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1458 } 1459 1460 // If X/C can be simplified by the division-by-constant logic, lower 1461 // X%C to the equivalent of X-X/C*C. 1462 if (N1C && !N1C->isNullValue()) { 1463 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1464 AddToWorkList(Div.getNode()); 1465 SDValue OptimizedDiv = combine(Div.getNode()); 1466 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1467 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1468 OptimizedDiv, N1); 1469 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1470 AddToWorkList(Mul.getNode()); 1471 return Sub; 1472 } 1473 } 1474 1475 // undef % X -> 0 1476 if (N0.getOpcode() == ISD::UNDEF) 1477 return DAG.getConstant(0, VT); 1478 // X % undef -> undef 1479 if (N1.getOpcode() == ISD::UNDEF) 1480 return N1; 1481 1482 return SDValue(); 1483} 1484 1485SDValue DAGCombiner::visitUREM(SDNode *N) { 1486 SDValue N0 = N->getOperand(0); 1487 SDValue N1 = N->getOperand(1); 1488 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1489 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1490 MVT VT = N->getValueType(0); 1491 1492 // fold (urem c1, c2) -> c1%c2 1493 if (N0C && N1C && !N1C->isNullValue()) 1494 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1495 // fold (urem x, pow2) -> (and x, pow2-1) 1496 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1497 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1498 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1499 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1500 if (N1.getOpcode() == ISD::SHL) { 1501 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1502 if (SHC->getAPIntValue().isPowerOf2()) { 1503 SDValue Add = 1504 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1505 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1506 VT)); 1507 AddToWorkList(Add.getNode()); 1508 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1509 } 1510 } 1511 } 1512 1513 // If X/C can be simplified by the division-by-constant logic, lower 1514 // X%C to the equivalent of X-X/C*C. 1515 if (N1C && !N1C->isNullValue()) { 1516 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1517 AddToWorkList(Div.getNode()); 1518 SDValue OptimizedDiv = combine(Div.getNode()); 1519 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1520 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1521 OptimizedDiv, N1); 1522 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1523 AddToWorkList(Mul.getNode()); 1524 return Sub; 1525 } 1526 } 1527 1528 // undef % X -> 0 1529 if (N0.getOpcode() == ISD::UNDEF) 1530 return DAG.getConstant(0, VT); 1531 // X % undef -> undef 1532 if (N1.getOpcode() == ISD::UNDEF) 1533 return N1; 1534 1535 return SDValue(); 1536} 1537 1538SDValue DAGCombiner::visitMULHS(SDNode *N) { 1539 SDValue N0 = N->getOperand(0); 1540 SDValue N1 = N->getOperand(1); 1541 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1542 MVT VT = N->getValueType(0); 1543 1544 // fold (mulhs x, 0) -> 0 1545 if (N1C && N1C->isNullValue()) 1546 return N1; 1547 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1548 if (N1C && N1C->getAPIntValue() == 1) 1549 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1550 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1551 getShiftAmountTy())); 1552 // fold (mulhs x, undef) -> 0 1553 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1554 return DAG.getConstant(0, VT); 1555 1556 return SDValue(); 1557} 1558 1559SDValue DAGCombiner::visitMULHU(SDNode *N) { 1560 SDValue N0 = N->getOperand(0); 1561 SDValue N1 = N->getOperand(1); 1562 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1563 MVT VT = N->getValueType(0); 1564 1565 // fold (mulhu x, 0) -> 0 1566 if (N1C && N1C->isNullValue()) 1567 return N1; 1568 // fold (mulhu x, 1) -> 0 1569 if (N1C && N1C->getAPIntValue() == 1) 1570 return DAG.getConstant(0, N0.getValueType()); 1571 // fold (mulhu x, undef) -> 0 1572 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1573 return DAG.getConstant(0, VT); 1574 1575 return SDValue(); 1576} 1577 1578/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1579/// compute two values. LoOp and HiOp give the opcodes for the two computations 1580/// that are being performed. Return true if a simplification was made. 1581/// 1582SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1583 unsigned HiOp) { 1584 // If the high half is not needed, just compute the low half. 1585 bool HiExists = N->hasAnyUseOfValue(1); 1586 if (!HiExists && 1587 (!LegalOperations || 1588 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1589 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1590 N->op_begin(), N->getNumOperands()); 1591 return CombineTo(N, Res, Res); 1592 } 1593 1594 // If the low half is not needed, just compute the high half. 1595 bool LoExists = N->hasAnyUseOfValue(0); 1596 if (!LoExists && 1597 (!LegalOperations || 1598 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1599 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1600 N->op_begin(), N->getNumOperands()); 1601 return CombineTo(N, Res, Res); 1602 } 1603 1604 // If both halves are used, return as it is. 1605 if (LoExists && HiExists) 1606 return SDValue(); 1607 1608 // If the two computed results can be simplified separately, separate them. 1609 if (LoExists) { 1610 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1611 N->op_begin(), N->getNumOperands()); 1612 AddToWorkList(Lo.getNode()); 1613 SDValue LoOpt = combine(Lo.getNode()); 1614 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1615 (!LegalOperations || 1616 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1617 return CombineTo(N, LoOpt, LoOpt); 1618 } 1619 1620 if (HiExists) { 1621 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1622 N->op_begin(), N->getNumOperands()); 1623 AddToWorkList(Hi.getNode()); 1624 SDValue HiOpt = combine(Hi.getNode()); 1625 if (HiOpt.getNode() && HiOpt != Hi && 1626 (!LegalOperations || 1627 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1628 return CombineTo(N, HiOpt, HiOpt); 1629 } 1630 1631 return SDValue(); 1632} 1633 1634SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1635 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1636 if (Res.getNode()) return Res; 1637 1638 return SDValue(); 1639} 1640 1641SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1642 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1643 if (Res.getNode()) return Res; 1644 1645 return SDValue(); 1646} 1647 1648SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1649 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1650 if (Res.getNode()) return Res; 1651 1652 return SDValue(); 1653} 1654 1655SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1656 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1657 if (Res.getNode()) return Res; 1658 1659 return SDValue(); 1660} 1661 1662/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1663/// two operands of the same opcode, try to simplify it. 1664SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1665 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1666 MVT VT = N0.getValueType(); 1667 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1668 1669 // For each of OP in AND/OR/XOR: 1670 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1671 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1672 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1673 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1674 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1675 N0.getOpcode() == ISD::SIGN_EXTEND || 1676 (N0.getOpcode() == ISD::TRUNCATE && 1677 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1678 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1679 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1680 N0.getOperand(0).getValueType(), 1681 N0.getOperand(0), N1.getOperand(0)); 1682 AddToWorkList(ORNode.getNode()); 1683 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1684 } 1685 1686 // For each of OP in SHL/SRL/SRA/AND... 1687 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1688 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1689 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1690 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1691 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1692 N0.getOperand(1) == N1.getOperand(1)) { 1693 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1694 N0.getOperand(0).getValueType(), 1695 N0.getOperand(0), N1.getOperand(0)); 1696 AddToWorkList(ORNode.getNode()); 1697 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1698 ORNode, N0.getOperand(1)); 1699 } 1700 1701 return SDValue(); 1702} 1703 1704SDValue DAGCombiner::visitAND(SDNode *N) { 1705 SDValue N0 = N->getOperand(0); 1706 SDValue N1 = N->getOperand(1); 1707 SDValue LL, LR, RL, RR, CC0, CC1; 1708 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1709 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1710 MVT VT = N1.getValueType(); 1711 unsigned BitWidth = VT.getSizeInBits(); 1712 1713 // fold vector ops 1714 if (VT.isVector()) { 1715 SDValue FoldedVOp = SimplifyVBinOp(N); 1716 if (FoldedVOp.getNode()) return FoldedVOp; 1717 } 1718 1719 // fold (and x, undef) -> 0 1720 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1721 return DAG.getConstant(0, VT); 1722 // fold (and c1, c2) -> c1&c2 1723 if (N0C && N1C) 1724 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1725 // canonicalize constant to RHS 1726 if (N0C && !N1C) 1727 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1728 // fold (and x, -1) -> x 1729 if (N1C && N1C->isAllOnesValue()) 1730 return N0; 1731 // if (and x, c) is known to be zero, return 0 1732 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1733 APInt::getAllOnesValue(BitWidth))) 1734 return DAG.getConstant(0, VT); 1735 // reassociate and 1736 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1737 if (RAND.getNode() != 0) 1738 return RAND; 1739 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1740 if (N1C && N0.getOpcode() == ISD::OR) 1741 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1742 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1743 return N1; 1744 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1745 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1746 SDValue N0Op0 = N0.getOperand(0); 1747 APInt Mask = ~N1C->getAPIntValue(); 1748 Mask.trunc(N0Op0.getValueSizeInBits()); 1749 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1750 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1751 N0.getValueType(), N0Op0); 1752 1753 // Replace uses of the AND with uses of the Zero extend node. 1754 CombineTo(N, Zext); 1755 1756 // We actually want to replace all uses of the any_extend with the 1757 // zero_extend, to avoid duplicating things. This will later cause this 1758 // AND to be folded. 1759 CombineTo(N0.getNode(), Zext); 1760 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1761 } 1762 } 1763 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1764 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1765 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1766 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1767 1768 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1769 LL.getValueType().isInteger()) { 1770 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1771 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1772 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1773 LR.getValueType(), LL, RL); 1774 AddToWorkList(ORNode.getNode()); 1775 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1776 } 1777 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1778 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1779 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1780 LR.getValueType(), LL, RL); 1781 AddToWorkList(ANDNode.getNode()); 1782 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1783 } 1784 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1785 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1786 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1787 LR.getValueType(), LL, RL); 1788 AddToWorkList(ORNode.getNode()); 1789 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1790 } 1791 } 1792 // canonicalize equivalent to ll == rl 1793 if (LL == RR && LR == RL) { 1794 Op1 = ISD::getSetCCSwappedOperands(Op1); 1795 std::swap(RL, RR); 1796 } 1797 if (LL == RL && LR == RR) { 1798 bool isInteger = LL.getValueType().isInteger(); 1799 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1800 if (Result != ISD::SETCC_INVALID && 1801 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1802 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1803 LL, LR, Result); 1804 } 1805 } 1806 1807 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1808 if (N0.getOpcode() == N1.getOpcode()) { 1809 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1810 if (Tmp.getNode()) return Tmp; 1811 } 1812 1813 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1814 // fold (and (sra)) -> (and (srl)) when possible. 1815 if (!VT.isVector() && 1816 SimplifyDemandedBits(SDValue(N, 0))) 1817 return SDValue(N, 0); 1818 // fold (zext_inreg (extload x)) -> (zextload x) 1819 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1820 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1821 MVT EVT = LN0->getMemoryVT(); 1822 // If we zero all the possible extended bits, then we can turn this into 1823 // a zextload if we are running before legalize or the operation is legal. 1824 unsigned BitWidth = N1.getValueSizeInBits(); 1825 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1826 BitWidth - EVT.getSizeInBits())) && 1827 ((!LegalOperations && !LN0->isVolatile()) || 1828 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1829 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1830 LN0->getChain(), LN0->getBasePtr(), 1831 LN0->getSrcValue(), 1832 LN0->getSrcValueOffset(), EVT, 1833 LN0->isVolatile(), LN0->getAlignment()); 1834 AddToWorkList(N); 1835 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1836 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1837 } 1838 } 1839 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1840 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1841 N0.hasOneUse()) { 1842 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1843 MVT EVT = LN0->getMemoryVT(); 1844 // If we zero all the possible extended bits, then we can turn this into 1845 // a zextload if we are running before legalize or the operation is legal. 1846 unsigned BitWidth = N1.getValueSizeInBits(); 1847 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1848 BitWidth - EVT.getSizeInBits())) && 1849 ((!LegalOperations && !LN0->isVolatile()) || 1850 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1851 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1852 LN0->getChain(), 1853 LN0->getBasePtr(), LN0->getSrcValue(), 1854 LN0->getSrcValueOffset(), EVT, 1855 LN0->isVolatile(), LN0->getAlignment()); 1856 AddToWorkList(N); 1857 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1858 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1859 } 1860 } 1861 1862 // fold (and (load x), 255) -> (zextload x, i8) 1863 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1864 if (N1C && N0.getOpcode() == ISD::LOAD) { 1865 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1866 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1867 LN0->isUnindexed() && N0.hasOneUse() && 1868 // Do not change the width of a volatile load. 1869 !LN0->isVolatile()) { 1870 MVT EVT = MVT::Other; 1871 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1872 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1873 EVT = MVT::getIntegerVT(ActiveBits); 1874 1875 MVT LoadedVT = LN0->getMemoryVT(); 1876 1877 // Do not generate loads of non-round integer types since these can 1878 // be expensive (and would be wrong if the type is not byte sized). 1879 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1880 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1881 MVT PtrType = N0.getOperand(1).getValueType(); 1882 1883 // For big endian targets, we need to add an offset to the pointer to 1884 // load the correct bytes. For little endian systems, we merely need to 1885 // read fewer bytes from the same pointer. 1886 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1887 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1888 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1889 unsigned Alignment = LN0->getAlignment(); 1890 SDValue NewPtr = LN0->getBasePtr(); 1891 1892 if (TLI.isBigEndian()) { 1893 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1894 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1895 Alignment = MinAlign(Alignment, PtrOff); 1896 } 1897 1898 AddToWorkList(NewPtr.getNode()); 1899 SDValue Load = 1900 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1901 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1902 EVT, LN0->isVolatile(), Alignment); 1903 AddToWorkList(N); 1904 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1905 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1906 } 1907 } 1908 } 1909 1910 return SDValue(); 1911} 1912 1913SDValue DAGCombiner::visitOR(SDNode *N) { 1914 SDValue N0 = N->getOperand(0); 1915 SDValue N1 = N->getOperand(1); 1916 SDValue LL, LR, RL, RR, CC0, CC1; 1917 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1918 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1919 MVT VT = N1.getValueType(); 1920 1921 // fold vector ops 1922 if (VT.isVector()) { 1923 SDValue FoldedVOp = SimplifyVBinOp(N); 1924 if (FoldedVOp.getNode()) return FoldedVOp; 1925 } 1926 1927 // fold (or x, undef) -> -1 1928 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1929 return DAG.getConstant(~0ULL, VT); 1930 // fold (or c1, c2) -> c1|c2 1931 if (N0C && N1C) 1932 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1933 // canonicalize constant to RHS 1934 if (N0C && !N1C) 1935 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1936 // fold (or x, 0) -> x 1937 if (N1C && N1C->isNullValue()) 1938 return N0; 1939 // fold (or x, -1) -> -1 1940 if (N1C && N1C->isAllOnesValue()) 1941 return N1; 1942 // fold (or x, c) -> c iff (x & ~c) == 0 1943 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1944 return N1; 1945 // reassociate or 1946 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1947 if (ROR.getNode() != 0) 1948 return ROR; 1949 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1950 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1951 isa<ConstantSDNode>(N0.getOperand(1))) { 1952 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1953 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1954 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1955 N0.getOperand(0), N1), 1956 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1957 } 1958 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1959 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1960 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1961 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1962 1963 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1964 LL.getValueType().isInteger()) { 1965 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1966 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1967 if (cast<ConstantSDNode>(LR)->isNullValue() && 1968 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1969 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1970 LR.getValueType(), LL, RL); 1971 AddToWorkList(ORNode.getNode()); 1972 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1973 } 1974 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 1975 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 1976 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1977 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1978 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 1979 LR.getValueType(), LL, RL); 1980 AddToWorkList(ANDNode.getNode()); 1981 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1982 } 1983 } 1984 // canonicalize equivalent to ll == rl 1985 if (LL == RR && LR == RL) { 1986 Op1 = ISD::getSetCCSwappedOperands(Op1); 1987 std::swap(RL, RR); 1988 } 1989 if (LL == RL && LR == RR) { 1990 bool isInteger = LL.getValueType().isInteger(); 1991 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1992 if (Result != ISD::SETCC_INVALID && 1993 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1994 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1995 LL, LR, Result); 1996 } 1997 } 1998 1999 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2000 if (N0.getOpcode() == N1.getOpcode()) { 2001 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2002 if (Tmp.getNode()) return Tmp; 2003 } 2004 2005 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2006 if (N0.getOpcode() == ISD::AND && 2007 N1.getOpcode() == ISD::AND && 2008 N0.getOperand(1).getOpcode() == ISD::Constant && 2009 N1.getOperand(1).getOpcode() == ISD::Constant && 2010 // Don't increase # computations. 2011 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2012 // We can only do this xform if we know that bits from X that are set in C2 2013 // but not in C1 are already zero. Likewise for Y. 2014 const APInt &LHSMask = 2015 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2016 const APInt &RHSMask = 2017 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2018 2019 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2020 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2021 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2022 N0.getOperand(0), N1.getOperand(0)); 2023 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2024 DAG.getConstant(LHSMask | RHSMask, VT)); 2025 } 2026 } 2027 2028 // See if this is some rotate idiom. 2029 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2030 return SDValue(Rot, 0); 2031 2032 return SDValue(); 2033} 2034 2035/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2036static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2037 if (Op.getOpcode() == ISD::AND) { 2038 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2039 Mask = Op.getOperand(1); 2040 Op = Op.getOperand(0); 2041 } else { 2042 return false; 2043 } 2044 } 2045 2046 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2047 Shift = Op; 2048 return true; 2049 } 2050 2051 return false; 2052} 2053 2054// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2055// idioms for rotate, and if the target supports rotation instructions, generate 2056// a rot[lr]. 2057SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2058 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2059 MVT VT = LHS.getValueType(); 2060 if (!TLI.isTypeLegal(VT)) return 0; 2061 2062 // The target must have at least one rotate flavor. 2063 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2064 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2065 if (!HasROTL && !HasROTR) return 0; 2066 2067 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2068 SDValue LHSShift; // The shift. 2069 SDValue LHSMask; // AND value if any. 2070 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2071 return 0; // Not part of a rotate. 2072 2073 SDValue RHSShift; // The shift. 2074 SDValue RHSMask; // AND value if any. 2075 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2076 return 0; // Not part of a rotate. 2077 2078 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2079 return 0; // Not shifting the same value. 2080 2081 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2082 return 0; // Shifts must disagree. 2083 2084 // Canonicalize shl to left side in a shl/srl pair. 2085 if (RHSShift.getOpcode() == ISD::SHL) { 2086 std::swap(LHS, RHS); 2087 std::swap(LHSShift, RHSShift); 2088 std::swap(LHSMask , RHSMask ); 2089 } 2090 2091 unsigned OpSizeInBits = VT.getSizeInBits(); 2092 SDValue LHSShiftArg = LHSShift.getOperand(0); 2093 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2094 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2095 2096 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2097 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2098 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2099 RHSShiftAmt.getOpcode() == ISD::Constant) { 2100 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2101 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2102 if ((LShVal + RShVal) != OpSizeInBits) 2103 return 0; 2104 2105 SDValue Rot; 2106 if (HasROTL) 2107 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2108 else 2109 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2110 2111 // If there is an AND of either shifted operand, apply it to the result. 2112 if (LHSMask.getNode() || RHSMask.getNode()) { 2113 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2114 2115 if (LHSMask.getNode()) { 2116 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2117 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2118 } 2119 if (RHSMask.getNode()) { 2120 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2121 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2122 } 2123 2124 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2125 } 2126 2127 return Rot.getNode(); 2128 } 2129 2130 // If there is a mask here, and we have a variable shift, we can't be sure 2131 // that we're masking out the right stuff. 2132 if (LHSMask.getNode() || RHSMask.getNode()) 2133 return 0; 2134 2135 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2136 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2137 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2138 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2139 if (ConstantSDNode *SUBC = 2140 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2141 if (SUBC->getAPIntValue() == OpSizeInBits) { 2142 if (HasROTL) 2143 return DAG.getNode(ISD::ROTL, DL, VT, 2144 LHSShiftArg, LHSShiftAmt).getNode(); 2145 else 2146 return DAG.getNode(ISD::ROTR, DL, VT, 2147 LHSShiftArg, RHSShiftAmt).getNode(); 2148 } 2149 } 2150 } 2151 2152 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2153 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2154 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2155 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2156 if (ConstantSDNode *SUBC = 2157 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2158 if (SUBC->getAPIntValue() == OpSizeInBits) { 2159 if (HasROTR) 2160 return DAG.getNode(ISD::ROTR, DL, VT, 2161 LHSShiftArg, RHSShiftAmt).getNode(); 2162 else 2163 return DAG.getNode(ISD::ROTL, DL, VT, 2164 LHSShiftArg, LHSShiftAmt).getNode(); 2165 } 2166 } 2167 } 2168 2169 // Look for sign/zext/any-extended or truncate cases: 2170 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2171 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2172 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2173 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2174 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2175 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2176 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2177 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2178 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2179 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2180 if (RExtOp0.getOpcode() == ISD::SUB && 2181 RExtOp0.getOperand(1) == LExtOp0) { 2182 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2183 // (rotl x, y) 2184 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2185 // (rotr x, (sub 32, y)) 2186 if (ConstantSDNode *SUBC = 2187 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2188 if (SUBC->getAPIntValue() == OpSizeInBits) { 2189 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2190 LHSShiftArg, 2191 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2192 } 2193 } 2194 } else if (LExtOp0.getOpcode() == ISD::SUB && 2195 RExtOp0 == LExtOp0.getOperand(1)) { 2196 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2197 // (rotr x, y) 2198 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2199 // (rotl x, (sub 32, y)) 2200 if (ConstantSDNode *SUBC = 2201 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2202 if (SUBC->getAPIntValue() == OpSizeInBits) { 2203 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2204 LHSShiftArg, 2205 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2206 } 2207 } 2208 } 2209 } 2210 2211 return 0; 2212} 2213 2214SDValue DAGCombiner::visitXOR(SDNode *N) { 2215 SDValue N0 = N->getOperand(0); 2216 SDValue N1 = N->getOperand(1); 2217 SDValue LHS, RHS, CC; 2218 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2219 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2220 MVT VT = N0.getValueType(); 2221 2222 // fold vector ops 2223 if (VT.isVector()) { 2224 SDValue FoldedVOp = SimplifyVBinOp(N); 2225 if (FoldedVOp.getNode()) return FoldedVOp; 2226 } 2227 2228 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2229 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2230 return DAG.getConstant(0, VT); 2231 // fold (xor x, undef) -> undef 2232 if (N0.getOpcode() == ISD::UNDEF) 2233 return N0; 2234 if (N1.getOpcode() == ISD::UNDEF) 2235 return N1; 2236 // fold (xor c1, c2) -> c1^c2 2237 if (N0C && N1C) 2238 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2239 // canonicalize constant to RHS 2240 if (N0C && !N1C) 2241 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2242 // fold (xor x, 0) -> x 2243 if (N1C && N1C->isNullValue()) 2244 return N0; 2245 // reassociate xor 2246 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2247 if (RXOR.getNode() != 0) 2248 return RXOR; 2249 2250 // fold !(x cc y) -> (x !cc y) 2251 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2252 bool isInt = LHS.getValueType().isInteger(); 2253 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2254 isInt); 2255 2256 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2257 switch (N0.getOpcode()) { 2258 default: 2259 assert(0 && "Unhandled SetCC Equivalent!"); 2260 abort(); 2261 case ISD::SETCC: 2262 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2263 case ISD::SELECT_CC: 2264 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2265 N0.getOperand(3), NotCC); 2266 } 2267 } 2268 } 2269 2270 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2271 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2272 N0.getNode()->hasOneUse() && 2273 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2274 SDValue V = N0.getOperand(0); 2275 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2276 DAG.getConstant(1, V.getValueType())); 2277 AddToWorkList(V.getNode()); 2278 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2279 } 2280 2281 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2282 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2283 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2284 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2285 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2286 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2287 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2288 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2289 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2290 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2291 } 2292 } 2293 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2294 if (N1C && N1C->isAllOnesValue() && 2295 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2296 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2297 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2298 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2299 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2300 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2301 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2302 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2303 } 2304 } 2305 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2306 if (N1C && N0.getOpcode() == ISD::XOR) { 2307 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2308 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2309 if (N00C) 2310 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2311 DAG.getConstant(N1C->getAPIntValue() ^ 2312 N00C->getAPIntValue(), VT)); 2313 if (N01C) 2314 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2315 DAG.getConstant(N1C->getAPIntValue() ^ 2316 N01C->getAPIntValue(), VT)); 2317 } 2318 // fold (xor x, x) -> 0 2319 if (N0 == N1) { 2320 if (!VT.isVector()) { 2321 return DAG.getConstant(0, VT); 2322 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2323 // Produce a vector of zeros. 2324 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2325 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2326 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2327 &Ops[0], Ops.size()); 2328 } 2329 } 2330 2331 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2332 if (N0.getOpcode() == N1.getOpcode()) { 2333 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2334 if (Tmp.getNode()) return Tmp; 2335 } 2336 2337 // Simplify the expression using non-local knowledge. 2338 if (!VT.isVector() && 2339 SimplifyDemandedBits(SDValue(N, 0))) 2340 return SDValue(N, 0); 2341 2342 return SDValue(); 2343} 2344 2345/// visitShiftByConstant - Handle transforms common to the three shifts, when 2346/// the shift amount is a constant. 2347SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2348 SDNode *LHS = N->getOperand(0).getNode(); 2349 if (!LHS->hasOneUse()) return SDValue(); 2350 2351 // We want to pull some binops through shifts, so that we have (and (shift)) 2352 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2353 // thing happens with address calculations, so it's important to canonicalize 2354 // it. 2355 bool HighBitSet = false; // Can we transform this if the high bit is set? 2356 2357 switch (LHS->getOpcode()) { 2358 default: return SDValue(); 2359 case ISD::OR: 2360 case ISD::XOR: 2361 HighBitSet = false; // We can only transform sra if the high bit is clear. 2362 break; 2363 case ISD::AND: 2364 HighBitSet = true; // We can only transform sra if the high bit is set. 2365 break; 2366 case ISD::ADD: 2367 if (N->getOpcode() != ISD::SHL) 2368 return SDValue(); // only shl(add) not sr[al](add). 2369 HighBitSet = false; // We can only transform sra if the high bit is clear. 2370 break; 2371 } 2372 2373 // We require the RHS of the binop to be a constant as well. 2374 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2375 if (!BinOpCst) return SDValue(); 2376 2377 // FIXME: disable this unless the input to the binop is a shift by a constant. 2378 // If it is not a shift, it pessimizes some common cases like: 2379 // 2380 // void foo(int *X, int i) { X[i & 1235] = 1; } 2381 // int bar(int *X, int i) { return X[i & 255]; } 2382 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2383 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2384 BinOpLHSVal->getOpcode() != ISD::SRA && 2385 BinOpLHSVal->getOpcode() != ISD::SRL) || 2386 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2387 return SDValue(); 2388 2389 MVT VT = N->getValueType(0); 2390 2391 // If this is a signed shift right, and the high bit is modified by the 2392 // logical operation, do not perform the transformation. The highBitSet 2393 // boolean indicates the value of the high bit of the constant which would 2394 // cause it to be modified for this operation. 2395 if (N->getOpcode() == ISD::SRA) { 2396 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2397 if (BinOpRHSSignSet != HighBitSet) 2398 return SDValue(); 2399 } 2400 2401 // Fold the constants, shifting the binop RHS by the shift amount. 2402 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2403 N->getValueType(0), 2404 LHS->getOperand(1), N->getOperand(1)); 2405 2406 // Create the new shift. 2407 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2408 VT, LHS->getOperand(0), N->getOperand(1)); 2409 2410 // Create the new binop. 2411 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2412} 2413 2414SDValue DAGCombiner::visitSHL(SDNode *N) { 2415 SDValue N0 = N->getOperand(0); 2416 SDValue N1 = N->getOperand(1); 2417 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2418 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2419 MVT VT = N0.getValueType(); 2420 unsigned OpSizeInBits = VT.getSizeInBits(); 2421 2422 // fold (shl c1, c2) -> c1<<c2 2423 if (N0C && N1C) 2424 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2425 // fold (shl 0, x) -> 0 2426 if (N0C && N0C->isNullValue()) 2427 return N0; 2428 // fold (shl x, c >= size(x)) -> undef 2429 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2430 return DAG.getUNDEF(VT); 2431 // fold (shl x, 0) -> x 2432 if (N1C && N1C->isNullValue()) 2433 return N0; 2434 // if (shl x, c) is known to be zero, return 0 2435 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2436 APInt::getAllOnesValue(VT.getSizeInBits()))) 2437 return DAG.getConstant(0, VT); 2438 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2439 if (N1.getOpcode() == ISD::TRUNCATE && 2440 N1.getOperand(0).getOpcode() == ISD::AND && 2441 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2442 SDValue N101 = N1.getOperand(0).getOperand(1); 2443 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2444 MVT TruncVT = N1.getValueType(); 2445 SDValue N100 = N1.getOperand(0).getOperand(0); 2446 APInt TruncC = N101C->getAPIntValue(); 2447 TruncC.trunc(TruncVT.getSizeInBits()); 2448 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2449 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2450 DAG.getNode(ISD::TRUNCATE, 2451 N->getDebugLoc(), 2452 TruncVT, N100), 2453 DAG.getConstant(TruncC, TruncVT))); 2454 } 2455 } 2456 2457 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2458 return SDValue(N, 0); 2459 2460 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2461 if (N1C && N0.getOpcode() == ISD::SHL && 2462 N0.getOperand(1).getOpcode() == ISD::Constant) { 2463 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2464 uint64_t c2 = N1C->getZExtValue(); 2465 if (c1 + c2 > OpSizeInBits) 2466 return DAG.getConstant(0, VT); 2467 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2468 DAG.getConstant(c1 + c2, N1.getValueType())); 2469 } 2470 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2471 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2472 if (N1C && N0.getOpcode() == ISD::SRL && 2473 N0.getOperand(1).getOpcode() == ISD::Constant) { 2474 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2475 uint64_t c2 = N1C->getZExtValue(); 2476 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), 2477 DAG.getConstant(~0ULL << c1, VT)); 2478 if (c2 > c1) 2479 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2480 DAG.getConstant(c2-c1, N1.getValueType())); 2481 else 2482 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2483 DAG.getConstant(c1-c2, N1.getValueType())); 2484 } 2485 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2486 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2487 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2488 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2489 2490 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2491} 2492 2493SDValue DAGCombiner::visitSRA(SDNode *N) { 2494 SDValue N0 = N->getOperand(0); 2495 SDValue N1 = N->getOperand(1); 2496 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2498 MVT VT = N0.getValueType(); 2499 2500 // fold (sra c1, c2) -> (sra c1, c2) 2501 if (N0C && N1C) 2502 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2503 // fold (sra 0, x) -> 0 2504 if (N0C && N0C->isNullValue()) 2505 return N0; 2506 // fold (sra -1, x) -> -1 2507 if (N0C && N0C->isAllOnesValue()) 2508 return N0; 2509 // fold (sra x, (setge c, size(x))) -> undef 2510 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2511 return DAG.getUNDEF(VT); 2512 // fold (sra x, 0) -> x 2513 if (N1C && N1C->isNullValue()) 2514 return N0; 2515 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2516 // sext_inreg. 2517 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2518 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2519 MVT EVT = MVT::getIntegerVT(LowBits); 2520 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2521 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2522 N0.getOperand(0), DAG.getValueType(EVT)); 2523 } 2524 2525 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2526 if (N1C && N0.getOpcode() == ISD::SRA) { 2527 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2528 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2529 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2530 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2531 DAG.getConstant(Sum, N1C->getValueType(0))); 2532 } 2533 } 2534 2535 // fold (sra (shl X, m), (sub result_size, n)) 2536 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2537 // result_size - n != m. 2538 // If truncate is free for the target sext(shl) is likely to result in better 2539 // code. 2540 if (N0.getOpcode() == ISD::SHL) { 2541 // Get the two constanst of the shifts, CN0 = m, CN = n. 2542 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2543 if (N01C && N1C) { 2544 // Determine what the truncate's result bitsize and type would be. 2545 unsigned VTValSize = VT.getSizeInBits(); 2546 MVT TruncVT = 2547 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2548 // Determine the residual right-shift amount. 2549 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2550 2551 // If the shift is not a no-op (in which case this should be just a sign 2552 // extend already), the truncated to type is legal, sign_extend is legal 2553 // on that type, and the the truncate to that type is both legal and free, 2554 // perform the transform. 2555 if ((ShiftAmt > 0) && 2556 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2557 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2558 TLI.isTruncateFree(VT, TruncVT)) { 2559 2560 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2561 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2562 N0.getOperand(0), Amt); 2563 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2564 Shift); 2565 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2566 N->getValueType(0), Trunc); 2567 } 2568 } 2569 } 2570 2571 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2572 if (N1.getOpcode() == ISD::TRUNCATE && 2573 N1.getOperand(0).getOpcode() == ISD::AND && 2574 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2575 SDValue N101 = N1.getOperand(0).getOperand(1); 2576 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2577 MVT TruncVT = N1.getValueType(); 2578 SDValue N100 = N1.getOperand(0).getOperand(0); 2579 APInt TruncC = N101C->getAPIntValue(); 2580 TruncC.trunc(TruncVT.getSizeInBits()); 2581 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2582 DAG.getNode(ISD::AND, N->getDebugLoc(), 2583 TruncVT, 2584 DAG.getNode(ISD::TRUNCATE, 2585 N->getDebugLoc(), 2586 TruncVT, N100), 2587 DAG.getConstant(TruncC, TruncVT))); 2588 } 2589 } 2590 2591 // Simplify, based on bits shifted out of the LHS. 2592 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2593 return SDValue(N, 0); 2594 2595 2596 // If the sign bit is known to be zero, switch this to a SRL. 2597 if (DAG.SignBitIsZero(N0)) 2598 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2599 2600 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2601} 2602 2603SDValue DAGCombiner::visitSRL(SDNode *N) { 2604 SDValue N0 = N->getOperand(0); 2605 SDValue N1 = N->getOperand(1); 2606 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2607 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2608 MVT VT = N0.getValueType(); 2609 unsigned OpSizeInBits = VT.getSizeInBits(); 2610 2611 // fold (srl c1, c2) -> c1 >>u c2 2612 if (N0C && N1C) 2613 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2614 // fold (srl 0, x) -> 0 2615 if (N0C && N0C->isNullValue()) 2616 return N0; 2617 // fold (srl x, c >= size(x)) -> undef 2618 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2619 return DAG.getUNDEF(VT); 2620 // fold (srl x, 0) -> x 2621 if (N1C && N1C->isNullValue()) 2622 return N0; 2623 // if (srl x, c) is known to be zero, return 0 2624 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2625 APInt::getAllOnesValue(OpSizeInBits))) 2626 return DAG.getConstant(0, VT); 2627 2628 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2629 if (N1C && N0.getOpcode() == ISD::SRL && 2630 N0.getOperand(1).getOpcode() == ISD::Constant) { 2631 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2632 uint64_t c2 = N1C->getZExtValue(); 2633 if (c1 + c2 > OpSizeInBits) 2634 return DAG.getConstant(0, VT); 2635 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2636 DAG.getConstant(c1 + c2, N1.getValueType())); 2637 } 2638 2639 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2640 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2641 // Shifting in all undef bits? 2642 MVT SmallVT = N0.getOperand(0).getValueType(); 2643 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2644 return DAG.getUNDEF(VT); 2645 2646 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2647 N0.getOperand(0), N1); 2648 AddToWorkList(SmallShift.getNode()); 2649 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2650 } 2651 2652 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2653 // bit, which is unmodified by sra. 2654 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2655 if (N0.getOpcode() == ISD::SRA) 2656 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2657 } 2658 2659 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2660 if (N1C && N0.getOpcode() == ISD::CTLZ && 2661 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2662 APInt KnownZero, KnownOne; 2663 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2664 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2665 2666 // If any of the input bits are KnownOne, then the input couldn't be all 2667 // zeros, thus the result of the srl will always be zero. 2668 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2669 2670 // If all of the bits input the to ctlz node are known to be zero, then 2671 // the result of the ctlz is "32" and the result of the shift is one. 2672 APInt UnknownBits = ~KnownZero & Mask; 2673 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2674 2675 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2676 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2677 // Okay, we know that only that the single bit specified by UnknownBits 2678 // could be set on input to the CTLZ node. If this bit is set, the SRL 2679 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2680 // to an SRL/XOR pair, which is likely to simplify more. 2681 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2682 SDValue Op = N0.getOperand(0); 2683 2684 if (ShAmt) { 2685 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2686 DAG.getConstant(ShAmt, getShiftAmountTy())); 2687 AddToWorkList(Op.getNode()); 2688 } 2689 2690 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2691 Op, DAG.getConstant(1, VT)); 2692 } 2693 } 2694 2695 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2696 if (N1.getOpcode() == ISD::TRUNCATE && 2697 N1.getOperand(0).getOpcode() == ISD::AND && 2698 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2699 SDValue N101 = N1.getOperand(0).getOperand(1); 2700 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2701 MVT TruncVT = N1.getValueType(); 2702 SDValue N100 = N1.getOperand(0).getOperand(0); 2703 APInt TruncC = N101C->getAPIntValue(); 2704 TruncC.trunc(TruncVT.getSizeInBits()); 2705 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2706 DAG.getNode(ISD::AND, N->getDebugLoc(), 2707 TruncVT, 2708 DAG.getNode(ISD::TRUNCATE, 2709 N->getDebugLoc(), 2710 TruncVT, N100), 2711 DAG.getConstant(TruncC, TruncVT))); 2712 } 2713 } 2714 2715 // fold operands of srl based on knowledge that the low bits are not 2716 // demanded. 2717 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2718 return SDValue(N, 0); 2719 2720 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2721} 2722 2723SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2724 SDValue N0 = N->getOperand(0); 2725 MVT VT = N->getValueType(0); 2726 2727 // fold (ctlz c1) -> c2 2728 if (isa<ConstantSDNode>(N0)) 2729 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2730 return SDValue(); 2731} 2732 2733SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2734 SDValue N0 = N->getOperand(0); 2735 MVT VT = N->getValueType(0); 2736 2737 // fold (cttz c1) -> c2 2738 if (isa<ConstantSDNode>(N0)) 2739 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2740 return SDValue(); 2741} 2742 2743SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2744 SDValue N0 = N->getOperand(0); 2745 MVT VT = N->getValueType(0); 2746 2747 // fold (ctpop c1) -> c2 2748 if (isa<ConstantSDNode>(N0)) 2749 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2750 return SDValue(); 2751} 2752 2753SDValue DAGCombiner::visitSELECT(SDNode *N) { 2754 SDValue N0 = N->getOperand(0); 2755 SDValue N1 = N->getOperand(1); 2756 SDValue N2 = N->getOperand(2); 2757 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2758 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2759 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2760 MVT VT = N->getValueType(0); 2761 MVT VT0 = N0.getValueType(); 2762 2763 // fold (select C, X, X) -> X 2764 if (N1 == N2) 2765 return N1; 2766 // fold (select true, X, Y) -> X 2767 if (N0C && !N0C->isNullValue()) 2768 return N1; 2769 // fold (select false, X, Y) -> Y 2770 if (N0C && N0C->isNullValue()) 2771 return N2; 2772 // fold (select C, 1, X) -> (or C, X) 2773 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2774 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2775 // fold (select C, 0, 1) -> (xor C, 1) 2776 if (VT.isInteger() && 2777 (VT0 == MVT::i1 || 2778 (VT0.isInteger() && 2779 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2780 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2781 SDValue XORNode; 2782 if (VT == VT0) 2783 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2784 N0, DAG.getConstant(1, VT0)); 2785 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2786 N0, DAG.getConstant(1, VT0)); 2787 AddToWorkList(XORNode.getNode()); 2788 if (VT.bitsGT(VT0)) 2789 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2790 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2791 } 2792 // fold (select C, 0, X) -> (and (not C), X) 2793 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2794 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2795 AddToWorkList(NOTNode.getNode()); 2796 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2797 } 2798 // fold (select C, X, 1) -> (or (not C), X) 2799 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2800 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2801 AddToWorkList(NOTNode.getNode()); 2802 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2803 } 2804 // fold (select C, X, 0) -> (and C, X) 2805 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2806 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2807 // fold (select X, X, Y) -> (or X, Y) 2808 // fold (select X, 1, Y) -> (or X, Y) 2809 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2810 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2811 // fold (select X, Y, X) -> (and X, Y) 2812 // fold (select X, Y, 0) -> (and X, Y) 2813 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2814 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2815 2816 // If we can fold this based on the true/false value, do so. 2817 if (SimplifySelectOps(N, N1, N2)) 2818 return SDValue(N, 0); // Don't revisit N. 2819 2820 // fold selects based on a setcc into other things, such as min/max/abs 2821 if (N0.getOpcode() == ISD::SETCC) { 2822 // FIXME: 2823 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2824 // having to say they don't support SELECT_CC on every type the DAG knows 2825 // about, since there is no way to mark an opcode illegal at all value types 2826 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2827 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2828 N0.getOperand(0), N0.getOperand(1), 2829 N1, N2, N0.getOperand(2)); 2830 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2831 } 2832 2833 return SDValue(); 2834} 2835 2836SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2837 SDValue N0 = N->getOperand(0); 2838 SDValue N1 = N->getOperand(1); 2839 SDValue N2 = N->getOperand(2); 2840 SDValue N3 = N->getOperand(3); 2841 SDValue N4 = N->getOperand(4); 2842 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2843 2844 // fold select_cc lhs, rhs, x, x, cc -> x 2845 if (N2 == N3) 2846 return N2; 2847 2848 // Determine if the condition we're dealing with is constant 2849 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2850 N0, N1, CC, N->getDebugLoc(), false); 2851 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2852 2853 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2854 if (!SCCC->isNullValue()) 2855 return N2; // cond always true -> true val 2856 else 2857 return N3; // cond always false -> false val 2858 } 2859 2860 // Fold to a simpler select_cc 2861 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2862 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2863 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2864 SCC.getOperand(2)); 2865 2866 // If we can fold this based on the true/false value, do so. 2867 if (SimplifySelectOps(N, N2, N3)) 2868 return SDValue(N, 0); // Don't revisit N. 2869 2870 // fold select_cc into other things, such as min/max/abs 2871 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2872} 2873 2874SDValue DAGCombiner::visitSETCC(SDNode *N) { 2875 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2876 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2877 N->getDebugLoc()); 2878} 2879 2880// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2881// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2882// transformation. Returns true if extension are possible and the above 2883// mentioned transformation is profitable. 2884static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2885 unsigned ExtOpc, 2886 SmallVector<SDNode*, 4> &ExtendNodes, 2887 const TargetLowering &TLI) { 2888 bool HasCopyToRegUses = false; 2889 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2890 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2891 UE = N0.getNode()->use_end(); 2892 UI != UE; ++UI) { 2893 SDNode *User = *UI; 2894 if (User == N) 2895 continue; 2896 if (UI.getUse().getResNo() != N0.getResNo()) 2897 continue; 2898 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2899 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 2900 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2901 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2902 // Sign bits will be lost after a zext. 2903 return false; 2904 bool Add = false; 2905 for (unsigned i = 0; i != 2; ++i) { 2906 SDValue UseOp = User->getOperand(i); 2907 if (UseOp == N0) 2908 continue; 2909 if (!isa<ConstantSDNode>(UseOp)) 2910 return false; 2911 Add = true; 2912 } 2913 if (Add) 2914 ExtendNodes.push_back(User); 2915 continue; 2916 } 2917 // If truncates aren't free and there are users we can't 2918 // extend, it isn't worthwhile. 2919 if (!isTruncFree) 2920 return false; 2921 // Remember if this value is live-out. 2922 if (User->getOpcode() == ISD::CopyToReg) 2923 HasCopyToRegUses = true; 2924 } 2925 2926 if (HasCopyToRegUses) { 2927 bool BothLiveOut = false; 2928 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2929 UI != UE; ++UI) { 2930 SDUse &Use = UI.getUse(); 2931 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 2932 BothLiveOut = true; 2933 break; 2934 } 2935 } 2936 if (BothLiveOut) 2937 // Both unextended and extended values are live out. There had better be 2938 // good a reason for the transformation. 2939 return ExtendNodes.size(); 2940 } 2941 return true; 2942} 2943 2944SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2945 SDValue N0 = N->getOperand(0); 2946 MVT VT = N->getValueType(0); 2947 2948 // fold (sext c1) -> c1 2949 if (isa<ConstantSDNode>(N0)) 2950 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2951 2952 // fold (sext (sext x)) -> (sext x) 2953 // fold (sext (aext x)) -> (sext x) 2954 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2955 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2956 N0.getOperand(0)); 2957 2958 if (N0.getOpcode() == ISD::TRUNCATE) { 2959 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2960 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2961 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2962 if (NarrowLoad.getNode()) { 2963 if (NarrowLoad.getNode() != N0.getNode()) 2964 CombineTo(N0.getNode(), NarrowLoad); 2965 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2966 } 2967 2968 // See if the value being truncated is already sign extended. If so, just 2969 // eliminate the trunc/sext pair. 2970 SDValue Op = N0.getOperand(0); 2971 unsigned OpBits = Op.getValueType().getSizeInBits(); 2972 unsigned MidBits = N0.getValueType().getSizeInBits(); 2973 unsigned DestBits = VT.getSizeInBits(); 2974 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2975 2976 if (OpBits == DestBits) { 2977 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2978 // bits, it is already ready. 2979 if (NumSignBits > DestBits-MidBits) 2980 return Op; 2981 } else if (OpBits < DestBits) { 2982 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2983 // bits, just sext from i32. 2984 if (NumSignBits > OpBits-MidBits) 2985 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 2986 } else { 2987 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2988 // bits, just truncate to i32. 2989 if (NumSignBits > OpBits-MidBits) 2990 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 2991 } 2992 2993 // fold (sext (truncate x)) -> (sextinreg x). 2994 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2995 N0.getValueType())) { 2996 if (Op.getValueType().bitsLT(VT)) 2997 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 2998 else if (Op.getValueType().bitsGT(VT)) 2999 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3000 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3001 DAG.getValueType(N0.getValueType())); 3002 } 3003 } 3004 3005 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3006 if (ISD::isNON_EXTLoad(N0.getNode()) && 3007 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3008 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3009 bool DoXform = true; 3010 SmallVector<SDNode*, 4> SetCCs; 3011 if (!N0.hasOneUse()) 3012 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3013 if (DoXform) { 3014 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3015 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3016 LN0->getChain(), 3017 LN0->getBasePtr(), LN0->getSrcValue(), 3018 LN0->getSrcValueOffset(), 3019 N0.getValueType(), 3020 LN0->isVolatile(), LN0->getAlignment()); 3021 CombineTo(N, ExtLoad); 3022 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3023 N0.getValueType(), ExtLoad); 3024 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3025 3026 // Extend SetCC uses if necessary. 3027 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3028 SDNode *SetCC = SetCCs[i]; 3029 SmallVector<SDValue, 4> Ops; 3030 3031 for (unsigned j = 0; j != 2; ++j) { 3032 SDValue SOp = SetCC->getOperand(j); 3033 if (SOp == Trunc) 3034 Ops.push_back(ExtLoad); 3035 else 3036 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3037 N->getDebugLoc(), VT, SOp)); 3038 } 3039 3040 Ops.push_back(SetCC->getOperand(2)); 3041 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3042 SetCC->getValueType(0), 3043 &Ops[0], Ops.size())); 3044 } 3045 3046 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3047 } 3048 } 3049 3050 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3051 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3052 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3053 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3054 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3055 MVT EVT = LN0->getMemoryVT(); 3056 if ((!LegalOperations && !LN0->isVolatile()) || 3057 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3058 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3059 LN0->getChain(), 3060 LN0->getBasePtr(), LN0->getSrcValue(), 3061 LN0->getSrcValueOffset(), EVT, 3062 LN0->isVolatile(), LN0->getAlignment()); 3063 CombineTo(N, ExtLoad); 3064 CombineTo(N0.getNode(), 3065 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3066 N0.getValueType(), ExtLoad), 3067 ExtLoad.getValue(1)); 3068 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3069 } 3070 } 3071 3072 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3073 if (N0.getOpcode() == ISD::SETCC) { 3074 SDValue SCC = 3075 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3076 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3077 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3078 if (SCC.getNode()) return SCC; 3079 } 3080 3081 // fold (sext x) -> (zext x) if the sign bit is known zero. 3082 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3083 DAG.SignBitIsZero(N0)) 3084 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3085 3086 return SDValue(); 3087} 3088 3089SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3090 SDValue N0 = N->getOperand(0); 3091 MVT VT = N->getValueType(0); 3092 3093 // fold (zext c1) -> c1 3094 if (isa<ConstantSDNode>(N0)) 3095 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3096 // fold (zext (zext x)) -> (zext x) 3097 // fold (zext (aext x)) -> (zext x) 3098 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3099 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3100 N0.getOperand(0)); 3101 3102 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3103 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3104 if (N0.getOpcode() == ISD::TRUNCATE) { 3105 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3106 if (NarrowLoad.getNode()) { 3107 if (NarrowLoad.getNode() != N0.getNode()) 3108 CombineTo(N0.getNode(), NarrowLoad); 3109 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3110 } 3111 } 3112 3113 // fold (zext (truncate x)) -> (and x, mask) 3114 if (N0.getOpcode() == ISD::TRUNCATE && 3115 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3116 SDValue Op = N0.getOperand(0); 3117 if (Op.getValueType().bitsLT(VT)) { 3118 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3119 } else if (Op.getValueType().bitsGT(VT)) { 3120 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3121 } 3122 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3123 } 3124 3125 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3126 // if either of the casts is not free. 3127 if (N0.getOpcode() == ISD::AND && 3128 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3129 N0.getOperand(1).getOpcode() == ISD::Constant && 3130 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3131 N0.getValueType()) || 3132 !TLI.isZExtFree(N0.getValueType(), VT))) { 3133 SDValue X = N0.getOperand(0).getOperand(0); 3134 if (X.getValueType().bitsLT(VT)) { 3135 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3136 } else if (X.getValueType().bitsGT(VT)) { 3137 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3138 } 3139 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3140 Mask.zext(VT.getSizeInBits()); 3141 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3142 X, DAG.getConstant(Mask, VT)); 3143 } 3144 3145 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3146 if (ISD::isNON_EXTLoad(N0.getNode()) && 3147 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3148 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3149 bool DoXform = true; 3150 SmallVector<SDNode*, 4> SetCCs; 3151 if (!N0.hasOneUse()) 3152 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3153 if (DoXform) { 3154 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3155 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3156 LN0->getChain(), 3157 LN0->getBasePtr(), LN0->getSrcValue(), 3158 LN0->getSrcValueOffset(), 3159 N0.getValueType(), 3160 LN0->isVolatile(), LN0->getAlignment()); 3161 CombineTo(N, ExtLoad); 3162 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3163 N0.getValueType(), ExtLoad); 3164 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3165 3166 // Extend SetCC uses if necessary. 3167 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3168 SDNode *SetCC = SetCCs[i]; 3169 SmallVector<SDValue, 4> Ops; 3170 3171 for (unsigned j = 0; j != 2; ++j) { 3172 SDValue SOp = SetCC->getOperand(j); 3173 if (SOp == Trunc) 3174 Ops.push_back(ExtLoad); 3175 else 3176 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3177 N->getDebugLoc(), VT, SOp)); 3178 } 3179 3180 Ops.push_back(SetCC->getOperand(2)); 3181 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3182 SetCC->getValueType(0), 3183 &Ops[0], Ops.size())); 3184 } 3185 3186 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3187 } 3188 } 3189 3190 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3191 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3192 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3193 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3194 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3195 MVT EVT = LN0->getMemoryVT(); 3196 if ((!LegalOperations && !LN0->isVolatile()) || 3197 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3198 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3199 LN0->getChain(), 3200 LN0->getBasePtr(), LN0->getSrcValue(), 3201 LN0->getSrcValueOffset(), EVT, 3202 LN0->isVolatile(), LN0->getAlignment()); 3203 CombineTo(N, ExtLoad); 3204 CombineTo(N0.getNode(), 3205 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3206 ExtLoad), 3207 ExtLoad.getValue(1)); 3208 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3209 } 3210 } 3211 3212 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3213 if (N0.getOpcode() == ISD::SETCC) { 3214 SDValue SCC = 3215 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3216 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3217 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3218 if (SCC.getNode()) return SCC; 3219 } 3220 3221 return SDValue(); 3222} 3223 3224SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3225 SDValue N0 = N->getOperand(0); 3226 MVT VT = N->getValueType(0); 3227 3228 // fold (aext c1) -> c1 3229 if (isa<ConstantSDNode>(N0)) 3230 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3231 // fold (aext (aext x)) -> (aext x) 3232 // fold (aext (zext x)) -> (zext x) 3233 // fold (aext (sext x)) -> (sext x) 3234 if (N0.getOpcode() == ISD::ANY_EXTEND || 3235 N0.getOpcode() == ISD::ZERO_EXTEND || 3236 N0.getOpcode() == ISD::SIGN_EXTEND) 3237 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3238 3239 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3240 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3241 if (N0.getOpcode() == ISD::TRUNCATE) { 3242 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3243 if (NarrowLoad.getNode()) { 3244 if (NarrowLoad.getNode() != N0.getNode()) 3245 CombineTo(N0.getNode(), NarrowLoad); 3246 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3247 } 3248 } 3249 3250 // fold (aext (truncate x)) 3251 if (N0.getOpcode() == ISD::TRUNCATE) { 3252 SDValue TruncOp = N0.getOperand(0); 3253 if (TruncOp.getValueType() == VT) 3254 return TruncOp; // x iff x size == zext size. 3255 if (TruncOp.getValueType().bitsGT(VT)) 3256 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3257 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3258 } 3259 3260 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3261 // if the trunc is not free. 3262 if (N0.getOpcode() == ISD::AND && 3263 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3264 N0.getOperand(1).getOpcode() == ISD::Constant && 3265 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3266 N0.getValueType())) { 3267 SDValue X = N0.getOperand(0).getOperand(0); 3268 if (X.getValueType().bitsLT(VT)) { 3269 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3270 } else if (X.getValueType().bitsGT(VT)) { 3271 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3272 } 3273 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3274 Mask.zext(VT.getSizeInBits()); 3275 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3276 X, DAG.getConstant(Mask, VT)); 3277 } 3278 3279 // fold (aext (load x)) -> (aext (truncate (extload x))) 3280 if (ISD::isNON_EXTLoad(N0.getNode()) && 3281 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3282 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3283 bool DoXform = true; 3284 SmallVector<SDNode*, 4> SetCCs; 3285 if (!N0.hasOneUse()) 3286 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3287 if (DoXform) { 3288 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3289 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3290 LN0->getChain(), 3291 LN0->getBasePtr(), LN0->getSrcValue(), 3292 LN0->getSrcValueOffset(), 3293 N0.getValueType(), 3294 LN0->isVolatile(), LN0->getAlignment()); 3295 CombineTo(N, ExtLoad); 3296 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3297 N0.getValueType(), ExtLoad); 3298 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3299 3300 // Extend SetCC uses if necessary. 3301 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3302 SDNode *SetCC = SetCCs[i]; 3303 SmallVector<SDValue, 4> Ops; 3304 3305 for (unsigned j = 0; j != 2; ++j) { 3306 SDValue SOp = SetCC->getOperand(j); 3307 if (SOp == Trunc) 3308 Ops.push_back(ExtLoad); 3309 else 3310 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3311 N->getDebugLoc(), VT, SOp)); 3312 } 3313 3314 Ops.push_back(SetCC->getOperand(2)); 3315 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3316 SetCC->getValueType(0), 3317 &Ops[0], Ops.size())); 3318 } 3319 3320 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3321 } 3322 } 3323 3324 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3325 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3326 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3327 if (N0.getOpcode() == ISD::LOAD && 3328 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3329 N0.hasOneUse()) { 3330 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3331 MVT EVT = LN0->getMemoryVT(); 3332 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3333 VT, LN0->getChain(), LN0->getBasePtr(), 3334 LN0->getSrcValue(), 3335 LN0->getSrcValueOffset(), EVT, 3336 LN0->isVolatile(), LN0->getAlignment()); 3337 CombineTo(N, ExtLoad); 3338 CombineTo(N0.getNode(), 3339 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3340 N0.getValueType(), ExtLoad), 3341 ExtLoad.getValue(1)); 3342 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3343 } 3344 3345 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3346 if (N0.getOpcode() == ISD::SETCC) { 3347 SDValue SCC = 3348 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3349 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3350 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3351 if (SCC.getNode()) 3352 return SCC; 3353 } 3354 3355 return SDValue(); 3356} 3357 3358/// GetDemandedBits - See if the specified operand can be simplified with the 3359/// knowledge that only the bits specified by Mask are used. If so, return the 3360/// simpler operand, otherwise return a null SDValue. 3361SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3362 switch (V.getOpcode()) { 3363 default: break; 3364 case ISD::OR: 3365 case ISD::XOR: 3366 // If the LHS or RHS don't contribute bits to the or, drop them. 3367 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3368 return V.getOperand(1); 3369 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3370 return V.getOperand(0); 3371 break; 3372 case ISD::SRL: 3373 // Only look at single-use SRLs. 3374 if (!V.getNode()->hasOneUse()) 3375 break; 3376 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3377 // See if we can recursively simplify the LHS. 3378 unsigned Amt = RHSC->getZExtValue(); 3379 3380 // Watch out for shift count overflow though. 3381 if (Amt >= Mask.getBitWidth()) break; 3382 APInt NewMask = Mask << Amt; 3383 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3384 if (SimplifyLHS.getNode()) 3385 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3386 SimplifyLHS, V.getOperand(1)); 3387 } 3388 } 3389 return SDValue(); 3390} 3391 3392/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3393/// bits and then truncated to a narrower type and where N is a multiple 3394/// of number of bits of the narrower type, transform it to a narrower load 3395/// from address + N / num of bits of new type. If the result is to be 3396/// extended, also fold the extension to form a extending load. 3397SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3398 unsigned Opc = N->getOpcode(); 3399 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3400 SDValue N0 = N->getOperand(0); 3401 MVT VT = N->getValueType(0); 3402 MVT EVT = VT; 3403 3404 // This transformation isn't valid for vector loads. 3405 if (VT.isVector()) 3406 return SDValue(); 3407 3408 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3409 // extended to VT. 3410 if (Opc == ISD::SIGN_EXTEND_INREG) { 3411 ExtType = ISD::SEXTLOAD; 3412 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3413 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3414 return SDValue(); 3415 } 3416 3417 unsigned EVTBits = EVT.getSizeInBits(); 3418 unsigned ShAmt = 0; 3419 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3420 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3421 ShAmt = N01->getZExtValue(); 3422 // Is the shift amount a multiple of size of VT? 3423 if ((ShAmt & (EVTBits-1)) == 0) { 3424 N0 = N0.getOperand(0); 3425 if (N0.getValueType().getSizeInBits() <= EVTBits) 3426 return SDValue(); 3427 } 3428 } 3429 } 3430 3431 // Do not generate loads of non-round integer types since these can 3432 // be expensive (and would be wrong if the type is not byte sized). 3433 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3434 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3435 // Do not change the width of a volatile load. 3436 !cast<LoadSDNode>(N0)->isVolatile()) { 3437 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3438 MVT PtrType = N0.getOperand(1).getValueType(); 3439 3440 // For big endian targets, we need to adjust the offset to the pointer to 3441 // load the correct bytes. 3442 if (TLI.isBigEndian()) { 3443 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3444 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3445 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3446 } 3447 3448 uint64_t PtrOff = ShAmt / 8; 3449 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3450 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3451 PtrType, LN0->getBasePtr(), 3452 DAG.getConstant(PtrOff, PtrType)); 3453 AddToWorkList(NewPtr.getNode()); 3454 3455 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3456 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3457 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3458 LN0->isVolatile(), NewAlign) 3459 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3460 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3461 EVT, LN0->isVolatile(), NewAlign); 3462 3463 // Replace the old load's chain with the new load's chain. 3464 WorkListRemover DeadNodes(*this); 3465 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3466 &DeadNodes); 3467 3468 // Return the new loaded value. 3469 return Load; 3470 } 3471 3472 return SDValue(); 3473} 3474 3475SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3476 SDValue N0 = N->getOperand(0); 3477 SDValue N1 = N->getOperand(1); 3478 MVT VT = N->getValueType(0); 3479 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3480 unsigned VTBits = VT.getSizeInBits(); 3481 unsigned EVTBits = EVT.getSizeInBits(); 3482 3483 // fold (sext_in_reg c1) -> c1 3484 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3485 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3486 3487 // If the input is already sign extended, just drop the extension. 3488 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3489 return N0; 3490 3491 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3492 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3493 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3494 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3495 N0.getOperand(0), N1); 3496 } 3497 3498 // fold (sext_in_reg (sext x)) -> (sext x) 3499 // fold (sext_in_reg (aext x)) -> (sext x) 3500 // if x is small enough. 3501 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3502 SDValue N00 = N0.getOperand(0); 3503 if (N00.getValueType().getSizeInBits() < EVTBits) 3504 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3505 } 3506 3507 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3508 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3509 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3510 3511 // fold operands of sext_in_reg based on knowledge that the top bits are not 3512 // demanded. 3513 if (SimplifyDemandedBits(SDValue(N, 0))) 3514 return SDValue(N, 0); 3515 3516 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3517 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3518 SDValue NarrowLoad = ReduceLoadWidth(N); 3519 if (NarrowLoad.getNode()) 3520 return NarrowLoad; 3521 3522 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3523 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3524 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3525 if (N0.getOpcode() == ISD::SRL) { 3526 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3527 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3528 // We can turn this into an SRA iff the input to the SRL is already sign 3529 // extended enough. 3530 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3531 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3532 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3533 N0.getOperand(0), N0.getOperand(1)); 3534 } 3535 } 3536 3537 // fold (sext_inreg (extload x)) -> (sextload x) 3538 if (ISD::isEXTLoad(N0.getNode()) && 3539 ISD::isUNINDEXEDLoad(N0.getNode()) && 3540 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3541 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3542 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3543 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3544 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3545 LN0->getChain(), 3546 LN0->getBasePtr(), LN0->getSrcValue(), 3547 LN0->getSrcValueOffset(), EVT, 3548 LN0->isVolatile(), LN0->getAlignment()); 3549 CombineTo(N, ExtLoad); 3550 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3551 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3552 } 3553 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3554 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3555 N0.hasOneUse() && 3556 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3557 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3558 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3559 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3560 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3561 LN0->getChain(), 3562 LN0->getBasePtr(), LN0->getSrcValue(), 3563 LN0->getSrcValueOffset(), EVT, 3564 LN0->isVolatile(), LN0->getAlignment()); 3565 CombineTo(N, ExtLoad); 3566 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3567 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3568 } 3569 return SDValue(); 3570} 3571 3572SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3573 SDValue N0 = N->getOperand(0); 3574 MVT VT = N->getValueType(0); 3575 3576 // noop truncate 3577 if (N0.getValueType() == N->getValueType(0)) 3578 return N0; 3579 // fold (truncate c1) -> c1 3580 if (isa<ConstantSDNode>(N0)) 3581 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3582 // fold (truncate (truncate x)) -> (truncate x) 3583 if (N0.getOpcode() == ISD::TRUNCATE) 3584 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3585 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3586 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3587 N0.getOpcode() == ISD::ANY_EXTEND) { 3588 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3589 // if the source is smaller than the dest, we still need an extend 3590 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3591 N0.getOperand(0)); 3592 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3593 // if the source is larger than the dest, than we just need the truncate 3594 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3595 else 3596 // if the source and dest are the same type, we can drop both the extend 3597 // and the truncate 3598 return N0.getOperand(0); 3599 } 3600 3601 // See if we can simplify the input to this truncate through knowledge that 3602 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3603 // -> trunc y 3604 SDValue Shorter = 3605 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3606 VT.getSizeInBits())); 3607 if (Shorter.getNode()) 3608 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3609 3610 // fold (truncate (load x)) -> (smaller load x) 3611 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3612 return ReduceLoadWidth(N); 3613} 3614 3615static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3616 SDValue Elt = N->getOperand(i); 3617 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3618 return Elt.getNode(); 3619 return Elt.getOperand(Elt.getResNo()).getNode(); 3620} 3621 3622/// CombineConsecutiveLoads - build_pair (load, load) -> load 3623/// if load locations are consecutive. 3624SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3625 assert(N->getOpcode() == ISD::BUILD_PAIR); 3626 3627 SDNode *LD1 = getBuildPairElt(N, 0); 3628 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3629 return SDValue(); 3630 MVT LD1VT = LD1->getValueType(0); 3631 SDNode *LD2 = getBuildPairElt(N, 1); 3632 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3633 3634 if (ISD::isNON_EXTLoad(LD2) && 3635 LD2->hasOneUse() && 3636 // If both are volatile this would reduce the number of volatile loads. 3637 // If one is volatile it might be ok, but play conservative and bail out. 3638 !cast<LoadSDNode>(LD1)->isVolatile() && 3639 !cast<LoadSDNode>(LD2)->isVolatile() && 3640 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3641 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3642 unsigned Align = LD->getAlignment(); 3643 unsigned NewAlign = TLI.getTargetData()-> 3644 getABITypeAlignment(VT.getTypeForMVT()); 3645 3646 if (NewAlign <= Align && 3647 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3648 return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(), 3649 LD->getSrcValue(), LD->getSrcValueOffset(), 3650 false, Align); 3651 } 3652 3653 return SDValue(); 3654} 3655 3656SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3657 SDValue N0 = N->getOperand(0); 3658 MVT VT = N->getValueType(0); 3659 3660 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3661 // Only do this before legalize, since afterward the target may be depending 3662 // on the bitconvert. 3663 // First check to see if this is all constant. 3664 if (!LegalTypes && 3665 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3666 VT.isVector()) { 3667 bool isSimple = true; 3668 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3669 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3670 N0.getOperand(i).getOpcode() != ISD::Constant && 3671 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3672 isSimple = false; 3673 break; 3674 } 3675 3676 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3677 assert(!DestEltVT.isVector() && 3678 "Element type of vector ValueType must not be vector!"); 3679 if (isSimple) 3680 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3681 } 3682 3683 // If the input is a constant, let getNode fold it. 3684 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3685 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3686 if (Res.getNode() != N) return Res; 3687 } 3688 3689 // (conv (conv x, t1), t2) -> (conv x, t2) 3690 if (N0.getOpcode() == ISD::BIT_CONVERT) 3691 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3692 N0.getOperand(0)); 3693 3694 // fold (conv (load x)) -> (load (conv*)x) 3695 // If the resultant load doesn't need a higher alignment than the original! 3696 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3697 // Do not change the width of a volatile load. 3698 !cast<LoadSDNode>(N0)->isVolatile() && 3699 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3700 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3701 unsigned Align = TLI.getTargetData()-> 3702 getABITypeAlignment(VT.getTypeForMVT()); 3703 unsigned OrigAlign = LN0->getAlignment(); 3704 3705 if (Align <= OrigAlign) { 3706 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3707 LN0->getBasePtr(), 3708 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3709 LN0->isVolatile(), OrigAlign); 3710 AddToWorkList(N); 3711 CombineTo(N0.getNode(), 3712 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3713 N0.getValueType(), Load), 3714 Load.getValue(1)); 3715 return Load; 3716 } 3717 } 3718 3719 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3720 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3721 // This often reduces constant pool loads. 3722 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3723 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3724 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3725 N0.getOperand(0)); 3726 AddToWorkList(NewConv.getNode()); 3727 3728 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3729 if (N0.getOpcode() == ISD::FNEG) 3730 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3731 NewConv, DAG.getConstant(SignBit, VT)); 3732 assert(N0.getOpcode() == ISD::FABS); 3733 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3734 NewConv, DAG.getConstant(~SignBit, VT)); 3735 } 3736 3737 // fold (bitconvert (fcopysign cst, x)) -> 3738 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3739 // Note that we don't handle (copysign x, cst) because this can always be 3740 // folded to an fneg or fabs. 3741 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3742 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3743 VT.isInteger() && !VT.isVector()) { 3744 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3745 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3746 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3747 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3748 IntXVT, N0.getOperand(1)); 3749 AddToWorkList(X.getNode()); 3750 3751 // If X has a different width than the result/lhs, sext it or truncate it. 3752 unsigned VTWidth = VT.getSizeInBits(); 3753 if (OrigXWidth < VTWidth) { 3754 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3755 AddToWorkList(X.getNode()); 3756 } else if (OrigXWidth > VTWidth) { 3757 // To get the sign bit in the right place, we have to shift it right 3758 // before truncating. 3759 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3760 X.getValueType(), X, 3761 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3762 AddToWorkList(X.getNode()); 3763 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3764 AddToWorkList(X.getNode()); 3765 } 3766 3767 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3768 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3769 X, DAG.getConstant(SignBit, VT)); 3770 AddToWorkList(X.getNode()); 3771 3772 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3773 VT, N0.getOperand(0)); 3774 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3775 Cst, DAG.getConstant(~SignBit, VT)); 3776 AddToWorkList(Cst.getNode()); 3777 3778 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3779 } 3780 } 3781 3782 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3783 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3784 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3785 if (CombineLD.getNode()) 3786 return CombineLD; 3787 } 3788 3789 return SDValue(); 3790} 3791 3792SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3793 MVT VT = N->getValueType(0); 3794 return CombineConsecutiveLoads(N, VT); 3795} 3796 3797/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3798/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3799/// destination element value type. 3800SDValue DAGCombiner:: 3801ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3802 MVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3803 3804 // If this is already the right type, we're done. 3805 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3806 3807 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3808 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3809 3810 // If this is a conversion of N elements of one type to N elements of another 3811 // type, convert each element. This handles FP<->INT cases. 3812 if (SrcBitSize == DstBitSize) { 3813 SmallVector<SDValue, 8> Ops; 3814 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3815 SDValue Op = BV->getOperand(i); 3816 // If the vector element type is not legal, the BUILD_VECTOR operands 3817 // are promoted and implicitly truncated. Make that explicit here. 3818 if (Op.getValueType() != SrcEltVT) 3819 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3820 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3821 DstEltVT, Op)); 3822 AddToWorkList(Ops.back().getNode()); 3823 } 3824 MVT VT = MVT::getVectorVT(DstEltVT, 3825 BV->getValueType(0).getVectorNumElements()); 3826 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3827 &Ops[0], Ops.size()); 3828 } 3829 3830 // Otherwise, we're growing or shrinking the elements. To avoid having to 3831 // handle annoying details of growing/shrinking FP values, we convert them to 3832 // int first. 3833 if (SrcEltVT.isFloatingPoint()) { 3834 // Convert the input float vector to a int vector where the elements are the 3835 // same sizes. 3836 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3837 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3838 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3839 SrcEltVT = IntVT; 3840 } 3841 3842 // Now we know the input is an integer vector. If the output is a FP type, 3843 // convert to integer first, then to FP of the right size. 3844 if (DstEltVT.isFloatingPoint()) { 3845 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3846 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3847 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3848 3849 // Next, convert to FP elements of the same size. 3850 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3851 } 3852 3853 // Okay, we know the src/dst types are both integers of differing types. 3854 // Handling growing first. 3855 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3856 if (SrcBitSize < DstBitSize) { 3857 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3858 3859 SmallVector<SDValue, 8> Ops; 3860 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3861 i += NumInputsPerOutput) { 3862 bool isLE = TLI.isLittleEndian(); 3863 APInt NewBits = APInt(DstBitSize, 0); 3864 bool EltIsUndef = true; 3865 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3866 // Shift the previously computed bits over. 3867 NewBits <<= SrcBitSize; 3868 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3869 if (Op.getOpcode() == ISD::UNDEF) continue; 3870 EltIsUndef = false; 3871 3872 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 3873 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 3874 } 3875 3876 if (EltIsUndef) 3877 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3878 else 3879 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3880 } 3881 3882 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3883 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3884 &Ops[0], Ops.size()); 3885 } 3886 3887 // Finally, this must be the case where we are shrinking elements: each input 3888 // turns into multiple outputs. 3889 bool isS2V = ISD::isScalarToVector(BV); 3890 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3891 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3892 SmallVector<SDValue, 8> Ops; 3893 3894 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3895 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3896 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3897 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3898 continue; 3899 } 3900 3901 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 3902 getAPIntValue()).zextOrTrunc(SrcBitSize); 3903 3904 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3905 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3906 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3907 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3908 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3909 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3910 Ops[0]); 3911 OpVal = OpVal.lshr(DstBitSize); 3912 } 3913 3914 // For big endian targets, swap the order of the pieces of each element. 3915 if (TLI.isBigEndian()) 3916 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3917 } 3918 3919 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3920 &Ops[0], Ops.size()); 3921} 3922 3923SDValue DAGCombiner::visitFADD(SDNode *N) { 3924 SDValue N0 = N->getOperand(0); 3925 SDValue N1 = N->getOperand(1); 3926 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3927 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3928 MVT VT = N->getValueType(0); 3929 3930 // fold vector ops 3931 if (VT.isVector()) { 3932 SDValue FoldedVOp = SimplifyVBinOp(N); 3933 if (FoldedVOp.getNode()) return FoldedVOp; 3934 } 3935 3936 // fold (fadd c1, c2) -> (fadd c1, c2) 3937 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3938 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3939 // canonicalize constant to RHS 3940 if (N0CFP && !N1CFP) 3941 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3942 // fold (fadd A, 0) -> A 3943 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3944 return N0; 3945 // fold (fadd A, (fneg B)) -> (fsub A, B) 3946 if (isNegatibleForFree(N1, LegalOperations) == 2) 3947 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3948 GetNegatedExpression(N1, DAG, LegalOperations)); 3949 // fold (fadd (fneg A), B) -> (fsub B, A) 3950 if (isNegatibleForFree(N0, LegalOperations) == 2) 3951 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3952 GetNegatedExpression(N0, DAG, LegalOperations)); 3953 3954 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3955 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3956 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3957 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3958 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3959 N0.getOperand(1), N1)); 3960 3961 return SDValue(); 3962} 3963 3964SDValue DAGCombiner::visitFSUB(SDNode *N) { 3965 SDValue N0 = N->getOperand(0); 3966 SDValue N1 = N->getOperand(1); 3967 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3968 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3969 MVT VT = N->getValueType(0); 3970 3971 // fold vector ops 3972 if (VT.isVector()) { 3973 SDValue FoldedVOp = SimplifyVBinOp(N); 3974 if (FoldedVOp.getNode()) return FoldedVOp; 3975 } 3976 3977 // fold (fsub c1, c2) -> c1-c2 3978 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3979 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 3980 // fold (fsub A, 0) -> A 3981 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3982 return N0; 3983 // fold (fsub 0, B) -> -B 3984 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3985 if (isNegatibleForFree(N1, LegalOperations)) 3986 return GetNegatedExpression(N1, DAG, LegalOperations); 3987 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3988 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 3989 } 3990 // fold (fsub A, (fneg B)) -> (fadd A, B) 3991 if (isNegatibleForFree(N1, LegalOperations)) 3992 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 3993 GetNegatedExpression(N1, DAG, LegalOperations)); 3994 3995 return SDValue(); 3996} 3997 3998SDValue DAGCombiner::visitFMUL(SDNode *N) { 3999 SDValue N0 = N->getOperand(0); 4000 SDValue N1 = N->getOperand(1); 4001 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4002 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4003 MVT VT = N->getValueType(0); 4004 4005 // fold vector ops 4006 if (VT.isVector()) { 4007 SDValue FoldedVOp = SimplifyVBinOp(N); 4008 if (FoldedVOp.getNode()) return FoldedVOp; 4009 } 4010 4011 // fold (fmul c1, c2) -> c1*c2 4012 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4013 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4014 // canonicalize constant to RHS 4015 if (N0CFP && !N1CFP) 4016 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4017 // fold (fmul A, 0) -> 0 4018 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4019 return N1; 4020 // fold (fmul X, 2.0) -> (fadd X, X) 4021 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4022 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4023 // fold (fmul X, (fneg 1.0)) -> (fneg X) 4024 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4025 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4026 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4027 4028 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4029 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4030 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4031 // Both can be negated for free, check to see if at least one is cheaper 4032 // negated. 4033 if (LHSNeg == 2 || RHSNeg == 2) 4034 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4035 GetNegatedExpression(N0, DAG, LegalOperations), 4036 GetNegatedExpression(N1, DAG, LegalOperations)); 4037 } 4038 } 4039 4040 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4041 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4042 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4043 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4044 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4045 N0.getOperand(1), N1)); 4046 4047 return SDValue(); 4048} 4049 4050SDValue DAGCombiner::visitFDIV(SDNode *N) { 4051 SDValue N0 = N->getOperand(0); 4052 SDValue N1 = N->getOperand(1); 4053 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4054 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4055 MVT VT = N->getValueType(0); 4056 4057 // fold vector ops 4058 if (VT.isVector()) { 4059 SDValue FoldedVOp = SimplifyVBinOp(N); 4060 if (FoldedVOp.getNode()) return FoldedVOp; 4061 } 4062 4063 // fold (fdiv c1, c2) -> c1/c2 4064 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4065 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4066 4067 4068 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4069 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4070 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4071 // Both can be negated for free, check to see if at least one is cheaper 4072 // negated. 4073 if (LHSNeg == 2 || RHSNeg == 2) 4074 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4075 GetNegatedExpression(N0, DAG, LegalOperations), 4076 GetNegatedExpression(N1, DAG, LegalOperations)); 4077 } 4078 } 4079 4080 return SDValue(); 4081} 4082 4083SDValue DAGCombiner::visitFREM(SDNode *N) { 4084 SDValue N0 = N->getOperand(0); 4085 SDValue N1 = N->getOperand(1); 4086 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4087 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4088 MVT VT = N->getValueType(0); 4089 4090 // fold (frem c1, c2) -> fmod(c1,c2) 4091 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4092 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4093 4094 return SDValue(); 4095} 4096 4097SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4098 SDValue N0 = N->getOperand(0); 4099 SDValue N1 = N->getOperand(1); 4100 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4101 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4102 MVT VT = N->getValueType(0); 4103 4104 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4105 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4106 4107 if (N1CFP) { 4108 const APFloat& V = N1CFP->getValueAPF(); 4109 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4110 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4111 if (!V.isNegative()) { 4112 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4113 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4114 } else { 4115 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4116 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4117 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4118 } 4119 } 4120 4121 // copysign(fabs(x), y) -> copysign(x, y) 4122 // copysign(fneg(x), y) -> copysign(x, y) 4123 // copysign(copysign(x,z), y) -> copysign(x, y) 4124 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4125 N0.getOpcode() == ISD::FCOPYSIGN) 4126 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4127 N0.getOperand(0), N1); 4128 4129 // copysign(x, abs(y)) -> abs(x) 4130 if (N1.getOpcode() == ISD::FABS) 4131 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4132 4133 // copysign(x, copysign(y,z)) -> copysign(x, z) 4134 if (N1.getOpcode() == ISD::FCOPYSIGN) 4135 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4136 N0, N1.getOperand(1)); 4137 4138 // copysign(x, fp_extend(y)) -> copysign(x, y) 4139 // copysign(x, fp_round(y)) -> copysign(x, y) 4140 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4141 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4142 N0, N1.getOperand(0)); 4143 4144 return SDValue(); 4145} 4146 4147SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4148 SDValue N0 = N->getOperand(0); 4149 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4150 MVT VT = N->getValueType(0); 4151 MVT OpVT = N0.getValueType(); 4152 4153 // fold (sint_to_fp c1) -> c1fp 4154 if (N0C && OpVT != MVT::ppcf128) 4155 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4156 4157 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4158 // but UINT_TO_FP is legal on this target, try to convert. 4159 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4160 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4161 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4162 if (DAG.SignBitIsZero(N0)) 4163 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4164 } 4165 4166 return SDValue(); 4167} 4168 4169SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4170 SDValue N0 = N->getOperand(0); 4171 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4172 MVT VT = N->getValueType(0); 4173 MVT OpVT = N0.getValueType(); 4174 4175 // fold (uint_to_fp c1) -> c1fp 4176 if (N0C && OpVT != MVT::ppcf128) 4177 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4178 4179 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4180 // but SINT_TO_FP is legal on this target, try to convert. 4181 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4182 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4183 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4184 if (DAG.SignBitIsZero(N0)) 4185 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4186 } 4187 4188 return SDValue(); 4189} 4190 4191SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4192 SDValue N0 = N->getOperand(0); 4193 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4194 MVT VT = N->getValueType(0); 4195 4196 // fold (fp_to_sint c1fp) -> c1 4197 if (N0CFP) 4198 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4199 4200 return SDValue(); 4201} 4202 4203SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4204 SDValue N0 = N->getOperand(0); 4205 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4206 MVT VT = N->getValueType(0); 4207 4208 // fold (fp_to_uint c1fp) -> c1 4209 if (N0CFP && VT != MVT::ppcf128) 4210 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4211 4212 return SDValue(); 4213} 4214 4215SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4216 SDValue N0 = N->getOperand(0); 4217 SDValue N1 = N->getOperand(1); 4218 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4219 MVT VT = N->getValueType(0); 4220 4221 // fold (fp_round c1fp) -> c1fp 4222 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4223 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4224 4225 // fold (fp_round (fp_extend x)) -> x 4226 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4227 return N0.getOperand(0); 4228 4229 // fold (fp_round (fp_round x)) -> (fp_round x) 4230 if (N0.getOpcode() == ISD::FP_ROUND) { 4231 // This is a value preserving truncation if both round's are. 4232 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4233 N0.getNode()->getConstantOperandVal(1) == 1; 4234 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4235 DAG.getIntPtrConstant(IsTrunc)); 4236 } 4237 4238 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4239 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4240 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4241 N0.getOperand(0), N1); 4242 AddToWorkList(Tmp.getNode()); 4243 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4244 Tmp, N0.getOperand(1)); 4245 } 4246 4247 return SDValue(); 4248} 4249 4250SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4251 SDValue N0 = N->getOperand(0); 4252 MVT VT = N->getValueType(0); 4253 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4254 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4255 4256 // fold (fp_round_inreg c1fp) -> c1fp 4257 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4258 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4259 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4260 } 4261 4262 return SDValue(); 4263} 4264 4265SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4266 SDValue N0 = N->getOperand(0); 4267 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4268 MVT VT = N->getValueType(0); 4269 4270 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4271 if (N->hasOneUse() && 4272 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4273 return SDValue(); 4274 4275 // fold (fp_extend c1fp) -> c1fp 4276 if (N0CFP && VT != MVT::ppcf128) 4277 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4278 4279 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4280 // value of X. 4281 if (N0.getOpcode() == ISD::FP_ROUND 4282 && N0.getNode()->getConstantOperandVal(1) == 1) { 4283 SDValue In = N0.getOperand(0); 4284 if (In.getValueType() == VT) return In; 4285 if (VT.bitsLT(In.getValueType())) 4286 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4287 In, N0.getOperand(1)); 4288 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4289 } 4290 4291 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4292 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4293 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4294 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4295 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4296 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4297 LN0->getChain(), 4298 LN0->getBasePtr(), LN0->getSrcValue(), 4299 LN0->getSrcValueOffset(), 4300 N0.getValueType(), 4301 LN0->isVolatile(), LN0->getAlignment()); 4302 CombineTo(N, ExtLoad); 4303 CombineTo(N0.getNode(), 4304 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4305 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4306 ExtLoad.getValue(1)); 4307 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4308 } 4309 4310 return SDValue(); 4311} 4312 4313SDValue DAGCombiner::visitFNEG(SDNode *N) { 4314 SDValue N0 = N->getOperand(0); 4315 4316 if (isNegatibleForFree(N0, LegalOperations)) 4317 return GetNegatedExpression(N0, DAG, LegalOperations); 4318 4319 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4320 // constant pool values. 4321 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4322 N0.getOperand(0).getValueType().isInteger() && 4323 !N0.getOperand(0).getValueType().isVector()) { 4324 SDValue Int = N0.getOperand(0); 4325 MVT IntVT = Int.getValueType(); 4326 if (IntVT.isInteger() && !IntVT.isVector()) { 4327 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4328 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4329 AddToWorkList(Int.getNode()); 4330 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4331 N->getValueType(0), Int); 4332 } 4333 } 4334 4335 return SDValue(); 4336} 4337 4338SDValue DAGCombiner::visitFABS(SDNode *N) { 4339 SDValue N0 = N->getOperand(0); 4340 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4341 MVT VT = N->getValueType(0); 4342 4343 // fold (fabs c1) -> fabs(c1) 4344 if (N0CFP && VT != MVT::ppcf128) 4345 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4346 // fold (fabs (fabs x)) -> (fabs x) 4347 if (N0.getOpcode() == ISD::FABS) 4348 return N->getOperand(0); 4349 // fold (fabs (fneg x)) -> (fabs x) 4350 // fold (fabs (fcopysign x, y)) -> (fabs x) 4351 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4352 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4353 4354 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4355 // constant pool values. 4356 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4357 N0.getOperand(0).getValueType().isInteger() && 4358 !N0.getOperand(0).getValueType().isVector()) { 4359 SDValue Int = N0.getOperand(0); 4360 MVT IntVT = Int.getValueType(); 4361 if (IntVT.isInteger() && !IntVT.isVector()) { 4362 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4363 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4364 AddToWorkList(Int.getNode()); 4365 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4366 N->getValueType(0), Int); 4367 } 4368 } 4369 4370 return SDValue(); 4371} 4372 4373SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4374 SDValue Chain = N->getOperand(0); 4375 SDValue N1 = N->getOperand(1); 4376 SDValue N2 = N->getOperand(2); 4377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4378 4379 // never taken branch, fold to chain 4380 if (N1C && N1C->isNullValue()) 4381 return Chain; 4382 // unconditional branch 4383 if (N1C && N1C->getAPIntValue() == 1) 4384 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4385 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4386 // on the target. 4387 if (N1.getOpcode() == ISD::SETCC && 4388 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4389 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4390 Chain, N1.getOperand(2), 4391 N1.getOperand(0), N1.getOperand(1), N2); 4392 } 4393 4394 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4395 // Match this pattern so that we can generate simpler code: 4396 // 4397 // %a = ... 4398 // %b = and i32 %a, 2 4399 // %c = srl i32 %b, 1 4400 // brcond i32 %c ... 4401 // 4402 // into 4403 // 4404 // %a = ... 4405 // %b = and %a, 2 4406 // %c = setcc eq %b, 0 4407 // brcond %c ... 4408 // 4409 // This applies only when the AND constant value has one bit set and the 4410 // SRL constant is equal to the log2 of the AND constant. The back-end is 4411 // smart enough to convert the result into a TEST/JMP sequence. 4412 SDValue Op0 = N1.getOperand(0); 4413 SDValue Op1 = N1.getOperand(1); 4414 4415 if (Op0.getOpcode() == ISD::AND && 4416 Op0.hasOneUse() && 4417 Op1.getOpcode() == ISD::Constant) { 4418 SDValue AndOp0 = Op0.getOperand(0); 4419 SDValue AndOp1 = Op0.getOperand(1); 4420 4421 if (AndOp1.getOpcode() == ISD::Constant) { 4422 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4423 4424 if (AndConst.isPowerOf2() && 4425 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4426 SDValue SetCC = 4427 DAG.getSetCC(N->getDebugLoc(), 4428 TLI.getSetCCResultType(Op0.getValueType()), 4429 Op0, DAG.getConstant(0, Op0.getValueType()), 4430 ISD::SETNE); 4431 4432 // Replace the uses of SRL with SETCC 4433 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4434 removeFromWorkList(N1.getNode()); 4435 DAG.DeleteNode(N1.getNode()); 4436 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4437 MVT::Other, Chain, SetCC, N2); 4438 } 4439 } 4440 } 4441 } 4442 4443 return SDValue(); 4444} 4445 4446// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4447// 4448SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4449 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4450 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4451 4452 // Use SimplifySetCC to simplify SETCC's. 4453 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4454 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4455 false); 4456 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4457 4458 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4459 4460 // fold br_cc true, dest -> br dest (unconditional branch) 4461 if (SCCC && !SCCC->isNullValue()) 4462 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4463 N->getOperand(0), N->getOperand(4)); 4464 // fold br_cc false, dest -> unconditional fall through 4465 if (SCCC && SCCC->isNullValue()) 4466 return N->getOperand(0); 4467 4468 // fold to a simpler setcc 4469 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4470 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4471 N->getOperand(0), Simp.getOperand(2), 4472 Simp.getOperand(0), Simp.getOperand(1), 4473 N->getOperand(4)); 4474 4475 return SDValue(); 4476} 4477 4478/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4479/// pre-indexed load / store when the base pointer is an add or subtract 4480/// and it has other uses besides the load / store. After the 4481/// transformation, the new indexed load / store has effectively folded 4482/// the add / subtract in and all of its other uses are redirected to the 4483/// new load / store. 4484bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4485 if (!LegalOperations) 4486 return false; 4487 4488 bool isLoad = true; 4489 SDValue Ptr; 4490 MVT VT; 4491 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4492 if (LD->isIndexed()) 4493 return false; 4494 VT = LD->getMemoryVT(); 4495 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4496 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4497 return false; 4498 Ptr = LD->getBasePtr(); 4499 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4500 if (ST->isIndexed()) 4501 return false; 4502 VT = ST->getMemoryVT(); 4503 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4504 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4505 return false; 4506 Ptr = ST->getBasePtr(); 4507 isLoad = false; 4508 } else { 4509 return false; 4510 } 4511 4512 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4513 // out. There is no reason to make this a preinc/predec. 4514 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4515 Ptr.getNode()->hasOneUse()) 4516 return false; 4517 4518 // Ask the target to do addressing mode selection. 4519 SDValue BasePtr; 4520 SDValue Offset; 4521 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4522 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4523 return false; 4524 // Don't create a indexed load / store with zero offset. 4525 if (isa<ConstantSDNode>(Offset) && 4526 cast<ConstantSDNode>(Offset)->isNullValue()) 4527 return false; 4528 4529 // Try turning it into a pre-indexed load / store except when: 4530 // 1) The new base ptr is a frame index. 4531 // 2) If N is a store and the new base ptr is either the same as or is a 4532 // predecessor of the value being stored. 4533 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4534 // that would create a cycle. 4535 // 4) All uses are load / store ops that use it as old base ptr. 4536 4537 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4538 // (plus the implicit offset) to a register to preinc anyway. 4539 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4540 return false; 4541 4542 // Check #2. 4543 if (!isLoad) { 4544 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4545 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4546 return false; 4547 } 4548 4549 // Now check for #3 and #4. 4550 bool RealUse = false; 4551 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4552 E = Ptr.getNode()->use_end(); I != E; ++I) { 4553 SDNode *Use = *I; 4554 if (Use == N) 4555 continue; 4556 if (Use->isPredecessorOf(N)) 4557 return false; 4558 4559 if (!((Use->getOpcode() == ISD::LOAD && 4560 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4561 (Use->getOpcode() == ISD::STORE && 4562 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4563 RealUse = true; 4564 } 4565 4566 if (!RealUse) 4567 return false; 4568 4569 SDValue Result; 4570 if (isLoad) 4571 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4572 BasePtr, Offset, AM); 4573 else 4574 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4575 BasePtr, Offset, AM); 4576 ++PreIndexedNodes; 4577 ++NodesCombined; 4578 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4579 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4580 DOUT << '\n'; 4581 WorkListRemover DeadNodes(*this); 4582 if (isLoad) { 4583 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4584 &DeadNodes); 4585 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4586 &DeadNodes); 4587 } else { 4588 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4589 &DeadNodes); 4590 } 4591 4592 // Finally, since the node is now dead, remove it from the graph. 4593 DAG.DeleteNode(N); 4594 4595 // Replace the uses of Ptr with uses of the updated base value. 4596 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4597 &DeadNodes); 4598 removeFromWorkList(Ptr.getNode()); 4599 DAG.DeleteNode(Ptr.getNode()); 4600 4601 return true; 4602} 4603 4604/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4605/// add / sub of the base pointer node into a post-indexed load / store. 4606/// The transformation folded the add / subtract into the new indexed 4607/// load / store effectively and all of its uses are redirected to the 4608/// new load / store. 4609bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4610 if (!LegalOperations) 4611 return false; 4612 4613 bool isLoad = true; 4614 SDValue Ptr; 4615 MVT VT; 4616 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4617 if (LD->isIndexed()) 4618 return false; 4619 VT = LD->getMemoryVT(); 4620 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4621 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4622 return false; 4623 Ptr = LD->getBasePtr(); 4624 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4625 if (ST->isIndexed()) 4626 return false; 4627 VT = ST->getMemoryVT(); 4628 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4629 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4630 return false; 4631 Ptr = ST->getBasePtr(); 4632 isLoad = false; 4633 } else { 4634 return false; 4635 } 4636 4637 if (Ptr.getNode()->hasOneUse()) 4638 return false; 4639 4640 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4641 E = Ptr.getNode()->use_end(); I != E; ++I) { 4642 SDNode *Op = *I; 4643 if (Op == N || 4644 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4645 continue; 4646 4647 SDValue BasePtr; 4648 SDValue Offset; 4649 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4650 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4651 if (Ptr == Offset) 4652 std::swap(BasePtr, Offset); 4653 if (Ptr != BasePtr) 4654 continue; 4655 // Don't create a indexed load / store with zero offset. 4656 if (isa<ConstantSDNode>(Offset) && 4657 cast<ConstantSDNode>(Offset)->isNullValue()) 4658 continue; 4659 4660 // Try turning it into a post-indexed load / store except when 4661 // 1) All uses are load / store ops that use it as base ptr. 4662 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4663 // nor a successor of N. Otherwise, if Op is folded that would 4664 // create a cycle. 4665 4666 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4667 continue; 4668 4669 // Check for #1. 4670 bool TryNext = false; 4671 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4672 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4673 SDNode *Use = *II; 4674 if (Use == Ptr.getNode()) 4675 continue; 4676 4677 // If all the uses are load / store addresses, then don't do the 4678 // transformation. 4679 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4680 bool RealUse = false; 4681 for (SDNode::use_iterator III = Use->use_begin(), 4682 EEE = Use->use_end(); III != EEE; ++III) { 4683 SDNode *UseUse = *III; 4684 if (!((UseUse->getOpcode() == ISD::LOAD && 4685 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4686 (UseUse->getOpcode() == ISD::STORE && 4687 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4688 RealUse = true; 4689 } 4690 4691 if (!RealUse) { 4692 TryNext = true; 4693 break; 4694 } 4695 } 4696 } 4697 4698 if (TryNext) 4699 continue; 4700 4701 // Check for #2 4702 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4703 SDValue Result = isLoad 4704 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4705 BasePtr, Offset, AM) 4706 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4707 BasePtr, Offset, AM); 4708 ++PostIndexedNodes; 4709 ++NodesCombined; 4710 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4711 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4712 DOUT << '\n'; 4713 WorkListRemover DeadNodes(*this); 4714 if (isLoad) { 4715 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4716 &DeadNodes); 4717 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4718 &DeadNodes); 4719 } else { 4720 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4721 &DeadNodes); 4722 } 4723 4724 // Finally, since the node is now dead, remove it from the graph. 4725 DAG.DeleteNode(N); 4726 4727 // Replace the uses of Use with uses of the updated base value. 4728 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4729 Result.getValue(isLoad ? 1 : 0), 4730 &DeadNodes); 4731 removeFromWorkList(Op); 4732 DAG.DeleteNode(Op); 4733 return true; 4734 } 4735 } 4736 } 4737 4738 return false; 4739} 4740 4741/// InferAlignment - If we can infer some alignment information from this 4742/// pointer, return it. 4743static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4744 // If this is a direct reference to a stack slot, use information about the 4745 // stack slot's alignment. 4746 int FrameIdx = 1 << 31; 4747 int64_t FrameOffset = 0; 4748 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4749 FrameIdx = FI->getIndex(); 4750 } else if (Ptr.getOpcode() == ISD::ADD && 4751 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4752 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4753 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4754 FrameOffset = Ptr.getConstantOperandVal(1); 4755 } 4756 4757 if (FrameIdx != (1 << 31)) { 4758 // FIXME: Handle FI+CST. 4759 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4760 if (MFI.isFixedObjectIndex(FrameIdx)) { 4761 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4762 4763 // The alignment of the frame index can be determined from its offset from 4764 // the incoming frame position. If the frame object is at offset 32 and 4765 // the stack is guaranteed to be 16-byte aligned, then we know that the 4766 // object is 16-byte aligned. 4767 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4768 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4769 4770 // Finally, the frame object itself may have a known alignment. Factor 4771 // the alignment + offset into a new alignment. For example, if we know 4772 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4773 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4774 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4775 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4776 FrameOffset); 4777 return std::max(Align, FIInfoAlign); 4778 } 4779 } 4780 4781 return 0; 4782} 4783 4784SDValue DAGCombiner::visitLOAD(SDNode *N) { 4785 LoadSDNode *LD = cast<LoadSDNode>(N); 4786 SDValue Chain = LD->getChain(); 4787 SDValue Ptr = LD->getBasePtr(); 4788 4789 // Try to infer better alignment information than the load already has. 4790 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4791 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4792 if (Align > LD->getAlignment()) 4793 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4794 LD->getValueType(0), 4795 Chain, Ptr, LD->getSrcValue(), 4796 LD->getSrcValueOffset(), LD->getMemoryVT(), 4797 LD->isVolatile(), Align); 4798 } 4799 } 4800 4801 // If load is not volatile and there are no uses of the loaded value (and 4802 // the updated indexed value in case of indexed loads), change uses of the 4803 // chain value into uses of the chain input (i.e. delete the dead load). 4804 if (!LD->isVolatile()) { 4805 if (N->getValueType(1) == MVT::Other) { 4806 // Unindexed loads. 4807 if (N->hasNUsesOfValue(0, 0)) { 4808 // It's not safe to use the two value CombineTo variant here. e.g. 4809 // v1, chain2 = load chain1, loc 4810 // v2, chain3 = load chain2, loc 4811 // v3 = add v2, c 4812 // Now we replace use of chain2 with chain1. This makes the second load 4813 // isomorphic to the one we are deleting, and thus makes this load live. 4814 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4815 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4816 DOUT << "\n"; 4817 WorkListRemover DeadNodes(*this); 4818 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4819 4820 if (N->use_empty()) { 4821 removeFromWorkList(N); 4822 DAG.DeleteNode(N); 4823 } 4824 4825 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4826 } 4827 } else { 4828 // Indexed loads. 4829 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4830 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4831 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4832 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4833 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4834 DOUT << " and 2 other values\n"; 4835 WorkListRemover DeadNodes(*this); 4836 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4837 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4838 DAG.getUNDEF(N->getValueType(1)), 4839 &DeadNodes); 4840 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4841 removeFromWorkList(N); 4842 DAG.DeleteNode(N); 4843 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4844 } 4845 } 4846 } 4847 4848 // If this load is directly stored, replace the load value with the stored 4849 // value. 4850 // TODO: Handle store large -> read small portion. 4851 // TODO: Handle TRUNCSTORE/LOADEXT 4852 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4853 !LD->isVolatile()) { 4854 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4855 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4856 if (PrevST->getBasePtr() == Ptr && 4857 PrevST->getValue().getValueType() == N->getValueType(0)) 4858 return CombineTo(N, Chain.getOperand(1), Chain); 4859 } 4860 } 4861 4862 if (CombinerAA) { 4863 // Walk up chain skipping non-aliasing memory nodes. 4864 SDValue BetterChain = FindBetterChain(N, Chain); 4865 4866 // If there is a better chain. 4867 if (Chain != BetterChain) { 4868 SDValue ReplLoad; 4869 4870 // Replace the chain to void dependency. 4871 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4872 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4873 BetterChain, Ptr, 4874 LD->getSrcValue(), LD->getSrcValueOffset(), 4875 LD->isVolatile(), LD->getAlignment()); 4876 } else { 4877 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4878 LD->getValueType(0), 4879 BetterChain, Ptr, LD->getSrcValue(), 4880 LD->getSrcValueOffset(), 4881 LD->getMemoryVT(), 4882 LD->isVolatile(), 4883 LD->getAlignment()); 4884 } 4885 4886 // Create token factor to keep old chain connected. 4887 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4888 MVT::Other, Chain, ReplLoad.getValue(1)); 4889 4890 // Replace uses with load result and token factor. Don't add users 4891 // to work list. 4892 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4893 } 4894 } 4895 4896 // Try transforming N to an indexed load. 4897 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4898 return SDValue(N, 0); 4899 4900 return SDValue(); 4901} 4902 4903 4904/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 4905/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 4906/// of the loaded bits, try narrowing the load and store if it would end up 4907/// being a win for performance or code size. 4908SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 4909 StoreSDNode *ST = cast<StoreSDNode>(N); 4910 if (ST->isVolatile()) 4911 return SDValue(); 4912 4913 SDValue Chain = ST->getChain(); 4914 SDValue Value = ST->getValue(); 4915 SDValue Ptr = ST->getBasePtr(); 4916 MVT VT = Value.getValueType(); 4917 4918 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 4919 return SDValue(); 4920 4921 unsigned Opc = Value.getOpcode(); 4922 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 4923 Value.getOperand(1).getOpcode() != ISD::Constant) 4924 return SDValue(); 4925 4926 SDValue N0 = Value.getOperand(0); 4927 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 4928 LoadSDNode *LD = cast<LoadSDNode>(N0); 4929 if (LD->getBasePtr() != Ptr) 4930 return SDValue(); 4931 4932 // Find the type to narrow it the load / op / store to. 4933 SDValue N1 = Value.getOperand(1); 4934 unsigned BitWidth = N1.getValueSizeInBits(); 4935 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 4936 if (Opc == ISD::AND) 4937 Imm ^= APInt::getAllOnesValue(BitWidth); 4938 if (Imm == 0 || Imm.isAllOnesValue()) 4939 return SDValue(); 4940 unsigned ShAmt = Imm.countTrailingZeros(); 4941 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 4942 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 4943 MVT NewVT = MVT::getIntegerVT(NewBW); 4944 while (NewBW < BitWidth && 4945 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 4946 TLI.isNarrowingProfitable(VT, NewVT))) { 4947 NewBW = NextPowerOf2(NewBW); 4948 NewVT = MVT::getIntegerVT(NewBW); 4949 } 4950 if (NewBW >= BitWidth) 4951 return SDValue(); 4952 4953 // If the lsb changed does not start at the type bitwidth boundary, 4954 // start at the previous one. 4955 if (ShAmt % NewBW) 4956 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 4957 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 4958 if ((Imm & Mask) == Imm) { 4959 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 4960 if (Opc == ISD::AND) 4961 NewImm ^= APInt::getAllOnesValue(NewBW); 4962 uint64_t PtrOff = ShAmt / 8; 4963 // For big endian targets, we need to adjust the offset to the pointer to 4964 // load the correct bytes. 4965 if (TLI.isBigEndian()) 4966 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 4967 4968 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 4969 if (NewAlign < 4970 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT())) 4971 return SDValue(); 4972 4973 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 4974 Ptr.getValueType(), Ptr, 4975 DAG.getConstant(PtrOff, Ptr.getValueType())); 4976 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 4977 LD->getChain(), NewPtr, 4978 LD->getSrcValue(), LD->getSrcValueOffset(), 4979 LD->isVolatile(), NewAlign); 4980 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 4981 DAG.getConstant(NewImm, NewVT)); 4982 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 4983 NewVal, NewPtr, 4984 ST->getSrcValue(), ST->getSrcValueOffset(), 4985 false, NewAlign); 4986 4987 AddToWorkList(NewPtr.getNode()); 4988 AddToWorkList(NewLD.getNode()); 4989 AddToWorkList(NewVal.getNode()); 4990 WorkListRemover DeadNodes(*this); 4991 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 4992 &DeadNodes); 4993 ++OpsNarrowed; 4994 return NewST; 4995 } 4996 } 4997 4998 return SDValue(); 4999} 5000 5001SDValue DAGCombiner::visitSTORE(SDNode *N) { 5002 StoreSDNode *ST = cast<StoreSDNode>(N); 5003 SDValue Chain = ST->getChain(); 5004 SDValue Value = ST->getValue(); 5005 SDValue Ptr = ST->getBasePtr(); 5006 5007 // Try to infer better alignment information than the store already has. 5008 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5009 if (unsigned Align = InferAlignment(Ptr, DAG)) { 5010 if (Align > ST->getAlignment()) 5011 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5012 Ptr, ST->getSrcValue(), 5013 ST->getSrcValueOffset(), ST->getMemoryVT(), 5014 ST->isVolatile(), Align); 5015 } 5016 } 5017 5018 // If this is a store of a bit convert, store the input value if the 5019 // resultant store does not need a higher alignment than the original. 5020 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5021 ST->isUnindexed()) { 5022 unsigned OrigAlign = ST->getAlignment(); 5023 MVT SVT = Value.getOperand(0).getValueType(); 5024 unsigned Align = TLI.getTargetData()-> 5025 getABITypeAlignment(SVT.getTypeForMVT()); 5026 if (Align <= OrigAlign && 5027 ((!LegalOperations && !ST->isVolatile()) || 5028 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5029 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5030 Ptr, ST->getSrcValue(), 5031 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5032 } 5033 5034 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5035 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5036 // NOTE: If the original store is volatile, this transform must not increase 5037 // the number of stores. For example, on x86-32 an f64 can be stored in one 5038 // processor operation but an i64 (which is not legal) requires two. So the 5039 // transform should not be done in this case. 5040 if (Value.getOpcode() != ISD::TargetConstantFP) { 5041 SDValue Tmp; 5042 switch (CFP->getValueType(0).getSimpleVT()) { 5043 default: assert(0 && "Unknown FP type"); 5044 case MVT::f80: // We don't do this for these yet. 5045 case MVT::f128: 5046 case MVT::ppcf128: 5047 break; 5048 case MVT::f32: 5049 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5050 !ST->isVolatile()) || 5051 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5052 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5053 bitcastToAPInt().getZExtValue(), MVT::i32); 5054 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5055 Ptr, ST->getSrcValue(), 5056 ST->getSrcValueOffset(), ST->isVolatile(), 5057 ST->getAlignment()); 5058 } 5059 break; 5060 case MVT::f64: 5061 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5062 !ST->isVolatile()) || 5063 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5064 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5065 getZExtValue(), MVT::i64); 5066 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5067 Ptr, ST->getSrcValue(), 5068 ST->getSrcValueOffset(), ST->isVolatile(), 5069 ST->getAlignment()); 5070 } else if (!ST->isVolatile() && 5071 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5072 // Many FP stores are not made apparent until after legalize, e.g. for 5073 // argument passing. Since this is so common, custom legalize the 5074 // 64-bit integer store into two 32-bit stores. 5075 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5076 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5077 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5078 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5079 5080 int SVOffset = ST->getSrcValueOffset(); 5081 unsigned Alignment = ST->getAlignment(); 5082 bool isVolatile = ST->isVolatile(); 5083 5084 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5085 Ptr, ST->getSrcValue(), 5086 ST->getSrcValueOffset(), 5087 isVolatile, ST->getAlignment()); 5088 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5089 DAG.getConstant(4, Ptr.getValueType())); 5090 SVOffset += 4; 5091 Alignment = MinAlign(Alignment, 4U); 5092 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5093 Ptr, ST->getSrcValue(), 5094 SVOffset, isVolatile, Alignment); 5095 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5096 St0, St1); 5097 } 5098 5099 break; 5100 } 5101 } 5102 } 5103 5104 if (CombinerAA) { 5105 // Walk up chain skipping non-aliasing memory nodes. 5106 SDValue BetterChain = FindBetterChain(N, Chain); 5107 5108 // If there is a better chain. 5109 if (Chain != BetterChain) { 5110 // Replace the chain to avoid dependency. 5111 SDValue ReplStore; 5112 if (ST->isTruncatingStore()) { 5113 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5114 ST->getSrcValue(),ST->getSrcValueOffset(), 5115 ST->getMemoryVT(), 5116 ST->isVolatile(), ST->getAlignment()); 5117 } else { 5118 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5119 ST->getSrcValue(), ST->getSrcValueOffset(), 5120 ST->isVolatile(), ST->getAlignment()); 5121 } 5122 5123 // Create token to keep both nodes around. 5124 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5125 MVT::Other, Chain, ReplStore); 5126 5127 // Don't add users to work list. 5128 return CombineTo(N, Token, false); 5129 } 5130 } 5131 5132 // Try transforming N to an indexed store. 5133 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5134 return SDValue(N, 0); 5135 5136 // FIXME: is there such a thing as a truncating indexed store? 5137 if (ST->isTruncatingStore() && ST->isUnindexed() && 5138 Value.getValueType().isInteger()) { 5139 // See if we can simplify the input to this truncstore with knowledge that 5140 // only the low bits are being used. For example: 5141 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5142 SDValue Shorter = 5143 GetDemandedBits(Value, 5144 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5145 ST->getMemoryVT().getSizeInBits())); 5146 AddToWorkList(Value.getNode()); 5147 if (Shorter.getNode()) 5148 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5149 Ptr, ST->getSrcValue(), 5150 ST->getSrcValueOffset(), ST->getMemoryVT(), 5151 ST->isVolatile(), ST->getAlignment()); 5152 5153 // Otherwise, see if we can simplify the operation with 5154 // SimplifyDemandedBits, which only works if the value has a single use. 5155 if (SimplifyDemandedBits(Value, 5156 APInt::getLowBitsSet( 5157 Value.getValueSizeInBits(), 5158 ST->getMemoryVT().getSizeInBits()))) 5159 return SDValue(N, 0); 5160 } 5161 5162 // If this is a load followed by a store to the same location, then the store 5163 // is dead/noop. 5164 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5165 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5166 ST->isUnindexed() && !ST->isVolatile() && 5167 // There can't be any side effects between the load and store, such as 5168 // a call or store. 5169 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5170 // The store is dead, remove it. 5171 return Chain; 5172 } 5173 } 5174 5175 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5176 // truncating store. We can do this even if this is already a truncstore. 5177 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5178 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5179 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5180 ST->getMemoryVT())) { 5181 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5182 Ptr, ST->getSrcValue(), 5183 ST->getSrcValueOffset(), ST->getMemoryVT(), 5184 ST->isVolatile(), ST->getAlignment()); 5185 } 5186 5187 return ReduceLoadOpStoreWidth(N); 5188} 5189 5190SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5191 SDValue InVec = N->getOperand(0); 5192 SDValue InVal = N->getOperand(1); 5193 SDValue EltNo = N->getOperand(2); 5194 5195 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5196 // vector with the inserted element. 5197 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5198 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5199 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5200 InVec.getNode()->op_end()); 5201 if (Elt < Ops.size()) 5202 Ops[Elt] = InVal; 5203 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5204 InVec.getValueType(), &Ops[0], Ops.size()); 5205 } 5206 // If the invec is an UNDEF and if EltNo is a constant, create a new 5207 // BUILD_VECTOR with undef elements and the inserted element. 5208 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5209 isa<ConstantSDNode>(EltNo)) { 5210 MVT VT = InVec.getValueType(); 5211 MVT EVT = VT.getVectorElementType(); 5212 unsigned NElts = VT.getVectorNumElements(); 5213 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT)); 5214 5215 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5216 if (Elt < Ops.size()) 5217 Ops[Elt] = InVal; 5218 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5219 InVec.getValueType(), &Ops[0], Ops.size()); 5220 } 5221 return SDValue(); 5222} 5223 5224SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5225 // (vextract (scalar_to_vector val, 0) -> val 5226 SDValue InVec = N->getOperand(0); 5227 5228 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5229 // If the operand is wider than the vector element type then it is implicitly 5230 // truncated. Make that explicit here. 5231 MVT EltVT = InVec.getValueType().getVectorElementType(); 5232 SDValue InOp = InVec.getOperand(0); 5233 if (InOp.getValueType() != EltVT) 5234 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5235 return InOp; 5236 } 5237 5238 // Perform only after legalization to ensure build_vector / vector_shuffle 5239 // optimizations have already been done. 5240 if (!LegalOperations) return SDValue(); 5241 5242 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5243 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5244 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5245 SDValue EltNo = N->getOperand(1); 5246 5247 if (isa<ConstantSDNode>(EltNo)) { 5248 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5249 bool NewLoad = false; 5250 bool BCNumEltsChanged = false; 5251 MVT VT = InVec.getValueType(); 5252 MVT EVT = VT.getVectorElementType(); 5253 MVT LVT = EVT; 5254 5255 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5256 MVT BCVT = InVec.getOperand(0).getValueType(); 5257 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5258 return SDValue(); 5259 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5260 BCNumEltsChanged = true; 5261 InVec = InVec.getOperand(0); 5262 EVT = BCVT.getVectorElementType(); 5263 NewLoad = true; 5264 } 5265 5266 LoadSDNode *LN0 = NULL; 5267 const ShuffleVectorSDNode *SVN = NULL; 5268 if (ISD::isNormalLoad(InVec.getNode())) { 5269 LN0 = cast<LoadSDNode>(InVec); 5270 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5271 InVec.getOperand(0).getValueType() == EVT && 5272 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5273 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5274 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5275 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5276 // => 5277 // (load $addr+1*size) 5278 5279 // If the bit convert changed the number of elements, it is unsafe 5280 // to examine the mask. 5281 if (BCNumEltsChanged) 5282 return SDValue(); 5283 5284 // Select the input vector, guarding against out of range extract vector. 5285 unsigned NumElems = VT.getVectorNumElements(); 5286 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5287 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5288 5289 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5290 InVec = InVec.getOperand(0); 5291 if (ISD::isNormalLoad(InVec.getNode())) { 5292 LN0 = cast<LoadSDNode>(InVec); 5293 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5294 } 5295 } 5296 5297 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5298 return SDValue(); 5299 5300 unsigned Align = LN0->getAlignment(); 5301 if (NewLoad) { 5302 // Check the resultant load doesn't need a higher alignment than the 5303 // original load. 5304 unsigned NewAlign = 5305 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); 5306 5307 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5308 return SDValue(); 5309 5310 Align = NewAlign; 5311 } 5312 5313 SDValue NewPtr = LN0->getBasePtr(); 5314 if (Elt) { 5315 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5316 MVT PtrType = NewPtr.getValueType(); 5317 if (TLI.isBigEndian()) 5318 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5319 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5320 DAG.getConstant(PtrOff, PtrType)); 5321 } 5322 5323 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5324 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5325 LN0->isVolatile(), Align); 5326 } 5327 5328 return SDValue(); 5329} 5330 5331SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5332 unsigned NumInScalars = N->getNumOperands(); 5333 MVT VT = N->getValueType(0); 5334 MVT EltType = VT.getVectorElementType(); 5335 5336 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5337 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5338 // at most two distinct vectors, turn this into a shuffle node. 5339 SDValue VecIn1, VecIn2; 5340 for (unsigned i = 0; i != NumInScalars; ++i) { 5341 // Ignore undef inputs. 5342 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5343 5344 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5345 // constant index, bail out. 5346 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5347 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5348 VecIn1 = VecIn2 = SDValue(0, 0); 5349 break; 5350 } 5351 5352 // If the input vector type disagrees with the result of the build_vector, 5353 // we can't make a shuffle. 5354 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5355 if (ExtractedFromVec.getValueType() != VT) { 5356 VecIn1 = VecIn2 = SDValue(0, 0); 5357 break; 5358 } 5359 5360 // Otherwise, remember this. We allow up to two distinct input vectors. 5361 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5362 continue; 5363 5364 if (VecIn1.getNode() == 0) { 5365 VecIn1 = ExtractedFromVec; 5366 } else if (VecIn2.getNode() == 0) { 5367 VecIn2 = ExtractedFromVec; 5368 } else { 5369 // Too many inputs. 5370 VecIn1 = VecIn2 = SDValue(0, 0); 5371 break; 5372 } 5373 } 5374 5375 // If everything is good, we can make a shuffle operation. 5376 if (VecIn1.getNode()) { 5377 SmallVector<int, 8> Mask; 5378 for (unsigned i = 0; i != NumInScalars; ++i) { 5379 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5380 Mask.push_back(-1); 5381 continue; 5382 } 5383 5384 // If extracting from the first vector, just use the index directly. 5385 SDValue Extract = N->getOperand(i); 5386 SDValue ExtVal = Extract.getOperand(1); 5387 if (Extract.getOperand(0) == VecIn1) { 5388 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5389 if (ExtIndex > VT.getVectorNumElements()) 5390 return SDValue(); 5391 5392 Mask.push_back(ExtIndex); 5393 continue; 5394 } 5395 5396 // Otherwise, use InIdx + VecSize 5397 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5398 Mask.push_back(Idx+NumInScalars); 5399 } 5400 5401 // Add count and size info. 5402 if (!TLI.isTypeLegal(VT) && LegalTypes) 5403 return SDValue(); 5404 5405 // Return the new VECTOR_SHUFFLE node. 5406 SDValue Ops[2]; 5407 Ops[0] = VecIn1; 5408 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5409 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5410 } 5411 5412 return SDValue(); 5413} 5414 5415SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5416 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5417 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5418 // inputs come from at most two distinct vectors, turn this into a shuffle 5419 // node. 5420 5421 // If we only have one input vector, we don't need to do any concatenation. 5422 if (N->getNumOperands() == 1) 5423 return N->getOperand(0); 5424 5425 return SDValue(); 5426} 5427 5428SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5429 return SDValue(); 5430 5431 MVT VT = N->getValueType(0); 5432 unsigned NumElts = VT.getVectorNumElements(); 5433 5434 SDValue N0 = N->getOperand(0); 5435 SDValue N1 = N->getOperand(1); 5436 5437 assert(N0.getValueType().getVectorNumElements() == NumElts && 5438 "Vector shuffle must be normalized in DAG"); 5439 5440 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5441 5442 // If it is a splat, check if the argument vector is a build_vector with 5443 // all scalar elements the same. 5444 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5445 SDNode *V = N0.getNode(); 5446 5447 5448 // If this is a bit convert that changes the element type of the vector but 5449 // not the number of vector elements, look through it. Be careful not to 5450 // look though conversions that change things like v4f32 to v2f64. 5451 if (V->getOpcode() == ISD::BIT_CONVERT) { 5452 SDValue ConvInput = V->getOperand(0); 5453 if (ConvInput.getValueType().isVector() && 5454 ConvInput.getValueType().getVectorNumElements() == NumElts) 5455 V = ConvInput.getNode(); 5456 } 5457 5458 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5459 unsigned NumElems = V->getNumOperands(); 5460 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5461 if (NumElems > BaseIdx) { 5462 SDValue Base; 5463 bool AllSame = true; 5464 for (unsigned i = 0; i != NumElems; ++i) { 5465 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5466 Base = V->getOperand(i); 5467 break; 5468 } 5469 } 5470 // Splat of <u, u, u, u>, return <u, u, u, u> 5471 if (!Base.getNode()) 5472 return N0; 5473 for (unsigned i = 0; i != NumElems; ++i) { 5474 if (V->getOperand(i) != Base) { 5475 AllSame = false; 5476 break; 5477 } 5478 } 5479 // Splat of <x, x, x, x>, return <x, x, x, x> 5480 if (AllSame) 5481 return N0; 5482 } 5483 } 5484 } 5485 return SDValue(); 5486} 5487 5488/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5489/// an AND to a vector_shuffle with the destination vector and a zero vector. 5490/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5491/// vector_shuffle V, Zero, <0, 4, 2, 4> 5492SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5493 MVT VT = N->getValueType(0); 5494 DebugLoc dl = N->getDebugLoc(); 5495 SDValue LHS = N->getOperand(0); 5496 SDValue RHS = N->getOperand(1); 5497 if (N->getOpcode() == ISD::AND) { 5498 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5499 RHS = RHS.getOperand(0); 5500 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5501 SmallVector<int, 8> Indices; 5502 unsigned NumElts = RHS.getNumOperands(); 5503 for (unsigned i = 0; i != NumElts; ++i) { 5504 SDValue Elt = RHS.getOperand(i); 5505 if (!isa<ConstantSDNode>(Elt)) 5506 return SDValue(); 5507 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5508 Indices.push_back(i); 5509 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5510 Indices.push_back(NumElts); 5511 else 5512 return SDValue(); 5513 } 5514 5515 // Let's see if the target supports this vector_shuffle. 5516 MVT RVT = RHS.getValueType(); 5517 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5518 return SDValue(); 5519 5520 // Return the new VECTOR_SHUFFLE node. 5521 MVT EVT = RVT.getVectorElementType(); 5522 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5523 DAG.getConstant(0, EVT)); 5524 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5525 RVT, &ZeroOps[0], ZeroOps.size()); 5526 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5527 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5528 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5529 } 5530 } 5531 5532 return SDValue(); 5533} 5534 5535/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5536SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5537 // After legalize, the target may be depending on adds and other 5538 // binary ops to provide legal ways to construct constants or other 5539 // things. Simplifying them may result in a loss of legality. 5540 if (LegalOperations) return SDValue(); 5541 5542 MVT VT = N->getValueType(0); 5543 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5544 5545 MVT EltType = VT.getVectorElementType(); 5546 SDValue LHS = N->getOperand(0); 5547 SDValue RHS = N->getOperand(1); 5548 SDValue Shuffle = XformToShuffleWithZero(N); 5549 if (Shuffle.getNode()) return Shuffle; 5550 5551 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5552 // this operation. 5553 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5554 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5555 SmallVector<SDValue, 8> Ops; 5556 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5557 SDValue LHSOp = LHS.getOperand(i); 5558 SDValue RHSOp = RHS.getOperand(i); 5559 // If these two elements can't be folded, bail out. 5560 if ((LHSOp.getOpcode() != ISD::UNDEF && 5561 LHSOp.getOpcode() != ISD::Constant && 5562 LHSOp.getOpcode() != ISD::ConstantFP) || 5563 (RHSOp.getOpcode() != ISD::UNDEF && 5564 RHSOp.getOpcode() != ISD::Constant && 5565 RHSOp.getOpcode() != ISD::ConstantFP)) 5566 break; 5567 5568 // Can't fold divide by zero. 5569 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5570 N->getOpcode() == ISD::FDIV) { 5571 if ((RHSOp.getOpcode() == ISD::Constant && 5572 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5573 (RHSOp.getOpcode() == ISD::ConstantFP && 5574 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5575 break; 5576 } 5577 5578 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5579 EltType, LHSOp, RHSOp)); 5580 AddToWorkList(Ops.back().getNode()); 5581 assert((Ops.back().getOpcode() == ISD::UNDEF || 5582 Ops.back().getOpcode() == ISD::Constant || 5583 Ops.back().getOpcode() == ISD::ConstantFP) && 5584 "Scalar binop didn't fold!"); 5585 } 5586 5587 if (Ops.size() == LHS.getNumOperands()) { 5588 MVT VT = LHS.getValueType(); 5589 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5590 &Ops[0], Ops.size()); 5591 } 5592 } 5593 5594 return SDValue(); 5595} 5596 5597SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5598 SDValue N1, SDValue N2){ 5599 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5600 5601 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5602 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5603 5604 // If we got a simplified select_cc node back from SimplifySelectCC, then 5605 // break it down into a new SETCC node, and a new SELECT node, and then return 5606 // the SELECT node, since we were called with a SELECT node. 5607 if (SCC.getNode()) { 5608 // Check to see if we got a select_cc back (to turn into setcc/select). 5609 // Otherwise, just return whatever node we got back, like fabs. 5610 if (SCC.getOpcode() == ISD::SELECT_CC) { 5611 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5612 N0.getValueType(), 5613 SCC.getOperand(0), SCC.getOperand(1), 5614 SCC.getOperand(4)); 5615 AddToWorkList(SETCC.getNode()); 5616 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5617 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5618 } 5619 5620 return SCC; 5621 } 5622 return SDValue(); 5623} 5624 5625/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5626/// are the two values being selected between, see if we can simplify the 5627/// select. Callers of this should assume that TheSelect is deleted if this 5628/// returns true. As such, they should return the appropriate thing (e.g. the 5629/// node) back to the top-level of the DAG combiner loop to avoid it being 5630/// looked at. 5631bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5632 SDValue RHS) { 5633 5634 // If this is a select from two identical things, try to pull the operation 5635 // through the select. 5636 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5637 // If this is a load and the token chain is identical, replace the select 5638 // of two loads with a load through a select of the address to load from. 5639 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5640 // constants have been dropped into the constant pool. 5641 if (LHS.getOpcode() == ISD::LOAD && 5642 // Do not let this transformation reduce the number of volatile loads. 5643 !cast<LoadSDNode>(LHS)->isVolatile() && 5644 !cast<LoadSDNode>(RHS)->isVolatile() && 5645 // Token chains must be identical. 5646 LHS.getOperand(0) == RHS.getOperand(0)) { 5647 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5648 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5649 5650 // If this is an EXTLOAD, the VT's must match. 5651 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5652 // FIXME: this conflates two src values, discarding one. This is not 5653 // the right thing to do, but nothing uses srcvalues now. When they do, 5654 // turn SrcValue into a list of locations. 5655 SDValue Addr; 5656 if (TheSelect->getOpcode() == ISD::SELECT) { 5657 // Check that the condition doesn't reach either load. If so, folding 5658 // this will induce a cycle into the DAG. 5659 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5660 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5661 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5662 LLD->getBasePtr().getValueType(), 5663 TheSelect->getOperand(0), LLD->getBasePtr(), 5664 RLD->getBasePtr()); 5665 } 5666 } else { 5667 // Check that the condition doesn't reach either load. If so, folding 5668 // this will induce a cycle into the DAG. 5669 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5670 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5671 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5672 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5673 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5674 LLD->getBasePtr().getValueType(), 5675 TheSelect->getOperand(0), 5676 TheSelect->getOperand(1), 5677 LLD->getBasePtr(), RLD->getBasePtr(), 5678 TheSelect->getOperand(4)); 5679 } 5680 } 5681 5682 if (Addr.getNode()) { 5683 SDValue Load; 5684 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5685 Load = DAG.getLoad(TheSelect->getValueType(0), 5686 TheSelect->getDebugLoc(), 5687 LLD->getChain(), 5688 Addr,LLD->getSrcValue(), 5689 LLD->getSrcValueOffset(), 5690 LLD->isVolatile(), 5691 LLD->getAlignment()); 5692 } else { 5693 Load = DAG.getExtLoad(LLD->getExtensionType(), 5694 TheSelect->getDebugLoc(), 5695 TheSelect->getValueType(0), 5696 LLD->getChain(), Addr, LLD->getSrcValue(), 5697 LLD->getSrcValueOffset(), 5698 LLD->getMemoryVT(), 5699 LLD->isVolatile(), 5700 LLD->getAlignment()); 5701 } 5702 5703 // Users of the select now use the result of the load. 5704 CombineTo(TheSelect, Load); 5705 5706 // Users of the old loads now use the new load's chain. We know the 5707 // old-load value is dead now. 5708 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5709 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5710 return true; 5711 } 5712 } 5713 } 5714 } 5715 5716 return false; 5717} 5718 5719/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5720/// where 'cond' is the comparison specified by CC. 5721SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5722 SDValue N2, SDValue N3, 5723 ISD::CondCode CC, bool NotExtCompare) { 5724 // (x ? y : y) -> y. 5725 if (N2 == N3) return N2; 5726 5727 MVT VT = N2.getValueType(); 5728 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5729 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5730 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5731 5732 // Determine if the condition we're dealing with is constant 5733 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5734 N0, N1, CC, DL, false); 5735 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5736 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5737 5738 // fold select_cc true, x, y -> x 5739 if (SCCC && !SCCC->isNullValue()) 5740 return N2; 5741 // fold select_cc false, x, y -> y 5742 if (SCCC && SCCC->isNullValue()) 5743 return N3; 5744 5745 // Check to see if we can simplify the select into an fabs node 5746 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5747 // Allow either -0.0 or 0.0 5748 if (CFP->getValueAPF().isZero()) { 5749 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5750 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5751 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5752 N2 == N3.getOperand(0)) 5753 return DAG.getNode(ISD::FABS, DL, VT, N0); 5754 5755 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5756 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5757 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5758 N2.getOperand(0) == N3) 5759 return DAG.getNode(ISD::FABS, DL, VT, N3); 5760 } 5761 } 5762 5763 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5764 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5765 // in it. This is a win when the constant is not otherwise available because 5766 // it replaces two constant pool loads with one. We only do this if the FP 5767 // type is known to be legal, because if it isn't, then we are before legalize 5768 // types an we want the other legalization to happen first (e.g. to avoid 5769 // messing with soft float) and if the ConstantFP is not legal, because if 5770 // it is legal, we may not need to store the FP constant in a constant pool. 5771 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5772 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5773 if (TLI.isTypeLegal(N2.getValueType()) && 5774 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5775 TargetLowering::Legal) && 5776 // If both constants have multiple uses, then we won't need to do an 5777 // extra load, they are likely around in registers for other users. 5778 (TV->hasOneUse() || FV->hasOneUse())) { 5779 Constant *Elts[] = { 5780 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5781 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5782 }; 5783 const Type *FPTy = Elts[0]->getType(); 5784 const TargetData &TD = *TLI.getTargetData(); 5785 5786 // Create a ConstantArray of the two constants. 5787 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5788 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5789 TD.getPrefTypeAlignment(FPTy)); 5790 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5791 5792 // Get the offsets to the 0 and 1 element of the array so that we can 5793 // select between them. 5794 SDValue Zero = DAG.getIntPtrConstant(0); 5795 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5796 SDValue One = DAG.getIntPtrConstant(EltSize); 5797 5798 SDValue Cond = DAG.getSetCC(DL, 5799 TLI.getSetCCResultType(N0.getValueType()), 5800 N0, N1, CC); 5801 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5802 Cond, One, Zero); 5803 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5804 CstOffset); 5805 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5806 PseudoSourceValue::getConstantPool(), 0, false, 5807 Alignment); 5808 5809 } 5810 } 5811 5812 // Check to see if we can perform the "gzip trick", transforming 5813 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5814 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5815 N0.getValueType().isInteger() && 5816 N2.getValueType().isInteger() && 5817 (N1C->isNullValue() || // (a < 0) ? b : 0 5818 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5819 MVT XType = N0.getValueType(); 5820 MVT AType = N2.getValueType(); 5821 if (XType.bitsGE(AType)) { 5822 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5823 // single-bit constant. 5824 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5825 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5826 ShCtV = XType.getSizeInBits()-ShCtV-1; 5827 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5828 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5829 XType, N0, ShCt); 5830 AddToWorkList(Shift.getNode()); 5831 5832 if (XType.bitsGT(AType)) { 5833 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5834 AddToWorkList(Shift.getNode()); 5835 } 5836 5837 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5838 } 5839 5840 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5841 XType, N0, 5842 DAG.getConstant(XType.getSizeInBits()-1, 5843 getShiftAmountTy())); 5844 AddToWorkList(Shift.getNode()); 5845 5846 if (XType.bitsGT(AType)) { 5847 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5848 AddToWorkList(Shift.getNode()); 5849 } 5850 5851 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5852 } 5853 } 5854 5855 // fold select C, 16, 0 -> shl C, 4 5856 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5857 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5858 5859 // If the caller doesn't want us to simplify this into a zext of a compare, 5860 // don't do it. 5861 if (NotExtCompare && N2C->getAPIntValue() == 1) 5862 return SDValue(); 5863 5864 // Get a SetCC of the condition 5865 // FIXME: Should probably make sure that setcc is legal if we ever have a 5866 // target where it isn't. 5867 SDValue Temp, SCC; 5868 // cast from setcc result type to select result type 5869 if (LegalTypes) { 5870 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5871 N0, N1, CC); 5872 if (N2.getValueType().bitsLT(SCC.getValueType())) 5873 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5874 else 5875 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5876 N2.getValueType(), SCC); 5877 } else { 5878 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5879 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5880 N2.getValueType(), SCC); 5881 } 5882 5883 AddToWorkList(SCC.getNode()); 5884 AddToWorkList(Temp.getNode()); 5885 5886 if (N2C->getAPIntValue() == 1) 5887 return Temp; 5888 5889 // shl setcc result by log2 n2c 5890 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5891 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5892 getShiftAmountTy())); 5893 } 5894 5895 // Check to see if this is the equivalent of setcc 5896 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5897 // otherwise, go ahead with the folds. 5898 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5899 MVT XType = N0.getValueType(); 5900 if (!LegalOperations || 5901 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5902 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5903 if (Res.getValueType() != VT) 5904 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5905 return Res; 5906 } 5907 5908 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5909 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5910 (!LegalOperations || 5911 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5912 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5913 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5914 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5915 getShiftAmountTy())); 5916 } 5917 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5918 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5919 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5920 XType, DAG.getConstant(0, XType), N0); 5921 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5922 return DAG.getNode(ISD::SRL, DL, XType, 5923 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5924 DAG.getConstant(XType.getSizeInBits()-1, 5925 getShiftAmountTy())); 5926 } 5927 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5928 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5929 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5930 DAG.getConstant(XType.getSizeInBits()-1, 5931 getShiftAmountTy())); 5932 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5933 } 5934 } 5935 5936 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5937 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5938 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5939 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5940 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5941 MVT XType = N0.getValueType(); 5942 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5943 DAG.getConstant(XType.getSizeInBits()-1, 5944 getShiftAmountTy())); 5945 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5946 N0, Shift); 5947 AddToWorkList(Shift.getNode()); 5948 AddToWorkList(Add.getNode()); 5949 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5950 } 5951 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5952 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5953 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5954 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5955 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5956 MVT XType = N0.getValueType(); 5957 if (SubC->isNullValue() && XType.isInteger()) { 5958 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5959 N0, 5960 DAG.getConstant(XType.getSizeInBits()-1, 5961 getShiftAmountTy())); 5962 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 5963 XType, N0, Shift); 5964 AddToWorkList(Shift.getNode()); 5965 AddToWorkList(Add.getNode()); 5966 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5967 } 5968 } 5969 } 5970 5971 return SDValue(); 5972} 5973 5974/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5975SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5976 SDValue N1, ISD::CondCode Cond, 5977 DebugLoc DL, bool foldBooleans) { 5978 TargetLowering::DAGCombinerInfo 5979 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5980 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 5981} 5982 5983/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5984/// return a DAG expression to select that will generate the same value by 5985/// multiplying by a magic number. See: 5986/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5987SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5988 std::vector<SDNode*> Built; 5989 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5990 5991 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5992 ii != ee; ++ii) 5993 AddToWorkList(*ii); 5994 return S; 5995} 5996 5997/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5998/// return a DAG expression to select that will generate the same value by 5999/// multiplying by a magic number. See: 6000/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6001SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6002 std::vector<SDNode*> Built; 6003 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6004 6005 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6006 ii != ee; ++ii) 6007 AddToWorkList(*ii); 6008 return S; 6009} 6010 6011/// FindBaseOffset - Return true if base is known not to alias with anything 6012/// but itself. Provides base object and offset as results. 6013static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 6014 // Assume it is a primitive operation. 6015 Base = Ptr; Offset = 0; 6016 6017 // If it's an adding a simple constant then integrate the offset. 6018 if (Base.getOpcode() == ISD::ADD) { 6019 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6020 Base = Base.getOperand(0); 6021 Offset += C->getZExtValue(); 6022 } 6023 } 6024 6025 // If it's any of the following then it can't alias with anything but itself. 6026 return isa<FrameIndexSDNode>(Base) || 6027 isa<ConstantPoolSDNode>(Base) || 6028 isa<GlobalAddressSDNode>(Base); 6029} 6030 6031/// isAlias - Return true if there is any possibility that the two addresses 6032/// overlap. 6033bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6034 const Value *SrcValue1, int SrcValueOffset1, 6035 SDValue Ptr2, int64_t Size2, 6036 const Value *SrcValue2, int SrcValueOffset2) const { 6037 // If they are the same then they must be aliases. 6038 if (Ptr1 == Ptr2) return true; 6039 6040 // Gather base node and offset information. 6041 SDValue Base1, Base2; 6042 int64_t Offset1, Offset2; 6043 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 6044 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 6045 6046 // If they have a same base address then... 6047 if (Base1 == Base2) 6048 // Check to see if the addresses overlap. 6049 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6050 6051 // If we know both bases then they can't alias. 6052 if (KnownBase1 && KnownBase2) return false; 6053 6054 if (CombinerGlobalAA) { 6055 // Use alias analysis information. 6056 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6057 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6058 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6059 AliasAnalysis::AliasResult AAResult = 6060 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6061 if (AAResult == AliasAnalysis::NoAlias) 6062 return false; 6063 } 6064 6065 // Otherwise we have to assume they alias. 6066 return true; 6067} 6068 6069/// FindAliasInfo - Extracts the relevant alias information from the memory 6070/// node. Returns true if the operand was a load. 6071bool DAGCombiner::FindAliasInfo(SDNode *N, 6072 SDValue &Ptr, int64_t &Size, 6073 const Value *&SrcValue, int &SrcValueOffset) const { 6074 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6075 Ptr = LD->getBasePtr(); 6076 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6077 SrcValue = LD->getSrcValue(); 6078 SrcValueOffset = LD->getSrcValueOffset(); 6079 return true; 6080 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6081 Ptr = ST->getBasePtr(); 6082 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6083 SrcValue = ST->getSrcValue(); 6084 SrcValueOffset = ST->getSrcValueOffset(); 6085 } else { 6086 assert(0 && "FindAliasInfo expected a memory operand"); 6087 } 6088 6089 return false; 6090} 6091 6092/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6093/// looking for aliasing nodes and adding them to the Aliases vector. 6094void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6095 SmallVector<SDValue, 8> &Aliases) { 6096 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6097 std::set<SDNode *> Visited; // Visited node set. 6098 6099 // Get alias information for node. 6100 SDValue Ptr; 6101 int64_t Size = 0; 6102 const Value *SrcValue = 0; 6103 int SrcValueOffset = 0; 6104 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6105 6106 // Starting off. 6107 Chains.push_back(OriginalChain); 6108 6109 // Look at each chain and determine if it is an alias. If so, add it to the 6110 // aliases list. If not, then continue up the chain looking for the next 6111 // candidate. 6112 while (!Chains.empty()) { 6113 SDValue Chain = Chains.back(); 6114 Chains.pop_back(); 6115 6116 // Don't bother if we've been before. 6117 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6118 Visited.insert(Chain.getNode()); 6119 6120 switch (Chain.getOpcode()) { 6121 case ISD::EntryToken: 6122 // Entry token is ideal chain operand, but handled in FindBetterChain. 6123 break; 6124 6125 case ISD::LOAD: 6126 case ISD::STORE: { 6127 // Get alias information for Chain. 6128 SDValue OpPtr; 6129 int64_t OpSize = 0; 6130 const Value *OpSrcValue = 0; 6131 int OpSrcValueOffset = 0; 6132 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6133 OpSrcValue, OpSrcValueOffset); 6134 6135 // If chain is alias then stop here. 6136 if (!(IsLoad && IsOpLoad) && 6137 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6138 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6139 Aliases.push_back(Chain); 6140 } else { 6141 // Look further up the chain. 6142 Chains.push_back(Chain.getOperand(0)); 6143 // Clean up old chain. 6144 AddToWorkList(Chain.getNode()); 6145 } 6146 break; 6147 } 6148 6149 case ISD::TokenFactor: 6150 // We have to check each of the operands of the token factor, so we queue 6151 // then up. Adding the operands to the queue (stack) in reverse order 6152 // maintains the original order and increases the likelihood that getNode 6153 // will find a matching token factor (CSE.) 6154 for (unsigned n = Chain.getNumOperands(); n;) 6155 Chains.push_back(Chain.getOperand(--n)); 6156 // Eliminate the token factor if we can. 6157 AddToWorkList(Chain.getNode()); 6158 break; 6159 6160 default: 6161 // For all other instructions we will just have to take what we can get. 6162 Aliases.push_back(Chain); 6163 break; 6164 } 6165 } 6166} 6167 6168/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6169/// for a better chain (aliasing node.) 6170SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6171 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6172 6173 // Accumulate all the aliases to this node. 6174 GatherAllAliases(N, OldChain, Aliases); 6175 6176 if (Aliases.size() == 0) { 6177 // If no operands then chain to entry token. 6178 return DAG.getEntryNode(); 6179 } else if (Aliases.size() == 1) { 6180 // If a single operand then chain to it. We don't need to revisit it. 6181 return Aliases[0]; 6182 } 6183 6184 // Construct a custom tailored token factor. 6185 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6186 &Aliases[0], Aliases.size()); 6187 6188 // Make sure the old chain gets cleaned up. 6189 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6190 6191 return NewChain; 6192} 6193 6194// SelectionDAG::Combine - This is the entry point for the file. 6195// 6196void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6197 CodeGenOpt::Level OptLevel) { 6198 /// run - This is the main entry point to this class. 6199 /// 6200 DAGCombiner(*this, AA, OptLevel).Run(Level); 6201} 6202