DAGCombiner.cpp revision 41d88d2ac07d1ccbb3c0d1430d57102aada89390
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 const TargetLowering &TLI; 53 CombineLevel Level; 54 bool LegalOperations; 55 bool LegalTypes; 56 bool Fast; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 // AA - Used for DAG load/store alias analysis. 62 AliasAnalysis &AA; 63 64 /// AddUsersToWorkList - When an instruction is simplified, add all users of 65 /// the instruction to the work lists because they might get more simplified 66 /// now. 67 /// 68 void AddUsersToWorkList(SDNode *N) { 69 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 70 UI != UE; ++UI) 71 AddToWorkList(*UI); 72 } 73 74 /// visit - call the node-specific routine that knows how to fold each 75 /// particular type of node. 76 SDValue visit(SDNode *N); 77 78 public: 79 /// AddToWorkList - Add to the work list making sure it's instance is at the 80 /// the back (next to be processed.) 81 void AddToWorkList(SDNode *N) { 82 removeFromWorkList(N); 83 WorkList.push_back(N); 84 } 85 86 /// removeFromWorkList - remove all instances of N from the worklist. 87 /// 88 void removeFromWorkList(SDNode *N) { 89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 90 WorkList.end()); 91 } 92 93 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 94 bool AddTo = true); 95 96 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 97 return CombineTo(N, &Res, 1, AddTo); 98 } 99 100 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 101 bool AddTo = true) { 102 SDValue To[] = { Res0, Res1 }; 103 return CombineTo(N, To, 2, AddTo); 104 } 105 106 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 107 108 private: 109 110 /// SimplifyDemandedBits - Check the specified integer node value to see if 111 /// it can be simplified or if things it uses can be simplified by bit 112 /// propagation. If so, return true. 113 bool SimplifyDemandedBits(SDValue Op) { 114 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 115 return SimplifyDemandedBits(Op, Demanded); 116 } 117 118 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 119 120 bool CombineToPreIndexedLoadStore(SDNode *N); 121 bool CombineToPostIndexedLoadStore(SDNode *N); 122 123 124 /// combine - call the node-specific routine that knows how to fold each 125 /// particular type of node. If that doesn't do anything, try the 126 /// target-specific DAG combines. 127 SDValue combine(SDNode *N); 128 129 // Visitation implementation - Implement dag node combining for different 130 // node types. The semantics are as follows: 131 // Return Value: 132 // SDValue.getNode() == 0 - No change was made 133 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 134 // otherwise - N should be replaced by the returned Operand. 135 // 136 SDValue visitTokenFactor(SDNode *N); 137 SDValue visitMERGE_VALUES(SDNode *N); 138 SDValue visitADD(SDNode *N); 139 SDValue visitSUB(SDNode *N); 140 SDValue visitADDC(SDNode *N); 141 SDValue visitADDE(SDNode *N); 142 SDValue visitMUL(SDNode *N); 143 SDValue visitSDIV(SDNode *N); 144 SDValue visitUDIV(SDNode *N); 145 SDValue visitSREM(SDNode *N); 146 SDValue visitUREM(SDNode *N); 147 SDValue visitMULHU(SDNode *N); 148 SDValue visitMULHS(SDNode *N); 149 SDValue visitSMUL_LOHI(SDNode *N); 150 SDValue visitUMUL_LOHI(SDNode *N); 151 SDValue visitSDIVREM(SDNode *N); 152 SDValue visitUDIVREM(SDNode *N); 153 SDValue visitAND(SDNode *N); 154 SDValue visitOR(SDNode *N); 155 SDValue visitXOR(SDNode *N); 156 SDValue SimplifyVBinOp(SDNode *N); 157 SDValue visitSHL(SDNode *N); 158 SDValue visitSRA(SDNode *N); 159 SDValue visitSRL(SDNode *N); 160 SDValue visitCTLZ(SDNode *N); 161 SDValue visitCTTZ(SDNode *N); 162 SDValue visitCTPOP(SDNode *N); 163 SDValue visitSELECT(SDNode *N); 164 SDValue visitSELECT_CC(SDNode *N); 165 SDValue visitSETCC(SDNode *N); 166 SDValue visitSIGN_EXTEND(SDNode *N); 167 SDValue visitZERO_EXTEND(SDNode *N); 168 SDValue visitANY_EXTEND(SDNode *N); 169 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 170 SDValue visitTRUNCATE(SDNode *N); 171 SDValue visitBIT_CONVERT(SDNode *N); 172 SDValue visitBUILD_PAIR(SDNode *N); 173 SDValue visitFADD(SDNode *N); 174 SDValue visitFSUB(SDNode *N); 175 SDValue visitFMUL(SDNode *N); 176 SDValue visitFDIV(SDNode *N); 177 SDValue visitFREM(SDNode *N); 178 SDValue visitFCOPYSIGN(SDNode *N); 179 SDValue visitSINT_TO_FP(SDNode *N); 180 SDValue visitUINT_TO_FP(SDNode *N); 181 SDValue visitFP_TO_SINT(SDNode *N); 182 SDValue visitFP_TO_UINT(SDNode *N); 183 SDValue visitFP_ROUND(SDNode *N); 184 SDValue visitFP_ROUND_INREG(SDNode *N); 185 SDValue visitFP_EXTEND(SDNode *N); 186 SDValue visitFNEG(SDNode *N); 187 SDValue visitFABS(SDNode *N); 188 SDValue visitBRCOND(SDNode *N); 189 SDValue visitBR_CC(SDNode *N); 190 SDValue visitLOAD(SDNode *N); 191 SDValue visitSTORE(SDNode *N); 192 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 193 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 194 SDValue visitBUILD_VECTOR(SDNode *N); 195 SDValue visitCONCAT_VECTORS(SDNode *N); 196 SDValue visitVECTOR_SHUFFLE(SDNode *N); 197 198 SDValue XformToShuffleWithZero(SDNode *N); 199 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 200 201 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 202 203 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 204 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 205 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 206 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 207 SDValue N3, ISD::CondCode CC, 208 bool NotExtCompare = false); 209 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 210 DebugLoc DL, bool foldBooleans = true); 211 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 212 unsigned HiOp); 213 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 214 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 215 SDValue BuildSDIV(SDNode *N); 216 SDValue BuildUDIV(SDNode *N); 217 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 218 SDValue ReduceLoadWidth(SDNode *N); 219 220 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 221 222 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 223 /// looking for aliasing nodes and adding them to the Aliases vector. 224 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 225 SmallVector<SDValue, 8> &Aliases); 226 227 /// isAlias - Return true if there is any possibility that the two addresses 228 /// overlap. 229 bool isAlias(SDValue Ptr1, int64_t Size1, 230 const Value *SrcValue1, int SrcValueOffset1, 231 SDValue Ptr2, int64_t Size2, 232 const Value *SrcValue2, int SrcValueOffset2) const; 233 234 /// FindAliasInfo - Extracts the relevant alias information from the memory 235 /// node. Returns true if the operand was a load. 236 bool FindAliasInfo(SDNode *N, 237 SDValue &Ptr, int64_t &Size, 238 const Value *&SrcValue, int &SrcValueOffset) const; 239 240 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 241 /// looking for a better chain (aliasing node.) 242 SDValue FindBetterChain(SDNode *N, SDValue Chain); 243 244 /// getShiftAmountTy - Returns a type large enough to hold any valid 245 /// shift amount - before type legalization these can be huge. 246 MVT getShiftAmountTy() { 247 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 248 } 249 250public: 251 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 252 : DAG(D), 253 TLI(D.getTargetLoweringInfo()), 254 Level(Unrestricted), 255 LegalOperations(false), 256 LegalTypes(false), 257 Fast(fast), 258 AA(A) {} 259 260 /// Run - runs the dag combiner on all nodes in the work list 261 void Run(CombineLevel AtLevel); 262 }; 263} 264 265 266namespace { 267/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 268/// nodes from the worklist. 269class VISIBILITY_HIDDEN WorkListRemover : 270 public SelectionDAG::DAGUpdateListener { 271 DAGCombiner &DC; 272public: 273 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 274 275 virtual void NodeDeleted(SDNode *N, SDNode *E) { 276 DC.removeFromWorkList(N); 277 } 278 279 virtual void NodeUpdated(SDNode *N) { 280 // Ignore updates. 281 } 282}; 283} 284 285//===----------------------------------------------------------------------===// 286// TargetLowering::DAGCombinerInfo implementation 287//===----------------------------------------------------------------------===// 288 289void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 290 ((DAGCombiner*)DC)->AddToWorkList(N); 291} 292 293SDValue TargetLowering::DAGCombinerInfo:: 294CombineTo(SDNode *N, const std::vector<SDValue> &To) { 295 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 296} 297 298SDValue TargetLowering::DAGCombinerInfo:: 299CombineTo(SDNode *N, SDValue Res) { 300 return ((DAGCombiner*)DC)->CombineTo(N, Res); 301} 302 303 304SDValue TargetLowering::DAGCombinerInfo:: 305CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 306 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 307} 308 309void TargetLowering::DAGCombinerInfo:: 310CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 311 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 312} 313 314//===----------------------------------------------------------------------===// 315// Helper Functions 316//===----------------------------------------------------------------------===// 317 318/// isNegatibleForFree - Return 1 if we can compute the negated form of the 319/// specified expression for the same cost as the expression itself, or 2 if we 320/// can compute the negated form more cheaply than the expression itself. 321static char isNegatibleForFree(SDValue Op, bool LegalOperations, 322 unsigned Depth = 0) { 323 // No compile time optimizations on this type. 324 if (Op.getValueType() == MVT::ppcf128) 325 return 0; 326 327 // fneg is removable even if it has multiple uses. 328 if (Op.getOpcode() == ISD::FNEG) return 2; 329 330 // Don't allow anything with multiple uses. 331 if (!Op.hasOneUse()) return 0; 332 333 // Don't recurse exponentially. 334 if (Depth > 6) return 0; 335 336 switch (Op.getOpcode()) { 337 default: return false; 338 case ISD::ConstantFP: 339 // Don't invert constant FP values after legalize. The negated constant 340 // isn't necessarily legal. 341 return LegalOperations ? 0 : 1; 342 case ISD::FADD: 343 // FIXME: determine better conditions for this xform. 344 if (!UnsafeFPMath) return 0; 345 346 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 347 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 348 return V; 349 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 350 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 351 case ISD::FSUB: 352 // We can't turn -(A-B) into B-A when we honor signed zeros. 353 if (!UnsafeFPMath) return 0; 354 355 // fold (fneg (fsub A, B)) -> (fsub B, A) 356 return 1; 357 358 case ISD::FMUL: 359 case ISD::FDIV: 360 if (HonorSignDependentRoundingFPMath()) return 0; 361 362 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 363 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 364 return V; 365 366 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 367 368 case ISD::FP_EXTEND: 369 case ISD::FP_ROUND: 370 case ISD::FSIN: 371 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 372 } 373} 374 375/// GetNegatedExpression - If isNegatibleForFree returns true, this function 376/// returns the newly negated expression. 377static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 378 bool LegalOperations, unsigned Depth = 0) { 379 // fneg is removable even if it has multiple uses. 380 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 381 382 // Don't allow anything with multiple uses. 383 assert(Op.hasOneUse() && "Unknown reuse!"); 384 385 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 386 switch (Op.getOpcode()) { 387 default: assert(0 && "Unknown code"); 388 case ISD::ConstantFP: { 389 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 390 V.changeSign(); 391 return DAG.getConstantFP(V, Op.getValueType()); 392 } 393 case ISD::FADD: 394 // FIXME: determine better conditions for this xform. 395 assert(UnsafeFPMath); 396 397 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 398 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 399 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 400 GetNegatedExpression(Op.getOperand(0), DAG, 401 LegalOperations, Depth+1), 402 Op.getOperand(1)); 403 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 404 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 405 GetNegatedExpression(Op.getOperand(1), DAG, 406 LegalOperations, Depth+1), 407 Op.getOperand(0)); 408 case ISD::FSUB: 409 // We can't turn -(A-B) into B-A when we honor signed zeros. 410 assert(UnsafeFPMath); 411 412 // fold (fneg (fsub 0, B)) -> B 413 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 414 if (N0CFP->getValueAPF().isZero()) 415 return Op.getOperand(1); 416 417 // fold (fneg (fsub A, B)) -> (fsub B, A) 418 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 419 Op.getOperand(1), Op.getOperand(0)); 420 421 case ISD::FMUL: 422 case ISD::FDIV: 423 assert(!HonorSignDependentRoundingFPMath()); 424 425 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 426 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 427 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 428 GetNegatedExpression(Op.getOperand(0), DAG, 429 LegalOperations, Depth+1), 430 Op.getOperand(1)); 431 432 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 433 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 434 Op.getOperand(0), 435 GetNegatedExpression(Op.getOperand(1), DAG, 436 LegalOperations, Depth+1)); 437 438 case ISD::FP_EXTEND: 439 case ISD::FSIN: 440 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 441 GetNegatedExpression(Op.getOperand(0), DAG, 442 LegalOperations, Depth+1)); 443 case ISD::FP_ROUND: 444 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 445 GetNegatedExpression(Op.getOperand(0), DAG, 446 LegalOperations, Depth+1), 447 Op.getOperand(1)); 448 } 449} 450 451 452// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 453// that selects between the values 1 and 0, making it equivalent to a setcc. 454// Also, set the incoming LHS, RHS, and CC references to the appropriate 455// nodes based on the type of node we are checking. This simplifies life a 456// bit for the callers. 457static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 458 SDValue &CC) { 459 if (N.getOpcode() == ISD::SETCC) { 460 LHS = N.getOperand(0); 461 RHS = N.getOperand(1); 462 CC = N.getOperand(2); 463 return true; 464 } 465 if (N.getOpcode() == ISD::SELECT_CC && 466 N.getOperand(2).getOpcode() == ISD::Constant && 467 N.getOperand(3).getOpcode() == ISD::Constant && 468 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 469 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 470 LHS = N.getOperand(0); 471 RHS = N.getOperand(1); 472 CC = N.getOperand(4); 473 return true; 474 } 475 return false; 476} 477 478// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 479// one use. If this is true, it allows the users to invert the operation for 480// free when it is profitable to do so. 481static bool isOneUseSetCC(SDValue N) { 482 SDValue N0, N1, N2; 483 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 484 return true; 485 return false; 486} 487 488SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 489 SDValue N0, SDValue N1) { 490 MVT VT = N0.getValueType(); 491 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 492 if (isa<ConstantSDNode>(N1)) { 493 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 494 SDValue OpNode = 495 DAG.FoldConstantArithmetic(Opc, VT, 496 cast<ConstantSDNode>(N0.getOperand(1)), 497 cast<ConstantSDNode>(N1)); 498 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 499 } else if (N0.hasOneUse()) { 500 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 501 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 502 N0.getOperand(0), N1); 503 AddToWorkList(OpNode.getNode()); 504 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 505 } 506 } 507 508 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 509 if (isa<ConstantSDNode>(N0)) { 510 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 511 SDValue OpNode = 512 DAG.FoldConstantArithmetic(Opc, VT, 513 cast<ConstantSDNode>(N1.getOperand(1)), 514 cast<ConstantSDNode>(N0)); 515 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 516 } else if (N1.hasOneUse()) { 517 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 518 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 519 N1.getOperand(0), N0); 520 AddToWorkList(OpNode.getNode()); 521 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 522 } 523 } 524 525 return SDValue(); 526} 527 528SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 529 bool AddTo) { 530 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 531 ++NodesCombined; 532 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 533 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 534 DOUT << " and " << NumTo-1 << " other values\n"; 535 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 536 assert(N->getValueType(i) == To[i].getValueType() && 537 "Cannot combine value to value of different type!")); 538 WorkListRemover DeadNodes(*this); 539 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 540 541 if (AddTo) { 542 // Push the new nodes and any users onto the worklist 543 for (unsigned i = 0, e = NumTo; i != e; ++i) { 544 AddToWorkList(To[i].getNode()); 545 AddUsersToWorkList(To[i].getNode()); 546 } 547 } 548 549 // Finally, if the node is now dead, remove it from the graph. The node 550 // may not be dead if the replacement process recursively simplified to 551 // something else needing this node. 552 if (N->use_empty()) { 553 // Nodes can be reintroduced into the worklist. Make sure we do not 554 // process a node that has been replaced. 555 removeFromWorkList(N); 556 557 // Finally, since the node is now dead, remove it from the graph. 558 DAG.DeleteNode(N); 559 } 560 return SDValue(N, 0); 561} 562 563void 564DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 565 TLO) { 566 // Replace all uses. If any nodes become isomorphic to other nodes and 567 // are deleted, make sure to remove them from our worklist. 568 WorkListRemover DeadNodes(*this); 569 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 570 571 // Push the new node and any (possibly new) users onto the worklist. 572 AddToWorkList(TLO.New.getNode()); 573 AddUsersToWorkList(TLO.New.getNode()); 574 575 // Finally, if the node is now dead, remove it from the graph. The node 576 // may not be dead if the replacement process recursively simplified to 577 // something else needing this node. 578 if (TLO.Old.getNode()->use_empty()) { 579 removeFromWorkList(TLO.Old.getNode()); 580 581 // If the operands of this node are only used by the node, they will now 582 // be dead. Make sure to visit them first to delete dead nodes early. 583 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 584 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 585 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 586 587 DAG.DeleteNode(TLO.Old.getNode()); 588 } 589} 590 591/// SimplifyDemandedBits - Check the specified integer node value to see if 592/// it can be simplified or if things it uses can be simplified by bit 593/// propagation. If so, return true. 594bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 595 TargetLowering::TargetLoweringOpt TLO(DAG); 596 APInt KnownZero, KnownOne; 597 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 598 return false; 599 600 // Revisit the node. 601 AddToWorkList(Op.getNode()); 602 603 // Replace the old value with the new one. 604 ++NodesCombined; 605 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 606 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 607 DOUT << '\n'; 608 609 CommitTargetLoweringOpt(TLO); 610 return true; 611} 612 613//===----------------------------------------------------------------------===// 614// Main DAG Combiner implementation 615//===----------------------------------------------------------------------===// 616 617void DAGCombiner::Run(CombineLevel AtLevel) { 618 // set the instance variables, so that the various visit routines may use it. 619 Level = AtLevel; 620 LegalOperations = Level >= NoIllegalOperations; 621 LegalTypes = Level >= NoIllegalTypes; 622 623 // Add all the dag nodes to the worklist. 624 WorkList.reserve(DAG.allnodes_size()); 625 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 626 E = DAG.allnodes_end(); I != E; ++I) 627 WorkList.push_back(I); 628 629 // Create a dummy node (which is not added to allnodes), that adds a reference 630 // to the root node, preventing it from being deleted, and tracking any 631 // changes of the root. 632 HandleSDNode Dummy(DAG.getRoot()); 633 634 // The root of the dag may dangle to deleted nodes until the dag combiner is 635 // done. Set it to null to avoid confusion. 636 DAG.setRoot(SDValue()); 637 638 // while the worklist isn't empty, inspect the node on the end of it and 639 // try and combine it. 640 while (!WorkList.empty()) { 641 SDNode *N = WorkList.back(); 642 WorkList.pop_back(); 643 644 // If N has no uses, it is dead. Make sure to revisit all N's operands once 645 // N is deleted from the DAG, since they too may now be dead or may have a 646 // reduced number of uses, allowing other xforms. 647 if (N->use_empty() && N != &Dummy) { 648 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 649 AddToWorkList(N->getOperand(i).getNode()); 650 651 DAG.DeleteNode(N); 652 continue; 653 } 654 655 SDValue RV = combine(N); 656 657 if (RV.getNode() == 0) 658 continue; 659 660 ++NodesCombined; 661 662 // If we get back the same node we passed in, rather than a new node or 663 // zero, we know that the node must have defined multiple values and 664 // CombineTo was used. Since CombineTo takes care of the worklist 665 // mechanics for us, we have no work to do in this case. 666 if (RV.getNode() == N) 667 continue; 668 669 assert(N->getOpcode() != ISD::DELETED_NODE && 670 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 671 "Node was deleted but visit returned new node!"); 672 673 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 674 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 675 DOUT << '\n'; 676 WorkListRemover DeadNodes(*this); 677 if (N->getNumValues() == RV.getNode()->getNumValues()) 678 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 679 else { 680 assert(N->getValueType(0) == RV.getValueType() && 681 N->getNumValues() == 1 && "Type mismatch"); 682 SDValue OpV = RV; 683 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 684 } 685 686 // Push the new node and any users onto the worklist 687 AddToWorkList(RV.getNode()); 688 AddUsersToWorkList(RV.getNode()); 689 690 // Add any uses of the old node to the worklist in case this node is the 691 // last one that uses them. They may become dead after this node is 692 // deleted. 693 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 694 AddToWorkList(N->getOperand(i).getNode()); 695 696 // Finally, if the node is now dead, remove it from the graph. The node 697 // may not be dead if the replacement process recursively simplified to 698 // something else needing this node. 699 if (N->use_empty()) { 700 // Nodes can be reintroduced into the worklist. Make sure we do not 701 // process a node that has been replaced. 702 removeFromWorkList(N); 703 704 // Finally, since the node is now dead, remove it from the graph. 705 DAG.DeleteNode(N); 706 } 707 } 708 709 // If the root changed (e.g. it was a dead load, update the root). 710 DAG.setRoot(Dummy.getValue()); 711} 712 713SDValue DAGCombiner::visit(SDNode *N) { 714 switch(N->getOpcode()) { 715 default: break; 716 case ISD::TokenFactor: return visitTokenFactor(N); 717 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 718 case ISD::ADD: return visitADD(N); 719 case ISD::SUB: return visitSUB(N); 720 case ISD::ADDC: return visitADDC(N); 721 case ISD::ADDE: return visitADDE(N); 722 case ISD::MUL: return visitMUL(N); 723 case ISD::SDIV: return visitSDIV(N); 724 case ISD::UDIV: return visitUDIV(N); 725 case ISD::SREM: return visitSREM(N); 726 case ISD::UREM: return visitUREM(N); 727 case ISD::MULHU: return visitMULHU(N); 728 case ISD::MULHS: return visitMULHS(N); 729 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 730 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 731 case ISD::SDIVREM: return visitSDIVREM(N); 732 case ISD::UDIVREM: return visitUDIVREM(N); 733 case ISD::AND: return visitAND(N); 734 case ISD::OR: return visitOR(N); 735 case ISD::XOR: return visitXOR(N); 736 case ISD::SHL: return visitSHL(N); 737 case ISD::SRA: return visitSRA(N); 738 case ISD::SRL: return visitSRL(N); 739 case ISD::CTLZ: return visitCTLZ(N); 740 case ISD::CTTZ: return visitCTTZ(N); 741 case ISD::CTPOP: return visitCTPOP(N); 742 case ISD::SELECT: return visitSELECT(N); 743 case ISD::SELECT_CC: return visitSELECT_CC(N); 744 case ISD::SETCC: return visitSETCC(N); 745 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 746 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 747 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 748 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 749 case ISD::TRUNCATE: return visitTRUNCATE(N); 750 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 751 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 752 case ISD::FADD: return visitFADD(N); 753 case ISD::FSUB: return visitFSUB(N); 754 case ISD::FMUL: return visitFMUL(N); 755 case ISD::FDIV: return visitFDIV(N); 756 case ISD::FREM: return visitFREM(N); 757 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 758 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 759 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 760 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 761 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 762 case ISD::FP_ROUND: return visitFP_ROUND(N); 763 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 764 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 765 case ISD::FNEG: return visitFNEG(N); 766 case ISD::FABS: return visitFABS(N); 767 case ISD::BRCOND: return visitBRCOND(N); 768 case ISD::BR_CC: return visitBR_CC(N); 769 case ISD::LOAD: return visitLOAD(N); 770 case ISD::STORE: return visitSTORE(N); 771 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 772 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 773 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 774 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 775 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 776 } 777 return SDValue(); 778} 779 780SDValue DAGCombiner::combine(SDNode *N) { 781 SDValue RV = visit(N); 782 783 // If nothing happened, try a target-specific DAG combine. 784 if (RV.getNode() == 0) { 785 assert(N->getOpcode() != ISD::DELETED_NODE && 786 "Node was deleted but visit returned NULL!"); 787 788 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 789 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 790 791 // Expose the DAG combiner to the target combiner impls. 792 TargetLowering::DAGCombinerInfo 793 DagCombineInfo(DAG, Level == Unrestricted, false, this); 794 795 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 796 } 797 } 798 799 // If N is a commutative binary node, try commuting it to enable more 800 // sdisel CSE. 801 if (RV.getNode() == 0 && 802 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 803 N->getNumValues() == 1) { 804 SDValue N0 = N->getOperand(0); 805 SDValue N1 = N->getOperand(1); 806 807 // Constant operands are canonicalized to RHS. 808 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 809 SDValue Ops[] = { N1, N0 }; 810 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 811 Ops, 2); 812 if (CSENode) 813 return SDValue(CSENode, 0); 814 } 815 } 816 817 return RV; 818} 819 820/// getInputChainForNode - Given a node, return its input chain if it has one, 821/// otherwise return a null sd operand. 822static SDValue getInputChainForNode(SDNode *N) { 823 if (unsigned NumOps = N->getNumOperands()) { 824 if (N->getOperand(0).getValueType() == MVT::Other) 825 return N->getOperand(0); 826 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 827 return N->getOperand(NumOps-1); 828 for (unsigned i = 1; i < NumOps-1; ++i) 829 if (N->getOperand(i).getValueType() == MVT::Other) 830 return N->getOperand(i); 831 } 832 return SDValue(); 833} 834 835SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 836 // If N has two operands, where one has an input chain equal to the other, 837 // the 'other' chain is redundant. 838 if (N->getNumOperands() == 2) { 839 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 840 return N->getOperand(0); 841 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 842 return N->getOperand(1); 843 } 844 845 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 846 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 847 SmallPtrSet<SDNode*, 16> SeenOps; 848 bool Changed = false; // If we should replace this token factor. 849 850 // Start out with this token factor. 851 TFs.push_back(N); 852 853 // Iterate through token factors. The TFs grows when new token factors are 854 // encountered. 855 for (unsigned i = 0; i < TFs.size(); ++i) { 856 SDNode *TF = TFs[i]; 857 858 // Check each of the operands. 859 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 860 SDValue Op = TF->getOperand(i); 861 862 switch (Op.getOpcode()) { 863 case ISD::EntryToken: 864 // Entry tokens don't need to be added to the list. They are 865 // rededundant. 866 Changed = true; 867 break; 868 869 case ISD::TokenFactor: 870 if ((CombinerAA || Op.hasOneUse()) && 871 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 872 // Queue up for processing. 873 TFs.push_back(Op.getNode()); 874 // Clean up in case the token factor is removed. 875 AddToWorkList(Op.getNode()); 876 Changed = true; 877 break; 878 } 879 // Fall thru 880 881 default: 882 // Only add if it isn't already in the list. 883 if (SeenOps.insert(Op.getNode())) 884 Ops.push_back(Op); 885 else 886 Changed = true; 887 break; 888 } 889 } 890 } 891 892 SDValue Result; 893 894 // If we've change things around then replace token factor. 895 if (Changed) { 896 if (Ops.empty()) { 897 // The entry token is the only possible outcome. 898 Result = DAG.getEntryNode(); 899 } else { 900 // New and improved token factor. 901 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 902 MVT::Other, &Ops[0], Ops.size()); 903 } 904 905 // Don't add users to work list. 906 return CombineTo(N, Result, false); 907 } 908 909 return Result; 910} 911 912/// MERGE_VALUES can always be eliminated. 913SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 914 WorkListRemover DeadNodes(*this); 915 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 916 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 917 &DeadNodes); 918 removeFromWorkList(N); 919 DAG.DeleteNode(N); 920 return SDValue(N, 0); // Return N so it doesn't get rechecked! 921} 922 923static 924SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 925 SelectionDAG &DAG) { 926 MVT VT = N0.getValueType(); 927 SDValue N00 = N0.getOperand(0); 928 SDValue N01 = N0.getOperand(1); 929 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 930 931 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 932 isa<ConstantSDNode>(N00.getOperand(1))) { 933 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 934 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 935 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 936 N00.getOperand(0), N01), 937 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 938 N00.getOperand(1), N01)); 939 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 940 } 941 942 return SDValue(); 943} 944 945static 946SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 947 SelectionDAG &DAG, const TargetLowering &TLI, 948 bool LegalOperations) { 949 MVT VT = N->getValueType(0); 950 unsigned Opc = N->getOpcode(); 951 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 952 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 953 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 954 ISD::CondCode CC = ISD::SETCC_INVALID; 955 956 if (isSlctCC) { 957 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 958 } else { 959 SDValue CCOp = Slct.getOperand(0); 960 if (CCOp.getOpcode() == ISD::SETCC) 961 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 962 } 963 964 bool DoXform = false; 965 bool InvCC = false; 966 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 967 "Bad input!"); 968 969 if (LHS.getOpcode() == ISD::Constant && 970 cast<ConstantSDNode>(LHS)->isNullValue()) { 971 DoXform = true; 972 } else if (CC != ISD::SETCC_INVALID && 973 RHS.getOpcode() == ISD::Constant && 974 cast<ConstantSDNode>(RHS)->isNullValue()) { 975 std::swap(LHS, RHS); 976 SDValue Op0 = Slct.getOperand(0); 977 MVT OpVT = isSlctCC ? Op0.getValueType() : 978 Op0.getOperand(0).getValueType(); 979 bool isInt = OpVT.isInteger(); 980 CC = ISD::getSetCCInverse(CC, isInt); 981 982 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT)) 983 return SDValue(); // Inverse operator isn't legal. 984 985 DoXform = true; 986 InvCC = true; 987 } 988 989 if (DoXform) { 990 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 991 if (isSlctCC) 992 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 993 Slct.getOperand(0), Slct.getOperand(1), CC); 994 SDValue CCOp = Slct.getOperand(0); 995 if (InvCC) 996 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 997 CCOp.getOperand(0), CCOp.getOperand(1), CC); 998 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 999 CCOp, OtherOp, Result); 1000 } 1001 return SDValue(); 1002} 1003 1004SDValue DAGCombiner::visitADD(SDNode *N) { 1005 SDValue N0 = N->getOperand(0); 1006 SDValue N1 = N->getOperand(1); 1007 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1008 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1009 MVT VT = N0.getValueType(); 1010 1011 // fold vector ops 1012 if (VT.isVector()) { 1013 SDValue FoldedVOp = SimplifyVBinOp(N); 1014 if (FoldedVOp.getNode()) return FoldedVOp; 1015 } 1016 1017 // fold (add x, undef) -> undef 1018 if (N0.getOpcode() == ISD::UNDEF) 1019 return N0; 1020 if (N1.getOpcode() == ISD::UNDEF) 1021 return N1; 1022 // fold (add c1, c2) -> c1+c2 1023 if (N0C && N1C) 1024 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1025 // canonicalize constant to RHS 1026 if (N0C && !N1C) 1027 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1028 // fold (add x, 0) -> x 1029 if (N1C && N1C->isNullValue()) 1030 return N0; 1031 // fold (add Sym, c) -> Sym+c 1032 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1033 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1034 GA->getOpcode() == ISD::GlobalAddress) 1035 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1036 GA->getOffset() + 1037 (uint64_t)N1C->getSExtValue()); 1038 // fold ((c1-A)+c2) -> (c1+c2)-A 1039 if (N1C && N0.getOpcode() == ISD::SUB) 1040 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1041 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1042 DAG.getConstant(N1C->getAPIntValue()+ 1043 N0C->getAPIntValue(), VT), 1044 N0.getOperand(1)); 1045 // reassociate add 1046 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1047 if (RADD.getNode() != 0) 1048 return RADD; 1049 // fold ((0-A) + B) -> B-A 1050 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1051 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1052 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1053 // fold (A + (0-B)) -> A-B 1054 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1055 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1056 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1057 // fold (A+(B-A)) -> B 1058 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1059 return N1.getOperand(0); 1060 // fold ((B-A)+A) -> B 1061 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1062 return N0.getOperand(0); 1063 // fold (A+(B-(A+C))) to (B-C) 1064 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1065 N0 == N1.getOperand(1).getOperand(0)) 1066 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1067 N1.getOperand(1).getOperand(1)); 1068 // fold (A+(B-(C+A))) to (B-C) 1069 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1070 N0 == N1.getOperand(1).getOperand(1)) 1071 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1072 N1.getOperand(1).getOperand(0)); 1073 // fold (A+((B-A)+or-C)) to (B+or-C) 1074 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1075 N1.getOperand(0).getOpcode() == ISD::SUB && 1076 N0 == N1.getOperand(0).getOperand(1)) 1077 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1078 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1079 1080 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1081 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1082 SDValue N00 = N0.getOperand(0); 1083 SDValue N01 = N0.getOperand(1); 1084 SDValue N10 = N1.getOperand(0); 1085 SDValue N11 = N1.getOperand(1); 1086 1087 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1088 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1089 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1090 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1091 } 1092 1093 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1094 return SDValue(N, 0); 1095 1096 // fold (a+b) -> (a|b) iff a and b share no bits. 1097 if (VT.isInteger() && !VT.isVector()) { 1098 APInt LHSZero, LHSOne; 1099 APInt RHSZero, RHSOne; 1100 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1101 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1102 1103 if (LHSZero.getBoolValue()) { 1104 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1105 1106 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1107 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1108 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1109 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1110 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1111 } 1112 } 1113 1114 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1115 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1116 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1117 if (Result.getNode()) return Result; 1118 } 1119 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1120 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1121 if (Result.getNode()) return Result; 1122 } 1123 1124 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1125 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1126 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations); 1127 if (Result.getNode()) return Result; 1128 } 1129 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1130 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1131 if (Result.getNode()) return Result; 1132 } 1133 1134 return SDValue(); 1135} 1136 1137SDValue DAGCombiner::visitADDC(SDNode *N) { 1138 SDValue N0 = N->getOperand(0); 1139 SDValue N1 = N->getOperand(1); 1140 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1141 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1142 MVT VT = N0.getValueType(); 1143 1144 // If the flag result is dead, turn this into an ADD. 1145 if (N->hasNUsesOfValue(0, 1)) 1146 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1147 DAG.getNode(ISD::CARRY_FALSE, 1148 N->getDebugLoc(), MVT::Flag)); 1149 1150 // canonicalize constant to RHS. 1151 if (N0C && !N1C) 1152 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1153 1154 // fold (addc x, 0) -> x + no carry out 1155 if (N1C && N1C->isNullValue()) 1156 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1157 N->getDebugLoc(), MVT::Flag)); 1158 1159 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1160 APInt LHSZero, LHSOne; 1161 APInt RHSZero, RHSOne; 1162 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1163 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1164 1165 if (LHSZero.getBoolValue()) { 1166 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1167 1168 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1169 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1170 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1171 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1172 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1173 DAG.getNode(ISD::CARRY_FALSE, 1174 N->getDebugLoc(), MVT::Flag)); 1175 } 1176 1177 return SDValue(); 1178} 1179 1180SDValue DAGCombiner::visitADDE(SDNode *N) { 1181 SDValue N0 = N->getOperand(0); 1182 SDValue N1 = N->getOperand(1); 1183 SDValue CarryIn = N->getOperand(2); 1184 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1185 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1186 1187 // canonicalize constant to RHS 1188 if (N0C && !N1C) 1189 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1190 N1, N0, CarryIn); 1191 1192 // fold (adde x, y, false) -> (addc x, y) 1193 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1194 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1195 1196 return SDValue(); 1197} 1198 1199SDValue DAGCombiner::visitSUB(SDNode *N) { 1200 SDValue N0 = N->getOperand(0); 1201 SDValue N1 = N->getOperand(1); 1202 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1203 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1204 MVT VT = N0.getValueType(); 1205 1206 // fold vector ops 1207 if (VT.isVector()) { 1208 SDValue FoldedVOp = SimplifyVBinOp(N); 1209 if (FoldedVOp.getNode()) return FoldedVOp; 1210 } 1211 1212 // fold (sub x, x) -> 0 1213 if (N0 == N1) 1214 return DAG.getConstant(0, N->getValueType(0)); 1215 // fold (sub c1, c2) -> c1-c2 1216 if (N0C && N1C) 1217 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1218 // fold (sub x, c) -> (add x, -c) 1219 if (N1C) 1220 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1221 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1222 // fold (A+B)-A -> B 1223 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1224 return N0.getOperand(1); 1225 // fold (A+B)-B -> A 1226 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1227 return N0.getOperand(0); 1228 // fold ((A+(B+or-C))-B) -> A+or-C 1229 if (N0.getOpcode() == ISD::ADD && 1230 (N0.getOperand(1).getOpcode() == ISD::SUB || 1231 N0.getOperand(1).getOpcode() == ISD::ADD) && 1232 N0.getOperand(1).getOperand(0) == N1) 1233 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1234 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1235 // fold ((A+(C+B))-B) -> A+C 1236 if (N0.getOpcode() == ISD::ADD && 1237 N0.getOperand(1).getOpcode() == ISD::ADD && 1238 N0.getOperand(1).getOperand(1) == N1) 1239 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1240 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1241 // fold ((A-(B-C))-C) -> A-B 1242 if (N0.getOpcode() == ISD::SUB && 1243 N0.getOperand(1).getOpcode() == ISD::SUB && 1244 N0.getOperand(1).getOperand(1) == N1) 1245 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1246 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1247 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1248 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1249 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1250 if (Result.getNode()) return Result; 1251 } 1252 1253 // If either operand of a sub is undef, the result is undef 1254 if (N0.getOpcode() == ISD::UNDEF) 1255 return N0; 1256 if (N1.getOpcode() == ISD::UNDEF) 1257 return N1; 1258 1259 // If the relocation model supports it, consider symbol offsets. 1260 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1261 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1262 // fold (sub Sym, c) -> Sym-c 1263 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1264 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1265 GA->getOffset() - 1266 (uint64_t)N1C->getSExtValue()); 1267 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1268 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1269 if (GA->getGlobal() == GB->getGlobal()) 1270 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1271 VT); 1272 } 1273 1274 return SDValue(); 1275} 1276 1277SDValue DAGCombiner::visitMUL(SDNode *N) { 1278 SDValue N0 = N->getOperand(0); 1279 SDValue N1 = N->getOperand(1); 1280 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1281 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1282 MVT VT = N0.getValueType(); 1283 1284 // fold vector ops 1285 if (VT.isVector()) { 1286 SDValue FoldedVOp = SimplifyVBinOp(N); 1287 if (FoldedVOp.getNode()) return FoldedVOp; 1288 } 1289 1290 // fold (mul x, undef) -> 0 1291 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1292 return DAG.getConstant(0, VT); 1293 // fold (mul c1, c2) -> c1*c2 1294 if (N0C && N1C) 1295 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1296 // canonicalize constant to RHS 1297 if (N0C && !N1C) 1298 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1299 // fold (mul x, 0) -> 0 1300 if (N1C && N1C->isNullValue()) 1301 return N1; 1302 // fold (mul x, -1) -> 0-x 1303 if (N1C && N1C->isAllOnesValue()) 1304 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1305 DAG.getConstant(0, VT), N0); 1306 // fold (mul x, (1 << c)) -> x << c 1307 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1308 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1309 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1310 getShiftAmountTy())); 1311 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1312 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1313 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1314 // FIXME: If the input is something that is easily negated (e.g. a 1315 // single-use add), we should put the negate there. 1316 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1317 DAG.getConstant(0, VT), 1318 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1319 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1320 } 1321 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1322 if (N1C && N0.getOpcode() == ISD::SHL && 1323 isa<ConstantSDNode>(N0.getOperand(1))) { 1324 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1325 N1, N0.getOperand(1)); 1326 AddToWorkList(C3.getNode()); 1327 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1328 N0.getOperand(0), C3); 1329 } 1330 1331 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1332 // use. 1333 { 1334 SDValue Sh(0,0), Y(0,0); 1335 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1336 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1337 N0.getNode()->hasOneUse()) { 1338 Sh = N0; Y = N1; 1339 } else if (N1.getOpcode() == ISD::SHL && 1340 isa<ConstantSDNode>(N1.getOperand(1)) && 1341 N1.getNode()->hasOneUse()) { 1342 Sh = N1; Y = N0; 1343 } 1344 1345 if (Sh.getNode()) { 1346 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1347 Sh.getOperand(0), Y); 1348 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1349 Mul, Sh.getOperand(1)); 1350 } 1351 } 1352 1353 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1354 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1355 isa<ConstantSDNode>(N0.getOperand(1))) 1356 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1357 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1358 N0.getOperand(0), N1), 1359 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1360 N0.getOperand(1), N1)); 1361 1362 // reassociate mul 1363 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1364 if (RMUL.getNode() != 0) 1365 return RMUL; 1366 1367 return SDValue(); 1368} 1369 1370SDValue DAGCombiner::visitSDIV(SDNode *N) { 1371 SDValue N0 = N->getOperand(0); 1372 SDValue N1 = N->getOperand(1); 1373 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1374 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1375 MVT VT = N->getValueType(0); 1376 1377 // fold vector ops 1378 if (VT.isVector()) { 1379 SDValue FoldedVOp = SimplifyVBinOp(N); 1380 if (FoldedVOp.getNode()) return FoldedVOp; 1381 } 1382 1383 // fold (sdiv c1, c2) -> c1/c2 1384 if (N0C && N1C && !N1C->isNullValue()) 1385 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1386 // fold (sdiv X, 1) -> X 1387 if (N1C && N1C->getSExtValue() == 1LL) 1388 return N0; 1389 // fold (sdiv X, -1) -> 0-X 1390 if (N1C && N1C->isAllOnesValue()) 1391 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1392 DAG.getConstant(0, VT), N0); 1393 // If we know the sign bits of both operands are zero, strength reduce to a 1394 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1395 if (!VT.isVector()) { 1396 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1397 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1398 N0, N1); 1399 } 1400 // fold (sdiv X, pow2) -> simple ops after legalize 1401 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1402 (isPowerOf2_64(N1C->getSExtValue()) || 1403 isPowerOf2_64(-N1C->getSExtValue()))) { 1404 // If dividing by powers of two is cheap, then don't perform the following 1405 // fold. 1406 if (TLI.isPow2DivCheap()) 1407 return SDValue(); 1408 1409 int64_t pow2 = N1C->getSExtValue(); 1410 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1411 unsigned lg2 = Log2_64(abs2); 1412 1413 // Splat the sign bit into the register 1414 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1415 DAG.getConstant(VT.getSizeInBits()-1, 1416 getShiftAmountTy())); 1417 AddToWorkList(SGN.getNode()); 1418 1419 // Add (N0 < 0) ? abs2 - 1 : 0; 1420 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1421 DAG.getConstant(VT.getSizeInBits() - lg2, 1422 getShiftAmountTy())); 1423 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1424 AddToWorkList(SRL.getNode()); 1425 AddToWorkList(ADD.getNode()); // Divide by pow2 1426 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1427 DAG.getConstant(lg2, getShiftAmountTy())); 1428 1429 // If we're dividing by a positive value, we're done. Otherwise, we must 1430 // negate the result. 1431 if (pow2 > 0) 1432 return SRA; 1433 1434 AddToWorkList(SRA.getNode()); 1435 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1436 DAG.getConstant(0, VT), SRA); 1437 } 1438 1439 // if integer divide is expensive and we satisfy the requirements, emit an 1440 // alternate sequence. 1441 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1442 !TLI.isIntDivCheap()) { 1443 SDValue Op = BuildSDIV(N); 1444 if (Op.getNode()) return Op; 1445 } 1446 1447 // undef / X -> 0 1448 if (N0.getOpcode() == ISD::UNDEF) 1449 return DAG.getConstant(0, VT); 1450 // X / undef -> undef 1451 if (N1.getOpcode() == ISD::UNDEF) 1452 return N1; 1453 1454 return SDValue(); 1455} 1456 1457SDValue DAGCombiner::visitUDIV(SDNode *N) { 1458 SDValue N0 = N->getOperand(0); 1459 SDValue N1 = N->getOperand(1); 1460 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1461 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1462 MVT VT = N->getValueType(0); 1463 1464 // fold vector ops 1465 if (VT.isVector()) { 1466 SDValue FoldedVOp = SimplifyVBinOp(N); 1467 if (FoldedVOp.getNode()) return FoldedVOp; 1468 } 1469 1470 // fold (udiv c1, c2) -> c1/c2 1471 if (N0C && N1C && !N1C->isNullValue()) 1472 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1473 // fold (udiv x, (1 << c)) -> x >>u c 1474 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1475 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1476 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1477 getShiftAmountTy())); 1478 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1479 if (N1.getOpcode() == ISD::SHL) { 1480 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1481 if (SHC->getAPIntValue().isPowerOf2()) { 1482 MVT ADDVT = N1.getOperand(1).getValueType(); 1483 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1484 N1.getOperand(1), 1485 DAG.getConstant(SHC->getAPIntValue() 1486 .logBase2(), 1487 ADDVT)); 1488 AddToWorkList(Add.getNode()); 1489 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1490 } 1491 } 1492 } 1493 // fold (udiv x, c) -> alternate 1494 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1495 SDValue Op = BuildUDIV(N); 1496 if (Op.getNode()) return Op; 1497 } 1498 1499 // undef / X -> 0 1500 if (N0.getOpcode() == ISD::UNDEF) 1501 return DAG.getConstant(0, VT); 1502 // X / undef -> undef 1503 if (N1.getOpcode() == ISD::UNDEF) 1504 return N1; 1505 1506 return SDValue(); 1507} 1508 1509SDValue DAGCombiner::visitSREM(SDNode *N) { 1510 SDValue N0 = N->getOperand(0); 1511 SDValue N1 = N->getOperand(1); 1512 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1513 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1514 MVT VT = N->getValueType(0); 1515 1516 // fold (srem c1, c2) -> c1%c2 1517 if (N0C && N1C && !N1C->isNullValue()) 1518 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1519 // If we know the sign bits of both operands are zero, strength reduce to a 1520 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1521 if (!VT.isVector()) { 1522 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1523 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1524 } 1525 1526 // If X/C can be simplified by the division-by-constant logic, lower 1527 // X%C to the equivalent of X-X/C*C. 1528 if (N1C && !N1C->isNullValue()) { 1529 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1530 AddToWorkList(Div.getNode()); 1531 SDValue OptimizedDiv = combine(Div.getNode()); 1532 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1533 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1534 OptimizedDiv, N1); 1535 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1536 AddToWorkList(Mul.getNode()); 1537 return Sub; 1538 } 1539 } 1540 1541 // undef % X -> 0 1542 if (N0.getOpcode() == ISD::UNDEF) 1543 return DAG.getConstant(0, VT); 1544 // X % undef -> undef 1545 if (N1.getOpcode() == ISD::UNDEF) 1546 return N1; 1547 1548 return SDValue(); 1549} 1550 1551SDValue DAGCombiner::visitUREM(SDNode *N) { 1552 SDValue N0 = N->getOperand(0); 1553 SDValue N1 = N->getOperand(1); 1554 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1555 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1556 MVT VT = N->getValueType(0); 1557 1558 // fold (urem c1, c2) -> c1%c2 1559 if (N0C && N1C && !N1C->isNullValue()) 1560 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1561 // fold (urem x, pow2) -> (and x, pow2-1) 1562 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1563 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1564 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1565 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1566 if (N1.getOpcode() == ISD::SHL) { 1567 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1568 if (SHC->getAPIntValue().isPowerOf2()) { 1569 SDValue Add = 1570 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1571 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1572 VT)); 1573 AddToWorkList(Add.getNode()); 1574 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1575 } 1576 } 1577 } 1578 1579 // If X/C can be simplified by the division-by-constant logic, lower 1580 // X%C to the equivalent of X-X/C*C. 1581 if (N1C && !N1C->isNullValue()) { 1582 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1583 AddToWorkList(Div.getNode()); 1584 SDValue OptimizedDiv = combine(Div.getNode()); 1585 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1586 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1587 OptimizedDiv, N1); 1588 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1589 AddToWorkList(Mul.getNode()); 1590 return Sub; 1591 } 1592 } 1593 1594 // undef % X -> 0 1595 if (N0.getOpcode() == ISD::UNDEF) 1596 return DAG.getConstant(0, VT); 1597 // X % undef -> undef 1598 if (N1.getOpcode() == ISD::UNDEF) 1599 return N1; 1600 1601 return SDValue(); 1602} 1603 1604SDValue DAGCombiner::visitMULHS(SDNode *N) { 1605 SDValue N0 = N->getOperand(0); 1606 SDValue N1 = N->getOperand(1); 1607 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1608 MVT VT = N->getValueType(0); 1609 1610 // fold (mulhs x, 0) -> 0 1611 if (N1C && N1C->isNullValue()) 1612 return N1; 1613 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1614 if (N1C && N1C->getAPIntValue() == 1) 1615 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1616 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1617 getShiftAmountTy())); 1618 // fold (mulhs x, undef) -> 0 1619 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1620 return DAG.getConstant(0, VT); 1621 1622 return SDValue(); 1623} 1624 1625SDValue DAGCombiner::visitMULHU(SDNode *N) { 1626 SDValue N0 = N->getOperand(0); 1627 SDValue N1 = N->getOperand(1); 1628 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1629 MVT VT = N->getValueType(0); 1630 1631 // fold (mulhu x, 0) -> 0 1632 if (N1C && N1C->isNullValue()) 1633 return N1; 1634 // fold (mulhu x, 1) -> 0 1635 if (N1C && N1C->getAPIntValue() == 1) 1636 return DAG.getConstant(0, N0.getValueType()); 1637 // fold (mulhu x, undef) -> 0 1638 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1639 return DAG.getConstant(0, VT); 1640 1641 return SDValue(); 1642} 1643 1644/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1645/// compute two values. LoOp and HiOp give the opcodes for the two computations 1646/// that are being performed. Return true if a simplification was made. 1647/// 1648SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1649 unsigned HiOp) { 1650 // If the high half is not needed, just compute the low half. 1651 bool HiExists = N->hasAnyUseOfValue(1); 1652 if (!HiExists && 1653 (!LegalOperations || 1654 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1655 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1656 N->op_begin(), N->getNumOperands()); 1657 return CombineTo(N, Res, Res); 1658 } 1659 1660 // If the low half is not needed, just compute the high half. 1661 bool LoExists = N->hasAnyUseOfValue(0); 1662 if (!LoExists && 1663 (!LegalOperations || 1664 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1665 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1666 N->op_begin(), N->getNumOperands()); 1667 return CombineTo(N, Res, Res); 1668 } 1669 1670 // If both halves are used, return as it is. 1671 if (LoExists && HiExists) 1672 return SDValue(); 1673 1674 // If the two computed results can be simplified separately, separate them. 1675 if (LoExists) { 1676 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1677 N->op_begin(), N->getNumOperands()); 1678 AddToWorkList(Lo.getNode()); 1679 SDValue LoOpt = combine(Lo.getNode()); 1680 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1681 (!LegalOperations || 1682 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1683 return CombineTo(N, LoOpt, LoOpt); 1684 } 1685 1686 if (HiExists) { 1687 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1688 N->op_begin(), N->getNumOperands()); 1689 AddToWorkList(Hi.getNode()); 1690 SDValue HiOpt = combine(Hi.getNode()); 1691 if (HiOpt.getNode() && HiOpt != Hi && 1692 (!LegalOperations || 1693 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1694 return CombineTo(N, HiOpt, HiOpt); 1695 } 1696 1697 return SDValue(); 1698} 1699 1700SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1701 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1702 if (Res.getNode()) return Res; 1703 1704 return SDValue(); 1705} 1706 1707SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1708 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1709 if (Res.getNode()) return Res; 1710 1711 return SDValue(); 1712} 1713 1714SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1715 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1716 if (Res.getNode()) return Res; 1717 1718 return SDValue(); 1719} 1720 1721SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1722 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1723 if (Res.getNode()) return Res; 1724 1725 return SDValue(); 1726} 1727 1728/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1729/// two operands of the same opcode, try to simplify it. 1730SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1731 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1732 MVT VT = N0.getValueType(); 1733 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1734 1735 // For each of OP in AND/OR/XOR: 1736 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1737 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1738 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1739 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1740 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1741 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1742 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1743 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1744 N0.getOperand(0).getValueType(), 1745 N0.getOperand(0), N1.getOperand(0)); 1746 AddToWorkList(ORNode.getNode()); 1747 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1748 } 1749 1750 // For each of OP in SHL/SRL/SRA/AND... 1751 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1752 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1753 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1754 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1755 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1756 N0.getOperand(1) == N1.getOperand(1)) { 1757 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1758 N0.getOperand(0).getValueType(), 1759 N0.getOperand(0), N1.getOperand(0)); 1760 AddToWorkList(ORNode.getNode()); 1761 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1762 ORNode, N0.getOperand(1)); 1763 } 1764 1765 return SDValue(); 1766} 1767 1768SDValue DAGCombiner::visitAND(SDNode *N) { 1769 SDValue N0 = N->getOperand(0); 1770 SDValue N1 = N->getOperand(1); 1771 SDValue LL, LR, RL, RR, CC0, CC1; 1772 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1773 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1774 MVT VT = N1.getValueType(); 1775 unsigned BitWidth = VT.getSizeInBits(); 1776 1777 // fold vector ops 1778 if (VT.isVector()) { 1779 SDValue FoldedVOp = SimplifyVBinOp(N); 1780 if (FoldedVOp.getNode()) return FoldedVOp; 1781 } 1782 1783 // fold (and x, undef) -> 0 1784 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1785 return DAG.getConstant(0, VT); 1786 // fold (and c1, c2) -> c1&c2 1787 if (N0C && N1C) 1788 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1789 // canonicalize constant to RHS 1790 if (N0C && !N1C) 1791 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1792 // fold (and x, -1) -> x 1793 if (N1C && N1C->isAllOnesValue()) 1794 return N0; 1795 // if (and x, c) is known to be zero, return 0 1796 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1797 APInt::getAllOnesValue(BitWidth))) 1798 return DAG.getConstant(0, VT); 1799 // reassociate and 1800 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1801 if (RAND.getNode() != 0) 1802 return RAND; 1803 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1804 if (N1C && N0.getOpcode() == ISD::OR) 1805 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1806 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1807 return N1; 1808 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1809 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1810 SDValue N0Op0 = N0.getOperand(0); 1811 APInt Mask = ~N1C->getAPIntValue(); 1812 Mask.trunc(N0Op0.getValueSizeInBits()); 1813 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1814 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1815 N0.getValueType(), N0Op0); 1816 1817 // Replace uses of the AND with uses of the Zero extend node. 1818 CombineTo(N, Zext); 1819 1820 // We actually want to replace all uses of the any_extend with the 1821 // zero_extend, to avoid duplicating things. This will later cause this 1822 // AND to be folded. 1823 CombineTo(N0.getNode(), Zext); 1824 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1825 } 1826 } 1827 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1828 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1829 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1830 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1831 1832 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1833 LL.getValueType().isInteger()) { 1834 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1835 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1836 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1837 LR.getValueType(), LL, RL); 1838 AddToWorkList(ORNode.getNode()); 1839 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1840 } 1841 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1842 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1843 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1844 LR.getValueType(), LL, RL); 1845 AddToWorkList(ANDNode.getNode()); 1846 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1847 } 1848 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1849 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1850 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1851 LR.getValueType(), LL, RL); 1852 AddToWorkList(ORNode.getNode()); 1853 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1854 } 1855 } 1856 // canonicalize equivalent to ll == rl 1857 if (LL == RR && LR == RL) { 1858 Op1 = ISD::getSetCCSwappedOperands(Op1); 1859 std::swap(RL, RR); 1860 } 1861 if (LL == RL && LR == RR) { 1862 bool isInteger = LL.getValueType().isInteger(); 1863 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1864 if (Result != ISD::SETCC_INVALID && 1865 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1866 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1867 LL, LR, Result); 1868 } 1869 } 1870 1871 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1872 if (N0.getOpcode() == N1.getOpcode()) { 1873 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1874 if (Tmp.getNode()) return Tmp; 1875 } 1876 1877 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1878 // fold (and (sra)) -> (and (srl)) when possible. 1879 if (!VT.isVector() && 1880 SimplifyDemandedBits(SDValue(N, 0))) 1881 return SDValue(N, 0); 1882 // fold (zext_inreg (extload x)) -> (zextload x) 1883 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1884 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1885 MVT EVT = LN0->getMemoryVT(); 1886 // If we zero all the possible extended bits, then we can turn this into 1887 // a zextload if we are running before legalize or the operation is legal. 1888 unsigned BitWidth = N1.getValueSizeInBits(); 1889 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1890 BitWidth - EVT.getSizeInBits())) && 1891 ((!LegalOperations && !LN0->isVolatile()) || 1892 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1893 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1894 LN0->getChain(), LN0->getBasePtr(), 1895 LN0->getSrcValue(), 1896 LN0->getSrcValueOffset(), EVT, 1897 LN0->isVolatile(), LN0->getAlignment()); 1898 AddToWorkList(N); 1899 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1900 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1901 } 1902 } 1903 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1904 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1905 N0.hasOneUse()) { 1906 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1907 MVT EVT = LN0->getMemoryVT(); 1908 // If we zero all the possible extended bits, then we can turn this into 1909 // a zextload if we are running before legalize or the operation is legal. 1910 unsigned BitWidth = N1.getValueSizeInBits(); 1911 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1912 BitWidth - EVT.getSizeInBits())) && 1913 ((!LegalOperations && !LN0->isVolatile()) || 1914 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1915 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1916 LN0->getChain(), 1917 LN0->getBasePtr(), LN0->getSrcValue(), 1918 LN0->getSrcValueOffset(), EVT, 1919 LN0->isVolatile(), LN0->getAlignment()); 1920 AddToWorkList(N); 1921 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1922 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1923 } 1924 } 1925 1926 // fold (and (load x), 255) -> (zextload x, i8) 1927 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1928 if (N1C && N0.getOpcode() == ISD::LOAD) { 1929 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1930 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1931 LN0->isUnindexed() && N0.hasOneUse() && 1932 // Do not change the width of a volatile load. 1933 !LN0->isVolatile()) { 1934 MVT EVT = MVT::Other; 1935 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1936 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1937 EVT = MVT::getIntegerVT(ActiveBits); 1938 1939 MVT LoadedVT = LN0->getMemoryVT(); 1940 1941 // Do not generate loads of non-round integer types since these can 1942 // be expensive (and would be wrong if the type is not byte sized). 1943 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1944 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1945 MVT PtrType = N0.getOperand(1).getValueType(); 1946 1947 // For big endian targets, we need to add an offset to the pointer to 1948 // load the correct bytes. For little endian systems, we merely need to 1949 // read fewer bytes from the same pointer. 1950 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1951 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1952 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1953 unsigned Alignment = LN0->getAlignment(); 1954 SDValue NewPtr = LN0->getBasePtr(); 1955 1956 if (TLI.isBigEndian()) { 1957 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1958 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1959 Alignment = MinAlign(Alignment, PtrOff); 1960 } 1961 1962 AddToWorkList(NewPtr.getNode()); 1963 SDValue Load = 1964 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1965 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1966 EVT, LN0->isVolatile(), Alignment); 1967 AddToWorkList(N); 1968 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1969 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1970 } 1971 } 1972 } 1973 1974 return SDValue(); 1975} 1976 1977SDValue DAGCombiner::visitOR(SDNode *N) { 1978 SDValue N0 = N->getOperand(0); 1979 SDValue N1 = N->getOperand(1); 1980 SDValue LL, LR, RL, RR, CC0, CC1; 1981 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1982 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1983 MVT VT = N1.getValueType(); 1984 1985 // fold vector ops 1986 if (VT.isVector()) { 1987 SDValue FoldedVOp = SimplifyVBinOp(N); 1988 if (FoldedVOp.getNode()) return FoldedVOp; 1989 } 1990 1991 // fold (or x, undef) -> -1 1992 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1993 return DAG.getConstant(~0ULL, VT); 1994 // fold (or c1, c2) -> c1|c2 1995 if (N0C && N1C) 1996 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1997 // canonicalize constant to RHS 1998 if (N0C && !N1C) 1999 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2000 // fold (or x, 0) -> x 2001 if (N1C && N1C->isNullValue()) 2002 return N0; 2003 // fold (or x, -1) -> -1 2004 if (N1C && N1C->isAllOnesValue()) 2005 return N1; 2006 // fold (or x, c) -> c iff (x & ~c) == 0 2007 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2008 return N1; 2009 // reassociate or 2010 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2011 if (ROR.getNode() != 0) 2012 return ROR; 2013 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2014 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2015 isa<ConstantSDNode>(N0.getOperand(1))) { 2016 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2017 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2018 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2019 N0.getOperand(0), N1), 2020 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2021 } 2022 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2023 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2024 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2025 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2026 2027 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2028 LL.getValueType().isInteger()) { 2029 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2030 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2031 if (cast<ConstantSDNode>(LR)->isNullValue() && 2032 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2033 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2034 LR.getValueType(), LL, RL); 2035 AddToWorkList(ORNode.getNode()); 2036 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2037 } 2038 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2039 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2040 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2041 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2042 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2043 LR.getValueType(), LL, RL); 2044 AddToWorkList(ANDNode.getNode()); 2045 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2046 } 2047 } 2048 // canonicalize equivalent to ll == rl 2049 if (LL == RR && LR == RL) { 2050 Op1 = ISD::getSetCCSwappedOperands(Op1); 2051 std::swap(RL, RR); 2052 } 2053 if (LL == RL && LR == RR) { 2054 bool isInteger = LL.getValueType().isInteger(); 2055 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2056 if (Result != ISD::SETCC_INVALID && 2057 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2058 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2059 LL, LR, Result); 2060 } 2061 } 2062 2063 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2064 if (N0.getOpcode() == N1.getOpcode()) { 2065 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2066 if (Tmp.getNode()) return Tmp; 2067 } 2068 2069 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2070 if (N0.getOpcode() == ISD::AND && 2071 N1.getOpcode() == ISD::AND && 2072 N0.getOperand(1).getOpcode() == ISD::Constant && 2073 N1.getOperand(1).getOpcode() == ISD::Constant && 2074 // Don't increase # computations. 2075 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2076 // We can only do this xform if we know that bits from X that are set in C2 2077 // but not in C1 are already zero. Likewise for Y. 2078 const APInt &LHSMask = 2079 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2080 const APInt &RHSMask = 2081 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2082 2083 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2084 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2085 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2086 N0.getOperand(0), N1.getOperand(0)); 2087 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2088 DAG.getConstant(LHSMask | RHSMask, VT)); 2089 } 2090 } 2091 2092 // See if this is some rotate idiom. 2093 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2094 return SDValue(Rot, 0); 2095 2096 return SDValue(); 2097} 2098 2099/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2100static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2101 if (Op.getOpcode() == ISD::AND) { 2102 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2103 Mask = Op.getOperand(1); 2104 Op = Op.getOperand(0); 2105 } else { 2106 return false; 2107 } 2108 } 2109 2110 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2111 Shift = Op; 2112 return true; 2113 } 2114 2115 return false; 2116} 2117 2118// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2119// idioms for rotate, and if the target supports rotation instructions, generate 2120// a rot[lr]. 2121SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2122 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2123 MVT VT = LHS.getValueType(); 2124 if (!TLI.isTypeLegal(VT)) return 0; 2125 2126 // The target must have at least one rotate flavor. 2127 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2128 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2129 if (!HasROTL && !HasROTR) return 0; 2130 2131 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2132 SDValue LHSShift; // The shift. 2133 SDValue LHSMask; // AND value if any. 2134 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2135 return 0; // Not part of a rotate. 2136 2137 SDValue RHSShift; // The shift. 2138 SDValue RHSMask; // AND value if any. 2139 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2140 return 0; // Not part of a rotate. 2141 2142 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2143 return 0; // Not shifting the same value. 2144 2145 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2146 return 0; // Shifts must disagree. 2147 2148 // Canonicalize shl to left side in a shl/srl pair. 2149 if (RHSShift.getOpcode() == ISD::SHL) { 2150 std::swap(LHS, RHS); 2151 std::swap(LHSShift, RHSShift); 2152 std::swap(LHSMask , RHSMask ); 2153 } 2154 2155 unsigned OpSizeInBits = VT.getSizeInBits(); 2156 SDValue LHSShiftArg = LHSShift.getOperand(0); 2157 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2158 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2159 2160 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2161 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2162 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2163 RHSShiftAmt.getOpcode() == ISD::Constant) { 2164 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2165 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2166 if ((LShVal + RShVal) != OpSizeInBits) 2167 return 0; 2168 2169 SDValue Rot; 2170 if (HasROTL) 2171 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2172 else 2173 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2174 2175 // If there is an AND of either shifted operand, apply it to the result. 2176 if (LHSMask.getNode() || RHSMask.getNode()) { 2177 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2178 2179 if (LHSMask.getNode()) { 2180 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2181 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2182 } 2183 if (RHSMask.getNode()) { 2184 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2185 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2186 } 2187 2188 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2189 } 2190 2191 return Rot.getNode(); 2192 } 2193 2194 // If there is a mask here, and we have a variable shift, we can't be sure 2195 // that we're masking out the right stuff. 2196 if (LHSMask.getNode() || RHSMask.getNode()) 2197 return 0; 2198 2199 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2200 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2201 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2202 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2203 if (ConstantSDNode *SUBC = 2204 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2205 if (SUBC->getAPIntValue() == OpSizeInBits) { 2206 if (HasROTL) 2207 return DAG.getNode(ISD::ROTL, DL, VT, 2208 LHSShiftArg, LHSShiftAmt).getNode(); 2209 else 2210 return DAG.getNode(ISD::ROTR, DL, VT, 2211 LHSShiftArg, RHSShiftAmt).getNode(); 2212 } 2213 } 2214 } 2215 2216 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2217 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2218 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2219 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2220 if (ConstantSDNode *SUBC = 2221 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2222 if (SUBC->getAPIntValue() == OpSizeInBits) { 2223 if (HasROTR) 2224 return DAG.getNode(ISD::ROTR, DL, VT, 2225 LHSShiftArg, RHSShiftAmt).getNode(); 2226 else 2227 return DAG.getNode(ISD::ROTL, DL, VT, 2228 LHSShiftArg, LHSShiftAmt).getNode(); 2229 } 2230 } 2231 } 2232 2233 // Look for sign/zext/any-extended or truncate cases: 2234 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2235 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2236 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2237 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2238 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2239 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2240 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2241 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2242 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2243 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2244 if (RExtOp0.getOpcode() == ISD::SUB && 2245 RExtOp0.getOperand(1) == LExtOp0) { 2246 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2247 // (rotl x, y) 2248 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2249 // (rotr x, (sub 32, y)) 2250 if (ConstantSDNode *SUBC = 2251 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2252 if (SUBC->getAPIntValue() == OpSizeInBits) { 2253 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2254 LHSShiftArg, 2255 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2256 } 2257 } 2258 } else if (LExtOp0.getOpcode() == ISD::SUB && 2259 RExtOp0 == LExtOp0.getOperand(1)) { 2260 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2261 // (rotr x, y) 2262 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2263 // (rotl x, (sub 32, y)) 2264 if (ConstantSDNode *SUBC = 2265 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2266 if (SUBC->getAPIntValue() == OpSizeInBits) { 2267 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2268 LHSShiftArg, 2269 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2270 } 2271 } 2272 } 2273 } 2274 2275 return 0; 2276} 2277 2278SDValue DAGCombiner::visitXOR(SDNode *N) { 2279 SDValue N0 = N->getOperand(0); 2280 SDValue N1 = N->getOperand(1); 2281 SDValue LHS, RHS, CC; 2282 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2283 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2284 MVT VT = N0.getValueType(); 2285 2286 // fold vector ops 2287 if (VT.isVector()) { 2288 SDValue FoldedVOp = SimplifyVBinOp(N); 2289 if (FoldedVOp.getNode()) return FoldedVOp; 2290 } 2291 2292 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2293 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2294 return DAG.getConstant(0, VT); 2295 // fold (xor x, undef) -> undef 2296 if (N0.getOpcode() == ISD::UNDEF) 2297 return N0; 2298 if (N1.getOpcode() == ISD::UNDEF) 2299 return N1; 2300 // fold (xor c1, c2) -> c1^c2 2301 if (N0C && N1C) 2302 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2303 // canonicalize constant to RHS 2304 if (N0C && !N1C) 2305 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2306 // fold (xor x, 0) -> x 2307 if (N1C && N1C->isNullValue()) 2308 return N0; 2309 // reassociate xor 2310 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2311 if (RXOR.getNode() != 0) 2312 return RXOR; 2313 2314 // fold !(x cc y) -> (x !cc y) 2315 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2316 bool isInt = LHS.getValueType().isInteger(); 2317 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2318 isInt); 2319 2320 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2321 switch (N0.getOpcode()) { 2322 default: 2323 assert(0 && "Unhandled SetCC Equivalent!"); 2324 abort(); 2325 case ISD::SETCC: 2326 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2327 case ISD::SELECT_CC: 2328 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2329 N0.getOperand(3), NotCC); 2330 } 2331 } 2332 } 2333 2334 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2335 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2336 N0.getNode()->hasOneUse() && 2337 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2338 SDValue V = N0.getOperand(0); 2339 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2340 DAG.getConstant(1, V.getValueType())); 2341 AddToWorkList(V.getNode()); 2342 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2343 } 2344 2345 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2346 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2347 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2348 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2349 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2350 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2351 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2352 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2353 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2354 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2355 } 2356 } 2357 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2358 if (N1C && N1C->isAllOnesValue() && 2359 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2360 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2361 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2362 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2363 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2364 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2365 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2366 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2367 } 2368 } 2369 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2370 if (N1C && N0.getOpcode() == ISD::XOR) { 2371 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2372 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2373 if (N00C) 2374 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2375 DAG.getConstant(N1C->getAPIntValue() ^ 2376 N00C->getAPIntValue(), VT)); 2377 if (N01C) 2378 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2379 DAG.getConstant(N1C->getAPIntValue() ^ 2380 N01C->getAPIntValue(), VT)); 2381 } 2382 // fold (xor x, x) -> 0 2383 if (N0 == N1) { 2384 if (!VT.isVector()) { 2385 return DAG.getConstant(0, VT); 2386 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2387 // Produce a vector of zeros. 2388 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2389 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2390 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2391 &Ops[0], Ops.size()); 2392 } 2393 } 2394 2395 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2396 if (N0.getOpcode() == N1.getOpcode()) { 2397 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2398 if (Tmp.getNode()) return Tmp; 2399 } 2400 2401 // Simplify the expression using non-local knowledge. 2402 if (!VT.isVector() && 2403 SimplifyDemandedBits(SDValue(N, 0))) 2404 return SDValue(N, 0); 2405 2406 return SDValue(); 2407} 2408 2409/// visitShiftByConstant - Handle transforms common to the three shifts, when 2410/// the shift amount is a constant. 2411SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2412 SDNode *LHS = N->getOperand(0).getNode(); 2413 if (!LHS->hasOneUse()) return SDValue(); 2414 2415 // We want to pull some binops through shifts, so that we have (and (shift)) 2416 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2417 // thing happens with address calculations, so it's important to canonicalize 2418 // it. 2419 bool HighBitSet = false; // Can we transform this if the high bit is set? 2420 2421 switch (LHS->getOpcode()) { 2422 default: return SDValue(); 2423 case ISD::OR: 2424 case ISD::XOR: 2425 HighBitSet = false; // We can only transform sra if the high bit is clear. 2426 break; 2427 case ISD::AND: 2428 HighBitSet = true; // We can only transform sra if the high bit is set. 2429 break; 2430 case ISD::ADD: 2431 if (N->getOpcode() != ISD::SHL) 2432 return SDValue(); // only shl(add) not sr[al](add). 2433 HighBitSet = false; // We can only transform sra if the high bit is clear. 2434 break; 2435 } 2436 2437 // We require the RHS of the binop to be a constant as well. 2438 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2439 if (!BinOpCst) return SDValue(); 2440 2441 // FIXME: disable this unless the input to the binop is a shift by a constant. 2442 // If it is not a shift, it pessimizes some common cases like: 2443 // 2444 // void foo(int *X, int i) { X[i & 1235] = 1; } 2445 // int bar(int *X, int i) { return X[i & 255]; } 2446 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2447 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2448 BinOpLHSVal->getOpcode() != ISD::SRA && 2449 BinOpLHSVal->getOpcode() != ISD::SRL) || 2450 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2451 return SDValue(); 2452 2453 MVT VT = N->getValueType(0); 2454 2455 // If this is a signed shift right, and the high bit is modified by the 2456 // logical operation, do not perform the transformation. The highBitSet 2457 // boolean indicates the value of the high bit of the constant which would 2458 // cause it to be modified for this operation. 2459 if (N->getOpcode() == ISD::SRA) { 2460 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2461 if (BinOpRHSSignSet != HighBitSet) 2462 return SDValue(); 2463 } 2464 2465 // Fold the constants, shifting the binop RHS by the shift amount. 2466 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2467 N->getValueType(0), 2468 LHS->getOperand(1), N->getOperand(1)); 2469 2470 // Create the new shift. 2471 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2472 VT, LHS->getOperand(0), N->getOperand(1)); 2473 2474 // Create the new binop. 2475 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2476} 2477 2478SDValue DAGCombiner::visitSHL(SDNode *N) { 2479 SDValue N0 = N->getOperand(0); 2480 SDValue N1 = N->getOperand(1); 2481 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2482 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2483 MVT VT = N0.getValueType(); 2484 unsigned OpSizeInBits = VT.getSizeInBits(); 2485 2486 // fold (shl c1, c2) -> c1<<c2 2487 if (N0C && N1C) 2488 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2489 // fold (shl 0, x) -> 0 2490 if (N0C && N0C->isNullValue()) 2491 return N0; 2492 // fold (shl x, c >= size(x)) -> undef 2493 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2494 return DAG.getUNDEF(VT); 2495 // fold (shl x, 0) -> x 2496 if (N1C && N1C->isNullValue()) 2497 return N0; 2498 // if (shl x, c) is known to be zero, return 0 2499 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2500 APInt::getAllOnesValue(VT.getSizeInBits()))) 2501 return DAG.getConstant(0, VT); 2502 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2503 if (N1.getOpcode() == ISD::TRUNCATE && 2504 N1.getOperand(0).getOpcode() == ISD::AND && 2505 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2506 SDValue N101 = N1.getOperand(0).getOperand(1); 2507 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2508 MVT TruncVT = N1.getValueType(); 2509 SDValue N100 = N1.getOperand(0).getOperand(0); 2510 APInt TruncC = N101C->getAPIntValue(); 2511 TruncC.trunc(TruncVT.getSizeInBits()); 2512 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2513 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2514 DAG.getNode(ISD::TRUNCATE, 2515 N->getDebugLoc(), 2516 TruncVT, N100), 2517 DAG.getConstant(TruncC, TruncVT))); 2518 } 2519 } 2520 2521 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2522 return SDValue(N, 0); 2523 2524 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2525 if (N1C && N0.getOpcode() == ISD::SHL && 2526 N0.getOperand(1).getOpcode() == ISD::Constant) { 2527 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2528 uint64_t c2 = N1C->getZExtValue(); 2529 if (c1 + c2 > OpSizeInBits) 2530 return DAG.getConstant(0, VT); 2531 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2532 DAG.getConstant(c1 + c2, N1.getValueType())); 2533 } 2534 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2535 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2536 if (N1C && N0.getOpcode() == ISD::SRL && 2537 N0.getOperand(1).getOpcode() == ISD::Constant) { 2538 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2539 uint64_t c2 = N1C->getZExtValue(); 2540 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), 2541 DAG.getConstant(~0ULL << c1, VT)); 2542 if (c2 > c1) 2543 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2544 DAG.getConstant(c2-c1, N1.getValueType())); 2545 else 2546 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2547 DAG.getConstant(c1-c2, N1.getValueType())); 2548 } 2549 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2550 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2551 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2552 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2553 2554 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2555} 2556 2557SDValue DAGCombiner::visitSRA(SDNode *N) { 2558 SDValue N0 = N->getOperand(0); 2559 SDValue N1 = N->getOperand(1); 2560 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2561 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2562 MVT VT = N0.getValueType(); 2563 2564 // fold (sra c1, c2) -> (sra c1, c2) 2565 if (N0C && N1C) 2566 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2567 // fold (sra 0, x) -> 0 2568 if (N0C && N0C->isNullValue()) 2569 return N0; 2570 // fold (sra -1, x) -> -1 2571 if (N0C && N0C->isAllOnesValue()) 2572 return N0; 2573 // fold (sra x, (setge c, size(x))) -> undef 2574 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2575 return DAG.getUNDEF(VT); 2576 // fold (sra x, 0) -> x 2577 if (N1C && N1C->isNullValue()) 2578 return N0; 2579 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2580 // sext_inreg. 2581 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2582 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2583 MVT EVT = MVT::getIntegerVT(LowBits); 2584 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2585 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2586 N0.getOperand(0), DAG.getValueType(EVT)); 2587 } 2588 2589 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2590 if (N1C && N0.getOpcode() == ISD::SRA) { 2591 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2592 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2593 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2594 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2595 DAG.getConstant(Sum, N1C->getValueType(0))); 2596 } 2597 } 2598 2599 // fold (sra (shl X, m), (sub result_size, n)) 2600 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2601 // result_size - n != m. 2602 // If truncate is free for the target sext(shl) is likely to result in better 2603 // code. 2604 if (N0.getOpcode() == ISD::SHL) { 2605 // Get the two constanst of the shifts, CN0 = m, CN = n. 2606 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2607 if (N01C && N1C) { 2608 // Determine what the truncate's result bitsize and type would be. 2609 unsigned VTValSize = VT.getSizeInBits(); 2610 MVT TruncVT = 2611 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2612 // Determine the residual right-shift amount. 2613 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2614 2615 // If the shift is not a no-op (in which case this should be just a sign 2616 // extend already), the truncated to type is legal, sign_extend is legal 2617 // on that type, and the the truncate to that type is both legal and free, 2618 // perform the transform. 2619 if (ShiftAmt && 2620 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2621 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2622 TLI.isTruncateFree(VT, TruncVT)) { 2623 2624 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2625 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2626 N0.getOperand(0), Amt); 2627 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2628 Shift); 2629 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2630 N->getValueType(0), Trunc); 2631 } 2632 } 2633 } 2634 2635 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2636 if (N1.getOpcode() == ISD::TRUNCATE && 2637 N1.getOperand(0).getOpcode() == ISD::AND && 2638 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2639 SDValue N101 = N1.getOperand(0).getOperand(1); 2640 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2641 MVT TruncVT = N1.getValueType(); 2642 SDValue N100 = N1.getOperand(0).getOperand(0); 2643 APInt TruncC = N101C->getAPIntValue(); 2644 TruncC.trunc(TruncVT.getSizeInBits()); 2645 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2646 DAG.getNode(ISD::AND, N->getDebugLoc(), 2647 TruncVT, 2648 DAG.getNode(ISD::TRUNCATE, 2649 N->getDebugLoc(), 2650 TruncVT, N100), 2651 DAG.getConstant(TruncC, TruncVT))); 2652 } 2653 } 2654 2655 // Simplify, based on bits shifted out of the LHS. 2656 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2657 return SDValue(N, 0); 2658 2659 2660 // If the sign bit is known to be zero, switch this to a SRL. 2661 if (DAG.SignBitIsZero(N0)) 2662 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2663 2664 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2665} 2666 2667SDValue DAGCombiner::visitSRL(SDNode *N) { 2668 SDValue N0 = N->getOperand(0); 2669 SDValue N1 = N->getOperand(1); 2670 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2671 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2672 MVT VT = N0.getValueType(); 2673 unsigned OpSizeInBits = VT.getSizeInBits(); 2674 2675 // fold (srl c1, c2) -> c1 >>u c2 2676 if (N0C && N1C) 2677 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2678 // fold (srl 0, x) -> 0 2679 if (N0C && N0C->isNullValue()) 2680 return N0; 2681 // fold (srl x, c >= size(x)) -> undef 2682 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2683 return DAG.getUNDEF(VT); 2684 // fold (srl x, 0) -> x 2685 if (N1C && N1C->isNullValue()) 2686 return N0; 2687 // if (srl x, c) is known to be zero, return 0 2688 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2689 APInt::getAllOnesValue(OpSizeInBits))) 2690 return DAG.getConstant(0, VT); 2691 2692 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2693 if (N1C && N0.getOpcode() == ISD::SRL && 2694 N0.getOperand(1).getOpcode() == ISD::Constant) { 2695 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2696 uint64_t c2 = N1C->getZExtValue(); 2697 if (c1 + c2 > OpSizeInBits) 2698 return DAG.getConstant(0, VT); 2699 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2700 DAG.getConstant(c1 + c2, N1.getValueType())); 2701 } 2702 2703 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2704 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2705 // Shifting in all undef bits? 2706 MVT SmallVT = N0.getOperand(0).getValueType(); 2707 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2708 return DAG.getUNDEF(VT); 2709 2710 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2711 N0.getOperand(0), N1); 2712 AddToWorkList(SmallShift.getNode()); 2713 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2714 } 2715 2716 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2717 // bit, which is unmodified by sra. 2718 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2719 if (N0.getOpcode() == ISD::SRA) 2720 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2721 } 2722 2723 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2724 if (N1C && N0.getOpcode() == ISD::CTLZ && 2725 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2726 APInt KnownZero, KnownOne; 2727 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2728 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2729 2730 // If any of the input bits are KnownOne, then the input couldn't be all 2731 // zeros, thus the result of the srl will always be zero. 2732 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2733 2734 // If all of the bits input the to ctlz node are known to be zero, then 2735 // the result of the ctlz is "32" and the result of the shift is one. 2736 APInt UnknownBits = ~KnownZero & Mask; 2737 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2738 2739 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2740 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2741 // Okay, we know that only that the single bit specified by UnknownBits 2742 // could be set on input to the CTLZ node. If this bit is set, the SRL 2743 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2744 // to an SRL/XOR pair, which is likely to simplify more. 2745 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2746 SDValue Op = N0.getOperand(0); 2747 2748 if (ShAmt) { 2749 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2750 DAG.getConstant(ShAmt, getShiftAmountTy())); 2751 AddToWorkList(Op.getNode()); 2752 } 2753 2754 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2755 Op, DAG.getConstant(1, VT)); 2756 } 2757 } 2758 2759 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2760 if (N1.getOpcode() == ISD::TRUNCATE && 2761 N1.getOperand(0).getOpcode() == ISD::AND && 2762 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2763 SDValue N101 = N1.getOperand(0).getOperand(1); 2764 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2765 MVT TruncVT = N1.getValueType(); 2766 SDValue N100 = N1.getOperand(0).getOperand(0); 2767 APInt TruncC = N101C->getAPIntValue(); 2768 TruncC.trunc(TruncVT.getSizeInBits()); 2769 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2770 DAG.getNode(ISD::AND, N->getDebugLoc(), 2771 TruncVT, 2772 DAG.getNode(ISD::TRUNCATE, 2773 N->getDebugLoc(), 2774 TruncVT, N100), 2775 DAG.getConstant(TruncC, TruncVT))); 2776 } 2777 } 2778 2779 // fold operands of srl based on knowledge that the low bits are not 2780 // demanded. 2781 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2782 return SDValue(N, 0); 2783 2784 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2785} 2786 2787SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2788 SDValue N0 = N->getOperand(0); 2789 MVT VT = N->getValueType(0); 2790 2791 // fold (ctlz c1) -> c2 2792 if (isa<ConstantSDNode>(N0)) 2793 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2794 return SDValue(); 2795} 2796 2797SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2798 SDValue N0 = N->getOperand(0); 2799 MVT VT = N->getValueType(0); 2800 2801 // fold (cttz c1) -> c2 2802 if (isa<ConstantSDNode>(N0)) 2803 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2804 return SDValue(); 2805} 2806 2807SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2808 SDValue N0 = N->getOperand(0); 2809 MVT VT = N->getValueType(0); 2810 2811 // fold (ctpop c1) -> c2 2812 if (isa<ConstantSDNode>(N0)) 2813 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2814 return SDValue(); 2815} 2816 2817SDValue DAGCombiner::visitSELECT(SDNode *N) { 2818 SDValue N0 = N->getOperand(0); 2819 SDValue N1 = N->getOperand(1); 2820 SDValue N2 = N->getOperand(2); 2821 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2822 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2823 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2824 MVT VT = N->getValueType(0); 2825 MVT VT0 = N0.getValueType(); 2826 2827 // fold (select C, X, X) -> X 2828 if (N1 == N2) 2829 return N1; 2830 // fold (select true, X, Y) -> X 2831 if (N0C && !N0C->isNullValue()) 2832 return N1; 2833 // fold (select false, X, Y) -> Y 2834 if (N0C && N0C->isNullValue()) 2835 return N2; 2836 // fold (select C, 1, X) -> (or C, X) 2837 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2838 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2839 // fold (select C, 0, 1) -> (xor C, 1) 2840 if (VT.isInteger() && 2841 (VT0 == MVT::i1 || 2842 (VT0.isInteger() && 2843 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2844 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2845 SDValue XORNode; 2846 if (VT == VT0) 2847 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2848 N0, DAG.getConstant(1, VT0)); 2849 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2850 N0, DAG.getConstant(1, VT0)); 2851 AddToWorkList(XORNode.getNode()); 2852 if (VT.bitsGT(VT0)) 2853 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2854 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2855 } 2856 // fold (select C, 0, X) -> (and (not C), X) 2857 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2858 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2859 AddToWorkList(NOTNode.getNode()); 2860 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2861 } 2862 // fold (select C, X, 1) -> (or (not C), X) 2863 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2864 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2865 AddToWorkList(NOTNode.getNode()); 2866 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2867 } 2868 // fold (select C, X, 0) -> (and C, X) 2869 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2870 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2871 // fold (select X, X, Y) -> (or X, Y) 2872 // fold (select X, 1, Y) -> (or X, Y) 2873 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2874 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2875 // fold (select X, Y, X) -> (and X, Y) 2876 // fold (select X, Y, 0) -> (and X, Y) 2877 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2878 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2879 2880 // If we can fold this based on the true/false value, do so. 2881 if (SimplifySelectOps(N, N1, N2)) 2882 return SDValue(N, 0); // Don't revisit N. 2883 2884 // fold selects based on a setcc into other things, such as min/max/abs 2885 if (N0.getOpcode() == ISD::SETCC) { 2886 // FIXME: 2887 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2888 // having to say they don't support SELECT_CC on every type the DAG knows 2889 // about, since there is no way to mark an opcode illegal at all value types 2890 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2891 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2892 N0.getOperand(0), N0.getOperand(1), 2893 N1, N2, N0.getOperand(2)); 2894 else 2895 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2896 } 2897 2898 return SDValue(); 2899} 2900 2901SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2902 SDValue N0 = N->getOperand(0); 2903 SDValue N1 = N->getOperand(1); 2904 SDValue N2 = N->getOperand(2); 2905 SDValue N3 = N->getOperand(3); 2906 SDValue N4 = N->getOperand(4); 2907 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2908 2909 // fold select_cc lhs, rhs, x, x, cc -> x 2910 if (N2 == N3) 2911 return N2; 2912 2913 // Determine if the condition we're dealing with is constant 2914 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2915 N0, N1, CC, N->getDebugLoc(), false); 2916 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2917 2918 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2919 if (!SCCC->isNullValue()) 2920 return N2; // cond always true -> true val 2921 else 2922 return N3; // cond always false -> false val 2923 } 2924 2925 // Fold to a simpler select_cc 2926 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2927 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2928 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2929 SCC.getOperand(2)); 2930 2931 // If we can fold this based on the true/false value, do so. 2932 if (SimplifySelectOps(N, N2, N3)) 2933 return SDValue(N, 0); // Don't revisit N. 2934 2935 // fold select_cc into other things, such as min/max/abs 2936 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2937} 2938 2939SDValue DAGCombiner::visitSETCC(SDNode *N) { 2940 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2941 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2942 N->getDebugLoc()); 2943} 2944 2945// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2946// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2947// transformation. Returns true if extension are possible and the above 2948// mentioned transformation is profitable. 2949static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2950 unsigned ExtOpc, 2951 SmallVector<SDNode*, 4> &ExtendNodes, 2952 const TargetLowering &TLI) { 2953 bool HasCopyToRegUses = false; 2954 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2955 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2956 UE = N0.getNode()->use_end(); 2957 UI != UE; ++UI) { 2958 SDNode *User = *UI; 2959 if (User == N) 2960 continue; 2961 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2962 if (User->getOpcode() == ISD::SETCC) { 2963 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2964 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2965 // Sign bits will be lost after a zext. 2966 return false; 2967 bool Add = false; 2968 for (unsigned i = 0; i != 2; ++i) { 2969 SDValue UseOp = User->getOperand(i); 2970 if (UseOp == N0) 2971 continue; 2972 if (!isa<ConstantSDNode>(UseOp)) 2973 return false; 2974 Add = true; 2975 } 2976 if (Add) 2977 ExtendNodes.push_back(User); 2978 } else { 2979 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2980 SDValue UseOp = User->getOperand(i); 2981 if (UseOp == N0) { 2982 // If truncate from extended type to original load type is free 2983 // on this target, then it's ok to extend a CopyToReg. 2984 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2985 HasCopyToRegUses = true; 2986 else 2987 return false; 2988 } 2989 } 2990 } 2991 } 2992 2993 if (HasCopyToRegUses) { 2994 bool BothLiveOut = false; 2995 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2996 UI != UE; ++UI) { 2997 SDNode *User = *UI; 2998 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2999 SDValue UseOp = User->getOperand(i); 3000 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 3001 BothLiveOut = true; 3002 break; 3003 } 3004 } 3005 } 3006 if (BothLiveOut) 3007 // Both unextended and extended values are live out. There had better be 3008 // good a reason for the transformation. 3009 return ExtendNodes.size(); 3010 } 3011 return true; 3012} 3013 3014SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3015 SDValue N0 = N->getOperand(0); 3016 MVT VT = N->getValueType(0); 3017 3018 // fold (sext c1) -> c1 3019 if (isa<ConstantSDNode>(N0)) 3020 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3021 3022 // fold (sext (sext x)) -> (sext x) 3023 // fold (sext (aext x)) -> (sext x) 3024 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3025 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3026 N0.getOperand(0)); 3027 3028 if (N0.getOpcode() == ISD::TRUNCATE) { 3029 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3030 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3031 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3032 if (NarrowLoad.getNode()) { 3033 if (NarrowLoad.getNode() != N0.getNode()) 3034 CombineTo(N0.getNode(), NarrowLoad); 3035 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3036 } 3037 3038 // See if the value being truncated is already sign extended. If so, just 3039 // eliminate the trunc/sext pair. 3040 SDValue Op = N0.getOperand(0); 3041 unsigned OpBits = Op.getValueType().getSizeInBits(); 3042 unsigned MidBits = N0.getValueType().getSizeInBits(); 3043 unsigned DestBits = VT.getSizeInBits(); 3044 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3045 3046 if (OpBits == DestBits) { 3047 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3048 // bits, it is already ready. 3049 if (NumSignBits > DestBits-MidBits) 3050 return Op; 3051 } else if (OpBits < DestBits) { 3052 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3053 // bits, just sext from i32. 3054 if (NumSignBits > OpBits-MidBits) 3055 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3056 } else { 3057 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3058 // bits, just truncate to i32. 3059 if (NumSignBits > OpBits-MidBits) 3060 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3061 } 3062 3063 // fold (sext (truncate x)) -> (sextinreg x). 3064 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3065 N0.getValueType())) { 3066 if (Op.getValueType().bitsLT(VT)) 3067 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3068 else if (Op.getValueType().bitsGT(VT)) 3069 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3070 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3071 DAG.getValueType(N0.getValueType())); 3072 } 3073 } 3074 3075 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3076 if (ISD::isNON_EXTLoad(N0.getNode()) && 3077 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3078 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3079 bool DoXform = true; 3080 SmallVector<SDNode*, 4> SetCCs; 3081 if (!N0.hasOneUse()) 3082 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3083 if (DoXform) { 3084 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3085 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), 3086 VT, LN0->getChain(), 3087 LN0->getBasePtr(), LN0->getSrcValue(), 3088 LN0->getSrcValueOffset(), 3089 N0.getValueType(), 3090 LN0->isVolatile(), LN0->getAlignment()); 3091 CombineTo(N, ExtLoad); 3092 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3093 N0.getValueType(), ExtLoad); 3094 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3095 3096 // Extend SetCC uses if necessary. 3097 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3098 SDNode *SetCC = SetCCs[i]; 3099 SmallVector<SDValue, 4> Ops; 3100 3101 for (unsigned j = 0; j != 2; ++j) { 3102 SDValue SOp = SetCC->getOperand(j); 3103 if (SOp == Trunc) 3104 Ops.push_back(ExtLoad); 3105 else 3106 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3107 VT, SOp)); 3108 } 3109 3110 Ops.push_back(SetCC->getOperand(2)); 3111 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3112 SetCC->getValueType(0), 3113 &Ops[0], Ops.size())); 3114 } 3115 3116 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3117 } 3118 } 3119 3120 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3121 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3122 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3123 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3124 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3125 MVT EVT = LN0->getMemoryVT(); 3126 if ((!LegalOperations && !LN0->isVolatile()) || 3127 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3128 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3129 LN0->getChain(), 3130 LN0->getBasePtr(), LN0->getSrcValue(), 3131 LN0->getSrcValueOffset(), EVT, 3132 LN0->isVolatile(), LN0->getAlignment()); 3133 CombineTo(N, ExtLoad); 3134 CombineTo(N0.getNode(), 3135 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3136 N0.getValueType(), ExtLoad), 3137 ExtLoad.getValue(1)); 3138 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3139 } 3140 } 3141 3142 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3143 if (N0.getOpcode() == ISD::SETCC) { 3144 SDValue SCC = 3145 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3146 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3147 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3148 if (SCC.getNode()) return SCC; 3149 } 3150 3151 // fold (sext x) -> (zext x) if the sign bit is known zero. 3152 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3153 DAG.SignBitIsZero(N0)) 3154 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3155 3156 return SDValue(); 3157} 3158 3159SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3160 SDValue N0 = N->getOperand(0); 3161 MVT VT = N->getValueType(0); 3162 3163 // fold (zext c1) -> c1 3164 if (isa<ConstantSDNode>(N0)) 3165 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3166 // fold (zext (zext x)) -> (zext x) 3167 // fold (zext (aext x)) -> (zext x) 3168 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3169 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3170 N0.getOperand(0)); 3171 3172 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3173 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3174 if (N0.getOpcode() == ISD::TRUNCATE) { 3175 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3176 if (NarrowLoad.getNode()) { 3177 if (NarrowLoad.getNode() != N0.getNode()) 3178 CombineTo(N0.getNode(), NarrowLoad); 3179 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3180 } 3181 } 3182 3183 // fold (zext (truncate x)) -> (and x, mask) 3184 if (N0.getOpcode() == ISD::TRUNCATE && 3185 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3186 SDValue Op = N0.getOperand(0); 3187 if (Op.getValueType().bitsLT(VT)) { 3188 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3189 } else if (Op.getValueType().bitsGT(VT)) { 3190 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3191 } 3192 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3193 } 3194 3195 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3196 if (N0.getOpcode() == ISD::AND && 3197 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3198 N0.getOperand(1).getOpcode() == ISD::Constant) { 3199 SDValue X = N0.getOperand(0).getOperand(0); 3200 if (X.getValueType().bitsLT(VT)) { 3201 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3202 } else if (X.getValueType().bitsGT(VT)) { 3203 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3204 } 3205 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3206 Mask.zext(VT.getSizeInBits()); 3207 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3208 X, DAG.getConstant(Mask, VT)); 3209 } 3210 3211 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3212 if (ISD::isNON_EXTLoad(N0.getNode()) && 3213 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3214 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3215 bool DoXform = true; 3216 SmallVector<SDNode*, 4> SetCCs; 3217 if (!N0.hasOneUse()) 3218 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3219 if (DoXform) { 3220 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3221 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3222 LN0->getChain(), 3223 LN0->getBasePtr(), LN0->getSrcValue(), 3224 LN0->getSrcValueOffset(), 3225 N0.getValueType(), 3226 LN0->isVolatile(), LN0->getAlignment()); 3227 CombineTo(N, ExtLoad); 3228 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3229 N0.getValueType(), ExtLoad); 3230 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3231 3232 // Extend SetCC uses if necessary. 3233 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3234 SDNode *SetCC = SetCCs[i]; 3235 SmallVector<SDValue, 4> Ops; 3236 3237 for (unsigned j = 0; j != 2; ++j) { 3238 SDValue SOp = SetCC->getOperand(j); 3239 if (SOp == Trunc) 3240 Ops.push_back(ExtLoad); 3241 else 3242 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3243 N->getDebugLoc(), VT, SOp)); 3244 } 3245 3246 Ops.push_back(SetCC->getOperand(2)); 3247 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3248 SetCC->getValueType(0), 3249 &Ops[0], Ops.size())); 3250 } 3251 3252 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3253 } 3254 } 3255 3256 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3257 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3258 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3259 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3260 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3261 MVT EVT = LN0->getMemoryVT(); 3262 if ((!LegalOperations && !LN0->isVolatile()) || 3263 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3264 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3265 LN0->getChain(), 3266 LN0->getBasePtr(), LN0->getSrcValue(), 3267 LN0->getSrcValueOffset(), EVT, 3268 LN0->isVolatile(), LN0->getAlignment()); 3269 CombineTo(N, ExtLoad); 3270 CombineTo(N0.getNode(), 3271 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3272 ExtLoad), 3273 ExtLoad.getValue(1)); 3274 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3275 } 3276 } 3277 3278 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3279 if (N0.getOpcode() == ISD::SETCC) { 3280 SDValue SCC = 3281 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3282 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3283 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3284 if (SCC.getNode()) return SCC; 3285 } 3286 3287 return SDValue(); 3288} 3289 3290SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3291 SDValue N0 = N->getOperand(0); 3292 MVT VT = N->getValueType(0); 3293 3294 // fold (aext c1) -> c1 3295 if (isa<ConstantSDNode>(N0)) 3296 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3297 // fold (aext (aext x)) -> (aext x) 3298 // fold (aext (zext x)) -> (zext x) 3299 // fold (aext (sext x)) -> (sext x) 3300 if (N0.getOpcode() == ISD::ANY_EXTEND || 3301 N0.getOpcode() == ISD::ZERO_EXTEND || 3302 N0.getOpcode() == ISD::SIGN_EXTEND) 3303 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3304 3305 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3306 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3307 if (N0.getOpcode() == ISD::TRUNCATE) { 3308 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3309 if (NarrowLoad.getNode()) { 3310 if (NarrowLoad.getNode() != N0.getNode()) 3311 CombineTo(N0.getNode(), NarrowLoad); 3312 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3313 } 3314 } 3315 3316 // fold (aext (truncate x)) 3317 if (N0.getOpcode() == ISD::TRUNCATE) { 3318 SDValue TruncOp = N0.getOperand(0); 3319 if (TruncOp.getValueType() == VT) 3320 return TruncOp; // x iff x size == zext size. 3321 if (TruncOp.getValueType().bitsGT(VT)) 3322 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3323 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3324 } 3325 3326 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3327 if (N0.getOpcode() == ISD::AND && 3328 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3329 N0.getOperand(1).getOpcode() == ISD::Constant) { 3330 SDValue X = N0.getOperand(0).getOperand(0); 3331 if (X.getValueType().bitsLT(VT)) { 3332 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3333 } else if (X.getValueType().bitsGT(VT)) { 3334 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3335 } 3336 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3337 Mask.zext(VT.getSizeInBits()); 3338 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3339 X, DAG.getConstant(Mask, VT)); 3340 } 3341 3342 // fold (aext (load x)) -> (aext (truncate (extload x))) 3343 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3344 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3345 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3346 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3347 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3348 LN0->getChain(), 3349 LN0->getBasePtr(), LN0->getSrcValue(), 3350 LN0->getSrcValueOffset(), 3351 N0.getValueType(), 3352 LN0->isVolatile(), LN0->getAlignment()); 3353 CombineTo(N, ExtLoad); 3354 // Redirect any chain users to the new load. 3355 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3356 SDValue(ExtLoad.getNode(), 1)); 3357 // If any node needs the original loaded value, recompute it. 3358 if (!LN0->use_empty()) 3359 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3360 N0.getValueType(), ExtLoad), 3361 ExtLoad.getValue(1)); 3362 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3363 } 3364 3365 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3366 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3367 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3368 if (N0.getOpcode() == ISD::LOAD && 3369 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3370 N0.hasOneUse()) { 3371 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3372 MVT EVT = LN0->getMemoryVT(); 3373 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3374 VT, LN0->getChain(), LN0->getBasePtr(), 3375 LN0->getSrcValue(), 3376 LN0->getSrcValueOffset(), EVT, 3377 LN0->isVolatile(), LN0->getAlignment()); 3378 CombineTo(N, ExtLoad); 3379 CombineTo(N0.getNode(), 3380 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3381 N0.getValueType(), ExtLoad), 3382 ExtLoad.getValue(1)); 3383 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3384 } 3385 3386 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3387 if (N0.getOpcode() == ISD::SETCC) { 3388 SDValue SCC = 3389 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3390 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3391 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3392 if (SCC.getNode()) 3393 return SCC; 3394 } 3395 3396 return SDValue(); 3397} 3398 3399/// GetDemandedBits - See if the specified operand can be simplified with the 3400/// knowledge that only the bits specified by Mask are used. If so, return the 3401/// simpler operand, otherwise return a null SDValue. 3402SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3403 switch (V.getOpcode()) { 3404 default: break; 3405 case ISD::OR: 3406 case ISD::XOR: 3407 // If the LHS or RHS don't contribute bits to the or, drop them. 3408 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3409 return V.getOperand(1); 3410 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3411 return V.getOperand(0); 3412 break; 3413 case ISD::SRL: 3414 // Only look at single-use SRLs. 3415 if (!V.getNode()->hasOneUse()) 3416 break; 3417 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3418 // See if we can recursively simplify the LHS. 3419 unsigned Amt = RHSC->getZExtValue(); 3420 3421 // Watch out for shift count overflow though. 3422 if (Amt >= Mask.getBitWidth()) break; 3423 APInt NewMask = Mask << Amt; 3424 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3425 if (SimplifyLHS.getNode()) 3426 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3427 SimplifyLHS, V.getOperand(1)); 3428 } 3429 } 3430 return SDValue(); 3431} 3432 3433/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3434/// bits and then truncated to a narrower type and where N is a multiple 3435/// of number of bits of the narrower type, transform it to a narrower load 3436/// from address + N / num of bits of new type. If the result is to be 3437/// extended, also fold the extension to form a extending load. 3438SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3439 unsigned Opc = N->getOpcode(); 3440 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3441 SDValue N0 = N->getOperand(0); 3442 MVT VT = N->getValueType(0); 3443 MVT EVT = VT; 3444 3445 // This transformation isn't valid for vector loads. 3446 if (VT.isVector()) 3447 return SDValue(); 3448 3449 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3450 // extended to VT. 3451 if (Opc == ISD::SIGN_EXTEND_INREG) { 3452 ExtType = ISD::SEXTLOAD; 3453 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3454 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3455 return SDValue(); 3456 } 3457 3458 unsigned EVTBits = EVT.getSizeInBits(); 3459 unsigned ShAmt = 0; 3460 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3461 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3462 ShAmt = N01->getZExtValue(); 3463 // Is the shift amount a multiple of size of VT? 3464 if ((ShAmt & (EVTBits-1)) == 0) { 3465 N0 = N0.getOperand(0); 3466 if (N0.getValueType().getSizeInBits() <= EVTBits) 3467 return SDValue(); 3468 } 3469 } 3470 } 3471 3472 // Do not generate loads of non-round integer types since these can 3473 // be expensive (and would be wrong if the type is not byte sized). 3474 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3475 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3476 // Do not change the width of a volatile load. 3477 !cast<LoadSDNode>(N0)->isVolatile()) { 3478 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3479 MVT PtrType = N0.getOperand(1).getValueType(); 3480 3481 // For big endian targets, we need to adjust the offset to the pointer to 3482 // load the correct bytes. 3483 if (TLI.isBigEndian()) { 3484 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3485 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3486 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3487 } 3488 3489 uint64_t PtrOff = ShAmt / 8; 3490 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3491 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3492 PtrType, LN0->getBasePtr(), 3493 DAG.getConstant(PtrOff, PtrType)); 3494 AddToWorkList(NewPtr.getNode()); 3495 3496 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3497 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3498 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3499 LN0->isVolatile(), NewAlign) 3500 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3501 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3502 EVT, LN0->isVolatile(), NewAlign); 3503 3504 // Replace the old load's chain with the new load's chain. 3505 WorkListRemover DeadNodes(*this); 3506 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3507 &DeadNodes); 3508 3509 // Return the new loaded value. 3510 return Load; 3511 } 3512 3513 return SDValue(); 3514} 3515 3516SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3517 SDValue N0 = N->getOperand(0); 3518 SDValue N1 = N->getOperand(1); 3519 MVT VT = N->getValueType(0); 3520 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3521 unsigned VTBits = VT.getSizeInBits(); 3522 unsigned EVTBits = EVT.getSizeInBits(); 3523 3524 // fold (sext_in_reg c1) -> c1 3525 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3526 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3527 3528 // If the input is already sign extended, just drop the extension. 3529 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3530 return N0; 3531 3532 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3533 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3534 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3535 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3536 N0.getOperand(0), N1); 3537 } 3538 3539 // fold (sext_in_reg (sext x)) -> (sext x) 3540 // fold (sext_in_reg (aext x)) -> (sext x) 3541 // if x is small enough. 3542 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3543 SDValue N00 = N0.getOperand(0); 3544 if (N00.getValueType().getSizeInBits() < EVTBits) 3545 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3546 } 3547 3548 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3549 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3550 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3551 3552 // fold operands of sext_in_reg based on knowledge that the top bits are not 3553 // demanded. 3554 if (SimplifyDemandedBits(SDValue(N, 0))) 3555 return SDValue(N, 0); 3556 3557 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3558 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3559 SDValue NarrowLoad = ReduceLoadWidth(N); 3560 if (NarrowLoad.getNode()) 3561 return NarrowLoad; 3562 3563 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3564 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3565 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3566 if (N0.getOpcode() == ISD::SRL) { 3567 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3568 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3569 // We can turn this into an SRA iff the input to the SRL is already sign 3570 // extended enough. 3571 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3572 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3573 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3574 N0.getOperand(0), N0.getOperand(1)); 3575 } 3576 } 3577 3578 // fold (sext_inreg (extload x)) -> (sextload x) 3579 if (ISD::isEXTLoad(N0.getNode()) && 3580 ISD::isUNINDEXEDLoad(N0.getNode()) && 3581 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3582 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3583 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3584 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3585 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3586 LN0->getChain(), 3587 LN0->getBasePtr(), LN0->getSrcValue(), 3588 LN0->getSrcValueOffset(), EVT, 3589 LN0->isVolatile(), LN0->getAlignment()); 3590 CombineTo(N, ExtLoad); 3591 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3592 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3593 } 3594 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3595 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3596 N0.hasOneUse() && 3597 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3598 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3599 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3600 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3601 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3602 LN0->getChain(), 3603 LN0->getBasePtr(), LN0->getSrcValue(), 3604 LN0->getSrcValueOffset(), EVT, 3605 LN0->isVolatile(), LN0->getAlignment()); 3606 CombineTo(N, ExtLoad); 3607 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3608 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3609 } 3610 return SDValue(); 3611} 3612 3613SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3614 SDValue N0 = N->getOperand(0); 3615 MVT VT = N->getValueType(0); 3616 3617 // noop truncate 3618 if (N0.getValueType() == N->getValueType(0)) 3619 return N0; 3620 // fold (truncate c1) -> c1 3621 if (isa<ConstantSDNode>(N0)) 3622 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3623 // fold (truncate (truncate x)) -> (truncate x) 3624 if (N0.getOpcode() == ISD::TRUNCATE) 3625 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3626 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3627 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3628 N0.getOpcode() == ISD::ANY_EXTEND) { 3629 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3630 // if the source is smaller than the dest, we still need an extend 3631 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3632 N0.getOperand(0)); 3633 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3634 // if the source is larger than the dest, than we just need the truncate 3635 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3636 else 3637 // if the source and dest are the same type, we can drop both the extend 3638 // and the truncate 3639 return N0.getOperand(0); 3640 } 3641 3642 // See if we can simplify the input to this truncate through knowledge that 3643 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3644 // -> trunc y 3645 SDValue Shorter = 3646 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3647 VT.getSizeInBits())); 3648 if (Shorter.getNode()) 3649 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3650 3651 // fold (truncate (load x)) -> (smaller load x) 3652 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3653 return ReduceLoadWidth(N); 3654} 3655 3656static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3657 SDValue Elt = N->getOperand(i); 3658 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3659 return Elt.getNode(); 3660 return Elt.getOperand(Elt.getResNo()).getNode(); 3661} 3662 3663/// CombineConsecutiveLoads - build_pair (load, load) -> load 3664/// if load locations are consecutive. 3665SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3666 assert(N->getOpcode() == ISD::BUILD_PAIR); 3667 3668 SDNode *LD1 = getBuildPairElt(N, 0); 3669 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3670 return SDValue(); 3671 MVT LD1VT = LD1->getValueType(0); 3672 SDNode *LD2 = getBuildPairElt(N, 1); 3673 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3674 3675 if (ISD::isNON_EXTLoad(LD2) && 3676 LD2->hasOneUse() && 3677 // If both are volatile this would reduce the number of volatile loads. 3678 // If one is volatile it might be ok, but play conservative and bail out. 3679 !cast<LoadSDNode>(LD1)->isVolatile() && 3680 !cast<LoadSDNode>(LD2)->isVolatile() && 3681 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3682 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3683 unsigned Align = LD->getAlignment(); 3684 unsigned NewAlign = TLI.getTargetData()-> 3685 getABITypeAlignment(VT.getTypeForMVT()); 3686 3687 if (NewAlign <= Align && 3688 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3689 return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(), 3690 LD->getSrcValue(), LD->getSrcValueOffset(), 3691 false, Align); 3692 } 3693 3694 return SDValue(); 3695} 3696 3697SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3698 SDValue N0 = N->getOperand(0); 3699 MVT VT = N->getValueType(0); 3700 3701 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3702 // Only do this before legalize, since afterward the target may be depending 3703 // on the bitconvert. 3704 // First check to see if this is all constant. 3705 if (!LegalTypes && 3706 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3707 VT.isVector()) { 3708 bool isSimple = true; 3709 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3710 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3711 N0.getOperand(i).getOpcode() != ISD::Constant && 3712 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3713 isSimple = false; 3714 break; 3715 } 3716 3717 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3718 assert(!DestEltVT.isVector() && 3719 "Element type of vector ValueType must not be vector!"); 3720 if (isSimple) 3721 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3722 } 3723 3724 // If the input is a constant, let getNode fold it. 3725 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3726 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3727 if (Res.getNode() != N) return Res; 3728 } 3729 3730 // (conv (conv x, t1), t2) -> (conv x, t2) 3731 if (N0.getOpcode() == ISD::BIT_CONVERT) 3732 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3733 N0.getOperand(0)); 3734 3735 // fold (conv (load x)) -> (load (conv*)x) 3736 // If the resultant load doesn't need a higher alignment than the original! 3737 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3738 // Do not change the width of a volatile load. 3739 !cast<LoadSDNode>(N0)->isVolatile() && 3740 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3741 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3742 unsigned Align = TLI.getTargetData()-> 3743 getABITypeAlignment(VT.getTypeForMVT()); 3744 unsigned OrigAlign = LN0->getAlignment(); 3745 3746 if (Align <= OrigAlign) { 3747 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3748 LN0->getBasePtr(), 3749 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3750 LN0->isVolatile(), OrigAlign); 3751 AddToWorkList(N); 3752 CombineTo(N0.getNode(), 3753 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3754 N0.getValueType(), Load), 3755 Load.getValue(1)); 3756 return Load; 3757 } 3758 } 3759 3760 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3761 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3762 // This often reduces constant pool loads. 3763 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3764 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3765 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3766 N0.getOperand(0)); 3767 AddToWorkList(NewConv.getNode()); 3768 3769 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3770 if (N0.getOpcode() == ISD::FNEG) 3771 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3772 NewConv, DAG.getConstant(SignBit, VT)); 3773 assert(N0.getOpcode() == ISD::FABS); 3774 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3775 NewConv, DAG.getConstant(~SignBit, VT)); 3776 } 3777 3778 // fold (bitconvert (fcopysign cst, x)) -> 3779 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3780 // Note that we don't handle (copysign x, cst) because this can always be 3781 // folded to an fneg or fabs. 3782 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3783 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3784 VT.isInteger() && !VT.isVector()) { 3785 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3786 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3787 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3788 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3789 IntXVT, N0.getOperand(1)); 3790 AddToWorkList(X.getNode()); 3791 3792 // If X has a different width than the result/lhs, sext it or truncate it. 3793 unsigned VTWidth = VT.getSizeInBits(); 3794 if (OrigXWidth < VTWidth) { 3795 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3796 AddToWorkList(X.getNode()); 3797 } else if (OrigXWidth > VTWidth) { 3798 // To get the sign bit in the right place, we have to shift it right 3799 // before truncating. 3800 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3801 X.getValueType(), X, 3802 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3803 AddToWorkList(X.getNode()); 3804 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3805 AddToWorkList(X.getNode()); 3806 } 3807 3808 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3809 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3810 X, DAG.getConstant(SignBit, VT)); 3811 AddToWorkList(X.getNode()); 3812 3813 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3814 VT, N0.getOperand(0)); 3815 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3816 Cst, DAG.getConstant(~SignBit, VT)); 3817 AddToWorkList(Cst.getNode()); 3818 3819 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3820 } 3821 } 3822 3823 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3824 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3825 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3826 if (CombineLD.getNode()) 3827 return CombineLD; 3828 } 3829 3830 return SDValue(); 3831} 3832 3833SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3834 MVT VT = N->getValueType(0); 3835 return CombineConsecutiveLoads(N, VT); 3836} 3837 3838/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3839/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3840/// destination element value type. 3841SDValue DAGCombiner:: 3842ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3843 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3844 3845 // If this is already the right type, we're done. 3846 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3847 3848 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3849 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3850 3851 // If this is a conversion of N elements of one type to N elements of another 3852 // type, convert each element. This handles FP<->INT cases. 3853 if (SrcBitSize == DstBitSize) { 3854 SmallVector<SDValue, 8> Ops; 3855 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3856 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3857 DstEltVT, BV->getOperand(i))); 3858 AddToWorkList(Ops.back().getNode()); 3859 } 3860 MVT VT = MVT::getVectorVT(DstEltVT, 3861 BV->getValueType(0).getVectorNumElements()); 3862 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3863 &Ops[0], Ops.size()); 3864 } 3865 3866 // Otherwise, we're growing or shrinking the elements. To avoid having to 3867 // handle annoying details of growing/shrinking FP values, we convert them to 3868 // int first. 3869 if (SrcEltVT.isFloatingPoint()) { 3870 // Convert the input float vector to a int vector where the elements are the 3871 // same sizes. 3872 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3873 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3874 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3875 SrcEltVT = IntVT; 3876 } 3877 3878 // Now we know the input is an integer vector. If the output is a FP type, 3879 // convert to integer first, then to FP of the right size. 3880 if (DstEltVT.isFloatingPoint()) { 3881 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3882 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3883 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3884 3885 // Next, convert to FP elements of the same size. 3886 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3887 } 3888 3889 // Okay, we know the src/dst types are both integers of differing types. 3890 // Handling growing first. 3891 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3892 if (SrcBitSize < DstBitSize) { 3893 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3894 3895 SmallVector<SDValue, 8> Ops; 3896 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3897 i += NumInputsPerOutput) { 3898 bool isLE = TLI.isLittleEndian(); 3899 APInt NewBits = APInt(DstBitSize, 0); 3900 bool EltIsUndef = true; 3901 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3902 // Shift the previously computed bits over. 3903 NewBits <<= SrcBitSize; 3904 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3905 if (Op.getOpcode() == ISD::UNDEF) continue; 3906 EltIsUndef = false; 3907 3908 NewBits |= 3909 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3910 } 3911 3912 if (EltIsUndef) 3913 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3914 else 3915 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3916 } 3917 3918 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3919 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3920 &Ops[0], Ops.size()); 3921 } 3922 3923 // Finally, this must be the case where we are shrinking elements: each input 3924 // turns into multiple outputs. 3925 bool isS2V = ISD::isScalarToVector(BV); 3926 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3927 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3928 SmallVector<SDValue, 8> Ops; 3929 3930 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3931 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3932 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3933 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3934 continue; 3935 } 3936 3937 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3938 3939 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3940 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3941 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3942 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3943 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3944 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3945 Ops[0]); 3946 OpVal = OpVal.lshr(DstBitSize); 3947 } 3948 3949 // For big endian targets, swap the order of the pieces of each element. 3950 if (TLI.isBigEndian()) 3951 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3952 } 3953 3954 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3955 &Ops[0], Ops.size()); 3956} 3957 3958SDValue DAGCombiner::visitFADD(SDNode *N) { 3959 SDValue N0 = N->getOperand(0); 3960 SDValue N1 = N->getOperand(1); 3961 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3962 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3963 MVT VT = N->getValueType(0); 3964 3965 // fold vector ops 3966 if (VT.isVector()) { 3967 SDValue FoldedVOp = SimplifyVBinOp(N); 3968 if (FoldedVOp.getNode()) return FoldedVOp; 3969 } 3970 3971 // fold (fadd c1, c2) -> (fadd c1, c2) 3972 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3973 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3974 // canonicalize constant to RHS 3975 if (N0CFP && !N1CFP) 3976 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3977 // fold (fadd A, 0) -> A 3978 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3979 return N0; 3980 // fold (fadd A, (fneg B)) -> (fsub A, B) 3981 if (isNegatibleForFree(N1, LegalOperations) == 2) 3982 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3983 GetNegatedExpression(N1, DAG, LegalOperations)); 3984 // fold (fadd (fneg A), B) -> (fsub B, A) 3985 if (isNegatibleForFree(N0, LegalOperations) == 2) 3986 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3987 GetNegatedExpression(N0, DAG, LegalOperations)); 3988 3989 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3990 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3991 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3992 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3993 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3994 N0.getOperand(1), N1)); 3995 3996 return SDValue(); 3997} 3998 3999SDValue DAGCombiner::visitFSUB(SDNode *N) { 4000 SDValue N0 = N->getOperand(0); 4001 SDValue N1 = N->getOperand(1); 4002 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4003 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4004 MVT VT = N->getValueType(0); 4005 4006 // fold vector ops 4007 if (VT.isVector()) { 4008 SDValue FoldedVOp = SimplifyVBinOp(N); 4009 if (FoldedVOp.getNode()) return FoldedVOp; 4010 } 4011 4012 // fold (fsub c1, c2) -> c1-c2 4013 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4014 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4015 // fold (fsub A, 0) -> A 4016 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4017 return N0; 4018 // fold (fsub 0, B) -> -B 4019 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4020 if (isNegatibleForFree(N1, LegalOperations)) 4021 return GetNegatedExpression(N1, DAG, LegalOperations); 4022 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4023 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4024 } 4025 // fold (fsub A, (fneg B)) -> (fadd A, B) 4026 if (isNegatibleForFree(N1, LegalOperations)) 4027 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4028 GetNegatedExpression(N1, DAG, LegalOperations)); 4029 4030 return SDValue(); 4031} 4032 4033SDValue DAGCombiner::visitFMUL(SDNode *N) { 4034 SDValue N0 = N->getOperand(0); 4035 SDValue N1 = N->getOperand(1); 4036 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4037 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4038 MVT VT = N->getValueType(0); 4039 4040 // fold vector ops 4041 if (VT.isVector()) { 4042 SDValue FoldedVOp = SimplifyVBinOp(N); 4043 if (FoldedVOp.getNode()) return FoldedVOp; 4044 } 4045 4046 // fold (fmul c1, c2) -> c1*c2 4047 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4048 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4049 // canonicalize constant to RHS 4050 if (N0CFP && !N1CFP) 4051 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4052 // fold (fmul A, 0) -> 0 4053 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4054 return N1; 4055 // fold (fmul X, 2.0) -> (fadd X, X) 4056 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4057 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4058 // fold (fmul X, (fneg 1.0)) -> (fneg X) 4059 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4060 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4061 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4062 4063 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4064 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4065 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4066 // Both can be negated for free, check to see if at least one is cheaper 4067 // negated. 4068 if (LHSNeg == 2 || RHSNeg == 2) 4069 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4070 GetNegatedExpression(N0, DAG, LegalOperations), 4071 GetNegatedExpression(N1, DAG, LegalOperations)); 4072 } 4073 } 4074 4075 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4076 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4077 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4078 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4079 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4080 N0.getOperand(1), N1)); 4081 4082 return SDValue(); 4083} 4084 4085SDValue DAGCombiner::visitFDIV(SDNode *N) { 4086 SDValue N0 = N->getOperand(0); 4087 SDValue N1 = N->getOperand(1); 4088 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4089 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4090 MVT VT = N->getValueType(0); 4091 4092 // fold vector ops 4093 if (VT.isVector()) { 4094 SDValue FoldedVOp = SimplifyVBinOp(N); 4095 if (FoldedVOp.getNode()) return FoldedVOp; 4096 } 4097 4098 // fold (fdiv c1, c2) -> c1/c2 4099 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4100 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4101 4102 4103 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4104 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4105 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4106 // Both can be negated for free, check to see if at least one is cheaper 4107 // negated. 4108 if (LHSNeg == 2 || RHSNeg == 2) 4109 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4110 GetNegatedExpression(N0, DAG, LegalOperations), 4111 GetNegatedExpression(N1, DAG, LegalOperations)); 4112 } 4113 } 4114 4115 return SDValue(); 4116} 4117 4118SDValue DAGCombiner::visitFREM(SDNode *N) { 4119 SDValue N0 = N->getOperand(0); 4120 SDValue N1 = N->getOperand(1); 4121 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4122 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4123 MVT VT = N->getValueType(0); 4124 4125 // fold (frem c1, c2) -> fmod(c1,c2) 4126 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4127 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4128 4129 return SDValue(); 4130} 4131 4132SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4133 SDValue N0 = N->getOperand(0); 4134 SDValue N1 = N->getOperand(1); 4135 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4136 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4137 MVT VT = N->getValueType(0); 4138 4139 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4140 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4141 4142 if (N1CFP) { 4143 const APFloat& V = N1CFP->getValueAPF(); 4144 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4145 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4146 if (!V.isNegative()) { 4147 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4148 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4149 } else { 4150 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4151 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4152 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4153 } 4154 } 4155 4156 // copysign(fabs(x), y) -> copysign(x, y) 4157 // copysign(fneg(x), y) -> copysign(x, y) 4158 // copysign(copysign(x,z), y) -> copysign(x, y) 4159 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4160 N0.getOpcode() == ISD::FCOPYSIGN) 4161 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4162 N0.getOperand(0), N1); 4163 4164 // copysign(x, abs(y)) -> abs(x) 4165 if (N1.getOpcode() == ISD::FABS) 4166 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4167 4168 // copysign(x, copysign(y,z)) -> copysign(x, z) 4169 if (N1.getOpcode() == ISD::FCOPYSIGN) 4170 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4171 N0, N1.getOperand(1)); 4172 4173 // copysign(x, fp_extend(y)) -> copysign(x, y) 4174 // copysign(x, fp_round(y)) -> copysign(x, y) 4175 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4176 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4177 N0, N1.getOperand(0)); 4178 4179 return SDValue(); 4180} 4181 4182SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4183 SDValue N0 = N->getOperand(0); 4184 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4185 MVT VT = N->getValueType(0); 4186 MVT OpVT = N0.getValueType(); 4187 4188 // fold (sint_to_fp c1) -> c1fp 4189 if (N0C && OpVT != MVT::ppcf128) 4190 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4191 4192 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4193 // but UINT_TO_FP is legal on this target, try to convert. 4194 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4195 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4196 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4197 if (DAG.SignBitIsZero(N0)) 4198 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4199 } 4200 4201 return SDValue(); 4202} 4203 4204SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4205 SDValue N0 = N->getOperand(0); 4206 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4207 MVT VT = N->getValueType(0); 4208 MVT OpVT = N0.getValueType(); 4209 4210 // fold (uint_to_fp c1) -> c1fp 4211 if (N0C && OpVT != MVT::ppcf128) 4212 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4213 4214 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4215 // but SINT_TO_FP is legal on this target, try to convert. 4216 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4217 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4218 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4219 if (DAG.SignBitIsZero(N0)) 4220 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4221 } 4222 4223 return SDValue(); 4224} 4225 4226SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4227 SDValue N0 = N->getOperand(0); 4228 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4229 MVT VT = N->getValueType(0); 4230 4231 // fold (fp_to_sint c1fp) -> c1 4232 if (N0CFP) 4233 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4234 4235 return SDValue(); 4236} 4237 4238SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4239 SDValue N0 = N->getOperand(0); 4240 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4241 MVT VT = N->getValueType(0); 4242 4243 // fold (fp_to_uint c1fp) -> c1 4244 if (N0CFP && VT != MVT::ppcf128) 4245 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4246 4247 return SDValue(); 4248} 4249 4250SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4251 SDValue N0 = N->getOperand(0); 4252 SDValue N1 = N->getOperand(1); 4253 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4254 MVT VT = N->getValueType(0); 4255 4256 // fold (fp_round c1fp) -> c1fp 4257 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4258 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4259 4260 // fold (fp_round (fp_extend x)) -> x 4261 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4262 return N0.getOperand(0); 4263 4264 // fold (fp_round (fp_round x)) -> (fp_round x) 4265 if (N0.getOpcode() == ISD::FP_ROUND) { 4266 // This is a value preserving truncation if both round's are. 4267 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4268 N0.getNode()->getConstantOperandVal(1) == 1; 4269 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4270 DAG.getIntPtrConstant(IsTrunc)); 4271 } 4272 4273 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4274 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4275 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4276 N0.getOperand(0), N1); 4277 AddToWorkList(Tmp.getNode()); 4278 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4279 Tmp, N0.getOperand(1)); 4280 } 4281 4282 return SDValue(); 4283} 4284 4285SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4286 SDValue N0 = N->getOperand(0); 4287 MVT VT = N->getValueType(0); 4288 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4289 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4290 4291 // fold (fp_round_inreg c1fp) -> c1fp 4292 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4293 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4294 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4295 } 4296 4297 return SDValue(); 4298} 4299 4300SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4301 SDValue N0 = N->getOperand(0); 4302 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4303 MVT VT = N->getValueType(0); 4304 4305 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4306 if (N->hasOneUse() && 4307 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4308 return SDValue(); 4309 4310 // fold (fp_extend c1fp) -> c1fp 4311 if (N0CFP && VT != MVT::ppcf128) 4312 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4313 4314 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4315 // value of X. 4316 if (N0.getOpcode() == ISD::FP_ROUND 4317 && N0.getNode()->getConstantOperandVal(1) == 1) { 4318 SDValue In = N0.getOperand(0); 4319 if (In.getValueType() == VT) return In; 4320 if (VT.bitsLT(In.getValueType())) 4321 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4322 In, N0.getOperand(1)); 4323 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4324 } 4325 4326 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4327 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4328 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4329 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4330 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4331 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4332 LN0->getChain(), 4333 LN0->getBasePtr(), LN0->getSrcValue(), 4334 LN0->getSrcValueOffset(), 4335 N0.getValueType(), 4336 LN0->isVolatile(), LN0->getAlignment()); 4337 CombineTo(N, ExtLoad); 4338 CombineTo(N0.getNode(), 4339 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4340 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4341 ExtLoad.getValue(1)); 4342 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4343 } 4344 4345 return SDValue(); 4346} 4347 4348SDValue DAGCombiner::visitFNEG(SDNode *N) { 4349 SDValue N0 = N->getOperand(0); 4350 4351 if (isNegatibleForFree(N0, LegalOperations)) 4352 return GetNegatedExpression(N0, DAG, LegalOperations); 4353 4354 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4355 // constant pool values. 4356 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4357 N0.getOperand(0).getValueType().isInteger() && 4358 !N0.getOperand(0).getValueType().isVector()) { 4359 SDValue Int = N0.getOperand(0); 4360 MVT IntVT = Int.getValueType(); 4361 if (IntVT.isInteger() && !IntVT.isVector()) { 4362 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4363 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4364 AddToWorkList(Int.getNode()); 4365 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4366 N->getValueType(0), Int); 4367 } 4368 } 4369 4370 return SDValue(); 4371} 4372 4373SDValue DAGCombiner::visitFABS(SDNode *N) { 4374 SDValue N0 = N->getOperand(0); 4375 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4376 MVT VT = N->getValueType(0); 4377 4378 // fold (fabs c1) -> fabs(c1) 4379 if (N0CFP && VT != MVT::ppcf128) 4380 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4381 // fold (fabs (fabs x)) -> (fabs x) 4382 if (N0.getOpcode() == ISD::FABS) 4383 return N->getOperand(0); 4384 // fold (fabs (fneg x)) -> (fabs x) 4385 // fold (fabs (fcopysign x, y)) -> (fabs x) 4386 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4387 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4388 4389 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4390 // constant pool values. 4391 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4392 N0.getOperand(0).getValueType().isInteger() && 4393 !N0.getOperand(0).getValueType().isVector()) { 4394 SDValue Int = N0.getOperand(0); 4395 MVT IntVT = Int.getValueType(); 4396 if (IntVT.isInteger() && !IntVT.isVector()) { 4397 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4398 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4399 AddToWorkList(Int.getNode()); 4400 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4401 N->getValueType(0), Int); 4402 } 4403 } 4404 4405 return SDValue(); 4406} 4407 4408SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4409 SDValue Chain = N->getOperand(0); 4410 SDValue N1 = N->getOperand(1); 4411 SDValue N2 = N->getOperand(2); 4412 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4413 4414 // never taken branch, fold to chain 4415 if (N1C && N1C->isNullValue()) 4416 return Chain; 4417 // unconditional branch 4418 if (N1C && N1C->getAPIntValue() == 1) 4419 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4420 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4421 // on the target. 4422 if (N1.getOpcode() == ISD::SETCC && 4423 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4424 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4425 Chain, N1.getOperand(2), 4426 N1.getOperand(0), N1.getOperand(1), N2); 4427 } 4428 4429 return SDValue(); 4430} 4431 4432// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4433// 4434SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4435 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4436 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4437 4438 // Use SimplifySetCC to simplify SETCC's. 4439 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4440 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4441 false); 4442 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4443 4444 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4445 4446 // fold br_cc true, dest -> br dest (unconditional branch) 4447 if (SCCC && !SCCC->isNullValue()) 4448 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4449 N->getOperand(0), N->getOperand(4)); 4450 // fold br_cc false, dest -> unconditional fall through 4451 if (SCCC && SCCC->isNullValue()) 4452 return N->getOperand(0); 4453 4454 // fold to a simpler setcc 4455 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4456 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4457 N->getOperand(0), Simp.getOperand(2), 4458 Simp.getOperand(0), Simp.getOperand(1), 4459 N->getOperand(4)); 4460 4461 return SDValue(); 4462} 4463 4464/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4465/// pre-indexed load / store when the base pointer is an add or subtract 4466/// and it has other uses besides the load / store. After the 4467/// transformation, the new indexed load / store has effectively folded 4468/// the add / subtract in and all of its other uses are redirected to the 4469/// new load / store. 4470bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4471 if (!LegalOperations) 4472 return false; 4473 4474 bool isLoad = true; 4475 SDValue Ptr; 4476 MVT VT; 4477 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4478 if (LD->isIndexed()) 4479 return false; 4480 VT = LD->getMemoryVT(); 4481 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4482 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4483 return false; 4484 Ptr = LD->getBasePtr(); 4485 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4486 if (ST->isIndexed()) 4487 return false; 4488 VT = ST->getMemoryVT(); 4489 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4490 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4491 return false; 4492 Ptr = ST->getBasePtr(); 4493 isLoad = false; 4494 } else { 4495 return false; 4496 } 4497 4498 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4499 // out. There is no reason to make this a preinc/predec. 4500 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4501 Ptr.getNode()->hasOneUse()) 4502 return false; 4503 4504 // Ask the target to do addressing mode selection. 4505 SDValue BasePtr; 4506 SDValue Offset; 4507 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4508 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4509 return false; 4510 // Don't create a indexed load / store with zero offset. 4511 if (isa<ConstantSDNode>(Offset) && 4512 cast<ConstantSDNode>(Offset)->isNullValue()) 4513 return false; 4514 4515 // Try turning it into a pre-indexed load / store except when: 4516 // 1) The new base ptr is a frame index. 4517 // 2) If N is a store and the new base ptr is either the same as or is a 4518 // predecessor of the value being stored. 4519 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4520 // that would create a cycle. 4521 // 4) All uses are load / store ops that use it as old base ptr. 4522 4523 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4524 // (plus the implicit offset) to a register to preinc anyway. 4525 if (isa<FrameIndexSDNode>(BasePtr)) 4526 return false; 4527 4528 // Check #2. 4529 if (!isLoad) { 4530 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4531 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4532 return false; 4533 } 4534 4535 // Now check for #3 and #4. 4536 bool RealUse = false; 4537 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4538 E = Ptr.getNode()->use_end(); I != E; ++I) { 4539 SDNode *Use = *I; 4540 if (Use == N) 4541 continue; 4542 if (Use->isPredecessorOf(N)) 4543 return false; 4544 4545 if (!((Use->getOpcode() == ISD::LOAD && 4546 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4547 (Use->getOpcode() == ISD::STORE && 4548 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4549 RealUse = true; 4550 } 4551 4552 if (!RealUse) 4553 return false; 4554 4555 SDValue Result; 4556 if (isLoad) 4557 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4558 BasePtr, Offset, AM); 4559 else 4560 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4561 BasePtr, Offset, AM); 4562 ++PreIndexedNodes; 4563 ++NodesCombined; 4564 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4565 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4566 DOUT << '\n'; 4567 WorkListRemover DeadNodes(*this); 4568 if (isLoad) { 4569 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4570 &DeadNodes); 4571 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4572 &DeadNodes); 4573 } else { 4574 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4575 &DeadNodes); 4576 } 4577 4578 // Finally, since the node is now dead, remove it from the graph. 4579 DAG.DeleteNode(N); 4580 4581 // Replace the uses of Ptr with uses of the updated base value. 4582 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4583 &DeadNodes); 4584 removeFromWorkList(Ptr.getNode()); 4585 DAG.DeleteNode(Ptr.getNode()); 4586 4587 return true; 4588} 4589 4590/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4591/// add / sub of the base pointer node into a post-indexed load / store. 4592/// The transformation folded the add / subtract into the new indexed 4593/// load / store effectively and all of its uses are redirected to the 4594/// new load / store. 4595bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4596 if (!LegalOperations) 4597 return false; 4598 4599 bool isLoad = true; 4600 SDValue Ptr; 4601 MVT VT; 4602 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4603 if (LD->isIndexed()) 4604 return false; 4605 VT = LD->getMemoryVT(); 4606 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4607 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4608 return false; 4609 Ptr = LD->getBasePtr(); 4610 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4611 if (ST->isIndexed()) 4612 return false; 4613 VT = ST->getMemoryVT(); 4614 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4615 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4616 return false; 4617 Ptr = ST->getBasePtr(); 4618 isLoad = false; 4619 } else { 4620 return false; 4621 } 4622 4623 if (Ptr.getNode()->hasOneUse()) 4624 return false; 4625 4626 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4627 E = Ptr.getNode()->use_end(); I != E; ++I) { 4628 SDNode *Op = *I; 4629 if (Op == N || 4630 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4631 continue; 4632 4633 SDValue BasePtr; 4634 SDValue Offset; 4635 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4636 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4637 if (Ptr == Offset) 4638 std::swap(BasePtr, Offset); 4639 if (Ptr != BasePtr) 4640 continue; 4641 // Don't create a indexed load / store with zero offset. 4642 if (isa<ConstantSDNode>(Offset) && 4643 cast<ConstantSDNode>(Offset)->isNullValue()) 4644 continue; 4645 4646 // Try turning it into a post-indexed load / store except when 4647 // 1) All uses are load / store ops that use it as base ptr. 4648 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4649 // nor a successor of N. Otherwise, if Op is folded that would 4650 // create a cycle. 4651 4652 // Check for #1. 4653 bool TryNext = false; 4654 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4655 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4656 SDNode *Use = *II; 4657 if (Use == Ptr.getNode()) 4658 continue; 4659 4660 // If all the uses are load / store addresses, then don't do the 4661 // transformation. 4662 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4663 bool RealUse = false; 4664 for (SDNode::use_iterator III = Use->use_begin(), 4665 EEE = Use->use_end(); III != EEE; ++III) { 4666 SDNode *UseUse = *III; 4667 if (!((UseUse->getOpcode() == ISD::LOAD && 4668 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4669 (UseUse->getOpcode() == ISD::STORE && 4670 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4671 RealUse = true; 4672 } 4673 4674 if (!RealUse) { 4675 TryNext = true; 4676 break; 4677 } 4678 } 4679 } 4680 4681 if (TryNext) 4682 continue; 4683 4684 // Check for #2 4685 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4686 SDValue Result = isLoad 4687 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4688 BasePtr, Offset, AM) 4689 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4690 BasePtr, Offset, AM); 4691 ++PostIndexedNodes; 4692 ++NodesCombined; 4693 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4694 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4695 DOUT << '\n'; 4696 WorkListRemover DeadNodes(*this); 4697 if (isLoad) { 4698 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4699 &DeadNodes); 4700 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4701 &DeadNodes); 4702 } else { 4703 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4704 &DeadNodes); 4705 } 4706 4707 // Finally, since the node is now dead, remove it from the graph. 4708 DAG.DeleteNode(N); 4709 4710 // Replace the uses of Use with uses of the updated base value. 4711 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4712 Result.getValue(isLoad ? 1 : 0), 4713 &DeadNodes); 4714 removeFromWorkList(Op); 4715 DAG.DeleteNode(Op); 4716 return true; 4717 } 4718 } 4719 } 4720 4721 return false; 4722} 4723 4724/// InferAlignment - If we can infer some alignment information from this 4725/// pointer, return it. 4726static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4727 // If this is a direct reference to a stack slot, use information about the 4728 // stack slot's alignment. 4729 int FrameIdx = 1 << 31; 4730 int64_t FrameOffset = 0; 4731 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4732 FrameIdx = FI->getIndex(); 4733 } else if (Ptr.getOpcode() == ISD::ADD && 4734 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4735 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4736 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4737 FrameOffset = Ptr.getConstantOperandVal(1); 4738 } 4739 4740 if (FrameIdx != (1 << 31)) { 4741 // FIXME: Handle FI+CST. 4742 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4743 if (MFI.isFixedObjectIndex(FrameIdx)) { 4744 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4745 4746 // The alignment of the frame index can be determined from its offset from 4747 // the incoming frame position. If the frame object is at offset 32 and 4748 // the stack is guaranteed to be 16-byte aligned, then we know that the 4749 // object is 16-byte aligned. 4750 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4751 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4752 4753 // Finally, the frame object itself may have a known alignment. Factor 4754 // the alignment + offset into a new alignment. For example, if we know 4755 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4756 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4757 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4758 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4759 FrameOffset); 4760 return std::max(Align, FIInfoAlign); 4761 } 4762 } 4763 4764 return 0; 4765} 4766 4767SDValue DAGCombiner::visitLOAD(SDNode *N) { 4768 LoadSDNode *LD = cast<LoadSDNode>(N); 4769 SDValue Chain = LD->getChain(); 4770 SDValue Ptr = LD->getBasePtr(); 4771 4772 // Try to infer better alignment information than the load already has. 4773 if (!Fast && LD->isUnindexed()) { 4774 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4775 if (Align > LD->getAlignment()) 4776 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4777 LD->getValueType(0), 4778 Chain, Ptr, LD->getSrcValue(), 4779 LD->getSrcValueOffset(), LD->getMemoryVT(), 4780 LD->isVolatile(), Align); 4781 } 4782 } 4783 4784 // If load is not volatile and there are no uses of the loaded value (and 4785 // the updated indexed value in case of indexed loads), change uses of the 4786 // chain value into uses of the chain input (i.e. delete the dead load). 4787 if (!LD->isVolatile()) { 4788 if (N->getValueType(1) == MVT::Other) { 4789 // Unindexed loads. 4790 if (N->hasNUsesOfValue(0, 0)) { 4791 // It's not safe to use the two value CombineTo variant here. e.g. 4792 // v1, chain2 = load chain1, loc 4793 // v2, chain3 = load chain2, loc 4794 // v3 = add v2, c 4795 // Now we replace use of chain2 with chain1. This makes the second load 4796 // isomorphic to the one we are deleting, and thus makes this load live. 4797 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4798 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4799 DOUT << "\n"; 4800 WorkListRemover DeadNodes(*this); 4801 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4802 4803 if (N->use_empty()) { 4804 removeFromWorkList(N); 4805 DAG.DeleteNode(N); 4806 } 4807 4808 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4809 } 4810 } else { 4811 // Indexed loads. 4812 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4813 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4814 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4815 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4816 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4817 DOUT << " and 2 other values\n"; 4818 WorkListRemover DeadNodes(*this); 4819 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4820 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4821 DAG.getUNDEF(N->getValueType(1)), 4822 &DeadNodes); 4823 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4824 removeFromWorkList(N); 4825 DAG.DeleteNode(N); 4826 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4827 } 4828 } 4829 } 4830 4831 // If this load is directly stored, replace the load value with the stored 4832 // value. 4833 // TODO: Handle store large -> read small portion. 4834 // TODO: Handle TRUNCSTORE/LOADEXT 4835 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4836 !LD->isVolatile()) { 4837 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4838 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4839 if (PrevST->getBasePtr() == Ptr && 4840 PrevST->getValue().getValueType() == N->getValueType(0)) 4841 return CombineTo(N, Chain.getOperand(1), Chain); 4842 } 4843 } 4844 4845 if (CombinerAA) { 4846 // Walk up chain skipping non-aliasing memory nodes. 4847 SDValue BetterChain = FindBetterChain(N, Chain); 4848 4849 // If there is a better chain. 4850 if (Chain != BetterChain) { 4851 SDValue ReplLoad; 4852 4853 // Replace the chain to void dependency. 4854 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4855 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4856 BetterChain, Ptr, 4857 LD->getSrcValue(), LD->getSrcValueOffset(), 4858 LD->isVolatile(), LD->getAlignment()); 4859 } else { 4860 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4861 LD->getValueType(0), 4862 BetterChain, Ptr, LD->getSrcValue(), 4863 LD->getSrcValueOffset(), 4864 LD->getMemoryVT(), 4865 LD->isVolatile(), 4866 LD->getAlignment()); 4867 } 4868 4869 // Create token factor to keep old chain connected. 4870 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4871 MVT::Other, Chain, ReplLoad.getValue(1)); 4872 4873 // Replace uses with load result and token factor. Don't add users 4874 // to work list. 4875 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4876 } 4877 } 4878 4879 // Try transforming N to an indexed load. 4880 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4881 return SDValue(N, 0); 4882 4883 return SDValue(); 4884} 4885 4886SDValue DAGCombiner::visitSTORE(SDNode *N) { 4887 StoreSDNode *ST = cast<StoreSDNode>(N); 4888 SDValue Chain = ST->getChain(); 4889 SDValue Value = ST->getValue(); 4890 SDValue Ptr = ST->getBasePtr(); 4891 4892 // Try to infer better alignment information than the store already has. 4893 if (!Fast && ST->isUnindexed()) { 4894 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4895 if (Align > ST->getAlignment()) 4896 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 4897 Ptr, ST->getSrcValue(), 4898 ST->getSrcValueOffset(), ST->getMemoryVT(), 4899 ST->isVolatile(), Align); 4900 } 4901 } 4902 4903 // If this is a store of a bit convert, store the input value if the 4904 // resultant store does not need a higher alignment than the original. 4905 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4906 ST->isUnindexed()) { 4907 unsigned OrigAlign = ST->getAlignment(); 4908 MVT SVT = Value.getOperand(0).getValueType(); 4909 unsigned Align = TLI.getTargetData()-> 4910 getABITypeAlignment(SVT.getTypeForMVT()); 4911 if (Align <= OrigAlign && 4912 ((!LegalOperations && !ST->isVolatile()) || 4913 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 4914 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 4915 Ptr, ST->getSrcValue(), 4916 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4917 } 4918 4919 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4920 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4921 // NOTE: If the original store is volatile, this transform must not increase 4922 // the number of stores. For example, on x86-32 an f64 can be stored in one 4923 // processor operation but an i64 (which is not legal) requires two. So the 4924 // transform should not be done in this case. 4925 if (Value.getOpcode() != ISD::TargetConstantFP) { 4926 SDValue Tmp; 4927 switch (CFP->getValueType(0).getSimpleVT()) { 4928 default: assert(0 && "Unknown FP type"); 4929 case MVT::f80: // We don't do this for these yet. 4930 case MVT::f128: 4931 case MVT::ppcf128: 4932 break; 4933 case MVT::f32: 4934 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 4935 !ST->isVolatile()) || 4936 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4937 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4938 bitcastToAPInt().getZExtValue(), MVT::i32); 4939 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 4940 Ptr, ST->getSrcValue(), 4941 ST->getSrcValueOffset(), ST->isVolatile(), 4942 ST->getAlignment()); 4943 } 4944 break; 4945 case MVT::f64: 4946 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 4947 !ST->isVolatile()) || 4948 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 4949 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4950 getZExtValue(), MVT::i64); 4951 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 4952 Ptr, ST->getSrcValue(), 4953 ST->getSrcValueOffset(), ST->isVolatile(), 4954 ST->getAlignment()); 4955 } else if (!ST->isVolatile() && 4956 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4957 // Many FP stores are not made apparent until after legalize, e.g. for 4958 // argument passing. Since this is so common, custom legalize the 4959 // 64-bit integer store into two 32-bit stores. 4960 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4961 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4962 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4963 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4964 4965 int SVOffset = ST->getSrcValueOffset(); 4966 unsigned Alignment = ST->getAlignment(); 4967 bool isVolatile = ST->isVolatile(); 4968 4969 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 4970 Ptr, ST->getSrcValue(), 4971 ST->getSrcValueOffset(), 4972 isVolatile, ST->getAlignment()); 4973 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 4974 DAG.getConstant(4, Ptr.getValueType())); 4975 SVOffset += 4; 4976 Alignment = MinAlign(Alignment, 4U); 4977 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 4978 Ptr, ST->getSrcValue(), 4979 SVOffset, isVolatile, Alignment); 4980 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 4981 St0, St1); 4982 } 4983 4984 break; 4985 } 4986 } 4987 } 4988 4989 if (CombinerAA) { 4990 // Walk up chain skipping non-aliasing memory nodes. 4991 SDValue BetterChain = FindBetterChain(N, Chain); 4992 4993 // If there is a better chain. 4994 if (Chain != BetterChain) { 4995 // Replace the chain to avoid dependency. 4996 SDValue ReplStore; 4997 if (ST->isTruncatingStore()) { 4998 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 4999 ST->getSrcValue(),ST->getSrcValueOffset(), 5000 ST->getMemoryVT(), 5001 ST->isVolatile(), ST->getAlignment()); 5002 } else { 5003 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5004 ST->getSrcValue(), ST->getSrcValueOffset(), 5005 ST->isVolatile(), ST->getAlignment()); 5006 } 5007 5008 // Create token to keep both nodes around. 5009 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5010 MVT::Other, Chain, ReplStore); 5011 5012 // Don't add users to work list. 5013 return CombineTo(N, Token, false); 5014 } 5015 } 5016 5017 // Try transforming N to an indexed store. 5018 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5019 return SDValue(N, 0); 5020 5021 // FIXME: is there such a thing as a truncating indexed store? 5022 if (ST->isTruncatingStore() && ST->isUnindexed() && 5023 Value.getValueType().isInteger()) { 5024 // See if we can simplify the input to this truncstore with knowledge that 5025 // only the low bits are being used. For example: 5026 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5027 SDValue Shorter = 5028 GetDemandedBits(Value, 5029 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5030 ST->getMemoryVT().getSizeInBits())); 5031 AddToWorkList(Value.getNode()); 5032 if (Shorter.getNode()) 5033 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5034 Ptr, ST->getSrcValue(), 5035 ST->getSrcValueOffset(), ST->getMemoryVT(), 5036 ST->isVolatile(), ST->getAlignment()); 5037 5038 // Otherwise, see if we can simplify the operation with 5039 // SimplifyDemandedBits, which only works if the value has a single use. 5040 if (SimplifyDemandedBits(Value, 5041 APInt::getLowBitsSet( 5042 Value.getValueSizeInBits(), 5043 ST->getMemoryVT().getSizeInBits()))) 5044 return SDValue(N, 0); 5045 } 5046 5047 // If this is a load followed by a store to the same location, then the store 5048 // is dead/noop. 5049 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5050 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5051 ST->isUnindexed() && !ST->isVolatile() && 5052 // There can't be any side effects between the load and store, such as 5053 // a call or store. 5054 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5055 // The store is dead, remove it. 5056 return Chain; 5057 } 5058 } 5059 5060 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5061 // truncating store. We can do this even if this is already a truncstore. 5062 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5063 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5064 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5065 ST->getMemoryVT())) { 5066 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5067 Ptr, ST->getSrcValue(), 5068 ST->getSrcValueOffset(), ST->getMemoryVT(), 5069 ST->isVolatile(), ST->getAlignment()); 5070 } 5071 5072 return SDValue(); 5073} 5074 5075SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5076 SDValue InVec = N->getOperand(0); 5077 SDValue InVal = N->getOperand(1); 5078 SDValue EltNo = N->getOperand(2); 5079 5080 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5081 // vector with the inserted element. 5082 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5083 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5084 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5085 InVec.getNode()->op_end()); 5086 if (Elt < Ops.size()) 5087 Ops[Elt] = InVal; 5088 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5089 InVec.getValueType(), &Ops[0], Ops.size()); 5090 } 5091 5092 return SDValue(); 5093} 5094 5095SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5096 // (vextract (scalar_to_vector val, 0) -> val 5097 SDValue InVec = N->getOperand(0); 5098 5099 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) 5100 return InVec.getOperand(0); 5101 5102 // Perform only after legalization to ensure build_vector / vector_shuffle 5103 // optimizations have already been done. 5104 if (!LegalOperations) return SDValue(); 5105 5106 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5107 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5108 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5109 SDValue EltNo = N->getOperand(1); 5110 5111 if (isa<ConstantSDNode>(EltNo)) { 5112 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5113 bool NewLoad = false; 5114 bool BCNumEltsChanged = false; 5115 MVT VT = InVec.getValueType(); 5116 MVT EVT = VT.getVectorElementType(); 5117 MVT LVT = EVT; 5118 5119 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5120 MVT BCVT = InVec.getOperand(0).getValueType(); 5121 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5122 return SDValue(); 5123 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5124 BCNumEltsChanged = true; 5125 InVec = InVec.getOperand(0); 5126 EVT = BCVT.getVectorElementType(); 5127 NewLoad = true; 5128 } 5129 5130 LoadSDNode *LN0 = NULL; 5131 if (ISD::isNormalLoad(InVec.getNode())) { 5132 LN0 = cast<LoadSDNode>(InVec); 5133 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5134 InVec.getOperand(0).getValueType() == EVT && 5135 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5136 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5137 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 5138 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5139 // => 5140 // (load $addr+1*size) 5141 5142 // If the bit convert changed the number of elements, it is unsafe 5143 // to examine the mask. 5144 if (BCNumEltsChanged) 5145 return SDValue(); 5146 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 5147 getOperand(Elt))->getZExtValue(); 5148 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 5149 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5150 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5151 InVec = InVec.getOperand(0); 5152 if (ISD::isNormalLoad(InVec.getNode())) { 5153 LN0 = cast<LoadSDNode>(InVec); 5154 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 5155 } 5156 } 5157 5158 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5159 return SDValue(); 5160 5161 unsigned Align = LN0->getAlignment(); 5162 if (NewLoad) { 5163 // Check the resultant load doesn't need a higher alignment than the 5164 // original load. 5165 unsigned NewAlign = 5166 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); 5167 5168 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5169 return SDValue(); 5170 5171 Align = NewAlign; 5172 } 5173 5174 SDValue NewPtr = LN0->getBasePtr(); 5175 if (Elt) { 5176 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5177 MVT PtrType = NewPtr.getValueType(); 5178 if (TLI.isBigEndian()) 5179 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5180 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5181 DAG.getConstant(PtrOff, PtrType)); 5182 } 5183 5184 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5185 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5186 LN0->isVolatile(), Align); 5187 } 5188 5189 return SDValue(); 5190} 5191 5192SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5193 unsigned NumInScalars = N->getNumOperands(); 5194 MVT VT = N->getValueType(0); 5195 unsigned NumElts = VT.getVectorNumElements(); 5196 MVT EltType = VT.getVectorElementType(); 5197 5198 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5199 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5200 // at most two distinct vectors, turn this into a shuffle node. 5201 SDValue VecIn1, VecIn2; 5202 for (unsigned i = 0; i != NumInScalars; ++i) { 5203 // Ignore undef inputs. 5204 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5205 5206 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5207 // constant index, bail out. 5208 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5209 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5210 VecIn1 = VecIn2 = SDValue(0, 0); 5211 break; 5212 } 5213 5214 // If the input vector type disagrees with the result of the build_vector, 5215 // we can't make a shuffle. 5216 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5217 if (ExtractedFromVec.getValueType() != VT) { 5218 VecIn1 = VecIn2 = SDValue(0, 0); 5219 break; 5220 } 5221 5222 // Otherwise, remember this. We allow up to two distinct input vectors. 5223 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5224 continue; 5225 5226 if (VecIn1.getNode() == 0) { 5227 VecIn1 = ExtractedFromVec; 5228 } else if (VecIn2.getNode() == 0) { 5229 VecIn2 = ExtractedFromVec; 5230 } else { 5231 // Too many inputs. 5232 VecIn1 = VecIn2 = SDValue(0, 0); 5233 break; 5234 } 5235 } 5236 5237 // If everything is good, we can make a shuffle operation. 5238 if (VecIn1.getNode()) { 5239 SmallVector<SDValue, 8> BuildVecIndices; 5240 for (unsigned i = 0; i != NumInScalars; ++i) { 5241 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5242 BuildVecIndices.push_back(DAG.getUNDEF(TLI.getPointerTy())); 5243 continue; 5244 } 5245 5246 SDValue Extract = N->getOperand(i); 5247 5248 // If extracting from the first vector, just use the index directly. 5249 if (Extract.getOperand(0) == VecIn1) { 5250 BuildVecIndices.push_back(Extract.getOperand(1)); 5251 continue; 5252 } 5253 5254 // Otherwise, use InIdx + VecSize 5255 unsigned Idx = 5256 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 5257 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 5258 } 5259 5260 // Add count and size info. 5261 MVT IndexVT = MVT::getIntegerVT(EltType.getSizeInBits()); 5262 MVT BuildVecVT = MVT::getVectorVT(IndexVT, NumElts); 5263 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes) 5264 return SDValue(); 5265 5266 // Return the new VECTOR_SHUFFLE node. 5267 SDValue Ops[5]; 5268 Ops[0] = VecIn1; 5269 if (VecIn2.getNode()) { 5270 Ops[1] = VecIn2; 5271 } else { 5272 // Use an undef build_vector as input for the second operand. 5273 std::vector<SDValue> UnOps(NumInScalars, 5274 DAG.getUNDEF(EltType)); 5275 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5276 &UnOps[0], UnOps.size()); 5277 AddToWorkList(Ops[1].getNode()); 5278 } 5279 5280 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), BuildVecVT, 5281 &BuildVecIndices[0], BuildVecIndices.size()); 5282 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3); 5283 } 5284 5285 return SDValue(); 5286} 5287 5288SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5289 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5290 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5291 // inputs come from at most two distinct vectors, turn this into a shuffle 5292 // node. 5293 5294 // If we only have one input vector, we don't need to do any concatenation. 5295 if (N->getNumOperands() == 1) 5296 return N->getOperand(0); 5297 5298 return SDValue(); 5299} 5300 5301SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5302 SDValue ShufMask = N->getOperand(2); 5303 unsigned NumElts = ShufMask.getNumOperands(); 5304 5305 SDValue N0 = N->getOperand(0); 5306 SDValue N1 = N->getOperand(1); 5307 5308 assert(N0.getValueType().getVectorNumElements() == NumElts && 5309 "Vector shuffle must be normalized in DAG"); 5310 5311 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5312 bool isIdentity = true; 5313 for (unsigned i = 0; i != NumElts; ++i) { 5314 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5315 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5316 isIdentity = false; 5317 break; 5318 } 5319 } 5320 if (isIdentity) return N->getOperand(0); 5321 5322 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5323 isIdentity = true; 5324 for (unsigned i = 0; i != NumElts; ++i) { 5325 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5326 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5327 i+NumElts) { 5328 isIdentity = false; 5329 break; 5330 } 5331 } 5332 if (isIdentity) return N->getOperand(1); 5333 5334 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5335 // needed at all. 5336 bool isUnary = true; 5337 bool isSplat = true; 5338 int VecNum = -1; 5339 unsigned BaseIdx = 0; 5340 for (unsigned i = 0; i != NumElts; ++i) 5341 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5342 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5343 int V = (Idx < NumElts) ? 0 : 1; 5344 if (VecNum == -1) { 5345 VecNum = V; 5346 BaseIdx = Idx; 5347 } else { 5348 if (BaseIdx != Idx) 5349 isSplat = false; 5350 if (VecNum != V) { 5351 isUnary = false; 5352 break; 5353 } 5354 } 5355 } 5356 5357 // Normalize unary shuffle so the RHS is undef. 5358 if (isUnary && VecNum == 1) 5359 std::swap(N0, N1); 5360 5361 // If it is a splat, check if the argument vector is a build_vector with 5362 // all scalar elements the same. 5363 if (isSplat) { 5364 SDNode *V = N0.getNode(); 5365 5366 // If this is a bit convert that changes the element type of the vector but 5367 // not the number of vector elements, look through it. Be careful not to 5368 // look though conversions that change things like v4f32 to v2f64. 5369 if (V->getOpcode() == ISD::BIT_CONVERT) { 5370 SDValue ConvInput = V->getOperand(0); 5371 if (ConvInput.getValueType().isVector() && 5372 ConvInput.getValueType().getVectorNumElements() == NumElts) 5373 V = ConvInput.getNode(); 5374 } 5375 5376 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5377 unsigned NumElems = V->getNumOperands(); 5378 if (NumElems > BaseIdx) { 5379 SDValue Base; 5380 bool AllSame = true; 5381 for (unsigned i = 0; i != NumElems; ++i) { 5382 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5383 Base = V->getOperand(i); 5384 break; 5385 } 5386 } 5387 // Splat of <u, u, u, u>, return <u, u, u, u> 5388 if (!Base.getNode()) 5389 return N0; 5390 for (unsigned i = 0; i != NumElems; ++i) { 5391 if (V->getOperand(i) != Base) { 5392 AllSame = false; 5393 break; 5394 } 5395 } 5396 // Splat of <x, x, x, x>, return <x, x, x, x> 5397 if (AllSame) 5398 return N0; 5399 } 5400 } 5401 } 5402 5403 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5404 // into an undef. 5405 if (isUnary || N0 == N1) { 5406 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5407 // first operand. 5408 SmallVector<SDValue, 8> MappedOps; 5409 5410 for (unsigned i = 0; i != NumElts; ++i) { 5411 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5412 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5413 NumElts) { 5414 MappedOps.push_back(ShufMask.getOperand(i)); 5415 } else { 5416 unsigned NewIdx = 5417 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5418 NumElts; 5419 MappedOps.push_back(DAG.getConstant(NewIdx, 5420 ShufMask.getOperand(i).getValueType())); 5421 } 5422 } 5423 5424 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5425 ShufMask.getValueType(), 5426 &MappedOps[0], MappedOps.size()); 5427 AddToWorkList(ShufMask.getNode()); 5428 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), 5429 N->getValueType(0), N0, 5430 DAG.getUNDEF(N->getValueType(0)), 5431 ShufMask); 5432 } 5433 5434 return SDValue(); 5435} 5436 5437/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5438/// an AND to a vector_shuffle with the destination vector and a zero vector. 5439/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5440/// vector_shuffle V, Zero, <0, 4, 2, 4> 5441SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5442 SDValue LHS = N->getOperand(0); 5443 SDValue RHS = N->getOperand(1); 5444 if (N->getOpcode() == ISD::AND) { 5445 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5446 RHS = RHS.getOperand(0); 5447 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5448 std::vector<SDValue> IdxOps; 5449 unsigned NumOps = RHS.getNumOperands(); 5450 unsigned NumElts = NumOps; 5451 for (unsigned i = 0; i != NumElts; ++i) { 5452 SDValue Elt = RHS.getOperand(i); 5453 if (!isa<ConstantSDNode>(Elt)) 5454 return SDValue(); 5455 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5456 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5457 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5458 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5459 else 5460 return SDValue(); 5461 } 5462 5463 // Let's see if the target supports this vector_shuffle. 5464 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5465 return SDValue(); 5466 5467 // Return the new VECTOR_SHUFFLE node. 5468 MVT EVT = RHS.getValueType().getVectorElementType(); 5469 MVT VT = MVT::getVectorVT(EVT, NumElts); 5470 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5471 std::vector<SDValue> Ops; 5472 LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS); 5473 Ops.push_back(LHS); 5474 AddToWorkList(LHS.getNode()); 5475 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5476 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5477 VT, &ZeroOps[0], ZeroOps.size())); 5478 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5479 MaskVT, &IdxOps[0], IdxOps.size())); 5480 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), 5481 VT, &Ops[0], Ops.size()); 5482 5483 if (VT != N->getValueType(0)) 5484 Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5485 N->getValueType(0), Result); 5486 5487 return Result; 5488 } 5489 } 5490 5491 return SDValue(); 5492} 5493 5494/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5495SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5496 // After legalize, the target may be depending on adds and other 5497 // binary ops to provide legal ways to construct constants or other 5498 // things. Simplifying them may result in a loss of legality. 5499 if (LegalOperations) return SDValue(); 5500 5501 MVT VT = N->getValueType(0); 5502 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5503 5504 MVT EltType = VT.getVectorElementType(); 5505 SDValue LHS = N->getOperand(0); 5506 SDValue RHS = N->getOperand(1); 5507 SDValue Shuffle = XformToShuffleWithZero(N); 5508 if (Shuffle.getNode()) return Shuffle; 5509 5510 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5511 // this operation. 5512 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5513 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5514 SmallVector<SDValue, 8> Ops; 5515 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5516 SDValue LHSOp = LHS.getOperand(i); 5517 SDValue RHSOp = RHS.getOperand(i); 5518 // If these two elements can't be folded, bail out. 5519 if ((LHSOp.getOpcode() != ISD::UNDEF && 5520 LHSOp.getOpcode() != ISD::Constant && 5521 LHSOp.getOpcode() != ISD::ConstantFP) || 5522 (RHSOp.getOpcode() != ISD::UNDEF && 5523 RHSOp.getOpcode() != ISD::Constant && 5524 RHSOp.getOpcode() != ISD::ConstantFP)) 5525 break; 5526 5527 // Can't fold divide by zero. 5528 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5529 N->getOpcode() == ISD::FDIV) { 5530 if ((RHSOp.getOpcode() == ISD::Constant && 5531 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5532 (RHSOp.getOpcode() == ISD::ConstantFP && 5533 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5534 break; 5535 } 5536 5537 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5538 EltType, LHSOp, RHSOp)); 5539 AddToWorkList(Ops.back().getNode()); 5540 assert((Ops.back().getOpcode() == ISD::UNDEF || 5541 Ops.back().getOpcode() == ISD::Constant || 5542 Ops.back().getOpcode() == ISD::ConstantFP) && 5543 "Scalar binop didn't fold!"); 5544 } 5545 5546 if (Ops.size() == LHS.getNumOperands()) { 5547 MVT VT = LHS.getValueType(); 5548 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5549 &Ops[0], Ops.size()); 5550 } 5551 } 5552 5553 return SDValue(); 5554} 5555 5556SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5557 SDValue N1, SDValue N2){ 5558 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5559 5560 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5561 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5562 5563 // If we got a simplified select_cc node back from SimplifySelectCC, then 5564 // break it down into a new SETCC node, and a new SELECT node, and then return 5565 // the SELECT node, since we were called with a SELECT node. 5566 if (SCC.getNode()) { 5567 // Check to see if we got a select_cc back (to turn into setcc/select). 5568 // Otherwise, just return whatever node we got back, like fabs. 5569 if (SCC.getOpcode() == ISD::SELECT_CC) { 5570 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5571 N0.getValueType(), 5572 SCC.getOperand(0), SCC.getOperand(1), 5573 SCC.getOperand(4)); 5574 AddToWorkList(SETCC.getNode()); 5575 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5576 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5577 } 5578 5579 return SCC; 5580 } 5581 return SDValue(); 5582} 5583 5584/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5585/// are the two values being selected between, see if we can simplify the 5586/// select. Callers of this should assume that TheSelect is deleted if this 5587/// returns true. As such, they should return the appropriate thing (e.g. the 5588/// node) back to the top-level of the DAG combiner loop to avoid it being 5589/// looked at. 5590bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5591 SDValue RHS) { 5592 5593 // If this is a select from two identical things, try to pull the operation 5594 // through the select. 5595 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5596 // If this is a load and the token chain is identical, replace the select 5597 // of two loads with a load through a select of the address to load from. 5598 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5599 // constants have been dropped into the constant pool. 5600 if (LHS.getOpcode() == ISD::LOAD && 5601 // Do not let this transformation reduce the number of volatile loads. 5602 !cast<LoadSDNode>(LHS)->isVolatile() && 5603 !cast<LoadSDNode>(RHS)->isVolatile() && 5604 // Token chains must be identical. 5605 LHS.getOperand(0) == RHS.getOperand(0)) { 5606 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5607 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5608 5609 // If this is an EXTLOAD, the VT's must match. 5610 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5611 // FIXME: this conflates two src values, discarding one. This is not 5612 // the right thing to do, but nothing uses srcvalues now. When they do, 5613 // turn SrcValue into a list of locations. 5614 SDValue Addr; 5615 if (TheSelect->getOpcode() == ISD::SELECT) { 5616 // Check that the condition doesn't reach either load. If so, folding 5617 // this will induce a cycle into the DAG. 5618 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5619 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5620 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5621 LLD->getBasePtr().getValueType(), 5622 TheSelect->getOperand(0), LLD->getBasePtr(), 5623 RLD->getBasePtr()); 5624 } 5625 } else { 5626 // Check that the condition doesn't reach either load. If so, folding 5627 // this will induce a cycle into the DAG. 5628 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5629 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5630 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5631 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5632 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5633 LLD->getBasePtr().getValueType(), 5634 TheSelect->getOperand(0), 5635 TheSelect->getOperand(1), 5636 LLD->getBasePtr(), RLD->getBasePtr(), 5637 TheSelect->getOperand(4)); 5638 } 5639 } 5640 5641 if (Addr.getNode()) { 5642 SDValue Load; 5643 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5644 Load = DAG.getLoad(TheSelect->getValueType(0), 5645 TheSelect->getDebugLoc(), 5646 LLD->getChain(), 5647 Addr,LLD->getSrcValue(), 5648 LLD->getSrcValueOffset(), 5649 LLD->isVolatile(), 5650 LLD->getAlignment()); 5651 } else { 5652 Load = DAG.getExtLoad(LLD->getExtensionType(), 5653 TheSelect->getDebugLoc(), 5654 TheSelect->getValueType(0), 5655 LLD->getChain(), Addr, LLD->getSrcValue(), 5656 LLD->getSrcValueOffset(), 5657 LLD->getMemoryVT(), 5658 LLD->isVolatile(), 5659 LLD->getAlignment()); 5660 } 5661 5662 // Users of the select now use the result of the load. 5663 CombineTo(TheSelect, Load); 5664 5665 // Users of the old loads now use the new load's chain. We know the 5666 // old-load value is dead now. 5667 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5668 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5669 return true; 5670 } 5671 } 5672 } 5673 } 5674 5675 return false; 5676} 5677 5678SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5679 SDValue N2, SDValue N3, 5680 ISD::CondCode CC, bool NotExtCompare) { 5681 MVT VT = N2.getValueType(); 5682 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5683 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5684 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5685 5686 // Determine if the condition we're dealing with is constant 5687 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5688 N0, N1, CC, DL, false); 5689 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5690 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5691 5692 // fold select_cc true, x, y -> x 5693 if (SCCC && !SCCC->isNullValue()) 5694 return N2; 5695 // fold select_cc false, x, y -> y 5696 if (SCCC && SCCC->isNullValue()) 5697 return N3; 5698 5699 // Check to see if we can simplify the select into an fabs node 5700 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5701 // Allow either -0.0 or 0.0 5702 if (CFP->getValueAPF().isZero()) { 5703 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5704 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5705 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5706 N2 == N3.getOperand(0)) 5707 return DAG.getNode(ISD::FABS, DL, VT, N0); 5708 5709 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5710 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5711 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5712 N2.getOperand(0) == N3) 5713 return DAG.getNode(ISD::FABS, DL, VT, N3); 5714 } 5715 } 5716 5717 // Check to see if we can perform the "gzip trick", transforming 5718 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5719 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5720 N0.getValueType().isInteger() && 5721 N2.getValueType().isInteger() && 5722 (N1C->isNullValue() || // (a < 0) ? b : 0 5723 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5724 MVT XType = N0.getValueType(); 5725 MVT AType = N2.getValueType(); 5726 if (XType.bitsGE(AType)) { 5727 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5728 // single-bit constant. 5729 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5730 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5731 ShCtV = XType.getSizeInBits()-ShCtV-1; 5732 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5733 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5734 XType, N0, ShCt); 5735 AddToWorkList(Shift.getNode()); 5736 5737 if (XType.bitsGT(AType)) { 5738 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5739 AddToWorkList(Shift.getNode()); 5740 } 5741 5742 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5743 } 5744 5745 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5746 XType, N0, 5747 DAG.getConstant(XType.getSizeInBits()-1, 5748 getShiftAmountTy())); 5749 AddToWorkList(Shift.getNode()); 5750 5751 if (XType.bitsGT(AType)) { 5752 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5753 AddToWorkList(Shift.getNode()); 5754 } 5755 5756 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5757 } 5758 } 5759 5760 // fold select C, 16, 0 -> shl C, 4 5761 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5762 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5763 5764 // If the caller doesn't want us to simplify this into a zext of a compare, 5765 // don't do it. 5766 if (NotExtCompare && N2C->getAPIntValue() == 1) 5767 return SDValue(); 5768 5769 // Get a SetCC of the condition 5770 // FIXME: Should probably make sure that setcc is legal if we ever have a 5771 // target where it isn't. 5772 SDValue Temp, SCC; 5773 // cast from setcc result type to select result type 5774 if (LegalTypes) { 5775 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5776 N0, N1, CC); 5777 if (N2.getValueType().bitsLT(SCC.getValueType())) 5778 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5779 else 5780 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5781 N2.getValueType(), SCC); 5782 } else { 5783 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5784 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5785 N2.getValueType(), SCC); 5786 } 5787 5788 AddToWorkList(SCC.getNode()); 5789 AddToWorkList(Temp.getNode()); 5790 5791 if (N2C->getAPIntValue() == 1) 5792 return Temp; 5793 5794 // shl setcc result by log2 n2c 5795 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5796 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5797 getShiftAmountTy())); 5798 } 5799 5800 // Check to see if this is the equivalent of setcc 5801 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5802 // otherwise, go ahead with the folds. 5803 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5804 MVT XType = N0.getValueType(); 5805 if (!LegalOperations || 5806 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5807 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5808 if (Res.getValueType() != VT) 5809 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5810 return Res; 5811 } 5812 5813 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5814 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5815 (!LegalOperations || 5816 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5817 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5818 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5819 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5820 getShiftAmountTy())); 5821 } 5822 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5823 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5824 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5825 XType, DAG.getConstant(0, XType), N0); 5826 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5827 return DAG.getNode(ISD::SRL, DL, XType, 5828 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5829 DAG.getConstant(XType.getSizeInBits()-1, 5830 getShiftAmountTy())); 5831 } 5832 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5833 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5834 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5835 DAG.getConstant(XType.getSizeInBits()-1, 5836 getShiftAmountTy())); 5837 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5838 } 5839 } 5840 5841 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5842 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5843 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5844 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5845 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5846 MVT XType = N0.getValueType(); 5847 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5848 DAG.getConstant(XType.getSizeInBits()-1, 5849 getShiftAmountTy())); 5850 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5851 N0, Shift); 5852 AddToWorkList(Shift.getNode()); 5853 AddToWorkList(Add.getNode()); 5854 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5855 } 5856 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5857 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5858 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5859 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5860 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5861 MVT XType = N0.getValueType(); 5862 if (SubC->isNullValue() && XType.isInteger()) { 5863 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5864 N0, 5865 DAG.getConstant(XType.getSizeInBits()-1, 5866 getShiftAmountTy())); 5867 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 5868 XType, N0, Shift); 5869 AddToWorkList(Shift.getNode()); 5870 AddToWorkList(Add.getNode()); 5871 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5872 } 5873 } 5874 } 5875 5876 return SDValue(); 5877} 5878 5879/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5880SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5881 SDValue N1, ISD::CondCode Cond, 5882 DebugLoc DL, bool foldBooleans) { 5883 TargetLowering::DAGCombinerInfo 5884 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5885 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 5886} 5887 5888/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5889/// return a DAG expression to select that will generate the same value by 5890/// multiplying by a magic number. See: 5891/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5892SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5893 std::vector<SDNode*> Built; 5894 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5895 5896 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5897 ii != ee; ++ii) 5898 AddToWorkList(*ii); 5899 return S; 5900} 5901 5902/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5903/// return a DAG expression to select that will generate the same value by 5904/// multiplying by a magic number. See: 5905/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5906SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5907 std::vector<SDNode*> Built; 5908 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5909 5910 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5911 ii != ee; ++ii) 5912 AddToWorkList(*ii); 5913 return S; 5914} 5915 5916/// FindBaseOffset - Return true if base is known not to alias with anything 5917/// but itself. Provides base object and offset as results. 5918static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5919 // Assume it is a primitive operation. 5920 Base = Ptr; Offset = 0; 5921 5922 // If it's an adding a simple constant then integrate the offset. 5923 if (Base.getOpcode() == ISD::ADD) { 5924 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5925 Base = Base.getOperand(0); 5926 Offset += C->getZExtValue(); 5927 } 5928 } 5929 5930 // If it's any of the following then it can't alias with anything but itself. 5931 return isa<FrameIndexSDNode>(Base) || 5932 isa<ConstantPoolSDNode>(Base) || 5933 isa<GlobalAddressSDNode>(Base); 5934} 5935 5936/// isAlias - Return true if there is any possibility that the two addresses 5937/// overlap. 5938bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5939 const Value *SrcValue1, int SrcValueOffset1, 5940 SDValue Ptr2, int64_t Size2, 5941 const Value *SrcValue2, int SrcValueOffset2) const { 5942 // If they are the same then they must be aliases. 5943 if (Ptr1 == Ptr2) return true; 5944 5945 // Gather base node and offset information. 5946 SDValue Base1, Base2; 5947 int64_t Offset1, Offset2; 5948 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5949 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5950 5951 // If they have a same base address then... 5952 if (Base1 == Base2) 5953 // Check to see if the addresses overlap. 5954 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5955 5956 // If we know both bases then they can't alias. 5957 if (KnownBase1 && KnownBase2) return false; 5958 5959 if (CombinerGlobalAA) { 5960 // Use alias analysis information. 5961 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5962 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5963 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5964 AliasAnalysis::AliasResult AAResult = 5965 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5966 if (AAResult == AliasAnalysis::NoAlias) 5967 return false; 5968 } 5969 5970 // Otherwise we have to assume they alias. 5971 return true; 5972} 5973 5974/// FindAliasInfo - Extracts the relevant alias information from the memory 5975/// node. Returns true if the operand was a load. 5976bool DAGCombiner::FindAliasInfo(SDNode *N, 5977 SDValue &Ptr, int64_t &Size, 5978 const Value *&SrcValue, int &SrcValueOffset) const { 5979 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5980 Ptr = LD->getBasePtr(); 5981 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5982 SrcValue = LD->getSrcValue(); 5983 SrcValueOffset = LD->getSrcValueOffset(); 5984 return true; 5985 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5986 Ptr = ST->getBasePtr(); 5987 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5988 SrcValue = ST->getSrcValue(); 5989 SrcValueOffset = ST->getSrcValueOffset(); 5990 } else { 5991 assert(0 && "FindAliasInfo expected a memory operand"); 5992 } 5993 5994 return false; 5995} 5996 5997/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5998/// looking for aliasing nodes and adding them to the Aliases vector. 5999void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6000 SmallVector<SDValue, 8> &Aliases) { 6001 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6002 std::set<SDNode *> Visited; // Visited node set. 6003 6004 // Get alias information for node. 6005 SDValue Ptr; 6006 int64_t Size; 6007 const Value *SrcValue; 6008 int SrcValueOffset; 6009 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6010 6011 // Starting off. 6012 Chains.push_back(OriginalChain); 6013 6014 // Look at each chain and determine if it is an alias. If so, add it to the 6015 // aliases list. If not, then continue up the chain looking for the next 6016 // candidate. 6017 while (!Chains.empty()) { 6018 SDValue Chain = Chains.back(); 6019 Chains.pop_back(); 6020 6021 // Don't bother if we've been before. 6022 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6023 Visited.insert(Chain.getNode()); 6024 6025 switch (Chain.getOpcode()) { 6026 case ISD::EntryToken: 6027 // Entry token is ideal chain operand, but handled in FindBetterChain. 6028 break; 6029 6030 case ISD::LOAD: 6031 case ISD::STORE: { 6032 // Get alias information for Chain. 6033 SDValue OpPtr; 6034 int64_t OpSize; 6035 const Value *OpSrcValue; 6036 int OpSrcValueOffset; 6037 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6038 OpSrcValue, OpSrcValueOffset); 6039 6040 // If chain is alias then stop here. 6041 if (!(IsLoad && IsOpLoad) && 6042 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6043 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6044 Aliases.push_back(Chain); 6045 } else { 6046 // Look further up the chain. 6047 Chains.push_back(Chain.getOperand(0)); 6048 // Clean up old chain. 6049 AddToWorkList(Chain.getNode()); 6050 } 6051 break; 6052 } 6053 6054 case ISD::TokenFactor: 6055 // We have to check each of the operands of the token factor, so we queue 6056 // then up. Adding the operands to the queue (stack) in reverse order 6057 // maintains the original order and increases the likelihood that getNode 6058 // will find a matching token factor (CSE.) 6059 for (unsigned n = Chain.getNumOperands(); n;) 6060 Chains.push_back(Chain.getOperand(--n)); 6061 // Eliminate the token factor if we can. 6062 AddToWorkList(Chain.getNode()); 6063 break; 6064 6065 default: 6066 // For all other instructions we will just have to take what we can get. 6067 Aliases.push_back(Chain); 6068 break; 6069 } 6070 } 6071} 6072 6073/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6074/// for a better chain (aliasing node.) 6075SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6076 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6077 6078 // Accumulate all the aliases to this node. 6079 GatherAllAliases(N, OldChain, Aliases); 6080 6081 if (Aliases.size() == 0) { 6082 // If no operands then chain to entry token. 6083 return DAG.getEntryNode(); 6084 } else if (Aliases.size() == 1) { 6085 // If a single operand then chain to it. We don't need to revisit it. 6086 return Aliases[0]; 6087 } 6088 6089 // Construct a custom tailored token factor. 6090 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6091 &Aliases[0], Aliases.size()); 6092 6093 // Make sure the old chain gets cleaned up. 6094 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6095 6096 return NewChain; 6097} 6098 6099// SelectionDAG::Combine - This is the entry point for the file. 6100// 6101void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { 6102 /// run - This is the main entry point to this class. 6103 /// 6104 DAGCombiner(*this, AA, Fast).Run(Level); 6105} 6106