DAGCombiner.cpp revision 42febc6e9963f82d5c56c3c7e6afe5e00769af41
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include <algorithm> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 /// combine - call the node-specific routine that knows how to fold each 142 /// particular type of node. If that doesn't do anything, try the 143 /// target-specific DAG combines. 144 SDValue combine(SDNode *N); 145 146 // Visitation implementation - Implement dag node combining for different 147 // node types. The semantics are as follows: 148 // Return Value: 149 // SDValue.getNode() == 0 - No change was made 150 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151 // otherwise - N should be replaced by the returned Operand. 152 // 153 SDValue visitTokenFactor(SDNode *N); 154 SDValue visitMERGE_VALUES(SDNode *N); 155 SDValue visitADD(SDNode *N); 156 SDValue visitSUB(SDNode *N); 157 SDValue visitADDC(SDNode *N); 158 SDValue visitADDE(SDNode *N); 159 SDValue visitMUL(SDNode *N); 160 SDValue visitSDIV(SDNode *N); 161 SDValue visitUDIV(SDNode *N); 162 SDValue visitSREM(SDNode *N); 163 SDValue visitUREM(SDNode *N); 164 SDValue visitMULHU(SDNode *N); 165 SDValue visitMULHS(SDNode *N); 166 SDValue visitSMUL_LOHI(SDNode *N); 167 SDValue visitUMUL_LOHI(SDNode *N); 168 SDValue visitSDIVREM(SDNode *N); 169 SDValue visitUDIVREM(SDNode *N); 170 SDValue visitAND(SDNode *N); 171 SDValue visitOR(SDNode *N); 172 SDValue visitXOR(SDNode *N); 173 SDValue SimplifyVBinOp(SDNode *N); 174 SDValue visitSHL(SDNode *N); 175 SDValue visitSRA(SDNode *N); 176 SDValue visitSRL(SDNode *N); 177 SDValue visitCTLZ(SDNode *N); 178 SDValue visitCTTZ(SDNode *N); 179 SDValue visitCTPOP(SDNode *N); 180 SDValue visitSELECT(SDNode *N); 181 SDValue visitSELECT_CC(SDNode *N); 182 SDValue visitSETCC(SDNode *N); 183 SDValue visitSIGN_EXTEND(SDNode *N); 184 SDValue visitZERO_EXTEND(SDNode *N); 185 SDValue visitANY_EXTEND(SDNode *N); 186 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 187 SDValue visitTRUNCATE(SDNode *N); 188 SDValue visitBITCAST(SDNode *N); 189 SDValue visitBUILD_PAIR(SDNode *N); 190 SDValue visitFADD(SDNode *N); 191 SDValue visitFSUB(SDNode *N); 192 SDValue visitFMUL(SDNode *N); 193 SDValue visitFDIV(SDNode *N); 194 SDValue visitFREM(SDNode *N); 195 SDValue visitFCOPYSIGN(SDNode *N); 196 SDValue visitSINT_TO_FP(SDNode *N); 197 SDValue visitUINT_TO_FP(SDNode *N); 198 SDValue visitFP_TO_SINT(SDNode *N); 199 SDValue visitFP_TO_UINT(SDNode *N); 200 SDValue visitFP_ROUND(SDNode *N); 201 SDValue visitFP_ROUND_INREG(SDNode *N); 202 SDValue visitFP_EXTEND(SDNode *N); 203 SDValue visitFNEG(SDNode *N); 204 SDValue visitFABS(SDNode *N); 205 SDValue visitBRCOND(SDNode *N); 206 SDValue visitBR_CC(SDNode *N); 207 SDValue visitLOAD(SDNode *N); 208 SDValue visitSTORE(SDNode *N); 209 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 211 SDValue visitBUILD_VECTOR(SDNode *N); 212 SDValue visitCONCAT_VECTORS(SDNode *N); 213 SDValue visitVECTOR_SHUFFLE(SDNode *N); 214 SDValue visitMEMBARRIER(SDNode *N); 215 216 SDValue XformToShuffleWithZero(SDNode *N); 217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 218 219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 220 221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 225 SDValue N3, ISD::CondCode CC, 226 bool NotExtCompare = false); 227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 228 DebugLoc DL, bool foldBooleans = true); 229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 230 unsigned HiOp); 231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 232 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 233 SDValue BuildSDIV(SDNode *N); 234 SDValue BuildUDIV(SDNode *N); 235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 236 SDValue ReduceLoadWidth(SDNode *N); 237 SDValue ReduceLoadOpStoreWidth(SDNode *N); 238 SDValue TransformFPLoadStorePair(SDNode *N); 239 240 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 241 242 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 243 /// looking for aliasing nodes and adding them to the Aliases vector. 244 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 245 SmallVector<SDValue, 8> &Aliases); 246 247 /// isAlias - Return true if there is any possibility that the two addresses 248 /// overlap. 249 bool isAlias(SDValue Ptr1, int64_t Size1, 250 const Value *SrcValue1, int SrcValueOffset1, 251 unsigned SrcValueAlign1, 252 const MDNode *TBAAInfo1, 253 SDValue Ptr2, int64_t Size2, 254 const Value *SrcValue2, int SrcValueOffset2, 255 unsigned SrcValueAlign2, 256 const MDNode *TBAAInfo2) const; 257 258 /// FindAliasInfo - Extracts the relevant alias information from the memory 259 /// node. Returns true if the operand was a load. 260 bool FindAliasInfo(SDNode *N, 261 SDValue &Ptr, int64_t &Size, 262 const Value *&SrcValue, int &SrcValueOffset, 263 unsigned &SrcValueAlignment, 264 const MDNode *&TBAAInfo) const; 265 266 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 267 /// looking for a better chain (aliasing node.) 268 SDValue FindBetterChain(SDNode *N, SDValue Chain); 269 270 public: 271 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 272 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 273 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 274 275 /// Run - runs the dag combiner on all nodes in the work list 276 void Run(CombineLevel AtLevel); 277 278 SelectionDAG &getDAG() const { return DAG; } 279 280 /// getShiftAmountTy - Returns a type large enough to hold any valid 281 /// shift amount - before type legalization these can be huge. 282 EVT getShiftAmountTy(EVT LHSTy) { 283 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 284 } 285 286 /// isTypeLegal - This method returns true if we are running before type 287 /// legalization or if the specified VT is legal. 288 bool isTypeLegal(const EVT &VT) { 289 if (!LegalTypes) return true; 290 return TLI.isTypeLegal(VT); 291 } 292 }; 293} 294 295 296namespace { 297/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 298/// nodes from the worklist. 299class WorkListRemover : public SelectionDAG::DAGUpdateListener { 300 DAGCombiner &DC; 301public: 302 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 303 304 virtual void NodeDeleted(SDNode *N, SDNode *E) { 305 DC.removeFromWorkList(N); 306 } 307 308 virtual void NodeUpdated(SDNode *N) { 309 // Ignore updates. 310 } 311}; 312} 313 314//===----------------------------------------------------------------------===// 315// TargetLowering::DAGCombinerInfo implementation 316//===----------------------------------------------------------------------===// 317 318void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 319 ((DAGCombiner*)DC)->AddToWorkList(N); 320} 321 322void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 323 ((DAGCombiner*)DC)->removeFromWorkList(N); 324} 325 326SDValue TargetLowering::DAGCombinerInfo:: 327CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 328 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 329} 330 331SDValue TargetLowering::DAGCombinerInfo:: 332CombineTo(SDNode *N, SDValue Res, bool AddTo) { 333 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 334} 335 336 337SDValue TargetLowering::DAGCombinerInfo:: 338CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 339 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 340} 341 342void TargetLowering::DAGCombinerInfo:: 343CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 344 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 345} 346 347//===----------------------------------------------------------------------===// 348// Helper Functions 349//===----------------------------------------------------------------------===// 350 351/// isNegatibleForFree - Return 1 if we can compute the negated form of the 352/// specified expression for the same cost as the expression itself, or 2 if we 353/// can compute the negated form more cheaply than the expression itself. 354static char isNegatibleForFree(SDValue Op, bool LegalOperations, 355 unsigned Depth = 0) { 356 // No compile time optimizations on this type. 357 if (Op.getValueType() == MVT::ppcf128) 358 return 0; 359 360 // fneg is removable even if it has multiple uses. 361 if (Op.getOpcode() == ISD::FNEG) return 2; 362 363 // Don't allow anything with multiple uses. 364 if (!Op.hasOneUse()) return 0; 365 366 // Don't recurse exponentially. 367 if (Depth > 6) return 0; 368 369 switch (Op.getOpcode()) { 370 default: return false; 371 case ISD::ConstantFP: 372 // Don't invert constant FP values after legalize. The negated constant 373 // isn't necessarily legal. 374 return LegalOperations ? 0 : 1; 375 case ISD::FADD: 376 // FIXME: determine better conditions for this xform. 377 if (!UnsafeFPMath) return 0; 378 379 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 380 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 381 return V; 382 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 383 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 384 case ISD::FSUB: 385 // We can't turn -(A-B) into B-A when we honor signed zeros. 386 if (!UnsafeFPMath) return 0; 387 388 // fold (fneg (fsub A, B)) -> (fsub B, A) 389 return 1; 390 391 case ISD::FMUL: 392 case ISD::FDIV: 393 if (HonorSignDependentRoundingFPMath()) return 0; 394 395 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 396 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 397 return V; 398 399 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 400 401 case ISD::FP_EXTEND: 402 case ISD::FP_ROUND: 403 case ISD::FSIN: 404 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 405 } 406} 407 408/// GetNegatedExpression - If isNegatibleForFree returns true, this function 409/// returns the newly negated expression. 410static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 411 bool LegalOperations, unsigned Depth = 0) { 412 // fneg is removable even if it has multiple uses. 413 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 414 415 // Don't allow anything with multiple uses. 416 assert(Op.hasOneUse() && "Unknown reuse!"); 417 418 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 419 switch (Op.getOpcode()) { 420 default: llvm_unreachable("Unknown code"); 421 case ISD::ConstantFP: { 422 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 423 V.changeSign(); 424 return DAG.getConstantFP(V, Op.getValueType()); 425 } 426 case ISD::FADD: 427 // FIXME: determine better conditions for this xform. 428 assert(UnsafeFPMath); 429 430 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 431 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 432 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 433 GetNegatedExpression(Op.getOperand(0), DAG, 434 LegalOperations, Depth+1), 435 Op.getOperand(1)); 436 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 437 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(1), DAG, 439 LegalOperations, Depth+1), 440 Op.getOperand(0)); 441 case ISD::FSUB: 442 // We can't turn -(A-B) into B-A when we honor signed zeros. 443 assert(UnsafeFPMath); 444 445 // fold (fneg (fsub 0, B)) -> B 446 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 447 if (N0CFP->getValueAPF().isZero()) 448 return Op.getOperand(1); 449 450 // fold (fneg (fsub A, B)) -> (fsub B, A) 451 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 452 Op.getOperand(1), Op.getOperand(0)); 453 454 case ISD::FMUL: 455 case ISD::FDIV: 456 assert(!HonorSignDependentRoundingFPMath()); 457 458 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 459 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 460 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 461 GetNegatedExpression(Op.getOperand(0), DAG, 462 LegalOperations, Depth+1), 463 Op.getOperand(1)); 464 465 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 466 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 467 Op.getOperand(0), 468 GetNegatedExpression(Op.getOperand(1), DAG, 469 LegalOperations, Depth+1)); 470 471 case ISD::FP_EXTEND: 472 case ISD::FSIN: 473 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 474 GetNegatedExpression(Op.getOperand(0), DAG, 475 LegalOperations, Depth+1)); 476 case ISD::FP_ROUND: 477 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 478 GetNegatedExpression(Op.getOperand(0), DAG, 479 LegalOperations, Depth+1), 480 Op.getOperand(1)); 481 } 482} 483 484 485// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 486// that selects between the values 1 and 0, making it equivalent to a setcc. 487// Also, set the incoming LHS, RHS, and CC references to the appropriate 488// nodes based on the type of node we are checking. This simplifies life a 489// bit for the callers. 490static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 491 SDValue &CC) { 492 if (N.getOpcode() == ISD::SETCC) { 493 LHS = N.getOperand(0); 494 RHS = N.getOperand(1); 495 CC = N.getOperand(2); 496 return true; 497 } 498 if (N.getOpcode() == ISD::SELECT_CC && 499 N.getOperand(2).getOpcode() == ISD::Constant && 500 N.getOperand(3).getOpcode() == ISD::Constant && 501 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 502 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 503 LHS = N.getOperand(0); 504 RHS = N.getOperand(1); 505 CC = N.getOperand(4); 506 return true; 507 } 508 return false; 509} 510 511// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 512// one use. If this is true, it allows the users to invert the operation for 513// free when it is profitable to do so. 514static bool isOneUseSetCC(SDValue N) { 515 SDValue N0, N1, N2; 516 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 517 return true; 518 return false; 519} 520 521SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 522 SDValue N0, SDValue N1) { 523 EVT VT = N0.getValueType(); 524 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 525 if (isa<ConstantSDNode>(N1)) { 526 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 527 SDValue OpNode = 528 DAG.FoldConstantArithmetic(Opc, VT, 529 cast<ConstantSDNode>(N0.getOperand(1)), 530 cast<ConstantSDNode>(N1)); 531 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 532 } else if (N0.hasOneUse()) { 533 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 534 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 535 N0.getOperand(0), N1); 536 AddToWorkList(OpNode.getNode()); 537 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 538 } 539 } 540 541 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 542 if (isa<ConstantSDNode>(N0)) { 543 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 544 SDValue OpNode = 545 DAG.FoldConstantArithmetic(Opc, VT, 546 cast<ConstantSDNode>(N1.getOperand(1)), 547 cast<ConstantSDNode>(N0)); 548 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 549 } else if (N1.hasOneUse()) { 550 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 551 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 552 N1.getOperand(0), N0); 553 AddToWorkList(OpNode.getNode()); 554 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 555 } 556 } 557 558 return SDValue(); 559} 560 561SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 562 bool AddTo) { 563 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 564 ++NodesCombined; 565 DEBUG(dbgs() << "\nReplacing.1 "; 566 N->dump(&DAG); 567 dbgs() << "\nWith: "; 568 To[0].getNode()->dump(&DAG); 569 dbgs() << " and " << NumTo-1 << " other values\n"; 570 for (unsigned i = 0, e = NumTo; i != e; ++i) 571 assert((!To[i].getNode() || 572 N->getValueType(i) == To[i].getValueType()) && 573 "Cannot combine value to value of different type!")); 574 WorkListRemover DeadNodes(*this); 575 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 576 577 if (AddTo) { 578 // Push the new nodes and any users onto the worklist 579 for (unsigned i = 0, e = NumTo; i != e; ++i) { 580 if (To[i].getNode()) { 581 AddToWorkList(To[i].getNode()); 582 AddUsersToWorkList(To[i].getNode()); 583 } 584 } 585 } 586 587 // Finally, if the node is now dead, remove it from the graph. The node 588 // may not be dead if the replacement process recursively simplified to 589 // something else needing this node. 590 if (N->use_empty()) { 591 // Nodes can be reintroduced into the worklist. Make sure we do not 592 // process a node that has been replaced. 593 removeFromWorkList(N); 594 595 // Finally, since the node is now dead, remove it from the graph. 596 DAG.DeleteNode(N); 597 } 598 return SDValue(N, 0); 599} 600 601void DAGCombiner:: 602CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 603 // Replace all uses. If any nodes become isomorphic to other nodes and 604 // are deleted, make sure to remove them from our worklist. 605 WorkListRemover DeadNodes(*this); 606 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 607 608 // Push the new node and any (possibly new) users onto the worklist. 609 AddToWorkList(TLO.New.getNode()); 610 AddUsersToWorkList(TLO.New.getNode()); 611 612 // Finally, if the node is now dead, remove it from the graph. The node 613 // may not be dead if the replacement process recursively simplified to 614 // something else needing this node. 615 if (TLO.Old.getNode()->use_empty()) { 616 removeFromWorkList(TLO.Old.getNode()); 617 618 // If the operands of this node are only used by the node, they will now 619 // be dead. Make sure to visit them first to delete dead nodes early. 620 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 621 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 622 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 623 624 DAG.DeleteNode(TLO.Old.getNode()); 625 } 626} 627 628/// SimplifyDemandedBits - Check the specified integer node value to see if 629/// it can be simplified or if things it uses can be simplified by bit 630/// propagation. If so, return true. 631bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 632 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 633 APInt KnownZero, KnownOne; 634 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 635 return false; 636 637 // Revisit the node. 638 AddToWorkList(Op.getNode()); 639 640 // Replace the old value with the new one. 641 ++NodesCombined; 642 DEBUG(dbgs() << "\nReplacing.2 "; 643 TLO.Old.getNode()->dump(&DAG); 644 dbgs() << "\nWith: "; 645 TLO.New.getNode()->dump(&DAG); 646 dbgs() << '\n'); 647 648 CommitTargetLoweringOpt(TLO); 649 return true; 650} 651 652void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 653 DebugLoc dl = Load->getDebugLoc(); 654 EVT VT = Load->getValueType(0); 655 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 656 657 DEBUG(dbgs() << "\nReplacing.9 "; 658 Load->dump(&DAG); 659 dbgs() << "\nWith: "; 660 Trunc.getNode()->dump(&DAG); 661 dbgs() << '\n'); 662 WorkListRemover DeadNodes(*this); 663 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 664 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 665 &DeadNodes); 666 removeFromWorkList(Load); 667 DAG.DeleteNode(Load); 668 AddToWorkList(Trunc.getNode()); 669} 670 671SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 672 Replace = false; 673 DebugLoc dl = Op.getDebugLoc(); 674 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 675 EVT MemVT = LD->getMemoryVT(); 676 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 677 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 678 : ISD::EXTLOAD) 679 : LD->getExtensionType(); 680 Replace = true; 681 return DAG.getExtLoad(ExtType, dl, PVT, 682 LD->getChain(), LD->getBasePtr(), 683 LD->getPointerInfo(), 684 MemVT, LD->isVolatile(), 685 LD->isNonTemporal(), LD->getAlignment()); 686 } 687 688 unsigned Opc = Op.getOpcode(); 689 switch (Opc) { 690 default: break; 691 case ISD::AssertSext: 692 return DAG.getNode(ISD::AssertSext, dl, PVT, 693 SExtPromoteOperand(Op.getOperand(0), PVT), 694 Op.getOperand(1)); 695 case ISD::AssertZext: 696 return DAG.getNode(ISD::AssertZext, dl, PVT, 697 ZExtPromoteOperand(Op.getOperand(0), PVT), 698 Op.getOperand(1)); 699 case ISD::Constant: { 700 unsigned ExtOpc = 701 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 702 return DAG.getNode(ExtOpc, dl, PVT, Op); 703 } 704 } 705 706 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 707 return SDValue(); 708 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 709} 710 711SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 712 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 713 return SDValue(); 714 EVT OldVT = Op.getValueType(); 715 DebugLoc dl = Op.getDebugLoc(); 716 bool Replace = false; 717 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 718 if (NewOp.getNode() == 0) 719 return SDValue(); 720 AddToWorkList(NewOp.getNode()); 721 722 if (Replace) 723 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 724 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 725 DAG.getValueType(OldVT)); 726} 727 728SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 729 EVT OldVT = Op.getValueType(); 730 DebugLoc dl = Op.getDebugLoc(); 731 bool Replace = false; 732 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 733 if (NewOp.getNode() == 0) 734 return SDValue(); 735 AddToWorkList(NewOp.getNode()); 736 737 if (Replace) 738 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 739 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 740} 741 742/// PromoteIntBinOp - Promote the specified integer binary operation if the 743/// target indicates it is beneficial. e.g. On x86, it's usually better to 744/// promote i16 operations to i32 since i16 instructions are longer. 745SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 746 if (!LegalOperations) 747 return SDValue(); 748 749 EVT VT = Op.getValueType(); 750 if (VT.isVector() || !VT.isInteger()) 751 return SDValue(); 752 753 // If operation type is 'undesirable', e.g. i16 on x86, consider 754 // promoting it. 755 unsigned Opc = Op.getOpcode(); 756 if (TLI.isTypeDesirableForOp(Opc, VT)) 757 return SDValue(); 758 759 EVT PVT = VT; 760 // Consult target whether it is a good idea to promote this operation and 761 // what's the right type to promote it to. 762 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 763 assert(PVT != VT && "Don't know what type to promote to!"); 764 765 bool Replace0 = false; 766 SDValue N0 = Op.getOperand(0); 767 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 768 if (NN0.getNode() == 0) 769 return SDValue(); 770 771 bool Replace1 = false; 772 SDValue N1 = Op.getOperand(1); 773 SDValue NN1; 774 if (N0 == N1) 775 NN1 = NN0; 776 else { 777 NN1 = PromoteOperand(N1, PVT, Replace1); 778 if (NN1.getNode() == 0) 779 return SDValue(); 780 } 781 782 AddToWorkList(NN0.getNode()); 783 if (NN1.getNode()) 784 AddToWorkList(NN1.getNode()); 785 786 if (Replace0) 787 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 788 if (Replace1) 789 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 790 791 DEBUG(dbgs() << "\nPromoting "; 792 Op.getNode()->dump(&DAG)); 793 DebugLoc dl = Op.getDebugLoc(); 794 return DAG.getNode(ISD::TRUNCATE, dl, VT, 795 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 796 } 797 return SDValue(); 798} 799 800/// PromoteIntShiftOp - Promote the specified integer shift operation if the 801/// target indicates it is beneficial. e.g. On x86, it's usually better to 802/// promote i16 operations to i32 since i16 instructions are longer. 803SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 804 if (!LegalOperations) 805 return SDValue(); 806 807 EVT VT = Op.getValueType(); 808 if (VT.isVector() || !VT.isInteger()) 809 return SDValue(); 810 811 // If operation type is 'undesirable', e.g. i16 on x86, consider 812 // promoting it. 813 unsigned Opc = Op.getOpcode(); 814 if (TLI.isTypeDesirableForOp(Opc, VT)) 815 return SDValue(); 816 817 EVT PVT = VT; 818 // Consult target whether it is a good idea to promote this operation and 819 // what's the right type to promote it to. 820 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 821 assert(PVT != VT && "Don't know what type to promote to!"); 822 823 bool Replace = false; 824 SDValue N0 = Op.getOperand(0); 825 if (Opc == ISD::SRA) 826 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 827 else if (Opc == ISD::SRL) 828 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 829 else 830 N0 = PromoteOperand(N0, PVT, Replace); 831 if (N0.getNode() == 0) 832 return SDValue(); 833 834 AddToWorkList(N0.getNode()); 835 if (Replace) 836 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 837 838 DEBUG(dbgs() << "\nPromoting "; 839 Op.getNode()->dump(&DAG)); 840 DebugLoc dl = Op.getDebugLoc(); 841 return DAG.getNode(ISD::TRUNCATE, dl, VT, 842 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 843 } 844 return SDValue(); 845} 846 847SDValue DAGCombiner::PromoteExtend(SDValue Op) { 848 if (!LegalOperations) 849 return SDValue(); 850 851 EVT VT = Op.getValueType(); 852 if (VT.isVector() || !VT.isInteger()) 853 return SDValue(); 854 855 // If operation type is 'undesirable', e.g. i16 on x86, consider 856 // promoting it. 857 unsigned Opc = Op.getOpcode(); 858 if (TLI.isTypeDesirableForOp(Opc, VT)) 859 return SDValue(); 860 861 EVT PVT = VT; 862 // Consult target whether it is a good idea to promote this operation and 863 // what's the right type to promote it to. 864 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 865 assert(PVT != VT && "Don't know what type to promote to!"); 866 // fold (aext (aext x)) -> (aext x) 867 // fold (aext (zext x)) -> (zext x) 868 // fold (aext (sext x)) -> (sext x) 869 DEBUG(dbgs() << "\nPromoting "; 870 Op.getNode()->dump(&DAG)); 871 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 872 } 873 return SDValue(); 874} 875 876bool DAGCombiner::PromoteLoad(SDValue Op) { 877 if (!LegalOperations) 878 return false; 879 880 EVT VT = Op.getValueType(); 881 if (VT.isVector() || !VT.isInteger()) 882 return false; 883 884 // If operation type is 'undesirable', e.g. i16 on x86, consider 885 // promoting it. 886 unsigned Opc = Op.getOpcode(); 887 if (TLI.isTypeDesirableForOp(Opc, VT)) 888 return false; 889 890 EVT PVT = VT; 891 // Consult target whether it is a good idea to promote this operation and 892 // what's the right type to promote it to. 893 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 894 assert(PVT != VT && "Don't know what type to promote to!"); 895 896 DebugLoc dl = Op.getDebugLoc(); 897 SDNode *N = Op.getNode(); 898 LoadSDNode *LD = cast<LoadSDNode>(N); 899 EVT MemVT = LD->getMemoryVT(); 900 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 901 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 902 : ISD::EXTLOAD) 903 : LD->getExtensionType(); 904 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 905 LD->getChain(), LD->getBasePtr(), 906 LD->getPointerInfo(), 907 MemVT, LD->isVolatile(), 908 LD->isNonTemporal(), LD->getAlignment()); 909 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 910 911 DEBUG(dbgs() << "\nPromoting "; 912 N->dump(&DAG); 913 dbgs() << "\nTo: "; 914 Result.getNode()->dump(&DAG); 915 dbgs() << '\n'); 916 WorkListRemover DeadNodes(*this); 917 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 918 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 919 removeFromWorkList(N); 920 DAG.DeleteNode(N); 921 AddToWorkList(Result.getNode()); 922 return true; 923 } 924 return false; 925} 926 927 928//===----------------------------------------------------------------------===// 929// Main DAG Combiner implementation 930//===----------------------------------------------------------------------===// 931 932void DAGCombiner::Run(CombineLevel AtLevel) { 933 // set the instance variables, so that the various visit routines may use it. 934 Level = AtLevel; 935 LegalOperations = Level >= NoIllegalOperations; 936 LegalTypes = Level >= NoIllegalTypes; 937 938 // Add all the dag nodes to the worklist. 939 WorkList.reserve(DAG.allnodes_size()); 940 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 941 E = DAG.allnodes_end(); I != E; ++I) 942 WorkList.push_back(I); 943 944 // Create a dummy node (which is not added to allnodes), that adds a reference 945 // to the root node, preventing it from being deleted, and tracking any 946 // changes of the root. 947 HandleSDNode Dummy(DAG.getRoot()); 948 949 // The root of the dag may dangle to deleted nodes until the dag combiner is 950 // done. Set it to null to avoid confusion. 951 DAG.setRoot(SDValue()); 952 953 // while the worklist isn't empty, inspect the node on the end of it and 954 // try and combine it. 955 while (!WorkList.empty()) { 956 SDNode *N = WorkList.back(); 957 WorkList.pop_back(); 958 959 // If N has no uses, it is dead. Make sure to revisit all N's operands once 960 // N is deleted from the DAG, since they too may now be dead or may have a 961 // reduced number of uses, allowing other xforms. 962 if (N->use_empty() && N != &Dummy) { 963 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 964 AddToWorkList(N->getOperand(i).getNode()); 965 966 DAG.DeleteNode(N); 967 continue; 968 } 969 970 SDValue RV = combine(N); 971 972 if (RV.getNode() == 0) 973 continue; 974 975 ++NodesCombined; 976 977 // If we get back the same node we passed in, rather than a new node or 978 // zero, we know that the node must have defined multiple values and 979 // CombineTo was used. Since CombineTo takes care of the worklist 980 // mechanics for us, we have no work to do in this case. 981 if (RV.getNode() == N) 982 continue; 983 984 assert(N->getOpcode() != ISD::DELETED_NODE && 985 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 986 "Node was deleted but visit returned new node!"); 987 988 DEBUG(dbgs() << "\nReplacing.3 "; 989 N->dump(&DAG); 990 dbgs() << "\nWith: "; 991 RV.getNode()->dump(&DAG); 992 dbgs() << '\n'); 993 WorkListRemover DeadNodes(*this); 994 if (N->getNumValues() == RV.getNode()->getNumValues()) 995 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 996 else { 997 assert(N->getValueType(0) == RV.getValueType() && 998 N->getNumValues() == 1 && "Type mismatch"); 999 SDValue OpV = RV; 1000 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1001 } 1002 1003 // Push the new node and any users onto the worklist 1004 AddToWorkList(RV.getNode()); 1005 AddUsersToWorkList(RV.getNode()); 1006 1007 // Add any uses of the old node to the worklist in case this node is the 1008 // last one that uses them. They may become dead after this node is 1009 // deleted. 1010 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1011 AddToWorkList(N->getOperand(i).getNode()); 1012 1013 // Finally, if the node is now dead, remove it from the graph. The node 1014 // may not be dead if the replacement process recursively simplified to 1015 // something else needing this node. 1016 if (N->use_empty()) { 1017 // Nodes can be reintroduced into the worklist. Make sure we do not 1018 // process a node that has been replaced. 1019 removeFromWorkList(N); 1020 1021 // Finally, since the node is now dead, remove it from the graph. 1022 DAG.DeleteNode(N); 1023 } 1024 } 1025 1026 // If the root changed (e.g. it was a dead load, update the root). 1027 DAG.setRoot(Dummy.getValue()); 1028} 1029 1030SDValue DAGCombiner::visit(SDNode *N) { 1031 switch (N->getOpcode()) { 1032 default: break; 1033 case ISD::TokenFactor: return visitTokenFactor(N); 1034 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1035 case ISD::ADD: return visitADD(N); 1036 case ISD::SUB: return visitSUB(N); 1037 case ISD::ADDC: return visitADDC(N); 1038 case ISD::ADDE: return visitADDE(N); 1039 case ISD::MUL: return visitMUL(N); 1040 case ISD::SDIV: return visitSDIV(N); 1041 case ISD::UDIV: return visitUDIV(N); 1042 case ISD::SREM: return visitSREM(N); 1043 case ISD::UREM: return visitUREM(N); 1044 case ISD::MULHU: return visitMULHU(N); 1045 case ISD::MULHS: return visitMULHS(N); 1046 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1047 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1048 case ISD::SDIVREM: return visitSDIVREM(N); 1049 case ISD::UDIVREM: return visitUDIVREM(N); 1050 case ISD::AND: return visitAND(N); 1051 case ISD::OR: return visitOR(N); 1052 case ISD::XOR: return visitXOR(N); 1053 case ISD::SHL: return visitSHL(N); 1054 case ISD::SRA: return visitSRA(N); 1055 case ISD::SRL: return visitSRL(N); 1056 case ISD::CTLZ: return visitCTLZ(N); 1057 case ISD::CTTZ: return visitCTTZ(N); 1058 case ISD::CTPOP: return visitCTPOP(N); 1059 case ISD::SELECT: return visitSELECT(N); 1060 case ISD::SELECT_CC: return visitSELECT_CC(N); 1061 case ISD::SETCC: return visitSETCC(N); 1062 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1063 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1064 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1065 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1066 case ISD::TRUNCATE: return visitTRUNCATE(N); 1067 case ISD::BITCAST: return visitBITCAST(N); 1068 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1069 case ISD::FADD: return visitFADD(N); 1070 case ISD::FSUB: return visitFSUB(N); 1071 case ISD::FMUL: return visitFMUL(N); 1072 case ISD::FDIV: return visitFDIV(N); 1073 case ISD::FREM: return visitFREM(N); 1074 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1075 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1076 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1077 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1078 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1079 case ISD::FP_ROUND: return visitFP_ROUND(N); 1080 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1081 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1082 case ISD::FNEG: return visitFNEG(N); 1083 case ISD::FABS: return visitFABS(N); 1084 case ISD::BRCOND: return visitBRCOND(N); 1085 case ISD::BR_CC: return visitBR_CC(N); 1086 case ISD::LOAD: return visitLOAD(N); 1087 case ISD::STORE: return visitSTORE(N); 1088 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1089 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1090 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1091 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1092 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1093 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1094 } 1095 return SDValue(); 1096} 1097 1098SDValue DAGCombiner::combine(SDNode *N) { 1099 SDValue RV = visit(N); 1100 1101 // If nothing happened, try a target-specific DAG combine. 1102 if (RV.getNode() == 0) { 1103 assert(N->getOpcode() != ISD::DELETED_NODE && 1104 "Node was deleted but visit returned NULL!"); 1105 1106 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1107 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1108 1109 // Expose the DAG combiner to the target combiner impls. 1110 TargetLowering::DAGCombinerInfo 1111 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1112 1113 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1114 } 1115 } 1116 1117 // If nothing happened still, try promoting the operation. 1118 if (RV.getNode() == 0) { 1119 switch (N->getOpcode()) { 1120 default: break; 1121 case ISD::ADD: 1122 case ISD::SUB: 1123 case ISD::MUL: 1124 case ISD::AND: 1125 case ISD::OR: 1126 case ISD::XOR: 1127 RV = PromoteIntBinOp(SDValue(N, 0)); 1128 break; 1129 case ISD::SHL: 1130 case ISD::SRA: 1131 case ISD::SRL: 1132 RV = PromoteIntShiftOp(SDValue(N, 0)); 1133 break; 1134 case ISD::SIGN_EXTEND: 1135 case ISD::ZERO_EXTEND: 1136 case ISD::ANY_EXTEND: 1137 RV = PromoteExtend(SDValue(N, 0)); 1138 break; 1139 case ISD::LOAD: 1140 if (PromoteLoad(SDValue(N, 0))) 1141 RV = SDValue(N, 0); 1142 break; 1143 } 1144 } 1145 1146 // If N is a commutative binary node, try commuting it to enable more 1147 // sdisel CSE. 1148 if (RV.getNode() == 0 && 1149 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1150 N->getNumValues() == 1) { 1151 SDValue N0 = N->getOperand(0); 1152 SDValue N1 = N->getOperand(1); 1153 1154 // Constant operands are canonicalized to RHS. 1155 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1156 SDValue Ops[] = { N1, N0 }; 1157 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1158 Ops, 2); 1159 if (CSENode) 1160 return SDValue(CSENode, 0); 1161 } 1162 } 1163 1164 return RV; 1165} 1166 1167/// getInputChainForNode - Given a node, return its input chain if it has one, 1168/// otherwise return a null sd operand. 1169static SDValue getInputChainForNode(SDNode *N) { 1170 if (unsigned NumOps = N->getNumOperands()) { 1171 if (N->getOperand(0).getValueType() == MVT::Other) 1172 return N->getOperand(0); 1173 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1174 return N->getOperand(NumOps-1); 1175 for (unsigned i = 1; i < NumOps-1; ++i) 1176 if (N->getOperand(i).getValueType() == MVT::Other) 1177 return N->getOperand(i); 1178 } 1179 return SDValue(); 1180} 1181 1182SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1183 // If N has two operands, where one has an input chain equal to the other, 1184 // the 'other' chain is redundant. 1185 if (N->getNumOperands() == 2) { 1186 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1187 return N->getOperand(0); 1188 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1189 return N->getOperand(1); 1190 } 1191 1192 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1193 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1194 SmallPtrSet<SDNode*, 16> SeenOps; 1195 bool Changed = false; // If we should replace this token factor. 1196 1197 // Start out with this token factor. 1198 TFs.push_back(N); 1199 1200 // Iterate through token factors. The TFs grows when new token factors are 1201 // encountered. 1202 for (unsigned i = 0; i < TFs.size(); ++i) { 1203 SDNode *TF = TFs[i]; 1204 1205 // Check each of the operands. 1206 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1207 SDValue Op = TF->getOperand(i); 1208 1209 switch (Op.getOpcode()) { 1210 case ISD::EntryToken: 1211 // Entry tokens don't need to be added to the list. They are 1212 // rededundant. 1213 Changed = true; 1214 break; 1215 1216 case ISD::TokenFactor: 1217 if (Op.hasOneUse() && 1218 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1219 // Queue up for processing. 1220 TFs.push_back(Op.getNode()); 1221 // Clean up in case the token factor is removed. 1222 AddToWorkList(Op.getNode()); 1223 Changed = true; 1224 break; 1225 } 1226 // Fall thru 1227 1228 default: 1229 // Only add if it isn't already in the list. 1230 if (SeenOps.insert(Op.getNode())) 1231 Ops.push_back(Op); 1232 else 1233 Changed = true; 1234 break; 1235 } 1236 } 1237 } 1238 1239 SDValue Result; 1240 1241 // If we've change things around then replace token factor. 1242 if (Changed) { 1243 if (Ops.empty()) { 1244 // The entry token is the only possible outcome. 1245 Result = DAG.getEntryNode(); 1246 } else { 1247 // New and improved token factor. 1248 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1249 MVT::Other, &Ops[0], Ops.size()); 1250 } 1251 1252 // Don't add users to work list. 1253 return CombineTo(N, Result, false); 1254 } 1255 1256 return Result; 1257} 1258 1259/// MERGE_VALUES can always be eliminated. 1260SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1261 WorkListRemover DeadNodes(*this); 1262 // Replacing results may cause a different MERGE_VALUES to suddenly 1263 // be CSE'd with N, and carry its uses with it. Iterate until no 1264 // uses remain, to ensure that the node can be safely deleted. 1265 do { 1266 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1267 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1268 &DeadNodes); 1269 } while (!N->use_empty()); 1270 removeFromWorkList(N); 1271 DAG.DeleteNode(N); 1272 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1273} 1274 1275static 1276SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1277 SelectionDAG &DAG) { 1278 EVT VT = N0.getValueType(); 1279 SDValue N00 = N0.getOperand(0); 1280 SDValue N01 = N0.getOperand(1); 1281 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1282 1283 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1284 isa<ConstantSDNode>(N00.getOperand(1))) { 1285 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1286 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1287 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1288 N00.getOperand(0), N01), 1289 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1290 N00.getOperand(1), N01)); 1291 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1292 } 1293 1294 return SDValue(); 1295} 1296 1297/// isCarryMaterialization - Returns true if V is an ADDE node that is known to 1298/// return 0 or 1 depending on the carry flag. 1299static bool isCarryMaterialization(SDValue V) { 1300 if (V.getOpcode() != ISD::ADDE) 1301 return false; 1302 1303 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(0)); 1304 return C && C->isNullValue() && V.getOperand(0) == V.getOperand(1); 1305} 1306 1307SDValue DAGCombiner::visitADD(SDNode *N) { 1308 SDValue N0 = N->getOperand(0); 1309 SDValue N1 = N->getOperand(1); 1310 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1311 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1312 EVT VT = N0.getValueType(); 1313 1314 // fold vector ops 1315 if (VT.isVector()) { 1316 SDValue FoldedVOp = SimplifyVBinOp(N); 1317 if (FoldedVOp.getNode()) return FoldedVOp; 1318 } 1319 1320 // fold (add x, undef) -> undef 1321 if (N0.getOpcode() == ISD::UNDEF) 1322 return N0; 1323 if (N1.getOpcode() == ISD::UNDEF) 1324 return N1; 1325 // fold (add c1, c2) -> c1+c2 1326 if (N0C && N1C) 1327 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1328 // canonicalize constant to RHS 1329 if (N0C && !N1C) 1330 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1331 // fold (add x, 0) -> x 1332 if (N1C && N1C->isNullValue()) 1333 return N0; 1334 // fold (add Sym, c) -> Sym+c 1335 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1336 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1337 GA->getOpcode() == ISD::GlobalAddress) 1338 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1339 GA->getOffset() + 1340 (uint64_t)N1C->getSExtValue()); 1341 // fold ((c1-A)+c2) -> (c1+c2)-A 1342 if (N1C && N0.getOpcode() == ISD::SUB) 1343 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1344 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1345 DAG.getConstant(N1C->getAPIntValue()+ 1346 N0C->getAPIntValue(), VT), 1347 N0.getOperand(1)); 1348 // reassociate add 1349 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1350 if (RADD.getNode() != 0) 1351 return RADD; 1352 // fold ((0-A) + B) -> B-A 1353 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1354 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1355 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1356 // fold (A + (0-B)) -> A-B 1357 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1358 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1359 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1360 // fold (A+(B-A)) -> B 1361 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1362 return N1.getOperand(0); 1363 // fold ((B-A)+A) -> B 1364 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1365 return N0.getOperand(0); 1366 // fold (A+(B-(A+C))) to (B-C) 1367 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1368 N0 == N1.getOperand(1).getOperand(0)) 1369 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1370 N1.getOperand(1).getOperand(1)); 1371 // fold (A+(B-(C+A))) to (B-C) 1372 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1373 N0 == N1.getOperand(1).getOperand(1)) 1374 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1375 N1.getOperand(1).getOperand(0)); 1376 // fold (A+((B-A)+or-C)) to (B+or-C) 1377 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1378 N1.getOperand(0).getOpcode() == ISD::SUB && 1379 N0 == N1.getOperand(0).getOperand(1)) 1380 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1381 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1382 1383 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1384 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1385 SDValue N00 = N0.getOperand(0); 1386 SDValue N01 = N0.getOperand(1); 1387 SDValue N10 = N1.getOperand(0); 1388 SDValue N11 = N1.getOperand(1); 1389 1390 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1391 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1392 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1393 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1394 } 1395 1396 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1397 return SDValue(N, 0); 1398 1399 // fold (a+b) -> (a|b) iff a and b share no bits. 1400 if (VT.isInteger() && !VT.isVector()) { 1401 APInt LHSZero, LHSOne; 1402 APInt RHSZero, RHSOne; 1403 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1404 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1405 1406 if (LHSZero.getBoolValue()) { 1407 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1408 1409 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1410 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1411 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1412 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1413 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1414 } 1415 } 1416 1417 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1418 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1419 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1420 if (Result.getNode()) return Result; 1421 } 1422 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1423 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1424 if (Result.getNode()) return Result; 1425 } 1426 1427 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1428 if (N1.getOpcode() == ISD::SHL && 1429 N1.getOperand(0).getOpcode() == ISD::SUB) 1430 if (ConstantSDNode *C = 1431 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1432 if (C->getAPIntValue() == 0) 1433 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1434 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1435 N1.getOperand(0).getOperand(1), 1436 N1.getOperand(1))); 1437 if (N0.getOpcode() == ISD::SHL && 1438 N0.getOperand(0).getOpcode() == ISD::SUB) 1439 if (ConstantSDNode *C = 1440 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1441 if (C->getAPIntValue() == 0) 1442 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1443 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1444 N0.getOperand(0).getOperand(1), 1445 N0.getOperand(1))); 1446 1447 if (N1.getOpcode() == ISD::AND) { 1448 SDValue AndOp0 = N1.getOperand(0); 1449 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1450 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1451 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1452 1453 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1454 // and similar xforms where the inner op is either ~0 or 0. 1455 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1456 DebugLoc DL = N->getDebugLoc(); 1457 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1458 } 1459 } 1460 1461 // add (sext i1), X -> sub X, (zext i1) 1462 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1463 N0.getOperand(0).getValueType() == MVT::i1 && 1464 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1465 DebugLoc DL = N->getDebugLoc(); 1466 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1467 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1468 } 1469 1470 // add (adde 0, 0, glue), X -> adde X, 0, glue 1471 if (N0->hasOneUse() && isCarryMaterialization(N0)) 1472 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), 1473 DAG.getVTList(VT, MVT::Glue), N1, N0.getOperand(0), 1474 N0.getOperand(2)); 1475 1476 // add X, (adde 0, 0, glue) -> adde X, 0, glue 1477 if (N1->hasOneUse() && isCarryMaterialization(N1)) 1478 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), 1479 DAG.getVTList(VT, MVT::Glue), N0, N1.getOperand(0), 1480 N1.getOperand(2)); 1481 1482 return SDValue(); 1483} 1484 1485SDValue DAGCombiner::visitADDC(SDNode *N) { 1486 SDValue N0 = N->getOperand(0); 1487 SDValue N1 = N->getOperand(1); 1488 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1489 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1490 EVT VT = N0.getValueType(); 1491 1492 // If the flag result is dead, turn this into an ADD. 1493 if (N->hasNUsesOfValue(0, 1)) 1494 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1495 DAG.getNode(ISD::CARRY_FALSE, 1496 N->getDebugLoc(), MVT::Glue)); 1497 1498 // canonicalize constant to RHS. 1499 if (N0C && !N1C) 1500 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1501 1502 // fold (addc x, 0) -> x + no carry out 1503 if (N1C && N1C->isNullValue()) 1504 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1505 N->getDebugLoc(), MVT::Glue)); 1506 1507 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1508 APInt LHSZero, LHSOne; 1509 APInt RHSZero, RHSOne; 1510 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1511 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1512 1513 if (LHSZero.getBoolValue()) { 1514 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1515 1516 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1517 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1518 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1519 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1520 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1521 DAG.getNode(ISD::CARRY_FALSE, 1522 N->getDebugLoc(), MVT::Glue)); 1523 } 1524 1525 // addc (adde 0, 0, glue), X -> adde X, 0, glue 1526 if (N0->hasOneUse() && isCarryMaterialization(N0)) 1527 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N1, 1528 DAG.getConstant(0, VT), N0.getOperand(2)); 1529 1530 // addc X, (adde 0, 0, glue) -> adde X, 0, glue 1531 if (N1->hasOneUse() && isCarryMaterialization(N1)) 1532 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N0, 1533 DAG.getConstant(0, VT), N1.getOperand(2)); 1534 1535 return SDValue(); 1536} 1537 1538SDValue DAGCombiner::visitADDE(SDNode *N) { 1539 SDValue N0 = N->getOperand(0); 1540 SDValue N1 = N->getOperand(1); 1541 SDValue CarryIn = N->getOperand(2); 1542 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1543 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1544 1545 // If both operands are null we know that carry out will always be false. 1546 if (N0C && N0C->isNullValue() && N0 == N1) 1547 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), DAG.getNode(ISD::CARRY_FALSE, 1548 N->getDebugLoc(), 1549 MVT::Glue)); 1550 1551 // canonicalize constant to RHS 1552 if (N0C && !N1C) 1553 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1554 N1, N0, CarryIn); 1555 1556 // fold (adde x, y, false) -> (addc x, y) 1557 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1558 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1559 1560 return SDValue(); 1561} 1562 1563// Since it may not be valid to emit a fold to zero for vector initializers 1564// check if we can before folding. 1565static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1566 SelectionDAG &DAG, bool LegalOperations) { 1567 if (!VT.isVector()) { 1568 return DAG.getConstant(0, VT); 1569 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1570 // Produce a vector of zeros. 1571 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1572 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1573 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1574 &Ops[0], Ops.size()); 1575 } 1576 return SDValue(); 1577} 1578 1579SDValue DAGCombiner::visitSUB(SDNode *N) { 1580 SDValue N0 = N->getOperand(0); 1581 SDValue N1 = N->getOperand(1); 1582 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1583 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1584 EVT VT = N0.getValueType(); 1585 1586 // fold vector ops 1587 if (VT.isVector()) { 1588 SDValue FoldedVOp = SimplifyVBinOp(N); 1589 if (FoldedVOp.getNode()) return FoldedVOp; 1590 } 1591 1592 // fold (sub x, x) -> 0 1593 // FIXME: Refactor this and xor and other similar operations together. 1594 if (N0 == N1) 1595 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1596 // fold (sub c1, c2) -> c1-c2 1597 if (N0C && N1C) 1598 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1599 // fold (sub x, c) -> (add x, -c) 1600 if (N1C) 1601 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1602 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1603 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1604 if (N0C && N0C->isAllOnesValue()) 1605 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1606 // fold A-(A-B) -> B 1607 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1608 return N1.getOperand(1); 1609 // fold (A+B)-A -> B 1610 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1611 return N0.getOperand(1); 1612 // fold (A+B)-B -> A 1613 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1614 return N0.getOperand(0); 1615 // fold ((A+(B+or-C))-B) -> A+or-C 1616 if (N0.getOpcode() == ISD::ADD && 1617 (N0.getOperand(1).getOpcode() == ISD::SUB || 1618 N0.getOperand(1).getOpcode() == ISD::ADD) && 1619 N0.getOperand(1).getOperand(0) == N1) 1620 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1621 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1622 // fold ((A+(C+B))-B) -> A+C 1623 if (N0.getOpcode() == ISD::ADD && 1624 N0.getOperand(1).getOpcode() == ISD::ADD && 1625 N0.getOperand(1).getOperand(1) == N1) 1626 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1627 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1628 // fold ((A-(B-C))-C) -> A-B 1629 if (N0.getOpcode() == ISD::SUB && 1630 N0.getOperand(1).getOpcode() == ISD::SUB && 1631 N0.getOperand(1).getOperand(1) == N1) 1632 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1633 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1634 1635 // If either operand of a sub is undef, the result is undef 1636 if (N0.getOpcode() == ISD::UNDEF) 1637 return N0; 1638 if (N1.getOpcode() == ISD::UNDEF) 1639 return N1; 1640 1641 // If the relocation model supports it, consider symbol offsets. 1642 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1643 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1644 // fold (sub Sym, c) -> Sym-c 1645 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1646 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1647 GA->getOffset() - 1648 (uint64_t)N1C->getSExtValue()); 1649 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1650 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1651 if (GA->getGlobal() == GB->getGlobal()) 1652 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1653 VT); 1654 } 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitMUL(SDNode *N) { 1660 SDValue N0 = N->getOperand(0); 1661 SDValue N1 = N->getOperand(1); 1662 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1663 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1664 EVT VT = N0.getValueType(); 1665 1666 // fold vector ops 1667 if (VT.isVector()) { 1668 SDValue FoldedVOp = SimplifyVBinOp(N); 1669 if (FoldedVOp.getNode()) return FoldedVOp; 1670 } 1671 1672 // fold (mul x, undef) -> 0 1673 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1674 return DAG.getConstant(0, VT); 1675 // fold (mul c1, c2) -> c1*c2 1676 if (N0C && N1C) 1677 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1678 // canonicalize constant to RHS 1679 if (N0C && !N1C) 1680 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1681 // fold (mul x, 0) -> 0 1682 if (N1C && N1C->isNullValue()) 1683 return N1; 1684 // fold (mul x, -1) -> 0-x 1685 if (N1C && N1C->isAllOnesValue()) 1686 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1687 DAG.getConstant(0, VT), N0); 1688 // fold (mul x, (1 << c)) -> x << c 1689 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1690 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1691 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1692 getShiftAmountTy(N0.getValueType()))); 1693 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1694 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1695 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1696 // FIXME: If the input is something that is easily negated (e.g. a 1697 // single-use add), we should put the negate there. 1698 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1699 DAG.getConstant(0, VT), 1700 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1701 DAG.getConstant(Log2Val, 1702 getShiftAmountTy(N0.getValueType())))); 1703 } 1704 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1705 if (N1C && N0.getOpcode() == ISD::SHL && 1706 isa<ConstantSDNode>(N0.getOperand(1))) { 1707 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1708 N1, N0.getOperand(1)); 1709 AddToWorkList(C3.getNode()); 1710 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1711 N0.getOperand(0), C3); 1712 } 1713 1714 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1715 // use. 1716 { 1717 SDValue Sh(0,0), Y(0,0); 1718 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1719 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1720 N0.getNode()->hasOneUse()) { 1721 Sh = N0; Y = N1; 1722 } else if (N1.getOpcode() == ISD::SHL && 1723 isa<ConstantSDNode>(N1.getOperand(1)) && 1724 N1.getNode()->hasOneUse()) { 1725 Sh = N1; Y = N0; 1726 } 1727 1728 if (Sh.getNode()) { 1729 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1730 Sh.getOperand(0), Y); 1731 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1732 Mul, Sh.getOperand(1)); 1733 } 1734 } 1735 1736 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1737 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1738 isa<ConstantSDNode>(N0.getOperand(1))) 1739 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1740 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1741 N0.getOperand(0), N1), 1742 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1743 N0.getOperand(1), N1)); 1744 1745 // reassociate mul 1746 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1747 if (RMUL.getNode() != 0) 1748 return RMUL; 1749 1750 return SDValue(); 1751} 1752 1753SDValue DAGCombiner::visitSDIV(SDNode *N) { 1754 SDValue N0 = N->getOperand(0); 1755 SDValue N1 = N->getOperand(1); 1756 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1757 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1758 EVT VT = N->getValueType(0); 1759 1760 // fold vector ops 1761 if (VT.isVector()) { 1762 SDValue FoldedVOp = SimplifyVBinOp(N); 1763 if (FoldedVOp.getNode()) return FoldedVOp; 1764 } 1765 1766 // fold (sdiv c1, c2) -> c1/c2 1767 if (N0C && N1C && !N1C->isNullValue()) 1768 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1769 // fold (sdiv X, 1) -> X 1770 if (N1C && N1C->getSExtValue() == 1LL) 1771 return N0; 1772 // fold (sdiv X, -1) -> 0-X 1773 if (N1C && N1C->isAllOnesValue()) 1774 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1775 DAG.getConstant(0, VT), N0); 1776 // If we know the sign bits of both operands are zero, strength reduce to a 1777 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1778 if (!VT.isVector()) { 1779 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1780 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1781 N0, N1); 1782 } 1783 // fold (sdiv X, pow2) -> simple ops after legalize 1784 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1785 (isPowerOf2_64(N1C->getSExtValue()) || 1786 isPowerOf2_64(-N1C->getSExtValue()))) { 1787 // If dividing by powers of two is cheap, then don't perform the following 1788 // fold. 1789 if (TLI.isPow2DivCheap()) 1790 return SDValue(); 1791 1792 int64_t pow2 = N1C->getSExtValue(); 1793 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1794 unsigned lg2 = Log2_64(abs2); 1795 1796 // Splat the sign bit into the register 1797 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1798 DAG.getConstant(VT.getSizeInBits()-1, 1799 getShiftAmountTy(N0.getValueType()))); 1800 AddToWorkList(SGN.getNode()); 1801 1802 // Add (N0 < 0) ? abs2 - 1 : 0; 1803 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1804 DAG.getConstant(VT.getSizeInBits() - lg2, 1805 getShiftAmountTy(SGN.getValueType()))); 1806 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1807 AddToWorkList(SRL.getNode()); 1808 AddToWorkList(ADD.getNode()); // Divide by pow2 1809 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1810 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1811 1812 // If we're dividing by a positive value, we're done. Otherwise, we must 1813 // negate the result. 1814 if (pow2 > 0) 1815 return SRA; 1816 1817 AddToWorkList(SRA.getNode()); 1818 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1819 DAG.getConstant(0, VT), SRA); 1820 } 1821 1822 // if integer divide is expensive and we satisfy the requirements, emit an 1823 // alternate sequence. 1824 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1825 !TLI.isIntDivCheap()) { 1826 SDValue Op = BuildSDIV(N); 1827 if (Op.getNode()) return Op; 1828 } 1829 1830 // undef / X -> 0 1831 if (N0.getOpcode() == ISD::UNDEF) 1832 return DAG.getConstant(0, VT); 1833 // X / undef -> undef 1834 if (N1.getOpcode() == ISD::UNDEF) 1835 return N1; 1836 1837 return SDValue(); 1838} 1839 1840SDValue DAGCombiner::visitUDIV(SDNode *N) { 1841 SDValue N0 = N->getOperand(0); 1842 SDValue N1 = N->getOperand(1); 1843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1845 EVT VT = N->getValueType(0); 1846 1847 // fold vector ops 1848 if (VT.isVector()) { 1849 SDValue FoldedVOp = SimplifyVBinOp(N); 1850 if (FoldedVOp.getNode()) return FoldedVOp; 1851 } 1852 1853 // fold (udiv c1, c2) -> c1/c2 1854 if (N0C && N1C && !N1C->isNullValue()) 1855 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1856 // fold (udiv x, (1 << c)) -> x >>u c 1857 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1858 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1859 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1860 getShiftAmountTy(N0.getValueType()))); 1861 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1862 if (N1.getOpcode() == ISD::SHL) { 1863 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1864 if (SHC->getAPIntValue().isPowerOf2()) { 1865 EVT ADDVT = N1.getOperand(1).getValueType(); 1866 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1867 N1.getOperand(1), 1868 DAG.getConstant(SHC->getAPIntValue() 1869 .logBase2(), 1870 ADDVT)); 1871 AddToWorkList(Add.getNode()); 1872 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1873 } 1874 } 1875 } 1876 // fold (udiv x, c) -> alternate 1877 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1878 SDValue Op = BuildUDIV(N); 1879 if (Op.getNode()) return Op; 1880 } 1881 1882 // undef / X -> 0 1883 if (N0.getOpcode() == ISD::UNDEF) 1884 return DAG.getConstant(0, VT); 1885 // X / undef -> undef 1886 if (N1.getOpcode() == ISD::UNDEF) 1887 return N1; 1888 1889 return SDValue(); 1890} 1891 1892SDValue DAGCombiner::visitSREM(SDNode *N) { 1893 SDValue N0 = N->getOperand(0); 1894 SDValue N1 = N->getOperand(1); 1895 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1896 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1897 EVT VT = N->getValueType(0); 1898 1899 // fold (srem c1, c2) -> c1%c2 1900 if (N0C && N1C && !N1C->isNullValue()) 1901 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1902 // If we know the sign bits of both operands are zero, strength reduce to a 1903 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1904 if (!VT.isVector()) { 1905 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1906 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1907 } 1908 1909 // If X/C can be simplified by the division-by-constant logic, lower 1910 // X%C to the equivalent of X-X/C*C. 1911 if (N1C && !N1C->isNullValue()) { 1912 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1913 AddToWorkList(Div.getNode()); 1914 SDValue OptimizedDiv = combine(Div.getNode()); 1915 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1916 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1917 OptimizedDiv, N1); 1918 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1919 AddToWorkList(Mul.getNode()); 1920 return Sub; 1921 } 1922 } 1923 1924 // undef % X -> 0 1925 if (N0.getOpcode() == ISD::UNDEF) 1926 return DAG.getConstant(0, VT); 1927 // X % undef -> undef 1928 if (N1.getOpcode() == ISD::UNDEF) 1929 return N1; 1930 1931 return SDValue(); 1932} 1933 1934SDValue DAGCombiner::visitUREM(SDNode *N) { 1935 SDValue N0 = N->getOperand(0); 1936 SDValue N1 = N->getOperand(1); 1937 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1938 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1939 EVT VT = N->getValueType(0); 1940 1941 // fold (urem c1, c2) -> c1%c2 1942 if (N0C && N1C && !N1C->isNullValue()) 1943 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1944 // fold (urem x, pow2) -> (and x, pow2-1) 1945 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1946 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1947 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1948 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1949 if (N1.getOpcode() == ISD::SHL) { 1950 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1951 if (SHC->getAPIntValue().isPowerOf2()) { 1952 SDValue Add = 1953 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1954 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1955 VT)); 1956 AddToWorkList(Add.getNode()); 1957 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1958 } 1959 } 1960 } 1961 1962 // If X/C can be simplified by the division-by-constant logic, lower 1963 // X%C to the equivalent of X-X/C*C. 1964 if (N1C && !N1C->isNullValue()) { 1965 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1966 AddToWorkList(Div.getNode()); 1967 SDValue OptimizedDiv = combine(Div.getNode()); 1968 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1969 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1970 OptimizedDiv, N1); 1971 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1972 AddToWorkList(Mul.getNode()); 1973 return Sub; 1974 } 1975 } 1976 1977 // undef % X -> 0 1978 if (N0.getOpcode() == ISD::UNDEF) 1979 return DAG.getConstant(0, VT); 1980 // X % undef -> undef 1981 if (N1.getOpcode() == ISD::UNDEF) 1982 return N1; 1983 1984 return SDValue(); 1985} 1986 1987SDValue DAGCombiner::visitMULHS(SDNode *N) { 1988 SDValue N0 = N->getOperand(0); 1989 SDValue N1 = N->getOperand(1); 1990 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1991 EVT VT = N->getValueType(0); 1992 DebugLoc DL = N->getDebugLoc(); 1993 1994 // fold (mulhs x, 0) -> 0 1995 if (N1C && N1C->isNullValue()) 1996 return N1; 1997 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1998 if (N1C && N1C->getAPIntValue() == 1) 1999 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2000 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2001 getShiftAmountTy(N0.getValueType()))); 2002 // fold (mulhs x, undef) -> 0 2003 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2004 return DAG.getConstant(0, VT); 2005 2006 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2007 // plus a shift. 2008 if (VT.isSimple() && !VT.isVector()) { 2009 MVT Simple = VT.getSimpleVT(); 2010 unsigned SimpleSize = Simple.getSizeInBits(); 2011 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2012 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2013 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2014 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2015 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2016 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2017 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2018 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2019 } 2020 } 2021 2022 return SDValue(); 2023} 2024 2025SDValue DAGCombiner::visitMULHU(SDNode *N) { 2026 SDValue N0 = N->getOperand(0); 2027 SDValue N1 = N->getOperand(1); 2028 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2029 EVT VT = N->getValueType(0); 2030 DebugLoc DL = N->getDebugLoc(); 2031 2032 // fold (mulhu x, 0) -> 0 2033 if (N1C && N1C->isNullValue()) 2034 return N1; 2035 // fold (mulhu x, 1) -> 0 2036 if (N1C && N1C->getAPIntValue() == 1) 2037 return DAG.getConstant(0, N0.getValueType()); 2038 // fold (mulhu x, undef) -> 0 2039 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2040 return DAG.getConstant(0, VT); 2041 2042 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2043 // plus a shift. 2044 if (VT.isSimple() && !VT.isVector()) { 2045 MVT Simple = VT.getSimpleVT(); 2046 unsigned SimpleSize = Simple.getSizeInBits(); 2047 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2048 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2049 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2050 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2051 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2052 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2053 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2054 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2055 } 2056 } 2057 2058 return SDValue(); 2059} 2060 2061/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2062/// compute two values. LoOp and HiOp give the opcodes for the two computations 2063/// that are being performed. Return true if a simplification was made. 2064/// 2065SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2066 unsigned HiOp) { 2067 // If the high half is not needed, just compute the low half. 2068 bool HiExists = N->hasAnyUseOfValue(1); 2069 if (!HiExists && 2070 (!LegalOperations || 2071 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2072 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2073 N->op_begin(), N->getNumOperands()); 2074 return CombineTo(N, Res, Res); 2075 } 2076 2077 // If the low half is not needed, just compute the high half. 2078 bool LoExists = N->hasAnyUseOfValue(0); 2079 if (!LoExists && 2080 (!LegalOperations || 2081 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2082 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2083 N->op_begin(), N->getNumOperands()); 2084 return CombineTo(N, Res, Res); 2085 } 2086 2087 // If both halves are used, return as it is. 2088 if (LoExists && HiExists) 2089 return SDValue(); 2090 2091 // If the two computed results can be simplified separately, separate them. 2092 if (LoExists) { 2093 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2094 N->op_begin(), N->getNumOperands()); 2095 AddToWorkList(Lo.getNode()); 2096 SDValue LoOpt = combine(Lo.getNode()); 2097 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2098 (!LegalOperations || 2099 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2100 return CombineTo(N, LoOpt, LoOpt); 2101 } 2102 2103 if (HiExists) { 2104 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2105 N->op_begin(), N->getNumOperands()); 2106 AddToWorkList(Hi.getNode()); 2107 SDValue HiOpt = combine(Hi.getNode()); 2108 if (HiOpt.getNode() && HiOpt != Hi && 2109 (!LegalOperations || 2110 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2111 return CombineTo(N, HiOpt, HiOpt); 2112 } 2113 2114 return SDValue(); 2115} 2116 2117SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2118 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2119 if (Res.getNode()) return Res; 2120 2121 EVT VT = N->getValueType(0); 2122 DebugLoc DL = N->getDebugLoc(); 2123 2124 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2125 // plus a shift. 2126 if (VT.isSimple() && !VT.isVector()) { 2127 MVT Simple = VT.getSimpleVT(); 2128 unsigned SimpleSize = Simple.getSizeInBits(); 2129 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2130 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2131 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2132 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2133 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2134 // Compute the high part as N1. 2135 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2136 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2137 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2138 // Compute the low part as N0. 2139 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2140 return CombineTo(N, Lo, Hi); 2141 } 2142 } 2143 2144 return SDValue(); 2145} 2146 2147SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2148 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2149 if (Res.getNode()) return Res; 2150 2151 EVT VT = N->getValueType(0); 2152 DebugLoc DL = N->getDebugLoc(); 2153 2154 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2155 // plus a shift. 2156 if (VT.isSimple() && !VT.isVector()) { 2157 MVT Simple = VT.getSimpleVT(); 2158 unsigned SimpleSize = Simple.getSizeInBits(); 2159 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2160 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2161 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2162 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2163 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2164 // Compute the high part as N1. 2165 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2166 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2167 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2168 // Compute the low part as N0. 2169 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2170 return CombineTo(N, Lo, Hi); 2171 } 2172 } 2173 2174 return SDValue(); 2175} 2176 2177SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2178 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2179 if (Res.getNode()) return Res; 2180 2181 return SDValue(); 2182} 2183 2184SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2185 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2186 if (Res.getNode()) return Res; 2187 2188 return SDValue(); 2189} 2190 2191/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2192/// two operands of the same opcode, try to simplify it. 2193SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2194 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2195 EVT VT = N0.getValueType(); 2196 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2197 2198 // Bail early if none of these transforms apply. 2199 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2200 2201 // For each of OP in AND/OR/XOR: 2202 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2203 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2204 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2205 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2206 // 2207 // do not sink logical op inside of a vector extend, since it may combine 2208 // into a vsetcc. 2209 EVT Op0VT = N0.getOperand(0).getValueType(); 2210 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2211 N0.getOpcode() == ISD::SIGN_EXTEND || 2212 // Avoid infinite looping with PromoteIntBinOp. 2213 (N0.getOpcode() == ISD::ANY_EXTEND && 2214 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2215 (N0.getOpcode() == ISD::TRUNCATE && 2216 (!TLI.isZExtFree(VT, Op0VT) || 2217 !TLI.isTruncateFree(Op0VT, VT)) && 2218 TLI.isTypeLegal(Op0VT))) && 2219 !VT.isVector() && 2220 Op0VT == N1.getOperand(0).getValueType() && 2221 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2222 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2223 N0.getOperand(0).getValueType(), 2224 N0.getOperand(0), N1.getOperand(0)); 2225 AddToWorkList(ORNode.getNode()); 2226 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2227 } 2228 2229 // For each of OP in SHL/SRL/SRA/AND... 2230 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2231 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2232 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2233 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2234 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2235 N0.getOperand(1) == N1.getOperand(1)) { 2236 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2237 N0.getOperand(0).getValueType(), 2238 N0.getOperand(0), N1.getOperand(0)); 2239 AddToWorkList(ORNode.getNode()); 2240 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2241 ORNode, N0.getOperand(1)); 2242 } 2243 2244 return SDValue(); 2245} 2246 2247SDValue DAGCombiner::visitAND(SDNode *N) { 2248 SDValue N0 = N->getOperand(0); 2249 SDValue N1 = N->getOperand(1); 2250 SDValue LL, LR, RL, RR, CC0, CC1; 2251 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2252 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2253 EVT VT = N1.getValueType(); 2254 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2255 2256 // fold vector ops 2257 if (VT.isVector()) { 2258 SDValue FoldedVOp = SimplifyVBinOp(N); 2259 if (FoldedVOp.getNode()) return FoldedVOp; 2260 } 2261 2262 // fold (and x, undef) -> 0 2263 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2264 return DAG.getConstant(0, VT); 2265 // fold (and c1, c2) -> c1&c2 2266 if (N0C && N1C) 2267 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2268 // canonicalize constant to RHS 2269 if (N0C && !N1C) 2270 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2271 // fold (and x, -1) -> x 2272 if (N1C && N1C->isAllOnesValue()) 2273 return N0; 2274 // if (and x, c) is known to be zero, return 0 2275 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2276 APInt::getAllOnesValue(BitWidth))) 2277 return DAG.getConstant(0, VT); 2278 // reassociate and 2279 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2280 if (RAND.getNode() != 0) 2281 return RAND; 2282 // fold (and (or x, C), D) -> D if (C & D) == D 2283 if (N1C && N0.getOpcode() == ISD::OR) 2284 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2285 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2286 return N1; 2287 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2288 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2289 SDValue N0Op0 = N0.getOperand(0); 2290 APInt Mask = ~N1C->getAPIntValue(); 2291 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2292 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2293 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2294 N0.getValueType(), N0Op0); 2295 2296 // Replace uses of the AND with uses of the Zero extend node. 2297 CombineTo(N, Zext); 2298 2299 // We actually want to replace all uses of the any_extend with the 2300 // zero_extend, to avoid duplicating things. This will later cause this 2301 // AND to be folded. 2302 CombineTo(N0.getNode(), Zext); 2303 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2304 } 2305 } 2306 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2307 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2308 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2309 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2310 2311 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2312 LL.getValueType().isInteger()) { 2313 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2314 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2315 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2316 LR.getValueType(), LL, RL); 2317 AddToWorkList(ORNode.getNode()); 2318 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2319 } 2320 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2321 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2322 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2323 LR.getValueType(), LL, RL); 2324 AddToWorkList(ANDNode.getNode()); 2325 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2326 } 2327 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2328 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2329 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2330 LR.getValueType(), LL, RL); 2331 AddToWorkList(ORNode.getNode()); 2332 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2333 } 2334 } 2335 // canonicalize equivalent to ll == rl 2336 if (LL == RR && LR == RL) { 2337 Op1 = ISD::getSetCCSwappedOperands(Op1); 2338 std::swap(RL, RR); 2339 } 2340 if (LL == RL && LR == RR) { 2341 bool isInteger = LL.getValueType().isInteger(); 2342 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2343 if (Result != ISD::SETCC_INVALID && 2344 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2345 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2346 LL, LR, Result); 2347 } 2348 } 2349 2350 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2351 if (N0.getOpcode() == N1.getOpcode()) { 2352 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2353 if (Tmp.getNode()) return Tmp; 2354 } 2355 2356 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2357 // fold (and (sra)) -> (and (srl)) when possible. 2358 if (!VT.isVector() && 2359 SimplifyDemandedBits(SDValue(N, 0))) 2360 return SDValue(N, 0); 2361 2362 // fold (zext_inreg (extload x)) -> (zextload x) 2363 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2364 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2365 EVT MemVT = LN0->getMemoryVT(); 2366 // If we zero all the possible extended bits, then we can turn this into 2367 // a zextload if we are running before legalize or the operation is legal. 2368 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2369 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2370 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2371 ((!LegalOperations && !LN0->isVolatile()) || 2372 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2373 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2374 LN0->getChain(), LN0->getBasePtr(), 2375 LN0->getPointerInfo(), MemVT, 2376 LN0->isVolatile(), LN0->isNonTemporal(), 2377 LN0->getAlignment()); 2378 AddToWorkList(N); 2379 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2380 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2381 } 2382 } 2383 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2384 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2385 N0.hasOneUse()) { 2386 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2387 EVT MemVT = LN0->getMemoryVT(); 2388 // If we zero all the possible extended bits, then we can turn this into 2389 // a zextload if we are running before legalize or the operation is legal. 2390 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2391 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2392 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2393 ((!LegalOperations && !LN0->isVolatile()) || 2394 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2395 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2396 LN0->getChain(), 2397 LN0->getBasePtr(), LN0->getPointerInfo(), 2398 MemVT, 2399 LN0->isVolatile(), LN0->isNonTemporal(), 2400 LN0->getAlignment()); 2401 AddToWorkList(N); 2402 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2403 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2404 } 2405 } 2406 2407 // fold (and (load x), 255) -> (zextload x, i8) 2408 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2409 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2410 if (N1C && (N0.getOpcode() == ISD::LOAD || 2411 (N0.getOpcode() == ISD::ANY_EXTEND && 2412 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2413 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2414 LoadSDNode *LN0 = HasAnyExt 2415 ? cast<LoadSDNode>(N0.getOperand(0)) 2416 : cast<LoadSDNode>(N0); 2417 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2418 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2419 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2420 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2421 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2422 EVT LoadedVT = LN0->getMemoryVT(); 2423 2424 if (ExtVT == LoadedVT && 2425 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2426 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2427 2428 SDValue NewLoad = 2429 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2430 LN0->getChain(), LN0->getBasePtr(), 2431 LN0->getPointerInfo(), 2432 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2433 LN0->getAlignment()); 2434 AddToWorkList(N); 2435 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2436 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2437 } 2438 2439 // Do not change the width of a volatile load. 2440 // Do not generate loads of non-round integer types since these can 2441 // be expensive (and would be wrong if the type is not byte sized). 2442 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2443 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2444 EVT PtrType = LN0->getOperand(1).getValueType(); 2445 2446 unsigned Alignment = LN0->getAlignment(); 2447 SDValue NewPtr = LN0->getBasePtr(); 2448 2449 // For big endian targets, we need to add an offset to the pointer 2450 // to load the correct bytes. For little endian systems, we merely 2451 // need to read fewer bytes from the same pointer. 2452 if (TLI.isBigEndian()) { 2453 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2454 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2455 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2456 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2457 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2458 Alignment = MinAlign(Alignment, PtrOff); 2459 } 2460 2461 AddToWorkList(NewPtr.getNode()); 2462 2463 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2464 SDValue Load = 2465 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2466 LN0->getChain(), NewPtr, 2467 LN0->getPointerInfo(), 2468 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2469 Alignment); 2470 AddToWorkList(N); 2471 CombineTo(LN0, Load, Load.getValue(1)); 2472 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2473 } 2474 } 2475 } 2476 } 2477 2478 return SDValue(); 2479} 2480 2481SDValue DAGCombiner::visitOR(SDNode *N) { 2482 SDValue N0 = N->getOperand(0); 2483 SDValue N1 = N->getOperand(1); 2484 SDValue LL, LR, RL, RR, CC0, CC1; 2485 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2486 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2487 EVT VT = N1.getValueType(); 2488 2489 // fold vector ops 2490 if (VT.isVector()) { 2491 SDValue FoldedVOp = SimplifyVBinOp(N); 2492 if (FoldedVOp.getNode()) return FoldedVOp; 2493 } 2494 2495 // fold (or x, undef) -> -1 2496 if (!LegalOperations && 2497 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2498 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2499 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2500 } 2501 // fold (or c1, c2) -> c1|c2 2502 if (N0C && N1C) 2503 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2504 // canonicalize constant to RHS 2505 if (N0C && !N1C) 2506 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2507 // fold (or x, 0) -> x 2508 if (N1C && N1C->isNullValue()) 2509 return N0; 2510 // fold (or x, -1) -> -1 2511 if (N1C && N1C->isAllOnesValue()) 2512 return N1; 2513 // fold (or x, c) -> c iff (x & ~c) == 0 2514 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2515 return N1; 2516 // reassociate or 2517 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2518 if (ROR.getNode() != 0) 2519 return ROR; 2520 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2521 // iff (c1 & c2) == 0. 2522 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2523 isa<ConstantSDNode>(N0.getOperand(1))) { 2524 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2525 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2526 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2527 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2528 N0.getOperand(0), N1), 2529 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2530 } 2531 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2532 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2533 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2534 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2535 2536 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2537 LL.getValueType().isInteger()) { 2538 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2539 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2540 if (cast<ConstantSDNode>(LR)->isNullValue() && 2541 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2542 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2543 LR.getValueType(), LL, RL); 2544 AddToWorkList(ORNode.getNode()); 2545 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2546 } 2547 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2548 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2549 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2550 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2551 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2552 LR.getValueType(), LL, RL); 2553 AddToWorkList(ANDNode.getNode()); 2554 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2555 } 2556 } 2557 // canonicalize equivalent to ll == rl 2558 if (LL == RR && LR == RL) { 2559 Op1 = ISD::getSetCCSwappedOperands(Op1); 2560 std::swap(RL, RR); 2561 } 2562 if (LL == RL && LR == RR) { 2563 bool isInteger = LL.getValueType().isInteger(); 2564 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2565 if (Result != ISD::SETCC_INVALID && 2566 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2567 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2568 LL, LR, Result); 2569 } 2570 } 2571 2572 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2573 if (N0.getOpcode() == N1.getOpcode()) { 2574 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2575 if (Tmp.getNode()) return Tmp; 2576 } 2577 2578 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2579 if (N0.getOpcode() == ISD::AND && 2580 N1.getOpcode() == ISD::AND && 2581 N0.getOperand(1).getOpcode() == ISD::Constant && 2582 N1.getOperand(1).getOpcode() == ISD::Constant && 2583 // Don't increase # computations. 2584 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2585 // We can only do this xform if we know that bits from X that are set in C2 2586 // but not in C1 are already zero. Likewise for Y. 2587 const APInt &LHSMask = 2588 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2589 const APInt &RHSMask = 2590 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2591 2592 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2593 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2594 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2595 N0.getOperand(0), N1.getOperand(0)); 2596 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2597 DAG.getConstant(LHSMask | RHSMask, VT)); 2598 } 2599 } 2600 2601 // See if this is some rotate idiom. 2602 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2603 return SDValue(Rot, 0); 2604 2605 // Simplify the operands using demanded-bits information. 2606 if (!VT.isVector() && 2607 SimplifyDemandedBits(SDValue(N, 0))) 2608 return SDValue(N, 0); 2609 2610 return SDValue(); 2611} 2612 2613/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2614static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2615 if (Op.getOpcode() == ISD::AND) { 2616 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2617 Mask = Op.getOperand(1); 2618 Op = Op.getOperand(0); 2619 } else { 2620 return false; 2621 } 2622 } 2623 2624 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2625 Shift = Op; 2626 return true; 2627 } 2628 2629 return false; 2630} 2631 2632// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2633// idioms for rotate, and if the target supports rotation instructions, generate 2634// a rot[lr]. 2635SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2636 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2637 EVT VT = LHS.getValueType(); 2638 if (!TLI.isTypeLegal(VT)) return 0; 2639 2640 // The target must have at least one rotate flavor. 2641 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2642 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2643 if (!HasROTL && !HasROTR) return 0; 2644 2645 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2646 SDValue LHSShift; // The shift. 2647 SDValue LHSMask; // AND value if any. 2648 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2649 return 0; // Not part of a rotate. 2650 2651 SDValue RHSShift; // The shift. 2652 SDValue RHSMask; // AND value if any. 2653 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2654 return 0; // Not part of a rotate. 2655 2656 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2657 return 0; // Not shifting the same value. 2658 2659 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2660 return 0; // Shifts must disagree. 2661 2662 // Canonicalize shl to left side in a shl/srl pair. 2663 if (RHSShift.getOpcode() == ISD::SHL) { 2664 std::swap(LHS, RHS); 2665 std::swap(LHSShift, RHSShift); 2666 std::swap(LHSMask , RHSMask ); 2667 } 2668 2669 unsigned OpSizeInBits = VT.getSizeInBits(); 2670 SDValue LHSShiftArg = LHSShift.getOperand(0); 2671 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2672 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2673 2674 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2675 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2676 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2677 RHSShiftAmt.getOpcode() == ISD::Constant) { 2678 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2679 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2680 if ((LShVal + RShVal) != OpSizeInBits) 2681 return 0; 2682 2683 SDValue Rot; 2684 if (HasROTL) 2685 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2686 else 2687 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2688 2689 // If there is an AND of either shifted operand, apply it to the result. 2690 if (LHSMask.getNode() || RHSMask.getNode()) { 2691 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2692 2693 if (LHSMask.getNode()) { 2694 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2695 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2696 } 2697 if (RHSMask.getNode()) { 2698 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2699 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2700 } 2701 2702 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2703 } 2704 2705 return Rot.getNode(); 2706 } 2707 2708 // If there is a mask here, and we have a variable shift, we can't be sure 2709 // that we're masking out the right stuff. 2710 if (LHSMask.getNode() || RHSMask.getNode()) 2711 return 0; 2712 2713 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2714 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2715 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2716 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2717 if (ConstantSDNode *SUBC = 2718 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2719 if (SUBC->getAPIntValue() == OpSizeInBits) { 2720 if (HasROTL) 2721 return DAG.getNode(ISD::ROTL, DL, VT, 2722 LHSShiftArg, LHSShiftAmt).getNode(); 2723 else 2724 return DAG.getNode(ISD::ROTR, DL, VT, 2725 LHSShiftArg, RHSShiftAmt).getNode(); 2726 } 2727 } 2728 } 2729 2730 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2731 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2732 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2733 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2734 if (ConstantSDNode *SUBC = 2735 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2736 if (SUBC->getAPIntValue() == OpSizeInBits) { 2737 if (HasROTR) 2738 return DAG.getNode(ISD::ROTR, DL, VT, 2739 LHSShiftArg, RHSShiftAmt).getNode(); 2740 else 2741 return DAG.getNode(ISD::ROTL, DL, VT, 2742 LHSShiftArg, LHSShiftAmt).getNode(); 2743 } 2744 } 2745 } 2746 2747 // Look for sign/zext/any-extended or truncate cases: 2748 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2749 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2750 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2751 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2752 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2753 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2754 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2755 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2756 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2757 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2758 if (RExtOp0.getOpcode() == ISD::SUB && 2759 RExtOp0.getOperand(1) == LExtOp0) { 2760 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2761 // (rotl x, y) 2762 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2763 // (rotr x, (sub 32, y)) 2764 if (ConstantSDNode *SUBC = 2765 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2766 if (SUBC->getAPIntValue() == OpSizeInBits) { 2767 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2768 LHSShiftArg, 2769 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2770 } 2771 } 2772 } else if (LExtOp0.getOpcode() == ISD::SUB && 2773 RExtOp0 == LExtOp0.getOperand(1)) { 2774 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2775 // (rotr x, y) 2776 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2777 // (rotl x, (sub 32, y)) 2778 if (ConstantSDNode *SUBC = 2779 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2780 if (SUBC->getAPIntValue() == OpSizeInBits) { 2781 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2782 LHSShiftArg, 2783 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2784 } 2785 } 2786 } 2787 } 2788 2789 return 0; 2790} 2791 2792SDValue DAGCombiner::visitXOR(SDNode *N) { 2793 SDValue N0 = N->getOperand(0); 2794 SDValue N1 = N->getOperand(1); 2795 SDValue LHS, RHS, CC; 2796 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2797 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2798 EVT VT = N0.getValueType(); 2799 2800 // fold vector ops 2801 if (VT.isVector()) { 2802 SDValue FoldedVOp = SimplifyVBinOp(N); 2803 if (FoldedVOp.getNode()) return FoldedVOp; 2804 } 2805 2806 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2807 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2808 return DAG.getConstant(0, VT); 2809 // fold (xor x, undef) -> undef 2810 if (N0.getOpcode() == ISD::UNDEF) 2811 return N0; 2812 if (N1.getOpcode() == ISD::UNDEF) 2813 return N1; 2814 // fold (xor c1, c2) -> c1^c2 2815 if (N0C && N1C) 2816 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2817 // canonicalize constant to RHS 2818 if (N0C && !N1C) 2819 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2820 // fold (xor x, 0) -> x 2821 if (N1C && N1C->isNullValue()) 2822 return N0; 2823 // reassociate xor 2824 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2825 if (RXOR.getNode() != 0) 2826 return RXOR; 2827 2828 // fold !(x cc y) -> (x !cc y) 2829 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2830 bool isInt = LHS.getValueType().isInteger(); 2831 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2832 isInt); 2833 2834 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2835 switch (N0.getOpcode()) { 2836 default: 2837 llvm_unreachable("Unhandled SetCC Equivalent!"); 2838 case ISD::SETCC: 2839 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2840 case ISD::SELECT_CC: 2841 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2842 N0.getOperand(3), NotCC); 2843 } 2844 } 2845 } 2846 2847 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2848 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2849 N0.getNode()->hasOneUse() && 2850 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2851 SDValue V = N0.getOperand(0); 2852 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2853 DAG.getConstant(1, V.getValueType())); 2854 AddToWorkList(V.getNode()); 2855 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2856 } 2857 2858 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2859 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2860 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2861 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2862 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2863 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2864 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2865 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2866 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2867 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2868 } 2869 } 2870 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2871 if (N1C && N1C->isAllOnesValue() && 2872 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2873 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2874 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2875 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2876 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2877 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2878 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2879 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2880 } 2881 } 2882 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2883 if (N1C && N0.getOpcode() == ISD::XOR) { 2884 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2885 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2886 if (N00C) 2887 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2888 DAG.getConstant(N1C->getAPIntValue() ^ 2889 N00C->getAPIntValue(), VT)); 2890 if (N01C) 2891 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2892 DAG.getConstant(N1C->getAPIntValue() ^ 2893 N01C->getAPIntValue(), VT)); 2894 } 2895 // fold (xor x, x) -> 0 2896 if (N0 == N1) 2897 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 2898 2899 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2900 if (N0.getOpcode() == N1.getOpcode()) { 2901 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2902 if (Tmp.getNode()) return Tmp; 2903 } 2904 2905 // Simplify the expression using non-local knowledge. 2906 if (!VT.isVector() && 2907 SimplifyDemandedBits(SDValue(N, 0))) 2908 return SDValue(N, 0); 2909 2910 return SDValue(); 2911} 2912 2913/// visitShiftByConstant - Handle transforms common to the three shifts, when 2914/// the shift amount is a constant. 2915SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2916 SDNode *LHS = N->getOperand(0).getNode(); 2917 if (!LHS->hasOneUse()) return SDValue(); 2918 2919 // We want to pull some binops through shifts, so that we have (and (shift)) 2920 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2921 // thing happens with address calculations, so it's important to canonicalize 2922 // it. 2923 bool HighBitSet = false; // Can we transform this if the high bit is set? 2924 2925 switch (LHS->getOpcode()) { 2926 default: return SDValue(); 2927 case ISD::OR: 2928 case ISD::XOR: 2929 HighBitSet = false; // We can only transform sra if the high bit is clear. 2930 break; 2931 case ISD::AND: 2932 HighBitSet = true; // We can only transform sra if the high bit is set. 2933 break; 2934 case ISD::ADD: 2935 if (N->getOpcode() != ISD::SHL) 2936 return SDValue(); // only shl(add) not sr[al](add). 2937 HighBitSet = false; // We can only transform sra if the high bit is clear. 2938 break; 2939 } 2940 2941 // We require the RHS of the binop to be a constant as well. 2942 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2943 if (!BinOpCst) return SDValue(); 2944 2945 // FIXME: disable this unless the input to the binop is a shift by a constant. 2946 // If it is not a shift, it pessimizes some common cases like: 2947 // 2948 // void foo(int *X, int i) { X[i & 1235] = 1; } 2949 // int bar(int *X, int i) { return X[i & 255]; } 2950 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2951 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2952 BinOpLHSVal->getOpcode() != ISD::SRA && 2953 BinOpLHSVal->getOpcode() != ISD::SRL) || 2954 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2955 return SDValue(); 2956 2957 EVT VT = N->getValueType(0); 2958 2959 // If this is a signed shift right, and the high bit is modified by the 2960 // logical operation, do not perform the transformation. The highBitSet 2961 // boolean indicates the value of the high bit of the constant which would 2962 // cause it to be modified for this operation. 2963 if (N->getOpcode() == ISD::SRA) { 2964 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2965 if (BinOpRHSSignSet != HighBitSet) 2966 return SDValue(); 2967 } 2968 2969 // Fold the constants, shifting the binop RHS by the shift amount. 2970 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2971 N->getValueType(0), 2972 LHS->getOperand(1), N->getOperand(1)); 2973 2974 // Create the new shift. 2975 SDValue NewShift = DAG.getNode(N->getOpcode(), 2976 LHS->getOperand(0).getDebugLoc(), 2977 VT, LHS->getOperand(0), N->getOperand(1)); 2978 2979 // Create the new binop. 2980 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2981} 2982 2983SDValue DAGCombiner::visitSHL(SDNode *N) { 2984 SDValue N0 = N->getOperand(0); 2985 SDValue N1 = N->getOperand(1); 2986 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2987 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2988 EVT VT = N0.getValueType(); 2989 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2990 2991 // fold (shl c1, c2) -> c1<<c2 2992 if (N0C && N1C) 2993 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2994 // fold (shl 0, x) -> 0 2995 if (N0C && N0C->isNullValue()) 2996 return N0; 2997 // fold (shl x, c >= size(x)) -> undef 2998 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2999 return DAG.getUNDEF(VT); 3000 // fold (shl x, 0) -> x 3001 if (N1C && N1C->isNullValue()) 3002 return N0; 3003 // if (shl x, c) is known to be zero, return 0 3004 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3005 APInt::getAllOnesValue(OpSizeInBits))) 3006 return DAG.getConstant(0, VT); 3007 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3008 if (N1.getOpcode() == ISD::TRUNCATE && 3009 N1.getOperand(0).getOpcode() == ISD::AND && 3010 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3011 SDValue N101 = N1.getOperand(0).getOperand(1); 3012 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3013 EVT TruncVT = N1.getValueType(); 3014 SDValue N100 = N1.getOperand(0).getOperand(0); 3015 APInt TruncC = N101C->getAPIntValue(); 3016 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3017 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3018 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3019 DAG.getNode(ISD::TRUNCATE, 3020 N->getDebugLoc(), 3021 TruncVT, N100), 3022 DAG.getConstant(TruncC, TruncVT))); 3023 } 3024 } 3025 3026 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3027 return SDValue(N, 0); 3028 3029 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3030 if (N1C && N0.getOpcode() == ISD::SHL && 3031 N0.getOperand(1).getOpcode() == ISD::Constant) { 3032 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3033 uint64_t c2 = N1C->getZExtValue(); 3034 if (c1 + c2 >= OpSizeInBits) 3035 return DAG.getConstant(0, VT); 3036 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3037 DAG.getConstant(c1 + c2, N1.getValueType())); 3038 } 3039 3040 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3041 // For this to be valid, the second form must not preserve any of the bits 3042 // that are shifted out by the inner shift in the first form. This means 3043 // the outer shift size must be >= the number of bits added by the ext. 3044 // As a corollary, we don't care what kind of ext it is. 3045 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3046 N0.getOpcode() == ISD::ANY_EXTEND || 3047 N0.getOpcode() == ISD::SIGN_EXTEND) && 3048 N0.getOperand(0).getOpcode() == ISD::SHL && 3049 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3050 uint64_t c1 = 3051 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3052 uint64_t c2 = N1C->getZExtValue(); 3053 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3054 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3055 if (c2 >= OpSizeInBits - InnerShiftSize) { 3056 if (c1 + c2 >= OpSizeInBits) 3057 return DAG.getConstant(0, VT); 3058 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3059 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3060 N0.getOperand(0)->getOperand(0)), 3061 DAG.getConstant(c1 + c2, N1.getValueType())); 3062 } 3063 } 3064 3065 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 3066 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 3067 if (N1C && N0.getOpcode() == ISD::SRL && 3068 N0.getOperand(1).getOpcode() == ISD::Constant) { 3069 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3070 if (c1 < VT.getSizeInBits()) { 3071 uint64_t c2 = N1C->getZExtValue(); 3072 SDValue HiBitsMask = 3073 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3074 VT.getSizeInBits() - c1), 3075 VT); 3076 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 3077 N0.getOperand(0), 3078 HiBitsMask); 3079 if (c2 > c1) 3080 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 3081 DAG.getConstant(c2-c1, N1.getValueType())); 3082 else 3083 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 3084 DAG.getConstant(c1-c2, N1.getValueType())); 3085 } 3086 } 3087 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3088 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3089 SDValue HiBitsMask = 3090 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3091 VT.getSizeInBits() - 3092 N1C->getZExtValue()), 3093 VT); 3094 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3095 HiBitsMask); 3096 } 3097 3098 if (N1C) { 3099 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3100 if (NewSHL.getNode()) 3101 return NewSHL; 3102 } 3103 3104 return SDValue(); 3105} 3106 3107SDValue DAGCombiner::visitSRA(SDNode *N) { 3108 SDValue N0 = N->getOperand(0); 3109 SDValue N1 = N->getOperand(1); 3110 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3111 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3112 EVT VT = N0.getValueType(); 3113 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3114 3115 // fold (sra c1, c2) -> (sra c1, c2) 3116 if (N0C && N1C) 3117 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3118 // fold (sra 0, x) -> 0 3119 if (N0C && N0C->isNullValue()) 3120 return N0; 3121 // fold (sra -1, x) -> -1 3122 if (N0C && N0C->isAllOnesValue()) 3123 return N0; 3124 // fold (sra x, (setge c, size(x))) -> undef 3125 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3126 return DAG.getUNDEF(VT); 3127 // fold (sra x, 0) -> x 3128 if (N1C && N1C->isNullValue()) 3129 return N0; 3130 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3131 // sext_inreg. 3132 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3133 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3134 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3135 if (VT.isVector()) 3136 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3137 ExtVT, VT.getVectorNumElements()); 3138 if ((!LegalOperations || 3139 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3140 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3141 N0.getOperand(0), DAG.getValueType(ExtVT)); 3142 } 3143 3144 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3145 if (N1C && N0.getOpcode() == ISD::SRA) { 3146 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3147 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3148 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3149 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3150 DAG.getConstant(Sum, N1C->getValueType(0))); 3151 } 3152 } 3153 3154 // fold (sra (shl X, m), (sub result_size, n)) 3155 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3156 // result_size - n != m. 3157 // If truncate is free for the target sext(shl) is likely to result in better 3158 // code. 3159 if (N0.getOpcode() == ISD::SHL) { 3160 // Get the two constanst of the shifts, CN0 = m, CN = n. 3161 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3162 if (N01C && N1C) { 3163 // Determine what the truncate's result bitsize and type would be. 3164 EVT TruncVT = 3165 EVT::getIntegerVT(*DAG.getContext(), 3166 OpSizeInBits - N1C->getZExtValue()); 3167 // Determine the residual right-shift amount. 3168 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3169 3170 // If the shift is not a no-op (in which case this should be just a sign 3171 // extend already), the truncated to type is legal, sign_extend is legal 3172 // on that type, and the truncate to that type is both legal and free, 3173 // perform the transform. 3174 if ((ShiftAmt > 0) && 3175 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3176 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3177 TLI.isTruncateFree(VT, TruncVT)) { 3178 3179 SDValue Amt = DAG.getConstant(ShiftAmt, 3180 getShiftAmountTy(N0.getOperand(0).getValueType())); 3181 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3182 N0.getOperand(0), Amt); 3183 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3184 Shift); 3185 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3186 N->getValueType(0), Trunc); 3187 } 3188 } 3189 } 3190 3191 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3192 if (N1.getOpcode() == ISD::TRUNCATE && 3193 N1.getOperand(0).getOpcode() == ISD::AND && 3194 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3195 SDValue N101 = N1.getOperand(0).getOperand(1); 3196 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3197 EVT TruncVT = N1.getValueType(); 3198 SDValue N100 = N1.getOperand(0).getOperand(0); 3199 APInt TruncC = N101C->getAPIntValue(); 3200 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3201 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3202 DAG.getNode(ISD::AND, N->getDebugLoc(), 3203 TruncVT, 3204 DAG.getNode(ISD::TRUNCATE, 3205 N->getDebugLoc(), 3206 TruncVT, N100), 3207 DAG.getConstant(TruncC, TruncVT))); 3208 } 3209 } 3210 3211 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3212 // if c1 is equal to the number of bits the trunc removes 3213 if (N0.getOpcode() == ISD::TRUNCATE && 3214 (N0.getOperand(0).getOpcode() == ISD::SRL || 3215 N0.getOperand(0).getOpcode() == ISD::SRA) && 3216 N0.getOperand(0).hasOneUse() && 3217 N0.getOperand(0).getOperand(1).hasOneUse() && 3218 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3219 EVT LargeVT = N0.getOperand(0).getValueType(); 3220 ConstantSDNode *LargeShiftAmt = 3221 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3222 3223 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3224 LargeShiftAmt->getZExtValue()) { 3225 SDValue Amt = 3226 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3227 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3228 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3229 N0.getOperand(0).getOperand(0), Amt); 3230 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3231 } 3232 } 3233 3234 // Simplify, based on bits shifted out of the LHS. 3235 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3236 return SDValue(N, 0); 3237 3238 3239 // If the sign bit is known to be zero, switch this to a SRL. 3240 if (DAG.SignBitIsZero(N0)) 3241 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3242 3243 if (N1C) { 3244 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3245 if (NewSRA.getNode()) 3246 return NewSRA; 3247 } 3248 3249 return SDValue(); 3250} 3251 3252SDValue DAGCombiner::visitSRL(SDNode *N) { 3253 SDValue N0 = N->getOperand(0); 3254 SDValue N1 = N->getOperand(1); 3255 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3256 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3257 EVT VT = N0.getValueType(); 3258 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3259 3260 // fold (srl c1, c2) -> c1 >>u c2 3261 if (N0C && N1C) 3262 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3263 // fold (srl 0, x) -> 0 3264 if (N0C && N0C->isNullValue()) 3265 return N0; 3266 // fold (srl x, c >= size(x)) -> undef 3267 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3268 return DAG.getUNDEF(VT); 3269 // fold (srl x, 0) -> x 3270 if (N1C && N1C->isNullValue()) 3271 return N0; 3272 // if (srl x, c) is known to be zero, return 0 3273 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3274 APInt::getAllOnesValue(OpSizeInBits))) 3275 return DAG.getConstant(0, VT); 3276 3277 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3278 if (N1C && N0.getOpcode() == ISD::SRL && 3279 N0.getOperand(1).getOpcode() == ISD::Constant) { 3280 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3281 uint64_t c2 = N1C->getZExtValue(); 3282 if (c1 + c2 >= OpSizeInBits) 3283 return DAG.getConstant(0, VT); 3284 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3285 DAG.getConstant(c1 + c2, N1.getValueType())); 3286 } 3287 3288 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3289 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3290 N0.getOperand(0).getOpcode() == ISD::SRL && 3291 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3292 uint64_t c1 = 3293 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3294 uint64_t c2 = N1C->getZExtValue(); 3295 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3296 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3297 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3298 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3299 if (c1 + OpSizeInBits == InnerShiftSize) { 3300 if (c1 + c2 >= InnerShiftSize) 3301 return DAG.getConstant(0, VT); 3302 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3303 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3304 N0.getOperand(0)->getOperand(0), 3305 DAG.getConstant(c1 + c2, ShiftCountVT))); 3306 } 3307 } 3308 3309 // fold (srl (shl x, c), c) -> (and x, cst2) 3310 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3311 N0.getValueSizeInBits() <= 64) { 3312 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3313 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3314 DAG.getConstant(~0ULL >> ShAmt, VT)); 3315 } 3316 3317 3318 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3319 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3320 // Shifting in all undef bits? 3321 EVT SmallVT = N0.getOperand(0).getValueType(); 3322 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3323 return DAG.getUNDEF(VT); 3324 3325 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3326 uint64_t ShiftAmt = N1C->getZExtValue(); 3327 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3328 N0.getOperand(0), 3329 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3330 AddToWorkList(SmallShift.getNode()); 3331 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3332 } 3333 } 3334 3335 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3336 // bit, which is unmodified by sra. 3337 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3338 if (N0.getOpcode() == ISD::SRA) 3339 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3340 } 3341 3342 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3343 if (N1C && N0.getOpcode() == ISD::CTLZ && 3344 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3345 APInt KnownZero, KnownOne; 3346 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3347 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3348 3349 // If any of the input bits are KnownOne, then the input couldn't be all 3350 // zeros, thus the result of the srl will always be zero. 3351 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3352 3353 // If all of the bits input the to ctlz node are known to be zero, then 3354 // the result of the ctlz is "32" and the result of the shift is one. 3355 APInt UnknownBits = ~KnownZero & Mask; 3356 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3357 3358 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3359 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3360 // Okay, we know that only that the single bit specified by UnknownBits 3361 // could be set on input to the CTLZ node. If this bit is set, the SRL 3362 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3363 // to an SRL/XOR pair, which is likely to simplify more. 3364 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3365 SDValue Op = N0.getOperand(0); 3366 3367 if (ShAmt) { 3368 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3369 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3370 AddToWorkList(Op.getNode()); 3371 } 3372 3373 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3374 Op, DAG.getConstant(1, VT)); 3375 } 3376 } 3377 3378 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3379 if (N1.getOpcode() == ISD::TRUNCATE && 3380 N1.getOperand(0).getOpcode() == ISD::AND && 3381 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3382 SDValue N101 = N1.getOperand(0).getOperand(1); 3383 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3384 EVT TruncVT = N1.getValueType(); 3385 SDValue N100 = N1.getOperand(0).getOperand(0); 3386 APInt TruncC = N101C->getAPIntValue(); 3387 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3388 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3389 DAG.getNode(ISD::AND, N->getDebugLoc(), 3390 TruncVT, 3391 DAG.getNode(ISD::TRUNCATE, 3392 N->getDebugLoc(), 3393 TruncVT, N100), 3394 DAG.getConstant(TruncC, TruncVT))); 3395 } 3396 } 3397 3398 // fold operands of srl based on knowledge that the low bits are not 3399 // demanded. 3400 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3401 return SDValue(N, 0); 3402 3403 if (N1C) { 3404 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3405 if (NewSRL.getNode()) 3406 return NewSRL; 3407 } 3408 3409 // Attempt to convert a srl of a load into a narrower zero-extending load. 3410 SDValue NarrowLoad = ReduceLoadWidth(N); 3411 if (NarrowLoad.getNode()) 3412 return NarrowLoad; 3413 3414 // Here is a common situation. We want to optimize: 3415 // 3416 // %a = ... 3417 // %b = and i32 %a, 2 3418 // %c = srl i32 %b, 1 3419 // brcond i32 %c ... 3420 // 3421 // into 3422 // 3423 // %a = ... 3424 // %b = and %a, 2 3425 // %c = setcc eq %b, 0 3426 // brcond %c ... 3427 // 3428 // However when after the source operand of SRL is optimized into AND, the SRL 3429 // itself may not be optimized further. Look for it and add the BRCOND into 3430 // the worklist. 3431 if (N->hasOneUse()) { 3432 SDNode *Use = *N->use_begin(); 3433 if (Use->getOpcode() == ISD::BRCOND) 3434 AddToWorkList(Use); 3435 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3436 // Also look pass the truncate. 3437 Use = *Use->use_begin(); 3438 if (Use->getOpcode() == ISD::BRCOND) 3439 AddToWorkList(Use); 3440 } 3441 } 3442 3443 return SDValue(); 3444} 3445 3446SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3447 SDValue N0 = N->getOperand(0); 3448 EVT VT = N->getValueType(0); 3449 3450 // fold (ctlz c1) -> c2 3451 if (isa<ConstantSDNode>(N0)) 3452 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3453 return SDValue(); 3454} 3455 3456SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3457 SDValue N0 = N->getOperand(0); 3458 EVT VT = N->getValueType(0); 3459 3460 // fold (cttz c1) -> c2 3461 if (isa<ConstantSDNode>(N0)) 3462 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3463 return SDValue(); 3464} 3465 3466SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3467 SDValue N0 = N->getOperand(0); 3468 EVT VT = N->getValueType(0); 3469 3470 // fold (ctpop c1) -> c2 3471 if (isa<ConstantSDNode>(N0)) 3472 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3473 return SDValue(); 3474} 3475 3476SDValue DAGCombiner::visitSELECT(SDNode *N) { 3477 SDValue N0 = N->getOperand(0); 3478 SDValue N1 = N->getOperand(1); 3479 SDValue N2 = N->getOperand(2); 3480 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3481 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3482 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3483 EVT VT = N->getValueType(0); 3484 EVT VT0 = N0.getValueType(); 3485 3486 // fold (select C, X, X) -> X 3487 if (N1 == N2) 3488 return N1; 3489 // fold (select true, X, Y) -> X 3490 if (N0C && !N0C->isNullValue()) 3491 return N1; 3492 // fold (select false, X, Y) -> Y 3493 if (N0C && N0C->isNullValue()) 3494 return N2; 3495 // fold (select C, 1, X) -> (or C, X) 3496 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3497 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3498 // fold (select C, 0, 1) -> (xor C, 1) 3499 if (VT.isInteger() && 3500 (VT0 == MVT::i1 || 3501 (VT0.isInteger() && 3502 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3503 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3504 SDValue XORNode; 3505 if (VT == VT0) 3506 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3507 N0, DAG.getConstant(1, VT0)); 3508 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3509 N0, DAG.getConstant(1, VT0)); 3510 AddToWorkList(XORNode.getNode()); 3511 if (VT.bitsGT(VT0)) 3512 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3513 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3514 } 3515 // fold (select C, 0, X) -> (and (not C), X) 3516 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3517 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3518 AddToWorkList(NOTNode.getNode()); 3519 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3520 } 3521 // fold (select C, X, 1) -> (or (not C), X) 3522 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3523 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3524 AddToWorkList(NOTNode.getNode()); 3525 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3526 } 3527 // fold (select C, X, 0) -> (and C, X) 3528 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3529 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3530 // fold (select X, X, Y) -> (or X, Y) 3531 // fold (select X, 1, Y) -> (or X, Y) 3532 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3533 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3534 // fold (select X, Y, X) -> (and X, Y) 3535 // fold (select X, Y, 0) -> (and X, Y) 3536 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3537 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3538 3539 // If we can fold this based on the true/false value, do so. 3540 if (SimplifySelectOps(N, N1, N2)) 3541 return SDValue(N, 0); // Don't revisit N. 3542 3543 // fold selects based on a setcc into other things, such as min/max/abs 3544 if (N0.getOpcode() == ISD::SETCC) { 3545 // FIXME: 3546 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3547 // having to say they don't support SELECT_CC on every type the DAG knows 3548 // about, since there is no way to mark an opcode illegal at all value types 3549 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3550 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3551 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3552 N0.getOperand(0), N0.getOperand(1), 3553 N1, N2, N0.getOperand(2)); 3554 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3555 } 3556 3557 return SDValue(); 3558} 3559 3560SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3561 SDValue N0 = N->getOperand(0); 3562 SDValue N1 = N->getOperand(1); 3563 SDValue N2 = N->getOperand(2); 3564 SDValue N3 = N->getOperand(3); 3565 SDValue N4 = N->getOperand(4); 3566 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3567 3568 // fold select_cc lhs, rhs, x, x, cc -> x 3569 if (N2 == N3) 3570 return N2; 3571 3572 // Determine if the condition we're dealing with is constant 3573 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3574 N0, N1, CC, N->getDebugLoc(), false); 3575 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3576 3577 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3578 if (!SCCC->isNullValue()) 3579 return N2; // cond always true -> true val 3580 else 3581 return N3; // cond always false -> false val 3582 } 3583 3584 // Fold to a simpler select_cc 3585 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3586 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3587 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3588 SCC.getOperand(2)); 3589 3590 // If we can fold this based on the true/false value, do so. 3591 if (SimplifySelectOps(N, N2, N3)) 3592 return SDValue(N, 0); // Don't revisit N. 3593 3594 // fold select_cc into other things, such as min/max/abs 3595 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3596} 3597 3598SDValue DAGCombiner::visitSETCC(SDNode *N) { 3599 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3600 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3601 N->getDebugLoc()); 3602} 3603 3604// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3605// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3606// transformation. Returns true if extension are possible and the above 3607// mentioned transformation is profitable. 3608static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3609 unsigned ExtOpc, 3610 SmallVector<SDNode*, 4> &ExtendNodes, 3611 const TargetLowering &TLI) { 3612 bool HasCopyToRegUses = false; 3613 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3614 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3615 UE = N0.getNode()->use_end(); 3616 UI != UE; ++UI) { 3617 SDNode *User = *UI; 3618 if (User == N) 3619 continue; 3620 if (UI.getUse().getResNo() != N0.getResNo()) 3621 continue; 3622 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3623 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3624 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3625 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3626 // Sign bits will be lost after a zext. 3627 return false; 3628 bool Add = false; 3629 for (unsigned i = 0; i != 2; ++i) { 3630 SDValue UseOp = User->getOperand(i); 3631 if (UseOp == N0) 3632 continue; 3633 if (!isa<ConstantSDNode>(UseOp)) 3634 return false; 3635 Add = true; 3636 } 3637 if (Add) 3638 ExtendNodes.push_back(User); 3639 continue; 3640 } 3641 // If truncates aren't free and there are users we can't 3642 // extend, it isn't worthwhile. 3643 if (!isTruncFree) 3644 return false; 3645 // Remember if this value is live-out. 3646 if (User->getOpcode() == ISD::CopyToReg) 3647 HasCopyToRegUses = true; 3648 } 3649 3650 if (HasCopyToRegUses) { 3651 bool BothLiveOut = false; 3652 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3653 UI != UE; ++UI) { 3654 SDUse &Use = UI.getUse(); 3655 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3656 BothLiveOut = true; 3657 break; 3658 } 3659 } 3660 if (BothLiveOut) 3661 // Both unextended and extended values are live out. There had better be 3662 // a good reason for the transformation. 3663 return ExtendNodes.size(); 3664 } 3665 return true; 3666} 3667 3668SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3669 SDValue N0 = N->getOperand(0); 3670 EVT VT = N->getValueType(0); 3671 3672 // fold (sext c1) -> c1 3673 if (isa<ConstantSDNode>(N0)) 3674 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3675 3676 // fold (sext (sext x)) -> (sext x) 3677 // fold (sext (aext x)) -> (sext x) 3678 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3679 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3680 N0.getOperand(0)); 3681 3682 if (N0.getOpcode() == ISD::TRUNCATE) { 3683 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3684 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3685 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3686 if (NarrowLoad.getNode()) { 3687 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3688 if (NarrowLoad.getNode() != N0.getNode()) { 3689 CombineTo(N0.getNode(), NarrowLoad); 3690 // CombineTo deleted the truncate, if needed, but not what's under it. 3691 AddToWorkList(oye); 3692 } 3693 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3694 } 3695 3696 // See if the value being truncated is already sign extended. If so, just 3697 // eliminate the trunc/sext pair. 3698 SDValue Op = N0.getOperand(0); 3699 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3700 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3701 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3702 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3703 3704 if (OpBits == DestBits) { 3705 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3706 // bits, it is already ready. 3707 if (NumSignBits > DestBits-MidBits) 3708 return Op; 3709 } else if (OpBits < DestBits) { 3710 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3711 // bits, just sext from i32. 3712 if (NumSignBits > OpBits-MidBits) 3713 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3714 } else { 3715 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3716 // bits, just truncate to i32. 3717 if (NumSignBits > OpBits-MidBits) 3718 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3719 } 3720 3721 // fold (sext (truncate x)) -> (sextinreg x). 3722 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3723 N0.getValueType())) { 3724 if (OpBits < DestBits) 3725 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3726 else if (OpBits > DestBits) 3727 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3728 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3729 DAG.getValueType(N0.getValueType())); 3730 } 3731 } 3732 3733 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3734 // None of the supported targets knows how to perform load and sign extend 3735 // on vectors in one instruction. We only perform this transformation on 3736 // scalars. 3737 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 3738 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3739 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3740 bool DoXform = true; 3741 SmallVector<SDNode*, 4> SetCCs; 3742 if (!N0.hasOneUse()) 3743 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3744 if (DoXform) { 3745 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3746 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3747 LN0->getChain(), 3748 LN0->getBasePtr(), LN0->getPointerInfo(), 3749 N0.getValueType(), 3750 LN0->isVolatile(), LN0->isNonTemporal(), 3751 LN0->getAlignment()); 3752 CombineTo(N, ExtLoad); 3753 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3754 N0.getValueType(), ExtLoad); 3755 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3756 3757 // Extend SetCC uses if necessary. 3758 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3759 SDNode *SetCC = SetCCs[i]; 3760 SmallVector<SDValue, 4> Ops; 3761 3762 for (unsigned j = 0; j != 2; ++j) { 3763 SDValue SOp = SetCC->getOperand(j); 3764 if (SOp == Trunc) 3765 Ops.push_back(ExtLoad); 3766 else 3767 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3768 N->getDebugLoc(), VT, SOp)); 3769 } 3770 3771 Ops.push_back(SetCC->getOperand(2)); 3772 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3773 SetCC->getValueType(0), 3774 &Ops[0], Ops.size())); 3775 } 3776 3777 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3778 } 3779 } 3780 3781 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3782 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3783 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3784 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3785 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3786 EVT MemVT = LN0->getMemoryVT(); 3787 if ((!LegalOperations && !LN0->isVolatile()) || 3788 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3789 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3790 LN0->getChain(), 3791 LN0->getBasePtr(), LN0->getPointerInfo(), 3792 MemVT, 3793 LN0->isVolatile(), LN0->isNonTemporal(), 3794 LN0->getAlignment()); 3795 CombineTo(N, ExtLoad); 3796 CombineTo(N0.getNode(), 3797 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3798 N0.getValueType(), ExtLoad), 3799 ExtLoad.getValue(1)); 3800 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3801 } 3802 } 3803 3804 if (N0.getOpcode() == ISD::SETCC) { 3805 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3806 // Only do this before legalize for now. 3807 if (VT.isVector() && !LegalOperations) { 3808 EVT N0VT = N0.getOperand(0).getValueType(); 3809 // We know that the # elements of the results is the same as the 3810 // # elements of the compare (and the # elements of the compare result 3811 // for that matter). Check to see that they are the same size. If so, 3812 // we know that the element size of the sext'd result matches the 3813 // element size of the compare operands. 3814 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3815 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3816 N0.getOperand(1), 3817 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3818 // If the desired elements are smaller or larger than the source 3819 // elements we can use a matching integer vector type and then 3820 // truncate/sign extend 3821 else { 3822 EVT MatchingElementType = 3823 EVT::getIntegerVT(*DAG.getContext(), 3824 N0VT.getScalarType().getSizeInBits()); 3825 EVT MatchingVectorType = 3826 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3827 N0VT.getVectorNumElements()); 3828 SDValue VsetCC = 3829 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3830 N0.getOperand(1), 3831 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3832 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3833 } 3834 } 3835 3836 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3837 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3838 SDValue NegOne = 3839 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3840 SDValue SCC = 3841 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3842 NegOne, DAG.getConstant(0, VT), 3843 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3844 if (SCC.getNode()) return SCC; 3845 if (!LegalOperations || 3846 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3847 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3848 DAG.getSetCC(N->getDebugLoc(), 3849 TLI.getSetCCResultType(VT), 3850 N0.getOperand(0), N0.getOperand(1), 3851 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3852 NegOne, DAG.getConstant(0, VT)); 3853 } 3854 3855 // fold (sext x) -> (zext x) if the sign bit is known zero. 3856 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3857 DAG.SignBitIsZero(N0)) 3858 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3859 3860 return SDValue(); 3861} 3862 3863SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3864 SDValue N0 = N->getOperand(0); 3865 EVT VT = N->getValueType(0); 3866 3867 // fold (zext c1) -> c1 3868 if (isa<ConstantSDNode>(N0)) 3869 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3870 // fold (zext (zext x)) -> (zext x) 3871 // fold (zext (aext x)) -> (zext x) 3872 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3873 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3874 N0.getOperand(0)); 3875 3876 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3877 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3878 if (N0.getOpcode() == ISD::TRUNCATE) { 3879 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3880 if (NarrowLoad.getNode()) { 3881 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3882 if (NarrowLoad.getNode() != N0.getNode()) { 3883 CombineTo(N0.getNode(), NarrowLoad); 3884 // CombineTo deleted the truncate, if needed, but not what's under it. 3885 AddToWorkList(oye); 3886 } 3887 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3888 } 3889 } 3890 3891 // fold (zext (truncate x)) -> (and x, mask) 3892 if (N0.getOpcode() == ISD::TRUNCATE && 3893 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3894 3895 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3896 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 3897 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3898 if (NarrowLoad.getNode()) { 3899 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3900 if (NarrowLoad.getNode() != N0.getNode()) { 3901 CombineTo(N0.getNode(), NarrowLoad); 3902 // CombineTo deleted the truncate, if needed, but not what's under it. 3903 AddToWorkList(oye); 3904 } 3905 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3906 } 3907 3908 SDValue Op = N0.getOperand(0); 3909 if (Op.getValueType().bitsLT(VT)) { 3910 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3911 } else if (Op.getValueType().bitsGT(VT)) { 3912 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3913 } 3914 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3915 N0.getValueType().getScalarType()); 3916 } 3917 3918 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3919 // if either of the casts is not free. 3920 if (N0.getOpcode() == ISD::AND && 3921 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3922 N0.getOperand(1).getOpcode() == ISD::Constant && 3923 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3924 N0.getValueType()) || 3925 !TLI.isZExtFree(N0.getValueType(), VT))) { 3926 SDValue X = N0.getOperand(0).getOperand(0); 3927 if (X.getValueType().bitsLT(VT)) { 3928 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3929 } else if (X.getValueType().bitsGT(VT)) { 3930 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3931 } 3932 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3933 Mask = Mask.zext(VT.getSizeInBits()); 3934 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3935 X, DAG.getConstant(Mask, VT)); 3936 } 3937 3938 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3939 // None of the supported targets knows how to perform load and vector_zext 3940 // on vectors in one instruction. We only perform this transformation on 3941 // scalars. 3942 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 3943 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3944 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3945 bool DoXform = true; 3946 SmallVector<SDNode*, 4> SetCCs; 3947 if (!N0.hasOneUse()) 3948 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3949 if (DoXform) { 3950 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3951 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3952 LN0->getChain(), 3953 LN0->getBasePtr(), LN0->getPointerInfo(), 3954 N0.getValueType(), 3955 LN0->isVolatile(), LN0->isNonTemporal(), 3956 LN0->getAlignment()); 3957 CombineTo(N, ExtLoad); 3958 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3959 N0.getValueType(), ExtLoad); 3960 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3961 3962 // Extend SetCC uses if necessary. 3963 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3964 SDNode *SetCC = SetCCs[i]; 3965 SmallVector<SDValue, 4> Ops; 3966 3967 for (unsigned j = 0; j != 2; ++j) { 3968 SDValue SOp = SetCC->getOperand(j); 3969 if (SOp == Trunc) 3970 Ops.push_back(ExtLoad); 3971 else 3972 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3973 N->getDebugLoc(), VT, SOp)); 3974 } 3975 3976 Ops.push_back(SetCC->getOperand(2)); 3977 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3978 SetCC->getValueType(0), 3979 &Ops[0], Ops.size())); 3980 } 3981 3982 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3983 } 3984 } 3985 3986 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3987 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3988 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3989 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3990 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3991 EVT MemVT = LN0->getMemoryVT(); 3992 if ((!LegalOperations && !LN0->isVolatile()) || 3993 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3994 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3995 LN0->getChain(), 3996 LN0->getBasePtr(), LN0->getPointerInfo(), 3997 MemVT, 3998 LN0->isVolatile(), LN0->isNonTemporal(), 3999 LN0->getAlignment()); 4000 CombineTo(N, ExtLoad); 4001 CombineTo(N0.getNode(), 4002 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4003 ExtLoad), 4004 ExtLoad.getValue(1)); 4005 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4006 } 4007 } 4008 4009 if (N0.getOpcode() == ISD::SETCC) { 4010 if (!LegalOperations && VT.isVector()) { 4011 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4012 // Only do this before legalize for now. 4013 EVT N0VT = N0.getOperand(0).getValueType(); 4014 EVT EltVT = VT.getVectorElementType(); 4015 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4016 DAG.getConstant(1, EltVT)); 4017 if (VT.getSizeInBits() == N0VT.getSizeInBits()) { 4018 // We know that the # elements of the results is the same as the 4019 // # elements of the compare (and the # elements of the compare result 4020 // for that matter). Check to see that they are the same size. If so, 4021 // we know that the element size of the sext'd result matches the 4022 // element size of the compare operands. 4023 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4024 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4025 N0.getOperand(1), 4026 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4027 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4028 &OneOps[0], OneOps.size())); 4029 } else { 4030 // If the desired elements are smaller or larger than the source 4031 // elements we can use a matching integer vector type and then 4032 // truncate/sign extend 4033 EVT MatchingElementType = 4034 EVT::getIntegerVT(*DAG.getContext(), 4035 N0VT.getScalarType().getSizeInBits()); 4036 EVT MatchingVectorType = 4037 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4038 N0VT.getVectorNumElements()); 4039 SDValue VsetCC = 4040 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4041 N0.getOperand(1), 4042 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4043 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4044 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4045 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4046 &OneOps[0], OneOps.size())); 4047 } 4048 } 4049 4050 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4051 SDValue SCC = 4052 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4053 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4054 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4055 if (SCC.getNode()) return SCC; 4056 } 4057 4058 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4059 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4060 isa<ConstantSDNode>(N0.getOperand(1)) && 4061 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4062 N0.hasOneUse()) { 4063 SDValue ShAmt = N0.getOperand(1); 4064 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4065 if (N0.getOpcode() == ISD::SHL) { 4066 SDValue InnerZExt = N0.getOperand(0); 4067 // If the original shl may be shifting out bits, do not perform this 4068 // transformation. 4069 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4070 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4071 if (ShAmtVal > KnownZeroBits) 4072 return SDValue(); 4073 } 4074 4075 DebugLoc DL = N->getDebugLoc(); 4076 4077 // Ensure that the shift amount is wide enough for the shifted value. 4078 if (VT.getSizeInBits() >= 256) 4079 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4080 4081 return DAG.getNode(N0.getOpcode(), DL, VT, 4082 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4083 ShAmt); 4084 } 4085 4086 return SDValue(); 4087} 4088 4089SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4090 SDValue N0 = N->getOperand(0); 4091 EVT VT = N->getValueType(0); 4092 4093 // fold (aext c1) -> c1 4094 if (isa<ConstantSDNode>(N0)) 4095 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4096 // fold (aext (aext x)) -> (aext x) 4097 // fold (aext (zext x)) -> (zext x) 4098 // fold (aext (sext x)) -> (sext x) 4099 if (N0.getOpcode() == ISD::ANY_EXTEND || 4100 N0.getOpcode() == ISD::ZERO_EXTEND || 4101 N0.getOpcode() == ISD::SIGN_EXTEND) 4102 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4103 4104 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4105 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4106 if (N0.getOpcode() == ISD::TRUNCATE) { 4107 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4108 if (NarrowLoad.getNode()) { 4109 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4110 if (NarrowLoad.getNode() != N0.getNode()) { 4111 CombineTo(N0.getNode(), NarrowLoad); 4112 // CombineTo deleted the truncate, if needed, but not what's under it. 4113 AddToWorkList(oye); 4114 } 4115 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4116 } 4117 } 4118 4119 // fold (aext (truncate x)) 4120 if (N0.getOpcode() == ISD::TRUNCATE) { 4121 SDValue TruncOp = N0.getOperand(0); 4122 if (TruncOp.getValueType() == VT) 4123 return TruncOp; // x iff x size == zext size. 4124 if (TruncOp.getValueType().bitsGT(VT)) 4125 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4126 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4127 } 4128 4129 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4130 // if the trunc is not free. 4131 if (N0.getOpcode() == ISD::AND && 4132 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4133 N0.getOperand(1).getOpcode() == ISD::Constant && 4134 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4135 N0.getValueType())) { 4136 SDValue X = N0.getOperand(0).getOperand(0); 4137 if (X.getValueType().bitsLT(VT)) { 4138 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4139 } else if (X.getValueType().bitsGT(VT)) { 4140 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4141 } 4142 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4143 Mask = Mask.zext(VT.getSizeInBits()); 4144 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4145 X, DAG.getConstant(Mask, VT)); 4146 } 4147 4148 // fold (aext (load x)) -> (aext (truncate (extload x))) 4149 // None of the supported targets knows how to perform load and any_ext 4150 // on vectors in one instruction. We only perform this transformation on 4151 // scalars. 4152 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4153 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4154 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4155 bool DoXform = true; 4156 SmallVector<SDNode*, 4> SetCCs; 4157 if (!N0.hasOneUse()) 4158 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4159 if (DoXform) { 4160 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4161 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4162 LN0->getChain(), 4163 LN0->getBasePtr(), LN0->getPointerInfo(), 4164 N0.getValueType(), 4165 LN0->isVolatile(), LN0->isNonTemporal(), 4166 LN0->getAlignment()); 4167 CombineTo(N, ExtLoad); 4168 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4169 N0.getValueType(), ExtLoad); 4170 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4171 4172 // Extend SetCC uses if necessary. 4173 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4174 SDNode *SetCC = SetCCs[i]; 4175 SmallVector<SDValue, 4> Ops; 4176 4177 for (unsigned j = 0; j != 2; ++j) { 4178 SDValue SOp = SetCC->getOperand(j); 4179 if (SOp == Trunc) 4180 Ops.push_back(ExtLoad); 4181 else 4182 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 4183 N->getDebugLoc(), VT, SOp)); 4184 } 4185 4186 Ops.push_back(SetCC->getOperand(2)); 4187 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 4188 SetCC->getValueType(0), 4189 &Ops[0], Ops.size())); 4190 } 4191 4192 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4193 } 4194 } 4195 4196 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4197 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4198 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4199 if (N0.getOpcode() == ISD::LOAD && 4200 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4201 N0.hasOneUse()) { 4202 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4203 EVT MemVT = LN0->getMemoryVT(); 4204 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4205 VT, LN0->getChain(), LN0->getBasePtr(), 4206 LN0->getPointerInfo(), MemVT, 4207 LN0->isVolatile(), LN0->isNonTemporal(), 4208 LN0->getAlignment()); 4209 CombineTo(N, ExtLoad); 4210 CombineTo(N0.getNode(), 4211 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4212 N0.getValueType(), ExtLoad), 4213 ExtLoad.getValue(1)); 4214 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4215 } 4216 4217 if (N0.getOpcode() == ISD::SETCC) { 4218 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4219 // Only do this before legalize for now. 4220 if (VT.isVector() && !LegalOperations) { 4221 EVT N0VT = N0.getOperand(0).getValueType(); 4222 // We know that the # elements of the results is the same as the 4223 // # elements of the compare (and the # elements of the compare result 4224 // for that matter). Check to see that they are the same size. If so, 4225 // we know that the element size of the sext'd result matches the 4226 // element size of the compare operands. 4227 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4228 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4229 N0.getOperand(1), 4230 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4231 // If the desired elements are smaller or larger than the source 4232 // elements we can use a matching integer vector type and then 4233 // truncate/sign extend 4234 else { 4235 EVT MatchingElementType = 4236 EVT::getIntegerVT(*DAG.getContext(), 4237 N0VT.getScalarType().getSizeInBits()); 4238 EVT MatchingVectorType = 4239 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4240 N0VT.getVectorNumElements()); 4241 SDValue VsetCC = 4242 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4243 N0.getOperand(1), 4244 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4245 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4246 } 4247 } 4248 4249 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4250 SDValue SCC = 4251 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4252 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4253 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4254 if (SCC.getNode()) 4255 return SCC; 4256 } 4257 4258 return SDValue(); 4259} 4260 4261/// GetDemandedBits - See if the specified operand can be simplified with the 4262/// knowledge that only the bits specified by Mask are used. If so, return the 4263/// simpler operand, otherwise return a null SDValue. 4264SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4265 switch (V.getOpcode()) { 4266 default: break; 4267 case ISD::OR: 4268 case ISD::XOR: 4269 // If the LHS or RHS don't contribute bits to the or, drop them. 4270 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4271 return V.getOperand(1); 4272 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4273 return V.getOperand(0); 4274 break; 4275 case ISD::SRL: 4276 // Only look at single-use SRLs. 4277 if (!V.getNode()->hasOneUse()) 4278 break; 4279 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4280 // See if we can recursively simplify the LHS. 4281 unsigned Amt = RHSC->getZExtValue(); 4282 4283 // Watch out for shift count overflow though. 4284 if (Amt >= Mask.getBitWidth()) break; 4285 APInt NewMask = Mask << Amt; 4286 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4287 if (SimplifyLHS.getNode()) 4288 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4289 SimplifyLHS, V.getOperand(1)); 4290 } 4291 } 4292 return SDValue(); 4293} 4294 4295/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4296/// bits and then truncated to a narrower type and where N is a multiple 4297/// of number of bits of the narrower type, transform it to a narrower load 4298/// from address + N / num of bits of new type. If the result is to be 4299/// extended, also fold the extension to form a extending load. 4300SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4301 unsigned Opc = N->getOpcode(); 4302 4303 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4304 SDValue N0 = N->getOperand(0); 4305 EVT VT = N->getValueType(0); 4306 EVT ExtVT = VT; 4307 4308 // This transformation isn't valid for vector loads. 4309 if (VT.isVector()) 4310 return SDValue(); 4311 4312 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4313 // extended to VT. 4314 if (Opc == ISD::SIGN_EXTEND_INREG) { 4315 ExtType = ISD::SEXTLOAD; 4316 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4317 } else if (Opc == ISD::SRL) { 4318 // Another special-case: SRL is basically zero-extending a narrower value. 4319 ExtType = ISD::ZEXTLOAD; 4320 N0 = SDValue(N, 0); 4321 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4322 if (!N01) return SDValue(); 4323 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4324 VT.getSizeInBits() - N01->getZExtValue()); 4325 } 4326 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4327 return SDValue(); 4328 4329 unsigned EVTBits = ExtVT.getSizeInBits(); 4330 4331 // Do not generate loads of non-round integer types since these can 4332 // be expensive (and would be wrong if the type is not byte sized). 4333 if (!ExtVT.isRound()) 4334 return SDValue(); 4335 4336 unsigned ShAmt = 0; 4337 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4338 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4339 ShAmt = N01->getZExtValue(); 4340 // Is the shift amount a multiple of size of VT? 4341 if ((ShAmt & (EVTBits-1)) == 0) { 4342 N0 = N0.getOperand(0); 4343 // Is the load width a multiple of size of VT? 4344 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4345 return SDValue(); 4346 } 4347 4348 // At this point, we must have a load or else we can't do the transform. 4349 if (!isa<LoadSDNode>(N0)) return SDValue(); 4350 4351 // If the shift amount is larger than the input type then we're not 4352 // accessing any of the loaded bytes. If the load was a zextload/extload 4353 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4354 // If the load was a sextload then the result is a splat of the sign bit 4355 // of the extended byte. This is not worth optimizing for. 4356 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4357 return SDValue(); 4358 } 4359 } 4360 4361 // If the load is shifted left (and the result isn't shifted back right), 4362 // we can fold the truncate through the shift. 4363 unsigned ShLeftAmt = 0; 4364 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4365 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4366 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4367 ShLeftAmt = N01->getZExtValue(); 4368 N0 = N0.getOperand(0); 4369 } 4370 } 4371 4372 // If we haven't found a load, we can't narrow it. Don't transform one with 4373 // multiple uses, this would require adding a new load. 4374 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4375 // Don't change the width of a volatile load. 4376 cast<LoadSDNode>(N0)->isVolatile()) 4377 return SDValue(); 4378 4379 // Verify that we are actually reducing a load width here. 4380 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4381 return SDValue(); 4382 4383 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4384 EVT PtrType = N0.getOperand(1).getValueType(); 4385 4386 // For big endian targets, we need to adjust the offset to the pointer to 4387 // load the correct bytes. 4388 if (TLI.isBigEndian()) { 4389 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4390 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4391 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4392 } 4393 4394 uint64_t PtrOff = ShAmt / 8; 4395 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4396 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4397 PtrType, LN0->getBasePtr(), 4398 DAG.getConstant(PtrOff, PtrType)); 4399 AddToWorkList(NewPtr.getNode()); 4400 4401 SDValue Load; 4402 if (ExtType == ISD::NON_EXTLOAD) 4403 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4404 LN0->getPointerInfo().getWithOffset(PtrOff), 4405 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign); 4406 else 4407 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4408 LN0->getPointerInfo().getWithOffset(PtrOff), 4409 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4410 NewAlign); 4411 4412 // Replace the old load's chain with the new load's chain. 4413 WorkListRemover DeadNodes(*this); 4414 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4415 &DeadNodes); 4416 4417 // Shift the result left, if we've swallowed a left shift. 4418 SDValue Result = Load; 4419 if (ShLeftAmt != 0) { 4420 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 4421 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4422 ShImmTy = VT; 4423 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4424 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4425 } 4426 4427 // Return the new loaded value. 4428 return Result; 4429} 4430 4431SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4432 SDValue N0 = N->getOperand(0); 4433 SDValue N1 = N->getOperand(1); 4434 EVT VT = N->getValueType(0); 4435 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4436 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4437 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4438 4439 // fold (sext_in_reg c1) -> c1 4440 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4441 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4442 4443 // If the input is already sign extended, just drop the extension. 4444 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4445 return N0; 4446 4447 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4448 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4449 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4450 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4451 N0.getOperand(0), N1); 4452 } 4453 4454 // fold (sext_in_reg (sext x)) -> (sext x) 4455 // fold (sext_in_reg (aext x)) -> (sext x) 4456 // if x is small enough. 4457 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4458 SDValue N00 = N0.getOperand(0); 4459 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4460 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4461 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4462 } 4463 4464 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4465 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4466 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4467 4468 // fold operands of sext_in_reg based on knowledge that the top bits are not 4469 // demanded. 4470 if (SimplifyDemandedBits(SDValue(N, 0))) 4471 return SDValue(N, 0); 4472 4473 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4474 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4475 SDValue NarrowLoad = ReduceLoadWidth(N); 4476 if (NarrowLoad.getNode()) 4477 return NarrowLoad; 4478 4479 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4480 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4481 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4482 if (N0.getOpcode() == ISD::SRL) { 4483 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4484 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4485 // We can turn this into an SRA iff the input to the SRL is already sign 4486 // extended enough. 4487 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4488 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4489 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4490 N0.getOperand(0), N0.getOperand(1)); 4491 } 4492 } 4493 4494 // fold (sext_inreg (extload x)) -> (sextload x) 4495 if (ISD::isEXTLoad(N0.getNode()) && 4496 ISD::isUNINDEXEDLoad(N0.getNode()) && 4497 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4498 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4499 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4500 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4501 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4502 LN0->getChain(), 4503 LN0->getBasePtr(), LN0->getPointerInfo(), 4504 EVT, 4505 LN0->isVolatile(), LN0->isNonTemporal(), 4506 LN0->getAlignment()); 4507 CombineTo(N, ExtLoad); 4508 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4509 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4510 } 4511 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4512 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4513 N0.hasOneUse() && 4514 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4515 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4516 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4517 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4518 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4519 LN0->getChain(), 4520 LN0->getBasePtr(), LN0->getPointerInfo(), 4521 EVT, 4522 LN0->isVolatile(), LN0->isNonTemporal(), 4523 LN0->getAlignment()); 4524 CombineTo(N, ExtLoad); 4525 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4526 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4527 } 4528 return SDValue(); 4529} 4530 4531SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4532 SDValue N0 = N->getOperand(0); 4533 EVT VT = N->getValueType(0); 4534 4535 // noop truncate 4536 if (N0.getValueType() == N->getValueType(0)) 4537 return N0; 4538 // fold (truncate c1) -> c1 4539 if (isa<ConstantSDNode>(N0)) 4540 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4541 // fold (truncate (truncate x)) -> (truncate x) 4542 if (N0.getOpcode() == ISD::TRUNCATE) 4543 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4544 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4545 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4546 N0.getOpcode() == ISD::SIGN_EXTEND || 4547 N0.getOpcode() == ISD::ANY_EXTEND) { 4548 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4549 // if the source is smaller than the dest, we still need an extend 4550 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4551 N0.getOperand(0)); 4552 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4553 // if the source is larger than the dest, than we just need the truncate 4554 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4555 else 4556 // if the source and dest are the same type, we can drop both the extend 4557 // and the truncate. 4558 return N0.getOperand(0); 4559 } 4560 4561 // See if we can simplify the input to this truncate through knowledge that 4562 // only the low bits are being used. 4563 // For example "trunc (or (shl x, 8), y)" // -> trunc y 4564 // Currently we only perform this optimization on scalars because vectors 4565 // may have different active low bits. 4566 if (!VT.isVector()) { 4567 SDValue Shorter = 4568 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4569 VT.getSizeInBits())); 4570 if (Shorter.getNode()) 4571 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4572 } 4573 // fold (truncate (load x)) -> (smaller load x) 4574 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4575 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4576 SDValue Reduced = ReduceLoadWidth(N); 4577 if (Reduced.getNode()) 4578 return Reduced; 4579 } 4580 4581 // Simplify the operands using demanded-bits information. 4582 if (!VT.isVector() && 4583 SimplifyDemandedBits(SDValue(N, 0))) 4584 return SDValue(N, 0); 4585 4586 return SDValue(); 4587} 4588 4589static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4590 SDValue Elt = N->getOperand(i); 4591 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4592 return Elt.getNode(); 4593 return Elt.getOperand(Elt.getResNo()).getNode(); 4594} 4595 4596/// CombineConsecutiveLoads - build_pair (load, load) -> load 4597/// if load locations are consecutive. 4598SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4599 assert(N->getOpcode() == ISD::BUILD_PAIR); 4600 4601 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4602 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4603 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4604 LD1->getPointerInfo().getAddrSpace() != 4605 LD2->getPointerInfo().getAddrSpace()) 4606 return SDValue(); 4607 EVT LD1VT = LD1->getValueType(0); 4608 4609 if (ISD::isNON_EXTLoad(LD2) && 4610 LD2->hasOneUse() && 4611 // If both are volatile this would reduce the number of volatile loads. 4612 // If one is volatile it might be ok, but play conservative and bail out. 4613 !LD1->isVolatile() && 4614 !LD2->isVolatile() && 4615 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4616 unsigned Align = LD1->getAlignment(); 4617 unsigned NewAlign = TLI.getTargetData()-> 4618 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4619 4620 if (NewAlign <= Align && 4621 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4622 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4623 LD1->getBasePtr(), LD1->getPointerInfo(), 4624 false, false, Align); 4625 } 4626 4627 return SDValue(); 4628} 4629 4630SDValue DAGCombiner::visitBITCAST(SDNode *N) { 4631 SDValue N0 = N->getOperand(0); 4632 EVT VT = N->getValueType(0); 4633 4634 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4635 // Only do this before legalize, since afterward the target may be depending 4636 // on the bitconvert. 4637 // First check to see if this is all constant. 4638 if (!LegalTypes && 4639 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4640 VT.isVector()) { 4641 bool isSimple = true; 4642 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4643 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4644 N0.getOperand(i).getOpcode() != ISD::Constant && 4645 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4646 isSimple = false; 4647 break; 4648 } 4649 4650 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4651 assert(!DestEltVT.isVector() && 4652 "Element type of vector ValueType must not be vector!"); 4653 if (isSimple) 4654 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4655 } 4656 4657 // If the input is a constant, let getNode fold it. 4658 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4659 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 4660 if (Res.getNode() != N) { 4661 if (!LegalOperations || 4662 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4663 return Res; 4664 4665 // Folding it resulted in an illegal node, and it's too late to 4666 // do that. Clean up the old node and forego the transformation. 4667 // Ideally this won't happen very often, because instcombine 4668 // and the earlier dagcombine runs (where illegal nodes are 4669 // permitted) should have folded most of them already. 4670 DAG.DeleteNode(Res.getNode()); 4671 } 4672 } 4673 4674 // (conv (conv x, t1), t2) -> (conv x, t2) 4675 if (N0.getOpcode() == ISD::BITCAST) 4676 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 4677 N0.getOperand(0)); 4678 4679 // fold (conv (load x)) -> (load (conv*)x) 4680 // If the resultant load doesn't need a higher alignment than the original! 4681 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4682 // Do not change the width of a volatile load. 4683 !cast<LoadSDNode>(N0)->isVolatile() && 4684 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4685 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4686 unsigned Align = TLI.getTargetData()-> 4687 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4688 unsigned OrigAlign = LN0->getAlignment(); 4689 4690 if (Align <= OrigAlign) { 4691 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4692 LN0->getBasePtr(), LN0->getPointerInfo(), 4693 LN0->isVolatile(), LN0->isNonTemporal(), 4694 OrigAlign); 4695 AddToWorkList(N); 4696 CombineTo(N0.getNode(), 4697 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4698 N0.getValueType(), Load), 4699 Load.getValue(1)); 4700 return Load; 4701 } 4702 } 4703 4704 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4705 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4706 // This often reduces constant pool loads. 4707 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4708 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4709 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 4710 N0.getOperand(0)); 4711 AddToWorkList(NewConv.getNode()); 4712 4713 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4714 if (N0.getOpcode() == ISD::FNEG) 4715 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4716 NewConv, DAG.getConstant(SignBit, VT)); 4717 assert(N0.getOpcode() == ISD::FABS); 4718 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4719 NewConv, DAG.getConstant(~SignBit, VT)); 4720 } 4721 4722 // fold (bitconvert (fcopysign cst, x)) -> 4723 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4724 // Note that we don't handle (copysign x, cst) because this can always be 4725 // folded to an fneg or fabs. 4726 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4727 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4728 VT.isInteger() && !VT.isVector()) { 4729 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4730 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4731 if (isTypeLegal(IntXVT)) { 4732 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4733 IntXVT, N0.getOperand(1)); 4734 AddToWorkList(X.getNode()); 4735 4736 // If X has a different width than the result/lhs, sext it or truncate it. 4737 unsigned VTWidth = VT.getSizeInBits(); 4738 if (OrigXWidth < VTWidth) { 4739 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4740 AddToWorkList(X.getNode()); 4741 } else if (OrigXWidth > VTWidth) { 4742 // To get the sign bit in the right place, we have to shift it right 4743 // before truncating. 4744 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4745 X.getValueType(), X, 4746 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4747 AddToWorkList(X.getNode()); 4748 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4749 AddToWorkList(X.getNode()); 4750 } 4751 4752 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4753 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4754 X, DAG.getConstant(SignBit, VT)); 4755 AddToWorkList(X.getNode()); 4756 4757 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4758 VT, N0.getOperand(0)); 4759 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4760 Cst, DAG.getConstant(~SignBit, VT)); 4761 AddToWorkList(Cst.getNode()); 4762 4763 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4764 } 4765 } 4766 4767 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4768 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4769 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4770 if (CombineLD.getNode()) 4771 return CombineLD; 4772 } 4773 4774 return SDValue(); 4775} 4776 4777SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4778 EVT VT = N->getValueType(0); 4779 return CombineConsecutiveLoads(N, VT); 4780} 4781 4782/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 4783/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4784/// destination element value type. 4785SDValue DAGCombiner:: 4786ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4787 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4788 4789 // If this is already the right type, we're done. 4790 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4791 4792 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4793 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4794 4795 // If this is a conversion of N elements of one type to N elements of another 4796 // type, convert each element. This handles FP<->INT cases. 4797 if (SrcBitSize == DstBitSize) { 4798 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4799 BV->getValueType(0).getVectorNumElements()); 4800 4801 // Due to the FP element handling below calling this routine recursively, 4802 // we can end up with a scalar-to-vector node here. 4803 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 4804 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4805 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4806 DstEltVT, BV->getOperand(0))); 4807 4808 SmallVector<SDValue, 8> Ops; 4809 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4810 SDValue Op = BV->getOperand(i); 4811 // If the vector element type is not legal, the BUILD_VECTOR operands 4812 // are promoted and implicitly truncated. Make that explicit here. 4813 if (Op.getValueType() != SrcEltVT) 4814 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4815 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4816 DstEltVT, Op)); 4817 AddToWorkList(Ops.back().getNode()); 4818 } 4819 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4820 &Ops[0], Ops.size()); 4821 } 4822 4823 // Otherwise, we're growing or shrinking the elements. To avoid having to 4824 // handle annoying details of growing/shrinking FP values, we convert them to 4825 // int first. 4826 if (SrcEltVT.isFloatingPoint()) { 4827 // Convert the input float vector to a int vector where the elements are the 4828 // same sizes. 4829 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4830 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4831 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 4832 SrcEltVT = IntVT; 4833 } 4834 4835 // Now we know the input is an integer vector. If the output is a FP type, 4836 // convert to integer first, then to FP of the right size. 4837 if (DstEltVT.isFloatingPoint()) { 4838 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4839 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4840 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 4841 4842 // Next, convert to FP elements of the same size. 4843 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 4844 } 4845 4846 // Okay, we know the src/dst types are both integers of differing types. 4847 // Handling growing first. 4848 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4849 if (SrcBitSize < DstBitSize) { 4850 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4851 4852 SmallVector<SDValue, 8> Ops; 4853 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4854 i += NumInputsPerOutput) { 4855 bool isLE = TLI.isLittleEndian(); 4856 APInt NewBits = APInt(DstBitSize, 0); 4857 bool EltIsUndef = true; 4858 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4859 // Shift the previously computed bits over. 4860 NewBits <<= SrcBitSize; 4861 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4862 if (Op.getOpcode() == ISD::UNDEF) continue; 4863 EltIsUndef = false; 4864 4865 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 4866 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4867 } 4868 4869 if (EltIsUndef) 4870 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4871 else 4872 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4873 } 4874 4875 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4876 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4877 &Ops[0], Ops.size()); 4878 } 4879 4880 // Finally, this must be the case where we are shrinking elements: each input 4881 // turns into multiple outputs. 4882 bool isS2V = ISD::isScalarToVector(BV); 4883 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4884 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4885 NumOutputsPerInput*BV->getNumOperands()); 4886 SmallVector<SDValue, 8> Ops; 4887 4888 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4889 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4890 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4891 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4892 continue; 4893 } 4894 4895 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 4896 getAPIntValue().zextOrTrunc(SrcBitSize); 4897 4898 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4899 APInt ThisVal = OpVal.trunc(DstBitSize); 4900 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4901 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 4902 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4903 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4904 Ops[0]); 4905 OpVal = OpVal.lshr(DstBitSize); 4906 } 4907 4908 // For big endian targets, swap the order of the pieces of each element. 4909 if (TLI.isBigEndian()) 4910 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4911 } 4912 4913 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4914 &Ops[0], Ops.size()); 4915} 4916 4917SDValue DAGCombiner::visitFADD(SDNode *N) { 4918 SDValue N0 = N->getOperand(0); 4919 SDValue N1 = N->getOperand(1); 4920 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4921 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4922 EVT VT = N->getValueType(0); 4923 4924 // fold vector ops 4925 if (VT.isVector()) { 4926 SDValue FoldedVOp = SimplifyVBinOp(N); 4927 if (FoldedVOp.getNode()) return FoldedVOp; 4928 } 4929 4930 // fold (fadd c1, c2) -> (fadd c1, c2) 4931 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4932 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4933 // canonicalize constant to RHS 4934 if (N0CFP && !N1CFP) 4935 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4936 // fold (fadd A, 0) -> A 4937 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4938 return N0; 4939 // fold (fadd A, (fneg B)) -> (fsub A, B) 4940 if (isNegatibleForFree(N1, LegalOperations) == 2) 4941 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4942 GetNegatedExpression(N1, DAG, LegalOperations)); 4943 // fold (fadd (fneg A), B) -> (fsub B, A) 4944 if (isNegatibleForFree(N0, LegalOperations) == 2) 4945 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4946 GetNegatedExpression(N0, DAG, LegalOperations)); 4947 4948 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4949 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4950 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4951 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4952 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4953 N0.getOperand(1), N1)); 4954 4955 return SDValue(); 4956} 4957 4958SDValue DAGCombiner::visitFSUB(SDNode *N) { 4959 SDValue N0 = N->getOperand(0); 4960 SDValue N1 = N->getOperand(1); 4961 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4962 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4963 EVT VT = N->getValueType(0); 4964 4965 // fold vector ops 4966 if (VT.isVector()) { 4967 SDValue FoldedVOp = SimplifyVBinOp(N); 4968 if (FoldedVOp.getNode()) return FoldedVOp; 4969 } 4970 4971 // fold (fsub c1, c2) -> c1-c2 4972 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4973 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4974 // fold (fsub A, 0) -> A 4975 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4976 return N0; 4977 // fold (fsub 0, B) -> -B 4978 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4979 if (isNegatibleForFree(N1, LegalOperations)) 4980 return GetNegatedExpression(N1, DAG, LegalOperations); 4981 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4982 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4983 } 4984 // fold (fsub A, (fneg B)) -> (fadd A, B) 4985 if (isNegatibleForFree(N1, LegalOperations)) 4986 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4987 GetNegatedExpression(N1, DAG, LegalOperations)); 4988 4989 return SDValue(); 4990} 4991 4992SDValue DAGCombiner::visitFMUL(SDNode *N) { 4993 SDValue N0 = N->getOperand(0); 4994 SDValue N1 = N->getOperand(1); 4995 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4996 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4997 EVT VT = N->getValueType(0); 4998 4999 // fold vector ops 5000 if (VT.isVector()) { 5001 SDValue FoldedVOp = SimplifyVBinOp(N); 5002 if (FoldedVOp.getNode()) return FoldedVOp; 5003 } 5004 5005 // fold (fmul c1, c2) -> c1*c2 5006 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5007 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5008 // canonicalize constant to RHS 5009 if (N0CFP && !N1CFP) 5010 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5011 // fold (fmul A, 0) -> 0 5012 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5013 return N1; 5014 // fold (fmul A, 0) -> 0, vector edition. 5015 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 5016 return N1; 5017 // fold (fmul X, 2.0) -> (fadd X, X) 5018 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5019 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5020 // fold (fmul X, -1.0) -> (fneg X) 5021 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5022 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5023 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5024 5025 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5026 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5027 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5028 // Both can be negated for free, check to see if at least one is cheaper 5029 // negated. 5030 if (LHSNeg == 2 || RHSNeg == 2) 5031 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5032 GetNegatedExpression(N0, DAG, LegalOperations), 5033 GetNegatedExpression(N1, DAG, LegalOperations)); 5034 } 5035 } 5036 5037 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5038 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 5039 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5040 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5041 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5042 N0.getOperand(1), N1)); 5043 5044 return SDValue(); 5045} 5046 5047SDValue DAGCombiner::visitFDIV(SDNode *N) { 5048 SDValue N0 = N->getOperand(0); 5049 SDValue N1 = N->getOperand(1); 5050 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5051 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5052 EVT VT = N->getValueType(0); 5053 5054 // fold vector ops 5055 if (VT.isVector()) { 5056 SDValue FoldedVOp = SimplifyVBinOp(N); 5057 if (FoldedVOp.getNode()) return FoldedVOp; 5058 } 5059 5060 // fold (fdiv c1, c2) -> c1/c2 5061 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5062 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5063 5064 5065 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5066 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5067 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5068 // Both can be negated for free, check to see if at least one is cheaper 5069 // negated. 5070 if (LHSNeg == 2 || RHSNeg == 2) 5071 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5072 GetNegatedExpression(N0, DAG, LegalOperations), 5073 GetNegatedExpression(N1, DAG, LegalOperations)); 5074 } 5075 } 5076 5077 return SDValue(); 5078} 5079 5080SDValue DAGCombiner::visitFREM(SDNode *N) { 5081 SDValue N0 = N->getOperand(0); 5082 SDValue N1 = N->getOperand(1); 5083 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5084 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5085 EVT VT = N->getValueType(0); 5086 5087 // fold (frem c1, c2) -> fmod(c1,c2) 5088 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5089 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5090 5091 return SDValue(); 5092} 5093 5094SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5095 SDValue N0 = N->getOperand(0); 5096 SDValue N1 = N->getOperand(1); 5097 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5098 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5099 EVT VT = N->getValueType(0); 5100 5101 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5102 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5103 5104 if (N1CFP) { 5105 const APFloat& V = N1CFP->getValueAPF(); 5106 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5107 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5108 if (!V.isNegative()) { 5109 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5110 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5111 } else { 5112 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5113 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5114 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5115 } 5116 } 5117 5118 // copysign(fabs(x), y) -> copysign(x, y) 5119 // copysign(fneg(x), y) -> copysign(x, y) 5120 // copysign(copysign(x,z), y) -> copysign(x, y) 5121 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5122 N0.getOpcode() == ISD::FCOPYSIGN) 5123 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5124 N0.getOperand(0), N1); 5125 5126 // copysign(x, abs(y)) -> abs(x) 5127 if (N1.getOpcode() == ISD::FABS) 5128 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5129 5130 // copysign(x, copysign(y,z)) -> copysign(x, z) 5131 if (N1.getOpcode() == ISD::FCOPYSIGN) 5132 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5133 N0, N1.getOperand(1)); 5134 5135 // copysign(x, fp_extend(y)) -> copysign(x, y) 5136 // copysign(x, fp_round(y)) -> copysign(x, y) 5137 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5138 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5139 N0, N1.getOperand(0)); 5140 5141 return SDValue(); 5142} 5143 5144SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5145 SDValue N0 = N->getOperand(0); 5146 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5147 EVT VT = N->getValueType(0); 5148 EVT OpVT = N0.getValueType(); 5149 5150 // fold (sint_to_fp c1) -> c1fp 5151 if (N0C && OpVT != MVT::ppcf128 && 5152 // ...but only if the target supports immediate floating-point values 5153 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5154 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5155 5156 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5157 // but UINT_TO_FP is legal on this target, try to convert. 5158 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5159 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5160 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5161 if (DAG.SignBitIsZero(N0)) 5162 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5163 } 5164 5165 return SDValue(); 5166} 5167 5168SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5169 SDValue N0 = N->getOperand(0); 5170 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5171 EVT VT = N->getValueType(0); 5172 EVT OpVT = N0.getValueType(); 5173 5174 // fold (uint_to_fp c1) -> c1fp 5175 if (N0C && OpVT != MVT::ppcf128 && 5176 // ...but only if the target supports immediate floating-point values 5177 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5178 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5179 5180 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5181 // but SINT_TO_FP is legal on this target, try to convert. 5182 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5183 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5184 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5185 if (DAG.SignBitIsZero(N0)) 5186 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5187 } 5188 5189 return SDValue(); 5190} 5191 5192SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5193 SDValue N0 = N->getOperand(0); 5194 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5195 EVT VT = N->getValueType(0); 5196 5197 // fold (fp_to_sint c1fp) -> c1 5198 if (N0CFP) 5199 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5200 5201 return SDValue(); 5202} 5203 5204SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5205 SDValue N0 = N->getOperand(0); 5206 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5207 EVT VT = N->getValueType(0); 5208 5209 // fold (fp_to_uint c1fp) -> c1 5210 if (N0CFP && VT != MVT::ppcf128) 5211 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5212 5213 return SDValue(); 5214} 5215 5216SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5217 SDValue N0 = N->getOperand(0); 5218 SDValue N1 = N->getOperand(1); 5219 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5220 EVT VT = N->getValueType(0); 5221 5222 // fold (fp_round c1fp) -> c1fp 5223 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5224 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5225 5226 // fold (fp_round (fp_extend x)) -> x 5227 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5228 return N0.getOperand(0); 5229 5230 // fold (fp_round (fp_round x)) -> (fp_round x) 5231 if (N0.getOpcode() == ISD::FP_ROUND) { 5232 // This is a value preserving truncation if both round's are. 5233 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5234 N0.getNode()->getConstantOperandVal(1) == 1; 5235 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5236 DAG.getIntPtrConstant(IsTrunc)); 5237 } 5238 5239 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5240 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5241 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5242 N0.getOperand(0), N1); 5243 AddToWorkList(Tmp.getNode()); 5244 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5245 Tmp, N0.getOperand(1)); 5246 } 5247 5248 return SDValue(); 5249} 5250 5251SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5252 SDValue N0 = N->getOperand(0); 5253 EVT VT = N->getValueType(0); 5254 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5255 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5256 5257 // fold (fp_round_inreg c1fp) -> c1fp 5258 if (N0CFP && isTypeLegal(EVT)) { 5259 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5260 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5261 } 5262 5263 return SDValue(); 5264} 5265 5266SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5267 SDValue N0 = N->getOperand(0); 5268 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5269 EVT VT = N->getValueType(0); 5270 5271 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5272 if (N->hasOneUse() && 5273 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5274 return SDValue(); 5275 5276 // fold (fp_extend c1fp) -> c1fp 5277 if (N0CFP && VT != MVT::ppcf128) 5278 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5279 5280 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5281 // value of X. 5282 if (N0.getOpcode() == ISD::FP_ROUND 5283 && N0.getNode()->getConstantOperandVal(1) == 1) { 5284 SDValue In = N0.getOperand(0); 5285 if (In.getValueType() == VT) return In; 5286 if (VT.bitsLT(In.getValueType())) 5287 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5288 In, N0.getOperand(1)); 5289 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5290 } 5291 5292 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5293 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5294 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5295 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5296 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5297 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5298 LN0->getChain(), 5299 LN0->getBasePtr(), LN0->getPointerInfo(), 5300 N0.getValueType(), 5301 LN0->isVolatile(), LN0->isNonTemporal(), 5302 LN0->getAlignment()); 5303 CombineTo(N, ExtLoad); 5304 CombineTo(N0.getNode(), 5305 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5306 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5307 ExtLoad.getValue(1)); 5308 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5309 } 5310 5311 return SDValue(); 5312} 5313 5314SDValue DAGCombiner::visitFNEG(SDNode *N) { 5315 SDValue N0 = N->getOperand(0); 5316 EVT VT = N->getValueType(0); 5317 5318 if (isNegatibleForFree(N0, LegalOperations)) 5319 return GetNegatedExpression(N0, DAG, LegalOperations); 5320 5321 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5322 // constant pool values. 5323 if (N0.getOpcode() == ISD::BITCAST && 5324 !VT.isVector() && 5325 N0.getNode()->hasOneUse() && 5326 N0.getOperand(0).getValueType().isInteger()) { 5327 SDValue Int = N0.getOperand(0); 5328 EVT IntVT = Int.getValueType(); 5329 if (IntVT.isInteger() && !IntVT.isVector()) { 5330 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5331 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5332 AddToWorkList(Int.getNode()); 5333 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5334 VT, Int); 5335 } 5336 } 5337 5338 return SDValue(); 5339} 5340 5341SDValue DAGCombiner::visitFABS(SDNode *N) { 5342 SDValue N0 = N->getOperand(0); 5343 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5344 EVT VT = N->getValueType(0); 5345 5346 // fold (fabs c1) -> fabs(c1) 5347 if (N0CFP && VT != MVT::ppcf128) 5348 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5349 // fold (fabs (fabs x)) -> (fabs x) 5350 if (N0.getOpcode() == ISD::FABS) 5351 return N->getOperand(0); 5352 // fold (fabs (fneg x)) -> (fabs x) 5353 // fold (fabs (fcopysign x, y)) -> (fabs x) 5354 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5355 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5356 5357 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5358 // constant pool values. 5359 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5360 N0.getOperand(0).getValueType().isInteger() && 5361 !N0.getOperand(0).getValueType().isVector()) { 5362 SDValue Int = N0.getOperand(0); 5363 EVT IntVT = Int.getValueType(); 5364 if (IntVT.isInteger() && !IntVT.isVector()) { 5365 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5366 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5367 AddToWorkList(Int.getNode()); 5368 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5369 N->getValueType(0), Int); 5370 } 5371 } 5372 5373 return SDValue(); 5374} 5375 5376SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5377 SDValue Chain = N->getOperand(0); 5378 SDValue N1 = N->getOperand(1); 5379 SDValue N2 = N->getOperand(2); 5380 5381 // If N is a constant we could fold this into a fallthrough or unconditional 5382 // branch. However that doesn't happen very often in normal code, because 5383 // Instcombine/SimplifyCFG should have handled the available opportunities. 5384 // If we did this folding here, it would be necessary to update the 5385 // MachineBasicBlock CFG, which is awkward. 5386 5387 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5388 // on the target. 5389 if (N1.getOpcode() == ISD::SETCC && 5390 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5391 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5392 Chain, N1.getOperand(2), 5393 N1.getOperand(0), N1.getOperand(1), N2); 5394 } 5395 5396 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5397 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5398 (N1.getOperand(0).hasOneUse() && 5399 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5400 SDNode *Trunc = 0; 5401 if (N1.getOpcode() == ISD::TRUNCATE) { 5402 // Look pass the truncate. 5403 Trunc = N1.getNode(); 5404 N1 = N1.getOperand(0); 5405 } 5406 5407 // Match this pattern so that we can generate simpler code: 5408 // 5409 // %a = ... 5410 // %b = and i32 %a, 2 5411 // %c = srl i32 %b, 1 5412 // brcond i32 %c ... 5413 // 5414 // into 5415 // 5416 // %a = ... 5417 // %b = and i32 %a, 2 5418 // %c = setcc eq %b, 0 5419 // brcond %c ... 5420 // 5421 // This applies only when the AND constant value has one bit set and the 5422 // SRL constant is equal to the log2 of the AND constant. The back-end is 5423 // smart enough to convert the result into a TEST/JMP sequence. 5424 SDValue Op0 = N1.getOperand(0); 5425 SDValue Op1 = N1.getOperand(1); 5426 5427 if (Op0.getOpcode() == ISD::AND && 5428 Op1.getOpcode() == ISD::Constant) { 5429 SDValue AndOp1 = Op0.getOperand(1); 5430 5431 if (AndOp1.getOpcode() == ISD::Constant) { 5432 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5433 5434 if (AndConst.isPowerOf2() && 5435 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5436 SDValue SetCC = 5437 DAG.getSetCC(N->getDebugLoc(), 5438 TLI.getSetCCResultType(Op0.getValueType()), 5439 Op0, DAG.getConstant(0, Op0.getValueType()), 5440 ISD::SETNE); 5441 5442 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5443 MVT::Other, Chain, SetCC, N2); 5444 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5445 // will convert it back to (X & C1) >> C2. 5446 CombineTo(N, NewBRCond, false); 5447 // Truncate is dead. 5448 if (Trunc) { 5449 removeFromWorkList(Trunc); 5450 DAG.DeleteNode(Trunc); 5451 } 5452 // Replace the uses of SRL with SETCC 5453 WorkListRemover DeadNodes(*this); 5454 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5455 removeFromWorkList(N1.getNode()); 5456 DAG.DeleteNode(N1.getNode()); 5457 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5458 } 5459 } 5460 } 5461 5462 if (Trunc) 5463 // Restore N1 if the above transformation doesn't match. 5464 N1 = N->getOperand(1); 5465 } 5466 5467 // Transform br(xor(x, y)) -> br(x != y) 5468 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5469 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5470 SDNode *TheXor = N1.getNode(); 5471 SDValue Op0 = TheXor->getOperand(0); 5472 SDValue Op1 = TheXor->getOperand(1); 5473 if (Op0.getOpcode() == Op1.getOpcode()) { 5474 // Avoid missing important xor optimizations. 5475 SDValue Tmp = visitXOR(TheXor); 5476 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5477 DEBUG(dbgs() << "\nReplacing.8 "; 5478 TheXor->dump(&DAG); 5479 dbgs() << "\nWith: "; 5480 Tmp.getNode()->dump(&DAG); 5481 dbgs() << '\n'); 5482 WorkListRemover DeadNodes(*this); 5483 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5484 removeFromWorkList(TheXor); 5485 DAG.DeleteNode(TheXor); 5486 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5487 MVT::Other, Chain, Tmp, N2); 5488 } 5489 } 5490 5491 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5492 bool Equal = false; 5493 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5494 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5495 Op0.getOpcode() == ISD::XOR) { 5496 TheXor = Op0.getNode(); 5497 Equal = true; 5498 } 5499 5500 EVT SetCCVT = N1.getValueType(); 5501 if (LegalTypes) 5502 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5503 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5504 SetCCVT, 5505 Op0, Op1, 5506 Equal ? ISD::SETEQ : ISD::SETNE); 5507 // Replace the uses of XOR with SETCC 5508 WorkListRemover DeadNodes(*this); 5509 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5510 removeFromWorkList(N1.getNode()); 5511 DAG.DeleteNode(N1.getNode()); 5512 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5513 MVT::Other, Chain, SetCC, N2); 5514 } 5515 } 5516 5517 return SDValue(); 5518} 5519 5520// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5521// 5522SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5523 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5524 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5525 5526 // If N is a constant we could fold this into a fallthrough or unconditional 5527 // branch. However that doesn't happen very often in normal code, because 5528 // Instcombine/SimplifyCFG should have handled the available opportunities. 5529 // If we did this folding here, it would be necessary to update the 5530 // MachineBasicBlock CFG, which is awkward. 5531 5532 // Use SimplifySetCC to simplify SETCC's. 5533 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5534 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5535 false); 5536 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5537 5538 // fold to a simpler setcc 5539 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5540 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5541 N->getOperand(0), Simp.getOperand(2), 5542 Simp.getOperand(0), Simp.getOperand(1), 5543 N->getOperand(4)); 5544 5545 return SDValue(); 5546} 5547 5548/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5549/// pre-indexed load / store when the base pointer is an add or subtract 5550/// and it has other uses besides the load / store. After the 5551/// transformation, the new indexed load / store has effectively folded 5552/// the add / subtract in and all of its other uses are redirected to the 5553/// new load / store. 5554bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5555 if (!LegalOperations) 5556 return false; 5557 5558 bool isLoad = true; 5559 SDValue Ptr; 5560 EVT VT; 5561 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5562 if (LD->isIndexed()) 5563 return false; 5564 VT = LD->getMemoryVT(); 5565 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5566 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5567 return false; 5568 Ptr = LD->getBasePtr(); 5569 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5570 if (ST->isIndexed()) 5571 return false; 5572 VT = ST->getMemoryVT(); 5573 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5574 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5575 return false; 5576 Ptr = ST->getBasePtr(); 5577 isLoad = false; 5578 } else { 5579 return false; 5580 } 5581 5582 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5583 // out. There is no reason to make this a preinc/predec. 5584 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5585 Ptr.getNode()->hasOneUse()) 5586 return false; 5587 5588 // Ask the target to do addressing mode selection. 5589 SDValue BasePtr; 5590 SDValue Offset; 5591 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5592 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5593 return false; 5594 // Don't create a indexed load / store with zero offset. 5595 if (isa<ConstantSDNode>(Offset) && 5596 cast<ConstantSDNode>(Offset)->isNullValue()) 5597 return false; 5598 5599 // Try turning it into a pre-indexed load / store except when: 5600 // 1) The new base ptr is a frame index. 5601 // 2) If N is a store and the new base ptr is either the same as or is a 5602 // predecessor of the value being stored. 5603 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5604 // that would create a cycle. 5605 // 4) All uses are load / store ops that use it as old base ptr. 5606 5607 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5608 // (plus the implicit offset) to a register to preinc anyway. 5609 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5610 return false; 5611 5612 // Check #2. 5613 if (!isLoad) { 5614 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5615 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5616 return false; 5617 } 5618 5619 // Now check for #3 and #4. 5620 bool RealUse = false; 5621 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5622 E = Ptr.getNode()->use_end(); I != E; ++I) { 5623 SDNode *Use = *I; 5624 if (Use == N) 5625 continue; 5626 if (Use->isPredecessorOf(N)) 5627 return false; 5628 5629 if (!((Use->getOpcode() == ISD::LOAD && 5630 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5631 (Use->getOpcode() == ISD::STORE && 5632 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5633 RealUse = true; 5634 } 5635 5636 if (!RealUse) 5637 return false; 5638 5639 SDValue Result; 5640 if (isLoad) 5641 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5642 BasePtr, Offset, AM); 5643 else 5644 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5645 BasePtr, Offset, AM); 5646 ++PreIndexedNodes; 5647 ++NodesCombined; 5648 DEBUG(dbgs() << "\nReplacing.4 "; 5649 N->dump(&DAG); 5650 dbgs() << "\nWith: "; 5651 Result.getNode()->dump(&DAG); 5652 dbgs() << '\n'); 5653 WorkListRemover DeadNodes(*this); 5654 if (isLoad) { 5655 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5656 &DeadNodes); 5657 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5658 &DeadNodes); 5659 } else { 5660 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5661 &DeadNodes); 5662 } 5663 5664 // Finally, since the node is now dead, remove it from the graph. 5665 DAG.DeleteNode(N); 5666 5667 // Replace the uses of Ptr with uses of the updated base value. 5668 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5669 &DeadNodes); 5670 removeFromWorkList(Ptr.getNode()); 5671 DAG.DeleteNode(Ptr.getNode()); 5672 5673 return true; 5674} 5675 5676/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5677/// add / sub of the base pointer node into a post-indexed load / store. 5678/// The transformation folded the add / subtract into the new indexed 5679/// load / store effectively and all of its uses are redirected to the 5680/// new load / store. 5681bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5682 if (!LegalOperations) 5683 return false; 5684 5685 bool isLoad = true; 5686 SDValue Ptr; 5687 EVT VT; 5688 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5689 if (LD->isIndexed()) 5690 return false; 5691 VT = LD->getMemoryVT(); 5692 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5693 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5694 return false; 5695 Ptr = LD->getBasePtr(); 5696 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5697 if (ST->isIndexed()) 5698 return false; 5699 VT = ST->getMemoryVT(); 5700 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5701 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5702 return false; 5703 Ptr = ST->getBasePtr(); 5704 isLoad = false; 5705 } else { 5706 return false; 5707 } 5708 5709 if (Ptr.getNode()->hasOneUse()) 5710 return false; 5711 5712 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5713 E = Ptr.getNode()->use_end(); I != E; ++I) { 5714 SDNode *Op = *I; 5715 if (Op == N || 5716 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5717 continue; 5718 5719 SDValue BasePtr; 5720 SDValue Offset; 5721 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5722 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5723 // Don't create a indexed load / store with zero offset. 5724 if (isa<ConstantSDNode>(Offset) && 5725 cast<ConstantSDNode>(Offset)->isNullValue()) 5726 continue; 5727 5728 // Try turning it into a post-indexed load / store except when 5729 // 1) All uses are load / store ops that use it as base ptr. 5730 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5731 // nor a successor of N. Otherwise, if Op is folded that would 5732 // create a cycle. 5733 5734 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5735 continue; 5736 5737 // Check for #1. 5738 bool TryNext = false; 5739 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5740 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5741 SDNode *Use = *II; 5742 if (Use == Ptr.getNode()) 5743 continue; 5744 5745 // If all the uses are load / store addresses, then don't do the 5746 // transformation. 5747 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5748 bool RealUse = false; 5749 for (SDNode::use_iterator III = Use->use_begin(), 5750 EEE = Use->use_end(); III != EEE; ++III) { 5751 SDNode *UseUse = *III; 5752 if (!((UseUse->getOpcode() == ISD::LOAD && 5753 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5754 (UseUse->getOpcode() == ISD::STORE && 5755 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5756 RealUse = true; 5757 } 5758 5759 if (!RealUse) { 5760 TryNext = true; 5761 break; 5762 } 5763 } 5764 } 5765 5766 if (TryNext) 5767 continue; 5768 5769 // Check for #2 5770 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5771 SDValue Result = isLoad 5772 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5773 BasePtr, Offset, AM) 5774 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5775 BasePtr, Offset, AM); 5776 ++PostIndexedNodes; 5777 ++NodesCombined; 5778 DEBUG(dbgs() << "\nReplacing.5 "; 5779 N->dump(&DAG); 5780 dbgs() << "\nWith: "; 5781 Result.getNode()->dump(&DAG); 5782 dbgs() << '\n'); 5783 WorkListRemover DeadNodes(*this); 5784 if (isLoad) { 5785 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5786 &DeadNodes); 5787 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5788 &DeadNodes); 5789 } else { 5790 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5791 &DeadNodes); 5792 } 5793 5794 // Finally, since the node is now dead, remove it from the graph. 5795 DAG.DeleteNode(N); 5796 5797 // Replace the uses of Use with uses of the updated base value. 5798 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5799 Result.getValue(isLoad ? 1 : 0), 5800 &DeadNodes); 5801 removeFromWorkList(Op); 5802 DAG.DeleteNode(Op); 5803 return true; 5804 } 5805 } 5806 } 5807 5808 return false; 5809} 5810 5811SDValue DAGCombiner::visitLOAD(SDNode *N) { 5812 LoadSDNode *LD = cast<LoadSDNode>(N); 5813 SDValue Chain = LD->getChain(); 5814 SDValue Ptr = LD->getBasePtr(); 5815 5816 // If load is not volatile and there are no uses of the loaded value (and 5817 // the updated indexed value in case of indexed loads), change uses of the 5818 // chain value into uses of the chain input (i.e. delete the dead load). 5819 if (!LD->isVolatile()) { 5820 if (N->getValueType(1) == MVT::Other) { 5821 // Unindexed loads. 5822 if (N->hasNUsesOfValue(0, 0)) { 5823 // It's not safe to use the two value CombineTo variant here. e.g. 5824 // v1, chain2 = load chain1, loc 5825 // v2, chain3 = load chain2, loc 5826 // v3 = add v2, c 5827 // Now we replace use of chain2 with chain1. This makes the second load 5828 // isomorphic to the one we are deleting, and thus makes this load live. 5829 DEBUG(dbgs() << "\nReplacing.6 "; 5830 N->dump(&DAG); 5831 dbgs() << "\nWith chain: "; 5832 Chain.getNode()->dump(&DAG); 5833 dbgs() << "\n"); 5834 WorkListRemover DeadNodes(*this); 5835 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5836 5837 if (N->use_empty()) { 5838 removeFromWorkList(N); 5839 DAG.DeleteNode(N); 5840 } 5841 5842 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5843 } 5844 } else { 5845 // Indexed loads. 5846 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5847 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5848 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5849 DEBUG(dbgs() << "\nReplacing.7 "; 5850 N->dump(&DAG); 5851 dbgs() << "\nWith: "; 5852 Undef.getNode()->dump(&DAG); 5853 dbgs() << " and 2 other values\n"); 5854 WorkListRemover DeadNodes(*this); 5855 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5856 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5857 DAG.getUNDEF(N->getValueType(1)), 5858 &DeadNodes); 5859 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5860 removeFromWorkList(N); 5861 DAG.DeleteNode(N); 5862 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5863 } 5864 } 5865 } 5866 5867 // If this load is directly stored, replace the load value with the stored 5868 // value. 5869 // TODO: Handle store large -> read small portion. 5870 // TODO: Handle TRUNCSTORE/LOADEXT 5871 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 5872 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5873 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5874 if (PrevST->getBasePtr() == Ptr && 5875 PrevST->getValue().getValueType() == N->getValueType(0)) 5876 return CombineTo(N, Chain.getOperand(1), Chain); 5877 } 5878 } 5879 5880 // Try to infer better alignment information than the load already has. 5881 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5882 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5883 if (Align > LD->getAlignment()) 5884 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5885 LD->getValueType(0), 5886 Chain, Ptr, LD->getPointerInfo(), 5887 LD->getMemoryVT(), 5888 LD->isVolatile(), LD->isNonTemporal(), Align); 5889 } 5890 } 5891 5892 if (CombinerAA) { 5893 // Walk up chain skipping non-aliasing memory nodes. 5894 SDValue BetterChain = FindBetterChain(N, Chain); 5895 5896 // If there is a better chain. 5897 if (Chain != BetterChain) { 5898 SDValue ReplLoad; 5899 5900 // Replace the chain to void dependency. 5901 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5902 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5903 BetterChain, Ptr, LD->getPointerInfo(), 5904 LD->isVolatile(), LD->isNonTemporal(), 5905 LD->getAlignment()); 5906 } else { 5907 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5908 LD->getValueType(0), 5909 BetterChain, Ptr, LD->getPointerInfo(), 5910 LD->getMemoryVT(), 5911 LD->isVolatile(), 5912 LD->isNonTemporal(), 5913 LD->getAlignment()); 5914 } 5915 5916 // Create token factor to keep old chain connected. 5917 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5918 MVT::Other, Chain, ReplLoad.getValue(1)); 5919 5920 // Make sure the new and old chains are cleaned up. 5921 AddToWorkList(Token.getNode()); 5922 5923 // Replace uses with load result and token factor. Don't add users 5924 // to work list. 5925 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5926 } 5927 } 5928 5929 // Try transforming N to an indexed load. 5930 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5931 return SDValue(N, 0); 5932 5933 return SDValue(); 5934} 5935 5936/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5937/// load is having specific bytes cleared out. If so, return the byte size 5938/// being masked out and the shift amount. 5939static std::pair<unsigned, unsigned> 5940CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5941 std::pair<unsigned, unsigned> Result(0, 0); 5942 5943 // Check for the structure we're looking for. 5944 if (V->getOpcode() != ISD::AND || 5945 !isa<ConstantSDNode>(V->getOperand(1)) || 5946 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5947 return Result; 5948 5949 // Check the chain and pointer. 5950 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5951 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5952 5953 // The store should be chained directly to the load or be an operand of a 5954 // tokenfactor. 5955 if (LD == Chain.getNode()) 5956 ; // ok. 5957 else if (Chain->getOpcode() != ISD::TokenFactor) 5958 return Result; // Fail. 5959 else { 5960 bool isOk = false; 5961 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5962 if (Chain->getOperand(i).getNode() == LD) { 5963 isOk = true; 5964 break; 5965 } 5966 if (!isOk) return Result; 5967 } 5968 5969 // This only handles simple types. 5970 if (V.getValueType() != MVT::i16 && 5971 V.getValueType() != MVT::i32 && 5972 V.getValueType() != MVT::i64) 5973 return Result; 5974 5975 // Check the constant mask. Invert it so that the bits being masked out are 5976 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5977 // follow the sign bit for uniformity. 5978 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5979 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5980 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5981 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5982 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5983 if (NotMaskLZ == 64) return Result; // All zero mask. 5984 5985 // See if we have a continuous run of bits. If so, we have 0*1+0* 5986 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5987 return Result; 5988 5989 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5990 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5991 NotMaskLZ -= 64-V.getValueSizeInBits(); 5992 5993 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5994 switch (MaskedBytes) { 5995 case 1: 5996 case 2: 5997 case 4: break; 5998 default: return Result; // All one mask, or 5-byte mask. 5999 } 6000 6001 // Verify that the first bit starts at a multiple of mask so that the access 6002 // is aligned the same as the access width. 6003 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6004 6005 Result.first = MaskedBytes; 6006 Result.second = NotMaskTZ/8; 6007 return Result; 6008} 6009 6010 6011/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6012/// provides a value as specified by MaskInfo. If so, replace the specified 6013/// store with a narrower store of truncated IVal. 6014static SDNode * 6015ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6016 SDValue IVal, StoreSDNode *St, 6017 DAGCombiner *DC) { 6018 unsigned NumBytes = MaskInfo.first; 6019 unsigned ByteShift = MaskInfo.second; 6020 SelectionDAG &DAG = DC->getDAG(); 6021 6022 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6023 // that uses this. If not, this is not a replacement. 6024 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6025 ByteShift*8, (ByteShift+NumBytes)*8); 6026 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6027 6028 // Check that it is legal on the target to do this. It is legal if the new 6029 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6030 // legalization. 6031 MVT VT = MVT::getIntegerVT(NumBytes*8); 6032 if (!DC->isTypeLegal(VT)) 6033 return 0; 6034 6035 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6036 // shifted by ByteShift and truncated down to NumBytes. 6037 if (ByteShift) 6038 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6039 DAG.getConstant(ByteShift*8, 6040 DC->getShiftAmountTy(IVal.getValueType()))); 6041 6042 // Figure out the offset for the store and the alignment of the access. 6043 unsigned StOffset; 6044 unsigned NewAlign = St->getAlignment(); 6045 6046 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6047 StOffset = ByteShift; 6048 else 6049 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6050 6051 SDValue Ptr = St->getBasePtr(); 6052 if (StOffset) { 6053 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6054 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6055 NewAlign = MinAlign(NewAlign, StOffset); 6056 } 6057 6058 // Truncate down to the new size. 6059 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6060 6061 ++OpsNarrowed; 6062 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6063 St->getPointerInfo().getWithOffset(StOffset), 6064 false, false, NewAlign).getNode(); 6065} 6066 6067 6068/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6069/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6070/// of the loaded bits, try narrowing the load and store if it would end up 6071/// being a win for performance or code size. 6072SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6073 StoreSDNode *ST = cast<StoreSDNode>(N); 6074 if (ST->isVolatile()) 6075 return SDValue(); 6076 6077 SDValue Chain = ST->getChain(); 6078 SDValue Value = ST->getValue(); 6079 SDValue Ptr = ST->getBasePtr(); 6080 EVT VT = Value.getValueType(); 6081 6082 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6083 return SDValue(); 6084 6085 unsigned Opc = Value.getOpcode(); 6086 6087 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6088 // is a byte mask indicating a consecutive number of bytes, check to see if 6089 // Y is known to provide just those bytes. If so, we try to replace the 6090 // load + replace + store sequence with a single (narrower) store, which makes 6091 // the load dead. 6092 if (Opc == ISD::OR) { 6093 std::pair<unsigned, unsigned> MaskedLoad; 6094 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6095 if (MaskedLoad.first) 6096 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6097 Value.getOperand(1), ST,this)) 6098 return SDValue(NewST, 0); 6099 6100 // Or is commutative, so try swapping X and Y. 6101 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6102 if (MaskedLoad.first) 6103 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6104 Value.getOperand(0), ST,this)) 6105 return SDValue(NewST, 0); 6106 } 6107 6108 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6109 Value.getOperand(1).getOpcode() != ISD::Constant) 6110 return SDValue(); 6111 6112 SDValue N0 = Value.getOperand(0); 6113 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6114 Chain == SDValue(N0.getNode(), 1)) { 6115 LoadSDNode *LD = cast<LoadSDNode>(N0); 6116 if (LD->getBasePtr() != Ptr || 6117 LD->getPointerInfo().getAddrSpace() != 6118 ST->getPointerInfo().getAddrSpace()) 6119 return SDValue(); 6120 6121 // Find the type to narrow it the load / op / store to. 6122 SDValue N1 = Value.getOperand(1); 6123 unsigned BitWidth = N1.getValueSizeInBits(); 6124 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6125 if (Opc == ISD::AND) 6126 Imm ^= APInt::getAllOnesValue(BitWidth); 6127 if (Imm == 0 || Imm.isAllOnesValue()) 6128 return SDValue(); 6129 unsigned ShAmt = Imm.countTrailingZeros(); 6130 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6131 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6132 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6133 while (NewBW < BitWidth && 6134 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6135 TLI.isNarrowingProfitable(VT, NewVT))) { 6136 NewBW = NextPowerOf2(NewBW); 6137 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6138 } 6139 if (NewBW >= BitWidth) 6140 return SDValue(); 6141 6142 // If the lsb changed does not start at the type bitwidth boundary, 6143 // start at the previous one. 6144 if (ShAmt % NewBW) 6145 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6146 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6147 if ((Imm & Mask) == Imm) { 6148 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6149 if (Opc == ISD::AND) 6150 NewImm ^= APInt::getAllOnesValue(NewBW); 6151 uint64_t PtrOff = ShAmt / 8; 6152 // For big endian targets, we need to adjust the offset to the pointer to 6153 // load the correct bytes. 6154 if (TLI.isBigEndian()) 6155 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6156 6157 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6158 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6159 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6160 return SDValue(); 6161 6162 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6163 Ptr.getValueType(), Ptr, 6164 DAG.getConstant(PtrOff, Ptr.getValueType())); 6165 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6166 LD->getChain(), NewPtr, 6167 LD->getPointerInfo().getWithOffset(PtrOff), 6168 LD->isVolatile(), LD->isNonTemporal(), 6169 NewAlign); 6170 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6171 DAG.getConstant(NewImm, NewVT)); 6172 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6173 NewVal, NewPtr, 6174 ST->getPointerInfo().getWithOffset(PtrOff), 6175 false, false, NewAlign); 6176 6177 AddToWorkList(NewPtr.getNode()); 6178 AddToWorkList(NewLD.getNode()); 6179 AddToWorkList(NewVal.getNode()); 6180 WorkListRemover DeadNodes(*this); 6181 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6182 &DeadNodes); 6183 ++OpsNarrowed; 6184 return NewST; 6185 } 6186 } 6187 6188 return SDValue(); 6189} 6190 6191/// TransformFPLoadStorePair - For a given floating point load / store pair, 6192/// if the load value isn't used by any other operations, then consider 6193/// transforming the pair to integer load / store operations if the target 6194/// deems the transformation profitable. 6195SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6196 StoreSDNode *ST = cast<StoreSDNode>(N); 6197 SDValue Chain = ST->getChain(); 6198 SDValue Value = ST->getValue(); 6199 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6200 Value.hasOneUse() && 6201 Chain == SDValue(Value.getNode(), 1)) { 6202 LoadSDNode *LD = cast<LoadSDNode>(Value); 6203 EVT VT = LD->getMemoryVT(); 6204 if (!VT.isFloatingPoint() || 6205 VT != ST->getMemoryVT() || 6206 LD->isNonTemporal() || 6207 ST->isNonTemporal() || 6208 LD->getPointerInfo().getAddrSpace() != 0 || 6209 ST->getPointerInfo().getAddrSpace() != 0) 6210 return SDValue(); 6211 6212 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6213 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6214 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6215 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6216 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6217 return SDValue(); 6218 6219 unsigned LDAlign = LD->getAlignment(); 6220 unsigned STAlign = ST->getAlignment(); 6221 const Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6222 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6223 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6224 return SDValue(); 6225 6226 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6227 LD->getChain(), LD->getBasePtr(), 6228 LD->getPointerInfo(), 6229 false, false, LDAlign); 6230 6231 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6232 NewLD, ST->getBasePtr(), 6233 ST->getPointerInfo(), 6234 false, false, STAlign); 6235 6236 AddToWorkList(NewLD.getNode()); 6237 AddToWorkList(NewST.getNode()); 6238 WorkListRemover DeadNodes(*this); 6239 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6240 &DeadNodes); 6241 ++LdStFP2Int; 6242 return NewST; 6243 } 6244 6245 return SDValue(); 6246} 6247 6248SDValue DAGCombiner::visitSTORE(SDNode *N) { 6249 StoreSDNode *ST = cast<StoreSDNode>(N); 6250 SDValue Chain = ST->getChain(); 6251 SDValue Value = ST->getValue(); 6252 SDValue Ptr = ST->getBasePtr(); 6253 6254 // If this is a store of a bit convert, store the input value if the 6255 // resultant store does not need a higher alignment than the original. 6256 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6257 ST->isUnindexed()) { 6258 unsigned OrigAlign = ST->getAlignment(); 6259 EVT SVT = Value.getOperand(0).getValueType(); 6260 unsigned Align = TLI.getTargetData()-> 6261 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6262 if (Align <= OrigAlign && 6263 ((!LegalOperations && !ST->isVolatile()) || 6264 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6265 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6266 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6267 ST->isNonTemporal(), OrigAlign); 6268 } 6269 6270 // Turn 'store undef, Ptr' -> nothing. 6271 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6272 return Chain; 6273 6274 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6275 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6276 // NOTE: If the original store is volatile, this transform must not increase 6277 // the number of stores. For example, on x86-32 an f64 can be stored in one 6278 // processor operation but an i64 (which is not legal) requires two. So the 6279 // transform should not be done in this case. 6280 if (Value.getOpcode() != ISD::TargetConstantFP) { 6281 SDValue Tmp; 6282 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6283 default: llvm_unreachable("Unknown FP type"); 6284 case MVT::f80: // We don't do this for these yet. 6285 case MVT::f128: 6286 case MVT::ppcf128: 6287 break; 6288 case MVT::f32: 6289 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6290 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6291 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6292 bitcastToAPInt().getZExtValue(), MVT::i32); 6293 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6294 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6295 ST->isNonTemporal(), ST->getAlignment()); 6296 } 6297 break; 6298 case MVT::f64: 6299 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6300 !ST->isVolatile()) || 6301 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6302 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6303 getZExtValue(), MVT::i64); 6304 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6305 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6306 ST->isNonTemporal(), ST->getAlignment()); 6307 } 6308 6309 if (!ST->isVolatile() && 6310 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6311 // Many FP stores are not made apparent until after legalize, e.g. for 6312 // argument passing. Since this is so common, custom legalize the 6313 // 64-bit integer store into two 32-bit stores. 6314 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6315 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6316 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6317 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6318 6319 unsigned Alignment = ST->getAlignment(); 6320 bool isVolatile = ST->isVolatile(); 6321 bool isNonTemporal = ST->isNonTemporal(); 6322 6323 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6324 Ptr, ST->getPointerInfo(), 6325 isVolatile, isNonTemporal, 6326 ST->getAlignment()); 6327 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6328 DAG.getConstant(4, Ptr.getValueType())); 6329 Alignment = MinAlign(Alignment, 4U); 6330 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6331 Ptr, ST->getPointerInfo().getWithOffset(4), 6332 isVolatile, isNonTemporal, 6333 Alignment); 6334 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6335 St0, St1); 6336 } 6337 6338 break; 6339 } 6340 } 6341 } 6342 6343 // Try to infer better alignment information than the store already has. 6344 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6345 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6346 if (Align > ST->getAlignment()) 6347 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6348 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6349 ST->isVolatile(), ST->isNonTemporal(), Align); 6350 } 6351 } 6352 6353 // Try transforming a pair floating point load / store ops to integer 6354 // load / store ops. 6355 SDValue NewST = TransformFPLoadStorePair(N); 6356 if (NewST.getNode()) 6357 return NewST; 6358 6359 if (CombinerAA) { 6360 // Walk up chain skipping non-aliasing memory nodes. 6361 SDValue BetterChain = FindBetterChain(N, Chain); 6362 6363 // If there is a better chain. 6364 if (Chain != BetterChain) { 6365 SDValue ReplStore; 6366 6367 // Replace the chain to avoid dependency. 6368 if (ST->isTruncatingStore()) { 6369 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6370 ST->getPointerInfo(), 6371 ST->getMemoryVT(), ST->isVolatile(), 6372 ST->isNonTemporal(), ST->getAlignment()); 6373 } else { 6374 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6375 ST->getPointerInfo(), 6376 ST->isVolatile(), ST->isNonTemporal(), 6377 ST->getAlignment()); 6378 } 6379 6380 // Create token to keep both nodes around. 6381 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6382 MVT::Other, Chain, ReplStore); 6383 6384 // Make sure the new and old chains are cleaned up. 6385 AddToWorkList(Token.getNode()); 6386 6387 // Don't add users to work list. 6388 return CombineTo(N, Token, false); 6389 } 6390 } 6391 6392 // Try transforming N to an indexed store. 6393 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6394 return SDValue(N, 0); 6395 6396 // FIXME: is there such a thing as a truncating indexed store? 6397 if (ST->isTruncatingStore() && ST->isUnindexed() && 6398 Value.getValueType().isInteger()) { 6399 // See if we can simplify the input to this truncstore with knowledge that 6400 // only the low bits are being used. For example: 6401 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6402 SDValue Shorter = 6403 GetDemandedBits(Value, 6404 APInt::getLowBitsSet(Value.getValueSizeInBits(), 6405 ST->getMemoryVT().getSizeInBits())); 6406 AddToWorkList(Value.getNode()); 6407 if (Shorter.getNode()) 6408 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6409 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6410 ST->isVolatile(), ST->isNonTemporal(), 6411 ST->getAlignment()); 6412 6413 // Otherwise, see if we can simplify the operation with 6414 // SimplifyDemandedBits, which only works if the value has a single use. 6415 if (SimplifyDemandedBits(Value, 6416 APInt::getLowBitsSet( 6417 Value.getValueType().getScalarType().getSizeInBits(), 6418 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6419 return SDValue(N, 0); 6420 } 6421 6422 // If this is a load followed by a store to the same location, then the store 6423 // is dead/noop. 6424 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6425 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6426 ST->isUnindexed() && !ST->isVolatile() && 6427 // There can't be any side effects between the load and store, such as 6428 // a call or store. 6429 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6430 // The store is dead, remove it. 6431 return Chain; 6432 } 6433 } 6434 6435 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6436 // truncating store. We can do this even if this is already a truncstore. 6437 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6438 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6439 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6440 ST->getMemoryVT())) { 6441 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6442 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6443 ST->isVolatile(), ST->isNonTemporal(), 6444 ST->getAlignment()); 6445 } 6446 6447 return ReduceLoadOpStoreWidth(N); 6448} 6449 6450SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6451 SDValue InVec = N->getOperand(0); 6452 SDValue InVal = N->getOperand(1); 6453 SDValue EltNo = N->getOperand(2); 6454 6455 // If the inserted element is an UNDEF, just use the input vector. 6456 if (InVal.getOpcode() == ISD::UNDEF) 6457 return InVec; 6458 6459 EVT VT = InVec.getValueType(); 6460 6461 // If we can't generate a legal BUILD_VECTOR, exit 6462 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 6463 return SDValue(); 6464 6465 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6466 // vector with the inserted element. 6467 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6468 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6469 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6470 InVec.getNode()->op_end()); 6471 if (Elt < Ops.size()) 6472 Ops[Elt] = InVal; 6473 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6474 VT, &Ops[0], Ops.size()); 6475 } 6476 // If the invec is an UNDEF and if EltNo is a constant, create a new 6477 // BUILD_VECTOR with undef elements and the inserted element. 6478 if (InVec.getOpcode() == ISD::UNDEF && 6479 isa<ConstantSDNode>(EltNo)) { 6480 EVT EltVT = VT.getVectorElementType(); 6481 unsigned NElts = VT.getVectorNumElements(); 6482 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6483 6484 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6485 if (Elt < Ops.size()) 6486 Ops[Elt] = InVal; 6487 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6488 VT, &Ops[0], Ops.size()); 6489 } 6490 return SDValue(); 6491} 6492 6493SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6494 // (vextract (scalar_to_vector val, 0) -> val 6495 SDValue InVec = N->getOperand(0); 6496 6497 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6498 // Check if the result type doesn't match the inserted element type. A 6499 // SCALAR_TO_VECTOR may truncate the inserted element and the 6500 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6501 SDValue InOp = InVec.getOperand(0); 6502 EVT NVT = N->getValueType(0); 6503 if (InOp.getValueType() != NVT) { 6504 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6505 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6506 } 6507 return InOp; 6508 } 6509 6510 // Perform only after legalization to ensure build_vector / vector_shuffle 6511 // optimizations have already been done. 6512 if (!LegalOperations) return SDValue(); 6513 6514 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6515 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6516 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6517 SDValue EltNo = N->getOperand(1); 6518 6519 if (isa<ConstantSDNode>(EltNo)) { 6520 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6521 bool NewLoad = false; 6522 bool BCNumEltsChanged = false; 6523 EVT VT = InVec.getValueType(); 6524 EVT ExtVT = VT.getVectorElementType(); 6525 EVT LVT = ExtVT; 6526 6527 if (InVec.getOpcode() == ISD::BITCAST) { 6528 EVT BCVT = InVec.getOperand(0).getValueType(); 6529 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6530 return SDValue(); 6531 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6532 BCNumEltsChanged = true; 6533 InVec = InVec.getOperand(0); 6534 ExtVT = BCVT.getVectorElementType(); 6535 NewLoad = true; 6536 } 6537 6538 LoadSDNode *LN0 = NULL; 6539 const ShuffleVectorSDNode *SVN = NULL; 6540 if (ISD::isNormalLoad(InVec.getNode())) { 6541 LN0 = cast<LoadSDNode>(InVec); 6542 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6543 InVec.getOperand(0).getValueType() == ExtVT && 6544 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6545 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6546 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6547 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6548 // => 6549 // (load $addr+1*size) 6550 6551 // If the bit convert changed the number of elements, it is unsafe 6552 // to examine the mask. 6553 if (BCNumEltsChanged) 6554 return SDValue(); 6555 6556 // Select the input vector, guarding against out of range extract vector. 6557 unsigned NumElems = VT.getVectorNumElements(); 6558 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 6559 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6560 6561 if (InVec.getOpcode() == ISD::BITCAST) 6562 InVec = InVec.getOperand(0); 6563 if (ISD::isNormalLoad(InVec.getNode())) { 6564 LN0 = cast<LoadSDNode>(InVec); 6565 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6566 } 6567 } 6568 6569 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6570 return SDValue(); 6571 6572 // If Idx was -1 above, Elt is going to be -1, so just return undef. 6573 if (Elt == -1) 6574 return DAG.getUNDEF(LN0->getBasePtr().getValueType()); 6575 6576 unsigned Align = LN0->getAlignment(); 6577 if (NewLoad) { 6578 // Check the resultant load doesn't need a higher alignment than the 6579 // original load. 6580 unsigned NewAlign = 6581 TLI.getTargetData() 6582 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6583 6584 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6585 return SDValue(); 6586 6587 Align = NewAlign; 6588 } 6589 6590 SDValue NewPtr = LN0->getBasePtr(); 6591 unsigned PtrOff = 0; 6592 6593 if (Elt) { 6594 PtrOff = LVT.getSizeInBits() * Elt / 8; 6595 EVT PtrType = NewPtr.getValueType(); 6596 if (TLI.isBigEndian()) 6597 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6598 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6599 DAG.getConstant(PtrOff, PtrType)); 6600 } 6601 6602 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6603 LN0->getPointerInfo().getWithOffset(PtrOff), 6604 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6605 } 6606 6607 return SDValue(); 6608} 6609 6610SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6611 unsigned NumInScalars = N->getNumOperands(); 6612 EVT VT = N->getValueType(0); 6613 6614 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6615 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6616 // at most two distinct vectors, turn this into a shuffle node. 6617 SDValue VecIn1, VecIn2; 6618 for (unsigned i = 0; i != NumInScalars; ++i) { 6619 // Ignore undef inputs. 6620 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6621 6622 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6623 // constant index, bail out. 6624 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6625 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6626 VecIn1 = VecIn2 = SDValue(0, 0); 6627 break; 6628 } 6629 6630 // If the input vector type disagrees with the result of the build_vector, 6631 // we can't make a shuffle. 6632 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6633 if (ExtractedFromVec.getValueType() != VT) { 6634 VecIn1 = VecIn2 = SDValue(0, 0); 6635 break; 6636 } 6637 6638 // Otherwise, remember this. We allow up to two distinct input vectors. 6639 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6640 continue; 6641 6642 if (VecIn1.getNode() == 0) { 6643 VecIn1 = ExtractedFromVec; 6644 } else if (VecIn2.getNode() == 0) { 6645 VecIn2 = ExtractedFromVec; 6646 } else { 6647 // Too many inputs. 6648 VecIn1 = VecIn2 = SDValue(0, 0); 6649 break; 6650 } 6651 } 6652 6653 // If everything is good, we can make a shuffle operation. 6654 if (VecIn1.getNode()) { 6655 SmallVector<int, 8> Mask; 6656 for (unsigned i = 0; i != NumInScalars; ++i) { 6657 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6658 Mask.push_back(-1); 6659 continue; 6660 } 6661 6662 // If extracting from the first vector, just use the index directly. 6663 SDValue Extract = N->getOperand(i); 6664 SDValue ExtVal = Extract.getOperand(1); 6665 if (Extract.getOperand(0) == VecIn1) { 6666 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6667 if (ExtIndex > VT.getVectorNumElements()) 6668 return SDValue(); 6669 6670 Mask.push_back(ExtIndex); 6671 continue; 6672 } 6673 6674 // Otherwise, use InIdx + VecSize 6675 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6676 Mask.push_back(Idx+NumInScalars); 6677 } 6678 6679 // Add count and size info. 6680 if (!isTypeLegal(VT)) 6681 return SDValue(); 6682 6683 // Return the new VECTOR_SHUFFLE node. 6684 SDValue Ops[2]; 6685 Ops[0] = VecIn1; 6686 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6687 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6688 } 6689 6690 return SDValue(); 6691} 6692 6693SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6694 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6695 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6696 // inputs come from at most two distinct vectors, turn this into a shuffle 6697 // node. 6698 6699 // If we only have one input vector, we don't need to do any concatenation. 6700 if (N->getNumOperands() == 1) 6701 return N->getOperand(0); 6702 6703 return SDValue(); 6704} 6705 6706SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6707 EVT VT = N->getValueType(0); 6708 unsigned NumElts = VT.getVectorNumElements(); 6709 6710 SDValue N0 = N->getOperand(0); 6711 6712 assert(N0.getValueType().getVectorNumElements() == NumElts && 6713 "Vector shuffle must be normalized in DAG"); 6714 6715 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6716 6717 // If it is a splat, check if the argument vector is another splat or a 6718 // build_vector with all scalar elements the same. 6719 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 6720 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 6721 SDNode *V = N0.getNode(); 6722 6723 // If this is a bit convert that changes the element type of the vector but 6724 // not the number of vector elements, look through it. Be careful not to 6725 // look though conversions that change things like v4f32 to v2f64. 6726 if (V->getOpcode() == ISD::BITCAST) { 6727 SDValue ConvInput = V->getOperand(0); 6728 if (ConvInput.getValueType().isVector() && 6729 ConvInput.getValueType().getVectorNumElements() == NumElts) 6730 V = ConvInput.getNode(); 6731 } 6732 6733 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6734 assert(V->getNumOperands() == NumElts && 6735 "BUILD_VECTOR has wrong number of operands"); 6736 SDValue Base; 6737 bool AllSame = true; 6738 for (unsigned i = 0; i != NumElts; ++i) { 6739 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6740 Base = V->getOperand(i); 6741 break; 6742 } 6743 } 6744 // Splat of <u, u, u, u>, return <u, u, u, u> 6745 if (!Base.getNode()) 6746 return N0; 6747 for (unsigned i = 0; i != NumElts; ++i) { 6748 if (V->getOperand(i) != Base) { 6749 AllSame = false; 6750 break; 6751 } 6752 } 6753 // Splat of <x, x, x, x>, return <x, x, x, x> 6754 if (AllSame) 6755 return N0; 6756 } 6757 } 6758 return SDValue(); 6759} 6760 6761SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 6762 if (!TLI.getShouldFoldAtomicFences()) 6763 return SDValue(); 6764 6765 SDValue atomic = N->getOperand(0); 6766 switch (atomic.getOpcode()) { 6767 case ISD::ATOMIC_CMP_SWAP: 6768 case ISD::ATOMIC_SWAP: 6769 case ISD::ATOMIC_LOAD_ADD: 6770 case ISD::ATOMIC_LOAD_SUB: 6771 case ISD::ATOMIC_LOAD_AND: 6772 case ISD::ATOMIC_LOAD_OR: 6773 case ISD::ATOMIC_LOAD_XOR: 6774 case ISD::ATOMIC_LOAD_NAND: 6775 case ISD::ATOMIC_LOAD_MIN: 6776 case ISD::ATOMIC_LOAD_MAX: 6777 case ISD::ATOMIC_LOAD_UMIN: 6778 case ISD::ATOMIC_LOAD_UMAX: 6779 break; 6780 default: 6781 return SDValue(); 6782 } 6783 6784 SDValue fence = atomic.getOperand(0); 6785 if (fence.getOpcode() != ISD::MEMBARRIER) 6786 return SDValue(); 6787 6788 switch (atomic.getOpcode()) { 6789 case ISD::ATOMIC_CMP_SWAP: 6790 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6791 fence.getOperand(0), 6792 atomic.getOperand(1), atomic.getOperand(2), 6793 atomic.getOperand(3)), atomic.getResNo()); 6794 case ISD::ATOMIC_SWAP: 6795 case ISD::ATOMIC_LOAD_ADD: 6796 case ISD::ATOMIC_LOAD_SUB: 6797 case ISD::ATOMIC_LOAD_AND: 6798 case ISD::ATOMIC_LOAD_OR: 6799 case ISD::ATOMIC_LOAD_XOR: 6800 case ISD::ATOMIC_LOAD_NAND: 6801 case ISD::ATOMIC_LOAD_MIN: 6802 case ISD::ATOMIC_LOAD_MAX: 6803 case ISD::ATOMIC_LOAD_UMIN: 6804 case ISD::ATOMIC_LOAD_UMAX: 6805 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6806 fence.getOperand(0), 6807 atomic.getOperand(1), atomic.getOperand(2)), 6808 atomic.getResNo()); 6809 default: 6810 return SDValue(); 6811 } 6812} 6813 6814/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6815/// an AND to a vector_shuffle with the destination vector and a zero vector. 6816/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6817/// vector_shuffle V, Zero, <0, 4, 2, 4> 6818SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6819 EVT VT = N->getValueType(0); 6820 DebugLoc dl = N->getDebugLoc(); 6821 SDValue LHS = N->getOperand(0); 6822 SDValue RHS = N->getOperand(1); 6823 if (N->getOpcode() == ISD::AND) { 6824 if (RHS.getOpcode() == ISD::BITCAST) 6825 RHS = RHS.getOperand(0); 6826 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6827 SmallVector<int, 8> Indices; 6828 unsigned NumElts = RHS.getNumOperands(); 6829 for (unsigned i = 0; i != NumElts; ++i) { 6830 SDValue Elt = RHS.getOperand(i); 6831 if (!isa<ConstantSDNode>(Elt)) 6832 return SDValue(); 6833 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6834 Indices.push_back(i); 6835 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6836 Indices.push_back(NumElts); 6837 else 6838 return SDValue(); 6839 } 6840 6841 // Let's see if the target supports this vector_shuffle. 6842 EVT RVT = RHS.getValueType(); 6843 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6844 return SDValue(); 6845 6846 // Return the new VECTOR_SHUFFLE node. 6847 EVT EltVT = RVT.getVectorElementType(); 6848 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6849 DAG.getConstant(0, EltVT)); 6850 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6851 RVT, &ZeroOps[0], ZeroOps.size()); 6852 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 6853 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6854 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 6855 } 6856 } 6857 6858 return SDValue(); 6859} 6860 6861/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6862SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6863 // After legalize, the target may be depending on adds and other 6864 // binary ops to provide legal ways to construct constants or other 6865 // things. Simplifying them may result in a loss of legality. 6866 if (LegalOperations) return SDValue(); 6867 6868 assert(N->getValueType(0).isVector() && 6869 "SimplifyVBinOp only works on vectors!"); 6870 6871 SDValue LHS = N->getOperand(0); 6872 SDValue RHS = N->getOperand(1); 6873 SDValue Shuffle = XformToShuffleWithZero(N); 6874 if (Shuffle.getNode()) return Shuffle; 6875 6876 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6877 // this operation. 6878 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6879 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6880 SmallVector<SDValue, 8> Ops; 6881 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6882 SDValue LHSOp = LHS.getOperand(i); 6883 SDValue RHSOp = RHS.getOperand(i); 6884 // If these two elements can't be folded, bail out. 6885 if ((LHSOp.getOpcode() != ISD::UNDEF && 6886 LHSOp.getOpcode() != ISD::Constant && 6887 LHSOp.getOpcode() != ISD::ConstantFP) || 6888 (RHSOp.getOpcode() != ISD::UNDEF && 6889 RHSOp.getOpcode() != ISD::Constant && 6890 RHSOp.getOpcode() != ISD::ConstantFP)) 6891 break; 6892 6893 // Can't fold divide by zero. 6894 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6895 N->getOpcode() == ISD::FDIV) { 6896 if ((RHSOp.getOpcode() == ISD::Constant && 6897 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6898 (RHSOp.getOpcode() == ISD::ConstantFP && 6899 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6900 break; 6901 } 6902 6903 EVT VT = LHSOp.getValueType(); 6904 assert(RHSOp.getValueType() == VT && 6905 "SimplifyVBinOp with different BUILD_VECTOR element types"); 6906 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 6907 LHSOp, RHSOp); 6908 if (FoldOp.getOpcode() != ISD::UNDEF && 6909 FoldOp.getOpcode() != ISD::Constant && 6910 FoldOp.getOpcode() != ISD::ConstantFP) 6911 break; 6912 Ops.push_back(FoldOp); 6913 AddToWorkList(FoldOp.getNode()); 6914 } 6915 6916 if (Ops.size() == LHS.getNumOperands()) 6917 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6918 LHS.getValueType(), &Ops[0], Ops.size()); 6919 } 6920 6921 return SDValue(); 6922} 6923 6924SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6925 SDValue N1, SDValue N2){ 6926 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6927 6928 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6929 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6930 6931 // If we got a simplified select_cc node back from SimplifySelectCC, then 6932 // break it down into a new SETCC node, and a new SELECT node, and then return 6933 // the SELECT node, since we were called with a SELECT node. 6934 if (SCC.getNode()) { 6935 // Check to see if we got a select_cc back (to turn into setcc/select). 6936 // Otherwise, just return whatever node we got back, like fabs. 6937 if (SCC.getOpcode() == ISD::SELECT_CC) { 6938 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6939 N0.getValueType(), 6940 SCC.getOperand(0), SCC.getOperand(1), 6941 SCC.getOperand(4)); 6942 AddToWorkList(SETCC.getNode()); 6943 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6944 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6945 } 6946 6947 return SCC; 6948 } 6949 return SDValue(); 6950} 6951 6952/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6953/// are the two values being selected between, see if we can simplify the 6954/// select. Callers of this should assume that TheSelect is deleted if this 6955/// returns true. As such, they should return the appropriate thing (e.g. the 6956/// node) back to the top-level of the DAG combiner loop to avoid it being 6957/// looked at. 6958bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6959 SDValue RHS) { 6960 6961 // Cannot simplify select with vector condition 6962 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 6963 6964 // If this is a select from two identical things, try to pull the operation 6965 // through the select. 6966 if (LHS.getOpcode() != RHS.getOpcode() || 6967 !LHS.hasOneUse() || !RHS.hasOneUse()) 6968 return false; 6969 6970 // If this is a load and the token chain is identical, replace the select 6971 // of two loads with a load through a select of the address to load from. 6972 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6973 // constants have been dropped into the constant pool. 6974 if (LHS.getOpcode() == ISD::LOAD) { 6975 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6976 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6977 6978 // Token chains must be identical. 6979 if (LHS.getOperand(0) != RHS.getOperand(0) || 6980 // Do not let this transformation reduce the number of volatile loads. 6981 LLD->isVolatile() || RLD->isVolatile() || 6982 // If this is an EXTLOAD, the VT's must match. 6983 LLD->getMemoryVT() != RLD->getMemoryVT() || 6984 // If this is an EXTLOAD, the kind of extension must match. 6985 (LLD->getExtensionType() != RLD->getExtensionType() && 6986 // The only exception is if one of the extensions is anyext. 6987 LLD->getExtensionType() != ISD::EXTLOAD && 6988 RLD->getExtensionType() != ISD::EXTLOAD) || 6989 // FIXME: this discards src value information. This is 6990 // over-conservative. It would be beneficial to be able to remember 6991 // both potential memory locations. Since we are discarding 6992 // src value info, don't do the transformation if the memory 6993 // locations are not in the default address space. 6994 LLD->getPointerInfo().getAddrSpace() != 0 || 6995 RLD->getPointerInfo().getAddrSpace() != 0) 6996 return false; 6997 6998 // Check that the select condition doesn't reach either load. If so, 6999 // folding this will induce a cycle into the DAG. If not, this is safe to 7000 // xform, so create a select of the addresses. 7001 SDValue Addr; 7002 if (TheSelect->getOpcode() == ISD::SELECT) { 7003 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 7004 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 7005 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 7006 return false; 7007 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 7008 LLD->getBasePtr().getValueType(), 7009 TheSelect->getOperand(0), LLD->getBasePtr(), 7010 RLD->getBasePtr()); 7011 } else { // Otherwise SELECT_CC 7012 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 7013 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 7014 7015 if ((LLD->hasAnyUseOfValue(1) && 7016 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 7017 (LLD->hasAnyUseOfValue(1) && 7018 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 7019 return false; 7020 7021 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 7022 LLD->getBasePtr().getValueType(), 7023 TheSelect->getOperand(0), 7024 TheSelect->getOperand(1), 7025 LLD->getBasePtr(), RLD->getBasePtr(), 7026 TheSelect->getOperand(4)); 7027 } 7028 7029 SDValue Load; 7030 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 7031 Load = DAG.getLoad(TheSelect->getValueType(0), 7032 TheSelect->getDebugLoc(), 7033 // FIXME: Discards pointer info. 7034 LLD->getChain(), Addr, MachinePointerInfo(), 7035 LLD->isVolatile(), LLD->isNonTemporal(), 7036 LLD->getAlignment()); 7037 } else { 7038 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 7039 RLD->getExtensionType() : LLD->getExtensionType(), 7040 TheSelect->getDebugLoc(), 7041 TheSelect->getValueType(0), 7042 // FIXME: Discards pointer info. 7043 LLD->getChain(), Addr, MachinePointerInfo(), 7044 LLD->getMemoryVT(), LLD->isVolatile(), 7045 LLD->isNonTemporal(), LLD->getAlignment()); 7046 } 7047 7048 // Users of the select now use the result of the load. 7049 CombineTo(TheSelect, Load); 7050 7051 // Users of the old loads now use the new load's chain. We know the 7052 // old-load value is dead now. 7053 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 7054 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 7055 return true; 7056 } 7057 7058 return false; 7059} 7060 7061/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 7062/// where 'cond' is the comparison specified by CC. 7063SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 7064 SDValue N2, SDValue N3, 7065 ISD::CondCode CC, bool NotExtCompare) { 7066 // (x ? y : y) -> y. 7067 if (N2 == N3) return N2; 7068 7069 EVT VT = N2.getValueType(); 7070 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 7071 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 7072 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 7073 7074 // Determine if the condition we're dealing with is constant 7075 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 7076 N0, N1, CC, DL, false); 7077 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 7078 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 7079 7080 // fold select_cc true, x, y -> x 7081 if (SCCC && !SCCC->isNullValue()) 7082 return N2; 7083 // fold select_cc false, x, y -> y 7084 if (SCCC && SCCC->isNullValue()) 7085 return N3; 7086 7087 // Check to see if we can simplify the select into an fabs node 7088 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 7089 // Allow either -0.0 or 0.0 7090 if (CFP->getValueAPF().isZero()) { 7091 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 7092 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 7093 N0 == N2 && N3.getOpcode() == ISD::FNEG && 7094 N2 == N3.getOperand(0)) 7095 return DAG.getNode(ISD::FABS, DL, VT, N0); 7096 7097 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 7098 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 7099 N0 == N3 && N2.getOpcode() == ISD::FNEG && 7100 N2.getOperand(0) == N3) 7101 return DAG.getNode(ISD::FABS, DL, VT, N3); 7102 } 7103 } 7104 7105 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 7106 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 7107 // in it. This is a win when the constant is not otherwise available because 7108 // it replaces two constant pool loads with one. We only do this if the FP 7109 // type is known to be legal, because if it isn't, then we are before legalize 7110 // types an we want the other legalization to happen first (e.g. to avoid 7111 // messing with soft float) and if the ConstantFP is not legal, because if 7112 // it is legal, we may not need to store the FP constant in a constant pool. 7113 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 7114 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 7115 if (TLI.isTypeLegal(N2.getValueType()) && 7116 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 7117 TargetLowering::Legal) && 7118 // If both constants have multiple uses, then we won't need to do an 7119 // extra load, they are likely around in registers for other users. 7120 (TV->hasOneUse() || FV->hasOneUse())) { 7121 Constant *Elts[] = { 7122 const_cast<ConstantFP*>(FV->getConstantFPValue()), 7123 const_cast<ConstantFP*>(TV->getConstantFPValue()) 7124 }; 7125 const Type *FPTy = Elts[0]->getType(); 7126 const TargetData &TD = *TLI.getTargetData(); 7127 7128 // Create a ConstantArray of the two constants. 7129 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 7130 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 7131 TD.getPrefTypeAlignment(FPTy)); 7132 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 7133 7134 // Get the offsets to the 0 and 1 element of the array so that we can 7135 // select between them. 7136 SDValue Zero = DAG.getIntPtrConstant(0); 7137 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 7138 SDValue One = DAG.getIntPtrConstant(EltSize); 7139 7140 SDValue Cond = DAG.getSetCC(DL, 7141 TLI.getSetCCResultType(N0.getValueType()), 7142 N0, N1, CC); 7143 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 7144 Cond, One, Zero); 7145 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 7146 CstOffset); 7147 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 7148 MachinePointerInfo::getConstantPool(), false, 7149 false, Alignment); 7150 7151 } 7152 } 7153 7154 // Check to see if we can perform the "gzip trick", transforming 7155 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 7156 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 7157 N0.getValueType().isInteger() && 7158 N2.getValueType().isInteger() && 7159 (N1C->isNullValue() || // (a < 0) ? b : 0 7160 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 7161 EVT XType = N0.getValueType(); 7162 EVT AType = N2.getValueType(); 7163 if (XType.bitsGE(AType)) { 7164 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 7165 // single-bit constant. 7166 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 7167 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 7168 ShCtV = XType.getSizeInBits()-ShCtV-1; 7169 SDValue ShCt = DAG.getConstant(ShCtV, 7170 getShiftAmountTy(N0.getValueType())); 7171 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 7172 XType, N0, ShCt); 7173 AddToWorkList(Shift.getNode()); 7174 7175 if (XType.bitsGT(AType)) { 7176 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7177 AddToWorkList(Shift.getNode()); 7178 } 7179 7180 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7181 } 7182 7183 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 7184 XType, N0, 7185 DAG.getConstant(XType.getSizeInBits()-1, 7186 getShiftAmountTy(N0.getValueType()))); 7187 AddToWorkList(Shift.getNode()); 7188 7189 if (XType.bitsGT(AType)) { 7190 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7191 AddToWorkList(Shift.getNode()); 7192 } 7193 7194 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7195 } 7196 } 7197 7198 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 7199 // where y is has a single bit set. 7200 // A plaintext description would be, we can turn the SELECT_CC into an AND 7201 // when the condition can be materialized as an all-ones register. Any 7202 // single bit-test can be materialized as an all-ones register with 7203 // shift-left and shift-right-arith. 7204 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 7205 N0->getValueType(0) == VT && 7206 N1C && N1C->isNullValue() && 7207 N2C && N2C->isNullValue()) { 7208 SDValue AndLHS = N0->getOperand(0); 7209 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 7210 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 7211 // Shift the tested bit over the sign bit. 7212 APInt AndMask = ConstAndRHS->getAPIntValue(); 7213 SDValue ShlAmt = 7214 DAG.getConstant(AndMask.countLeadingZeros(), 7215 getShiftAmountTy(AndLHS.getValueType())); 7216 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 7217 7218 // Now arithmetic right shift it all the way over, so the result is either 7219 // all-ones, or zero. 7220 SDValue ShrAmt = 7221 DAG.getConstant(AndMask.getBitWidth()-1, 7222 getShiftAmountTy(Shl.getValueType())); 7223 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 7224 7225 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 7226 } 7227 } 7228 7229 // fold select C, 16, 0 -> shl C, 4 7230 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 7231 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 7232 7233 // If the caller doesn't want us to simplify this into a zext of a compare, 7234 // don't do it. 7235 if (NotExtCompare && N2C->getAPIntValue() == 1) 7236 return SDValue(); 7237 7238 // Get a SetCC of the condition 7239 // FIXME: Should probably make sure that setcc is legal if we ever have a 7240 // target where it isn't. 7241 SDValue Temp, SCC; 7242 // cast from setcc result type to select result type 7243 if (LegalTypes) { 7244 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 7245 N0, N1, CC); 7246 if (N2.getValueType().bitsLT(SCC.getValueType())) 7247 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 7248 else 7249 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7250 N2.getValueType(), SCC); 7251 } else { 7252 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 7253 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7254 N2.getValueType(), SCC); 7255 } 7256 7257 AddToWorkList(SCC.getNode()); 7258 AddToWorkList(Temp.getNode()); 7259 7260 if (N2C->getAPIntValue() == 1) 7261 return Temp; 7262 7263 // shl setcc result by log2 n2c 7264 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 7265 DAG.getConstant(N2C->getAPIntValue().logBase2(), 7266 getShiftAmountTy(Temp.getValueType()))); 7267 } 7268 7269 // Check to see if this is the equivalent of setcc 7270 // FIXME: Turn all of these into setcc if setcc if setcc is legal 7271 // otherwise, go ahead with the folds. 7272 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 7273 EVT XType = N0.getValueType(); 7274 if (!LegalOperations || 7275 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 7276 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 7277 if (Res.getValueType() != VT) 7278 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 7279 return Res; 7280 } 7281 7282 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 7283 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 7284 (!LegalOperations || 7285 TLI.isOperationLegal(ISD::CTLZ, XType))) { 7286 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 7287 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 7288 DAG.getConstant(Log2_32(XType.getSizeInBits()), 7289 getShiftAmountTy(Ctlz.getValueType()))); 7290 } 7291 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 7292 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 7293 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 7294 XType, DAG.getConstant(0, XType), N0); 7295 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 7296 return DAG.getNode(ISD::SRL, DL, XType, 7297 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 7298 DAG.getConstant(XType.getSizeInBits()-1, 7299 getShiftAmountTy(XType))); 7300 } 7301 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 7302 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 7303 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 7304 DAG.getConstant(XType.getSizeInBits()-1, 7305 getShiftAmountTy(N0.getValueType()))); 7306 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 7307 } 7308 } 7309 7310 // Check to see if this is an integer abs. 7311 // select_cc setg[te] X, 0, X, -X -> 7312 // select_cc setgt X, -1, X, -X -> 7313 // select_cc setl[te] X, 0, -X, X -> 7314 // select_cc setlt X, 1, -X, X -> 7315 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 7316 if (N1C) { 7317 ConstantSDNode *SubC = NULL; 7318 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 7319 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 7320 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7321 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7322 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7323 (N1C->isOne() && CC == ISD::SETLT)) && 7324 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7325 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7326 7327 EVT XType = N0.getValueType(); 7328 if (SubC && SubC->isNullValue() && XType.isInteger()) { 7329 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7330 N0, 7331 DAG.getConstant(XType.getSizeInBits()-1, 7332 getShiftAmountTy(N0.getValueType()))); 7333 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7334 XType, N0, Shift); 7335 AddToWorkList(Shift.getNode()); 7336 AddToWorkList(Add.getNode()); 7337 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7338 } 7339 } 7340 7341 return SDValue(); 7342} 7343 7344/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 7345SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 7346 SDValue N1, ISD::CondCode Cond, 7347 DebugLoc DL, bool foldBooleans) { 7348 TargetLowering::DAGCombinerInfo 7349 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 7350 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 7351} 7352 7353/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 7354/// return a DAG expression to select that will generate the same value by 7355/// multiplying by a magic number. See: 7356/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7357SDValue DAGCombiner::BuildSDIV(SDNode *N) { 7358 std::vector<SDNode*> Built; 7359 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 7360 7361 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7362 ii != ee; ++ii) 7363 AddToWorkList(*ii); 7364 return S; 7365} 7366 7367/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 7368/// return a DAG expression to select that will generate the same value by 7369/// multiplying by a magic number. See: 7370/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7371SDValue DAGCombiner::BuildUDIV(SDNode *N) { 7372 std::vector<SDNode*> Built; 7373 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 7374 7375 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7376 ii != ee; ++ii) 7377 AddToWorkList(*ii); 7378 return S; 7379} 7380 7381/// FindBaseOffset - Return true if base is a frame index, which is known not 7382// to alias with anything but itself. Provides base object and offset as 7383// results. 7384static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7385 const GlobalValue *&GV, void *&CV) { 7386 // Assume it is a primitive operation. 7387 Base = Ptr; Offset = 0; GV = 0; CV = 0; 7388 7389 // If it's an adding a simple constant then integrate the offset. 7390 if (Base.getOpcode() == ISD::ADD) { 7391 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7392 Base = Base.getOperand(0); 7393 Offset += C->getZExtValue(); 7394 } 7395 } 7396 7397 // Return the underlying GlobalValue, and update the Offset. Return false 7398 // for GlobalAddressSDNode since the same GlobalAddress may be represented 7399 // by multiple nodes with different offsets. 7400 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7401 GV = G->getGlobal(); 7402 Offset += G->getOffset(); 7403 return false; 7404 } 7405 7406 // Return the underlying Constant value, and update the Offset. Return false 7407 // for ConstantSDNodes since the same constant pool entry may be represented 7408 // by multiple nodes with different offsets. 7409 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7410 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7411 : (void *)C->getConstVal(); 7412 Offset += C->getOffset(); 7413 return false; 7414 } 7415 // If it's any of the following then it can't alias with anything but itself. 7416 return isa<FrameIndexSDNode>(Base); 7417} 7418 7419/// isAlias - Return true if there is any possibility that the two addresses 7420/// overlap. 7421bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7422 const Value *SrcValue1, int SrcValueOffset1, 7423 unsigned SrcValueAlign1, 7424 const MDNode *TBAAInfo1, 7425 SDValue Ptr2, int64_t Size2, 7426 const Value *SrcValue2, int SrcValueOffset2, 7427 unsigned SrcValueAlign2, 7428 const MDNode *TBAAInfo2) const { 7429 // If they are the same then they must be aliases. 7430 if (Ptr1 == Ptr2) return true; 7431 7432 // Gather base node and offset information. 7433 SDValue Base1, Base2; 7434 int64_t Offset1, Offset2; 7435 const GlobalValue *GV1, *GV2; 7436 void *CV1, *CV2; 7437 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7438 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7439 7440 // If they have a same base address then check to see if they overlap. 7441 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7442 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7443 7444 // It is possible for different frame indices to alias each other, mostly 7445 // when tail call optimization reuses return address slots for arguments. 7446 // To catch this case, look up the actual index of frame indices to compute 7447 // the real alias relationship. 7448 if (isFrameIndex1 && isFrameIndex2) { 7449 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7450 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7451 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7452 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7453 } 7454 7455 // Otherwise, if we know what the bases are, and they aren't identical, then 7456 // we know they cannot alias. 7457 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7458 return false; 7459 7460 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7461 // compared to the size and offset of the access, we may be able to prove they 7462 // do not alias. This check is conservative for now to catch cases created by 7463 // splitting vector types. 7464 if ((SrcValueAlign1 == SrcValueAlign2) && 7465 (SrcValueOffset1 != SrcValueOffset2) && 7466 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7467 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7468 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7469 7470 // There is no overlap between these relatively aligned accesses of similar 7471 // size, return no alias. 7472 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7473 return false; 7474 } 7475 7476 if (CombinerGlobalAA) { 7477 // Use alias analysis information. 7478 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7479 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7480 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7481 AliasAnalysis::AliasResult AAResult = 7482 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 7483 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 7484 if (AAResult == AliasAnalysis::NoAlias) 7485 return false; 7486 } 7487 7488 // Otherwise we have to assume they alias. 7489 return true; 7490} 7491 7492/// FindAliasInfo - Extracts the relevant alias information from the memory 7493/// node. Returns true if the operand was a load. 7494bool DAGCombiner::FindAliasInfo(SDNode *N, 7495 SDValue &Ptr, int64_t &Size, 7496 const Value *&SrcValue, 7497 int &SrcValueOffset, 7498 unsigned &SrcValueAlign, 7499 const MDNode *&TBAAInfo) const { 7500 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7501 Ptr = LD->getBasePtr(); 7502 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7503 SrcValue = LD->getSrcValue(); 7504 SrcValueOffset = LD->getSrcValueOffset(); 7505 SrcValueAlign = LD->getOriginalAlignment(); 7506 TBAAInfo = LD->getTBAAInfo(); 7507 return true; 7508 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7509 Ptr = ST->getBasePtr(); 7510 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7511 SrcValue = ST->getSrcValue(); 7512 SrcValueOffset = ST->getSrcValueOffset(); 7513 SrcValueAlign = ST->getOriginalAlignment(); 7514 TBAAInfo = ST->getTBAAInfo(); 7515 } else { 7516 llvm_unreachable("FindAliasInfo expected a memory operand"); 7517 } 7518 7519 return false; 7520} 7521 7522/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7523/// looking for aliasing nodes and adding them to the Aliases vector. 7524void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7525 SmallVector<SDValue, 8> &Aliases) { 7526 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7527 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7528 7529 // Get alias information for node. 7530 SDValue Ptr; 7531 int64_t Size; 7532 const Value *SrcValue; 7533 int SrcValueOffset; 7534 unsigned SrcValueAlign; 7535 const MDNode *SrcTBAAInfo; 7536 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7537 SrcValueAlign, SrcTBAAInfo); 7538 7539 // Starting off. 7540 Chains.push_back(OriginalChain); 7541 unsigned Depth = 0; 7542 7543 // Look at each chain and determine if it is an alias. If so, add it to the 7544 // aliases list. If not, then continue up the chain looking for the next 7545 // candidate. 7546 while (!Chains.empty()) { 7547 SDValue Chain = Chains.back(); 7548 Chains.pop_back(); 7549 7550 // For TokenFactor nodes, look at each operand and only continue up the 7551 // chain until we find two aliases. If we've seen two aliases, assume we'll 7552 // find more and revert to original chain since the xform is unlikely to be 7553 // profitable. 7554 // 7555 // FIXME: The depth check could be made to return the last non-aliasing 7556 // chain we found before we hit a tokenfactor rather than the original 7557 // chain. 7558 if (Depth > 6 || Aliases.size() == 2) { 7559 Aliases.clear(); 7560 Aliases.push_back(OriginalChain); 7561 break; 7562 } 7563 7564 // Don't bother if we've been before. 7565 if (!Visited.insert(Chain.getNode())) 7566 continue; 7567 7568 switch (Chain.getOpcode()) { 7569 case ISD::EntryToken: 7570 // Entry token is ideal chain operand, but handled in FindBetterChain. 7571 break; 7572 7573 case ISD::LOAD: 7574 case ISD::STORE: { 7575 // Get alias information for Chain. 7576 SDValue OpPtr; 7577 int64_t OpSize; 7578 const Value *OpSrcValue; 7579 int OpSrcValueOffset; 7580 unsigned OpSrcValueAlign; 7581 const MDNode *OpSrcTBAAInfo; 7582 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7583 OpSrcValue, OpSrcValueOffset, 7584 OpSrcValueAlign, 7585 OpSrcTBAAInfo); 7586 7587 // If chain is alias then stop here. 7588 if (!(IsLoad && IsOpLoad) && 7589 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7590 SrcTBAAInfo, 7591 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7592 OpSrcValueAlign, OpSrcTBAAInfo)) { 7593 Aliases.push_back(Chain); 7594 } else { 7595 // Look further up the chain. 7596 Chains.push_back(Chain.getOperand(0)); 7597 ++Depth; 7598 } 7599 break; 7600 } 7601 7602 case ISD::TokenFactor: 7603 // We have to check each of the operands of the token factor for "small" 7604 // token factors, so we queue them up. Adding the operands to the queue 7605 // (stack) in reverse order maintains the original order and increases the 7606 // likelihood that getNode will find a matching token factor (CSE.) 7607 if (Chain.getNumOperands() > 16) { 7608 Aliases.push_back(Chain); 7609 break; 7610 } 7611 for (unsigned n = Chain.getNumOperands(); n;) 7612 Chains.push_back(Chain.getOperand(--n)); 7613 ++Depth; 7614 break; 7615 7616 default: 7617 // For all other instructions we will just have to take what we can get. 7618 Aliases.push_back(Chain); 7619 break; 7620 } 7621 } 7622} 7623 7624/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7625/// for a better chain (aliasing node.) 7626SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7627 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7628 7629 // Accumulate all the aliases to this node. 7630 GatherAllAliases(N, OldChain, Aliases); 7631 7632 if (Aliases.size() == 0) { 7633 // If no operands then chain to entry token. 7634 return DAG.getEntryNode(); 7635 } else if (Aliases.size() == 1) { 7636 // If a single operand then chain to it. We don't need to revisit it. 7637 return Aliases[0]; 7638 } 7639 7640 // Construct a custom tailored token factor. 7641 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7642 &Aliases[0], Aliases.size()); 7643} 7644 7645// SelectionDAG::Combine - This is the entry point for the file. 7646// 7647void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7648 CodeGenOpt::Level OptLevel) { 7649 /// run - This is the main entry point to this class. 7650 /// 7651 DAGCombiner(*this, AA, OptLevel).Run(Level); 7652} 7653