DAGCombiner.cpp revision 501fee71e077aad705ab2ab86741aec15b779174
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/CodeGen/SelectionDAG.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/Target/TargetData.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include "llvm/ADT/Statistic.h" 40#include "llvm/Support/Compiler.h" 41#include "llvm/Support/CommandLine.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Support/MathExtras.h" 44#include <algorithm> 45using namespace llvm; 46 47STATISTIC(NodesCombined , "Number of dag nodes combined"); 48STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 49STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 50 51namespace { 52#ifndef NDEBUG 53 static cl::opt<bool> 54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 55 cl::desc("Pop up a window to show dags before the first " 56 "dag combine pass")); 57 static cl::opt<bool> 58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 59 cl::desc("Pop up a window to show dags before the second " 60 "dag combine pass")); 61#else 62 static const bool ViewDAGCombine1 = false; 63 static const bool ViewDAGCombine2 = false; 64#endif 65 66 static cl::opt<bool> 67 CombinerAA("combiner-alias-analysis", cl::Hidden, 68 cl::desc("Turn on alias analysis during testing")); 69 70 static cl::opt<bool> 71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 72 cl::desc("Include global information in alias analysis")); 73 74//------------------------------ DAGCombiner ---------------------------------// 75 76 class VISIBILITY_HIDDEN DAGCombiner { 77 SelectionDAG &DAG; 78 TargetLowering &TLI; 79 bool AfterLegalize; 80 81 // Worklist of all of the nodes that need to be simplified. 82 std::vector<SDNode*> WorkList; 83 84 // AA - Used for DAG load/store alias analysis. 85 AliasAnalysis &AA; 86 87 /// AddUsersToWorkList - When an instruction is simplified, add all users of 88 /// the instruction to the work lists because they might get more simplified 89 /// now. 90 /// 91 void AddUsersToWorkList(SDNode *N) { 92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 93 UI != UE; ++UI) 94 AddToWorkList(*UI); 95 } 96 97 /// removeFromWorkList - remove all instances of N from the worklist. 98 /// 99 void removeFromWorkList(SDNode *N) { 100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 101 WorkList.end()); 102 } 103 104 public: 105 /// AddToWorkList - Add to the work list making sure it's instance is at the 106 /// the back (next to be processed.) 107 void AddToWorkList(SDNode *N) { 108 removeFromWorkList(N); 109 WorkList.push_back(N); 110 } 111 112 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 113 bool AddTo = true) { 114 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 115 ++NodesCombined; 116 DOUT << "\nReplacing.1 "; DEBUG(N->dump()); 117 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 118 DOUT << " and " << NumTo-1 << " other values\n"; 119 std::vector<SDNode*> NowDead; 120 DAG.ReplaceAllUsesWith(N, To, &NowDead); 121 122 if (AddTo) { 123 // Push the new nodes and any users onto the worklist 124 for (unsigned i = 0, e = NumTo; i != e; ++i) { 125 AddToWorkList(To[i].Val); 126 AddUsersToWorkList(To[i].Val); 127 } 128 } 129 130 // Nodes can be reintroduced into the worklist. Make sure we do not 131 // process a node that has been replaced. 132 removeFromWorkList(N); 133 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 134 removeFromWorkList(NowDead[i]); 135 136 // Finally, since the node is now dead, remove it from the graph. 137 DAG.DeleteNode(N); 138 return SDOperand(N, 0); 139 } 140 141 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 142 return CombineTo(N, &Res, 1, AddTo); 143 } 144 145 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 146 bool AddTo = true) { 147 SDOperand To[] = { Res0, Res1 }; 148 return CombineTo(N, To, 2, AddTo); 149 } 150 private: 151 152 /// SimplifyDemandedBits - Check the specified integer node value to see if 153 /// it can be simplified or if things it uses can be simplified by bit 154 /// propagation. If so, return true. 155 bool SimplifyDemandedBits(SDOperand Op) { 156 TargetLowering::TargetLoweringOpt TLO(DAG); 157 uint64_t KnownZero, KnownOne; 158 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 159 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 160 return false; 161 162 // Revisit the node. 163 AddToWorkList(Op.Val); 164 165 // Replace the old value with the new one. 166 ++NodesCombined; 167 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump()); 168 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 169 DOUT << '\n'; 170 171 std::vector<SDNode*> NowDead; 172 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 173 174 // Push the new node and any (possibly new) users onto the worklist. 175 AddToWorkList(TLO.New.Val); 176 AddUsersToWorkList(TLO.New.Val); 177 178 // Nodes can end up on the worklist more than once. Make sure we do 179 // not process a node that has been replaced. 180 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 181 removeFromWorkList(NowDead[i]); 182 183 // Finally, if the node is now dead, remove it from the graph. The node 184 // may not be dead if the replacement process recursively simplified to 185 // something else needing this node. 186 if (TLO.Old.Val->use_empty()) { 187 removeFromWorkList(TLO.Old.Val); 188 189 // If the operands of this node are only used by the node, they will now 190 // be dead. Make sure to visit them first to delete dead nodes early. 191 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 192 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 193 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 194 195 DAG.DeleteNode(TLO.Old.Val); 196 } 197 return true; 198 } 199 200 bool CombineToPreIndexedLoadStore(SDNode *N); 201 bool CombineToPostIndexedLoadStore(SDNode *N); 202 203 204 /// visit - call the node-specific routine that knows how to fold each 205 /// particular type of node. 206 SDOperand visit(SDNode *N); 207 208 // Visitation implementation - Implement dag node combining for different 209 // node types. The semantics are as follows: 210 // Return Value: 211 // SDOperand.Val == 0 - No change was made 212 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 213 // otherwise - N should be replaced by the returned Operand. 214 // 215 SDOperand visitTokenFactor(SDNode *N); 216 SDOperand visitADD(SDNode *N); 217 SDOperand visitSUB(SDNode *N); 218 SDOperand visitADDC(SDNode *N); 219 SDOperand visitADDE(SDNode *N); 220 SDOperand visitMUL(SDNode *N); 221 SDOperand visitSDIV(SDNode *N); 222 SDOperand visitUDIV(SDNode *N); 223 SDOperand visitSREM(SDNode *N); 224 SDOperand visitUREM(SDNode *N); 225 SDOperand visitMULHU(SDNode *N); 226 SDOperand visitMULHS(SDNode *N); 227 SDOperand visitAND(SDNode *N); 228 SDOperand visitOR(SDNode *N); 229 SDOperand visitXOR(SDNode *N); 230 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 231 SDOperand visitSHL(SDNode *N); 232 SDOperand visitSRA(SDNode *N); 233 SDOperand visitSRL(SDNode *N); 234 SDOperand visitCTLZ(SDNode *N); 235 SDOperand visitCTTZ(SDNode *N); 236 SDOperand visitCTPOP(SDNode *N); 237 SDOperand visitSELECT(SDNode *N); 238 SDOperand visitSELECT_CC(SDNode *N); 239 SDOperand visitSETCC(SDNode *N); 240 SDOperand visitSIGN_EXTEND(SDNode *N); 241 SDOperand visitZERO_EXTEND(SDNode *N); 242 SDOperand visitANY_EXTEND(SDNode *N); 243 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 244 SDOperand visitTRUNCATE(SDNode *N); 245 SDOperand visitBIT_CONVERT(SDNode *N); 246 SDOperand visitVBIT_CONVERT(SDNode *N); 247 SDOperand visitFADD(SDNode *N); 248 SDOperand visitFSUB(SDNode *N); 249 SDOperand visitFMUL(SDNode *N); 250 SDOperand visitFDIV(SDNode *N); 251 SDOperand visitFREM(SDNode *N); 252 SDOperand visitFCOPYSIGN(SDNode *N); 253 SDOperand visitSINT_TO_FP(SDNode *N); 254 SDOperand visitUINT_TO_FP(SDNode *N); 255 SDOperand visitFP_TO_SINT(SDNode *N); 256 SDOperand visitFP_TO_UINT(SDNode *N); 257 SDOperand visitFP_ROUND(SDNode *N); 258 SDOperand visitFP_ROUND_INREG(SDNode *N); 259 SDOperand visitFP_EXTEND(SDNode *N); 260 SDOperand visitFNEG(SDNode *N); 261 SDOperand visitFABS(SDNode *N); 262 SDOperand visitBRCOND(SDNode *N); 263 SDOperand visitBR_CC(SDNode *N); 264 SDOperand visitLOAD(SDNode *N); 265 SDOperand visitSTORE(SDNode *N); 266 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 267 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 268 SDOperand visitVBUILD_VECTOR(SDNode *N); 269 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 270 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 271 272 SDOperand XformToShuffleWithZero(SDNode *N); 273 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 274 275 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 276 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 277 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 278 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 279 SDOperand N3, ISD::CondCode CC, 280 bool NotExtCompare = false); 281 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 282 ISD::CondCode Cond, bool foldBooleans = true); 283 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 284 SDOperand BuildSDIV(SDNode *N); 285 SDOperand BuildUDIV(SDNode *N); 286 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 287 SDOperand ReduceLoadWidth(SDNode *N); 288 289 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 290 /// looking for aliasing nodes and adding them to the Aliases vector. 291 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 292 SmallVector<SDOperand, 8> &Aliases); 293 294 /// isAlias - Return true if there is any possibility that the two addresses 295 /// overlap. 296 bool isAlias(SDOperand Ptr1, int64_t Size1, 297 const Value *SrcValue1, int SrcValueOffset1, 298 SDOperand Ptr2, int64_t Size2, 299 const Value *SrcValue2, int SrcValueOffset2); 300 301 /// FindAliasInfo - Extracts the relevant alias information from the memory 302 /// node. Returns true if the operand was a load. 303 bool FindAliasInfo(SDNode *N, 304 SDOperand &Ptr, int64_t &Size, 305 const Value *&SrcValue, int &SrcValueOffset); 306 307 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 308 /// looking for a better chain (aliasing node.) 309 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 310 311public: 312 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 313 : DAG(D), 314 TLI(D.getTargetLoweringInfo()), 315 AfterLegalize(false), 316 AA(A) {} 317 318 /// Run - runs the dag combiner on all nodes in the work list 319 void Run(bool RunningAfterLegalize); 320 }; 321} 322 323//===----------------------------------------------------------------------===// 324// TargetLowering::DAGCombinerInfo implementation 325//===----------------------------------------------------------------------===// 326 327void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 328 ((DAGCombiner*)DC)->AddToWorkList(N); 329} 330 331SDOperand TargetLowering::DAGCombinerInfo:: 332CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 333 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 334} 335 336SDOperand TargetLowering::DAGCombinerInfo:: 337CombineTo(SDNode *N, SDOperand Res) { 338 return ((DAGCombiner*)DC)->CombineTo(N, Res); 339} 340 341 342SDOperand TargetLowering::DAGCombinerInfo:: 343CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 344 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 345} 346 347 348//===----------------------------------------------------------------------===// 349// Helper Functions 350//===----------------------------------------------------------------------===// 351 352/// isNegatibleForFree - Return 1 if we can compute the negated form of the 353/// specified expression for the same cost as the expression itself, or 2 if we 354/// can compute the negated form more cheaply than the expression itself. 355static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 356 // Don't recurse exponentially. 357 if (Depth > 6) return false; 358 359 // fneg is removable even if it has multiple uses. 360 if (Op.getOpcode() == ISD::FNEG) return 2; 361 362 // Don't allow anything with multiple uses. 363 if (!Op.hasOneUse()) return 0; 364 365 switch (Op.getOpcode()) { 366 default: return false; 367 case ISD::ConstantFP: 368 return 1; 369 case ISD::FADD: 370 // FIXME: determine better conditions for this xform. 371 if (!UnsafeFPMath) return 0; 372 373 // -(A+B) -> -A - B 374 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 375 return V; 376 // -(A+B) -> -B - A 377 return isNegatibleForFree(Op.getOperand(1), Depth+1); 378 case ISD::FSUB: 379 // We can't turn -(A-B) into B-A when we honor signed zeros. 380 if (!UnsafeFPMath) return 0; 381 382 // -(A-B) -> B-A 383 return 1; 384 385 case ISD::FMUL: 386 case ISD::FDIV: 387 if (HonorSignDependentRoundingFPMath()) return 0; 388 389 // -(X*Y) -> (-X * Y) or (X*-Y) 390 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 391 return V; 392 393 return isNegatibleForFree(Op.getOperand(1), Depth+1); 394 395 case ISD::FP_EXTEND: 396 case ISD::FP_ROUND: 397 case ISD::FSIN: 398 return isNegatibleForFree(Op.getOperand(0), Depth+1); 399 } 400} 401 402/// GetNegatedExpression - If isNegatibleForFree returns true, this function 403/// returns the newly negated expression. 404static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG) { 405 // fneg is removable even if it has multiple uses. 406 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 407 408 // Don't allow anything with multiple uses. 409 assert(Op.hasOneUse() && "Unknown reuse!"); 410 411 switch (Op.getOpcode()) { 412 default: assert(0 && "Unknown code"); 413 case ISD::ConstantFP: 414 return DAG.getConstantFP(-cast<ConstantFPSDNode>(Op)->getValue(), 415 Op.getValueType()); 416 case ISD::FADD: 417 // FIXME: determine better conditions for this xform. 418 assert(UnsafeFPMath); 419 420 // -(A+B) -> -A - B 421 if (isNegatibleForFree(Op.getOperand(0))) 422 return DAG.getNode(ISD::FSUB, Op.getValueType(), 423 GetNegatedExpression(Op.getOperand(0), DAG), 424 Op.getOperand(1)); 425 // -(A+B) -> -B - A 426 return DAG.getNode(ISD::FSUB, Op.getValueType(), 427 GetNegatedExpression(Op.getOperand(1), DAG), 428 Op.getOperand(0)); 429 case ISD::FSUB: 430 // We can't turn -(A-B) into B-A when we honor signed zeros. 431 assert(UnsafeFPMath); 432 433 // -(A-B) -> B-A 434 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 435 Op.getOperand(0)); 436 437 case ISD::FMUL: 438 case ISD::FDIV: 439 assert(!HonorSignDependentRoundingFPMath()); 440 441 // -(X*Y) -> -X * Y 442 if (isNegatibleForFree(Op.getOperand(0))) 443 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 444 GetNegatedExpression(Op.getOperand(0), DAG), 445 Op.getOperand(1)); 446 447 // -(X*Y) -> X * -Y 448 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 449 Op.getOperand(0), 450 GetNegatedExpression(Op.getOperand(1), DAG)); 451 452 case ISD::FP_EXTEND: 453 case ISD::FP_ROUND: 454 case ISD::FSIN: 455 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 456 GetNegatedExpression(Op.getOperand(0), DAG)); 457 } 458} 459 460 461// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 462// that selects between the values 1 and 0, making it equivalent to a setcc. 463// Also, set the incoming LHS, RHS, and CC references to the appropriate 464// nodes based on the type of node we are checking. This simplifies life a 465// bit for the callers. 466static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 467 SDOperand &CC) { 468 if (N.getOpcode() == ISD::SETCC) { 469 LHS = N.getOperand(0); 470 RHS = N.getOperand(1); 471 CC = N.getOperand(2); 472 return true; 473 } 474 if (N.getOpcode() == ISD::SELECT_CC && 475 N.getOperand(2).getOpcode() == ISD::Constant && 476 N.getOperand(3).getOpcode() == ISD::Constant && 477 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 478 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 479 LHS = N.getOperand(0); 480 RHS = N.getOperand(1); 481 CC = N.getOperand(4); 482 return true; 483 } 484 return false; 485} 486 487// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 488// one use. If this is true, it allows the users to invert the operation for 489// free when it is profitable to do so. 490static bool isOneUseSetCC(SDOperand N) { 491 SDOperand N0, N1, N2; 492 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 493 return true; 494 return false; 495} 496 497SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 498 MVT::ValueType VT = N0.getValueType(); 499 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 500 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 501 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 502 if (isa<ConstantSDNode>(N1)) { 503 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 504 AddToWorkList(OpNode.Val); 505 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 506 } else if (N0.hasOneUse()) { 507 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 508 AddToWorkList(OpNode.Val); 509 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 510 } 511 } 512 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 513 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 514 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 515 if (isa<ConstantSDNode>(N0)) { 516 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 517 AddToWorkList(OpNode.Val); 518 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 519 } else if (N1.hasOneUse()) { 520 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 521 AddToWorkList(OpNode.Val); 522 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 523 } 524 } 525 return SDOperand(); 526} 527 528//===----------------------------------------------------------------------===// 529// Main DAG Combiner implementation 530//===----------------------------------------------------------------------===// 531 532void DAGCombiner::Run(bool RunningAfterLegalize) { 533 // set the instance variable, so that the various visit routines may use it. 534 AfterLegalize = RunningAfterLegalize; 535 536 // Add all the dag nodes to the worklist. 537 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 538 E = DAG.allnodes_end(); I != E; ++I) 539 WorkList.push_back(I); 540 541 // Create a dummy node (which is not added to allnodes), that adds a reference 542 // to the root node, preventing it from being deleted, and tracking any 543 // changes of the root. 544 HandleSDNode Dummy(DAG.getRoot()); 545 546 // The root of the dag may dangle to deleted nodes until the dag combiner is 547 // done. Set it to null to avoid confusion. 548 DAG.setRoot(SDOperand()); 549 550 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 551 TargetLowering::DAGCombinerInfo 552 DagCombineInfo(DAG, !RunningAfterLegalize, false, this); 553 554 // while the worklist isn't empty, inspect the node on the end of it and 555 // try and combine it. 556 while (!WorkList.empty()) { 557 SDNode *N = WorkList.back(); 558 WorkList.pop_back(); 559 560 // If N has no uses, it is dead. Make sure to revisit all N's operands once 561 // N is deleted from the DAG, since they too may now be dead or may have a 562 // reduced number of uses, allowing other xforms. 563 if (N->use_empty() && N != &Dummy) { 564 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 565 AddToWorkList(N->getOperand(i).Val); 566 567 DAG.DeleteNode(N); 568 continue; 569 } 570 571 SDOperand RV = visit(N); 572 573 // If nothing happened, try a target-specific DAG combine. 574 if (RV.Val == 0) { 575 assert(N->getOpcode() != ISD::DELETED_NODE && 576 "Node was deleted but visit returned NULL!"); 577 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 578 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 579 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 580 } 581 582 if (RV.Val) { 583 ++NodesCombined; 584 // If we get back the same node we passed in, rather than a new node or 585 // zero, we know that the node must have defined multiple values and 586 // CombineTo was used. Since CombineTo takes care of the worklist 587 // mechanics for us, we have no work to do in this case. 588 if (RV.Val != N) { 589 assert(N->getOpcode() != ISD::DELETED_NODE && 590 RV.Val->getOpcode() != ISD::DELETED_NODE && 591 "Node was deleted but visit returned new node!"); 592 593 DOUT << "\nReplacing.3 "; DEBUG(N->dump()); 594 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 595 DOUT << '\n'; 596 std::vector<SDNode*> NowDead; 597 if (N->getNumValues() == RV.Val->getNumValues()) 598 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 599 else { 600 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 601 SDOperand OpV = RV; 602 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 603 } 604 605 // Push the new node and any users onto the worklist 606 AddToWorkList(RV.Val); 607 AddUsersToWorkList(RV.Val); 608 609 // Nodes can be reintroduced into the worklist. Make sure we do not 610 // process a node that has been replaced. 611 removeFromWorkList(N); 612 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 613 removeFromWorkList(NowDead[i]); 614 615 // Finally, since the node is now dead, remove it from the graph. 616 DAG.DeleteNode(N); 617 } 618 } 619 } 620 621 // If the root changed (e.g. it was a dead load, update the root). 622 DAG.setRoot(Dummy.getValue()); 623} 624 625SDOperand DAGCombiner::visit(SDNode *N) { 626 switch(N->getOpcode()) { 627 default: break; 628 case ISD::TokenFactor: return visitTokenFactor(N); 629 case ISD::ADD: return visitADD(N); 630 case ISD::SUB: return visitSUB(N); 631 case ISD::ADDC: return visitADDC(N); 632 case ISD::ADDE: return visitADDE(N); 633 case ISD::MUL: return visitMUL(N); 634 case ISD::SDIV: return visitSDIV(N); 635 case ISD::UDIV: return visitUDIV(N); 636 case ISD::SREM: return visitSREM(N); 637 case ISD::UREM: return visitUREM(N); 638 case ISD::MULHU: return visitMULHU(N); 639 case ISD::MULHS: return visitMULHS(N); 640 case ISD::AND: return visitAND(N); 641 case ISD::OR: return visitOR(N); 642 case ISD::XOR: return visitXOR(N); 643 case ISD::SHL: return visitSHL(N); 644 case ISD::SRA: return visitSRA(N); 645 case ISD::SRL: return visitSRL(N); 646 case ISD::CTLZ: return visitCTLZ(N); 647 case ISD::CTTZ: return visitCTTZ(N); 648 case ISD::CTPOP: return visitCTPOP(N); 649 case ISD::SELECT: return visitSELECT(N); 650 case ISD::SELECT_CC: return visitSELECT_CC(N); 651 case ISD::SETCC: return visitSETCC(N); 652 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 653 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 654 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 655 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 656 case ISD::TRUNCATE: return visitTRUNCATE(N); 657 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 658 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 659 case ISD::FADD: return visitFADD(N); 660 case ISD::FSUB: return visitFSUB(N); 661 case ISD::FMUL: return visitFMUL(N); 662 case ISD::FDIV: return visitFDIV(N); 663 case ISD::FREM: return visitFREM(N); 664 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 665 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 666 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 667 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 668 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 669 case ISD::FP_ROUND: return visitFP_ROUND(N); 670 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 671 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 672 case ISD::FNEG: return visitFNEG(N); 673 case ISD::FABS: return visitFABS(N); 674 case ISD::BRCOND: return visitBRCOND(N); 675 case ISD::BR_CC: return visitBR_CC(N); 676 case ISD::LOAD: return visitLOAD(N); 677 case ISD::STORE: return visitSTORE(N); 678 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 679 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 680 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 681 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 682 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 683 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 684 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 685 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 686 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 687 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 688 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 689 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 690 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 691 } 692 return SDOperand(); 693} 694 695/// getInputChainForNode - Given a node, return its input chain if it has one, 696/// otherwise return a null sd operand. 697static SDOperand getInputChainForNode(SDNode *N) { 698 if (unsigned NumOps = N->getNumOperands()) { 699 if (N->getOperand(0).getValueType() == MVT::Other) 700 return N->getOperand(0); 701 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 702 return N->getOperand(NumOps-1); 703 for (unsigned i = 1; i < NumOps-1; ++i) 704 if (N->getOperand(i).getValueType() == MVT::Other) 705 return N->getOperand(i); 706 } 707 return SDOperand(0, 0); 708} 709 710SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 711 // If N has two operands, where one has an input chain equal to the other, 712 // the 'other' chain is redundant. 713 if (N->getNumOperands() == 2) { 714 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 715 return N->getOperand(0); 716 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 717 return N->getOperand(1); 718 } 719 720 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 721 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 722 SmallPtrSet<SDNode*, 16> SeenOps; 723 bool Changed = false; // If we should replace this token factor. 724 725 // Start out with this token factor. 726 TFs.push_back(N); 727 728 // Iterate through token factors. The TFs grows when new token factors are 729 // encountered. 730 for (unsigned i = 0; i < TFs.size(); ++i) { 731 SDNode *TF = TFs[i]; 732 733 // Check each of the operands. 734 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 735 SDOperand Op = TF->getOperand(i); 736 737 switch (Op.getOpcode()) { 738 case ISD::EntryToken: 739 // Entry tokens don't need to be added to the list. They are 740 // rededundant. 741 Changed = true; 742 break; 743 744 case ISD::TokenFactor: 745 if ((CombinerAA || Op.hasOneUse()) && 746 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 747 // Queue up for processing. 748 TFs.push_back(Op.Val); 749 // Clean up in case the token factor is removed. 750 AddToWorkList(Op.Val); 751 Changed = true; 752 break; 753 } 754 // Fall thru 755 756 default: 757 // Only add if it isn't already in the list. 758 if (SeenOps.insert(Op.Val)) 759 Ops.push_back(Op); 760 else 761 Changed = true; 762 break; 763 } 764 } 765 } 766 767 SDOperand Result; 768 769 // If we've change things around then replace token factor. 770 if (Changed) { 771 if (Ops.size() == 0) { 772 // The entry token is the only possible outcome. 773 Result = DAG.getEntryNode(); 774 } else { 775 // New and improved token factor. 776 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 777 } 778 779 // Don't add users to work list. 780 return CombineTo(N, Result, false); 781 } 782 783 return Result; 784} 785 786static 787SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 788 MVT::ValueType VT = N0.getValueType(); 789 SDOperand N00 = N0.getOperand(0); 790 SDOperand N01 = N0.getOperand(1); 791 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 792 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 793 isa<ConstantSDNode>(N00.getOperand(1))) { 794 N0 = DAG.getNode(ISD::ADD, VT, 795 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 796 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 797 return DAG.getNode(ISD::ADD, VT, N0, N1); 798 } 799 return SDOperand(); 800} 801 802SDOperand DAGCombiner::visitADD(SDNode *N) { 803 SDOperand N0 = N->getOperand(0); 804 SDOperand N1 = N->getOperand(1); 805 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 806 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 807 MVT::ValueType VT = N0.getValueType(); 808 809 // fold (add c1, c2) -> c1+c2 810 if (N0C && N1C) 811 return DAG.getNode(ISD::ADD, VT, N0, N1); 812 // canonicalize constant to RHS 813 if (N0C && !N1C) 814 return DAG.getNode(ISD::ADD, VT, N1, N0); 815 // fold (add x, 0) -> x 816 if (N1C && N1C->isNullValue()) 817 return N0; 818 // fold ((c1-A)+c2) -> (c1+c2)-A 819 if (N1C && N0.getOpcode() == ISD::SUB) 820 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 821 return DAG.getNode(ISD::SUB, VT, 822 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 823 N0.getOperand(1)); 824 // reassociate add 825 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 826 if (RADD.Val != 0) 827 return RADD; 828 // fold ((0-A) + B) -> B-A 829 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 830 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 831 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 832 // fold (A + (0-B)) -> A-B 833 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 834 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 835 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 836 // fold (A+(B-A)) -> B 837 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 838 return N1.getOperand(0); 839 840 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 841 return SDOperand(N, 0); 842 843 // fold (a+b) -> (a|b) iff a and b share no bits. 844 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 845 uint64_t LHSZero, LHSOne; 846 uint64_t RHSZero, RHSOne; 847 uint64_t Mask = MVT::getIntVTBitMask(VT); 848 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 849 if (LHSZero) { 850 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 851 852 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 853 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 854 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 855 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 856 return DAG.getNode(ISD::OR, VT, N0, N1); 857 } 858 } 859 860 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 861 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 862 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 863 if (Result.Val) return Result; 864 } 865 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 866 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 867 if (Result.Val) return Result; 868 } 869 870 return SDOperand(); 871} 872 873SDOperand DAGCombiner::visitADDC(SDNode *N) { 874 SDOperand N0 = N->getOperand(0); 875 SDOperand N1 = N->getOperand(1); 876 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 877 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 878 MVT::ValueType VT = N0.getValueType(); 879 880 // If the flag result is dead, turn this into an ADD. 881 if (N->hasNUsesOfValue(0, 1)) 882 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 883 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 884 885 // canonicalize constant to RHS. 886 if (N0C && !N1C) { 887 SDOperand Ops[] = { N1, N0 }; 888 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 889 } 890 891 // fold (addc x, 0) -> x + no carry out 892 if (N1C && N1C->isNullValue()) 893 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 894 895 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 896 uint64_t LHSZero, LHSOne; 897 uint64_t RHSZero, RHSOne; 898 uint64_t Mask = MVT::getIntVTBitMask(VT); 899 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 900 if (LHSZero) { 901 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 902 903 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 904 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 905 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 906 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 907 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 908 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 909 } 910 911 return SDOperand(); 912} 913 914SDOperand DAGCombiner::visitADDE(SDNode *N) { 915 SDOperand N0 = N->getOperand(0); 916 SDOperand N1 = N->getOperand(1); 917 SDOperand CarryIn = N->getOperand(2); 918 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 919 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 920 //MVT::ValueType VT = N0.getValueType(); 921 922 // canonicalize constant to RHS 923 if (N0C && !N1C) { 924 SDOperand Ops[] = { N1, N0, CarryIn }; 925 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 926 } 927 928 // fold (adde x, y, false) -> (addc x, y) 929 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 930 SDOperand Ops[] = { N1, N0 }; 931 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 932 } 933 934 return SDOperand(); 935} 936 937 938 939SDOperand DAGCombiner::visitSUB(SDNode *N) { 940 SDOperand N0 = N->getOperand(0); 941 SDOperand N1 = N->getOperand(1); 942 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 943 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 944 MVT::ValueType VT = N0.getValueType(); 945 946 // fold (sub x, x) -> 0 947 if (N0 == N1) 948 return DAG.getConstant(0, N->getValueType(0)); 949 // fold (sub c1, c2) -> c1-c2 950 if (N0C && N1C) 951 return DAG.getNode(ISD::SUB, VT, N0, N1); 952 // fold (sub x, c) -> (add x, -c) 953 if (N1C) 954 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 955 // fold (A+B)-A -> B 956 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 957 return N0.getOperand(1); 958 // fold (A+B)-B -> A 959 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 960 return N0.getOperand(0); 961 return SDOperand(); 962} 963 964SDOperand DAGCombiner::visitMUL(SDNode *N) { 965 SDOperand N0 = N->getOperand(0); 966 SDOperand N1 = N->getOperand(1); 967 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 968 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 969 MVT::ValueType VT = N0.getValueType(); 970 971 // fold (mul c1, c2) -> c1*c2 972 if (N0C && N1C) 973 return DAG.getNode(ISD::MUL, VT, N0, N1); 974 // canonicalize constant to RHS 975 if (N0C && !N1C) 976 return DAG.getNode(ISD::MUL, VT, N1, N0); 977 // fold (mul x, 0) -> 0 978 if (N1C && N1C->isNullValue()) 979 return N1; 980 // fold (mul x, -1) -> 0-x 981 if (N1C && N1C->isAllOnesValue()) 982 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 983 // fold (mul x, (1 << c)) -> x << c 984 if (N1C && isPowerOf2_64(N1C->getValue())) 985 return DAG.getNode(ISD::SHL, VT, N0, 986 DAG.getConstant(Log2_64(N1C->getValue()), 987 TLI.getShiftAmountTy())); 988 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 989 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 990 // FIXME: If the input is something that is easily negated (e.g. a 991 // single-use add), we should put the negate there. 992 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 993 DAG.getNode(ISD::SHL, VT, N0, 994 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 995 TLI.getShiftAmountTy()))); 996 } 997 998 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 999 if (N1C && N0.getOpcode() == ISD::SHL && 1000 isa<ConstantSDNode>(N0.getOperand(1))) { 1001 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1002 AddToWorkList(C3.Val); 1003 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1004 } 1005 1006 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1007 // use. 1008 { 1009 SDOperand Sh(0,0), Y(0,0); 1010 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1011 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1012 N0.Val->hasOneUse()) { 1013 Sh = N0; Y = N1; 1014 } else if (N1.getOpcode() == ISD::SHL && 1015 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1016 Sh = N1; Y = N0; 1017 } 1018 if (Sh.Val) { 1019 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1020 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1021 } 1022 } 1023 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1024 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1025 isa<ConstantSDNode>(N0.getOperand(1))) { 1026 return DAG.getNode(ISD::ADD, VT, 1027 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1028 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1029 } 1030 1031 // reassociate mul 1032 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1033 if (RMUL.Val != 0) 1034 return RMUL; 1035 return SDOperand(); 1036} 1037 1038SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1039 SDOperand N0 = N->getOperand(0); 1040 SDOperand N1 = N->getOperand(1); 1041 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1042 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1043 MVT::ValueType VT = N->getValueType(0); 1044 1045 // fold (sdiv c1, c2) -> c1/c2 1046 if (N0C && N1C && !N1C->isNullValue()) 1047 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1048 // fold (sdiv X, 1) -> X 1049 if (N1C && N1C->getSignExtended() == 1LL) 1050 return N0; 1051 // fold (sdiv X, -1) -> 0-X 1052 if (N1C && N1C->isAllOnesValue()) 1053 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1054 // If we know the sign bits of both operands are zero, strength reduce to a 1055 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1056 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1057 if (TLI.MaskedValueIsZero(N1, SignBit) && 1058 TLI.MaskedValueIsZero(N0, SignBit)) 1059 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1060 // fold (sdiv X, pow2) -> simple ops after legalize 1061 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1062 (isPowerOf2_64(N1C->getSignExtended()) || 1063 isPowerOf2_64(-N1C->getSignExtended()))) { 1064 // If dividing by powers of two is cheap, then don't perform the following 1065 // fold. 1066 if (TLI.isPow2DivCheap()) 1067 return SDOperand(); 1068 int64_t pow2 = N1C->getSignExtended(); 1069 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1070 unsigned lg2 = Log2_64(abs2); 1071 // Splat the sign bit into the register 1072 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1073 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1074 TLI.getShiftAmountTy())); 1075 AddToWorkList(SGN.Val); 1076 // Add (N0 < 0) ? abs2 - 1 : 0; 1077 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1078 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1079 TLI.getShiftAmountTy())); 1080 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1081 AddToWorkList(SRL.Val); 1082 AddToWorkList(ADD.Val); // Divide by pow2 1083 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1084 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1085 // If we're dividing by a positive value, we're done. Otherwise, we must 1086 // negate the result. 1087 if (pow2 > 0) 1088 return SRA; 1089 AddToWorkList(SRA.Val); 1090 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1091 } 1092 // if integer divide is expensive and we satisfy the requirements, emit an 1093 // alternate sequence. 1094 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1095 !TLI.isIntDivCheap()) { 1096 SDOperand Op = BuildSDIV(N); 1097 if (Op.Val) return Op; 1098 } 1099 return SDOperand(); 1100} 1101 1102SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1103 SDOperand N0 = N->getOperand(0); 1104 SDOperand N1 = N->getOperand(1); 1105 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1106 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1107 MVT::ValueType VT = N->getValueType(0); 1108 1109 // fold (udiv c1, c2) -> c1/c2 1110 if (N0C && N1C && !N1C->isNullValue()) 1111 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1112 // fold (udiv x, (1 << c)) -> x >>u c 1113 if (N1C && isPowerOf2_64(N1C->getValue())) 1114 return DAG.getNode(ISD::SRL, VT, N0, 1115 DAG.getConstant(Log2_64(N1C->getValue()), 1116 TLI.getShiftAmountTy())); 1117 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1118 if (N1.getOpcode() == ISD::SHL) { 1119 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1120 if (isPowerOf2_64(SHC->getValue())) { 1121 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1122 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1123 DAG.getConstant(Log2_64(SHC->getValue()), 1124 ADDVT)); 1125 AddToWorkList(Add.Val); 1126 return DAG.getNode(ISD::SRL, VT, N0, Add); 1127 } 1128 } 1129 } 1130 // fold (udiv x, c) -> alternate 1131 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1132 SDOperand Op = BuildUDIV(N); 1133 if (Op.Val) return Op; 1134 } 1135 return SDOperand(); 1136} 1137 1138SDOperand DAGCombiner::visitSREM(SDNode *N) { 1139 SDOperand N0 = N->getOperand(0); 1140 SDOperand N1 = N->getOperand(1); 1141 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1142 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1143 MVT::ValueType VT = N->getValueType(0); 1144 1145 // fold (srem c1, c2) -> c1%c2 1146 if (N0C && N1C && !N1C->isNullValue()) 1147 return DAG.getNode(ISD::SREM, VT, N0, N1); 1148 // If we know the sign bits of both operands are zero, strength reduce to a 1149 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1150 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1151 if (TLI.MaskedValueIsZero(N1, SignBit) && 1152 TLI.MaskedValueIsZero(N0, SignBit)) 1153 return DAG.getNode(ISD::UREM, VT, N0, N1); 1154 1155 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1156 // the remainder operation. 1157 if (N1C && !N1C->isNullValue()) { 1158 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1159 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1160 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1161 AddToWorkList(Div.Val); 1162 AddToWorkList(Mul.Val); 1163 return Sub; 1164 } 1165 1166 return SDOperand(); 1167} 1168 1169SDOperand DAGCombiner::visitUREM(SDNode *N) { 1170 SDOperand N0 = N->getOperand(0); 1171 SDOperand N1 = N->getOperand(1); 1172 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1173 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1174 MVT::ValueType VT = N->getValueType(0); 1175 1176 // fold (urem c1, c2) -> c1%c2 1177 if (N0C && N1C && !N1C->isNullValue()) 1178 return DAG.getNode(ISD::UREM, VT, N0, N1); 1179 // fold (urem x, pow2) -> (and x, pow2-1) 1180 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1181 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1182 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1183 if (N1.getOpcode() == ISD::SHL) { 1184 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1185 if (isPowerOf2_64(SHC->getValue())) { 1186 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1187 AddToWorkList(Add.Val); 1188 return DAG.getNode(ISD::AND, VT, N0, Add); 1189 } 1190 } 1191 } 1192 1193 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1194 // the remainder operation. 1195 if (N1C && !N1C->isNullValue()) { 1196 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1197 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1198 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1199 AddToWorkList(Div.Val); 1200 AddToWorkList(Mul.Val); 1201 return Sub; 1202 } 1203 1204 return SDOperand(); 1205} 1206 1207SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1208 SDOperand N0 = N->getOperand(0); 1209 SDOperand N1 = N->getOperand(1); 1210 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1211 1212 // fold (mulhs x, 0) -> 0 1213 if (N1C && N1C->isNullValue()) 1214 return N1; 1215 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1216 if (N1C && N1C->getValue() == 1) 1217 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1218 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1219 TLI.getShiftAmountTy())); 1220 return SDOperand(); 1221} 1222 1223SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1224 SDOperand N0 = N->getOperand(0); 1225 SDOperand N1 = N->getOperand(1); 1226 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1227 1228 // fold (mulhu x, 0) -> 0 1229 if (N1C && N1C->isNullValue()) 1230 return N1; 1231 // fold (mulhu x, 1) -> 0 1232 if (N1C && N1C->getValue() == 1) 1233 return DAG.getConstant(0, N0.getValueType()); 1234 return SDOperand(); 1235} 1236 1237/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1238/// two operands of the same opcode, try to simplify it. 1239SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1240 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1241 MVT::ValueType VT = N0.getValueType(); 1242 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1243 1244 // For each of OP in AND/OR/XOR: 1245 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1246 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1247 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1248 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1249 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1250 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1251 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1252 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1253 N0.getOperand(0).getValueType(), 1254 N0.getOperand(0), N1.getOperand(0)); 1255 AddToWorkList(ORNode.Val); 1256 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1257 } 1258 1259 // For each of OP in SHL/SRL/SRA/AND... 1260 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1261 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1262 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1263 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1264 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1265 N0.getOperand(1) == N1.getOperand(1)) { 1266 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1267 N0.getOperand(0).getValueType(), 1268 N0.getOperand(0), N1.getOperand(0)); 1269 AddToWorkList(ORNode.Val); 1270 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1271 } 1272 1273 return SDOperand(); 1274} 1275 1276SDOperand DAGCombiner::visitAND(SDNode *N) { 1277 SDOperand N0 = N->getOperand(0); 1278 SDOperand N1 = N->getOperand(1); 1279 SDOperand LL, LR, RL, RR, CC0, CC1; 1280 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1281 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1282 MVT::ValueType VT = N1.getValueType(); 1283 1284 // fold (and c1, c2) -> c1&c2 1285 if (N0C && N1C) 1286 return DAG.getNode(ISD::AND, VT, N0, N1); 1287 // canonicalize constant to RHS 1288 if (N0C && !N1C) 1289 return DAG.getNode(ISD::AND, VT, N1, N0); 1290 // fold (and x, -1) -> x 1291 if (N1C && N1C->isAllOnesValue()) 1292 return N0; 1293 // if (and x, c) is known to be zero, return 0 1294 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1295 return DAG.getConstant(0, VT); 1296 // reassociate and 1297 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1298 if (RAND.Val != 0) 1299 return RAND; 1300 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1301 if (N1C && N0.getOpcode() == ISD::OR) 1302 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1303 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1304 return N1; 1305 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1306 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1307 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1308 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1309 ~N1C->getValue() & InMask)) { 1310 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1311 N0.getOperand(0)); 1312 1313 // Replace uses of the AND with uses of the Zero extend node. 1314 CombineTo(N, Zext); 1315 1316 // We actually want to replace all uses of the any_extend with the 1317 // zero_extend, to avoid duplicating things. This will later cause this 1318 // AND to be folded. 1319 CombineTo(N0.Val, Zext); 1320 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1321 } 1322 } 1323 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1324 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1325 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1326 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1327 1328 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1329 MVT::isInteger(LL.getValueType())) { 1330 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1331 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1332 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1333 AddToWorkList(ORNode.Val); 1334 return DAG.getSetCC(VT, ORNode, LR, Op1); 1335 } 1336 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1337 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1338 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1339 AddToWorkList(ANDNode.Val); 1340 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1341 } 1342 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1343 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1344 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1345 AddToWorkList(ORNode.Val); 1346 return DAG.getSetCC(VT, ORNode, LR, Op1); 1347 } 1348 } 1349 // canonicalize equivalent to ll == rl 1350 if (LL == RR && LR == RL) { 1351 Op1 = ISD::getSetCCSwappedOperands(Op1); 1352 std::swap(RL, RR); 1353 } 1354 if (LL == RL && LR == RR) { 1355 bool isInteger = MVT::isInteger(LL.getValueType()); 1356 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1357 if (Result != ISD::SETCC_INVALID) 1358 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1359 } 1360 } 1361 1362 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1363 if (N0.getOpcode() == N1.getOpcode()) { 1364 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1365 if (Tmp.Val) return Tmp; 1366 } 1367 1368 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1369 // fold (and (sra)) -> (and (srl)) when possible. 1370 if (!MVT::isVector(VT) && 1371 SimplifyDemandedBits(SDOperand(N, 0))) 1372 return SDOperand(N, 0); 1373 // fold (zext_inreg (extload x)) -> (zextload x) 1374 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1375 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1376 MVT::ValueType EVT = LN0->getLoadedVT(); 1377 // If we zero all the possible extended bits, then we can turn this into 1378 // a zextload if we are running before legalize or the operation is legal. 1379 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1380 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1381 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1382 LN0->getBasePtr(), LN0->getSrcValue(), 1383 LN0->getSrcValueOffset(), EVT, 1384 LN0->isVolatile(), 1385 LN0->getAlignment()); 1386 AddToWorkList(N); 1387 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1388 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1389 } 1390 } 1391 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1392 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1393 N0.hasOneUse()) { 1394 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1395 MVT::ValueType EVT = LN0->getLoadedVT(); 1396 // If we zero all the possible extended bits, then we can turn this into 1397 // a zextload if we are running before legalize or the operation is legal. 1398 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1399 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1400 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1401 LN0->getBasePtr(), LN0->getSrcValue(), 1402 LN0->getSrcValueOffset(), EVT, 1403 LN0->isVolatile(), 1404 LN0->getAlignment()); 1405 AddToWorkList(N); 1406 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1407 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1408 } 1409 } 1410 1411 // fold (and (load x), 255) -> (zextload x, i8) 1412 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1413 if (N1C && N0.getOpcode() == ISD::LOAD) { 1414 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1415 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1416 LN0->getAddressingMode() == ISD::UNINDEXED && 1417 N0.hasOneUse()) { 1418 MVT::ValueType EVT, LoadedVT; 1419 if (N1C->getValue() == 255) 1420 EVT = MVT::i8; 1421 else if (N1C->getValue() == 65535) 1422 EVT = MVT::i16; 1423 else if (N1C->getValue() == ~0U) 1424 EVT = MVT::i32; 1425 else 1426 EVT = MVT::Other; 1427 1428 LoadedVT = LN0->getLoadedVT(); 1429 if (EVT != MVT::Other && LoadedVT > EVT && 1430 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1431 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1432 // For big endian targets, we need to add an offset to the pointer to 1433 // load the correct bytes. For little endian systems, we merely need to 1434 // read fewer bytes from the same pointer. 1435 unsigned PtrOff = 1436 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1437 SDOperand NewPtr = LN0->getBasePtr(); 1438 if (!TLI.isLittleEndian()) 1439 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1440 DAG.getConstant(PtrOff, PtrType)); 1441 AddToWorkList(NewPtr.Val); 1442 SDOperand Load = 1443 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1444 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1445 LN0->isVolatile(), LN0->getAlignment()); 1446 AddToWorkList(N); 1447 CombineTo(N0.Val, Load, Load.getValue(1)); 1448 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1449 } 1450 } 1451 } 1452 1453 return SDOperand(); 1454} 1455 1456SDOperand DAGCombiner::visitOR(SDNode *N) { 1457 SDOperand N0 = N->getOperand(0); 1458 SDOperand N1 = N->getOperand(1); 1459 SDOperand LL, LR, RL, RR, CC0, CC1; 1460 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1461 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1462 MVT::ValueType VT = N1.getValueType(); 1463 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1464 1465 // fold (or c1, c2) -> c1|c2 1466 if (N0C && N1C) 1467 return DAG.getNode(ISD::OR, VT, N0, N1); 1468 // canonicalize constant to RHS 1469 if (N0C && !N1C) 1470 return DAG.getNode(ISD::OR, VT, N1, N0); 1471 // fold (or x, 0) -> x 1472 if (N1C && N1C->isNullValue()) 1473 return N0; 1474 // fold (or x, -1) -> -1 1475 if (N1C && N1C->isAllOnesValue()) 1476 return N1; 1477 // fold (or x, c) -> c iff (x & ~c) == 0 1478 if (N1C && 1479 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1480 return N1; 1481 // reassociate or 1482 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1483 if (ROR.Val != 0) 1484 return ROR; 1485 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1486 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1487 isa<ConstantSDNode>(N0.getOperand(1))) { 1488 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1489 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1490 N1), 1491 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1492 } 1493 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1494 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1495 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1496 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1497 1498 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1499 MVT::isInteger(LL.getValueType())) { 1500 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1501 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1502 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1503 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1504 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1505 AddToWorkList(ORNode.Val); 1506 return DAG.getSetCC(VT, ORNode, LR, Op1); 1507 } 1508 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1509 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1510 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1511 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1512 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1513 AddToWorkList(ANDNode.Val); 1514 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1515 } 1516 } 1517 // canonicalize equivalent to ll == rl 1518 if (LL == RR && LR == RL) { 1519 Op1 = ISD::getSetCCSwappedOperands(Op1); 1520 std::swap(RL, RR); 1521 } 1522 if (LL == RL && LR == RR) { 1523 bool isInteger = MVT::isInteger(LL.getValueType()); 1524 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1525 if (Result != ISD::SETCC_INVALID) 1526 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1527 } 1528 } 1529 1530 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1531 if (N0.getOpcode() == N1.getOpcode()) { 1532 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1533 if (Tmp.Val) return Tmp; 1534 } 1535 1536 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1537 if (N0.getOpcode() == ISD::AND && 1538 N1.getOpcode() == ISD::AND && 1539 N0.getOperand(1).getOpcode() == ISD::Constant && 1540 N1.getOperand(1).getOpcode() == ISD::Constant && 1541 // Don't increase # computations. 1542 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1543 // We can only do this xform if we know that bits from X that are set in C2 1544 // but not in C1 are already zero. Likewise for Y. 1545 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1546 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1547 1548 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1549 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1550 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1551 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1552 } 1553 } 1554 1555 1556 // See if this is some rotate idiom. 1557 if (SDNode *Rot = MatchRotate(N0, N1)) 1558 return SDOperand(Rot, 0); 1559 1560 return SDOperand(); 1561} 1562 1563 1564/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1565static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1566 if (Op.getOpcode() == ISD::AND) { 1567 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1568 Mask = Op.getOperand(1); 1569 Op = Op.getOperand(0); 1570 } else { 1571 return false; 1572 } 1573 } 1574 1575 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1576 Shift = Op; 1577 return true; 1578 } 1579 return false; 1580} 1581 1582 1583// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1584// idioms for rotate, and if the target supports rotation instructions, generate 1585// a rot[lr]. 1586SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1587 // Must be a legal type. Expanded an promoted things won't work with rotates. 1588 MVT::ValueType VT = LHS.getValueType(); 1589 if (!TLI.isTypeLegal(VT)) return 0; 1590 1591 // The target must have at least one rotate flavor. 1592 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1593 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1594 if (!HasROTL && !HasROTR) return 0; 1595 1596 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1597 SDOperand LHSShift; // The shift. 1598 SDOperand LHSMask; // AND value if any. 1599 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1600 return 0; // Not part of a rotate. 1601 1602 SDOperand RHSShift; // The shift. 1603 SDOperand RHSMask; // AND value if any. 1604 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1605 return 0; // Not part of a rotate. 1606 1607 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1608 return 0; // Not shifting the same value. 1609 1610 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1611 return 0; // Shifts must disagree. 1612 1613 // Canonicalize shl to left side in a shl/srl pair. 1614 if (RHSShift.getOpcode() == ISD::SHL) { 1615 std::swap(LHS, RHS); 1616 std::swap(LHSShift, RHSShift); 1617 std::swap(LHSMask , RHSMask ); 1618 } 1619 1620 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1621 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1622 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1623 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1624 1625 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1626 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1627 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1628 RHSShiftAmt.getOpcode() == ISD::Constant) { 1629 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1630 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1631 if ((LShVal + RShVal) != OpSizeInBits) 1632 return 0; 1633 1634 SDOperand Rot; 1635 if (HasROTL) 1636 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1637 else 1638 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1639 1640 // If there is an AND of either shifted operand, apply it to the result. 1641 if (LHSMask.Val || RHSMask.Val) { 1642 uint64_t Mask = MVT::getIntVTBitMask(VT); 1643 1644 if (LHSMask.Val) { 1645 uint64_t RHSBits = (1ULL << LShVal)-1; 1646 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1647 } 1648 if (RHSMask.Val) { 1649 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1650 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1651 } 1652 1653 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1654 } 1655 1656 return Rot.Val; 1657 } 1658 1659 // If there is a mask here, and we have a variable shift, we can't be sure 1660 // that we're masking out the right stuff. 1661 if (LHSMask.Val || RHSMask.Val) 1662 return 0; 1663 1664 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1665 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1666 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1667 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1668 if (ConstantSDNode *SUBC = 1669 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1670 if (SUBC->getValue() == OpSizeInBits) 1671 if (HasROTL) 1672 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1673 else 1674 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1675 } 1676 } 1677 1678 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1679 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1680 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1681 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1682 if (ConstantSDNode *SUBC = 1683 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1684 if (SUBC->getValue() == OpSizeInBits) 1685 if (HasROTL) 1686 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1687 else 1688 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1689 } 1690 } 1691 1692 // Look for sign/zext/any-extended cases: 1693 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1694 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1695 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1696 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1697 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1698 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1699 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1700 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1701 if (RExtOp0.getOpcode() == ISD::SUB && 1702 RExtOp0.getOperand(1) == LExtOp0) { 1703 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1704 // (rotr x, y) 1705 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1706 // (rotl x, (sub 32, y)) 1707 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1708 if (SUBC->getValue() == OpSizeInBits) { 1709 if (HasROTL) 1710 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1711 else 1712 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1713 } 1714 } 1715 } else if (LExtOp0.getOpcode() == ISD::SUB && 1716 RExtOp0 == LExtOp0.getOperand(1)) { 1717 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1718 // (rotl x, y) 1719 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1720 // (rotr x, (sub 32, y)) 1721 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 1722 if (SUBC->getValue() == OpSizeInBits) { 1723 if (HasROTL) 1724 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 1725 else 1726 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1727 } 1728 } 1729 } 1730 } 1731 1732 return 0; 1733} 1734 1735 1736SDOperand DAGCombiner::visitXOR(SDNode *N) { 1737 SDOperand N0 = N->getOperand(0); 1738 SDOperand N1 = N->getOperand(1); 1739 SDOperand LHS, RHS, CC; 1740 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1741 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1742 MVT::ValueType VT = N0.getValueType(); 1743 1744 // fold (xor c1, c2) -> c1^c2 1745 if (N0C && N1C) 1746 return DAG.getNode(ISD::XOR, VT, N0, N1); 1747 // canonicalize constant to RHS 1748 if (N0C && !N1C) 1749 return DAG.getNode(ISD::XOR, VT, N1, N0); 1750 // fold (xor x, 0) -> x 1751 if (N1C && N1C->isNullValue()) 1752 return N0; 1753 // reassociate xor 1754 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1755 if (RXOR.Val != 0) 1756 return RXOR; 1757 // fold !(x cc y) -> (x !cc y) 1758 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1759 bool isInt = MVT::isInteger(LHS.getValueType()); 1760 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1761 isInt); 1762 if (N0.getOpcode() == ISD::SETCC) 1763 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1764 if (N0.getOpcode() == ISD::SELECT_CC) 1765 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1766 assert(0 && "Unhandled SetCC Equivalent!"); 1767 abort(); 1768 } 1769 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1770 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 1771 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1772 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1773 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1774 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1775 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1776 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1777 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1778 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1779 } 1780 } 1781 // fold !(x or y) -> (!x and !y) iff x or y are constants 1782 if (N1C && N1C->isAllOnesValue() && 1783 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1784 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1785 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1786 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1787 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1788 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1789 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1790 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1791 } 1792 } 1793 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1794 if (N1C && N0.getOpcode() == ISD::XOR) { 1795 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1796 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1797 if (N00C) 1798 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1799 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1800 if (N01C) 1801 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1802 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1803 } 1804 // fold (xor x, x) -> 0 1805 if (N0 == N1) { 1806 if (!MVT::isVector(VT)) { 1807 return DAG.getConstant(0, VT); 1808 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1809 // Produce a vector of zeros. 1810 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1811 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1812 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1813 } 1814 } 1815 1816 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1817 if (N0.getOpcode() == N1.getOpcode()) { 1818 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1819 if (Tmp.Val) return Tmp; 1820 } 1821 1822 // Simplify the expression using non-local knowledge. 1823 if (!MVT::isVector(VT) && 1824 SimplifyDemandedBits(SDOperand(N, 0))) 1825 return SDOperand(N, 0); 1826 1827 return SDOperand(); 1828} 1829 1830SDOperand DAGCombiner::visitSHL(SDNode *N) { 1831 SDOperand N0 = N->getOperand(0); 1832 SDOperand N1 = N->getOperand(1); 1833 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1834 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1835 MVT::ValueType VT = N0.getValueType(); 1836 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1837 1838 // fold (shl c1, c2) -> c1<<c2 1839 if (N0C && N1C) 1840 return DAG.getNode(ISD::SHL, VT, N0, N1); 1841 // fold (shl 0, x) -> 0 1842 if (N0C && N0C->isNullValue()) 1843 return N0; 1844 // fold (shl x, c >= size(x)) -> undef 1845 if (N1C && N1C->getValue() >= OpSizeInBits) 1846 return DAG.getNode(ISD::UNDEF, VT); 1847 // fold (shl x, 0) -> x 1848 if (N1C && N1C->isNullValue()) 1849 return N0; 1850 // if (shl x, c) is known to be zero, return 0 1851 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1852 return DAG.getConstant(0, VT); 1853 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1854 return SDOperand(N, 0); 1855 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1856 if (N1C && N0.getOpcode() == ISD::SHL && 1857 N0.getOperand(1).getOpcode() == ISD::Constant) { 1858 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1859 uint64_t c2 = N1C->getValue(); 1860 if (c1 + c2 > OpSizeInBits) 1861 return DAG.getConstant(0, VT); 1862 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1863 DAG.getConstant(c1 + c2, N1.getValueType())); 1864 } 1865 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1866 // (srl (and x, -1 << c1), c1-c2) 1867 if (N1C && N0.getOpcode() == ISD::SRL && 1868 N0.getOperand(1).getOpcode() == ISD::Constant) { 1869 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1870 uint64_t c2 = N1C->getValue(); 1871 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1872 DAG.getConstant(~0ULL << c1, VT)); 1873 if (c2 > c1) 1874 return DAG.getNode(ISD::SHL, VT, Mask, 1875 DAG.getConstant(c2-c1, N1.getValueType())); 1876 else 1877 return DAG.getNode(ISD::SRL, VT, Mask, 1878 DAG.getConstant(c1-c2, N1.getValueType())); 1879 } 1880 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1881 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1882 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1883 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1884 return SDOperand(); 1885} 1886 1887SDOperand DAGCombiner::visitSRA(SDNode *N) { 1888 SDOperand N0 = N->getOperand(0); 1889 SDOperand N1 = N->getOperand(1); 1890 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1891 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1892 MVT::ValueType VT = N0.getValueType(); 1893 1894 // fold (sra c1, c2) -> c1>>c2 1895 if (N0C && N1C) 1896 return DAG.getNode(ISD::SRA, VT, N0, N1); 1897 // fold (sra 0, x) -> 0 1898 if (N0C && N0C->isNullValue()) 1899 return N0; 1900 // fold (sra -1, x) -> -1 1901 if (N0C && N0C->isAllOnesValue()) 1902 return N0; 1903 // fold (sra x, c >= size(x)) -> undef 1904 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1905 return DAG.getNode(ISD::UNDEF, VT); 1906 // fold (sra x, 0) -> x 1907 if (N1C && N1C->isNullValue()) 1908 return N0; 1909 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1910 // sext_inreg. 1911 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1912 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1913 MVT::ValueType EVT; 1914 switch (LowBits) { 1915 default: EVT = MVT::Other; break; 1916 case 1: EVT = MVT::i1; break; 1917 case 8: EVT = MVT::i8; break; 1918 case 16: EVT = MVT::i16; break; 1919 case 32: EVT = MVT::i32; break; 1920 } 1921 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1922 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1923 DAG.getValueType(EVT)); 1924 } 1925 1926 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1927 if (N1C && N0.getOpcode() == ISD::SRA) { 1928 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1929 unsigned Sum = N1C->getValue() + C1->getValue(); 1930 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1931 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1932 DAG.getConstant(Sum, N1C->getValueType(0))); 1933 } 1934 } 1935 1936 // Simplify, based on bits shifted out of the LHS. 1937 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1938 return SDOperand(N, 0); 1939 1940 1941 // If the sign bit is known to be zero, switch this to a SRL. 1942 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1943 return DAG.getNode(ISD::SRL, VT, N0, N1); 1944 return SDOperand(); 1945} 1946 1947SDOperand DAGCombiner::visitSRL(SDNode *N) { 1948 SDOperand N0 = N->getOperand(0); 1949 SDOperand N1 = N->getOperand(1); 1950 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1951 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1952 MVT::ValueType VT = N0.getValueType(); 1953 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1954 1955 // fold (srl c1, c2) -> c1 >>u c2 1956 if (N0C && N1C) 1957 return DAG.getNode(ISD::SRL, VT, N0, N1); 1958 // fold (srl 0, x) -> 0 1959 if (N0C && N0C->isNullValue()) 1960 return N0; 1961 // fold (srl x, c >= size(x)) -> undef 1962 if (N1C && N1C->getValue() >= OpSizeInBits) 1963 return DAG.getNode(ISD::UNDEF, VT); 1964 // fold (srl x, 0) -> x 1965 if (N1C && N1C->isNullValue()) 1966 return N0; 1967 // if (srl x, c) is known to be zero, return 0 1968 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1969 return DAG.getConstant(0, VT); 1970 1971 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1972 if (N1C && N0.getOpcode() == ISD::SRL && 1973 N0.getOperand(1).getOpcode() == ISD::Constant) { 1974 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1975 uint64_t c2 = N1C->getValue(); 1976 if (c1 + c2 > OpSizeInBits) 1977 return DAG.getConstant(0, VT); 1978 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1979 DAG.getConstant(c1 + c2, N1.getValueType())); 1980 } 1981 1982 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1983 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1984 // Shifting in all undef bits? 1985 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1986 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1987 return DAG.getNode(ISD::UNDEF, VT); 1988 1989 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1990 AddToWorkList(SmallShift.Val); 1991 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1992 } 1993 1994 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 1995 // bit, which is unmodified by sra. 1996 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 1997 if (N0.getOpcode() == ISD::SRA) 1998 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 1999 } 2000 2001 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2002 if (N1C && N0.getOpcode() == ISD::CTLZ && 2003 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2004 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2005 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2006 2007 // If any of the input bits are KnownOne, then the input couldn't be all 2008 // zeros, thus the result of the srl will always be zero. 2009 if (KnownOne) return DAG.getConstant(0, VT); 2010 2011 // If all of the bits input the to ctlz node are known to be zero, then 2012 // the result of the ctlz is "32" and the result of the shift is one. 2013 uint64_t UnknownBits = ~KnownZero & Mask; 2014 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2015 2016 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2017 if ((UnknownBits & (UnknownBits-1)) == 0) { 2018 // Okay, we know that only that the single bit specified by UnknownBits 2019 // could be set on input to the CTLZ node. If this bit is set, the SRL 2020 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2021 // to an SRL,XOR pair, which is likely to simplify more. 2022 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2023 SDOperand Op = N0.getOperand(0); 2024 if (ShAmt) { 2025 Op = DAG.getNode(ISD::SRL, VT, Op, 2026 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2027 AddToWorkList(Op.Val); 2028 } 2029 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2030 } 2031 } 2032 2033 // fold operands of srl based on knowledge that the low bits are not 2034 // demanded. 2035 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2036 return SDOperand(N, 0); 2037 2038 return SDOperand(); 2039} 2040 2041SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2042 SDOperand N0 = N->getOperand(0); 2043 MVT::ValueType VT = N->getValueType(0); 2044 2045 // fold (ctlz c1) -> c2 2046 if (isa<ConstantSDNode>(N0)) 2047 return DAG.getNode(ISD::CTLZ, VT, N0); 2048 return SDOperand(); 2049} 2050 2051SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2052 SDOperand N0 = N->getOperand(0); 2053 MVT::ValueType VT = N->getValueType(0); 2054 2055 // fold (cttz c1) -> c2 2056 if (isa<ConstantSDNode>(N0)) 2057 return DAG.getNode(ISD::CTTZ, VT, N0); 2058 return SDOperand(); 2059} 2060 2061SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2062 SDOperand N0 = N->getOperand(0); 2063 MVT::ValueType VT = N->getValueType(0); 2064 2065 // fold (ctpop c1) -> c2 2066 if (isa<ConstantSDNode>(N0)) 2067 return DAG.getNode(ISD::CTPOP, VT, N0); 2068 return SDOperand(); 2069} 2070 2071SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2072 SDOperand N0 = N->getOperand(0); 2073 SDOperand N1 = N->getOperand(1); 2074 SDOperand N2 = N->getOperand(2); 2075 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2076 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2077 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2078 MVT::ValueType VT = N->getValueType(0); 2079 2080 // fold select C, X, X -> X 2081 if (N1 == N2) 2082 return N1; 2083 // fold select true, X, Y -> X 2084 if (N0C && !N0C->isNullValue()) 2085 return N1; 2086 // fold select false, X, Y -> Y 2087 if (N0C && N0C->isNullValue()) 2088 return N2; 2089 // fold select C, 1, X -> C | X 2090 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2091 return DAG.getNode(ISD::OR, VT, N0, N2); 2092 // fold select C, 0, X -> ~C & X 2093 // FIXME: this should check for C type == X type, not i1? 2094 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 2095 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2096 AddToWorkList(XORNode.Val); 2097 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2098 } 2099 // fold select C, X, 1 -> ~C | X 2100 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 2101 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2102 AddToWorkList(XORNode.Val); 2103 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2104 } 2105 // fold select C, X, 0 -> C & X 2106 // FIXME: this should check for C type == X type, not i1? 2107 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2108 return DAG.getNode(ISD::AND, VT, N0, N1); 2109 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2110 if (MVT::i1 == VT && N0 == N1) 2111 return DAG.getNode(ISD::OR, VT, N0, N2); 2112 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2113 if (MVT::i1 == VT && N0 == N2) 2114 return DAG.getNode(ISD::AND, VT, N0, N1); 2115 2116 // If we can fold this based on the true/false value, do so. 2117 if (SimplifySelectOps(N, N1, N2)) 2118 return SDOperand(N, 0); // Don't revisit N. 2119 2120 // fold selects based on a setcc into other things, such as min/max/abs 2121 if (N0.getOpcode() == ISD::SETCC) 2122 // FIXME: 2123 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2124 // having to say they don't support SELECT_CC on every type the DAG knows 2125 // about, since there is no way to mark an opcode illegal at all value types 2126 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2127 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2128 N1, N2, N0.getOperand(2)); 2129 else 2130 return SimplifySelect(N0, N1, N2); 2131 return SDOperand(); 2132} 2133 2134SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2135 SDOperand N0 = N->getOperand(0); 2136 SDOperand N1 = N->getOperand(1); 2137 SDOperand N2 = N->getOperand(2); 2138 SDOperand N3 = N->getOperand(3); 2139 SDOperand N4 = N->getOperand(4); 2140 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2141 2142 // fold select_cc lhs, rhs, x, x, cc -> x 2143 if (N2 == N3) 2144 return N2; 2145 2146 // Determine if the condition we're dealing with is constant 2147 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2148 if (SCC.Val) AddToWorkList(SCC.Val); 2149 2150 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2151 if (SCCC->getValue()) 2152 return N2; // cond always true -> true val 2153 else 2154 return N3; // cond always false -> false val 2155 } 2156 2157 // Fold to a simpler select_cc 2158 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2159 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2160 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2161 SCC.getOperand(2)); 2162 2163 // If we can fold this based on the true/false value, do so. 2164 if (SimplifySelectOps(N, N2, N3)) 2165 return SDOperand(N, 0); // Don't revisit N. 2166 2167 // fold select_cc into other things, such as min/max/abs 2168 return SimplifySelectCC(N0, N1, N2, N3, CC); 2169} 2170 2171SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2172 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2173 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2174} 2175 2176SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2177 SDOperand N0 = N->getOperand(0); 2178 MVT::ValueType VT = N->getValueType(0); 2179 2180 // fold (sext c1) -> c1 2181 if (isa<ConstantSDNode>(N0)) 2182 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2183 2184 // fold (sext (sext x)) -> (sext x) 2185 // fold (sext (aext x)) -> (sext x) 2186 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2187 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2188 2189 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2190 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2191 if (N0.getOpcode() == ISD::TRUNCATE) { 2192 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2193 if (NarrowLoad.Val) { 2194 if (NarrowLoad.Val != N0.Val) 2195 CombineTo(N0.Val, NarrowLoad); 2196 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2197 } 2198 } 2199 2200 // See if the value being truncated is already sign extended. If so, just 2201 // eliminate the trunc/sext pair. 2202 if (N0.getOpcode() == ISD::TRUNCATE) { 2203 SDOperand Op = N0.getOperand(0); 2204 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2205 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2206 unsigned DestBits = MVT::getSizeInBits(VT); 2207 unsigned NumSignBits = TLI.ComputeNumSignBits(Op); 2208 2209 if (OpBits == DestBits) { 2210 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2211 // bits, it is already ready. 2212 if (NumSignBits > DestBits-MidBits) 2213 return Op; 2214 } else if (OpBits < DestBits) { 2215 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2216 // bits, just sext from i32. 2217 if (NumSignBits > OpBits-MidBits) 2218 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2219 } else { 2220 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2221 // bits, just truncate to i32. 2222 if (NumSignBits > OpBits-MidBits) 2223 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2224 } 2225 2226 // fold (sext (truncate x)) -> (sextinreg x). 2227 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2228 N0.getValueType())) { 2229 if (Op.getValueType() < VT) 2230 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2231 else if (Op.getValueType() > VT) 2232 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2233 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2234 DAG.getValueType(N0.getValueType())); 2235 } 2236 } 2237 2238 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2239 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2240 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2241 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2242 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2243 LN0->getBasePtr(), LN0->getSrcValue(), 2244 LN0->getSrcValueOffset(), 2245 N0.getValueType(), 2246 LN0->isVolatile()); 2247 CombineTo(N, ExtLoad); 2248 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2249 ExtLoad.getValue(1)); 2250 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2251 } 2252 2253 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2254 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2255 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2256 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2257 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2258 MVT::ValueType EVT = LN0->getLoadedVT(); 2259 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2260 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2261 LN0->getBasePtr(), LN0->getSrcValue(), 2262 LN0->getSrcValueOffset(), EVT, 2263 LN0->isVolatile(), 2264 LN0->getAlignment()); 2265 CombineTo(N, ExtLoad); 2266 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2267 ExtLoad.getValue(1)); 2268 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2269 } 2270 } 2271 2272 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2273 if (N0.getOpcode() == ISD::SETCC) { 2274 SDOperand SCC = 2275 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2276 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2277 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2278 if (SCC.Val) return SCC; 2279 } 2280 2281 return SDOperand(); 2282} 2283 2284SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2285 SDOperand N0 = N->getOperand(0); 2286 MVT::ValueType VT = N->getValueType(0); 2287 2288 // fold (zext c1) -> c1 2289 if (isa<ConstantSDNode>(N0)) 2290 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2291 // fold (zext (zext x)) -> (zext x) 2292 // fold (zext (aext x)) -> (zext x) 2293 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2294 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2295 2296 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2297 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2298 if (N0.getOpcode() == ISD::TRUNCATE) { 2299 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2300 if (NarrowLoad.Val) { 2301 if (NarrowLoad.Val != N0.Val) 2302 CombineTo(N0.Val, NarrowLoad); 2303 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2304 } 2305 } 2306 2307 // fold (zext (truncate x)) -> (and x, mask) 2308 if (N0.getOpcode() == ISD::TRUNCATE && 2309 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2310 SDOperand Op = N0.getOperand(0); 2311 if (Op.getValueType() < VT) { 2312 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2313 } else if (Op.getValueType() > VT) { 2314 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2315 } 2316 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2317 } 2318 2319 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2320 if (N0.getOpcode() == ISD::AND && 2321 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2322 N0.getOperand(1).getOpcode() == ISD::Constant) { 2323 SDOperand X = N0.getOperand(0).getOperand(0); 2324 if (X.getValueType() < VT) { 2325 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2326 } else if (X.getValueType() > VT) { 2327 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2328 } 2329 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2330 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2331 } 2332 2333 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2334 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2335 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2336 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2337 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2338 LN0->getBasePtr(), LN0->getSrcValue(), 2339 LN0->getSrcValueOffset(), 2340 N0.getValueType(), 2341 LN0->isVolatile(), 2342 LN0->getAlignment()); 2343 CombineTo(N, ExtLoad); 2344 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2345 ExtLoad.getValue(1)); 2346 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2347 } 2348 2349 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2350 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2351 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2352 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2353 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2354 MVT::ValueType EVT = LN0->getLoadedVT(); 2355 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2356 LN0->getBasePtr(), LN0->getSrcValue(), 2357 LN0->getSrcValueOffset(), EVT, 2358 LN0->isVolatile(), 2359 LN0->getAlignment()); 2360 CombineTo(N, ExtLoad); 2361 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2362 ExtLoad.getValue(1)); 2363 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2364 } 2365 2366 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2367 if (N0.getOpcode() == ISD::SETCC) { 2368 SDOperand SCC = 2369 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2370 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2371 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2372 if (SCC.Val) return SCC; 2373 } 2374 2375 return SDOperand(); 2376} 2377 2378SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2379 SDOperand N0 = N->getOperand(0); 2380 MVT::ValueType VT = N->getValueType(0); 2381 2382 // fold (aext c1) -> c1 2383 if (isa<ConstantSDNode>(N0)) 2384 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2385 // fold (aext (aext x)) -> (aext x) 2386 // fold (aext (zext x)) -> (zext x) 2387 // fold (aext (sext x)) -> (sext x) 2388 if (N0.getOpcode() == ISD::ANY_EXTEND || 2389 N0.getOpcode() == ISD::ZERO_EXTEND || 2390 N0.getOpcode() == ISD::SIGN_EXTEND) 2391 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2392 2393 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2394 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2395 if (N0.getOpcode() == ISD::TRUNCATE) { 2396 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2397 if (NarrowLoad.Val) { 2398 if (NarrowLoad.Val != N0.Val) 2399 CombineTo(N0.Val, NarrowLoad); 2400 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2401 } 2402 } 2403 2404 // fold (aext (truncate x)) 2405 if (N0.getOpcode() == ISD::TRUNCATE) { 2406 SDOperand TruncOp = N0.getOperand(0); 2407 if (TruncOp.getValueType() == VT) 2408 return TruncOp; // x iff x size == zext size. 2409 if (TruncOp.getValueType() > VT) 2410 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2411 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2412 } 2413 2414 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2415 if (N0.getOpcode() == ISD::AND && 2416 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2417 N0.getOperand(1).getOpcode() == ISD::Constant) { 2418 SDOperand X = N0.getOperand(0).getOperand(0); 2419 if (X.getValueType() < VT) { 2420 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2421 } else if (X.getValueType() > VT) { 2422 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2423 } 2424 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2425 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2426 } 2427 2428 // fold (aext (load x)) -> (aext (truncate (extload x))) 2429 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2430 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2431 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2432 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2433 LN0->getBasePtr(), LN0->getSrcValue(), 2434 LN0->getSrcValueOffset(), 2435 N0.getValueType(), 2436 LN0->isVolatile(), 2437 LN0->getAlignment()); 2438 CombineTo(N, ExtLoad); 2439 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2440 ExtLoad.getValue(1)); 2441 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2442 } 2443 2444 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2445 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2446 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2447 if (N0.getOpcode() == ISD::LOAD && 2448 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2449 N0.hasOneUse()) { 2450 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2451 MVT::ValueType EVT = LN0->getLoadedVT(); 2452 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2453 LN0->getChain(), LN0->getBasePtr(), 2454 LN0->getSrcValue(), 2455 LN0->getSrcValueOffset(), EVT, 2456 LN0->isVolatile(), 2457 LN0->getAlignment()); 2458 CombineTo(N, ExtLoad); 2459 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2460 ExtLoad.getValue(1)); 2461 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2462 } 2463 2464 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2465 if (N0.getOpcode() == ISD::SETCC) { 2466 SDOperand SCC = 2467 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2468 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2469 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2470 if (SCC.Val) 2471 return SCC; 2472 } 2473 2474 return SDOperand(); 2475} 2476 2477/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2478/// bits and then truncated to a narrower type and where N is a multiple 2479/// of number of bits of the narrower type, transform it to a narrower load 2480/// from address + N / num of bits of new type. If the result is to be 2481/// extended, also fold the extension to form a extending load. 2482SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2483 unsigned Opc = N->getOpcode(); 2484 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2485 SDOperand N0 = N->getOperand(0); 2486 MVT::ValueType VT = N->getValueType(0); 2487 MVT::ValueType EVT = N->getValueType(0); 2488 2489 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2490 // extended to VT. 2491 if (Opc == ISD::SIGN_EXTEND_INREG) { 2492 ExtType = ISD::SEXTLOAD; 2493 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2494 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2495 return SDOperand(); 2496 } 2497 2498 unsigned EVTBits = MVT::getSizeInBits(EVT); 2499 unsigned ShAmt = 0; 2500 bool CombineSRL = false; 2501 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2502 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2503 ShAmt = N01->getValue(); 2504 // Is the shift amount a multiple of size of VT? 2505 if ((ShAmt & (EVTBits-1)) == 0) { 2506 N0 = N0.getOperand(0); 2507 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2508 return SDOperand(); 2509 CombineSRL = true; 2510 } 2511 } 2512 } 2513 2514 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2515 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2516 // zero extended form: by shrinking the load, we lose track of the fact 2517 // that it is already zero extended. 2518 // FIXME: This should be reevaluated. 2519 VT != MVT::i1) { 2520 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 2521 "Cannot truncate to larger type!"); 2522 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2523 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2524 // For big endian targets, we need to adjust the offset to the pointer to 2525 // load the correct bytes. 2526 if (!TLI.isLittleEndian()) 2527 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; 2528 uint64_t PtrOff = ShAmt / 8; 2529 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2530 DAG.getConstant(PtrOff, PtrType)); 2531 AddToWorkList(NewPtr.Val); 2532 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 2533 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 2534 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2535 LN0->isVolatile(), LN0->getAlignment()) 2536 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 2537 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 2538 LN0->isVolatile(), LN0->getAlignment()); 2539 AddToWorkList(N); 2540 if (CombineSRL) { 2541 std::vector<SDNode*> NowDead; 2542 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead); 2543 CombineTo(N->getOperand(0).Val, Load); 2544 } else 2545 CombineTo(N0.Val, Load, Load.getValue(1)); 2546 if (ShAmt) { 2547 if (Opc == ISD::SIGN_EXTEND_INREG) 2548 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 2549 else 2550 return DAG.getNode(Opc, VT, Load); 2551 } 2552 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2553 } 2554 2555 return SDOperand(); 2556} 2557 2558 2559SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2560 SDOperand N0 = N->getOperand(0); 2561 SDOperand N1 = N->getOperand(1); 2562 MVT::ValueType VT = N->getValueType(0); 2563 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2564 unsigned EVTBits = MVT::getSizeInBits(EVT); 2565 2566 // fold (sext_in_reg c1) -> c1 2567 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2568 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2569 2570 // If the input is already sign extended, just drop the extension. 2571 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2572 return N0; 2573 2574 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2575 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2576 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2577 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2578 } 2579 2580 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 2581 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2582 return DAG.getZeroExtendInReg(N0, EVT); 2583 2584 // fold operands of sext_in_reg based on knowledge that the top bits are not 2585 // demanded. 2586 if (SimplifyDemandedBits(SDOperand(N, 0))) 2587 return SDOperand(N, 0); 2588 2589 // fold (sext_in_reg (load x)) -> (smaller sextload x) 2590 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 2591 SDOperand NarrowLoad = ReduceLoadWidth(N); 2592 if (NarrowLoad.Val) 2593 return NarrowLoad; 2594 2595 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2596 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2597 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2598 if (N0.getOpcode() == ISD::SRL) { 2599 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2600 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2601 // We can turn this into an SRA iff the input to the SRL is already sign 2602 // extended enough. 2603 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 2604 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2605 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2606 } 2607 } 2608 2609 // fold (sext_inreg (extload x)) -> (sextload x) 2610 if (ISD::isEXTLoad(N0.Val) && 2611 ISD::isUNINDEXEDLoad(N0.Val) && 2612 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2613 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2614 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2615 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2616 LN0->getBasePtr(), LN0->getSrcValue(), 2617 LN0->getSrcValueOffset(), EVT, 2618 LN0->isVolatile(), 2619 LN0->getAlignment()); 2620 CombineTo(N, ExtLoad); 2621 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2622 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2623 } 2624 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2625 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2626 N0.hasOneUse() && 2627 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2628 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2629 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2630 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2631 LN0->getBasePtr(), LN0->getSrcValue(), 2632 LN0->getSrcValueOffset(), EVT, 2633 LN0->isVolatile(), 2634 LN0->getAlignment()); 2635 CombineTo(N, ExtLoad); 2636 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2637 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2638 } 2639 return SDOperand(); 2640} 2641 2642SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2643 SDOperand N0 = N->getOperand(0); 2644 MVT::ValueType VT = N->getValueType(0); 2645 2646 // noop truncate 2647 if (N0.getValueType() == N->getValueType(0)) 2648 return N0; 2649 // fold (truncate c1) -> c1 2650 if (isa<ConstantSDNode>(N0)) 2651 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2652 // fold (truncate (truncate x)) -> (truncate x) 2653 if (N0.getOpcode() == ISD::TRUNCATE) 2654 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2655 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2656 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2657 N0.getOpcode() == ISD::ANY_EXTEND) { 2658 if (N0.getOperand(0).getValueType() < VT) 2659 // if the source is smaller than the dest, we still need an extend 2660 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2661 else if (N0.getOperand(0).getValueType() > VT) 2662 // if the source is larger than the dest, than we just need the truncate 2663 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2664 else 2665 // if the source and dest are the same type, we can drop both the extend 2666 // and the truncate 2667 return N0.getOperand(0); 2668 } 2669 2670 // fold (truncate (load x)) -> (smaller load x) 2671 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 2672 return ReduceLoadWidth(N); 2673} 2674 2675SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2676 SDOperand N0 = N->getOperand(0); 2677 MVT::ValueType VT = N->getValueType(0); 2678 2679 // If the input is a constant, let getNode() fold it. 2680 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2681 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2682 if (Res.Val != N) return Res; 2683 } 2684 2685 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2686 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2687 2688 // fold (conv (load x)) -> (load (conv*)x) 2689 // If the resultant load doesn't need a higher alignment than the original! 2690 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2691 ISD::isUNINDEXEDLoad(N0.Val) && 2692 TLI.isOperationLegal(ISD::LOAD, VT)) { 2693 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2694 unsigned Align = TLI.getTargetMachine().getTargetData()-> 2695 getABITypeAlignment(MVT::getTypeForValueType(VT)); 2696 unsigned OrigAlign = LN0->getAlignment(); 2697 if (Align <= OrigAlign) { 2698 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 2699 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2700 LN0->isVolatile(), LN0->getAlignment()); 2701 AddToWorkList(N); 2702 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2703 Load.getValue(1)); 2704 return Load; 2705 } 2706 } 2707 2708 return SDOperand(); 2709} 2710 2711SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2712 SDOperand N0 = N->getOperand(0); 2713 MVT::ValueType VT = N->getValueType(0); 2714 2715 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2716 // First check to see if this is all constant. 2717 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2718 VT == MVT::Vector) { 2719 bool isSimple = true; 2720 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2721 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2722 N0.getOperand(i).getOpcode() != ISD::Constant && 2723 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2724 isSimple = false; 2725 break; 2726 } 2727 2728 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2729 if (isSimple && !MVT::isVector(DestEltVT)) { 2730 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2731 } 2732 } 2733 2734 return SDOperand(); 2735} 2736 2737/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2738/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2739/// destination element value type. 2740SDOperand DAGCombiner:: 2741ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2742 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2743 2744 // If this is already the right type, we're done. 2745 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2746 2747 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2748 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2749 2750 // If this is a conversion of N elements of one type to N elements of another 2751 // type, convert each element. This handles FP<->INT cases. 2752 if (SrcBitSize == DstBitSize) { 2753 SmallVector<SDOperand, 8> Ops; 2754 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2755 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2756 AddToWorkList(Ops.back().Val); 2757 } 2758 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2759 Ops.push_back(DAG.getValueType(DstEltVT)); 2760 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2761 } 2762 2763 // Otherwise, we're growing or shrinking the elements. To avoid having to 2764 // handle annoying details of growing/shrinking FP values, we convert them to 2765 // int first. 2766 if (MVT::isFloatingPoint(SrcEltVT)) { 2767 // Convert the input float vector to a int vector where the elements are the 2768 // same sizes. 2769 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2770 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2771 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2772 SrcEltVT = IntVT; 2773 } 2774 2775 // Now we know the input is an integer vector. If the output is a FP type, 2776 // convert to integer first, then to FP of the right size. 2777 if (MVT::isFloatingPoint(DstEltVT)) { 2778 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2779 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2780 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2781 2782 // Next, convert to FP elements of the same size. 2783 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2784 } 2785 2786 // Okay, we know the src/dst types are both integers of differing types. 2787 // Handling growing first. 2788 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2789 if (SrcBitSize < DstBitSize) { 2790 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2791 2792 SmallVector<SDOperand, 8> Ops; 2793 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2794 i += NumInputsPerOutput) { 2795 bool isLE = TLI.isLittleEndian(); 2796 uint64_t NewBits = 0; 2797 bool EltIsUndef = true; 2798 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2799 // Shift the previously computed bits over. 2800 NewBits <<= SrcBitSize; 2801 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2802 if (Op.getOpcode() == ISD::UNDEF) continue; 2803 EltIsUndef = false; 2804 2805 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2806 } 2807 2808 if (EltIsUndef) 2809 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2810 else 2811 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2812 } 2813 2814 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2815 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2816 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2817 } 2818 2819 // Finally, this must be the case where we are shrinking elements: each input 2820 // turns into multiple outputs. 2821 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2822 SmallVector<SDOperand, 8> Ops; 2823 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2824 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2825 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2826 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2827 continue; 2828 } 2829 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2830 2831 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2832 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2833 OpVal >>= DstBitSize; 2834 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2835 } 2836 2837 // For big endian targets, swap the order of the pieces of each element. 2838 if (!TLI.isLittleEndian()) 2839 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2840 } 2841 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2842 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2843 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2844} 2845 2846 2847 2848SDOperand DAGCombiner::visitFADD(SDNode *N) { 2849 SDOperand N0 = N->getOperand(0); 2850 SDOperand N1 = N->getOperand(1); 2851 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2852 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2853 MVT::ValueType VT = N->getValueType(0); 2854 2855 // fold (fadd c1, c2) -> c1+c2 2856 if (N0CFP && N1CFP) 2857 return DAG.getNode(ISD::FADD, VT, N0, N1); 2858 // canonicalize constant to RHS 2859 if (N0CFP && !N1CFP) 2860 return DAG.getNode(ISD::FADD, VT, N1, N0); 2861 // fold (A + (-B)) -> A-B 2862 if (isNegatibleForFree(N1) == 2) 2863 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 2864 // fold ((-A) + B) -> B-A 2865 if (isNegatibleForFree(N0) == 2) 2866 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 2867 2868 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 2869 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 2870 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2871 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 2872 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 2873 2874 return SDOperand(); 2875} 2876 2877SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2878 SDOperand N0 = N->getOperand(0); 2879 SDOperand N1 = N->getOperand(1); 2880 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2881 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2882 MVT::ValueType VT = N->getValueType(0); 2883 2884 // fold (fsub c1, c2) -> c1-c2 2885 if (N0CFP && N1CFP) 2886 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2887 // fold (A-(-B)) -> A+B 2888 if (isNegatibleForFree(N1)) 2889 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 2890 2891 return SDOperand(); 2892} 2893 2894SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2895 SDOperand N0 = N->getOperand(0); 2896 SDOperand N1 = N->getOperand(1); 2897 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2898 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2899 MVT::ValueType VT = N->getValueType(0); 2900 2901 // fold (fmul c1, c2) -> c1*c2 2902 if (N0CFP && N1CFP) 2903 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2904 // canonicalize constant to RHS 2905 if (N0CFP && !N1CFP) 2906 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2907 // fold (fmul X, 2.0) -> (fadd X, X) 2908 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2909 return DAG.getNode(ISD::FADD, VT, N0, N0); 2910 // fold (fmul X, -1.0) -> (fneg X) 2911 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 2912 return DAG.getNode(ISD::FNEG, VT, N0); 2913 2914 // -X * -Y -> X*Y 2915 if (char LHSNeg = isNegatibleForFree(N0)) { 2916 if (char RHSNeg = isNegatibleForFree(N1)) { 2917 // Both can be negated for free, check to see if at least one is cheaper 2918 // negated. 2919 if (LHSNeg == 2 || RHSNeg == 2) 2920 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 2921 GetNegatedExpression(N1, DAG)); 2922 } 2923 } 2924 2925 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 2926 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 2927 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2928 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 2929 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 2930 2931 return SDOperand(); 2932} 2933 2934SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2935 SDOperand N0 = N->getOperand(0); 2936 SDOperand N1 = N->getOperand(1); 2937 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2938 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2939 MVT::ValueType VT = N->getValueType(0); 2940 2941 // fold (fdiv c1, c2) -> c1/c2 2942 if (N0CFP && N1CFP) 2943 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2944 2945 2946 // -X / -Y -> X*Y 2947 if (char LHSNeg = isNegatibleForFree(N0)) { 2948 if (char RHSNeg = isNegatibleForFree(N1)) { 2949 // Both can be negated for free, check to see if at least one is cheaper 2950 // negated. 2951 if (LHSNeg == 2 || RHSNeg == 2) 2952 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 2953 GetNegatedExpression(N1, DAG)); 2954 } 2955 } 2956 2957 return SDOperand(); 2958} 2959 2960SDOperand DAGCombiner::visitFREM(SDNode *N) { 2961 SDOperand N0 = N->getOperand(0); 2962 SDOperand N1 = N->getOperand(1); 2963 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2964 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2965 MVT::ValueType VT = N->getValueType(0); 2966 2967 // fold (frem c1, c2) -> fmod(c1,c2) 2968 if (N0CFP && N1CFP) 2969 return DAG.getNode(ISD::FREM, VT, N0, N1); 2970 return SDOperand(); 2971} 2972 2973SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2974 SDOperand N0 = N->getOperand(0); 2975 SDOperand N1 = N->getOperand(1); 2976 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2977 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2978 MVT::ValueType VT = N->getValueType(0); 2979 2980 if (N0CFP && N1CFP) // Constant fold 2981 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2982 2983 if (N1CFP) { 2984 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2985 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2986 union { 2987 double d; 2988 int64_t i; 2989 } u; 2990 u.d = N1CFP->getValue(); 2991 if (u.i >= 0) 2992 return DAG.getNode(ISD::FABS, VT, N0); 2993 else 2994 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2995 } 2996 2997 // copysign(fabs(x), y) -> copysign(x, y) 2998 // copysign(fneg(x), y) -> copysign(x, y) 2999 // copysign(copysign(x,z), y) -> copysign(x, y) 3000 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3001 N0.getOpcode() == ISD::FCOPYSIGN) 3002 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3003 3004 // copysign(x, abs(y)) -> abs(x) 3005 if (N1.getOpcode() == ISD::FABS) 3006 return DAG.getNode(ISD::FABS, VT, N0); 3007 3008 // copysign(x, copysign(y,z)) -> copysign(x, z) 3009 if (N1.getOpcode() == ISD::FCOPYSIGN) 3010 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3011 3012 // copysign(x, fp_extend(y)) -> copysign(x, y) 3013 // copysign(x, fp_round(y)) -> copysign(x, y) 3014 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3015 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3016 3017 return SDOperand(); 3018} 3019 3020 3021 3022SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3023 SDOperand N0 = N->getOperand(0); 3024 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3025 MVT::ValueType VT = N->getValueType(0); 3026 3027 // fold (sint_to_fp c1) -> c1fp 3028 if (N0C) 3029 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3030 return SDOperand(); 3031} 3032 3033SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3034 SDOperand N0 = N->getOperand(0); 3035 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3036 MVT::ValueType VT = N->getValueType(0); 3037 3038 // fold (uint_to_fp c1) -> c1fp 3039 if (N0C) 3040 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3041 return SDOperand(); 3042} 3043 3044SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3045 SDOperand N0 = N->getOperand(0); 3046 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3047 MVT::ValueType VT = N->getValueType(0); 3048 3049 // fold (fp_to_sint c1fp) -> c1 3050 if (N0CFP) 3051 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3052 return SDOperand(); 3053} 3054 3055SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3056 SDOperand N0 = N->getOperand(0); 3057 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3058 MVT::ValueType VT = N->getValueType(0); 3059 3060 // fold (fp_to_uint c1fp) -> c1 3061 if (N0CFP) 3062 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3063 return SDOperand(); 3064} 3065 3066SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3067 SDOperand N0 = N->getOperand(0); 3068 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3069 MVT::ValueType VT = N->getValueType(0); 3070 3071 // fold (fp_round c1fp) -> c1fp 3072 if (N0CFP) 3073 return DAG.getNode(ISD::FP_ROUND, VT, N0); 3074 3075 // fold (fp_round (fp_extend x)) -> x 3076 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3077 return N0.getOperand(0); 3078 3079 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3080 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3081 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 3082 AddToWorkList(Tmp.Val); 3083 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3084 } 3085 3086 return SDOperand(); 3087} 3088 3089SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3090 SDOperand N0 = N->getOperand(0); 3091 MVT::ValueType VT = N->getValueType(0); 3092 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3093 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3094 3095 // fold (fp_round_inreg c1fp) -> c1fp 3096 if (N0CFP) { 3097 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 3098 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3099 } 3100 return SDOperand(); 3101} 3102 3103SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3104 SDOperand N0 = N->getOperand(0); 3105 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3106 MVT::ValueType VT = N->getValueType(0); 3107 3108 // fold (fp_extend c1fp) -> c1fp 3109 if (N0CFP) 3110 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3111 3112 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 3113 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3114 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3115 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3116 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3117 LN0->getBasePtr(), LN0->getSrcValue(), 3118 LN0->getSrcValueOffset(), 3119 N0.getValueType(), 3120 LN0->isVolatile(), 3121 LN0->getAlignment()); 3122 CombineTo(N, ExtLoad); 3123 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 3124 ExtLoad.getValue(1)); 3125 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3126 } 3127 3128 3129 return SDOperand(); 3130} 3131 3132SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3133 SDOperand N0 = N->getOperand(0); 3134 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3135 MVT::ValueType VT = N->getValueType(0); 3136 3137 // fold (fneg c1) -> -c1 3138 if (N0CFP) 3139 return DAG.getNode(ISD::FNEG, VT, N0); 3140 // fold (fneg (sub x, y)) -> (sub y, x) 3141 if (N0.getOpcode() == ISD::SUB) 3142 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 3143 // fold (fneg (fneg x)) -> x 3144 if (N0.getOpcode() == ISD::FNEG) 3145 return N0.getOperand(0); 3146 return SDOperand(); 3147} 3148 3149SDOperand DAGCombiner::visitFABS(SDNode *N) { 3150 SDOperand N0 = N->getOperand(0); 3151 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3152 MVT::ValueType VT = N->getValueType(0); 3153 3154 // fold (fabs c1) -> fabs(c1) 3155 if (N0CFP) 3156 return DAG.getNode(ISD::FABS, VT, N0); 3157 // fold (fabs (fabs x)) -> (fabs x) 3158 if (N0.getOpcode() == ISD::FABS) 3159 return N->getOperand(0); 3160 // fold (fabs (fneg x)) -> (fabs x) 3161 // fold (fabs (fcopysign x, y)) -> (fabs x) 3162 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3163 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3164 3165 return SDOperand(); 3166} 3167 3168SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3169 SDOperand Chain = N->getOperand(0); 3170 SDOperand N1 = N->getOperand(1); 3171 SDOperand N2 = N->getOperand(2); 3172 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3173 3174 // never taken branch, fold to chain 3175 if (N1C && N1C->isNullValue()) 3176 return Chain; 3177 // unconditional branch 3178 if (N1C && N1C->getValue() == 1) 3179 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3180 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3181 // on the target. 3182 if (N1.getOpcode() == ISD::SETCC && 3183 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3184 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3185 N1.getOperand(0), N1.getOperand(1), N2); 3186 } 3187 return SDOperand(); 3188} 3189 3190// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3191// 3192SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3193 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3194 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3195 3196 // Use SimplifySetCC to simplify SETCC's. 3197 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3198 if (Simp.Val) AddToWorkList(Simp.Val); 3199 3200 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3201 3202 // fold br_cc true, dest -> br dest (unconditional branch) 3203 if (SCCC && SCCC->getValue()) 3204 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3205 N->getOperand(4)); 3206 // fold br_cc false, dest -> unconditional fall through 3207 if (SCCC && SCCC->isNullValue()) 3208 return N->getOperand(0); 3209 3210 // fold to a simpler setcc 3211 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3212 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3213 Simp.getOperand(2), Simp.getOperand(0), 3214 Simp.getOperand(1), N->getOperand(4)); 3215 return SDOperand(); 3216} 3217 3218 3219/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3220/// pre-indexed load / store when the base pointer is a add or subtract 3221/// and it has other uses besides the load / store. After the 3222/// transformation, the new indexed load / store has effectively folded 3223/// the add / subtract in and all of its other uses are redirected to the 3224/// new load / store. 3225bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3226 if (!AfterLegalize) 3227 return false; 3228 3229 bool isLoad = true; 3230 SDOperand Ptr; 3231 MVT::ValueType VT; 3232 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3233 if (LD->getAddressingMode() != ISD::UNINDEXED) 3234 return false; 3235 VT = LD->getLoadedVT(); 3236 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3237 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3238 return false; 3239 Ptr = LD->getBasePtr(); 3240 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3241 if (ST->getAddressingMode() != ISD::UNINDEXED) 3242 return false; 3243 VT = ST->getStoredVT(); 3244 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3245 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3246 return false; 3247 Ptr = ST->getBasePtr(); 3248 isLoad = false; 3249 } else 3250 return false; 3251 3252 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3253 // out. There is no reason to make this a preinc/predec. 3254 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3255 Ptr.Val->hasOneUse()) 3256 return false; 3257 3258 // Ask the target to do addressing mode selection. 3259 SDOperand BasePtr; 3260 SDOperand Offset; 3261 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3262 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3263 return false; 3264 // Don't create a indexed load / store with zero offset. 3265 if (isa<ConstantSDNode>(Offset) && 3266 cast<ConstantSDNode>(Offset)->getValue() == 0) 3267 return false; 3268 3269 // Try turning it into a pre-indexed load / store except when: 3270 // 1) The base is a frame index. 3271 // 2) If N is a store and the ptr is either the same as or is a 3272 // predecessor of the value being stored. 3273 // 3) Another use of base ptr is a predecessor of N. If ptr is folded 3274 // that would create a cycle. 3275 // 4) All uses are load / store ops that use it as base ptr. 3276 3277 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3278 // (plus the implicit offset) to a register to preinc anyway. 3279 if (isa<FrameIndexSDNode>(BasePtr)) 3280 return false; 3281 3282 // Check #2. 3283 if (!isLoad) { 3284 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3285 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val)) 3286 return false; 3287 } 3288 3289 // Now check for #2 and #3. 3290 bool RealUse = false; 3291 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3292 E = Ptr.Val->use_end(); I != E; ++I) { 3293 SDNode *Use = *I; 3294 if (Use == N) 3295 continue; 3296 if (Use->isPredecessor(N)) 3297 return false; 3298 3299 if (!((Use->getOpcode() == ISD::LOAD && 3300 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3301 (Use->getOpcode() == ISD::STORE) && 3302 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3303 RealUse = true; 3304 } 3305 if (!RealUse) 3306 return false; 3307 3308 SDOperand Result; 3309 if (isLoad) 3310 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3311 else 3312 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3313 ++PreIndexedNodes; 3314 ++NodesCombined; 3315 DOUT << "\nReplacing.4 "; DEBUG(N->dump()); 3316 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3317 DOUT << '\n'; 3318 std::vector<SDNode*> NowDead; 3319 if (isLoad) { 3320 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3321 NowDead); 3322 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3323 NowDead); 3324 } else { 3325 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3326 NowDead); 3327 } 3328 3329 // Nodes can end up on the worklist more than once. Make sure we do 3330 // not process a node that has been replaced. 3331 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3332 removeFromWorkList(NowDead[i]); 3333 // Finally, since the node is now dead, remove it from the graph. 3334 DAG.DeleteNode(N); 3335 3336 // Replace the uses of Ptr with uses of the updated base value. 3337 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3338 NowDead); 3339 removeFromWorkList(Ptr.Val); 3340 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3341 removeFromWorkList(NowDead[i]); 3342 DAG.DeleteNode(Ptr.Val); 3343 3344 return true; 3345} 3346 3347/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3348/// add / sub of the base pointer node into a post-indexed load / store. 3349/// The transformation folded the add / subtract into the new indexed 3350/// load / store effectively and all of its uses are redirected to the 3351/// new load / store. 3352bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3353 if (!AfterLegalize) 3354 return false; 3355 3356 bool isLoad = true; 3357 SDOperand Ptr; 3358 MVT::ValueType VT; 3359 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3360 if (LD->getAddressingMode() != ISD::UNINDEXED) 3361 return false; 3362 VT = LD->getLoadedVT(); 3363 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3364 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3365 return false; 3366 Ptr = LD->getBasePtr(); 3367 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3368 if (ST->getAddressingMode() != ISD::UNINDEXED) 3369 return false; 3370 VT = ST->getStoredVT(); 3371 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3372 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3373 return false; 3374 Ptr = ST->getBasePtr(); 3375 isLoad = false; 3376 } else 3377 return false; 3378 3379 if (Ptr.Val->hasOneUse()) 3380 return false; 3381 3382 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3383 E = Ptr.Val->use_end(); I != E; ++I) { 3384 SDNode *Op = *I; 3385 if (Op == N || 3386 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3387 continue; 3388 3389 SDOperand BasePtr; 3390 SDOperand Offset; 3391 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3392 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3393 if (Ptr == Offset) 3394 std::swap(BasePtr, Offset); 3395 if (Ptr != BasePtr) 3396 continue; 3397 // Don't create a indexed load / store with zero offset. 3398 if (isa<ConstantSDNode>(Offset) && 3399 cast<ConstantSDNode>(Offset)->getValue() == 0) 3400 continue; 3401 3402 // Try turning it into a post-indexed load / store except when 3403 // 1) All uses are load / store ops that use it as base ptr. 3404 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3405 // nor a successor of N. Otherwise, if Op is folded that would 3406 // create a cycle. 3407 3408 // Check for #1. 3409 bool TryNext = false; 3410 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3411 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3412 SDNode *Use = *II; 3413 if (Use == Ptr.Val) 3414 continue; 3415 3416 // If all the uses are load / store addresses, then don't do the 3417 // transformation. 3418 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3419 bool RealUse = false; 3420 for (SDNode::use_iterator III = Use->use_begin(), 3421 EEE = Use->use_end(); III != EEE; ++III) { 3422 SDNode *UseUse = *III; 3423 if (!((UseUse->getOpcode() == ISD::LOAD && 3424 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3425 (UseUse->getOpcode() == ISD::STORE) && 3426 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3427 RealUse = true; 3428 } 3429 3430 if (!RealUse) { 3431 TryNext = true; 3432 break; 3433 } 3434 } 3435 } 3436 if (TryNext) 3437 continue; 3438 3439 // Check for #2 3440 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3441 SDOperand Result = isLoad 3442 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3443 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3444 ++PostIndexedNodes; 3445 ++NodesCombined; 3446 DOUT << "\nReplacing.5 "; DEBUG(N->dump()); 3447 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3448 DOUT << '\n'; 3449 std::vector<SDNode*> NowDead; 3450 if (isLoad) { 3451 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3452 NowDead); 3453 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3454 NowDead); 3455 } else { 3456 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3457 NowDead); 3458 } 3459 3460 // Nodes can end up on the worklist more than once. Make sure we do 3461 // not process a node that has been replaced. 3462 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3463 removeFromWorkList(NowDead[i]); 3464 // Finally, since the node is now dead, remove it from the graph. 3465 DAG.DeleteNode(N); 3466 3467 // Replace the uses of Use with uses of the updated base value. 3468 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3469 Result.getValue(isLoad ? 1 : 0), 3470 NowDead); 3471 removeFromWorkList(Op); 3472 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3473 removeFromWorkList(NowDead[i]); 3474 DAG.DeleteNode(Op); 3475 3476 return true; 3477 } 3478 } 3479 } 3480 return false; 3481} 3482 3483 3484SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3485 LoadSDNode *LD = cast<LoadSDNode>(N); 3486 SDOperand Chain = LD->getChain(); 3487 SDOperand Ptr = LD->getBasePtr(); 3488 3489 // If load is not volatile and there are no uses of the loaded value (and 3490 // the updated indexed value in case of indexed loads), change uses of the 3491 // chain value into uses of the chain input (i.e. delete the dead load). 3492 if (!LD->isVolatile()) { 3493 if (N->getValueType(1) == MVT::Other) { 3494 // Unindexed loads. 3495 if (N->hasNUsesOfValue(0, 0)) 3496 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3497 } else { 3498 // Indexed loads. 3499 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 3500 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 3501 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3502 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1)); 3503 SDOperand To[] = { Undef0, Undef1, Chain }; 3504 return CombineTo(N, To, 3); 3505 } 3506 } 3507 } 3508 3509 // If this load is directly stored, replace the load value with the stored 3510 // value. 3511 // TODO: Handle store large -> read small portion. 3512 // TODO: Handle TRUNCSTORE/LOADEXT 3513 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3514 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3515 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3516 if (PrevST->getBasePtr() == Ptr && 3517 PrevST->getValue().getValueType() == N->getValueType(0)) 3518 return CombineTo(N, Chain.getOperand(1), Chain); 3519 } 3520 } 3521 3522 if (CombinerAA) { 3523 // Walk up chain skipping non-aliasing memory nodes. 3524 SDOperand BetterChain = FindBetterChain(N, Chain); 3525 3526 // If there is a better chain. 3527 if (Chain != BetterChain) { 3528 SDOperand ReplLoad; 3529 3530 // Replace the chain to void dependency. 3531 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3532 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3533 LD->getSrcValue(), LD->getSrcValueOffset(), 3534 LD->isVolatile(), LD->getAlignment()); 3535 } else { 3536 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3537 LD->getValueType(0), 3538 BetterChain, Ptr, LD->getSrcValue(), 3539 LD->getSrcValueOffset(), 3540 LD->getLoadedVT(), 3541 LD->isVolatile(), 3542 LD->getAlignment()); 3543 } 3544 3545 // Create token factor to keep old chain connected. 3546 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3547 Chain, ReplLoad.getValue(1)); 3548 3549 // Replace uses with load result and token factor. Don't add users 3550 // to work list. 3551 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3552 } 3553 } 3554 3555 // Try transforming N to an indexed load. 3556 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3557 return SDOperand(N, 0); 3558 3559 return SDOperand(); 3560} 3561 3562SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3563 StoreSDNode *ST = cast<StoreSDNode>(N); 3564 SDOperand Chain = ST->getChain(); 3565 SDOperand Value = ST->getValue(); 3566 SDOperand Ptr = ST->getBasePtr(); 3567 3568 // If this is a store of a bit convert, store the input value if the 3569 // resultant store does not need a higher alignment than the original. 3570 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 3571 ST->getAddressingMode() == ISD::UNINDEXED) { 3572 unsigned Align = ST->getAlignment(); 3573 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 3574 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 3575 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 3576 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 3577 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3578 ST->getSrcValueOffset()); 3579 } 3580 3581 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3582 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3583 if (Value.getOpcode() != ISD::TargetConstantFP) { 3584 SDOperand Tmp; 3585 switch (CFP->getValueType(0)) { 3586 default: assert(0 && "Unknown FP type"); 3587 case MVT::f32: 3588 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3589 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 3590 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3591 ST->getSrcValueOffset()); 3592 } 3593 break; 3594 case MVT::f64: 3595 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3596 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 3597 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3598 ST->getSrcValueOffset()); 3599 } else if (TLI.isTypeLegal(MVT::i32)) { 3600 // Many FP stores are not make apparent until after legalize, e.g. for 3601 // argument passing. Since this is so common, custom legalize the 3602 // 64-bit integer store into two 32-bit stores. 3603 uint64_t Val = DoubleToBits(CFP->getValue()); 3604 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3605 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3606 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3607 3608 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3609 ST->getSrcValueOffset()); 3610 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3611 DAG.getConstant(4, Ptr.getValueType())); 3612 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 3613 ST->getSrcValueOffset()+4); 3614 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 3615 } 3616 break; 3617 } 3618 } 3619 } 3620 3621 if (CombinerAA) { 3622 // Walk up chain skipping non-aliasing memory nodes. 3623 SDOperand BetterChain = FindBetterChain(N, Chain); 3624 3625 // If there is a better chain. 3626 if (Chain != BetterChain) { 3627 // Replace the chain to avoid dependency. 3628 SDOperand ReplStore; 3629 if (ST->isTruncatingStore()) { 3630 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 3631 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT()); 3632 } else { 3633 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 3634 ST->getSrcValue(), ST->getSrcValueOffset()); 3635 } 3636 3637 // Create token to keep both nodes around. 3638 SDOperand Token = 3639 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 3640 3641 // Don't add users to work list. 3642 return CombineTo(N, Token, false); 3643 } 3644 } 3645 3646 // Try transforming N to an indexed store. 3647 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3648 return SDOperand(N, 0); 3649 3650 return SDOperand(); 3651} 3652 3653SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 3654 SDOperand InVec = N->getOperand(0); 3655 SDOperand InVal = N->getOperand(1); 3656 SDOperand EltNo = N->getOperand(2); 3657 3658 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 3659 // vector with the inserted element. 3660 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3661 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3662 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3663 if (Elt < Ops.size()) 3664 Ops[Elt] = InVal; 3665 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 3666 &Ops[0], Ops.size()); 3667 } 3668 3669 return SDOperand(); 3670} 3671 3672SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 3673 SDOperand InVec = N->getOperand(0); 3674 SDOperand InVal = N->getOperand(1); 3675 SDOperand EltNo = N->getOperand(2); 3676 SDOperand NumElts = N->getOperand(3); 3677 SDOperand EltType = N->getOperand(4); 3678 3679 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 3680 // vector with the inserted element. 3681 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3682 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3683 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3684 if (Elt < Ops.size()-2) 3685 Ops[Elt] = InVal; 3686 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), 3687 &Ops[0], Ops.size()); 3688 } 3689 3690 return SDOperand(); 3691} 3692 3693SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 3694 unsigned NumInScalars = N->getNumOperands()-2; 3695 SDOperand NumElts = N->getOperand(NumInScalars); 3696 SDOperand EltType = N->getOperand(NumInScalars+1); 3697 3698 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 3699 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 3700 // two distinct vectors, turn this into a shuffle node. 3701 SDOperand VecIn1, VecIn2; 3702 for (unsigned i = 0; i != NumInScalars; ++i) { 3703 // Ignore undef inputs. 3704 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3705 3706 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 3707 // constant index, bail out. 3708 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 3709 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 3710 VecIn1 = VecIn2 = SDOperand(0, 0); 3711 break; 3712 } 3713 3714 // If the input vector type disagrees with the result of the vbuild_vector, 3715 // we can't make a shuffle. 3716 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 3717 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 3718 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 3719 VecIn1 = VecIn2 = SDOperand(0, 0); 3720 break; 3721 } 3722 3723 // Otherwise, remember this. We allow up to two distinct input vectors. 3724 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 3725 continue; 3726 3727 if (VecIn1.Val == 0) { 3728 VecIn1 = ExtractedFromVec; 3729 } else if (VecIn2.Val == 0) { 3730 VecIn2 = ExtractedFromVec; 3731 } else { 3732 // Too many inputs. 3733 VecIn1 = VecIn2 = SDOperand(0, 0); 3734 break; 3735 } 3736 } 3737 3738 // If everything is good, we can make a shuffle operation. 3739 if (VecIn1.Val) { 3740 SmallVector<SDOperand, 8> BuildVecIndices; 3741 for (unsigned i = 0; i != NumInScalars; ++i) { 3742 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 3743 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 3744 continue; 3745 } 3746 3747 SDOperand Extract = N->getOperand(i); 3748 3749 // If extracting from the first vector, just use the index directly. 3750 if (Extract.getOperand(0) == VecIn1) { 3751 BuildVecIndices.push_back(Extract.getOperand(1)); 3752 continue; 3753 } 3754 3755 // Otherwise, use InIdx + VecSize 3756 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 3757 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 3758 TLI.getPointerTy())); 3759 } 3760 3761 // Add count and size info. 3762 BuildVecIndices.push_back(NumElts); 3763 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy())); 3764 3765 // Return the new VVECTOR_SHUFFLE node. 3766 SDOperand Ops[5]; 3767 Ops[0] = VecIn1; 3768 if (VecIn2.Val) { 3769 Ops[1] = VecIn2; 3770 } else { 3771 // Use an undef vbuild_vector as input for the second operand. 3772 std::vector<SDOperand> UnOps(NumInScalars, 3773 DAG.getNode(ISD::UNDEF, 3774 cast<VTSDNode>(EltType)->getVT())); 3775 UnOps.push_back(NumElts); 3776 UnOps.push_back(EltType); 3777 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3778 &UnOps[0], UnOps.size()); 3779 AddToWorkList(Ops[1].Val); 3780 } 3781 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3782 &BuildVecIndices[0], BuildVecIndices.size()); 3783 Ops[3] = NumElts; 3784 Ops[4] = EltType; 3785 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5); 3786 } 3787 3788 return SDOperand(); 3789} 3790 3791SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 3792 SDOperand ShufMask = N->getOperand(2); 3793 unsigned NumElts = ShufMask.getNumOperands(); 3794 3795 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3796 bool isIdentity = true; 3797 for (unsigned i = 0; i != NumElts; ++i) { 3798 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3799 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3800 isIdentity = false; 3801 break; 3802 } 3803 } 3804 if (isIdentity) return N->getOperand(0); 3805 3806 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3807 isIdentity = true; 3808 for (unsigned i = 0; i != NumElts; ++i) { 3809 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3810 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3811 isIdentity = false; 3812 break; 3813 } 3814 } 3815 if (isIdentity) return N->getOperand(1); 3816 3817 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3818 // needed at all. 3819 bool isUnary = true; 3820 bool isSplat = true; 3821 int VecNum = -1; 3822 unsigned BaseIdx = 0; 3823 for (unsigned i = 0; i != NumElts; ++i) 3824 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3825 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3826 int V = (Idx < NumElts) ? 0 : 1; 3827 if (VecNum == -1) { 3828 VecNum = V; 3829 BaseIdx = Idx; 3830 } else { 3831 if (BaseIdx != Idx) 3832 isSplat = false; 3833 if (VecNum != V) { 3834 isUnary = false; 3835 break; 3836 } 3837 } 3838 } 3839 3840 SDOperand N0 = N->getOperand(0); 3841 SDOperand N1 = N->getOperand(1); 3842 // Normalize unary shuffle so the RHS is undef. 3843 if (isUnary && VecNum == 1) 3844 std::swap(N0, N1); 3845 3846 // If it is a splat, check if the argument vector is a build_vector with 3847 // all scalar elements the same. 3848 if (isSplat) { 3849 SDNode *V = N0.Val; 3850 if (V->getOpcode() == ISD::BIT_CONVERT) 3851 V = V->getOperand(0).Val; 3852 if (V->getOpcode() == ISD::BUILD_VECTOR) { 3853 unsigned NumElems = V->getNumOperands()-2; 3854 if (NumElems > BaseIdx) { 3855 SDOperand Base; 3856 bool AllSame = true; 3857 for (unsigned i = 0; i != NumElems; ++i) { 3858 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3859 Base = V->getOperand(i); 3860 break; 3861 } 3862 } 3863 // Splat of <u, u, u, u>, return <u, u, u, u> 3864 if (!Base.Val) 3865 return N0; 3866 for (unsigned i = 0; i != NumElems; ++i) { 3867 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3868 V->getOperand(i) != Base) { 3869 AllSame = false; 3870 break; 3871 } 3872 } 3873 // Splat of <x, x, x, x>, return <x, x, x, x> 3874 if (AllSame) 3875 return N0; 3876 } 3877 } 3878 } 3879 3880 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3881 // into an undef. 3882 if (isUnary || N0 == N1) { 3883 if (N0.getOpcode() == ISD::UNDEF) 3884 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3885 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3886 // first operand. 3887 SmallVector<SDOperand, 8> MappedOps; 3888 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 3889 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3890 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3891 MappedOps.push_back(ShufMask.getOperand(i)); 3892 } else { 3893 unsigned NewIdx = 3894 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3895 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3896 } 3897 } 3898 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 3899 &MappedOps[0], MappedOps.size()); 3900 AddToWorkList(ShufMask.Val); 3901 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 3902 N0, 3903 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 3904 ShufMask); 3905 } 3906 3907 return SDOperand(); 3908} 3909 3910SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 3911 SDOperand ShufMask = N->getOperand(2); 3912 unsigned NumElts = ShufMask.getNumOperands()-2; 3913 3914 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3915 bool isIdentity = true; 3916 for (unsigned i = 0; i != NumElts; ++i) { 3917 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3918 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3919 isIdentity = false; 3920 break; 3921 } 3922 } 3923 if (isIdentity) return N->getOperand(0); 3924 3925 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3926 isIdentity = true; 3927 for (unsigned i = 0; i != NumElts; ++i) { 3928 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3929 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3930 isIdentity = false; 3931 break; 3932 } 3933 } 3934 if (isIdentity) return N->getOperand(1); 3935 3936 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3937 // needed at all. 3938 bool isUnary = true; 3939 bool isSplat = true; 3940 int VecNum = -1; 3941 unsigned BaseIdx = 0; 3942 for (unsigned i = 0; i != NumElts; ++i) 3943 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3944 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3945 int V = (Idx < NumElts) ? 0 : 1; 3946 if (VecNum == -1) { 3947 VecNum = V; 3948 BaseIdx = Idx; 3949 } else { 3950 if (BaseIdx != Idx) 3951 isSplat = false; 3952 if (VecNum != V) { 3953 isUnary = false; 3954 break; 3955 } 3956 } 3957 } 3958 3959 SDOperand N0 = N->getOperand(0); 3960 SDOperand N1 = N->getOperand(1); 3961 // Normalize unary shuffle so the RHS is undef. 3962 if (isUnary && VecNum == 1) 3963 std::swap(N0, N1); 3964 3965 // If it is a splat, check if the argument vector is a build_vector with 3966 // all scalar elements the same. 3967 if (isSplat) { 3968 SDNode *V = N0.Val; 3969 3970 // If this is a vbit convert that changes the element type of the vector but 3971 // not the number of vector elements, look through it. Be careful not to 3972 // look though conversions that change things like v4f32 to v2f64. 3973 if (V->getOpcode() == ISD::VBIT_CONVERT) { 3974 SDOperand ConvInput = V->getOperand(0); 3975 if (ConvInput.getValueType() == MVT::Vector && 3976 NumElts == 3977 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2)) 3978 V = ConvInput.Val; 3979 } 3980 3981 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 3982 unsigned NumElems = V->getNumOperands()-2; 3983 if (NumElems > BaseIdx) { 3984 SDOperand Base; 3985 bool AllSame = true; 3986 for (unsigned i = 0; i != NumElems; ++i) { 3987 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3988 Base = V->getOperand(i); 3989 break; 3990 } 3991 } 3992 // Splat of <u, u, u, u>, return <u, u, u, u> 3993 if (!Base.Val) 3994 return N0; 3995 for (unsigned i = 0; i != NumElems; ++i) { 3996 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3997 V->getOperand(i) != Base) { 3998 AllSame = false; 3999 break; 4000 } 4001 } 4002 // Splat of <x, x, x, x>, return <x, x, x, x> 4003 if (AllSame) 4004 return N0; 4005 } 4006 } 4007 } 4008 4009 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4010 // into an undef. 4011 if (isUnary || N0 == N1) { 4012 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4013 // first operand. 4014 SmallVector<SDOperand, 8> MappedOps; 4015 for (unsigned i = 0; i != NumElts; ++i) { 4016 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4017 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4018 MappedOps.push_back(ShufMask.getOperand(i)); 4019 } else { 4020 unsigned NewIdx = 4021 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4022 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4023 } 4024 } 4025 // Add the type/#elts values. 4026 MappedOps.push_back(ShufMask.getOperand(NumElts)); 4027 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 4028 4029 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 4030 &MappedOps[0], MappedOps.size()); 4031 AddToWorkList(ShufMask.Val); 4032 4033 // Build the undef vector. 4034 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 4035 for (unsigned i = 0; i != NumElts; ++i) 4036 MappedOps[i] = UDVal; 4037 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 4038 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 4039 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 4040 &MappedOps[0], MappedOps.size()); 4041 4042 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 4043 N0, UDVal, ShufMask, 4044 MappedOps[NumElts], MappedOps[NumElts+1]); 4045 } 4046 4047 return SDOperand(); 4048} 4049 4050/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4051/// a VAND to a vector_shuffle with the destination vector and a zero vector. 4052/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4053/// vector_shuffle V, Zero, <0, 4, 2, 4> 4054SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4055 SDOperand LHS = N->getOperand(0); 4056 SDOperand RHS = N->getOperand(1); 4057 if (N->getOpcode() == ISD::VAND) { 4058 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 4059 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 4060 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 4061 RHS = RHS.getOperand(0); 4062 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 4063 std::vector<SDOperand> IdxOps; 4064 unsigned NumOps = RHS.getNumOperands(); 4065 unsigned NumElts = NumOps-2; 4066 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 4067 for (unsigned i = 0; i != NumElts; ++i) { 4068 SDOperand Elt = RHS.getOperand(i); 4069 if (!isa<ConstantSDNode>(Elt)) 4070 return SDOperand(); 4071 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4072 IdxOps.push_back(DAG.getConstant(i, EVT)); 4073 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4074 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4075 else 4076 return SDOperand(); 4077 } 4078 4079 // Let's see if the target supports this vector_shuffle. 4080 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4081 return SDOperand(); 4082 4083 // Return the new VVECTOR_SHUFFLE node. 4084 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 4085 SDOperand EVTNode = DAG.getValueType(EVT); 4086 std::vector<SDOperand> Ops; 4087 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, 4088 EVTNode); 4089 Ops.push_back(LHS); 4090 AddToWorkList(LHS.Val); 4091 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4092 ZeroOps.push_back(NumEltsNode); 4093 ZeroOps.push_back(EVTNode); 4094 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 4095 &ZeroOps[0], ZeroOps.size())); 4096 IdxOps.push_back(NumEltsNode); 4097 IdxOps.push_back(EVTNode); 4098 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 4099 &IdxOps[0], IdxOps.size())); 4100 Ops.push_back(NumEltsNode); 4101 Ops.push_back(EVTNode); 4102 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 4103 &Ops[0], Ops.size()); 4104 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 4105 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 4106 DstVecSize, DstVecEVT); 4107 } 4108 return Result; 4109 } 4110 } 4111 return SDOperand(); 4112} 4113 4114/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 4115/// the scalar operation of the vop if it is operating on an integer vector 4116/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 4117SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 4118 ISD::NodeType FPOp) { 4119 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 4120 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 4121 SDOperand LHS = N->getOperand(0); 4122 SDOperand RHS = N->getOperand(1); 4123 SDOperand Shuffle = XformToShuffleWithZero(N); 4124 if (Shuffle.Val) return Shuffle; 4125 4126 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 4127 // this operation. 4128 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 4129 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 4130 SmallVector<SDOperand, 8> Ops; 4131 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 4132 SDOperand LHSOp = LHS.getOperand(i); 4133 SDOperand RHSOp = RHS.getOperand(i); 4134 // If these two elements can't be folded, bail out. 4135 if ((LHSOp.getOpcode() != ISD::UNDEF && 4136 LHSOp.getOpcode() != ISD::Constant && 4137 LHSOp.getOpcode() != ISD::ConstantFP) || 4138 (RHSOp.getOpcode() != ISD::UNDEF && 4139 RHSOp.getOpcode() != ISD::Constant && 4140 RHSOp.getOpcode() != ISD::ConstantFP)) 4141 break; 4142 // Can't fold divide by zero. 4143 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 4144 if ((RHSOp.getOpcode() == ISD::Constant && 4145 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4146 (RHSOp.getOpcode() == ISD::ConstantFP && 4147 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 4148 break; 4149 } 4150 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 4151 AddToWorkList(Ops.back().Val); 4152 assert((Ops.back().getOpcode() == ISD::UNDEF || 4153 Ops.back().getOpcode() == ISD::Constant || 4154 Ops.back().getOpcode() == ISD::ConstantFP) && 4155 "Scalar binop didn't fold!"); 4156 } 4157 4158 if (Ops.size() == LHS.getNumOperands()-2) { 4159 Ops.push_back(*(LHS.Val->op_end()-2)); 4160 Ops.push_back(*(LHS.Val->op_end()-1)); 4161 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 4162 } 4163 } 4164 4165 return SDOperand(); 4166} 4167 4168SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4169 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4170 4171 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4172 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4173 // If we got a simplified select_cc node back from SimplifySelectCC, then 4174 // break it down into a new SETCC node, and a new SELECT node, and then return 4175 // the SELECT node, since we were called with a SELECT node. 4176 if (SCC.Val) { 4177 // Check to see if we got a select_cc back (to turn into setcc/select). 4178 // Otherwise, just return whatever node we got back, like fabs. 4179 if (SCC.getOpcode() == ISD::SELECT_CC) { 4180 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4181 SCC.getOperand(0), SCC.getOperand(1), 4182 SCC.getOperand(4)); 4183 AddToWorkList(SETCC.Val); 4184 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4185 SCC.getOperand(3), SETCC); 4186 } 4187 return SCC; 4188 } 4189 return SDOperand(); 4190} 4191 4192/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4193/// are the two values being selected between, see if we can simplify the 4194/// select. Callers of this should assume that TheSelect is deleted if this 4195/// returns true. As such, they should return the appropriate thing (e.g. the 4196/// node) back to the top-level of the DAG combiner loop to avoid it being 4197/// looked at. 4198/// 4199bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4200 SDOperand RHS) { 4201 4202 // If this is a select from two identical things, try to pull the operation 4203 // through the select. 4204 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4205 // If this is a load and the token chain is identical, replace the select 4206 // of two loads with a load through a select of the address to load from. 4207 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4208 // constants have been dropped into the constant pool. 4209 if (LHS.getOpcode() == ISD::LOAD && 4210 // Token chains must be identical. 4211 LHS.getOperand(0) == RHS.getOperand(0)) { 4212 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4213 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4214 4215 // If this is an EXTLOAD, the VT's must match. 4216 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4217 // FIXME: this conflates two src values, discarding one. This is not 4218 // the right thing to do, but nothing uses srcvalues now. When they do, 4219 // turn SrcValue into a list of locations. 4220 SDOperand Addr; 4221 if (TheSelect->getOpcode() == ISD::SELECT) { 4222 // Check that the condition doesn't reach either load. If so, folding 4223 // this will induce a cycle into the DAG. 4224 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4225 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4226 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4227 TheSelect->getOperand(0), LLD->getBasePtr(), 4228 RLD->getBasePtr()); 4229 } 4230 } else { 4231 // Check that the condition doesn't reach either load. If so, folding 4232 // this will induce a cycle into the DAG. 4233 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4234 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4235 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4236 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4237 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4238 TheSelect->getOperand(0), 4239 TheSelect->getOperand(1), 4240 LLD->getBasePtr(), RLD->getBasePtr(), 4241 TheSelect->getOperand(4)); 4242 } 4243 } 4244 4245 if (Addr.Val) { 4246 SDOperand Load; 4247 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4248 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4249 Addr,LLD->getSrcValue(), 4250 LLD->getSrcValueOffset(), 4251 LLD->isVolatile(), 4252 LLD->getAlignment()); 4253 else { 4254 Load = DAG.getExtLoad(LLD->getExtensionType(), 4255 TheSelect->getValueType(0), 4256 LLD->getChain(), Addr, LLD->getSrcValue(), 4257 LLD->getSrcValueOffset(), 4258 LLD->getLoadedVT(), 4259 LLD->isVolatile(), 4260 LLD->getAlignment()); 4261 } 4262 // Users of the select now use the result of the load. 4263 CombineTo(TheSelect, Load); 4264 4265 // Users of the old loads now use the new load's chain. We know the 4266 // old-load value is dead now. 4267 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4268 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4269 return true; 4270 } 4271 } 4272 } 4273 } 4274 4275 return false; 4276} 4277 4278SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4279 SDOperand N2, SDOperand N3, 4280 ISD::CondCode CC, bool NotExtCompare) { 4281 4282 MVT::ValueType VT = N2.getValueType(); 4283 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4284 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4285 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4286 4287 // Determine if the condition we're dealing with is constant 4288 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4289 if (SCC.Val) AddToWorkList(SCC.Val); 4290 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4291 4292 // fold select_cc true, x, y -> x 4293 if (SCCC && SCCC->getValue()) 4294 return N2; 4295 // fold select_cc false, x, y -> y 4296 if (SCCC && SCCC->getValue() == 0) 4297 return N3; 4298 4299 // Check to see if we can simplify the select into an fabs node 4300 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4301 // Allow either -0.0 or 0.0 4302 if (CFP->getValue() == 0.0) { 4303 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4304 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4305 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4306 N2 == N3.getOperand(0)) 4307 return DAG.getNode(ISD::FABS, VT, N0); 4308 4309 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4310 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4311 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4312 N2.getOperand(0) == N3) 4313 return DAG.getNode(ISD::FABS, VT, N3); 4314 } 4315 } 4316 4317 // Check to see if we can perform the "gzip trick", transforming 4318 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4319 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4320 MVT::isInteger(N0.getValueType()) && 4321 MVT::isInteger(N2.getValueType()) && 4322 (N1C->isNullValue() || // (a < 0) ? b : 0 4323 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4324 MVT::ValueType XType = N0.getValueType(); 4325 MVT::ValueType AType = N2.getValueType(); 4326 if (XType >= AType) { 4327 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4328 // single-bit constant. 4329 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4330 unsigned ShCtV = Log2_64(N2C->getValue()); 4331 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4332 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4333 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4334 AddToWorkList(Shift.Val); 4335 if (XType > AType) { 4336 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4337 AddToWorkList(Shift.Val); 4338 } 4339 return DAG.getNode(ISD::AND, AType, Shift, N2); 4340 } 4341 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4342 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4343 TLI.getShiftAmountTy())); 4344 AddToWorkList(Shift.Val); 4345 if (XType > AType) { 4346 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4347 AddToWorkList(Shift.Val); 4348 } 4349 return DAG.getNode(ISD::AND, AType, Shift, N2); 4350 } 4351 } 4352 4353 // fold select C, 16, 0 -> shl C, 4 4354 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4355 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4356 4357 // If the caller doesn't want us to simplify this into a zext of a compare, 4358 // don't do it. 4359 if (NotExtCompare && N2C->getValue() == 1) 4360 return SDOperand(); 4361 4362 // Get a SetCC of the condition 4363 // FIXME: Should probably make sure that setcc is legal if we ever have a 4364 // target where it isn't. 4365 SDOperand Temp, SCC; 4366 // cast from setcc result type to select result type 4367 if (AfterLegalize) { 4368 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4369 if (N2.getValueType() < SCC.getValueType()) 4370 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4371 else 4372 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4373 } else { 4374 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4375 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4376 } 4377 AddToWorkList(SCC.Val); 4378 AddToWorkList(Temp.Val); 4379 4380 if (N2C->getValue() == 1) 4381 return Temp; 4382 // shl setcc result by log2 n2c 4383 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4384 DAG.getConstant(Log2_64(N2C->getValue()), 4385 TLI.getShiftAmountTy())); 4386 } 4387 4388 // Check to see if this is the equivalent of setcc 4389 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4390 // otherwise, go ahead with the folds. 4391 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4392 MVT::ValueType XType = N0.getValueType(); 4393 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4394 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4395 if (Res.getValueType() != VT) 4396 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4397 return Res; 4398 } 4399 4400 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4401 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4402 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4403 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4404 return DAG.getNode(ISD::SRL, XType, Ctlz, 4405 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4406 TLI.getShiftAmountTy())); 4407 } 4408 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4409 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4410 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4411 N0); 4412 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4413 DAG.getConstant(~0ULL, XType)); 4414 return DAG.getNode(ISD::SRL, XType, 4415 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4416 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4417 TLI.getShiftAmountTy())); 4418 } 4419 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4420 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4421 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4422 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4423 TLI.getShiftAmountTy())); 4424 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4425 } 4426 } 4427 4428 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4429 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4430 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4431 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4432 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4433 MVT::ValueType XType = N0.getValueType(); 4434 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4435 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4436 TLI.getShiftAmountTy())); 4437 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4438 AddToWorkList(Shift.Val); 4439 AddToWorkList(Add.Val); 4440 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4441 } 4442 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4443 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4444 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4445 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4446 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4447 MVT::ValueType XType = N0.getValueType(); 4448 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4449 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4450 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4451 TLI.getShiftAmountTy())); 4452 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4453 AddToWorkList(Shift.Val); 4454 AddToWorkList(Add.Val); 4455 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4456 } 4457 } 4458 } 4459 4460 return SDOperand(); 4461} 4462 4463/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4464SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4465 SDOperand N1, ISD::CondCode Cond, 4466 bool foldBooleans) { 4467 TargetLowering::DAGCombinerInfo 4468 DagCombineInfo(DAG, !AfterLegalize, false, this); 4469 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4470} 4471 4472/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4473/// return a DAG expression to select that will generate the same value by 4474/// multiplying by a magic number. See: 4475/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4476SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4477 std::vector<SDNode*> Built; 4478 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4479 4480 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4481 ii != ee; ++ii) 4482 AddToWorkList(*ii); 4483 return S; 4484} 4485 4486/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4487/// return a DAG expression to select that will generate the same value by 4488/// multiplying by a magic number. See: 4489/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4490SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4491 std::vector<SDNode*> Built; 4492 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4493 4494 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4495 ii != ee; ++ii) 4496 AddToWorkList(*ii); 4497 return S; 4498} 4499 4500/// FindBaseOffset - Return true if base is known not to alias with anything 4501/// but itself. Provides base object and offset as results. 4502static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4503 // Assume it is a primitive operation. 4504 Base = Ptr; Offset = 0; 4505 4506 // If it's an adding a simple constant then integrate the offset. 4507 if (Base.getOpcode() == ISD::ADD) { 4508 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4509 Base = Base.getOperand(0); 4510 Offset += C->getValue(); 4511 } 4512 } 4513 4514 // If it's any of the following then it can't alias with anything but itself. 4515 return isa<FrameIndexSDNode>(Base) || 4516 isa<ConstantPoolSDNode>(Base) || 4517 isa<GlobalAddressSDNode>(Base); 4518} 4519 4520/// isAlias - Return true if there is any possibility that the two addresses 4521/// overlap. 4522bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4523 const Value *SrcValue1, int SrcValueOffset1, 4524 SDOperand Ptr2, int64_t Size2, 4525 const Value *SrcValue2, int SrcValueOffset2) 4526{ 4527 // If they are the same then they must be aliases. 4528 if (Ptr1 == Ptr2) return true; 4529 4530 // Gather base node and offset information. 4531 SDOperand Base1, Base2; 4532 int64_t Offset1, Offset2; 4533 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4534 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4535 4536 // If they have a same base address then... 4537 if (Base1 == Base2) { 4538 // Check to see if the addresses overlap. 4539 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4540 } 4541 4542 // If we know both bases then they can't alias. 4543 if (KnownBase1 && KnownBase2) return false; 4544 4545 if (CombinerGlobalAA) { 4546 // Use alias analysis information. 4547 int Overlap1 = Size1 + SrcValueOffset1 + Offset1; 4548 int Overlap2 = Size2 + SrcValueOffset2 + Offset2; 4549 AliasAnalysis::AliasResult AAResult = 4550 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4551 if (AAResult == AliasAnalysis::NoAlias) 4552 return false; 4553 } 4554 4555 // Otherwise we have to assume they alias. 4556 return true; 4557} 4558 4559/// FindAliasInfo - Extracts the relevant alias information from the memory 4560/// node. Returns true if the operand was a load. 4561bool DAGCombiner::FindAliasInfo(SDNode *N, 4562 SDOperand &Ptr, int64_t &Size, 4563 const Value *&SrcValue, int &SrcValueOffset) { 4564 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4565 Ptr = LD->getBasePtr(); 4566 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4567 SrcValue = LD->getSrcValue(); 4568 SrcValueOffset = LD->getSrcValueOffset(); 4569 return true; 4570 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4571 Ptr = ST->getBasePtr(); 4572 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4573 SrcValue = ST->getSrcValue(); 4574 SrcValueOffset = ST->getSrcValueOffset(); 4575 } else { 4576 assert(0 && "FindAliasInfo expected a memory operand"); 4577 } 4578 4579 return false; 4580} 4581 4582/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4583/// looking for aliasing nodes and adding them to the Aliases vector. 4584void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4585 SmallVector<SDOperand, 8> &Aliases) { 4586 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4587 std::set<SDNode *> Visited; // Visited node set. 4588 4589 // Get alias information for node. 4590 SDOperand Ptr; 4591 int64_t Size; 4592 const Value *SrcValue; 4593 int SrcValueOffset; 4594 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4595 4596 // Starting off. 4597 Chains.push_back(OriginalChain); 4598 4599 // Look at each chain and determine if it is an alias. If so, add it to the 4600 // aliases list. If not, then continue up the chain looking for the next 4601 // candidate. 4602 while (!Chains.empty()) { 4603 SDOperand Chain = Chains.back(); 4604 Chains.pop_back(); 4605 4606 // Don't bother if we've been before. 4607 if (Visited.find(Chain.Val) != Visited.end()) continue; 4608 Visited.insert(Chain.Val); 4609 4610 switch (Chain.getOpcode()) { 4611 case ISD::EntryToken: 4612 // Entry token is ideal chain operand, but handled in FindBetterChain. 4613 break; 4614 4615 case ISD::LOAD: 4616 case ISD::STORE: { 4617 // Get alias information for Chain. 4618 SDOperand OpPtr; 4619 int64_t OpSize; 4620 const Value *OpSrcValue; 4621 int OpSrcValueOffset; 4622 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4623 OpSrcValue, OpSrcValueOffset); 4624 4625 // If chain is alias then stop here. 4626 if (!(IsLoad && IsOpLoad) && 4627 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4628 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4629 Aliases.push_back(Chain); 4630 } else { 4631 // Look further up the chain. 4632 Chains.push_back(Chain.getOperand(0)); 4633 // Clean up old chain. 4634 AddToWorkList(Chain.Val); 4635 } 4636 break; 4637 } 4638 4639 case ISD::TokenFactor: 4640 // We have to check each of the operands of the token factor, so we queue 4641 // then up. Adding the operands to the queue (stack) in reverse order 4642 // maintains the original order and increases the likelihood that getNode 4643 // will find a matching token factor (CSE.) 4644 for (unsigned n = Chain.getNumOperands(); n;) 4645 Chains.push_back(Chain.getOperand(--n)); 4646 // Eliminate the token factor if we can. 4647 AddToWorkList(Chain.Val); 4648 break; 4649 4650 default: 4651 // For all other instructions we will just have to take what we can get. 4652 Aliases.push_back(Chain); 4653 break; 4654 } 4655 } 4656} 4657 4658/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4659/// for a better chain (aliasing node.) 4660SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4661 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4662 4663 // Accumulate all the aliases to this node. 4664 GatherAllAliases(N, OldChain, Aliases); 4665 4666 if (Aliases.size() == 0) { 4667 // If no operands then chain to entry token. 4668 return DAG.getEntryNode(); 4669 } else if (Aliases.size() == 1) { 4670 // If a single operand then chain to it. We don't need to revisit it. 4671 return Aliases[0]; 4672 } 4673 4674 // Construct a custom tailored token factor. 4675 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4676 &Aliases[0], Aliases.size()); 4677 4678 // Make sure the old chain gets cleaned up. 4679 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4680 4681 return NewChain; 4682} 4683 4684// SelectionDAG::Combine - This is the entry point for the file. 4685// 4686void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4687 if (!RunningAfterLegalize && ViewDAGCombine1) 4688 viewGraph(); 4689 if (RunningAfterLegalize && ViewDAGCombine2) 4690 viewGraph(); 4691 /// run - This is the main entry point to this class. 4692 /// 4693 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 4694} 4695