DAGCombiner.cpp revision 503a64dcd47e6ed9216a75ac68299a2f081b313c
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 /// combine - call the node-specific routine that knows how to fold each 142 /// particular type of node. If that doesn't do anything, try the 143 /// target-specific DAG combines. 144 SDValue combine(SDNode *N); 145 146 // Visitation implementation - Implement dag node combining for different 147 // node types. The semantics are as follows: 148 // Return Value: 149 // SDValue.getNode() == 0 - No change was made 150 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151 // otherwise - N should be replaced by the returned Operand. 152 // 153 SDValue visitTokenFactor(SDNode *N); 154 SDValue visitMERGE_VALUES(SDNode *N); 155 SDValue visitADD(SDNode *N); 156 SDValue visitSUB(SDNode *N); 157 SDValue visitADDC(SDNode *N); 158 SDValue visitADDE(SDNode *N); 159 SDValue visitMUL(SDNode *N); 160 SDValue visitSDIV(SDNode *N); 161 SDValue visitUDIV(SDNode *N); 162 SDValue visitSREM(SDNode *N); 163 SDValue visitUREM(SDNode *N); 164 SDValue visitMULHU(SDNode *N); 165 SDValue visitMULHS(SDNode *N); 166 SDValue visitSMUL_LOHI(SDNode *N); 167 SDValue visitUMUL_LOHI(SDNode *N); 168 SDValue visitSDIVREM(SDNode *N); 169 SDValue visitUDIVREM(SDNode *N); 170 SDValue visitAND(SDNode *N); 171 SDValue visitOR(SDNode *N); 172 SDValue visitXOR(SDNode *N); 173 SDValue SimplifyVBinOp(SDNode *N); 174 SDValue visitSHL(SDNode *N); 175 SDValue visitSRA(SDNode *N); 176 SDValue visitSRL(SDNode *N); 177 SDValue visitCTLZ(SDNode *N); 178 SDValue visitCTTZ(SDNode *N); 179 SDValue visitCTPOP(SDNode *N); 180 SDValue visitSELECT(SDNode *N); 181 SDValue visitSELECT_CC(SDNode *N); 182 SDValue visitSETCC(SDNode *N); 183 SDValue visitSIGN_EXTEND(SDNode *N); 184 SDValue visitZERO_EXTEND(SDNode *N); 185 SDValue visitANY_EXTEND(SDNode *N); 186 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 187 SDValue visitTRUNCATE(SDNode *N); 188 SDValue visitBITCAST(SDNode *N); 189 SDValue visitBUILD_PAIR(SDNode *N); 190 SDValue visitFADD(SDNode *N); 191 SDValue visitFSUB(SDNode *N); 192 SDValue visitFMUL(SDNode *N); 193 SDValue visitFDIV(SDNode *N); 194 SDValue visitFREM(SDNode *N); 195 SDValue visitFCOPYSIGN(SDNode *N); 196 SDValue visitSINT_TO_FP(SDNode *N); 197 SDValue visitUINT_TO_FP(SDNode *N); 198 SDValue visitFP_TO_SINT(SDNode *N); 199 SDValue visitFP_TO_UINT(SDNode *N); 200 SDValue visitFP_ROUND(SDNode *N); 201 SDValue visitFP_ROUND_INREG(SDNode *N); 202 SDValue visitFP_EXTEND(SDNode *N); 203 SDValue visitFNEG(SDNode *N); 204 SDValue visitFABS(SDNode *N); 205 SDValue visitBRCOND(SDNode *N); 206 SDValue visitBR_CC(SDNode *N); 207 SDValue visitLOAD(SDNode *N); 208 SDValue visitSTORE(SDNode *N); 209 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 211 SDValue visitBUILD_VECTOR(SDNode *N); 212 SDValue visitCONCAT_VECTORS(SDNode *N); 213 SDValue visitVECTOR_SHUFFLE(SDNode *N); 214 SDValue visitMEMBARRIER(SDNode *N); 215 216 SDValue XformToShuffleWithZero(SDNode *N); 217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 218 219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 220 221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 225 SDValue N3, ISD::CondCode CC, 226 bool NotExtCompare = false); 227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 228 DebugLoc DL, bool foldBooleans = true); 229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 230 unsigned HiOp); 231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 232 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 233 SDValue BuildSDIV(SDNode *N); 234 SDValue BuildUDIV(SDNode *N); 235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 236 SDValue ReduceLoadWidth(SDNode *N); 237 SDValue ReduceLoadOpStoreWidth(SDNode *N); 238 239 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 240 241 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 242 /// looking for aliasing nodes and adding them to the Aliases vector. 243 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 244 SmallVector<SDValue, 8> &Aliases); 245 246 /// isAlias - Return true if there is any possibility that the two addresses 247 /// overlap. 248 bool isAlias(SDValue Ptr1, int64_t Size1, 249 const Value *SrcValue1, int SrcValueOffset1, 250 unsigned SrcValueAlign1, 251 const MDNode *TBAAInfo1, 252 SDValue Ptr2, int64_t Size2, 253 const Value *SrcValue2, int SrcValueOffset2, 254 unsigned SrcValueAlign2, 255 const MDNode *TBAAInfo2) const; 256 257 /// FindAliasInfo - Extracts the relevant alias information from the memory 258 /// node. Returns true if the operand was a load. 259 bool FindAliasInfo(SDNode *N, 260 SDValue &Ptr, int64_t &Size, 261 const Value *&SrcValue, int &SrcValueOffset, 262 unsigned &SrcValueAlignment, 263 const MDNode *&TBAAInfo) const; 264 265 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 266 /// looking for a better chain (aliasing node.) 267 SDValue FindBetterChain(SDNode *N, SDValue Chain); 268 269 public: 270 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 271 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 272 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 273 274 /// Run - runs the dag combiner on all nodes in the work list 275 void Run(CombineLevel AtLevel); 276 277 SelectionDAG &getDAG() const { return DAG; } 278 279 /// getShiftAmountTy - Returns a type large enough to hold any valid 280 /// shift amount - before type legalization these can be huge. 281 EVT getShiftAmountTy() { 282 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 283 } 284 285 /// isTypeLegal - This method returns true if we are running before type 286 /// legalization or if the specified VT is legal. 287 bool isTypeLegal(const EVT &VT) { 288 if (!LegalTypes) return true; 289 return TLI.isTypeLegal(VT); 290 } 291 }; 292} 293 294 295namespace { 296/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 297/// nodes from the worklist. 298class WorkListRemover : public SelectionDAG::DAGUpdateListener { 299 DAGCombiner &DC; 300public: 301 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 302 303 virtual void NodeDeleted(SDNode *N, SDNode *E) { 304 DC.removeFromWorkList(N); 305 } 306 307 virtual void NodeUpdated(SDNode *N) { 308 // Ignore updates. 309 } 310}; 311} 312 313//===----------------------------------------------------------------------===// 314// TargetLowering::DAGCombinerInfo implementation 315//===----------------------------------------------------------------------===// 316 317void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 318 ((DAGCombiner*)DC)->AddToWorkList(N); 319} 320 321SDValue TargetLowering::DAGCombinerInfo:: 322CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 323 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 324} 325 326SDValue TargetLowering::DAGCombinerInfo:: 327CombineTo(SDNode *N, SDValue Res, bool AddTo) { 328 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 329} 330 331 332SDValue TargetLowering::DAGCombinerInfo:: 333CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 334 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 335} 336 337void TargetLowering::DAGCombinerInfo:: 338CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 339 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 340} 341 342//===----------------------------------------------------------------------===// 343// Helper Functions 344//===----------------------------------------------------------------------===// 345 346/// isNegatibleForFree - Return 1 if we can compute the negated form of the 347/// specified expression for the same cost as the expression itself, or 2 if we 348/// can compute the negated form more cheaply than the expression itself. 349static char isNegatibleForFree(SDValue Op, bool LegalOperations, 350 unsigned Depth = 0) { 351 // No compile time optimizations on this type. 352 if (Op.getValueType() == MVT::ppcf128) 353 return 0; 354 355 // fneg is removable even if it has multiple uses. 356 if (Op.getOpcode() == ISD::FNEG) return 2; 357 358 // Don't allow anything with multiple uses. 359 if (!Op.hasOneUse()) return 0; 360 361 // Don't recurse exponentially. 362 if (Depth > 6) return 0; 363 364 switch (Op.getOpcode()) { 365 default: return false; 366 case ISD::ConstantFP: 367 // Don't invert constant FP values after legalize. The negated constant 368 // isn't necessarily legal. 369 return LegalOperations ? 0 : 1; 370 case ISD::FADD: 371 // FIXME: determine better conditions for this xform. 372 if (!UnsafeFPMath) return 0; 373 374 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 376 return V; 377 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 379 case ISD::FSUB: 380 // We can't turn -(A-B) into B-A when we honor signed zeros. 381 if (!UnsafeFPMath) return 0; 382 383 // fold (fneg (fsub A, B)) -> (fsub B, A) 384 return 1; 385 386 case ISD::FMUL: 387 case ISD::FDIV: 388 if (HonorSignDependentRoundingFPMath()) return 0; 389 390 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 391 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 392 return V; 393 394 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 395 396 case ISD::FP_EXTEND: 397 case ISD::FP_ROUND: 398 case ISD::FSIN: 399 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 400 } 401} 402 403/// GetNegatedExpression - If isNegatibleForFree returns true, this function 404/// returns the newly negated expression. 405static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 406 bool LegalOperations, unsigned Depth = 0) { 407 // fneg is removable even if it has multiple uses. 408 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 409 410 // Don't allow anything with multiple uses. 411 assert(Op.hasOneUse() && "Unknown reuse!"); 412 413 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 414 switch (Op.getOpcode()) { 415 default: llvm_unreachable("Unknown code"); 416 case ISD::ConstantFP: { 417 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 418 V.changeSign(); 419 return DAG.getConstantFP(V, Op.getValueType()); 420 } 421 case ISD::FADD: 422 // FIXME: determine better conditions for this xform. 423 assert(UnsafeFPMath); 424 425 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 426 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 427 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 428 GetNegatedExpression(Op.getOperand(0), DAG, 429 LegalOperations, Depth+1), 430 Op.getOperand(1)); 431 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 432 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 433 GetNegatedExpression(Op.getOperand(1), DAG, 434 LegalOperations, Depth+1), 435 Op.getOperand(0)); 436 case ISD::FSUB: 437 // We can't turn -(A-B) into B-A when we honor signed zeros. 438 assert(UnsafeFPMath); 439 440 // fold (fneg (fsub 0, B)) -> B 441 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 442 if (N0CFP->getValueAPF().isZero()) 443 return Op.getOperand(1); 444 445 // fold (fneg (fsub A, B)) -> (fsub B, A) 446 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 447 Op.getOperand(1), Op.getOperand(0)); 448 449 case ISD::FMUL: 450 case ISD::FDIV: 451 assert(!HonorSignDependentRoundingFPMath()); 452 453 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 454 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 455 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 456 GetNegatedExpression(Op.getOperand(0), DAG, 457 LegalOperations, Depth+1), 458 Op.getOperand(1)); 459 460 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 461 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 462 Op.getOperand(0), 463 GetNegatedExpression(Op.getOperand(1), DAG, 464 LegalOperations, Depth+1)); 465 466 case ISD::FP_EXTEND: 467 case ISD::FSIN: 468 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 469 GetNegatedExpression(Op.getOperand(0), DAG, 470 LegalOperations, Depth+1)); 471 case ISD::FP_ROUND: 472 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 473 GetNegatedExpression(Op.getOperand(0), DAG, 474 LegalOperations, Depth+1), 475 Op.getOperand(1)); 476 } 477} 478 479 480// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 481// that selects between the values 1 and 0, making it equivalent to a setcc. 482// Also, set the incoming LHS, RHS, and CC references to the appropriate 483// nodes based on the type of node we are checking. This simplifies life a 484// bit for the callers. 485static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 486 SDValue &CC) { 487 if (N.getOpcode() == ISD::SETCC) { 488 LHS = N.getOperand(0); 489 RHS = N.getOperand(1); 490 CC = N.getOperand(2); 491 return true; 492 } 493 if (N.getOpcode() == ISD::SELECT_CC && 494 N.getOperand(2).getOpcode() == ISD::Constant && 495 N.getOperand(3).getOpcode() == ISD::Constant && 496 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 497 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 498 LHS = N.getOperand(0); 499 RHS = N.getOperand(1); 500 CC = N.getOperand(4); 501 return true; 502 } 503 return false; 504} 505 506// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 507// one use. If this is true, it allows the users to invert the operation for 508// free when it is profitable to do so. 509static bool isOneUseSetCC(SDValue N) { 510 SDValue N0, N1, N2; 511 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 512 return true; 513 return false; 514} 515 516SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 517 SDValue N0, SDValue N1) { 518 EVT VT = N0.getValueType(); 519 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 520 if (isa<ConstantSDNode>(N1)) { 521 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 522 SDValue OpNode = 523 DAG.FoldConstantArithmetic(Opc, VT, 524 cast<ConstantSDNode>(N0.getOperand(1)), 525 cast<ConstantSDNode>(N1)); 526 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 527 } else if (N0.hasOneUse()) { 528 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 529 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 530 N0.getOperand(0), N1); 531 AddToWorkList(OpNode.getNode()); 532 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 533 } 534 } 535 536 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 537 if (isa<ConstantSDNode>(N0)) { 538 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 539 SDValue OpNode = 540 DAG.FoldConstantArithmetic(Opc, VT, 541 cast<ConstantSDNode>(N1.getOperand(1)), 542 cast<ConstantSDNode>(N0)); 543 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 544 } else if (N1.hasOneUse()) { 545 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 546 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 547 N1.getOperand(0), N0); 548 AddToWorkList(OpNode.getNode()); 549 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 550 } 551 } 552 553 return SDValue(); 554} 555 556SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 557 bool AddTo) { 558 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 559 ++NodesCombined; 560 DEBUG(dbgs() << "\nReplacing.1 "; 561 N->dump(&DAG); 562 dbgs() << "\nWith: "; 563 To[0].getNode()->dump(&DAG); 564 dbgs() << " and " << NumTo-1 << " other values\n"; 565 for (unsigned i = 0, e = NumTo; i != e; ++i) 566 assert((!To[i].getNode() || 567 N->getValueType(i) == To[i].getValueType()) && 568 "Cannot combine value to value of different type!")); 569 WorkListRemover DeadNodes(*this); 570 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 571 572 if (AddTo) { 573 // Push the new nodes and any users onto the worklist 574 for (unsigned i = 0, e = NumTo; i != e; ++i) { 575 if (To[i].getNode()) { 576 AddToWorkList(To[i].getNode()); 577 AddUsersToWorkList(To[i].getNode()); 578 } 579 } 580 } 581 582 // Finally, if the node is now dead, remove it from the graph. The node 583 // may not be dead if the replacement process recursively simplified to 584 // something else needing this node. 585 if (N->use_empty()) { 586 // Nodes can be reintroduced into the worklist. Make sure we do not 587 // process a node that has been replaced. 588 removeFromWorkList(N); 589 590 // Finally, since the node is now dead, remove it from the graph. 591 DAG.DeleteNode(N); 592 } 593 return SDValue(N, 0); 594} 595 596void DAGCombiner:: 597CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 598 // Replace all uses. If any nodes become isomorphic to other nodes and 599 // are deleted, make sure to remove them from our worklist. 600 WorkListRemover DeadNodes(*this); 601 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 602 603 // Push the new node and any (possibly new) users onto the worklist. 604 AddToWorkList(TLO.New.getNode()); 605 AddUsersToWorkList(TLO.New.getNode()); 606 607 // Finally, if the node is now dead, remove it from the graph. The node 608 // may not be dead if the replacement process recursively simplified to 609 // something else needing this node. 610 if (TLO.Old.getNode()->use_empty()) { 611 removeFromWorkList(TLO.Old.getNode()); 612 613 // If the operands of this node are only used by the node, they will now 614 // be dead. Make sure to visit them first to delete dead nodes early. 615 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 616 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 617 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 618 619 DAG.DeleteNode(TLO.Old.getNode()); 620 } 621} 622 623/// SimplifyDemandedBits - Check the specified integer node value to see if 624/// it can be simplified or if things it uses can be simplified by bit 625/// propagation. If so, return true. 626bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 627 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 628 APInt KnownZero, KnownOne; 629 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 630 return false; 631 632 // Revisit the node. 633 AddToWorkList(Op.getNode()); 634 635 // Replace the old value with the new one. 636 ++NodesCombined; 637 DEBUG(dbgs() << "\nReplacing.2 "; 638 TLO.Old.getNode()->dump(&DAG); 639 dbgs() << "\nWith: "; 640 TLO.New.getNode()->dump(&DAG); 641 dbgs() << '\n'); 642 643 CommitTargetLoweringOpt(TLO); 644 return true; 645} 646 647void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 648 DebugLoc dl = Load->getDebugLoc(); 649 EVT VT = Load->getValueType(0); 650 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 651 652 DEBUG(dbgs() << "\nReplacing.9 "; 653 Load->dump(&DAG); 654 dbgs() << "\nWith: "; 655 Trunc.getNode()->dump(&DAG); 656 dbgs() << '\n'); 657 WorkListRemover DeadNodes(*this); 658 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 659 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 660 &DeadNodes); 661 removeFromWorkList(Load); 662 DAG.DeleteNode(Load); 663 AddToWorkList(Trunc.getNode()); 664} 665 666SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 667 Replace = false; 668 DebugLoc dl = Op.getDebugLoc(); 669 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 670 EVT MemVT = LD->getMemoryVT(); 671 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 672 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 673 : ISD::EXTLOAD) 674 : LD->getExtensionType(); 675 Replace = true; 676 return DAG.getExtLoad(ExtType, PVT, dl, 677 LD->getChain(), LD->getBasePtr(), 678 LD->getPointerInfo(), 679 MemVT, LD->isVolatile(), 680 LD->isNonTemporal(), LD->getAlignment()); 681 } 682 683 unsigned Opc = Op.getOpcode(); 684 switch (Opc) { 685 default: break; 686 case ISD::AssertSext: 687 return DAG.getNode(ISD::AssertSext, dl, PVT, 688 SExtPromoteOperand(Op.getOperand(0), PVT), 689 Op.getOperand(1)); 690 case ISD::AssertZext: 691 return DAG.getNode(ISD::AssertZext, dl, PVT, 692 ZExtPromoteOperand(Op.getOperand(0), PVT), 693 Op.getOperand(1)); 694 case ISD::Constant: { 695 unsigned ExtOpc = 696 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 697 return DAG.getNode(ExtOpc, dl, PVT, Op); 698 } 699 } 700 701 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 702 return SDValue(); 703 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 704} 705 706SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 707 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 708 return SDValue(); 709 EVT OldVT = Op.getValueType(); 710 DebugLoc dl = Op.getDebugLoc(); 711 bool Replace = false; 712 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 713 if (NewOp.getNode() == 0) 714 return SDValue(); 715 AddToWorkList(NewOp.getNode()); 716 717 if (Replace) 718 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 719 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 720 DAG.getValueType(OldVT)); 721} 722 723SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 724 EVT OldVT = Op.getValueType(); 725 DebugLoc dl = Op.getDebugLoc(); 726 bool Replace = false; 727 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 728 if (NewOp.getNode() == 0) 729 return SDValue(); 730 AddToWorkList(NewOp.getNode()); 731 732 if (Replace) 733 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 734 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 735} 736 737/// PromoteIntBinOp - Promote the specified integer binary operation if the 738/// target indicates it is beneficial. e.g. On x86, it's usually better to 739/// promote i16 operations to i32 since i16 instructions are longer. 740SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 741 if (!LegalOperations) 742 return SDValue(); 743 744 EVT VT = Op.getValueType(); 745 if (VT.isVector() || !VT.isInteger()) 746 return SDValue(); 747 748 // If operation type is 'undesirable', e.g. i16 on x86, consider 749 // promoting it. 750 unsigned Opc = Op.getOpcode(); 751 if (TLI.isTypeDesirableForOp(Opc, VT)) 752 return SDValue(); 753 754 EVT PVT = VT; 755 // Consult target whether it is a good idea to promote this operation and 756 // what's the right type to promote it to. 757 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 758 assert(PVT != VT && "Don't know what type to promote to!"); 759 760 bool Replace0 = false; 761 SDValue N0 = Op.getOperand(0); 762 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 763 if (NN0.getNode() == 0) 764 return SDValue(); 765 766 bool Replace1 = false; 767 SDValue N1 = Op.getOperand(1); 768 SDValue NN1; 769 if (N0 == N1) 770 NN1 = NN0; 771 else { 772 NN1 = PromoteOperand(N1, PVT, Replace1); 773 if (NN1.getNode() == 0) 774 return SDValue(); 775 } 776 777 AddToWorkList(NN0.getNode()); 778 if (NN1.getNode()) 779 AddToWorkList(NN1.getNode()); 780 781 if (Replace0) 782 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 783 if (Replace1) 784 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 785 786 DEBUG(dbgs() << "\nPromoting "; 787 Op.getNode()->dump(&DAG)); 788 DebugLoc dl = Op.getDebugLoc(); 789 return DAG.getNode(ISD::TRUNCATE, dl, VT, 790 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 791 } 792 return SDValue(); 793} 794 795/// PromoteIntShiftOp - Promote the specified integer shift operation if the 796/// target indicates it is beneficial. e.g. On x86, it's usually better to 797/// promote i16 operations to i32 since i16 instructions are longer. 798SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 799 if (!LegalOperations) 800 return SDValue(); 801 802 EVT VT = Op.getValueType(); 803 if (VT.isVector() || !VT.isInteger()) 804 return SDValue(); 805 806 // If operation type is 'undesirable', e.g. i16 on x86, consider 807 // promoting it. 808 unsigned Opc = Op.getOpcode(); 809 if (TLI.isTypeDesirableForOp(Opc, VT)) 810 return SDValue(); 811 812 EVT PVT = VT; 813 // Consult target whether it is a good idea to promote this operation and 814 // what's the right type to promote it to. 815 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 816 assert(PVT != VT && "Don't know what type to promote to!"); 817 818 bool Replace = false; 819 SDValue N0 = Op.getOperand(0); 820 if (Opc == ISD::SRA) 821 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 822 else if (Opc == ISD::SRL) 823 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 824 else 825 N0 = PromoteOperand(N0, PVT, Replace); 826 if (N0.getNode() == 0) 827 return SDValue(); 828 829 AddToWorkList(N0.getNode()); 830 if (Replace) 831 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 832 833 DEBUG(dbgs() << "\nPromoting "; 834 Op.getNode()->dump(&DAG)); 835 DebugLoc dl = Op.getDebugLoc(); 836 return DAG.getNode(ISD::TRUNCATE, dl, VT, 837 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 838 } 839 return SDValue(); 840} 841 842SDValue DAGCombiner::PromoteExtend(SDValue Op) { 843 if (!LegalOperations) 844 return SDValue(); 845 846 EVT VT = Op.getValueType(); 847 if (VT.isVector() || !VT.isInteger()) 848 return SDValue(); 849 850 // If operation type is 'undesirable', e.g. i16 on x86, consider 851 // promoting it. 852 unsigned Opc = Op.getOpcode(); 853 if (TLI.isTypeDesirableForOp(Opc, VT)) 854 return SDValue(); 855 856 EVT PVT = VT; 857 // Consult target whether it is a good idea to promote this operation and 858 // what's the right type to promote it to. 859 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 860 assert(PVT != VT && "Don't know what type to promote to!"); 861 // fold (aext (aext x)) -> (aext x) 862 // fold (aext (zext x)) -> (zext x) 863 // fold (aext (sext x)) -> (sext x) 864 DEBUG(dbgs() << "\nPromoting "; 865 Op.getNode()->dump(&DAG)); 866 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 867 } 868 return SDValue(); 869} 870 871bool DAGCombiner::PromoteLoad(SDValue Op) { 872 if (!LegalOperations) 873 return false; 874 875 EVT VT = Op.getValueType(); 876 if (VT.isVector() || !VT.isInteger()) 877 return false; 878 879 // If operation type is 'undesirable', e.g. i16 on x86, consider 880 // promoting it. 881 unsigned Opc = Op.getOpcode(); 882 if (TLI.isTypeDesirableForOp(Opc, VT)) 883 return false; 884 885 EVT PVT = VT; 886 // Consult target whether it is a good idea to promote this operation and 887 // what's the right type to promote it to. 888 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 889 assert(PVT != VT && "Don't know what type to promote to!"); 890 891 DebugLoc dl = Op.getDebugLoc(); 892 SDNode *N = Op.getNode(); 893 LoadSDNode *LD = cast<LoadSDNode>(N); 894 EVT MemVT = LD->getMemoryVT(); 895 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 896 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 897 : ISD::EXTLOAD) 898 : LD->getExtensionType(); 899 SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl, 900 LD->getChain(), LD->getBasePtr(), 901 LD->getPointerInfo(), 902 MemVT, LD->isVolatile(), 903 LD->isNonTemporal(), LD->getAlignment()); 904 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 905 906 DEBUG(dbgs() << "\nPromoting "; 907 N->dump(&DAG); 908 dbgs() << "\nTo: "; 909 Result.getNode()->dump(&DAG); 910 dbgs() << '\n'); 911 WorkListRemover DeadNodes(*this); 912 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 913 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 914 removeFromWorkList(N); 915 DAG.DeleteNode(N); 916 AddToWorkList(Result.getNode()); 917 return true; 918 } 919 return false; 920} 921 922 923//===----------------------------------------------------------------------===// 924// Main DAG Combiner implementation 925//===----------------------------------------------------------------------===// 926 927void DAGCombiner::Run(CombineLevel AtLevel) { 928 // set the instance variables, so that the various visit routines may use it. 929 Level = AtLevel; 930 LegalOperations = Level >= NoIllegalOperations; 931 LegalTypes = Level >= NoIllegalTypes; 932 933 // Add all the dag nodes to the worklist. 934 WorkList.reserve(DAG.allnodes_size()); 935 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 936 E = DAG.allnodes_end(); I != E; ++I) 937 WorkList.push_back(I); 938 939 // Create a dummy node (which is not added to allnodes), that adds a reference 940 // to the root node, preventing it from being deleted, and tracking any 941 // changes of the root. 942 HandleSDNode Dummy(DAG.getRoot()); 943 944 // The root of the dag may dangle to deleted nodes until the dag combiner is 945 // done. Set it to null to avoid confusion. 946 DAG.setRoot(SDValue()); 947 948 // while the worklist isn't empty, inspect the node on the end of it and 949 // try and combine it. 950 while (!WorkList.empty()) { 951 SDNode *N = WorkList.back(); 952 WorkList.pop_back(); 953 954 // If N has no uses, it is dead. Make sure to revisit all N's operands once 955 // N is deleted from the DAG, since they too may now be dead or may have a 956 // reduced number of uses, allowing other xforms. 957 if (N->use_empty() && N != &Dummy) { 958 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 959 AddToWorkList(N->getOperand(i).getNode()); 960 961 DAG.DeleteNode(N); 962 continue; 963 } 964 965 SDValue RV = combine(N); 966 967 if (RV.getNode() == 0) 968 continue; 969 970 ++NodesCombined; 971 972 // If we get back the same node we passed in, rather than a new node or 973 // zero, we know that the node must have defined multiple values and 974 // CombineTo was used. Since CombineTo takes care of the worklist 975 // mechanics for us, we have no work to do in this case. 976 if (RV.getNode() == N) 977 continue; 978 979 assert(N->getOpcode() != ISD::DELETED_NODE && 980 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 981 "Node was deleted but visit returned new node!"); 982 983 DEBUG(dbgs() << "\nReplacing.3 "; 984 N->dump(&DAG); 985 dbgs() << "\nWith: "; 986 RV.getNode()->dump(&DAG); 987 dbgs() << '\n'); 988 WorkListRemover DeadNodes(*this); 989 if (N->getNumValues() == RV.getNode()->getNumValues()) 990 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 991 else { 992 assert(N->getValueType(0) == RV.getValueType() && 993 N->getNumValues() == 1 && "Type mismatch"); 994 SDValue OpV = RV; 995 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 996 } 997 998 // Push the new node and any users onto the worklist 999 AddToWorkList(RV.getNode()); 1000 AddUsersToWorkList(RV.getNode()); 1001 1002 // Add any uses of the old node to the worklist in case this node is the 1003 // last one that uses them. They may become dead after this node is 1004 // deleted. 1005 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1006 AddToWorkList(N->getOperand(i).getNode()); 1007 1008 // Finally, if the node is now dead, remove it from the graph. The node 1009 // may not be dead if the replacement process recursively simplified to 1010 // something else needing this node. 1011 if (N->use_empty()) { 1012 // Nodes can be reintroduced into the worklist. Make sure we do not 1013 // process a node that has been replaced. 1014 removeFromWorkList(N); 1015 1016 // Finally, since the node is now dead, remove it from the graph. 1017 DAG.DeleteNode(N); 1018 } 1019 } 1020 1021 // If the root changed (e.g. it was a dead load, update the root). 1022 DAG.setRoot(Dummy.getValue()); 1023} 1024 1025SDValue DAGCombiner::visit(SDNode *N) { 1026 switch (N->getOpcode()) { 1027 default: break; 1028 case ISD::TokenFactor: return visitTokenFactor(N); 1029 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1030 case ISD::ADD: return visitADD(N); 1031 case ISD::SUB: return visitSUB(N); 1032 case ISD::ADDC: return visitADDC(N); 1033 case ISD::ADDE: return visitADDE(N); 1034 case ISD::MUL: return visitMUL(N); 1035 case ISD::SDIV: return visitSDIV(N); 1036 case ISD::UDIV: return visitUDIV(N); 1037 case ISD::SREM: return visitSREM(N); 1038 case ISD::UREM: return visitUREM(N); 1039 case ISD::MULHU: return visitMULHU(N); 1040 case ISD::MULHS: return visitMULHS(N); 1041 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1042 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1043 case ISD::SDIVREM: return visitSDIVREM(N); 1044 case ISD::UDIVREM: return visitUDIVREM(N); 1045 case ISD::AND: return visitAND(N); 1046 case ISD::OR: return visitOR(N); 1047 case ISD::XOR: return visitXOR(N); 1048 case ISD::SHL: return visitSHL(N); 1049 case ISD::SRA: return visitSRA(N); 1050 case ISD::SRL: return visitSRL(N); 1051 case ISD::CTLZ: return visitCTLZ(N); 1052 case ISD::CTTZ: return visitCTTZ(N); 1053 case ISD::CTPOP: return visitCTPOP(N); 1054 case ISD::SELECT: return visitSELECT(N); 1055 case ISD::SELECT_CC: return visitSELECT_CC(N); 1056 case ISD::SETCC: return visitSETCC(N); 1057 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1058 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1059 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1060 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1061 case ISD::TRUNCATE: return visitTRUNCATE(N); 1062 case ISD::BITCAST: return visitBITCAST(N); 1063 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1064 case ISD::FADD: return visitFADD(N); 1065 case ISD::FSUB: return visitFSUB(N); 1066 case ISD::FMUL: return visitFMUL(N); 1067 case ISD::FDIV: return visitFDIV(N); 1068 case ISD::FREM: return visitFREM(N); 1069 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1070 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1071 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1072 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1073 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1074 case ISD::FP_ROUND: return visitFP_ROUND(N); 1075 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1076 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1077 case ISD::FNEG: return visitFNEG(N); 1078 case ISD::FABS: return visitFABS(N); 1079 case ISD::BRCOND: return visitBRCOND(N); 1080 case ISD::BR_CC: return visitBR_CC(N); 1081 case ISD::LOAD: return visitLOAD(N); 1082 case ISD::STORE: return visitSTORE(N); 1083 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1084 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1085 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1086 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1087 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1088 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1089 } 1090 return SDValue(); 1091} 1092 1093SDValue DAGCombiner::combine(SDNode *N) { 1094 SDValue RV = visit(N); 1095 1096 // If nothing happened, try a target-specific DAG combine. 1097 if (RV.getNode() == 0) { 1098 assert(N->getOpcode() != ISD::DELETED_NODE && 1099 "Node was deleted but visit returned NULL!"); 1100 1101 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1102 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1103 1104 // Expose the DAG combiner to the target combiner impls. 1105 TargetLowering::DAGCombinerInfo 1106 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1107 1108 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1109 } 1110 } 1111 1112 // If nothing happened still, try promoting the operation. 1113 if (RV.getNode() == 0) { 1114 switch (N->getOpcode()) { 1115 default: break; 1116 case ISD::ADD: 1117 case ISD::SUB: 1118 case ISD::MUL: 1119 case ISD::AND: 1120 case ISD::OR: 1121 case ISD::XOR: 1122 RV = PromoteIntBinOp(SDValue(N, 0)); 1123 break; 1124 case ISD::SHL: 1125 case ISD::SRA: 1126 case ISD::SRL: 1127 RV = PromoteIntShiftOp(SDValue(N, 0)); 1128 break; 1129 case ISD::SIGN_EXTEND: 1130 case ISD::ZERO_EXTEND: 1131 case ISD::ANY_EXTEND: 1132 RV = PromoteExtend(SDValue(N, 0)); 1133 break; 1134 case ISD::LOAD: 1135 if (PromoteLoad(SDValue(N, 0))) 1136 RV = SDValue(N, 0); 1137 break; 1138 } 1139 } 1140 1141 // If N is a commutative binary node, try commuting it to enable more 1142 // sdisel CSE. 1143 if (RV.getNode() == 0 && 1144 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1145 N->getNumValues() == 1) { 1146 SDValue N0 = N->getOperand(0); 1147 SDValue N1 = N->getOperand(1); 1148 1149 // Constant operands are canonicalized to RHS. 1150 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1151 SDValue Ops[] = { N1, N0 }; 1152 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1153 Ops, 2); 1154 if (CSENode) 1155 return SDValue(CSENode, 0); 1156 } 1157 } 1158 1159 return RV; 1160} 1161 1162/// getInputChainForNode - Given a node, return its input chain if it has one, 1163/// otherwise return a null sd operand. 1164static SDValue getInputChainForNode(SDNode *N) { 1165 if (unsigned NumOps = N->getNumOperands()) { 1166 if (N->getOperand(0).getValueType() == MVT::Other) 1167 return N->getOperand(0); 1168 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1169 return N->getOperand(NumOps-1); 1170 for (unsigned i = 1; i < NumOps-1; ++i) 1171 if (N->getOperand(i).getValueType() == MVT::Other) 1172 return N->getOperand(i); 1173 } 1174 return SDValue(); 1175} 1176 1177SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1178 // If N has two operands, where one has an input chain equal to the other, 1179 // the 'other' chain is redundant. 1180 if (N->getNumOperands() == 2) { 1181 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1182 return N->getOperand(0); 1183 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1184 return N->getOperand(1); 1185 } 1186 1187 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1188 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1189 SmallPtrSet<SDNode*, 16> SeenOps; 1190 bool Changed = false; // If we should replace this token factor. 1191 1192 // Start out with this token factor. 1193 TFs.push_back(N); 1194 1195 // Iterate through token factors. The TFs grows when new token factors are 1196 // encountered. 1197 for (unsigned i = 0; i < TFs.size(); ++i) { 1198 SDNode *TF = TFs[i]; 1199 1200 // Check each of the operands. 1201 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1202 SDValue Op = TF->getOperand(i); 1203 1204 switch (Op.getOpcode()) { 1205 case ISD::EntryToken: 1206 // Entry tokens don't need to be added to the list. They are 1207 // rededundant. 1208 Changed = true; 1209 break; 1210 1211 case ISD::TokenFactor: 1212 if (Op.hasOneUse() && 1213 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1214 // Queue up for processing. 1215 TFs.push_back(Op.getNode()); 1216 // Clean up in case the token factor is removed. 1217 AddToWorkList(Op.getNode()); 1218 Changed = true; 1219 break; 1220 } 1221 // Fall thru 1222 1223 default: 1224 // Only add if it isn't already in the list. 1225 if (SeenOps.insert(Op.getNode())) 1226 Ops.push_back(Op); 1227 else 1228 Changed = true; 1229 break; 1230 } 1231 } 1232 } 1233 1234 SDValue Result; 1235 1236 // If we've change things around then replace token factor. 1237 if (Changed) { 1238 if (Ops.empty()) { 1239 // The entry token is the only possible outcome. 1240 Result = DAG.getEntryNode(); 1241 } else { 1242 // New and improved token factor. 1243 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1244 MVT::Other, &Ops[0], Ops.size()); 1245 } 1246 1247 // Don't add users to work list. 1248 return CombineTo(N, Result, false); 1249 } 1250 1251 return Result; 1252} 1253 1254/// MERGE_VALUES can always be eliminated. 1255SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1256 WorkListRemover DeadNodes(*this); 1257 // Replacing results may cause a different MERGE_VALUES to suddenly 1258 // be CSE'd with N, and carry its uses with it. Iterate until no 1259 // uses remain, to ensure that the node can be safely deleted. 1260 do { 1261 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1262 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1263 &DeadNodes); 1264 } while (!N->use_empty()); 1265 removeFromWorkList(N); 1266 DAG.DeleteNode(N); 1267 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1268} 1269 1270static 1271SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1272 SelectionDAG &DAG) { 1273 EVT VT = N0.getValueType(); 1274 SDValue N00 = N0.getOperand(0); 1275 SDValue N01 = N0.getOperand(1); 1276 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1277 1278 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1279 isa<ConstantSDNode>(N00.getOperand(1))) { 1280 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1281 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1282 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1283 N00.getOperand(0), N01), 1284 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1285 N00.getOperand(1), N01)); 1286 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1287 } 1288 1289 return SDValue(); 1290} 1291 1292SDValue DAGCombiner::visitADD(SDNode *N) { 1293 SDValue N0 = N->getOperand(0); 1294 SDValue N1 = N->getOperand(1); 1295 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1296 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1297 EVT VT = N0.getValueType(); 1298 1299 // fold vector ops 1300 if (VT.isVector()) { 1301 SDValue FoldedVOp = SimplifyVBinOp(N); 1302 if (FoldedVOp.getNode()) return FoldedVOp; 1303 } 1304 1305 // fold (add x, undef) -> undef 1306 if (N0.getOpcode() == ISD::UNDEF) 1307 return N0; 1308 if (N1.getOpcode() == ISD::UNDEF) 1309 return N1; 1310 // fold (add c1, c2) -> c1+c2 1311 if (N0C && N1C) 1312 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1313 // canonicalize constant to RHS 1314 if (N0C && !N1C) 1315 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1316 // fold (add x, 0) -> x 1317 if (N1C && N1C->isNullValue()) 1318 return N0; 1319 // fold (add Sym, c) -> Sym+c 1320 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1321 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1322 GA->getOpcode() == ISD::GlobalAddress) 1323 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1324 GA->getOffset() + 1325 (uint64_t)N1C->getSExtValue()); 1326 // fold ((c1-A)+c2) -> (c1+c2)-A 1327 if (N1C && N0.getOpcode() == ISD::SUB) 1328 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1329 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1330 DAG.getConstant(N1C->getAPIntValue()+ 1331 N0C->getAPIntValue(), VT), 1332 N0.getOperand(1)); 1333 // reassociate add 1334 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1335 if (RADD.getNode() != 0) 1336 return RADD; 1337 // fold ((0-A) + B) -> B-A 1338 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1339 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1340 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1341 // fold (A + (0-B)) -> A-B 1342 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1343 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1344 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1345 // fold (A+(B-A)) -> B 1346 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1347 return N1.getOperand(0); 1348 // fold ((B-A)+A) -> B 1349 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1350 return N0.getOperand(0); 1351 // fold (A+(B-(A+C))) to (B-C) 1352 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1353 N0 == N1.getOperand(1).getOperand(0)) 1354 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1355 N1.getOperand(1).getOperand(1)); 1356 // fold (A+(B-(C+A))) to (B-C) 1357 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1358 N0 == N1.getOperand(1).getOperand(1)) 1359 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1360 N1.getOperand(1).getOperand(0)); 1361 // fold (A+((B-A)+or-C)) to (B+or-C) 1362 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1363 N1.getOperand(0).getOpcode() == ISD::SUB && 1364 N0 == N1.getOperand(0).getOperand(1)) 1365 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1366 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1367 1368 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1369 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1370 SDValue N00 = N0.getOperand(0); 1371 SDValue N01 = N0.getOperand(1); 1372 SDValue N10 = N1.getOperand(0); 1373 SDValue N11 = N1.getOperand(1); 1374 1375 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1376 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1377 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1378 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1379 } 1380 1381 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1382 return SDValue(N, 0); 1383 1384 // fold (a+b) -> (a|b) iff a and b share no bits. 1385 if (VT.isInteger() && !VT.isVector()) { 1386 APInt LHSZero, LHSOne; 1387 APInt RHSZero, RHSOne; 1388 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1389 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1390 1391 if (LHSZero.getBoolValue()) { 1392 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1393 1394 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1395 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1396 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1397 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1398 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1399 } 1400 } 1401 1402 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1403 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1404 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1405 if (Result.getNode()) return Result; 1406 } 1407 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1408 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1409 if (Result.getNode()) return Result; 1410 } 1411 1412 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1413 if (N1.getOpcode() == ISD::SHL && 1414 N1.getOperand(0).getOpcode() == ISD::SUB) 1415 if (ConstantSDNode *C = 1416 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1417 if (C->getAPIntValue() == 0) 1418 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1419 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1420 N1.getOperand(0).getOperand(1), 1421 N1.getOperand(1))); 1422 if (N0.getOpcode() == ISD::SHL && 1423 N0.getOperand(0).getOpcode() == ISD::SUB) 1424 if (ConstantSDNode *C = 1425 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1426 if (C->getAPIntValue() == 0) 1427 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1428 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1429 N0.getOperand(0).getOperand(1), 1430 N0.getOperand(1))); 1431 1432 if (N1.getOpcode() == ISD::AND) { 1433 SDValue AndOp0 = N1.getOperand(0); 1434 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1435 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1436 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1437 1438 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1439 // and similar xforms where the inner op is either ~0 or 0. 1440 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1441 DebugLoc DL = N->getDebugLoc(); 1442 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1443 } 1444 } 1445 1446 return SDValue(); 1447} 1448 1449SDValue DAGCombiner::visitADDC(SDNode *N) { 1450 SDValue N0 = N->getOperand(0); 1451 SDValue N1 = N->getOperand(1); 1452 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1453 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1454 EVT VT = N0.getValueType(); 1455 1456 // If the flag result is dead, turn this into an ADD. 1457 if (N->hasNUsesOfValue(0, 1)) 1458 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1459 DAG.getNode(ISD::CARRY_FALSE, 1460 N->getDebugLoc(), MVT::Flag)); 1461 1462 // canonicalize constant to RHS. 1463 if (N0C && !N1C) 1464 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1465 1466 // fold (addc x, 0) -> x + no carry out 1467 if (N1C && N1C->isNullValue()) 1468 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1469 N->getDebugLoc(), MVT::Flag)); 1470 1471 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1472 APInt LHSZero, LHSOne; 1473 APInt RHSZero, RHSOne; 1474 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1475 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1476 1477 if (LHSZero.getBoolValue()) { 1478 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1479 1480 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1481 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1482 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1483 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1484 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1485 DAG.getNode(ISD::CARRY_FALSE, 1486 N->getDebugLoc(), MVT::Flag)); 1487 } 1488 1489 return SDValue(); 1490} 1491 1492SDValue DAGCombiner::visitADDE(SDNode *N) { 1493 SDValue N0 = N->getOperand(0); 1494 SDValue N1 = N->getOperand(1); 1495 SDValue CarryIn = N->getOperand(2); 1496 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1498 1499 // canonicalize constant to RHS 1500 if (N0C && !N1C) 1501 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1502 N1, N0, CarryIn); 1503 1504 // fold (adde x, y, false) -> (addc x, y) 1505 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1506 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1507 1508 return SDValue(); 1509} 1510 1511SDValue DAGCombiner::visitSUB(SDNode *N) { 1512 SDValue N0 = N->getOperand(0); 1513 SDValue N1 = N->getOperand(1); 1514 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1515 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1516 EVT VT = N0.getValueType(); 1517 1518 // fold vector ops 1519 if (VT.isVector()) { 1520 SDValue FoldedVOp = SimplifyVBinOp(N); 1521 if (FoldedVOp.getNode()) return FoldedVOp; 1522 } 1523 1524 // fold (sub x, x) -> 0 1525 if (N0 == N1) 1526 return DAG.getConstant(0, N->getValueType(0)); 1527 // fold (sub c1, c2) -> c1-c2 1528 if (N0C && N1C) 1529 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1530 // fold (sub x, c) -> (add x, -c) 1531 if (N1C) 1532 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1533 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1534 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1535 if (N0C && N0C->isAllOnesValue()) 1536 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1537 // fold (A+B)-A -> B 1538 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1539 return N0.getOperand(1); 1540 // fold (A+B)-B -> A 1541 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1542 return N0.getOperand(0); 1543 // fold ((A+(B+or-C))-B) -> A+or-C 1544 if (N0.getOpcode() == ISD::ADD && 1545 (N0.getOperand(1).getOpcode() == ISD::SUB || 1546 N0.getOperand(1).getOpcode() == ISD::ADD) && 1547 N0.getOperand(1).getOperand(0) == N1) 1548 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1549 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1550 // fold ((A+(C+B))-B) -> A+C 1551 if (N0.getOpcode() == ISD::ADD && 1552 N0.getOperand(1).getOpcode() == ISD::ADD && 1553 N0.getOperand(1).getOperand(1) == N1) 1554 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1555 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1556 // fold ((A-(B-C))-C) -> A-B 1557 if (N0.getOpcode() == ISD::SUB && 1558 N0.getOperand(1).getOpcode() == ISD::SUB && 1559 N0.getOperand(1).getOperand(1) == N1) 1560 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1561 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1562 1563 // If either operand of a sub is undef, the result is undef 1564 if (N0.getOpcode() == ISD::UNDEF) 1565 return N0; 1566 if (N1.getOpcode() == ISD::UNDEF) 1567 return N1; 1568 1569 // If the relocation model supports it, consider symbol offsets. 1570 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1571 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1572 // fold (sub Sym, c) -> Sym-c 1573 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1574 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1575 GA->getOffset() - 1576 (uint64_t)N1C->getSExtValue()); 1577 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1578 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1579 if (GA->getGlobal() == GB->getGlobal()) 1580 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1581 VT); 1582 } 1583 1584 return SDValue(); 1585} 1586 1587SDValue DAGCombiner::visitMUL(SDNode *N) { 1588 SDValue N0 = N->getOperand(0); 1589 SDValue N1 = N->getOperand(1); 1590 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1591 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1592 EVT VT = N0.getValueType(); 1593 1594 // fold vector ops 1595 if (VT.isVector()) { 1596 SDValue FoldedVOp = SimplifyVBinOp(N); 1597 if (FoldedVOp.getNode()) return FoldedVOp; 1598 } 1599 1600 // fold (mul x, undef) -> 0 1601 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1602 return DAG.getConstant(0, VT); 1603 // fold (mul c1, c2) -> c1*c2 1604 if (N0C && N1C) 1605 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1606 // canonicalize constant to RHS 1607 if (N0C && !N1C) 1608 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1609 // fold (mul x, 0) -> 0 1610 if (N1C && N1C->isNullValue()) 1611 return N1; 1612 // fold (mul x, -1) -> 0-x 1613 if (N1C && N1C->isAllOnesValue()) 1614 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1615 DAG.getConstant(0, VT), N0); 1616 // fold (mul x, (1 << c)) -> x << c 1617 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1618 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1619 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1620 getShiftAmountTy())); 1621 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1622 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1623 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1624 // FIXME: If the input is something that is easily negated (e.g. a 1625 // single-use add), we should put the negate there. 1626 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1627 DAG.getConstant(0, VT), 1628 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1629 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1630 } 1631 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1632 if (N1C && N0.getOpcode() == ISD::SHL && 1633 isa<ConstantSDNode>(N0.getOperand(1))) { 1634 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1635 N1, N0.getOperand(1)); 1636 AddToWorkList(C3.getNode()); 1637 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1638 N0.getOperand(0), C3); 1639 } 1640 1641 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1642 // use. 1643 { 1644 SDValue Sh(0,0), Y(0,0); 1645 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1646 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1647 N0.getNode()->hasOneUse()) { 1648 Sh = N0; Y = N1; 1649 } else if (N1.getOpcode() == ISD::SHL && 1650 isa<ConstantSDNode>(N1.getOperand(1)) && 1651 N1.getNode()->hasOneUse()) { 1652 Sh = N1; Y = N0; 1653 } 1654 1655 if (Sh.getNode()) { 1656 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1657 Sh.getOperand(0), Y); 1658 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1659 Mul, Sh.getOperand(1)); 1660 } 1661 } 1662 1663 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1664 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1665 isa<ConstantSDNode>(N0.getOperand(1))) 1666 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1667 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1668 N0.getOperand(0), N1), 1669 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1670 N0.getOperand(1), N1)); 1671 1672 // reassociate mul 1673 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1674 if (RMUL.getNode() != 0) 1675 return RMUL; 1676 1677 return SDValue(); 1678} 1679 1680SDValue DAGCombiner::visitSDIV(SDNode *N) { 1681 SDValue N0 = N->getOperand(0); 1682 SDValue N1 = N->getOperand(1); 1683 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1684 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1685 EVT VT = N->getValueType(0); 1686 1687 // fold vector ops 1688 if (VT.isVector()) { 1689 SDValue FoldedVOp = SimplifyVBinOp(N); 1690 if (FoldedVOp.getNode()) return FoldedVOp; 1691 } 1692 1693 // fold (sdiv c1, c2) -> c1/c2 1694 if (N0C && N1C && !N1C->isNullValue()) 1695 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1696 // fold (sdiv X, 1) -> X 1697 if (N1C && N1C->getSExtValue() == 1LL) 1698 return N0; 1699 // fold (sdiv X, -1) -> 0-X 1700 if (N1C && N1C->isAllOnesValue()) 1701 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1702 DAG.getConstant(0, VT), N0); 1703 // If we know the sign bits of both operands are zero, strength reduce to a 1704 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1705 if (!VT.isVector()) { 1706 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1707 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1708 N0, N1); 1709 } 1710 // fold (sdiv X, pow2) -> simple ops after legalize 1711 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1712 (isPowerOf2_64(N1C->getSExtValue()) || 1713 isPowerOf2_64(-N1C->getSExtValue()))) { 1714 // If dividing by powers of two is cheap, then don't perform the following 1715 // fold. 1716 if (TLI.isPow2DivCheap()) 1717 return SDValue(); 1718 1719 int64_t pow2 = N1C->getSExtValue(); 1720 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1721 unsigned lg2 = Log2_64(abs2); 1722 1723 // Splat the sign bit into the register 1724 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1725 DAG.getConstant(VT.getSizeInBits()-1, 1726 getShiftAmountTy())); 1727 AddToWorkList(SGN.getNode()); 1728 1729 // Add (N0 < 0) ? abs2 - 1 : 0; 1730 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1731 DAG.getConstant(VT.getSizeInBits() - lg2, 1732 getShiftAmountTy())); 1733 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1734 AddToWorkList(SRL.getNode()); 1735 AddToWorkList(ADD.getNode()); // Divide by pow2 1736 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1737 DAG.getConstant(lg2, getShiftAmountTy())); 1738 1739 // If we're dividing by a positive value, we're done. Otherwise, we must 1740 // negate the result. 1741 if (pow2 > 0) 1742 return SRA; 1743 1744 AddToWorkList(SRA.getNode()); 1745 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1746 DAG.getConstant(0, VT), SRA); 1747 } 1748 1749 // if integer divide is expensive and we satisfy the requirements, emit an 1750 // alternate sequence. 1751 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1752 !TLI.isIntDivCheap()) { 1753 SDValue Op = BuildSDIV(N); 1754 if (Op.getNode()) return Op; 1755 } 1756 1757 // undef / X -> 0 1758 if (N0.getOpcode() == ISD::UNDEF) 1759 return DAG.getConstant(0, VT); 1760 // X / undef -> undef 1761 if (N1.getOpcode() == ISD::UNDEF) 1762 return N1; 1763 1764 return SDValue(); 1765} 1766 1767SDValue DAGCombiner::visitUDIV(SDNode *N) { 1768 SDValue N0 = N->getOperand(0); 1769 SDValue N1 = N->getOperand(1); 1770 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1771 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1772 EVT VT = N->getValueType(0); 1773 1774 // fold vector ops 1775 if (VT.isVector()) { 1776 SDValue FoldedVOp = SimplifyVBinOp(N); 1777 if (FoldedVOp.getNode()) return FoldedVOp; 1778 } 1779 1780 // fold (udiv c1, c2) -> c1/c2 1781 if (N0C && N1C && !N1C->isNullValue()) 1782 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1783 // fold (udiv x, (1 << c)) -> x >>u c 1784 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1785 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1786 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1787 getShiftAmountTy())); 1788 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1789 if (N1.getOpcode() == ISD::SHL) { 1790 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1791 if (SHC->getAPIntValue().isPowerOf2()) { 1792 EVT ADDVT = N1.getOperand(1).getValueType(); 1793 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1794 N1.getOperand(1), 1795 DAG.getConstant(SHC->getAPIntValue() 1796 .logBase2(), 1797 ADDVT)); 1798 AddToWorkList(Add.getNode()); 1799 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1800 } 1801 } 1802 } 1803 // fold (udiv x, c) -> alternate 1804 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1805 SDValue Op = BuildUDIV(N); 1806 if (Op.getNode()) return Op; 1807 } 1808 1809 // undef / X -> 0 1810 if (N0.getOpcode() == ISD::UNDEF) 1811 return DAG.getConstant(0, VT); 1812 // X / undef -> undef 1813 if (N1.getOpcode() == ISD::UNDEF) 1814 return N1; 1815 1816 return SDValue(); 1817} 1818 1819SDValue DAGCombiner::visitSREM(SDNode *N) { 1820 SDValue N0 = N->getOperand(0); 1821 SDValue N1 = N->getOperand(1); 1822 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1823 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1824 EVT VT = N->getValueType(0); 1825 1826 // fold (srem c1, c2) -> c1%c2 1827 if (N0C && N1C && !N1C->isNullValue()) 1828 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1829 // If we know the sign bits of both operands are zero, strength reduce to a 1830 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1831 if (!VT.isVector()) { 1832 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1833 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1834 } 1835 1836 // If X/C can be simplified by the division-by-constant logic, lower 1837 // X%C to the equivalent of X-X/C*C. 1838 if (N1C && !N1C->isNullValue()) { 1839 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1840 AddToWorkList(Div.getNode()); 1841 SDValue OptimizedDiv = combine(Div.getNode()); 1842 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1843 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1844 OptimizedDiv, N1); 1845 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1846 AddToWorkList(Mul.getNode()); 1847 return Sub; 1848 } 1849 } 1850 1851 // undef % X -> 0 1852 if (N0.getOpcode() == ISD::UNDEF) 1853 return DAG.getConstant(0, VT); 1854 // X % undef -> undef 1855 if (N1.getOpcode() == ISD::UNDEF) 1856 return N1; 1857 1858 return SDValue(); 1859} 1860 1861SDValue DAGCombiner::visitUREM(SDNode *N) { 1862 SDValue N0 = N->getOperand(0); 1863 SDValue N1 = N->getOperand(1); 1864 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1865 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1866 EVT VT = N->getValueType(0); 1867 1868 // fold (urem c1, c2) -> c1%c2 1869 if (N0C && N1C && !N1C->isNullValue()) 1870 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1871 // fold (urem x, pow2) -> (and x, pow2-1) 1872 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1873 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1874 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1875 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1876 if (N1.getOpcode() == ISD::SHL) { 1877 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1878 if (SHC->getAPIntValue().isPowerOf2()) { 1879 SDValue Add = 1880 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1881 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1882 VT)); 1883 AddToWorkList(Add.getNode()); 1884 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1885 } 1886 } 1887 } 1888 1889 // If X/C can be simplified by the division-by-constant logic, lower 1890 // X%C to the equivalent of X-X/C*C. 1891 if (N1C && !N1C->isNullValue()) { 1892 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1893 AddToWorkList(Div.getNode()); 1894 SDValue OptimizedDiv = combine(Div.getNode()); 1895 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1896 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1897 OptimizedDiv, N1); 1898 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1899 AddToWorkList(Mul.getNode()); 1900 return Sub; 1901 } 1902 } 1903 1904 // undef % X -> 0 1905 if (N0.getOpcode() == ISD::UNDEF) 1906 return DAG.getConstant(0, VT); 1907 // X % undef -> undef 1908 if (N1.getOpcode() == ISD::UNDEF) 1909 return N1; 1910 1911 return SDValue(); 1912} 1913 1914SDValue DAGCombiner::visitMULHS(SDNode *N) { 1915 SDValue N0 = N->getOperand(0); 1916 SDValue N1 = N->getOperand(1); 1917 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1918 EVT VT = N->getValueType(0); 1919 1920 // fold (mulhs x, 0) -> 0 1921 if (N1C && N1C->isNullValue()) 1922 return N1; 1923 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1924 if (N1C && N1C->getAPIntValue() == 1) 1925 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1926 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1927 getShiftAmountTy())); 1928 // fold (mulhs x, undef) -> 0 1929 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1930 return DAG.getConstant(0, VT); 1931 1932 return SDValue(); 1933} 1934 1935SDValue DAGCombiner::visitMULHU(SDNode *N) { 1936 SDValue N0 = N->getOperand(0); 1937 SDValue N1 = N->getOperand(1); 1938 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1939 EVT VT = N->getValueType(0); 1940 1941 // fold (mulhu x, 0) -> 0 1942 if (N1C && N1C->isNullValue()) 1943 return N1; 1944 // fold (mulhu x, 1) -> 0 1945 if (N1C && N1C->getAPIntValue() == 1) 1946 return DAG.getConstant(0, N0.getValueType()); 1947 // fold (mulhu x, undef) -> 0 1948 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1949 return DAG.getConstant(0, VT); 1950 1951 return SDValue(); 1952} 1953 1954/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1955/// compute two values. LoOp and HiOp give the opcodes for the two computations 1956/// that are being performed. Return true if a simplification was made. 1957/// 1958SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1959 unsigned HiOp) { 1960 // If the high half is not needed, just compute the low half. 1961 bool HiExists = N->hasAnyUseOfValue(1); 1962 if (!HiExists && 1963 (!LegalOperations || 1964 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1965 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1966 N->op_begin(), N->getNumOperands()); 1967 return CombineTo(N, Res, Res); 1968 } 1969 1970 // If the low half is not needed, just compute the high half. 1971 bool LoExists = N->hasAnyUseOfValue(0); 1972 if (!LoExists && 1973 (!LegalOperations || 1974 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1975 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1976 N->op_begin(), N->getNumOperands()); 1977 return CombineTo(N, Res, Res); 1978 } 1979 1980 // If both halves are used, return as it is. 1981 if (LoExists && HiExists) 1982 return SDValue(); 1983 1984 // If the two computed results can be simplified separately, separate them. 1985 if (LoExists) { 1986 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1987 N->op_begin(), N->getNumOperands()); 1988 AddToWorkList(Lo.getNode()); 1989 SDValue LoOpt = combine(Lo.getNode()); 1990 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1991 (!LegalOperations || 1992 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1993 return CombineTo(N, LoOpt, LoOpt); 1994 } 1995 1996 if (HiExists) { 1997 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1998 N->op_begin(), N->getNumOperands()); 1999 AddToWorkList(Hi.getNode()); 2000 SDValue HiOpt = combine(Hi.getNode()); 2001 if (HiOpt.getNode() && HiOpt != Hi && 2002 (!LegalOperations || 2003 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2004 return CombineTo(N, HiOpt, HiOpt); 2005 } 2006 2007 return SDValue(); 2008} 2009 2010SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2011 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2012 if (Res.getNode()) return Res; 2013 2014 return SDValue(); 2015} 2016 2017SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2018 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2019 if (Res.getNode()) return Res; 2020 2021 return SDValue(); 2022} 2023 2024SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2025 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2026 if (Res.getNode()) return Res; 2027 2028 return SDValue(); 2029} 2030 2031SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2032 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2033 if (Res.getNode()) return Res; 2034 2035 return SDValue(); 2036} 2037 2038/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2039/// two operands of the same opcode, try to simplify it. 2040SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2041 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2042 EVT VT = N0.getValueType(); 2043 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2044 2045 // Bail early if none of these transforms apply. 2046 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2047 2048 // For each of OP in AND/OR/XOR: 2049 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2050 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2051 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2052 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2053 // 2054 // do not sink logical op inside of a vector extend, since it may combine 2055 // into a vsetcc. 2056 EVT Op0VT = N0.getOperand(0).getValueType(); 2057 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2058 N0.getOpcode() == ISD::SIGN_EXTEND || 2059 // Avoid infinite looping with PromoteIntBinOp. 2060 (N0.getOpcode() == ISD::ANY_EXTEND && 2061 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2062 (N0.getOpcode() == ISD::TRUNCATE && 2063 (!TLI.isZExtFree(VT, Op0VT) || 2064 !TLI.isTruncateFree(Op0VT, VT)) && 2065 TLI.isTypeLegal(Op0VT))) && 2066 !VT.isVector() && 2067 Op0VT == N1.getOperand(0).getValueType() && 2068 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2069 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2070 N0.getOperand(0).getValueType(), 2071 N0.getOperand(0), N1.getOperand(0)); 2072 AddToWorkList(ORNode.getNode()); 2073 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2074 } 2075 2076 // For each of OP in SHL/SRL/SRA/AND... 2077 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2078 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2079 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2080 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2081 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2082 N0.getOperand(1) == N1.getOperand(1)) { 2083 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2084 N0.getOperand(0).getValueType(), 2085 N0.getOperand(0), N1.getOperand(0)); 2086 AddToWorkList(ORNode.getNode()); 2087 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2088 ORNode, N0.getOperand(1)); 2089 } 2090 2091 return SDValue(); 2092} 2093 2094SDValue DAGCombiner::visitAND(SDNode *N) { 2095 SDValue N0 = N->getOperand(0); 2096 SDValue N1 = N->getOperand(1); 2097 SDValue LL, LR, RL, RR, CC0, CC1; 2098 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2099 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2100 EVT VT = N1.getValueType(); 2101 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2102 2103 // fold vector ops 2104 if (VT.isVector()) { 2105 SDValue FoldedVOp = SimplifyVBinOp(N); 2106 if (FoldedVOp.getNode()) return FoldedVOp; 2107 } 2108 2109 // fold (and x, undef) -> 0 2110 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2111 return DAG.getConstant(0, VT); 2112 // fold (and c1, c2) -> c1&c2 2113 if (N0C && N1C) 2114 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2115 // canonicalize constant to RHS 2116 if (N0C && !N1C) 2117 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2118 // fold (and x, -1) -> x 2119 if (N1C && N1C->isAllOnesValue()) 2120 return N0; 2121 // if (and x, c) is known to be zero, return 0 2122 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2123 APInt::getAllOnesValue(BitWidth))) 2124 return DAG.getConstant(0, VT); 2125 // reassociate and 2126 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2127 if (RAND.getNode() != 0) 2128 return RAND; 2129 // fold (and (or x, C), D) -> D if (C & D) == D 2130 if (N1C && N0.getOpcode() == ISD::OR) 2131 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2132 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2133 return N1; 2134 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2135 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2136 SDValue N0Op0 = N0.getOperand(0); 2137 APInt Mask = ~N1C->getAPIntValue(); 2138 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2139 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2140 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2141 N0.getValueType(), N0Op0); 2142 2143 // Replace uses of the AND with uses of the Zero extend node. 2144 CombineTo(N, Zext); 2145 2146 // We actually want to replace all uses of the any_extend with the 2147 // zero_extend, to avoid duplicating things. This will later cause this 2148 // AND to be folded. 2149 CombineTo(N0.getNode(), Zext); 2150 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2151 } 2152 } 2153 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2154 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2155 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2156 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2157 2158 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2159 LL.getValueType().isInteger()) { 2160 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2161 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2162 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2163 LR.getValueType(), LL, RL); 2164 AddToWorkList(ORNode.getNode()); 2165 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2166 } 2167 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2168 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2169 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2170 LR.getValueType(), LL, RL); 2171 AddToWorkList(ANDNode.getNode()); 2172 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2173 } 2174 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2175 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2176 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2177 LR.getValueType(), LL, RL); 2178 AddToWorkList(ORNode.getNode()); 2179 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2180 } 2181 } 2182 // canonicalize equivalent to ll == rl 2183 if (LL == RR && LR == RL) { 2184 Op1 = ISD::getSetCCSwappedOperands(Op1); 2185 std::swap(RL, RR); 2186 } 2187 if (LL == RL && LR == RR) { 2188 bool isInteger = LL.getValueType().isInteger(); 2189 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2190 if (Result != ISD::SETCC_INVALID && 2191 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2192 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2193 LL, LR, Result); 2194 } 2195 } 2196 2197 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2198 if (N0.getOpcode() == N1.getOpcode()) { 2199 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2200 if (Tmp.getNode()) return Tmp; 2201 } 2202 2203 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2204 // fold (and (sra)) -> (and (srl)) when possible. 2205 if (!VT.isVector() && 2206 SimplifyDemandedBits(SDValue(N, 0))) 2207 return SDValue(N, 0); 2208 2209 // fold (zext_inreg (extload x)) -> (zextload x) 2210 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2211 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2212 EVT MemVT = LN0->getMemoryVT(); 2213 // If we zero all the possible extended bits, then we can turn this into 2214 // a zextload if we are running before legalize or the operation is legal. 2215 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2216 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2217 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2218 ((!LegalOperations && !LN0->isVolatile()) || 2219 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2220 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(), 2221 LN0->getChain(), LN0->getBasePtr(), 2222 LN0->getPointerInfo(), MemVT, 2223 LN0->isVolatile(), LN0->isNonTemporal(), 2224 LN0->getAlignment()); 2225 AddToWorkList(N); 2226 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2227 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2228 } 2229 } 2230 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2231 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2232 N0.hasOneUse()) { 2233 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2234 EVT MemVT = LN0->getMemoryVT(); 2235 // If we zero all the possible extended bits, then we can turn this into 2236 // a zextload if we are running before legalize or the operation is legal. 2237 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2238 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2239 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2240 ((!LegalOperations && !LN0->isVolatile()) || 2241 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2242 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(), 2243 LN0->getChain(), 2244 LN0->getBasePtr(), LN0->getPointerInfo(), 2245 MemVT, 2246 LN0->isVolatile(), LN0->isNonTemporal(), 2247 LN0->getAlignment()); 2248 AddToWorkList(N); 2249 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2250 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2251 } 2252 } 2253 2254 // fold (and (load x), 255) -> (zextload x, i8) 2255 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2256 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2257 if (N1C && (N0.getOpcode() == ISD::LOAD || 2258 (N0.getOpcode() == ISD::ANY_EXTEND && 2259 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2260 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2261 LoadSDNode *LN0 = HasAnyExt 2262 ? cast<LoadSDNode>(N0.getOperand(0)) 2263 : cast<LoadSDNode>(N0); 2264 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2265 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2266 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2267 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2268 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2269 EVT LoadedVT = LN0->getMemoryVT(); 2270 2271 if (ExtVT == LoadedVT && 2272 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2273 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2274 2275 SDValue NewLoad = 2276 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(), 2277 LN0->getChain(), LN0->getBasePtr(), 2278 LN0->getPointerInfo(), 2279 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2280 LN0->getAlignment()); 2281 AddToWorkList(N); 2282 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2283 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2284 } 2285 2286 // Do not change the width of a volatile load. 2287 // Do not generate loads of non-round integer types since these can 2288 // be expensive (and would be wrong if the type is not byte sized). 2289 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2290 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2291 EVT PtrType = LN0->getOperand(1).getValueType(); 2292 2293 unsigned Alignment = LN0->getAlignment(); 2294 SDValue NewPtr = LN0->getBasePtr(); 2295 2296 // For big endian targets, we need to add an offset to the pointer 2297 // to load the correct bytes. For little endian systems, we merely 2298 // need to read fewer bytes from the same pointer. 2299 if (TLI.isBigEndian()) { 2300 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2301 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2302 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2303 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2304 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2305 Alignment = MinAlign(Alignment, PtrOff); 2306 } 2307 2308 AddToWorkList(NewPtr.getNode()); 2309 2310 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2311 SDValue Load = 2312 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(), 2313 LN0->getChain(), NewPtr, 2314 LN0->getPointerInfo(), 2315 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2316 Alignment); 2317 AddToWorkList(N); 2318 CombineTo(LN0, Load, Load.getValue(1)); 2319 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2320 } 2321 } 2322 } 2323 } 2324 2325 return SDValue(); 2326} 2327 2328SDValue DAGCombiner::visitOR(SDNode *N) { 2329 SDValue N0 = N->getOperand(0); 2330 SDValue N1 = N->getOperand(1); 2331 SDValue LL, LR, RL, RR, CC0, CC1; 2332 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2333 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2334 EVT VT = N1.getValueType(); 2335 2336 // fold vector ops 2337 if (VT.isVector()) { 2338 SDValue FoldedVOp = SimplifyVBinOp(N); 2339 if (FoldedVOp.getNode()) return FoldedVOp; 2340 } 2341 2342 // fold (or x, undef) -> -1 2343 if (!LegalOperations && 2344 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2345 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2346 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2347 } 2348 // fold (or c1, c2) -> c1|c2 2349 if (N0C && N1C) 2350 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2351 // canonicalize constant to RHS 2352 if (N0C && !N1C) 2353 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2354 // fold (or x, 0) -> x 2355 if (N1C && N1C->isNullValue()) 2356 return N0; 2357 // fold (or x, -1) -> -1 2358 if (N1C && N1C->isAllOnesValue()) 2359 return N1; 2360 // fold (or x, c) -> c iff (x & ~c) == 0 2361 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2362 return N1; 2363 // reassociate or 2364 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2365 if (ROR.getNode() != 0) 2366 return ROR; 2367 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2368 // iff (c1 & c2) == 0. 2369 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2370 isa<ConstantSDNode>(N0.getOperand(1))) { 2371 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2372 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2373 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2374 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2375 N0.getOperand(0), N1), 2376 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2377 } 2378 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2379 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2380 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2381 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2382 2383 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2384 LL.getValueType().isInteger()) { 2385 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2386 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2387 if (cast<ConstantSDNode>(LR)->isNullValue() && 2388 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2389 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2390 LR.getValueType(), LL, RL); 2391 AddToWorkList(ORNode.getNode()); 2392 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2393 } 2394 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2395 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2396 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2397 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2398 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2399 LR.getValueType(), LL, RL); 2400 AddToWorkList(ANDNode.getNode()); 2401 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2402 } 2403 } 2404 // canonicalize equivalent to ll == rl 2405 if (LL == RR && LR == RL) { 2406 Op1 = ISD::getSetCCSwappedOperands(Op1); 2407 std::swap(RL, RR); 2408 } 2409 if (LL == RL && LR == RR) { 2410 bool isInteger = LL.getValueType().isInteger(); 2411 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2412 if (Result != ISD::SETCC_INVALID && 2413 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2414 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2415 LL, LR, Result); 2416 } 2417 } 2418 2419 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2420 if (N0.getOpcode() == N1.getOpcode()) { 2421 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2422 if (Tmp.getNode()) return Tmp; 2423 } 2424 2425 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2426 if (N0.getOpcode() == ISD::AND && 2427 N1.getOpcode() == ISD::AND && 2428 N0.getOperand(1).getOpcode() == ISD::Constant && 2429 N1.getOperand(1).getOpcode() == ISD::Constant && 2430 // Don't increase # computations. 2431 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2432 // We can only do this xform if we know that bits from X that are set in C2 2433 // but not in C1 are already zero. Likewise for Y. 2434 const APInt &LHSMask = 2435 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2436 const APInt &RHSMask = 2437 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2438 2439 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2440 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2441 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2442 N0.getOperand(0), N1.getOperand(0)); 2443 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2444 DAG.getConstant(LHSMask | RHSMask, VT)); 2445 } 2446 } 2447 2448 // See if this is some rotate idiom. 2449 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2450 return SDValue(Rot, 0); 2451 2452 // Simplify the operands using demanded-bits information. 2453 if (!VT.isVector() && 2454 SimplifyDemandedBits(SDValue(N, 0))) 2455 return SDValue(N, 0); 2456 2457 return SDValue(); 2458} 2459 2460/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2461static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2462 if (Op.getOpcode() == ISD::AND) { 2463 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2464 Mask = Op.getOperand(1); 2465 Op = Op.getOperand(0); 2466 } else { 2467 return false; 2468 } 2469 } 2470 2471 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2472 Shift = Op; 2473 return true; 2474 } 2475 2476 return false; 2477} 2478 2479// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2480// idioms for rotate, and if the target supports rotation instructions, generate 2481// a rot[lr]. 2482SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2483 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2484 EVT VT = LHS.getValueType(); 2485 if (!TLI.isTypeLegal(VT)) return 0; 2486 2487 // The target must have at least one rotate flavor. 2488 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2489 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2490 if (!HasROTL && !HasROTR) return 0; 2491 2492 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2493 SDValue LHSShift; // The shift. 2494 SDValue LHSMask; // AND value if any. 2495 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2496 return 0; // Not part of a rotate. 2497 2498 SDValue RHSShift; // The shift. 2499 SDValue RHSMask; // AND value if any. 2500 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2501 return 0; // Not part of a rotate. 2502 2503 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2504 return 0; // Not shifting the same value. 2505 2506 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2507 return 0; // Shifts must disagree. 2508 2509 // Canonicalize shl to left side in a shl/srl pair. 2510 if (RHSShift.getOpcode() == ISD::SHL) { 2511 std::swap(LHS, RHS); 2512 std::swap(LHSShift, RHSShift); 2513 std::swap(LHSMask , RHSMask ); 2514 } 2515 2516 unsigned OpSizeInBits = VT.getSizeInBits(); 2517 SDValue LHSShiftArg = LHSShift.getOperand(0); 2518 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2519 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2520 2521 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2522 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2523 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2524 RHSShiftAmt.getOpcode() == ISD::Constant) { 2525 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2526 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2527 if ((LShVal + RShVal) != OpSizeInBits) 2528 return 0; 2529 2530 SDValue Rot; 2531 if (HasROTL) 2532 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2533 else 2534 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2535 2536 // If there is an AND of either shifted operand, apply it to the result. 2537 if (LHSMask.getNode() || RHSMask.getNode()) { 2538 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2539 2540 if (LHSMask.getNode()) { 2541 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2542 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2543 } 2544 if (RHSMask.getNode()) { 2545 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2546 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2547 } 2548 2549 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2550 } 2551 2552 return Rot.getNode(); 2553 } 2554 2555 // If there is a mask here, and we have a variable shift, we can't be sure 2556 // that we're masking out the right stuff. 2557 if (LHSMask.getNode() || RHSMask.getNode()) 2558 return 0; 2559 2560 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2561 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2562 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2563 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2564 if (ConstantSDNode *SUBC = 2565 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2566 if (SUBC->getAPIntValue() == OpSizeInBits) { 2567 if (HasROTL) 2568 return DAG.getNode(ISD::ROTL, DL, VT, 2569 LHSShiftArg, LHSShiftAmt).getNode(); 2570 else 2571 return DAG.getNode(ISD::ROTR, DL, VT, 2572 LHSShiftArg, RHSShiftAmt).getNode(); 2573 } 2574 } 2575 } 2576 2577 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2578 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2579 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2580 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2581 if (ConstantSDNode *SUBC = 2582 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2583 if (SUBC->getAPIntValue() == OpSizeInBits) { 2584 if (HasROTR) 2585 return DAG.getNode(ISD::ROTR, DL, VT, 2586 LHSShiftArg, RHSShiftAmt).getNode(); 2587 else 2588 return DAG.getNode(ISD::ROTL, DL, VT, 2589 LHSShiftArg, LHSShiftAmt).getNode(); 2590 } 2591 } 2592 } 2593 2594 // Look for sign/zext/any-extended or truncate cases: 2595 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2596 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2597 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2598 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2599 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2600 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2601 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2602 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2603 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2604 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2605 if (RExtOp0.getOpcode() == ISD::SUB && 2606 RExtOp0.getOperand(1) == LExtOp0) { 2607 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2608 // (rotl x, y) 2609 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2610 // (rotr x, (sub 32, y)) 2611 if (ConstantSDNode *SUBC = 2612 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2613 if (SUBC->getAPIntValue() == OpSizeInBits) { 2614 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2615 LHSShiftArg, 2616 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2617 } 2618 } 2619 } else if (LExtOp0.getOpcode() == ISD::SUB && 2620 RExtOp0 == LExtOp0.getOperand(1)) { 2621 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2622 // (rotr x, y) 2623 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2624 // (rotl x, (sub 32, y)) 2625 if (ConstantSDNode *SUBC = 2626 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2627 if (SUBC->getAPIntValue() == OpSizeInBits) { 2628 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2629 LHSShiftArg, 2630 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2631 } 2632 } 2633 } 2634 } 2635 2636 return 0; 2637} 2638 2639SDValue DAGCombiner::visitXOR(SDNode *N) { 2640 SDValue N0 = N->getOperand(0); 2641 SDValue N1 = N->getOperand(1); 2642 SDValue LHS, RHS, CC; 2643 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2644 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2645 EVT VT = N0.getValueType(); 2646 2647 // fold vector ops 2648 if (VT.isVector()) { 2649 SDValue FoldedVOp = SimplifyVBinOp(N); 2650 if (FoldedVOp.getNode()) return FoldedVOp; 2651 } 2652 2653 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2654 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2655 return DAG.getConstant(0, VT); 2656 // fold (xor x, undef) -> undef 2657 if (N0.getOpcode() == ISD::UNDEF) 2658 return N0; 2659 if (N1.getOpcode() == ISD::UNDEF) 2660 return N1; 2661 // fold (xor c1, c2) -> c1^c2 2662 if (N0C && N1C) 2663 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2664 // canonicalize constant to RHS 2665 if (N0C && !N1C) 2666 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2667 // fold (xor x, 0) -> x 2668 if (N1C && N1C->isNullValue()) 2669 return N0; 2670 // reassociate xor 2671 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2672 if (RXOR.getNode() != 0) 2673 return RXOR; 2674 2675 // fold !(x cc y) -> (x !cc y) 2676 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2677 bool isInt = LHS.getValueType().isInteger(); 2678 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2679 isInt); 2680 2681 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2682 switch (N0.getOpcode()) { 2683 default: 2684 llvm_unreachable("Unhandled SetCC Equivalent!"); 2685 case ISD::SETCC: 2686 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2687 case ISD::SELECT_CC: 2688 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2689 N0.getOperand(3), NotCC); 2690 } 2691 } 2692 } 2693 2694 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2695 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2696 N0.getNode()->hasOneUse() && 2697 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2698 SDValue V = N0.getOperand(0); 2699 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2700 DAG.getConstant(1, V.getValueType())); 2701 AddToWorkList(V.getNode()); 2702 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2703 } 2704 2705 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2706 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2707 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2708 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2709 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2710 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2711 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2712 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2713 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2714 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2715 } 2716 } 2717 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2718 if (N1C && N1C->isAllOnesValue() && 2719 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2720 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2721 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2722 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2723 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2724 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2725 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2726 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2727 } 2728 } 2729 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2730 if (N1C && N0.getOpcode() == ISD::XOR) { 2731 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2732 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2733 if (N00C) 2734 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2735 DAG.getConstant(N1C->getAPIntValue() ^ 2736 N00C->getAPIntValue(), VT)); 2737 if (N01C) 2738 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2739 DAG.getConstant(N1C->getAPIntValue() ^ 2740 N01C->getAPIntValue(), VT)); 2741 } 2742 // fold (xor x, x) -> 0 2743 if (N0 == N1) { 2744 if (!VT.isVector()) { 2745 return DAG.getConstant(0, VT); 2746 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2747 // Produce a vector of zeros. 2748 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2749 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2750 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2751 &Ops[0], Ops.size()); 2752 } 2753 } 2754 2755 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2756 if (N0.getOpcode() == N1.getOpcode()) { 2757 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2758 if (Tmp.getNode()) return Tmp; 2759 } 2760 2761 // Simplify the expression using non-local knowledge. 2762 if (!VT.isVector() && 2763 SimplifyDemandedBits(SDValue(N, 0))) 2764 return SDValue(N, 0); 2765 2766 return SDValue(); 2767} 2768 2769/// visitShiftByConstant - Handle transforms common to the three shifts, when 2770/// the shift amount is a constant. 2771SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2772 SDNode *LHS = N->getOperand(0).getNode(); 2773 if (!LHS->hasOneUse()) return SDValue(); 2774 2775 // We want to pull some binops through shifts, so that we have (and (shift)) 2776 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2777 // thing happens with address calculations, so it's important to canonicalize 2778 // it. 2779 bool HighBitSet = false; // Can we transform this if the high bit is set? 2780 2781 switch (LHS->getOpcode()) { 2782 default: return SDValue(); 2783 case ISD::OR: 2784 case ISD::XOR: 2785 HighBitSet = false; // We can only transform sra if the high bit is clear. 2786 break; 2787 case ISD::AND: 2788 HighBitSet = true; // We can only transform sra if the high bit is set. 2789 break; 2790 case ISD::ADD: 2791 if (N->getOpcode() != ISD::SHL) 2792 return SDValue(); // only shl(add) not sr[al](add). 2793 HighBitSet = false; // We can only transform sra if the high bit is clear. 2794 break; 2795 } 2796 2797 // We require the RHS of the binop to be a constant as well. 2798 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2799 if (!BinOpCst) return SDValue(); 2800 2801 // FIXME: disable this unless the input to the binop is a shift by a constant. 2802 // If it is not a shift, it pessimizes some common cases like: 2803 // 2804 // void foo(int *X, int i) { X[i & 1235] = 1; } 2805 // int bar(int *X, int i) { return X[i & 255]; } 2806 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2807 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2808 BinOpLHSVal->getOpcode() != ISD::SRA && 2809 BinOpLHSVal->getOpcode() != ISD::SRL) || 2810 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2811 return SDValue(); 2812 2813 EVT VT = N->getValueType(0); 2814 2815 // If this is a signed shift right, and the high bit is modified by the 2816 // logical operation, do not perform the transformation. The highBitSet 2817 // boolean indicates the value of the high bit of the constant which would 2818 // cause it to be modified for this operation. 2819 if (N->getOpcode() == ISD::SRA) { 2820 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2821 if (BinOpRHSSignSet != HighBitSet) 2822 return SDValue(); 2823 } 2824 2825 // Fold the constants, shifting the binop RHS by the shift amount. 2826 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2827 N->getValueType(0), 2828 LHS->getOperand(1), N->getOperand(1)); 2829 2830 // Create the new shift. 2831 SDValue NewShift = DAG.getNode(N->getOpcode(), 2832 LHS->getOperand(0).getDebugLoc(), 2833 VT, LHS->getOperand(0), N->getOperand(1)); 2834 2835 // Create the new binop. 2836 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2837} 2838 2839SDValue DAGCombiner::visitSHL(SDNode *N) { 2840 SDValue N0 = N->getOperand(0); 2841 SDValue N1 = N->getOperand(1); 2842 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2843 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2844 EVT VT = N0.getValueType(); 2845 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2846 2847 // fold (shl c1, c2) -> c1<<c2 2848 if (N0C && N1C) 2849 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2850 // fold (shl 0, x) -> 0 2851 if (N0C && N0C->isNullValue()) 2852 return N0; 2853 // fold (shl x, c >= size(x)) -> undef 2854 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2855 return DAG.getUNDEF(VT); 2856 // fold (shl x, 0) -> x 2857 if (N1C && N1C->isNullValue()) 2858 return N0; 2859 // if (shl x, c) is known to be zero, return 0 2860 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2861 APInt::getAllOnesValue(OpSizeInBits))) 2862 return DAG.getConstant(0, VT); 2863 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2864 if (N1.getOpcode() == ISD::TRUNCATE && 2865 N1.getOperand(0).getOpcode() == ISD::AND && 2866 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2867 SDValue N101 = N1.getOperand(0).getOperand(1); 2868 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2869 EVT TruncVT = N1.getValueType(); 2870 SDValue N100 = N1.getOperand(0).getOperand(0); 2871 APInt TruncC = N101C->getAPIntValue(); 2872 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 2873 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2874 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2875 DAG.getNode(ISD::TRUNCATE, 2876 N->getDebugLoc(), 2877 TruncVT, N100), 2878 DAG.getConstant(TruncC, TruncVT))); 2879 } 2880 } 2881 2882 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2883 return SDValue(N, 0); 2884 2885 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2886 if (N1C && N0.getOpcode() == ISD::SHL && 2887 N0.getOperand(1).getOpcode() == ISD::Constant) { 2888 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2889 uint64_t c2 = N1C->getZExtValue(); 2890 if (c1 + c2 > OpSizeInBits) 2891 return DAG.getConstant(0, VT); 2892 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2893 DAG.getConstant(c1 + c2, N1.getValueType())); 2894 } 2895 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2896 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2897 if (N1C && N0.getOpcode() == ISD::SRL && 2898 N0.getOperand(1).getOpcode() == ISD::Constant) { 2899 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2900 if (c1 < VT.getSizeInBits()) { 2901 uint64_t c2 = N1C->getZExtValue(); 2902 SDValue HiBitsMask = 2903 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2904 VT.getSizeInBits() - c1), 2905 VT); 2906 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2907 N0.getOperand(0), 2908 HiBitsMask); 2909 if (c2 > c1) 2910 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2911 DAG.getConstant(c2-c1, N1.getValueType())); 2912 else 2913 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2914 DAG.getConstant(c1-c2, N1.getValueType())); 2915 } 2916 } 2917 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2918 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2919 SDValue HiBitsMask = 2920 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2921 VT.getSizeInBits() - 2922 N1C->getZExtValue()), 2923 VT); 2924 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2925 HiBitsMask); 2926 } 2927 2928 if (N1C) { 2929 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 2930 if (NewSHL.getNode()) 2931 return NewSHL; 2932 } 2933 2934 return SDValue(); 2935} 2936 2937SDValue DAGCombiner::visitSRA(SDNode *N) { 2938 SDValue N0 = N->getOperand(0); 2939 SDValue N1 = N->getOperand(1); 2940 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2941 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2942 EVT VT = N0.getValueType(); 2943 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2944 2945 // fold (sra c1, c2) -> (sra c1, c2) 2946 if (N0C && N1C) 2947 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2948 // fold (sra 0, x) -> 0 2949 if (N0C && N0C->isNullValue()) 2950 return N0; 2951 // fold (sra -1, x) -> -1 2952 if (N0C && N0C->isAllOnesValue()) 2953 return N0; 2954 // fold (sra x, (setge c, size(x))) -> undef 2955 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2956 return DAG.getUNDEF(VT); 2957 // fold (sra x, 0) -> x 2958 if (N1C && N1C->isNullValue()) 2959 return N0; 2960 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2961 // sext_inreg. 2962 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2963 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2964 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2965 if (VT.isVector()) 2966 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2967 ExtVT, VT.getVectorNumElements()); 2968 if ((!LegalOperations || 2969 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2970 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2971 N0.getOperand(0), DAG.getValueType(ExtVT)); 2972 } 2973 2974 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2975 if (N1C && N0.getOpcode() == ISD::SRA) { 2976 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2977 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2978 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2979 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2980 DAG.getConstant(Sum, N1C->getValueType(0))); 2981 } 2982 } 2983 2984 // fold (sra (shl X, m), (sub result_size, n)) 2985 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2986 // result_size - n != m. 2987 // If truncate is free for the target sext(shl) is likely to result in better 2988 // code. 2989 if (N0.getOpcode() == ISD::SHL) { 2990 // Get the two constanst of the shifts, CN0 = m, CN = n. 2991 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2992 if (N01C && N1C) { 2993 // Determine what the truncate's result bitsize and type would be. 2994 EVT TruncVT = 2995 EVT::getIntegerVT(*DAG.getContext(), 2996 OpSizeInBits - N1C->getZExtValue()); 2997 // Determine the residual right-shift amount. 2998 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2999 3000 // If the shift is not a no-op (in which case this should be just a sign 3001 // extend already), the truncated to type is legal, sign_extend is legal 3002 // on that type, and the truncate to that type is both legal and free, 3003 // perform the transform. 3004 if ((ShiftAmt > 0) && 3005 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3006 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3007 TLI.isTruncateFree(VT, TruncVT)) { 3008 3009 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 3010 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3011 N0.getOperand(0), Amt); 3012 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3013 Shift); 3014 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3015 N->getValueType(0), Trunc); 3016 } 3017 } 3018 } 3019 3020 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3021 if (N1.getOpcode() == ISD::TRUNCATE && 3022 N1.getOperand(0).getOpcode() == ISD::AND && 3023 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3024 SDValue N101 = N1.getOperand(0).getOperand(1); 3025 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3026 EVT TruncVT = N1.getValueType(); 3027 SDValue N100 = N1.getOperand(0).getOperand(0); 3028 APInt TruncC = N101C->getAPIntValue(); 3029 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3030 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3031 DAG.getNode(ISD::AND, N->getDebugLoc(), 3032 TruncVT, 3033 DAG.getNode(ISD::TRUNCATE, 3034 N->getDebugLoc(), 3035 TruncVT, N100), 3036 DAG.getConstant(TruncC, TruncVT))); 3037 } 3038 } 3039 3040 // Simplify, based on bits shifted out of the LHS. 3041 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3042 return SDValue(N, 0); 3043 3044 3045 // If the sign bit is known to be zero, switch this to a SRL. 3046 if (DAG.SignBitIsZero(N0)) 3047 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3048 3049 if (N1C) { 3050 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3051 if (NewSRA.getNode()) 3052 return NewSRA; 3053 } 3054 3055 return SDValue(); 3056} 3057 3058SDValue DAGCombiner::visitSRL(SDNode *N) { 3059 SDValue N0 = N->getOperand(0); 3060 SDValue N1 = N->getOperand(1); 3061 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3062 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3063 EVT VT = N0.getValueType(); 3064 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3065 3066 // fold (srl c1, c2) -> c1 >>u c2 3067 if (N0C && N1C) 3068 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3069 // fold (srl 0, x) -> 0 3070 if (N0C && N0C->isNullValue()) 3071 return N0; 3072 // fold (srl x, c >= size(x)) -> undef 3073 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3074 return DAG.getUNDEF(VT); 3075 // fold (srl x, 0) -> x 3076 if (N1C && N1C->isNullValue()) 3077 return N0; 3078 // if (srl x, c) is known to be zero, return 0 3079 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3080 APInt::getAllOnesValue(OpSizeInBits))) 3081 return DAG.getConstant(0, VT); 3082 3083 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3084 if (N1C && N0.getOpcode() == ISD::SRL && 3085 N0.getOperand(1).getOpcode() == ISD::Constant) { 3086 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3087 uint64_t c2 = N1C->getZExtValue(); 3088 if (c1 + c2 > OpSizeInBits) 3089 return DAG.getConstant(0, VT); 3090 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3091 DAG.getConstant(c1 + c2, N1.getValueType())); 3092 } 3093 3094 // fold (srl (shl x, c), c) -> (and x, cst2) 3095 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3096 N0.getValueSizeInBits() <= 64) { 3097 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3098 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3099 DAG.getConstant(~0ULL >> ShAmt, VT)); 3100 } 3101 3102 3103 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3104 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3105 // Shifting in all undef bits? 3106 EVT SmallVT = N0.getOperand(0).getValueType(); 3107 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3108 return DAG.getUNDEF(VT); 3109 3110 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3111 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3112 N0.getOperand(0), N1); 3113 AddToWorkList(SmallShift.getNode()); 3114 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3115 } 3116 } 3117 3118 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3119 // bit, which is unmodified by sra. 3120 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3121 if (N0.getOpcode() == ISD::SRA) 3122 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3123 } 3124 3125 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3126 if (N1C && N0.getOpcode() == ISD::CTLZ && 3127 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3128 APInt KnownZero, KnownOne; 3129 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3130 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3131 3132 // If any of the input bits are KnownOne, then the input couldn't be all 3133 // zeros, thus the result of the srl will always be zero. 3134 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3135 3136 // If all of the bits input the to ctlz node are known to be zero, then 3137 // the result of the ctlz is "32" and the result of the shift is one. 3138 APInt UnknownBits = ~KnownZero & Mask; 3139 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3140 3141 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3142 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3143 // Okay, we know that only that the single bit specified by UnknownBits 3144 // could be set on input to the CTLZ node. If this bit is set, the SRL 3145 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3146 // to an SRL/XOR pair, which is likely to simplify more. 3147 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3148 SDValue Op = N0.getOperand(0); 3149 3150 if (ShAmt) { 3151 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3152 DAG.getConstant(ShAmt, getShiftAmountTy())); 3153 AddToWorkList(Op.getNode()); 3154 } 3155 3156 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3157 Op, DAG.getConstant(1, VT)); 3158 } 3159 } 3160 3161 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3162 if (N1.getOpcode() == ISD::TRUNCATE && 3163 N1.getOperand(0).getOpcode() == ISD::AND && 3164 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3165 SDValue N101 = N1.getOperand(0).getOperand(1); 3166 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3167 EVT TruncVT = N1.getValueType(); 3168 SDValue N100 = N1.getOperand(0).getOperand(0); 3169 APInt TruncC = N101C->getAPIntValue(); 3170 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3171 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3172 DAG.getNode(ISD::AND, N->getDebugLoc(), 3173 TruncVT, 3174 DAG.getNode(ISD::TRUNCATE, 3175 N->getDebugLoc(), 3176 TruncVT, N100), 3177 DAG.getConstant(TruncC, TruncVT))); 3178 } 3179 } 3180 3181 // fold operands of srl based on knowledge that the low bits are not 3182 // demanded. 3183 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3184 return SDValue(N, 0); 3185 3186 if (N1C) { 3187 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3188 if (NewSRL.getNode()) 3189 return NewSRL; 3190 } 3191 3192 // Attempt to convert a srl of a load into a narrower zero-extending load. 3193 SDValue NarrowLoad = ReduceLoadWidth(N); 3194 if (NarrowLoad.getNode()) 3195 return NarrowLoad; 3196 3197 // Here is a common situation. We want to optimize: 3198 // 3199 // %a = ... 3200 // %b = and i32 %a, 2 3201 // %c = srl i32 %b, 1 3202 // brcond i32 %c ... 3203 // 3204 // into 3205 // 3206 // %a = ... 3207 // %b = and %a, 2 3208 // %c = setcc eq %b, 0 3209 // brcond %c ... 3210 // 3211 // However when after the source operand of SRL is optimized into AND, the SRL 3212 // itself may not be optimized further. Look for it and add the BRCOND into 3213 // the worklist. 3214 if (N->hasOneUse()) { 3215 SDNode *Use = *N->use_begin(); 3216 if (Use->getOpcode() == ISD::BRCOND) 3217 AddToWorkList(Use); 3218 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3219 // Also look pass the truncate. 3220 Use = *Use->use_begin(); 3221 if (Use->getOpcode() == ISD::BRCOND) 3222 AddToWorkList(Use); 3223 } 3224 } 3225 3226 return SDValue(); 3227} 3228 3229SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3230 SDValue N0 = N->getOperand(0); 3231 EVT VT = N->getValueType(0); 3232 3233 // fold (ctlz c1) -> c2 3234 if (isa<ConstantSDNode>(N0)) 3235 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3236 return SDValue(); 3237} 3238 3239SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3240 SDValue N0 = N->getOperand(0); 3241 EVT VT = N->getValueType(0); 3242 3243 // fold (cttz c1) -> c2 3244 if (isa<ConstantSDNode>(N0)) 3245 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3246 return SDValue(); 3247} 3248 3249SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3250 SDValue N0 = N->getOperand(0); 3251 EVT VT = N->getValueType(0); 3252 3253 // fold (ctpop c1) -> c2 3254 if (isa<ConstantSDNode>(N0)) 3255 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3256 return SDValue(); 3257} 3258 3259SDValue DAGCombiner::visitSELECT(SDNode *N) { 3260 SDValue N0 = N->getOperand(0); 3261 SDValue N1 = N->getOperand(1); 3262 SDValue N2 = N->getOperand(2); 3263 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3264 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3265 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3266 EVT VT = N->getValueType(0); 3267 EVT VT0 = N0.getValueType(); 3268 3269 // fold (select C, X, X) -> X 3270 if (N1 == N2) 3271 return N1; 3272 // fold (select true, X, Y) -> X 3273 if (N0C && !N0C->isNullValue()) 3274 return N1; 3275 // fold (select false, X, Y) -> Y 3276 if (N0C && N0C->isNullValue()) 3277 return N2; 3278 // fold (select C, 1, X) -> (or C, X) 3279 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3280 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3281 // fold (select C, 0, 1) -> (xor C, 1) 3282 if (VT.isInteger() && 3283 (VT0 == MVT::i1 || 3284 (VT0.isInteger() && 3285 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3286 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3287 SDValue XORNode; 3288 if (VT == VT0) 3289 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3290 N0, DAG.getConstant(1, VT0)); 3291 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3292 N0, DAG.getConstant(1, VT0)); 3293 AddToWorkList(XORNode.getNode()); 3294 if (VT.bitsGT(VT0)) 3295 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3296 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3297 } 3298 // fold (select C, 0, X) -> (and (not C), X) 3299 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3300 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3301 AddToWorkList(NOTNode.getNode()); 3302 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3303 } 3304 // fold (select C, X, 1) -> (or (not C), X) 3305 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3306 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3307 AddToWorkList(NOTNode.getNode()); 3308 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3309 } 3310 // fold (select C, X, 0) -> (and C, X) 3311 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3312 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3313 // fold (select X, X, Y) -> (or X, Y) 3314 // fold (select X, 1, Y) -> (or X, Y) 3315 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3316 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3317 // fold (select X, Y, X) -> (and X, Y) 3318 // fold (select X, Y, 0) -> (and X, Y) 3319 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3320 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3321 3322 // If we can fold this based on the true/false value, do so. 3323 if (SimplifySelectOps(N, N1, N2)) 3324 return SDValue(N, 0); // Don't revisit N. 3325 3326 // fold selects based on a setcc into other things, such as min/max/abs 3327 if (N0.getOpcode() == ISD::SETCC) { 3328 // FIXME: 3329 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3330 // having to say they don't support SELECT_CC on every type the DAG knows 3331 // about, since there is no way to mark an opcode illegal at all value types 3332 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3333 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3334 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3335 N0.getOperand(0), N0.getOperand(1), 3336 N1, N2, N0.getOperand(2)); 3337 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3338 } 3339 3340 return SDValue(); 3341} 3342 3343SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3344 SDValue N0 = N->getOperand(0); 3345 SDValue N1 = N->getOperand(1); 3346 SDValue N2 = N->getOperand(2); 3347 SDValue N3 = N->getOperand(3); 3348 SDValue N4 = N->getOperand(4); 3349 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3350 3351 // fold select_cc lhs, rhs, x, x, cc -> x 3352 if (N2 == N3) 3353 return N2; 3354 3355 // Determine if the condition we're dealing with is constant 3356 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3357 N0, N1, CC, N->getDebugLoc(), false); 3358 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3359 3360 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3361 if (!SCCC->isNullValue()) 3362 return N2; // cond always true -> true val 3363 else 3364 return N3; // cond always false -> false val 3365 } 3366 3367 // Fold to a simpler select_cc 3368 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3369 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3370 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3371 SCC.getOperand(2)); 3372 3373 // If we can fold this based on the true/false value, do so. 3374 if (SimplifySelectOps(N, N2, N3)) 3375 return SDValue(N, 0); // Don't revisit N. 3376 3377 // fold select_cc into other things, such as min/max/abs 3378 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3379} 3380 3381SDValue DAGCombiner::visitSETCC(SDNode *N) { 3382 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3383 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3384 N->getDebugLoc()); 3385} 3386 3387// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3388// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3389// transformation. Returns true if extension are possible and the above 3390// mentioned transformation is profitable. 3391static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3392 unsigned ExtOpc, 3393 SmallVector<SDNode*, 4> &ExtendNodes, 3394 const TargetLowering &TLI) { 3395 bool HasCopyToRegUses = false; 3396 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3397 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3398 UE = N0.getNode()->use_end(); 3399 UI != UE; ++UI) { 3400 SDNode *User = *UI; 3401 if (User == N) 3402 continue; 3403 if (UI.getUse().getResNo() != N0.getResNo()) 3404 continue; 3405 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3406 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3407 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3408 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3409 // Sign bits will be lost after a zext. 3410 return false; 3411 bool Add = false; 3412 for (unsigned i = 0; i != 2; ++i) { 3413 SDValue UseOp = User->getOperand(i); 3414 if (UseOp == N0) 3415 continue; 3416 if (!isa<ConstantSDNode>(UseOp)) 3417 return false; 3418 Add = true; 3419 } 3420 if (Add) 3421 ExtendNodes.push_back(User); 3422 continue; 3423 } 3424 // If truncates aren't free and there are users we can't 3425 // extend, it isn't worthwhile. 3426 if (!isTruncFree) 3427 return false; 3428 // Remember if this value is live-out. 3429 if (User->getOpcode() == ISD::CopyToReg) 3430 HasCopyToRegUses = true; 3431 } 3432 3433 if (HasCopyToRegUses) { 3434 bool BothLiveOut = false; 3435 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3436 UI != UE; ++UI) { 3437 SDUse &Use = UI.getUse(); 3438 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3439 BothLiveOut = true; 3440 break; 3441 } 3442 } 3443 if (BothLiveOut) 3444 // Both unextended and extended values are live out. There had better be 3445 // a good reason for the transformation. 3446 return ExtendNodes.size(); 3447 } 3448 return true; 3449} 3450 3451SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3452 SDValue N0 = N->getOperand(0); 3453 EVT VT = N->getValueType(0); 3454 3455 // fold (sext c1) -> c1 3456 if (isa<ConstantSDNode>(N0)) 3457 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3458 3459 // fold (sext (sext x)) -> (sext x) 3460 // fold (sext (aext x)) -> (sext x) 3461 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3462 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3463 N0.getOperand(0)); 3464 3465 if (N0.getOpcode() == ISD::TRUNCATE) { 3466 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3467 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3468 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3469 if (NarrowLoad.getNode()) { 3470 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3471 if (NarrowLoad.getNode() != N0.getNode()) { 3472 CombineTo(N0.getNode(), NarrowLoad); 3473 // CombineTo deleted the truncate, if needed, but not what's under it. 3474 AddToWorkList(oye); 3475 } 3476 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3477 } 3478 3479 // See if the value being truncated is already sign extended. If so, just 3480 // eliminate the trunc/sext pair. 3481 SDValue Op = N0.getOperand(0); 3482 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3483 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3484 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3485 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3486 3487 if (OpBits == DestBits) { 3488 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3489 // bits, it is already ready. 3490 if (NumSignBits > DestBits-MidBits) 3491 return Op; 3492 } else if (OpBits < DestBits) { 3493 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3494 // bits, just sext from i32. 3495 if (NumSignBits > OpBits-MidBits) 3496 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3497 } else { 3498 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3499 // bits, just truncate to i32. 3500 if (NumSignBits > OpBits-MidBits) 3501 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3502 } 3503 3504 // fold (sext (truncate x)) -> (sextinreg x). 3505 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3506 N0.getValueType())) { 3507 if (OpBits < DestBits) 3508 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3509 else if (OpBits > DestBits) 3510 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3511 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3512 DAG.getValueType(N0.getValueType())); 3513 } 3514 } 3515 3516 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3517 if (ISD::isNON_EXTLoad(N0.getNode()) && 3518 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3519 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3520 bool DoXform = true; 3521 SmallVector<SDNode*, 4> SetCCs; 3522 if (!N0.hasOneUse()) 3523 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3524 if (DoXform) { 3525 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3526 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 3527 LN0->getChain(), 3528 LN0->getBasePtr(), LN0->getPointerInfo(), 3529 N0.getValueType(), 3530 LN0->isVolatile(), LN0->isNonTemporal(), 3531 LN0->getAlignment()); 3532 CombineTo(N, ExtLoad); 3533 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3534 N0.getValueType(), ExtLoad); 3535 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3536 3537 // Extend SetCC uses if necessary. 3538 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3539 SDNode *SetCC = SetCCs[i]; 3540 SmallVector<SDValue, 4> Ops; 3541 3542 for (unsigned j = 0; j != 2; ++j) { 3543 SDValue SOp = SetCC->getOperand(j); 3544 if (SOp == Trunc) 3545 Ops.push_back(ExtLoad); 3546 else 3547 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3548 N->getDebugLoc(), VT, SOp)); 3549 } 3550 3551 Ops.push_back(SetCC->getOperand(2)); 3552 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3553 SetCC->getValueType(0), 3554 &Ops[0], Ops.size())); 3555 } 3556 3557 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3558 } 3559 } 3560 3561 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3562 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3563 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3564 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3565 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3566 EVT MemVT = LN0->getMemoryVT(); 3567 if ((!LegalOperations && !LN0->isVolatile()) || 3568 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3569 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 3570 LN0->getChain(), 3571 LN0->getBasePtr(), LN0->getPointerInfo(), 3572 MemVT, 3573 LN0->isVolatile(), LN0->isNonTemporal(), 3574 LN0->getAlignment()); 3575 CombineTo(N, ExtLoad); 3576 CombineTo(N0.getNode(), 3577 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3578 N0.getValueType(), ExtLoad), 3579 ExtLoad.getValue(1)); 3580 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3581 } 3582 } 3583 3584 if (N0.getOpcode() == ISD::SETCC) { 3585 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3586 // Only do this before legalize for now. 3587 if (VT.isVector() && !LegalOperations) { 3588 EVT N0VT = N0.getOperand(0).getValueType(); 3589 // We know that the # elements of the results is the same as the 3590 // # elements of the compare (and the # elements of the compare result 3591 // for that matter). Check to see that they are the same size. If so, 3592 // we know that the element size of the sext'd result matches the 3593 // element size of the compare operands. 3594 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3595 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3596 N0.getOperand(1), 3597 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3598 // If the desired elements are smaller or larger than the source 3599 // elements we can use a matching integer vector type and then 3600 // truncate/sign extend 3601 else { 3602 EVT MatchingElementType = 3603 EVT::getIntegerVT(*DAG.getContext(), 3604 N0VT.getScalarType().getSizeInBits()); 3605 EVT MatchingVectorType = 3606 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3607 N0VT.getVectorNumElements()); 3608 SDValue VsetCC = 3609 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3610 N0.getOperand(1), 3611 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3612 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3613 } 3614 } 3615 3616 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3617 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3618 SDValue NegOne = 3619 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3620 SDValue SCC = 3621 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3622 NegOne, DAG.getConstant(0, VT), 3623 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3624 if (SCC.getNode()) return SCC; 3625 if (!LegalOperations || 3626 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3627 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3628 DAG.getSetCC(N->getDebugLoc(), 3629 TLI.getSetCCResultType(VT), 3630 N0.getOperand(0), N0.getOperand(1), 3631 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3632 NegOne, DAG.getConstant(0, VT)); 3633 } 3634 3635 // fold (sext x) -> (zext x) if the sign bit is known zero. 3636 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3637 DAG.SignBitIsZero(N0)) 3638 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3639 3640 return SDValue(); 3641} 3642 3643SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3644 SDValue N0 = N->getOperand(0); 3645 EVT VT = N->getValueType(0); 3646 3647 // fold (zext c1) -> c1 3648 if (isa<ConstantSDNode>(N0)) 3649 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3650 // fold (zext (zext x)) -> (zext x) 3651 // fold (zext (aext x)) -> (zext x) 3652 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3653 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3654 N0.getOperand(0)); 3655 3656 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3657 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3658 if (N0.getOpcode() == ISD::TRUNCATE) { 3659 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3660 if (NarrowLoad.getNode()) { 3661 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3662 if (NarrowLoad.getNode() != N0.getNode()) { 3663 CombineTo(N0.getNode(), NarrowLoad); 3664 // CombineTo deleted the truncate, if needed, but not what's under it. 3665 AddToWorkList(oye); 3666 } 3667 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3668 } 3669 } 3670 3671 // fold (zext (truncate x)) -> (and x, mask) 3672 if (N0.getOpcode() == ISD::TRUNCATE && 3673 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3674 3675 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3676 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 3677 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3678 if (NarrowLoad.getNode()) { 3679 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3680 if (NarrowLoad.getNode() != N0.getNode()) { 3681 CombineTo(N0.getNode(), NarrowLoad); 3682 // CombineTo deleted the truncate, if needed, but not what's under it. 3683 AddToWorkList(oye); 3684 } 3685 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3686 } 3687 3688 SDValue Op = N0.getOperand(0); 3689 if (Op.getValueType().bitsLT(VT)) { 3690 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3691 } else if (Op.getValueType().bitsGT(VT)) { 3692 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3693 } 3694 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3695 N0.getValueType().getScalarType()); 3696 } 3697 3698 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3699 // if either of the casts is not free. 3700 if (N0.getOpcode() == ISD::AND && 3701 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3702 N0.getOperand(1).getOpcode() == ISD::Constant && 3703 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3704 N0.getValueType()) || 3705 !TLI.isZExtFree(N0.getValueType(), VT))) { 3706 SDValue X = N0.getOperand(0).getOperand(0); 3707 if (X.getValueType().bitsLT(VT)) { 3708 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3709 } else if (X.getValueType().bitsGT(VT)) { 3710 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3711 } 3712 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3713 Mask = Mask.zext(VT.getSizeInBits()); 3714 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3715 X, DAG.getConstant(Mask, VT)); 3716 } 3717 3718 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3719 if (ISD::isNON_EXTLoad(N0.getNode()) && 3720 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3721 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3722 bool DoXform = true; 3723 SmallVector<SDNode*, 4> SetCCs; 3724 if (!N0.hasOneUse()) 3725 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3726 if (DoXform) { 3727 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3728 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(), 3729 LN0->getChain(), 3730 LN0->getBasePtr(), LN0->getPointerInfo(), 3731 N0.getValueType(), 3732 LN0->isVolatile(), LN0->isNonTemporal(), 3733 LN0->getAlignment()); 3734 CombineTo(N, ExtLoad); 3735 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3736 N0.getValueType(), ExtLoad); 3737 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3738 3739 // Extend SetCC uses if necessary. 3740 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3741 SDNode *SetCC = SetCCs[i]; 3742 SmallVector<SDValue, 4> Ops; 3743 3744 for (unsigned j = 0; j != 2; ++j) { 3745 SDValue SOp = SetCC->getOperand(j); 3746 if (SOp == Trunc) 3747 Ops.push_back(ExtLoad); 3748 else 3749 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3750 N->getDebugLoc(), VT, SOp)); 3751 } 3752 3753 Ops.push_back(SetCC->getOperand(2)); 3754 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3755 SetCC->getValueType(0), 3756 &Ops[0], Ops.size())); 3757 } 3758 3759 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3760 } 3761 } 3762 3763 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3764 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3765 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3766 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3767 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3768 EVT MemVT = LN0->getMemoryVT(); 3769 if ((!LegalOperations && !LN0->isVolatile()) || 3770 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3771 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(), 3772 LN0->getChain(), 3773 LN0->getBasePtr(), LN0->getPointerInfo(), 3774 MemVT, 3775 LN0->isVolatile(), LN0->isNonTemporal(), 3776 LN0->getAlignment()); 3777 CombineTo(N, ExtLoad); 3778 CombineTo(N0.getNode(), 3779 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3780 ExtLoad), 3781 ExtLoad.getValue(1)); 3782 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3783 } 3784 } 3785 3786 if (N0.getOpcode() == ISD::SETCC) { 3787 if (!LegalOperations && VT.isVector()) { 3788 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 3789 // Only do this before legalize for now. 3790 EVT N0VT = N0.getOperand(0).getValueType(); 3791 EVT EltVT = VT.getVectorElementType(); 3792 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 3793 DAG.getConstant(1, EltVT)); 3794 if (VT.getSizeInBits() == N0VT.getSizeInBits()) { 3795 // We know that the # elements of the results is the same as the 3796 // # elements of the compare (and the # elements of the compare result 3797 // for that matter). Check to see that they are the same size. If so, 3798 // we know that the element size of the sext'd result matches the 3799 // element size of the compare operands. 3800 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3801 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3802 N0.getOperand(1), 3803 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3804 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3805 &OneOps[0], OneOps.size())); 3806 } else { 3807 // If the desired elements are smaller or larger than the source 3808 // elements we can use a matching integer vector type and then 3809 // truncate/sign extend 3810 EVT MatchingElementType = 3811 EVT::getIntegerVT(*DAG.getContext(), 3812 N0VT.getScalarType().getSizeInBits()); 3813 EVT MatchingVectorType = 3814 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3815 N0VT.getVectorNumElements()); 3816 SDValue VsetCC = 3817 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3818 N0.getOperand(1), 3819 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3820 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3821 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 3822 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3823 &OneOps[0], OneOps.size())); 3824 } 3825 } 3826 3827 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3828 SDValue SCC = 3829 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3830 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3831 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3832 if (SCC.getNode()) return SCC; 3833 } 3834 3835 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3836 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3837 isa<ConstantSDNode>(N0.getOperand(1)) && 3838 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3839 N0.hasOneUse()) { 3840 if (N0.getOpcode() == ISD::SHL) { 3841 // If the original shl may be shifting out bits, do not perform this 3842 // transformation. 3843 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3844 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3845 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3846 if (ShAmt > KnownZeroBits) 3847 return SDValue(); 3848 } 3849 DebugLoc dl = N->getDebugLoc(); 3850 return DAG.getNode(N0.getOpcode(), dl, VT, 3851 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3852 DAG.getNode(ISD::ZERO_EXTEND, dl, 3853 N0.getOperand(1).getValueType(), 3854 N0.getOperand(1))); 3855 } 3856 3857 return SDValue(); 3858} 3859 3860SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3861 SDValue N0 = N->getOperand(0); 3862 EVT VT = N->getValueType(0); 3863 3864 // fold (aext c1) -> c1 3865 if (isa<ConstantSDNode>(N0)) 3866 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3867 // fold (aext (aext x)) -> (aext x) 3868 // fold (aext (zext x)) -> (zext x) 3869 // fold (aext (sext x)) -> (sext x) 3870 if (N0.getOpcode() == ISD::ANY_EXTEND || 3871 N0.getOpcode() == ISD::ZERO_EXTEND || 3872 N0.getOpcode() == ISD::SIGN_EXTEND) 3873 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3874 3875 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3876 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3877 if (N0.getOpcode() == ISD::TRUNCATE) { 3878 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3879 if (NarrowLoad.getNode()) { 3880 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3881 if (NarrowLoad.getNode() != N0.getNode()) { 3882 CombineTo(N0.getNode(), NarrowLoad); 3883 // CombineTo deleted the truncate, if needed, but not what's under it. 3884 AddToWorkList(oye); 3885 } 3886 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3887 } 3888 } 3889 3890 // fold (aext (truncate x)) 3891 if (N0.getOpcode() == ISD::TRUNCATE) { 3892 SDValue TruncOp = N0.getOperand(0); 3893 if (TruncOp.getValueType() == VT) 3894 return TruncOp; // x iff x size == zext size. 3895 if (TruncOp.getValueType().bitsGT(VT)) 3896 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3897 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3898 } 3899 3900 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3901 // if the trunc is not free. 3902 if (N0.getOpcode() == ISD::AND && 3903 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3904 N0.getOperand(1).getOpcode() == ISD::Constant && 3905 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3906 N0.getValueType())) { 3907 SDValue X = N0.getOperand(0).getOperand(0); 3908 if (X.getValueType().bitsLT(VT)) { 3909 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3910 } else if (X.getValueType().bitsGT(VT)) { 3911 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3912 } 3913 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3914 Mask = Mask.zext(VT.getSizeInBits()); 3915 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3916 X, DAG.getConstant(Mask, VT)); 3917 } 3918 3919 // fold (aext (load x)) -> (aext (truncate (extload x))) 3920 if (ISD::isNON_EXTLoad(N0.getNode()) && 3921 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3922 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3923 bool DoXform = true; 3924 SmallVector<SDNode*, 4> SetCCs; 3925 if (!N0.hasOneUse()) 3926 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3927 if (DoXform) { 3928 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3929 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(), 3930 LN0->getChain(), 3931 LN0->getBasePtr(), LN0->getPointerInfo(), 3932 N0.getValueType(), 3933 LN0->isVolatile(), LN0->isNonTemporal(), 3934 LN0->getAlignment()); 3935 CombineTo(N, ExtLoad); 3936 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3937 N0.getValueType(), ExtLoad); 3938 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3939 3940 // Extend SetCC uses if necessary. 3941 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3942 SDNode *SetCC = SetCCs[i]; 3943 SmallVector<SDValue, 4> Ops; 3944 3945 for (unsigned j = 0; j != 2; ++j) { 3946 SDValue SOp = SetCC->getOperand(j); 3947 if (SOp == Trunc) 3948 Ops.push_back(ExtLoad); 3949 else 3950 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3951 N->getDebugLoc(), VT, SOp)); 3952 } 3953 3954 Ops.push_back(SetCC->getOperand(2)); 3955 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3956 SetCC->getValueType(0), 3957 &Ops[0], Ops.size())); 3958 } 3959 3960 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3961 } 3962 } 3963 3964 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3965 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3966 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3967 if (N0.getOpcode() == ISD::LOAD && 3968 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3969 N0.hasOneUse()) { 3970 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3971 EVT MemVT = LN0->getMemoryVT(); 3972 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3973 N->getDebugLoc(), 3974 LN0->getChain(), LN0->getBasePtr(), 3975 LN0->getPointerInfo(), MemVT, 3976 LN0->isVolatile(), LN0->isNonTemporal(), 3977 LN0->getAlignment()); 3978 CombineTo(N, ExtLoad); 3979 CombineTo(N0.getNode(), 3980 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3981 N0.getValueType(), ExtLoad), 3982 ExtLoad.getValue(1)); 3983 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3984 } 3985 3986 if (N0.getOpcode() == ISD::SETCC) { 3987 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 3988 // Only do this before legalize for now. 3989 if (VT.isVector() && !LegalOperations) { 3990 EVT N0VT = N0.getOperand(0).getValueType(); 3991 // We know that the # elements of the results is the same as the 3992 // # elements of the compare (and the # elements of the compare result 3993 // for that matter). Check to see that they are the same size. If so, 3994 // we know that the element size of the sext'd result matches the 3995 // element size of the compare operands. 3996 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3997 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3998 N0.getOperand(1), 3999 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4000 // If the desired elements are smaller or larger than the source 4001 // elements we can use a matching integer vector type and then 4002 // truncate/sign extend 4003 else { 4004 EVT MatchingElementType = 4005 EVT::getIntegerVT(*DAG.getContext(), 4006 N0VT.getScalarType().getSizeInBits()); 4007 EVT MatchingVectorType = 4008 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4009 N0VT.getVectorNumElements()); 4010 SDValue VsetCC = 4011 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4012 N0.getOperand(1), 4013 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4014 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4015 } 4016 } 4017 4018 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4019 SDValue SCC = 4020 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4021 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4022 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4023 if (SCC.getNode()) 4024 return SCC; 4025 } 4026 4027 return SDValue(); 4028} 4029 4030/// GetDemandedBits - See if the specified operand can be simplified with the 4031/// knowledge that only the bits specified by Mask are used. If so, return the 4032/// simpler operand, otherwise return a null SDValue. 4033SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4034 switch (V.getOpcode()) { 4035 default: break; 4036 case ISD::OR: 4037 case ISD::XOR: 4038 // If the LHS or RHS don't contribute bits to the or, drop them. 4039 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4040 return V.getOperand(1); 4041 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4042 return V.getOperand(0); 4043 break; 4044 case ISD::SRL: 4045 // Only look at single-use SRLs. 4046 if (!V.getNode()->hasOneUse()) 4047 break; 4048 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4049 // See if we can recursively simplify the LHS. 4050 unsigned Amt = RHSC->getZExtValue(); 4051 4052 // Watch out for shift count overflow though. 4053 if (Amt >= Mask.getBitWidth()) break; 4054 APInt NewMask = Mask << Amt; 4055 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4056 if (SimplifyLHS.getNode()) 4057 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4058 SimplifyLHS, V.getOperand(1)); 4059 } 4060 } 4061 return SDValue(); 4062} 4063 4064/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4065/// bits and then truncated to a narrower type and where N is a multiple 4066/// of number of bits of the narrower type, transform it to a narrower load 4067/// from address + N / num of bits of new type. If the result is to be 4068/// extended, also fold the extension to form a extending load. 4069SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4070 unsigned Opc = N->getOpcode(); 4071 4072 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4073 SDValue N0 = N->getOperand(0); 4074 EVT VT = N->getValueType(0); 4075 EVT ExtVT = VT; 4076 4077 // This transformation isn't valid for vector loads. 4078 if (VT.isVector()) 4079 return SDValue(); 4080 4081 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4082 // extended to VT. 4083 if (Opc == ISD::SIGN_EXTEND_INREG) { 4084 ExtType = ISD::SEXTLOAD; 4085 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4086 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 4087 return SDValue(); 4088 } else if (Opc == ISD::SRL) { 4089 // Annother special-case: SRL is basically zero-extending a narrower 4090 // value. 4091 ExtType = ISD::ZEXTLOAD; 4092 N0 = SDValue(N, 0); 4093 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4094 if (!N01) return SDValue(); 4095 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4096 VT.getSizeInBits() - N01->getZExtValue()); 4097 } 4098 4099 unsigned EVTBits = ExtVT.getSizeInBits(); 4100 unsigned ShAmt = 0; 4101 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 4102 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4103 ShAmt = N01->getZExtValue(); 4104 // Is the shift amount a multiple of size of VT? 4105 if ((ShAmt & (EVTBits-1)) == 0) { 4106 N0 = N0.getOperand(0); 4107 // Is the load width a multiple of size of VT? 4108 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4109 return SDValue(); 4110 } 4111 4112 // If the shift amount is larger than the input type then we're not 4113 // accessing any of the loaded bytes. If the load was a zextload/extload 4114 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4115 // If the load was a sextload then the result is a splat of the sign bit 4116 // of the extended byte. This is not worth optimizing for. 4117 if (ShAmt >= VT.getSizeInBits()) 4118 return SDValue(); 4119 4120 } 4121 } 4122 4123 // If the load is shifted left (and the result isn't shifted back right), 4124 // we can fold the truncate through the shift. 4125 unsigned ShLeftAmt = 0; 4126 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4127 ExtVT == VT && 4128 TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4129 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4130 ShLeftAmt = N01->getZExtValue(); 4131 N0 = N0.getOperand(0); 4132 } 4133 } 4134 4135 // Do not generate loads of non-round integer types since these can 4136 // be expensive (and would be wrong if the type is not byte sized). 4137 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 4138 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits && 4139 // Do not change the width of a volatile load. 4140 !cast<LoadSDNode>(N0)->isVolatile()) { 4141 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4142 EVT PtrType = N0.getOperand(1).getValueType(); 4143 4144 // For big endian targets, we need to adjust the offset to the pointer to 4145 // load the correct bytes. 4146 if (TLI.isBigEndian()) { 4147 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4148 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4149 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4150 } 4151 4152 uint64_t PtrOff = ShAmt / 8; 4153 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4154 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4155 PtrType, LN0->getBasePtr(), 4156 DAG.getConstant(PtrOff, PtrType)); 4157 AddToWorkList(NewPtr.getNode()); 4158 4159 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 4160 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4161 LN0->getPointerInfo().getWithOffset(PtrOff), 4162 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign) 4163 : DAG.getExtLoad(ExtType, VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4164 LN0->getPointerInfo().getWithOffset(PtrOff), 4165 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4166 NewAlign); 4167 4168 // Replace the old load's chain with the new load's chain. 4169 WorkListRemover DeadNodes(*this); 4170 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4171 &DeadNodes); 4172 4173 // Shift the result left, if we've swallowed a left shift. 4174 SDValue Result = Load; 4175 if (ShLeftAmt != 0) { 4176 EVT ShImmTy = getShiftAmountTy(); 4177 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4178 ShImmTy = VT; 4179 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4180 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4181 } 4182 4183 // Return the new loaded value. 4184 return Result; 4185 } 4186 4187 return SDValue(); 4188} 4189 4190SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4191 SDValue N0 = N->getOperand(0); 4192 SDValue N1 = N->getOperand(1); 4193 EVT VT = N->getValueType(0); 4194 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4195 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4196 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4197 4198 // fold (sext_in_reg c1) -> c1 4199 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4200 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4201 4202 // If the input is already sign extended, just drop the extension. 4203 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4204 return N0; 4205 4206 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4207 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4208 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4209 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4210 N0.getOperand(0), N1); 4211 } 4212 4213 // fold (sext_in_reg (sext x)) -> (sext x) 4214 // fold (sext_in_reg (aext x)) -> (sext x) 4215 // if x is small enough. 4216 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4217 SDValue N00 = N0.getOperand(0); 4218 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4219 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4220 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4221 } 4222 4223 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4224 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4225 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4226 4227 // fold operands of sext_in_reg based on knowledge that the top bits are not 4228 // demanded. 4229 if (SimplifyDemandedBits(SDValue(N, 0))) 4230 return SDValue(N, 0); 4231 4232 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4233 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4234 SDValue NarrowLoad = ReduceLoadWidth(N); 4235 if (NarrowLoad.getNode()) 4236 return NarrowLoad; 4237 4238 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4239 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4240 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4241 if (N0.getOpcode() == ISD::SRL) { 4242 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4243 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4244 // We can turn this into an SRA iff the input to the SRL is already sign 4245 // extended enough. 4246 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4247 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4248 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4249 N0.getOperand(0), N0.getOperand(1)); 4250 } 4251 } 4252 4253 // fold (sext_inreg (extload x)) -> (sextload x) 4254 if (ISD::isEXTLoad(N0.getNode()) && 4255 ISD::isUNINDEXEDLoad(N0.getNode()) && 4256 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4257 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4258 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4259 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4260 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 4261 LN0->getChain(), 4262 LN0->getBasePtr(), LN0->getPointerInfo(), 4263 EVT, 4264 LN0->isVolatile(), LN0->isNonTemporal(), 4265 LN0->getAlignment()); 4266 CombineTo(N, ExtLoad); 4267 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4268 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4269 } 4270 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4271 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4272 N0.hasOneUse() && 4273 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4274 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4275 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4276 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4277 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 4278 LN0->getChain(), 4279 LN0->getBasePtr(), LN0->getPointerInfo(), 4280 EVT, 4281 LN0->isVolatile(), LN0->isNonTemporal(), 4282 LN0->getAlignment()); 4283 CombineTo(N, ExtLoad); 4284 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4285 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4286 } 4287 return SDValue(); 4288} 4289 4290SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4291 SDValue N0 = N->getOperand(0); 4292 EVT VT = N->getValueType(0); 4293 4294 // noop truncate 4295 if (N0.getValueType() == N->getValueType(0)) 4296 return N0; 4297 // fold (truncate c1) -> c1 4298 if (isa<ConstantSDNode>(N0)) 4299 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4300 // fold (truncate (truncate x)) -> (truncate x) 4301 if (N0.getOpcode() == ISD::TRUNCATE) 4302 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4303 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4304 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4305 N0.getOpcode() == ISD::SIGN_EXTEND || 4306 N0.getOpcode() == ISD::ANY_EXTEND) { 4307 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4308 // if the source is smaller than the dest, we still need an extend 4309 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4310 N0.getOperand(0)); 4311 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4312 // if the source is larger than the dest, than we just need the truncate 4313 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4314 else 4315 // if the source and dest are the same type, we can drop both the extend 4316 // and the truncate. 4317 return N0.getOperand(0); 4318 } 4319 4320 // See if we can simplify the input to this truncate through knowledge that 4321 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 4322 // -> trunc y 4323 SDValue Shorter = 4324 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4325 VT.getSizeInBits())); 4326 if (Shorter.getNode()) 4327 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4328 4329 // fold (truncate (load x)) -> (smaller load x) 4330 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4331 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4332 SDValue Reduced = ReduceLoadWidth(N); 4333 if (Reduced.getNode()) 4334 return Reduced; 4335 } 4336 4337 // Simplify the operands using demanded-bits information. 4338 if (!VT.isVector() && 4339 SimplifyDemandedBits(SDValue(N, 0))) 4340 return SDValue(N, 0); 4341 4342 return SDValue(); 4343} 4344 4345static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4346 SDValue Elt = N->getOperand(i); 4347 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4348 return Elt.getNode(); 4349 return Elt.getOperand(Elt.getResNo()).getNode(); 4350} 4351 4352/// CombineConsecutiveLoads - build_pair (load, load) -> load 4353/// if load locations are consecutive. 4354SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4355 assert(N->getOpcode() == ISD::BUILD_PAIR); 4356 4357 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4358 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4359 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4360 LD1->getPointerInfo().getAddrSpace() != 4361 LD2->getPointerInfo().getAddrSpace()) 4362 return SDValue(); 4363 EVT LD1VT = LD1->getValueType(0); 4364 4365 if (ISD::isNON_EXTLoad(LD2) && 4366 LD2->hasOneUse() && 4367 // If both are volatile this would reduce the number of volatile loads. 4368 // If one is volatile it might be ok, but play conservative and bail out. 4369 !LD1->isVolatile() && 4370 !LD2->isVolatile() && 4371 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4372 unsigned Align = LD1->getAlignment(); 4373 unsigned NewAlign = TLI.getTargetData()-> 4374 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4375 4376 if (NewAlign <= Align && 4377 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4378 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4379 LD1->getBasePtr(), LD1->getPointerInfo(), 4380 false, false, Align); 4381 } 4382 4383 return SDValue(); 4384} 4385 4386SDValue DAGCombiner::visitBITCAST(SDNode *N) { 4387 SDValue N0 = N->getOperand(0); 4388 EVT VT = N->getValueType(0); 4389 4390 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4391 // Only do this before legalize, since afterward the target may be depending 4392 // on the bitconvert. 4393 // First check to see if this is all constant. 4394 if (!LegalTypes && 4395 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4396 VT.isVector()) { 4397 bool isSimple = true; 4398 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4399 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4400 N0.getOperand(i).getOpcode() != ISD::Constant && 4401 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4402 isSimple = false; 4403 break; 4404 } 4405 4406 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4407 assert(!DestEltVT.isVector() && 4408 "Element type of vector ValueType must not be vector!"); 4409 if (isSimple) 4410 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4411 } 4412 4413 // If the input is a constant, let getNode fold it. 4414 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4415 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 4416 if (Res.getNode() != N) { 4417 if (!LegalOperations || 4418 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4419 return Res; 4420 4421 // Folding it resulted in an illegal node, and it's too late to 4422 // do that. Clean up the old node and forego the transformation. 4423 // Ideally this won't happen very often, because instcombine 4424 // and the earlier dagcombine runs (where illegal nodes are 4425 // permitted) should have folded most of them already. 4426 DAG.DeleteNode(Res.getNode()); 4427 } 4428 } 4429 4430 // (conv (conv x, t1), t2) -> (conv x, t2) 4431 if (N0.getOpcode() == ISD::BITCAST) 4432 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 4433 N0.getOperand(0)); 4434 4435 // fold (conv (load x)) -> (load (conv*)x) 4436 // If the resultant load doesn't need a higher alignment than the original! 4437 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4438 // Do not change the width of a volatile load. 4439 !cast<LoadSDNode>(N0)->isVolatile() && 4440 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4441 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4442 unsigned Align = TLI.getTargetData()-> 4443 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4444 unsigned OrigAlign = LN0->getAlignment(); 4445 4446 if (Align <= OrigAlign) { 4447 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4448 LN0->getBasePtr(), LN0->getPointerInfo(), 4449 LN0->isVolatile(), LN0->isNonTemporal(), 4450 OrigAlign); 4451 AddToWorkList(N); 4452 CombineTo(N0.getNode(), 4453 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4454 N0.getValueType(), Load), 4455 Load.getValue(1)); 4456 return Load; 4457 } 4458 } 4459 4460 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4461 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4462 // This often reduces constant pool loads. 4463 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4464 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4465 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 4466 N0.getOperand(0)); 4467 AddToWorkList(NewConv.getNode()); 4468 4469 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4470 if (N0.getOpcode() == ISD::FNEG) 4471 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4472 NewConv, DAG.getConstant(SignBit, VT)); 4473 assert(N0.getOpcode() == ISD::FABS); 4474 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4475 NewConv, DAG.getConstant(~SignBit, VT)); 4476 } 4477 4478 // fold (bitconvert (fcopysign cst, x)) -> 4479 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4480 // Note that we don't handle (copysign x, cst) because this can always be 4481 // folded to an fneg or fabs. 4482 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4483 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4484 VT.isInteger() && !VT.isVector()) { 4485 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4486 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4487 if (isTypeLegal(IntXVT)) { 4488 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4489 IntXVT, N0.getOperand(1)); 4490 AddToWorkList(X.getNode()); 4491 4492 // If X has a different width than the result/lhs, sext it or truncate it. 4493 unsigned VTWidth = VT.getSizeInBits(); 4494 if (OrigXWidth < VTWidth) { 4495 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4496 AddToWorkList(X.getNode()); 4497 } else if (OrigXWidth > VTWidth) { 4498 // To get the sign bit in the right place, we have to shift it right 4499 // before truncating. 4500 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4501 X.getValueType(), X, 4502 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4503 AddToWorkList(X.getNode()); 4504 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4505 AddToWorkList(X.getNode()); 4506 } 4507 4508 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4509 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4510 X, DAG.getConstant(SignBit, VT)); 4511 AddToWorkList(X.getNode()); 4512 4513 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4514 VT, N0.getOperand(0)); 4515 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4516 Cst, DAG.getConstant(~SignBit, VT)); 4517 AddToWorkList(Cst.getNode()); 4518 4519 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4520 } 4521 } 4522 4523 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4524 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4525 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4526 if (CombineLD.getNode()) 4527 return CombineLD; 4528 } 4529 4530 return SDValue(); 4531} 4532 4533SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4534 EVT VT = N->getValueType(0); 4535 return CombineConsecutiveLoads(N, VT); 4536} 4537 4538/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 4539/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4540/// destination element value type. 4541SDValue DAGCombiner:: 4542ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4543 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4544 4545 // If this is already the right type, we're done. 4546 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4547 4548 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4549 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4550 4551 // If this is a conversion of N elements of one type to N elements of another 4552 // type, convert each element. This handles FP<->INT cases. 4553 if (SrcBitSize == DstBitSize) { 4554 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4555 BV->getValueType(0).getVectorNumElements()); 4556 4557 // Due to the FP element handling below calling this routine recursively, 4558 // we can end up with a scalar-to-vector node here. 4559 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 4560 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4561 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4562 DstEltVT, BV->getOperand(0))); 4563 4564 SmallVector<SDValue, 8> Ops; 4565 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4566 SDValue Op = BV->getOperand(i); 4567 // If the vector element type is not legal, the BUILD_VECTOR operands 4568 // are promoted and implicitly truncated. Make that explicit here. 4569 if (Op.getValueType() != SrcEltVT) 4570 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4571 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4572 DstEltVT, Op)); 4573 AddToWorkList(Ops.back().getNode()); 4574 } 4575 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4576 &Ops[0], Ops.size()); 4577 } 4578 4579 // Otherwise, we're growing or shrinking the elements. To avoid having to 4580 // handle annoying details of growing/shrinking FP values, we convert them to 4581 // int first. 4582 if (SrcEltVT.isFloatingPoint()) { 4583 // Convert the input float vector to a int vector where the elements are the 4584 // same sizes. 4585 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4586 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4587 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 4588 SrcEltVT = IntVT; 4589 } 4590 4591 // Now we know the input is an integer vector. If the output is a FP type, 4592 // convert to integer first, then to FP of the right size. 4593 if (DstEltVT.isFloatingPoint()) { 4594 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4595 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4596 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 4597 4598 // Next, convert to FP elements of the same size. 4599 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 4600 } 4601 4602 // Okay, we know the src/dst types are both integers of differing types. 4603 // Handling growing first. 4604 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4605 if (SrcBitSize < DstBitSize) { 4606 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4607 4608 SmallVector<SDValue, 8> Ops; 4609 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4610 i += NumInputsPerOutput) { 4611 bool isLE = TLI.isLittleEndian(); 4612 APInt NewBits = APInt(DstBitSize, 0); 4613 bool EltIsUndef = true; 4614 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4615 // Shift the previously computed bits over. 4616 NewBits <<= SrcBitSize; 4617 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4618 if (Op.getOpcode() == ISD::UNDEF) continue; 4619 EltIsUndef = false; 4620 4621 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 4622 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4623 } 4624 4625 if (EltIsUndef) 4626 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4627 else 4628 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4629 } 4630 4631 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4632 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4633 &Ops[0], Ops.size()); 4634 } 4635 4636 // Finally, this must be the case where we are shrinking elements: each input 4637 // turns into multiple outputs. 4638 bool isS2V = ISD::isScalarToVector(BV); 4639 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4640 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4641 NumOutputsPerInput*BV->getNumOperands()); 4642 SmallVector<SDValue, 8> Ops; 4643 4644 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4645 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4646 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4647 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4648 continue; 4649 } 4650 4651 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 4652 getAPIntValue().zextOrTrunc(SrcBitSize); 4653 4654 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4655 APInt ThisVal = OpVal.trunc(DstBitSize); 4656 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4657 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 4658 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4659 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4660 Ops[0]); 4661 OpVal = OpVal.lshr(DstBitSize); 4662 } 4663 4664 // For big endian targets, swap the order of the pieces of each element. 4665 if (TLI.isBigEndian()) 4666 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4667 } 4668 4669 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4670 &Ops[0], Ops.size()); 4671} 4672 4673SDValue DAGCombiner::visitFADD(SDNode *N) { 4674 SDValue N0 = N->getOperand(0); 4675 SDValue N1 = N->getOperand(1); 4676 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4677 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4678 EVT VT = N->getValueType(0); 4679 4680 // fold vector ops 4681 if (VT.isVector()) { 4682 SDValue FoldedVOp = SimplifyVBinOp(N); 4683 if (FoldedVOp.getNode()) return FoldedVOp; 4684 } 4685 4686 // fold (fadd c1, c2) -> (fadd c1, c2) 4687 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4688 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4689 // canonicalize constant to RHS 4690 if (N0CFP && !N1CFP) 4691 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4692 // fold (fadd A, 0) -> A 4693 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4694 return N0; 4695 // fold (fadd A, (fneg B)) -> (fsub A, B) 4696 if (isNegatibleForFree(N1, LegalOperations) == 2) 4697 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4698 GetNegatedExpression(N1, DAG, LegalOperations)); 4699 // fold (fadd (fneg A), B) -> (fsub B, A) 4700 if (isNegatibleForFree(N0, LegalOperations) == 2) 4701 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4702 GetNegatedExpression(N0, DAG, LegalOperations)); 4703 4704 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4705 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4706 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4707 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4708 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4709 N0.getOperand(1), N1)); 4710 4711 return SDValue(); 4712} 4713 4714SDValue DAGCombiner::visitFSUB(SDNode *N) { 4715 SDValue N0 = N->getOperand(0); 4716 SDValue N1 = N->getOperand(1); 4717 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4718 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4719 EVT VT = N->getValueType(0); 4720 4721 // fold vector ops 4722 if (VT.isVector()) { 4723 SDValue FoldedVOp = SimplifyVBinOp(N); 4724 if (FoldedVOp.getNode()) return FoldedVOp; 4725 } 4726 4727 // fold (fsub c1, c2) -> c1-c2 4728 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4729 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4730 // fold (fsub A, 0) -> A 4731 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4732 return N0; 4733 // fold (fsub 0, B) -> -B 4734 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4735 if (isNegatibleForFree(N1, LegalOperations)) 4736 return GetNegatedExpression(N1, DAG, LegalOperations); 4737 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4738 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4739 } 4740 // fold (fsub A, (fneg B)) -> (fadd A, B) 4741 if (isNegatibleForFree(N1, LegalOperations)) 4742 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4743 GetNegatedExpression(N1, DAG, LegalOperations)); 4744 4745 return SDValue(); 4746} 4747 4748SDValue DAGCombiner::visitFMUL(SDNode *N) { 4749 SDValue N0 = N->getOperand(0); 4750 SDValue N1 = N->getOperand(1); 4751 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4752 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4753 EVT VT = N->getValueType(0); 4754 4755 // fold vector ops 4756 if (VT.isVector()) { 4757 SDValue FoldedVOp = SimplifyVBinOp(N); 4758 if (FoldedVOp.getNode()) return FoldedVOp; 4759 } 4760 4761 // fold (fmul c1, c2) -> c1*c2 4762 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4763 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4764 // canonicalize constant to RHS 4765 if (N0CFP && !N1CFP) 4766 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4767 // fold (fmul A, 0) -> 0 4768 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4769 return N1; 4770 // fold (fmul A, 0) -> 0, vector edition. 4771 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4772 return N1; 4773 // fold (fmul X, 2.0) -> (fadd X, X) 4774 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4775 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4776 // fold (fmul X, -1.0) -> (fneg X) 4777 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4778 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4779 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4780 4781 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4782 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4783 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4784 // Both can be negated for free, check to see if at least one is cheaper 4785 // negated. 4786 if (LHSNeg == 2 || RHSNeg == 2) 4787 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4788 GetNegatedExpression(N0, DAG, LegalOperations), 4789 GetNegatedExpression(N1, DAG, LegalOperations)); 4790 } 4791 } 4792 4793 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4794 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4795 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4796 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4797 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4798 N0.getOperand(1), N1)); 4799 4800 return SDValue(); 4801} 4802 4803SDValue DAGCombiner::visitFDIV(SDNode *N) { 4804 SDValue N0 = N->getOperand(0); 4805 SDValue N1 = N->getOperand(1); 4806 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4807 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4808 EVT VT = N->getValueType(0); 4809 4810 // fold vector ops 4811 if (VT.isVector()) { 4812 SDValue FoldedVOp = SimplifyVBinOp(N); 4813 if (FoldedVOp.getNode()) return FoldedVOp; 4814 } 4815 4816 // fold (fdiv c1, c2) -> c1/c2 4817 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4818 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4819 4820 4821 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4822 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4823 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4824 // Both can be negated for free, check to see if at least one is cheaper 4825 // negated. 4826 if (LHSNeg == 2 || RHSNeg == 2) 4827 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4828 GetNegatedExpression(N0, DAG, LegalOperations), 4829 GetNegatedExpression(N1, DAG, LegalOperations)); 4830 } 4831 } 4832 4833 return SDValue(); 4834} 4835 4836SDValue DAGCombiner::visitFREM(SDNode *N) { 4837 SDValue N0 = N->getOperand(0); 4838 SDValue N1 = N->getOperand(1); 4839 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4840 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4841 EVT VT = N->getValueType(0); 4842 4843 // fold (frem c1, c2) -> fmod(c1,c2) 4844 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4845 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4846 4847 return SDValue(); 4848} 4849 4850SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4851 SDValue N0 = N->getOperand(0); 4852 SDValue N1 = N->getOperand(1); 4853 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4854 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4855 EVT VT = N->getValueType(0); 4856 4857 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4858 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4859 4860 if (N1CFP) { 4861 const APFloat& V = N1CFP->getValueAPF(); 4862 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4863 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4864 if (!V.isNegative()) { 4865 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4866 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4867 } else { 4868 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4869 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4870 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4871 } 4872 } 4873 4874 // copysign(fabs(x), y) -> copysign(x, y) 4875 // copysign(fneg(x), y) -> copysign(x, y) 4876 // copysign(copysign(x,z), y) -> copysign(x, y) 4877 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4878 N0.getOpcode() == ISD::FCOPYSIGN) 4879 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4880 N0.getOperand(0), N1); 4881 4882 // copysign(x, abs(y)) -> abs(x) 4883 if (N1.getOpcode() == ISD::FABS) 4884 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4885 4886 // copysign(x, copysign(y,z)) -> copysign(x, z) 4887 if (N1.getOpcode() == ISD::FCOPYSIGN) 4888 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4889 N0, N1.getOperand(1)); 4890 4891 // copysign(x, fp_extend(y)) -> copysign(x, y) 4892 // copysign(x, fp_round(y)) -> copysign(x, y) 4893 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4894 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4895 N0, N1.getOperand(0)); 4896 4897 return SDValue(); 4898} 4899 4900SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4901 SDValue N0 = N->getOperand(0); 4902 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4903 EVT VT = N->getValueType(0); 4904 EVT OpVT = N0.getValueType(); 4905 4906 // fold (sint_to_fp c1) -> c1fp 4907 if (N0C && OpVT != MVT::ppcf128) 4908 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4909 4910 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4911 // but UINT_TO_FP is legal on this target, try to convert. 4912 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4913 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4914 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4915 if (DAG.SignBitIsZero(N0)) 4916 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4917 } 4918 4919 return SDValue(); 4920} 4921 4922SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4923 SDValue N0 = N->getOperand(0); 4924 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4925 EVT VT = N->getValueType(0); 4926 EVT OpVT = N0.getValueType(); 4927 4928 // fold (uint_to_fp c1) -> c1fp 4929 if (N0C && OpVT != MVT::ppcf128) 4930 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4931 4932 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4933 // but SINT_TO_FP is legal on this target, try to convert. 4934 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4935 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4936 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4937 if (DAG.SignBitIsZero(N0)) 4938 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4939 } 4940 4941 return SDValue(); 4942} 4943 4944SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4945 SDValue N0 = N->getOperand(0); 4946 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4947 EVT VT = N->getValueType(0); 4948 4949 // fold (fp_to_sint c1fp) -> c1 4950 if (N0CFP) 4951 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4952 4953 return SDValue(); 4954} 4955 4956SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4957 SDValue N0 = N->getOperand(0); 4958 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4959 EVT VT = N->getValueType(0); 4960 4961 // fold (fp_to_uint c1fp) -> c1 4962 if (N0CFP && VT != MVT::ppcf128) 4963 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4964 4965 return SDValue(); 4966} 4967 4968SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4969 SDValue N0 = N->getOperand(0); 4970 SDValue N1 = N->getOperand(1); 4971 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4972 EVT VT = N->getValueType(0); 4973 4974 // fold (fp_round c1fp) -> c1fp 4975 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4976 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4977 4978 // fold (fp_round (fp_extend x)) -> x 4979 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4980 return N0.getOperand(0); 4981 4982 // fold (fp_round (fp_round x)) -> (fp_round x) 4983 if (N0.getOpcode() == ISD::FP_ROUND) { 4984 // This is a value preserving truncation if both round's are. 4985 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4986 N0.getNode()->getConstantOperandVal(1) == 1; 4987 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4988 DAG.getIntPtrConstant(IsTrunc)); 4989 } 4990 4991 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4992 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4993 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4994 N0.getOperand(0), N1); 4995 AddToWorkList(Tmp.getNode()); 4996 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4997 Tmp, N0.getOperand(1)); 4998 } 4999 5000 return SDValue(); 5001} 5002 5003SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5004 SDValue N0 = N->getOperand(0); 5005 EVT VT = N->getValueType(0); 5006 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5007 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5008 5009 // fold (fp_round_inreg c1fp) -> c1fp 5010 if (N0CFP && isTypeLegal(EVT)) { 5011 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5012 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5013 } 5014 5015 return SDValue(); 5016} 5017 5018SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5019 SDValue N0 = N->getOperand(0); 5020 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5021 EVT VT = N->getValueType(0); 5022 5023 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5024 if (N->hasOneUse() && 5025 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5026 return SDValue(); 5027 5028 // fold (fp_extend c1fp) -> c1fp 5029 if (N0CFP && VT != MVT::ppcf128) 5030 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5031 5032 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5033 // value of X. 5034 if (N0.getOpcode() == ISD::FP_ROUND 5035 && N0.getNode()->getConstantOperandVal(1) == 1) { 5036 SDValue In = N0.getOperand(0); 5037 if (In.getValueType() == VT) return In; 5038 if (VT.bitsLT(In.getValueType())) 5039 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5040 In, N0.getOperand(1)); 5041 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5042 } 5043 5044 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5045 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5046 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5047 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5048 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5049 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(), 5050 LN0->getChain(), 5051 LN0->getBasePtr(), LN0->getPointerInfo(), 5052 N0.getValueType(), 5053 LN0->isVolatile(), LN0->isNonTemporal(), 5054 LN0->getAlignment()); 5055 CombineTo(N, ExtLoad); 5056 CombineTo(N0.getNode(), 5057 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5058 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5059 ExtLoad.getValue(1)); 5060 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5061 } 5062 5063 return SDValue(); 5064} 5065 5066SDValue DAGCombiner::visitFNEG(SDNode *N) { 5067 SDValue N0 = N->getOperand(0); 5068 EVT VT = N->getValueType(0); 5069 5070 if (isNegatibleForFree(N0, LegalOperations)) 5071 return GetNegatedExpression(N0, DAG, LegalOperations); 5072 5073 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5074 // constant pool values. 5075 if (N0.getOpcode() == ISD::BITCAST && 5076 !VT.isVector() && 5077 N0.getNode()->hasOneUse() && 5078 N0.getOperand(0).getValueType().isInteger()) { 5079 SDValue Int = N0.getOperand(0); 5080 EVT IntVT = Int.getValueType(); 5081 if (IntVT.isInteger() && !IntVT.isVector()) { 5082 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5083 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5084 AddToWorkList(Int.getNode()); 5085 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5086 VT, Int); 5087 } 5088 } 5089 5090 return SDValue(); 5091} 5092 5093SDValue DAGCombiner::visitFABS(SDNode *N) { 5094 SDValue N0 = N->getOperand(0); 5095 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5096 EVT VT = N->getValueType(0); 5097 5098 // fold (fabs c1) -> fabs(c1) 5099 if (N0CFP && VT != MVT::ppcf128) 5100 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5101 // fold (fabs (fabs x)) -> (fabs x) 5102 if (N0.getOpcode() == ISD::FABS) 5103 return N->getOperand(0); 5104 // fold (fabs (fneg x)) -> (fabs x) 5105 // fold (fabs (fcopysign x, y)) -> (fabs x) 5106 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5107 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5108 5109 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5110 // constant pool values. 5111 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5112 N0.getOperand(0).getValueType().isInteger() && 5113 !N0.getOperand(0).getValueType().isVector()) { 5114 SDValue Int = N0.getOperand(0); 5115 EVT IntVT = Int.getValueType(); 5116 if (IntVT.isInteger() && !IntVT.isVector()) { 5117 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5118 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5119 AddToWorkList(Int.getNode()); 5120 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5121 N->getValueType(0), Int); 5122 } 5123 } 5124 5125 return SDValue(); 5126} 5127 5128SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5129 SDValue Chain = N->getOperand(0); 5130 SDValue N1 = N->getOperand(1); 5131 SDValue N2 = N->getOperand(2); 5132 5133 // If N is a constant we could fold this into a fallthrough or unconditional 5134 // branch. However that doesn't happen very often in normal code, because 5135 // Instcombine/SimplifyCFG should have handled the available opportunities. 5136 // If we did this folding here, it would be necessary to update the 5137 // MachineBasicBlock CFG, which is awkward. 5138 5139 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5140 // on the target. 5141 if (N1.getOpcode() == ISD::SETCC && 5142 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5143 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5144 Chain, N1.getOperand(2), 5145 N1.getOperand(0), N1.getOperand(1), N2); 5146 } 5147 5148 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5149 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5150 (N1.getOperand(0).hasOneUse() && 5151 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5152 SDNode *Trunc = 0; 5153 if (N1.getOpcode() == ISD::TRUNCATE) { 5154 // Look pass the truncate. 5155 Trunc = N1.getNode(); 5156 N1 = N1.getOperand(0); 5157 } 5158 5159 // Match this pattern so that we can generate simpler code: 5160 // 5161 // %a = ... 5162 // %b = and i32 %a, 2 5163 // %c = srl i32 %b, 1 5164 // brcond i32 %c ... 5165 // 5166 // into 5167 // 5168 // %a = ... 5169 // %b = and i32 %a, 2 5170 // %c = setcc eq %b, 0 5171 // brcond %c ... 5172 // 5173 // This applies only when the AND constant value has one bit set and the 5174 // SRL constant is equal to the log2 of the AND constant. The back-end is 5175 // smart enough to convert the result into a TEST/JMP sequence. 5176 SDValue Op0 = N1.getOperand(0); 5177 SDValue Op1 = N1.getOperand(1); 5178 5179 if (Op0.getOpcode() == ISD::AND && 5180 Op1.getOpcode() == ISD::Constant) { 5181 SDValue AndOp1 = Op0.getOperand(1); 5182 5183 if (AndOp1.getOpcode() == ISD::Constant) { 5184 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5185 5186 if (AndConst.isPowerOf2() && 5187 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5188 SDValue SetCC = 5189 DAG.getSetCC(N->getDebugLoc(), 5190 TLI.getSetCCResultType(Op0.getValueType()), 5191 Op0, DAG.getConstant(0, Op0.getValueType()), 5192 ISD::SETNE); 5193 5194 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5195 MVT::Other, Chain, SetCC, N2); 5196 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5197 // will convert it back to (X & C1) >> C2. 5198 CombineTo(N, NewBRCond, false); 5199 // Truncate is dead. 5200 if (Trunc) { 5201 removeFromWorkList(Trunc); 5202 DAG.DeleteNode(Trunc); 5203 } 5204 // Replace the uses of SRL with SETCC 5205 WorkListRemover DeadNodes(*this); 5206 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5207 removeFromWorkList(N1.getNode()); 5208 DAG.DeleteNode(N1.getNode()); 5209 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5210 } 5211 } 5212 } 5213 5214 if (Trunc) 5215 // Restore N1 if the above transformation doesn't match. 5216 N1 = N->getOperand(1); 5217 } 5218 5219 // Transform br(xor(x, y)) -> br(x != y) 5220 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5221 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5222 SDNode *TheXor = N1.getNode(); 5223 SDValue Op0 = TheXor->getOperand(0); 5224 SDValue Op1 = TheXor->getOperand(1); 5225 if (Op0.getOpcode() == Op1.getOpcode()) { 5226 // Avoid missing important xor optimizations. 5227 SDValue Tmp = visitXOR(TheXor); 5228 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5229 DEBUG(dbgs() << "\nReplacing.8 "; 5230 TheXor->dump(&DAG); 5231 dbgs() << "\nWith: "; 5232 Tmp.getNode()->dump(&DAG); 5233 dbgs() << '\n'); 5234 WorkListRemover DeadNodes(*this); 5235 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5236 removeFromWorkList(TheXor); 5237 DAG.DeleteNode(TheXor); 5238 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5239 MVT::Other, Chain, Tmp, N2); 5240 } 5241 } 5242 5243 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5244 bool Equal = false; 5245 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5246 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5247 Op0.getOpcode() == ISD::XOR) { 5248 TheXor = Op0.getNode(); 5249 Equal = true; 5250 } 5251 5252 EVT SetCCVT = N1.getValueType(); 5253 if (LegalTypes) 5254 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5255 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5256 SetCCVT, 5257 Op0, Op1, 5258 Equal ? ISD::SETEQ : ISD::SETNE); 5259 // Replace the uses of XOR with SETCC 5260 WorkListRemover DeadNodes(*this); 5261 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5262 removeFromWorkList(N1.getNode()); 5263 DAG.DeleteNode(N1.getNode()); 5264 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5265 MVT::Other, Chain, SetCC, N2); 5266 } 5267 } 5268 5269 return SDValue(); 5270} 5271 5272// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5273// 5274SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5275 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5276 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5277 5278 // If N is a constant we could fold this into a fallthrough or unconditional 5279 // branch. However that doesn't happen very often in normal code, because 5280 // Instcombine/SimplifyCFG should have handled the available opportunities. 5281 // If we did this folding here, it would be necessary to update the 5282 // MachineBasicBlock CFG, which is awkward. 5283 5284 // Use SimplifySetCC to simplify SETCC's. 5285 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5286 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5287 false); 5288 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5289 5290 // fold to a simpler setcc 5291 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5292 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5293 N->getOperand(0), Simp.getOperand(2), 5294 Simp.getOperand(0), Simp.getOperand(1), 5295 N->getOperand(4)); 5296 5297 return SDValue(); 5298} 5299 5300/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5301/// pre-indexed load / store when the base pointer is an add or subtract 5302/// and it has other uses besides the load / store. After the 5303/// transformation, the new indexed load / store has effectively folded 5304/// the add / subtract in and all of its other uses are redirected to the 5305/// new load / store. 5306bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5307 if (!LegalOperations) 5308 return false; 5309 5310 bool isLoad = true; 5311 SDValue Ptr; 5312 EVT VT; 5313 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5314 if (LD->isIndexed()) 5315 return false; 5316 VT = LD->getMemoryVT(); 5317 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5318 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5319 return false; 5320 Ptr = LD->getBasePtr(); 5321 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5322 if (ST->isIndexed()) 5323 return false; 5324 VT = ST->getMemoryVT(); 5325 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5326 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5327 return false; 5328 Ptr = ST->getBasePtr(); 5329 isLoad = false; 5330 } else { 5331 return false; 5332 } 5333 5334 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5335 // out. There is no reason to make this a preinc/predec. 5336 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5337 Ptr.getNode()->hasOneUse()) 5338 return false; 5339 5340 // Ask the target to do addressing mode selection. 5341 SDValue BasePtr; 5342 SDValue Offset; 5343 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5344 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5345 return false; 5346 // Don't create a indexed load / store with zero offset. 5347 if (isa<ConstantSDNode>(Offset) && 5348 cast<ConstantSDNode>(Offset)->isNullValue()) 5349 return false; 5350 5351 // Try turning it into a pre-indexed load / store except when: 5352 // 1) The new base ptr is a frame index. 5353 // 2) If N is a store and the new base ptr is either the same as or is a 5354 // predecessor of the value being stored. 5355 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5356 // that would create a cycle. 5357 // 4) All uses are load / store ops that use it as old base ptr. 5358 5359 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5360 // (plus the implicit offset) to a register to preinc anyway. 5361 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5362 return false; 5363 5364 // Check #2. 5365 if (!isLoad) { 5366 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5367 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5368 return false; 5369 } 5370 5371 // Now check for #3 and #4. 5372 bool RealUse = false; 5373 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5374 E = Ptr.getNode()->use_end(); I != E; ++I) { 5375 SDNode *Use = *I; 5376 if (Use == N) 5377 continue; 5378 if (Use->isPredecessorOf(N)) 5379 return false; 5380 5381 if (!((Use->getOpcode() == ISD::LOAD && 5382 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5383 (Use->getOpcode() == ISD::STORE && 5384 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5385 RealUse = true; 5386 } 5387 5388 if (!RealUse) 5389 return false; 5390 5391 SDValue Result; 5392 if (isLoad) 5393 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5394 BasePtr, Offset, AM); 5395 else 5396 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5397 BasePtr, Offset, AM); 5398 ++PreIndexedNodes; 5399 ++NodesCombined; 5400 DEBUG(dbgs() << "\nReplacing.4 "; 5401 N->dump(&DAG); 5402 dbgs() << "\nWith: "; 5403 Result.getNode()->dump(&DAG); 5404 dbgs() << '\n'); 5405 WorkListRemover DeadNodes(*this); 5406 if (isLoad) { 5407 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5408 &DeadNodes); 5409 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5410 &DeadNodes); 5411 } else { 5412 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5413 &DeadNodes); 5414 } 5415 5416 // Finally, since the node is now dead, remove it from the graph. 5417 DAG.DeleteNode(N); 5418 5419 // Replace the uses of Ptr with uses of the updated base value. 5420 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5421 &DeadNodes); 5422 removeFromWorkList(Ptr.getNode()); 5423 DAG.DeleteNode(Ptr.getNode()); 5424 5425 return true; 5426} 5427 5428/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5429/// add / sub of the base pointer node into a post-indexed load / store. 5430/// The transformation folded the add / subtract into the new indexed 5431/// load / store effectively and all of its uses are redirected to the 5432/// new load / store. 5433bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5434 if (!LegalOperations) 5435 return false; 5436 5437 bool isLoad = true; 5438 SDValue Ptr; 5439 EVT VT; 5440 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5441 if (LD->isIndexed()) 5442 return false; 5443 VT = LD->getMemoryVT(); 5444 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5445 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5446 return false; 5447 Ptr = LD->getBasePtr(); 5448 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5449 if (ST->isIndexed()) 5450 return false; 5451 VT = ST->getMemoryVT(); 5452 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5453 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5454 return false; 5455 Ptr = ST->getBasePtr(); 5456 isLoad = false; 5457 } else { 5458 return false; 5459 } 5460 5461 if (Ptr.getNode()->hasOneUse()) 5462 return false; 5463 5464 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5465 E = Ptr.getNode()->use_end(); I != E; ++I) { 5466 SDNode *Op = *I; 5467 if (Op == N || 5468 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5469 continue; 5470 5471 SDValue BasePtr; 5472 SDValue Offset; 5473 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5474 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5475 // Don't create a indexed load / store with zero offset. 5476 if (isa<ConstantSDNode>(Offset) && 5477 cast<ConstantSDNode>(Offset)->isNullValue()) 5478 continue; 5479 5480 // Try turning it into a post-indexed load / store except when 5481 // 1) All uses are load / store ops that use it as base ptr. 5482 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5483 // nor a successor of N. Otherwise, if Op is folded that would 5484 // create a cycle. 5485 5486 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5487 continue; 5488 5489 // Check for #1. 5490 bool TryNext = false; 5491 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5492 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5493 SDNode *Use = *II; 5494 if (Use == Ptr.getNode()) 5495 continue; 5496 5497 // If all the uses are load / store addresses, then don't do the 5498 // transformation. 5499 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5500 bool RealUse = false; 5501 for (SDNode::use_iterator III = Use->use_begin(), 5502 EEE = Use->use_end(); III != EEE; ++III) { 5503 SDNode *UseUse = *III; 5504 if (!((UseUse->getOpcode() == ISD::LOAD && 5505 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5506 (UseUse->getOpcode() == ISD::STORE && 5507 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5508 RealUse = true; 5509 } 5510 5511 if (!RealUse) { 5512 TryNext = true; 5513 break; 5514 } 5515 } 5516 } 5517 5518 if (TryNext) 5519 continue; 5520 5521 // Check for #2 5522 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5523 SDValue Result = isLoad 5524 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5525 BasePtr, Offset, AM) 5526 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5527 BasePtr, Offset, AM); 5528 ++PostIndexedNodes; 5529 ++NodesCombined; 5530 DEBUG(dbgs() << "\nReplacing.5 "; 5531 N->dump(&DAG); 5532 dbgs() << "\nWith: "; 5533 Result.getNode()->dump(&DAG); 5534 dbgs() << '\n'); 5535 WorkListRemover DeadNodes(*this); 5536 if (isLoad) { 5537 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5538 &DeadNodes); 5539 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5540 &DeadNodes); 5541 } else { 5542 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5543 &DeadNodes); 5544 } 5545 5546 // Finally, since the node is now dead, remove it from the graph. 5547 DAG.DeleteNode(N); 5548 5549 // Replace the uses of Use with uses of the updated base value. 5550 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5551 Result.getValue(isLoad ? 1 : 0), 5552 &DeadNodes); 5553 removeFromWorkList(Op); 5554 DAG.DeleteNode(Op); 5555 return true; 5556 } 5557 } 5558 } 5559 5560 return false; 5561} 5562 5563SDValue DAGCombiner::visitLOAD(SDNode *N) { 5564 LoadSDNode *LD = cast<LoadSDNode>(N); 5565 SDValue Chain = LD->getChain(); 5566 SDValue Ptr = LD->getBasePtr(); 5567 5568 // If load is not volatile and there are no uses of the loaded value (and 5569 // the updated indexed value in case of indexed loads), change uses of the 5570 // chain value into uses of the chain input (i.e. delete the dead load). 5571 if (!LD->isVolatile()) { 5572 if (N->getValueType(1) == MVT::Other) { 5573 // Unindexed loads. 5574 if (N->hasNUsesOfValue(0, 0)) { 5575 // It's not safe to use the two value CombineTo variant here. e.g. 5576 // v1, chain2 = load chain1, loc 5577 // v2, chain3 = load chain2, loc 5578 // v3 = add v2, c 5579 // Now we replace use of chain2 with chain1. This makes the second load 5580 // isomorphic to the one we are deleting, and thus makes this load live. 5581 DEBUG(dbgs() << "\nReplacing.6 "; 5582 N->dump(&DAG); 5583 dbgs() << "\nWith chain: "; 5584 Chain.getNode()->dump(&DAG); 5585 dbgs() << "\n"); 5586 WorkListRemover DeadNodes(*this); 5587 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5588 5589 if (N->use_empty()) { 5590 removeFromWorkList(N); 5591 DAG.DeleteNode(N); 5592 } 5593 5594 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5595 } 5596 } else { 5597 // Indexed loads. 5598 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5599 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5600 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5601 DEBUG(dbgs() << "\nReplacing.7 "; 5602 N->dump(&DAG); 5603 dbgs() << "\nWith: "; 5604 Undef.getNode()->dump(&DAG); 5605 dbgs() << " and 2 other values\n"); 5606 WorkListRemover DeadNodes(*this); 5607 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5608 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5609 DAG.getUNDEF(N->getValueType(1)), 5610 &DeadNodes); 5611 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5612 removeFromWorkList(N); 5613 DAG.DeleteNode(N); 5614 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5615 } 5616 } 5617 } 5618 5619 // If this load is directly stored, replace the load value with the stored 5620 // value. 5621 // TODO: Handle store large -> read small portion. 5622 // TODO: Handle TRUNCSTORE/LOADEXT 5623 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5624 !LD->isVolatile()) { 5625 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5626 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5627 if (PrevST->getBasePtr() == Ptr && 5628 PrevST->getValue().getValueType() == N->getValueType(0)) 5629 return CombineTo(N, Chain.getOperand(1), Chain); 5630 } 5631 } 5632 5633 // Try to infer better alignment information than the load already has. 5634 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5635 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5636 if (Align > LD->getAlignment()) 5637 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 5638 N->getDebugLoc(), 5639 Chain, Ptr, LD->getPointerInfo(), 5640 LD->getMemoryVT(), 5641 LD->isVolatile(), LD->isNonTemporal(), Align); 5642 } 5643 } 5644 5645 if (CombinerAA) { 5646 // Walk up chain skipping non-aliasing memory nodes. 5647 SDValue BetterChain = FindBetterChain(N, Chain); 5648 5649 // If there is a better chain. 5650 if (Chain != BetterChain) { 5651 SDValue ReplLoad; 5652 5653 // Replace the chain to void dependency. 5654 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5655 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5656 BetterChain, Ptr, LD->getPointerInfo(), 5657 LD->isVolatile(), LD->isNonTemporal(), 5658 LD->getAlignment()); 5659 } else { 5660 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 5661 LD->getDebugLoc(), 5662 BetterChain, Ptr, LD->getPointerInfo(), 5663 LD->getMemoryVT(), 5664 LD->isVolatile(), 5665 LD->isNonTemporal(), 5666 LD->getAlignment()); 5667 } 5668 5669 // Create token factor to keep old chain connected. 5670 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5671 MVT::Other, Chain, ReplLoad.getValue(1)); 5672 5673 // Make sure the new and old chains are cleaned up. 5674 AddToWorkList(Token.getNode()); 5675 5676 // Replace uses with load result and token factor. Don't add users 5677 // to work list. 5678 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5679 } 5680 } 5681 5682 // Try transforming N to an indexed load. 5683 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5684 return SDValue(N, 0); 5685 5686 return SDValue(); 5687} 5688 5689/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5690/// load is having specific bytes cleared out. If so, return the byte size 5691/// being masked out and the shift amount. 5692static std::pair<unsigned, unsigned> 5693CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5694 std::pair<unsigned, unsigned> Result(0, 0); 5695 5696 // Check for the structure we're looking for. 5697 if (V->getOpcode() != ISD::AND || 5698 !isa<ConstantSDNode>(V->getOperand(1)) || 5699 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5700 return Result; 5701 5702 // Check the chain and pointer. 5703 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5704 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5705 5706 // The store should be chained directly to the load or be an operand of a 5707 // tokenfactor. 5708 if (LD == Chain.getNode()) 5709 ; // ok. 5710 else if (Chain->getOpcode() != ISD::TokenFactor) 5711 return Result; // Fail. 5712 else { 5713 bool isOk = false; 5714 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5715 if (Chain->getOperand(i).getNode() == LD) { 5716 isOk = true; 5717 break; 5718 } 5719 if (!isOk) return Result; 5720 } 5721 5722 // This only handles simple types. 5723 if (V.getValueType() != MVT::i16 && 5724 V.getValueType() != MVT::i32 && 5725 V.getValueType() != MVT::i64) 5726 return Result; 5727 5728 // Check the constant mask. Invert it so that the bits being masked out are 5729 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5730 // follow the sign bit for uniformity. 5731 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5732 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5733 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5734 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5735 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5736 if (NotMaskLZ == 64) return Result; // All zero mask. 5737 5738 // See if we have a continuous run of bits. If so, we have 0*1+0* 5739 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5740 return Result; 5741 5742 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5743 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5744 NotMaskLZ -= 64-V.getValueSizeInBits(); 5745 5746 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5747 switch (MaskedBytes) { 5748 case 1: 5749 case 2: 5750 case 4: break; 5751 default: return Result; // All one mask, or 5-byte mask. 5752 } 5753 5754 // Verify that the first bit starts at a multiple of mask so that the access 5755 // is aligned the same as the access width. 5756 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 5757 5758 Result.first = MaskedBytes; 5759 Result.second = NotMaskTZ/8; 5760 return Result; 5761} 5762 5763 5764/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 5765/// provides a value as specified by MaskInfo. If so, replace the specified 5766/// store with a narrower store of truncated IVal. 5767static SDNode * 5768ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 5769 SDValue IVal, StoreSDNode *St, 5770 DAGCombiner *DC) { 5771 unsigned NumBytes = MaskInfo.first; 5772 unsigned ByteShift = MaskInfo.second; 5773 SelectionDAG &DAG = DC->getDAG(); 5774 5775 // Check to see if IVal is all zeros in the part being masked in by the 'or' 5776 // that uses this. If not, this is not a replacement. 5777 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 5778 ByteShift*8, (ByteShift+NumBytes)*8); 5779 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 5780 5781 // Check that it is legal on the target to do this. It is legal if the new 5782 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 5783 // legalization. 5784 MVT VT = MVT::getIntegerVT(NumBytes*8); 5785 if (!DC->isTypeLegal(VT)) 5786 return 0; 5787 5788 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 5789 // shifted by ByteShift and truncated down to NumBytes. 5790 if (ByteShift) 5791 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 5792 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy())); 5793 5794 // Figure out the offset for the store and the alignment of the access. 5795 unsigned StOffset; 5796 unsigned NewAlign = St->getAlignment(); 5797 5798 if (DAG.getTargetLoweringInfo().isLittleEndian()) 5799 StOffset = ByteShift; 5800 else 5801 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 5802 5803 SDValue Ptr = St->getBasePtr(); 5804 if (StOffset) { 5805 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 5806 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 5807 NewAlign = MinAlign(NewAlign, StOffset); 5808 } 5809 5810 // Truncate down to the new size. 5811 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 5812 5813 ++OpsNarrowed; 5814 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 5815 St->getPointerInfo().getWithOffset(StOffset), 5816 false, false, NewAlign).getNode(); 5817} 5818 5819 5820/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5821/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5822/// of the loaded bits, try narrowing the load and store if it would end up 5823/// being a win for performance or code size. 5824SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5825 StoreSDNode *ST = cast<StoreSDNode>(N); 5826 if (ST->isVolatile()) 5827 return SDValue(); 5828 5829 SDValue Chain = ST->getChain(); 5830 SDValue Value = ST->getValue(); 5831 SDValue Ptr = ST->getBasePtr(); 5832 EVT VT = Value.getValueType(); 5833 5834 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5835 return SDValue(); 5836 5837 unsigned Opc = Value.getOpcode(); 5838 5839 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 5840 // is a byte mask indicating a consecutive number of bytes, check to see if 5841 // Y is known to provide just those bytes. If so, we try to replace the 5842 // load + replace + store sequence with a single (narrower) store, which makes 5843 // the load dead. 5844 if (Opc == ISD::OR) { 5845 std::pair<unsigned, unsigned> MaskedLoad; 5846 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 5847 if (MaskedLoad.first) 5848 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5849 Value.getOperand(1), ST,this)) 5850 return SDValue(NewST, 0); 5851 5852 // Or is commutative, so try swapping X and Y. 5853 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 5854 if (MaskedLoad.first) 5855 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5856 Value.getOperand(0), ST,this)) 5857 return SDValue(NewST, 0); 5858 } 5859 5860 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5861 Value.getOperand(1).getOpcode() != ISD::Constant) 5862 return SDValue(); 5863 5864 SDValue N0 = Value.getOperand(0); 5865 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5866 Chain == SDValue(N0.getNode(), 1)) { 5867 LoadSDNode *LD = cast<LoadSDNode>(N0); 5868 if (LD->getBasePtr() != Ptr || 5869 LD->getPointerInfo().getAddrSpace() != 5870 ST->getPointerInfo().getAddrSpace()) 5871 return SDValue(); 5872 5873 // Find the type to narrow it the load / op / store to. 5874 SDValue N1 = Value.getOperand(1); 5875 unsigned BitWidth = N1.getValueSizeInBits(); 5876 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5877 if (Opc == ISD::AND) 5878 Imm ^= APInt::getAllOnesValue(BitWidth); 5879 if (Imm == 0 || Imm.isAllOnesValue()) 5880 return SDValue(); 5881 unsigned ShAmt = Imm.countTrailingZeros(); 5882 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5883 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5884 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5885 while (NewBW < BitWidth && 5886 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5887 TLI.isNarrowingProfitable(VT, NewVT))) { 5888 NewBW = NextPowerOf2(NewBW); 5889 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5890 } 5891 if (NewBW >= BitWidth) 5892 return SDValue(); 5893 5894 // If the lsb changed does not start at the type bitwidth boundary, 5895 // start at the previous one. 5896 if (ShAmt % NewBW) 5897 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5898 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5899 if ((Imm & Mask) == Imm) { 5900 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5901 if (Opc == ISD::AND) 5902 NewImm ^= APInt::getAllOnesValue(NewBW); 5903 uint64_t PtrOff = ShAmt / 8; 5904 // For big endian targets, we need to adjust the offset to the pointer to 5905 // load the correct bytes. 5906 if (TLI.isBigEndian()) 5907 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5908 5909 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5910 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 5911 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 5912 return SDValue(); 5913 5914 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5915 Ptr.getValueType(), Ptr, 5916 DAG.getConstant(PtrOff, Ptr.getValueType())); 5917 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5918 LD->getChain(), NewPtr, 5919 LD->getPointerInfo().getWithOffset(PtrOff), 5920 LD->isVolatile(), LD->isNonTemporal(), 5921 NewAlign); 5922 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5923 DAG.getConstant(NewImm, NewVT)); 5924 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5925 NewVal, NewPtr, 5926 ST->getPointerInfo().getWithOffset(PtrOff), 5927 false, false, NewAlign); 5928 5929 AddToWorkList(NewPtr.getNode()); 5930 AddToWorkList(NewLD.getNode()); 5931 AddToWorkList(NewVal.getNode()); 5932 WorkListRemover DeadNodes(*this); 5933 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5934 &DeadNodes); 5935 ++OpsNarrowed; 5936 return NewST; 5937 } 5938 } 5939 5940 return SDValue(); 5941} 5942 5943SDValue DAGCombiner::visitSTORE(SDNode *N) { 5944 StoreSDNode *ST = cast<StoreSDNode>(N); 5945 SDValue Chain = ST->getChain(); 5946 SDValue Value = ST->getValue(); 5947 SDValue Ptr = ST->getBasePtr(); 5948 5949 // If this is a store of a bit convert, store the input value if the 5950 // resultant store does not need a higher alignment than the original. 5951 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 5952 ST->isUnindexed()) { 5953 unsigned OrigAlign = ST->getAlignment(); 5954 EVT SVT = Value.getOperand(0).getValueType(); 5955 unsigned Align = TLI.getTargetData()-> 5956 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5957 if (Align <= OrigAlign && 5958 ((!LegalOperations && !ST->isVolatile()) || 5959 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5960 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5961 Ptr, ST->getPointerInfo(), ST->isVolatile(), 5962 ST->isNonTemporal(), OrigAlign); 5963 } 5964 5965 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5966 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5967 // NOTE: If the original store is volatile, this transform must not increase 5968 // the number of stores. For example, on x86-32 an f64 can be stored in one 5969 // processor operation but an i64 (which is not legal) requires two. So the 5970 // transform should not be done in this case. 5971 if (Value.getOpcode() != ISD::TargetConstantFP) { 5972 SDValue Tmp; 5973 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5974 default: llvm_unreachable("Unknown FP type"); 5975 case MVT::f80: // We don't do this for these yet. 5976 case MVT::f128: 5977 case MVT::ppcf128: 5978 break; 5979 case MVT::f32: 5980 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 5981 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5982 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5983 bitcastToAPInt().getZExtValue(), MVT::i32); 5984 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5985 Ptr, ST->getPointerInfo(), ST->isVolatile(), 5986 ST->isNonTemporal(), ST->getAlignment()); 5987 } 5988 break; 5989 case MVT::f64: 5990 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 5991 !ST->isVolatile()) || 5992 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5993 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5994 getZExtValue(), MVT::i64); 5995 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5996 Ptr, ST->getPointerInfo(), ST->isVolatile(), 5997 ST->isNonTemporal(), ST->getAlignment()); 5998 } else if (!ST->isVolatile() && 5999 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6000 // Many FP stores are not made apparent until after legalize, e.g. for 6001 // argument passing. Since this is so common, custom legalize the 6002 // 64-bit integer store into two 32-bit stores. 6003 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6004 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6005 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6006 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6007 6008 unsigned Alignment = ST->getAlignment(); 6009 bool isVolatile = ST->isVolatile(); 6010 bool isNonTemporal = ST->isNonTemporal(); 6011 6012 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6013 Ptr, ST->getPointerInfo(), 6014 isVolatile, isNonTemporal, 6015 ST->getAlignment()); 6016 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6017 DAG.getConstant(4, Ptr.getValueType())); 6018 Alignment = MinAlign(Alignment, 4U); 6019 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6020 Ptr, ST->getPointerInfo().getWithOffset(4), 6021 isVolatile, isNonTemporal, 6022 Alignment); 6023 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6024 St0, St1); 6025 } 6026 6027 break; 6028 } 6029 } 6030 } 6031 6032 // Try to infer better alignment information than the store already has. 6033 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6034 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6035 if (Align > ST->getAlignment()) 6036 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6037 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6038 ST->isVolatile(), ST->isNonTemporal(), Align); 6039 } 6040 } 6041 6042 if (CombinerAA) { 6043 // Walk up chain skipping non-aliasing memory nodes. 6044 SDValue BetterChain = FindBetterChain(N, Chain); 6045 6046 // If there is a better chain. 6047 if (Chain != BetterChain) { 6048 SDValue ReplStore; 6049 6050 // Replace the chain to avoid dependency. 6051 if (ST->isTruncatingStore()) { 6052 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6053 ST->getPointerInfo(), 6054 ST->getMemoryVT(), ST->isVolatile(), 6055 ST->isNonTemporal(), ST->getAlignment()); 6056 } else { 6057 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6058 ST->getPointerInfo(), 6059 ST->isVolatile(), ST->isNonTemporal(), 6060 ST->getAlignment()); 6061 } 6062 6063 // Create token to keep both nodes around. 6064 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6065 MVT::Other, Chain, ReplStore); 6066 6067 // Make sure the new and old chains are cleaned up. 6068 AddToWorkList(Token.getNode()); 6069 6070 // Don't add users to work list. 6071 return CombineTo(N, Token, false); 6072 } 6073 } 6074 6075 // Try transforming N to an indexed store. 6076 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6077 return SDValue(N, 0); 6078 6079 // FIXME: is there such a thing as a truncating indexed store? 6080 if (ST->isTruncatingStore() && ST->isUnindexed() && 6081 Value.getValueType().isInteger()) { 6082 // See if we can simplify the input to this truncstore with knowledge that 6083 // only the low bits are being used. For example: 6084 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6085 SDValue Shorter = 6086 GetDemandedBits(Value, 6087 APInt::getLowBitsSet(Value.getValueSizeInBits(), 6088 ST->getMemoryVT().getSizeInBits())); 6089 AddToWorkList(Value.getNode()); 6090 if (Shorter.getNode()) 6091 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6092 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6093 ST->isVolatile(), ST->isNonTemporal(), 6094 ST->getAlignment()); 6095 6096 // Otherwise, see if we can simplify the operation with 6097 // SimplifyDemandedBits, which only works if the value has a single use. 6098 if (SimplifyDemandedBits(Value, 6099 APInt::getLowBitsSet( 6100 Value.getValueType().getScalarType().getSizeInBits(), 6101 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6102 return SDValue(N, 0); 6103 } 6104 6105 // If this is a load followed by a store to the same location, then the store 6106 // is dead/noop. 6107 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6108 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6109 ST->isUnindexed() && !ST->isVolatile() && 6110 // There can't be any side effects between the load and store, such as 6111 // a call or store. 6112 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6113 // The store is dead, remove it. 6114 return Chain; 6115 } 6116 } 6117 6118 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6119 // truncating store. We can do this even if this is already a truncstore. 6120 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6121 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6122 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6123 ST->getMemoryVT())) { 6124 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6125 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6126 ST->isVolatile(), ST->isNonTemporal(), 6127 ST->getAlignment()); 6128 } 6129 6130 return ReduceLoadOpStoreWidth(N); 6131} 6132 6133SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6134 SDValue InVec = N->getOperand(0); 6135 SDValue InVal = N->getOperand(1); 6136 SDValue EltNo = N->getOperand(2); 6137 6138 // If the inserted element is an UNDEF, just use the input vector. 6139 if (InVal.getOpcode() == ISD::UNDEF) 6140 return InVec; 6141 6142 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6143 // vector with the inserted element. 6144 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6145 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6146 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6147 InVec.getNode()->op_end()); 6148 if (Elt < Ops.size()) 6149 Ops[Elt] = InVal; 6150 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6151 InVec.getValueType(), &Ops[0], Ops.size()); 6152 } 6153 // If the invec is an UNDEF and if EltNo is a constant, create a new 6154 // BUILD_VECTOR with undef elements and the inserted element. 6155 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 6156 isa<ConstantSDNode>(EltNo)) { 6157 EVT VT = InVec.getValueType(); 6158 EVT EltVT = VT.getVectorElementType(); 6159 unsigned NElts = VT.getVectorNumElements(); 6160 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6161 6162 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6163 if (Elt < Ops.size()) 6164 Ops[Elt] = InVal; 6165 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6166 InVec.getValueType(), &Ops[0], Ops.size()); 6167 } 6168 return SDValue(); 6169} 6170 6171SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6172 // (vextract (scalar_to_vector val, 0) -> val 6173 SDValue InVec = N->getOperand(0); 6174 6175 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6176 // Check if the result type doesn't match the inserted element type. A 6177 // SCALAR_TO_VECTOR may truncate the inserted element and the 6178 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6179 SDValue InOp = InVec.getOperand(0); 6180 EVT NVT = N->getValueType(0); 6181 if (InOp.getValueType() != NVT) { 6182 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6183 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6184 } 6185 return InOp; 6186 } 6187 6188 // Perform only after legalization to ensure build_vector / vector_shuffle 6189 // optimizations have already been done. 6190 if (!LegalOperations) return SDValue(); 6191 6192 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6193 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6194 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6195 SDValue EltNo = N->getOperand(1); 6196 6197 if (isa<ConstantSDNode>(EltNo)) { 6198 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6199 bool NewLoad = false; 6200 bool BCNumEltsChanged = false; 6201 EVT VT = InVec.getValueType(); 6202 EVT ExtVT = VT.getVectorElementType(); 6203 EVT LVT = ExtVT; 6204 6205 if (InVec.getOpcode() == ISD::BITCAST) { 6206 EVT BCVT = InVec.getOperand(0).getValueType(); 6207 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6208 return SDValue(); 6209 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6210 BCNumEltsChanged = true; 6211 InVec = InVec.getOperand(0); 6212 ExtVT = BCVT.getVectorElementType(); 6213 NewLoad = true; 6214 } 6215 6216 LoadSDNode *LN0 = NULL; 6217 const ShuffleVectorSDNode *SVN = NULL; 6218 if (ISD::isNormalLoad(InVec.getNode())) { 6219 LN0 = cast<LoadSDNode>(InVec); 6220 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6221 InVec.getOperand(0).getValueType() == ExtVT && 6222 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6223 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6224 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6225 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6226 // => 6227 // (load $addr+1*size) 6228 6229 // If the bit convert changed the number of elements, it is unsafe 6230 // to examine the mask. 6231 if (BCNumEltsChanged) 6232 return SDValue(); 6233 6234 // Select the input vector, guarding against out of range extract vector. 6235 unsigned NumElems = VT.getVectorNumElements(); 6236 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 6237 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6238 6239 if (InVec.getOpcode() == ISD::BITCAST) 6240 InVec = InVec.getOperand(0); 6241 if (ISD::isNormalLoad(InVec.getNode())) { 6242 LN0 = cast<LoadSDNode>(InVec); 6243 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6244 } 6245 } 6246 6247 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 6248 return SDValue(); 6249 6250 // If Idx was -1 above, Elt is going to be -1, so just return undef. 6251 if (Elt == -1) 6252 return DAG.getUNDEF(LN0->getBasePtr().getValueType()); 6253 6254 unsigned Align = LN0->getAlignment(); 6255 if (NewLoad) { 6256 // Check the resultant load doesn't need a higher alignment than the 6257 // original load. 6258 unsigned NewAlign = 6259 TLI.getTargetData() 6260 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6261 6262 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6263 return SDValue(); 6264 6265 Align = NewAlign; 6266 } 6267 6268 SDValue NewPtr = LN0->getBasePtr(); 6269 unsigned PtrOff = 0; 6270 6271 if (Elt) { 6272 PtrOff = LVT.getSizeInBits() * Elt / 8; 6273 EVT PtrType = NewPtr.getValueType(); 6274 if (TLI.isBigEndian()) 6275 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6276 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6277 DAG.getConstant(PtrOff, PtrType)); 6278 } 6279 6280 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6281 LN0->getPointerInfo().getWithOffset(PtrOff), 6282 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6283 } 6284 6285 return SDValue(); 6286} 6287 6288SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6289 unsigned NumInScalars = N->getNumOperands(); 6290 EVT VT = N->getValueType(0); 6291 6292 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6293 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6294 // at most two distinct vectors, turn this into a shuffle node. 6295 SDValue VecIn1, VecIn2; 6296 for (unsigned i = 0; i != NumInScalars; ++i) { 6297 // Ignore undef inputs. 6298 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6299 6300 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6301 // constant index, bail out. 6302 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6303 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6304 VecIn1 = VecIn2 = SDValue(0, 0); 6305 break; 6306 } 6307 6308 // If the input vector type disagrees with the result of the build_vector, 6309 // we can't make a shuffle. 6310 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6311 if (ExtractedFromVec.getValueType() != VT) { 6312 VecIn1 = VecIn2 = SDValue(0, 0); 6313 break; 6314 } 6315 6316 // Otherwise, remember this. We allow up to two distinct input vectors. 6317 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6318 continue; 6319 6320 if (VecIn1.getNode() == 0) { 6321 VecIn1 = ExtractedFromVec; 6322 } else if (VecIn2.getNode() == 0) { 6323 VecIn2 = ExtractedFromVec; 6324 } else { 6325 // Too many inputs. 6326 VecIn1 = VecIn2 = SDValue(0, 0); 6327 break; 6328 } 6329 } 6330 6331 // If everything is good, we can make a shuffle operation. 6332 if (VecIn1.getNode()) { 6333 SmallVector<int, 8> Mask; 6334 for (unsigned i = 0; i != NumInScalars; ++i) { 6335 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6336 Mask.push_back(-1); 6337 continue; 6338 } 6339 6340 // If extracting from the first vector, just use the index directly. 6341 SDValue Extract = N->getOperand(i); 6342 SDValue ExtVal = Extract.getOperand(1); 6343 if (Extract.getOperand(0) == VecIn1) { 6344 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6345 if (ExtIndex > VT.getVectorNumElements()) 6346 return SDValue(); 6347 6348 Mask.push_back(ExtIndex); 6349 continue; 6350 } 6351 6352 // Otherwise, use InIdx + VecSize 6353 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6354 Mask.push_back(Idx+NumInScalars); 6355 } 6356 6357 // Add count and size info. 6358 if (!isTypeLegal(VT)) 6359 return SDValue(); 6360 6361 // Return the new VECTOR_SHUFFLE node. 6362 SDValue Ops[2]; 6363 Ops[0] = VecIn1; 6364 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6365 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6366 } 6367 6368 return SDValue(); 6369} 6370 6371SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6372 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6373 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6374 // inputs come from at most two distinct vectors, turn this into a shuffle 6375 // node. 6376 6377 // If we only have one input vector, we don't need to do any concatenation. 6378 if (N->getNumOperands() == 1) 6379 return N->getOperand(0); 6380 6381 return SDValue(); 6382} 6383 6384SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6385 EVT VT = N->getValueType(0); 6386 unsigned NumElts = VT.getVectorNumElements(); 6387 6388 SDValue N0 = N->getOperand(0); 6389 6390 assert(N0.getValueType().getVectorNumElements() == NumElts && 6391 "Vector shuffle must be normalized in DAG"); 6392 6393 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6394 6395 // If it is a splat, check if the argument vector is another splat or a 6396 // build_vector with all scalar elements the same. 6397 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 6398 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 6399 SDNode *V = N0.getNode(); 6400 6401 // If this is a bit convert that changes the element type of the vector but 6402 // not the number of vector elements, look through it. Be careful not to 6403 // look though conversions that change things like v4f32 to v2f64. 6404 if (V->getOpcode() == ISD::BITCAST) { 6405 SDValue ConvInput = V->getOperand(0); 6406 if (ConvInput.getValueType().isVector() && 6407 ConvInput.getValueType().getVectorNumElements() == NumElts) 6408 V = ConvInput.getNode(); 6409 } 6410 6411 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6412 assert(V->getNumOperands() == NumElts && 6413 "BUILD_VECTOR has wrong number of operands"); 6414 SDValue Base; 6415 bool AllSame = true; 6416 for (unsigned i = 0; i != NumElts; ++i) { 6417 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6418 Base = V->getOperand(i); 6419 break; 6420 } 6421 } 6422 // Splat of <u, u, u, u>, return <u, u, u, u> 6423 if (!Base.getNode()) 6424 return N0; 6425 for (unsigned i = 0; i != NumElts; ++i) { 6426 if (V->getOperand(i) != Base) { 6427 AllSame = false; 6428 break; 6429 } 6430 } 6431 // Splat of <x, x, x, x>, return <x, x, x, x> 6432 if (AllSame) 6433 return N0; 6434 } 6435 } 6436 return SDValue(); 6437} 6438 6439SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 6440 if (!TLI.getShouldFoldAtomicFences()) 6441 return SDValue(); 6442 6443 SDValue atomic = N->getOperand(0); 6444 switch (atomic.getOpcode()) { 6445 case ISD::ATOMIC_CMP_SWAP: 6446 case ISD::ATOMIC_SWAP: 6447 case ISD::ATOMIC_LOAD_ADD: 6448 case ISD::ATOMIC_LOAD_SUB: 6449 case ISD::ATOMIC_LOAD_AND: 6450 case ISD::ATOMIC_LOAD_OR: 6451 case ISD::ATOMIC_LOAD_XOR: 6452 case ISD::ATOMIC_LOAD_NAND: 6453 case ISD::ATOMIC_LOAD_MIN: 6454 case ISD::ATOMIC_LOAD_MAX: 6455 case ISD::ATOMIC_LOAD_UMIN: 6456 case ISD::ATOMIC_LOAD_UMAX: 6457 break; 6458 default: 6459 return SDValue(); 6460 } 6461 6462 SDValue fence = atomic.getOperand(0); 6463 if (fence.getOpcode() != ISD::MEMBARRIER) 6464 return SDValue(); 6465 6466 switch (atomic.getOpcode()) { 6467 case ISD::ATOMIC_CMP_SWAP: 6468 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6469 fence.getOperand(0), 6470 atomic.getOperand(1), atomic.getOperand(2), 6471 atomic.getOperand(3)), atomic.getResNo()); 6472 case ISD::ATOMIC_SWAP: 6473 case ISD::ATOMIC_LOAD_ADD: 6474 case ISD::ATOMIC_LOAD_SUB: 6475 case ISD::ATOMIC_LOAD_AND: 6476 case ISD::ATOMIC_LOAD_OR: 6477 case ISD::ATOMIC_LOAD_XOR: 6478 case ISD::ATOMIC_LOAD_NAND: 6479 case ISD::ATOMIC_LOAD_MIN: 6480 case ISD::ATOMIC_LOAD_MAX: 6481 case ISD::ATOMIC_LOAD_UMIN: 6482 case ISD::ATOMIC_LOAD_UMAX: 6483 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6484 fence.getOperand(0), 6485 atomic.getOperand(1), atomic.getOperand(2)), 6486 atomic.getResNo()); 6487 default: 6488 return SDValue(); 6489 } 6490} 6491 6492/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6493/// an AND to a vector_shuffle with the destination vector and a zero vector. 6494/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6495/// vector_shuffle V, Zero, <0, 4, 2, 4> 6496SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6497 EVT VT = N->getValueType(0); 6498 DebugLoc dl = N->getDebugLoc(); 6499 SDValue LHS = N->getOperand(0); 6500 SDValue RHS = N->getOperand(1); 6501 if (N->getOpcode() == ISD::AND) { 6502 if (RHS.getOpcode() == ISD::BITCAST) 6503 RHS = RHS.getOperand(0); 6504 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6505 SmallVector<int, 8> Indices; 6506 unsigned NumElts = RHS.getNumOperands(); 6507 for (unsigned i = 0; i != NumElts; ++i) { 6508 SDValue Elt = RHS.getOperand(i); 6509 if (!isa<ConstantSDNode>(Elt)) 6510 return SDValue(); 6511 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6512 Indices.push_back(i); 6513 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6514 Indices.push_back(NumElts); 6515 else 6516 return SDValue(); 6517 } 6518 6519 // Let's see if the target supports this vector_shuffle. 6520 EVT RVT = RHS.getValueType(); 6521 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6522 return SDValue(); 6523 6524 // Return the new VECTOR_SHUFFLE node. 6525 EVT EltVT = RVT.getVectorElementType(); 6526 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6527 DAG.getConstant(0, EltVT)); 6528 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6529 RVT, &ZeroOps[0], ZeroOps.size()); 6530 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 6531 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6532 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 6533 } 6534 } 6535 6536 return SDValue(); 6537} 6538 6539/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6540SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6541 // After legalize, the target may be depending on adds and other 6542 // binary ops to provide legal ways to construct constants or other 6543 // things. Simplifying them may result in a loss of legality. 6544 if (LegalOperations) return SDValue(); 6545 6546 EVT VT = N->getValueType(0); 6547 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 6548 6549 EVT EltType = VT.getVectorElementType(); 6550 SDValue LHS = N->getOperand(0); 6551 SDValue RHS = N->getOperand(1); 6552 SDValue Shuffle = XformToShuffleWithZero(N); 6553 if (Shuffle.getNode()) return Shuffle; 6554 6555 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6556 // this operation. 6557 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6558 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6559 SmallVector<SDValue, 8> Ops; 6560 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6561 SDValue LHSOp = LHS.getOperand(i); 6562 SDValue RHSOp = RHS.getOperand(i); 6563 // If these two elements can't be folded, bail out. 6564 if ((LHSOp.getOpcode() != ISD::UNDEF && 6565 LHSOp.getOpcode() != ISD::Constant && 6566 LHSOp.getOpcode() != ISD::ConstantFP) || 6567 (RHSOp.getOpcode() != ISD::UNDEF && 6568 RHSOp.getOpcode() != ISD::Constant && 6569 RHSOp.getOpcode() != ISD::ConstantFP)) 6570 break; 6571 6572 // Can't fold divide by zero. 6573 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6574 N->getOpcode() == ISD::FDIV) { 6575 if ((RHSOp.getOpcode() == ISD::Constant && 6576 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6577 (RHSOp.getOpcode() == ISD::ConstantFP && 6578 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6579 break; 6580 } 6581 6582 // If the vector element type is not legal, the BUILD_VECTOR operands 6583 // are promoted and implicitly truncated. Make that explicit here. 6584 if (LHSOp.getValueType() != EltType) 6585 LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp); 6586 if (RHSOp.getValueType() != EltType) 6587 RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp); 6588 6589 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType, 6590 LHSOp, RHSOp); 6591 if (FoldOp.getOpcode() != ISD::UNDEF && 6592 FoldOp.getOpcode() != ISD::Constant && 6593 FoldOp.getOpcode() != ISD::ConstantFP) 6594 break; 6595 Ops.push_back(FoldOp); 6596 AddToWorkList(FoldOp.getNode()); 6597 } 6598 6599 if (Ops.size() == LHS.getNumOperands()) { 6600 EVT VT = LHS.getValueType(); 6601 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 6602 &Ops[0], Ops.size()); 6603 } 6604 } 6605 6606 return SDValue(); 6607} 6608 6609SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6610 SDValue N1, SDValue N2){ 6611 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6612 6613 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6614 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6615 6616 // If we got a simplified select_cc node back from SimplifySelectCC, then 6617 // break it down into a new SETCC node, and a new SELECT node, and then return 6618 // the SELECT node, since we were called with a SELECT node. 6619 if (SCC.getNode()) { 6620 // Check to see if we got a select_cc back (to turn into setcc/select). 6621 // Otherwise, just return whatever node we got back, like fabs. 6622 if (SCC.getOpcode() == ISD::SELECT_CC) { 6623 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6624 N0.getValueType(), 6625 SCC.getOperand(0), SCC.getOperand(1), 6626 SCC.getOperand(4)); 6627 AddToWorkList(SETCC.getNode()); 6628 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6629 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6630 } 6631 6632 return SCC; 6633 } 6634 return SDValue(); 6635} 6636 6637/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6638/// are the two values being selected between, see if we can simplify the 6639/// select. Callers of this should assume that TheSelect is deleted if this 6640/// returns true. As such, they should return the appropriate thing (e.g. the 6641/// node) back to the top-level of the DAG combiner loop to avoid it being 6642/// looked at. 6643bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6644 SDValue RHS) { 6645 6646 // If this is a select from two identical things, try to pull the operation 6647 // through the select. 6648 if (LHS.getOpcode() != RHS.getOpcode() || 6649 !LHS.hasOneUse() || !RHS.hasOneUse()) 6650 return false; 6651 6652 // If this is a load and the token chain is identical, replace the select 6653 // of two loads with a load through a select of the address to load from. 6654 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6655 // constants have been dropped into the constant pool. 6656 if (LHS.getOpcode() == ISD::LOAD) { 6657 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6658 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6659 6660 // Token chains must be identical. 6661 if (LHS.getOperand(0) != RHS.getOperand(0) || 6662 // Do not let this transformation reduce the number of volatile loads. 6663 LLD->isVolatile() || RLD->isVolatile() || 6664 // If this is an EXTLOAD, the VT's must match. 6665 LLD->getMemoryVT() != RLD->getMemoryVT() || 6666 // If this is an EXTLOAD, the kind of extension must match. 6667 (LLD->getExtensionType() != RLD->getExtensionType() && 6668 // The only exception is if one of the extensions is anyext. 6669 LLD->getExtensionType() != ISD::EXTLOAD && 6670 RLD->getExtensionType() != ISD::EXTLOAD) || 6671 // FIXME: this discards src value information. This is 6672 // over-conservative. It would be beneficial to be able to remember 6673 // both potential memory locations. Since we are discarding 6674 // src value info, don't do the transformation if the memory 6675 // locations are not in the default address space. 6676 LLD->getPointerInfo().getAddrSpace() != 0 || 6677 RLD->getPointerInfo().getAddrSpace() != 0) 6678 return false; 6679 6680 // Check that the select condition doesn't reach either load. If so, 6681 // folding this will induce a cycle into the DAG. If not, this is safe to 6682 // xform, so create a select of the addresses. 6683 SDValue Addr; 6684 if (TheSelect->getOpcode() == ISD::SELECT) { 6685 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 6686 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 6687 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 6688 return false; 6689 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 6690 LLD->getBasePtr().getValueType(), 6691 TheSelect->getOperand(0), LLD->getBasePtr(), 6692 RLD->getBasePtr()); 6693 } else { // Otherwise SELECT_CC 6694 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 6695 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 6696 6697 if ((LLD->hasAnyUseOfValue(1) && 6698 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 6699 (LLD->hasAnyUseOfValue(1) && 6700 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 6701 return false; 6702 6703 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 6704 LLD->getBasePtr().getValueType(), 6705 TheSelect->getOperand(0), 6706 TheSelect->getOperand(1), 6707 LLD->getBasePtr(), RLD->getBasePtr(), 6708 TheSelect->getOperand(4)); 6709 } 6710 6711 SDValue Load; 6712 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 6713 Load = DAG.getLoad(TheSelect->getValueType(0), 6714 TheSelect->getDebugLoc(), 6715 // FIXME: Discards pointer info. 6716 LLD->getChain(), Addr, MachinePointerInfo(), 6717 LLD->isVolatile(), LLD->isNonTemporal(), 6718 LLD->getAlignment()); 6719 } else { 6720 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 6721 RLD->getExtensionType() : LLD->getExtensionType(), 6722 TheSelect->getValueType(0), 6723 TheSelect->getDebugLoc(), 6724 // FIXME: Discards pointer info. 6725 LLD->getChain(), Addr, MachinePointerInfo(), 6726 LLD->getMemoryVT(), LLD->isVolatile(), 6727 LLD->isNonTemporal(), LLD->getAlignment()); 6728 } 6729 6730 // Users of the select now use the result of the load. 6731 CombineTo(TheSelect, Load); 6732 6733 // Users of the old loads now use the new load's chain. We know the 6734 // old-load value is dead now. 6735 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 6736 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 6737 return true; 6738 } 6739 6740 return false; 6741} 6742 6743/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 6744/// where 'cond' is the comparison specified by CC. 6745SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 6746 SDValue N2, SDValue N3, 6747 ISD::CondCode CC, bool NotExtCompare) { 6748 // (x ? y : y) -> y. 6749 if (N2 == N3) return N2; 6750 6751 EVT VT = N2.getValueType(); 6752 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 6753 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 6754 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 6755 6756 // Determine if the condition we're dealing with is constant 6757 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 6758 N0, N1, CC, DL, false); 6759 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 6760 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 6761 6762 // fold select_cc true, x, y -> x 6763 if (SCCC && !SCCC->isNullValue()) 6764 return N2; 6765 // fold select_cc false, x, y -> y 6766 if (SCCC && SCCC->isNullValue()) 6767 return N3; 6768 6769 // Check to see if we can simplify the select into an fabs node 6770 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 6771 // Allow either -0.0 or 0.0 6772 if (CFP->getValueAPF().isZero()) { 6773 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 6774 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 6775 N0 == N2 && N3.getOpcode() == ISD::FNEG && 6776 N2 == N3.getOperand(0)) 6777 return DAG.getNode(ISD::FABS, DL, VT, N0); 6778 6779 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 6780 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 6781 N0 == N3 && N2.getOpcode() == ISD::FNEG && 6782 N2.getOperand(0) == N3) 6783 return DAG.getNode(ISD::FABS, DL, VT, N3); 6784 } 6785 } 6786 6787 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 6788 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 6789 // in it. This is a win when the constant is not otherwise available because 6790 // it replaces two constant pool loads with one. We only do this if the FP 6791 // type is known to be legal, because if it isn't, then we are before legalize 6792 // types an we want the other legalization to happen first (e.g. to avoid 6793 // messing with soft float) and if the ConstantFP is not legal, because if 6794 // it is legal, we may not need to store the FP constant in a constant pool. 6795 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 6796 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 6797 if (TLI.isTypeLegal(N2.getValueType()) && 6798 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 6799 TargetLowering::Legal) && 6800 // If both constants have multiple uses, then we won't need to do an 6801 // extra load, they are likely around in registers for other users. 6802 (TV->hasOneUse() || FV->hasOneUse())) { 6803 Constant *Elts[] = { 6804 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6805 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6806 }; 6807 const Type *FPTy = Elts[0]->getType(); 6808 const TargetData &TD = *TLI.getTargetData(); 6809 6810 // Create a ConstantArray of the two constants. 6811 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6812 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6813 TD.getPrefTypeAlignment(FPTy)); 6814 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6815 6816 // Get the offsets to the 0 and 1 element of the array so that we can 6817 // select between them. 6818 SDValue Zero = DAG.getIntPtrConstant(0); 6819 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6820 SDValue One = DAG.getIntPtrConstant(EltSize); 6821 6822 SDValue Cond = DAG.getSetCC(DL, 6823 TLI.getSetCCResultType(N0.getValueType()), 6824 N0, N1, CC); 6825 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6826 Cond, One, Zero); 6827 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6828 CstOffset); 6829 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6830 MachinePointerInfo::getConstantPool(), false, 6831 false, Alignment); 6832 6833 } 6834 } 6835 6836 // Check to see if we can perform the "gzip trick", transforming 6837 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6838 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6839 N0.getValueType().isInteger() && 6840 N2.getValueType().isInteger() && 6841 (N1C->isNullValue() || // (a < 0) ? b : 0 6842 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6843 EVT XType = N0.getValueType(); 6844 EVT AType = N2.getValueType(); 6845 if (XType.bitsGE(AType)) { 6846 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6847 // single-bit constant. 6848 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6849 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6850 ShCtV = XType.getSizeInBits()-ShCtV-1; 6851 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6852 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6853 XType, N0, ShCt); 6854 AddToWorkList(Shift.getNode()); 6855 6856 if (XType.bitsGT(AType)) { 6857 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6858 AddToWorkList(Shift.getNode()); 6859 } 6860 6861 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6862 } 6863 6864 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6865 XType, N0, 6866 DAG.getConstant(XType.getSizeInBits()-1, 6867 getShiftAmountTy())); 6868 AddToWorkList(Shift.getNode()); 6869 6870 if (XType.bitsGT(AType)) { 6871 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6872 AddToWorkList(Shift.getNode()); 6873 } 6874 6875 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6876 } 6877 } 6878 6879 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 6880 // where y is has a single bit set. 6881 // A plaintext description would be, we can turn the SELECT_CC into an AND 6882 // when the condition can be materialized as an all-ones register. Any 6883 // single bit-test can be materialized as an all-ones register with 6884 // shift-left and shift-right-arith. 6885 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 6886 N0->getValueType(0) == VT && 6887 N1C && N1C->isNullValue() && 6888 N2C && N2C->isNullValue()) { 6889 SDValue AndLHS = N0->getOperand(0); 6890 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 6891 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 6892 // Shift the tested bit over the sign bit. 6893 APInt AndMask = ConstAndRHS->getAPIntValue(); 6894 SDValue ShlAmt = 6895 DAG.getConstant(AndMask.countLeadingZeros(), getShiftAmountTy()); 6896 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 6897 6898 // Now arithmetic right shift it all the way over, so the result is either 6899 // all-ones, or zero. 6900 SDValue ShrAmt = 6901 DAG.getConstant(AndMask.getBitWidth()-1, getShiftAmountTy()); 6902 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 6903 6904 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 6905 } 6906 } 6907 6908 // fold select C, 16, 0 -> shl C, 4 6909 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6910 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6911 6912 // If the caller doesn't want us to simplify this into a zext of a compare, 6913 // don't do it. 6914 if (NotExtCompare && N2C->getAPIntValue() == 1) 6915 return SDValue(); 6916 6917 // Get a SetCC of the condition 6918 // FIXME: Should probably make sure that setcc is legal if we ever have a 6919 // target where it isn't. 6920 SDValue Temp, SCC; 6921 // cast from setcc result type to select result type 6922 if (LegalTypes) { 6923 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6924 N0, N1, CC); 6925 if (N2.getValueType().bitsLT(SCC.getValueType())) 6926 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6927 else 6928 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6929 N2.getValueType(), SCC); 6930 } else { 6931 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6932 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6933 N2.getValueType(), SCC); 6934 } 6935 6936 AddToWorkList(SCC.getNode()); 6937 AddToWorkList(Temp.getNode()); 6938 6939 if (N2C->getAPIntValue() == 1) 6940 return Temp; 6941 6942 // shl setcc result by log2 n2c 6943 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6944 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6945 getShiftAmountTy())); 6946 } 6947 6948 // Check to see if this is the equivalent of setcc 6949 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6950 // otherwise, go ahead with the folds. 6951 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6952 EVT XType = N0.getValueType(); 6953 if (!LegalOperations || 6954 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6955 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6956 if (Res.getValueType() != VT) 6957 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6958 return Res; 6959 } 6960 6961 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6962 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6963 (!LegalOperations || 6964 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6965 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6966 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6967 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6968 getShiftAmountTy())); 6969 } 6970 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6971 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6972 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6973 XType, DAG.getConstant(0, XType), N0); 6974 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6975 return DAG.getNode(ISD::SRL, DL, XType, 6976 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6977 DAG.getConstant(XType.getSizeInBits()-1, 6978 getShiftAmountTy())); 6979 } 6980 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6981 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6982 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6983 DAG.getConstant(XType.getSizeInBits()-1, 6984 getShiftAmountTy())); 6985 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6986 } 6987 } 6988 6989 // Check to see if this is an integer abs. 6990 // select_cc setg[te] X, 0, X, -X -> 6991 // select_cc setgt X, -1, X, -X -> 6992 // select_cc setl[te] X, 0, -X, X -> 6993 // select_cc setlt X, 1, -X, X -> 6994 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6995 if (N1C) { 6996 ConstantSDNode *SubC = NULL; 6997 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 6998 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 6999 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7000 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7001 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7002 (N1C->isOne() && CC == ISD::SETLT)) && 7003 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7004 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7005 7006 EVT XType = N0.getValueType(); 7007 if (SubC && SubC->isNullValue() && XType.isInteger()) { 7008 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7009 N0, 7010 DAG.getConstant(XType.getSizeInBits()-1, 7011 getShiftAmountTy())); 7012 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7013 XType, N0, Shift); 7014 AddToWorkList(Shift.getNode()); 7015 AddToWorkList(Add.getNode()); 7016 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7017 } 7018 } 7019 7020 return SDValue(); 7021} 7022 7023/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 7024SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 7025 SDValue N1, ISD::CondCode Cond, 7026 DebugLoc DL, bool foldBooleans) { 7027 TargetLowering::DAGCombinerInfo 7028 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 7029 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 7030} 7031 7032/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 7033/// return a DAG expression to select that will generate the same value by 7034/// multiplying by a magic number. See: 7035/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7036SDValue DAGCombiner::BuildSDIV(SDNode *N) { 7037 std::vector<SDNode*> Built; 7038 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 7039 7040 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7041 ii != ee; ++ii) 7042 AddToWorkList(*ii); 7043 return S; 7044} 7045 7046/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 7047/// return a DAG expression to select that will generate the same value by 7048/// multiplying by a magic number. See: 7049/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7050SDValue DAGCombiner::BuildUDIV(SDNode *N) { 7051 std::vector<SDNode*> Built; 7052 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 7053 7054 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7055 ii != ee; ++ii) 7056 AddToWorkList(*ii); 7057 return S; 7058} 7059 7060/// FindBaseOffset - Return true if base is a frame index, which is known not 7061// to alias with anything but itself. Provides base object and offset as 7062// results. 7063static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7064 const GlobalValue *&GV, void *&CV) { 7065 // Assume it is a primitive operation. 7066 Base = Ptr; Offset = 0; GV = 0; CV = 0; 7067 7068 // If it's an adding a simple constant then integrate the offset. 7069 if (Base.getOpcode() == ISD::ADD) { 7070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7071 Base = Base.getOperand(0); 7072 Offset += C->getZExtValue(); 7073 } 7074 } 7075 7076 // Return the underlying GlobalValue, and update the Offset. Return false 7077 // for GlobalAddressSDNode since the same GlobalAddress may be represented 7078 // by multiple nodes with different offsets. 7079 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7080 GV = G->getGlobal(); 7081 Offset += G->getOffset(); 7082 return false; 7083 } 7084 7085 // Return the underlying Constant value, and update the Offset. Return false 7086 // for ConstantSDNodes since the same constant pool entry may be represented 7087 // by multiple nodes with different offsets. 7088 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7089 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7090 : (void *)C->getConstVal(); 7091 Offset += C->getOffset(); 7092 return false; 7093 } 7094 // If it's any of the following then it can't alias with anything but itself. 7095 return isa<FrameIndexSDNode>(Base); 7096} 7097 7098/// isAlias - Return true if there is any possibility that the two addresses 7099/// overlap. 7100bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7101 const Value *SrcValue1, int SrcValueOffset1, 7102 unsigned SrcValueAlign1, 7103 const MDNode *TBAAInfo1, 7104 SDValue Ptr2, int64_t Size2, 7105 const Value *SrcValue2, int SrcValueOffset2, 7106 unsigned SrcValueAlign2, 7107 const MDNode *TBAAInfo2) const { 7108 // If they are the same then they must be aliases. 7109 if (Ptr1 == Ptr2) return true; 7110 7111 // Gather base node and offset information. 7112 SDValue Base1, Base2; 7113 int64_t Offset1, Offset2; 7114 const GlobalValue *GV1, *GV2; 7115 void *CV1, *CV2; 7116 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7117 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7118 7119 // If they have a same base address then check to see if they overlap. 7120 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7121 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7122 7123 // It is possible for different frame indices to alias each other, mostly 7124 // when tail call optimization reuses return address slots for arguments. 7125 // To catch this case, look up the actual index of frame indices to compute 7126 // the real alias relationship. 7127 if (isFrameIndex1 && isFrameIndex2) { 7128 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7129 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7130 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7131 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7132 } 7133 7134 // Otherwise, if we know what the bases are, and they aren't identical, then 7135 // we know they cannot alias. 7136 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7137 return false; 7138 7139 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7140 // compared to the size and offset of the access, we may be able to prove they 7141 // do not alias. This check is conservative for now to catch cases created by 7142 // splitting vector types. 7143 if ((SrcValueAlign1 == SrcValueAlign2) && 7144 (SrcValueOffset1 != SrcValueOffset2) && 7145 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7146 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7147 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7148 7149 // There is no overlap between these relatively aligned accesses of similar 7150 // size, return no alias. 7151 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7152 return false; 7153 } 7154 7155 if (CombinerGlobalAA) { 7156 // Use alias analysis information. 7157 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7158 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7159 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7160 AliasAnalysis::AliasResult AAResult = 7161 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 7162 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 7163 if (AAResult == AliasAnalysis::NoAlias) 7164 return false; 7165 } 7166 7167 // Otherwise we have to assume they alias. 7168 return true; 7169} 7170 7171/// FindAliasInfo - Extracts the relevant alias information from the memory 7172/// node. Returns true if the operand was a load. 7173bool DAGCombiner::FindAliasInfo(SDNode *N, 7174 SDValue &Ptr, int64_t &Size, 7175 const Value *&SrcValue, 7176 int &SrcValueOffset, 7177 unsigned &SrcValueAlign, 7178 const MDNode *&TBAAInfo) const { 7179 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7180 Ptr = LD->getBasePtr(); 7181 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7182 SrcValue = LD->getSrcValue(); 7183 SrcValueOffset = LD->getSrcValueOffset(); 7184 SrcValueAlign = LD->getOriginalAlignment(); 7185 TBAAInfo = LD->getTBAAInfo(); 7186 return true; 7187 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7188 Ptr = ST->getBasePtr(); 7189 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7190 SrcValue = ST->getSrcValue(); 7191 SrcValueOffset = ST->getSrcValueOffset(); 7192 SrcValueAlign = ST->getOriginalAlignment(); 7193 TBAAInfo = ST->getTBAAInfo(); 7194 } else { 7195 llvm_unreachable("FindAliasInfo expected a memory operand"); 7196 } 7197 7198 return false; 7199} 7200 7201/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7202/// looking for aliasing nodes and adding them to the Aliases vector. 7203void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7204 SmallVector<SDValue, 8> &Aliases) { 7205 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7206 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7207 7208 // Get alias information for node. 7209 SDValue Ptr; 7210 int64_t Size; 7211 const Value *SrcValue; 7212 int SrcValueOffset; 7213 unsigned SrcValueAlign; 7214 const MDNode *SrcTBAAInfo; 7215 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7216 SrcValueAlign, SrcTBAAInfo); 7217 7218 // Starting off. 7219 Chains.push_back(OriginalChain); 7220 unsigned Depth = 0; 7221 7222 // Look at each chain and determine if it is an alias. If so, add it to the 7223 // aliases list. If not, then continue up the chain looking for the next 7224 // candidate. 7225 while (!Chains.empty()) { 7226 SDValue Chain = Chains.back(); 7227 Chains.pop_back(); 7228 7229 // For TokenFactor nodes, look at each operand and only continue up the 7230 // chain until we find two aliases. If we've seen two aliases, assume we'll 7231 // find more and revert to original chain since the xform is unlikely to be 7232 // profitable. 7233 // 7234 // FIXME: The depth check could be made to return the last non-aliasing 7235 // chain we found before we hit a tokenfactor rather than the original 7236 // chain. 7237 if (Depth > 6 || Aliases.size() == 2) { 7238 Aliases.clear(); 7239 Aliases.push_back(OriginalChain); 7240 break; 7241 } 7242 7243 // Don't bother if we've been before. 7244 if (!Visited.insert(Chain.getNode())) 7245 continue; 7246 7247 switch (Chain.getOpcode()) { 7248 case ISD::EntryToken: 7249 // Entry token is ideal chain operand, but handled in FindBetterChain. 7250 break; 7251 7252 case ISD::LOAD: 7253 case ISD::STORE: { 7254 // Get alias information for Chain. 7255 SDValue OpPtr; 7256 int64_t OpSize; 7257 const Value *OpSrcValue; 7258 int OpSrcValueOffset; 7259 unsigned OpSrcValueAlign; 7260 const MDNode *OpSrcTBAAInfo; 7261 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7262 OpSrcValue, OpSrcValueOffset, 7263 OpSrcValueAlign, 7264 OpSrcTBAAInfo); 7265 7266 // If chain is alias then stop here. 7267 if (!(IsLoad && IsOpLoad) && 7268 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7269 SrcTBAAInfo, 7270 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7271 OpSrcValueAlign, OpSrcTBAAInfo)) { 7272 Aliases.push_back(Chain); 7273 } else { 7274 // Look further up the chain. 7275 Chains.push_back(Chain.getOperand(0)); 7276 ++Depth; 7277 } 7278 break; 7279 } 7280 7281 case ISD::TokenFactor: 7282 // We have to check each of the operands of the token factor for "small" 7283 // token factors, so we queue them up. Adding the operands to the queue 7284 // (stack) in reverse order maintains the original order and increases the 7285 // likelihood that getNode will find a matching token factor (CSE.) 7286 if (Chain.getNumOperands() > 16) { 7287 Aliases.push_back(Chain); 7288 break; 7289 } 7290 for (unsigned n = Chain.getNumOperands(); n;) 7291 Chains.push_back(Chain.getOperand(--n)); 7292 ++Depth; 7293 break; 7294 7295 default: 7296 // For all other instructions we will just have to take what we can get. 7297 Aliases.push_back(Chain); 7298 break; 7299 } 7300 } 7301} 7302 7303/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7304/// for a better chain (aliasing node.) 7305SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7306 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7307 7308 // Accumulate all the aliases to this node. 7309 GatherAllAliases(N, OldChain, Aliases); 7310 7311 if (Aliases.size() == 0) { 7312 // If no operands then chain to entry token. 7313 return DAG.getEntryNode(); 7314 } else if (Aliases.size() == 1) { 7315 // If a single operand then chain to it. We don't need to revisit it. 7316 return Aliases[0]; 7317 } 7318 7319 // Construct a custom tailored token factor. 7320 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7321 &Aliases[0], Aliases.size()); 7322} 7323 7324// SelectionDAG::Combine - This is the entry point for the file. 7325// 7326void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7327 CodeGenOpt::Level OptLevel) { 7328 /// run - This is the main entry point to this class. 7329 /// 7330 DAGCombiner(*this, AA, OptLevel).Run(Level); 7331} 7332