DAGCombiner.cpp revision 517abf0ad2611e9d459b77ce8fd3a746dc382866
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 TargetLowering &TLI; 53 bool AfterLegalize; 54 bool Fast; 55 56 // Worklist of all of the nodes that need to be simplified. 57 std::vector<SDNode*> WorkList; 58 59 // AA - Used for DAG load/store alias analysis. 60 AliasAnalysis &AA; 61 62 /// AddUsersToWorkList - When an instruction is simplified, add all users of 63 /// the instruction to the work lists because they might get more simplified 64 /// now. 65 /// 66 void AddUsersToWorkList(SDNode *N) { 67 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 68 UI != UE; ++UI) 69 AddToWorkList(*UI); 70 } 71 72 /// visit - call the node-specific routine that knows how to fold each 73 /// particular type of node. 74 SDValue visit(SDNode *N); 75 76 public: 77 /// AddToWorkList - Add to the work list making sure it's instance is at the 78 /// the back (next to be processed.) 79 void AddToWorkList(SDNode *N) { 80 removeFromWorkList(N); 81 WorkList.push_back(N); 82 } 83 84 /// removeFromWorkList - remove all instances of N from the worklist. 85 /// 86 void removeFromWorkList(SDNode *N) { 87 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 88 WorkList.end()); 89 } 90 91 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 92 bool AddTo = true); 93 94 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 95 return CombineTo(N, &Res, 1, AddTo); 96 } 97 98 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 99 bool AddTo = true) { 100 SDValue To[] = { Res0, Res1 }; 101 return CombineTo(N, To, 2, AddTo); 102 } 103 104 private: 105 106 /// SimplifyDemandedBits - Check the specified integer node value to see if 107 /// it can be simplified or if things it uses can be simplified by bit 108 /// propagation. If so, return true. 109 bool SimplifyDemandedBits(SDValue Op) { 110 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 111 return SimplifyDemandedBits(Op, Demanded); 112 } 113 114 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 115 116 bool CombineToPreIndexedLoadStore(SDNode *N); 117 bool CombineToPostIndexedLoadStore(SDNode *N); 118 119 120 /// combine - call the node-specific routine that knows how to fold each 121 /// particular type of node. If that doesn't do anything, try the 122 /// target-specific DAG combines. 123 SDValue combine(SDNode *N); 124 125 // Visitation implementation - Implement dag node combining for different 126 // node types. The semantics are as follows: 127 // Return Value: 128 // SDValue.getNode() == 0 - No change was made 129 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 130 // otherwise - N should be replaced by the returned Operand. 131 // 132 SDValue visitTokenFactor(SDNode *N); 133 SDValue visitMERGE_VALUES(SDNode *N); 134 SDValue visitADD(SDNode *N); 135 SDValue visitSUB(SDNode *N); 136 SDValue visitADDC(SDNode *N); 137 SDValue visitADDE(SDNode *N); 138 SDValue visitMUL(SDNode *N); 139 SDValue visitSDIV(SDNode *N); 140 SDValue visitUDIV(SDNode *N); 141 SDValue visitSREM(SDNode *N); 142 SDValue visitUREM(SDNode *N); 143 SDValue visitMULHU(SDNode *N); 144 SDValue visitMULHS(SDNode *N); 145 SDValue visitSMUL_LOHI(SDNode *N); 146 SDValue visitUMUL_LOHI(SDNode *N); 147 SDValue visitSDIVREM(SDNode *N); 148 SDValue visitUDIVREM(SDNode *N); 149 SDValue visitAND(SDNode *N); 150 SDValue visitOR(SDNode *N); 151 SDValue visitXOR(SDNode *N); 152 SDValue SimplifyVBinOp(SDNode *N); 153 SDValue visitSHL(SDNode *N); 154 SDValue visitSRA(SDNode *N); 155 SDValue visitSRL(SDNode *N); 156 SDValue visitCTLZ(SDNode *N); 157 SDValue visitCTTZ(SDNode *N); 158 SDValue visitCTPOP(SDNode *N); 159 SDValue visitSELECT(SDNode *N); 160 SDValue visitSELECT_CC(SDNode *N); 161 SDValue visitSETCC(SDNode *N); 162 SDValue visitSIGN_EXTEND(SDNode *N); 163 SDValue visitZERO_EXTEND(SDNode *N); 164 SDValue visitANY_EXTEND(SDNode *N); 165 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 166 SDValue visitTRUNCATE(SDNode *N); 167 SDValue visitBIT_CONVERT(SDNode *N); 168 SDValue visitBUILD_PAIR(SDNode *N); 169 SDValue visitFADD(SDNode *N); 170 SDValue visitFSUB(SDNode *N); 171 SDValue visitFMUL(SDNode *N); 172 SDValue visitFDIV(SDNode *N); 173 SDValue visitFREM(SDNode *N); 174 SDValue visitFCOPYSIGN(SDNode *N); 175 SDValue visitSINT_TO_FP(SDNode *N); 176 SDValue visitUINT_TO_FP(SDNode *N); 177 SDValue visitFP_TO_SINT(SDNode *N); 178 SDValue visitFP_TO_UINT(SDNode *N); 179 SDValue visitFP_ROUND(SDNode *N); 180 SDValue visitFP_ROUND_INREG(SDNode *N); 181 SDValue visitFP_EXTEND(SDNode *N); 182 SDValue visitFNEG(SDNode *N); 183 SDValue visitFABS(SDNode *N); 184 SDValue visitBRCOND(SDNode *N); 185 SDValue visitBR_CC(SDNode *N); 186 SDValue visitLOAD(SDNode *N); 187 SDValue visitSTORE(SDNode *N); 188 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 189 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 190 SDValue visitBUILD_VECTOR(SDNode *N); 191 SDValue visitCONCAT_VECTORS(SDNode *N); 192 SDValue visitVECTOR_SHUFFLE(SDNode *N); 193 SDValue visitSADDO(SDNode *N); 194 SDValue visitUADDO(SDNode *N); 195 196 SDValue XformToShuffleWithZero(SDNode *N); 197 SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS); 198 199 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 200 201 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 202 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 203 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 204 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 205 SDValue N3, ISD::CondCode CC, 206 bool NotExtCompare = false); 207 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 208 ISD::CondCode Cond, bool foldBooleans = true); 209 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 210 unsigned HiOp); 211 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 212 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 213 SDValue BuildSDIV(SDNode *N); 214 SDValue BuildUDIV(SDNode *N); 215 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 216 SDValue ReduceLoadWidth(SDNode *N); 217 218 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 219 220 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 221 /// looking for aliasing nodes and adding them to the Aliases vector. 222 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 223 SmallVector<SDValue, 8> &Aliases); 224 225 /// isAlias - Return true if there is any possibility that the two addresses 226 /// overlap. 227 bool isAlias(SDValue Ptr1, int64_t Size1, 228 const Value *SrcValue1, int SrcValueOffset1, 229 SDValue Ptr2, int64_t Size2, 230 const Value *SrcValue2, int SrcValueOffset2); 231 232 /// FindAliasInfo - Extracts the relevant alias information from the memory 233 /// node. Returns true if the operand was a load. 234 bool FindAliasInfo(SDNode *N, 235 SDValue &Ptr, int64_t &Size, 236 const Value *&SrcValue, int &SrcValueOffset); 237 238 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 239 /// looking for a better chain (aliasing node.) 240 SDValue FindBetterChain(SDNode *N, SDValue Chain); 241 242public: 243 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 244 : DAG(D), 245 TLI(D.getTargetLoweringInfo()), 246 AfterLegalize(false), 247 Fast(fast), 248 AA(A) {} 249 250 /// Run - runs the dag combiner on all nodes in the work list 251 void Run(bool RunningAfterLegalize); 252 }; 253} 254 255 256namespace { 257/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 258/// nodes from the worklist. 259class VISIBILITY_HIDDEN WorkListRemover : 260 public SelectionDAG::DAGUpdateListener { 261 DAGCombiner &DC; 262public: 263 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 264 265 virtual void NodeDeleted(SDNode *N, SDNode *E) { 266 DC.removeFromWorkList(N); 267 } 268 269 virtual void NodeUpdated(SDNode *N) { 270 // Ignore updates. 271 } 272}; 273} 274 275//===----------------------------------------------------------------------===// 276// TargetLowering::DAGCombinerInfo implementation 277//===----------------------------------------------------------------------===// 278 279void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 280 ((DAGCombiner*)DC)->AddToWorkList(N); 281} 282 283SDValue TargetLowering::DAGCombinerInfo:: 284CombineTo(SDNode *N, const std::vector<SDValue> &To) { 285 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 286} 287 288SDValue TargetLowering::DAGCombinerInfo:: 289CombineTo(SDNode *N, SDValue Res) { 290 return ((DAGCombiner*)DC)->CombineTo(N, Res); 291} 292 293 294SDValue TargetLowering::DAGCombinerInfo:: 295CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 296 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 297} 298 299 300//===----------------------------------------------------------------------===// 301// Helper Functions 302//===----------------------------------------------------------------------===// 303 304/// isNegatibleForFree - Return 1 if we can compute the negated form of the 305/// specified expression for the same cost as the expression itself, or 2 if we 306/// can compute the negated form more cheaply than the expression itself. 307static char isNegatibleForFree(SDValue Op, bool AfterLegalize, 308 unsigned Depth = 0) { 309 // No compile time optimizations on this type. 310 if (Op.getValueType() == MVT::ppcf128) 311 return 0; 312 313 // fneg is removable even if it has multiple uses. 314 if (Op.getOpcode() == ISD::FNEG) return 2; 315 316 // Don't allow anything with multiple uses. 317 if (!Op.hasOneUse()) return 0; 318 319 // Don't recurse exponentially. 320 if (Depth > 6) return 0; 321 322 switch (Op.getOpcode()) { 323 default: return false; 324 case ISD::ConstantFP: 325 // Don't invert constant FP values after legalize. The negated constant 326 // isn't necessarily legal. 327 return AfterLegalize ? 0 : 1; 328 case ISD::FADD: 329 // FIXME: determine better conditions for this xform. 330 if (!UnsafeFPMath) return 0; 331 332 // -(A+B) -> -A - B 333 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 334 return V; 335 // -(A+B) -> -B - A 336 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 337 case ISD::FSUB: 338 // We can't turn -(A-B) into B-A when we honor signed zeros. 339 if (!UnsafeFPMath) return 0; 340 341 // -(A-B) -> B-A 342 return 1; 343 344 case ISD::FMUL: 345 case ISD::FDIV: 346 if (HonorSignDependentRoundingFPMath()) return 0; 347 348 // -(X*Y) -> (-X * Y) or (X*-Y) 349 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 350 return V; 351 352 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 353 354 case ISD::FP_EXTEND: 355 case ISD::FP_ROUND: 356 case ISD::FSIN: 357 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 358 } 359} 360 361/// GetNegatedExpression - If isNegatibleForFree returns true, this function 362/// returns the newly negated expression. 363static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 364 bool AfterLegalize, unsigned Depth = 0) { 365 // fneg is removable even if it has multiple uses. 366 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 367 368 // Don't allow anything with multiple uses. 369 assert(Op.hasOneUse() && "Unknown reuse!"); 370 371 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 372 switch (Op.getOpcode()) { 373 default: assert(0 && "Unknown code"); 374 case ISD::ConstantFP: { 375 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 376 V.changeSign(); 377 return DAG.getConstantFP(V, Op.getValueType()); 378 } 379 case ISD::FADD: 380 // FIXME: determine better conditions for this xform. 381 assert(UnsafeFPMath); 382 383 // -(A+B) -> -A - B 384 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 385 return DAG.getNode(ISD::FSUB, Op.getValueType(), 386 GetNegatedExpression(Op.getOperand(0), DAG, 387 AfterLegalize, Depth+1), 388 Op.getOperand(1)); 389 // -(A+B) -> -B - A 390 return DAG.getNode(ISD::FSUB, Op.getValueType(), 391 GetNegatedExpression(Op.getOperand(1), DAG, 392 AfterLegalize, Depth+1), 393 Op.getOperand(0)); 394 case ISD::FSUB: 395 // We can't turn -(A-B) into B-A when we honor signed zeros. 396 assert(UnsafeFPMath); 397 398 // -(0-B) -> B 399 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 400 if (N0CFP->getValueAPF().isZero()) 401 return Op.getOperand(1); 402 403 // -(A-B) -> B-A 404 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 405 Op.getOperand(0)); 406 407 case ISD::FMUL: 408 case ISD::FDIV: 409 assert(!HonorSignDependentRoundingFPMath()); 410 411 // -(X*Y) -> -X * Y 412 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 413 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 414 GetNegatedExpression(Op.getOperand(0), DAG, 415 AfterLegalize, Depth+1), 416 Op.getOperand(1)); 417 418 // -(X*Y) -> X * -Y 419 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 420 Op.getOperand(0), 421 GetNegatedExpression(Op.getOperand(1), DAG, 422 AfterLegalize, Depth+1)); 423 424 case ISD::FP_EXTEND: 425 case ISD::FSIN: 426 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 427 GetNegatedExpression(Op.getOperand(0), DAG, 428 AfterLegalize, Depth+1)); 429 case ISD::FP_ROUND: 430 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 431 GetNegatedExpression(Op.getOperand(0), DAG, 432 AfterLegalize, Depth+1), 433 Op.getOperand(1)); 434 } 435} 436 437 438// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 439// that selects between the values 1 and 0, making it equivalent to a setcc. 440// Also, set the incoming LHS, RHS, and CC references to the appropriate 441// nodes based on the type of node we are checking. This simplifies life a 442// bit for the callers. 443static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 444 SDValue &CC) { 445 if (N.getOpcode() == ISD::SETCC) { 446 LHS = N.getOperand(0); 447 RHS = N.getOperand(1); 448 CC = N.getOperand(2); 449 return true; 450 } 451 if (N.getOpcode() == ISD::SELECT_CC && 452 N.getOperand(2).getOpcode() == ISD::Constant && 453 N.getOperand(3).getOpcode() == ISD::Constant && 454 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 455 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 456 LHS = N.getOperand(0); 457 RHS = N.getOperand(1); 458 CC = N.getOperand(4); 459 return true; 460 } 461 return false; 462} 463 464// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 465// one use. If this is true, it allows the users to invert the operation for 466// free when it is profitable to do so. 467static bool isOneUseSetCC(SDValue N) { 468 SDValue N0, N1, N2; 469 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 470 return true; 471 return false; 472} 473 474SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){ 475 MVT VT = N0.getValueType(); 476 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 477 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 478 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 479 if (isa<ConstantSDNode>(N1)) { 480 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 481 AddToWorkList(OpNode.getNode()); 482 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 483 } else if (N0.hasOneUse()) { 484 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 485 AddToWorkList(OpNode.getNode()); 486 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 487 } 488 } 489 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 490 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 491 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 492 if (isa<ConstantSDNode>(N0)) { 493 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 494 AddToWorkList(OpNode.getNode()); 495 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 496 } else if (N1.hasOneUse()) { 497 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 498 AddToWorkList(OpNode.getNode()); 499 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 500 } 501 } 502 return SDValue(); 503} 504 505SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 506 bool AddTo) { 507 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 508 ++NodesCombined; 509 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 510 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 511 DOUT << " and " << NumTo-1 << " other values\n"; 512 WorkListRemover DeadNodes(*this); 513 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 514 515 if (AddTo) { 516 // Push the new nodes and any users onto the worklist 517 for (unsigned i = 0, e = NumTo; i != e; ++i) { 518 AddToWorkList(To[i].getNode()); 519 AddUsersToWorkList(To[i].getNode()); 520 } 521 } 522 523 // Nodes can be reintroduced into the worklist. Make sure we do not 524 // process a node that has been replaced. 525 removeFromWorkList(N); 526 527 // Finally, since the node is now dead, remove it from the graph. 528 DAG.DeleteNode(N); 529 return SDValue(N, 0); 530} 531 532/// SimplifyDemandedBits - Check the specified integer node value to see if 533/// it can be simplified or if things it uses can be simplified by bit 534/// propagation. If so, return true. 535bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 536 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 537 APInt KnownZero, KnownOne; 538 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 539 return false; 540 541 // Revisit the node. 542 AddToWorkList(Op.getNode()); 543 544 // Replace the old value with the new one. 545 ++NodesCombined; 546 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 547 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 548 DOUT << '\n'; 549 550 // Replace all uses. If any nodes become isomorphic to other nodes and 551 // are deleted, make sure to remove them from our worklist. 552 WorkListRemover DeadNodes(*this); 553 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 554 555 // Push the new node and any (possibly new) users onto the worklist. 556 AddToWorkList(TLO.New.getNode()); 557 AddUsersToWorkList(TLO.New.getNode()); 558 559 // Finally, if the node is now dead, remove it from the graph. The node 560 // may not be dead if the replacement process recursively simplified to 561 // something else needing this node. 562 if (TLO.Old.getNode()->use_empty()) { 563 removeFromWorkList(TLO.Old.getNode()); 564 565 // If the operands of this node are only used by the node, they will now 566 // be dead. Make sure to visit them first to delete dead nodes early. 567 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 568 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 569 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 570 571 DAG.DeleteNode(TLO.Old.getNode()); 572 } 573 return true; 574} 575 576//===----------------------------------------------------------------------===// 577// Main DAG Combiner implementation 578//===----------------------------------------------------------------------===// 579 580void DAGCombiner::Run(bool RunningAfterLegalize) { 581 // set the instance variable, so that the various visit routines may use it. 582 AfterLegalize = RunningAfterLegalize; 583 584 // Add all the dag nodes to the worklist. 585 WorkList.reserve(DAG.allnodes_size()); 586 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 587 E = DAG.allnodes_end(); I != E; ++I) 588 WorkList.push_back(I); 589 590 // Create a dummy node (which is not added to allnodes), that adds a reference 591 // to the root node, preventing it from being deleted, and tracking any 592 // changes of the root. 593 HandleSDNode Dummy(DAG.getRoot()); 594 595 // The root of the dag may dangle to deleted nodes until the dag combiner is 596 // done. Set it to null to avoid confusion. 597 DAG.setRoot(SDValue()); 598 599 // while the worklist isn't empty, inspect the node on the end of it and 600 // try and combine it. 601 while (!WorkList.empty()) { 602 SDNode *N = WorkList.back(); 603 WorkList.pop_back(); 604 605 // If N has no uses, it is dead. Make sure to revisit all N's operands once 606 // N is deleted from the DAG, since they too may now be dead or may have a 607 // reduced number of uses, allowing other xforms. 608 if (N->use_empty() && N != &Dummy) { 609 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 610 AddToWorkList(N->getOperand(i).getNode()); 611 612 DAG.DeleteNode(N); 613 continue; 614 } 615 616 SDValue RV = combine(N); 617 618 if (RV.getNode() == 0) 619 continue; 620 621 ++NodesCombined; 622 623 // If we get back the same node we passed in, rather than a new node or 624 // zero, we know that the node must have defined multiple values and 625 // CombineTo was used. Since CombineTo takes care of the worklist 626 // mechanics for us, we have no work to do in this case. 627 if (RV.getNode() == N) 628 continue; 629 630 assert(N->getOpcode() != ISD::DELETED_NODE && 631 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 632 "Node was deleted but visit returned new node!"); 633 634 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 635 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 636 DOUT << '\n'; 637 WorkListRemover DeadNodes(*this); 638 if (N->getNumValues() == RV.getNode()->getNumValues()) 639 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 640 else { 641 assert(N->getValueType(0) == RV.getValueType() && 642 N->getNumValues() == 1 && "Type mismatch"); 643 SDValue OpV = RV; 644 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 645 } 646 647 // Push the new node and any users onto the worklist 648 AddToWorkList(RV.getNode()); 649 AddUsersToWorkList(RV.getNode()); 650 651 // Add any uses of the old node to the worklist in case this node is the 652 // last one that uses them. They may become dead after this node is 653 // deleted. 654 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 655 AddToWorkList(N->getOperand(i).getNode()); 656 657 // Nodes can be reintroduced into the worklist. Make sure we do not 658 // process a node that has been replaced. 659 removeFromWorkList(N); 660 661 // Finally, since the node is now dead, remove it from the graph. 662 DAG.DeleteNode(N); 663 } 664 665 // If the root changed (e.g. it was a dead load, update the root). 666 DAG.setRoot(Dummy.getValue()); 667} 668 669SDValue DAGCombiner::visit(SDNode *N) { 670 switch(N->getOpcode()) { 671 default: break; 672 case ISD::TokenFactor: return visitTokenFactor(N); 673 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 674 case ISD::ADD: return visitADD(N); 675 case ISD::SUB: return visitSUB(N); 676 case ISD::ADDC: return visitADDC(N); 677 case ISD::ADDE: return visitADDE(N); 678 case ISD::MUL: return visitMUL(N); 679 case ISD::SDIV: return visitSDIV(N); 680 case ISD::UDIV: return visitUDIV(N); 681 case ISD::SREM: return visitSREM(N); 682 case ISD::UREM: return visitUREM(N); 683 case ISD::MULHU: return visitMULHU(N); 684 case ISD::MULHS: return visitMULHS(N); 685 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 686 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 687 case ISD::SDIVREM: return visitSDIVREM(N); 688 case ISD::UDIVREM: return visitUDIVREM(N); 689 case ISD::AND: return visitAND(N); 690 case ISD::OR: return visitOR(N); 691 case ISD::XOR: return visitXOR(N); 692 case ISD::SHL: return visitSHL(N); 693 case ISD::SRA: return visitSRA(N); 694 case ISD::SRL: return visitSRL(N); 695 case ISD::CTLZ: return visitCTLZ(N); 696 case ISD::CTTZ: return visitCTTZ(N); 697 case ISD::CTPOP: return visitCTPOP(N); 698 case ISD::SELECT: return visitSELECT(N); 699 case ISD::SELECT_CC: return visitSELECT_CC(N); 700 case ISD::SETCC: return visitSETCC(N); 701 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 702 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 703 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 704 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 705 case ISD::TRUNCATE: return visitTRUNCATE(N); 706 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 707 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 708 case ISD::FADD: return visitFADD(N); 709 case ISD::FSUB: return visitFSUB(N); 710 case ISD::FMUL: return visitFMUL(N); 711 case ISD::FDIV: return visitFDIV(N); 712 case ISD::FREM: return visitFREM(N); 713 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 714 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 715 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 716 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 717 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 718 case ISD::FP_ROUND: return visitFP_ROUND(N); 719 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 720 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 721 case ISD::FNEG: return visitFNEG(N); 722 case ISD::FABS: return visitFABS(N); 723 case ISD::BRCOND: return visitBRCOND(N); 724 case ISD::BR_CC: return visitBR_CC(N); 725 case ISD::LOAD: return visitLOAD(N); 726 case ISD::STORE: return visitSTORE(N); 727 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 728 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 729 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 730 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 731 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 732 case ISD::SADDO: return visitSADDO(N); 733 case ISD::UADDO: return visitUADDO(N); 734 } 735 return SDValue(); 736} 737 738SDValue DAGCombiner::combine(SDNode *N) { 739 740 SDValue RV = visit(N); 741 742 // If nothing happened, try a target-specific DAG combine. 743 if (RV.getNode() == 0) { 744 assert(N->getOpcode() != ISD::DELETED_NODE && 745 "Node was deleted but visit returned NULL!"); 746 747 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 748 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 749 750 // Expose the DAG combiner to the target combiner impls. 751 TargetLowering::DAGCombinerInfo 752 DagCombineInfo(DAG, !AfterLegalize, false, this); 753 754 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 755 } 756 } 757 758 // If N is a commutative binary node, try commuting it to enable more 759 // sdisel CSE. 760 if (RV.getNode() == 0 && 761 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 762 N->getNumValues() == 1) { 763 SDValue N0 = N->getOperand(0); 764 SDValue N1 = N->getOperand(1); 765 // Constant operands are canonicalized to RHS. 766 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 767 SDValue Ops[] = { N1, N0 }; 768 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 769 Ops, 2); 770 if (CSENode) 771 return SDValue(CSENode, 0); 772 } 773 } 774 775 return RV; 776} 777 778/// getInputChainForNode - Given a node, return its input chain if it has one, 779/// otherwise return a null sd operand. 780static SDValue getInputChainForNode(SDNode *N) { 781 if (unsigned NumOps = N->getNumOperands()) { 782 if (N->getOperand(0).getValueType() == MVT::Other) 783 return N->getOperand(0); 784 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 785 return N->getOperand(NumOps-1); 786 for (unsigned i = 1; i < NumOps-1; ++i) 787 if (N->getOperand(i).getValueType() == MVT::Other) 788 return N->getOperand(i); 789 } 790 return SDValue(0, 0); 791} 792 793SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 794 // If N has two operands, where one has an input chain equal to the other, 795 // the 'other' chain is redundant. 796 if (N->getNumOperands() == 2) { 797 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 798 return N->getOperand(0); 799 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 800 return N->getOperand(1); 801 } 802 803 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 804 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 805 SmallPtrSet<SDNode*, 16> SeenOps; 806 bool Changed = false; // If we should replace this token factor. 807 808 // Start out with this token factor. 809 TFs.push_back(N); 810 811 // Iterate through token factors. The TFs grows when new token factors are 812 // encountered. 813 for (unsigned i = 0; i < TFs.size(); ++i) { 814 SDNode *TF = TFs[i]; 815 816 // Check each of the operands. 817 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 818 SDValue Op = TF->getOperand(i); 819 820 switch (Op.getOpcode()) { 821 case ISD::EntryToken: 822 // Entry tokens don't need to be added to the list. They are 823 // rededundant. 824 Changed = true; 825 break; 826 827 case ISD::TokenFactor: 828 if ((CombinerAA || Op.hasOneUse()) && 829 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 830 // Queue up for processing. 831 TFs.push_back(Op.getNode()); 832 // Clean up in case the token factor is removed. 833 AddToWorkList(Op.getNode()); 834 Changed = true; 835 break; 836 } 837 // Fall thru 838 839 default: 840 // Only add if it isn't already in the list. 841 if (SeenOps.insert(Op.getNode())) 842 Ops.push_back(Op); 843 else 844 Changed = true; 845 break; 846 } 847 } 848 } 849 850 SDValue Result; 851 852 // If we've change things around then replace token factor. 853 if (Changed) { 854 if (Ops.empty()) { 855 // The entry token is the only possible outcome. 856 Result = DAG.getEntryNode(); 857 } else { 858 // New and improved token factor. 859 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 860 } 861 862 // Don't add users to work list. 863 return CombineTo(N, Result, false); 864 } 865 866 return Result; 867} 868 869/// MERGE_VALUES can always be eliminated. 870SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 871 WorkListRemover DeadNodes(*this); 872 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 873 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 874 &DeadNodes); 875 removeFromWorkList(N); 876 DAG.DeleteNode(N); 877 return SDValue(N, 0); // Return N so it doesn't get rechecked! 878} 879 880 881static 882SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) { 883 MVT VT = N0.getValueType(); 884 SDValue N00 = N0.getOperand(0); 885 SDValue N01 = N0.getOperand(1); 886 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 887 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 888 isa<ConstantSDNode>(N00.getOperand(1))) { 889 N0 = DAG.getNode(ISD::ADD, VT, 890 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 891 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 892 return DAG.getNode(ISD::ADD, VT, N0, N1); 893 } 894 return SDValue(); 895} 896 897static 898SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 899 SelectionDAG &DAG, const TargetLowering &TLI, 900 bool AfterLegalize) { 901 MVT VT = N->getValueType(0); 902 unsigned Opc = N->getOpcode(); 903 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 904 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 905 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 906 ISD::CondCode CC = ISD::SETCC_INVALID; 907 908 if (isSlctCC) { 909 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 910 } else { 911 SDValue CCOp = Slct.getOperand(0); 912 if (CCOp.getOpcode() == ISD::SETCC) 913 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 914 } 915 916 bool DoXform = false; 917 bool InvCC = false; 918 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 919 "Bad input!"); 920 921 if (LHS.getOpcode() == ISD::Constant && 922 cast<ConstantSDNode>(LHS)->isNullValue()) { 923 DoXform = true; 924 } else if (CC != ISD::SETCC_INVALID && 925 RHS.getOpcode() == ISD::Constant && 926 cast<ConstantSDNode>(RHS)->isNullValue()) { 927 std::swap(LHS, RHS); 928 SDValue Op0 = Slct.getOperand(0); 929 MVT OpVT = isSlctCC ? Op0.getValueType() : 930 Op0.getOperand(0).getValueType(); 931 bool isInt = OpVT.isInteger(); 932 CC = ISD::getSetCCInverse(CC, isInt); 933 934 if (AfterLegalize && !TLI.isCondCodeLegal(CC, OpVT)) 935 return SDValue(); // Inverse operator isn't legal. 936 937 DoXform = true; 938 InvCC = true; 939 } 940 941 if (DoXform) { 942 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS); 943 if (isSlctCC) 944 return DAG.getSelectCC(OtherOp, Result, 945 Slct.getOperand(0), Slct.getOperand(1), CC); 946 SDValue CCOp = Slct.getOperand(0); 947 if (InvCC) 948 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 949 CCOp.getOperand(1), CC); 950 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 951 } 952 return SDValue(); 953} 954 955SDValue DAGCombiner::visitADD(SDNode *N) { 956 SDValue N0 = N->getOperand(0); 957 SDValue N1 = N->getOperand(1); 958 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 959 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 960 MVT VT = N0.getValueType(); 961 962 // fold vector ops 963 if (VT.isVector()) { 964 SDValue FoldedVOp = SimplifyVBinOp(N); 965 if (FoldedVOp.getNode()) return FoldedVOp; 966 } 967 968 // fold (add x, undef) -> undef 969 if (N0.getOpcode() == ISD::UNDEF) 970 return N0; 971 if (N1.getOpcode() == ISD::UNDEF) 972 return N1; 973 // fold (add c1, c2) -> c1+c2 974 if (N0C && N1C) 975 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 976 // canonicalize constant to RHS 977 if (N0C && !N1C) 978 return DAG.getNode(ISD::ADD, VT, N1, N0); 979 // fold (add x, 0) -> x 980 if (N1C && N1C->isNullValue()) 981 return N0; 982 // fold (add Sym, c) -> Sym+c 983 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 984 if (!AfterLegalize && TLI.isOffsetFoldingLegal(GA) && N1C && 985 GA->getOpcode() == ISD::GlobalAddress) 986 return DAG.getGlobalAddress(GA->getGlobal(), VT, 987 GA->getOffset() + 988 (uint64_t)N1C->getSExtValue()); 989 // fold ((c1-A)+c2) -> (c1+c2)-A 990 if (N1C && N0.getOpcode() == ISD::SUB) 991 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 992 return DAG.getNode(ISD::SUB, VT, 993 DAG.getConstant(N1C->getAPIntValue()+ 994 N0C->getAPIntValue(), VT), 995 N0.getOperand(1)); 996 // reassociate add 997 SDValue RADD = ReassociateOps(ISD::ADD, N0, N1); 998 if (RADD.getNode() != 0) 999 return RADD; 1000 // fold ((0-A) + B) -> B-A 1001 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1002 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1003 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 1004 // fold (A + (0-B)) -> A-B 1005 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1006 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1007 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 1008 // fold (A+(B-A)) -> B 1009 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1010 return N1.getOperand(0); 1011 1012 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1013 return SDValue(N, 0); 1014 1015 // fold (a+b) -> (a|b) iff a and b share no bits. 1016 if (VT.isInteger() && !VT.isVector()) { 1017 APInt LHSZero, LHSOne; 1018 APInt RHSZero, RHSOne; 1019 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1020 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1021 if (LHSZero.getBoolValue()) { 1022 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1023 1024 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1025 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1026 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1027 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1028 return DAG.getNode(ISD::OR, VT, N0, N1); 1029 } 1030 } 1031 1032 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1033 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1034 SDValue Result = combineShlAddConstant(N0, N1, DAG); 1035 if (Result.getNode()) return Result; 1036 } 1037 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1038 SDValue Result = combineShlAddConstant(N1, N0, DAG); 1039 if (Result.getNode()) return Result; 1040 } 1041 1042 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1043 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1044 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, AfterLegalize); 1045 if (Result.getNode()) return Result; 1046 } 1047 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1048 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, AfterLegalize); 1049 if (Result.getNode()) return Result; 1050 } 1051 1052 return SDValue(); 1053} 1054 1055SDValue DAGCombiner::visitADDC(SDNode *N) { 1056 SDValue N0 = N->getOperand(0); 1057 SDValue N1 = N->getOperand(1); 1058 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1059 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1060 MVT VT = N0.getValueType(); 1061 1062 // If the flag result is dead, turn this into an ADD. 1063 if (N->hasNUsesOfValue(0, 1)) 1064 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1065 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1066 1067 // canonicalize constant to RHS. 1068 if (N0C && !N1C) 1069 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1070 1071 // fold (addc x, 0) -> x + no carry out 1072 if (N1C && N1C->isNullValue()) 1073 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1074 1075 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1076 APInt LHSZero, LHSOne; 1077 APInt RHSZero, RHSOne; 1078 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1079 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1080 if (LHSZero.getBoolValue()) { 1081 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1082 1083 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1084 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1085 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1086 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1087 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1088 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1089 } 1090 1091 return SDValue(); 1092} 1093 1094SDValue DAGCombiner::visitADDE(SDNode *N) { 1095 SDValue N0 = N->getOperand(0); 1096 SDValue N1 = N->getOperand(1); 1097 SDValue CarryIn = N->getOperand(2); 1098 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1099 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1100 //MVT VT = N0.getValueType(); 1101 1102 // canonicalize constant to RHS 1103 if (N0C && !N1C) 1104 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1105 1106 // fold (adde x, y, false) -> (addc x, y) 1107 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1108 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1109 1110 return SDValue(); 1111} 1112 1113 1114 1115SDValue DAGCombiner::visitSUB(SDNode *N) { 1116 SDValue N0 = N->getOperand(0); 1117 SDValue N1 = N->getOperand(1); 1118 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1119 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1120 MVT VT = N0.getValueType(); 1121 1122 // fold vector ops 1123 if (VT.isVector()) { 1124 SDValue FoldedVOp = SimplifyVBinOp(N); 1125 if (FoldedVOp.getNode()) return FoldedVOp; 1126 } 1127 1128 // fold (sub x, x) -> 0 1129 if (N0 == N1) 1130 return DAG.getConstant(0, N->getValueType(0)); 1131 // fold (sub c1, c2) -> c1-c2 1132 if (N0C && N1C) 1133 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1134 // fold (sub x, c) -> (add x, -c) 1135 if (N1C) 1136 return DAG.getNode(ISD::ADD, VT, N0, 1137 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1138 // fold (A+B)-A -> B 1139 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1140 return N0.getOperand(1); 1141 // fold (A+B)-B -> A 1142 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1143 return N0.getOperand(0); 1144 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1145 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1146 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, AfterLegalize); 1147 if (Result.getNode()) return Result; 1148 } 1149 // If either operand of a sub is undef, the result is undef 1150 if (N0.getOpcode() == ISD::UNDEF) 1151 return N0; 1152 if (N1.getOpcode() == ISD::UNDEF) 1153 return N1; 1154 1155 // If the relocation model supports it, consider symbol offsets. 1156 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1157 if (!AfterLegalize && TLI.isOffsetFoldingLegal(GA)) { 1158 // fold (sub Sym, c) -> Sym-c 1159 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1160 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1161 GA->getOffset() - 1162 (uint64_t)N1C->getSExtValue()); 1163 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1164 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1165 if (GA->getGlobal() == GB->getGlobal()) 1166 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1167 VT); 1168 } 1169 1170 return SDValue(); 1171} 1172 1173SDValue DAGCombiner::visitMUL(SDNode *N) { 1174 SDValue N0 = N->getOperand(0); 1175 SDValue N1 = N->getOperand(1); 1176 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1177 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1178 MVT VT = N0.getValueType(); 1179 1180 // fold vector ops 1181 if (VT.isVector()) { 1182 SDValue FoldedVOp = SimplifyVBinOp(N); 1183 if (FoldedVOp.getNode()) return FoldedVOp; 1184 } 1185 1186 // fold (mul x, undef) -> 0 1187 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1188 return DAG.getConstant(0, VT); 1189 // fold (mul c1, c2) -> c1*c2 1190 if (N0C && N1C) 1191 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1192 // canonicalize constant to RHS 1193 if (N0C && !N1C) 1194 return DAG.getNode(ISD::MUL, VT, N1, N0); 1195 // fold (mul x, 0) -> 0 1196 if (N1C && N1C->isNullValue()) 1197 return N1; 1198 // fold (mul x, -1) -> 0-x 1199 if (N1C && N1C->isAllOnesValue()) 1200 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1201 // fold (mul x, (1 << c)) -> x << c 1202 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1203 return DAG.getNode(ISD::SHL, VT, N0, 1204 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1205 TLI.getShiftAmountTy())); 1206 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1207 if (N1C && isPowerOf2_64(-N1C->getSExtValue())) { 1208 // FIXME: If the input is something that is easily negated (e.g. a 1209 // single-use add), we should put the negate there. 1210 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1211 DAG.getNode(ISD::SHL, VT, N0, 1212 DAG.getConstant(Log2_64(-N1C->getSExtValue()), 1213 TLI.getShiftAmountTy()))); 1214 } 1215 1216 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1217 if (N1C && N0.getOpcode() == ISD::SHL && 1218 isa<ConstantSDNode>(N0.getOperand(1))) { 1219 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1220 AddToWorkList(C3.getNode()); 1221 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1222 } 1223 1224 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1225 // use. 1226 { 1227 SDValue Sh(0,0), Y(0,0); 1228 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1229 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1230 N0.getNode()->hasOneUse()) { 1231 Sh = N0; Y = N1; 1232 } else if (N1.getOpcode() == ISD::SHL && 1233 isa<ConstantSDNode>(N1.getOperand(1)) && 1234 N1.getNode()->hasOneUse()) { 1235 Sh = N1; Y = N0; 1236 } 1237 if (Sh.getNode()) { 1238 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1239 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1240 } 1241 } 1242 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1243 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1244 isa<ConstantSDNode>(N0.getOperand(1))) { 1245 return DAG.getNode(ISD::ADD, VT, 1246 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1247 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1248 } 1249 1250 // reassociate mul 1251 SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1); 1252 if (RMUL.getNode() != 0) 1253 return RMUL; 1254 1255 return SDValue(); 1256} 1257 1258SDValue DAGCombiner::visitSDIV(SDNode *N) { 1259 SDValue N0 = N->getOperand(0); 1260 SDValue N1 = N->getOperand(1); 1261 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1262 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1263 MVT VT = N->getValueType(0); 1264 1265 // fold vector ops 1266 if (VT.isVector()) { 1267 SDValue FoldedVOp = SimplifyVBinOp(N); 1268 if (FoldedVOp.getNode()) return FoldedVOp; 1269 } 1270 1271 // fold (sdiv c1, c2) -> c1/c2 1272 if (N0C && N1C && !N1C->isNullValue()) 1273 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1274 // fold (sdiv X, 1) -> X 1275 if (N1C && N1C->getSExtValue() == 1LL) 1276 return N0; 1277 // fold (sdiv X, -1) -> 0-X 1278 if (N1C && N1C->isAllOnesValue()) 1279 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1280 // If we know the sign bits of both operands are zero, strength reduce to a 1281 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1282 if (!VT.isVector()) { 1283 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1284 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1285 } 1286 // fold (sdiv X, pow2) -> simple ops after legalize 1287 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1288 (isPowerOf2_64(N1C->getSExtValue()) || 1289 isPowerOf2_64(-N1C->getSExtValue()))) { 1290 // If dividing by powers of two is cheap, then don't perform the following 1291 // fold. 1292 if (TLI.isPow2DivCheap()) 1293 return SDValue(); 1294 int64_t pow2 = N1C->getSExtValue(); 1295 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1296 unsigned lg2 = Log2_64(abs2); 1297 // Splat the sign bit into the register 1298 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1299 DAG.getConstant(VT.getSizeInBits()-1, 1300 TLI.getShiftAmountTy())); 1301 AddToWorkList(SGN.getNode()); 1302 // Add (N0 < 0) ? abs2 - 1 : 0; 1303 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1304 DAG.getConstant(VT.getSizeInBits()-lg2, 1305 TLI.getShiftAmountTy())); 1306 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1307 AddToWorkList(SRL.getNode()); 1308 AddToWorkList(ADD.getNode()); // Divide by pow2 1309 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1310 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1311 // If we're dividing by a positive value, we're done. Otherwise, we must 1312 // negate the result. 1313 if (pow2 > 0) 1314 return SRA; 1315 AddToWorkList(SRA.getNode()); 1316 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1317 } 1318 // if integer divide is expensive and we satisfy the requirements, emit an 1319 // alternate sequence. 1320 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1321 !TLI.isIntDivCheap()) { 1322 SDValue Op = BuildSDIV(N); 1323 if (Op.getNode()) return Op; 1324 } 1325 1326 // undef / X -> 0 1327 if (N0.getOpcode() == ISD::UNDEF) 1328 return DAG.getConstant(0, VT); 1329 // X / undef -> undef 1330 if (N1.getOpcode() == ISD::UNDEF) 1331 return N1; 1332 1333 return SDValue(); 1334} 1335 1336SDValue DAGCombiner::visitUDIV(SDNode *N) { 1337 SDValue N0 = N->getOperand(0); 1338 SDValue N1 = N->getOperand(1); 1339 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1340 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1341 MVT VT = N->getValueType(0); 1342 1343 // fold vector ops 1344 if (VT.isVector()) { 1345 SDValue FoldedVOp = SimplifyVBinOp(N); 1346 if (FoldedVOp.getNode()) return FoldedVOp; 1347 } 1348 1349 // fold (udiv c1, c2) -> c1/c2 1350 if (N0C && N1C && !N1C->isNullValue()) 1351 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1352 // fold (udiv x, (1 << c)) -> x >>u c 1353 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1354 return DAG.getNode(ISD::SRL, VT, N0, 1355 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1356 TLI.getShiftAmountTy())); 1357 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1358 if (N1.getOpcode() == ISD::SHL) { 1359 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1360 if (SHC->getAPIntValue().isPowerOf2()) { 1361 MVT ADDVT = N1.getOperand(1).getValueType(); 1362 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1363 DAG.getConstant(SHC->getAPIntValue() 1364 .logBase2(), 1365 ADDVT)); 1366 AddToWorkList(Add.getNode()); 1367 return DAG.getNode(ISD::SRL, VT, N0, Add); 1368 } 1369 } 1370 } 1371 // fold (udiv x, c) -> alternate 1372 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1373 SDValue Op = BuildUDIV(N); 1374 if (Op.getNode()) return Op; 1375 } 1376 1377 // undef / X -> 0 1378 if (N0.getOpcode() == ISD::UNDEF) 1379 return DAG.getConstant(0, VT); 1380 // X / undef -> undef 1381 if (N1.getOpcode() == ISD::UNDEF) 1382 return N1; 1383 1384 return SDValue(); 1385} 1386 1387SDValue DAGCombiner::visitSREM(SDNode *N) { 1388 SDValue N0 = N->getOperand(0); 1389 SDValue N1 = N->getOperand(1); 1390 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1391 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1392 MVT VT = N->getValueType(0); 1393 1394 // fold (srem c1, c2) -> c1%c2 1395 if (N0C && N1C && !N1C->isNullValue()) 1396 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1397 // If we know the sign bits of both operands are zero, strength reduce to a 1398 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1399 if (!VT.isVector()) { 1400 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1401 return DAG.getNode(ISD::UREM, VT, N0, N1); 1402 } 1403 1404 // If X/C can be simplified by the division-by-constant logic, lower 1405 // X%C to the equivalent of X-X/C*C. 1406 if (N1C && !N1C->isNullValue()) { 1407 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1408 AddToWorkList(Div.getNode()); 1409 SDValue OptimizedDiv = combine(Div.getNode()); 1410 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1411 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1412 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1413 AddToWorkList(Mul.getNode()); 1414 return Sub; 1415 } 1416 } 1417 1418 // undef % X -> 0 1419 if (N0.getOpcode() == ISD::UNDEF) 1420 return DAG.getConstant(0, VT); 1421 // X % undef -> undef 1422 if (N1.getOpcode() == ISD::UNDEF) 1423 return N1; 1424 1425 return SDValue(); 1426} 1427 1428SDValue DAGCombiner::visitUREM(SDNode *N) { 1429 SDValue N0 = N->getOperand(0); 1430 SDValue N1 = N->getOperand(1); 1431 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1432 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1433 MVT VT = N->getValueType(0); 1434 1435 // fold (urem c1, c2) -> c1%c2 1436 if (N0C && N1C && !N1C->isNullValue()) 1437 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1438 // fold (urem x, pow2) -> (and x, pow2-1) 1439 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1440 return DAG.getNode(ISD::AND, VT, N0, 1441 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1442 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1443 if (N1.getOpcode() == ISD::SHL) { 1444 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1445 if (SHC->getAPIntValue().isPowerOf2()) { 1446 SDValue Add = 1447 DAG.getNode(ISD::ADD, VT, N1, 1448 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1449 VT)); 1450 AddToWorkList(Add.getNode()); 1451 return DAG.getNode(ISD::AND, VT, N0, Add); 1452 } 1453 } 1454 } 1455 1456 // If X/C can be simplified by the division-by-constant logic, lower 1457 // X%C to the equivalent of X-X/C*C. 1458 if (N1C && !N1C->isNullValue()) { 1459 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1460 AddToWorkList(Div.getNode()); 1461 SDValue OptimizedDiv = combine(Div.getNode()); 1462 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1463 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1464 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1465 AddToWorkList(Mul.getNode()); 1466 return Sub; 1467 } 1468 } 1469 1470 // undef % X -> 0 1471 if (N0.getOpcode() == ISD::UNDEF) 1472 return DAG.getConstant(0, VT); 1473 // X % undef -> undef 1474 if (N1.getOpcode() == ISD::UNDEF) 1475 return N1; 1476 1477 return SDValue(); 1478} 1479 1480SDValue DAGCombiner::visitMULHS(SDNode *N) { 1481 SDValue N0 = N->getOperand(0); 1482 SDValue N1 = N->getOperand(1); 1483 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1484 MVT VT = N->getValueType(0); 1485 1486 // fold (mulhs x, 0) -> 0 1487 if (N1C && N1C->isNullValue()) 1488 return N1; 1489 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1490 if (N1C && N1C->getAPIntValue() == 1) 1491 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1492 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1493 TLI.getShiftAmountTy())); 1494 // fold (mulhs x, undef) -> 0 1495 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1496 return DAG.getConstant(0, VT); 1497 1498 return SDValue(); 1499} 1500 1501SDValue DAGCombiner::visitMULHU(SDNode *N) { 1502 SDValue N0 = N->getOperand(0); 1503 SDValue N1 = N->getOperand(1); 1504 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1505 MVT VT = N->getValueType(0); 1506 1507 // fold (mulhu x, 0) -> 0 1508 if (N1C && N1C->isNullValue()) 1509 return N1; 1510 // fold (mulhu x, 1) -> 0 1511 if (N1C && N1C->getAPIntValue() == 1) 1512 return DAG.getConstant(0, N0.getValueType()); 1513 // fold (mulhu x, undef) -> 0 1514 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1515 return DAG.getConstant(0, VT); 1516 1517 return SDValue(); 1518} 1519 1520/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1521/// compute two values. LoOp and HiOp give the opcodes for the two computations 1522/// that are being performed. Return true if a simplification was made. 1523/// 1524SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1525 unsigned HiOp) { 1526 // If the high half is not needed, just compute the low half. 1527 bool HiExists = N->hasAnyUseOfValue(1); 1528 if (!HiExists && 1529 (!AfterLegalize || 1530 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1531 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1532 N->getNumOperands()); 1533 return CombineTo(N, Res, Res); 1534 } 1535 1536 // If the low half is not needed, just compute the high half. 1537 bool LoExists = N->hasAnyUseOfValue(0); 1538 if (!LoExists && 1539 (!AfterLegalize || 1540 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1541 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1542 N->getNumOperands()); 1543 return CombineTo(N, Res, Res); 1544 } 1545 1546 // If both halves are used, return as it is. 1547 if (LoExists && HiExists) 1548 return SDValue(); 1549 1550 // If the two computed results can be simplified separately, separate them. 1551 if (LoExists) { 1552 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1553 N->op_begin(), N->getNumOperands()); 1554 AddToWorkList(Lo.getNode()); 1555 SDValue LoOpt = combine(Lo.getNode()); 1556 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1557 (!AfterLegalize || 1558 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1559 return CombineTo(N, LoOpt, LoOpt); 1560 } 1561 1562 if (HiExists) { 1563 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1564 N->op_begin(), N->getNumOperands()); 1565 AddToWorkList(Hi.getNode()); 1566 SDValue HiOpt = combine(Hi.getNode()); 1567 if (HiOpt.getNode() && HiOpt != Hi && 1568 (!AfterLegalize || 1569 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1570 return CombineTo(N, HiOpt, HiOpt); 1571 } 1572 return SDValue(); 1573} 1574 1575SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1576 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1577 if (Res.getNode()) return Res; 1578 1579 return SDValue(); 1580} 1581 1582SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1583 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1584 if (Res.getNode()) return Res; 1585 1586 return SDValue(); 1587} 1588 1589SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1590 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1591 if (Res.getNode()) return Res; 1592 1593 return SDValue(); 1594} 1595 1596SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1597 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1598 if (Res.getNode()) return Res; 1599 1600 return SDValue(); 1601} 1602 1603/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1604/// two operands of the same opcode, try to simplify it. 1605SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1606 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1607 MVT VT = N0.getValueType(); 1608 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1609 1610 // For each of OP in AND/OR/XOR: 1611 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1612 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1613 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1614 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1615 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1616 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1617 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1618 SDValue ORNode = DAG.getNode(N->getOpcode(), 1619 N0.getOperand(0).getValueType(), 1620 N0.getOperand(0), N1.getOperand(0)); 1621 AddToWorkList(ORNode.getNode()); 1622 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1623 } 1624 1625 // For each of OP in SHL/SRL/SRA/AND... 1626 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1627 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1628 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1629 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1630 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1631 N0.getOperand(1) == N1.getOperand(1)) { 1632 SDValue ORNode = DAG.getNode(N->getOpcode(), 1633 N0.getOperand(0).getValueType(), 1634 N0.getOperand(0), N1.getOperand(0)); 1635 AddToWorkList(ORNode.getNode()); 1636 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1637 } 1638 1639 return SDValue(); 1640} 1641 1642SDValue DAGCombiner::visitAND(SDNode *N) { 1643 SDValue N0 = N->getOperand(0); 1644 SDValue N1 = N->getOperand(1); 1645 SDValue LL, LR, RL, RR, CC0, CC1; 1646 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1647 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1648 MVT VT = N1.getValueType(); 1649 unsigned BitWidth = VT.getSizeInBits(); 1650 1651 // fold vector ops 1652 if (VT.isVector()) { 1653 SDValue FoldedVOp = SimplifyVBinOp(N); 1654 if (FoldedVOp.getNode()) return FoldedVOp; 1655 } 1656 1657 // fold (and x, undef) -> 0 1658 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1659 return DAG.getConstant(0, VT); 1660 // fold (and c1, c2) -> c1&c2 1661 if (N0C && N1C) 1662 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1663 // canonicalize constant to RHS 1664 if (N0C && !N1C) 1665 return DAG.getNode(ISD::AND, VT, N1, N0); 1666 // fold (and x, -1) -> x 1667 if (N1C && N1C->isAllOnesValue()) 1668 return N0; 1669 // if (and x, c) is known to be zero, return 0 1670 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1671 APInt::getAllOnesValue(BitWidth))) 1672 return DAG.getConstant(0, VT); 1673 // reassociate and 1674 SDValue RAND = ReassociateOps(ISD::AND, N0, N1); 1675 if (RAND.getNode() != 0) 1676 return RAND; 1677 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1678 if (N1C && N0.getOpcode() == ISD::OR) 1679 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1680 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1681 return N1; 1682 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1683 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1684 SDValue N0Op0 = N0.getOperand(0); 1685 APInt Mask = ~N1C->getAPIntValue(); 1686 Mask.trunc(N0Op0.getValueSizeInBits()); 1687 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1688 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1689 N0Op0); 1690 1691 // Replace uses of the AND with uses of the Zero extend node. 1692 CombineTo(N, Zext); 1693 1694 // We actually want to replace all uses of the any_extend with the 1695 // zero_extend, to avoid duplicating things. This will later cause this 1696 // AND to be folded. 1697 CombineTo(N0.getNode(), Zext); 1698 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1699 } 1700 } 1701 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1702 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1703 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1704 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1705 1706 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1707 LL.getValueType().isInteger()) { 1708 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1709 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1710 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1711 AddToWorkList(ORNode.getNode()); 1712 return DAG.getSetCC(VT, ORNode, LR, Op1); 1713 } 1714 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1715 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1716 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1717 AddToWorkList(ANDNode.getNode()); 1718 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1719 } 1720 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1721 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1722 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1723 AddToWorkList(ORNode.getNode()); 1724 return DAG.getSetCC(VT, ORNode, LR, Op1); 1725 } 1726 } 1727 // canonicalize equivalent to ll == rl 1728 if (LL == RR && LR == RL) { 1729 Op1 = ISD::getSetCCSwappedOperands(Op1); 1730 std::swap(RL, RR); 1731 } 1732 if (LL == RL && LR == RR) { 1733 bool isInteger = LL.getValueType().isInteger(); 1734 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1735 if (Result != ISD::SETCC_INVALID && 1736 (!AfterLegalize || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1737 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1738 } 1739 } 1740 1741 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1742 if (N0.getOpcode() == N1.getOpcode()) { 1743 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1744 if (Tmp.getNode()) return Tmp; 1745 } 1746 1747 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1748 // fold (and (sra)) -> (and (srl)) when possible. 1749 if (!VT.isVector() && 1750 SimplifyDemandedBits(SDValue(N, 0))) 1751 return SDValue(N, 0); 1752 // fold (zext_inreg (extload x)) -> (zextload x) 1753 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1754 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1755 MVT EVT = LN0->getMemoryVT(); 1756 // If we zero all the possible extended bits, then we can turn this into 1757 // a zextload if we are running before legalize or the operation is legal. 1758 unsigned BitWidth = N1.getValueSizeInBits(); 1759 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1760 BitWidth - EVT.getSizeInBits())) && 1761 ((!AfterLegalize && !LN0->isVolatile()) || 1762 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1763 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1764 LN0->getBasePtr(), LN0->getSrcValue(), 1765 LN0->getSrcValueOffset(), EVT, 1766 LN0->isVolatile(), 1767 LN0->getAlignment()); 1768 AddToWorkList(N); 1769 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1770 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1771 } 1772 } 1773 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1774 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1775 N0.hasOneUse()) { 1776 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1777 MVT EVT = LN0->getMemoryVT(); 1778 // If we zero all the possible extended bits, then we can turn this into 1779 // a zextload if we are running before legalize or the operation is legal. 1780 unsigned BitWidth = N1.getValueSizeInBits(); 1781 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1782 BitWidth - EVT.getSizeInBits())) && 1783 ((!AfterLegalize && !LN0->isVolatile()) || 1784 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1785 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1786 LN0->getBasePtr(), LN0->getSrcValue(), 1787 LN0->getSrcValueOffset(), EVT, 1788 LN0->isVolatile(), 1789 LN0->getAlignment()); 1790 AddToWorkList(N); 1791 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1792 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1793 } 1794 } 1795 1796 // fold (and (load x), 255) -> (zextload x, i8) 1797 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1798 if (N1C && N0.getOpcode() == ISD::LOAD) { 1799 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1800 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1801 LN0->isUnindexed() && N0.hasOneUse() && 1802 // Do not change the width of a volatile load. 1803 !LN0->isVolatile()) { 1804 MVT EVT = MVT::Other; 1805 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1806 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1807 EVT = MVT::getIntegerVT(ActiveBits); 1808 1809 MVT LoadedVT = LN0->getMemoryVT(); 1810 // Do not generate loads of non-round integer types since these can 1811 // be expensive (and would be wrong if the type is not byte sized). 1812 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1813 (!AfterLegalize || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1814 MVT PtrType = N0.getOperand(1).getValueType(); 1815 // For big endian targets, we need to add an offset to the pointer to 1816 // load the correct bytes. For little endian systems, we merely need to 1817 // read fewer bytes from the same pointer. 1818 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1819 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1820 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1821 unsigned Alignment = LN0->getAlignment(); 1822 SDValue NewPtr = LN0->getBasePtr(); 1823 if (TLI.isBigEndian()) { 1824 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1825 DAG.getConstant(PtrOff, PtrType)); 1826 Alignment = MinAlign(Alignment, PtrOff); 1827 } 1828 AddToWorkList(NewPtr.getNode()); 1829 SDValue Load = 1830 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1831 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1832 LN0->isVolatile(), Alignment); 1833 AddToWorkList(N); 1834 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1835 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1836 } 1837 } 1838 } 1839 1840 return SDValue(); 1841} 1842 1843SDValue DAGCombiner::visitOR(SDNode *N) { 1844 SDValue N0 = N->getOperand(0); 1845 SDValue N1 = N->getOperand(1); 1846 SDValue LL, LR, RL, RR, CC0, CC1; 1847 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1848 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1849 MVT VT = N1.getValueType(); 1850 1851 // fold vector ops 1852 if (VT.isVector()) { 1853 SDValue FoldedVOp = SimplifyVBinOp(N); 1854 if (FoldedVOp.getNode()) return FoldedVOp; 1855 } 1856 1857 // fold (or x, undef) -> -1 1858 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1859 return DAG.getConstant(~0ULL, VT); 1860 // fold (or c1, c2) -> c1|c2 1861 if (N0C && N1C) 1862 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1863 // canonicalize constant to RHS 1864 if (N0C && !N1C) 1865 return DAG.getNode(ISD::OR, VT, N1, N0); 1866 // fold (or x, 0) -> x 1867 if (N1C && N1C->isNullValue()) 1868 return N0; 1869 // fold (or x, -1) -> -1 1870 if (N1C && N1C->isAllOnesValue()) 1871 return N1; 1872 // fold (or x, c) -> c iff (x & ~c) == 0 1873 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1874 return N1; 1875 // reassociate or 1876 SDValue ROR = ReassociateOps(ISD::OR, N0, N1); 1877 if (ROR.getNode() != 0) 1878 return ROR; 1879 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1880 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1881 isa<ConstantSDNode>(N0.getOperand(1))) { 1882 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1883 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1884 N1), 1885 DAG.getConstant(N1C->getAPIntValue() | 1886 C1->getAPIntValue(), VT)); 1887 } 1888 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1889 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1890 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1891 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1892 1893 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1894 LL.getValueType().isInteger()) { 1895 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1896 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1897 if (cast<ConstantSDNode>(LR)->isNullValue() && 1898 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1899 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1900 AddToWorkList(ORNode.getNode()); 1901 return DAG.getSetCC(VT, ORNode, LR, Op1); 1902 } 1903 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1904 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1905 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1906 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1907 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1908 AddToWorkList(ANDNode.getNode()); 1909 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1910 } 1911 } 1912 // canonicalize equivalent to ll == rl 1913 if (LL == RR && LR == RL) { 1914 Op1 = ISD::getSetCCSwappedOperands(Op1); 1915 std::swap(RL, RR); 1916 } 1917 if (LL == RL && LR == RR) { 1918 bool isInteger = LL.getValueType().isInteger(); 1919 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1920 if (Result != ISD::SETCC_INVALID && 1921 (!AfterLegalize || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1922 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1923 } 1924 } 1925 1926 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1927 if (N0.getOpcode() == N1.getOpcode()) { 1928 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1929 if (Tmp.getNode()) return Tmp; 1930 } 1931 1932 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1933 if (N0.getOpcode() == ISD::AND && 1934 N1.getOpcode() == ISD::AND && 1935 N0.getOperand(1).getOpcode() == ISD::Constant && 1936 N1.getOperand(1).getOpcode() == ISD::Constant && 1937 // Don't increase # computations. 1938 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 1939 // We can only do this xform if we know that bits from X that are set in C2 1940 // but not in C1 are already zero. Likewise for Y. 1941 const APInt &LHSMask = 1942 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1943 const APInt &RHSMask = 1944 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1945 1946 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1947 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1948 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1949 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1950 } 1951 } 1952 1953 1954 // See if this is some rotate idiom. 1955 if (SDNode *Rot = MatchRotate(N0, N1)) 1956 return SDValue(Rot, 0); 1957 1958 return SDValue(); 1959} 1960 1961 1962/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1963static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 1964 if (Op.getOpcode() == ISD::AND) { 1965 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1966 Mask = Op.getOperand(1); 1967 Op = Op.getOperand(0); 1968 } else { 1969 return false; 1970 } 1971 } 1972 1973 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1974 Shift = Op; 1975 return true; 1976 } 1977 return false; 1978} 1979 1980 1981// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1982// idioms for rotate, and if the target supports rotation instructions, generate 1983// a rot[lr]. 1984SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 1985 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 1986 MVT VT = LHS.getValueType(); 1987 if (!TLI.isTypeLegal(VT)) return 0; 1988 1989 // The target must have at least one rotate flavor. 1990 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1991 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1992 if (!HasROTL && !HasROTR) return 0; 1993 1994 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1995 SDValue LHSShift; // The shift. 1996 SDValue LHSMask; // AND value if any. 1997 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1998 return 0; // Not part of a rotate. 1999 2000 SDValue RHSShift; // The shift. 2001 SDValue RHSMask; // AND value if any. 2002 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2003 return 0; // Not part of a rotate. 2004 2005 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2006 return 0; // Not shifting the same value. 2007 2008 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2009 return 0; // Shifts must disagree. 2010 2011 // Canonicalize shl to left side in a shl/srl pair. 2012 if (RHSShift.getOpcode() == ISD::SHL) { 2013 std::swap(LHS, RHS); 2014 std::swap(LHSShift, RHSShift); 2015 std::swap(LHSMask , RHSMask ); 2016 } 2017 2018 unsigned OpSizeInBits = VT.getSizeInBits(); 2019 SDValue LHSShiftArg = LHSShift.getOperand(0); 2020 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2021 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2022 2023 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2024 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2025 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2026 RHSShiftAmt.getOpcode() == ISD::Constant) { 2027 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2028 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2029 if ((LShVal + RShVal) != OpSizeInBits) 2030 return 0; 2031 2032 SDValue Rot; 2033 if (HasROTL) 2034 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2035 else 2036 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2037 2038 // If there is an AND of either shifted operand, apply it to the result. 2039 if (LHSMask.getNode() || RHSMask.getNode()) { 2040 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2041 2042 if (LHSMask.getNode()) { 2043 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2044 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2045 } 2046 if (RHSMask.getNode()) { 2047 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2048 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2049 } 2050 2051 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2052 } 2053 2054 return Rot.getNode(); 2055 } 2056 2057 // If there is a mask here, and we have a variable shift, we can't be sure 2058 // that we're masking out the right stuff. 2059 if (LHSMask.getNode() || RHSMask.getNode()) 2060 return 0; 2061 2062 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2063 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2064 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2065 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2066 if (ConstantSDNode *SUBC = 2067 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2068 if (SUBC->getAPIntValue() == OpSizeInBits) { 2069 if (HasROTL) 2070 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2071 else 2072 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2073 } 2074 } 2075 } 2076 2077 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2078 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2079 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2080 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2081 if (ConstantSDNode *SUBC = 2082 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2083 if (SUBC->getAPIntValue() == OpSizeInBits) { 2084 if (HasROTR) 2085 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2086 else 2087 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2088 } 2089 } 2090 } 2091 2092 // Look for sign/zext/any-extended or truncate cases: 2093 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2094 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2095 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2096 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2097 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2098 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2099 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2100 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2101 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2102 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2103 if (RExtOp0.getOpcode() == ISD::SUB && 2104 RExtOp0.getOperand(1) == LExtOp0) { 2105 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2106 // (rotl x, y) 2107 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2108 // (rotr x, (sub 32, y)) 2109 if (ConstantSDNode *SUBC = 2110 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2111 if (SUBC->getAPIntValue() == OpSizeInBits) { 2112 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, 2113 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2114 } 2115 } 2116 } else if (LExtOp0.getOpcode() == ISD::SUB && 2117 RExtOp0 == LExtOp0.getOperand(1)) { 2118 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2119 // (rotr x, y) 2120 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2121 // (rotl x, (sub 32, y)) 2122 if (ConstantSDNode *SUBC = 2123 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2124 if (SUBC->getAPIntValue() == OpSizeInBits) { 2125 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, 2126 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2127 } 2128 } 2129 } 2130 } 2131 2132 return 0; 2133} 2134 2135 2136SDValue DAGCombiner::visitXOR(SDNode *N) { 2137 SDValue N0 = N->getOperand(0); 2138 SDValue N1 = N->getOperand(1); 2139 SDValue LHS, RHS, CC; 2140 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2141 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2142 MVT VT = N0.getValueType(); 2143 2144 // fold vector ops 2145 if (VT.isVector()) { 2146 SDValue FoldedVOp = SimplifyVBinOp(N); 2147 if (FoldedVOp.getNode()) return FoldedVOp; 2148 } 2149 2150 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2151 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2152 return DAG.getConstant(0, VT); 2153 // fold (xor x, undef) -> undef 2154 if (N0.getOpcode() == ISD::UNDEF) 2155 return N0; 2156 if (N1.getOpcode() == ISD::UNDEF) 2157 return N1; 2158 // fold (xor c1, c2) -> c1^c2 2159 if (N0C && N1C) 2160 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2161 // canonicalize constant to RHS 2162 if (N0C && !N1C) 2163 return DAG.getNode(ISD::XOR, VT, N1, N0); 2164 // fold (xor x, 0) -> x 2165 if (N1C && N1C->isNullValue()) 2166 return N0; 2167 // reassociate xor 2168 SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1); 2169 if (RXOR.getNode() != 0) 2170 return RXOR; 2171 2172 // fold !(x cc y) -> (x !cc y) 2173 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2174 bool isInt = LHS.getValueType().isInteger(); 2175 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2176 isInt); 2177 2178 if (!AfterLegalize || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2179 switch (N0.getOpcode()) { 2180 default: 2181 assert(0 && "Unhandled SetCC Equivalent!"); 2182 abort(); 2183 case ISD::SETCC: 2184 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2185 case ISD::SELECT_CC: 2186 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2), 2187 N0.getOperand(3), NotCC); 2188 } 2189 } 2190 } 2191 2192 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2193 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2194 N0.getNode()->hasOneUse() && 2195 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2196 SDValue V = N0.getOperand(0); 2197 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2198 DAG.getConstant(1, V.getValueType())); 2199 AddToWorkList(V.getNode()); 2200 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2201 } 2202 2203 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2204 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2205 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2206 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2207 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2208 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2209 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2210 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2211 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2212 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2213 } 2214 } 2215 // fold !(x or y) -> (!x and !y) iff x or y are constants 2216 if (N1C && N1C->isAllOnesValue() && 2217 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2218 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2219 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2220 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2221 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2222 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2223 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2224 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2225 } 2226 } 2227 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2228 if (N1C && N0.getOpcode() == ISD::XOR) { 2229 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2230 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2231 if (N00C) 2232 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2233 DAG.getConstant(N1C->getAPIntValue()^ 2234 N00C->getAPIntValue(), VT)); 2235 if (N01C) 2236 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2237 DAG.getConstant(N1C->getAPIntValue()^ 2238 N01C->getAPIntValue(), VT)); 2239 } 2240 // fold (xor x, x) -> 0 2241 if (N0 == N1) { 2242 if (!VT.isVector()) { 2243 return DAG.getConstant(0, VT); 2244 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2245 // Produce a vector of zeros. 2246 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2247 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2248 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2249 } 2250 } 2251 2252 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2253 if (N0.getOpcode() == N1.getOpcode()) { 2254 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2255 if (Tmp.getNode()) return Tmp; 2256 } 2257 2258 // Simplify the expression using non-local knowledge. 2259 if (!VT.isVector() && 2260 SimplifyDemandedBits(SDValue(N, 0))) 2261 return SDValue(N, 0); 2262 2263 return SDValue(); 2264} 2265 2266/// visitShiftByConstant - Handle transforms common to the three shifts, when 2267/// the shift amount is a constant. 2268SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2269 SDNode *LHS = N->getOperand(0).getNode(); 2270 if (!LHS->hasOneUse()) return SDValue(); 2271 2272 // We want to pull some binops through shifts, so that we have (and (shift)) 2273 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2274 // thing happens with address calculations, so it's important to canonicalize 2275 // it. 2276 bool HighBitSet = false; // Can we transform this if the high bit is set? 2277 2278 switch (LHS->getOpcode()) { 2279 default: return SDValue(); 2280 case ISD::OR: 2281 case ISD::XOR: 2282 HighBitSet = false; // We can only transform sra if the high bit is clear. 2283 break; 2284 case ISD::AND: 2285 HighBitSet = true; // We can only transform sra if the high bit is set. 2286 break; 2287 case ISD::ADD: 2288 if (N->getOpcode() != ISD::SHL) 2289 return SDValue(); // only shl(add) not sr[al](add). 2290 HighBitSet = false; // We can only transform sra if the high bit is clear. 2291 break; 2292 } 2293 2294 // We require the RHS of the binop to be a constant as well. 2295 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2296 if (!BinOpCst) return SDValue(); 2297 2298 2299 // FIXME: disable this for unless the input to the binop is a shift by a 2300 // constant. If it is not a shift, it pessimizes some common cases like: 2301 // 2302 //void foo(int *X, int i) { X[i & 1235] = 1; } 2303 //int bar(int *X, int i) { return X[i & 255]; } 2304 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2305 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2306 BinOpLHSVal->getOpcode() != ISD::SRA && 2307 BinOpLHSVal->getOpcode() != ISD::SRL) || 2308 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2309 return SDValue(); 2310 2311 MVT VT = N->getValueType(0); 2312 2313 // If this is a signed shift right, and the high bit is modified 2314 // by the logical operation, do not perform the transformation. 2315 // The highBitSet boolean indicates the value of the high bit of 2316 // the constant which would cause it to be modified for this 2317 // operation. 2318 if (N->getOpcode() == ISD::SRA) { 2319 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2320 if (BinOpRHSSignSet != HighBitSet) 2321 return SDValue(); 2322 } 2323 2324 // Fold the constants, shifting the binop RHS by the shift amount. 2325 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2326 LHS->getOperand(1), N->getOperand(1)); 2327 2328 // Create the new shift. 2329 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2330 N->getOperand(1)); 2331 2332 // Create the new binop. 2333 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2334} 2335 2336 2337SDValue DAGCombiner::visitSHL(SDNode *N) { 2338 SDValue N0 = N->getOperand(0); 2339 SDValue N1 = N->getOperand(1); 2340 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2341 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2342 MVT VT = N0.getValueType(); 2343 unsigned OpSizeInBits = VT.getSizeInBits(); 2344 2345 // fold (shl c1, c2) -> c1<<c2 2346 if (N0C && N1C) 2347 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2348 // fold (shl 0, x) -> 0 2349 if (N0C && N0C->isNullValue()) 2350 return N0; 2351 // fold (shl x, c >= size(x)) -> undef 2352 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2353 return DAG.getNode(ISD::UNDEF, VT); 2354 // fold (shl x, 0) -> x 2355 if (N1C && N1C->isNullValue()) 2356 return N0; 2357 // if (shl x, c) is known to be zero, return 0 2358 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2359 APInt::getAllOnesValue(VT.getSizeInBits()))) 2360 return DAG.getConstant(0, VT); 2361 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2362 // iff (trunc c) == c 2363 if (N1.getOpcode() == ISD::TRUNCATE && 2364 N1.getOperand(0).getOpcode() == ISD::AND && 2365 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2366 SDValue N101 = N1.getOperand(0).getOperand(1); 2367 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2368 MVT TruncVT = N1.getValueType(); 2369 SDValue N100 = N1.getOperand(0).getOperand(0); 2370 return DAG.getNode(ISD::SHL, VT, N0, 2371 DAG.getNode(ISD::AND, TruncVT, 2372 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2373 DAG.getConstant(N101C->getZExtValue(), 2374 TruncVT))); 2375 } 2376 } 2377 2378 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2379 return SDValue(N, 0); 2380 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2381 if (N1C && N0.getOpcode() == ISD::SHL && 2382 N0.getOperand(1).getOpcode() == ISD::Constant) { 2383 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2384 uint64_t c2 = N1C->getZExtValue(); 2385 if (c1 + c2 > OpSizeInBits) 2386 return DAG.getConstant(0, VT); 2387 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2388 DAG.getConstant(c1 + c2, N1.getValueType())); 2389 } 2390 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2391 // (srl (and x, -1 << c1), c1-c2) 2392 if (N1C && N0.getOpcode() == ISD::SRL && 2393 N0.getOperand(1).getOpcode() == ISD::Constant) { 2394 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2395 uint64_t c2 = N1C->getZExtValue(); 2396 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2397 DAG.getConstant(~0ULL << c1, VT)); 2398 if (c2 > c1) 2399 return DAG.getNode(ISD::SHL, VT, Mask, 2400 DAG.getConstant(c2-c1, N1.getValueType())); 2401 else 2402 return DAG.getNode(ISD::SRL, VT, Mask, 2403 DAG.getConstant(c1-c2, N1.getValueType())); 2404 } 2405 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2406 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2407 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2408 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2409 2410 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2411} 2412 2413SDValue DAGCombiner::visitSRA(SDNode *N) { 2414 SDValue N0 = N->getOperand(0); 2415 SDValue N1 = N->getOperand(1); 2416 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2417 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2418 MVT VT = N0.getValueType(); 2419 2420 // fold (sra c1, c2) -> c1>>c2 2421 if (N0C && N1C) 2422 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2423 // fold (sra 0, x) -> 0 2424 if (N0C && N0C->isNullValue()) 2425 return N0; 2426 // fold (sra -1, x) -> -1 2427 if (N0C && N0C->isAllOnesValue()) 2428 return N0; 2429 // fold (sra x, c >= size(x)) -> undef 2430 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2431 return DAG.getNode(ISD::UNDEF, VT); 2432 // fold (sra x, 0) -> x 2433 if (N1C && N1C->isNullValue()) 2434 return N0; 2435 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2436 // sext_inreg. 2437 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2438 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2439 MVT EVT = MVT::getIntegerVT(LowBits); 2440 if (EVT.isSimple() && // TODO: remove when apint codegen support lands. 2441 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2442 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2443 DAG.getValueType(EVT)); 2444 } 2445 2446 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2447 if (N1C && N0.getOpcode() == ISD::SRA) { 2448 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2449 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2450 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2451 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2452 DAG.getConstant(Sum, N1C->getValueType(0))); 2453 } 2454 } 2455 2456 // fold sra (shl X, m), result_size - n 2457 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2458 // result_size - n != m. 2459 // If truncate is free for the target sext(shl) is likely to result in better 2460 // code. 2461 if (N0.getOpcode() == ISD::SHL) { 2462 // Get the two constanst of the shifts, CN0 = m, CN = n. 2463 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2464 if (N01C && N1C) { 2465 // Determine what the truncate's result bitsize and type would be. 2466 unsigned VTValSize = VT.getSizeInBits(); 2467 MVT TruncVT = 2468 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2469 // Determine the residual right-shift amount. 2470 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2471 2472 // If the shift is not a no-op (in which case this should be just a sign 2473 // extend already), the truncated to type is legal, sign_extend is legal 2474 // on that type, and the the truncate to that type is both legal and free, 2475 // perform the transform. 2476 if (ShiftAmt && 2477 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2478 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2479 TLI.isTruncateFree(VT, TruncVT)) { 2480 2481 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2482 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2483 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2484 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2485 } 2486 } 2487 } 2488 2489 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2490 // iff (trunc c) == c 2491 if (N1.getOpcode() == ISD::TRUNCATE && 2492 N1.getOperand(0).getOpcode() == ISD::AND && 2493 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2494 SDValue N101 = N1.getOperand(0).getOperand(1); 2495 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2496 MVT TruncVT = N1.getValueType(); 2497 SDValue N100 = N1.getOperand(0).getOperand(0); 2498 return DAG.getNode(ISD::SRA, VT, N0, 2499 DAG.getNode(ISD::AND, TruncVT, 2500 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2501 DAG.getConstant(N101C->getZExtValue(), 2502 TruncVT))); 2503 } 2504 } 2505 2506 // Simplify, based on bits shifted out of the LHS. 2507 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2508 return SDValue(N, 0); 2509 2510 2511 // If the sign bit is known to be zero, switch this to a SRL. 2512 if (DAG.SignBitIsZero(N0)) 2513 return DAG.getNode(ISD::SRL, VT, N0, N1); 2514 2515 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2516} 2517 2518SDValue DAGCombiner::visitSRL(SDNode *N) { 2519 SDValue N0 = N->getOperand(0); 2520 SDValue N1 = N->getOperand(1); 2521 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2522 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2523 MVT VT = N0.getValueType(); 2524 unsigned OpSizeInBits = VT.getSizeInBits(); 2525 2526 // fold (srl c1, c2) -> c1 >>u c2 2527 if (N0C && N1C) 2528 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2529 // fold (srl 0, x) -> 0 2530 if (N0C && N0C->isNullValue()) 2531 return N0; 2532 // fold (srl x, c >= size(x)) -> undef 2533 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2534 return DAG.getNode(ISD::UNDEF, VT); 2535 // fold (srl x, 0) -> x 2536 if (N1C && N1C->isNullValue()) 2537 return N0; 2538 // if (srl x, c) is known to be zero, return 0 2539 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2540 APInt::getAllOnesValue(OpSizeInBits))) 2541 return DAG.getConstant(0, VT); 2542 2543 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2544 if (N1C && N0.getOpcode() == ISD::SRL && 2545 N0.getOperand(1).getOpcode() == ISD::Constant) { 2546 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2547 uint64_t c2 = N1C->getZExtValue(); 2548 if (c1 + c2 > OpSizeInBits) 2549 return DAG.getConstant(0, VT); 2550 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2551 DAG.getConstant(c1 + c2, N1.getValueType())); 2552 } 2553 2554 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2555 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2556 // Shifting in all undef bits? 2557 MVT SmallVT = N0.getOperand(0).getValueType(); 2558 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2559 return DAG.getNode(ISD::UNDEF, VT); 2560 2561 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2562 AddToWorkList(SmallShift.getNode()); 2563 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2564 } 2565 2566 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2567 // bit, which is unmodified by sra. 2568 if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { 2569 if (N0.getOpcode() == ISD::SRA) 2570 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2571 } 2572 2573 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2574 if (N1C && N0.getOpcode() == ISD::CTLZ && 2575 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2576 APInt KnownZero, KnownOne; 2577 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2578 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2579 2580 // If any of the input bits are KnownOne, then the input couldn't be all 2581 // zeros, thus the result of the srl will always be zero. 2582 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2583 2584 // If all of the bits input the to ctlz node are known to be zero, then 2585 // the result of the ctlz is "32" and the result of the shift is one. 2586 APInt UnknownBits = ~KnownZero & Mask; 2587 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2588 2589 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2590 if ((UnknownBits & (UnknownBits-1)) == 0) { 2591 // Okay, we know that only that the single bit specified by UnknownBits 2592 // could be set on input to the CTLZ node. If this bit is set, the SRL 2593 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2594 // to an SRL,XOR pair, which is likely to simplify more. 2595 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2596 SDValue Op = N0.getOperand(0); 2597 if (ShAmt) { 2598 Op = DAG.getNode(ISD::SRL, VT, Op, 2599 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2600 AddToWorkList(Op.getNode()); 2601 } 2602 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2603 } 2604 } 2605 2606 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2607 // iff (trunc c) == c 2608 if (N1.getOpcode() == ISD::TRUNCATE && 2609 N1.getOperand(0).getOpcode() == ISD::AND && 2610 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2611 SDValue N101 = N1.getOperand(0).getOperand(1); 2612 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2613 MVT TruncVT = N1.getValueType(); 2614 SDValue N100 = N1.getOperand(0).getOperand(0); 2615 return DAG.getNode(ISD::SRL, VT, N0, 2616 DAG.getNode(ISD::AND, TruncVT, 2617 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2618 DAG.getConstant(N101C->getZExtValue(), 2619 TruncVT))); 2620 } 2621 } 2622 2623 // fold operands of srl based on knowledge that the low bits are not 2624 // demanded. 2625 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2626 return SDValue(N, 0); 2627 2628 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2629} 2630 2631SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2632 SDValue N0 = N->getOperand(0); 2633 MVT VT = N->getValueType(0); 2634 2635 // fold (ctlz c1) -> c2 2636 if (isa<ConstantSDNode>(N0)) 2637 return DAG.getNode(ISD::CTLZ, VT, N0); 2638 return SDValue(); 2639} 2640 2641SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2642 SDValue N0 = N->getOperand(0); 2643 MVT VT = N->getValueType(0); 2644 2645 // fold (cttz c1) -> c2 2646 if (isa<ConstantSDNode>(N0)) 2647 return DAG.getNode(ISD::CTTZ, VT, N0); 2648 return SDValue(); 2649} 2650 2651SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2652 SDValue N0 = N->getOperand(0); 2653 MVT VT = N->getValueType(0); 2654 2655 // fold (ctpop c1) -> c2 2656 if (isa<ConstantSDNode>(N0)) 2657 return DAG.getNode(ISD::CTPOP, VT, N0); 2658 return SDValue(); 2659} 2660 2661SDValue DAGCombiner::visitSELECT(SDNode *N) { 2662 SDValue N0 = N->getOperand(0); 2663 SDValue N1 = N->getOperand(1); 2664 SDValue N2 = N->getOperand(2); 2665 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2666 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2667 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2668 MVT VT = N->getValueType(0); 2669 MVT VT0 = N0.getValueType(); 2670 2671 // fold select C, X, X -> X 2672 if (N1 == N2) 2673 return N1; 2674 // fold select true, X, Y -> X 2675 if (N0C && !N0C->isNullValue()) 2676 return N1; 2677 // fold select false, X, Y -> Y 2678 if (N0C && N0C->isNullValue()) 2679 return N2; 2680 // fold select C, 1, X -> C | X 2681 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2682 return DAG.getNode(ISD::OR, VT, N0, N2); 2683 // fold select C, 0, 1 -> ~C 2684 if (VT.isInteger() && VT0.isInteger() && 2685 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2686 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2687 if (VT == VT0) 2688 return XORNode; 2689 AddToWorkList(XORNode.getNode()); 2690 if (VT.bitsGT(VT0)) 2691 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2692 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2693 } 2694 // fold select C, 0, X -> ~C & X 2695 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2696 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2697 AddToWorkList(XORNode.getNode()); 2698 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2699 } 2700 // fold select C, X, 1 -> ~C | X 2701 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2702 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2703 AddToWorkList(XORNode.getNode()); 2704 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2705 } 2706 // fold select C, X, 0 -> C & X 2707 // FIXME: this should check for C type == X type, not i1? 2708 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2709 return DAG.getNode(ISD::AND, VT, N0, N1); 2710 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2711 if (VT == MVT::i1 && N0 == N1) 2712 return DAG.getNode(ISD::OR, VT, N0, N2); 2713 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2714 if (VT == MVT::i1 && N0 == N2) 2715 return DAG.getNode(ISD::AND, VT, N0, N1); 2716 2717 // If we can fold this based on the true/false value, do so. 2718 if (SimplifySelectOps(N, N1, N2)) 2719 return SDValue(N, 0); // Don't revisit N. 2720 2721 // fold selects based on a setcc into other things, such as min/max/abs 2722 if (N0.getOpcode() == ISD::SETCC) { 2723 // FIXME: 2724 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2725 // having to say they don't support SELECT_CC on every type the DAG knows 2726 // about, since there is no way to mark an opcode illegal at all value types 2727 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2728 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2729 N1, N2, N0.getOperand(2)); 2730 else 2731 return SimplifySelect(N0, N1, N2); 2732 } 2733 return SDValue(); 2734} 2735 2736SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2737 SDValue N0 = N->getOperand(0); 2738 SDValue N1 = N->getOperand(1); 2739 SDValue N2 = N->getOperand(2); 2740 SDValue N3 = N->getOperand(3); 2741 SDValue N4 = N->getOperand(4); 2742 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2743 2744 // fold select_cc lhs, rhs, x, x, cc -> x 2745 if (N2 == N3) 2746 return N2; 2747 2748 // Determine if the condition we're dealing with is constant 2749 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2750 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2751 2752 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2753 if (!SCCC->isNullValue()) 2754 return N2; // cond always true -> true val 2755 else 2756 return N3; // cond always false -> false val 2757 } 2758 2759 // Fold to a simpler select_cc 2760 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2761 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2762 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2763 SCC.getOperand(2)); 2764 2765 // If we can fold this based on the true/false value, do so. 2766 if (SimplifySelectOps(N, N2, N3)) 2767 return SDValue(N, 0); // Don't revisit N. 2768 2769 // fold select_cc into other things, such as min/max/abs 2770 return SimplifySelectCC(N0, N1, N2, N3, CC); 2771} 2772 2773SDValue DAGCombiner::visitSETCC(SDNode *N) { 2774 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2775 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2776} 2777 2778// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2779// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2780// transformation. Returns true if extension are possible and the above 2781// mentioned transformation is profitable. 2782static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2783 unsigned ExtOpc, 2784 SmallVector<SDNode*, 4> &ExtendNodes, 2785 TargetLowering &TLI) { 2786 bool HasCopyToRegUses = false; 2787 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2788 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2789 UE = N0.getNode()->use_end(); 2790 UI != UE; ++UI) { 2791 SDNode *User = *UI; 2792 if (User == N) 2793 continue; 2794 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2795 if (User->getOpcode() == ISD::SETCC) { 2796 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2797 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2798 // Sign bits will be lost after a zext. 2799 return false; 2800 bool Add = false; 2801 for (unsigned i = 0; i != 2; ++i) { 2802 SDValue UseOp = User->getOperand(i); 2803 if (UseOp == N0) 2804 continue; 2805 if (!isa<ConstantSDNode>(UseOp)) 2806 return false; 2807 Add = true; 2808 } 2809 if (Add) 2810 ExtendNodes.push_back(User); 2811 } else { 2812 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2813 SDValue UseOp = User->getOperand(i); 2814 if (UseOp == N0) { 2815 // If truncate from extended type to original load type is free 2816 // on this target, then it's ok to extend a CopyToReg. 2817 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2818 HasCopyToRegUses = true; 2819 else 2820 return false; 2821 } 2822 } 2823 } 2824 } 2825 2826 if (HasCopyToRegUses) { 2827 bool BothLiveOut = false; 2828 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2829 UI != UE; ++UI) { 2830 SDNode *User = *UI; 2831 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2832 SDValue UseOp = User->getOperand(i); 2833 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2834 BothLiveOut = true; 2835 break; 2836 } 2837 } 2838 } 2839 if (BothLiveOut) 2840 // Both unextended and extended values are live out. There had better be 2841 // good a reason for the transformation. 2842 return ExtendNodes.size(); 2843 } 2844 return true; 2845} 2846 2847SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2848 SDValue N0 = N->getOperand(0); 2849 MVT VT = N->getValueType(0); 2850 2851 // fold (sext c1) -> c1 2852 if (isa<ConstantSDNode>(N0)) 2853 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2854 2855 // fold (sext (sext x)) -> (sext x) 2856 // fold (sext (aext x)) -> (sext x) 2857 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2858 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2859 2860 if (N0.getOpcode() == ISD::TRUNCATE) { 2861 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2862 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2863 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2864 if (NarrowLoad.getNode()) { 2865 if (NarrowLoad.getNode() != N0.getNode()) 2866 CombineTo(N0.getNode(), NarrowLoad); 2867 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2868 } 2869 2870 // See if the value being truncated is already sign extended. If so, just 2871 // eliminate the trunc/sext pair. 2872 SDValue Op = N0.getOperand(0); 2873 unsigned OpBits = Op.getValueType().getSizeInBits(); 2874 unsigned MidBits = N0.getValueType().getSizeInBits(); 2875 unsigned DestBits = VT.getSizeInBits(); 2876 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2877 2878 if (OpBits == DestBits) { 2879 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2880 // bits, it is already ready. 2881 if (NumSignBits > DestBits-MidBits) 2882 return Op; 2883 } else if (OpBits < DestBits) { 2884 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2885 // bits, just sext from i32. 2886 if (NumSignBits > OpBits-MidBits) 2887 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2888 } else { 2889 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2890 // bits, just truncate to i32. 2891 if (NumSignBits > OpBits-MidBits) 2892 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2893 } 2894 2895 // fold (sext (truncate x)) -> (sextinreg x). 2896 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2897 N0.getValueType())) { 2898 if (Op.getValueType().bitsLT(VT)) 2899 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2900 else if (Op.getValueType().bitsGT(VT)) 2901 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2902 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2903 DAG.getValueType(N0.getValueType())); 2904 } 2905 } 2906 2907 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2908 if (ISD::isNON_EXTLoad(N0.getNode()) && 2909 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2910 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 2911 bool DoXform = true; 2912 SmallVector<SDNode*, 4> SetCCs; 2913 if (!N0.hasOneUse()) 2914 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2915 if (DoXform) { 2916 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2917 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2918 LN0->getBasePtr(), LN0->getSrcValue(), 2919 LN0->getSrcValueOffset(), 2920 N0.getValueType(), 2921 LN0->isVolatile(), 2922 LN0->getAlignment()); 2923 CombineTo(N, ExtLoad); 2924 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2925 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 2926 // Extend SetCC uses if necessary. 2927 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2928 SDNode *SetCC = SetCCs[i]; 2929 SmallVector<SDValue, 4> Ops; 2930 for (unsigned j = 0; j != 2; ++j) { 2931 SDValue SOp = SetCC->getOperand(j); 2932 if (SOp == Trunc) 2933 Ops.push_back(ExtLoad); 2934 else 2935 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2936 } 2937 Ops.push_back(SetCC->getOperand(2)); 2938 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2939 &Ops[0], Ops.size())); 2940 } 2941 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2942 } 2943 } 2944 2945 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2946 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2947 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 2948 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 2949 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2950 MVT EVT = LN0->getMemoryVT(); 2951 if ((!AfterLegalize && !LN0->isVolatile()) || 2952 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 2953 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2954 LN0->getBasePtr(), LN0->getSrcValue(), 2955 LN0->getSrcValueOffset(), EVT, 2956 LN0->isVolatile(), 2957 LN0->getAlignment()); 2958 CombineTo(N, ExtLoad); 2959 CombineTo(N0.getNode(), 2960 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2961 ExtLoad.getValue(1)); 2962 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2963 } 2964 } 2965 2966 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2967 if (N0.getOpcode() == ISD::SETCC) { 2968 SDValue SCC = 2969 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2970 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2971 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2972 if (SCC.getNode()) return SCC; 2973 } 2974 2975 // fold (sext x) -> (zext x) if the sign bit is known zero. 2976 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 2977 DAG.SignBitIsZero(N0)) 2978 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2979 2980 return SDValue(); 2981} 2982 2983SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2984 SDValue N0 = N->getOperand(0); 2985 MVT VT = N->getValueType(0); 2986 2987 // fold (zext c1) -> c1 2988 if (isa<ConstantSDNode>(N0)) 2989 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2990 // fold (zext (zext x)) -> (zext x) 2991 // fold (zext (aext x)) -> (zext x) 2992 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2993 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2994 2995 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2996 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2997 if (N0.getOpcode() == ISD::TRUNCATE) { 2998 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2999 if (NarrowLoad.getNode()) { 3000 if (NarrowLoad.getNode() != N0.getNode()) 3001 CombineTo(N0.getNode(), NarrowLoad); 3002 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 3003 } 3004 } 3005 3006 // fold (zext (truncate x)) -> (and x, mask) 3007 if (N0.getOpcode() == ISD::TRUNCATE && 3008 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 3009 SDValue Op = N0.getOperand(0); 3010 if (Op.getValueType().bitsLT(VT)) { 3011 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 3012 } else if (Op.getValueType().bitsGT(VT)) { 3013 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3014 } 3015 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 3016 } 3017 3018 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3019 if (N0.getOpcode() == ISD::AND && 3020 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3021 N0.getOperand(1).getOpcode() == ISD::Constant) { 3022 SDValue X = N0.getOperand(0).getOperand(0); 3023 if (X.getValueType().bitsLT(VT)) { 3024 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3025 } else if (X.getValueType().bitsGT(VT)) { 3026 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3027 } 3028 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3029 Mask.zext(VT.getSizeInBits()); 3030 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3031 } 3032 3033 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3034 if (ISD::isNON_EXTLoad(N0.getNode()) && 3035 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3036 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3037 bool DoXform = true; 3038 SmallVector<SDNode*, 4> SetCCs; 3039 if (!N0.hasOneUse()) 3040 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3041 if (DoXform) { 3042 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3043 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3044 LN0->getBasePtr(), LN0->getSrcValue(), 3045 LN0->getSrcValueOffset(), 3046 N0.getValueType(), 3047 LN0->isVolatile(), 3048 LN0->getAlignment()); 3049 CombineTo(N, ExtLoad); 3050 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3051 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3052 // Extend SetCC uses if necessary. 3053 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3054 SDNode *SetCC = SetCCs[i]; 3055 SmallVector<SDValue, 4> Ops; 3056 for (unsigned j = 0; j != 2; ++j) { 3057 SDValue SOp = SetCC->getOperand(j); 3058 if (SOp == Trunc) 3059 Ops.push_back(ExtLoad); 3060 else 3061 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3062 } 3063 Ops.push_back(SetCC->getOperand(2)); 3064 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3065 &Ops[0], Ops.size())); 3066 } 3067 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3068 } 3069 } 3070 3071 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3072 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3073 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3074 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3075 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3076 MVT EVT = LN0->getMemoryVT(); 3077 if ((!AfterLegalize && !LN0->isVolatile()) || 3078 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3079 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3080 LN0->getBasePtr(), LN0->getSrcValue(), 3081 LN0->getSrcValueOffset(), EVT, 3082 LN0->isVolatile(), 3083 LN0->getAlignment()); 3084 CombineTo(N, ExtLoad); 3085 CombineTo(N0.getNode(), 3086 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3087 ExtLoad.getValue(1)); 3088 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3089 } 3090 } 3091 3092 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3093 if (N0.getOpcode() == ISD::SETCC) { 3094 SDValue SCC = 3095 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3096 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3097 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3098 if (SCC.getNode()) return SCC; 3099 } 3100 3101 return SDValue(); 3102} 3103 3104SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3105 SDValue N0 = N->getOperand(0); 3106 MVT VT = N->getValueType(0); 3107 3108 // fold (aext c1) -> c1 3109 if (isa<ConstantSDNode>(N0)) 3110 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3111 // fold (aext (aext x)) -> (aext x) 3112 // fold (aext (zext x)) -> (zext x) 3113 // fold (aext (sext x)) -> (sext x) 3114 if (N0.getOpcode() == ISD::ANY_EXTEND || 3115 N0.getOpcode() == ISD::ZERO_EXTEND || 3116 N0.getOpcode() == ISD::SIGN_EXTEND) 3117 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3118 3119 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3120 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3121 if (N0.getOpcode() == ISD::TRUNCATE) { 3122 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3123 if (NarrowLoad.getNode()) { 3124 if (NarrowLoad.getNode() != N0.getNode()) 3125 CombineTo(N0.getNode(), NarrowLoad); 3126 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3127 } 3128 } 3129 3130 // fold (aext (truncate x)) 3131 if (N0.getOpcode() == ISD::TRUNCATE) { 3132 SDValue TruncOp = N0.getOperand(0); 3133 if (TruncOp.getValueType() == VT) 3134 return TruncOp; // x iff x size == zext size. 3135 if (TruncOp.getValueType().bitsGT(VT)) 3136 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3137 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3138 } 3139 3140 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3141 if (N0.getOpcode() == ISD::AND && 3142 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3143 N0.getOperand(1).getOpcode() == ISD::Constant) { 3144 SDValue X = N0.getOperand(0).getOperand(0); 3145 if (X.getValueType().bitsLT(VT)) { 3146 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3147 } else if (X.getValueType().bitsGT(VT)) { 3148 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3149 } 3150 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3151 Mask.zext(VT.getSizeInBits()); 3152 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3153 } 3154 3155 // fold (aext (load x)) -> (aext (truncate (extload x))) 3156 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3157 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3158 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3159 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3160 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3161 LN0->getBasePtr(), LN0->getSrcValue(), 3162 LN0->getSrcValueOffset(), 3163 N0.getValueType(), 3164 LN0->isVolatile(), 3165 LN0->getAlignment()); 3166 CombineTo(N, ExtLoad); 3167 // Redirect any chain users to the new load. 3168 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3169 SDValue(ExtLoad.getNode(), 1)); 3170 // If any node needs the original loaded value, recompute it. 3171 if (!LN0->use_empty()) 3172 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3173 ExtLoad.getValue(1)); 3174 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3175 } 3176 3177 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3178 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3179 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3180 if (N0.getOpcode() == ISD::LOAD && 3181 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3182 N0.hasOneUse()) { 3183 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3184 MVT EVT = LN0->getMemoryVT(); 3185 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3186 LN0->getChain(), LN0->getBasePtr(), 3187 LN0->getSrcValue(), 3188 LN0->getSrcValueOffset(), EVT, 3189 LN0->isVolatile(), 3190 LN0->getAlignment()); 3191 CombineTo(N, ExtLoad); 3192 CombineTo(N0.getNode(), 3193 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3194 ExtLoad.getValue(1)); 3195 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3196 } 3197 3198 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3199 if (N0.getOpcode() == ISD::SETCC) { 3200 SDValue SCC = 3201 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3202 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3203 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3204 if (SCC.getNode()) 3205 return SCC; 3206 } 3207 3208 return SDValue(); 3209} 3210 3211/// GetDemandedBits - See if the specified operand can be simplified with the 3212/// knowledge that only the bits specified by Mask are used. If so, return the 3213/// simpler operand, otherwise return a null SDValue. 3214SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3215 switch (V.getOpcode()) { 3216 default: break; 3217 case ISD::OR: 3218 case ISD::XOR: 3219 // If the LHS or RHS don't contribute bits to the or, drop them. 3220 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3221 return V.getOperand(1); 3222 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3223 return V.getOperand(0); 3224 break; 3225 case ISD::SRL: 3226 // Only look at single-use SRLs. 3227 if (!V.getNode()->hasOneUse()) 3228 break; 3229 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3230 // See if we can recursively simplify the LHS. 3231 unsigned Amt = RHSC->getZExtValue(); 3232 APInt NewMask = Mask << Amt; 3233 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3234 if (SimplifyLHS.getNode()) { 3235 return DAG.getNode(ISD::SRL, V.getValueType(), 3236 SimplifyLHS, V.getOperand(1)); 3237 } 3238 } 3239 } 3240 return SDValue(); 3241} 3242 3243/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3244/// bits and then truncated to a narrower type and where N is a multiple 3245/// of number of bits of the narrower type, transform it to a narrower load 3246/// from address + N / num of bits of new type. If the result is to be 3247/// extended, also fold the extension to form a extending load. 3248SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3249 unsigned Opc = N->getOpcode(); 3250 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3251 SDValue N0 = N->getOperand(0); 3252 MVT VT = N->getValueType(0); 3253 MVT EVT = N->getValueType(0); 3254 3255 // This transformation isn't valid for vector loads. 3256 if (VT.isVector()) 3257 return SDValue(); 3258 3259 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3260 // extended to VT. 3261 if (Opc == ISD::SIGN_EXTEND_INREG) { 3262 ExtType = ISD::SEXTLOAD; 3263 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3264 if (AfterLegalize && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3265 return SDValue(); 3266 } 3267 3268 unsigned EVTBits = EVT.getSizeInBits(); 3269 unsigned ShAmt = 0; 3270 bool CombineSRL = false; 3271 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3272 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3273 ShAmt = N01->getZExtValue(); 3274 // Is the shift amount a multiple of size of VT? 3275 if ((ShAmt & (EVTBits-1)) == 0) { 3276 N0 = N0.getOperand(0); 3277 if (N0.getValueType().getSizeInBits() <= EVTBits) 3278 return SDValue(); 3279 CombineSRL = true; 3280 } 3281 } 3282 } 3283 3284 // Do not generate loads of non-round integer types since these can 3285 // be expensive (and would be wrong if the type is not byte sized). 3286 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() && 3287 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3288 // Do not change the width of a volatile load. 3289 !cast<LoadSDNode>(N0)->isVolatile()) { 3290 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3291 MVT PtrType = N0.getOperand(1).getValueType(); 3292 // For big endian targets, we need to adjust the offset to the pointer to 3293 // load the correct bytes. 3294 if (TLI.isBigEndian()) { 3295 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3296 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3297 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3298 } 3299 uint64_t PtrOff = ShAmt / 8; 3300 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3301 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3302 DAG.getConstant(PtrOff, PtrType)); 3303 AddToWorkList(NewPtr.getNode()); 3304 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3305 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3306 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3307 LN0->isVolatile(), NewAlign) 3308 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3309 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3310 EVT, LN0->isVolatile(), NewAlign); 3311 AddToWorkList(N); 3312 if (CombineSRL) { 3313 WorkListRemover DeadNodes(*this); 3314 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3315 &DeadNodes); 3316 CombineTo(N->getOperand(0).getNode(), Load); 3317 } else 3318 CombineTo(N0.getNode(), Load, Load.getValue(1)); 3319 if (ShAmt) { 3320 if (Opc == ISD::SIGN_EXTEND_INREG) 3321 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3322 else 3323 return DAG.getNode(Opc, VT, Load); 3324 } 3325 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3326 } 3327 3328 return SDValue(); 3329} 3330 3331 3332SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3333 SDValue N0 = N->getOperand(0); 3334 SDValue N1 = N->getOperand(1); 3335 MVT VT = N->getValueType(0); 3336 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3337 unsigned VTBits = VT.getSizeInBits(); 3338 unsigned EVTBits = EVT.getSizeInBits(); 3339 3340 // fold (sext_in_reg c1) -> c1 3341 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3342 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3343 3344 // If the input is already sign extended, just drop the extension. 3345 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3346 return N0; 3347 3348 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3349 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3350 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3351 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3352 } 3353 3354 // fold (sext_in_reg (sext x)) -> (sext x) 3355 // fold (sext_in_reg (aext x)) -> (sext x) 3356 // if x is small enough. 3357 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3358 SDValue N00 = N0.getOperand(0); 3359 if (N00.getValueType().getSizeInBits() < EVTBits) 3360 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3361 } 3362 3363 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3364 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3365 return DAG.getZeroExtendInReg(N0, EVT); 3366 3367 // fold operands of sext_in_reg based on knowledge that the top bits are not 3368 // demanded. 3369 if (SimplifyDemandedBits(SDValue(N, 0))) 3370 return SDValue(N, 0); 3371 3372 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3373 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3374 SDValue NarrowLoad = ReduceLoadWidth(N); 3375 if (NarrowLoad.getNode()) 3376 return NarrowLoad; 3377 3378 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3379 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3380 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3381 if (N0.getOpcode() == ISD::SRL) { 3382 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3383 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3384 // We can turn this into an SRA iff the input to the SRL is already sign 3385 // extended enough. 3386 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3387 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3388 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3389 } 3390 } 3391 3392 // fold (sext_inreg (extload x)) -> (sextload x) 3393 if (ISD::isEXTLoad(N0.getNode()) && 3394 ISD::isUNINDEXEDLoad(N0.getNode()) && 3395 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3396 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3397 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3398 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3399 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3400 LN0->getBasePtr(), LN0->getSrcValue(), 3401 LN0->getSrcValueOffset(), EVT, 3402 LN0->isVolatile(), 3403 LN0->getAlignment()); 3404 CombineTo(N, ExtLoad); 3405 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3406 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3407 } 3408 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3409 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3410 N0.hasOneUse() && 3411 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3412 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3413 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3414 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3415 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3416 LN0->getBasePtr(), LN0->getSrcValue(), 3417 LN0->getSrcValueOffset(), EVT, 3418 LN0->isVolatile(), 3419 LN0->getAlignment()); 3420 CombineTo(N, ExtLoad); 3421 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3422 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3423 } 3424 return SDValue(); 3425} 3426 3427SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3428 SDValue N0 = N->getOperand(0); 3429 MVT VT = N->getValueType(0); 3430 3431 // noop truncate 3432 if (N0.getValueType() == N->getValueType(0)) 3433 return N0; 3434 // fold (truncate c1) -> c1 3435 if (isa<ConstantSDNode>(N0)) 3436 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3437 // fold (truncate (truncate x)) -> (truncate x) 3438 if (N0.getOpcode() == ISD::TRUNCATE) 3439 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3440 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3441 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3442 N0.getOpcode() == ISD::ANY_EXTEND) { 3443 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3444 // if the source is smaller than the dest, we still need an extend 3445 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3446 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3447 // if the source is larger than the dest, than we just need the truncate 3448 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3449 else 3450 // if the source and dest are the same type, we can drop both the extend 3451 // and the truncate 3452 return N0.getOperand(0); 3453 } 3454 3455 // See if we can simplify the input to this truncate through knowledge that 3456 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3457 // -> trunc y 3458 SDValue Shorter = 3459 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3460 VT.getSizeInBits())); 3461 if (Shorter.getNode()) 3462 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3463 3464 // fold (truncate (load x)) -> (smaller load x) 3465 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3466 return ReduceLoadWidth(N); 3467} 3468 3469static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3470 SDValue Elt = N->getOperand(i); 3471 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3472 return Elt.getNode(); 3473 return Elt.getOperand(Elt.getResNo()).getNode(); 3474} 3475 3476/// CombineConsecutiveLoads - build_pair (load, load) -> load 3477/// if load locations are consecutive. 3478SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3479 assert(N->getOpcode() == ISD::BUILD_PAIR); 3480 3481 SDNode *LD1 = getBuildPairElt(N, 0); 3482 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3483 return SDValue(); 3484 MVT LD1VT = LD1->getValueType(0); 3485 SDNode *LD2 = getBuildPairElt(N, 1); 3486 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3487 if (ISD::isNON_EXTLoad(LD2) && 3488 LD2->hasOneUse() && 3489 // If both are volatile this would reduce the number of volatile loads. 3490 // If one is volatile it might be ok, but play conservative and bail out. 3491 !cast<LoadSDNode>(LD1)->isVolatile() && 3492 !cast<LoadSDNode>(LD2)->isVolatile() && 3493 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3494 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3495 unsigned Align = LD->getAlignment(); 3496 unsigned NewAlign = TLI.getTargetData()-> 3497 getABITypeAlignment(VT.getTypeForMVT()); 3498 if (NewAlign <= Align && 3499 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) 3500 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3501 LD->getSrcValue(), LD->getSrcValueOffset(), 3502 false, Align); 3503 } 3504 return SDValue(); 3505} 3506 3507SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3508 SDValue N0 = N->getOperand(0); 3509 MVT VT = N->getValueType(0); 3510 3511 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3512 // Only do this before legalize, since afterward the target may be depending 3513 // on the bitconvert. 3514 // First check to see if this is all constant. 3515 if (!AfterLegalize && 3516 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3517 VT.isVector()) { 3518 bool isSimple = true; 3519 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3520 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3521 N0.getOperand(i).getOpcode() != ISD::Constant && 3522 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3523 isSimple = false; 3524 break; 3525 } 3526 3527 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3528 assert(!DestEltVT.isVector() && 3529 "Element type of vector ValueType must not be vector!"); 3530 if (isSimple) { 3531 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3532 } 3533 } 3534 3535 // If the input is a constant, let getNode fold it. 3536 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3537 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3538 if (Res.getNode() != N) return Res; 3539 } 3540 3541 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3542 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3543 3544 // fold (conv (load x)) -> (load (conv*)x) 3545 // If the resultant load doesn't need a higher alignment than the original! 3546 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3547 // Do not change the width of a volatile load. 3548 !cast<LoadSDNode>(N0)->isVolatile() && 3549 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) { 3550 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3551 unsigned Align = TLI.getTargetData()-> 3552 getABITypeAlignment(VT.getTypeForMVT()); 3553 unsigned OrigAlign = LN0->getAlignment(); 3554 if (Align <= OrigAlign) { 3555 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3556 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3557 LN0->isVolatile(), OrigAlign); 3558 AddToWorkList(N); 3559 CombineTo(N0.getNode(), 3560 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3561 Load.getValue(1)); 3562 return Load; 3563 } 3564 } 3565 3566 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3567 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3568 // This often reduces constant pool loads. 3569 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3570 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3571 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3572 AddToWorkList(NewConv.getNode()); 3573 3574 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3575 if (N0.getOpcode() == ISD::FNEG) 3576 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3577 assert(N0.getOpcode() == ISD::FABS); 3578 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3579 } 3580 3581 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3582 // Note that we don't handle copysign(x,cst) because this can always be folded 3583 // to an fneg or fabs. 3584 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3585 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3586 VT.isInteger() && !VT.isVector()) { 3587 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3588 SDValue X = DAG.getNode(ISD::BIT_CONVERT, 3589 MVT::getIntegerVT(OrigXWidth), 3590 N0.getOperand(1)); 3591 AddToWorkList(X.getNode()); 3592 3593 // If X has a different width than the result/lhs, sext it or truncate it. 3594 unsigned VTWidth = VT.getSizeInBits(); 3595 if (OrigXWidth < VTWidth) { 3596 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3597 AddToWorkList(X.getNode()); 3598 } else if (OrigXWidth > VTWidth) { 3599 // To get the sign bit in the right place, we have to shift it right 3600 // before truncating. 3601 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3602 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3603 AddToWorkList(X.getNode()); 3604 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3605 AddToWorkList(X.getNode()); 3606 } 3607 3608 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3609 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3610 AddToWorkList(X.getNode()); 3611 3612 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3613 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3614 AddToWorkList(Cst.getNode()); 3615 3616 return DAG.getNode(ISD::OR, VT, X, Cst); 3617 } 3618 3619 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3620 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3621 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3622 if (CombineLD.getNode()) 3623 return CombineLD; 3624 } 3625 3626 return SDValue(); 3627} 3628 3629SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3630 MVT VT = N->getValueType(0); 3631 return CombineConsecutiveLoads(N, VT); 3632} 3633 3634/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3635/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3636/// destination element value type. 3637SDValue DAGCombiner:: 3638ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3639 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3640 3641 // If this is already the right type, we're done. 3642 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3643 3644 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3645 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3646 3647 // If this is a conversion of N elements of one type to N elements of another 3648 // type, convert each element. This handles FP<->INT cases. 3649 if (SrcBitSize == DstBitSize) { 3650 SmallVector<SDValue, 8> Ops; 3651 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3652 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3653 AddToWorkList(Ops.back().getNode()); 3654 } 3655 MVT VT = MVT::getVectorVT(DstEltVT, 3656 BV->getValueType(0).getVectorNumElements()); 3657 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3658 } 3659 3660 // Otherwise, we're growing or shrinking the elements. To avoid having to 3661 // handle annoying details of growing/shrinking FP values, we convert them to 3662 // int first. 3663 if (SrcEltVT.isFloatingPoint()) { 3664 // Convert the input float vector to a int vector where the elements are the 3665 // same sizes. 3666 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3667 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3668 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3669 SrcEltVT = IntVT; 3670 } 3671 3672 // Now we know the input is an integer vector. If the output is a FP type, 3673 // convert to integer first, then to FP of the right size. 3674 if (DstEltVT.isFloatingPoint()) { 3675 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3676 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3677 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3678 3679 // Next, convert to FP elements of the same size. 3680 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3681 } 3682 3683 // Okay, we know the src/dst types are both integers of differing types. 3684 // Handling growing first. 3685 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3686 if (SrcBitSize < DstBitSize) { 3687 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3688 3689 SmallVector<SDValue, 8> Ops; 3690 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3691 i += NumInputsPerOutput) { 3692 bool isLE = TLI.isLittleEndian(); 3693 APInt NewBits = APInt(DstBitSize, 0); 3694 bool EltIsUndef = true; 3695 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3696 // Shift the previously computed bits over. 3697 NewBits <<= SrcBitSize; 3698 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3699 if (Op.getOpcode() == ISD::UNDEF) continue; 3700 EltIsUndef = false; 3701 3702 NewBits |= 3703 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3704 } 3705 3706 if (EltIsUndef) 3707 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3708 else 3709 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3710 } 3711 3712 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3713 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3714 } 3715 3716 // Finally, this must be the case where we are shrinking elements: each input 3717 // turns into multiple outputs. 3718 bool isS2V = ISD::isScalarToVector(BV); 3719 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3720 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3721 SmallVector<SDValue, 8> Ops; 3722 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3723 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3724 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3725 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3726 continue; 3727 } 3728 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3729 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3730 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3731 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3732 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3733 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3734 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3735 OpVal = OpVal.lshr(DstBitSize); 3736 } 3737 3738 // For big endian targets, swap the order of the pieces of each element. 3739 if (TLI.isBigEndian()) 3740 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3741 } 3742 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3743} 3744 3745 3746 3747SDValue DAGCombiner::visitFADD(SDNode *N) { 3748 SDValue N0 = N->getOperand(0); 3749 SDValue N1 = N->getOperand(1); 3750 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3751 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3752 MVT VT = N->getValueType(0); 3753 3754 // fold vector ops 3755 if (VT.isVector()) { 3756 SDValue FoldedVOp = SimplifyVBinOp(N); 3757 if (FoldedVOp.getNode()) return FoldedVOp; 3758 } 3759 3760 // fold (fadd c1, c2) -> c1+c2 3761 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3762 return DAG.getNode(ISD::FADD, VT, N0, N1); 3763 // canonicalize constant to RHS 3764 if (N0CFP && !N1CFP) 3765 return DAG.getNode(ISD::FADD, VT, N1, N0); 3766 // fold (A + (-B)) -> A-B 3767 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3768 return DAG.getNode(ISD::FSUB, VT, N0, 3769 GetNegatedExpression(N1, DAG, AfterLegalize)); 3770 // fold ((-A) + B) -> B-A 3771 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3772 return DAG.getNode(ISD::FSUB, VT, N1, 3773 GetNegatedExpression(N0, DAG, AfterLegalize)); 3774 3775 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3776 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3777 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3778 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3779 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3780 3781 return SDValue(); 3782} 3783 3784SDValue DAGCombiner::visitFSUB(SDNode *N) { 3785 SDValue N0 = N->getOperand(0); 3786 SDValue N1 = N->getOperand(1); 3787 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3788 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3789 MVT VT = N->getValueType(0); 3790 3791 // fold vector ops 3792 if (VT.isVector()) { 3793 SDValue FoldedVOp = SimplifyVBinOp(N); 3794 if (FoldedVOp.getNode()) return FoldedVOp; 3795 } 3796 3797 // fold (fsub c1, c2) -> c1-c2 3798 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3799 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3800 // fold (0-B) -> -B 3801 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3802 if (isNegatibleForFree(N1, AfterLegalize)) 3803 return GetNegatedExpression(N1, DAG, AfterLegalize); 3804 return DAG.getNode(ISD::FNEG, VT, N1); 3805 } 3806 // fold (A-(-B)) -> A+B 3807 if (isNegatibleForFree(N1, AfterLegalize)) 3808 return DAG.getNode(ISD::FADD, VT, N0, 3809 GetNegatedExpression(N1, DAG, AfterLegalize)); 3810 3811 return SDValue(); 3812} 3813 3814SDValue DAGCombiner::visitFMUL(SDNode *N) { 3815 SDValue N0 = N->getOperand(0); 3816 SDValue N1 = N->getOperand(1); 3817 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3818 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3819 MVT VT = N->getValueType(0); 3820 3821 // fold vector ops 3822 if (VT.isVector()) { 3823 SDValue FoldedVOp = SimplifyVBinOp(N); 3824 if (FoldedVOp.getNode()) return FoldedVOp; 3825 } 3826 3827 // fold (fmul c1, c2) -> c1*c2 3828 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3829 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3830 // canonicalize constant to RHS 3831 if (N0CFP && !N1CFP) 3832 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3833 // fold (fmul X, 2.0) -> (fadd X, X) 3834 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3835 return DAG.getNode(ISD::FADD, VT, N0, N0); 3836 // fold (fmul X, -1.0) -> (fneg X) 3837 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3838 return DAG.getNode(ISD::FNEG, VT, N0); 3839 3840 // -X * -Y -> X*Y 3841 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3842 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3843 // Both can be negated for free, check to see if at least one is cheaper 3844 // negated. 3845 if (LHSNeg == 2 || RHSNeg == 2) 3846 return DAG.getNode(ISD::FMUL, VT, 3847 GetNegatedExpression(N0, DAG, AfterLegalize), 3848 GetNegatedExpression(N1, DAG, AfterLegalize)); 3849 } 3850 } 3851 3852 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3853 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3854 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3855 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3856 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3857 3858 return SDValue(); 3859} 3860 3861SDValue DAGCombiner::visitFDIV(SDNode *N) { 3862 SDValue N0 = N->getOperand(0); 3863 SDValue N1 = N->getOperand(1); 3864 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3865 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3866 MVT VT = N->getValueType(0); 3867 3868 // fold vector ops 3869 if (VT.isVector()) { 3870 SDValue FoldedVOp = SimplifyVBinOp(N); 3871 if (FoldedVOp.getNode()) return FoldedVOp; 3872 } 3873 3874 // fold (fdiv c1, c2) -> c1/c2 3875 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3876 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3877 3878 3879 // -X / -Y -> X*Y 3880 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3881 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3882 // Both can be negated for free, check to see if at least one is cheaper 3883 // negated. 3884 if (LHSNeg == 2 || RHSNeg == 2) 3885 return DAG.getNode(ISD::FDIV, VT, 3886 GetNegatedExpression(N0, DAG, AfterLegalize), 3887 GetNegatedExpression(N1, DAG, AfterLegalize)); 3888 } 3889 } 3890 3891 return SDValue(); 3892} 3893 3894SDValue DAGCombiner::visitFREM(SDNode *N) { 3895 SDValue N0 = N->getOperand(0); 3896 SDValue N1 = N->getOperand(1); 3897 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3898 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3899 MVT VT = N->getValueType(0); 3900 3901 // fold (frem c1, c2) -> fmod(c1,c2) 3902 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3903 return DAG.getNode(ISD::FREM, VT, N0, N1); 3904 3905 return SDValue(); 3906} 3907 3908SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3909 SDValue N0 = N->getOperand(0); 3910 SDValue N1 = N->getOperand(1); 3911 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3912 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3913 MVT VT = N->getValueType(0); 3914 3915 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3916 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3917 3918 if (N1CFP) { 3919 const APFloat& V = N1CFP->getValueAPF(); 3920 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3921 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3922 if (!V.isNegative()) 3923 return DAG.getNode(ISD::FABS, VT, N0); 3924 else 3925 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3926 } 3927 3928 // copysign(fabs(x), y) -> copysign(x, y) 3929 // copysign(fneg(x), y) -> copysign(x, y) 3930 // copysign(copysign(x,z), y) -> copysign(x, y) 3931 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3932 N0.getOpcode() == ISD::FCOPYSIGN) 3933 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3934 3935 // copysign(x, abs(y)) -> abs(x) 3936 if (N1.getOpcode() == ISD::FABS) 3937 return DAG.getNode(ISD::FABS, VT, N0); 3938 3939 // copysign(x, copysign(y,z)) -> copysign(x, z) 3940 if (N1.getOpcode() == ISD::FCOPYSIGN) 3941 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3942 3943 // copysign(x, fp_extend(y)) -> copysign(x, y) 3944 // copysign(x, fp_round(y)) -> copysign(x, y) 3945 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3946 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3947 3948 return SDValue(); 3949} 3950 3951 3952 3953SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3954 SDValue N0 = N->getOperand(0); 3955 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3956 MVT VT = N->getValueType(0); 3957 MVT OpVT = N0.getValueType(); 3958 3959 // fold (sint_to_fp c1) -> c1fp 3960 if (N0C && OpVT != MVT::ppcf128) 3961 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3962 3963 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 3964 // but UINT_TO_FP is legal on this target, try to convert. 3965 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && 3966 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { 3967 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 3968 if (DAG.SignBitIsZero(N0)) 3969 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3970 } 3971 3972 3973 return SDValue(); 3974} 3975 3976SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3977 SDValue N0 = N->getOperand(0); 3978 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3979 MVT VT = N->getValueType(0); 3980 MVT OpVT = N0.getValueType(); 3981 3982 // fold (uint_to_fp c1) -> c1fp 3983 if (N0C && OpVT != MVT::ppcf128) 3984 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3985 3986 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 3987 // but SINT_TO_FP is legal on this target, try to convert. 3988 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && 3989 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { 3990 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 3991 if (DAG.SignBitIsZero(N0)) 3992 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3993 } 3994 3995 return SDValue(); 3996} 3997 3998SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3999 SDValue N0 = N->getOperand(0); 4000 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4001 MVT VT = N->getValueType(0); 4002 4003 // fold (fp_to_sint c1fp) -> c1 4004 if (N0CFP) 4005 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 4006 return SDValue(); 4007} 4008 4009SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4010 SDValue N0 = N->getOperand(0); 4011 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4012 MVT VT = N->getValueType(0); 4013 4014 // fold (fp_to_uint c1fp) -> c1 4015 if (N0CFP && VT != MVT::ppcf128) 4016 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 4017 return SDValue(); 4018} 4019 4020SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4021 SDValue N0 = N->getOperand(0); 4022 SDValue N1 = N->getOperand(1); 4023 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4024 MVT VT = N->getValueType(0); 4025 4026 // fold (fp_round c1fp) -> c1fp 4027 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4028 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 4029 4030 // fold (fp_round (fp_extend x)) -> x 4031 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4032 return N0.getOperand(0); 4033 4034 // fold (fp_round (fp_round x)) -> (fp_round x) 4035 if (N0.getOpcode() == ISD::FP_ROUND) { 4036 // This is a value preserving truncation if both round's are. 4037 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4038 N0.getNode()->getConstantOperandVal(1) == 1; 4039 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 4040 DAG.getIntPtrConstant(IsTrunc)); 4041 } 4042 4043 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4044 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4045 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 4046 AddToWorkList(Tmp.getNode()); 4047 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 4048 } 4049 4050 return SDValue(); 4051} 4052 4053SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4054 SDValue N0 = N->getOperand(0); 4055 MVT VT = N->getValueType(0); 4056 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4057 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4058 4059 // fold (fp_round_inreg c1fp) -> c1fp 4060 if (N0CFP) { 4061 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4062 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4063 } 4064 return SDValue(); 4065} 4066 4067SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4068 SDValue N0 = N->getOperand(0); 4069 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4070 MVT VT = N->getValueType(0); 4071 4072 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4073 if (N->hasOneUse() && 4074 N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND) 4075 return SDValue(); 4076 4077 // fold (fp_extend c1fp) -> c1fp 4078 if (N0CFP && VT != MVT::ppcf128) 4079 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4080 4081 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4082 // value of X. 4083 if (N0.getOpcode() == ISD::FP_ROUND 4084 && N0.getNode()->getConstantOperandVal(1) == 1) { 4085 SDValue In = N0.getOperand(0); 4086 if (In.getValueType() == VT) return In; 4087 if (VT.bitsLT(In.getValueType())) 4088 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4089 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4090 } 4091 4092 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4093 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4094 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 4095 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4096 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4097 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4098 LN0->getBasePtr(), LN0->getSrcValue(), 4099 LN0->getSrcValueOffset(), 4100 N0.getValueType(), 4101 LN0->isVolatile(), 4102 LN0->getAlignment()); 4103 CombineTo(N, ExtLoad); 4104 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4105 ExtLoad, DAG.getIntPtrConstant(1)), 4106 ExtLoad.getValue(1)); 4107 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4108 } 4109 4110 return SDValue(); 4111} 4112 4113SDValue DAGCombiner::visitFNEG(SDNode *N) { 4114 SDValue N0 = N->getOperand(0); 4115 4116 if (isNegatibleForFree(N0, AfterLegalize)) 4117 return GetNegatedExpression(N0, DAG, AfterLegalize); 4118 4119 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4120 // constant pool values. 4121 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4122 N0.getOperand(0).getValueType().isInteger() && 4123 !N0.getOperand(0).getValueType().isVector()) { 4124 SDValue Int = N0.getOperand(0); 4125 MVT IntVT = Int.getValueType(); 4126 if (IntVT.isInteger() && !IntVT.isVector()) { 4127 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4128 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4129 AddToWorkList(Int.getNode()); 4130 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4131 } 4132 } 4133 4134 return SDValue(); 4135} 4136 4137SDValue DAGCombiner::visitFABS(SDNode *N) { 4138 SDValue N0 = N->getOperand(0); 4139 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4140 MVT VT = N->getValueType(0); 4141 4142 // fold (fabs c1) -> fabs(c1) 4143 if (N0CFP && VT != MVT::ppcf128) 4144 return DAG.getNode(ISD::FABS, VT, N0); 4145 // fold (fabs (fabs x)) -> (fabs x) 4146 if (N0.getOpcode() == ISD::FABS) 4147 return N->getOperand(0); 4148 // fold (fabs (fneg x)) -> (fabs x) 4149 // fold (fabs (fcopysign x, y)) -> (fabs x) 4150 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4151 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4152 4153 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4154 // constant pool values. 4155 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4156 N0.getOperand(0).getValueType().isInteger() && 4157 !N0.getOperand(0).getValueType().isVector()) { 4158 SDValue Int = N0.getOperand(0); 4159 MVT IntVT = Int.getValueType(); 4160 if (IntVT.isInteger() && !IntVT.isVector()) { 4161 Int = DAG.getNode(ISD::AND, IntVT, Int, 4162 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4163 AddToWorkList(Int.getNode()); 4164 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4165 } 4166 } 4167 4168 return SDValue(); 4169} 4170 4171SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4172 SDValue Chain = N->getOperand(0); 4173 SDValue N1 = N->getOperand(1); 4174 SDValue N2 = N->getOperand(2); 4175 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4176 4177 // never taken branch, fold to chain 4178 if (N1C && N1C->isNullValue()) 4179 return Chain; 4180 // unconditional branch 4181 if (N1C && N1C->getAPIntValue() == 1) 4182 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4183 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4184 // on the target. 4185 if (N1.getOpcode() == ISD::SETCC && 4186 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4187 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4188 N1.getOperand(0), N1.getOperand(1), N2); 4189 } 4190 return SDValue(); 4191} 4192 4193// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4194// 4195SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4196 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4197 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4198 4199 // Use SimplifySetCC to simplify SETCC's. 4200 SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 4201 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4202 4203 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4204 4205 // fold br_cc true, dest -> br dest (unconditional branch) 4206 if (SCCC && !SCCC->isNullValue()) 4207 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4208 N->getOperand(4)); 4209 // fold br_cc false, dest -> unconditional fall through 4210 if (SCCC && SCCC->isNullValue()) 4211 return N->getOperand(0); 4212 4213 // fold to a simpler setcc 4214 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4215 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4216 Simp.getOperand(2), Simp.getOperand(0), 4217 Simp.getOperand(1), N->getOperand(4)); 4218 return SDValue(); 4219} 4220 4221 4222/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4223/// pre-indexed load / store when the base pointer is an add or subtract 4224/// and it has other uses besides the load / store. After the 4225/// transformation, the new indexed load / store has effectively folded 4226/// the add / subtract in and all of its other uses are redirected to the 4227/// new load / store. 4228bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4229 if (!AfterLegalize) 4230 return false; 4231 4232 bool isLoad = true; 4233 SDValue Ptr; 4234 MVT VT; 4235 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4236 if (LD->isIndexed()) 4237 return false; 4238 VT = LD->getMemoryVT(); 4239 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4240 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4241 return false; 4242 Ptr = LD->getBasePtr(); 4243 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4244 if (ST->isIndexed()) 4245 return false; 4246 VT = ST->getMemoryVT(); 4247 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4248 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4249 return false; 4250 Ptr = ST->getBasePtr(); 4251 isLoad = false; 4252 } else 4253 return false; 4254 4255 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4256 // out. There is no reason to make this a preinc/predec. 4257 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4258 Ptr.getNode()->hasOneUse()) 4259 return false; 4260 4261 // Ask the target to do addressing mode selection. 4262 SDValue BasePtr; 4263 SDValue Offset; 4264 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4265 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4266 return false; 4267 // Don't create a indexed load / store with zero offset. 4268 if (isa<ConstantSDNode>(Offset) && 4269 cast<ConstantSDNode>(Offset)->isNullValue()) 4270 return false; 4271 4272 // Try turning it into a pre-indexed load / store except when: 4273 // 1) The new base ptr is a frame index. 4274 // 2) If N is a store and the new base ptr is either the same as or is a 4275 // predecessor of the value being stored. 4276 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4277 // that would create a cycle. 4278 // 4) All uses are load / store ops that use it as old base ptr. 4279 4280 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4281 // (plus the implicit offset) to a register to preinc anyway. 4282 if (isa<FrameIndexSDNode>(BasePtr)) 4283 return false; 4284 4285 // Check #2. 4286 if (!isLoad) { 4287 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4288 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4289 return false; 4290 } 4291 4292 // Now check for #3 and #4. 4293 bool RealUse = false; 4294 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4295 E = Ptr.getNode()->use_end(); I != E; ++I) { 4296 SDNode *Use = *I; 4297 if (Use == N) 4298 continue; 4299 if (Use->isPredecessorOf(N)) 4300 return false; 4301 4302 if (!((Use->getOpcode() == ISD::LOAD && 4303 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4304 (Use->getOpcode() == ISD::STORE && 4305 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4306 RealUse = true; 4307 } 4308 if (!RealUse) 4309 return false; 4310 4311 SDValue Result; 4312 if (isLoad) 4313 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4314 else 4315 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4316 ++PreIndexedNodes; 4317 ++NodesCombined; 4318 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4319 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4320 DOUT << '\n'; 4321 WorkListRemover DeadNodes(*this); 4322 if (isLoad) { 4323 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4324 &DeadNodes); 4325 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4326 &DeadNodes); 4327 } else { 4328 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4329 &DeadNodes); 4330 } 4331 4332 // Finally, since the node is now dead, remove it from the graph. 4333 DAG.DeleteNode(N); 4334 4335 // Replace the uses of Ptr with uses of the updated base value. 4336 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4337 &DeadNodes); 4338 removeFromWorkList(Ptr.getNode()); 4339 DAG.DeleteNode(Ptr.getNode()); 4340 4341 return true; 4342} 4343 4344/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4345/// add / sub of the base pointer node into a post-indexed load / store. 4346/// The transformation folded the add / subtract into the new indexed 4347/// load / store effectively and all of its uses are redirected to the 4348/// new load / store. 4349bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4350 if (!AfterLegalize) 4351 return false; 4352 4353 bool isLoad = true; 4354 SDValue Ptr; 4355 MVT VT; 4356 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4357 if (LD->isIndexed()) 4358 return false; 4359 VT = LD->getMemoryVT(); 4360 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4361 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4362 return false; 4363 Ptr = LD->getBasePtr(); 4364 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4365 if (ST->isIndexed()) 4366 return false; 4367 VT = ST->getMemoryVT(); 4368 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4369 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4370 return false; 4371 Ptr = ST->getBasePtr(); 4372 isLoad = false; 4373 } else 4374 return false; 4375 4376 if (Ptr.getNode()->hasOneUse()) 4377 return false; 4378 4379 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4380 E = Ptr.getNode()->use_end(); I != E; ++I) { 4381 SDNode *Op = *I; 4382 if (Op == N || 4383 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4384 continue; 4385 4386 SDValue BasePtr; 4387 SDValue Offset; 4388 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4389 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4390 if (Ptr == Offset) 4391 std::swap(BasePtr, Offset); 4392 if (Ptr != BasePtr) 4393 continue; 4394 // Don't create a indexed load / store with zero offset. 4395 if (isa<ConstantSDNode>(Offset) && 4396 cast<ConstantSDNode>(Offset)->isNullValue()) 4397 continue; 4398 4399 // Try turning it into a post-indexed load / store except when 4400 // 1) All uses are load / store ops that use it as base ptr. 4401 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4402 // nor a successor of N. Otherwise, if Op is folded that would 4403 // create a cycle. 4404 4405 // Check for #1. 4406 bool TryNext = false; 4407 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4408 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4409 SDNode *Use = *II; 4410 if (Use == Ptr.getNode()) 4411 continue; 4412 4413 // If all the uses are load / store addresses, then don't do the 4414 // transformation. 4415 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4416 bool RealUse = false; 4417 for (SDNode::use_iterator III = Use->use_begin(), 4418 EEE = Use->use_end(); III != EEE; ++III) { 4419 SDNode *UseUse = *III; 4420 if (!((UseUse->getOpcode() == ISD::LOAD && 4421 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4422 (UseUse->getOpcode() == ISD::STORE && 4423 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4424 RealUse = true; 4425 } 4426 4427 if (!RealUse) { 4428 TryNext = true; 4429 break; 4430 } 4431 } 4432 } 4433 if (TryNext) 4434 continue; 4435 4436 // Check for #2 4437 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4438 SDValue Result = isLoad 4439 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4440 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4441 ++PostIndexedNodes; 4442 ++NodesCombined; 4443 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4444 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4445 DOUT << '\n'; 4446 WorkListRemover DeadNodes(*this); 4447 if (isLoad) { 4448 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4449 &DeadNodes); 4450 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4451 &DeadNodes); 4452 } else { 4453 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4454 &DeadNodes); 4455 } 4456 4457 // Finally, since the node is now dead, remove it from the graph. 4458 DAG.DeleteNode(N); 4459 4460 // Replace the uses of Use with uses of the updated base value. 4461 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4462 Result.getValue(isLoad ? 1 : 0), 4463 &DeadNodes); 4464 removeFromWorkList(Op); 4465 DAG.DeleteNode(Op); 4466 return true; 4467 } 4468 } 4469 } 4470 return false; 4471} 4472 4473/// InferAlignment - If we can infer some alignment information from this 4474/// pointer, return it. 4475static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4476 // If this is a direct reference to a stack slot, use information about the 4477 // stack slot's alignment. 4478 int FrameIdx = 1 << 31; 4479 int64_t FrameOffset = 0; 4480 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4481 FrameIdx = FI->getIndex(); 4482 } else if (Ptr.getOpcode() == ISD::ADD && 4483 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4484 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4485 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4486 FrameOffset = Ptr.getConstantOperandVal(1); 4487 } 4488 4489 if (FrameIdx != (1 << 31)) { 4490 // FIXME: Handle FI+CST. 4491 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4492 if (MFI.isFixedObjectIndex(FrameIdx)) { 4493 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4494 4495 // The alignment of the frame index can be determined from its offset from 4496 // the incoming frame position. If the frame object is at offset 32 and 4497 // the stack is guaranteed to be 16-byte aligned, then we know that the 4498 // object is 16-byte aligned. 4499 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4500 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4501 4502 // Finally, the frame object itself may have a known alignment. Factor 4503 // the alignment + offset into a new alignment. For example, if we know 4504 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4505 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4506 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4507 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4508 FrameOffset); 4509 return std::max(Align, FIInfoAlign); 4510 } 4511 } 4512 4513 return 0; 4514} 4515 4516SDValue DAGCombiner::visitLOAD(SDNode *N) { 4517 LoadSDNode *LD = cast<LoadSDNode>(N); 4518 SDValue Chain = LD->getChain(); 4519 SDValue Ptr = LD->getBasePtr(); 4520 4521 // Try to infer better alignment information than the load already has. 4522 if (!Fast && LD->isUnindexed()) { 4523 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4524 if (Align > LD->getAlignment()) 4525 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4526 Chain, Ptr, LD->getSrcValue(), 4527 LD->getSrcValueOffset(), LD->getMemoryVT(), 4528 LD->isVolatile(), Align); 4529 } 4530 } 4531 4532 4533 // If load is not volatile and there are no uses of the loaded value (and 4534 // the updated indexed value in case of indexed loads), change uses of the 4535 // chain value into uses of the chain input (i.e. delete the dead load). 4536 if (!LD->isVolatile()) { 4537 if (N->getValueType(1) == MVT::Other) { 4538 // Unindexed loads. 4539 if (N->hasNUsesOfValue(0, 0)) { 4540 // It's not safe to use the two value CombineTo variant here. e.g. 4541 // v1, chain2 = load chain1, loc 4542 // v2, chain3 = load chain2, loc 4543 // v3 = add v2, c 4544 // Now we replace use of chain2 with chain1. This makes the second load 4545 // isomorphic to the one we are deleting, and thus makes this load live. 4546 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4547 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4548 DOUT << "\n"; 4549 WorkListRemover DeadNodes(*this); 4550 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4551 if (N->use_empty()) { 4552 removeFromWorkList(N); 4553 DAG.DeleteNode(N); 4554 } 4555 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4556 } 4557 } else { 4558 // Indexed loads. 4559 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4560 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4561 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4562 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4563 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4564 DOUT << " and 2 other values\n"; 4565 WorkListRemover DeadNodes(*this); 4566 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4567 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4568 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4569 &DeadNodes); 4570 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4571 removeFromWorkList(N); 4572 DAG.DeleteNode(N); 4573 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4574 } 4575 } 4576 } 4577 4578 // If this load is directly stored, replace the load value with the stored 4579 // value. 4580 // TODO: Handle store large -> read small portion. 4581 // TODO: Handle TRUNCSTORE/LOADEXT 4582 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4583 !LD->isVolatile()) { 4584 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4585 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4586 if (PrevST->getBasePtr() == Ptr && 4587 PrevST->getValue().getValueType() == N->getValueType(0)) 4588 return CombineTo(N, Chain.getOperand(1), Chain); 4589 } 4590 } 4591 4592 if (CombinerAA) { 4593 // Walk up chain skipping non-aliasing memory nodes. 4594 SDValue BetterChain = FindBetterChain(N, Chain); 4595 4596 // If there is a better chain. 4597 if (Chain != BetterChain) { 4598 SDValue ReplLoad; 4599 4600 // Replace the chain to void dependency. 4601 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4602 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4603 LD->getSrcValue(), LD->getSrcValueOffset(), 4604 LD->isVolatile(), LD->getAlignment()); 4605 } else { 4606 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4607 LD->getValueType(0), 4608 BetterChain, Ptr, LD->getSrcValue(), 4609 LD->getSrcValueOffset(), 4610 LD->getMemoryVT(), 4611 LD->isVolatile(), 4612 LD->getAlignment()); 4613 } 4614 4615 // Create token factor to keep old chain connected. 4616 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4617 Chain, ReplLoad.getValue(1)); 4618 4619 // Replace uses with load result and token factor. Don't add users 4620 // to work list. 4621 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4622 } 4623 } 4624 4625 // Try transforming N to an indexed load. 4626 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4627 return SDValue(N, 0); 4628 4629 return SDValue(); 4630} 4631 4632 4633SDValue DAGCombiner::visitSTORE(SDNode *N) { 4634 StoreSDNode *ST = cast<StoreSDNode>(N); 4635 SDValue Chain = ST->getChain(); 4636 SDValue Value = ST->getValue(); 4637 SDValue Ptr = ST->getBasePtr(); 4638 4639 // Try to infer better alignment information than the store already has. 4640 if (!Fast && ST->isUnindexed()) { 4641 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4642 if (Align > ST->getAlignment()) 4643 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4644 ST->getSrcValueOffset(), ST->getMemoryVT(), 4645 ST->isVolatile(), Align); 4646 } 4647 } 4648 4649 // If this is a store of a bit convert, store the input value if the 4650 // resultant store does not need a higher alignment than the original. 4651 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4652 ST->isUnindexed()) { 4653 unsigned Align = ST->getAlignment(); 4654 MVT SVT = Value.getOperand(0).getValueType(); 4655 unsigned OrigAlign = TLI.getTargetData()-> 4656 getABITypeAlignment(SVT.getTypeForMVT()); 4657 if (Align <= OrigAlign && 4658 ((!AfterLegalize && !ST->isVolatile()) || 4659 TLI.isOperationLegal(ISD::STORE, SVT))) 4660 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4661 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4662 } 4663 4664 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4665 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4666 // NOTE: If the original store is volatile, this transform must not increase 4667 // the number of stores. For example, on x86-32 an f64 can be stored in one 4668 // processor operation but an i64 (which is not legal) requires two. So the 4669 // transform should not be done in this case. 4670 if (Value.getOpcode() != ISD::TargetConstantFP) { 4671 SDValue Tmp; 4672 switch (CFP->getValueType(0).getSimpleVT()) { 4673 default: assert(0 && "Unknown FP type"); 4674 case MVT::f80: // We don't do this for these yet. 4675 case MVT::f128: 4676 case MVT::ppcf128: 4677 break; 4678 case MVT::f32: 4679 if ((!AfterLegalize && !ST->isVolatile()) || 4680 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4681 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4682 bitcastToAPInt().getZExtValue(), MVT::i32); 4683 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4684 ST->getSrcValueOffset(), ST->isVolatile(), 4685 ST->getAlignment()); 4686 } 4687 break; 4688 case MVT::f64: 4689 if ((!AfterLegalize && !ST->isVolatile()) || 4690 TLI.isOperationLegal(ISD::STORE, MVT::i64)) { 4691 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4692 getZExtValue(), MVT::i64); 4693 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4694 ST->getSrcValueOffset(), ST->isVolatile(), 4695 ST->getAlignment()); 4696 } else if (!ST->isVolatile() && 4697 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4698 // Many FP stores are not made apparent until after legalize, e.g. for 4699 // argument passing. Since this is so common, custom legalize the 4700 // 64-bit integer store into two 32-bit stores. 4701 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4702 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4703 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4704 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4705 4706 int SVOffset = ST->getSrcValueOffset(); 4707 unsigned Alignment = ST->getAlignment(); 4708 bool isVolatile = ST->isVolatile(); 4709 4710 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4711 ST->getSrcValueOffset(), 4712 isVolatile, ST->getAlignment()); 4713 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4714 DAG.getConstant(4, Ptr.getValueType())); 4715 SVOffset += 4; 4716 Alignment = MinAlign(Alignment, 4U); 4717 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4718 SVOffset, isVolatile, Alignment); 4719 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4720 } 4721 break; 4722 } 4723 } 4724 } 4725 4726 if (CombinerAA) { 4727 // Walk up chain skipping non-aliasing memory nodes. 4728 SDValue BetterChain = FindBetterChain(N, Chain); 4729 4730 // If there is a better chain. 4731 if (Chain != BetterChain) { 4732 // Replace the chain to avoid dependency. 4733 SDValue ReplStore; 4734 if (ST->isTruncatingStore()) { 4735 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4736 ST->getSrcValue(),ST->getSrcValueOffset(), 4737 ST->getMemoryVT(), 4738 ST->isVolatile(), ST->getAlignment()); 4739 } else { 4740 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4741 ST->getSrcValue(), ST->getSrcValueOffset(), 4742 ST->isVolatile(), ST->getAlignment()); 4743 } 4744 4745 // Create token to keep both nodes around. 4746 SDValue Token = 4747 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4748 4749 // Don't add users to work list. 4750 return CombineTo(N, Token, false); 4751 } 4752 } 4753 4754 // Try transforming N to an indexed store. 4755 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4756 return SDValue(N, 0); 4757 4758 // FIXME: is there such a thing as a truncating indexed store? 4759 if (ST->isTruncatingStore() && ST->isUnindexed() && 4760 Value.getValueType().isInteger()) { 4761 // See if we can simplify the input to this truncstore with knowledge that 4762 // only the low bits are being used. For example: 4763 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4764 SDValue Shorter = 4765 GetDemandedBits(Value, 4766 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4767 ST->getMemoryVT().getSizeInBits())); 4768 AddToWorkList(Value.getNode()); 4769 if (Shorter.getNode()) 4770 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4771 ST->getSrcValueOffset(), ST->getMemoryVT(), 4772 ST->isVolatile(), ST->getAlignment()); 4773 4774 // Otherwise, see if we can simplify the operation with 4775 // SimplifyDemandedBits, which only works if the value has a single use. 4776 if (SimplifyDemandedBits(Value, 4777 APInt::getLowBitsSet( 4778 Value.getValueSizeInBits(), 4779 ST->getMemoryVT().getSizeInBits()))) 4780 return SDValue(N, 0); 4781 } 4782 4783 // If this is a load followed by a store to the same location, then the store 4784 // is dead/noop. 4785 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4786 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4787 ST->isUnindexed() && !ST->isVolatile() && 4788 // There can't be any side effects between the load and store, such as 4789 // a call or store. 4790 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4791 // The store is dead, remove it. 4792 return Chain; 4793 } 4794 } 4795 4796 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4797 // truncating store. We can do this even if this is already a truncstore. 4798 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4799 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4800 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4801 ST->getMemoryVT())) { 4802 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4803 ST->getSrcValueOffset(), ST->getMemoryVT(), 4804 ST->isVolatile(), ST->getAlignment()); 4805 } 4806 4807 return SDValue(); 4808} 4809 4810SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4811 SDValue InVec = N->getOperand(0); 4812 SDValue InVal = N->getOperand(1); 4813 SDValue EltNo = N->getOperand(2); 4814 4815 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4816 // vector with the inserted element. 4817 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4818 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4819 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 4820 InVec.getNode()->op_end()); 4821 if (Elt < Ops.size()) 4822 Ops[Elt] = InVal; 4823 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4824 &Ops[0], Ops.size()); 4825 } 4826 4827 return SDValue(); 4828} 4829 4830SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4831 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4832 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4833 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4834 4835 // Perform only after legalization to ensure build_vector / vector_shuffle 4836 // optimizations have already been done. 4837 if (!AfterLegalize) return SDValue(); 4838 4839 SDValue InVec = N->getOperand(0); 4840 SDValue EltNo = N->getOperand(1); 4841 4842 if (isa<ConstantSDNode>(EltNo)) { 4843 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4844 bool NewLoad = false; 4845 MVT VT = InVec.getValueType(); 4846 MVT EVT = VT.getVectorElementType(); 4847 MVT LVT = EVT; 4848 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4849 MVT BCVT = InVec.getOperand(0).getValueType(); 4850 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4851 return SDValue(); 4852 InVec = InVec.getOperand(0); 4853 EVT = BCVT.getVectorElementType(); 4854 NewLoad = true; 4855 } 4856 4857 LoadSDNode *LN0 = NULL; 4858 if (ISD::isNormalLoad(InVec.getNode())) 4859 LN0 = cast<LoadSDNode>(InVec); 4860 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4861 InVec.getOperand(0).getValueType() == EVT && 4862 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 4863 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4864 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4865 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4866 // => 4867 // (load $addr+1*size) 4868 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4869 getOperand(Elt))->getZExtValue(); 4870 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4871 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4872 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4873 InVec = InVec.getOperand(0); 4874 if (ISD::isNormalLoad(InVec.getNode())) { 4875 LN0 = cast<LoadSDNode>(InVec); 4876 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4877 } 4878 } 4879 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4880 return SDValue(); 4881 4882 unsigned Align = LN0->getAlignment(); 4883 if (NewLoad) { 4884 // Check the resultant load doesn't need a higher alignment than the 4885 // original load. 4886 unsigned NewAlign = TLI.getTargetData()-> 4887 getABITypeAlignment(LVT.getTypeForMVT()); 4888 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) 4889 return SDValue(); 4890 Align = NewAlign; 4891 } 4892 4893 SDValue NewPtr = LN0->getBasePtr(); 4894 if (Elt) { 4895 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4896 MVT PtrType = NewPtr.getValueType(); 4897 if (TLI.isBigEndian()) 4898 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4899 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4900 DAG.getConstant(PtrOff, PtrType)); 4901 } 4902 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4903 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4904 LN0->isVolatile(), Align); 4905 } 4906 return SDValue(); 4907} 4908 4909 4910SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4911 unsigned NumInScalars = N->getNumOperands(); 4912 MVT VT = N->getValueType(0); 4913 unsigned NumElts = VT.getVectorNumElements(); 4914 MVT EltType = VT.getVectorElementType(); 4915 4916 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4917 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4918 // at most two distinct vectors, turn this into a shuffle node. 4919 SDValue VecIn1, VecIn2; 4920 for (unsigned i = 0; i != NumInScalars; ++i) { 4921 // Ignore undef inputs. 4922 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4923 4924 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4925 // constant index, bail out. 4926 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4927 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4928 VecIn1 = VecIn2 = SDValue(0, 0); 4929 break; 4930 } 4931 4932 // If the input vector type disagrees with the result of the build_vector, 4933 // we can't make a shuffle. 4934 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 4935 if (ExtractedFromVec.getValueType() != VT) { 4936 VecIn1 = VecIn2 = SDValue(0, 0); 4937 break; 4938 } 4939 4940 // Otherwise, remember this. We allow up to two distinct input vectors. 4941 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4942 continue; 4943 4944 if (VecIn1.getNode() == 0) { 4945 VecIn1 = ExtractedFromVec; 4946 } else if (VecIn2.getNode() == 0) { 4947 VecIn2 = ExtractedFromVec; 4948 } else { 4949 // Too many inputs. 4950 VecIn1 = VecIn2 = SDValue(0, 0); 4951 break; 4952 } 4953 } 4954 4955 // If everything is good, we can make a shuffle operation. 4956 if (VecIn1.getNode()) { 4957 SmallVector<SDValue, 8> BuildVecIndices; 4958 for (unsigned i = 0; i != NumInScalars; ++i) { 4959 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4960 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4961 continue; 4962 } 4963 4964 SDValue Extract = N->getOperand(i); 4965 4966 // If extracting from the first vector, just use the index directly. 4967 if (Extract.getOperand(0) == VecIn1) { 4968 BuildVecIndices.push_back(Extract.getOperand(1)); 4969 continue; 4970 } 4971 4972 // Otherwise, use InIdx + VecSize 4973 unsigned Idx = 4974 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 4975 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4976 } 4977 4978 // Add count and size info. 4979 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 4980 4981 // Return the new VECTOR_SHUFFLE node. 4982 SDValue Ops[5]; 4983 Ops[0] = VecIn1; 4984 if (VecIn2.getNode()) { 4985 Ops[1] = VecIn2; 4986 } else { 4987 // Use an undef build_vector as input for the second operand. 4988 std::vector<SDValue> UnOps(NumInScalars, 4989 DAG.getNode(ISD::UNDEF, 4990 EltType)); 4991 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4992 &UnOps[0], UnOps.size()); 4993 AddToWorkList(Ops[1].getNode()); 4994 } 4995 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4996 &BuildVecIndices[0], BuildVecIndices.size()); 4997 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4998 } 4999 5000 return SDValue(); 5001} 5002 5003SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5004 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5005 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5006 // inputs come from at most two distinct vectors, turn this into a shuffle 5007 // node. 5008 5009 // If we only have one input vector, we don't need to do any concatenation. 5010 if (N->getNumOperands() == 1) { 5011 return N->getOperand(0); 5012 } 5013 5014 return SDValue(); 5015} 5016 5017SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5018 SDValue ShufMask = N->getOperand(2); 5019 unsigned NumElts = ShufMask.getNumOperands(); 5020 5021 SDValue N0 = N->getOperand(0); 5022 SDValue N1 = N->getOperand(1); 5023 5024 assert(N0.getValueType().getVectorNumElements() == NumElts && 5025 "Vector shuffle must be normalized in DAG"); 5026 5027 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5028 bool isIdentity = true; 5029 for (unsigned i = 0; i != NumElts; ++i) { 5030 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5031 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5032 isIdentity = false; 5033 break; 5034 } 5035 } 5036 if (isIdentity) return N->getOperand(0); 5037 5038 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5039 isIdentity = true; 5040 for (unsigned i = 0; i != NumElts; ++i) { 5041 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5042 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5043 i+NumElts) { 5044 isIdentity = false; 5045 break; 5046 } 5047 } 5048 if (isIdentity) return N->getOperand(1); 5049 5050 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5051 // needed at all. 5052 bool isUnary = true; 5053 bool isSplat = true; 5054 int VecNum = -1; 5055 unsigned BaseIdx = 0; 5056 for (unsigned i = 0; i != NumElts; ++i) 5057 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5058 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5059 int V = (Idx < NumElts) ? 0 : 1; 5060 if (VecNum == -1) { 5061 VecNum = V; 5062 BaseIdx = Idx; 5063 } else { 5064 if (BaseIdx != Idx) 5065 isSplat = false; 5066 if (VecNum != V) { 5067 isUnary = false; 5068 break; 5069 } 5070 } 5071 } 5072 5073 // Normalize unary shuffle so the RHS is undef. 5074 if (isUnary && VecNum == 1) 5075 std::swap(N0, N1); 5076 5077 // If it is a splat, check if the argument vector is a build_vector with 5078 // all scalar elements the same. 5079 if (isSplat) { 5080 SDNode *V = N0.getNode(); 5081 5082 // If this is a bit convert that changes the element type of the vector but 5083 // not the number of vector elements, look through it. Be careful not to 5084 // look though conversions that change things like v4f32 to v2f64. 5085 if (V->getOpcode() == ISD::BIT_CONVERT) { 5086 SDValue ConvInput = V->getOperand(0); 5087 if (ConvInput.getValueType().isVector() && 5088 ConvInput.getValueType().getVectorNumElements() == NumElts) 5089 V = ConvInput.getNode(); 5090 } 5091 5092 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5093 unsigned NumElems = V->getNumOperands(); 5094 if (NumElems > BaseIdx) { 5095 SDValue Base; 5096 bool AllSame = true; 5097 for (unsigned i = 0; i != NumElems; ++i) { 5098 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5099 Base = V->getOperand(i); 5100 break; 5101 } 5102 } 5103 // Splat of <u, u, u, u>, return <u, u, u, u> 5104 if (!Base.getNode()) 5105 return N0; 5106 for (unsigned i = 0; i != NumElems; ++i) { 5107 if (V->getOperand(i) != Base) { 5108 AllSame = false; 5109 break; 5110 } 5111 } 5112 // Splat of <x, x, x, x>, return <x, x, x, x> 5113 if (AllSame) 5114 return N0; 5115 } 5116 } 5117 } 5118 5119 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5120 // into an undef. 5121 if (isUnary || N0 == N1) { 5122 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5123 // first operand. 5124 SmallVector<SDValue, 8> MappedOps; 5125 for (unsigned i = 0; i != NumElts; ++i) { 5126 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5127 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5128 NumElts) { 5129 MappedOps.push_back(ShufMask.getOperand(i)); 5130 } else { 5131 unsigned NewIdx = 5132 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5133 NumElts; 5134 MappedOps.push_back(DAG.getConstant(NewIdx, 5135 ShufMask.getOperand(i).getValueType())); 5136 } 5137 } 5138 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5139 &MappedOps[0], MappedOps.size()); 5140 AddToWorkList(ShufMask.getNode()); 5141 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5142 N0, 5143 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5144 ShufMask); 5145 } 5146 5147 return SDValue(); 5148} 5149 5150SDValue DAGCombiner::visitSADDO(SDNode *N) { 5151 SDValue LHS = N->getOperand(0); 5152 SDValue RHS = N->getOperand(1); 5153 5154 SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); 5155 AddToWorkList(Sum.getNode()); 5156 SDValue Cmp = DAG.getSetCC(MVT::i1, Sum, LHS, ISD::SETLT); 5157 AddToWorkList(Cmp.getNode()); 5158 5159 MVT ValueVTs[] = { LHS.getValueType(), MVT::i1 }; 5160 SDValue Ops[] = { Sum, Cmp }; 5161 5162 SDValue Merge = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2), 5163 &Ops[0], 2); 5164 SDNode *MNode = Merge.getNode(); 5165 5166 AddToWorkList(MNode); 5167 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(MNode, 0)); 5168 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(MNode, 1)); 5169 5170 // Since the node is now dead, remove it from the graph. 5171 removeFromWorkList(N); 5172 DAG.DeleteNode(N); 5173 return SDValue(N, 0); 5174} 5175 5176SDValue DAGCombiner::visitUADDO(SDNode *N) { 5177 return SDValue(); 5178} 5179 5180/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5181/// an AND to a vector_shuffle with the destination vector and a zero vector. 5182/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5183/// vector_shuffle V, Zero, <0, 4, 2, 4> 5184SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5185 SDValue LHS = N->getOperand(0); 5186 SDValue RHS = N->getOperand(1); 5187 if (N->getOpcode() == ISD::AND) { 5188 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5189 RHS = RHS.getOperand(0); 5190 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5191 std::vector<SDValue> IdxOps; 5192 unsigned NumOps = RHS.getNumOperands(); 5193 unsigned NumElts = NumOps; 5194 for (unsigned i = 0; i != NumElts; ++i) { 5195 SDValue Elt = RHS.getOperand(i); 5196 if (!isa<ConstantSDNode>(Elt)) 5197 return SDValue(); 5198 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5199 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5200 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5201 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5202 else 5203 return SDValue(); 5204 } 5205 5206 // Let's see if the target supports this vector_shuffle. 5207 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5208 return SDValue(); 5209 5210 // Return the new VECTOR_SHUFFLE node. 5211 MVT EVT = RHS.getValueType().getVectorElementType(); 5212 MVT VT = MVT::getVectorVT(EVT, NumElts); 5213 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5214 std::vector<SDValue> Ops; 5215 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5216 Ops.push_back(LHS); 5217 AddToWorkList(LHS.getNode()); 5218 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5219 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5220 &ZeroOps[0], ZeroOps.size())); 5221 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5222 &IdxOps[0], IdxOps.size())); 5223 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5224 &Ops[0], Ops.size()); 5225 if (VT != N->getValueType(0)) 5226 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5227 return Result; 5228 } 5229 } 5230 return SDValue(); 5231} 5232 5233/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5234SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5235 // After legalize, the target may be depending on adds and other 5236 // binary ops to provide legal ways to construct constants or other 5237 // things. Simplifying them may result in a loss of legality. 5238 if (AfterLegalize) return SDValue(); 5239 5240 MVT VT = N->getValueType(0); 5241 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5242 5243 MVT EltType = VT.getVectorElementType(); 5244 SDValue LHS = N->getOperand(0); 5245 SDValue RHS = N->getOperand(1); 5246 SDValue Shuffle = XformToShuffleWithZero(N); 5247 if (Shuffle.getNode()) return Shuffle; 5248 5249 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5250 // this operation. 5251 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5252 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5253 SmallVector<SDValue, 8> Ops; 5254 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5255 SDValue LHSOp = LHS.getOperand(i); 5256 SDValue RHSOp = RHS.getOperand(i); 5257 // If these two elements can't be folded, bail out. 5258 if ((LHSOp.getOpcode() != ISD::UNDEF && 5259 LHSOp.getOpcode() != ISD::Constant && 5260 LHSOp.getOpcode() != ISD::ConstantFP) || 5261 (RHSOp.getOpcode() != ISD::UNDEF && 5262 RHSOp.getOpcode() != ISD::Constant && 5263 RHSOp.getOpcode() != ISD::ConstantFP)) 5264 break; 5265 // Can't fold divide by zero. 5266 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5267 N->getOpcode() == ISD::FDIV) { 5268 if ((RHSOp.getOpcode() == ISD::Constant && 5269 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5270 (RHSOp.getOpcode() == ISD::ConstantFP && 5271 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5272 break; 5273 } 5274 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5275 AddToWorkList(Ops.back().getNode()); 5276 assert((Ops.back().getOpcode() == ISD::UNDEF || 5277 Ops.back().getOpcode() == ISD::Constant || 5278 Ops.back().getOpcode() == ISD::ConstantFP) && 5279 "Scalar binop didn't fold!"); 5280 } 5281 5282 if (Ops.size() == LHS.getNumOperands()) { 5283 MVT VT = LHS.getValueType(); 5284 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5285 } 5286 } 5287 5288 return SDValue(); 5289} 5290 5291SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5292 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5293 5294 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5295 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5296 // If we got a simplified select_cc node back from SimplifySelectCC, then 5297 // break it down into a new SETCC node, and a new SELECT node, and then return 5298 // the SELECT node, since we were called with a SELECT node. 5299 if (SCC.getNode()) { 5300 // Check to see if we got a select_cc back (to turn into setcc/select). 5301 // Otherwise, just return whatever node we got back, like fabs. 5302 if (SCC.getOpcode() == ISD::SELECT_CC) { 5303 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5304 SCC.getOperand(0), SCC.getOperand(1), 5305 SCC.getOperand(4)); 5306 AddToWorkList(SETCC.getNode()); 5307 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5308 SCC.getOperand(3), SETCC); 5309 } 5310 return SCC; 5311 } 5312 return SDValue(); 5313} 5314 5315/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5316/// are the two values being selected between, see if we can simplify the 5317/// select. Callers of this should assume that TheSelect is deleted if this 5318/// returns true. As such, they should return the appropriate thing (e.g. the 5319/// node) back to the top-level of the DAG combiner loop to avoid it being 5320/// looked at. 5321/// 5322bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5323 SDValue RHS) { 5324 5325 // If this is a select from two identical things, try to pull the operation 5326 // through the select. 5327 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5328 // If this is a load and the token chain is identical, replace the select 5329 // of two loads with a load through a select of the address to load from. 5330 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5331 // constants have been dropped into the constant pool. 5332 if (LHS.getOpcode() == ISD::LOAD && 5333 // Do not let this transformation reduce the number of volatile loads. 5334 !cast<LoadSDNode>(LHS)->isVolatile() && 5335 !cast<LoadSDNode>(RHS)->isVolatile() && 5336 // Token chains must be identical. 5337 LHS.getOperand(0) == RHS.getOperand(0)) { 5338 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5339 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5340 5341 // If this is an EXTLOAD, the VT's must match. 5342 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5343 // FIXME: this conflates two src values, discarding one. This is not 5344 // the right thing to do, but nothing uses srcvalues now. When they do, 5345 // turn SrcValue into a list of locations. 5346 SDValue Addr; 5347 if (TheSelect->getOpcode() == ISD::SELECT) { 5348 // Check that the condition doesn't reach either load. If so, folding 5349 // this will induce a cycle into the DAG. 5350 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5351 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5352 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5353 TheSelect->getOperand(0), LLD->getBasePtr(), 5354 RLD->getBasePtr()); 5355 } 5356 } else { 5357 // Check that the condition doesn't reach either load. If so, folding 5358 // this will induce a cycle into the DAG. 5359 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5360 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5361 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5362 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5363 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5364 TheSelect->getOperand(0), 5365 TheSelect->getOperand(1), 5366 LLD->getBasePtr(), RLD->getBasePtr(), 5367 TheSelect->getOperand(4)); 5368 } 5369 } 5370 5371 if (Addr.getNode()) { 5372 SDValue Load; 5373 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5374 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5375 Addr,LLD->getSrcValue(), 5376 LLD->getSrcValueOffset(), 5377 LLD->isVolatile(), 5378 LLD->getAlignment()); 5379 else { 5380 Load = DAG.getExtLoad(LLD->getExtensionType(), 5381 TheSelect->getValueType(0), 5382 LLD->getChain(), Addr, LLD->getSrcValue(), 5383 LLD->getSrcValueOffset(), 5384 LLD->getMemoryVT(), 5385 LLD->isVolatile(), 5386 LLD->getAlignment()); 5387 } 5388 // Users of the select now use the result of the load. 5389 CombineTo(TheSelect, Load); 5390 5391 // Users of the old loads now use the new load's chain. We know the 5392 // old-load value is dead now. 5393 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5394 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5395 return true; 5396 } 5397 } 5398 } 5399 } 5400 5401 return false; 5402} 5403 5404SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5405 SDValue N2, SDValue N3, 5406 ISD::CondCode CC, bool NotExtCompare) { 5407 5408 MVT VT = N2.getValueType(); 5409 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5410 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5411 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5412 5413 // Determine if the condition we're dealing with is constant 5414 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5415 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5416 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5417 5418 // fold select_cc true, x, y -> x 5419 if (SCCC && !SCCC->isNullValue()) 5420 return N2; 5421 // fold select_cc false, x, y -> y 5422 if (SCCC && SCCC->isNullValue()) 5423 return N3; 5424 5425 // Check to see if we can simplify the select into an fabs node 5426 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5427 // Allow either -0.0 or 0.0 5428 if (CFP->getValueAPF().isZero()) { 5429 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5430 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5431 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5432 N2 == N3.getOperand(0)) 5433 return DAG.getNode(ISD::FABS, VT, N0); 5434 5435 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5436 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5437 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5438 N2.getOperand(0) == N3) 5439 return DAG.getNode(ISD::FABS, VT, N3); 5440 } 5441 } 5442 5443 // Check to see if we can perform the "gzip trick", transforming 5444 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5445 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5446 N0.getValueType().isInteger() && 5447 N2.getValueType().isInteger() && 5448 (N1C->isNullValue() || // (a < 0) ? b : 0 5449 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5450 MVT XType = N0.getValueType(); 5451 MVT AType = N2.getValueType(); 5452 if (XType.bitsGE(AType)) { 5453 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5454 // single-bit constant. 5455 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5456 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5457 ShCtV = XType.getSizeInBits()-ShCtV-1; 5458 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5459 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5460 AddToWorkList(Shift.getNode()); 5461 if (XType.bitsGT(AType)) { 5462 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5463 AddToWorkList(Shift.getNode()); 5464 } 5465 return DAG.getNode(ISD::AND, AType, Shift, N2); 5466 } 5467 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5468 DAG.getConstant(XType.getSizeInBits()-1, 5469 TLI.getShiftAmountTy())); 5470 AddToWorkList(Shift.getNode()); 5471 if (XType.bitsGT(AType)) { 5472 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5473 AddToWorkList(Shift.getNode()); 5474 } 5475 return DAG.getNode(ISD::AND, AType, Shift, N2); 5476 } 5477 } 5478 5479 // fold select C, 16, 0 -> shl C, 4 5480 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5481 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5482 5483 // If the caller doesn't want us to simplify this into a zext of a compare, 5484 // don't do it. 5485 if (NotExtCompare && N2C->getAPIntValue() == 1) 5486 return SDValue(); 5487 5488 // Get a SetCC of the condition 5489 // FIXME: Should probably make sure that setcc is legal if we ever have a 5490 // target where it isn't. 5491 SDValue Temp, SCC; 5492 // cast from setcc result type to select result type 5493 if (AfterLegalize) { 5494 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5495 if (N2.getValueType().bitsLT(SCC.getValueType())) 5496 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5497 else 5498 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5499 } else { 5500 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5501 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5502 } 5503 AddToWorkList(SCC.getNode()); 5504 AddToWorkList(Temp.getNode()); 5505 5506 if (N2C->getAPIntValue() == 1) 5507 return Temp; 5508 // shl setcc result by log2 n2c 5509 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5510 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5511 TLI.getShiftAmountTy())); 5512 } 5513 5514 // Check to see if this is the equivalent of setcc 5515 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5516 // otherwise, go ahead with the folds. 5517 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5518 MVT XType = N0.getValueType(); 5519 if (!AfterLegalize || 5520 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5521 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5522 if (Res.getValueType() != VT) 5523 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5524 return Res; 5525 } 5526 5527 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5528 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5529 (!AfterLegalize || 5530 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5531 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5532 return DAG.getNode(ISD::SRL, XType, Ctlz, 5533 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5534 TLI.getShiftAmountTy())); 5535 } 5536 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5537 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5538 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5539 N0); 5540 SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5541 DAG.getConstant(~0ULL, XType)); 5542 return DAG.getNode(ISD::SRL, XType, 5543 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5544 DAG.getConstant(XType.getSizeInBits()-1, 5545 TLI.getShiftAmountTy())); 5546 } 5547 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5548 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5549 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5550 DAG.getConstant(XType.getSizeInBits()-1, 5551 TLI.getShiftAmountTy())); 5552 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5553 } 5554 } 5555 5556 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5557 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5558 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5559 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5560 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5561 MVT XType = N0.getValueType(); 5562 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5563 DAG.getConstant(XType.getSizeInBits()-1, 5564 TLI.getShiftAmountTy())); 5565 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5566 AddToWorkList(Shift.getNode()); 5567 AddToWorkList(Add.getNode()); 5568 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5569 } 5570 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5571 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5572 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5573 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5574 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5575 MVT XType = N0.getValueType(); 5576 if (SubC->isNullValue() && XType.isInteger()) { 5577 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5578 DAG.getConstant(XType.getSizeInBits()-1, 5579 TLI.getShiftAmountTy())); 5580 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5581 AddToWorkList(Shift.getNode()); 5582 AddToWorkList(Add.getNode()); 5583 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5584 } 5585 } 5586 } 5587 5588 return SDValue(); 5589} 5590 5591/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5592SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5593 SDValue N1, ISD::CondCode Cond, 5594 bool foldBooleans) { 5595 TargetLowering::DAGCombinerInfo 5596 DagCombineInfo(DAG, !AfterLegalize, false, this); 5597 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5598} 5599 5600/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5601/// return a DAG expression to select that will generate the same value by 5602/// multiplying by a magic number. See: 5603/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5604SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5605 std::vector<SDNode*> Built; 5606 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5607 5608 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5609 ii != ee; ++ii) 5610 AddToWorkList(*ii); 5611 return S; 5612} 5613 5614/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5615/// return a DAG expression to select that will generate the same value by 5616/// multiplying by a magic number. See: 5617/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5618SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5619 std::vector<SDNode*> Built; 5620 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5621 5622 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5623 ii != ee; ++ii) 5624 AddToWorkList(*ii); 5625 return S; 5626} 5627 5628/// FindBaseOffset - Return true if base is known not to alias with anything 5629/// but itself. Provides base object and offset as results. 5630static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5631 // Assume it is a primitive operation. 5632 Base = Ptr; Offset = 0; 5633 5634 // If it's an adding a simple constant then integrate the offset. 5635 if (Base.getOpcode() == ISD::ADD) { 5636 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5637 Base = Base.getOperand(0); 5638 Offset += C->getZExtValue(); 5639 } 5640 } 5641 5642 // If it's any of the following then it can't alias with anything but itself. 5643 return isa<FrameIndexSDNode>(Base) || 5644 isa<ConstantPoolSDNode>(Base) || 5645 isa<GlobalAddressSDNode>(Base); 5646} 5647 5648/// isAlias - Return true if there is any possibility that the two addresses 5649/// overlap. 5650bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5651 const Value *SrcValue1, int SrcValueOffset1, 5652 SDValue Ptr2, int64_t Size2, 5653 const Value *SrcValue2, int SrcValueOffset2) 5654{ 5655 // If they are the same then they must be aliases. 5656 if (Ptr1 == Ptr2) return true; 5657 5658 // Gather base node and offset information. 5659 SDValue Base1, Base2; 5660 int64_t Offset1, Offset2; 5661 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5662 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5663 5664 // If they have a same base address then... 5665 if (Base1 == Base2) { 5666 // Check to see if the addresses overlap. 5667 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5668 } 5669 5670 // If we know both bases then they can't alias. 5671 if (KnownBase1 && KnownBase2) return false; 5672 5673 if (CombinerGlobalAA) { 5674 // Use alias analysis information. 5675 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5676 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5677 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5678 AliasAnalysis::AliasResult AAResult = 5679 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5680 if (AAResult == AliasAnalysis::NoAlias) 5681 return false; 5682 } 5683 5684 // Otherwise we have to assume they alias. 5685 return true; 5686} 5687 5688/// FindAliasInfo - Extracts the relevant alias information from the memory 5689/// node. Returns true if the operand was a load. 5690bool DAGCombiner::FindAliasInfo(SDNode *N, 5691 SDValue &Ptr, int64_t &Size, 5692 const Value *&SrcValue, int &SrcValueOffset) { 5693 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5694 Ptr = LD->getBasePtr(); 5695 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5696 SrcValue = LD->getSrcValue(); 5697 SrcValueOffset = LD->getSrcValueOffset(); 5698 return true; 5699 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5700 Ptr = ST->getBasePtr(); 5701 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5702 SrcValue = ST->getSrcValue(); 5703 SrcValueOffset = ST->getSrcValueOffset(); 5704 } else { 5705 assert(0 && "FindAliasInfo expected a memory operand"); 5706 } 5707 5708 return false; 5709} 5710 5711/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5712/// looking for aliasing nodes and adding them to the Aliases vector. 5713void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5714 SmallVector<SDValue, 8> &Aliases) { 5715 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5716 std::set<SDNode *> Visited; // Visited node set. 5717 5718 // Get alias information for node. 5719 SDValue Ptr; 5720 int64_t Size; 5721 const Value *SrcValue; 5722 int SrcValueOffset; 5723 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5724 5725 // Starting off. 5726 Chains.push_back(OriginalChain); 5727 5728 // Look at each chain and determine if it is an alias. If so, add it to the 5729 // aliases list. If not, then continue up the chain looking for the next 5730 // candidate. 5731 while (!Chains.empty()) { 5732 SDValue Chain = Chains.back(); 5733 Chains.pop_back(); 5734 5735 // Don't bother if we've been before. 5736 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5737 Visited.insert(Chain.getNode()); 5738 5739 switch (Chain.getOpcode()) { 5740 case ISD::EntryToken: 5741 // Entry token is ideal chain operand, but handled in FindBetterChain. 5742 break; 5743 5744 case ISD::LOAD: 5745 case ISD::STORE: { 5746 // Get alias information for Chain. 5747 SDValue OpPtr; 5748 int64_t OpSize; 5749 const Value *OpSrcValue; 5750 int OpSrcValueOffset; 5751 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5752 OpSrcValue, OpSrcValueOffset); 5753 5754 // If chain is alias then stop here. 5755 if (!(IsLoad && IsOpLoad) && 5756 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5757 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5758 Aliases.push_back(Chain); 5759 } else { 5760 // Look further up the chain. 5761 Chains.push_back(Chain.getOperand(0)); 5762 // Clean up old chain. 5763 AddToWorkList(Chain.getNode()); 5764 } 5765 break; 5766 } 5767 5768 case ISD::TokenFactor: 5769 // We have to check each of the operands of the token factor, so we queue 5770 // then up. Adding the operands to the queue (stack) in reverse order 5771 // maintains the original order and increases the likelihood that getNode 5772 // will find a matching token factor (CSE.) 5773 for (unsigned n = Chain.getNumOperands(); n;) 5774 Chains.push_back(Chain.getOperand(--n)); 5775 // Eliminate the token factor if we can. 5776 AddToWorkList(Chain.getNode()); 5777 break; 5778 5779 default: 5780 // For all other instructions we will just have to take what we can get. 5781 Aliases.push_back(Chain); 5782 break; 5783 } 5784 } 5785} 5786 5787/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5788/// for a better chain (aliasing node.) 5789SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5790 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5791 5792 // Accumulate all the aliases to this node. 5793 GatherAllAliases(N, OldChain, Aliases); 5794 5795 if (Aliases.size() == 0) { 5796 // If no operands then chain to entry token. 5797 return DAG.getEntryNode(); 5798 } else if (Aliases.size() == 1) { 5799 // If a single operand then chain to it. We don't need to revisit it. 5800 return Aliases[0]; 5801 } 5802 5803 // Construct a custom tailored token factor. 5804 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5805 &Aliases[0], Aliases.size()); 5806 5807 // Make sure the old chain gets cleaned up. 5808 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5809 5810 return NewChain; 5811} 5812 5813// SelectionDAG::Combine - This is the entry point for the file. 5814// 5815void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA, 5816 bool Fast) { 5817 /// run - This is the main entry point to this class. 5818 /// 5819 DAGCombiner(*this, AA, Fast).Run(RunningAfterLegalize); 5820} 5821