DAGCombiner.cpp revision 5c742681edc9d0e8be16f7518af5429d2b643078
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: make truncate see through SIGN_EXTEND and AND 26// FIXME: divide by zero is currently left unfolded. do we want to turn this 27// into an undef? 28// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "dagcombine" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include <algorithm> 39#include <cmath> 40#include <iostream> 41using namespace llvm; 42 43namespace { 44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 45 46 class DAGCombiner { 47 SelectionDAG &DAG; 48 TargetLowering &TLI; 49 bool AfterLegalize; 50 51 // Worklist of all of the nodes that need to be simplified. 52 std::vector<SDNode*> WorkList; 53 54 /// AddUsersToWorkList - When an instruction is simplified, add all users of 55 /// the instruction to the work lists because they might get more simplified 56 /// now. 57 /// 58 void AddUsersToWorkList(SDNode *N) { 59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 60 UI != UE; ++UI) 61 WorkList.push_back(*UI); 62 } 63 64 /// removeFromWorkList - remove all instances of N from the worklist. 65 /// 66 void removeFromWorkList(SDNode *N) { 67 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 68 WorkList.end()); 69 } 70 71 public: 72 void AddToWorkList(SDNode *N) { 73 WorkList.push_back(N); 74 } 75 76 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 77 ++NodesCombined; 78 DEBUG(std::cerr << "\nReplacing "; N->dump(); 79 std::cerr << "\nWith: "; To[0].Val->dump(); 80 std::cerr << " and " << To.size()-1 << " other values\n"); 81 std::vector<SDNode*> NowDead; 82 DAG.ReplaceAllUsesWith(N, To, &NowDead); 83 84 // Push the new nodes and any users onto the worklist 85 for (unsigned i = 0, e = To.size(); i != e; ++i) { 86 WorkList.push_back(To[i].Val); 87 AddUsersToWorkList(To[i].Val); 88 } 89 90 // Nodes can end up on the worklist more than once. Make sure we do 91 // not process a node that has been replaced. 92 removeFromWorkList(N); 93 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 94 removeFromWorkList(NowDead[i]); 95 96 // Finally, since the node is now dead, remove it from the graph. 97 DAG.DeleteNode(N); 98 return SDOperand(N, 0); 99 } 100 101 SDOperand CombineTo(SDNode *N, SDOperand Res) { 102 std::vector<SDOperand> To; 103 To.push_back(Res); 104 return CombineTo(N, To); 105 } 106 107 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 108 std::vector<SDOperand> To; 109 To.push_back(Res0); 110 To.push_back(Res1); 111 return CombineTo(N, To); 112 } 113 private: 114 115 /// SimplifyDemandedBits - Check the specified integer node value to see if 116 /// it can be simplified or if things it uses can be simplified by bit 117 /// propagation. If so, return true. 118 bool SimplifyDemandedBits(SDOperand Op) { 119 TargetLowering::TargetLoweringOpt TLO(DAG); 120 uint64_t KnownZero, KnownOne; 121 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 122 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 123 return false; 124 125 // Revisit the node. 126 WorkList.push_back(Op.Val); 127 128 // Replace the old value with the new one. 129 ++NodesCombined; 130 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 131 std::cerr << "\nWith: "; TLO.New.Val->dump()); 132 133 std::vector<SDNode*> NowDead; 134 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 135 136 // Push the new node and any (possibly new) users onto the worklist. 137 WorkList.push_back(TLO.New.Val); 138 AddUsersToWorkList(TLO.New.Val); 139 140 // Nodes can end up on the worklist more than once. Make sure we do 141 // not process a node that has been replaced. 142 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 143 removeFromWorkList(NowDead[i]); 144 145 // Finally, if the node is now dead, remove it from the graph. The node 146 // may not be dead if the replacement process recursively simplified to 147 // something else needing this node. 148 if (TLO.Old.Val->use_empty()) { 149 removeFromWorkList(TLO.Old.Val); 150 DAG.DeleteNode(TLO.Old.Val); 151 } 152 return true; 153 } 154 155 /// visit - call the node-specific routine that knows how to fold each 156 /// particular type of node. 157 SDOperand visit(SDNode *N); 158 159 // Visitation implementation - Implement dag node combining for different 160 // node types. The semantics are as follows: 161 // Return Value: 162 // SDOperand.Val == 0 - No change was made 163 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 164 // otherwise - N should be replaced by the returned Operand. 165 // 166 SDOperand visitTokenFactor(SDNode *N); 167 SDOperand visitADD(SDNode *N); 168 SDOperand visitSUB(SDNode *N); 169 SDOperand visitMUL(SDNode *N); 170 SDOperand visitSDIV(SDNode *N); 171 SDOperand visitUDIV(SDNode *N); 172 SDOperand visitSREM(SDNode *N); 173 SDOperand visitUREM(SDNode *N); 174 SDOperand visitMULHU(SDNode *N); 175 SDOperand visitMULHS(SDNode *N); 176 SDOperand visitAND(SDNode *N); 177 SDOperand visitOR(SDNode *N); 178 SDOperand visitXOR(SDNode *N); 179 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 180 SDOperand visitSHL(SDNode *N); 181 SDOperand visitSRA(SDNode *N); 182 SDOperand visitSRL(SDNode *N); 183 SDOperand visitCTLZ(SDNode *N); 184 SDOperand visitCTTZ(SDNode *N); 185 SDOperand visitCTPOP(SDNode *N); 186 SDOperand visitSELECT(SDNode *N); 187 SDOperand visitSELECT_CC(SDNode *N); 188 SDOperand visitSETCC(SDNode *N); 189 SDOperand visitSIGN_EXTEND(SDNode *N); 190 SDOperand visitZERO_EXTEND(SDNode *N); 191 SDOperand visitANY_EXTEND(SDNode *N); 192 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 193 SDOperand visitTRUNCATE(SDNode *N); 194 SDOperand visitBIT_CONVERT(SDNode *N); 195 SDOperand visitVBIT_CONVERT(SDNode *N); 196 SDOperand visitFADD(SDNode *N); 197 SDOperand visitFSUB(SDNode *N); 198 SDOperand visitFMUL(SDNode *N); 199 SDOperand visitFDIV(SDNode *N); 200 SDOperand visitFREM(SDNode *N); 201 SDOperand visitFCOPYSIGN(SDNode *N); 202 SDOperand visitSINT_TO_FP(SDNode *N); 203 SDOperand visitUINT_TO_FP(SDNode *N); 204 SDOperand visitFP_TO_SINT(SDNode *N); 205 SDOperand visitFP_TO_UINT(SDNode *N); 206 SDOperand visitFP_ROUND(SDNode *N); 207 SDOperand visitFP_ROUND_INREG(SDNode *N); 208 SDOperand visitFP_EXTEND(SDNode *N); 209 SDOperand visitFNEG(SDNode *N); 210 SDOperand visitFABS(SDNode *N); 211 SDOperand visitBRCOND(SDNode *N); 212 SDOperand visitBR_CC(SDNode *N); 213 SDOperand visitLOAD(SDNode *N); 214 SDOperand visitXEXTLOAD(SDNode *N); 215 SDOperand visitSTORE(SDNode *N); 216 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 217 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 218 SDOperand visitVBUILD_VECTOR(SDNode *N); 219 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 220 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 221 222 SDOperand XformToShuffleWithZero(SDNode *N); 223 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 224 225 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 226 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 227 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 228 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 229 SDOperand N3, ISD::CondCode CC); 230 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 231 ISD::CondCode Cond, bool foldBooleans = true); 232 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 233 SDOperand BuildSDIV(SDNode *N); 234 SDOperand BuildUDIV(SDNode *N); 235public: 236 DAGCombiner(SelectionDAG &D) 237 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 238 239 /// Run - runs the dag combiner on all nodes in the work list 240 void Run(bool RunningAfterLegalize); 241 }; 242} 243 244//===----------------------------------------------------------------------===// 245// TargetLowering::DAGCombinerInfo implementation 246//===----------------------------------------------------------------------===// 247 248void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 249 ((DAGCombiner*)DC)->AddToWorkList(N); 250} 251 252SDOperand TargetLowering::DAGCombinerInfo:: 253CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 254 return ((DAGCombiner*)DC)->CombineTo(N, To); 255} 256 257SDOperand TargetLowering::DAGCombinerInfo:: 258CombineTo(SDNode *N, SDOperand Res) { 259 return ((DAGCombiner*)DC)->CombineTo(N, Res); 260} 261 262 263SDOperand TargetLowering::DAGCombinerInfo:: 264CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 265 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 266} 267 268 269 270 271//===----------------------------------------------------------------------===// 272 273 274struct ms { 275 int64_t m; // magic number 276 int64_t s; // shift amount 277}; 278 279struct mu { 280 uint64_t m; // magic number 281 int64_t a; // add indicator 282 int64_t s; // shift amount 283}; 284 285/// magic - calculate the magic numbers required to codegen an integer sdiv as 286/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 287/// or -1. 288static ms magic32(int32_t d) { 289 int32_t p; 290 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 291 const uint32_t two31 = 0x80000000U; 292 struct ms mag; 293 294 ad = abs(d); 295 t = two31 + ((uint32_t)d >> 31); 296 anc = t - 1 - t%ad; // absolute value of nc 297 p = 31; // initialize p 298 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 299 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 300 q2 = two31/ad; // initialize q2 = 2p/abs(d) 301 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 302 do { 303 p = p + 1; 304 q1 = 2*q1; // update q1 = 2p/abs(nc) 305 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 306 if (r1 >= anc) { // must be unsigned comparison 307 q1 = q1 + 1; 308 r1 = r1 - anc; 309 } 310 q2 = 2*q2; // update q2 = 2p/abs(d) 311 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 312 if (r2 >= ad) { // must be unsigned comparison 313 q2 = q2 + 1; 314 r2 = r2 - ad; 315 } 316 delta = ad - r2; 317 } while (q1 < delta || (q1 == delta && r1 == 0)); 318 319 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 320 if (d < 0) mag.m = -mag.m; // resulting magic number 321 mag.s = p - 32; // resulting shift 322 return mag; 323} 324 325/// magicu - calculate the magic numbers required to codegen an integer udiv as 326/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 327static mu magicu32(uint32_t d) { 328 int32_t p; 329 uint32_t nc, delta, q1, r1, q2, r2; 330 struct mu magu; 331 magu.a = 0; // initialize "add" indicator 332 nc = - 1 - (-d)%d; 333 p = 31; // initialize p 334 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 335 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 336 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 337 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 338 do { 339 p = p + 1; 340 if (r1 >= nc - r1 ) { 341 q1 = 2*q1 + 1; // update q1 342 r1 = 2*r1 - nc; // update r1 343 } 344 else { 345 q1 = 2*q1; // update q1 346 r1 = 2*r1; // update r1 347 } 348 if (r2 + 1 >= d - r2) { 349 if (q2 >= 0x7FFFFFFF) magu.a = 1; 350 q2 = 2*q2 + 1; // update q2 351 r2 = 2*r2 + 1 - d; // update r2 352 } 353 else { 354 if (q2 >= 0x80000000) magu.a = 1; 355 q2 = 2*q2; // update q2 356 r2 = 2*r2 + 1; // update r2 357 } 358 delta = d - 1 - r2; 359 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 360 magu.m = q2 + 1; // resulting magic number 361 magu.s = p - 32; // resulting shift 362 return magu; 363} 364 365/// magic - calculate the magic numbers required to codegen an integer sdiv as 366/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 367/// or -1. 368static ms magic64(int64_t d) { 369 int64_t p; 370 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 371 const uint64_t two63 = 9223372036854775808ULL; // 2^63 372 struct ms mag; 373 374 ad = d >= 0 ? d : -d; 375 t = two63 + ((uint64_t)d >> 63); 376 anc = t - 1 - t%ad; // absolute value of nc 377 p = 63; // initialize p 378 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 379 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 380 q2 = two63/ad; // initialize q2 = 2p/abs(d) 381 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 382 do { 383 p = p + 1; 384 q1 = 2*q1; // update q1 = 2p/abs(nc) 385 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 386 if (r1 >= anc) { // must be unsigned comparison 387 q1 = q1 + 1; 388 r1 = r1 - anc; 389 } 390 q2 = 2*q2; // update q2 = 2p/abs(d) 391 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 392 if (r2 >= ad) { // must be unsigned comparison 393 q2 = q2 + 1; 394 r2 = r2 - ad; 395 } 396 delta = ad - r2; 397 } while (q1 < delta || (q1 == delta && r1 == 0)); 398 399 mag.m = q2 + 1; 400 if (d < 0) mag.m = -mag.m; // resulting magic number 401 mag.s = p - 64; // resulting shift 402 return mag; 403} 404 405/// magicu - calculate the magic numbers required to codegen an integer udiv as 406/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 407static mu magicu64(uint64_t d) 408{ 409 int64_t p; 410 uint64_t nc, delta, q1, r1, q2, r2; 411 struct mu magu; 412 magu.a = 0; // initialize "add" indicator 413 nc = - 1 - (-d)%d; 414 p = 63; // initialize p 415 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 416 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 417 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 418 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 419 do { 420 p = p + 1; 421 if (r1 >= nc - r1 ) { 422 q1 = 2*q1 + 1; // update q1 423 r1 = 2*r1 - nc; // update r1 424 } 425 else { 426 q1 = 2*q1; // update q1 427 r1 = 2*r1; // update r1 428 } 429 if (r2 + 1 >= d - r2) { 430 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 431 q2 = 2*q2 + 1; // update q2 432 r2 = 2*r2 + 1 - d; // update r2 433 } 434 else { 435 if (q2 >= 0x8000000000000000ull) magu.a = 1; 436 q2 = 2*q2; // update q2 437 r2 = 2*r2 + 1; // update r2 438 } 439 delta = d - 1 - r2; 440 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 441 magu.m = q2 + 1; // resulting magic number 442 magu.s = p - 64; // resulting shift 443 return magu; 444} 445 446// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 447// that selects between the values 1 and 0, making it equivalent to a setcc. 448// Also, set the incoming LHS, RHS, and CC references to the appropriate 449// nodes based on the type of node we are checking. This simplifies life a 450// bit for the callers. 451static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 452 SDOperand &CC) { 453 if (N.getOpcode() == ISD::SETCC) { 454 LHS = N.getOperand(0); 455 RHS = N.getOperand(1); 456 CC = N.getOperand(2); 457 return true; 458 } 459 if (N.getOpcode() == ISD::SELECT_CC && 460 N.getOperand(2).getOpcode() == ISD::Constant && 461 N.getOperand(3).getOpcode() == ISD::Constant && 462 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 463 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 464 LHS = N.getOperand(0); 465 RHS = N.getOperand(1); 466 CC = N.getOperand(4); 467 return true; 468 } 469 return false; 470} 471 472// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 473// one use. If this is true, it allows the users to invert the operation for 474// free when it is profitable to do so. 475static bool isOneUseSetCC(SDOperand N) { 476 SDOperand N0, N1, N2; 477 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 478 return true; 479 return false; 480} 481 482// FIXME: This should probably go in the ISD class rather than being duplicated 483// in several files. 484static bool isCommutativeBinOp(unsigned Opcode) { 485 switch (Opcode) { 486 case ISD::ADD: 487 case ISD::MUL: 488 case ISD::AND: 489 case ISD::OR: 490 case ISD::XOR: return true; 491 default: return false; // FIXME: Need commutative info for user ops! 492 } 493} 494 495SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 496 MVT::ValueType VT = N0.getValueType(); 497 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 498 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 499 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 500 if (isa<ConstantSDNode>(N1)) { 501 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 502 AddToWorkList(OpNode.Val); 503 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 504 } else if (N0.hasOneUse()) { 505 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 506 AddToWorkList(OpNode.Val); 507 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 508 } 509 } 510 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 511 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 512 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 513 if (isa<ConstantSDNode>(N0)) { 514 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 515 AddToWorkList(OpNode.Val); 516 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 517 } else if (N1.hasOneUse()) { 518 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 519 AddToWorkList(OpNode.Val); 520 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 521 } 522 } 523 return SDOperand(); 524} 525 526void DAGCombiner::Run(bool RunningAfterLegalize) { 527 // set the instance variable, so that the various visit routines may use it. 528 AfterLegalize = RunningAfterLegalize; 529 530 // Add all the dag nodes to the worklist. 531 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 532 E = DAG.allnodes_end(); I != E; ++I) 533 WorkList.push_back(I); 534 535 // Create a dummy node (which is not added to allnodes), that adds a reference 536 // to the root node, preventing it from being deleted, and tracking any 537 // changes of the root. 538 HandleSDNode Dummy(DAG.getRoot()); 539 540 541 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 542 TargetLowering::DAGCombinerInfo 543 DagCombineInfo(DAG, !RunningAfterLegalize, this); 544 545 // while the worklist isn't empty, inspect the node on the end of it and 546 // try and combine it. 547 while (!WorkList.empty()) { 548 SDNode *N = WorkList.back(); 549 WorkList.pop_back(); 550 551 // If N has no uses, it is dead. Make sure to revisit all N's operands once 552 // N is deleted from the DAG, since they too may now be dead or may have a 553 // reduced number of uses, allowing other xforms. 554 if (N->use_empty() && N != &Dummy) { 555 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 556 WorkList.push_back(N->getOperand(i).Val); 557 558 removeFromWorkList(N); 559 DAG.DeleteNode(N); 560 continue; 561 } 562 563 SDOperand RV = visit(N); 564 565 // If nothing happened, try a target-specific DAG combine. 566 if (RV.Val == 0) { 567 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 568 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 569 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 570 } 571 572 if (RV.Val) { 573 ++NodesCombined; 574 // If we get back the same node we passed in, rather than a new node or 575 // zero, we know that the node must have defined multiple values and 576 // CombineTo was used. Since CombineTo takes care of the worklist 577 // mechanics for us, we have no work to do in this case. 578 if (RV.Val != N) { 579 DEBUG(std::cerr << "\nReplacing "; N->dump(); 580 std::cerr << "\nWith: "; RV.Val->dump(); 581 std::cerr << '\n'); 582 std::vector<SDNode*> NowDead; 583 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 584 585 // Push the new node and any users onto the worklist 586 WorkList.push_back(RV.Val); 587 AddUsersToWorkList(RV.Val); 588 589 // Nodes can end up on the worklist more than once. Make sure we do 590 // not process a node that has been replaced. 591 removeFromWorkList(N); 592 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 593 removeFromWorkList(NowDead[i]); 594 595 // Finally, since the node is now dead, remove it from the graph. 596 DAG.DeleteNode(N); 597 } 598 } 599 } 600 601 // If the root changed (e.g. it was a dead load, update the root). 602 DAG.setRoot(Dummy.getValue()); 603} 604 605SDOperand DAGCombiner::visit(SDNode *N) { 606 switch(N->getOpcode()) { 607 default: break; 608 case ISD::TokenFactor: return visitTokenFactor(N); 609 case ISD::ADD: return visitADD(N); 610 case ISD::SUB: return visitSUB(N); 611 case ISD::MUL: return visitMUL(N); 612 case ISD::SDIV: return visitSDIV(N); 613 case ISD::UDIV: return visitUDIV(N); 614 case ISD::SREM: return visitSREM(N); 615 case ISD::UREM: return visitUREM(N); 616 case ISD::MULHU: return visitMULHU(N); 617 case ISD::MULHS: return visitMULHS(N); 618 case ISD::AND: return visitAND(N); 619 case ISD::OR: return visitOR(N); 620 case ISD::XOR: return visitXOR(N); 621 case ISD::SHL: return visitSHL(N); 622 case ISD::SRA: return visitSRA(N); 623 case ISD::SRL: return visitSRL(N); 624 case ISD::CTLZ: return visitCTLZ(N); 625 case ISD::CTTZ: return visitCTTZ(N); 626 case ISD::CTPOP: return visitCTPOP(N); 627 case ISD::SELECT: return visitSELECT(N); 628 case ISD::SELECT_CC: return visitSELECT_CC(N); 629 case ISD::SETCC: return visitSETCC(N); 630 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 631 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 632 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 633 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 634 case ISD::TRUNCATE: return visitTRUNCATE(N); 635 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 636 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 637 case ISD::FADD: return visitFADD(N); 638 case ISD::FSUB: return visitFSUB(N); 639 case ISD::FMUL: return visitFMUL(N); 640 case ISD::FDIV: return visitFDIV(N); 641 case ISD::FREM: return visitFREM(N); 642 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 643 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 644 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 645 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 646 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 647 case ISD::FP_ROUND: return visitFP_ROUND(N); 648 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 649 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 650 case ISD::FNEG: return visitFNEG(N); 651 case ISD::FABS: return visitFABS(N); 652 case ISD::BRCOND: return visitBRCOND(N); 653 case ISD::BR_CC: return visitBR_CC(N); 654 case ISD::LOAD: return visitLOAD(N); 655 case ISD::EXTLOAD: 656 case ISD::SEXTLOAD: 657 case ISD::ZEXTLOAD: return visitXEXTLOAD(N); 658 case ISD::STORE: return visitSTORE(N); 659 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 660 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 661 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 662 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 663 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 664 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 665 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 666 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 667 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 668 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 669 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 670 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 671 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 672 } 673 return SDOperand(); 674} 675 676SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 677 std::vector<SDOperand> Ops; 678 bool Changed = false; 679 680 // If the token factor has two operands and one is the entry token, replace 681 // the token factor with the other operand. 682 if (N->getNumOperands() == 2) { 683 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 684 return N->getOperand(1); 685 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 686 return N->getOperand(0); 687 } 688 689 // fold (tokenfactor (tokenfactor)) -> tokenfactor 690 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 691 SDOperand Op = N->getOperand(i); 692 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 693 AddToWorkList(Op.Val); // Remove dead node. 694 Changed = true; 695 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 696 Ops.push_back(Op.getOperand(j)); 697 } else { 698 Ops.push_back(Op); 699 } 700 } 701 if (Changed) 702 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 703 return SDOperand(); 704} 705 706SDOperand DAGCombiner::visitADD(SDNode *N) { 707 SDOperand N0 = N->getOperand(0); 708 SDOperand N1 = N->getOperand(1); 709 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 710 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 711 MVT::ValueType VT = N0.getValueType(); 712 713 // fold (add c1, c2) -> c1+c2 714 if (N0C && N1C) 715 return DAG.getNode(ISD::ADD, VT, N0, N1); 716 // canonicalize constant to RHS 717 if (N0C && !N1C) 718 return DAG.getNode(ISD::ADD, VT, N1, N0); 719 // fold (add x, 0) -> x 720 if (N1C && N1C->isNullValue()) 721 return N0; 722 // fold ((c1-A)+c2) -> (c1+c2)-A 723 if (N1C && N0.getOpcode() == ISD::SUB) 724 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 725 return DAG.getNode(ISD::SUB, VT, 726 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 727 N0.getOperand(1)); 728 // reassociate add 729 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 730 if (RADD.Val != 0) 731 return RADD; 732 // fold ((0-A) + B) -> B-A 733 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 734 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 735 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 736 // fold (A + (0-B)) -> A-B 737 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 738 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 739 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 740 // fold (A+(B-A)) -> B 741 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 742 return N1.getOperand(0); 743 744 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 745 return SDOperand(N, 0); 746 747 // fold (a+b) -> (a|b) iff a and b share no bits. 748 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 749 uint64_t LHSZero, LHSOne; 750 uint64_t RHSZero, RHSOne; 751 uint64_t Mask = MVT::getIntVTBitMask(VT); 752 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 753 if (LHSZero) { 754 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 755 756 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 757 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 758 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 759 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 760 return DAG.getNode(ISD::OR, VT, N0, N1); 761 } 762 } 763 764 return SDOperand(); 765} 766 767SDOperand DAGCombiner::visitSUB(SDNode *N) { 768 SDOperand N0 = N->getOperand(0); 769 SDOperand N1 = N->getOperand(1); 770 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 771 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 772 MVT::ValueType VT = N0.getValueType(); 773 774 // fold (sub x, x) -> 0 775 if (N0 == N1) 776 return DAG.getConstant(0, N->getValueType(0)); 777 // fold (sub c1, c2) -> c1-c2 778 if (N0C && N1C) 779 return DAG.getNode(ISD::SUB, VT, N0, N1); 780 // fold (sub x, c) -> (add x, -c) 781 if (N1C) 782 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 783 // fold (A+B)-A -> B 784 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 785 return N0.getOperand(1); 786 // fold (A+B)-B -> A 787 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 788 return N0.getOperand(0); 789 return SDOperand(); 790} 791 792SDOperand DAGCombiner::visitMUL(SDNode *N) { 793 SDOperand N0 = N->getOperand(0); 794 SDOperand N1 = N->getOperand(1); 795 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 796 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 797 MVT::ValueType VT = N0.getValueType(); 798 799 // fold (mul c1, c2) -> c1*c2 800 if (N0C && N1C) 801 return DAG.getNode(ISD::MUL, VT, N0, N1); 802 // canonicalize constant to RHS 803 if (N0C && !N1C) 804 return DAG.getNode(ISD::MUL, VT, N1, N0); 805 // fold (mul x, 0) -> 0 806 if (N1C && N1C->isNullValue()) 807 return N1; 808 // fold (mul x, -1) -> 0-x 809 if (N1C && N1C->isAllOnesValue()) 810 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 811 // fold (mul x, (1 << c)) -> x << c 812 if (N1C && isPowerOf2_64(N1C->getValue())) 813 return DAG.getNode(ISD::SHL, VT, N0, 814 DAG.getConstant(Log2_64(N1C->getValue()), 815 TLI.getShiftAmountTy())); 816 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 817 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 818 // FIXME: If the input is something that is easily negated (e.g. a 819 // single-use add), we should put the negate there. 820 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 821 DAG.getNode(ISD::SHL, VT, N0, 822 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 823 TLI.getShiftAmountTy()))); 824 } 825 826 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 827 if (N1C && N0.getOpcode() == ISD::SHL && 828 isa<ConstantSDNode>(N0.getOperand(1))) { 829 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 830 AddToWorkList(C3.Val); 831 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 832 } 833 834 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 835 // use. 836 { 837 SDOperand Sh(0,0), Y(0,0); 838 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 839 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 840 N0.Val->hasOneUse()) { 841 Sh = N0; Y = N1; 842 } else if (N1.getOpcode() == ISD::SHL && 843 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 844 Sh = N1; Y = N0; 845 } 846 if (Sh.Val) { 847 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 848 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 849 } 850 } 851 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 852 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 853 isa<ConstantSDNode>(N0.getOperand(1))) { 854 return DAG.getNode(ISD::ADD, VT, 855 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 856 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 857 } 858 859 // reassociate mul 860 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 861 if (RMUL.Val != 0) 862 return RMUL; 863 return SDOperand(); 864} 865 866SDOperand DAGCombiner::visitSDIV(SDNode *N) { 867 SDOperand N0 = N->getOperand(0); 868 SDOperand N1 = N->getOperand(1); 869 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 870 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 871 MVT::ValueType VT = N->getValueType(0); 872 873 // fold (sdiv c1, c2) -> c1/c2 874 if (N0C && N1C && !N1C->isNullValue()) 875 return DAG.getNode(ISD::SDIV, VT, N0, N1); 876 // fold (sdiv X, 1) -> X 877 if (N1C && N1C->getSignExtended() == 1LL) 878 return N0; 879 // fold (sdiv X, -1) -> 0-X 880 if (N1C && N1C->isAllOnesValue()) 881 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 882 // If we know the sign bits of both operands are zero, strength reduce to a 883 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 884 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 885 if (TLI.MaskedValueIsZero(N1, SignBit) && 886 TLI.MaskedValueIsZero(N0, SignBit)) 887 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 888 // fold (sdiv X, pow2) -> simple ops after legalize 889 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 890 (isPowerOf2_64(N1C->getSignExtended()) || 891 isPowerOf2_64(-N1C->getSignExtended()))) { 892 // If dividing by powers of two is cheap, then don't perform the following 893 // fold. 894 if (TLI.isPow2DivCheap()) 895 return SDOperand(); 896 int64_t pow2 = N1C->getSignExtended(); 897 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 898 unsigned lg2 = Log2_64(abs2); 899 // Splat the sign bit into the register 900 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 901 DAG.getConstant(MVT::getSizeInBits(VT)-1, 902 TLI.getShiftAmountTy())); 903 AddToWorkList(SGN.Val); 904 // Add (N0 < 0) ? abs2 - 1 : 0; 905 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 906 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 907 TLI.getShiftAmountTy())); 908 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 909 AddToWorkList(SRL.Val); 910 AddToWorkList(ADD.Val); // Divide by pow2 911 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 912 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 913 // If we're dividing by a positive value, we're done. Otherwise, we must 914 // negate the result. 915 if (pow2 > 0) 916 return SRA; 917 AddToWorkList(SRA.Val); 918 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 919 } 920 // if integer divide is expensive and we satisfy the requirements, emit an 921 // alternate sequence. 922 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 923 !TLI.isIntDivCheap()) { 924 SDOperand Op = BuildSDIV(N); 925 if (Op.Val) return Op; 926 } 927 return SDOperand(); 928} 929 930SDOperand DAGCombiner::visitUDIV(SDNode *N) { 931 SDOperand N0 = N->getOperand(0); 932 SDOperand N1 = N->getOperand(1); 933 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 934 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 935 MVT::ValueType VT = N->getValueType(0); 936 937 // fold (udiv c1, c2) -> c1/c2 938 if (N0C && N1C && !N1C->isNullValue()) 939 return DAG.getNode(ISD::UDIV, VT, N0, N1); 940 // fold (udiv x, (1 << c)) -> x >>u c 941 if (N1C && isPowerOf2_64(N1C->getValue())) 942 return DAG.getNode(ISD::SRL, VT, N0, 943 DAG.getConstant(Log2_64(N1C->getValue()), 944 TLI.getShiftAmountTy())); 945 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 946 if (N1.getOpcode() == ISD::SHL) { 947 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 948 if (isPowerOf2_64(SHC->getValue())) { 949 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 950 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 951 DAG.getConstant(Log2_64(SHC->getValue()), 952 ADDVT)); 953 AddToWorkList(Add.Val); 954 return DAG.getNode(ISD::SRL, VT, N0, Add); 955 } 956 } 957 } 958 // fold (udiv x, c) -> alternate 959 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 960 SDOperand Op = BuildUDIV(N); 961 if (Op.Val) return Op; 962 } 963 return SDOperand(); 964} 965 966SDOperand DAGCombiner::visitSREM(SDNode *N) { 967 SDOperand N0 = N->getOperand(0); 968 SDOperand N1 = N->getOperand(1); 969 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 970 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 971 MVT::ValueType VT = N->getValueType(0); 972 973 // fold (srem c1, c2) -> c1%c2 974 if (N0C && N1C && !N1C->isNullValue()) 975 return DAG.getNode(ISD::SREM, VT, N0, N1); 976 // If we know the sign bits of both operands are zero, strength reduce to a 977 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 978 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 979 if (TLI.MaskedValueIsZero(N1, SignBit) && 980 TLI.MaskedValueIsZero(N0, SignBit)) 981 return DAG.getNode(ISD::UREM, VT, N0, N1); 982 return SDOperand(); 983} 984 985SDOperand DAGCombiner::visitUREM(SDNode *N) { 986 SDOperand N0 = N->getOperand(0); 987 SDOperand N1 = N->getOperand(1); 988 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 989 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 990 MVT::ValueType VT = N->getValueType(0); 991 992 // fold (urem c1, c2) -> c1%c2 993 if (N0C && N1C && !N1C->isNullValue()) 994 return DAG.getNode(ISD::UREM, VT, N0, N1); 995 // fold (urem x, pow2) -> (and x, pow2-1) 996 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 997 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 998 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 999 if (N1.getOpcode() == ISD::SHL) { 1000 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1001 if (isPowerOf2_64(SHC->getValue())) { 1002 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1003 AddToWorkList(Add.Val); 1004 return DAG.getNode(ISD::AND, VT, N0, Add); 1005 } 1006 } 1007 } 1008 return SDOperand(); 1009} 1010 1011SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1012 SDOperand N0 = N->getOperand(0); 1013 SDOperand N1 = N->getOperand(1); 1014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1015 1016 // fold (mulhs x, 0) -> 0 1017 if (N1C && N1C->isNullValue()) 1018 return N1; 1019 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1020 if (N1C && N1C->getValue() == 1) 1021 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1022 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1023 TLI.getShiftAmountTy())); 1024 return SDOperand(); 1025} 1026 1027SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1028 SDOperand N0 = N->getOperand(0); 1029 SDOperand N1 = N->getOperand(1); 1030 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1031 1032 // fold (mulhu x, 0) -> 0 1033 if (N1C && N1C->isNullValue()) 1034 return N1; 1035 // fold (mulhu x, 1) -> 0 1036 if (N1C && N1C->getValue() == 1) 1037 return DAG.getConstant(0, N0.getValueType()); 1038 return SDOperand(); 1039} 1040 1041/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1042/// two operands of the same opcode, try to simplify it. 1043SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1044 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1045 MVT::ValueType VT = N0.getValueType(); 1046 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1047 1048 // For each of OP in AND/OR/XOR: 1049 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1050 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1051 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1052 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1053 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1054 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1055 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1056 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1057 N0.getOperand(0).getValueType(), 1058 N0.getOperand(0), N1.getOperand(0)); 1059 AddToWorkList(ORNode.Val); 1060 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1061 } 1062 1063 // For each of OP in SHL/SRL/SRA/AND... 1064 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1065 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1066 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1067 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1068 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1069 N0.getOperand(1) == N1.getOperand(1)) { 1070 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1071 N0.getOperand(0).getValueType(), 1072 N0.getOperand(0), N1.getOperand(0)); 1073 AddToWorkList(ORNode.Val); 1074 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1075 } 1076 1077 return SDOperand(); 1078} 1079 1080SDOperand DAGCombiner::visitAND(SDNode *N) { 1081 SDOperand N0 = N->getOperand(0); 1082 SDOperand N1 = N->getOperand(1); 1083 SDOperand LL, LR, RL, RR, CC0, CC1; 1084 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1085 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1086 MVT::ValueType VT = N1.getValueType(); 1087 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1088 1089 // fold (and c1, c2) -> c1&c2 1090 if (N0C && N1C) 1091 return DAG.getNode(ISD::AND, VT, N0, N1); 1092 // canonicalize constant to RHS 1093 if (N0C && !N1C) 1094 return DAG.getNode(ISD::AND, VT, N1, N0); 1095 // fold (and x, -1) -> x 1096 if (N1C && N1C->isAllOnesValue()) 1097 return N0; 1098 // if (and x, c) is known to be zero, return 0 1099 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1100 return DAG.getConstant(0, VT); 1101 // reassociate and 1102 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1103 if (RAND.Val != 0) 1104 return RAND; 1105 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1106 if (N1C && N0.getOpcode() == ISD::OR) 1107 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1108 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1109 return N1; 1110 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1111 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1112 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1113 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1114 ~N1C->getValue() & InMask)) { 1115 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1116 N0.getOperand(0)); 1117 1118 // Replace uses of the AND with uses of the Zero extend node. 1119 CombineTo(N, Zext); 1120 1121 // We actually want to replace all uses of the any_extend with the 1122 // zero_extend, to avoid duplicating things. This will later cause this 1123 // AND to be folded. 1124 CombineTo(N0.Val, Zext); 1125 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1126 } 1127 } 1128 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1129 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1130 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1131 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1132 1133 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1134 MVT::isInteger(LL.getValueType())) { 1135 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1136 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1137 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1138 AddToWorkList(ORNode.Val); 1139 return DAG.getSetCC(VT, ORNode, LR, Op1); 1140 } 1141 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1142 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1143 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1144 AddToWorkList(ANDNode.Val); 1145 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1146 } 1147 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1148 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1149 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1150 AddToWorkList(ORNode.Val); 1151 return DAG.getSetCC(VT, ORNode, LR, Op1); 1152 } 1153 } 1154 // canonicalize equivalent to ll == rl 1155 if (LL == RR && LR == RL) { 1156 Op1 = ISD::getSetCCSwappedOperands(Op1); 1157 std::swap(RL, RR); 1158 } 1159 if (LL == RL && LR == RR) { 1160 bool isInteger = MVT::isInteger(LL.getValueType()); 1161 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1162 if (Result != ISD::SETCC_INVALID) 1163 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1164 } 1165 } 1166 1167 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1168 if (N0.getOpcode() == N1.getOpcode()) { 1169 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1170 if (Tmp.Val) return Tmp; 1171 } 1172 1173 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1174 // fold (and (sra)) -> (and (srl)) when possible. 1175 if (!MVT::isVector(VT) && 1176 SimplifyDemandedBits(SDOperand(N, 0))) 1177 return SDOperand(N, 0); 1178 // fold (zext_inreg (extload x)) -> (zextload x) 1179 if (N0.getOpcode() == ISD::EXTLOAD) { 1180 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1181 // If we zero all the possible extended bits, then we can turn this into 1182 // a zextload if we are running before legalize or the operation is legal. 1183 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1184 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1185 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1186 N0.getOperand(1), N0.getOperand(2), 1187 EVT); 1188 AddToWorkList(N); 1189 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1190 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1191 } 1192 } 1193 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1194 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1195 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1196 // If we zero all the possible extended bits, then we can turn this into 1197 // a zextload if we are running before legalize or the operation is legal. 1198 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1199 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1200 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1201 N0.getOperand(1), N0.getOperand(2), 1202 EVT); 1203 AddToWorkList(N); 1204 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1205 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1206 } 1207 } 1208 1209 // fold (and (load x), 255) -> (zextload x, i8) 1210 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1211 if (N1C && 1212 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD || 1213 N0.getOpcode() == ISD::ZEXTLOAD) && 1214 N0.hasOneUse()) { 1215 MVT::ValueType EVT, LoadedVT; 1216 if (N1C->getValue() == 255) 1217 EVT = MVT::i8; 1218 else if (N1C->getValue() == 65535) 1219 EVT = MVT::i16; 1220 else if (N1C->getValue() == ~0U) 1221 EVT = MVT::i32; 1222 else 1223 EVT = MVT::Other; 1224 1225 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : 1226 cast<VTSDNode>(N0.getOperand(3))->getVT(); 1227 if (EVT != MVT::Other && LoadedVT > EVT && 1228 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1229 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1230 // For big endian targets, we need to add an offset to the pointer to load 1231 // the correct bytes. For little endian systems, we merely need to read 1232 // fewer bytes from the same pointer. 1233 unsigned PtrOff = 1234 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1235 SDOperand NewPtr = N0.getOperand(1); 1236 if (!TLI.isLittleEndian()) 1237 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1238 DAG.getConstant(PtrOff, PtrType)); 1239 AddToWorkList(NewPtr.Val); 1240 SDOperand Load = 1241 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr, 1242 N0.getOperand(2), EVT); 1243 AddToWorkList(N); 1244 CombineTo(N0.Val, Load, Load.getValue(1)); 1245 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1246 } 1247 } 1248 1249 return SDOperand(); 1250} 1251 1252SDOperand DAGCombiner::visitOR(SDNode *N) { 1253 SDOperand N0 = N->getOperand(0); 1254 SDOperand N1 = N->getOperand(1); 1255 SDOperand LL, LR, RL, RR, CC0, CC1; 1256 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1257 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1258 MVT::ValueType VT = N1.getValueType(); 1259 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1260 1261 // fold (or c1, c2) -> c1|c2 1262 if (N0C && N1C) 1263 return DAG.getNode(ISD::OR, VT, N0, N1); 1264 // canonicalize constant to RHS 1265 if (N0C && !N1C) 1266 return DAG.getNode(ISD::OR, VT, N1, N0); 1267 // fold (or x, 0) -> x 1268 if (N1C && N1C->isNullValue()) 1269 return N0; 1270 // fold (or x, -1) -> -1 1271 if (N1C && N1C->isAllOnesValue()) 1272 return N1; 1273 // fold (or x, c) -> c iff (x & ~c) == 0 1274 if (N1C && 1275 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1276 return N1; 1277 // reassociate or 1278 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1279 if (ROR.Val != 0) 1280 return ROR; 1281 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1282 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1283 isa<ConstantSDNode>(N0.getOperand(1))) { 1284 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1285 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1286 N1), 1287 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1288 } 1289 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1290 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1291 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1292 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1293 1294 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1295 MVT::isInteger(LL.getValueType())) { 1296 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1297 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1298 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1299 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1300 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1301 AddToWorkList(ORNode.Val); 1302 return DAG.getSetCC(VT, ORNode, LR, Op1); 1303 } 1304 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1305 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1306 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1307 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1308 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1309 AddToWorkList(ANDNode.Val); 1310 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1311 } 1312 } 1313 // canonicalize equivalent to ll == rl 1314 if (LL == RR && LR == RL) { 1315 Op1 = ISD::getSetCCSwappedOperands(Op1); 1316 std::swap(RL, RR); 1317 } 1318 if (LL == RL && LR == RR) { 1319 bool isInteger = MVT::isInteger(LL.getValueType()); 1320 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1321 if (Result != ISD::SETCC_INVALID) 1322 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1323 } 1324 } 1325 1326 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1327 if (N0.getOpcode() == N1.getOpcode()) { 1328 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1329 if (Tmp.Val) return Tmp; 1330 } 1331 1332 // canonicalize shl to left side in a shl/srl pair, to match rotate 1333 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 1334 std::swap(N0, N1); 1335 // check for rotl, rotr 1336 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 1337 N0.getOperand(0) == N1.getOperand(0) && 1338 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 1339 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1340 if (N0.getOperand(1).getOpcode() == ISD::Constant && 1341 N1.getOperand(1).getOpcode() == ISD::Constant) { 1342 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1343 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1344 if ((c1val + c2val) == OpSizeInBits) 1345 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1346 } 1347 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1348 if (N1.getOperand(1).getOpcode() == ISD::SUB && 1349 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 1350 if (ConstantSDNode *SUBC = 1351 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 1352 if (SUBC->getValue() == OpSizeInBits) 1353 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1354 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1355 if (N0.getOperand(1).getOpcode() == ISD::SUB && 1356 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 1357 if (ConstantSDNode *SUBC = 1358 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 1359 if (SUBC->getValue() == OpSizeInBits) { 1360 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 1361 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 1362 N1.getOperand(1)); 1363 else 1364 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 1365 N0.getOperand(1)); 1366 } 1367 } 1368 return SDOperand(); 1369} 1370 1371SDOperand DAGCombiner::visitXOR(SDNode *N) { 1372 SDOperand N0 = N->getOperand(0); 1373 SDOperand N1 = N->getOperand(1); 1374 SDOperand LHS, RHS, CC; 1375 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1376 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1377 MVT::ValueType VT = N0.getValueType(); 1378 1379 // fold (xor c1, c2) -> c1^c2 1380 if (N0C && N1C) 1381 return DAG.getNode(ISD::XOR, VT, N0, N1); 1382 // canonicalize constant to RHS 1383 if (N0C && !N1C) 1384 return DAG.getNode(ISD::XOR, VT, N1, N0); 1385 // fold (xor x, 0) -> x 1386 if (N1C && N1C->isNullValue()) 1387 return N0; 1388 // reassociate xor 1389 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1390 if (RXOR.Val != 0) 1391 return RXOR; 1392 // fold !(x cc y) -> (x !cc y) 1393 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1394 bool isInt = MVT::isInteger(LHS.getValueType()); 1395 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1396 isInt); 1397 if (N0.getOpcode() == ISD::SETCC) 1398 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1399 if (N0.getOpcode() == ISD::SELECT_CC) 1400 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1401 assert(0 && "Unhandled SetCC Equivalent!"); 1402 abort(); 1403 } 1404 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1405 if (N1C && N1C->getValue() == 1 && 1406 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1407 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1408 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1409 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1410 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1411 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1412 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1413 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1414 } 1415 } 1416 // fold !(x or y) -> (!x and !y) iff x or y are constants 1417 if (N1C && N1C->isAllOnesValue() && 1418 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1419 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1420 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1421 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1422 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1423 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1424 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1425 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1426 } 1427 } 1428 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1429 if (N1C && N0.getOpcode() == ISD::XOR) { 1430 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1431 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1432 if (N00C) 1433 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1434 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1435 if (N01C) 1436 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1437 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1438 } 1439 // fold (xor x, x) -> 0 1440 if (N0 == N1) { 1441 if (!MVT::isVector(VT)) { 1442 return DAG.getConstant(0, VT); 1443 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1444 // Produce a vector of zeros. 1445 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1446 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1447 return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); 1448 } 1449 } 1450 1451 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1452 if (N0.getOpcode() == N1.getOpcode()) { 1453 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1454 if (Tmp.Val) return Tmp; 1455 } 1456 1457 // Simplify the expression using non-local knowledge. 1458 if (!MVT::isVector(VT) && 1459 SimplifyDemandedBits(SDOperand(N, 0))) 1460 return SDOperand(N, 0); 1461 1462 return SDOperand(); 1463} 1464 1465SDOperand DAGCombiner::visitSHL(SDNode *N) { 1466 SDOperand N0 = N->getOperand(0); 1467 SDOperand N1 = N->getOperand(1); 1468 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1469 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1470 MVT::ValueType VT = N0.getValueType(); 1471 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1472 1473 // fold (shl c1, c2) -> c1<<c2 1474 if (N0C && N1C) 1475 return DAG.getNode(ISD::SHL, VT, N0, N1); 1476 // fold (shl 0, x) -> 0 1477 if (N0C && N0C->isNullValue()) 1478 return N0; 1479 // fold (shl x, c >= size(x)) -> undef 1480 if (N1C && N1C->getValue() >= OpSizeInBits) 1481 return DAG.getNode(ISD::UNDEF, VT); 1482 // fold (shl x, 0) -> x 1483 if (N1C && N1C->isNullValue()) 1484 return N0; 1485 // if (shl x, c) is known to be zero, return 0 1486 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1487 return DAG.getConstant(0, VT); 1488 if (SimplifyDemandedBits(SDOperand(N, 0))) 1489 return SDOperand(N, 0); 1490 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1491 if (N1C && N0.getOpcode() == ISD::SHL && 1492 N0.getOperand(1).getOpcode() == ISD::Constant) { 1493 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1494 uint64_t c2 = N1C->getValue(); 1495 if (c1 + c2 > OpSizeInBits) 1496 return DAG.getConstant(0, VT); 1497 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1498 DAG.getConstant(c1 + c2, N1.getValueType())); 1499 } 1500 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1501 // (srl (and x, -1 << c1), c1-c2) 1502 if (N1C && N0.getOpcode() == ISD::SRL && 1503 N0.getOperand(1).getOpcode() == ISD::Constant) { 1504 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1505 uint64_t c2 = N1C->getValue(); 1506 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1507 DAG.getConstant(~0ULL << c1, VT)); 1508 if (c2 > c1) 1509 return DAG.getNode(ISD::SHL, VT, Mask, 1510 DAG.getConstant(c2-c1, N1.getValueType())); 1511 else 1512 return DAG.getNode(ISD::SRL, VT, Mask, 1513 DAG.getConstant(c1-c2, N1.getValueType())); 1514 } 1515 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1516 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1517 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1518 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1519 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) 1520 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1521 isa<ConstantSDNode>(N0.getOperand(1))) { 1522 return DAG.getNode(ISD::ADD, VT, 1523 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1), 1524 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1)); 1525 } 1526 return SDOperand(); 1527} 1528 1529SDOperand DAGCombiner::visitSRA(SDNode *N) { 1530 SDOperand N0 = N->getOperand(0); 1531 SDOperand N1 = N->getOperand(1); 1532 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1533 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1534 MVT::ValueType VT = N0.getValueType(); 1535 1536 // fold (sra c1, c2) -> c1>>c2 1537 if (N0C && N1C) 1538 return DAG.getNode(ISD::SRA, VT, N0, N1); 1539 // fold (sra 0, x) -> 0 1540 if (N0C && N0C->isNullValue()) 1541 return N0; 1542 // fold (sra -1, x) -> -1 1543 if (N0C && N0C->isAllOnesValue()) 1544 return N0; 1545 // fold (sra x, c >= size(x)) -> undef 1546 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1547 return DAG.getNode(ISD::UNDEF, VT); 1548 // fold (sra x, 0) -> x 1549 if (N1C && N1C->isNullValue()) 1550 return N0; 1551 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1552 // sext_inreg. 1553 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1554 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1555 MVT::ValueType EVT; 1556 switch (LowBits) { 1557 default: EVT = MVT::Other; break; 1558 case 1: EVT = MVT::i1; break; 1559 case 8: EVT = MVT::i8; break; 1560 case 16: EVT = MVT::i16; break; 1561 case 32: EVT = MVT::i32; break; 1562 } 1563 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1564 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1565 DAG.getValueType(EVT)); 1566 } 1567 1568 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1569 if (N1C && N0.getOpcode() == ISD::SRA) { 1570 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1571 unsigned Sum = N1C->getValue() + C1->getValue(); 1572 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1573 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1574 DAG.getConstant(Sum, N1C->getValueType(0))); 1575 } 1576 } 1577 1578 // If the sign bit is known to be zero, switch this to a SRL. 1579 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1580 return DAG.getNode(ISD::SRL, VT, N0, N1); 1581 return SDOperand(); 1582} 1583 1584SDOperand DAGCombiner::visitSRL(SDNode *N) { 1585 SDOperand N0 = N->getOperand(0); 1586 SDOperand N1 = N->getOperand(1); 1587 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1588 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1589 MVT::ValueType VT = N0.getValueType(); 1590 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1591 1592 // fold (srl c1, c2) -> c1 >>u c2 1593 if (N0C && N1C) 1594 return DAG.getNode(ISD::SRL, VT, N0, N1); 1595 // fold (srl 0, x) -> 0 1596 if (N0C && N0C->isNullValue()) 1597 return N0; 1598 // fold (srl x, c >= size(x)) -> undef 1599 if (N1C && N1C->getValue() >= OpSizeInBits) 1600 return DAG.getNode(ISD::UNDEF, VT); 1601 // fold (srl x, 0) -> x 1602 if (N1C && N1C->isNullValue()) 1603 return N0; 1604 // if (srl x, c) is known to be zero, return 0 1605 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1606 return DAG.getConstant(0, VT); 1607 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1608 if (N1C && N0.getOpcode() == ISD::SRL && 1609 N0.getOperand(1).getOpcode() == ISD::Constant) { 1610 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1611 uint64_t c2 = N1C->getValue(); 1612 if (c1 + c2 > OpSizeInBits) 1613 return DAG.getConstant(0, VT); 1614 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1615 DAG.getConstant(c1 + c2, N1.getValueType())); 1616 } 1617 1618 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1619 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1620 // Shifting in all undef bits? 1621 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1622 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1623 return DAG.getNode(ISD::UNDEF, VT); 1624 1625 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1626 AddToWorkList(SmallShift.Val); 1627 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1628 } 1629 1630 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1631 if (N1C && N0.getOpcode() == ISD::CTLZ && 1632 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1633 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1634 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1635 1636 // If any of the input bits are KnownOne, then the input couldn't be all 1637 // zeros, thus the result of the srl will always be zero. 1638 if (KnownOne) return DAG.getConstant(0, VT); 1639 1640 // If all of the bits input the to ctlz node are known to be zero, then 1641 // the result of the ctlz is "32" and the result of the shift is one. 1642 uint64_t UnknownBits = ~KnownZero & Mask; 1643 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1644 1645 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1646 if ((UnknownBits & (UnknownBits-1)) == 0) { 1647 // Okay, we know that only that the single bit specified by UnknownBits 1648 // could be set on input to the CTLZ node. If this bit is set, the SRL 1649 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1650 // to an SRL,XOR pair, which is likely to simplify more. 1651 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1652 SDOperand Op = N0.getOperand(0); 1653 if (ShAmt) { 1654 Op = DAG.getNode(ISD::SRL, VT, Op, 1655 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1656 AddToWorkList(Op.Val); 1657 } 1658 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1659 } 1660 } 1661 1662 return SDOperand(); 1663} 1664 1665SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1666 SDOperand N0 = N->getOperand(0); 1667 MVT::ValueType VT = N->getValueType(0); 1668 1669 // fold (ctlz c1) -> c2 1670 if (isa<ConstantSDNode>(N0)) 1671 return DAG.getNode(ISD::CTLZ, VT, N0); 1672 return SDOperand(); 1673} 1674 1675SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1676 SDOperand N0 = N->getOperand(0); 1677 MVT::ValueType VT = N->getValueType(0); 1678 1679 // fold (cttz c1) -> c2 1680 if (isa<ConstantSDNode>(N0)) 1681 return DAG.getNode(ISD::CTTZ, VT, N0); 1682 return SDOperand(); 1683} 1684 1685SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1686 SDOperand N0 = N->getOperand(0); 1687 MVT::ValueType VT = N->getValueType(0); 1688 1689 // fold (ctpop c1) -> c2 1690 if (isa<ConstantSDNode>(N0)) 1691 return DAG.getNode(ISD::CTPOP, VT, N0); 1692 return SDOperand(); 1693} 1694 1695SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1696 SDOperand N0 = N->getOperand(0); 1697 SDOperand N1 = N->getOperand(1); 1698 SDOperand N2 = N->getOperand(2); 1699 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1700 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1701 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1702 MVT::ValueType VT = N->getValueType(0); 1703 1704 // fold select C, X, X -> X 1705 if (N1 == N2) 1706 return N1; 1707 // fold select true, X, Y -> X 1708 if (N0C && !N0C->isNullValue()) 1709 return N1; 1710 // fold select false, X, Y -> Y 1711 if (N0C && N0C->isNullValue()) 1712 return N2; 1713 // fold select C, 1, X -> C | X 1714 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1715 return DAG.getNode(ISD::OR, VT, N0, N2); 1716 // fold select C, 0, X -> ~C & X 1717 // FIXME: this should check for C type == X type, not i1? 1718 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1719 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1720 AddToWorkList(XORNode.Val); 1721 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1722 } 1723 // fold select C, X, 1 -> ~C | X 1724 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1725 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1726 AddToWorkList(XORNode.Val); 1727 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1728 } 1729 // fold select C, X, 0 -> C & X 1730 // FIXME: this should check for C type == X type, not i1? 1731 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1732 return DAG.getNode(ISD::AND, VT, N0, N1); 1733 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1734 if (MVT::i1 == VT && N0 == N1) 1735 return DAG.getNode(ISD::OR, VT, N0, N2); 1736 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1737 if (MVT::i1 == VT && N0 == N2) 1738 return DAG.getNode(ISD::AND, VT, N0, N1); 1739 // If we can fold this based on the true/false value, do so. 1740 if (SimplifySelectOps(N, N1, N2)) 1741 return SDOperand(); 1742 // fold selects based on a setcc into other things, such as min/max/abs 1743 if (N0.getOpcode() == ISD::SETCC) 1744 // FIXME: 1745 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1746 // having to say they don't support SELECT_CC on every type the DAG knows 1747 // about, since there is no way to mark an opcode illegal at all value types 1748 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1749 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1750 N1, N2, N0.getOperand(2)); 1751 else 1752 return SimplifySelect(N0, N1, N2); 1753 return SDOperand(); 1754} 1755 1756SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1757 SDOperand N0 = N->getOperand(0); 1758 SDOperand N1 = N->getOperand(1); 1759 SDOperand N2 = N->getOperand(2); 1760 SDOperand N3 = N->getOperand(3); 1761 SDOperand N4 = N->getOperand(4); 1762 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1763 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1764 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1765 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1766 1767 // Determine if the condition we're dealing with is constant 1768 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1769 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1770 1771 // fold select_cc lhs, rhs, x, x, cc -> x 1772 if (N2 == N3) 1773 return N2; 1774 1775 // If we can fold this based on the true/false value, do so. 1776 if (SimplifySelectOps(N, N2, N3)) 1777 return SDOperand(); 1778 1779 // fold select_cc into other things, such as min/max/abs 1780 return SimplifySelectCC(N0, N1, N2, N3, CC); 1781} 1782 1783SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1784 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1785 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1786} 1787 1788SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1789 SDOperand N0 = N->getOperand(0); 1790 MVT::ValueType VT = N->getValueType(0); 1791 1792 // fold (sext c1) -> c1 1793 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 1794 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1795 1796 // fold (sext (sext x)) -> (sext x) 1797 // fold (sext (aext x)) -> (sext x) 1798 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1799 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1800 1801 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1802 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1803 (!AfterLegalize || 1804 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1805 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1806 DAG.getValueType(N0.getValueType())); 1807 1808 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1809 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1810 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1811 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1812 N0.getOperand(1), N0.getOperand(2), 1813 N0.getValueType()); 1814 CombineTo(N, ExtLoad); 1815 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1816 ExtLoad.getValue(1)); 1817 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1818 } 1819 1820 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1821 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1822 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1823 N0.hasOneUse()) { 1824 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1825 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1826 N0.getOperand(1), N0.getOperand(2), EVT); 1827 CombineTo(N, ExtLoad); 1828 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1829 ExtLoad.getValue(1)); 1830 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1831 } 1832 1833 return SDOperand(); 1834} 1835 1836SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1837 SDOperand N0 = N->getOperand(0); 1838 MVT::ValueType VT = N->getValueType(0); 1839 1840 // fold (zext c1) -> c1 1841 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 1842 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1843 // fold (zext (zext x)) -> (zext x) 1844 // fold (zext (aext x)) -> (zext x) 1845 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1846 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1847 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1848 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1849 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1850 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1851 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1852 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1853 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1854 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1855 N0.getOperand(1), N0.getOperand(2), 1856 N0.getValueType()); 1857 CombineTo(N, ExtLoad); 1858 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1859 ExtLoad.getValue(1)); 1860 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1861 } 1862 1863 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1864 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1865 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1866 N0.hasOneUse()) { 1867 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1868 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1869 N0.getOperand(1), N0.getOperand(2), EVT); 1870 CombineTo(N, ExtLoad); 1871 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1872 ExtLoad.getValue(1)); 1873 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1874 } 1875 return SDOperand(); 1876} 1877 1878SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 1879 SDOperand N0 = N->getOperand(0); 1880 MVT::ValueType VT = N->getValueType(0); 1881 1882 // fold (aext c1) -> c1 1883 if (isa<ConstantSDNode>(N0)) 1884 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 1885 // fold (aext (aext x)) -> (aext x) 1886 // fold (aext (zext x)) -> (zext x) 1887 // fold (aext (sext x)) -> (sext x) 1888 if (N0.getOpcode() == ISD::ANY_EXTEND || 1889 N0.getOpcode() == ISD::ZERO_EXTEND || 1890 N0.getOpcode() == ISD::SIGN_EXTEND) 1891 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1892 1893 // fold (aext (truncate x)) -> x iff x size == zext size. 1894 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT) 1895 return N0.getOperand(0); 1896 // fold (aext (load x)) -> (aext (truncate (extload x))) 1897 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1898 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 1899 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 1900 N0.getOperand(1), N0.getOperand(2), 1901 N0.getValueType()); 1902 CombineTo(N, ExtLoad); 1903 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1904 ExtLoad.getValue(1)); 1905 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1906 } 1907 1908 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 1909 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 1910 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 1911 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD || 1912 N0.getOpcode() == ISD::SEXTLOAD) && 1913 N0.hasOneUse()) { 1914 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1915 SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0), 1916 N0.getOperand(1), N0.getOperand(2), EVT); 1917 CombineTo(N, ExtLoad); 1918 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1919 ExtLoad.getValue(1)); 1920 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1921 } 1922 return SDOperand(); 1923} 1924 1925 1926SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1927 SDOperand N0 = N->getOperand(0); 1928 SDOperand N1 = N->getOperand(1); 1929 MVT::ValueType VT = N->getValueType(0); 1930 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1931 unsigned EVTBits = MVT::getSizeInBits(EVT); 1932 1933 // fold (sext_in_reg c1) -> c1 1934 if (isa<ConstantSDNode>(N0)) 1935 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 1936 1937 // If the input is already sign extended, just drop the extension. 1938 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 1939 return N0; 1940 1941 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1942 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1943 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1944 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1945 } 1946 1947 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1948 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1949 return DAG.getZeroExtendInReg(N0, EVT); 1950 // fold (sext_inreg (extload x)) -> (sextload x) 1951 if (N0.getOpcode() == ISD::EXTLOAD && 1952 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1953 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1954 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1955 N0.getOperand(1), N0.getOperand(2), 1956 EVT); 1957 CombineTo(N, ExtLoad); 1958 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1959 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1960 } 1961 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1962 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1963 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1964 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1965 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1966 N0.getOperand(1), N0.getOperand(2), 1967 EVT); 1968 CombineTo(N, ExtLoad); 1969 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1970 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1971 } 1972 return SDOperand(); 1973} 1974 1975SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1976 SDOperand N0 = N->getOperand(0); 1977 MVT::ValueType VT = N->getValueType(0); 1978 1979 // noop truncate 1980 if (N0.getValueType() == N->getValueType(0)) 1981 return N0; 1982 // fold (truncate c1) -> c1 1983 if (isa<ConstantSDNode>(N0)) 1984 return DAG.getNode(ISD::TRUNCATE, VT, N0); 1985 // fold (truncate (truncate x)) -> (truncate x) 1986 if (N0.getOpcode() == ISD::TRUNCATE) 1987 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1988 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1989 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 1990 N0.getOpcode() == ISD::ANY_EXTEND) { 1991 if (N0.getValueType() < VT) 1992 // if the source is smaller than the dest, we still need an extend 1993 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1994 else if (N0.getValueType() > VT) 1995 // if the source is larger than the dest, than we just need the truncate 1996 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1997 else 1998 // if the source and dest are the same type, we can drop both the extend 1999 // and the truncate 2000 return N0.getOperand(0); 2001 } 2002 // fold (truncate (load x)) -> (smaller load x) 2003 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 2004 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 2005 "Cannot truncate to larger type!"); 2006 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2007 // For big endian targets, we need to add an offset to the pointer to load 2008 // the correct bytes. For little endian systems, we merely need to read 2009 // fewer bytes from the same pointer. 2010 uint64_t PtrOff = 2011 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 2012 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 2013 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 2014 DAG.getConstant(PtrOff, PtrType)); 2015 AddToWorkList(NewPtr.Val); 2016 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 2017 AddToWorkList(N); 2018 CombineTo(N0.Val, Load, Load.getValue(1)); 2019 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2020 } 2021 return SDOperand(); 2022} 2023 2024SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2025 SDOperand N0 = N->getOperand(0); 2026 MVT::ValueType VT = N->getValueType(0); 2027 2028 // If the input is a constant, let getNode() fold it. 2029 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2030 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2031 if (Res.Val != N) return Res; 2032 } 2033 2034 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2035 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2036 2037 // fold (conv (load x)) -> (load (conv*)x) 2038 // FIXME: These xforms need to know that the resultant load doesn't need a 2039 // higher alignment than the original! 2040 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 2041 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 2042 N0.getOperand(2)); 2043 AddToWorkList(N); 2044 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2045 Load.getValue(1)); 2046 return Load; 2047 } 2048 2049 return SDOperand(); 2050} 2051 2052SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2053 SDOperand N0 = N->getOperand(0); 2054 MVT::ValueType VT = N->getValueType(0); 2055 2056 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2057 // First check to see if this is all constant. 2058 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2059 VT == MVT::Vector) { 2060 bool isSimple = true; 2061 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2062 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2063 N0.getOperand(i).getOpcode() != ISD::Constant && 2064 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2065 isSimple = false; 2066 break; 2067 } 2068 2069 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2070 if (isSimple && !MVT::isVector(DestEltVT)) { 2071 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2072 } 2073 } 2074 2075 return SDOperand(); 2076} 2077 2078/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2079/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2080/// destination element value type. 2081SDOperand DAGCombiner:: 2082ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2083 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2084 2085 // If this is already the right type, we're done. 2086 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2087 2088 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2089 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2090 2091 // If this is a conversion of N elements of one type to N elements of another 2092 // type, convert each element. This handles FP<->INT cases. 2093 if (SrcBitSize == DstBitSize) { 2094 std::vector<SDOperand> Ops; 2095 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2096 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2097 AddToWorkList(Ops.back().Val); 2098 } 2099 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2100 Ops.push_back(DAG.getValueType(DstEltVT)); 2101 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2102 } 2103 2104 // Otherwise, we're growing or shrinking the elements. To avoid having to 2105 // handle annoying details of growing/shrinking FP values, we convert them to 2106 // int first. 2107 if (MVT::isFloatingPoint(SrcEltVT)) { 2108 // Convert the input float vector to a int vector where the elements are the 2109 // same sizes. 2110 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2111 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2112 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2113 SrcEltVT = IntVT; 2114 } 2115 2116 // Now we know the input is an integer vector. If the output is a FP type, 2117 // convert to integer first, then to FP of the right size. 2118 if (MVT::isFloatingPoint(DstEltVT)) { 2119 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2120 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2121 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2122 2123 // Next, convert to FP elements of the same size. 2124 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2125 } 2126 2127 // Okay, we know the src/dst types are both integers of differing types. 2128 // Handling growing first. 2129 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2130 if (SrcBitSize < DstBitSize) { 2131 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2132 2133 std::vector<SDOperand> Ops; 2134 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2135 i += NumInputsPerOutput) { 2136 bool isLE = TLI.isLittleEndian(); 2137 uint64_t NewBits = 0; 2138 bool EltIsUndef = true; 2139 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2140 // Shift the previously computed bits over. 2141 NewBits <<= SrcBitSize; 2142 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2143 if (Op.getOpcode() == ISD::UNDEF) continue; 2144 EltIsUndef = false; 2145 2146 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2147 } 2148 2149 if (EltIsUndef) 2150 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2151 else 2152 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2153 } 2154 2155 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2156 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2157 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2158 } 2159 2160 // Finally, this must be the case where we are shrinking elements: each input 2161 // turns into multiple outputs. 2162 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2163 std::vector<SDOperand> Ops; 2164 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2165 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2166 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2167 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2168 continue; 2169 } 2170 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2171 2172 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2173 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2174 OpVal >>= DstBitSize; 2175 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2176 } 2177 2178 // For big endian targets, swap the order of the pieces of each element. 2179 if (!TLI.isLittleEndian()) 2180 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2181 } 2182 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2183 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2184 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2185} 2186 2187 2188 2189SDOperand DAGCombiner::visitFADD(SDNode *N) { 2190 SDOperand N0 = N->getOperand(0); 2191 SDOperand N1 = N->getOperand(1); 2192 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2193 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2194 MVT::ValueType VT = N->getValueType(0); 2195 2196 // fold (fadd c1, c2) -> c1+c2 2197 if (N0CFP && N1CFP) 2198 return DAG.getNode(ISD::FADD, VT, N0, N1); 2199 // canonicalize constant to RHS 2200 if (N0CFP && !N1CFP) 2201 return DAG.getNode(ISD::FADD, VT, N1, N0); 2202 // fold (A + (-B)) -> A-B 2203 if (N1.getOpcode() == ISD::FNEG) 2204 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2205 // fold ((-A) + B) -> B-A 2206 if (N0.getOpcode() == ISD::FNEG) 2207 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2208 return SDOperand(); 2209} 2210 2211SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2212 SDOperand N0 = N->getOperand(0); 2213 SDOperand N1 = N->getOperand(1); 2214 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2215 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2216 MVT::ValueType VT = N->getValueType(0); 2217 2218 // fold (fsub c1, c2) -> c1-c2 2219 if (N0CFP && N1CFP) 2220 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2221 // fold (A-(-B)) -> A+B 2222 if (N1.getOpcode() == ISD::FNEG) 2223 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2224 return SDOperand(); 2225} 2226 2227SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2228 SDOperand N0 = N->getOperand(0); 2229 SDOperand N1 = N->getOperand(1); 2230 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2231 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2232 MVT::ValueType VT = N->getValueType(0); 2233 2234 // fold (fmul c1, c2) -> c1*c2 2235 if (N0CFP && N1CFP) 2236 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2237 // canonicalize constant to RHS 2238 if (N0CFP && !N1CFP) 2239 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2240 // fold (fmul X, 2.0) -> (fadd X, X) 2241 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2242 return DAG.getNode(ISD::FADD, VT, N0, N0); 2243 return SDOperand(); 2244} 2245 2246SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2247 SDOperand N0 = N->getOperand(0); 2248 SDOperand N1 = N->getOperand(1); 2249 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2250 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2251 MVT::ValueType VT = N->getValueType(0); 2252 2253 // fold (fdiv c1, c2) -> c1/c2 2254 if (N0CFP && N1CFP) 2255 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2256 return SDOperand(); 2257} 2258 2259SDOperand DAGCombiner::visitFREM(SDNode *N) { 2260 SDOperand N0 = N->getOperand(0); 2261 SDOperand N1 = N->getOperand(1); 2262 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2263 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2264 MVT::ValueType VT = N->getValueType(0); 2265 2266 // fold (frem c1, c2) -> fmod(c1,c2) 2267 if (N0CFP && N1CFP) 2268 return DAG.getNode(ISD::FREM, VT, N0, N1); 2269 return SDOperand(); 2270} 2271 2272SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2273 SDOperand N0 = N->getOperand(0); 2274 SDOperand N1 = N->getOperand(1); 2275 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2276 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2277 MVT::ValueType VT = N->getValueType(0); 2278 2279 if (N0CFP && N1CFP) // Constant fold 2280 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2281 2282 if (N1CFP) { 2283 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2284 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2285 union { 2286 double d; 2287 int64_t i; 2288 } u; 2289 u.d = N1CFP->getValue(); 2290 if (u.i >= 0) 2291 return DAG.getNode(ISD::FABS, VT, N0); 2292 else 2293 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2294 } 2295 2296 // copysign(fabs(x), y) -> copysign(x, y) 2297 // copysign(fneg(x), y) -> copysign(x, y) 2298 // copysign(copysign(x,z), y) -> copysign(x, y) 2299 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2300 N0.getOpcode() == ISD::FCOPYSIGN) 2301 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2302 2303 // copysign(x, abs(y)) -> abs(x) 2304 if (N1.getOpcode() == ISD::FABS) 2305 return DAG.getNode(ISD::FABS, VT, N0); 2306 2307 // copysign(x, copysign(y,z)) -> copysign(x, z) 2308 if (N1.getOpcode() == ISD::FCOPYSIGN) 2309 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2310 2311 // copysign(x, fp_extend(y)) -> copysign(x, y) 2312 // copysign(x, fp_round(y)) -> copysign(x, y) 2313 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2314 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2315 2316 return SDOperand(); 2317} 2318 2319 2320 2321SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2322 SDOperand N0 = N->getOperand(0); 2323 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2324 MVT::ValueType VT = N->getValueType(0); 2325 2326 // fold (sint_to_fp c1) -> c1fp 2327 if (N0C) 2328 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2329 return SDOperand(); 2330} 2331 2332SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2333 SDOperand N0 = N->getOperand(0); 2334 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2335 MVT::ValueType VT = N->getValueType(0); 2336 2337 // fold (uint_to_fp c1) -> c1fp 2338 if (N0C) 2339 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2340 return SDOperand(); 2341} 2342 2343SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2344 SDOperand N0 = N->getOperand(0); 2345 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2346 MVT::ValueType VT = N->getValueType(0); 2347 2348 // fold (fp_to_sint c1fp) -> c1 2349 if (N0CFP) 2350 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2351 return SDOperand(); 2352} 2353 2354SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2355 SDOperand N0 = N->getOperand(0); 2356 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2357 MVT::ValueType VT = N->getValueType(0); 2358 2359 // fold (fp_to_uint c1fp) -> c1 2360 if (N0CFP) 2361 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2362 return SDOperand(); 2363} 2364 2365SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2366 SDOperand N0 = N->getOperand(0); 2367 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2368 MVT::ValueType VT = N->getValueType(0); 2369 2370 // fold (fp_round c1fp) -> c1fp 2371 if (N0CFP) 2372 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2373 2374 // fold (fp_round (fp_extend x)) -> x 2375 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2376 return N0.getOperand(0); 2377 2378 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2379 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2380 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2381 AddToWorkList(Tmp.Val); 2382 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2383 } 2384 2385 return SDOperand(); 2386} 2387 2388SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2389 SDOperand N0 = N->getOperand(0); 2390 MVT::ValueType VT = N->getValueType(0); 2391 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2392 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2393 2394 // fold (fp_round_inreg c1fp) -> c1fp 2395 if (N0CFP) { 2396 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2397 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2398 } 2399 return SDOperand(); 2400} 2401 2402SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2403 SDOperand N0 = N->getOperand(0); 2404 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2405 MVT::ValueType VT = N->getValueType(0); 2406 2407 // fold (fp_extend c1fp) -> c1fp 2408 if (N0CFP) 2409 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2410 2411 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2412 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 2413 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 2414 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 2415 N0.getOperand(1), N0.getOperand(2), 2416 N0.getValueType()); 2417 CombineTo(N, ExtLoad); 2418 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2419 ExtLoad.getValue(1)); 2420 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2421 } 2422 2423 2424 return SDOperand(); 2425} 2426 2427SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2428 SDOperand N0 = N->getOperand(0); 2429 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2430 MVT::ValueType VT = N->getValueType(0); 2431 2432 // fold (fneg c1) -> -c1 2433 if (N0CFP) 2434 return DAG.getNode(ISD::FNEG, VT, N0); 2435 // fold (fneg (sub x, y)) -> (sub y, x) 2436 if (N0.getOpcode() == ISD::SUB) 2437 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2438 // fold (fneg (fneg x)) -> x 2439 if (N0.getOpcode() == ISD::FNEG) 2440 return N0.getOperand(0); 2441 return SDOperand(); 2442} 2443 2444SDOperand DAGCombiner::visitFABS(SDNode *N) { 2445 SDOperand N0 = N->getOperand(0); 2446 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2447 MVT::ValueType VT = N->getValueType(0); 2448 2449 // fold (fabs c1) -> fabs(c1) 2450 if (N0CFP) 2451 return DAG.getNode(ISD::FABS, VT, N0); 2452 // fold (fabs (fabs x)) -> (fabs x) 2453 if (N0.getOpcode() == ISD::FABS) 2454 return N->getOperand(0); 2455 // fold (fabs (fneg x)) -> (fabs x) 2456 // fold (fabs (fcopysign x, y)) -> (fabs x) 2457 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2458 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2459 2460 return SDOperand(); 2461} 2462 2463SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2464 SDOperand Chain = N->getOperand(0); 2465 SDOperand N1 = N->getOperand(1); 2466 SDOperand N2 = N->getOperand(2); 2467 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2468 2469 // never taken branch, fold to chain 2470 if (N1C && N1C->isNullValue()) 2471 return Chain; 2472 // unconditional branch 2473 if (N1C && N1C->getValue() == 1) 2474 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2475 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2476 // on the target. 2477 if (N1.getOpcode() == ISD::SETCC && 2478 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2479 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2480 N1.getOperand(0), N1.getOperand(1), N2); 2481 } 2482 return SDOperand(); 2483} 2484 2485// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2486// 2487SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2488 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2489 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2490 2491 // Use SimplifySetCC to simplify SETCC's. 2492 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2493 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2494 2495 // fold br_cc true, dest -> br dest (unconditional branch) 2496 if (SCCC && SCCC->getValue()) 2497 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2498 N->getOperand(4)); 2499 // fold br_cc false, dest -> unconditional fall through 2500 if (SCCC && SCCC->isNullValue()) 2501 return N->getOperand(0); 2502 // fold to a simpler setcc 2503 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2504 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2505 Simp.getOperand(2), Simp.getOperand(0), 2506 Simp.getOperand(1), N->getOperand(4)); 2507 return SDOperand(); 2508} 2509 2510SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2511 SDOperand Chain = N->getOperand(0); 2512 SDOperand Ptr = N->getOperand(1); 2513 SDOperand SrcValue = N->getOperand(2); 2514 2515 // If there are no uses of the loaded value, change uses of the chain value 2516 // into uses of the chain input (i.e. delete the dead load). 2517 if (N->hasNUsesOfValue(0, 0)) 2518 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2519 2520 // If this load is directly stored, replace the load value with the stored 2521 // value. 2522 // TODO: Handle store large -> read small portion. 2523 // TODO: Handle TRUNCSTORE/EXTLOAD 2524 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2525 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2526 return CombineTo(N, Chain.getOperand(1), Chain); 2527 2528 return SDOperand(); 2529} 2530 2531/// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD. 2532SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) { 2533 SDOperand Chain = N->getOperand(0); 2534 SDOperand Ptr = N->getOperand(1); 2535 SDOperand SrcValue = N->getOperand(2); 2536 SDOperand EVT = N->getOperand(3); 2537 2538 // If there are no uses of the loaded value, change uses of the chain value 2539 // into uses of the chain input (i.e. delete the dead load). 2540 if (N->hasNUsesOfValue(0, 0)) 2541 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2542 2543 return SDOperand(); 2544} 2545 2546SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2547 SDOperand Chain = N->getOperand(0); 2548 SDOperand Value = N->getOperand(1); 2549 SDOperand Ptr = N->getOperand(2); 2550 SDOperand SrcValue = N->getOperand(3); 2551 2552 // If this is a store that kills a previous store, remove the previous store. 2553 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2554 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2555 // Make sure that these stores are the same value type: 2556 // FIXME: we really care that the second store is >= size of the first. 2557 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2558 // Create a new store of Value that replaces both stores. 2559 SDNode *PrevStore = Chain.Val; 2560 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2561 return Chain; 2562 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2563 PrevStore->getOperand(0), Value, Ptr, 2564 SrcValue); 2565 CombineTo(N, NewStore); // Nuke this store. 2566 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2567 return SDOperand(N, 0); 2568 } 2569 2570 // If this is a store of a bit convert, store the input value. 2571 // FIXME: This needs to know that the resultant store does not need a 2572 // higher alignment than the original. 2573 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2574 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2575 Ptr, SrcValue); 2576 2577 return SDOperand(); 2578} 2579 2580SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 2581 SDOperand InVec = N->getOperand(0); 2582 SDOperand InVal = N->getOperand(1); 2583 SDOperand EltNo = N->getOperand(2); 2584 2585 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 2586 // vector with the inserted element. 2587 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2588 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2589 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2590 if (Elt < Ops.size()) 2591 Ops[Elt] = InVal; 2592 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops); 2593 } 2594 2595 return SDOperand(); 2596} 2597 2598SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 2599 SDOperand InVec = N->getOperand(0); 2600 SDOperand InVal = N->getOperand(1); 2601 SDOperand EltNo = N->getOperand(2); 2602 SDOperand NumElts = N->getOperand(3); 2603 SDOperand EltType = N->getOperand(4); 2604 2605 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 2606 // vector with the inserted element. 2607 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2608 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2609 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2610 if (Elt < Ops.size()-2) 2611 Ops[Elt] = InVal; 2612 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops); 2613 } 2614 2615 return SDOperand(); 2616} 2617 2618SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 2619 unsigned NumInScalars = N->getNumOperands()-2; 2620 SDOperand NumElts = N->getOperand(NumInScalars); 2621 SDOperand EltType = N->getOperand(NumInScalars+1); 2622 2623 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 2624 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 2625 // two distinct vectors, turn this into a shuffle node. 2626 SDOperand VecIn1, VecIn2; 2627 for (unsigned i = 0; i != NumInScalars; ++i) { 2628 // Ignore undef inputs. 2629 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 2630 2631 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 2632 // constant index, bail out. 2633 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 2634 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 2635 VecIn1 = VecIn2 = SDOperand(0, 0); 2636 break; 2637 } 2638 2639 // If the input vector type disagrees with the result of the vbuild_vector, 2640 // we can't make a shuffle. 2641 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 2642 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 2643 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 2644 VecIn1 = VecIn2 = SDOperand(0, 0); 2645 break; 2646 } 2647 2648 // Otherwise, remember this. We allow up to two distinct input vectors. 2649 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 2650 continue; 2651 2652 if (VecIn1.Val == 0) { 2653 VecIn1 = ExtractedFromVec; 2654 } else if (VecIn2.Val == 0) { 2655 VecIn2 = ExtractedFromVec; 2656 } else { 2657 // Too many inputs. 2658 VecIn1 = VecIn2 = SDOperand(0, 0); 2659 break; 2660 } 2661 } 2662 2663 // If everything is good, we can make a shuffle operation. 2664 if (VecIn1.Val) { 2665 std::vector<SDOperand> BuildVecIndices; 2666 for (unsigned i = 0; i != NumInScalars; ++i) { 2667 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 2668 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 2669 continue; 2670 } 2671 2672 SDOperand Extract = N->getOperand(i); 2673 2674 // If extracting from the first vector, just use the index directly. 2675 if (Extract.getOperand(0) == VecIn1) { 2676 BuildVecIndices.push_back(Extract.getOperand(1)); 2677 continue; 2678 } 2679 2680 // Otherwise, use InIdx + VecSize 2681 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 2682 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32)); 2683 } 2684 2685 // Add count and size info. 2686 BuildVecIndices.push_back(NumElts); 2687 BuildVecIndices.push_back(DAG.getValueType(MVT::i32)); 2688 2689 // Return the new VVECTOR_SHUFFLE node. 2690 std::vector<SDOperand> Ops; 2691 Ops.push_back(VecIn1); 2692 if (VecIn2.Val) { 2693 Ops.push_back(VecIn2); 2694 } else { 2695 // Use an undef vbuild_vector as input for the second operand. 2696 std::vector<SDOperand> UnOps(NumInScalars, 2697 DAG.getNode(ISD::UNDEF, 2698 cast<VTSDNode>(EltType)->getVT())); 2699 UnOps.push_back(NumElts); 2700 UnOps.push_back(EltType); 2701 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps)); 2702 AddToWorkList(Ops.back().Val); 2703 } 2704 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices)); 2705 Ops.push_back(NumElts); 2706 Ops.push_back(EltType); 2707 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops); 2708 } 2709 2710 return SDOperand(); 2711} 2712 2713SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 2714 SDOperand ShufMask = N->getOperand(2); 2715 unsigned NumElts = ShufMask.getNumOperands(); 2716 2717 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2718 bool isIdentity = true; 2719 for (unsigned i = 0; i != NumElts; ++i) { 2720 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2721 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2722 isIdentity = false; 2723 break; 2724 } 2725 } 2726 if (isIdentity) return N->getOperand(0); 2727 2728 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2729 isIdentity = true; 2730 for (unsigned i = 0; i != NumElts; ++i) { 2731 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2732 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2733 isIdentity = false; 2734 break; 2735 } 2736 } 2737 if (isIdentity) return N->getOperand(1); 2738 2739 // If the LHS and the RHS are the same node, turn the RHS into an undef. 2740 if (N->getOperand(0) == N->getOperand(1)) { 2741 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 2742 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 2743 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 2744 // first operand. 2745 std::vector<SDOperand> MappedOps; 2746 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 2747 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 2748 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 2749 MappedOps.push_back(ShufMask.getOperand(i)); 2750 } else { 2751 unsigned NewIdx = 2752 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 2753 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 2754 } 2755 } 2756 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 2757 MappedOps); 2758 AddToWorkList(ShufMask.Val); 2759 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 2760 N->getOperand(0), 2761 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 2762 ShufMask); 2763 } 2764 2765 return SDOperand(); 2766} 2767 2768SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 2769 SDOperand ShufMask = N->getOperand(2); 2770 unsigned NumElts = ShufMask.getNumOperands()-2; 2771 2772 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2773 bool isIdentity = true; 2774 for (unsigned i = 0; i != NumElts; ++i) { 2775 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2776 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2777 isIdentity = false; 2778 break; 2779 } 2780 } 2781 if (isIdentity) return N->getOperand(0); 2782 2783 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2784 isIdentity = true; 2785 for (unsigned i = 0; i != NumElts; ++i) { 2786 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2787 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2788 isIdentity = false; 2789 break; 2790 } 2791 } 2792 if (isIdentity) return N->getOperand(1); 2793 2794 // If the LHS and the RHS are the same node, turn the RHS into an undef. 2795 if (N->getOperand(0) == N->getOperand(1)) { 2796 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 2797 // first operand. 2798 std::vector<SDOperand> MappedOps; 2799 for (unsigned i = 0; i != NumElts; ++i) { 2800 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 2801 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 2802 MappedOps.push_back(ShufMask.getOperand(i)); 2803 } else { 2804 unsigned NewIdx = 2805 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 2806 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 2807 } 2808 } 2809 // Add the type/#elts values. 2810 MappedOps.push_back(ShufMask.getOperand(NumElts)); 2811 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 2812 2813 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 2814 MappedOps); 2815 AddToWorkList(ShufMask.Val); 2816 2817 // Build the undef vector. 2818 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 2819 for (unsigned i = 0; i != NumElts; ++i) 2820 MappedOps[i] = UDVal; 2821 MappedOps[NumElts ] = *(N->getOperand(0).Val->op_end()-2); 2822 MappedOps[NumElts+1] = *(N->getOperand(0).Val->op_end()-1); 2823 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps); 2824 2825 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 2826 N->getOperand(0), UDVal, ShufMask, 2827 MappedOps[NumElts], MappedOps[NumElts+1]); 2828 } 2829 2830 return SDOperand(); 2831} 2832 2833/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 2834/// a VAND to a vector_shuffle with the destination vector and a zero vector. 2835/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 2836/// vector_shuffle V, Zero, <0, 4, 2, 4> 2837SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 2838 SDOperand LHS = N->getOperand(0); 2839 SDOperand RHS = N->getOperand(1); 2840 if (N->getOpcode() == ISD::VAND) { 2841 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 2842 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 2843 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 2844 RHS = RHS.getOperand(0); 2845 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 2846 std::vector<SDOperand> IdxOps; 2847 unsigned NumOps = RHS.getNumOperands(); 2848 unsigned NumElts = NumOps-2; 2849 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 2850 for (unsigned i = 0; i != NumElts; ++i) { 2851 SDOperand Elt = RHS.getOperand(i); 2852 if (!isa<ConstantSDNode>(Elt)) 2853 return SDOperand(); 2854 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 2855 IdxOps.push_back(DAG.getConstant(i, EVT)); 2856 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 2857 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 2858 else 2859 return SDOperand(); 2860 } 2861 2862 // Let's see if the target supports this vector_shuffle. 2863 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 2864 return SDOperand(); 2865 2866 // Return the new VVECTOR_SHUFFLE node. 2867 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 2868 SDOperand EVTNode = DAG.getValueType(EVT); 2869 std::vector<SDOperand> Ops; 2870 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, EVTNode); 2871 Ops.push_back(LHS); 2872 AddToWorkList(LHS.Val); 2873 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 2874 ZeroOps.push_back(NumEltsNode); 2875 ZeroOps.push_back(EVTNode); 2876 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps)); 2877 IdxOps.push_back(NumEltsNode); 2878 IdxOps.push_back(EVTNode); 2879 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps)); 2880 Ops.push_back(NumEltsNode); 2881 Ops.push_back(EVTNode); 2882 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops); 2883 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 2884 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 2885 DstVecSize, DstVecEVT); 2886 } 2887 return Result; 2888 } 2889 } 2890 return SDOperand(); 2891} 2892 2893/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 2894/// the scalar operation of the vop if it is operating on an integer vector 2895/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 2896SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 2897 ISD::NodeType FPOp) { 2898 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 2899 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 2900 SDOperand LHS = N->getOperand(0); 2901 SDOperand RHS = N->getOperand(1); 2902 SDOperand Shuffle = XformToShuffleWithZero(N); 2903 if (Shuffle.Val) return Shuffle; 2904 2905 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 2906 // this operation. 2907 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 2908 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 2909 std::vector<SDOperand> Ops; 2910 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 2911 SDOperand LHSOp = LHS.getOperand(i); 2912 SDOperand RHSOp = RHS.getOperand(i); 2913 // If these two elements can't be folded, bail out. 2914 if ((LHSOp.getOpcode() != ISD::UNDEF && 2915 LHSOp.getOpcode() != ISD::Constant && 2916 LHSOp.getOpcode() != ISD::ConstantFP) || 2917 (RHSOp.getOpcode() != ISD::UNDEF && 2918 RHSOp.getOpcode() != ISD::Constant && 2919 RHSOp.getOpcode() != ISD::ConstantFP)) 2920 break; 2921 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 2922 AddToWorkList(Ops.back().Val); 2923 assert((Ops.back().getOpcode() == ISD::UNDEF || 2924 Ops.back().getOpcode() == ISD::Constant || 2925 Ops.back().getOpcode() == ISD::ConstantFP) && 2926 "Scalar binop didn't fold!"); 2927 } 2928 2929 if (Ops.size() == LHS.getNumOperands()-2) { 2930 Ops.push_back(*(LHS.Val->op_end()-2)); 2931 Ops.push_back(*(LHS.Val->op_end()-1)); 2932 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2933 } 2934 } 2935 2936 return SDOperand(); 2937} 2938 2939SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2940 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2941 2942 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2943 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2944 // If we got a simplified select_cc node back from SimplifySelectCC, then 2945 // break it down into a new SETCC node, and a new SELECT node, and then return 2946 // the SELECT node, since we were called with a SELECT node. 2947 if (SCC.Val) { 2948 // Check to see if we got a select_cc back (to turn into setcc/select). 2949 // Otherwise, just return whatever node we got back, like fabs. 2950 if (SCC.getOpcode() == ISD::SELECT_CC) { 2951 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2952 SCC.getOperand(0), SCC.getOperand(1), 2953 SCC.getOperand(4)); 2954 AddToWorkList(SETCC.Val); 2955 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2956 SCC.getOperand(3), SETCC); 2957 } 2958 return SCC; 2959 } 2960 return SDOperand(); 2961} 2962 2963/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2964/// are the two values being selected between, see if we can simplify the 2965/// select. 2966/// 2967bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2968 SDOperand RHS) { 2969 2970 // If this is a select from two identical things, try to pull the operation 2971 // through the select. 2972 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2973#if 0 2974 std::cerr << "SELECT: ["; LHS.Val->dump(); 2975 std::cerr << "] ["; RHS.Val->dump(); 2976 std::cerr << "]\n"; 2977#endif 2978 2979 // If this is a load and the token chain is identical, replace the select 2980 // of two loads with a load through a select of the address to load from. 2981 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2982 // constants have been dropped into the constant pool. 2983 if ((LHS.getOpcode() == ISD::LOAD || 2984 LHS.getOpcode() == ISD::EXTLOAD || 2985 LHS.getOpcode() == ISD::ZEXTLOAD || 2986 LHS.getOpcode() == ISD::SEXTLOAD) && 2987 // Token chains must be identical. 2988 LHS.getOperand(0) == RHS.getOperand(0) && 2989 // If this is an EXTLOAD, the VT's must match. 2990 (LHS.getOpcode() == ISD::LOAD || 2991 LHS.getOperand(3) == RHS.getOperand(3))) { 2992 // FIXME: this conflates two src values, discarding one. This is not 2993 // the right thing to do, but nothing uses srcvalues now. When they do, 2994 // turn SrcValue into a list of locations. 2995 SDOperand Addr; 2996 if (TheSelect->getOpcode() == ISD::SELECT) 2997 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2998 TheSelect->getOperand(0), LHS.getOperand(1), 2999 RHS.getOperand(1)); 3000 else 3001 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 3002 TheSelect->getOperand(0), 3003 TheSelect->getOperand(1), 3004 LHS.getOperand(1), RHS.getOperand(1), 3005 TheSelect->getOperand(4)); 3006 3007 SDOperand Load; 3008 if (LHS.getOpcode() == ISD::LOAD) 3009 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 3010 Addr, LHS.getOperand(2)); 3011 else 3012 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 3013 LHS.getOperand(0), Addr, LHS.getOperand(2), 3014 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 3015 // Users of the select now use the result of the load. 3016 CombineTo(TheSelect, Load); 3017 3018 // Users of the old loads now use the new load's chain. We know the 3019 // old-load value is dead now. 3020 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 3021 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 3022 return true; 3023 } 3024 } 3025 3026 return false; 3027} 3028 3029SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 3030 SDOperand N2, SDOperand N3, 3031 ISD::CondCode CC) { 3032 3033 MVT::ValueType VT = N2.getValueType(); 3034 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 3035 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 3036 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 3037 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 3038 3039 // Determine if the condition we're dealing with is constant 3040 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 3041 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 3042 3043 // fold select_cc true, x, y -> x 3044 if (SCCC && SCCC->getValue()) 3045 return N2; 3046 // fold select_cc false, x, y -> y 3047 if (SCCC && SCCC->getValue() == 0) 3048 return N3; 3049 3050 // Check to see if we can simplify the select into an fabs node 3051 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 3052 // Allow either -0.0 or 0.0 3053 if (CFP->getValue() == 0.0) { 3054 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 3055 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 3056 N0 == N2 && N3.getOpcode() == ISD::FNEG && 3057 N2 == N3.getOperand(0)) 3058 return DAG.getNode(ISD::FABS, VT, N0); 3059 3060 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 3061 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 3062 N0 == N3 && N2.getOpcode() == ISD::FNEG && 3063 N2.getOperand(0) == N3) 3064 return DAG.getNode(ISD::FABS, VT, N3); 3065 } 3066 } 3067 3068 // Check to see if we can perform the "gzip trick", transforming 3069 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 3070 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 3071 MVT::isInteger(N0.getValueType()) && 3072 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 3073 MVT::ValueType XType = N0.getValueType(); 3074 MVT::ValueType AType = N2.getValueType(); 3075 if (XType >= AType) { 3076 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 3077 // single-bit constant. 3078 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 3079 unsigned ShCtV = Log2_64(N2C->getValue()); 3080 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 3081 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 3082 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 3083 AddToWorkList(Shift.Val); 3084 if (XType > AType) { 3085 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3086 AddToWorkList(Shift.Val); 3087 } 3088 return DAG.getNode(ISD::AND, AType, Shift, N2); 3089 } 3090 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3091 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3092 TLI.getShiftAmountTy())); 3093 AddToWorkList(Shift.Val); 3094 if (XType > AType) { 3095 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3096 AddToWorkList(Shift.Val); 3097 } 3098 return DAG.getNode(ISD::AND, AType, Shift, N2); 3099 } 3100 } 3101 3102 // fold select C, 16, 0 -> shl C, 4 3103 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 3104 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 3105 // Get a SetCC of the condition 3106 // FIXME: Should probably make sure that setcc is legal if we ever have a 3107 // target where it isn't. 3108 SDOperand Temp, SCC; 3109 // cast from setcc result type to select result type 3110 if (AfterLegalize) { 3111 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3112 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 3113 } else { 3114 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 3115 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 3116 } 3117 AddToWorkList(SCC.Val); 3118 AddToWorkList(Temp.Val); 3119 // shl setcc result by log2 n2c 3120 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 3121 DAG.getConstant(Log2_64(N2C->getValue()), 3122 TLI.getShiftAmountTy())); 3123 } 3124 3125 // Check to see if this is the equivalent of setcc 3126 // FIXME: Turn all of these into setcc if setcc if setcc is legal 3127 // otherwise, go ahead with the folds. 3128 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 3129 MVT::ValueType XType = N0.getValueType(); 3130 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 3131 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3132 if (Res.getValueType() != VT) 3133 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 3134 return Res; 3135 } 3136 3137 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 3138 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 3139 TLI.isOperationLegal(ISD::CTLZ, XType)) { 3140 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 3141 return DAG.getNode(ISD::SRL, XType, Ctlz, 3142 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 3143 TLI.getShiftAmountTy())); 3144 } 3145 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 3146 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 3147 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 3148 N0); 3149 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 3150 DAG.getConstant(~0ULL, XType)); 3151 return DAG.getNode(ISD::SRL, XType, 3152 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 3153 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3154 TLI.getShiftAmountTy())); 3155 } 3156 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 3157 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 3158 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 3159 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3160 TLI.getShiftAmountTy())); 3161 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 3162 } 3163 } 3164 3165 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 3166 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 3167 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 3168 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 3169 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 3170 MVT::ValueType XType = N0.getValueType(); 3171 if (SubC->isNullValue() && MVT::isInteger(XType)) { 3172 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3173 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3174 TLI.getShiftAmountTy())); 3175 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 3176 AddToWorkList(Shift.Val); 3177 AddToWorkList(Add.Val); 3178 return DAG.getNode(ISD::XOR, XType, Add, Shift); 3179 } 3180 } 3181 } 3182 3183 return SDOperand(); 3184} 3185 3186SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 3187 SDOperand N1, ISD::CondCode Cond, 3188 bool foldBooleans) { 3189 // These setcc operations always fold. 3190 switch (Cond) { 3191 default: break; 3192 case ISD::SETFALSE: 3193 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 3194 case ISD::SETTRUE: 3195 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 3196 } 3197 3198 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 3199 uint64_t C1 = N1C->getValue(); 3200 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 3201 uint64_t C0 = N0C->getValue(); 3202 3203 // Sign extend the operands if required 3204 if (ISD::isSignedIntSetCC(Cond)) { 3205 C0 = N0C->getSignExtended(); 3206 C1 = N1C->getSignExtended(); 3207 } 3208 3209 switch (Cond) { 3210 default: assert(0 && "Unknown integer setcc!"); 3211 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3212 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3213 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 3214 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 3215 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 3216 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 3217 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 3218 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 3219 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 3220 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 3221 } 3222 } else { 3223 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 3224 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 3225 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 3226 3227 // If the comparison constant has bits in the upper part, the 3228 // zero-extended value could never match. 3229 if (C1 & (~0ULL << InSize)) { 3230 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 3231 switch (Cond) { 3232 case ISD::SETUGT: 3233 case ISD::SETUGE: 3234 case ISD::SETEQ: return DAG.getConstant(0, VT); 3235 case ISD::SETULT: 3236 case ISD::SETULE: 3237 case ISD::SETNE: return DAG.getConstant(1, VT); 3238 case ISD::SETGT: 3239 case ISD::SETGE: 3240 // True if the sign bit of C1 is set. 3241 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 3242 case ISD::SETLT: 3243 case ISD::SETLE: 3244 // True if the sign bit of C1 isn't set. 3245 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 3246 default: 3247 break; 3248 } 3249 } 3250 3251 // Otherwise, we can perform the comparison with the low bits. 3252 switch (Cond) { 3253 case ISD::SETEQ: 3254 case ISD::SETNE: 3255 case ISD::SETUGT: 3256 case ISD::SETUGE: 3257 case ISD::SETULT: 3258 case ISD::SETULE: 3259 return DAG.getSetCC(VT, N0.getOperand(0), 3260 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 3261 Cond); 3262 default: 3263 break; // todo, be more careful with signed comparisons 3264 } 3265 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3266 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 3267 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 3268 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 3269 MVT::ValueType ExtDstTy = N0.getValueType(); 3270 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 3271 3272 // If the extended part has any inconsistent bits, it cannot ever 3273 // compare equal. In other words, they have to be all ones or all 3274 // zeros. 3275 uint64_t ExtBits = 3276 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 3277 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 3278 return DAG.getConstant(Cond == ISD::SETNE, VT); 3279 3280 SDOperand ZextOp; 3281 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 3282 if (Op0Ty == ExtSrcTy) { 3283 ZextOp = N0.getOperand(0); 3284 } else { 3285 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 3286 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 3287 DAG.getConstant(Imm, Op0Ty)); 3288 } 3289 AddToWorkList(ZextOp.Val); 3290 // Otherwise, make this a use of a zext. 3291 return DAG.getSetCC(VT, ZextOp, 3292 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 3293 ExtDstTy), 3294 Cond); 3295 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 3296 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3297 (N0.getOpcode() == ISD::XOR || 3298 (N0.getOpcode() == ISD::AND && 3299 N0.getOperand(0).getOpcode() == ISD::XOR && 3300 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 3301 isa<ConstantSDNode>(N0.getOperand(1)) && 3302 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 3303 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 3304 // only do this if the top bits are known zero. 3305 if (TLI.MaskedValueIsZero(N1, 3306 MVT::getIntVTBitMask(N0.getValueType())-1)) { 3307 // Okay, get the un-inverted input value. 3308 SDOperand Val; 3309 if (N0.getOpcode() == ISD::XOR) 3310 Val = N0.getOperand(0); 3311 else { 3312 assert(N0.getOpcode() == ISD::AND && 3313 N0.getOperand(0).getOpcode() == ISD::XOR); 3314 // ((X^1)&1)^1 -> X & 1 3315 Val = DAG.getNode(ISD::AND, N0.getValueType(), 3316 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 3317 } 3318 return DAG.getSetCC(VT, Val, N1, 3319 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 3320 } 3321 } 3322 3323 uint64_t MinVal, MaxVal; 3324 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 3325 if (ISD::isSignedIntSetCC(Cond)) { 3326 MinVal = 1ULL << (OperandBitSize-1); 3327 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 3328 MaxVal = ~0ULL >> (65-OperandBitSize); 3329 else 3330 MaxVal = 0; 3331 } else { 3332 MinVal = 0; 3333 MaxVal = ~0ULL >> (64-OperandBitSize); 3334 } 3335 3336 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 3337 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 3338 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 3339 --C1; // X >= C0 --> X > (C0-1) 3340 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3341 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 3342 } 3343 3344 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 3345 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 3346 ++C1; // X <= C0 --> X < (C0+1) 3347 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3348 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 3349 } 3350 3351 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 3352 return DAG.getConstant(0, VT); // X < MIN --> false 3353 3354 // Canonicalize setgt X, Min --> setne X, Min 3355 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 3356 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3357 // Canonicalize setlt X, Max --> setne X, Max 3358 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 3359 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3360 3361 // If we have setult X, 1, turn it into seteq X, 0 3362 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 3363 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 3364 ISD::SETEQ); 3365 // If we have setugt X, Max-1, turn it into seteq X, Max 3366 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 3367 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 3368 ISD::SETEQ); 3369 3370 // If we have "setcc X, C0", check to see if we can shrink the immediate 3371 // by changing cc. 3372 3373 // SETUGT X, SINTMAX -> SETLT X, 0 3374 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 3375 C1 == (~0ULL >> (65-OperandBitSize))) 3376 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 3377 ISD::SETLT); 3378 3379 // FIXME: Implement the rest of these. 3380 3381 // Fold bit comparisons when we can. 3382 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3383 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 3384 if (ConstantSDNode *AndRHS = 3385 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3386 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 3387 // Perform the xform if the AND RHS is a single bit. 3388 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 3389 return DAG.getNode(ISD::SRL, VT, N0, 3390 DAG.getConstant(Log2_64(AndRHS->getValue()), 3391 TLI.getShiftAmountTy())); 3392 } 3393 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 3394 // (X & 8) == 8 --> (X & 8) >> 3 3395 // Perform the xform if C1 is a single bit. 3396 if ((C1 & (C1-1)) == 0) { 3397 return DAG.getNode(ISD::SRL, VT, N0, 3398 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 3399 } 3400 } 3401 } 3402 } 3403 } else if (isa<ConstantSDNode>(N0.Val)) { 3404 // Ensure that the constant occurs on the RHS. 3405 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3406 } 3407 3408 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 3409 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 3410 double C0 = N0C->getValue(), C1 = N1C->getValue(); 3411 3412 switch (Cond) { 3413 default: break; // FIXME: Implement the rest of these! 3414 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3415 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3416 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 3417 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 3418 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 3419 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 3420 } 3421 } else { 3422 // Ensure that the constant occurs on the RHS. 3423 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3424 } 3425 3426 if (N0 == N1) { 3427 // We can always fold X == Y for integer setcc's. 3428 if (MVT::isInteger(N0.getValueType())) 3429 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3430 unsigned UOF = ISD::getUnorderedFlavor(Cond); 3431 if (UOF == 2) // FP operators that are undefined on NaNs. 3432 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3433 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 3434 return DAG.getConstant(UOF, VT); 3435 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 3436 // if it is not already. 3437 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 3438 if (NewCond != Cond) 3439 return DAG.getSetCC(VT, N0, N1, NewCond); 3440 } 3441 3442 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3443 MVT::isInteger(N0.getValueType())) { 3444 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 3445 N0.getOpcode() == ISD::XOR) { 3446 // Simplify (X+Y) == (X+Z) --> Y == Z 3447 if (N0.getOpcode() == N1.getOpcode()) { 3448 if (N0.getOperand(0) == N1.getOperand(0)) 3449 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 3450 if (N0.getOperand(1) == N1.getOperand(1)) 3451 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 3452 if (isCommutativeBinOp(N0.getOpcode())) { 3453 // If X op Y == Y op X, try other combinations. 3454 if (N0.getOperand(0) == N1.getOperand(1)) 3455 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 3456 if (N0.getOperand(1) == N1.getOperand(0)) 3457 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 3458 } 3459 } 3460 3461 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 3462 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3463 // Turn (X+C1) == C2 --> X == C2-C1 3464 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 3465 return DAG.getSetCC(VT, N0.getOperand(0), 3466 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 3467 N0.getValueType()), Cond); 3468 } 3469 3470 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 3471 if (N0.getOpcode() == ISD::XOR) 3472 // If we know that all of the inverted bits are zero, don't bother 3473 // performing the inversion. 3474 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 3475 return DAG.getSetCC(VT, N0.getOperand(0), 3476 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 3477 N0.getValueType()), Cond); 3478 } 3479 3480 // Turn (C1-X) == C2 --> X == C1-C2 3481 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 3482 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 3483 return DAG.getSetCC(VT, N0.getOperand(1), 3484 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 3485 N0.getValueType()), Cond); 3486 } 3487 } 3488 } 3489 3490 // Simplify (X+Z) == X --> Z == 0 3491 if (N0.getOperand(0) == N1) 3492 return DAG.getSetCC(VT, N0.getOperand(1), 3493 DAG.getConstant(0, N0.getValueType()), Cond); 3494 if (N0.getOperand(1) == N1) { 3495 if (isCommutativeBinOp(N0.getOpcode())) 3496 return DAG.getSetCC(VT, N0.getOperand(0), 3497 DAG.getConstant(0, N0.getValueType()), Cond); 3498 else { 3499 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 3500 // (Z-X) == X --> Z == X<<1 3501 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 3502 N1, 3503 DAG.getConstant(1,TLI.getShiftAmountTy())); 3504 AddToWorkList(SH.Val); 3505 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 3506 } 3507 } 3508 } 3509 3510 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 3511 N1.getOpcode() == ISD::XOR) { 3512 // Simplify X == (X+Z) --> Z == 0 3513 if (N1.getOperand(0) == N0) { 3514 return DAG.getSetCC(VT, N1.getOperand(1), 3515 DAG.getConstant(0, N1.getValueType()), Cond); 3516 } else if (N1.getOperand(1) == N0) { 3517 if (isCommutativeBinOp(N1.getOpcode())) { 3518 return DAG.getSetCC(VT, N1.getOperand(0), 3519 DAG.getConstant(0, N1.getValueType()), Cond); 3520 } else { 3521 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 3522 // X == (Z-X) --> X<<1 == Z 3523 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 3524 DAG.getConstant(1,TLI.getShiftAmountTy())); 3525 AddToWorkList(SH.Val); 3526 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 3527 } 3528 } 3529 } 3530 } 3531 3532 // Fold away ALL boolean setcc's. 3533 SDOperand Temp; 3534 if (N0.getValueType() == MVT::i1 && foldBooleans) { 3535 switch (Cond) { 3536 default: assert(0 && "Unknown integer setcc!"); 3537 case ISD::SETEQ: // X == Y -> (X^Y)^1 3538 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3539 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 3540 AddToWorkList(Temp.Val); 3541 break; 3542 case ISD::SETNE: // X != Y --> (X^Y) 3543 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3544 break; 3545 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 3546 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 3547 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3548 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 3549 AddToWorkList(Temp.Val); 3550 break; 3551 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 3552 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 3553 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3554 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 3555 AddToWorkList(Temp.Val); 3556 break; 3557 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 3558 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 3559 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3560 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 3561 AddToWorkList(Temp.Val); 3562 break; 3563 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 3564 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 3565 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3566 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 3567 break; 3568 } 3569 if (VT != MVT::i1) { 3570 AddToWorkList(N0.Val); 3571 // FIXME: If running after legalize, we probably can't do this. 3572 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3573 } 3574 return N0; 3575 } 3576 3577 // Could not fold it. 3578 return SDOperand(); 3579} 3580 3581/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3582/// return a DAG expression to select that will generate the same value by 3583/// multiplying by a magic number. See: 3584/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3585SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 3586 MVT::ValueType VT = N->getValueType(0); 3587 3588 // Check to see if we can do this. 3589 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 3590 return SDOperand(); // BuildSDIV only operates on i32 or i64 3591 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 3592 return SDOperand(); // Make sure the target supports MULHS. 3593 3594 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 3595 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 3596 3597 // Multiply the numerator (operand 0) by the magic value 3598 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 3599 DAG.getConstant(magics.m, VT)); 3600 // If d > 0 and m < 0, add the numerator 3601 if (d > 0 && magics.m < 0) { 3602 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 3603 AddToWorkList(Q.Val); 3604 } 3605 // If d < 0 and m > 0, subtract the numerator. 3606 if (d < 0 && magics.m > 0) { 3607 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 3608 AddToWorkList(Q.Val); 3609 } 3610 // Shift right algebraic if shift value is nonzero 3611 if (magics.s > 0) { 3612 Q = DAG.getNode(ISD::SRA, VT, Q, 3613 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 3614 AddToWorkList(Q.Val); 3615 } 3616 // Extract the sign bit and add it to the quotient 3617 SDOperand T = 3618 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 3619 TLI.getShiftAmountTy())); 3620 AddToWorkList(T.Val); 3621 return DAG.getNode(ISD::ADD, VT, Q, T); 3622} 3623 3624/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3625/// return a DAG expression to select that will generate the same value by 3626/// multiplying by a magic number. See: 3627/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3628SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 3629 MVT::ValueType VT = N->getValueType(0); 3630 3631 // Check to see if we can do this. 3632 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 3633 return SDOperand(); // BuildUDIV only operates on i32 or i64 3634 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 3635 return SDOperand(); // Make sure the target supports MULHU. 3636 3637 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 3638 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 3639 3640 // Multiply the numerator (operand 0) by the magic value 3641 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 3642 DAG.getConstant(magics.m, VT)); 3643 AddToWorkList(Q.Val); 3644 3645 if (magics.a == 0) { 3646 return DAG.getNode(ISD::SRL, VT, Q, 3647 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 3648 } else { 3649 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 3650 AddToWorkList(NPQ.Val); 3651 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 3652 DAG.getConstant(1, TLI.getShiftAmountTy())); 3653 AddToWorkList(NPQ.Val); 3654 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 3655 AddToWorkList(NPQ.Val); 3656 return DAG.getNode(ISD::SRL, VT, NPQ, 3657 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 3658 } 3659} 3660 3661// SelectionDAG::Combine - This is the entry point for the file. 3662// 3663void SelectionDAG::Combine(bool RunningAfterLegalize) { 3664 /// run - This is the main entry point to this class. 3665 /// 3666 DAGCombiner(*this).Run(RunningAfterLegalize); 3667} 3668