DAGCombiner.cpp revision 5d00cb423a9033583f5bdb46d5bfee2dd23cf02e
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32using namespace llvm; 33 34STATISTIC(NodesCombined , "Number of dag nodes combined"); 35STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 36STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 37 38namespace { 39#ifndef NDEBUG 40 static cl::opt<bool> 41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 42 cl::desc("Pop up a window to show dags before the first " 43 "dag combine pass")); 44 static cl::opt<bool> 45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 46 cl::desc("Pop up a window to show dags before the second " 47 "dag combine pass")); 48#else 49 static const bool ViewDAGCombine1 = false; 50 static const bool ViewDAGCombine2 = false; 51#endif 52 53 static cl::opt<bool> 54 CombinerAA("combiner-alias-analysis", cl::Hidden, 55 cl::desc("Turn on alias analysis during testing")); 56 57 static cl::opt<bool> 58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 59 cl::desc("Include global information in alias analysis")); 60 61//------------------------------ DAGCombiner ---------------------------------// 62 63 class VISIBILITY_HIDDEN DAGCombiner { 64 SelectionDAG &DAG; 65 TargetLowering &TLI; 66 bool AfterLegalize; 67 68 // Worklist of all of the nodes that need to be simplified. 69 std::vector<SDNode*> WorkList; 70 71 // AA - Used for DAG load/store alias analysis. 72 AliasAnalysis &AA; 73 74 /// AddUsersToWorkList - When an instruction is simplified, add all users of 75 /// the instruction to the work lists because they might get more simplified 76 /// now. 77 /// 78 void AddUsersToWorkList(SDNode *N) { 79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 80 UI != UE; ++UI) 81 AddToWorkList(*UI); 82 } 83 84 /// visit - call the node-specific routine that knows how to fold each 85 /// particular type of node. 86 SDOperand visit(SDNode *N); 87 88 public: 89 /// AddToWorkList - Add to the work list making sure it's instance is at the 90 /// the back (next to be processed.) 91 void AddToWorkList(SDNode *N) { 92 removeFromWorkList(N); 93 WorkList.push_back(N); 94 } 95 96 /// removeFromWorkList - remove all instances of N from the worklist. 97 /// 98 void removeFromWorkList(SDNode *N) { 99 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 100 WorkList.end()); 101 } 102 103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 104 bool AddTo = true); 105 106 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 107 return CombineTo(N, &Res, 1, AddTo); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 111 bool AddTo = true) { 112 SDOperand To[] = { Res0, Res1 }; 113 return CombineTo(N, To, 2, AddTo); 114 } 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDOperand Op) { 122 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 123 return SimplifyDemandedBits(Op, Demanded); 124 } 125 126 bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded); 127 128 bool CombineToPreIndexedLoadStore(SDNode *N); 129 bool CombineToPostIndexedLoadStore(SDNode *N); 130 131 132 /// combine - call the node-specific routine that knows how to fold each 133 /// particular type of node. If that doesn't do anything, try the 134 /// target-specific DAG combines. 135 SDOperand combine(SDNode *N); 136 137 // Visitation implementation - Implement dag node combining for different 138 // node types. The semantics are as follows: 139 // Return Value: 140 // SDOperand.Val == 0 - No change was made 141 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 142 // otherwise - N should be replaced by the returned Operand. 143 // 144 SDOperand visitTokenFactor(SDNode *N); 145 SDOperand visitMERGE_VALUES(SDNode *N); 146 SDOperand visitADD(SDNode *N); 147 SDOperand visitSUB(SDNode *N); 148 SDOperand visitADDC(SDNode *N); 149 SDOperand visitADDE(SDNode *N); 150 SDOperand visitMUL(SDNode *N); 151 SDOperand visitSDIV(SDNode *N); 152 SDOperand visitUDIV(SDNode *N); 153 SDOperand visitSREM(SDNode *N); 154 SDOperand visitUREM(SDNode *N); 155 SDOperand visitMULHU(SDNode *N); 156 SDOperand visitMULHS(SDNode *N); 157 SDOperand visitSMUL_LOHI(SDNode *N); 158 SDOperand visitUMUL_LOHI(SDNode *N); 159 SDOperand visitSDIVREM(SDNode *N); 160 SDOperand visitUDIVREM(SDNode *N); 161 SDOperand visitAND(SDNode *N); 162 SDOperand visitOR(SDNode *N); 163 SDOperand visitXOR(SDNode *N); 164 SDOperand SimplifyVBinOp(SDNode *N); 165 SDOperand visitSHL(SDNode *N); 166 SDOperand visitSRA(SDNode *N); 167 SDOperand visitSRL(SDNode *N); 168 SDOperand visitCTLZ(SDNode *N); 169 SDOperand visitCTTZ(SDNode *N); 170 SDOperand visitCTPOP(SDNode *N); 171 SDOperand visitSELECT(SDNode *N); 172 SDOperand visitSELECT_CC(SDNode *N); 173 SDOperand visitSETCC(SDNode *N); 174 SDOperand visitSIGN_EXTEND(SDNode *N); 175 SDOperand visitZERO_EXTEND(SDNode *N); 176 SDOperand visitANY_EXTEND(SDNode *N); 177 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 178 SDOperand visitTRUNCATE(SDNode *N); 179 SDOperand visitBIT_CONVERT(SDNode *N); 180 SDOperand visitFADD(SDNode *N); 181 SDOperand visitFSUB(SDNode *N); 182 SDOperand visitFMUL(SDNode *N); 183 SDOperand visitFDIV(SDNode *N); 184 SDOperand visitFREM(SDNode *N); 185 SDOperand visitFCOPYSIGN(SDNode *N); 186 SDOperand visitSINT_TO_FP(SDNode *N); 187 SDOperand visitUINT_TO_FP(SDNode *N); 188 SDOperand visitFP_TO_SINT(SDNode *N); 189 SDOperand visitFP_TO_UINT(SDNode *N); 190 SDOperand visitFP_ROUND(SDNode *N); 191 SDOperand visitFP_ROUND_INREG(SDNode *N); 192 SDOperand visitFP_EXTEND(SDNode *N); 193 SDOperand visitFNEG(SDNode *N); 194 SDOperand visitFABS(SDNode *N); 195 SDOperand visitBRCOND(SDNode *N); 196 SDOperand visitBR_CC(SDNode *N); 197 SDOperand visitLOAD(SDNode *N); 198 SDOperand visitSTORE(SDNode *N); 199 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 200 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 201 SDOperand visitBUILD_VECTOR(SDNode *N); 202 SDOperand visitCONCAT_VECTORS(SDNode *N); 203 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 204 205 SDOperand XformToShuffleWithZero(SDNode *N); 206 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 207 208 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 209 210 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 211 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 212 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 213 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 214 SDOperand N3, ISD::CondCode CC, 215 bool NotExtCompare = false); 216 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 217 ISD::CondCode Cond, bool foldBooleans = true); 218 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 219 unsigned HiOp); 220 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 221 SDOperand BuildSDIV(SDNode *N); 222 SDOperand BuildUDIV(SDNode *N); 223 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 224 SDOperand ReduceLoadWidth(SDNode *N); 225 226 SDOperand GetDemandedBits(SDOperand V, const APInt &Mask); 227 228 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 229 /// looking for aliasing nodes and adding them to the Aliases vector. 230 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 231 SmallVector<SDOperand, 8> &Aliases); 232 233 /// isAlias - Return true if there is any possibility that the two addresses 234 /// overlap. 235 bool isAlias(SDOperand Ptr1, int64_t Size1, 236 const Value *SrcValue1, int SrcValueOffset1, 237 SDOperand Ptr2, int64_t Size2, 238 const Value *SrcValue2, int SrcValueOffset2); 239 240 /// FindAliasInfo - Extracts the relevant alias information from the memory 241 /// node. Returns true if the operand was a load. 242 bool FindAliasInfo(SDNode *N, 243 SDOperand &Ptr, int64_t &Size, 244 const Value *&SrcValue, int &SrcValueOffset); 245 246 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 247 /// looking for a better chain (aliasing node.) 248 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 249 250public: 251 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 252 : DAG(D), 253 TLI(D.getTargetLoweringInfo()), 254 AfterLegalize(false), 255 AA(A) {} 256 257 /// Run - runs the dag combiner on all nodes in the work list 258 void Run(bool RunningAfterLegalize); 259 }; 260} 261 262 263namespace { 264/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 265/// nodes from the worklist. 266class VISIBILITY_HIDDEN WorkListRemover : 267 public SelectionDAG::DAGUpdateListener { 268 DAGCombiner &DC; 269public: 270 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 271 272 virtual void NodeDeleted(SDNode *N) { 273 DC.removeFromWorkList(N); 274 } 275 276 virtual void NodeUpdated(SDNode *N) { 277 // Ignore updates. 278 } 279}; 280} 281 282//===----------------------------------------------------------------------===// 283// TargetLowering::DAGCombinerInfo implementation 284//===----------------------------------------------------------------------===// 285 286void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 287 ((DAGCombiner*)DC)->AddToWorkList(N); 288} 289 290SDOperand TargetLowering::DAGCombinerInfo:: 291CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 292 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 293} 294 295SDOperand TargetLowering::DAGCombinerInfo:: 296CombineTo(SDNode *N, SDOperand Res) { 297 return ((DAGCombiner*)DC)->CombineTo(N, Res); 298} 299 300 301SDOperand TargetLowering::DAGCombinerInfo:: 302CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 303 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 304} 305 306 307//===----------------------------------------------------------------------===// 308// Helper Functions 309//===----------------------------------------------------------------------===// 310 311/// isNegatibleForFree - Return 1 if we can compute the negated form of the 312/// specified expression for the same cost as the expression itself, or 2 if we 313/// can compute the negated form more cheaply than the expression itself. 314static char isNegatibleForFree(SDOperand Op, bool AfterLegalize, 315 unsigned Depth = 0) { 316 // No compile time optimizations on this type. 317 if (Op.getValueType() == MVT::ppcf128) 318 return 0; 319 320 // fneg is removable even if it has multiple uses. 321 if (Op.getOpcode() == ISD::FNEG) return 2; 322 323 // Don't allow anything with multiple uses. 324 if (!Op.hasOneUse()) return 0; 325 326 // Don't recurse exponentially. 327 if (Depth > 6) return 0; 328 329 switch (Op.getOpcode()) { 330 default: return false; 331 case ISD::ConstantFP: 332 // Don't invert constant FP values after legalize. The negated constant 333 // isn't necessarily legal. 334 return AfterLegalize ? 0 : 1; 335 case ISD::FADD: 336 // FIXME: determine better conditions for this xform. 337 if (!UnsafeFPMath) return 0; 338 339 // -(A+B) -> -A - B 340 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 341 return V; 342 // -(A+B) -> -B - A 343 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 344 case ISD::FSUB: 345 // We can't turn -(A-B) into B-A when we honor signed zeros. 346 if (!UnsafeFPMath) return 0; 347 348 // -(A-B) -> B-A 349 return 1; 350 351 case ISD::FMUL: 352 case ISD::FDIV: 353 if (HonorSignDependentRoundingFPMath()) return 0; 354 355 // -(X*Y) -> (-X * Y) or (X*-Y) 356 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 357 return V; 358 359 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 360 361 case ISD::FP_EXTEND: 362 case ISD::FP_ROUND: 363 case ISD::FSIN: 364 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 365 } 366} 367 368/// GetNegatedExpression - If isNegatibleForFree returns true, this function 369/// returns the newly negated expression. 370static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 371 bool AfterLegalize, unsigned Depth = 0) { 372 // fneg is removable even if it has multiple uses. 373 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 374 375 // Don't allow anything with multiple uses. 376 assert(Op.hasOneUse() && "Unknown reuse!"); 377 378 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 379 switch (Op.getOpcode()) { 380 default: assert(0 && "Unknown code"); 381 case ISD::ConstantFP: { 382 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 383 V.changeSign(); 384 return DAG.getConstantFP(V, Op.getValueType()); 385 } 386 case ISD::FADD: 387 // FIXME: determine better conditions for this xform. 388 assert(UnsafeFPMath); 389 390 // -(A+B) -> -A - B 391 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 392 return DAG.getNode(ISD::FSUB, Op.getValueType(), 393 GetNegatedExpression(Op.getOperand(0), DAG, 394 AfterLegalize, Depth+1), 395 Op.getOperand(1)); 396 // -(A+B) -> -B - A 397 return DAG.getNode(ISD::FSUB, Op.getValueType(), 398 GetNegatedExpression(Op.getOperand(1), DAG, 399 AfterLegalize, Depth+1), 400 Op.getOperand(0)); 401 case ISD::FSUB: 402 // We can't turn -(A-B) into B-A when we honor signed zeros. 403 assert(UnsafeFPMath); 404 405 // -(0-B) -> B 406 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 407 if (N0CFP->getValueAPF().isZero()) 408 return Op.getOperand(1); 409 410 // -(A-B) -> B-A 411 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 412 Op.getOperand(0)); 413 414 case ISD::FMUL: 415 case ISD::FDIV: 416 assert(!HonorSignDependentRoundingFPMath()); 417 418 // -(X*Y) -> -X * Y 419 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 420 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 421 GetNegatedExpression(Op.getOperand(0), DAG, 422 AfterLegalize, Depth+1), 423 Op.getOperand(1)); 424 425 // -(X*Y) -> X * -Y 426 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 427 Op.getOperand(0), 428 GetNegatedExpression(Op.getOperand(1), DAG, 429 AfterLegalize, Depth+1)); 430 431 case ISD::FP_EXTEND: 432 case ISD::FSIN: 433 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 434 GetNegatedExpression(Op.getOperand(0), DAG, 435 AfterLegalize, Depth+1)); 436 case ISD::FP_ROUND: 437 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(0), DAG, 439 AfterLegalize, Depth+1), 440 Op.getOperand(1)); 441 } 442} 443 444 445// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 446// that selects between the values 1 and 0, making it equivalent to a setcc. 447// Also, set the incoming LHS, RHS, and CC references to the appropriate 448// nodes based on the type of node we are checking. This simplifies life a 449// bit for the callers. 450static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 451 SDOperand &CC) { 452 if (N.getOpcode() == ISD::SETCC) { 453 LHS = N.getOperand(0); 454 RHS = N.getOperand(1); 455 CC = N.getOperand(2); 456 return true; 457 } 458 if (N.getOpcode() == ISD::SELECT_CC && 459 N.getOperand(2).getOpcode() == ISD::Constant && 460 N.getOperand(3).getOpcode() == ISD::Constant && 461 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 462 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 463 LHS = N.getOperand(0); 464 RHS = N.getOperand(1); 465 CC = N.getOperand(4); 466 return true; 467 } 468 return false; 469} 470 471// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 472// one use. If this is true, it allows the users to invert the operation for 473// free when it is profitable to do so. 474static bool isOneUseSetCC(SDOperand N) { 475 SDOperand N0, N1, N2; 476 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 477 return true; 478 return false; 479} 480 481SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 482 MVT::ValueType VT = N0.getValueType(); 483 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 484 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 485 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 486 if (isa<ConstantSDNode>(N1)) { 487 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 488 AddToWorkList(OpNode.Val); 489 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 490 } else if (N0.hasOneUse()) { 491 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 492 AddToWorkList(OpNode.Val); 493 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 494 } 495 } 496 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 497 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 498 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 499 if (isa<ConstantSDNode>(N0)) { 500 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 501 AddToWorkList(OpNode.Val); 502 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 503 } else if (N1.hasOneUse()) { 504 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 505 AddToWorkList(OpNode.Val); 506 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 507 } 508 } 509 return SDOperand(); 510} 511 512SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 513 bool AddTo) { 514 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 515 ++NodesCombined; 516 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 517 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 518 DOUT << " and " << NumTo-1 << " other values\n"; 519 WorkListRemover DeadNodes(*this); 520 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 521 522 if (AddTo) { 523 // Push the new nodes and any users onto the worklist 524 for (unsigned i = 0, e = NumTo; i != e; ++i) { 525 AddToWorkList(To[i].Val); 526 AddUsersToWorkList(To[i].Val); 527 } 528 } 529 530 // Nodes can be reintroduced into the worklist. Make sure we do not 531 // process a node that has been replaced. 532 removeFromWorkList(N); 533 534 // Finally, since the node is now dead, remove it from the graph. 535 DAG.DeleteNode(N); 536 return SDOperand(N, 0); 537} 538 539/// SimplifyDemandedBits - Check the specified integer node value to see if 540/// it can be simplified or if things it uses can be simplified by bit 541/// propagation. If so, return true. 542bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) { 543 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 544 APInt KnownZero, KnownOne; 545 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 546 return false; 547 548 // Revisit the node. 549 AddToWorkList(Op.Val); 550 551 // Replace the old value with the new one. 552 ++NodesCombined; 553 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 554 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 555 DOUT << '\n'; 556 557 // Replace all uses. If any nodes become isomorphic to other nodes and 558 // are deleted, make sure to remove them from our worklist. 559 WorkListRemover DeadNodes(*this); 560 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 561 562 // Push the new node and any (possibly new) users onto the worklist. 563 AddToWorkList(TLO.New.Val); 564 AddUsersToWorkList(TLO.New.Val); 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (TLO.Old.Val->use_empty()) { 570 removeFromWorkList(TLO.Old.Val); 571 572 // If the operands of this node are only used by the node, they will now 573 // be dead. Make sure to visit them first to delete dead nodes early. 574 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 575 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 576 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 577 578 DAG.DeleteNode(TLO.Old.Val); 579 } 580 return true; 581} 582 583//===----------------------------------------------------------------------===// 584// Main DAG Combiner implementation 585//===----------------------------------------------------------------------===// 586 587void DAGCombiner::Run(bool RunningAfterLegalize) { 588 // set the instance variable, so that the various visit routines may use it. 589 AfterLegalize = RunningAfterLegalize; 590 591 // Add all the dag nodes to the worklist. 592 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 593 E = DAG.allnodes_end(); I != E; ++I) 594 WorkList.push_back(I); 595 596 // Create a dummy node (which is not added to allnodes), that adds a reference 597 // to the root node, preventing it from being deleted, and tracking any 598 // changes of the root. 599 HandleSDNode Dummy(DAG.getRoot()); 600 601 // The root of the dag may dangle to deleted nodes until the dag combiner is 602 // done. Set it to null to avoid confusion. 603 DAG.setRoot(SDOperand()); 604 605 // while the worklist isn't empty, inspect the node on the end of it and 606 // try and combine it. 607 while (!WorkList.empty()) { 608 SDNode *N = WorkList.back(); 609 WorkList.pop_back(); 610 611 // If N has no uses, it is dead. Make sure to revisit all N's operands once 612 // N is deleted from the DAG, since they too may now be dead or may have a 613 // reduced number of uses, allowing other xforms. 614 if (N->use_empty() && N != &Dummy) { 615 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 616 AddToWorkList(N->getOperand(i).Val); 617 618 DAG.DeleteNode(N); 619 continue; 620 } 621 622 SDOperand RV = combine(N); 623 624 if (RV.Val == 0) 625 continue; 626 627 ++NodesCombined; 628 629 // If we get back the same node we passed in, rather than a new node or 630 // zero, we know that the node must have defined multiple values and 631 // CombineTo was used. Since CombineTo takes care of the worklist 632 // mechanics for us, we have no work to do in this case. 633 if (RV.Val == N) 634 continue; 635 636 assert(N->getOpcode() != ISD::DELETED_NODE && 637 RV.Val->getOpcode() != ISD::DELETED_NODE && 638 "Node was deleted but visit returned new node!"); 639 640 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 641 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 642 DOUT << '\n'; 643 WorkListRemover DeadNodes(*this); 644 if (N->getNumValues() == RV.Val->getNumValues()) 645 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes); 646 else { 647 assert(N->getValueType(0) == RV.getValueType() && 648 N->getNumValues() == 1 && "Type mismatch"); 649 SDOperand OpV = RV; 650 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 651 } 652 653 // Push the new node and any users onto the worklist 654 AddToWorkList(RV.Val); 655 AddUsersToWorkList(RV.Val); 656 657 // Add any uses of the old node to the worklist in case this node is the 658 // last one that uses them. They may become dead after this node is 659 // deleted. 660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 661 AddToWorkList(N->getOperand(i).Val); 662 663 // Nodes can be reintroduced into the worklist. Make sure we do not 664 // process a node that has been replaced. 665 removeFromWorkList(N); 666 667 // Finally, since the node is now dead, remove it from the graph. 668 DAG.DeleteNode(N); 669 } 670 671 // If the root changed (e.g. it was a dead load, update the root). 672 DAG.setRoot(Dummy.getValue()); 673} 674 675SDOperand DAGCombiner::visit(SDNode *N) { 676 switch(N->getOpcode()) { 677 default: break; 678 case ISD::TokenFactor: return visitTokenFactor(N); 679 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 680 case ISD::ADD: return visitADD(N); 681 case ISD::SUB: return visitSUB(N); 682 case ISD::ADDC: return visitADDC(N); 683 case ISD::ADDE: return visitADDE(N); 684 case ISD::MUL: return visitMUL(N); 685 case ISD::SDIV: return visitSDIV(N); 686 case ISD::UDIV: return visitUDIV(N); 687 case ISD::SREM: return visitSREM(N); 688 case ISD::UREM: return visitUREM(N); 689 case ISD::MULHU: return visitMULHU(N); 690 case ISD::MULHS: return visitMULHS(N); 691 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 692 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 693 case ISD::SDIVREM: return visitSDIVREM(N); 694 case ISD::UDIVREM: return visitUDIVREM(N); 695 case ISD::AND: return visitAND(N); 696 case ISD::OR: return visitOR(N); 697 case ISD::XOR: return visitXOR(N); 698 case ISD::SHL: return visitSHL(N); 699 case ISD::SRA: return visitSRA(N); 700 case ISD::SRL: return visitSRL(N); 701 case ISD::CTLZ: return visitCTLZ(N); 702 case ISD::CTTZ: return visitCTTZ(N); 703 case ISD::CTPOP: return visitCTPOP(N); 704 case ISD::SELECT: return visitSELECT(N); 705 case ISD::SELECT_CC: return visitSELECT_CC(N); 706 case ISD::SETCC: return visitSETCC(N); 707 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 708 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 709 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 710 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 711 case ISD::TRUNCATE: return visitTRUNCATE(N); 712 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 713 case ISD::FADD: return visitFADD(N); 714 case ISD::FSUB: return visitFSUB(N); 715 case ISD::FMUL: return visitFMUL(N); 716 case ISD::FDIV: return visitFDIV(N); 717 case ISD::FREM: return visitFREM(N); 718 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 719 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 720 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 721 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 722 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 723 case ISD::FP_ROUND: return visitFP_ROUND(N); 724 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 725 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 726 case ISD::FNEG: return visitFNEG(N); 727 case ISD::FABS: return visitFABS(N); 728 case ISD::BRCOND: return visitBRCOND(N); 729 case ISD::BR_CC: return visitBR_CC(N); 730 case ISD::LOAD: return visitLOAD(N); 731 case ISD::STORE: return visitSTORE(N); 732 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 733 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 734 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 735 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 736 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 737 } 738 return SDOperand(); 739} 740 741SDOperand DAGCombiner::combine(SDNode *N) { 742 743 SDOperand RV = visit(N); 744 745 // If nothing happened, try a target-specific DAG combine. 746 if (RV.Val == 0) { 747 assert(N->getOpcode() != ISD::DELETED_NODE && 748 "Node was deleted but visit returned NULL!"); 749 750 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 751 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 752 753 // Expose the DAG combiner to the target combiner impls. 754 TargetLowering::DAGCombinerInfo 755 DagCombineInfo(DAG, !AfterLegalize, false, this); 756 757 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 758 } 759 } 760 761 // If N is a commutative binary node, try commuting it to enable more 762 // sdisel CSE. 763 if (RV.Val == 0 && 764 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 765 N->getNumValues() == 1) { 766 SDOperand N0 = N->getOperand(0); 767 SDOperand N1 = N->getOperand(1); 768 // Constant operands are canonicalized to RHS. 769 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 770 SDOperand Ops[] = { N1, N0 }; 771 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 772 Ops, 2); 773 if (CSENode) 774 return SDOperand(CSENode, 0); 775 } 776 } 777 778 return RV; 779} 780 781/// getInputChainForNode - Given a node, return its input chain if it has one, 782/// otherwise return a null sd operand. 783static SDOperand getInputChainForNode(SDNode *N) { 784 if (unsigned NumOps = N->getNumOperands()) { 785 if (N->getOperand(0).getValueType() == MVT::Other) 786 return N->getOperand(0); 787 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 788 return N->getOperand(NumOps-1); 789 for (unsigned i = 1; i < NumOps-1; ++i) 790 if (N->getOperand(i).getValueType() == MVT::Other) 791 return N->getOperand(i); 792 } 793 return SDOperand(0, 0); 794} 795 796SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 797 // If N has two operands, where one has an input chain equal to the other, 798 // the 'other' chain is redundant. 799 if (N->getNumOperands() == 2) { 800 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 801 return N->getOperand(0); 802 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 803 return N->getOperand(1); 804 } 805 806 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 807 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 808 SmallPtrSet<SDNode*, 16> SeenOps; 809 bool Changed = false; // If we should replace this token factor. 810 811 // Start out with this token factor. 812 TFs.push_back(N); 813 814 // Iterate through token factors. The TFs grows when new token factors are 815 // encountered. 816 for (unsigned i = 0; i < TFs.size(); ++i) { 817 SDNode *TF = TFs[i]; 818 819 // Check each of the operands. 820 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 821 SDOperand Op = TF->getOperand(i); 822 823 switch (Op.getOpcode()) { 824 case ISD::EntryToken: 825 // Entry tokens don't need to be added to the list. They are 826 // rededundant. 827 Changed = true; 828 break; 829 830 case ISD::TokenFactor: 831 if ((CombinerAA || Op.hasOneUse()) && 832 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 833 // Queue up for processing. 834 TFs.push_back(Op.Val); 835 // Clean up in case the token factor is removed. 836 AddToWorkList(Op.Val); 837 Changed = true; 838 break; 839 } 840 // Fall thru 841 842 default: 843 // Only add if it isn't already in the list. 844 if (SeenOps.insert(Op.Val)) 845 Ops.push_back(Op); 846 else 847 Changed = true; 848 break; 849 } 850 } 851 } 852 853 SDOperand Result; 854 855 // If we've change things around then replace token factor. 856 if (Changed) { 857 if (Ops.empty()) { 858 // The entry token is the only possible outcome. 859 Result = DAG.getEntryNode(); 860 } else { 861 // New and improved token factor. 862 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 863 } 864 865 // Don't add users to work list. 866 return CombineTo(N, Result, false); 867 } 868 869 return Result; 870} 871 872/// MERGE_VALUES can always be eliminated. 873SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) { 874 WorkListRemover DeadNodes(*this); 875 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 876 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i), 877 &DeadNodes); 878 removeFromWorkList(N); 879 DAG.DeleteNode(N); 880 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 881} 882 883 884static 885SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 886 MVT::ValueType VT = N0.getValueType(); 887 SDOperand N00 = N0.getOperand(0); 888 SDOperand N01 = N0.getOperand(1); 889 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 890 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 891 isa<ConstantSDNode>(N00.getOperand(1))) { 892 N0 = DAG.getNode(ISD::ADD, VT, 893 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 894 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 895 return DAG.getNode(ISD::ADD, VT, N0, N1); 896 } 897 return SDOperand(); 898} 899 900static 901SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 902 SelectionDAG &DAG) { 903 MVT::ValueType VT = N->getValueType(0); 904 unsigned Opc = N->getOpcode(); 905 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 906 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 907 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 908 ISD::CondCode CC = ISD::SETCC_INVALID; 909 if (isSlctCC) 910 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 911 else { 912 SDOperand CCOp = Slct.getOperand(0); 913 if (CCOp.getOpcode() == ISD::SETCC) 914 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 915 } 916 917 bool DoXform = false; 918 bool InvCC = false; 919 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 920 "Bad input!"); 921 if (LHS.getOpcode() == ISD::Constant && 922 cast<ConstantSDNode>(LHS)->isNullValue()) 923 DoXform = true; 924 else if (CC != ISD::SETCC_INVALID && 925 RHS.getOpcode() == ISD::Constant && 926 cast<ConstantSDNode>(RHS)->isNullValue()) { 927 std::swap(LHS, RHS); 928 SDOperand Op0 = Slct.getOperand(0); 929 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() 930 : Op0.getOperand(0).getValueType()); 931 CC = ISD::getSetCCInverse(CC, isInt); 932 DoXform = true; 933 InvCC = true; 934 } 935 936 if (DoXform) { 937 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 938 if (isSlctCC) 939 return DAG.getSelectCC(OtherOp, Result, 940 Slct.getOperand(0), Slct.getOperand(1), CC); 941 SDOperand CCOp = Slct.getOperand(0); 942 if (InvCC) 943 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 944 CCOp.getOperand(1), CC); 945 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 946 } 947 return SDOperand(); 948} 949 950SDOperand DAGCombiner::visitADD(SDNode *N) { 951 SDOperand N0 = N->getOperand(0); 952 SDOperand N1 = N->getOperand(1); 953 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 954 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 955 MVT::ValueType VT = N0.getValueType(); 956 957 // fold vector ops 958 if (MVT::isVector(VT)) { 959 SDOperand FoldedVOp = SimplifyVBinOp(N); 960 if (FoldedVOp.Val) return FoldedVOp; 961 } 962 963 // fold (add x, undef) -> undef 964 if (N0.getOpcode() == ISD::UNDEF) 965 return N0; 966 if (N1.getOpcode() == ISD::UNDEF) 967 return N1; 968 // fold (add c1, c2) -> c1+c2 969 if (N0C && N1C) 970 return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT); 971 // canonicalize constant to RHS 972 if (N0C && !N1C) 973 return DAG.getNode(ISD::ADD, VT, N1, N0); 974 // fold (add x, 0) -> x 975 if (N1C && N1C->isNullValue()) 976 return N0; 977 // fold ((c1-A)+c2) -> (c1+c2)-A 978 if (N1C && N0.getOpcode() == ISD::SUB) 979 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 980 return DAG.getNode(ISD::SUB, VT, 981 DAG.getConstant(N1C->getAPIntValue()+ 982 N0C->getAPIntValue(), VT), 983 N0.getOperand(1)); 984 // reassociate add 985 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 986 if (RADD.Val != 0) 987 return RADD; 988 // fold ((0-A) + B) -> B-A 989 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 990 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 991 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 992 // fold (A + (0-B)) -> A-B 993 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 994 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 995 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 996 // fold (A+(B-A)) -> B 997 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 998 return N1.getOperand(0); 999 1000 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 1001 return SDOperand(N, 0); 1002 1003 // fold (a+b) -> (a|b) iff a and b share no bits. 1004 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 1005 APInt LHSZero, LHSOne; 1006 APInt RHSZero, RHSOne; 1007 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 1008 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1009 if (LHSZero.getBoolValue()) { 1010 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1011 1012 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1013 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1014 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1015 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1016 return DAG.getNode(ISD::OR, VT, N0, N1); 1017 } 1018 } 1019 1020 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1021 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 1022 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 1023 if (Result.Val) return Result; 1024 } 1025 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 1026 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 1027 if (Result.Val) return Result; 1028 } 1029 1030 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1031 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 1032 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 1033 if (Result.Val) return Result; 1034 } 1035 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1036 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1037 if (Result.Val) return Result; 1038 } 1039 1040 return SDOperand(); 1041} 1042 1043SDOperand DAGCombiner::visitADDC(SDNode *N) { 1044 SDOperand N0 = N->getOperand(0); 1045 SDOperand N1 = N->getOperand(1); 1046 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1048 MVT::ValueType VT = N0.getValueType(); 1049 1050 // If the flag result is dead, turn this into an ADD. 1051 if (N->hasNUsesOfValue(0, 1)) 1052 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1053 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1054 1055 // canonicalize constant to RHS. 1056 if (N0C && !N1C) { 1057 SDOperand Ops[] = { N1, N0 }; 1058 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1059 } 1060 1061 // fold (addc x, 0) -> x + no carry out 1062 if (N1C && N1C->isNullValue()) 1063 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1064 1065 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1066 APInt LHSZero, LHSOne; 1067 APInt RHSZero, RHSOne; 1068 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 1069 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1070 if (LHSZero.getBoolValue()) { 1071 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1072 1073 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1074 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1075 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1076 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1077 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1078 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1079 } 1080 1081 return SDOperand(); 1082} 1083 1084SDOperand DAGCombiner::visitADDE(SDNode *N) { 1085 SDOperand N0 = N->getOperand(0); 1086 SDOperand N1 = N->getOperand(1); 1087 SDOperand CarryIn = N->getOperand(2); 1088 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1090 //MVT::ValueType VT = N0.getValueType(); 1091 1092 // canonicalize constant to RHS 1093 if (N0C && !N1C) { 1094 SDOperand Ops[] = { N1, N0, CarryIn }; 1095 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1096 } 1097 1098 // fold (adde x, y, false) -> (addc x, y) 1099 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1100 SDOperand Ops[] = { N1, N0 }; 1101 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1102 } 1103 1104 return SDOperand(); 1105} 1106 1107 1108 1109SDOperand DAGCombiner::visitSUB(SDNode *N) { 1110 SDOperand N0 = N->getOperand(0); 1111 SDOperand N1 = N->getOperand(1); 1112 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1113 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1114 MVT::ValueType VT = N0.getValueType(); 1115 1116 // fold vector ops 1117 if (MVT::isVector(VT)) { 1118 SDOperand FoldedVOp = SimplifyVBinOp(N); 1119 if (FoldedVOp.Val) return FoldedVOp; 1120 } 1121 1122 // fold (sub x, x) -> 0 1123 if (N0 == N1) 1124 return DAG.getConstant(0, N->getValueType(0)); 1125 // fold (sub c1, c2) -> c1-c2 1126 if (N0C && N1C) 1127 return DAG.getNode(ISD::SUB, VT, N0, N1); 1128 // fold (sub x, c) -> (add x, -c) 1129 if (N1C) 1130 return DAG.getNode(ISD::ADD, VT, N0, 1131 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1132 // fold (A+B)-A -> B 1133 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1134 return N0.getOperand(1); 1135 // fold (A+B)-B -> A 1136 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1137 return N0.getOperand(0); 1138 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1139 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1140 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1141 if (Result.Val) return Result; 1142 } 1143 // If either operand of a sub is undef, the result is undef 1144 if (N0.getOpcode() == ISD::UNDEF) 1145 return N0; 1146 if (N1.getOpcode() == ISD::UNDEF) 1147 return N1; 1148 1149 return SDOperand(); 1150} 1151 1152SDOperand DAGCombiner::visitMUL(SDNode *N) { 1153 SDOperand N0 = N->getOperand(0); 1154 SDOperand N1 = N->getOperand(1); 1155 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1156 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1157 MVT::ValueType VT = N0.getValueType(); 1158 1159 // fold vector ops 1160 if (MVT::isVector(VT)) { 1161 SDOperand FoldedVOp = SimplifyVBinOp(N); 1162 if (FoldedVOp.Val) return FoldedVOp; 1163 } 1164 1165 // fold (mul x, undef) -> 0 1166 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1167 return DAG.getConstant(0, VT); 1168 // fold (mul c1, c2) -> c1*c2 1169 if (N0C && N1C) 1170 return DAG.getNode(ISD::MUL, VT, N0, N1); 1171 // canonicalize constant to RHS 1172 if (N0C && !N1C) 1173 return DAG.getNode(ISD::MUL, VT, N1, N0); 1174 // fold (mul x, 0) -> 0 1175 if (N1C && N1C->isNullValue()) 1176 return N1; 1177 // fold (mul x, -1) -> 0-x 1178 if (N1C && N1C->isAllOnesValue()) 1179 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1180 // fold (mul x, (1 << c)) -> x << c 1181 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1182 return DAG.getNode(ISD::SHL, VT, N0, 1183 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1184 TLI.getShiftAmountTy())); 1185 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1186 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1187 // FIXME: If the input is something that is easily negated (e.g. a 1188 // single-use add), we should put the negate there. 1189 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1190 DAG.getNode(ISD::SHL, VT, N0, 1191 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1192 TLI.getShiftAmountTy()))); 1193 } 1194 1195 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1196 if (N1C && N0.getOpcode() == ISD::SHL && 1197 isa<ConstantSDNode>(N0.getOperand(1))) { 1198 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1199 AddToWorkList(C3.Val); 1200 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1201 } 1202 1203 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1204 // use. 1205 { 1206 SDOperand Sh(0,0), Y(0,0); 1207 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1208 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1209 N0.Val->hasOneUse()) { 1210 Sh = N0; Y = N1; 1211 } else if (N1.getOpcode() == ISD::SHL && 1212 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1213 Sh = N1; Y = N0; 1214 } 1215 if (Sh.Val) { 1216 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1217 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1218 } 1219 } 1220 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1221 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1222 isa<ConstantSDNode>(N0.getOperand(1))) { 1223 return DAG.getNode(ISD::ADD, VT, 1224 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1225 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1226 } 1227 1228 // reassociate mul 1229 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1230 if (RMUL.Val != 0) 1231 return RMUL; 1232 1233 return SDOperand(); 1234} 1235 1236SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1237 SDOperand N0 = N->getOperand(0); 1238 SDOperand N1 = N->getOperand(1); 1239 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1240 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1241 MVT::ValueType VT = N->getValueType(0); 1242 1243 // fold vector ops 1244 if (MVT::isVector(VT)) { 1245 SDOperand FoldedVOp = SimplifyVBinOp(N); 1246 if (FoldedVOp.Val) return FoldedVOp; 1247 } 1248 1249 // fold (sdiv c1, c2) -> c1/c2 1250 if (N0C && N1C && !N1C->isNullValue()) 1251 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1252 // fold (sdiv X, 1) -> X 1253 if (N1C && N1C->getSignExtended() == 1LL) 1254 return N0; 1255 // fold (sdiv X, -1) -> 0-X 1256 if (N1C && N1C->isAllOnesValue()) 1257 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1258 // If we know the sign bits of both operands are zero, strength reduce to a 1259 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1260 if (!MVT::isVector(VT)) { 1261 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1262 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1263 } 1264 // fold (sdiv X, pow2) -> simple ops after legalize 1265 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1266 (isPowerOf2_64(N1C->getSignExtended()) || 1267 isPowerOf2_64(-N1C->getSignExtended()))) { 1268 // If dividing by powers of two is cheap, then don't perform the following 1269 // fold. 1270 if (TLI.isPow2DivCheap()) 1271 return SDOperand(); 1272 int64_t pow2 = N1C->getSignExtended(); 1273 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1274 unsigned lg2 = Log2_64(abs2); 1275 // Splat the sign bit into the register 1276 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1277 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1278 TLI.getShiftAmountTy())); 1279 AddToWorkList(SGN.Val); 1280 // Add (N0 < 0) ? abs2 - 1 : 0; 1281 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1282 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1283 TLI.getShiftAmountTy())); 1284 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1285 AddToWorkList(SRL.Val); 1286 AddToWorkList(ADD.Val); // Divide by pow2 1287 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1288 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1289 // If we're dividing by a positive value, we're done. Otherwise, we must 1290 // negate the result. 1291 if (pow2 > 0) 1292 return SRA; 1293 AddToWorkList(SRA.Val); 1294 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1295 } 1296 // if integer divide is expensive and we satisfy the requirements, emit an 1297 // alternate sequence. 1298 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1299 !TLI.isIntDivCheap()) { 1300 SDOperand Op = BuildSDIV(N); 1301 if (Op.Val) return Op; 1302 } 1303 1304 // undef / X -> 0 1305 if (N0.getOpcode() == ISD::UNDEF) 1306 return DAG.getConstant(0, VT); 1307 // X / undef -> undef 1308 if (N1.getOpcode() == ISD::UNDEF) 1309 return N1; 1310 1311 return SDOperand(); 1312} 1313 1314SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1315 SDOperand N0 = N->getOperand(0); 1316 SDOperand N1 = N->getOperand(1); 1317 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1318 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1319 MVT::ValueType VT = N->getValueType(0); 1320 1321 // fold vector ops 1322 if (MVT::isVector(VT)) { 1323 SDOperand FoldedVOp = SimplifyVBinOp(N); 1324 if (FoldedVOp.Val) return FoldedVOp; 1325 } 1326 1327 // fold (udiv c1, c2) -> c1/c2 1328 if (N0C && N1C && !N1C->isNullValue()) 1329 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1330 // fold (udiv x, (1 << c)) -> x >>u c 1331 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1332 return DAG.getNode(ISD::SRL, VT, N0, 1333 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1334 TLI.getShiftAmountTy())); 1335 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1336 if (N1.getOpcode() == ISD::SHL) { 1337 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1338 if (SHC->getAPIntValue().isPowerOf2()) { 1339 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1340 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1341 DAG.getConstant(SHC->getAPIntValue() 1342 .logBase2(), 1343 ADDVT)); 1344 AddToWorkList(Add.Val); 1345 return DAG.getNode(ISD::SRL, VT, N0, Add); 1346 } 1347 } 1348 } 1349 // fold (udiv x, c) -> alternate 1350 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1351 SDOperand Op = BuildUDIV(N); 1352 if (Op.Val) return Op; 1353 } 1354 1355 // undef / X -> 0 1356 if (N0.getOpcode() == ISD::UNDEF) 1357 return DAG.getConstant(0, VT); 1358 // X / undef -> undef 1359 if (N1.getOpcode() == ISD::UNDEF) 1360 return N1; 1361 1362 return SDOperand(); 1363} 1364 1365SDOperand DAGCombiner::visitSREM(SDNode *N) { 1366 SDOperand N0 = N->getOperand(0); 1367 SDOperand N1 = N->getOperand(1); 1368 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1369 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1370 MVT::ValueType VT = N->getValueType(0); 1371 1372 // fold (srem c1, c2) -> c1%c2 1373 if (N0C && N1C && !N1C->isNullValue()) 1374 return DAG.getNode(ISD::SREM, VT, N0, N1); 1375 // If we know the sign bits of both operands are zero, strength reduce to a 1376 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1377 if (!MVT::isVector(VT)) { 1378 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1379 return DAG.getNode(ISD::UREM, VT, N0, N1); 1380 } 1381 1382 // If X/C can be simplified by the division-by-constant logic, lower 1383 // X%C to the equivalent of X-X/C*C. 1384 if (N1C && !N1C->isNullValue()) { 1385 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1386 AddToWorkList(Div.Val); 1387 SDOperand OptimizedDiv = combine(Div.Val); 1388 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1389 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1390 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1391 AddToWorkList(Mul.Val); 1392 return Sub; 1393 } 1394 } 1395 1396 // undef % X -> 0 1397 if (N0.getOpcode() == ISD::UNDEF) 1398 return DAG.getConstant(0, VT); 1399 // X % undef -> undef 1400 if (N1.getOpcode() == ISD::UNDEF) 1401 return N1; 1402 1403 return SDOperand(); 1404} 1405 1406SDOperand DAGCombiner::visitUREM(SDNode *N) { 1407 SDOperand N0 = N->getOperand(0); 1408 SDOperand N1 = N->getOperand(1); 1409 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1410 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1411 MVT::ValueType VT = N->getValueType(0); 1412 1413 // fold (urem c1, c2) -> c1%c2 1414 if (N0C && N1C && !N1C->isNullValue()) 1415 return DAG.getNode(ISD::UREM, VT, N0, N1); 1416 // fold (urem x, pow2) -> (and x, pow2-1) 1417 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1418 return DAG.getNode(ISD::AND, VT, N0, 1419 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1420 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1421 if (N1.getOpcode() == ISD::SHL) { 1422 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1423 if (SHC->getAPIntValue().isPowerOf2()) { 1424 SDOperand Add = 1425 DAG.getNode(ISD::ADD, VT, N1, 1426 DAG.getConstant(APInt::getAllOnesValue(MVT::getSizeInBits(VT)), 1427 VT)); 1428 AddToWorkList(Add.Val); 1429 return DAG.getNode(ISD::AND, VT, N0, Add); 1430 } 1431 } 1432 } 1433 1434 // If X/C can be simplified by the division-by-constant logic, lower 1435 // X%C to the equivalent of X-X/C*C. 1436 if (N1C && !N1C->isNullValue()) { 1437 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1438 SDOperand OptimizedDiv = combine(Div.Val); 1439 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1440 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1441 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1442 AddToWorkList(Mul.Val); 1443 return Sub; 1444 } 1445 } 1446 1447 // undef % X -> 0 1448 if (N0.getOpcode() == ISD::UNDEF) 1449 return DAG.getConstant(0, VT); 1450 // X % undef -> undef 1451 if (N1.getOpcode() == ISD::UNDEF) 1452 return N1; 1453 1454 return SDOperand(); 1455} 1456 1457SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1458 SDOperand N0 = N->getOperand(0); 1459 SDOperand N1 = N->getOperand(1); 1460 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1461 MVT::ValueType VT = N->getValueType(0); 1462 1463 // fold (mulhs x, 0) -> 0 1464 if (N1C && N1C->isNullValue()) 1465 return N1; 1466 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1467 if (N1C && N1C->getAPIntValue() == 1) 1468 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1469 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1470 TLI.getShiftAmountTy())); 1471 // fold (mulhs x, undef) -> 0 1472 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1473 return DAG.getConstant(0, VT); 1474 1475 return SDOperand(); 1476} 1477 1478SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1479 SDOperand N0 = N->getOperand(0); 1480 SDOperand N1 = N->getOperand(1); 1481 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1482 MVT::ValueType VT = N->getValueType(0); 1483 1484 // fold (mulhu x, 0) -> 0 1485 if (N1C && N1C->isNullValue()) 1486 return N1; 1487 // fold (mulhu x, 1) -> 0 1488 if (N1C && N1C->getAPIntValue() == 1) 1489 return DAG.getConstant(0, N0.getValueType()); 1490 // fold (mulhu x, undef) -> 0 1491 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1492 return DAG.getConstant(0, VT); 1493 1494 return SDOperand(); 1495} 1496 1497/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1498/// compute two values. LoOp and HiOp give the opcodes for the two computations 1499/// that are being performed. Return true if a simplification was made. 1500/// 1501SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1502 unsigned HiOp) { 1503 // If the high half is not needed, just compute the low half. 1504 bool HiExists = N->hasAnyUseOfValue(1); 1505 if (!HiExists && 1506 (!AfterLegalize || 1507 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1508 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1509 N->getNumOperands()); 1510 return CombineTo(N, Res, Res); 1511 } 1512 1513 // If the low half is not needed, just compute the high half. 1514 bool LoExists = N->hasAnyUseOfValue(0); 1515 if (!LoExists && 1516 (!AfterLegalize || 1517 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1518 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1519 N->getNumOperands()); 1520 return CombineTo(N, Res, Res); 1521 } 1522 1523 // If both halves are used, return as it is. 1524 if (LoExists && HiExists) 1525 return SDOperand(); 1526 1527 // If the two computed results can be simplified separately, separate them. 1528 if (LoExists) { 1529 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1530 N->op_begin(), N->getNumOperands()); 1531 AddToWorkList(Lo.Val); 1532 SDOperand LoOpt = combine(Lo.Val); 1533 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1534 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) 1535 return CombineTo(N, LoOpt, LoOpt); 1536 } 1537 1538 if (HiExists) { 1539 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1540 N->op_begin(), N->getNumOperands()); 1541 AddToWorkList(Hi.Val); 1542 SDOperand HiOpt = combine(Hi.Val); 1543 if (HiOpt.Val && HiOpt != Hi && 1544 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) 1545 return CombineTo(N, HiOpt, HiOpt); 1546 } 1547 return SDOperand(); 1548} 1549 1550SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1551 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1552 if (Res.Val) return Res; 1553 1554 return SDOperand(); 1555} 1556 1557SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1558 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1559 if (Res.Val) return Res; 1560 1561 return SDOperand(); 1562} 1563 1564SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1565 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1566 if (Res.Val) return Res; 1567 1568 return SDOperand(); 1569} 1570 1571SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1572 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1573 if (Res.Val) return Res; 1574 1575 return SDOperand(); 1576} 1577 1578/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1579/// two operands of the same opcode, try to simplify it. 1580SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1581 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1582 MVT::ValueType VT = N0.getValueType(); 1583 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1584 1585 // For each of OP in AND/OR/XOR: 1586 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1587 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1588 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1589 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1590 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1591 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1592 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1593 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1594 N0.getOperand(0).getValueType(), 1595 N0.getOperand(0), N1.getOperand(0)); 1596 AddToWorkList(ORNode.Val); 1597 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1598 } 1599 1600 // For each of OP in SHL/SRL/SRA/AND... 1601 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1602 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1603 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1604 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1605 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1606 N0.getOperand(1) == N1.getOperand(1)) { 1607 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1608 N0.getOperand(0).getValueType(), 1609 N0.getOperand(0), N1.getOperand(0)); 1610 AddToWorkList(ORNode.Val); 1611 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1612 } 1613 1614 return SDOperand(); 1615} 1616 1617SDOperand DAGCombiner::visitAND(SDNode *N) { 1618 SDOperand N0 = N->getOperand(0); 1619 SDOperand N1 = N->getOperand(1); 1620 SDOperand LL, LR, RL, RR, CC0, CC1; 1621 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1622 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1623 MVT::ValueType VT = N1.getValueType(); 1624 unsigned BitWidth = MVT::getSizeInBits(VT); 1625 1626 // fold vector ops 1627 if (MVT::isVector(VT)) { 1628 SDOperand FoldedVOp = SimplifyVBinOp(N); 1629 if (FoldedVOp.Val) return FoldedVOp; 1630 } 1631 1632 // fold (and x, undef) -> 0 1633 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1634 return DAG.getConstant(0, VT); 1635 // fold (and c1, c2) -> c1&c2 1636 if (N0C && N1C) 1637 return DAG.getNode(ISD::AND, VT, N0, N1); 1638 // canonicalize constant to RHS 1639 if (N0C && !N1C) 1640 return DAG.getNode(ISD::AND, VT, N1, N0); 1641 // fold (and x, -1) -> x 1642 if (N1C && N1C->isAllOnesValue()) 1643 return N0; 1644 // if (and x, c) is known to be zero, return 0 1645 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 1646 APInt::getAllOnesValue(BitWidth))) 1647 return DAG.getConstant(0, VT); 1648 // reassociate and 1649 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1650 if (RAND.Val != 0) 1651 return RAND; 1652 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1653 if (N1C && N0.getOpcode() == ISD::OR) 1654 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1655 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1656 return N1; 1657 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1658 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1659 SDOperand N0Op0 = N0.getOperand(0); 1660 APInt Mask = ~N1C->getAPIntValue(); 1661 Mask.trunc(N0Op0.getValueSizeInBits()); 1662 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1663 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1664 N0Op0); 1665 1666 // Replace uses of the AND with uses of the Zero extend node. 1667 CombineTo(N, Zext); 1668 1669 // We actually want to replace all uses of the any_extend with the 1670 // zero_extend, to avoid duplicating things. This will later cause this 1671 // AND to be folded. 1672 CombineTo(N0.Val, Zext); 1673 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1674 } 1675 } 1676 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1677 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1678 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1679 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1680 1681 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1682 MVT::isInteger(LL.getValueType())) { 1683 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1684 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1685 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1686 AddToWorkList(ORNode.Val); 1687 return DAG.getSetCC(VT, ORNode, LR, Op1); 1688 } 1689 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1690 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1691 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1692 AddToWorkList(ANDNode.Val); 1693 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1694 } 1695 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1696 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1697 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1698 AddToWorkList(ORNode.Val); 1699 return DAG.getSetCC(VT, ORNode, LR, Op1); 1700 } 1701 } 1702 // canonicalize equivalent to ll == rl 1703 if (LL == RR && LR == RL) { 1704 Op1 = ISD::getSetCCSwappedOperands(Op1); 1705 std::swap(RL, RR); 1706 } 1707 if (LL == RL && LR == RR) { 1708 bool isInteger = MVT::isInteger(LL.getValueType()); 1709 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1710 if (Result != ISD::SETCC_INVALID) 1711 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1712 } 1713 } 1714 1715 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1716 if (N0.getOpcode() == N1.getOpcode()) { 1717 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1718 if (Tmp.Val) return Tmp; 1719 } 1720 1721 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1722 // fold (and (sra)) -> (and (srl)) when possible. 1723 if (!MVT::isVector(VT) && 1724 SimplifyDemandedBits(SDOperand(N, 0))) 1725 return SDOperand(N, 0); 1726 // fold (zext_inreg (extload x)) -> (zextload x) 1727 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1728 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1729 MVT::ValueType EVT = LN0->getMemoryVT(); 1730 // If we zero all the possible extended bits, then we can turn this into 1731 // a zextload if we are running before legalize or the operation is legal. 1732 unsigned BitWidth = N1.getValueSizeInBits(); 1733 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1734 BitWidth - MVT::getSizeInBits(EVT))) && 1735 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1736 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1737 LN0->getBasePtr(), LN0->getSrcValue(), 1738 LN0->getSrcValueOffset(), EVT, 1739 LN0->isVolatile(), 1740 LN0->getAlignment()); 1741 AddToWorkList(N); 1742 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1743 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1744 } 1745 } 1746 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1747 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1748 N0.hasOneUse()) { 1749 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1750 MVT::ValueType EVT = LN0->getMemoryVT(); 1751 // If we zero all the possible extended bits, then we can turn this into 1752 // a zextload if we are running before legalize or the operation is legal. 1753 unsigned BitWidth = N1.getValueSizeInBits(); 1754 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1755 BitWidth - MVT::getSizeInBits(EVT))) && 1756 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1757 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1758 LN0->getBasePtr(), LN0->getSrcValue(), 1759 LN0->getSrcValueOffset(), EVT, 1760 LN0->isVolatile(), 1761 LN0->getAlignment()); 1762 AddToWorkList(N); 1763 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1764 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1765 } 1766 } 1767 1768 // fold (and (load x), 255) -> (zextload x, i8) 1769 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1770 if (N1C && N0.getOpcode() == ISD::LOAD) { 1771 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1772 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1773 LN0->isUnindexed() && N0.hasOneUse()) { 1774 MVT::ValueType EVT, LoadedVT; 1775 if (N1C->getAPIntValue() == 255) 1776 EVT = MVT::i8; 1777 else if (N1C->getAPIntValue() == 65535) 1778 EVT = MVT::i16; 1779 else if (N1C->getAPIntValue() == ~0U) 1780 EVT = MVT::i32; 1781 else 1782 EVT = MVT::Other; 1783 1784 LoadedVT = LN0->getMemoryVT(); 1785 if (EVT != MVT::Other && LoadedVT > EVT && 1786 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1787 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1788 // For big endian targets, we need to add an offset to the pointer to 1789 // load the correct bytes. For little endian systems, we merely need to 1790 // read fewer bytes from the same pointer. 1791 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1792 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1793 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1794 unsigned Alignment = LN0->getAlignment(); 1795 SDOperand NewPtr = LN0->getBasePtr(); 1796 if (TLI.isBigEndian()) { 1797 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1798 DAG.getConstant(PtrOff, PtrType)); 1799 Alignment = MinAlign(Alignment, PtrOff); 1800 } 1801 AddToWorkList(NewPtr.Val); 1802 SDOperand Load = 1803 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1804 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1805 LN0->isVolatile(), Alignment); 1806 AddToWorkList(N); 1807 CombineTo(N0.Val, Load, Load.getValue(1)); 1808 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1809 } 1810 } 1811 } 1812 1813 return SDOperand(); 1814} 1815 1816SDOperand DAGCombiner::visitOR(SDNode *N) { 1817 SDOperand N0 = N->getOperand(0); 1818 SDOperand N1 = N->getOperand(1); 1819 SDOperand LL, LR, RL, RR, CC0, CC1; 1820 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1821 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1822 MVT::ValueType VT = N1.getValueType(); 1823 1824 // fold vector ops 1825 if (MVT::isVector(VT)) { 1826 SDOperand FoldedVOp = SimplifyVBinOp(N); 1827 if (FoldedVOp.Val) return FoldedVOp; 1828 } 1829 1830 // fold (or x, undef) -> -1 1831 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1832 return DAG.getConstant(~0ULL, VT); 1833 // fold (or c1, c2) -> c1|c2 1834 if (N0C && N1C) 1835 return DAG.getNode(ISD::OR, VT, N0, N1); 1836 // canonicalize constant to RHS 1837 if (N0C && !N1C) 1838 return DAG.getNode(ISD::OR, VT, N1, N0); 1839 // fold (or x, 0) -> x 1840 if (N1C && N1C->isNullValue()) 1841 return N0; 1842 // fold (or x, -1) -> -1 1843 if (N1C && N1C->isAllOnesValue()) 1844 return N1; 1845 // fold (or x, c) -> c iff (x & ~c) == 0 1846 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1847 return N1; 1848 // reassociate or 1849 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1850 if (ROR.Val != 0) 1851 return ROR; 1852 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1853 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1854 isa<ConstantSDNode>(N0.getOperand(1))) { 1855 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1856 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1857 N1), 1858 DAG.getConstant(N1C->getAPIntValue() | 1859 C1->getAPIntValue(), VT)); 1860 } 1861 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1862 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1863 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1864 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1865 1866 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1867 MVT::isInteger(LL.getValueType())) { 1868 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1869 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1870 if (cast<ConstantSDNode>(LR)->isNullValue() && 1871 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1872 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1873 AddToWorkList(ORNode.Val); 1874 return DAG.getSetCC(VT, ORNode, LR, Op1); 1875 } 1876 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1877 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1878 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1879 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1880 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1881 AddToWorkList(ANDNode.Val); 1882 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1883 } 1884 } 1885 // canonicalize equivalent to ll == rl 1886 if (LL == RR && LR == RL) { 1887 Op1 = ISD::getSetCCSwappedOperands(Op1); 1888 std::swap(RL, RR); 1889 } 1890 if (LL == RL && LR == RR) { 1891 bool isInteger = MVT::isInteger(LL.getValueType()); 1892 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1893 if (Result != ISD::SETCC_INVALID) 1894 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1895 } 1896 } 1897 1898 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1899 if (N0.getOpcode() == N1.getOpcode()) { 1900 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1901 if (Tmp.Val) return Tmp; 1902 } 1903 1904 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1905 if (N0.getOpcode() == ISD::AND && 1906 N1.getOpcode() == ISD::AND && 1907 N0.getOperand(1).getOpcode() == ISD::Constant && 1908 N1.getOperand(1).getOpcode() == ISD::Constant && 1909 // Don't increase # computations. 1910 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1911 // We can only do this xform if we know that bits from X that are set in C2 1912 // but not in C1 are already zero. Likewise for Y. 1913 const APInt &LHSMask = 1914 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1915 const APInt &RHSMask = 1916 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1917 1918 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1919 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1920 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1921 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1922 } 1923 } 1924 1925 1926 // See if this is some rotate idiom. 1927 if (SDNode *Rot = MatchRotate(N0, N1)) 1928 return SDOperand(Rot, 0); 1929 1930 return SDOperand(); 1931} 1932 1933 1934/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1935static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1936 if (Op.getOpcode() == ISD::AND) { 1937 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1938 Mask = Op.getOperand(1); 1939 Op = Op.getOperand(0); 1940 } else { 1941 return false; 1942 } 1943 } 1944 1945 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1946 Shift = Op; 1947 return true; 1948 } 1949 return false; 1950} 1951 1952 1953// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1954// idioms for rotate, and if the target supports rotation instructions, generate 1955// a rot[lr]. 1956SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1957 // Must be a legal type. Expanded an promoted things won't work with rotates. 1958 MVT::ValueType VT = LHS.getValueType(); 1959 if (!TLI.isTypeLegal(VT)) return 0; 1960 1961 // The target must have at least one rotate flavor. 1962 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1963 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1964 if (!HasROTL && !HasROTR) return 0; 1965 1966 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1967 SDOperand LHSShift; // The shift. 1968 SDOperand LHSMask; // AND value if any. 1969 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1970 return 0; // Not part of a rotate. 1971 1972 SDOperand RHSShift; // The shift. 1973 SDOperand RHSMask; // AND value if any. 1974 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1975 return 0; // Not part of a rotate. 1976 1977 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1978 return 0; // Not shifting the same value. 1979 1980 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1981 return 0; // Shifts must disagree. 1982 1983 // Canonicalize shl to left side in a shl/srl pair. 1984 if (RHSShift.getOpcode() == ISD::SHL) { 1985 std::swap(LHS, RHS); 1986 std::swap(LHSShift, RHSShift); 1987 std::swap(LHSMask , RHSMask ); 1988 } 1989 1990 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1991 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1992 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1993 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1994 1995 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1996 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1997 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1998 RHSShiftAmt.getOpcode() == ISD::Constant) { 1999 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 2000 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 2001 if ((LShVal + RShVal) != OpSizeInBits) 2002 return 0; 2003 2004 SDOperand Rot; 2005 if (HasROTL) 2006 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2007 else 2008 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2009 2010 // If there is an AND of either shifted operand, apply it to the result. 2011 if (LHSMask.Val || RHSMask.Val) { 2012 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2013 2014 if (LHSMask.Val) { 2015 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2016 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2017 } 2018 if (RHSMask.Val) { 2019 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2020 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2021 } 2022 2023 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2024 } 2025 2026 return Rot.Val; 2027 } 2028 2029 // If there is a mask here, and we have a variable shift, we can't be sure 2030 // that we're masking out the right stuff. 2031 if (LHSMask.Val || RHSMask.Val) 2032 return 0; 2033 2034 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2035 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2036 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2037 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2038 if (ConstantSDNode *SUBC = 2039 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2040 if (SUBC->getAPIntValue() == OpSizeInBits) { 2041 if (HasROTL) 2042 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2043 else 2044 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2045 } 2046 } 2047 } 2048 2049 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2050 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2051 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2052 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2053 if (ConstantSDNode *SUBC = 2054 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2055 if (SUBC->getAPIntValue() == OpSizeInBits) { 2056 if (HasROTL) 2057 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2058 else 2059 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2060 } 2061 } 2062 } 2063 2064 // Look for sign/zext/any-extended cases: 2065 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2066 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2067 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2068 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2069 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2070 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2071 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 2072 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 2073 if (RExtOp0.getOpcode() == ISD::SUB && 2074 RExtOp0.getOperand(1) == LExtOp0) { 2075 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2076 // (rotr x, y) 2077 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2078 // (rotl x, (sub 32, y)) 2079 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2080 if (SUBC->getAPIntValue() == OpSizeInBits) { 2081 if (HasROTL) 2082 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2083 else 2084 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2085 } 2086 } 2087 } else if (LExtOp0.getOpcode() == ISD::SUB && 2088 RExtOp0 == LExtOp0.getOperand(1)) { 2089 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2090 // (rotl x, y) 2091 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2092 // (rotr x, (sub 32, y)) 2093 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2094 if (SUBC->getAPIntValue() == OpSizeInBits) { 2095 if (HasROTL) 2096 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2097 else 2098 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2099 } 2100 } 2101 } 2102 } 2103 2104 return 0; 2105} 2106 2107 2108SDOperand DAGCombiner::visitXOR(SDNode *N) { 2109 SDOperand N0 = N->getOperand(0); 2110 SDOperand N1 = N->getOperand(1); 2111 SDOperand LHS, RHS, CC; 2112 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2113 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2114 MVT::ValueType VT = N0.getValueType(); 2115 2116 // fold vector ops 2117 if (MVT::isVector(VT)) { 2118 SDOperand FoldedVOp = SimplifyVBinOp(N); 2119 if (FoldedVOp.Val) return FoldedVOp; 2120 } 2121 2122 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2123 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2124 return DAG.getConstant(0, VT); 2125 // fold (xor x, undef) -> undef 2126 if (N0.getOpcode() == ISD::UNDEF) 2127 return N0; 2128 if (N1.getOpcode() == ISD::UNDEF) 2129 return N1; 2130 // fold (xor c1, c2) -> c1^c2 2131 if (N0C && N1C) 2132 return DAG.getNode(ISD::XOR, VT, N0, N1); 2133 // canonicalize constant to RHS 2134 if (N0C && !N1C) 2135 return DAG.getNode(ISD::XOR, VT, N1, N0); 2136 // fold (xor x, 0) -> x 2137 if (N1C && N1C->isNullValue()) 2138 return N0; 2139 // reassociate xor 2140 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2141 if (RXOR.Val != 0) 2142 return RXOR; 2143 // fold !(x cc y) -> (x !cc y) 2144 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2145 bool isInt = MVT::isInteger(LHS.getValueType()); 2146 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2147 isInt); 2148 if (N0.getOpcode() == ISD::SETCC) 2149 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2150 if (N0.getOpcode() == ISD::SELECT_CC) 2151 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2152 assert(0 && "Unhandled SetCC Equivalent!"); 2153 abort(); 2154 } 2155 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2156 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2157 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2158 SDOperand V = N0.getOperand(0); 2159 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2160 DAG.getConstant(1, V.getValueType())); 2161 AddToWorkList(V.Val); 2162 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2163 } 2164 2165 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2166 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2167 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2168 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2169 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2170 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2171 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2172 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2173 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2174 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2175 } 2176 } 2177 // fold !(x or y) -> (!x and !y) iff x or y are constants 2178 if (N1C && N1C->isAllOnesValue() && 2179 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2180 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2181 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2182 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2183 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2184 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2185 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2186 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2187 } 2188 } 2189 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2190 if (N1C && N0.getOpcode() == ISD::XOR) { 2191 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2192 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2193 if (N00C) 2194 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2195 DAG.getConstant(N1C->getAPIntValue()^ 2196 N00C->getAPIntValue(), VT)); 2197 if (N01C) 2198 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2199 DAG.getConstant(N1C->getAPIntValue()^ 2200 N01C->getAPIntValue(), VT)); 2201 } 2202 // fold (xor x, x) -> 0 2203 if (N0 == N1) { 2204 if (!MVT::isVector(VT)) { 2205 return DAG.getConstant(0, VT); 2206 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2207 // Produce a vector of zeros. 2208 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2209 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2210 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2211 } 2212 } 2213 2214 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2215 if (N0.getOpcode() == N1.getOpcode()) { 2216 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2217 if (Tmp.Val) return Tmp; 2218 } 2219 2220 // Simplify the expression using non-local knowledge. 2221 if (!MVT::isVector(VT) && 2222 SimplifyDemandedBits(SDOperand(N, 0))) 2223 return SDOperand(N, 0); 2224 2225 return SDOperand(); 2226} 2227 2228/// visitShiftByConstant - Handle transforms common to the three shifts, when 2229/// the shift amount is a constant. 2230SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2231 SDNode *LHS = N->getOperand(0).Val; 2232 if (!LHS->hasOneUse()) return SDOperand(); 2233 2234 // We want to pull some binops through shifts, so that we have (and (shift)) 2235 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2236 // thing happens with address calculations, so it's important to canonicalize 2237 // it. 2238 bool HighBitSet = false; // Can we transform this if the high bit is set? 2239 2240 switch (LHS->getOpcode()) { 2241 default: return SDOperand(); 2242 case ISD::OR: 2243 case ISD::XOR: 2244 HighBitSet = false; // We can only transform sra if the high bit is clear. 2245 break; 2246 case ISD::AND: 2247 HighBitSet = true; // We can only transform sra if the high bit is set. 2248 break; 2249 case ISD::ADD: 2250 if (N->getOpcode() != ISD::SHL) 2251 return SDOperand(); // only shl(add) not sr[al](add). 2252 HighBitSet = false; // We can only transform sra if the high bit is clear. 2253 break; 2254 } 2255 2256 // We require the RHS of the binop to be a constant as well. 2257 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2258 if (!BinOpCst) return SDOperand(); 2259 2260 2261 // FIXME: disable this for unless the input to the binop is a shift by a 2262 // constant. If it is not a shift, it pessimizes some common cases like: 2263 // 2264 //void foo(int *X, int i) { X[i & 1235] = 1; } 2265 //int bar(int *X, int i) { return X[i & 255]; } 2266 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2267 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2268 BinOpLHSVal->getOpcode() != ISD::SRA && 2269 BinOpLHSVal->getOpcode() != ISD::SRL) || 2270 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2271 return SDOperand(); 2272 2273 MVT::ValueType VT = N->getValueType(0); 2274 2275 // If this is a signed shift right, and the high bit is modified 2276 // by the logical operation, do not perform the transformation. 2277 // The highBitSet boolean indicates the value of the high bit of 2278 // the constant which would cause it to be modified for this 2279 // operation. 2280 if (N->getOpcode() == ISD::SRA) { 2281 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2282 if (BinOpRHSSignSet != HighBitSet) 2283 return SDOperand(); 2284 } 2285 2286 // Fold the constants, shifting the binop RHS by the shift amount. 2287 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2288 LHS->getOperand(1), N->getOperand(1)); 2289 2290 // Create the new shift. 2291 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2292 N->getOperand(1)); 2293 2294 // Create the new binop. 2295 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2296} 2297 2298 2299SDOperand DAGCombiner::visitSHL(SDNode *N) { 2300 SDOperand N0 = N->getOperand(0); 2301 SDOperand N1 = N->getOperand(1); 2302 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2303 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2304 MVT::ValueType VT = N0.getValueType(); 2305 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2306 2307 // fold (shl c1, c2) -> c1<<c2 2308 if (N0C && N1C) 2309 return DAG.getNode(ISD::SHL, VT, N0, N1); 2310 // fold (shl 0, x) -> 0 2311 if (N0C && N0C->isNullValue()) 2312 return N0; 2313 // fold (shl x, c >= size(x)) -> undef 2314 if (N1C && N1C->getValue() >= OpSizeInBits) 2315 return DAG.getNode(ISD::UNDEF, VT); 2316 // fold (shl x, 0) -> x 2317 if (N1C && N1C->isNullValue()) 2318 return N0; 2319 // if (shl x, c) is known to be zero, return 0 2320 if (DAG.MaskedValueIsZero(SDOperand(N, 0), 2321 APInt::getAllOnesValue(MVT::getSizeInBits(VT)))) 2322 return DAG.getConstant(0, VT); 2323 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2324 return SDOperand(N, 0); 2325 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2326 if (N1C && N0.getOpcode() == ISD::SHL && 2327 N0.getOperand(1).getOpcode() == ISD::Constant) { 2328 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2329 uint64_t c2 = N1C->getValue(); 2330 if (c1 + c2 > OpSizeInBits) 2331 return DAG.getConstant(0, VT); 2332 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2333 DAG.getConstant(c1 + c2, N1.getValueType())); 2334 } 2335 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2336 // (srl (and x, -1 << c1), c1-c2) 2337 if (N1C && N0.getOpcode() == ISD::SRL && 2338 N0.getOperand(1).getOpcode() == ISD::Constant) { 2339 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2340 uint64_t c2 = N1C->getValue(); 2341 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2342 DAG.getConstant(~0ULL << c1, VT)); 2343 if (c2 > c1) 2344 return DAG.getNode(ISD::SHL, VT, Mask, 2345 DAG.getConstant(c2-c1, N1.getValueType())); 2346 else 2347 return DAG.getNode(ISD::SRL, VT, Mask, 2348 DAG.getConstant(c1-c2, N1.getValueType())); 2349 } 2350 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2351 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2352 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2353 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2354 2355 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2356} 2357 2358SDOperand DAGCombiner::visitSRA(SDNode *N) { 2359 SDOperand N0 = N->getOperand(0); 2360 SDOperand N1 = N->getOperand(1); 2361 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2362 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2363 MVT::ValueType VT = N0.getValueType(); 2364 2365 // fold (sra c1, c2) -> c1>>c2 2366 if (N0C && N1C) 2367 return DAG.getNode(ISD::SRA, VT, N0, N1); 2368 // fold (sra 0, x) -> 0 2369 if (N0C && N0C->isNullValue()) 2370 return N0; 2371 // fold (sra -1, x) -> -1 2372 if (N0C && N0C->isAllOnesValue()) 2373 return N0; 2374 // fold (sra x, c >= size(x)) -> undef 2375 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2376 return DAG.getNode(ISD::UNDEF, VT); 2377 // fold (sra x, 0) -> x 2378 if (N1C && N1C->isNullValue()) 2379 return N0; 2380 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2381 // sext_inreg. 2382 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2383 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2384 MVT::ValueType EVT; 2385 switch (LowBits) { 2386 default: EVT = MVT::Other; break; 2387 case 1: EVT = MVT::i1; break; 2388 case 8: EVT = MVT::i8; break; 2389 case 16: EVT = MVT::i16; break; 2390 case 32: EVT = MVT::i32; break; 2391 } 2392 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2393 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2394 DAG.getValueType(EVT)); 2395 } 2396 2397 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2398 if (N1C && N0.getOpcode() == ISD::SRA) { 2399 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2400 unsigned Sum = N1C->getValue() + C1->getValue(); 2401 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2402 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2403 DAG.getConstant(Sum, N1C->getValueType(0))); 2404 } 2405 } 2406 2407 // fold sra (shl X, m), result_size - n 2408 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2409 // result_size - n != m. 2410 // If truncate is free for the target sext(shl) is likely to result in better 2411 // code. 2412 if (N0.getOpcode() == ISD::SHL) { 2413 // Get the two constanst of the shifts, CN0 = m, CN = n. 2414 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2415 if (N01C && N1C) { 2416 // Determine what the truncate's result bitsize and type would be. 2417 unsigned VTValSize = MVT::getSizeInBits(VT); 2418 MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue()); 2419 // Determine the residual right-shift amount. 2420 unsigned ShiftAmt = N1C->getValue() - N01C->getValue(); 2421 2422 // If the shift is not a no-op (in which case this should be just a sign 2423 // extend already), the truncated to type is legal, sign_extend is legal 2424 // on that type, and the the truncate to that type is both legal and free, 2425 // perform the transform. 2426 if (ShiftAmt && 2427 TLI.isTypeLegal(TruncVT) && 2428 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2429 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2430 TLI.isTruncateFree(VT, TruncVT)) { 2431 2432 SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2433 SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2434 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2435 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2436 } 2437 } 2438 } 2439 2440 // Simplify, based on bits shifted out of the LHS. 2441 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2442 return SDOperand(N, 0); 2443 2444 2445 // If the sign bit is known to be zero, switch this to a SRL. 2446 if (DAG.SignBitIsZero(N0)) 2447 return DAG.getNode(ISD::SRL, VT, N0, N1); 2448 2449 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2450} 2451 2452SDOperand DAGCombiner::visitSRL(SDNode *N) { 2453 SDOperand N0 = N->getOperand(0); 2454 SDOperand N1 = N->getOperand(1); 2455 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2456 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2457 MVT::ValueType VT = N0.getValueType(); 2458 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2459 2460 // fold (srl c1, c2) -> c1 >>u c2 2461 if (N0C && N1C) 2462 return DAG.getNode(ISD::SRL, VT, N0, N1); 2463 // fold (srl 0, x) -> 0 2464 if (N0C && N0C->isNullValue()) 2465 return N0; 2466 // fold (srl x, c >= size(x)) -> undef 2467 if (N1C && N1C->getValue() >= OpSizeInBits) 2468 return DAG.getNode(ISD::UNDEF, VT); 2469 // fold (srl x, 0) -> x 2470 if (N1C && N1C->isNullValue()) 2471 return N0; 2472 // if (srl x, c) is known to be zero, return 0 2473 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 2474 APInt::getAllOnesValue(OpSizeInBits))) 2475 return DAG.getConstant(0, VT); 2476 2477 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2478 if (N1C && N0.getOpcode() == ISD::SRL && 2479 N0.getOperand(1).getOpcode() == ISD::Constant) { 2480 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2481 uint64_t c2 = N1C->getValue(); 2482 if (c1 + c2 > OpSizeInBits) 2483 return DAG.getConstant(0, VT); 2484 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2485 DAG.getConstant(c1 + c2, N1.getValueType())); 2486 } 2487 2488 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2489 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2490 // Shifting in all undef bits? 2491 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2492 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2493 return DAG.getNode(ISD::UNDEF, VT); 2494 2495 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2496 AddToWorkList(SmallShift.Val); 2497 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2498 } 2499 2500 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2501 // bit, which is unmodified by sra. 2502 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2503 if (N0.getOpcode() == ISD::SRA) 2504 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2505 } 2506 2507 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2508 if (N1C && N0.getOpcode() == ISD::CTLZ && 2509 N1C->getAPIntValue() == Log2_32(MVT::getSizeInBits(VT))) { 2510 APInt KnownZero, KnownOne; 2511 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 2512 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2513 2514 // If any of the input bits are KnownOne, then the input couldn't be all 2515 // zeros, thus the result of the srl will always be zero. 2516 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2517 2518 // If all of the bits input the to ctlz node are known to be zero, then 2519 // the result of the ctlz is "32" and the result of the shift is one. 2520 APInt UnknownBits = ~KnownZero & Mask; 2521 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2522 2523 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2524 if ((UnknownBits & (UnknownBits-1)) == 0) { 2525 // Okay, we know that only that the single bit specified by UnknownBits 2526 // could be set on input to the CTLZ node. If this bit is set, the SRL 2527 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2528 // to an SRL,XOR pair, which is likely to simplify more. 2529 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2530 SDOperand Op = N0.getOperand(0); 2531 if (ShAmt) { 2532 Op = DAG.getNode(ISD::SRL, VT, Op, 2533 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2534 AddToWorkList(Op.Val); 2535 } 2536 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2537 } 2538 } 2539 2540 // fold operands of srl based on knowledge that the low bits are not 2541 // demanded. 2542 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2543 return SDOperand(N, 0); 2544 2545 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2546} 2547 2548SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2549 SDOperand N0 = N->getOperand(0); 2550 MVT::ValueType VT = N->getValueType(0); 2551 2552 // fold (ctlz c1) -> c2 2553 if (isa<ConstantSDNode>(N0)) 2554 return DAG.getNode(ISD::CTLZ, VT, N0); 2555 return SDOperand(); 2556} 2557 2558SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2559 SDOperand N0 = N->getOperand(0); 2560 MVT::ValueType VT = N->getValueType(0); 2561 2562 // fold (cttz c1) -> c2 2563 if (isa<ConstantSDNode>(N0)) 2564 return DAG.getNode(ISD::CTTZ, VT, N0); 2565 return SDOperand(); 2566} 2567 2568SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2569 SDOperand N0 = N->getOperand(0); 2570 MVT::ValueType VT = N->getValueType(0); 2571 2572 // fold (ctpop c1) -> c2 2573 if (isa<ConstantSDNode>(N0)) 2574 return DAG.getNode(ISD::CTPOP, VT, N0); 2575 return SDOperand(); 2576} 2577 2578SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2579 SDOperand N0 = N->getOperand(0); 2580 SDOperand N1 = N->getOperand(1); 2581 SDOperand N2 = N->getOperand(2); 2582 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2583 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2584 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2585 MVT::ValueType VT = N->getValueType(0); 2586 MVT::ValueType VT0 = N0.getValueType(); 2587 2588 // fold select C, X, X -> X 2589 if (N1 == N2) 2590 return N1; 2591 // fold select true, X, Y -> X 2592 if (N0C && !N0C->isNullValue()) 2593 return N1; 2594 // fold select false, X, Y -> Y 2595 if (N0C && N0C->isNullValue()) 2596 return N2; 2597 // fold select C, 1, X -> C | X 2598 if (MVT::i1 == VT && N1C && N1C->getAPIntValue() == 1) 2599 return DAG.getNode(ISD::OR, VT, N0, N2); 2600 // fold select C, 0, 1 -> ~C 2601 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2602 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2603 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2604 if (VT == VT0) 2605 return XORNode; 2606 AddToWorkList(XORNode.Val); 2607 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2608 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2609 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2610 } 2611 // fold select C, 0, X -> ~C & X 2612 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2613 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2614 AddToWorkList(XORNode.Val); 2615 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2616 } 2617 // fold select C, X, 1 -> ~C | X 2618 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2619 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2620 AddToWorkList(XORNode.Val); 2621 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2622 } 2623 // fold select C, X, 0 -> C & X 2624 // FIXME: this should check for C type == X type, not i1? 2625 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2626 return DAG.getNode(ISD::AND, VT, N0, N1); 2627 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2628 if (MVT::i1 == VT && N0 == N1) 2629 return DAG.getNode(ISD::OR, VT, N0, N2); 2630 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2631 if (MVT::i1 == VT && N0 == N2) 2632 return DAG.getNode(ISD::AND, VT, N0, N1); 2633 2634 // If we can fold this based on the true/false value, do so. 2635 if (SimplifySelectOps(N, N1, N2)) 2636 return SDOperand(N, 0); // Don't revisit N. 2637 2638 // fold selects based on a setcc into other things, such as min/max/abs 2639 if (N0.getOpcode() == ISD::SETCC) { 2640 // FIXME: 2641 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2642 // having to say they don't support SELECT_CC on every type the DAG knows 2643 // about, since there is no way to mark an opcode illegal at all value types 2644 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2645 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2646 N1, N2, N0.getOperand(2)); 2647 else 2648 return SimplifySelect(N0, N1, N2); 2649 } 2650 return SDOperand(); 2651} 2652 2653SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2654 SDOperand N0 = N->getOperand(0); 2655 SDOperand N1 = N->getOperand(1); 2656 SDOperand N2 = N->getOperand(2); 2657 SDOperand N3 = N->getOperand(3); 2658 SDOperand N4 = N->getOperand(4); 2659 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2660 2661 // fold select_cc lhs, rhs, x, x, cc -> x 2662 if (N2 == N3) 2663 return N2; 2664 2665 // Determine if the condition we're dealing with is constant 2666 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2667 if (SCC.Val) AddToWorkList(SCC.Val); 2668 2669 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2670 if (!SCCC->isNullValue()) 2671 return N2; // cond always true -> true val 2672 else 2673 return N3; // cond always false -> false val 2674 } 2675 2676 // Fold to a simpler select_cc 2677 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2678 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2679 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2680 SCC.getOperand(2)); 2681 2682 // If we can fold this based on the true/false value, do so. 2683 if (SimplifySelectOps(N, N2, N3)) 2684 return SDOperand(N, 0); // Don't revisit N. 2685 2686 // fold select_cc into other things, such as min/max/abs 2687 return SimplifySelectCC(N0, N1, N2, N3, CC); 2688} 2689 2690SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2691 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2692 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2693} 2694 2695// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2696// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2697// transformation. Returns true if extension are possible and the above 2698// mentioned transformation is profitable. 2699static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2700 unsigned ExtOpc, 2701 SmallVector<SDNode*, 4> &ExtendNodes, 2702 TargetLowering &TLI) { 2703 bool HasCopyToRegUses = false; 2704 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2705 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2706 UI != UE; ++UI) { 2707 SDNode *User = *UI; 2708 if (User == N) 2709 continue; 2710 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2711 if (User->getOpcode() == ISD::SETCC) { 2712 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2713 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2714 // Sign bits will be lost after a zext. 2715 return false; 2716 bool Add = false; 2717 for (unsigned i = 0; i != 2; ++i) { 2718 SDOperand UseOp = User->getOperand(i); 2719 if (UseOp == N0) 2720 continue; 2721 if (!isa<ConstantSDNode>(UseOp)) 2722 return false; 2723 Add = true; 2724 } 2725 if (Add) 2726 ExtendNodes.push_back(User); 2727 } else { 2728 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2729 SDOperand UseOp = User->getOperand(i); 2730 if (UseOp == N0) { 2731 // If truncate from extended type to original load type is free 2732 // on this target, then it's ok to extend a CopyToReg. 2733 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2734 HasCopyToRegUses = true; 2735 else 2736 return false; 2737 } 2738 } 2739 } 2740 } 2741 2742 if (HasCopyToRegUses) { 2743 bool BothLiveOut = false; 2744 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2745 UI != UE; ++UI) { 2746 SDNode *User = *UI; 2747 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2748 SDOperand UseOp = User->getOperand(i); 2749 if (UseOp.Val == N && UseOp.ResNo == 0) { 2750 BothLiveOut = true; 2751 break; 2752 } 2753 } 2754 } 2755 if (BothLiveOut) 2756 // Both unextended and extended values are live out. There had better be 2757 // good a reason for the transformation. 2758 return ExtendNodes.size(); 2759 } 2760 return true; 2761} 2762 2763SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2764 SDOperand N0 = N->getOperand(0); 2765 MVT::ValueType VT = N->getValueType(0); 2766 2767 // fold (sext c1) -> c1 2768 if (isa<ConstantSDNode>(N0)) 2769 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2770 2771 // fold (sext (sext x)) -> (sext x) 2772 // fold (sext (aext x)) -> (sext x) 2773 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2774 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2775 2776 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2777 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2778 if (N0.getOpcode() == ISD::TRUNCATE) { 2779 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2780 if (NarrowLoad.Val) { 2781 if (NarrowLoad.Val != N0.Val) 2782 CombineTo(N0.Val, NarrowLoad); 2783 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2784 } 2785 } 2786 2787 // See if the value being truncated is already sign extended. If so, just 2788 // eliminate the trunc/sext pair. 2789 if (N0.getOpcode() == ISD::TRUNCATE) { 2790 SDOperand Op = N0.getOperand(0); 2791 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2792 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2793 unsigned DestBits = MVT::getSizeInBits(VT); 2794 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2795 2796 if (OpBits == DestBits) { 2797 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2798 // bits, it is already ready. 2799 if (NumSignBits > DestBits-MidBits) 2800 return Op; 2801 } else if (OpBits < DestBits) { 2802 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2803 // bits, just sext from i32. 2804 if (NumSignBits > OpBits-MidBits) 2805 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2806 } else { 2807 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2808 // bits, just truncate to i32. 2809 if (NumSignBits > OpBits-MidBits) 2810 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2811 } 2812 2813 // fold (sext (truncate x)) -> (sextinreg x). 2814 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2815 N0.getValueType())) { 2816 if (Op.getValueType() < VT) 2817 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2818 else if (Op.getValueType() > VT) 2819 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2820 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2821 DAG.getValueType(N0.getValueType())); 2822 } 2823 } 2824 2825 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2826 if (ISD::isNON_EXTLoad(N0.Val) && 2827 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2828 bool DoXform = true; 2829 SmallVector<SDNode*, 4> SetCCs; 2830 if (!N0.hasOneUse()) 2831 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2832 if (DoXform) { 2833 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2834 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2835 LN0->getBasePtr(), LN0->getSrcValue(), 2836 LN0->getSrcValueOffset(), 2837 N0.getValueType(), 2838 LN0->isVolatile(), 2839 LN0->getAlignment()); 2840 CombineTo(N, ExtLoad); 2841 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2842 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2843 // Extend SetCC uses if necessary. 2844 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2845 SDNode *SetCC = SetCCs[i]; 2846 SmallVector<SDOperand, 4> Ops; 2847 for (unsigned j = 0; j != 2; ++j) { 2848 SDOperand SOp = SetCC->getOperand(j); 2849 if (SOp == Trunc) 2850 Ops.push_back(ExtLoad); 2851 else 2852 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2853 } 2854 Ops.push_back(SetCC->getOperand(2)); 2855 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2856 &Ops[0], Ops.size())); 2857 } 2858 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2859 } 2860 } 2861 2862 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2863 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2864 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2865 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2866 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2867 MVT::ValueType EVT = LN0->getMemoryVT(); 2868 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2869 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2870 LN0->getBasePtr(), LN0->getSrcValue(), 2871 LN0->getSrcValueOffset(), EVT, 2872 LN0->isVolatile(), 2873 LN0->getAlignment()); 2874 CombineTo(N, ExtLoad); 2875 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2876 ExtLoad.getValue(1)); 2877 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2878 } 2879 } 2880 2881 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2882 if (N0.getOpcode() == ISD::SETCC) { 2883 SDOperand SCC = 2884 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2885 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2886 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2887 if (SCC.Val) return SCC; 2888 } 2889 2890 return SDOperand(); 2891} 2892 2893SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2894 SDOperand N0 = N->getOperand(0); 2895 MVT::ValueType VT = N->getValueType(0); 2896 2897 // fold (zext c1) -> c1 2898 if (isa<ConstantSDNode>(N0)) 2899 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2900 // fold (zext (zext x)) -> (zext x) 2901 // fold (zext (aext x)) -> (zext x) 2902 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2903 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2904 2905 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2906 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2907 if (N0.getOpcode() == ISD::TRUNCATE) { 2908 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2909 if (NarrowLoad.Val) { 2910 if (NarrowLoad.Val != N0.Val) 2911 CombineTo(N0.Val, NarrowLoad); 2912 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2913 } 2914 } 2915 2916 // fold (zext (truncate x)) -> (and x, mask) 2917 if (N0.getOpcode() == ISD::TRUNCATE && 2918 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2919 SDOperand Op = N0.getOperand(0); 2920 if (Op.getValueType() < VT) { 2921 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2922 } else if (Op.getValueType() > VT) { 2923 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2924 } 2925 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2926 } 2927 2928 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2929 if (N0.getOpcode() == ISD::AND && 2930 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2931 N0.getOperand(1).getOpcode() == ISD::Constant) { 2932 SDOperand X = N0.getOperand(0).getOperand(0); 2933 if (X.getValueType() < VT) { 2934 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2935 } else if (X.getValueType() > VT) { 2936 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2937 } 2938 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2939 Mask.zext(MVT::getSizeInBits(VT)); 2940 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2941 } 2942 2943 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2944 if (ISD::isNON_EXTLoad(N0.Val) && 2945 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2946 bool DoXform = true; 2947 SmallVector<SDNode*, 4> SetCCs; 2948 if (!N0.hasOneUse()) 2949 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2950 if (DoXform) { 2951 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2952 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2953 LN0->getBasePtr(), LN0->getSrcValue(), 2954 LN0->getSrcValueOffset(), 2955 N0.getValueType(), 2956 LN0->isVolatile(), 2957 LN0->getAlignment()); 2958 CombineTo(N, ExtLoad); 2959 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2960 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2961 // Extend SetCC uses if necessary. 2962 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2963 SDNode *SetCC = SetCCs[i]; 2964 SmallVector<SDOperand, 4> Ops; 2965 for (unsigned j = 0; j != 2; ++j) { 2966 SDOperand SOp = SetCC->getOperand(j); 2967 if (SOp == Trunc) 2968 Ops.push_back(ExtLoad); 2969 else 2970 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2971 } 2972 Ops.push_back(SetCC->getOperand(2)); 2973 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2974 &Ops[0], Ops.size())); 2975 } 2976 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2977 } 2978 } 2979 2980 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2981 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2982 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2983 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2984 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2985 MVT::ValueType EVT = LN0->getMemoryVT(); 2986 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2987 LN0->getBasePtr(), LN0->getSrcValue(), 2988 LN0->getSrcValueOffset(), EVT, 2989 LN0->isVolatile(), 2990 LN0->getAlignment()); 2991 CombineTo(N, ExtLoad); 2992 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2993 ExtLoad.getValue(1)); 2994 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2995 } 2996 2997 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2998 if (N0.getOpcode() == ISD::SETCC) { 2999 SDOperand SCC = 3000 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3001 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3002 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3003 if (SCC.Val) return SCC; 3004 } 3005 3006 return SDOperand(); 3007} 3008 3009SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 3010 SDOperand N0 = N->getOperand(0); 3011 MVT::ValueType VT = N->getValueType(0); 3012 3013 // fold (aext c1) -> c1 3014 if (isa<ConstantSDNode>(N0)) 3015 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3016 // fold (aext (aext x)) -> (aext x) 3017 // fold (aext (zext x)) -> (zext x) 3018 // fold (aext (sext x)) -> (sext x) 3019 if (N0.getOpcode() == ISD::ANY_EXTEND || 3020 N0.getOpcode() == ISD::ZERO_EXTEND || 3021 N0.getOpcode() == ISD::SIGN_EXTEND) 3022 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3023 3024 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3025 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3026 if (N0.getOpcode() == ISD::TRUNCATE) { 3027 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 3028 if (NarrowLoad.Val) { 3029 if (NarrowLoad.Val != N0.Val) 3030 CombineTo(N0.Val, NarrowLoad); 3031 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3032 } 3033 } 3034 3035 // fold (aext (truncate x)) 3036 if (N0.getOpcode() == ISD::TRUNCATE) { 3037 SDOperand TruncOp = N0.getOperand(0); 3038 if (TruncOp.getValueType() == VT) 3039 return TruncOp; // x iff x size == zext size. 3040 if (TruncOp.getValueType() > VT) 3041 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3042 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3043 } 3044 3045 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3046 if (N0.getOpcode() == ISD::AND && 3047 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3048 N0.getOperand(1).getOpcode() == ISD::Constant) { 3049 SDOperand X = N0.getOperand(0).getOperand(0); 3050 if (X.getValueType() < VT) { 3051 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3052 } else if (X.getValueType() > VT) { 3053 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3054 } 3055 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3056 Mask.zext(MVT::getSizeInBits(VT)); 3057 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3058 } 3059 3060 // fold (aext (load x)) -> (aext (truncate (extload x))) 3061 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3062 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3063 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3064 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3065 LN0->getBasePtr(), LN0->getSrcValue(), 3066 LN0->getSrcValueOffset(), 3067 N0.getValueType(), 3068 LN0->isVolatile(), 3069 LN0->getAlignment()); 3070 CombineTo(N, ExtLoad); 3071 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3072 ExtLoad.getValue(1)); 3073 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3074 } 3075 3076 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3077 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3078 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3079 if (N0.getOpcode() == ISD::LOAD && 3080 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3081 N0.hasOneUse()) { 3082 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3083 MVT::ValueType EVT = LN0->getMemoryVT(); 3084 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3085 LN0->getChain(), LN0->getBasePtr(), 3086 LN0->getSrcValue(), 3087 LN0->getSrcValueOffset(), EVT, 3088 LN0->isVolatile(), 3089 LN0->getAlignment()); 3090 CombineTo(N, ExtLoad); 3091 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3092 ExtLoad.getValue(1)); 3093 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3094 } 3095 3096 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3097 if (N0.getOpcode() == ISD::SETCC) { 3098 SDOperand SCC = 3099 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3100 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3101 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3102 if (SCC.Val) 3103 return SCC; 3104 } 3105 3106 return SDOperand(); 3107} 3108 3109/// GetDemandedBits - See if the specified operand can be simplified with the 3110/// knowledge that only the bits specified by Mask are used. If so, return the 3111/// simpler operand, otherwise return a null SDOperand. 3112SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) { 3113 switch (V.getOpcode()) { 3114 default: break; 3115 case ISD::OR: 3116 case ISD::XOR: 3117 // If the LHS or RHS don't contribute bits to the or, drop them. 3118 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3119 return V.getOperand(1); 3120 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3121 return V.getOperand(0); 3122 break; 3123 case ISD::SRL: 3124 // Only look at single-use SRLs. 3125 if (!V.Val->hasOneUse()) 3126 break; 3127 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3128 // See if we can recursively simplify the LHS. 3129 unsigned Amt = RHSC->getValue(); 3130 APInt NewMask = Mask << Amt; 3131 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3132 if (SimplifyLHS.Val) { 3133 return DAG.getNode(ISD::SRL, V.getValueType(), 3134 SimplifyLHS, V.getOperand(1)); 3135 } 3136 } 3137 } 3138 return SDOperand(); 3139} 3140 3141/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3142/// bits and then truncated to a narrower type and where N is a multiple 3143/// of number of bits of the narrower type, transform it to a narrower load 3144/// from address + N / num of bits of new type. If the result is to be 3145/// extended, also fold the extension to form a extending load. 3146SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3147 unsigned Opc = N->getOpcode(); 3148 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3149 SDOperand N0 = N->getOperand(0); 3150 MVT::ValueType VT = N->getValueType(0); 3151 MVT::ValueType EVT = N->getValueType(0); 3152 3153 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3154 // extended to VT. 3155 if (Opc == ISD::SIGN_EXTEND_INREG) { 3156 ExtType = ISD::SEXTLOAD; 3157 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3158 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3159 return SDOperand(); 3160 } 3161 3162 unsigned EVTBits = MVT::getSizeInBits(EVT); 3163 unsigned ShAmt = 0; 3164 bool CombineSRL = false; 3165 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3166 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3167 ShAmt = N01->getValue(); 3168 // Is the shift amount a multiple of size of VT? 3169 if ((ShAmt & (EVTBits-1)) == 0) { 3170 N0 = N0.getOperand(0); 3171 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3172 return SDOperand(); 3173 CombineSRL = true; 3174 } 3175 } 3176 } 3177 3178 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3179 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3180 // zero extended form: by shrinking the load, we lose track of the fact 3181 // that it is already zero extended. 3182 // FIXME: This should be reevaluated. 3183 VT != MVT::i1) { 3184 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3185 "Cannot truncate to larger type!"); 3186 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3187 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3188 // For big endian targets, we need to adjust the offset to the pointer to 3189 // load the correct bytes. 3190 if (TLI.isBigEndian()) { 3191 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3192 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3193 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3194 } 3195 uint64_t PtrOff = ShAmt / 8; 3196 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3197 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3198 DAG.getConstant(PtrOff, PtrType)); 3199 AddToWorkList(NewPtr.Val); 3200 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3201 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3202 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3203 LN0->isVolatile(), NewAlign) 3204 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3205 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3206 LN0->isVolatile(), NewAlign); 3207 AddToWorkList(N); 3208 if (CombineSRL) { 3209 WorkListRemover DeadNodes(*this); 3210 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3211 &DeadNodes); 3212 CombineTo(N->getOperand(0).Val, Load); 3213 } else 3214 CombineTo(N0.Val, Load, Load.getValue(1)); 3215 if (ShAmt) { 3216 if (Opc == ISD::SIGN_EXTEND_INREG) 3217 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3218 else 3219 return DAG.getNode(Opc, VT, Load); 3220 } 3221 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3222 } 3223 3224 return SDOperand(); 3225} 3226 3227 3228SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3229 SDOperand N0 = N->getOperand(0); 3230 SDOperand N1 = N->getOperand(1); 3231 MVT::ValueType VT = N->getValueType(0); 3232 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3233 unsigned VTBits = MVT::getSizeInBits(VT); 3234 unsigned EVTBits = MVT::getSizeInBits(EVT); 3235 3236 // fold (sext_in_reg c1) -> c1 3237 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3238 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3239 3240 // If the input is already sign extended, just drop the extension. 3241 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3242 return N0; 3243 3244 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3245 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3246 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3247 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3248 } 3249 3250 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3251 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3252 return DAG.getZeroExtendInReg(N0, EVT); 3253 3254 // fold operands of sext_in_reg based on knowledge that the top bits are not 3255 // demanded. 3256 if (SimplifyDemandedBits(SDOperand(N, 0))) 3257 return SDOperand(N, 0); 3258 3259 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3260 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3261 SDOperand NarrowLoad = ReduceLoadWidth(N); 3262 if (NarrowLoad.Val) 3263 return NarrowLoad; 3264 3265 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3266 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3267 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3268 if (N0.getOpcode() == ISD::SRL) { 3269 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3270 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3271 // We can turn this into an SRA iff the input to the SRL is already sign 3272 // extended enough. 3273 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3274 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3275 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3276 } 3277 } 3278 3279 // fold (sext_inreg (extload x)) -> (sextload x) 3280 if (ISD::isEXTLoad(N0.Val) && 3281 ISD::isUNINDEXEDLoad(N0.Val) && 3282 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3283 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3284 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3285 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3286 LN0->getBasePtr(), LN0->getSrcValue(), 3287 LN0->getSrcValueOffset(), EVT, 3288 LN0->isVolatile(), 3289 LN0->getAlignment()); 3290 CombineTo(N, ExtLoad); 3291 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3292 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3293 } 3294 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3295 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3296 N0.hasOneUse() && 3297 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3298 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3299 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3300 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3301 LN0->getBasePtr(), LN0->getSrcValue(), 3302 LN0->getSrcValueOffset(), EVT, 3303 LN0->isVolatile(), 3304 LN0->getAlignment()); 3305 CombineTo(N, ExtLoad); 3306 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3307 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3308 } 3309 return SDOperand(); 3310} 3311 3312SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3313 SDOperand N0 = N->getOperand(0); 3314 MVT::ValueType VT = N->getValueType(0); 3315 3316 // noop truncate 3317 if (N0.getValueType() == N->getValueType(0)) 3318 return N0; 3319 // fold (truncate c1) -> c1 3320 if (isa<ConstantSDNode>(N0)) 3321 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3322 // fold (truncate (truncate x)) -> (truncate x) 3323 if (N0.getOpcode() == ISD::TRUNCATE) 3324 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3325 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3326 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3327 N0.getOpcode() == ISD::ANY_EXTEND) { 3328 if (N0.getOperand(0).getValueType() < VT) 3329 // if the source is smaller than the dest, we still need an extend 3330 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3331 else if (N0.getOperand(0).getValueType() > VT) 3332 // if the source is larger than the dest, than we just need the truncate 3333 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3334 else 3335 // if the source and dest are the same type, we can drop both the extend 3336 // and the truncate 3337 return N0.getOperand(0); 3338 } 3339 3340 // See if we can simplify the input to this truncate through knowledge that 3341 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3342 // -> trunc y 3343 SDOperand Shorter = 3344 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3345 MVT::getSizeInBits(VT))); 3346 if (Shorter.Val) 3347 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3348 3349 // fold (truncate (load x)) -> (smaller load x) 3350 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3351 return ReduceLoadWidth(N); 3352} 3353 3354SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3355 SDOperand N0 = N->getOperand(0); 3356 MVT::ValueType VT = N->getValueType(0); 3357 3358 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3359 // Only do this before legalize, since afterward the target may be depending 3360 // on the bitconvert. 3361 // First check to see if this is all constant. 3362 if (!AfterLegalize && 3363 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3364 MVT::isVector(VT)) { 3365 bool isSimple = true; 3366 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3367 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3368 N0.getOperand(i).getOpcode() != ISD::Constant && 3369 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3370 isSimple = false; 3371 break; 3372 } 3373 3374 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3375 assert(!MVT::isVector(DestEltVT) && 3376 "Element type of vector ValueType must not be vector!"); 3377 if (isSimple) { 3378 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3379 } 3380 } 3381 3382 // If the input is a constant, let getNode() fold it. 3383 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3384 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3385 if (Res.Val != N) return Res; 3386 } 3387 3388 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3389 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3390 3391 // fold (conv (load x)) -> (load (conv*)x) 3392 // If the resultant load doesn't need a higher alignment than the original! 3393 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3394 TLI.isOperationLegal(ISD::LOAD, VT)) { 3395 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3396 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3397 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3398 unsigned OrigAlign = LN0->getAlignment(); 3399 if (Align <= OrigAlign) { 3400 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3401 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3402 LN0->isVolatile(), Align); 3403 AddToWorkList(N); 3404 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3405 Load.getValue(1)); 3406 return Load; 3407 } 3408 } 3409 3410 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3411 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3412 // This often reduces constant pool loads. 3413 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3414 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) { 3415 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3416 AddToWorkList(NewConv.Val); 3417 3418 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); 3419 if (N0.getOpcode() == ISD::FNEG) 3420 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3421 assert(N0.getOpcode() == ISD::FABS); 3422 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3423 } 3424 3425 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3426 // Note that we don't handle copysign(x,cst) because this can always be folded 3427 // to an fneg or fabs. 3428 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3429 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3430 MVT::isInteger(VT) && !MVT::isVector(VT)) { 3431 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType()); 3432 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth), 3433 N0.getOperand(1)); 3434 AddToWorkList(X.Val); 3435 3436 // If X has a different width than the result/lhs, sext it or truncate it. 3437 unsigned VTWidth = MVT::getSizeInBits(VT); 3438 if (OrigXWidth < VTWidth) { 3439 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3440 AddToWorkList(X.Val); 3441 } else if (OrigXWidth > VTWidth) { 3442 // To get the sign bit in the right place, we have to shift it right 3443 // before truncating. 3444 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3445 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3446 AddToWorkList(X.Val); 3447 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3448 AddToWorkList(X.Val); 3449 } 3450 3451 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); 3452 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3453 AddToWorkList(X.Val); 3454 3455 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3456 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3457 AddToWorkList(Cst.Val); 3458 3459 return DAG.getNode(ISD::OR, VT, X, Cst); 3460 } 3461 3462 return SDOperand(); 3463} 3464 3465/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3466/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3467/// destination element value type. 3468SDOperand DAGCombiner:: 3469ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3470 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3471 3472 // If this is already the right type, we're done. 3473 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3474 3475 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3476 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3477 3478 // If this is a conversion of N elements of one type to N elements of another 3479 // type, convert each element. This handles FP<->INT cases. 3480 if (SrcBitSize == DstBitSize) { 3481 SmallVector<SDOperand, 8> Ops; 3482 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3483 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3484 AddToWorkList(Ops.back().Val); 3485 } 3486 MVT::ValueType VT = 3487 MVT::getVectorType(DstEltVT, 3488 MVT::getVectorNumElements(BV->getValueType(0))); 3489 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3490 } 3491 3492 // Otherwise, we're growing or shrinking the elements. To avoid having to 3493 // handle annoying details of growing/shrinking FP values, we convert them to 3494 // int first. 3495 if (MVT::isFloatingPoint(SrcEltVT)) { 3496 // Convert the input float vector to a int vector where the elements are the 3497 // same sizes. 3498 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3499 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3500 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3501 SrcEltVT = IntVT; 3502 } 3503 3504 // Now we know the input is an integer vector. If the output is a FP type, 3505 // convert to integer first, then to FP of the right size. 3506 if (MVT::isFloatingPoint(DstEltVT)) { 3507 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3508 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3509 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3510 3511 // Next, convert to FP elements of the same size. 3512 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3513 } 3514 3515 // Okay, we know the src/dst types are both integers of differing types. 3516 // Handling growing first. 3517 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3518 if (SrcBitSize < DstBitSize) { 3519 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3520 3521 SmallVector<SDOperand, 8> Ops; 3522 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3523 i += NumInputsPerOutput) { 3524 bool isLE = TLI.isLittleEndian(); 3525 APInt NewBits = APInt(DstBitSize, 0); 3526 bool EltIsUndef = true; 3527 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3528 // Shift the previously computed bits over. 3529 NewBits <<= SrcBitSize; 3530 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3531 if (Op.getOpcode() == ISD::UNDEF) continue; 3532 EltIsUndef = false; 3533 3534 NewBits |= 3535 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3536 } 3537 3538 if (EltIsUndef) 3539 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3540 else 3541 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3542 } 3543 3544 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3545 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3546 } 3547 3548 // Finally, this must be the case where we are shrinking elements: each input 3549 // turns into multiple outputs. 3550 bool isS2V = ISD::isScalarToVector(BV); 3551 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3552 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3553 NumOutputsPerInput * BV->getNumOperands()); 3554 SmallVector<SDOperand, 8> Ops; 3555 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3556 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3557 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3558 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3559 continue; 3560 } 3561 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3562 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3563 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3564 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3565 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3566 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3567 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3568 OpVal = OpVal.lshr(DstBitSize); 3569 } 3570 3571 // For big endian targets, swap the order of the pieces of each element. 3572 if (TLI.isBigEndian()) 3573 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3574 } 3575 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3576} 3577 3578 3579 3580SDOperand DAGCombiner::visitFADD(SDNode *N) { 3581 SDOperand N0 = N->getOperand(0); 3582 SDOperand N1 = N->getOperand(1); 3583 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3584 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3585 MVT::ValueType VT = N->getValueType(0); 3586 3587 // fold vector ops 3588 if (MVT::isVector(VT)) { 3589 SDOperand FoldedVOp = SimplifyVBinOp(N); 3590 if (FoldedVOp.Val) return FoldedVOp; 3591 } 3592 3593 // fold (fadd c1, c2) -> c1+c2 3594 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3595 return DAG.getNode(ISD::FADD, VT, N0, N1); 3596 // canonicalize constant to RHS 3597 if (N0CFP && !N1CFP) 3598 return DAG.getNode(ISD::FADD, VT, N1, N0); 3599 // fold (A + (-B)) -> A-B 3600 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3601 return DAG.getNode(ISD::FSUB, VT, N0, 3602 GetNegatedExpression(N1, DAG, AfterLegalize)); 3603 // fold ((-A) + B) -> B-A 3604 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3605 return DAG.getNode(ISD::FSUB, VT, N1, 3606 GetNegatedExpression(N0, DAG, AfterLegalize)); 3607 3608 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3609 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3610 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3611 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3612 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3613 3614 return SDOperand(); 3615} 3616 3617SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3618 SDOperand N0 = N->getOperand(0); 3619 SDOperand N1 = N->getOperand(1); 3620 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3621 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3622 MVT::ValueType VT = N->getValueType(0); 3623 3624 // fold vector ops 3625 if (MVT::isVector(VT)) { 3626 SDOperand FoldedVOp = SimplifyVBinOp(N); 3627 if (FoldedVOp.Val) return FoldedVOp; 3628 } 3629 3630 // fold (fsub c1, c2) -> c1-c2 3631 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3632 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3633 // fold (0-B) -> -B 3634 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3635 if (isNegatibleForFree(N1, AfterLegalize)) 3636 return GetNegatedExpression(N1, DAG, AfterLegalize); 3637 return DAG.getNode(ISD::FNEG, VT, N1); 3638 } 3639 // fold (A-(-B)) -> A+B 3640 if (isNegatibleForFree(N1, AfterLegalize)) 3641 return DAG.getNode(ISD::FADD, VT, N0, 3642 GetNegatedExpression(N1, DAG, AfterLegalize)); 3643 3644 return SDOperand(); 3645} 3646 3647SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3648 SDOperand N0 = N->getOperand(0); 3649 SDOperand N1 = N->getOperand(1); 3650 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3651 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3652 MVT::ValueType VT = N->getValueType(0); 3653 3654 // fold vector ops 3655 if (MVT::isVector(VT)) { 3656 SDOperand FoldedVOp = SimplifyVBinOp(N); 3657 if (FoldedVOp.Val) return FoldedVOp; 3658 } 3659 3660 // fold (fmul c1, c2) -> c1*c2 3661 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3662 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3663 // canonicalize constant to RHS 3664 if (N0CFP && !N1CFP) 3665 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3666 // fold (fmul X, 2.0) -> (fadd X, X) 3667 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3668 return DAG.getNode(ISD::FADD, VT, N0, N0); 3669 // fold (fmul X, -1.0) -> (fneg X) 3670 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3671 return DAG.getNode(ISD::FNEG, VT, N0); 3672 3673 // -X * -Y -> X*Y 3674 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3675 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3676 // Both can be negated for free, check to see if at least one is cheaper 3677 // negated. 3678 if (LHSNeg == 2 || RHSNeg == 2) 3679 return DAG.getNode(ISD::FMUL, VT, 3680 GetNegatedExpression(N0, DAG, AfterLegalize), 3681 GetNegatedExpression(N1, DAG, AfterLegalize)); 3682 } 3683 } 3684 3685 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3686 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3687 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3688 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3689 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3690 3691 return SDOperand(); 3692} 3693 3694SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3695 SDOperand N0 = N->getOperand(0); 3696 SDOperand N1 = N->getOperand(1); 3697 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3698 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3699 MVT::ValueType VT = N->getValueType(0); 3700 3701 // fold vector ops 3702 if (MVT::isVector(VT)) { 3703 SDOperand FoldedVOp = SimplifyVBinOp(N); 3704 if (FoldedVOp.Val) return FoldedVOp; 3705 } 3706 3707 // fold (fdiv c1, c2) -> c1/c2 3708 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3709 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3710 3711 3712 // -X / -Y -> X*Y 3713 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3714 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3715 // Both can be negated for free, check to see if at least one is cheaper 3716 // negated. 3717 if (LHSNeg == 2 || RHSNeg == 2) 3718 return DAG.getNode(ISD::FDIV, VT, 3719 GetNegatedExpression(N0, DAG, AfterLegalize), 3720 GetNegatedExpression(N1, DAG, AfterLegalize)); 3721 } 3722 } 3723 3724 return SDOperand(); 3725} 3726 3727SDOperand DAGCombiner::visitFREM(SDNode *N) { 3728 SDOperand N0 = N->getOperand(0); 3729 SDOperand N1 = N->getOperand(1); 3730 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3731 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3732 MVT::ValueType VT = N->getValueType(0); 3733 3734 // fold (frem c1, c2) -> fmod(c1,c2) 3735 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3736 return DAG.getNode(ISD::FREM, VT, N0, N1); 3737 3738 return SDOperand(); 3739} 3740 3741SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3742 SDOperand N0 = N->getOperand(0); 3743 SDOperand N1 = N->getOperand(1); 3744 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3745 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3746 MVT::ValueType VT = N->getValueType(0); 3747 3748 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3749 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3750 3751 if (N1CFP) { 3752 const APFloat& V = N1CFP->getValueAPF(); 3753 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3754 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3755 if (!V.isNegative()) 3756 return DAG.getNode(ISD::FABS, VT, N0); 3757 else 3758 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3759 } 3760 3761 // copysign(fabs(x), y) -> copysign(x, y) 3762 // copysign(fneg(x), y) -> copysign(x, y) 3763 // copysign(copysign(x,z), y) -> copysign(x, y) 3764 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3765 N0.getOpcode() == ISD::FCOPYSIGN) 3766 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3767 3768 // copysign(x, abs(y)) -> abs(x) 3769 if (N1.getOpcode() == ISD::FABS) 3770 return DAG.getNode(ISD::FABS, VT, N0); 3771 3772 // copysign(x, copysign(y,z)) -> copysign(x, z) 3773 if (N1.getOpcode() == ISD::FCOPYSIGN) 3774 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3775 3776 // copysign(x, fp_extend(y)) -> copysign(x, y) 3777 // copysign(x, fp_round(y)) -> copysign(x, y) 3778 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3779 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3780 3781 return SDOperand(); 3782} 3783 3784 3785 3786SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3787 SDOperand N0 = N->getOperand(0); 3788 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3789 MVT::ValueType VT = N->getValueType(0); 3790 3791 // fold (sint_to_fp c1) -> c1fp 3792 if (N0C && N0.getValueType() != MVT::ppcf128) 3793 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3794 return SDOperand(); 3795} 3796 3797SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3798 SDOperand N0 = N->getOperand(0); 3799 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3800 MVT::ValueType VT = N->getValueType(0); 3801 3802 // fold (uint_to_fp c1) -> c1fp 3803 if (N0C && N0.getValueType() != MVT::ppcf128) 3804 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3805 return SDOperand(); 3806} 3807 3808SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3809 SDOperand N0 = N->getOperand(0); 3810 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3811 MVT::ValueType VT = N->getValueType(0); 3812 3813 // fold (fp_to_sint c1fp) -> c1 3814 if (N0CFP) 3815 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3816 return SDOperand(); 3817} 3818 3819SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3820 SDOperand N0 = N->getOperand(0); 3821 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3822 MVT::ValueType VT = N->getValueType(0); 3823 3824 // fold (fp_to_uint c1fp) -> c1 3825 if (N0CFP && VT != MVT::ppcf128) 3826 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3827 return SDOperand(); 3828} 3829 3830SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3831 SDOperand N0 = N->getOperand(0); 3832 SDOperand N1 = N->getOperand(1); 3833 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3834 MVT::ValueType VT = N->getValueType(0); 3835 3836 // fold (fp_round c1fp) -> c1fp 3837 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3838 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3839 3840 // fold (fp_round (fp_extend x)) -> x 3841 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3842 return N0.getOperand(0); 3843 3844 // fold (fp_round (fp_round x)) -> (fp_round x) 3845 if (N0.getOpcode() == ISD::FP_ROUND) { 3846 // This is a value preserving truncation if both round's are. 3847 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3848 N0.Val->getConstantOperandVal(1) == 1; 3849 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3850 DAG.getIntPtrConstant(IsTrunc)); 3851 } 3852 3853 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3854 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3855 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3856 AddToWorkList(Tmp.Val); 3857 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3858 } 3859 3860 return SDOperand(); 3861} 3862 3863SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3864 SDOperand N0 = N->getOperand(0); 3865 MVT::ValueType VT = N->getValueType(0); 3866 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3867 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3868 3869 // fold (fp_round_inreg c1fp) -> c1fp 3870 if (N0CFP) { 3871 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3872 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3873 } 3874 return SDOperand(); 3875} 3876 3877SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3878 SDOperand N0 = N->getOperand(0); 3879 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3880 MVT::ValueType VT = N->getValueType(0); 3881 3882 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3883 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND) 3884 return SDOperand(); 3885 3886 // fold (fp_extend c1fp) -> c1fp 3887 if (N0CFP && VT != MVT::ppcf128) 3888 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3889 3890 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3891 // value of X. 3892 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3893 SDOperand In = N0.getOperand(0); 3894 if (In.getValueType() == VT) return In; 3895 if (VT < In.getValueType()) 3896 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3897 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3898 } 3899 3900 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3901 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3902 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3903 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3904 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3905 LN0->getBasePtr(), LN0->getSrcValue(), 3906 LN0->getSrcValueOffset(), 3907 N0.getValueType(), 3908 LN0->isVolatile(), 3909 LN0->getAlignment()); 3910 CombineTo(N, ExtLoad); 3911 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3912 DAG.getIntPtrConstant(1)), 3913 ExtLoad.getValue(1)); 3914 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3915 } 3916 3917 3918 return SDOperand(); 3919} 3920 3921SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3922 SDOperand N0 = N->getOperand(0); 3923 3924 if (isNegatibleForFree(N0, AfterLegalize)) 3925 return GetNegatedExpression(N0, DAG, AfterLegalize); 3926 3927 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 3928 // constant pool values. 3929 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3930 MVT::isInteger(N0.getOperand(0).getValueType()) && 3931 !MVT::isVector(N0.getOperand(0).getValueType())) { 3932 SDOperand Int = N0.getOperand(0); 3933 MVT::ValueType IntVT = Int.getValueType(); 3934 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3935 Int = DAG.getNode(ISD::XOR, IntVT, Int, 3936 DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT)); 3937 AddToWorkList(Int.Val); 3938 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3939 } 3940 } 3941 3942 return SDOperand(); 3943} 3944 3945SDOperand DAGCombiner::visitFABS(SDNode *N) { 3946 SDOperand N0 = N->getOperand(0); 3947 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3948 MVT::ValueType VT = N->getValueType(0); 3949 3950 // fold (fabs c1) -> fabs(c1) 3951 if (N0CFP && VT != MVT::ppcf128) 3952 return DAG.getNode(ISD::FABS, VT, N0); 3953 // fold (fabs (fabs x)) -> (fabs x) 3954 if (N0.getOpcode() == ISD::FABS) 3955 return N->getOperand(0); 3956 // fold (fabs (fneg x)) -> (fabs x) 3957 // fold (fabs (fcopysign x, y)) -> (fabs x) 3958 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3959 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3960 3961 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 3962 // constant pool values. 3963 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3964 MVT::isInteger(N0.getOperand(0).getValueType()) && 3965 !MVT::isVector(N0.getOperand(0).getValueType())) { 3966 SDOperand Int = N0.getOperand(0); 3967 MVT::ValueType IntVT = Int.getValueType(); 3968 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3969 Int = DAG.getNode(ISD::AND, IntVT, Int, 3970 DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT)); 3971 AddToWorkList(Int.Val); 3972 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3973 } 3974 } 3975 3976 return SDOperand(); 3977} 3978 3979SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3980 SDOperand Chain = N->getOperand(0); 3981 SDOperand N1 = N->getOperand(1); 3982 SDOperand N2 = N->getOperand(2); 3983 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3984 3985 // never taken branch, fold to chain 3986 if (N1C && N1C->isNullValue()) 3987 return Chain; 3988 // unconditional branch 3989 if (N1C && N1C->getAPIntValue() == 1) 3990 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3991 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3992 // on the target. 3993 if (N1.getOpcode() == ISD::SETCC && 3994 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3995 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3996 N1.getOperand(0), N1.getOperand(1), N2); 3997 } 3998 return SDOperand(); 3999} 4000 4001// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4002// 4003SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 4004 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4005 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4006 4007 // Use SimplifySetCC to simplify SETCC's. 4008 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 4009 if (Simp.Val) AddToWorkList(Simp.Val); 4010 4011 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 4012 4013 // fold br_cc true, dest -> br dest (unconditional branch) 4014 if (SCCC && !SCCC->isNullValue()) 4015 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4016 N->getOperand(4)); 4017 // fold br_cc false, dest -> unconditional fall through 4018 if (SCCC && SCCC->isNullValue()) 4019 return N->getOperand(0); 4020 4021 // fold to a simpler setcc 4022 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 4023 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4024 Simp.getOperand(2), Simp.getOperand(0), 4025 Simp.getOperand(1), N->getOperand(4)); 4026 return SDOperand(); 4027} 4028 4029 4030/// CombineToPreIndexedLoadStore - Try turning a load / store and a 4031/// pre-indexed load / store when the base pointer is a add or subtract 4032/// and it has other uses besides the load / store. After the 4033/// transformation, the new indexed load / store has effectively folded 4034/// the add / subtract in and all of its other uses are redirected to the 4035/// new load / store. 4036bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4037 if (!AfterLegalize) 4038 return false; 4039 4040 bool isLoad = true; 4041 SDOperand Ptr; 4042 MVT::ValueType VT; 4043 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4044 if (LD->isIndexed()) 4045 return false; 4046 VT = LD->getMemoryVT(); 4047 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4048 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4049 return false; 4050 Ptr = LD->getBasePtr(); 4051 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4052 if (ST->isIndexed()) 4053 return false; 4054 VT = ST->getMemoryVT(); 4055 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4056 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4057 return false; 4058 Ptr = ST->getBasePtr(); 4059 isLoad = false; 4060 } else 4061 return false; 4062 4063 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4064 // out. There is no reason to make this a preinc/predec. 4065 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4066 Ptr.Val->hasOneUse()) 4067 return false; 4068 4069 // Ask the target to do addressing mode selection. 4070 SDOperand BasePtr; 4071 SDOperand Offset; 4072 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4073 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4074 return false; 4075 // Don't create a indexed load / store with zero offset. 4076 if (isa<ConstantSDNode>(Offset) && 4077 cast<ConstantSDNode>(Offset)->isNullValue()) 4078 return false; 4079 4080 // Try turning it into a pre-indexed load / store except when: 4081 // 1) The new base ptr is a frame index. 4082 // 2) If N is a store and the new base ptr is either the same as or is a 4083 // predecessor of the value being stored. 4084 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4085 // that would create a cycle. 4086 // 4) All uses are load / store ops that use it as old base ptr. 4087 4088 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4089 // (plus the implicit offset) to a register to preinc anyway. 4090 if (isa<FrameIndexSDNode>(BasePtr)) 4091 return false; 4092 4093 // Check #2. 4094 if (!isLoad) { 4095 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 4096 if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val)) 4097 return false; 4098 } 4099 4100 // Now check for #3 and #4. 4101 bool RealUse = false; 4102 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4103 E = Ptr.Val->use_end(); I != E; ++I) { 4104 SDNode *Use = *I; 4105 if (Use == N) 4106 continue; 4107 if (Use->isPredecessorOf(N)) 4108 return false; 4109 4110 if (!((Use->getOpcode() == ISD::LOAD && 4111 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4112 (Use->getOpcode() == ISD::STORE && 4113 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4114 RealUse = true; 4115 } 4116 if (!RealUse) 4117 return false; 4118 4119 SDOperand Result; 4120 if (isLoad) 4121 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 4122 else 4123 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4124 ++PreIndexedNodes; 4125 ++NodesCombined; 4126 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4127 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4128 DOUT << '\n'; 4129 WorkListRemover DeadNodes(*this); 4130 if (isLoad) { 4131 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4132 &DeadNodes); 4133 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4134 &DeadNodes); 4135 } else { 4136 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4137 &DeadNodes); 4138 } 4139 4140 // Finally, since the node is now dead, remove it from the graph. 4141 DAG.DeleteNode(N); 4142 4143 // Replace the uses of Ptr with uses of the updated base value. 4144 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4145 &DeadNodes); 4146 removeFromWorkList(Ptr.Val); 4147 DAG.DeleteNode(Ptr.Val); 4148 4149 return true; 4150} 4151 4152/// CombineToPostIndexedLoadStore - Try combine a load / store with a 4153/// add / sub of the base pointer node into a post-indexed load / store. 4154/// The transformation folded the add / subtract into the new indexed 4155/// load / store effectively and all of its uses are redirected to the 4156/// new load / store. 4157bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4158 if (!AfterLegalize) 4159 return false; 4160 4161 bool isLoad = true; 4162 SDOperand Ptr; 4163 MVT::ValueType VT; 4164 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4165 if (LD->isIndexed()) 4166 return false; 4167 VT = LD->getMemoryVT(); 4168 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4169 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4170 return false; 4171 Ptr = LD->getBasePtr(); 4172 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4173 if (ST->isIndexed()) 4174 return false; 4175 VT = ST->getMemoryVT(); 4176 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4177 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4178 return false; 4179 Ptr = ST->getBasePtr(); 4180 isLoad = false; 4181 } else 4182 return false; 4183 4184 if (Ptr.Val->hasOneUse()) 4185 return false; 4186 4187 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4188 E = Ptr.Val->use_end(); I != E; ++I) { 4189 SDNode *Op = *I; 4190 if (Op == N || 4191 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4192 continue; 4193 4194 SDOperand BasePtr; 4195 SDOperand Offset; 4196 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4197 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4198 if (Ptr == Offset) 4199 std::swap(BasePtr, Offset); 4200 if (Ptr != BasePtr) 4201 continue; 4202 // Don't create a indexed load / store with zero offset. 4203 if (isa<ConstantSDNode>(Offset) && 4204 cast<ConstantSDNode>(Offset)->isNullValue()) 4205 continue; 4206 4207 // Try turning it into a post-indexed load / store except when 4208 // 1) All uses are load / store ops that use it as base ptr. 4209 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4210 // nor a successor of N. Otherwise, if Op is folded that would 4211 // create a cycle. 4212 4213 // Check for #1. 4214 bool TryNext = false; 4215 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4216 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4217 SDNode *Use = *II; 4218 if (Use == Ptr.Val) 4219 continue; 4220 4221 // If all the uses are load / store addresses, then don't do the 4222 // transformation. 4223 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4224 bool RealUse = false; 4225 for (SDNode::use_iterator III = Use->use_begin(), 4226 EEE = Use->use_end(); III != EEE; ++III) { 4227 SDNode *UseUse = *III; 4228 if (!((UseUse->getOpcode() == ISD::LOAD && 4229 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4230 (UseUse->getOpcode() == ISD::STORE && 4231 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))) 4232 RealUse = true; 4233 } 4234 4235 if (!RealUse) { 4236 TryNext = true; 4237 break; 4238 } 4239 } 4240 } 4241 if (TryNext) 4242 continue; 4243 4244 // Check for #2 4245 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4246 SDOperand Result = isLoad 4247 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4248 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4249 ++PostIndexedNodes; 4250 ++NodesCombined; 4251 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4252 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4253 DOUT << '\n'; 4254 WorkListRemover DeadNodes(*this); 4255 if (isLoad) { 4256 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4257 &DeadNodes); 4258 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4259 &DeadNodes); 4260 } else { 4261 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4262 &DeadNodes); 4263 } 4264 4265 // Finally, since the node is now dead, remove it from the graph. 4266 DAG.DeleteNode(N); 4267 4268 // Replace the uses of Use with uses of the updated base value. 4269 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4270 Result.getValue(isLoad ? 1 : 0), 4271 &DeadNodes); 4272 removeFromWorkList(Op); 4273 DAG.DeleteNode(Op); 4274 return true; 4275 } 4276 } 4277 } 4278 return false; 4279} 4280 4281/// InferAlignment - If we can infer some alignment information from this 4282/// pointer, return it. 4283static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4284 // If this is a direct reference to a stack slot, use information about the 4285 // stack slot's alignment. 4286 int FrameIdx = 1 << 31; 4287 int64_t FrameOffset = 0; 4288 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4289 FrameIdx = FI->getIndex(); 4290 } else if (Ptr.getOpcode() == ISD::ADD && 4291 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4292 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4293 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4294 FrameOffset = Ptr.getConstantOperandVal(1); 4295 } 4296 4297 if (FrameIdx != (1 << 31)) { 4298 // FIXME: Handle FI+CST. 4299 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4300 if (MFI.isFixedObjectIndex(FrameIdx)) { 4301 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4302 4303 // The alignment of the frame index can be determined from its offset from 4304 // the incoming frame position. If the frame object is at offset 32 and 4305 // the stack is guaranteed to be 16-byte aligned, then we know that the 4306 // object is 16-byte aligned. 4307 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4308 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4309 4310 // Finally, the frame object itself may have a known alignment. Factor 4311 // the alignment + offset into a new alignment. For example, if we know 4312 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4313 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4314 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4315 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4316 FrameOffset); 4317 return std::max(Align, FIInfoAlign); 4318 } 4319 } 4320 4321 return 0; 4322} 4323 4324SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4325 LoadSDNode *LD = cast<LoadSDNode>(N); 4326 SDOperand Chain = LD->getChain(); 4327 SDOperand Ptr = LD->getBasePtr(); 4328 4329 // Try to infer better alignment information than the load already has. 4330 if (LD->isUnindexed()) { 4331 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4332 if (Align > LD->getAlignment()) 4333 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4334 Chain, Ptr, LD->getSrcValue(), 4335 LD->getSrcValueOffset(), LD->getMemoryVT(), 4336 LD->isVolatile(), Align); 4337 } 4338 } 4339 4340 4341 // If load is not volatile and there are no uses of the loaded value (and 4342 // the updated indexed value in case of indexed loads), change uses of the 4343 // chain value into uses of the chain input (i.e. delete the dead load). 4344 if (!LD->isVolatile()) { 4345 if (N->getValueType(1) == MVT::Other) { 4346 // Unindexed loads. 4347 if (N->hasNUsesOfValue(0, 0)) { 4348 // It's not safe to use the two value CombineTo variant here. e.g. 4349 // v1, chain2 = load chain1, loc 4350 // v2, chain3 = load chain2, loc 4351 // v3 = add v2, c 4352 // Now we replace use of chain2 with chain1. This makes the second load 4353 // isomorphic to the one we are deleting, and thus makes this load live. 4354 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4355 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4356 DOUT << "\n"; 4357 WorkListRemover DeadNodes(*this); 4358 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes); 4359 if (N->use_empty()) { 4360 removeFromWorkList(N); 4361 DAG.DeleteNode(N); 4362 } 4363 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4364 } 4365 } else { 4366 // Indexed loads. 4367 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4368 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4369 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4370 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4371 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4372 DOUT << " and 2 other values\n"; 4373 WorkListRemover DeadNodes(*this); 4374 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes); 4375 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4376 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4377 &DeadNodes); 4378 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes); 4379 removeFromWorkList(N); 4380 DAG.DeleteNode(N); 4381 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4382 } 4383 } 4384 } 4385 4386 // If this load is directly stored, replace the load value with the stored 4387 // value. 4388 // TODO: Handle store large -> read small portion. 4389 // TODO: Handle TRUNCSTORE/LOADEXT 4390 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4391 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4392 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4393 if (PrevST->getBasePtr() == Ptr && 4394 PrevST->getValue().getValueType() == N->getValueType(0)) 4395 return CombineTo(N, Chain.getOperand(1), Chain); 4396 } 4397 } 4398 4399 if (CombinerAA) { 4400 // Walk up chain skipping non-aliasing memory nodes. 4401 SDOperand BetterChain = FindBetterChain(N, Chain); 4402 4403 // If there is a better chain. 4404 if (Chain != BetterChain) { 4405 SDOperand ReplLoad; 4406 4407 // Replace the chain to void dependency. 4408 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4409 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4410 LD->getSrcValue(), LD->getSrcValueOffset(), 4411 LD->isVolatile(), LD->getAlignment()); 4412 } else { 4413 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4414 LD->getValueType(0), 4415 BetterChain, Ptr, LD->getSrcValue(), 4416 LD->getSrcValueOffset(), 4417 LD->getMemoryVT(), 4418 LD->isVolatile(), 4419 LD->getAlignment()); 4420 } 4421 4422 // Create token factor to keep old chain connected. 4423 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4424 Chain, ReplLoad.getValue(1)); 4425 4426 // Replace uses with load result and token factor. Don't add users 4427 // to work list. 4428 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4429 } 4430 } 4431 4432 // Try transforming N to an indexed load. 4433 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4434 return SDOperand(N, 0); 4435 4436 return SDOperand(); 4437} 4438 4439 4440SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4441 StoreSDNode *ST = cast<StoreSDNode>(N); 4442 SDOperand Chain = ST->getChain(); 4443 SDOperand Value = ST->getValue(); 4444 SDOperand Ptr = ST->getBasePtr(); 4445 4446 // Try to infer better alignment information than the store already has. 4447 if (ST->isUnindexed()) { 4448 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4449 if (Align > ST->getAlignment()) 4450 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4451 ST->getSrcValueOffset(), ST->getMemoryVT(), 4452 ST->isVolatile(), Align); 4453 } 4454 } 4455 4456 // If this is a store of a bit convert, store the input value if the 4457 // resultant store does not need a higher alignment than the original. 4458 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4459 ST->isUnindexed()) { 4460 unsigned Align = ST->getAlignment(); 4461 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4462 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4463 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4464 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4465 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4466 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4467 } 4468 4469 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4470 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4471 if (Value.getOpcode() != ISD::TargetConstantFP) { 4472 SDOperand Tmp; 4473 switch (CFP->getValueType(0)) { 4474 default: assert(0 && "Unknown FP type"); 4475 case MVT::f80: // We don't do this for these yet. 4476 case MVT::f128: 4477 case MVT::ppcf128: 4478 break; 4479 case MVT::f32: 4480 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4481 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4482 convertToAPInt().getZExtValue(), MVT::i32); 4483 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4484 ST->getSrcValueOffset(), ST->isVolatile(), 4485 ST->getAlignment()); 4486 } 4487 break; 4488 case MVT::f64: 4489 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4490 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4491 getZExtValue(), MVT::i64); 4492 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4493 ST->getSrcValueOffset(), ST->isVolatile(), 4494 ST->getAlignment()); 4495 } else if (TLI.isTypeLegal(MVT::i32)) { 4496 // Many FP stores are not made apparent until after legalize, e.g. for 4497 // argument passing. Since this is so common, custom legalize the 4498 // 64-bit integer store into two 32-bit stores. 4499 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4500 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4501 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4502 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4503 4504 int SVOffset = ST->getSrcValueOffset(); 4505 unsigned Alignment = ST->getAlignment(); 4506 bool isVolatile = ST->isVolatile(); 4507 4508 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4509 ST->getSrcValueOffset(), 4510 isVolatile, ST->getAlignment()); 4511 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4512 DAG.getConstant(4, Ptr.getValueType())); 4513 SVOffset += 4; 4514 Alignment = MinAlign(Alignment, 4U); 4515 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4516 SVOffset, isVolatile, Alignment); 4517 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4518 } 4519 break; 4520 } 4521 } 4522 } 4523 4524 if (CombinerAA) { 4525 // Walk up chain skipping non-aliasing memory nodes. 4526 SDOperand BetterChain = FindBetterChain(N, Chain); 4527 4528 // If there is a better chain. 4529 if (Chain != BetterChain) { 4530 // Replace the chain to avoid dependency. 4531 SDOperand ReplStore; 4532 if (ST->isTruncatingStore()) { 4533 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4534 ST->getSrcValue(),ST->getSrcValueOffset(), 4535 ST->getMemoryVT(), 4536 ST->isVolatile(), ST->getAlignment()); 4537 } else { 4538 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4539 ST->getSrcValue(), ST->getSrcValueOffset(), 4540 ST->isVolatile(), ST->getAlignment()); 4541 } 4542 4543 // Create token to keep both nodes around. 4544 SDOperand Token = 4545 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4546 4547 // Don't add users to work list. 4548 return CombineTo(N, Token, false); 4549 } 4550 } 4551 4552 // Try transforming N to an indexed store. 4553 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4554 return SDOperand(N, 0); 4555 4556 // FIXME: is there such a thing as a truncating indexed store? 4557 if (ST->isTruncatingStore() && ST->isUnindexed() && 4558 MVT::isInteger(Value.getValueType())) { 4559 // See if we can simplify the input to this truncstore with knowledge that 4560 // only the low bits are being used. For example: 4561 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4562 SDOperand Shorter = 4563 GetDemandedBits(Value, 4564 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4565 MVT::getSizeInBits(ST->getMemoryVT()))); 4566 AddToWorkList(Value.Val); 4567 if (Shorter.Val) 4568 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4569 ST->getSrcValueOffset(), ST->getMemoryVT(), 4570 ST->isVolatile(), ST->getAlignment()); 4571 4572 // Otherwise, see if we can simplify the operation with 4573 // SimplifyDemandedBits, which only works if the value has a single use. 4574 if (SimplifyDemandedBits(Value, 4575 APInt::getLowBitsSet( 4576 Value.getValueSizeInBits(), 4577 MVT::getSizeInBits(ST->getMemoryVT())))) 4578 return SDOperand(N, 0); 4579 } 4580 4581 // If this is a load followed by a store to the same location, then the store 4582 // is dead/noop. 4583 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4584 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4585 ST->isUnindexed() && !ST->isVolatile() && 4586 // There can't be any side effects between the load and store, such as 4587 // a call or store. 4588 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4589 // The store is dead, remove it. 4590 return Chain; 4591 } 4592 } 4593 4594 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4595 // truncating store. We can do this even if this is already a truncstore. 4596 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4597 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) && 4598 Value.Val->hasOneUse() && ST->isUnindexed() && 4599 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4600 ST->getMemoryVT())) { 4601 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4602 ST->getSrcValueOffset(), ST->getMemoryVT(), 4603 ST->isVolatile(), ST->getAlignment()); 4604 } 4605 4606 return SDOperand(); 4607} 4608 4609SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4610 SDOperand InVec = N->getOperand(0); 4611 SDOperand InVal = N->getOperand(1); 4612 SDOperand EltNo = N->getOperand(2); 4613 4614 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4615 // vector with the inserted element. 4616 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4617 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4618 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4619 if (Elt < Ops.size()) 4620 Ops[Elt] = InVal; 4621 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4622 &Ops[0], Ops.size()); 4623 } 4624 4625 return SDOperand(); 4626} 4627 4628SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4629 SDOperand InVec = N->getOperand(0); 4630 SDOperand EltNo = N->getOperand(1); 4631 4632 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4633 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4634 if (isa<ConstantSDNode>(EltNo)) { 4635 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4636 bool NewLoad = false; 4637 if (Elt == 0) { 4638 MVT::ValueType VT = InVec.getValueType(); 4639 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4640 MVT::ValueType LVT = EVT; 4641 unsigned NumElts = MVT::getVectorNumElements(VT); 4642 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4643 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4644 if (!MVT::isVector(BCVT) || 4645 NumElts != MVT::getVectorNumElements(BCVT)) 4646 return SDOperand(); 4647 InVec = InVec.getOperand(0); 4648 EVT = MVT::getVectorElementType(BCVT); 4649 NewLoad = true; 4650 } 4651 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4652 InVec.getOperand(0).getValueType() == EVT && 4653 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4654 InVec.getOperand(0).hasOneUse()) { 4655 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4656 unsigned Align = LN0->getAlignment(); 4657 if (NewLoad) { 4658 // Check the resultant load doesn't need a higher alignment than the 4659 // original load. 4660 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4661 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4662 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4663 return SDOperand(); 4664 Align = NewAlign; 4665 } 4666 4667 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4668 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4669 LN0->isVolatile(), Align); 4670 } 4671 } 4672 } 4673 return SDOperand(); 4674} 4675 4676 4677SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4678 unsigned NumInScalars = N->getNumOperands(); 4679 MVT::ValueType VT = N->getValueType(0); 4680 unsigned NumElts = MVT::getVectorNumElements(VT); 4681 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4682 4683 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4684 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4685 // at most two distinct vectors, turn this into a shuffle node. 4686 SDOperand VecIn1, VecIn2; 4687 for (unsigned i = 0; i != NumInScalars; ++i) { 4688 // Ignore undef inputs. 4689 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4690 4691 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4692 // constant index, bail out. 4693 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4694 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4695 VecIn1 = VecIn2 = SDOperand(0, 0); 4696 break; 4697 } 4698 4699 // If the input vector type disagrees with the result of the build_vector, 4700 // we can't make a shuffle. 4701 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4702 if (ExtractedFromVec.getValueType() != VT) { 4703 VecIn1 = VecIn2 = SDOperand(0, 0); 4704 break; 4705 } 4706 4707 // Otherwise, remember this. We allow up to two distinct input vectors. 4708 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4709 continue; 4710 4711 if (VecIn1.Val == 0) { 4712 VecIn1 = ExtractedFromVec; 4713 } else if (VecIn2.Val == 0) { 4714 VecIn2 = ExtractedFromVec; 4715 } else { 4716 // Too many inputs. 4717 VecIn1 = VecIn2 = SDOperand(0, 0); 4718 break; 4719 } 4720 } 4721 4722 // If everything is good, we can make a shuffle operation. 4723 if (VecIn1.Val) { 4724 SmallVector<SDOperand, 8> BuildVecIndices; 4725 for (unsigned i = 0; i != NumInScalars; ++i) { 4726 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4727 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4728 continue; 4729 } 4730 4731 SDOperand Extract = N->getOperand(i); 4732 4733 // If extracting from the first vector, just use the index directly. 4734 if (Extract.getOperand(0) == VecIn1) { 4735 BuildVecIndices.push_back(Extract.getOperand(1)); 4736 continue; 4737 } 4738 4739 // Otherwise, use InIdx + VecSize 4740 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4741 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4742 } 4743 4744 // Add count and size info. 4745 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); 4746 4747 // Return the new VECTOR_SHUFFLE node. 4748 SDOperand Ops[5]; 4749 Ops[0] = VecIn1; 4750 if (VecIn2.Val) { 4751 Ops[1] = VecIn2; 4752 } else { 4753 // Use an undef build_vector as input for the second operand. 4754 std::vector<SDOperand> UnOps(NumInScalars, 4755 DAG.getNode(ISD::UNDEF, 4756 EltType)); 4757 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4758 &UnOps[0], UnOps.size()); 4759 AddToWorkList(Ops[1].Val); 4760 } 4761 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4762 &BuildVecIndices[0], BuildVecIndices.size()); 4763 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4764 } 4765 4766 return SDOperand(); 4767} 4768 4769SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4770 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4771 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4772 // inputs come from at most two distinct vectors, turn this into a shuffle 4773 // node. 4774 4775 // If we only have one input vector, we don't need to do any concatenation. 4776 if (N->getNumOperands() == 1) { 4777 return N->getOperand(0); 4778 } 4779 4780 return SDOperand(); 4781} 4782 4783SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4784 SDOperand ShufMask = N->getOperand(2); 4785 unsigned NumElts = ShufMask.getNumOperands(); 4786 4787 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4788 bool isIdentity = true; 4789 for (unsigned i = 0; i != NumElts; ++i) { 4790 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4791 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4792 isIdentity = false; 4793 break; 4794 } 4795 } 4796 if (isIdentity) return N->getOperand(0); 4797 4798 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4799 isIdentity = true; 4800 for (unsigned i = 0; i != NumElts; ++i) { 4801 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4802 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4803 isIdentity = false; 4804 break; 4805 } 4806 } 4807 if (isIdentity) return N->getOperand(1); 4808 4809 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4810 // needed at all. 4811 bool isUnary = true; 4812 bool isSplat = true; 4813 int VecNum = -1; 4814 unsigned BaseIdx = 0; 4815 for (unsigned i = 0; i != NumElts; ++i) 4816 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4817 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4818 int V = (Idx < NumElts) ? 0 : 1; 4819 if (VecNum == -1) { 4820 VecNum = V; 4821 BaseIdx = Idx; 4822 } else { 4823 if (BaseIdx != Idx) 4824 isSplat = false; 4825 if (VecNum != V) { 4826 isUnary = false; 4827 break; 4828 } 4829 } 4830 } 4831 4832 SDOperand N0 = N->getOperand(0); 4833 SDOperand N1 = N->getOperand(1); 4834 // Normalize unary shuffle so the RHS is undef. 4835 if (isUnary && VecNum == 1) 4836 std::swap(N0, N1); 4837 4838 // If it is a splat, check if the argument vector is a build_vector with 4839 // all scalar elements the same. 4840 if (isSplat) { 4841 SDNode *V = N0.Val; 4842 4843 // If this is a bit convert that changes the element type of the vector but 4844 // not the number of vector elements, look through it. Be careful not to 4845 // look though conversions that change things like v4f32 to v2f64. 4846 if (V->getOpcode() == ISD::BIT_CONVERT) { 4847 SDOperand ConvInput = V->getOperand(0); 4848 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4849 V = ConvInput.Val; 4850 } 4851 4852 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4853 unsigned NumElems = V->getNumOperands(); 4854 if (NumElems > BaseIdx) { 4855 SDOperand Base; 4856 bool AllSame = true; 4857 for (unsigned i = 0; i != NumElems; ++i) { 4858 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4859 Base = V->getOperand(i); 4860 break; 4861 } 4862 } 4863 // Splat of <u, u, u, u>, return <u, u, u, u> 4864 if (!Base.Val) 4865 return N0; 4866 for (unsigned i = 0; i != NumElems; ++i) { 4867 if (V->getOperand(i) != Base) { 4868 AllSame = false; 4869 break; 4870 } 4871 } 4872 // Splat of <x, x, x, x>, return <x, x, x, x> 4873 if (AllSame) 4874 return N0; 4875 } 4876 } 4877 } 4878 4879 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4880 // into an undef. 4881 if (isUnary || N0 == N1) { 4882 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4883 // first operand. 4884 SmallVector<SDOperand, 8> MappedOps; 4885 for (unsigned i = 0; i != NumElts; ++i) { 4886 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4887 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4888 MappedOps.push_back(ShufMask.getOperand(i)); 4889 } else { 4890 unsigned NewIdx = 4891 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4892 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4893 } 4894 } 4895 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4896 &MappedOps[0], MappedOps.size()); 4897 AddToWorkList(ShufMask.Val); 4898 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4899 N0, 4900 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4901 ShufMask); 4902 } 4903 4904 return SDOperand(); 4905} 4906 4907/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4908/// an AND to a vector_shuffle with the destination vector and a zero vector. 4909/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4910/// vector_shuffle V, Zero, <0, 4, 2, 4> 4911SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4912 SDOperand LHS = N->getOperand(0); 4913 SDOperand RHS = N->getOperand(1); 4914 if (N->getOpcode() == ISD::AND) { 4915 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4916 RHS = RHS.getOperand(0); 4917 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4918 std::vector<SDOperand> IdxOps; 4919 unsigned NumOps = RHS.getNumOperands(); 4920 unsigned NumElts = NumOps; 4921 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4922 for (unsigned i = 0; i != NumElts; ++i) { 4923 SDOperand Elt = RHS.getOperand(i); 4924 if (!isa<ConstantSDNode>(Elt)) 4925 return SDOperand(); 4926 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4927 IdxOps.push_back(DAG.getConstant(i, EVT)); 4928 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4929 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4930 else 4931 return SDOperand(); 4932 } 4933 4934 // Let's see if the target supports this vector_shuffle. 4935 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4936 return SDOperand(); 4937 4938 // Return the new VECTOR_SHUFFLE node. 4939 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4940 std::vector<SDOperand> Ops; 4941 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4942 Ops.push_back(LHS); 4943 AddToWorkList(LHS.Val); 4944 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4945 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4946 &ZeroOps[0], ZeroOps.size())); 4947 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4948 &IdxOps[0], IdxOps.size())); 4949 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4950 &Ops[0], Ops.size()); 4951 if (VT != LHS.getValueType()) { 4952 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4953 } 4954 return Result; 4955 } 4956 } 4957 return SDOperand(); 4958} 4959 4960/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4961SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4962 // After legalize, the target may be depending on adds and other 4963 // binary ops to provide legal ways to construct constants or other 4964 // things. Simplifying them may result in a loss of legality. 4965 if (AfterLegalize) return SDOperand(); 4966 4967 MVT::ValueType VT = N->getValueType(0); 4968 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4969 4970 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4971 SDOperand LHS = N->getOperand(0); 4972 SDOperand RHS = N->getOperand(1); 4973 SDOperand Shuffle = XformToShuffleWithZero(N); 4974 if (Shuffle.Val) return Shuffle; 4975 4976 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4977 // this operation. 4978 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4979 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4980 SmallVector<SDOperand, 8> Ops; 4981 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4982 SDOperand LHSOp = LHS.getOperand(i); 4983 SDOperand RHSOp = RHS.getOperand(i); 4984 // If these two elements can't be folded, bail out. 4985 if ((LHSOp.getOpcode() != ISD::UNDEF && 4986 LHSOp.getOpcode() != ISD::Constant && 4987 LHSOp.getOpcode() != ISD::ConstantFP) || 4988 (RHSOp.getOpcode() != ISD::UNDEF && 4989 RHSOp.getOpcode() != ISD::Constant && 4990 RHSOp.getOpcode() != ISD::ConstantFP)) 4991 break; 4992 // Can't fold divide by zero. 4993 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4994 N->getOpcode() == ISD::FDIV) { 4995 if ((RHSOp.getOpcode() == ISD::Constant && 4996 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4997 (RHSOp.getOpcode() == ISD::ConstantFP && 4998 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4999 break; 5000 } 5001 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5002 AddToWorkList(Ops.back().Val); 5003 assert((Ops.back().getOpcode() == ISD::UNDEF || 5004 Ops.back().getOpcode() == ISD::Constant || 5005 Ops.back().getOpcode() == ISD::ConstantFP) && 5006 "Scalar binop didn't fold!"); 5007 } 5008 5009 if (Ops.size() == LHS.getNumOperands()) { 5010 MVT::ValueType VT = LHS.getValueType(); 5011 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5012 } 5013 } 5014 5015 return SDOperand(); 5016} 5017 5018SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 5019 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5020 5021 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5022 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5023 // If we got a simplified select_cc node back from SimplifySelectCC, then 5024 // break it down into a new SETCC node, and a new SELECT node, and then return 5025 // the SELECT node, since we were called with a SELECT node. 5026 if (SCC.Val) { 5027 // Check to see if we got a select_cc back (to turn into setcc/select). 5028 // Otherwise, just return whatever node we got back, like fabs. 5029 if (SCC.getOpcode() == ISD::SELECT_CC) { 5030 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5031 SCC.getOperand(0), SCC.getOperand(1), 5032 SCC.getOperand(4)); 5033 AddToWorkList(SETCC.Val); 5034 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5035 SCC.getOperand(3), SETCC); 5036 } 5037 return SCC; 5038 } 5039 return SDOperand(); 5040} 5041 5042/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5043/// are the two values being selected between, see if we can simplify the 5044/// select. Callers of this should assume that TheSelect is deleted if this 5045/// returns true. As such, they should return the appropriate thing (e.g. the 5046/// node) back to the top-level of the DAG combiner loop to avoid it being 5047/// looked at. 5048/// 5049bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 5050 SDOperand RHS) { 5051 5052 // If this is a select from two identical things, try to pull the operation 5053 // through the select. 5054 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5055 // If this is a load and the token chain is identical, replace the select 5056 // of two loads with a load through a select of the address to load from. 5057 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5058 // constants have been dropped into the constant pool. 5059 if (LHS.getOpcode() == ISD::LOAD && 5060 // Token chains must be identical. 5061 LHS.getOperand(0) == RHS.getOperand(0)) { 5062 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5063 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5064 5065 // If this is an EXTLOAD, the VT's must match. 5066 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5067 // FIXME: this conflates two src values, discarding one. This is not 5068 // the right thing to do, but nothing uses srcvalues now. When they do, 5069 // turn SrcValue into a list of locations. 5070 SDOperand Addr; 5071 if (TheSelect->getOpcode() == ISD::SELECT) { 5072 // Check that the condition doesn't reach either load. If so, folding 5073 // this will induce a cycle into the DAG. 5074 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5075 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) { 5076 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5077 TheSelect->getOperand(0), LLD->getBasePtr(), 5078 RLD->getBasePtr()); 5079 } 5080 } else { 5081 // Check that the condition doesn't reach either load. If so, folding 5082 // this will induce a cycle into the DAG. 5083 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5084 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5085 !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) && 5086 !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) { 5087 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5088 TheSelect->getOperand(0), 5089 TheSelect->getOperand(1), 5090 LLD->getBasePtr(), RLD->getBasePtr(), 5091 TheSelect->getOperand(4)); 5092 } 5093 } 5094 5095 if (Addr.Val) { 5096 SDOperand Load; 5097 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5098 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5099 Addr,LLD->getSrcValue(), 5100 LLD->getSrcValueOffset(), 5101 LLD->isVolatile(), 5102 LLD->getAlignment()); 5103 else { 5104 Load = DAG.getExtLoad(LLD->getExtensionType(), 5105 TheSelect->getValueType(0), 5106 LLD->getChain(), Addr, LLD->getSrcValue(), 5107 LLD->getSrcValueOffset(), 5108 LLD->getMemoryVT(), 5109 LLD->isVolatile(), 5110 LLD->getAlignment()); 5111 } 5112 // Users of the select now use the result of the load. 5113 CombineTo(TheSelect, Load); 5114 5115 // Users of the old loads now use the new load's chain. We know the 5116 // old-load value is dead now. 5117 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 5118 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 5119 return true; 5120 } 5121 } 5122 } 5123 } 5124 5125 return false; 5126} 5127 5128SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 5129 SDOperand N2, SDOperand N3, 5130 ISD::CondCode CC, bool NotExtCompare) { 5131 5132 MVT::ValueType VT = N2.getValueType(); 5133 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5134 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5135 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5136 5137 // Determine if the condition we're dealing with is constant 5138 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5139 if (SCC.Val) AddToWorkList(SCC.Val); 5140 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5141 5142 // fold select_cc true, x, y -> x 5143 if (SCCC && !SCCC->isNullValue()) 5144 return N2; 5145 // fold select_cc false, x, y -> y 5146 if (SCCC && SCCC->isNullValue()) 5147 return N3; 5148 5149 // Check to see if we can simplify the select into an fabs node 5150 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5151 // Allow either -0.0 or 0.0 5152 if (CFP->getValueAPF().isZero()) { 5153 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5154 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5155 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5156 N2 == N3.getOperand(0)) 5157 return DAG.getNode(ISD::FABS, VT, N0); 5158 5159 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5160 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5161 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5162 N2.getOperand(0) == N3) 5163 return DAG.getNode(ISD::FABS, VT, N3); 5164 } 5165 } 5166 5167 // Check to see if we can perform the "gzip trick", transforming 5168 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5169 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5170 MVT::isInteger(N0.getValueType()) && 5171 MVT::isInteger(N2.getValueType()) && 5172 (N1C->isNullValue() || // (a < 0) ? b : 0 5173 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5174 MVT::ValueType XType = N0.getValueType(); 5175 MVT::ValueType AType = N2.getValueType(); 5176 if (XType >= AType) { 5177 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5178 // single-bit constant. 5179 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5180 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5181 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 5182 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5183 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5184 AddToWorkList(Shift.Val); 5185 if (XType > AType) { 5186 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5187 AddToWorkList(Shift.Val); 5188 } 5189 return DAG.getNode(ISD::AND, AType, Shift, N2); 5190 } 5191 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5192 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5193 TLI.getShiftAmountTy())); 5194 AddToWorkList(Shift.Val); 5195 if (XType > AType) { 5196 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5197 AddToWorkList(Shift.Val); 5198 } 5199 return DAG.getNode(ISD::AND, AType, Shift, N2); 5200 } 5201 } 5202 5203 // fold select C, 16, 0 -> shl C, 4 5204 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5205 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5206 5207 // If the caller doesn't want us to simplify this into a zext of a compare, 5208 // don't do it. 5209 if (NotExtCompare && N2C->getAPIntValue() == 1) 5210 return SDOperand(); 5211 5212 // Get a SetCC of the condition 5213 // FIXME: Should probably make sure that setcc is legal if we ever have a 5214 // target where it isn't. 5215 SDOperand Temp, SCC; 5216 // cast from setcc result type to select result type 5217 if (AfterLegalize) { 5218 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5219 if (N2.getValueType() < SCC.getValueType()) 5220 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5221 else 5222 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5223 } else { 5224 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5225 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5226 } 5227 AddToWorkList(SCC.Val); 5228 AddToWorkList(Temp.Val); 5229 5230 if (N2C->getAPIntValue() == 1) 5231 return Temp; 5232 // shl setcc result by log2 n2c 5233 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5234 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5235 TLI.getShiftAmountTy())); 5236 } 5237 5238 // Check to see if this is the equivalent of setcc 5239 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5240 // otherwise, go ahead with the folds. 5241 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5242 MVT::ValueType XType = N0.getValueType(); 5243 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5244 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5245 if (Res.getValueType() != VT) 5246 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5247 return Res; 5248 } 5249 5250 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5251 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5252 TLI.isOperationLegal(ISD::CTLZ, XType)) { 5253 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5254 return DAG.getNode(ISD::SRL, XType, Ctlz, 5255 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 5256 TLI.getShiftAmountTy())); 5257 } 5258 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5259 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5260 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5261 N0); 5262 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5263 DAG.getConstant(~0ULL, XType)); 5264 return DAG.getNode(ISD::SRL, XType, 5265 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5266 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5267 TLI.getShiftAmountTy())); 5268 } 5269 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5270 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5271 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5272 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5273 TLI.getShiftAmountTy())); 5274 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5275 } 5276 } 5277 5278 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5279 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5280 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5281 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5282 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 5283 MVT::ValueType XType = N0.getValueType(); 5284 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5285 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5286 TLI.getShiftAmountTy())); 5287 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5288 AddToWorkList(Shift.Val); 5289 AddToWorkList(Add.Val); 5290 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5291 } 5292 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5293 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5294 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5295 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5296 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5297 MVT::ValueType XType = N0.getValueType(); 5298 if (SubC->isNullValue() && MVT::isInteger(XType)) { 5299 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5300 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5301 TLI.getShiftAmountTy())); 5302 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5303 AddToWorkList(Shift.Val); 5304 AddToWorkList(Add.Val); 5305 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5306 } 5307 } 5308 } 5309 5310 return SDOperand(); 5311} 5312 5313/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5314SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 5315 SDOperand N1, ISD::CondCode Cond, 5316 bool foldBooleans) { 5317 TargetLowering::DAGCombinerInfo 5318 DagCombineInfo(DAG, !AfterLegalize, false, this); 5319 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5320} 5321 5322/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5323/// return a DAG expression to select that will generate the same value by 5324/// multiplying by a magic number. See: 5325/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5326SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5327 std::vector<SDNode*> Built; 5328 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5329 5330 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5331 ii != ee; ++ii) 5332 AddToWorkList(*ii); 5333 return S; 5334} 5335 5336/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5337/// return a DAG expression to select that will generate the same value by 5338/// multiplying by a magic number. See: 5339/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5340SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5341 std::vector<SDNode*> Built; 5342 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5343 5344 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5345 ii != ee; ++ii) 5346 AddToWorkList(*ii); 5347 return S; 5348} 5349 5350/// FindBaseOffset - Return true if base is known not to alias with anything 5351/// but itself. Provides base object and offset as results. 5352static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5353 // Assume it is a primitive operation. 5354 Base = Ptr; Offset = 0; 5355 5356 // If it's an adding a simple constant then integrate the offset. 5357 if (Base.getOpcode() == ISD::ADD) { 5358 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5359 Base = Base.getOperand(0); 5360 Offset += C->getValue(); 5361 } 5362 } 5363 5364 // If it's any of the following then it can't alias with anything but itself. 5365 return isa<FrameIndexSDNode>(Base) || 5366 isa<ConstantPoolSDNode>(Base) || 5367 isa<GlobalAddressSDNode>(Base); 5368} 5369 5370/// isAlias - Return true if there is any possibility that the two addresses 5371/// overlap. 5372bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5373 const Value *SrcValue1, int SrcValueOffset1, 5374 SDOperand Ptr2, int64_t Size2, 5375 const Value *SrcValue2, int SrcValueOffset2) 5376{ 5377 // If they are the same then they must be aliases. 5378 if (Ptr1 == Ptr2) return true; 5379 5380 // Gather base node and offset information. 5381 SDOperand Base1, Base2; 5382 int64_t Offset1, Offset2; 5383 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5384 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5385 5386 // If they have a same base address then... 5387 if (Base1 == Base2) { 5388 // Check to see if the addresses overlap. 5389 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5390 } 5391 5392 // If we know both bases then they can't alias. 5393 if (KnownBase1 && KnownBase2) return false; 5394 5395 if (CombinerGlobalAA) { 5396 // Use alias analysis information. 5397 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5398 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5399 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5400 AliasAnalysis::AliasResult AAResult = 5401 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5402 if (AAResult == AliasAnalysis::NoAlias) 5403 return false; 5404 } 5405 5406 // Otherwise we have to assume they alias. 5407 return true; 5408} 5409 5410/// FindAliasInfo - Extracts the relevant alias information from the memory 5411/// node. Returns true if the operand was a load. 5412bool DAGCombiner::FindAliasInfo(SDNode *N, 5413 SDOperand &Ptr, int64_t &Size, 5414 const Value *&SrcValue, int &SrcValueOffset) { 5415 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5416 Ptr = LD->getBasePtr(); 5417 Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3; 5418 SrcValue = LD->getSrcValue(); 5419 SrcValueOffset = LD->getSrcValueOffset(); 5420 return true; 5421 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5422 Ptr = ST->getBasePtr(); 5423 Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3; 5424 SrcValue = ST->getSrcValue(); 5425 SrcValueOffset = ST->getSrcValueOffset(); 5426 } else { 5427 assert(0 && "FindAliasInfo expected a memory operand"); 5428 } 5429 5430 return false; 5431} 5432 5433/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5434/// looking for aliasing nodes and adding them to the Aliases vector. 5435void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5436 SmallVector<SDOperand, 8> &Aliases) { 5437 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5438 std::set<SDNode *> Visited; // Visited node set. 5439 5440 // Get alias information for node. 5441 SDOperand Ptr; 5442 int64_t Size; 5443 const Value *SrcValue; 5444 int SrcValueOffset; 5445 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5446 5447 // Starting off. 5448 Chains.push_back(OriginalChain); 5449 5450 // Look at each chain and determine if it is an alias. If so, add it to the 5451 // aliases list. If not, then continue up the chain looking for the next 5452 // candidate. 5453 while (!Chains.empty()) { 5454 SDOperand Chain = Chains.back(); 5455 Chains.pop_back(); 5456 5457 // Don't bother if we've been before. 5458 if (Visited.find(Chain.Val) != Visited.end()) continue; 5459 Visited.insert(Chain.Val); 5460 5461 switch (Chain.getOpcode()) { 5462 case ISD::EntryToken: 5463 // Entry token is ideal chain operand, but handled in FindBetterChain. 5464 break; 5465 5466 case ISD::LOAD: 5467 case ISD::STORE: { 5468 // Get alias information for Chain. 5469 SDOperand OpPtr; 5470 int64_t OpSize; 5471 const Value *OpSrcValue; 5472 int OpSrcValueOffset; 5473 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5474 OpSrcValue, OpSrcValueOffset); 5475 5476 // If chain is alias then stop here. 5477 if (!(IsLoad && IsOpLoad) && 5478 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5479 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5480 Aliases.push_back(Chain); 5481 } else { 5482 // Look further up the chain. 5483 Chains.push_back(Chain.getOperand(0)); 5484 // Clean up old chain. 5485 AddToWorkList(Chain.Val); 5486 } 5487 break; 5488 } 5489 5490 case ISD::TokenFactor: 5491 // We have to check each of the operands of the token factor, so we queue 5492 // then up. Adding the operands to the queue (stack) in reverse order 5493 // maintains the original order and increases the likelihood that getNode 5494 // will find a matching token factor (CSE.) 5495 for (unsigned n = Chain.getNumOperands(); n;) 5496 Chains.push_back(Chain.getOperand(--n)); 5497 // Eliminate the token factor if we can. 5498 AddToWorkList(Chain.Val); 5499 break; 5500 5501 default: 5502 // For all other instructions we will just have to take what we can get. 5503 Aliases.push_back(Chain); 5504 break; 5505 } 5506 } 5507} 5508 5509/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5510/// for a better chain (aliasing node.) 5511SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5512 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5513 5514 // Accumulate all the aliases to this node. 5515 GatherAllAliases(N, OldChain, Aliases); 5516 5517 if (Aliases.size() == 0) { 5518 // If no operands then chain to entry token. 5519 return DAG.getEntryNode(); 5520 } else if (Aliases.size() == 1) { 5521 // If a single operand then chain to it. We don't need to revisit it. 5522 return Aliases[0]; 5523 } 5524 5525 // Construct a custom tailored token factor. 5526 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5527 &Aliases[0], Aliases.size()); 5528 5529 // Make sure the old chain gets cleaned up. 5530 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5531 5532 return NewChain; 5533} 5534 5535// SelectionDAG::Combine - This is the entry point for the file. 5536// 5537void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5538 if (!RunningAfterLegalize && ViewDAGCombine1) 5539 viewGraph(); 5540 if (RunningAfterLegalize && ViewDAGCombine2) 5541 viewGraph(); 5542 /// run - This is the main entry point to this class. 5543 /// 5544 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5545} 5546