DAGCombiner.cpp revision 5fc7e5c28a72511a17e5f84ef2b6327b8b8862e0
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 TargetLowering &TLI; 53 bool AfterLegalize; 54 bool Fast; 55 56 // Worklist of all of the nodes that need to be simplified. 57 std::vector<SDNode*> WorkList; 58 59 // AA - Used for DAG load/store alias analysis. 60 AliasAnalysis &AA; 61 62 /// AddUsersToWorkList - When an instruction is simplified, add all users of 63 /// the instruction to the work lists because they might get more simplified 64 /// now. 65 /// 66 void AddUsersToWorkList(SDNode *N) { 67 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 68 UI != UE; ++UI) 69 AddToWorkList(*UI); 70 } 71 72 /// visit - call the node-specific routine that knows how to fold each 73 /// particular type of node. 74 SDValue visit(SDNode *N); 75 76 public: 77 /// AddToWorkList - Add to the work list making sure it's instance is at the 78 /// the back (next to be processed.) 79 void AddToWorkList(SDNode *N) { 80 removeFromWorkList(N); 81 WorkList.push_back(N); 82 } 83 84 /// removeFromWorkList - remove all instances of N from the worklist. 85 /// 86 void removeFromWorkList(SDNode *N) { 87 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 88 WorkList.end()); 89 } 90 91 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 92 bool AddTo = true); 93 94 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 95 return CombineTo(N, &Res, 1, AddTo); 96 } 97 98 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 99 bool AddTo = true) { 100 SDValue To[] = { Res0, Res1 }; 101 return CombineTo(N, To, 2, AddTo); 102 } 103 104 private: 105 106 /// SimplifyDemandedBits - Check the specified integer node value to see if 107 /// it can be simplified or if things it uses can be simplified by bit 108 /// propagation. If so, return true. 109 bool SimplifyDemandedBits(SDValue Op) { 110 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 111 return SimplifyDemandedBits(Op, Demanded); 112 } 113 114 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 115 116 bool CombineToPreIndexedLoadStore(SDNode *N); 117 bool CombineToPostIndexedLoadStore(SDNode *N); 118 119 120 /// combine - call the node-specific routine that knows how to fold each 121 /// particular type of node. If that doesn't do anything, try the 122 /// target-specific DAG combines. 123 SDValue combine(SDNode *N); 124 125 // Visitation implementation - Implement dag node combining for different 126 // node types. The semantics are as follows: 127 // Return Value: 128 // SDValue.getNode() == 0 - No change was made 129 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 130 // otherwise - N should be replaced by the returned Operand. 131 // 132 SDValue visitTokenFactor(SDNode *N); 133 SDValue visitMERGE_VALUES(SDNode *N); 134 SDValue visitADD(SDNode *N); 135 SDValue visitSUB(SDNode *N); 136 SDValue visitADDC(SDNode *N); 137 SDValue visitADDE(SDNode *N); 138 SDValue visitMUL(SDNode *N); 139 SDValue visitSDIV(SDNode *N); 140 SDValue visitUDIV(SDNode *N); 141 SDValue visitSREM(SDNode *N); 142 SDValue visitUREM(SDNode *N); 143 SDValue visitMULHU(SDNode *N); 144 SDValue visitMULHS(SDNode *N); 145 SDValue visitSMUL_LOHI(SDNode *N); 146 SDValue visitUMUL_LOHI(SDNode *N); 147 SDValue visitSDIVREM(SDNode *N); 148 SDValue visitUDIVREM(SDNode *N); 149 SDValue visitAND(SDNode *N); 150 SDValue visitOR(SDNode *N); 151 SDValue visitXOR(SDNode *N); 152 SDValue SimplifyVBinOp(SDNode *N); 153 SDValue visitSHL(SDNode *N); 154 SDValue visitSRA(SDNode *N); 155 SDValue visitSRL(SDNode *N); 156 SDValue visitCTLZ(SDNode *N); 157 SDValue visitCTTZ(SDNode *N); 158 SDValue visitCTPOP(SDNode *N); 159 SDValue visitSELECT(SDNode *N); 160 SDValue visitSELECT_CC(SDNode *N); 161 SDValue visitSETCC(SDNode *N); 162 SDValue visitSIGN_EXTEND(SDNode *N); 163 SDValue visitZERO_EXTEND(SDNode *N); 164 SDValue visitANY_EXTEND(SDNode *N); 165 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 166 SDValue visitTRUNCATE(SDNode *N); 167 SDValue visitBIT_CONVERT(SDNode *N); 168 SDValue visitBUILD_PAIR(SDNode *N); 169 SDValue visitFADD(SDNode *N); 170 SDValue visitFSUB(SDNode *N); 171 SDValue visitFMUL(SDNode *N); 172 SDValue visitFDIV(SDNode *N); 173 SDValue visitFREM(SDNode *N); 174 SDValue visitFCOPYSIGN(SDNode *N); 175 SDValue visitSINT_TO_FP(SDNode *N); 176 SDValue visitUINT_TO_FP(SDNode *N); 177 SDValue visitFP_TO_SINT(SDNode *N); 178 SDValue visitFP_TO_UINT(SDNode *N); 179 SDValue visitFP_ROUND(SDNode *N); 180 SDValue visitFP_ROUND_INREG(SDNode *N); 181 SDValue visitFP_EXTEND(SDNode *N); 182 SDValue visitFNEG(SDNode *N); 183 SDValue visitFABS(SDNode *N); 184 SDValue visitBRCOND(SDNode *N); 185 SDValue visitBR_CC(SDNode *N); 186 SDValue visitLOAD(SDNode *N); 187 SDValue visitSTORE(SDNode *N); 188 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 189 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 190 SDValue visitBUILD_VECTOR(SDNode *N); 191 SDValue visitCONCAT_VECTORS(SDNode *N); 192 SDValue visitVECTOR_SHUFFLE(SDNode *N); 193 SDValue visitADDO(SDNode *N); 194 195 SDValue XformToShuffleWithZero(SDNode *N); 196 SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS); 197 198 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 199 200 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 201 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 202 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 203 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 204 SDValue N3, ISD::CondCode CC, 205 bool NotExtCompare = false); 206 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 207 ISD::CondCode Cond, bool foldBooleans = true); 208 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 209 unsigned HiOp); 210 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 211 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 212 SDValue BuildSDIV(SDNode *N); 213 SDValue BuildUDIV(SDNode *N); 214 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 215 SDValue ReduceLoadWidth(SDNode *N); 216 217 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 218 219 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 220 /// looking for aliasing nodes and adding them to the Aliases vector. 221 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 222 SmallVector<SDValue, 8> &Aliases); 223 224 /// isAlias - Return true if there is any possibility that the two addresses 225 /// overlap. 226 bool isAlias(SDValue Ptr1, int64_t Size1, 227 const Value *SrcValue1, int SrcValueOffset1, 228 SDValue Ptr2, int64_t Size2, 229 const Value *SrcValue2, int SrcValueOffset2); 230 231 /// FindAliasInfo - Extracts the relevant alias information from the memory 232 /// node. Returns true if the operand was a load. 233 bool FindAliasInfo(SDNode *N, 234 SDValue &Ptr, int64_t &Size, 235 const Value *&SrcValue, int &SrcValueOffset); 236 237 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 238 /// looking for a better chain (aliasing node.) 239 SDValue FindBetterChain(SDNode *N, SDValue Chain); 240 241public: 242 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 243 : DAG(D), 244 TLI(D.getTargetLoweringInfo()), 245 AfterLegalize(false), 246 Fast(fast), 247 AA(A) {} 248 249 /// Run - runs the dag combiner on all nodes in the work list 250 void Run(bool RunningAfterLegalize); 251 }; 252} 253 254 255namespace { 256/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 257/// nodes from the worklist. 258class VISIBILITY_HIDDEN WorkListRemover : 259 public SelectionDAG::DAGUpdateListener { 260 DAGCombiner &DC; 261public: 262 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 263 264 virtual void NodeDeleted(SDNode *N, SDNode *E) { 265 DC.removeFromWorkList(N); 266 } 267 268 virtual void NodeUpdated(SDNode *N) { 269 // Ignore updates. 270 } 271}; 272} 273 274//===----------------------------------------------------------------------===// 275// TargetLowering::DAGCombinerInfo implementation 276//===----------------------------------------------------------------------===// 277 278void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 279 ((DAGCombiner*)DC)->AddToWorkList(N); 280} 281 282SDValue TargetLowering::DAGCombinerInfo:: 283CombineTo(SDNode *N, const std::vector<SDValue> &To) { 284 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 285} 286 287SDValue TargetLowering::DAGCombinerInfo:: 288CombineTo(SDNode *N, SDValue Res) { 289 return ((DAGCombiner*)DC)->CombineTo(N, Res); 290} 291 292 293SDValue TargetLowering::DAGCombinerInfo:: 294CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 295 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 296} 297 298 299//===----------------------------------------------------------------------===// 300// Helper Functions 301//===----------------------------------------------------------------------===// 302 303/// isNegatibleForFree - Return 1 if we can compute the negated form of the 304/// specified expression for the same cost as the expression itself, or 2 if we 305/// can compute the negated form more cheaply than the expression itself. 306static char isNegatibleForFree(SDValue Op, bool AfterLegalize, 307 unsigned Depth = 0) { 308 // No compile time optimizations on this type. 309 if (Op.getValueType() == MVT::ppcf128) 310 return 0; 311 312 // fneg is removable even if it has multiple uses. 313 if (Op.getOpcode() == ISD::FNEG) return 2; 314 315 // Don't allow anything with multiple uses. 316 if (!Op.hasOneUse()) return 0; 317 318 // Don't recurse exponentially. 319 if (Depth > 6) return 0; 320 321 switch (Op.getOpcode()) { 322 default: return false; 323 case ISD::ConstantFP: 324 // Don't invert constant FP values after legalize. The negated constant 325 // isn't necessarily legal. 326 return AfterLegalize ? 0 : 1; 327 case ISD::FADD: 328 // FIXME: determine better conditions for this xform. 329 if (!UnsafeFPMath) return 0; 330 331 // -(A+B) -> -A - B 332 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 333 return V; 334 // -(A+B) -> -B - A 335 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 336 case ISD::FSUB: 337 // We can't turn -(A-B) into B-A when we honor signed zeros. 338 if (!UnsafeFPMath) return 0; 339 340 // -(A-B) -> B-A 341 return 1; 342 343 case ISD::FMUL: 344 case ISD::FDIV: 345 if (HonorSignDependentRoundingFPMath()) return 0; 346 347 // -(X*Y) -> (-X * Y) or (X*-Y) 348 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 349 return V; 350 351 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 352 353 case ISD::FP_EXTEND: 354 case ISD::FP_ROUND: 355 case ISD::FSIN: 356 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 357 } 358} 359 360/// GetNegatedExpression - If isNegatibleForFree returns true, this function 361/// returns the newly negated expression. 362static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 363 bool AfterLegalize, unsigned Depth = 0) { 364 // fneg is removable even if it has multiple uses. 365 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 366 367 // Don't allow anything with multiple uses. 368 assert(Op.hasOneUse() && "Unknown reuse!"); 369 370 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 371 switch (Op.getOpcode()) { 372 default: assert(0 && "Unknown code"); 373 case ISD::ConstantFP: { 374 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 375 V.changeSign(); 376 return DAG.getConstantFP(V, Op.getValueType()); 377 } 378 case ISD::FADD: 379 // FIXME: determine better conditions for this xform. 380 assert(UnsafeFPMath); 381 382 // -(A+B) -> -A - B 383 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 384 return DAG.getNode(ISD::FSUB, Op.getValueType(), 385 GetNegatedExpression(Op.getOperand(0), DAG, 386 AfterLegalize, Depth+1), 387 Op.getOperand(1)); 388 // -(A+B) -> -B - A 389 return DAG.getNode(ISD::FSUB, Op.getValueType(), 390 GetNegatedExpression(Op.getOperand(1), DAG, 391 AfterLegalize, Depth+1), 392 Op.getOperand(0)); 393 case ISD::FSUB: 394 // We can't turn -(A-B) into B-A when we honor signed zeros. 395 assert(UnsafeFPMath); 396 397 // -(0-B) -> B 398 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 399 if (N0CFP->getValueAPF().isZero()) 400 return Op.getOperand(1); 401 402 // -(A-B) -> B-A 403 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 404 Op.getOperand(0)); 405 406 case ISD::FMUL: 407 case ISD::FDIV: 408 assert(!HonorSignDependentRoundingFPMath()); 409 410 // -(X*Y) -> -X * Y 411 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 412 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 413 GetNegatedExpression(Op.getOperand(0), DAG, 414 AfterLegalize, Depth+1), 415 Op.getOperand(1)); 416 417 // -(X*Y) -> X * -Y 418 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 419 Op.getOperand(0), 420 GetNegatedExpression(Op.getOperand(1), DAG, 421 AfterLegalize, Depth+1)); 422 423 case ISD::FP_EXTEND: 424 case ISD::FSIN: 425 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 426 GetNegatedExpression(Op.getOperand(0), DAG, 427 AfterLegalize, Depth+1)); 428 case ISD::FP_ROUND: 429 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 430 GetNegatedExpression(Op.getOperand(0), DAG, 431 AfterLegalize, Depth+1), 432 Op.getOperand(1)); 433 } 434} 435 436 437// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 438// that selects between the values 1 and 0, making it equivalent to a setcc. 439// Also, set the incoming LHS, RHS, and CC references to the appropriate 440// nodes based on the type of node we are checking. This simplifies life a 441// bit for the callers. 442static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 443 SDValue &CC) { 444 if (N.getOpcode() == ISD::SETCC) { 445 LHS = N.getOperand(0); 446 RHS = N.getOperand(1); 447 CC = N.getOperand(2); 448 return true; 449 } 450 if (N.getOpcode() == ISD::SELECT_CC && 451 N.getOperand(2).getOpcode() == ISD::Constant && 452 N.getOperand(3).getOpcode() == ISD::Constant && 453 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 454 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 455 LHS = N.getOperand(0); 456 RHS = N.getOperand(1); 457 CC = N.getOperand(4); 458 return true; 459 } 460 return false; 461} 462 463// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 464// one use. If this is true, it allows the users to invert the operation for 465// free when it is profitable to do so. 466static bool isOneUseSetCC(SDValue N) { 467 SDValue N0, N1, N2; 468 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 469 return true; 470 return false; 471} 472 473SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){ 474 MVT VT = N0.getValueType(); 475 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 476 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 477 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 478 if (isa<ConstantSDNode>(N1)) { 479 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 480 AddToWorkList(OpNode.getNode()); 481 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 482 } else if (N0.hasOneUse()) { 483 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 484 AddToWorkList(OpNode.getNode()); 485 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 486 } 487 } 488 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 489 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 490 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 491 if (isa<ConstantSDNode>(N0)) { 492 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 493 AddToWorkList(OpNode.getNode()); 494 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 495 } else if (N1.hasOneUse()) { 496 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 497 AddToWorkList(OpNode.getNode()); 498 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 499 } 500 } 501 return SDValue(); 502} 503 504SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 505 bool AddTo) { 506 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 507 ++NodesCombined; 508 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 509 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 510 DOUT << " and " << NumTo-1 << " other values\n"; 511 WorkListRemover DeadNodes(*this); 512 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 513 514 if (AddTo) { 515 // Push the new nodes and any users onto the worklist 516 for (unsigned i = 0, e = NumTo; i != e; ++i) { 517 AddToWorkList(To[i].getNode()); 518 AddUsersToWorkList(To[i].getNode()); 519 } 520 } 521 522 // Nodes can be reintroduced into the worklist. Make sure we do not 523 // process a node that has been replaced. 524 removeFromWorkList(N); 525 526 // Finally, since the node is now dead, remove it from the graph. 527 DAG.DeleteNode(N); 528 return SDValue(N, 0); 529} 530 531/// SimplifyDemandedBits - Check the specified integer node value to see if 532/// it can be simplified or if things it uses can be simplified by bit 533/// propagation. If so, return true. 534bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 535 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 536 APInt KnownZero, KnownOne; 537 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 538 return false; 539 540 // Revisit the node. 541 AddToWorkList(Op.getNode()); 542 543 // Replace the old value with the new one. 544 ++NodesCombined; 545 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 546 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 547 DOUT << '\n'; 548 549 // Replace all uses. If any nodes become isomorphic to other nodes and 550 // are deleted, make sure to remove them from our worklist. 551 WorkListRemover DeadNodes(*this); 552 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 553 554 // Push the new node and any (possibly new) users onto the worklist. 555 AddToWorkList(TLO.New.getNode()); 556 AddUsersToWorkList(TLO.New.getNode()); 557 558 // Finally, if the node is now dead, remove it from the graph. The node 559 // may not be dead if the replacement process recursively simplified to 560 // something else needing this node. 561 if (TLO.Old.getNode()->use_empty()) { 562 removeFromWorkList(TLO.Old.getNode()); 563 564 // If the operands of this node are only used by the node, they will now 565 // be dead. Make sure to visit them first to delete dead nodes early. 566 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 567 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 568 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 569 570 DAG.DeleteNode(TLO.Old.getNode()); 571 } 572 return true; 573} 574 575//===----------------------------------------------------------------------===// 576// Main DAG Combiner implementation 577//===----------------------------------------------------------------------===// 578 579void DAGCombiner::Run(bool RunningAfterLegalize) { 580 // set the instance variable, so that the various visit routines may use it. 581 AfterLegalize = RunningAfterLegalize; 582 583 // Add all the dag nodes to the worklist. 584 WorkList.reserve(DAG.allnodes_size()); 585 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 586 E = DAG.allnodes_end(); I != E; ++I) 587 WorkList.push_back(I); 588 589 // Create a dummy node (which is not added to allnodes), that adds a reference 590 // to the root node, preventing it from being deleted, and tracking any 591 // changes of the root. 592 HandleSDNode Dummy(DAG.getRoot()); 593 594 // The root of the dag may dangle to deleted nodes until the dag combiner is 595 // done. Set it to null to avoid confusion. 596 DAG.setRoot(SDValue()); 597 598 // while the worklist isn't empty, inspect the node on the end of it and 599 // try and combine it. 600 while (!WorkList.empty()) { 601 SDNode *N = WorkList.back(); 602 WorkList.pop_back(); 603 604 // If N has no uses, it is dead. Make sure to revisit all N's operands once 605 // N is deleted from the DAG, since they too may now be dead or may have a 606 // reduced number of uses, allowing other xforms. 607 if (N->use_empty() && N != &Dummy) { 608 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 609 AddToWorkList(N->getOperand(i).getNode()); 610 611 DAG.DeleteNode(N); 612 continue; 613 } 614 615 SDValue RV = combine(N); 616 617 if (RV.getNode() == 0) 618 continue; 619 620 ++NodesCombined; 621 622 // If we get back the same node we passed in, rather than a new node or 623 // zero, we know that the node must have defined multiple values and 624 // CombineTo was used. Since CombineTo takes care of the worklist 625 // mechanics for us, we have no work to do in this case. 626 if (RV.getNode() == N) 627 continue; 628 629 assert(N->getOpcode() != ISD::DELETED_NODE && 630 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 631 "Node was deleted but visit returned new node!"); 632 633 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 634 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 635 DOUT << '\n'; 636 WorkListRemover DeadNodes(*this); 637 if (N->getNumValues() == RV.getNode()->getNumValues()) 638 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 639 else { 640 assert(N->getValueType(0) == RV.getValueType() && 641 N->getNumValues() == 1 && "Type mismatch"); 642 SDValue OpV = RV; 643 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 644 } 645 646 // Push the new node and any users onto the worklist 647 AddToWorkList(RV.getNode()); 648 AddUsersToWorkList(RV.getNode()); 649 650 // Add any uses of the old node to the worklist in case this node is the 651 // last one that uses them. They may become dead after this node is 652 // deleted. 653 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 654 AddToWorkList(N->getOperand(i).getNode()); 655 656 // Nodes can be reintroduced into the worklist. Make sure we do not 657 // process a node that has been replaced. 658 removeFromWorkList(N); 659 660 // Finally, since the node is now dead, remove it from the graph. 661 DAG.DeleteNode(N); 662 } 663 664 // If the root changed (e.g. it was a dead load, update the root). 665 DAG.setRoot(Dummy.getValue()); 666} 667 668SDValue DAGCombiner::visit(SDNode *N) { 669 switch(N->getOpcode()) { 670 default: break; 671 case ISD::TokenFactor: return visitTokenFactor(N); 672 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 673 case ISD::ADD: return visitADD(N); 674 case ISD::SUB: return visitSUB(N); 675 case ISD::ADDC: return visitADDC(N); 676 case ISD::ADDE: return visitADDE(N); 677 case ISD::MUL: return visitMUL(N); 678 case ISD::SDIV: return visitSDIV(N); 679 case ISD::UDIV: return visitUDIV(N); 680 case ISD::SREM: return visitSREM(N); 681 case ISD::UREM: return visitUREM(N); 682 case ISD::MULHU: return visitMULHU(N); 683 case ISD::MULHS: return visitMULHS(N); 684 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 685 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 686 case ISD::SDIVREM: return visitSDIVREM(N); 687 case ISD::UDIVREM: return visitUDIVREM(N); 688 case ISD::AND: return visitAND(N); 689 case ISD::OR: return visitOR(N); 690 case ISD::XOR: return visitXOR(N); 691 case ISD::SHL: return visitSHL(N); 692 case ISD::SRA: return visitSRA(N); 693 case ISD::SRL: return visitSRL(N); 694 case ISD::CTLZ: return visitCTLZ(N); 695 case ISD::CTTZ: return visitCTTZ(N); 696 case ISD::CTPOP: return visitCTPOP(N); 697 case ISD::SELECT: return visitSELECT(N); 698 case ISD::SELECT_CC: return visitSELECT_CC(N); 699 case ISD::SETCC: return visitSETCC(N); 700 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 701 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 702 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 703 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 704 case ISD::TRUNCATE: return visitTRUNCATE(N); 705 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 706 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 707 case ISD::FADD: return visitFADD(N); 708 case ISD::FSUB: return visitFSUB(N); 709 case ISD::FMUL: return visitFMUL(N); 710 case ISD::FDIV: return visitFDIV(N); 711 case ISD::FREM: return visitFREM(N); 712 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 713 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 714 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 715 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 716 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 717 case ISD::FP_ROUND: return visitFP_ROUND(N); 718 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 719 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 720 case ISD::FNEG: return visitFNEG(N); 721 case ISD::FABS: return visitFABS(N); 722 case ISD::BRCOND: return visitBRCOND(N); 723 case ISD::BR_CC: return visitBR_CC(N); 724 case ISD::LOAD: return visitLOAD(N); 725 case ISD::STORE: return visitSTORE(N); 726 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 727 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 728 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 729 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 730 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 731 case ISD::ADDO: return visitADDO(N); 732 } 733 return SDValue(); 734} 735 736SDValue DAGCombiner::combine(SDNode *N) { 737 738 SDValue RV = visit(N); 739 740 // If nothing happened, try a target-specific DAG combine. 741 if (RV.getNode() == 0) { 742 assert(N->getOpcode() != ISD::DELETED_NODE && 743 "Node was deleted but visit returned NULL!"); 744 745 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 746 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 747 748 // Expose the DAG combiner to the target combiner impls. 749 TargetLowering::DAGCombinerInfo 750 DagCombineInfo(DAG, !AfterLegalize, false, this); 751 752 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 753 } 754 } 755 756 // If N is a commutative binary node, try commuting it to enable more 757 // sdisel CSE. 758 if (RV.getNode() == 0 && 759 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 760 N->getNumValues() == 1) { 761 SDValue N0 = N->getOperand(0); 762 SDValue N1 = N->getOperand(1); 763 // Constant operands are canonicalized to RHS. 764 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 765 SDValue Ops[] = { N1, N0 }; 766 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 767 Ops, 2); 768 if (CSENode) 769 return SDValue(CSENode, 0); 770 } 771 } 772 773 return RV; 774} 775 776/// getInputChainForNode - Given a node, return its input chain if it has one, 777/// otherwise return a null sd operand. 778static SDValue getInputChainForNode(SDNode *N) { 779 if (unsigned NumOps = N->getNumOperands()) { 780 if (N->getOperand(0).getValueType() == MVT::Other) 781 return N->getOperand(0); 782 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 783 return N->getOperand(NumOps-1); 784 for (unsigned i = 1; i < NumOps-1; ++i) 785 if (N->getOperand(i).getValueType() == MVT::Other) 786 return N->getOperand(i); 787 } 788 return SDValue(0, 0); 789} 790 791SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 792 // If N has two operands, where one has an input chain equal to the other, 793 // the 'other' chain is redundant. 794 if (N->getNumOperands() == 2) { 795 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 796 return N->getOperand(0); 797 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 798 return N->getOperand(1); 799 } 800 801 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 802 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 803 SmallPtrSet<SDNode*, 16> SeenOps; 804 bool Changed = false; // If we should replace this token factor. 805 806 // Start out with this token factor. 807 TFs.push_back(N); 808 809 // Iterate through token factors. The TFs grows when new token factors are 810 // encountered. 811 for (unsigned i = 0; i < TFs.size(); ++i) { 812 SDNode *TF = TFs[i]; 813 814 // Check each of the operands. 815 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 816 SDValue Op = TF->getOperand(i); 817 818 switch (Op.getOpcode()) { 819 case ISD::EntryToken: 820 // Entry tokens don't need to be added to the list. They are 821 // rededundant. 822 Changed = true; 823 break; 824 825 case ISD::TokenFactor: 826 if ((CombinerAA || Op.hasOneUse()) && 827 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 828 // Queue up for processing. 829 TFs.push_back(Op.getNode()); 830 // Clean up in case the token factor is removed. 831 AddToWorkList(Op.getNode()); 832 Changed = true; 833 break; 834 } 835 // Fall thru 836 837 default: 838 // Only add if it isn't already in the list. 839 if (SeenOps.insert(Op.getNode())) 840 Ops.push_back(Op); 841 else 842 Changed = true; 843 break; 844 } 845 } 846 } 847 848 SDValue Result; 849 850 // If we've change things around then replace token factor. 851 if (Changed) { 852 if (Ops.empty()) { 853 // The entry token is the only possible outcome. 854 Result = DAG.getEntryNode(); 855 } else { 856 // New and improved token factor. 857 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 858 } 859 860 // Don't add users to work list. 861 return CombineTo(N, Result, false); 862 } 863 864 return Result; 865} 866 867/// MERGE_VALUES can always be eliminated. 868SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 869 WorkListRemover DeadNodes(*this); 870 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 871 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 872 &DeadNodes); 873 removeFromWorkList(N); 874 DAG.DeleteNode(N); 875 return SDValue(N, 0); // Return N so it doesn't get rechecked! 876} 877 878 879static 880SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) { 881 MVT VT = N0.getValueType(); 882 SDValue N00 = N0.getOperand(0); 883 SDValue N01 = N0.getOperand(1); 884 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 885 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 886 isa<ConstantSDNode>(N00.getOperand(1))) { 887 N0 = DAG.getNode(ISD::ADD, VT, 888 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 889 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 890 return DAG.getNode(ISD::ADD, VT, N0, N1); 891 } 892 return SDValue(); 893} 894 895static 896SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 897 SelectionDAG &DAG, const TargetLowering &TLI, 898 bool AfterLegalize) { 899 MVT VT = N->getValueType(0); 900 unsigned Opc = N->getOpcode(); 901 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 902 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 903 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 904 ISD::CondCode CC = ISD::SETCC_INVALID; 905 906 if (isSlctCC) { 907 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 908 } else { 909 SDValue CCOp = Slct.getOperand(0); 910 if (CCOp.getOpcode() == ISD::SETCC) 911 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 912 } 913 914 bool DoXform = false; 915 bool InvCC = false; 916 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 917 "Bad input!"); 918 919 if (LHS.getOpcode() == ISD::Constant && 920 cast<ConstantSDNode>(LHS)->isNullValue()) { 921 DoXform = true; 922 } else if (CC != ISD::SETCC_INVALID && 923 RHS.getOpcode() == ISD::Constant && 924 cast<ConstantSDNode>(RHS)->isNullValue()) { 925 std::swap(LHS, RHS); 926 SDValue Op0 = Slct.getOperand(0); 927 MVT OpVT = isSlctCC ? Op0.getValueType() : 928 Op0.getOperand(0).getValueType(); 929 bool isInt = OpVT.isInteger(); 930 CC = ISD::getSetCCInverse(CC, isInt); 931 932 if (AfterLegalize && !TLI.isCondCodeLegal(CC, OpVT)) 933 return SDValue(); // Inverse operator isn't legal. 934 935 DoXform = true; 936 InvCC = true; 937 } 938 939 if (DoXform) { 940 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS); 941 if (isSlctCC) 942 return DAG.getSelectCC(OtherOp, Result, 943 Slct.getOperand(0), Slct.getOperand(1), CC); 944 SDValue CCOp = Slct.getOperand(0); 945 if (InvCC) 946 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 947 CCOp.getOperand(1), CC); 948 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 949 } 950 return SDValue(); 951} 952 953SDValue DAGCombiner::visitADD(SDNode *N) { 954 SDValue N0 = N->getOperand(0); 955 SDValue N1 = N->getOperand(1); 956 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 957 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 958 MVT VT = N0.getValueType(); 959 960 // fold vector ops 961 if (VT.isVector()) { 962 SDValue FoldedVOp = SimplifyVBinOp(N); 963 if (FoldedVOp.getNode()) return FoldedVOp; 964 } 965 966 // fold (add x, undef) -> undef 967 if (N0.getOpcode() == ISD::UNDEF) 968 return N0; 969 if (N1.getOpcode() == ISD::UNDEF) 970 return N1; 971 // fold (add c1, c2) -> c1+c2 972 if (N0C && N1C) 973 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 974 // canonicalize constant to RHS 975 if (N0C && !N1C) 976 return DAG.getNode(ISD::ADD, VT, N1, N0); 977 // fold (add x, 0) -> x 978 if (N1C && N1C->isNullValue()) 979 return N0; 980 // fold (add Sym, c) -> Sym+c 981 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 982 if (!AfterLegalize && TLI.isOffsetFoldingLegal(GA) && N1C && 983 GA->getOpcode() == ISD::GlobalAddress) 984 return DAG.getGlobalAddress(GA->getGlobal(), VT, 985 GA->getOffset() + 986 (uint64_t)N1C->getSExtValue()); 987 // fold ((c1-A)+c2) -> (c1+c2)-A 988 if (N1C && N0.getOpcode() == ISD::SUB) 989 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 990 return DAG.getNode(ISD::SUB, VT, 991 DAG.getConstant(N1C->getAPIntValue()+ 992 N0C->getAPIntValue(), VT), 993 N0.getOperand(1)); 994 // reassociate add 995 SDValue RADD = ReassociateOps(ISD::ADD, N0, N1); 996 if (RADD.getNode() != 0) 997 return RADD; 998 // fold ((0-A) + B) -> B-A 999 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1000 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1001 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 1002 // fold (A + (0-B)) -> A-B 1003 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1004 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1005 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 1006 // fold (A+(B-A)) -> B 1007 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1008 return N1.getOperand(0); 1009 1010 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1011 return SDValue(N, 0); 1012 1013 // fold (a+b) -> (a|b) iff a and b share no bits. 1014 if (VT.isInteger() && !VT.isVector()) { 1015 APInt LHSZero, LHSOne; 1016 APInt RHSZero, RHSOne; 1017 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1018 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1019 if (LHSZero.getBoolValue()) { 1020 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1021 1022 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1023 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1024 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1025 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1026 return DAG.getNode(ISD::OR, VT, N0, N1); 1027 } 1028 } 1029 1030 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1031 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1032 SDValue Result = combineShlAddConstant(N0, N1, DAG); 1033 if (Result.getNode()) return Result; 1034 } 1035 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1036 SDValue Result = combineShlAddConstant(N1, N0, DAG); 1037 if (Result.getNode()) return Result; 1038 } 1039 1040 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1041 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1042 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, AfterLegalize); 1043 if (Result.getNode()) return Result; 1044 } 1045 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1046 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, AfterLegalize); 1047 if (Result.getNode()) return Result; 1048 } 1049 1050 return SDValue(); 1051} 1052 1053SDValue DAGCombiner::visitADDC(SDNode *N) { 1054 SDValue N0 = N->getOperand(0); 1055 SDValue N1 = N->getOperand(1); 1056 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1057 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1058 MVT VT = N0.getValueType(); 1059 1060 // If the flag result is dead, turn this into an ADD. 1061 if (N->hasNUsesOfValue(0, 1)) 1062 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1063 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1064 1065 // canonicalize constant to RHS. 1066 if (N0C && !N1C) 1067 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1068 1069 // fold (addc x, 0) -> x + no carry out 1070 if (N1C && N1C->isNullValue()) 1071 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1072 1073 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1074 APInt LHSZero, LHSOne; 1075 APInt RHSZero, RHSOne; 1076 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1077 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1078 if (LHSZero.getBoolValue()) { 1079 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1080 1081 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1082 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1083 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1084 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1085 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1086 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1087 } 1088 1089 return SDValue(); 1090} 1091 1092SDValue DAGCombiner::visitADDE(SDNode *N) { 1093 SDValue N0 = N->getOperand(0); 1094 SDValue N1 = N->getOperand(1); 1095 SDValue CarryIn = N->getOperand(2); 1096 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1097 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1098 //MVT VT = N0.getValueType(); 1099 1100 // canonicalize constant to RHS 1101 if (N0C && !N1C) 1102 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1103 1104 // fold (adde x, y, false) -> (addc x, y) 1105 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1106 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1107 1108 return SDValue(); 1109} 1110 1111 1112 1113SDValue DAGCombiner::visitSUB(SDNode *N) { 1114 SDValue N0 = N->getOperand(0); 1115 SDValue N1 = N->getOperand(1); 1116 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1117 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1118 MVT VT = N0.getValueType(); 1119 1120 // fold vector ops 1121 if (VT.isVector()) { 1122 SDValue FoldedVOp = SimplifyVBinOp(N); 1123 if (FoldedVOp.getNode()) return FoldedVOp; 1124 } 1125 1126 // fold (sub x, x) -> 0 1127 if (N0 == N1) 1128 return DAG.getConstant(0, N->getValueType(0)); 1129 // fold (sub c1, c2) -> c1-c2 1130 if (N0C && N1C) 1131 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1132 // fold (sub x, c) -> (add x, -c) 1133 if (N1C) 1134 return DAG.getNode(ISD::ADD, VT, N0, 1135 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1136 // fold (A+B)-A -> B 1137 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1138 return N0.getOperand(1); 1139 // fold (A+B)-B -> A 1140 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1141 return N0.getOperand(0); 1142 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1143 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1144 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, AfterLegalize); 1145 if (Result.getNode()) return Result; 1146 } 1147 // If either operand of a sub is undef, the result is undef 1148 if (N0.getOpcode() == ISD::UNDEF) 1149 return N0; 1150 if (N1.getOpcode() == ISD::UNDEF) 1151 return N1; 1152 1153 // If the relocation model supports it, consider symbol offsets. 1154 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1155 if (!AfterLegalize && TLI.isOffsetFoldingLegal(GA)) { 1156 // fold (sub Sym, c) -> Sym-c 1157 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1158 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1159 GA->getOffset() - 1160 (uint64_t)N1C->getSExtValue()); 1161 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1162 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1163 if (GA->getGlobal() == GB->getGlobal()) 1164 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1165 VT); 1166 } 1167 1168 return SDValue(); 1169} 1170 1171SDValue DAGCombiner::visitMUL(SDNode *N) { 1172 SDValue N0 = N->getOperand(0); 1173 SDValue N1 = N->getOperand(1); 1174 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1175 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1176 MVT VT = N0.getValueType(); 1177 1178 // fold vector ops 1179 if (VT.isVector()) { 1180 SDValue FoldedVOp = SimplifyVBinOp(N); 1181 if (FoldedVOp.getNode()) return FoldedVOp; 1182 } 1183 1184 // fold (mul x, undef) -> 0 1185 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1186 return DAG.getConstant(0, VT); 1187 // fold (mul c1, c2) -> c1*c2 1188 if (N0C && N1C) 1189 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1190 // canonicalize constant to RHS 1191 if (N0C && !N1C) 1192 return DAG.getNode(ISD::MUL, VT, N1, N0); 1193 // fold (mul x, 0) -> 0 1194 if (N1C && N1C->isNullValue()) 1195 return N1; 1196 // fold (mul x, -1) -> 0-x 1197 if (N1C && N1C->isAllOnesValue()) 1198 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1199 // fold (mul x, (1 << c)) -> x << c 1200 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1201 return DAG.getNode(ISD::SHL, VT, N0, 1202 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1203 TLI.getShiftAmountTy())); 1204 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1205 if (N1C && isPowerOf2_64(-N1C->getSExtValue())) { 1206 // FIXME: If the input is something that is easily negated (e.g. a 1207 // single-use add), we should put the negate there. 1208 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1209 DAG.getNode(ISD::SHL, VT, N0, 1210 DAG.getConstant(Log2_64(-N1C->getSExtValue()), 1211 TLI.getShiftAmountTy()))); 1212 } 1213 1214 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1215 if (N1C && N0.getOpcode() == ISD::SHL && 1216 isa<ConstantSDNode>(N0.getOperand(1))) { 1217 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1218 AddToWorkList(C3.getNode()); 1219 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1220 } 1221 1222 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1223 // use. 1224 { 1225 SDValue Sh(0,0), Y(0,0); 1226 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1227 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1228 N0.getNode()->hasOneUse()) { 1229 Sh = N0; Y = N1; 1230 } else if (N1.getOpcode() == ISD::SHL && 1231 isa<ConstantSDNode>(N1.getOperand(1)) && 1232 N1.getNode()->hasOneUse()) { 1233 Sh = N1; Y = N0; 1234 } 1235 if (Sh.getNode()) { 1236 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1237 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1238 } 1239 } 1240 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1241 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1242 isa<ConstantSDNode>(N0.getOperand(1))) { 1243 return DAG.getNode(ISD::ADD, VT, 1244 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1245 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1246 } 1247 1248 // reassociate mul 1249 SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1); 1250 if (RMUL.getNode() != 0) 1251 return RMUL; 1252 1253 return SDValue(); 1254} 1255 1256SDValue DAGCombiner::visitSDIV(SDNode *N) { 1257 SDValue N0 = N->getOperand(0); 1258 SDValue N1 = N->getOperand(1); 1259 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1260 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1261 MVT VT = N->getValueType(0); 1262 1263 // fold vector ops 1264 if (VT.isVector()) { 1265 SDValue FoldedVOp = SimplifyVBinOp(N); 1266 if (FoldedVOp.getNode()) return FoldedVOp; 1267 } 1268 1269 // fold (sdiv c1, c2) -> c1/c2 1270 if (N0C && N1C && !N1C->isNullValue()) 1271 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1272 // fold (sdiv X, 1) -> X 1273 if (N1C && N1C->getSExtValue() == 1LL) 1274 return N0; 1275 // fold (sdiv X, -1) -> 0-X 1276 if (N1C && N1C->isAllOnesValue()) 1277 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1278 // If we know the sign bits of both operands are zero, strength reduce to a 1279 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1280 if (!VT.isVector()) { 1281 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1282 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1283 } 1284 // fold (sdiv X, pow2) -> simple ops after legalize 1285 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1286 (isPowerOf2_64(N1C->getSExtValue()) || 1287 isPowerOf2_64(-N1C->getSExtValue()))) { 1288 // If dividing by powers of two is cheap, then don't perform the following 1289 // fold. 1290 if (TLI.isPow2DivCheap()) 1291 return SDValue(); 1292 int64_t pow2 = N1C->getSExtValue(); 1293 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1294 unsigned lg2 = Log2_64(abs2); 1295 // Splat the sign bit into the register 1296 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1297 DAG.getConstant(VT.getSizeInBits()-1, 1298 TLI.getShiftAmountTy())); 1299 AddToWorkList(SGN.getNode()); 1300 // Add (N0 < 0) ? abs2 - 1 : 0; 1301 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1302 DAG.getConstant(VT.getSizeInBits()-lg2, 1303 TLI.getShiftAmountTy())); 1304 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1305 AddToWorkList(SRL.getNode()); 1306 AddToWorkList(ADD.getNode()); // Divide by pow2 1307 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1308 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1309 // If we're dividing by a positive value, we're done. Otherwise, we must 1310 // negate the result. 1311 if (pow2 > 0) 1312 return SRA; 1313 AddToWorkList(SRA.getNode()); 1314 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1315 } 1316 // if integer divide is expensive and we satisfy the requirements, emit an 1317 // alternate sequence. 1318 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1319 !TLI.isIntDivCheap()) { 1320 SDValue Op = BuildSDIV(N); 1321 if (Op.getNode()) return Op; 1322 } 1323 1324 // undef / X -> 0 1325 if (N0.getOpcode() == ISD::UNDEF) 1326 return DAG.getConstant(0, VT); 1327 // X / undef -> undef 1328 if (N1.getOpcode() == ISD::UNDEF) 1329 return N1; 1330 1331 return SDValue(); 1332} 1333 1334SDValue DAGCombiner::visitUDIV(SDNode *N) { 1335 SDValue N0 = N->getOperand(0); 1336 SDValue N1 = N->getOperand(1); 1337 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1338 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1339 MVT VT = N->getValueType(0); 1340 1341 // fold vector ops 1342 if (VT.isVector()) { 1343 SDValue FoldedVOp = SimplifyVBinOp(N); 1344 if (FoldedVOp.getNode()) return FoldedVOp; 1345 } 1346 1347 // fold (udiv c1, c2) -> c1/c2 1348 if (N0C && N1C && !N1C->isNullValue()) 1349 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1350 // fold (udiv x, (1 << c)) -> x >>u c 1351 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1352 return DAG.getNode(ISD::SRL, VT, N0, 1353 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1354 TLI.getShiftAmountTy())); 1355 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1356 if (N1.getOpcode() == ISD::SHL) { 1357 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1358 if (SHC->getAPIntValue().isPowerOf2()) { 1359 MVT ADDVT = N1.getOperand(1).getValueType(); 1360 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1361 DAG.getConstant(SHC->getAPIntValue() 1362 .logBase2(), 1363 ADDVT)); 1364 AddToWorkList(Add.getNode()); 1365 return DAG.getNode(ISD::SRL, VT, N0, Add); 1366 } 1367 } 1368 } 1369 // fold (udiv x, c) -> alternate 1370 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1371 SDValue Op = BuildUDIV(N); 1372 if (Op.getNode()) return Op; 1373 } 1374 1375 // undef / X -> 0 1376 if (N0.getOpcode() == ISD::UNDEF) 1377 return DAG.getConstant(0, VT); 1378 // X / undef -> undef 1379 if (N1.getOpcode() == ISD::UNDEF) 1380 return N1; 1381 1382 return SDValue(); 1383} 1384 1385SDValue DAGCombiner::visitSREM(SDNode *N) { 1386 SDValue N0 = N->getOperand(0); 1387 SDValue N1 = N->getOperand(1); 1388 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1389 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1390 MVT VT = N->getValueType(0); 1391 1392 // fold (srem c1, c2) -> c1%c2 1393 if (N0C && N1C && !N1C->isNullValue()) 1394 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1395 // If we know the sign bits of both operands are zero, strength reduce to a 1396 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1397 if (!VT.isVector()) { 1398 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1399 return DAG.getNode(ISD::UREM, VT, N0, N1); 1400 } 1401 1402 // If X/C can be simplified by the division-by-constant logic, lower 1403 // X%C to the equivalent of X-X/C*C. 1404 if (N1C && !N1C->isNullValue()) { 1405 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1406 AddToWorkList(Div.getNode()); 1407 SDValue OptimizedDiv = combine(Div.getNode()); 1408 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1409 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1410 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1411 AddToWorkList(Mul.getNode()); 1412 return Sub; 1413 } 1414 } 1415 1416 // undef % X -> 0 1417 if (N0.getOpcode() == ISD::UNDEF) 1418 return DAG.getConstant(0, VT); 1419 // X % undef -> undef 1420 if (N1.getOpcode() == ISD::UNDEF) 1421 return N1; 1422 1423 return SDValue(); 1424} 1425 1426SDValue DAGCombiner::visitUREM(SDNode *N) { 1427 SDValue N0 = N->getOperand(0); 1428 SDValue N1 = N->getOperand(1); 1429 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1430 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1431 MVT VT = N->getValueType(0); 1432 1433 // fold (urem c1, c2) -> c1%c2 1434 if (N0C && N1C && !N1C->isNullValue()) 1435 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1436 // fold (urem x, pow2) -> (and x, pow2-1) 1437 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1438 return DAG.getNode(ISD::AND, VT, N0, 1439 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1440 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1441 if (N1.getOpcode() == ISD::SHL) { 1442 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1443 if (SHC->getAPIntValue().isPowerOf2()) { 1444 SDValue Add = 1445 DAG.getNode(ISD::ADD, VT, N1, 1446 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1447 VT)); 1448 AddToWorkList(Add.getNode()); 1449 return DAG.getNode(ISD::AND, VT, N0, Add); 1450 } 1451 } 1452 } 1453 1454 // If X/C can be simplified by the division-by-constant logic, lower 1455 // X%C to the equivalent of X-X/C*C. 1456 if (N1C && !N1C->isNullValue()) { 1457 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1458 AddToWorkList(Div.getNode()); 1459 SDValue OptimizedDiv = combine(Div.getNode()); 1460 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1461 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1462 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1463 AddToWorkList(Mul.getNode()); 1464 return Sub; 1465 } 1466 } 1467 1468 // undef % X -> 0 1469 if (N0.getOpcode() == ISD::UNDEF) 1470 return DAG.getConstant(0, VT); 1471 // X % undef -> undef 1472 if (N1.getOpcode() == ISD::UNDEF) 1473 return N1; 1474 1475 return SDValue(); 1476} 1477 1478SDValue DAGCombiner::visitMULHS(SDNode *N) { 1479 SDValue N0 = N->getOperand(0); 1480 SDValue N1 = N->getOperand(1); 1481 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1482 MVT VT = N->getValueType(0); 1483 1484 // fold (mulhs x, 0) -> 0 1485 if (N1C && N1C->isNullValue()) 1486 return N1; 1487 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1488 if (N1C && N1C->getAPIntValue() == 1) 1489 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1490 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1491 TLI.getShiftAmountTy())); 1492 // fold (mulhs x, undef) -> 0 1493 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1494 return DAG.getConstant(0, VT); 1495 1496 return SDValue(); 1497} 1498 1499SDValue DAGCombiner::visitMULHU(SDNode *N) { 1500 SDValue N0 = N->getOperand(0); 1501 SDValue N1 = N->getOperand(1); 1502 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1503 MVT VT = N->getValueType(0); 1504 1505 // fold (mulhu x, 0) -> 0 1506 if (N1C && N1C->isNullValue()) 1507 return N1; 1508 // fold (mulhu x, 1) -> 0 1509 if (N1C && N1C->getAPIntValue() == 1) 1510 return DAG.getConstant(0, N0.getValueType()); 1511 // fold (mulhu x, undef) -> 0 1512 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1513 return DAG.getConstant(0, VT); 1514 1515 return SDValue(); 1516} 1517 1518/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1519/// compute two values. LoOp and HiOp give the opcodes for the two computations 1520/// that are being performed. Return true if a simplification was made. 1521/// 1522SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1523 unsigned HiOp) { 1524 // If the high half is not needed, just compute the low half. 1525 bool HiExists = N->hasAnyUseOfValue(1); 1526 if (!HiExists && 1527 (!AfterLegalize || 1528 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1529 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1530 N->getNumOperands()); 1531 return CombineTo(N, Res, Res); 1532 } 1533 1534 // If the low half is not needed, just compute the high half. 1535 bool LoExists = N->hasAnyUseOfValue(0); 1536 if (!LoExists && 1537 (!AfterLegalize || 1538 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1539 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1540 N->getNumOperands()); 1541 return CombineTo(N, Res, Res); 1542 } 1543 1544 // If both halves are used, return as it is. 1545 if (LoExists && HiExists) 1546 return SDValue(); 1547 1548 // If the two computed results can be simplified separately, separate them. 1549 if (LoExists) { 1550 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1551 N->op_begin(), N->getNumOperands()); 1552 AddToWorkList(Lo.getNode()); 1553 SDValue LoOpt = combine(Lo.getNode()); 1554 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1555 (!AfterLegalize || 1556 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1557 return CombineTo(N, LoOpt, LoOpt); 1558 } 1559 1560 if (HiExists) { 1561 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1562 N->op_begin(), N->getNumOperands()); 1563 AddToWorkList(Hi.getNode()); 1564 SDValue HiOpt = combine(Hi.getNode()); 1565 if (HiOpt.getNode() && HiOpt != Hi && 1566 (!AfterLegalize || 1567 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1568 return CombineTo(N, HiOpt, HiOpt); 1569 } 1570 return SDValue(); 1571} 1572 1573SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1574 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1575 if (Res.getNode()) return Res; 1576 1577 return SDValue(); 1578} 1579 1580SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1581 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1582 if (Res.getNode()) return Res; 1583 1584 return SDValue(); 1585} 1586 1587SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1588 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1589 if (Res.getNode()) return Res; 1590 1591 return SDValue(); 1592} 1593 1594SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1595 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1596 if (Res.getNode()) return Res; 1597 1598 return SDValue(); 1599} 1600 1601/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1602/// two operands of the same opcode, try to simplify it. 1603SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1604 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1605 MVT VT = N0.getValueType(); 1606 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1607 1608 // For each of OP in AND/OR/XOR: 1609 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1610 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1611 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1612 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1613 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1614 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1615 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1616 SDValue ORNode = DAG.getNode(N->getOpcode(), 1617 N0.getOperand(0).getValueType(), 1618 N0.getOperand(0), N1.getOperand(0)); 1619 AddToWorkList(ORNode.getNode()); 1620 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1621 } 1622 1623 // For each of OP in SHL/SRL/SRA/AND... 1624 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1625 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1626 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1627 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1628 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1629 N0.getOperand(1) == N1.getOperand(1)) { 1630 SDValue ORNode = DAG.getNode(N->getOpcode(), 1631 N0.getOperand(0).getValueType(), 1632 N0.getOperand(0), N1.getOperand(0)); 1633 AddToWorkList(ORNode.getNode()); 1634 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1635 } 1636 1637 return SDValue(); 1638} 1639 1640SDValue DAGCombiner::visitAND(SDNode *N) { 1641 SDValue N0 = N->getOperand(0); 1642 SDValue N1 = N->getOperand(1); 1643 SDValue LL, LR, RL, RR, CC0, CC1; 1644 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1645 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1646 MVT VT = N1.getValueType(); 1647 unsigned BitWidth = VT.getSizeInBits(); 1648 1649 // fold vector ops 1650 if (VT.isVector()) { 1651 SDValue FoldedVOp = SimplifyVBinOp(N); 1652 if (FoldedVOp.getNode()) return FoldedVOp; 1653 } 1654 1655 // fold (and x, undef) -> 0 1656 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1657 return DAG.getConstant(0, VT); 1658 // fold (and c1, c2) -> c1&c2 1659 if (N0C && N1C) 1660 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1661 // canonicalize constant to RHS 1662 if (N0C && !N1C) 1663 return DAG.getNode(ISD::AND, VT, N1, N0); 1664 // fold (and x, -1) -> x 1665 if (N1C && N1C->isAllOnesValue()) 1666 return N0; 1667 // if (and x, c) is known to be zero, return 0 1668 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1669 APInt::getAllOnesValue(BitWidth))) 1670 return DAG.getConstant(0, VT); 1671 // reassociate and 1672 SDValue RAND = ReassociateOps(ISD::AND, N0, N1); 1673 if (RAND.getNode() != 0) 1674 return RAND; 1675 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1676 if (N1C && N0.getOpcode() == ISD::OR) 1677 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1678 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1679 return N1; 1680 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1681 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1682 SDValue N0Op0 = N0.getOperand(0); 1683 APInt Mask = ~N1C->getAPIntValue(); 1684 Mask.trunc(N0Op0.getValueSizeInBits()); 1685 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1686 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1687 N0Op0); 1688 1689 // Replace uses of the AND with uses of the Zero extend node. 1690 CombineTo(N, Zext); 1691 1692 // We actually want to replace all uses of the any_extend with the 1693 // zero_extend, to avoid duplicating things. This will later cause this 1694 // AND to be folded. 1695 CombineTo(N0.getNode(), Zext); 1696 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1697 } 1698 } 1699 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1700 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1701 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1702 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1703 1704 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1705 LL.getValueType().isInteger()) { 1706 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1707 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1708 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1709 AddToWorkList(ORNode.getNode()); 1710 return DAG.getSetCC(VT, ORNode, LR, Op1); 1711 } 1712 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1713 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1714 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1715 AddToWorkList(ANDNode.getNode()); 1716 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1717 } 1718 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1719 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1720 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1721 AddToWorkList(ORNode.getNode()); 1722 return DAG.getSetCC(VT, ORNode, LR, Op1); 1723 } 1724 } 1725 // canonicalize equivalent to ll == rl 1726 if (LL == RR && LR == RL) { 1727 Op1 = ISD::getSetCCSwappedOperands(Op1); 1728 std::swap(RL, RR); 1729 } 1730 if (LL == RL && LR == RR) { 1731 bool isInteger = LL.getValueType().isInteger(); 1732 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1733 if (Result != ISD::SETCC_INVALID && 1734 (!AfterLegalize || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1735 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1736 } 1737 } 1738 1739 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1740 if (N0.getOpcode() == N1.getOpcode()) { 1741 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1742 if (Tmp.getNode()) return Tmp; 1743 } 1744 1745 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1746 // fold (and (sra)) -> (and (srl)) when possible. 1747 if (!VT.isVector() && 1748 SimplifyDemandedBits(SDValue(N, 0))) 1749 return SDValue(N, 0); 1750 // fold (zext_inreg (extload x)) -> (zextload x) 1751 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1752 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1753 MVT EVT = LN0->getMemoryVT(); 1754 // If we zero all the possible extended bits, then we can turn this into 1755 // a zextload if we are running before legalize or the operation is legal. 1756 unsigned BitWidth = N1.getValueSizeInBits(); 1757 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1758 BitWidth - EVT.getSizeInBits())) && 1759 ((!AfterLegalize && !LN0->isVolatile()) || 1760 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1761 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1762 LN0->getBasePtr(), LN0->getSrcValue(), 1763 LN0->getSrcValueOffset(), EVT, 1764 LN0->isVolatile(), 1765 LN0->getAlignment()); 1766 AddToWorkList(N); 1767 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1768 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1769 } 1770 } 1771 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1772 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1773 N0.hasOneUse()) { 1774 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1775 MVT EVT = LN0->getMemoryVT(); 1776 // If we zero all the possible extended bits, then we can turn this into 1777 // a zextload if we are running before legalize or the operation is legal. 1778 unsigned BitWidth = N1.getValueSizeInBits(); 1779 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1780 BitWidth - EVT.getSizeInBits())) && 1781 ((!AfterLegalize && !LN0->isVolatile()) || 1782 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1783 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1784 LN0->getBasePtr(), LN0->getSrcValue(), 1785 LN0->getSrcValueOffset(), EVT, 1786 LN0->isVolatile(), 1787 LN0->getAlignment()); 1788 AddToWorkList(N); 1789 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1790 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1791 } 1792 } 1793 1794 // fold (and (load x), 255) -> (zextload x, i8) 1795 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1796 if (N1C && N0.getOpcode() == ISD::LOAD) { 1797 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1798 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1799 LN0->isUnindexed() && N0.hasOneUse() && 1800 // Do not change the width of a volatile load. 1801 !LN0->isVolatile()) { 1802 MVT EVT = MVT::Other; 1803 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1804 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1805 EVT = MVT::getIntegerVT(ActiveBits); 1806 1807 MVT LoadedVT = LN0->getMemoryVT(); 1808 // Do not generate loads of non-round integer types since these can 1809 // be expensive (and would be wrong if the type is not byte sized). 1810 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1811 (!AfterLegalize || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1812 MVT PtrType = N0.getOperand(1).getValueType(); 1813 // For big endian targets, we need to add an offset to the pointer to 1814 // load the correct bytes. For little endian systems, we merely need to 1815 // read fewer bytes from the same pointer. 1816 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1817 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1818 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1819 unsigned Alignment = LN0->getAlignment(); 1820 SDValue NewPtr = LN0->getBasePtr(); 1821 if (TLI.isBigEndian()) { 1822 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1823 DAG.getConstant(PtrOff, PtrType)); 1824 Alignment = MinAlign(Alignment, PtrOff); 1825 } 1826 AddToWorkList(NewPtr.getNode()); 1827 SDValue Load = 1828 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1829 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1830 LN0->isVolatile(), Alignment); 1831 AddToWorkList(N); 1832 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1833 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1834 } 1835 } 1836 } 1837 1838 return SDValue(); 1839} 1840 1841SDValue DAGCombiner::visitOR(SDNode *N) { 1842 SDValue N0 = N->getOperand(0); 1843 SDValue N1 = N->getOperand(1); 1844 SDValue LL, LR, RL, RR, CC0, CC1; 1845 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1846 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1847 MVT VT = N1.getValueType(); 1848 1849 // fold vector ops 1850 if (VT.isVector()) { 1851 SDValue FoldedVOp = SimplifyVBinOp(N); 1852 if (FoldedVOp.getNode()) return FoldedVOp; 1853 } 1854 1855 // fold (or x, undef) -> -1 1856 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1857 return DAG.getConstant(~0ULL, VT); 1858 // fold (or c1, c2) -> c1|c2 1859 if (N0C && N1C) 1860 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1861 // canonicalize constant to RHS 1862 if (N0C && !N1C) 1863 return DAG.getNode(ISD::OR, VT, N1, N0); 1864 // fold (or x, 0) -> x 1865 if (N1C && N1C->isNullValue()) 1866 return N0; 1867 // fold (or x, -1) -> -1 1868 if (N1C && N1C->isAllOnesValue()) 1869 return N1; 1870 // fold (or x, c) -> c iff (x & ~c) == 0 1871 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1872 return N1; 1873 // reassociate or 1874 SDValue ROR = ReassociateOps(ISD::OR, N0, N1); 1875 if (ROR.getNode() != 0) 1876 return ROR; 1877 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1878 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1879 isa<ConstantSDNode>(N0.getOperand(1))) { 1880 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1881 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1882 N1), 1883 DAG.getConstant(N1C->getAPIntValue() | 1884 C1->getAPIntValue(), VT)); 1885 } 1886 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1887 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1888 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1889 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1890 1891 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1892 LL.getValueType().isInteger()) { 1893 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1894 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1895 if (cast<ConstantSDNode>(LR)->isNullValue() && 1896 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1897 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1898 AddToWorkList(ORNode.getNode()); 1899 return DAG.getSetCC(VT, ORNode, LR, Op1); 1900 } 1901 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1902 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1903 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1904 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1905 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1906 AddToWorkList(ANDNode.getNode()); 1907 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1908 } 1909 } 1910 // canonicalize equivalent to ll == rl 1911 if (LL == RR && LR == RL) { 1912 Op1 = ISD::getSetCCSwappedOperands(Op1); 1913 std::swap(RL, RR); 1914 } 1915 if (LL == RL && LR == RR) { 1916 bool isInteger = LL.getValueType().isInteger(); 1917 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1918 if (Result != ISD::SETCC_INVALID && 1919 (!AfterLegalize || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1920 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1921 } 1922 } 1923 1924 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1925 if (N0.getOpcode() == N1.getOpcode()) { 1926 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1927 if (Tmp.getNode()) return Tmp; 1928 } 1929 1930 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1931 if (N0.getOpcode() == ISD::AND && 1932 N1.getOpcode() == ISD::AND && 1933 N0.getOperand(1).getOpcode() == ISD::Constant && 1934 N1.getOperand(1).getOpcode() == ISD::Constant && 1935 // Don't increase # computations. 1936 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 1937 // We can only do this xform if we know that bits from X that are set in C2 1938 // but not in C1 are already zero. Likewise for Y. 1939 const APInt &LHSMask = 1940 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1941 const APInt &RHSMask = 1942 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1943 1944 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1945 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1946 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1947 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1948 } 1949 } 1950 1951 1952 // See if this is some rotate idiom. 1953 if (SDNode *Rot = MatchRotate(N0, N1)) 1954 return SDValue(Rot, 0); 1955 1956 return SDValue(); 1957} 1958 1959 1960/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1961static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 1962 if (Op.getOpcode() == ISD::AND) { 1963 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1964 Mask = Op.getOperand(1); 1965 Op = Op.getOperand(0); 1966 } else { 1967 return false; 1968 } 1969 } 1970 1971 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1972 Shift = Op; 1973 return true; 1974 } 1975 return false; 1976} 1977 1978 1979// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1980// idioms for rotate, and if the target supports rotation instructions, generate 1981// a rot[lr]. 1982SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 1983 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 1984 MVT VT = LHS.getValueType(); 1985 if (!TLI.isTypeLegal(VT)) return 0; 1986 1987 // The target must have at least one rotate flavor. 1988 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1989 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1990 if (!HasROTL && !HasROTR) return 0; 1991 1992 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1993 SDValue LHSShift; // The shift. 1994 SDValue LHSMask; // AND value if any. 1995 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1996 return 0; // Not part of a rotate. 1997 1998 SDValue RHSShift; // The shift. 1999 SDValue RHSMask; // AND value if any. 2000 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2001 return 0; // Not part of a rotate. 2002 2003 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2004 return 0; // Not shifting the same value. 2005 2006 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2007 return 0; // Shifts must disagree. 2008 2009 // Canonicalize shl to left side in a shl/srl pair. 2010 if (RHSShift.getOpcode() == ISD::SHL) { 2011 std::swap(LHS, RHS); 2012 std::swap(LHSShift, RHSShift); 2013 std::swap(LHSMask , RHSMask ); 2014 } 2015 2016 unsigned OpSizeInBits = VT.getSizeInBits(); 2017 SDValue LHSShiftArg = LHSShift.getOperand(0); 2018 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2019 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2020 2021 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2022 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2023 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2024 RHSShiftAmt.getOpcode() == ISD::Constant) { 2025 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2026 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2027 if ((LShVal + RShVal) != OpSizeInBits) 2028 return 0; 2029 2030 SDValue Rot; 2031 if (HasROTL) 2032 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2033 else 2034 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2035 2036 // If there is an AND of either shifted operand, apply it to the result. 2037 if (LHSMask.getNode() || RHSMask.getNode()) { 2038 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2039 2040 if (LHSMask.getNode()) { 2041 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2042 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2043 } 2044 if (RHSMask.getNode()) { 2045 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2046 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2047 } 2048 2049 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2050 } 2051 2052 return Rot.getNode(); 2053 } 2054 2055 // If there is a mask here, and we have a variable shift, we can't be sure 2056 // that we're masking out the right stuff. 2057 if (LHSMask.getNode() || RHSMask.getNode()) 2058 return 0; 2059 2060 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2061 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2062 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2063 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2064 if (ConstantSDNode *SUBC = 2065 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2066 if (SUBC->getAPIntValue() == OpSizeInBits) { 2067 if (HasROTL) 2068 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2069 else 2070 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2071 } 2072 } 2073 } 2074 2075 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2076 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2077 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2078 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2079 if (ConstantSDNode *SUBC = 2080 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2081 if (SUBC->getAPIntValue() == OpSizeInBits) { 2082 if (HasROTR) 2083 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2084 else 2085 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2086 } 2087 } 2088 } 2089 2090 // Look for sign/zext/any-extended or truncate cases: 2091 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2092 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2093 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2094 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2095 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2096 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2097 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2098 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2099 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2100 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2101 if (RExtOp0.getOpcode() == ISD::SUB && 2102 RExtOp0.getOperand(1) == LExtOp0) { 2103 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2104 // (rotl x, y) 2105 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2106 // (rotr x, (sub 32, y)) 2107 if (ConstantSDNode *SUBC = 2108 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2109 if (SUBC->getAPIntValue() == OpSizeInBits) { 2110 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, 2111 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2112 } 2113 } 2114 } else if (LExtOp0.getOpcode() == ISD::SUB && 2115 RExtOp0 == LExtOp0.getOperand(1)) { 2116 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2117 // (rotr x, y) 2118 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2119 // (rotl x, (sub 32, y)) 2120 if (ConstantSDNode *SUBC = 2121 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2122 if (SUBC->getAPIntValue() == OpSizeInBits) { 2123 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, 2124 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2125 } 2126 } 2127 } 2128 } 2129 2130 return 0; 2131} 2132 2133 2134SDValue DAGCombiner::visitXOR(SDNode *N) { 2135 SDValue N0 = N->getOperand(0); 2136 SDValue N1 = N->getOperand(1); 2137 SDValue LHS, RHS, CC; 2138 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2139 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2140 MVT VT = N0.getValueType(); 2141 2142 // fold vector ops 2143 if (VT.isVector()) { 2144 SDValue FoldedVOp = SimplifyVBinOp(N); 2145 if (FoldedVOp.getNode()) return FoldedVOp; 2146 } 2147 2148 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2149 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2150 return DAG.getConstant(0, VT); 2151 // fold (xor x, undef) -> undef 2152 if (N0.getOpcode() == ISD::UNDEF) 2153 return N0; 2154 if (N1.getOpcode() == ISD::UNDEF) 2155 return N1; 2156 // fold (xor c1, c2) -> c1^c2 2157 if (N0C && N1C) 2158 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2159 // canonicalize constant to RHS 2160 if (N0C && !N1C) 2161 return DAG.getNode(ISD::XOR, VT, N1, N0); 2162 // fold (xor x, 0) -> x 2163 if (N1C && N1C->isNullValue()) 2164 return N0; 2165 // reassociate xor 2166 SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1); 2167 if (RXOR.getNode() != 0) 2168 return RXOR; 2169 2170 // fold !(x cc y) -> (x !cc y) 2171 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2172 bool isInt = LHS.getValueType().isInteger(); 2173 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2174 isInt); 2175 2176 if (!AfterLegalize || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2177 switch (N0.getOpcode()) { 2178 default: 2179 assert(0 && "Unhandled SetCC Equivalent!"); 2180 abort(); 2181 case ISD::SETCC: 2182 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2183 case ISD::SELECT_CC: 2184 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2), 2185 N0.getOperand(3), NotCC); 2186 } 2187 } 2188 } 2189 2190 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2191 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2192 N0.getNode()->hasOneUse() && 2193 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2194 SDValue V = N0.getOperand(0); 2195 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2196 DAG.getConstant(1, V.getValueType())); 2197 AddToWorkList(V.getNode()); 2198 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2199 } 2200 2201 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2202 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2203 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2204 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2205 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2206 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2207 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2208 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2209 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2210 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2211 } 2212 } 2213 // fold !(x or y) -> (!x and !y) iff x or y are constants 2214 if (N1C && N1C->isAllOnesValue() && 2215 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2216 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2217 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2218 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2219 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2220 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2221 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2222 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2223 } 2224 } 2225 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2226 if (N1C && N0.getOpcode() == ISD::XOR) { 2227 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2228 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2229 if (N00C) 2230 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2231 DAG.getConstant(N1C->getAPIntValue()^ 2232 N00C->getAPIntValue(), VT)); 2233 if (N01C) 2234 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2235 DAG.getConstant(N1C->getAPIntValue()^ 2236 N01C->getAPIntValue(), VT)); 2237 } 2238 // fold (xor x, x) -> 0 2239 if (N0 == N1) { 2240 if (!VT.isVector()) { 2241 return DAG.getConstant(0, VT); 2242 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2243 // Produce a vector of zeros. 2244 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2245 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2246 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2247 } 2248 } 2249 2250 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2251 if (N0.getOpcode() == N1.getOpcode()) { 2252 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2253 if (Tmp.getNode()) return Tmp; 2254 } 2255 2256 // Simplify the expression using non-local knowledge. 2257 if (!VT.isVector() && 2258 SimplifyDemandedBits(SDValue(N, 0))) 2259 return SDValue(N, 0); 2260 2261 return SDValue(); 2262} 2263 2264/// visitShiftByConstant - Handle transforms common to the three shifts, when 2265/// the shift amount is a constant. 2266SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2267 SDNode *LHS = N->getOperand(0).getNode(); 2268 if (!LHS->hasOneUse()) return SDValue(); 2269 2270 // We want to pull some binops through shifts, so that we have (and (shift)) 2271 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2272 // thing happens with address calculations, so it's important to canonicalize 2273 // it. 2274 bool HighBitSet = false; // Can we transform this if the high bit is set? 2275 2276 switch (LHS->getOpcode()) { 2277 default: return SDValue(); 2278 case ISD::OR: 2279 case ISD::XOR: 2280 HighBitSet = false; // We can only transform sra if the high bit is clear. 2281 break; 2282 case ISD::AND: 2283 HighBitSet = true; // We can only transform sra if the high bit is set. 2284 break; 2285 case ISD::ADD: 2286 if (N->getOpcode() != ISD::SHL) 2287 return SDValue(); // only shl(add) not sr[al](add). 2288 HighBitSet = false; // We can only transform sra if the high bit is clear. 2289 break; 2290 } 2291 2292 // We require the RHS of the binop to be a constant as well. 2293 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2294 if (!BinOpCst) return SDValue(); 2295 2296 2297 // FIXME: disable this for unless the input to the binop is a shift by a 2298 // constant. If it is not a shift, it pessimizes some common cases like: 2299 // 2300 //void foo(int *X, int i) { X[i & 1235] = 1; } 2301 //int bar(int *X, int i) { return X[i & 255]; } 2302 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2303 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2304 BinOpLHSVal->getOpcode() != ISD::SRA && 2305 BinOpLHSVal->getOpcode() != ISD::SRL) || 2306 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2307 return SDValue(); 2308 2309 MVT VT = N->getValueType(0); 2310 2311 // If this is a signed shift right, and the high bit is modified 2312 // by the logical operation, do not perform the transformation. 2313 // The highBitSet boolean indicates the value of the high bit of 2314 // the constant which would cause it to be modified for this 2315 // operation. 2316 if (N->getOpcode() == ISD::SRA) { 2317 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2318 if (BinOpRHSSignSet != HighBitSet) 2319 return SDValue(); 2320 } 2321 2322 // Fold the constants, shifting the binop RHS by the shift amount. 2323 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2324 LHS->getOperand(1), N->getOperand(1)); 2325 2326 // Create the new shift. 2327 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2328 N->getOperand(1)); 2329 2330 // Create the new binop. 2331 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2332} 2333 2334 2335SDValue DAGCombiner::visitSHL(SDNode *N) { 2336 SDValue N0 = N->getOperand(0); 2337 SDValue N1 = N->getOperand(1); 2338 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2339 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2340 MVT VT = N0.getValueType(); 2341 unsigned OpSizeInBits = VT.getSizeInBits(); 2342 2343 // fold (shl c1, c2) -> c1<<c2 2344 if (N0C && N1C) 2345 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2346 // fold (shl 0, x) -> 0 2347 if (N0C && N0C->isNullValue()) 2348 return N0; 2349 // fold (shl x, c >= size(x)) -> undef 2350 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2351 return DAG.getNode(ISD::UNDEF, VT); 2352 // fold (shl x, 0) -> x 2353 if (N1C && N1C->isNullValue()) 2354 return N0; 2355 // if (shl x, c) is known to be zero, return 0 2356 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2357 APInt::getAllOnesValue(VT.getSizeInBits()))) 2358 return DAG.getConstant(0, VT); 2359 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2360 // iff (trunc c) == c 2361 if (N1.getOpcode() == ISD::TRUNCATE && 2362 N1.getOperand(0).getOpcode() == ISD::AND && 2363 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2364 SDValue N101 = N1.getOperand(0).getOperand(1); 2365 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2366 MVT TruncVT = N1.getValueType(); 2367 SDValue N100 = N1.getOperand(0).getOperand(0); 2368 return DAG.getNode(ISD::SHL, VT, N0, 2369 DAG.getNode(ISD::AND, TruncVT, 2370 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2371 DAG.getConstant(N101C->getZExtValue(), 2372 TruncVT))); 2373 } 2374 } 2375 2376 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2377 return SDValue(N, 0); 2378 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2379 if (N1C && N0.getOpcode() == ISD::SHL && 2380 N0.getOperand(1).getOpcode() == ISD::Constant) { 2381 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2382 uint64_t c2 = N1C->getZExtValue(); 2383 if (c1 + c2 > OpSizeInBits) 2384 return DAG.getConstant(0, VT); 2385 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2386 DAG.getConstant(c1 + c2, N1.getValueType())); 2387 } 2388 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2389 // (srl (and x, -1 << c1), c1-c2) 2390 if (N1C && N0.getOpcode() == ISD::SRL && 2391 N0.getOperand(1).getOpcode() == ISD::Constant) { 2392 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2393 uint64_t c2 = N1C->getZExtValue(); 2394 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2395 DAG.getConstant(~0ULL << c1, VT)); 2396 if (c2 > c1) 2397 return DAG.getNode(ISD::SHL, VT, Mask, 2398 DAG.getConstant(c2-c1, N1.getValueType())); 2399 else 2400 return DAG.getNode(ISD::SRL, VT, Mask, 2401 DAG.getConstant(c1-c2, N1.getValueType())); 2402 } 2403 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2404 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2405 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2406 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2407 2408 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2409} 2410 2411SDValue DAGCombiner::visitSRA(SDNode *N) { 2412 SDValue N0 = N->getOperand(0); 2413 SDValue N1 = N->getOperand(1); 2414 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2415 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2416 MVT VT = N0.getValueType(); 2417 2418 // fold (sra c1, c2) -> c1>>c2 2419 if (N0C && N1C) 2420 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2421 // fold (sra 0, x) -> 0 2422 if (N0C && N0C->isNullValue()) 2423 return N0; 2424 // fold (sra -1, x) -> -1 2425 if (N0C && N0C->isAllOnesValue()) 2426 return N0; 2427 // fold (sra x, c >= size(x)) -> undef 2428 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2429 return DAG.getNode(ISD::UNDEF, VT); 2430 // fold (sra x, 0) -> x 2431 if (N1C && N1C->isNullValue()) 2432 return N0; 2433 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2434 // sext_inreg. 2435 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2436 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2437 MVT EVT = MVT::getIntegerVT(LowBits); 2438 if (EVT.isSimple() && // TODO: remove when apint codegen support lands. 2439 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2440 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2441 DAG.getValueType(EVT)); 2442 } 2443 2444 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2445 if (N1C && N0.getOpcode() == ISD::SRA) { 2446 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2447 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2448 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2449 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2450 DAG.getConstant(Sum, N1C->getValueType(0))); 2451 } 2452 } 2453 2454 // fold sra (shl X, m), result_size - n 2455 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2456 // result_size - n != m. 2457 // If truncate is free for the target sext(shl) is likely to result in better 2458 // code. 2459 if (N0.getOpcode() == ISD::SHL) { 2460 // Get the two constanst of the shifts, CN0 = m, CN = n. 2461 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2462 if (N01C && N1C) { 2463 // Determine what the truncate's result bitsize and type would be. 2464 unsigned VTValSize = VT.getSizeInBits(); 2465 MVT TruncVT = 2466 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2467 // Determine the residual right-shift amount. 2468 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2469 2470 // If the shift is not a no-op (in which case this should be just a sign 2471 // extend already), the truncated to type is legal, sign_extend is legal 2472 // on that type, and the the truncate to that type is both legal and free, 2473 // perform the transform. 2474 if (ShiftAmt && 2475 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2476 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2477 TLI.isTruncateFree(VT, TruncVT)) { 2478 2479 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2480 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2481 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2482 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2483 } 2484 } 2485 } 2486 2487 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2488 // iff (trunc c) == c 2489 if (N1.getOpcode() == ISD::TRUNCATE && 2490 N1.getOperand(0).getOpcode() == ISD::AND && 2491 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2492 SDValue N101 = N1.getOperand(0).getOperand(1); 2493 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2494 MVT TruncVT = N1.getValueType(); 2495 SDValue N100 = N1.getOperand(0).getOperand(0); 2496 return DAG.getNode(ISD::SRA, VT, N0, 2497 DAG.getNode(ISD::AND, TruncVT, 2498 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2499 DAG.getConstant(N101C->getZExtValue(), 2500 TruncVT))); 2501 } 2502 } 2503 2504 // Simplify, based on bits shifted out of the LHS. 2505 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2506 return SDValue(N, 0); 2507 2508 2509 // If the sign bit is known to be zero, switch this to a SRL. 2510 if (DAG.SignBitIsZero(N0)) 2511 return DAG.getNode(ISD::SRL, VT, N0, N1); 2512 2513 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2514} 2515 2516SDValue DAGCombiner::visitSRL(SDNode *N) { 2517 SDValue N0 = N->getOperand(0); 2518 SDValue N1 = N->getOperand(1); 2519 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2521 MVT VT = N0.getValueType(); 2522 unsigned OpSizeInBits = VT.getSizeInBits(); 2523 2524 // fold (srl c1, c2) -> c1 >>u c2 2525 if (N0C && N1C) 2526 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2527 // fold (srl 0, x) -> 0 2528 if (N0C && N0C->isNullValue()) 2529 return N0; 2530 // fold (srl x, c >= size(x)) -> undef 2531 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2532 return DAG.getNode(ISD::UNDEF, VT); 2533 // fold (srl x, 0) -> x 2534 if (N1C && N1C->isNullValue()) 2535 return N0; 2536 // if (srl x, c) is known to be zero, return 0 2537 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2538 APInt::getAllOnesValue(OpSizeInBits))) 2539 return DAG.getConstant(0, VT); 2540 2541 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2542 if (N1C && N0.getOpcode() == ISD::SRL && 2543 N0.getOperand(1).getOpcode() == ISD::Constant) { 2544 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2545 uint64_t c2 = N1C->getZExtValue(); 2546 if (c1 + c2 > OpSizeInBits) 2547 return DAG.getConstant(0, VT); 2548 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2549 DAG.getConstant(c1 + c2, N1.getValueType())); 2550 } 2551 2552 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2553 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2554 // Shifting in all undef bits? 2555 MVT SmallVT = N0.getOperand(0).getValueType(); 2556 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2557 return DAG.getNode(ISD::UNDEF, VT); 2558 2559 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2560 AddToWorkList(SmallShift.getNode()); 2561 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2562 } 2563 2564 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2565 // bit, which is unmodified by sra. 2566 if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { 2567 if (N0.getOpcode() == ISD::SRA) 2568 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2569 } 2570 2571 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2572 if (N1C && N0.getOpcode() == ISD::CTLZ && 2573 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2574 APInt KnownZero, KnownOne; 2575 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2576 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2577 2578 // If any of the input bits are KnownOne, then the input couldn't be all 2579 // zeros, thus the result of the srl will always be zero. 2580 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2581 2582 // If all of the bits input the to ctlz node are known to be zero, then 2583 // the result of the ctlz is "32" and the result of the shift is one. 2584 APInt UnknownBits = ~KnownZero & Mask; 2585 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2586 2587 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2588 if ((UnknownBits & (UnknownBits-1)) == 0) { 2589 // Okay, we know that only that the single bit specified by UnknownBits 2590 // could be set on input to the CTLZ node. If this bit is set, the SRL 2591 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2592 // to an SRL,XOR pair, which is likely to simplify more. 2593 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2594 SDValue Op = N0.getOperand(0); 2595 if (ShAmt) { 2596 Op = DAG.getNode(ISD::SRL, VT, Op, 2597 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2598 AddToWorkList(Op.getNode()); 2599 } 2600 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2601 } 2602 } 2603 2604 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2605 // iff (trunc c) == c 2606 if (N1.getOpcode() == ISD::TRUNCATE && 2607 N1.getOperand(0).getOpcode() == ISD::AND && 2608 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2609 SDValue N101 = N1.getOperand(0).getOperand(1); 2610 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2611 MVT TruncVT = N1.getValueType(); 2612 SDValue N100 = N1.getOperand(0).getOperand(0); 2613 return DAG.getNode(ISD::SRL, VT, N0, 2614 DAG.getNode(ISD::AND, TruncVT, 2615 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2616 DAG.getConstant(N101C->getZExtValue(), 2617 TruncVT))); 2618 } 2619 } 2620 2621 // fold operands of srl based on knowledge that the low bits are not 2622 // demanded. 2623 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2624 return SDValue(N, 0); 2625 2626 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2627} 2628 2629SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2630 SDValue N0 = N->getOperand(0); 2631 MVT VT = N->getValueType(0); 2632 2633 // fold (ctlz c1) -> c2 2634 if (isa<ConstantSDNode>(N0)) 2635 return DAG.getNode(ISD::CTLZ, VT, N0); 2636 return SDValue(); 2637} 2638 2639SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2640 SDValue N0 = N->getOperand(0); 2641 MVT VT = N->getValueType(0); 2642 2643 // fold (cttz c1) -> c2 2644 if (isa<ConstantSDNode>(N0)) 2645 return DAG.getNode(ISD::CTTZ, VT, N0); 2646 return SDValue(); 2647} 2648 2649SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2650 SDValue N0 = N->getOperand(0); 2651 MVT VT = N->getValueType(0); 2652 2653 // fold (ctpop c1) -> c2 2654 if (isa<ConstantSDNode>(N0)) 2655 return DAG.getNode(ISD::CTPOP, VT, N0); 2656 return SDValue(); 2657} 2658 2659SDValue DAGCombiner::visitSELECT(SDNode *N) { 2660 SDValue N0 = N->getOperand(0); 2661 SDValue N1 = N->getOperand(1); 2662 SDValue N2 = N->getOperand(2); 2663 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2664 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2665 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2666 MVT VT = N->getValueType(0); 2667 MVT VT0 = N0.getValueType(); 2668 2669 // fold select C, X, X -> X 2670 if (N1 == N2) 2671 return N1; 2672 // fold select true, X, Y -> X 2673 if (N0C && !N0C->isNullValue()) 2674 return N1; 2675 // fold select false, X, Y -> Y 2676 if (N0C && N0C->isNullValue()) 2677 return N2; 2678 // fold select C, 1, X -> C | X 2679 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2680 return DAG.getNode(ISD::OR, VT, N0, N2); 2681 // fold select C, 0, 1 -> ~C 2682 if (VT.isInteger() && VT0.isInteger() && 2683 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2684 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2685 if (VT == VT0) 2686 return XORNode; 2687 AddToWorkList(XORNode.getNode()); 2688 if (VT.bitsGT(VT0)) 2689 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2690 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2691 } 2692 // fold select C, 0, X -> ~C & X 2693 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2694 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2695 AddToWorkList(XORNode.getNode()); 2696 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2697 } 2698 // fold select C, X, 1 -> ~C | X 2699 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2700 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2701 AddToWorkList(XORNode.getNode()); 2702 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2703 } 2704 // fold select C, X, 0 -> C & X 2705 // FIXME: this should check for C type == X type, not i1? 2706 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2707 return DAG.getNode(ISD::AND, VT, N0, N1); 2708 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2709 if (VT == MVT::i1 && N0 == N1) 2710 return DAG.getNode(ISD::OR, VT, N0, N2); 2711 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2712 if (VT == MVT::i1 && N0 == N2) 2713 return DAG.getNode(ISD::AND, VT, N0, N1); 2714 2715 // If we can fold this based on the true/false value, do so. 2716 if (SimplifySelectOps(N, N1, N2)) 2717 return SDValue(N, 0); // Don't revisit N. 2718 2719 // fold selects based on a setcc into other things, such as min/max/abs 2720 if (N0.getOpcode() == ISD::SETCC) { 2721 // FIXME: 2722 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2723 // having to say they don't support SELECT_CC on every type the DAG knows 2724 // about, since there is no way to mark an opcode illegal at all value types 2725 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2726 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2727 N1, N2, N0.getOperand(2)); 2728 else 2729 return SimplifySelect(N0, N1, N2); 2730 } 2731 return SDValue(); 2732} 2733 2734SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2735 SDValue N0 = N->getOperand(0); 2736 SDValue N1 = N->getOperand(1); 2737 SDValue N2 = N->getOperand(2); 2738 SDValue N3 = N->getOperand(3); 2739 SDValue N4 = N->getOperand(4); 2740 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2741 2742 // fold select_cc lhs, rhs, x, x, cc -> x 2743 if (N2 == N3) 2744 return N2; 2745 2746 // Determine if the condition we're dealing with is constant 2747 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2748 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2749 2750 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2751 if (!SCCC->isNullValue()) 2752 return N2; // cond always true -> true val 2753 else 2754 return N3; // cond always false -> false val 2755 } 2756 2757 // Fold to a simpler select_cc 2758 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2759 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2760 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2761 SCC.getOperand(2)); 2762 2763 // If we can fold this based on the true/false value, do so. 2764 if (SimplifySelectOps(N, N2, N3)) 2765 return SDValue(N, 0); // Don't revisit N. 2766 2767 // fold select_cc into other things, such as min/max/abs 2768 return SimplifySelectCC(N0, N1, N2, N3, CC); 2769} 2770 2771SDValue DAGCombiner::visitSETCC(SDNode *N) { 2772 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2773 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2774} 2775 2776// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2777// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2778// transformation. Returns true if extension are possible and the above 2779// mentioned transformation is profitable. 2780static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2781 unsigned ExtOpc, 2782 SmallVector<SDNode*, 4> &ExtendNodes, 2783 TargetLowering &TLI) { 2784 bool HasCopyToRegUses = false; 2785 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2786 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2787 UE = N0.getNode()->use_end(); 2788 UI != UE; ++UI) { 2789 SDNode *User = *UI; 2790 if (User == N) 2791 continue; 2792 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2793 if (User->getOpcode() == ISD::SETCC) { 2794 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2795 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2796 // Sign bits will be lost after a zext. 2797 return false; 2798 bool Add = false; 2799 for (unsigned i = 0; i != 2; ++i) { 2800 SDValue UseOp = User->getOperand(i); 2801 if (UseOp == N0) 2802 continue; 2803 if (!isa<ConstantSDNode>(UseOp)) 2804 return false; 2805 Add = true; 2806 } 2807 if (Add) 2808 ExtendNodes.push_back(User); 2809 } else { 2810 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2811 SDValue UseOp = User->getOperand(i); 2812 if (UseOp == N0) { 2813 // If truncate from extended type to original load type is free 2814 // on this target, then it's ok to extend a CopyToReg. 2815 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2816 HasCopyToRegUses = true; 2817 else 2818 return false; 2819 } 2820 } 2821 } 2822 } 2823 2824 if (HasCopyToRegUses) { 2825 bool BothLiveOut = false; 2826 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2827 UI != UE; ++UI) { 2828 SDNode *User = *UI; 2829 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2830 SDValue UseOp = User->getOperand(i); 2831 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2832 BothLiveOut = true; 2833 break; 2834 } 2835 } 2836 } 2837 if (BothLiveOut) 2838 // Both unextended and extended values are live out. There had better be 2839 // good a reason for the transformation. 2840 return ExtendNodes.size(); 2841 } 2842 return true; 2843} 2844 2845SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2846 SDValue N0 = N->getOperand(0); 2847 MVT VT = N->getValueType(0); 2848 2849 // fold (sext c1) -> c1 2850 if (isa<ConstantSDNode>(N0)) 2851 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2852 2853 // fold (sext (sext x)) -> (sext x) 2854 // fold (sext (aext x)) -> (sext x) 2855 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2856 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2857 2858 if (N0.getOpcode() == ISD::TRUNCATE) { 2859 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2860 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2861 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2862 if (NarrowLoad.getNode()) { 2863 if (NarrowLoad.getNode() != N0.getNode()) 2864 CombineTo(N0.getNode(), NarrowLoad); 2865 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2866 } 2867 2868 // See if the value being truncated is already sign extended. If so, just 2869 // eliminate the trunc/sext pair. 2870 SDValue Op = N0.getOperand(0); 2871 unsigned OpBits = Op.getValueType().getSizeInBits(); 2872 unsigned MidBits = N0.getValueType().getSizeInBits(); 2873 unsigned DestBits = VT.getSizeInBits(); 2874 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2875 2876 if (OpBits == DestBits) { 2877 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2878 // bits, it is already ready. 2879 if (NumSignBits > DestBits-MidBits) 2880 return Op; 2881 } else if (OpBits < DestBits) { 2882 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2883 // bits, just sext from i32. 2884 if (NumSignBits > OpBits-MidBits) 2885 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2886 } else { 2887 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2888 // bits, just truncate to i32. 2889 if (NumSignBits > OpBits-MidBits) 2890 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2891 } 2892 2893 // fold (sext (truncate x)) -> (sextinreg x). 2894 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2895 N0.getValueType())) { 2896 if (Op.getValueType().bitsLT(VT)) 2897 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2898 else if (Op.getValueType().bitsGT(VT)) 2899 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2900 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2901 DAG.getValueType(N0.getValueType())); 2902 } 2903 } 2904 2905 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2906 if (ISD::isNON_EXTLoad(N0.getNode()) && 2907 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2908 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 2909 bool DoXform = true; 2910 SmallVector<SDNode*, 4> SetCCs; 2911 if (!N0.hasOneUse()) 2912 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2913 if (DoXform) { 2914 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2915 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2916 LN0->getBasePtr(), LN0->getSrcValue(), 2917 LN0->getSrcValueOffset(), 2918 N0.getValueType(), 2919 LN0->isVolatile(), 2920 LN0->getAlignment()); 2921 CombineTo(N, ExtLoad); 2922 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2923 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 2924 // Extend SetCC uses if necessary. 2925 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2926 SDNode *SetCC = SetCCs[i]; 2927 SmallVector<SDValue, 4> Ops; 2928 for (unsigned j = 0; j != 2; ++j) { 2929 SDValue SOp = SetCC->getOperand(j); 2930 if (SOp == Trunc) 2931 Ops.push_back(ExtLoad); 2932 else 2933 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2934 } 2935 Ops.push_back(SetCC->getOperand(2)); 2936 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2937 &Ops[0], Ops.size())); 2938 } 2939 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2940 } 2941 } 2942 2943 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2944 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2945 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 2946 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 2947 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2948 MVT EVT = LN0->getMemoryVT(); 2949 if ((!AfterLegalize && !LN0->isVolatile()) || 2950 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 2951 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2952 LN0->getBasePtr(), LN0->getSrcValue(), 2953 LN0->getSrcValueOffset(), EVT, 2954 LN0->isVolatile(), 2955 LN0->getAlignment()); 2956 CombineTo(N, ExtLoad); 2957 CombineTo(N0.getNode(), 2958 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2959 ExtLoad.getValue(1)); 2960 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2961 } 2962 } 2963 2964 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2965 if (N0.getOpcode() == ISD::SETCC) { 2966 SDValue SCC = 2967 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2968 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2969 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2970 if (SCC.getNode()) return SCC; 2971 } 2972 2973 // fold (sext x) -> (zext x) if the sign bit is known zero. 2974 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 2975 DAG.SignBitIsZero(N0)) 2976 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2977 2978 return SDValue(); 2979} 2980 2981SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2982 SDValue N0 = N->getOperand(0); 2983 MVT VT = N->getValueType(0); 2984 2985 // fold (zext c1) -> c1 2986 if (isa<ConstantSDNode>(N0)) 2987 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2988 // fold (zext (zext x)) -> (zext x) 2989 // fold (zext (aext x)) -> (zext x) 2990 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2991 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2992 2993 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2994 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2995 if (N0.getOpcode() == ISD::TRUNCATE) { 2996 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2997 if (NarrowLoad.getNode()) { 2998 if (NarrowLoad.getNode() != N0.getNode()) 2999 CombineTo(N0.getNode(), NarrowLoad); 3000 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 3001 } 3002 } 3003 3004 // fold (zext (truncate x)) -> (and x, mask) 3005 if (N0.getOpcode() == ISD::TRUNCATE && 3006 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 3007 SDValue Op = N0.getOperand(0); 3008 if (Op.getValueType().bitsLT(VT)) { 3009 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 3010 } else if (Op.getValueType().bitsGT(VT)) { 3011 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3012 } 3013 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 3014 } 3015 3016 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3017 if (N0.getOpcode() == ISD::AND && 3018 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3019 N0.getOperand(1).getOpcode() == ISD::Constant) { 3020 SDValue X = N0.getOperand(0).getOperand(0); 3021 if (X.getValueType().bitsLT(VT)) { 3022 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3023 } else if (X.getValueType().bitsGT(VT)) { 3024 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3025 } 3026 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3027 Mask.zext(VT.getSizeInBits()); 3028 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3029 } 3030 3031 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3032 if (ISD::isNON_EXTLoad(N0.getNode()) && 3033 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3034 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3035 bool DoXform = true; 3036 SmallVector<SDNode*, 4> SetCCs; 3037 if (!N0.hasOneUse()) 3038 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3039 if (DoXform) { 3040 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3041 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3042 LN0->getBasePtr(), LN0->getSrcValue(), 3043 LN0->getSrcValueOffset(), 3044 N0.getValueType(), 3045 LN0->isVolatile(), 3046 LN0->getAlignment()); 3047 CombineTo(N, ExtLoad); 3048 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3049 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3050 // Extend SetCC uses if necessary. 3051 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3052 SDNode *SetCC = SetCCs[i]; 3053 SmallVector<SDValue, 4> Ops; 3054 for (unsigned j = 0; j != 2; ++j) { 3055 SDValue SOp = SetCC->getOperand(j); 3056 if (SOp == Trunc) 3057 Ops.push_back(ExtLoad); 3058 else 3059 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3060 } 3061 Ops.push_back(SetCC->getOperand(2)); 3062 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3063 &Ops[0], Ops.size())); 3064 } 3065 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3066 } 3067 } 3068 3069 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3070 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3071 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3072 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3073 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3074 MVT EVT = LN0->getMemoryVT(); 3075 if ((!AfterLegalize && !LN0->isVolatile()) || 3076 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3077 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3078 LN0->getBasePtr(), LN0->getSrcValue(), 3079 LN0->getSrcValueOffset(), EVT, 3080 LN0->isVolatile(), 3081 LN0->getAlignment()); 3082 CombineTo(N, ExtLoad); 3083 CombineTo(N0.getNode(), 3084 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3085 ExtLoad.getValue(1)); 3086 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3087 } 3088 } 3089 3090 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3091 if (N0.getOpcode() == ISD::SETCC) { 3092 SDValue SCC = 3093 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3094 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3095 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3096 if (SCC.getNode()) return SCC; 3097 } 3098 3099 return SDValue(); 3100} 3101 3102SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3103 SDValue N0 = N->getOperand(0); 3104 MVT VT = N->getValueType(0); 3105 3106 // fold (aext c1) -> c1 3107 if (isa<ConstantSDNode>(N0)) 3108 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3109 // fold (aext (aext x)) -> (aext x) 3110 // fold (aext (zext x)) -> (zext x) 3111 // fold (aext (sext x)) -> (sext x) 3112 if (N0.getOpcode() == ISD::ANY_EXTEND || 3113 N0.getOpcode() == ISD::ZERO_EXTEND || 3114 N0.getOpcode() == ISD::SIGN_EXTEND) 3115 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3116 3117 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3118 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3119 if (N0.getOpcode() == ISD::TRUNCATE) { 3120 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3121 if (NarrowLoad.getNode()) { 3122 if (NarrowLoad.getNode() != N0.getNode()) 3123 CombineTo(N0.getNode(), NarrowLoad); 3124 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3125 } 3126 } 3127 3128 // fold (aext (truncate x)) 3129 if (N0.getOpcode() == ISD::TRUNCATE) { 3130 SDValue TruncOp = N0.getOperand(0); 3131 if (TruncOp.getValueType() == VT) 3132 return TruncOp; // x iff x size == zext size. 3133 if (TruncOp.getValueType().bitsGT(VT)) 3134 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3135 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3136 } 3137 3138 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3139 if (N0.getOpcode() == ISD::AND && 3140 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3141 N0.getOperand(1).getOpcode() == ISD::Constant) { 3142 SDValue X = N0.getOperand(0).getOperand(0); 3143 if (X.getValueType().bitsLT(VT)) { 3144 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3145 } else if (X.getValueType().bitsGT(VT)) { 3146 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3147 } 3148 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3149 Mask.zext(VT.getSizeInBits()); 3150 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3151 } 3152 3153 // fold (aext (load x)) -> (aext (truncate (extload x))) 3154 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3155 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3156 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3157 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3158 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3159 LN0->getBasePtr(), LN0->getSrcValue(), 3160 LN0->getSrcValueOffset(), 3161 N0.getValueType(), 3162 LN0->isVolatile(), 3163 LN0->getAlignment()); 3164 CombineTo(N, ExtLoad); 3165 // Redirect any chain users to the new load. 3166 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3167 SDValue(ExtLoad.getNode(), 1)); 3168 // If any node needs the original loaded value, recompute it. 3169 if (!LN0->use_empty()) 3170 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3171 ExtLoad.getValue(1)); 3172 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3173 } 3174 3175 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3176 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3177 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3178 if (N0.getOpcode() == ISD::LOAD && 3179 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3180 N0.hasOneUse()) { 3181 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3182 MVT EVT = LN0->getMemoryVT(); 3183 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3184 LN0->getChain(), LN0->getBasePtr(), 3185 LN0->getSrcValue(), 3186 LN0->getSrcValueOffset(), EVT, 3187 LN0->isVolatile(), 3188 LN0->getAlignment()); 3189 CombineTo(N, ExtLoad); 3190 CombineTo(N0.getNode(), 3191 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3192 ExtLoad.getValue(1)); 3193 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3194 } 3195 3196 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3197 if (N0.getOpcode() == ISD::SETCC) { 3198 SDValue SCC = 3199 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3200 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3201 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3202 if (SCC.getNode()) 3203 return SCC; 3204 } 3205 3206 return SDValue(); 3207} 3208 3209/// GetDemandedBits - See if the specified operand can be simplified with the 3210/// knowledge that only the bits specified by Mask are used. If so, return the 3211/// simpler operand, otherwise return a null SDValue. 3212SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3213 switch (V.getOpcode()) { 3214 default: break; 3215 case ISD::OR: 3216 case ISD::XOR: 3217 // If the LHS or RHS don't contribute bits to the or, drop them. 3218 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3219 return V.getOperand(1); 3220 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3221 return V.getOperand(0); 3222 break; 3223 case ISD::SRL: 3224 // Only look at single-use SRLs. 3225 if (!V.getNode()->hasOneUse()) 3226 break; 3227 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3228 // See if we can recursively simplify the LHS. 3229 unsigned Amt = RHSC->getZExtValue(); 3230 APInt NewMask = Mask << Amt; 3231 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3232 if (SimplifyLHS.getNode()) { 3233 return DAG.getNode(ISD::SRL, V.getValueType(), 3234 SimplifyLHS, V.getOperand(1)); 3235 } 3236 } 3237 } 3238 return SDValue(); 3239} 3240 3241/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3242/// bits and then truncated to a narrower type and where N is a multiple 3243/// of number of bits of the narrower type, transform it to a narrower load 3244/// from address + N / num of bits of new type. If the result is to be 3245/// extended, also fold the extension to form a extending load. 3246SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3247 unsigned Opc = N->getOpcode(); 3248 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3249 SDValue N0 = N->getOperand(0); 3250 MVT VT = N->getValueType(0); 3251 MVT EVT = N->getValueType(0); 3252 3253 // This transformation isn't valid for vector loads. 3254 if (VT.isVector()) 3255 return SDValue(); 3256 3257 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3258 // extended to VT. 3259 if (Opc == ISD::SIGN_EXTEND_INREG) { 3260 ExtType = ISD::SEXTLOAD; 3261 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3262 if (AfterLegalize && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3263 return SDValue(); 3264 } 3265 3266 unsigned EVTBits = EVT.getSizeInBits(); 3267 unsigned ShAmt = 0; 3268 bool CombineSRL = false; 3269 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3270 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3271 ShAmt = N01->getZExtValue(); 3272 // Is the shift amount a multiple of size of VT? 3273 if ((ShAmt & (EVTBits-1)) == 0) { 3274 N0 = N0.getOperand(0); 3275 if (N0.getValueType().getSizeInBits() <= EVTBits) 3276 return SDValue(); 3277 CombineSRL = true; 3278 } 3279 } 3280 } 3281 3282 // Do not generate loads of non-round integer types since these can 3283 // be expensive (and would be wrong if the type is not byte sized). 3284 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() && 3285 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3286 // Do not change the width of a volatile load. 3287 !cast<LoadSDNode>(N0)->isVolatile()) { 3288 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3289 MVT PtrType = N0.getOperand(1).getValueType(); 3290 // For big endian targets, we need to adjust the offset to the pointer to 3291 // load the correct bytes. 3292 if (TLI.isBigEndian()) { 3293 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3294 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3295 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3296 } 3297 uint64_t PtrOff = ShAmt / 8; 3298 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3299 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3300 DAG.getConstant(PtrOff, PtrType)); 3301 AddToWorkList(NewPtr.getNode()); 3302 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3303 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3304 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3305 LN0->isVolatile(), NewAlign) 3306 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3307 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3308 EVT, LN0->isVolatile(), NewAlign); 3309 AddToWorkList(N); 3310 if (CombineSRL) { 3311 WorkListRemover DeadNodes(*this); 3312 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3313 &DeadNodes); 3314 CombineTo(N->getOperand(0).getNode(), Load); 3315 } else 3316 CombineTo(N0.getNode(), Load, Load.getValue(1)); 3317 if (ShAmt) { 3318 if (Opc == ISD::SIGN_EXTEND_INREG) 3319 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3320 else 3321 return DAG.getNode(Opc, VT, Load); 3322 } 3323 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3324 } 3325 3326 return SDValue(); 3327} 3328 3329 3330SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3331 SDValue N0 = N->getOperand(0); 3332 SDValue N1 = N->getOperand(1); 3333 MVT VT = N->getValueType(0); 3334 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3335 unsigned VTBits = VT.getSizeInBits(); 3336 unsigned EVTBits = EVT.getSizeInBits(); 3337 3338 // fold (sext_in_reg c1) -> c1 3339 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3340 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3341 3342 // If the input is already sign extended, just drop the extension. 3343 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3344 return N0; 3345 3346 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3347 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3348 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3349 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3350 } 3351 3352 // fold (sext_in_reg (sext x)) -> (sext x) 3353 // fold (sext_in_reg (aext x)) -> (sext x) 3354 // if x is small enough. 3355 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3356 SDValue N00 = N0.getOperand(0); 3357 if (N00.getValueType().getSizeInBits() < EVTBits) 3358 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3359 } 3360 3361 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3362 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3363 return DAG.getZeroExtendInReg(N0, EVT); 3364 3365 // fold operands of sext_in_reg based on knowledge that the top bits are not 3366 // demanded. 3367 if (SimplifyDemandedBits(SDValue(N, 0))) 3368 return SDValue(N, 0); 3369 3370 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3371 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3372 SDValue NarrowLoad = ReduceLoadWidth(N); 3373 if (NarrowLoad.getNode()) 3374 return NarrowLoad; 3375 3376 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3377 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3378 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3379 if (N0.getOpcode() == ISD::SRL) { 3380 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3381 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3382 // We can turn this into an SRA iff the input to the SRL is already sign 3383 // extended enough. 3384 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3385 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3386 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3387 } 3388 } 3389 3390 // fold (sext_inreg (extload x)) -> (sextload x) 3391 if (ISD::isEXTLoad(N0.getNode()) && 3392 ISD::isUNINDEXEDLoad(N0.getNode()) && 3393 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3394 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3395 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3396 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3397 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3398 LN0->getBasePtr(), LN0->getSrcValue(), 3399 LN0->getSrcValueOffset(), EVT, 3400 LN0->isVolatile(), 3401 LN0->getAlignment()); 3402 CombineTo(N, ExtLoad); 3403 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3404 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3405 } 3406 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3407 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3408 N0.hasOneUse() && 3409 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3410 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3411 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3412 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3413 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3414 LN0->getBasePtr(), LN0->getSrcValue(), 3415 LN0->getSrcValueOffset(), EVT, 3416 LN0->isVolatile(), 3417 LN0->getAlignment()); 3418 CombineTo(N, ExtLoad); 3419 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3420 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3421 } 3422 return SDValue(); 3423} 3424 3425SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3426 SDValue N0 = N->getOperand(0); 3427 MVT VT = N->getValueType(0); 3428 3429 // noop truncate 3430 if (N0.getValueType() == N->getValueType(0)) 3431 return N0; 3432 // fold (truncate c1) -> c1 3433 if (isa<ConstantSDNode>(N0)) 3434 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3435 // fold (truncate (truncate x)) -> (truncate x) 3436 if (N0.getOpcode() == ISD::TRUNCATE) 3437 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3438 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3439 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3440 N0.getOpcode() == ISD::ANY_EXTEND) { 3441 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3442 // if the source is smaller than the dest, we still need an extend 3443 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3444 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3445 // if the source is larger than the dest, than we just need the truncate 3446 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3447 else 3448 // if the source and dest are the same type, we can drop both the extend 3449 // and the truncate 3450 return N0.getOperand(0); 3451 } 3452 3453 // See if we can simplify the input to this truncate through knowledge that 3454 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3455 // -> trunc y 3456 SDValue Shorter = 3457 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3458 VT.getSizeInBits())); 3459 if (Shorter.getNode()) 3460 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3461 3462 // fold (truncate (load x)) -> (smaller load x) 3463 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3464 return ReduceLoadWidth(N); 3465} 3466 3467static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3468 SDValue Elt = N->getOperand(i); 3469 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3470 return Elt.getNode(); 3471 return Elt.getOperand(Elt.getResNo()).getNode(); 3472} 3473 3474/// CombineConsecutiveLoads - build_pair (load, load) -> load 3475/// if load locations are consecutive. 3476SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3477 assert(N->getOpcode() == ISD::BUILD_PAIR); 3478 3479 SDNode *LD1 = getBuildPairElt(N, 0); 3480 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3481 return SDValue(); 3482 MVT LD1VT = LD1->getValueType(0); 3483 SDNode *LD2 = getBuildPairElt(N, 1); 3484 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3485 if (ISD::isNON_EXTLoad(LD2) && 3486 LD2->hasOneUse() && 3487 // If both are volatile this would reduce the number of volatile loads. 3488 // If one is volatile it might be ok, but play conservative and bail out. 3489 !cast<LoadSDNode>(LD1)->isVolatile() && 3490 !cast<LoadSDNode>(LD2)->isVolatile() && 3491 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3492 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3493 unsigned Align = LD->getAlignment(); 3494 unsigned NewAlign = TLI.getTargetData()-> 3495 getABITypeAlignment(VT.getTypeForMVT()); 3496 if (NewAlign <= Align && 3497 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) 3498 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3499 LD->getSrcValue(), LD->getSrcValueOffset(), 3500 false, Align); 3501 } 3502 return SDValue(); 3503} 3504 3505SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3506 SDValue N0 = N->getOperand(0); 3507 MVT VT = N->getValueType(0); 3508 3509 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3510 // Only do this before legalize, since afterward the target may be depending 3511 // on the bitconvert. 3512 // First check to see if this is all constant. 3513 if (!AfterLegalize && 3514 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3515 VT.isVector()) { 3516 bool isSimple = true; 3517 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3518 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3519 N0.getOperand(i).getOpcode() != ISD::Constant && 3520 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3521 isSimple = false; 3522 break; 3523 } 3524 3525 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3526 assert(!DestEltVT.isVector() && 3527 "Element type of vector ValueType must not be vector!"); 3528 if (isSimple) { 3529 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3530 } 3531 } 3532 3533 // If the input is a constant, let getNode fold it. 3534 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3535 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3536 if (Res.getNode() != N) return Res; 3537 } 3538 3539 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3540 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3541 3542 // fold (conv (load x)) -> (load (conv*)x) 3543 // If the resultant load doesn't need a higher alignment than the original! 3544 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3545 // Do not change the width of a volatile load. 3546 !cast<LoadSDNode>(N0)->isVolatile() && 3547 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) { 3548 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3549 unsigned Align = TLI.getTargetData()-> 3550 getABITypeAlignment(VT.getTypeForMVT()); 3551 unsigned OrigAlign = LN0->getAlignment(); 3552 if (Align <= OrigAlign) { 3553 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3554 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3555 LN0->isVolatile(), OrigAlign); 3556 AddToWorkList(N); 3557 CombineTo(N0.getNode(), 3558 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3559 Load.getValue(1)); 3560 return Load; 3561 } 3562 } 3563 3564 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3565 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3566 // This often reduces constant pool loads. 3567 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3568 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3569 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3570 AddToWorkList(NewConv.getNode()); 3571 3572 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3573 if (N0.getOpcode() == ISD::FNEG) 3574 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3575 assert(N0.getOpcode() == ISD::FABS); 3576 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3577 } 3578 3579 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3580 // Note that we don't handle copysign(x,cst) because this can always be folded 3581 // to an fneg or fabs. 3582 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3583 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3584 VT.isInteger() && !VT.isVector()) { 3585 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3586 SDValue X = DAG.getNode(ISD::BIT_CONVERT, 3587 MVT::getIntegerVT(OrigXWidth), 3588 N0.getOperand(1)); 3589 AddToWorkList(X.getNode()); 3590 3591 // If X has a different width than the result/lhs, sext it or truncate it. 3592 unsigned VTWidth = VT.getSizeInBits(); 3593 if (OrigXWidth < VTWidth) { 3594 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3595 AddToWorkList(X.getNode()); 3596 } else if (OrigXWidth > VTWidth) { 3597 // To get the sign bit in the right place, we have to shift it right 3598 // before truncating. 3599 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3600 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3601 AddToWorkList(X.getNode()); 3602 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3603 AddToWorkList(X.getNode()); 3604 } 3605 3606 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3607 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3608 AddToWorkList(X.getNode()); 3609 3610 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3611 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3612 AddToWorkList(Cst.getNode()); 3613 3614 return DAG.getNode(ISD::OR, VT, X, Cst); 3615 } 3616 3617 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3618 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3619 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3620 if (CombineLD.getNode()) 3621 return CombineLD; 3622 } 3623 3624 return SDValue(); 3625} 3626 3627SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3628 MVT VT = N->getValueType(0); 3629 return CombineConsecutiveLoads(N, VT); 3630} 3631 3632/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3633/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3634/// destination element value type. 3635SDValue DAGCombiner:: 3636ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3637 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3638 3639 // If this is already the right type, we're done. 3640 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3641 3642 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3643 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3644 3645 // If this is a conversion of N elements of one type to N elements of another 3646 // type, convert each element. This handles FP<->INT cases. 3647 if (SrcBitSize == DstBitSize) { 3648 SmallVector<SDValue, 8> Ops; 3649 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3650 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3651 AddToWorkList(Ops.back().getNode()); 3652 } 3653 MVT VT = MVT::getVectorVT(DstEltVT, 3654 BV->getValueType(0).getVectorNumElements()); 3655 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3656 } 3657 3658 // Otherwise, we're growing or shrinking the elements. To avoid having to 3659 // handle annoying details of growing/shrinking FP values, we convert them to 3660 // int first. 3661 if (SrcEltVT.isFloatingPoint()) { 3662 // Convert the input float vector to a int vector where the elements are the 3663 // same sizes. 3664 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3665 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3666 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3667 SrcEltVT = IntVT; 3668 } 3669 3670 // Now we know the input is an integer vector. If the output is a FP type, 3671 // convert to integer first, then to FP of the right size. 3672 if (DstEltVT.isFloatingPoint()) { 3673 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3674 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3675 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3676 3677 // Next, convert to FP elements of the same size. 3678 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3679 } 3680 3681 // Okay, we know the src/dst types are both integers of differing types. 3682 // Handling growing first. 3683 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3684 if (SrcBitSize < DstBitSize) { 3685 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3686 3687 SmallVector<SDValue, 8> Ops; 3688 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3689 i += NumInputsPerOutput) { 3690 bool isLE = TLI.isLittleEndian(); 3691 APInt NewBits = APInt(DstBitSize, 0); 3692 bool EltIsUndef = true; 3693 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3694 // Shift the previously computed bits over. 3695 NewBits <<= SrcBitSize; 3696 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3697 if (Op.getOpcode() == ISD::UNDEF) continue; 3698 EltIsUndef = false; 3699 3700 NewBits |= 3701 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3702 } 3703 3704 if (EltIsUndef) 3705 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3706 else 3707 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3708 } 3709 3710 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3711 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3712 } 3713 3714 // Finally, this must be the case where we are shrinking elements: each input 3715 // turns into multiple outputs. 3716 bool isS2V = ISD::isScalarToVector(BV); 3717 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3718 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3719 SmallVector<SDValue, 8> Ops; 3720 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3721 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3722 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3723 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3724 continue; 3725 } 3726 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3727 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3728 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3729 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3730 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3731 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3732 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3733 OpVal = OpVal.lshr(DstBitSize); 3734 } 3735 3736 // For big endian targets, swap the order of the pieces of each element. 3737 if (TLI.isBigEndian()) 3738 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3739 } 3740 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3741} 3742 3743 3744 3745SDValue DAGCombiner::visitFADD(SDNode *N) { 3746 SDValue N0 = N->getOperand(0); 3747 SDValue N1 = N->getOperand(1); 3748 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3749 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3750 MVT VT = N->getValueType(0); 3751 3752 // fold vector ops 3753 if (VT.isVector()) { 3754 SDValue FoldedVOp = SimplifyVBinOp(N); 3755 if (FoldedVOp.getNode()) return FoldedVOp; 3756 } 3757 3758 // fold (fadd c1, c2) -> c1+c2 3759 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3760 return DAG.getNode(ISD::FADD, VT, N0, N1); 3761 // canonicalize constant to RHS 3762 if (N0CFP && !N1CFP) 3763 return DAG.getNode(ISD::FADD, VT, N1, N0); 3764 // fold (A + (-B)) -> A-B 3765 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3766 return DAG.getNode(ISD::FSUB, VT, N0, 3767 GetNegatedExpression(N1, DAG, AfterLegalize)); 3768 // fold ((-A) + B) -> B-A 3769 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3770 return DAG.getNode(ISD::FSUB, VT, N1, 3771 GetNegatedExpression(N0, DAG, AfterLegalize)); 3772 3773 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3774 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3775 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3776 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3777 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3778 3779 return SDValue(); 3780} 3781 3782SDValue DAGCombiner::visitFSUB(SDNode *N) { 3783 SDValue N0 = N->getOperand(0); 3784 SDValue N1 = N->getOperand(1); 3785 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3786 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3787 MVT VT = N->getValueType(0); 3788 3789 // fold vector ops 3790 if (VT.isVector()) { 3791 SDValue FoldedVOp = SimplifyVBinOp(N); 3792 if (FoldedVOp.getNode()) return FoldedVOp; 3793 } 3794 3795 // fold (fsub c1, c2) -> c1-c2 3796 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3797 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3798 // fold (0-B) -> -B 3799 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3800 if (isNegatibleForFree(N1, AfterLegalize)) 3801 return GetNegatedExpression(N1, DAG, AfterLegalize); 3802 return DAG.getNode(ISD::FNEG, VT, N1); 3803 } 3804 // fold (A-(-B)) -> A+B 3805 if (isNegatibleForFree(N1, AfterLegalize)) 3806 return DAG.getNode(ISD::FADD, VT, N0, 3807 GetNegatedExpression(N1, DAG, AfterLegalize)); 3808 3809 return SDValue(); 3810} 3811 3812SDValue DAGCombiner::visitFMUL(SDNode *N) { 3813 SDValue N0 = N->getOperand(0); 3814 SDValue N1 = N->getOperand(1); 3815 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3816 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3817 MVT VT = N->getValueType(0); 3818 3819 // fold vector ops 3820 if (VT.isVector()) { 3821 SDValue FoldedVOp = SimplifyVBinOp(N); 3822 if (FoldedVOp.getNode()) return FoldedVOp; 3823 } 3824 3825 // fold (fmul c1, c2) -> c1*c2 3826 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3827 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3828 // canonicalize constant to RHS 3829 if (N0CFP && !N1CFP) 3830 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3831 // fold (fmul X, 2.0) -> (fadd X, X) 3832 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3833 return DAG.getNode(ISD::FADD, VT, N0, N0); 3834 // fold (fmul X, -1.0) -> (fneg X) 3835 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3836 return DAG.getNode(ISD::FNEG, VT, N0); 3837 3838 // -X * -Y -> X*Y 3839 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3840 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3841 // Both can be negated for free, check to see if at least one is cheaper 3842 // negated. 3843 if (LHSNeg == 2 || RHSNeg == 2) 3844 return DAG.getNode(ISD::FMUL, VT, 3845 GetNegatedExpression(N0, DAG, AfterLegalize), 3846 GetNegatedExpression(N1, DAG, AfterLegalize)); 3847 } 3848 } 3849 3850 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3851 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3852 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3853 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3854 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3855 3856 return SDValue(); 3857} 3858 3859SDValue DAGCombiner::visitFDIV(SDNode *N) { 3860 SDValue N0 = N->getOperand(0); 3861 SDValue N1 = N->getOperand(1); 3862 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3863 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3864 MVT VT = N->getValueType(0); 3865 3866 // fold vector ops 3867 if (VT.isVector()) { 3868 SDValue FoldedVOp = SimplifyVBinOp(N); 3869 if (FoldedVOp.getNode()) return FoldedVOp; 3870 } 3871 3872 // fold (fdiv c1, c2) -> c1/c2 3873 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3874 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3875 3876 3877 // -X / -Y -> X*Y 3878 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3879 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3880 // Both can be negated for free, check to see if at least one is cheaper 3881 // negated. 3882 if (LHSNeg == 2 || RHSNeg == 2) 3883 return DAG.getNode(ISD::FDIV, VT, 3884 GetNegatedExpression(N0, DAG, AfterLegalize), 3885 GetNegatedExpression(N1, DAG, AfterLegalize)); 3886 } 3887 } 3888 3889 return SDValue(); 3890} 3891 3892SDValue DAGCombiner::visitFREM(SDNode *N) { 3893 SDValue N0 = N->getOperand(0); 3894 SDValue N1 = N->getOperand(1); 3895 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3896 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3897 MVT VT = N->getValueType(0); 3898 3899 // fold (frem c1, c2) -> fmod(c1,c2) 3900 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3901 return DAG.getNode(ISD::FREM, VT, N0, N1); 3902 3903 return SDValue(); 3904} 3905 3906SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3907 SDValue N0 = N->getOperand(0); 3908 SDValue N1 = N->getOperand(1); 3909 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3910 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3911 MVT VT = N->getValueType(0); 3912 3913 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3914 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3915 3916 if (N1CFP) { 3917 const APFloat& V = N1CFP->getValueAPF(); 3918 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3919 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3920 if (!V.isNegative()) 3921 return DAG.getNode(ISD::FABS, VT, N0); 3922 else 3923 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3924 } 3925 3926 // copysign(fabs(x), y) -> copysign(x, y) 3927 // copysign(fneg(x), y) -> copysign(x, y) 3928 // copysign(copysign(x,z), y) -> copysign(x, y) 3929 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3930 N0.getOpcode() == ISD::FCOPYSIGN) 3931 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3932 3933 // copysign(x, abs(y)) -> abs(x) 3934 if (N1.getOpcode() == ISD::FABS) 3935 return DAG.getNode(ISD::FABS, VT, N0); 3936 3937 // copysign(x, copysign(y,z)) -> copysign(x, z) 3938 if (N1.getOpcode() == ISD::FCOPYSIGN) 3939 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3940 3941 // copysign(x, fp_extend(y)) -> copysign(x, y) 3942 // copysign(x, fp_round(y)) -> copysign(x, y) 3943 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3944 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3945 3946 return SDValue(); 3947} 3948 3949 3950 3951SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3952 SDValue N0 = N->getOperand(0); 3953 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3954 MVT VT = N->getValueType(0); 3955 MVT OpVT = N0.getValueType(); 3956 3957 // fold (sint_to_fp c1) -> c1fp 3958 if (N0C && OpVT != MVT::ppcf128) 3959 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3960 3961 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 3962 // but UINT_TO_FP is legal on this target, try to convert. 3963 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && 3964 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { 3965 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 3966 if (DAG.SignBitIsZero(N0)) 3967 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3968 } 3969 3970 3971 return SDValue(); 3972} 3973 3974SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3975 SDValue N0 = N->getOperand(0); 3976 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3977 MVT VT = N->getValueType(0); 3978 MVT OpVT = N0.getValueType(); 3979 3980 // fold (uint_to_fp c1) -> c1fp 3981 if (N0C && OpVT != MVT::ppcf128) 3982 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3983 3984 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 3985 // but SINT_TO_FP is legal on this target, try to convert. 3986 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && 3987 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { 3988 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 3989 if (DAG.SignBitIsZero(N0)) 3990 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3991 } 3992 3993 return SDValue(); 3994} 3995 3996SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3997 SDValue N0 = N->getOperand(0); 3998 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3999 MVT VT = N->getValueType(0); 4000 4001 // fold (fp_to_sint c1fp) -> c1 4002 if (N0CFP) 4003 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 4004 return SDValue(); 4005} 4006 4007SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4008 SDValue N0 = N->getOperand(0); 4009 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4010 MVT VT = N->getValueType(0); 4011 4012 // fold (fp_to_uint c1fp) -> c1 4013 if (N0CFP && VT != MVT::ppcf128) 4014 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 4015 return SDValue(); 4016} 4017 4018SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4019 SDValue N0 = N->getOperand(0); 4020 SDValue N1 = N->getOperand(1); 4021 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4022 MVT VT = N->getValueType(0); 4023 4024 // fold (fp_round c1fp) -> c1fp 4025 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4026 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 4027 4028 // fold (fp_round (fp_extend x)) -> x 4029 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4030 return N0.getOperand(0); 4031 4032 // fold (fp_round (fp_round x)) -> (fp_round x) 4033 if (N0.getOpcode() == ISD::FP_ROUND) { 4034 // This is a value preserving truncation if both round's are. 4035 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4036 N0.getNode()->getConstantOperandVal(1) == 1; 4037 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 4038 DAG.getIntPtrConstant(IsTrunc)); 4039 } 4040 4041 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4042 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4043 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 4044 AddToWorkList(Tmp.getNode()); 4045 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 4046 } 4047 4048 return SDValue(); 4049} 4050 4051SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4052 SDValue N0 = N->getOperand(0); 4053 MVT VT = N->getValueType(0); 4054 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4055 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4056 4057 // fold (fp_round_inreg c1fp) -> c1fp 4058 if (N0CFP) { 4059 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4060 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4061 } 4062 return SDValue(); 4063} 4064 4065SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4066 SDValue N0 = N->getOperand(0); 4067 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4068 MVT VT = N->getValueType(0); 4069 4070 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4071 if (N->hasOneUse() && 4072 N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND) 4073 return SDValue(); 4074 4075 // fold (fp_extend c1fp) -> c1fp 4076 if (N0CFP && VT != MVT::ppcf128) 4077 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4078 4079 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4080 // value of X. 4081 if (N0.getOpcode() == ISD::FP_ROUND 4082 && N0.getNode()->getConstantOperandVal(1) == 1) { 4083 SDValue In = N0.getOperand(0); 4084 if (In.getValueType() == VT) return In; 4085 if (VT.bitsLT(In.getValueType())) 4086 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4087 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4088 } 4089 4090 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4091 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4092 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 4093 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4094 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4095 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4096 LN0->getBasePtr(), LN0->getSrcValue(), 4097 LN0->getSrcValueOffset(), 4098 N0.getValueType(), 4099 LN0->isVolatile(), 4100 LN0->getAlignment()); 4101 CombineTo(N, ExtLoad); 4102 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4103 ExtLoad, DAG.getIntPtrConstant(1)), 4104 ExtLoad.getValue(1)); 4105 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4106 } 4107 4108 return SDValue(); 4109} 4110 4111SDValue DAGCombiner::visitFNEG(SDNode *N) { 4112 SDValue N0 = N->getOperand(0); 4113 4114 if (isNegatibleForFree(N0, AfterLegalize)) 4115 return GetNegatedExpression(N0, DAG, AfterLegalize); 4116 4117 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4118 // constant pool values. 4119 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4120 N0.getOperand(0).getValueType().isInteger() && 4121 !N0.getOperand(0).getValueType().isVector()) { 4122 SDValue Int = N0.getOperand(0); 4123 MVT IntVT = Int.getValueType(); 4124 if (IntVT.isInteger() && !IntVT.isVector()) { 4125 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4126 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4127 AddToWorkList(Int.getNode()); 4128 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4129 } 4130 } 4131 4132 return SDValue(); 4133} 4134 4135SDValue DAGCombiner::visitFABS(SDNode *N) { 4136 SDValue N0 = N->getOperand(0); 4137 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4138 MVT VT = N->getValueType(0); 4139 4140 // fold (fabs c1) -> fabs(c1) 4141 if (N0CFP && VT != MVT::ppcf128) 4142 return DAG.getNode(ISD::FABS, VT, N0); 4143 // fold (fabs (fabs x)) -> (fabs x) 4144 if (N0.getOpcode() == ISD::FABS) 4145 return N->getOperand(0); 4146 // fold (fabs (fneg x)) -> (fabs x) 4147 // fold (fabs (fcopysign x, y)) -> (fabs x) 4148 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4149 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4150 4151 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4152 // constant pool values. 4153 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4154 N0.getOperand(0).getValueType().isInteger() && 4155 !N0.getOperand(0).getValueType().isVector()) { 4156 SDValue Int = N0.getOperand(0); 4157 MVT IntVT = Int.getValueType(); 4158 if (IntVT.isInteger() && !IntVT.isVector()) { 4159 Int = DAG.getNode(ISD::AND, IntVT, Int, 4160 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4161 AddToWorkList(Int.getNode()); 4162 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4163 } 4164 } 4165 4166 return SDValue(); 4167} 4168 4169SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4170 SDValue Chain = N->getOperand(0); 4171 SDValue N1 = N->getOperand(1); 4172 SDValue N2 = N->getOperand(2); 4173 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4174 4175 // never taken branch, fold to chain 4176 if (N1C && N1C->isNullValue()) 4177 return Chain; 4178 // unconditional branch 4179 if (N1C && N1C->getAPIntValue() == 1) 4180 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4181 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4182 // on the target. 4183 if (N1.getOpcode() == ISD::SETCC && 4184 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4185 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4186 N1.getOperand(0), N1.getOperand(1), N2); 4187 } 4188 return SDValue(); 4189} 4190 4191// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4192// 4193SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4194 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4195 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4196 4197 // Use SimplifySetCC to simplify SETCC's. 4198 SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 4199 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4200 4201 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4202 4203 // fold br_cc true, dest -> br dest (unconditional branch) 4204 if (SCCC && !SCCC->isNullValue()) 4205 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4206 N->getOperand(4)); 4207 // fold br_cc false, dest -> unconditional fall through 4208 if (SCCC && SCCC->isNullValue()) 4209 return N->getOperand(0); 4210 4211 // fold to a simpler setcc 4212 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4213 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4214 Simp.getOperand(2), Simp.getOperand(0), 4215 Simp.getOperand(1), N->getOperand(4)); 4216 return SDValue(); 4217} 4218 4219 4220/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4221/// pre-indexed load / store when the base pointer is an add or subtract 4222/// and it has other uses besides the load / store. After the 4223/// transformation, the new indexed load / store has effectively folded 4224/// the add / subtract in and all of its other uses are redirected to the 4225/// new load / store. 4226bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4227 if (!AfterLegalize) 4228 return false; 4229 4230 bool isLoad = true; 4231 SDValue Ptr; 4232 MVT VT; 4233 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4234 if (LD->isIndexed()) 4235 return false; 4236 VT = LD->getMemoryVT(); 4237 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4238 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4239 return false; 4240 Ptr = LD->getBasePtr(); 4241 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4242 if (ST->isIndexed()) 4243 return false; 4244 VT = ST->getMemoryVT(); 4245 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4246 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4247 return false; 4248 Ptr = ST->getBasePtr(); 4249 isLoad = false; 4250 } else 4251 return false; 4252 4253 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4254 // out. There is no reason to make this a preinc/predec. 4255 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4256 Ptr.getNode()->hasOneUse()) 4257 return false; 4258 4259 // Ask the target to do addressing mode selection. 4260 SDValue BasePtr; 4261 SDValue Offset; 4262 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4263 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4264 return false; 4265 // Don't create a indexed load / store with zero offset. 4266 if (isa<ConstantSDNode>(Offset) && 4267 cast<ConstantSDNode>(Offset)->isNullValue()) 4268 return false; 4269 4270 // Try turning it into a pre-indexed load / store except when: 4271 // 1) The new base ptr is a frame index. 4272 // 2) If N is a store and the new base ptr is either the same as or is a 4273 // predecessor of the value being stored. 4274 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4275 // that would create a cycle. 4276 // 4) All uses are load / store ops that use it as old base ptr. 4277 4278 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4279 // (plus the implicit offset) to a register to preinc anyway. 4280 if (isa<FrameIndexSDNode>(BasePtr)) 4281 return false; 4282 4283 // Check #2. 4284 if (!isLoad) { 4285 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4286 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4287 return false; 4288 } 4289 4290 // Now check for #3 and #4. 4291 bool RealUse = false; 4292 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4293 E = Ptr.getNode()->use_end(); I != E; ++I) { 4294 SDNode *Use = *I; 4295 if (Use == N) 4296 continue; 4297 if (Use->isPredecessorOf(N)) 4298 return false; 4299 4300 if (!((Use->getOpcode() == ISD::LOAD && 4301 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4302 (Use->getOpcode() == ISD::STORE && 4303 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4304 RealUse = true; 4305 } 4306 if (!RealUse) 4307 return false; 4308 4309 SDValue Result; 4310 if (isLoad) 4311 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4312 else 4313 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4314 ++PreIndexedNodes; 4315 ++NodesCombined; 4316 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4317 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4318 DOUT << '\n'; 4319 WorkListRemover DeadNodes(*this); 4320 if (isLoad) { 4321 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4322 &DeadNodes); 4323 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4324 &DeadNodes); 4325 } else { 4326 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4327 &DeadNodes); 4328 } 4329 4330 // Finally, since the node is now dead, remove it from the graph. 4331 DAG.DeleteNode(N); 4332 4333 // Replace the uses of Ptr with uses of the updated base value. 4334 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4335 &DeadNodes); 4336 removeFromWorkList(Ptr.getNode()); 4337 DAG.DeleteNode(Ptr.getNode()); 4338 4339 return true; 4340} 4341 4342/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4343/// add / sub of the base pointer node into a post-indexed load / store. 4344/// The transformation folded the add / subtract into the new indexed 4345/// load / store effectively and all of its uses are redirected to the 4346/// new load / store. 4347bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4348 if (!AfterLegalize) 4349 return false; 4350 4351 bool isLoad = true; 4352 SDValue Ptr; 4353 MVT VT; 4354 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4355 if (LD->isIndexed()) 4356 return false; 4357 VT = LD->getMemoryVT(); 4358 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4359 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4360 return false; 4361 Ptr = LD->getBasePtr(); 4362 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4363 if (ST->isIndexed()) 4364 return false; 4365 VT = ST->getMemoryVT(); 4366 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4367 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4368 return false; 4369 Ptr = ST->getBasePtr(); 4370 isLoad = false; 4371 } else 4372 return false; 4373 4374 if (Ptr.getNode()->hasOneUse()) 4375 return false; 4376 4377 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4378 E = Ptr.getNode()->use_end(); I != E; ++I) { 4379 SDNode *Op = *I; 4380 if (Op == N || 4381 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4382 continue; 4383 4384 SDValue BasePtr; 4385 SDValue Offset; 4386 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4387 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4388 if (Ptr == Offset) 4389 std::swap(BasePtr, Offset); 4390 if (Ptr != BasePtr) 4391 continue; 4392 // Don't create a indexed load / store with zero offset. 4393 if (isa<ConstantSDNode>(Offset) && 4394 cast<ConstantSDNode>(Offset)->isNullValue()) 4395 continue; 4396 4397 // Try turning it into a post-indexed load / store except when 4398 // 1) All uses are load / store ops that use it as base ptr. 4399 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4400 // nor a successor of N. Otherwise, if Op is folded that would 4401 // create a cycle. 4402 4403 // Check for #1. 4404 bool TryNext = false; 4405 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4406 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4407 SDNode *Use = *II; 4408 if (Use == Ptr.getNode()) 4409 continue; 4410 4411 // If all the uses are load / store addresses, then don't do the 4412 // transformation. 4413 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4414 bool RealUse = false; 4415 for (SDNode::use_iterator III = Use->use_begin(), 4416 EEE = Use->use_end(); III != EEE; ++III) { 4417 SDNode *UseUse = *III; 4418 if (!((UseUse->getOpcode() == ISD::LOAD && 4419 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4420 (UseUse->getOpcode() == ISD::STORE && 4421 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4422 RealUse = true; 4423 } 4424 4425 if (!RealUse) { 4426 TryNext = true; 4427 break; 4428 } 4429 } 4430 } 4431 if (TryNext) 4432 continue; 4433 4434 // Check for #2 4435 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4436 SDValue Result = isLoad 4437 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4438 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4439 ++PostIndexedNodes; 4440 ++NodesCombined; 4441 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4442 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4443 DOUT << '\n'; 4444 WorkListRemover DeadNodes(*this); 4445 if (isLoad) { 4446 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4447 &DeadNodes); 4448 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4449 &DeadNodes); 4450 } else { 4451 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4452 &DeadNodes); 4453 } 4454 4455 // Finally, since the node is now dead, remove it from the graph. 4456 DAG.DeleteNode(N); 4457 4458 // Replace the uses of Use with uses of the updated base value. 4459 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4460 Result.getValue(isLoad ? 1 : 0), 4461 &DeadNodes); 4462 removeFromWorkList(Op); 4463 DAG.DeleteNode(Op); 4464 return true; 4465 } 4466 } 4467 } 4468 return false; 4469} 4470 4471/// InferAlignment - If we can infer some alignment information from this 4472/// pointer, return it. 4473static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4474 // If this is a direct reference to a stack slot, use information about the 4475 // stack slot's alignment. 4476 int FrameIdx = 1 << 31; 4477 int64_t FrameOffset = 0; 4478 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4479 FrameIdx = FI->getIndex(); 4480 } else if (Ptr.getOpcode() == ISD::ADD && 4481 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4482 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4483 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4484 FrameOffset = Ptr.getConstantOperandVal(1); 4485 } 4486 4487 if (FrameIdx != (1 << 31)) { 4488 // FIXME: Handle FI+CST. 4489 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4490 if (MFI.isFixedObjectIndex(FrameIdx)) { 4491 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4492 4493 // The alignment of the frame index can be determined from its offset from 4494 // the incoming frame position. If the frame object is at offset 32 and 4495 // the stack is guaranteed to be 16-byte aligned, then we know that the 4496 // object is 16-byte aligned. 4497 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4498 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4499 4500 // Finally, the frame object itself may have a known alignment. Factor 4501 // the alignment + offset into a new alignment. For example, if we know 4502 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4503 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4504 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4505 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4506 FrameOffset); 4507 return std::max(Align, FIInfoAlign); 4508 } 4509 } 4510 4511 return 0; 4512} 4513 4514SDValue DAGCombiner::visitLOAD(SDNode *N) { 4515 LoadSDNode *LD = cast<LoadSDNode>(N); 4516 SDValue Chain = LD->getChain(); 4517 SDValue Ptr = LD->getBasePtr(); 4518 4519 // Try to infer better alignment information than the load already has. 4520 if (!Fast && LD->isUnindexed()) { 4521 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4522 if (Align > LD->getAlignment()) 4523 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4524 Chain, Ptr, LD->getSrcValue(), 4525 LD->getSrcValueOffset(), LD->getMemoryVT(), 4526 LD->isVolatile(), Align); 4527 } 4528 } 4529 4530 4531 // If load is not volatile and there are no uses of the loaded value (and 4532 // the updated indexed value in case of indexed loads), change uses of the 4533 // chain value into uses of the chain input (i.e. delete the dead load). 4534 if (!LD->isVolatile()) { 4535 if (N->getValueType(1) == MVT::Other) { 4536 // Unindexed loads. 4537 if (N->hasNUsesOfValue(0, 0)) { 4538 // It's not safe to use the two value CombineTo variant here. e.g. 4539 // v1, chain2 = load chain1, loc 4540 // v2, chain3 = load chain2, loc 4541 // v3 = add v2, c 4542 // Now we replace use of chain2 with chain1. This makes the second load 4543 // isomorphic to the one we are deleting, and thus makes this load live. 4544 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4545 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4546 DOUT << "\n"; 4547 WorkListRemover DeadNodes(*this); 4548 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4549 if (N->use_empty()) { 4550 removeFromWorkList(N); 4551 DAG.DeleteNode(N); 4552 } 4553 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4554 } 4555 } else { 4556 // Indexed loads. 4557 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4558 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4559 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4560 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4561 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4562 DOUT << " and 2 other values\n"; 4563 WorkListRemover DeadNodes(*this); 4564 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4565 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4566 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4567 &DeadNodes); 4568 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4569 removeFromWorkList(N); 4570 DAG.DeleteNode(N); 4571 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4572 } 4573 } 4574 } 4575 4576 // If this load is directly stored, replace the load value with the stored 4577 // value. 4578 // TODO: Handle store large -> read small portion. 4579 // TODO: Handle TRUNCSTORE/LOADEXT 4580 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4581 !LD->isVolatile()) { 4582 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4583 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4584 if (PrevST->getBasePtr() == Ptr && 4585 PrevST->getValue().getValueType() == N->getValueType(0)) 4586 return CombineTo(N, Chain.getOperand(1), Chain); 4587 } 4588 } 4589 4590 if (CombinerAA) { 4591 // Walk up chain skipping non-aliasing memory nodes. 4592 SDValue BetterChain = FindBetterChain(N, Chain); 4593 4594 // If there is a better chain. 4595 if (Chain != BetterChain) { 4596 SDValue ReplLoad; 4597 4598 // Replace the chain to void dependency. 4599 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4600 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4601 LD->getSrcValue(), LD->getSrcValueOffset(), 4602 LD->isVolatile(), LD->getAlignment()); 4603 } else { 4604 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4605 LD->getValueType(0), 4606 BetterChain, Ptr, LD->getSrcValue(), 4607 LD->getSrcValueOffset(), 4608 LD->getMemoryVT(), 4609 LD->isVolatile(), 4610 LD->getAlignment()); 4611 } 4612 4613 // Create token factor to keep old chain connected. 4614 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4615 Chain, ReplLoad.getValue(1)); 4616 4617 // Replace uses with load result and token factor. Don't add users 4618 // to work list. 4619 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4620 } 4621 } 4622 4623 // Try transforming N to an indexed load. 4624 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4625 return SDValue(N, 0); 4626 4627 return SDValue(); 4628} 4629 4630 4631SDValue DAGCombiner::visitSTORE(SDNode *N) { 4632 StoreSDNode *ST = cast<StoreSDNode>(N); 4633 SDValue Chain = ST->getChain(); 4634 SDValue Value = ST->getValue(); 4635 SDValue Ptr = ST->getBasePtr(); 4636 4637 // Try to infer better alignment information than the store already has. 4638 if (!Fast && ST->isUnindexed()) { 4639 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4640 if (Align > ST->getAlignment()) 4641 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4642 ST->getSrcValueOffset(), ST->getMemoryVT(), 4643 ST->isVolatile(), Align); 4644 } 4645 } 4646 4647 // If this is a store of a bit convert, store the input value if the 4648 // resultant store does not need a higher alignment than the original. 4649 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4650 ST->isUnindexed()) { 4651 unsigned Align = ST->getAlignment(); 4652 MVT SVT = Value.getOperand(0).getValueType(); 4653 unsigned OrigAlign = TLI.getTargetData()-> 4654 getABITypeAlignment(SVT.getTypeForMVT()); 4655 if (Align <= OrigAlign && 4656 ((!AfterLegalize && !ST->isVolatile()) || 4657 TLI.isOperationLegal(ISD::STORE, SVT))) 4658 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4659 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4660 } 4661 4662 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4663 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4664 // NOTE: If the original store is volatile, this transform must not increase 4665 // the number of stores. For example, on x86-32 an f64 can be stored in one 4666 // processor operation but an i64 (which is not legal) requires two. So the 4667 // transform should not be done in this case. 4668 if (Value.getOpcode() != ISD::TargetConstantFP) { 4669 SDValue Tmp; 4670 switch (CFP->getValueType(0).getSimpleVT()) { 4671 default: assert(0 && "Unknown FP type"); 4672 case MVT::f80: // We don't do this for these yet. 4673 case MVT::f128: 4674 case MVT::ppcf128: 4675 break; 4676 case MVT::f32: 4677 if ((!AfterLegalize && !ST->isVolatile()) || 4678 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4679 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4680 bitcastToAPInt().getZExtValue(), MVT::i32); 4681 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4682 ST->getSrcValueOffset(), ST->isVolatile(), 4683 ST->getAlignment()); 4684 } 4685 break; 4686 case MVT::f64: 4687 if ((!AfterLegalize && !ST->isVolatile()) || 4688 TLI.isOperationLegal(ISD::STORE, MVT::i64)) { 4689 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4690 getZExtValue(), MVT::i64); 4691 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4692 ST->getSrcValueOffset(), ST->isVolatile(), 4693 ST->getAlignment()); 4694 } else if (!ST->isVolatile() && 4695 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4696 // Many FP stores are not made apparent until after legalize, e.g. for 4697 // argument passing. Since this is so common, custom legalize the 4698 // 64-bit integer store into two 32-bit stores. 4699 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4700 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4701 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4702 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4703 4704 int SVOffset = ST->getSrcValueOffset(); 4705 unsigned Alignment = ST->getAlignment(); 4706 bool isVolatile = ST->isVolatile(); 4707 4708 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4709 ST->getSrcValueOffset(), 4710 isVolatile, ST->getAlignment()); 4711 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4712 DAG.getConstant(4, Ptr.getValueType())); 4713 SVOffset += 4; 4714 Alignment = MinAlign(Alignment, 4U); 4715 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4716 SVOffset, isVolatile, Alignment); 4717 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4718 } 4719 break; 4720 } 4721 } 4722 } 4723 4724 if (CombinerAA) { 4725 // Walk up chain skipping non-aliasing memory nodes. 4726 SDValue BetterChain = FindBetterChain(N, Chain); 4727 4728 // If there is a better chain. 4729 if (Chain != BetterChain) { 4730 // Replace the chain to avoid dependency. 4731 SDValue ReplStore; 4732 if (ST->isTruncatingStore()) { 4733 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4734 ST->getSrcValue(),ST->getSrcValueOffset(), 4735 ST->getMemoryVT(), 4736 ST->isVolatile(), ST->getAlignment()); 4737 } else { 4738 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4739 ST->getSrcValue(), ST->getSrcValueOffset(), 4740 ST->isVolatile(), ST->getAlignment()); 4741 } 4742 4743 // Create token to keep both nodes around. 4744 SDValue Token = 4745 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4746 4747 // Don't add users to work list. 4748 return CombineTo(N, Token, false); 4749 } 4750 } 4751 4752 // Try transforming N to an indexed store. 4753 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4754 return SDValue(N, 0); 4755 4756 // FIXME: is there such a thing as a truncating indexed store? 4757 if (ST->isTruncatingStore() && ST->isUnindexed() && 4758 Value.getValueType().isInteger()) { 4759 // See if we can simplify the input to this truncstore with knowledge that 4760 // only the low bits are being used. For example: 4761 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4762 SDValue Shorter = 4763 GetDemandedBits(Value, 4764 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4765 ST->getMemoryVT().getSizeInBits())); 4766 AddToWorkList(Value.getNode()); 4767 if (Shorter.getNode()) 4768 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4769 ST->getSrcValueOffset(), ST->getMemoryVT(), 4770 ST->isVolatile(), ST->getAlignment()); 4771 4772 // Otherwise, see if we can simplify the operation with 4773 // SimplifyDemandedBits, which only works if the value has a single use. 4774 if (SimplifyDemandedBits(Value, 4775 APInt::getLowBitsSet( 4776 Value.getValueSizeInBits(), 4777 ST->getMemoryVT().getSizeInBits()))) 4778 return SDValue(N, 0); 4779 } 4780 4781 // If this is a load followed by a store to the same location, then the store 4782 // is dead/noop. 4783 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4784 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4785 ST->isUnindexed() && !ST->isVolatile() && 4786 // There can't be any side effects between the load and store, such as 4787 // a call or store. 4788 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4789 // The store is dead, remove it. 4790 return Chain; 4791 } 4792 } 4793 4794 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4795 // truncating store. We can do this even if this is already a truncstore. 4796 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4797 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4798 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4799 ST->getMemoryVT())) { 4800 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4801 ST->getSrcValueOffset(), ST->getMemoryVT(), 4802 ST->isVolatile(), ST->getAlignment()); 4803 } 4804 4805 return SDValue(); 4806} 4807 4808SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4809 SDValue InVec = N->getOperand(0); 4810 SDValue InVal = N->getOperand(1); 4811 SDValue EltNo = N->getOperand(2); 4812 4813 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4814 // vector with the inserted element. 4815 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4816 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4817 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 4818 InVec.getNode()->op_end()); 4819 if (Elt < Ops.size()) 4820 Ops[Elt] = InVal; 4821 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4822 &Ops[0], Ops.size()); 4823 } 4824 4825 return SDValue(); 4826} 4827 4828SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4829 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4830 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4831 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4832 4833 // Perform only after legalization to ensure build_vector / vector_shuffle 4834 // optimizations have already been done. 4835 if (!AfterLegalize) return SDValue(); 4836 4837 SDValue InVec = N->getOperand(0); 4838 SDValue EltNo = N->getOperand(1); 4839 4840 if (isa<ConstantSDNode>(EltNo)) { 4841 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4842 bool NewLoad = false; 4843 MVT VT = InVec.getValueType(); 4844 MVT EVT = VT.getVectorElementType(); 4845 MVT LVT = EVT; 4846 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4847 MVT BCVT = InVec.getOperand(0).getValueType(); 4848 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4849 return SDValue(); 4850 InVec = InVec.getOperand(0); 4851 EVT = BCVT.getVectorElementType(); 4852 NewLoad = true; 4853 } 4854 4855 LoadSDNode *LN0 = NULL; 4856 if (ISD::isNormalLoad(InVec.getNode())) 4857 LN0 = cast<LoadSDNode>(InVec); 4858 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4859 InVec.getOperand(0).getValueType() == EVT && 4860 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 4861 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4862 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4863 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4864 // => 4865 // (load $addr+1*size) 4866 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4867 getOperand(Elt))->getZExtValue(); 4868 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4869 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4870 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4871 InVec = InVec.getOperand(0); 4872 if (ISD::isNormalLoad(InVec.getNode())) { 4873 LN0 = cast<LoadSDNode>(InVec); 4874 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4875 } 4876 } 4877 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4878 return SDValue(); 4879 4880 unsigned Align = LN0->getAlignment(); 4881 if (NewLoad) { 4882 // Check the resultant load doesn't need a higher alignment than the 4883 // original load. 4884 unsigned NewAlign = TLI.getTargetData()-> 4885 getABITypeAlignment(LVT.getTypeForMVT()); 4886 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) 4887 return SDValue(); 4888 Align = NewAlign; 4889 } 4890 4891 SDValue NewPtr = LN0->getBasePtr(); 4892 if (Elt) { 4893 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4894 MVT PtrType = NewPtr.getValueType(); 4895 if (TLI.isBigEndian()) 4896 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4897 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4898 DAG.getConstant(PtrOff, PtrType)); 4899 } 4900 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4901 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4902 LN0->isVolatile(), Align); 4903 } 4904 return SDValue(); 4905} 4906 4907 4908SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4909 unsigned NumInScalars = N->getNumOperands(); 4910 MVT VT = N->getValueType(0); 4911 unsigned NumElts = VT.getVectorNumElements(); 4912 MVT EltType = VT.getVectorElementType(); 4913 4914 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4915 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4916 // at most two distinct vectors, turn this into a shuffle node. 4917 SDValue VecIn1, VecIn2; 4918 for (unsigned i = 0; i != NumInScalars; ++i) { 4919 // Ignore undef inputs. 4920 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4921 4922 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4923 // constant index, bail out. 4924 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4925 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4926 VecIn1 = VecIn2 = SDValue(0, 0); 4927 break; 4928 } 4929 4930 // If the input vector type disagrees with the result of the build_vector, 4931 // we can't make a shuffle. 4932 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 4933 if (ExtractedFromVec.getValueType() != VT) { 4934 VecIn1 = VecIn2 = SDValue(0, 0); 4935 break; 4936 } 4937 4938 // Otherwise, remember this. We allow up to two distinct input vectors. 4939 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4940 continue; 4941 4942 if (VecIn1.getNode() == 0) { 4943 VecIn1 = ExtractedFromVec; 4944 } else if (VecIn2.getNode() == 0) { 4945 VecIn2 = ExtractedFromVec; 4946 } else { 4947 // Too many inputs. 4948 VecIn1 = VecIn2 = SDValue(0, 0); 4949 break; 4950 } 4951 } 4952 4953 // If everything is good, we can make a shuffle operation. 4954 if (VecIn1.getNode()) { 4955 SmallVector<SDValue, 8> BuildVecIndices; 4956 for (unsigned i = 0; i != NumInScalars; ++i) { 4957 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4958 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4959 continue; 4960 } 4961 4962 SDValue Extract = N->getOperand(i); 4963 4964 // If extracting from the first vector, just use the index directly. 4965 if (Extract.getOperand(0) == VecIn1) { 4966 BuildVecIndices.push_back(Extract.getOperand(1)); 4967 continue; 4968 } 4969 4970 // Otherwise, use InIdx + VecSize 4971 unsigned Idx = 4972 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 4973 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4974 } 4975 4976 // Add count and size info. 4977 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 4978 4979 // Return the new VECTOR_SHUFFLE node. 4980 SDValue Ops[5]; 4981 Ops[0] = VecIn1; 4982 if (VecIn2.getNode()) { 4983 Ops[1] = VecIn2; 4984 } else { 4985 // Use an undef build_vector as input for the second operand. 4986 std::vector<SDValue> UnOps(NumInScalars, 4987 DAG.getNode(ISD::UNDEF, 4988 EltType)); 4989 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4990 &UnOps[0], UnOps.size()); 4991 AddToWorkList(Ops[1].getNode()); 4992 } 4993 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4994 &BuildVecIndices[0], BuildVecIndices.size()); 4995 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4996 } 4997 4998 return SDValue(); 4999} 5000 5001SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5002 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5003 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5004 // inputs come from at most two distinct vectors, turn this into a shuffle 5005 // node. 5006 5007 // If we only have one input vector, we don't need to do any concatenation. 5008 if (N->getNumOperands() == 1) { 5009 return N->getOperand(0); 5010 } 5011 5012 return SDValue(); 5013} 5014 5015SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5016 SDValue ShufMask = N->getOperand(2); 5017 unsigned NumElts = ShufMask.getNumOperands(); 5018 5019 SDValue N0 = N->getOperand(0); 5020 SDValue N1 = N->getOperand(1); 5021 5022 assert(N0.getValueType().getVectorNumElements() == NumElts && 5023 "Vector shuffle must be normalized in DAG"); 5024 5025 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5026 bool isIdentity = true; 5027 for (unsigned i = 0; i != NumElts; ++i) { 5028 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5029 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5030 isIdentity = false; 5031 break; 5032 } 5033 } 5034 if (isIdentity) return N->getOperand(0); 5035 5036 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5037 isIdentity = true; 5038 for (unsigned i = 0; i != NumElts; ++i) { 5039 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5040 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5041 i+NumElts) { 5042 isIdentity = false; 5043 break; 5044 } 5045 } 5046 if (isIdentity) return N->getOperand(1); 5047 5048 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5049 // needed at all. 5050 bool isUnary = true; 5051 bool isSplat = true; 5052 int VecNum = -1; 5053 unsigned BaseIdx = 0; 5054 for (unsigned i = 0; i != NumElts; ++i) 5055 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5056 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5057 int V = (Idx < NumElts) ? 0 : 1; 5058 if (VecNum == -1) { 5059 VecNum = V; 5060 BaseIdx = Idx; 5061 } else { 5062 if (BaseIdx != Idx) 5063 isSplat = false; 5064 if (VecNum != V) { 5065 isUnary = false; 5066 break; 5067 } 5068 } 5069 } 5070 5071 // Normalize unary shuffle so the RHS is undef. 5072 if (isUnary && VecNum == 1) 5073 std::swap(N0, N1); 5074 5075 // If it is a splat, check if the argument vector is a build_vector with 5076 // all scalar elements the same. 5077 if (isSplat) { 5078 SDNode *V = N0.getNode(); 5079 5080 // If this is a bit convert that changes the element type of the vector but 5081 // not the number of vector elements, look through it. Be careful not to 5082 // look though conversions that change things like v4f32 to v2f64. 5083 if (V->getOpcode() == ISD::BIT_CONVERT) { 5084 SDValue ConvInput = V->getOperand(0); 5085 if (ConvInput.getValueType().isVector() && 5086 ConvInput.getValueType().getVectorNumElements() == NumElts) 5087 V = ConvInput.getNode(); 5088 } 5089 5090 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5091 unsigned NumElems = V->getNumOperands(); 5092 if (NumElems > BaseIdx) { 5093 SDValue Base; 5094 bool AllSame = true; 5095 for (unsigned i = 0; i != NumElems; ++i) { 5096 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5097 Base = V->getOperand(i); 5098 break; 5099 } 5100 } 5101 // Splat of <u, u, u, u>, return <u, u, u, u> 5102 if (!Base.getNode()) 5103 return N0; 5104 for (unsigned i = 0; i != NumElems; ++i) { 5105 if (V->getOperand(i) != Base) { 5106 AllSame = false; 5107 break; 5108 } 5109 } 5110 // Splat of <x, x, x, x>, return <x, x, x, x> 5111 if (AllSame) 5112 return N0; 5113 } 5114 } 5115 } 5116 5117 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5118 // into an undef. 5119 if (isUnary || N0 == N1) { 5120 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5121 // first operand. 5122 SmallVector<SDValue, 8> MappedOps; 5123 for (unsigned i = 0; i != NumElts; ++i) { 5124 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5125 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5126 NumElts) { 5127 MappedOps.push_back(ShufMask.getOperand(i)); 5128 } else { 5129 unsigned NewIdx = 5130 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5131 NumElts; 5132 MappedOps.push_back(DAG.getConstant(NewIdx, 5133 ShufMask.getOperand(i).getValueType())); 5134 } 5135 } 5136 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5137 &MappedOps[0], MappedOps.size()); 5138 AddToWorkList(ShufMask.getNode()); 5139 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5140 N0, 5141 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5142 ShufMask); 5143 } 5144 5145 return SDValue(); 5146} 5147 5148SDValue DAGCombiner::visitADDO(SDNode *N) { 5149 SDValue Chain = N->getOperand(2); 5150 SDValue LHS = N->getOperand(0); 5151 SDValue RHS = N->getOperand(1); 5152 5153 SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); 5154 AddToWorkList(Sum.getNode()); 5155 SDValue Cmp = DAG.getSetCC(MVT::i1, Sum, LHS, ISD::SETLT); 5156 AddToWorkList(Cmp.getNode()); 5157 5158 MVT ValueVTs[] = { LHS.getValueType(), MVT::i1, MVT::Other }; 5159 SDValue Ops[] = { Sum, Cmp, Chain }; 5160 5161 SDValue Merge = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 3), 5162 &Ops[0], 3); 5163 SDNode *MNode = Merge.getNode(); 5164 5165 AddToWorkList(MNode); 5166 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(MNode, 0)); 5167 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(MNode, 1)); 5168 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), SDValue(MNode, 2)); 5169 5170 // Since the node is now dead, remove it from the graph. 5171 removeFromWorkList(N); 5172 DAG.DeleteNode(N); 5173 return SDValue(N, 0); 5174} 5175 5176/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5177/// an AND to a vector_shuffle with the destination vector and a zero vector. 5178/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5179/// vector_shuffle V, Zero, <0, 4, 2, 4> 5180SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5181 SDValue LHS = N->getOperand(0); 5182 SDValue RHS = N->getOperand(1); 5183 if (N->getOpcode() == ISD::AND) { 5184 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5185 RHS = RHS.getOperand(0); 5186 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5187 std::vector<SDValue> IdxOps; 5188 unsigned NumOps = RHS.getNumOperands(); 5189 unsigned NumElts = NumOps; 5190 for (unsigned i = 0; i != NumElts; ++i) { 5191 SDValue Elt = RHS.getOperand(i); 5192 if (!isa<ConstantSDNode>(Elt)) 5193 return SDValue(); 5194 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5195 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5196 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5197 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5198 else 5199 return SDValue(); 5200 } 5201 5202 // Let's see if the target supports this vector_shuffle. 5203 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5204 return SDValue(); 5205 5206 // Return the new VECTOR_SHUFFLE node. 5207 MVT EVT = RHS.getValueType().getVectorElementType(); 5208 MVT VT = MVT::getVectorVT(EVT, NumElts); 5209 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5210 std::vector<SDValue> Ops; 5211 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5212 Ops.push_back(LHS); 5213 AddToWorkList(LHS.getNode()); 5214 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5215 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5216 &ZeroOps[0], ZeroOps.size())); 5217 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5218 &IdxOps[0], IdxOps.size())); 5219 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5220 &Ops[0], Ops.size()); 5221 if (VT != N->getValueType(0)) 5222 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5223 return Result; 5224 } 5225 } 5226 return SDValue(); 5227} 5228 5229/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5230SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5231 // After legalize, the target may be depending on adds and other 5232 // binary ops to provide legal ways to construct constants or other 5233 // things. Simplifying them may result in a loss of legality. 5234 if (AfterLegalize) return SDValue(); 5235 5236 MVT VT = N->getValueType(0); 5237 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5238 5239 MVT EltType = VT.getVectorElementType(); 5240 SDValue LHS = N->getOperand(0); 5241 SDValue RHS = N->getOperand(1); 5242 SDValue Shuffle = XformToShuffleWithZero(N); 5243 if (Shuffle.getNode()) return Shuffle; 5244 5245 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5246 // this operation. 5247 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5248 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5249 SmallVector<SDValue, 8> Ops; 5250 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5251 SDValue LHSOp = LHS.getOperand(i); 5252 SDValue RHSOp = RHS.getOperand(i); 5253 // If these two elements can't be folded, bail out. 5254 if ((LHSOp.getOpcode() != ISD::UNDEF && 5255 LHSOp.getOpcode() != ISD::Constant && 5256 LHSOp.getOpcode() != ISD::ConstantFP) || 5257 (RHSOp.getOpcode() != ISD::UNDEF && 5258 RHSOp.getOpcode() != ISD::Constant && 5259 RHSOp.getOpcode() != ISD::ConstantFP)) 5260 break; 5261 // Can't fold divide by zero. 5262 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5263 N->getOpcode() == ISD::FDIV) { 5264 if ((RHSOp.getOpcode() == ISD::Constant && 5265 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5266 (RHSOp.getOpcode() == ISD::ConstantFP && 5267 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5268 break; 5269 } 5270 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5271 AddToWorkList(Ops.back().getNode()); 5272 assert((Ops.back().getOpcode() == ISD::UNDEF || 5273 Ops.back().getOpcode() == ISD::Constant || 5274 Ops.back().getOpcode() == ISD::ConstantFP) && 5275 "Scalar binop didn't fold!"); 5276 } 5277 5278 if (Ops.size() == LHS.getNumOperands()) { 5279 MVT VT = LHS.getValueType(); 5280 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5281 } 5282 } 5283 5284 return SDValue(); 5285} 5286 5287SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5288 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5289 5290 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5291 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5292 // If we got a simplified select_cc node back from SimplifySelectCC, then 5293 // break it down into a new SETCC node, and a new SELECT node, and then return 5294 // the SELECT node, since we were called with a SELECT node. 5295 if (SCC.getNode()) { 5296 // Check to see if we got a select_cc back (to turn into setcc/select). 5297 // Otherwise, just return whatever node we got back, like fabs. 5298 if (SCC.getOpcode() == ISD::SELECT_CC) { 5299 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5300 SCC.getOperand(0), SCC.getOperand(1), 5301 SCC.getOperand(4)); 5302 AddToWorkList(SETCC.getNode()); 5303 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5304 SCC.getOperand(3), SETCC); 5305 } 5306 return SCC; 5307 } 5308 return SDValue(); 5309} 5310 5311/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5312/// are the two values being selected between, see if we can simplify the 5313/// select. Callers of this should assume that TheSelect is deleted if this 5314/// returns true. As such, they should return the appropriate thing (e.g. the 5315/// node) back to the top-level of the DAG combiner loop to avoid it being 5316/// looked at. 5317/// 5318bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5319 SDValue RHS) { 5320 5321 // If this is a select from two identical things, try to pull the operation 5322 // through the select. 5323 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5324 // If this is a load and the token chain is identical, replace the select 5325 // of two loads with a load through a select of the address to load from. 5326 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5327 // constants have been dropped into the constant pool. 5328 if (LHS.getOpcode() == ISD::LOAD && 5329 // Do not let this transformation reduce the number of volatile loads. 5330 !cast<LoadSDNode>(LHS)->isVolatile() && 5331 !cast<LoadSDNode>(RHS)->isVolatile() && 5332 // Token chains must be identical. 5333 LHS.getOperand(0) == RHS.getOperand(0)) { 5334 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5335 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5336 5337 // If this is an EXTLOAD, the VT's must match. 5338 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5339 // FIXME: this conflates two src values, discarding one. This is not 5340 // the right thing to do, but nothing uses srcvalues now. When they do, 5341 // turn SrcValue into a list of locations. 5342 SDValue Addr; 5343 if (TheSelect->getOpcode() == ISD::SELECT) { 5344 // Check that the condition doesn't reach either load. If so, folding 5345 // this will induce a cycle into the DAG. 5346 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5347 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5348 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5349 TheSelect->getOperand(0), LLD->getBasePtr(), 5350 RLD->getBasePtr()); 5351 } 5352 } else { 5353 // Check that the condition doesn't reach either load. If so, folding 5354 // this will induce a cycle into the DAG. 5355 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5356 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5357 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5358 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5359 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5360 TheSelect->getOperand(0), 5361 TheSelect->getOperand(1), 5362 LLD->getBasePtr(), RLD->getBasePtr(), 5363 TheSelect->getOperand(4)); 5364 } 5365 } 5366 5367 if (Addr.getNode()) { 5368 SDValue Load; 5369 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5370 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5371 Addr,LLD->getSrcValue(), 5372 LLD->getSrcValueOffset(), 5373 LLD->isVolatile(), 5374 LLD->getAlignment()); 5375 else { 5376 Load = DAG.getExtLoad(LLD->getExtensionType(), 5377 TheSelect->getValueType(0), 5378 LLD->getChain(), Addr, LLD->getSrcValue(), 5379 LLD->getSrcValueOffset(), 5380 LLD->getMemoryVT(), 5381 LLD->isVolatile(), 5382 LLD->getAlignment()); 5383 } 5384 // Users of the select now use the result of the load. 5385 CombineTo(TheSelect, Load); 5386 5387 // Users of the old loads now use the new load's chain. We know the 5388 // old-load value is dead now. 5389 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5390 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5391 return true; 5392 } 5393 } 5394 } 5395 } 5396 5397 return false; 5398} 5399 5400SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5401 SDValue N2, SDValue N3, 5402 ISD::CondCode CC, bool NotExtCompare) { 5403 5404 MVT VT = N2.getValueType(); 5405 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5406 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5407 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5408 5409 // Determine if the condition we're dealing with is constant 5410 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5411 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5412 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5413 5414 // fold select_cc true, x, y -> x 5415 if (SCCC && !SCCC->isNullValue()) 5416 return N2; 5417 // fold select_cc false, x, y -> y 5418 if (SCCC && SCCC->isNullValue()) 5419 return N3; 5420 5421 // Check to see if we can simplify the select into an fabs node 5422 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5423 // Allow either -0.0 or 0.0 5424 if (CFP->getValueAPF().isZero()) { 5425 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5426 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5427 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5428 N2 == N3.getOperand(0)) 5429 return DAG.getNode(ISD::FABS, VT, N0); 5430 5431 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5432 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5433 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5434 N2.getOperand(0) == N3) 5435 return DAG.getNode(ISD::FABS, VT, N3); 5436 } 5437 } 5438 5439 // Check to see if we can perform the "gzip trick", transforming 5440 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5441 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5442 N0.getValueType().isInteger() && 5443 N2.getValueType().isInteger() && 5444 (N1C->isNullValue() || // (a < 0) ? b : 0 5445 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5446 MVT XType = N0.getValueType(); 5447 MVT AType = N2.getValueType(); 5448 if (XType.bitsGE(AType)) { 5449 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5450 // single-bit constant. 5451 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5452 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5453 ShCtV = XType.getSizeInBits()-ShCtV-1; 5454 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5455 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5456 AddToWorkList(Shift.getNode()); 5457 if (XType.bitsGT(AType)) { 5458 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5459 AddToWorkList(Shift.getNode()); 5460 } 5461 return DAG.getNode(ISD::AND, AType, Shift, N2); 5462 } 5463 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5464 DAG.getConstant(XType.getSizeInBits()-1, 5465 TLI.getShiftAmountTy())); 5466 AddToWorkList(Shift.getNode()); 5467 if (XType.bitsGT(AType)) { 5468 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5469 AddToWorkList(Shift.getNode()); 5470 } 5471 return DAG.getNode(ISD::AND, AType, Shift, N2); 5472 } 5473 } 5474 5475 // fold select C, 16, 0 -> shl C, 4 5476 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5477 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5478 5479 // If the caller doesn't want us to simplify this into a zext of a compare, 5480 // don't do it. 5481 if (NotExtCompare && N2C->getAPIntValue() == 1) 5482 return SDValue(); 5483 5484 // Get a SetCC of the condition 5485 // FIXME: Should probably make sure that setcc is legal if we ever have a 5486 // target where it isn't. 5487 SDValue Temp, SCC; 5488 // cast from setcc result type to select result type 5489 if (AfterLegalize) { 5490 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5491 if (N2.getValueType().bitsLT(SCC.getValueType())) 5492 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5493 else 5494 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5495 } else { 5496 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5497 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5498 } 5499 AddToWorkList(SCC.getNode()); 5500 AddToWorkList(Temp.getNode()); 5501 5502 if (N2C->getAPIntValue() == 1) 5503 return Temp; 5504 // shl setcc result by log2 n2c 5505 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5506 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5507 TLI.getShiftAmountTy())); 5508 } 5509 5510 // Check to see if this is the equivalent of setcc 5511 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5512 // otherwise, go ahead with the folds. 5513 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5514 MVT XType = N0.getValueType(); 5515 if (!AfterLegalize || 5516 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5517 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5518 if (Res.getValueType() != VT) 5519 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5520 return Res; 5521 } 5522 5523 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5524 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5525 (!AfterLegalize || 5526 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5527 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5528 return DAG.getNode(ISD::SRL, XType, Ctlz, 5529 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5530 TLI.getShiftAmountTy())); 5531 } 5532 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5533 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5534 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5535 N0); 5536 SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5537 DAG.getConstant(~0ULL, XType)); 5538 return DAG.getNode(ISD::SRL, XType, 5539 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5540 DAG.getConstant(XType.getSizeInBits()-1, 5541 TLI.getShiftAmountTy())); 5542 } 5543 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5544 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5545 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5546 DAG.getConstant(XType.getSizeInBits()-1, 5547 TLI.getShiftAmountTy())); 5548 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5549 } 5550 } 5551 5552 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5553 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5554 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5555 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5556 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5557 MVT XType = N0.getValueType(); 5558 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5559 DAG.getConstant(XType.getSizeInBits()-1, 5560 TLI.getShiftAmountTy())); 5561 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5562 AddToWorkList(Shift.getNode()); 5563 AddToWorkList(Add.getNode()); 5564 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5565 } 5566 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5567 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5568 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5569 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5570 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5571 MVT XType = N0.getValueType(); 5572 if (SubC->isNullValue() && XType.isInteger()) { 5573 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5574 DAG.getConstant(XType.getSizeInBits()-1, 5575 TLI.getShiftAmountTy())); 5576 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5577 AddToWorkList(Shift.getNode()); 5578 AddToWorkList(Add.getNode()); 5579 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5580 } 5581 } 5582 } 5583 5584 return SDValue(); 5585} 5586 5587/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5588SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5589 SDValue N1, ISD::CondCode Cond, 5590 bool foldBooleans) { 5591 TargetLowering::DAGCombinerInfo 5592 DagCombineInfo(DAG, !AfterLegalize, false, this); 5593 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5594} 5595 5596/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5597/// return a DAG expression to select that will generate the same value by 5598/// multiplying by a magic number. See: 5599/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5600SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5601 std::vector<SDNode*> Built; 5602 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5603 5604 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5605 ii != ee; ++ii) 5606 AddToWorkList(*ii); 5607 return S; 5608} 5609 5610/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5611/// return a DAG expression to select that will generate the same value by 5612/// multiplying by a magic number. See: 5613/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5614SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5615 std::vector<SDNode*> Built; 5616 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5617 5618 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5619 ii != ee; ++ii) 5620 AddToWorkList(*ii); 5621 return S; 5622} 5623 5624/// FindBaseOffset - Return true if base is known not to alias with anything 5625/// but itself. Provides base object and offset as results. 5626static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5627 // Assume it is a primitive operation. 5628 Base = Ptr; Offset = 0; 5629 5630 // If it's an adding a simple constant then integrate the offset. 5631 if (Base.getOpcode() == ISD::ADD) { 5632 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5633 Base = Base.getOperand(0); 5634 Offset += C->getZExtValue(); 5635 } 5636 } 5637 5638 // If it's any of the following then it can't alias with anything but itself. 5639 return isa<FrameIndexSDNode>(Base) || 5640 isa<ConstantPoolSDNode>(Base) || 5641 isa<GlobalAddressSDNode>(Base); 5642} 5643 5644/// isAlias - Return true if there is any possibility that the two addresses 5645/// overlap. 5646bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5647 const Value *SrcValue1, int SrcValueOffset1, 5648 SDValue Ptr2, int64_t Size2, 5649 const Value *SrcValue2, int SrcValueOffset2) 5650{ 5651 // If they are the same then they must be aliases. 5652 if (Ptr1 == Ptr2) return true; 5653 5654 // Gather base node and offset information. 5655 SDValue Base1, Base2; 5656 int64_t Offset1, Offset2; 5657 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5658 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5659 5660 // If they have a same base address then... 5661 if (Base1 == Base2) { 5662 // Check to see if the addresses overlap. 5663 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5664 } 5665 5666 // If we know both bases then they can't alias. 5667 if (KnownBase1 && KnownBase2) return false; 5668 5669 if (CombinerGlobalAA) { 5670 // Use alias analysis information. 5671 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5672 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5673 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5674 AliasAnalysis::AliasResult AAResult = 5675 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5676 if (AAResult == AliasAnalysis::NoAlias) 5677 return false; 5678 } 5679 5680 // Otherwise we have to assume they alias. 5681 return true; 5682} 5683 5684/// FindAliasInfo - Extracts the relevant alias information from the memory 5685/// node. Returns true if the operand was a load. 5686bool DAGCombiner::FindAliasInfo(SDNode *N, 5687 SDValue &Ptr, int64_t &Size, 5688 const Value *&SrcValue, int &SrcValueOffset) { 5689 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5690 Ptr = LD->getBasePtr(); 5691 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5692 SrcValue = LD->getSrcValue(); 5693 SrcValueOffset = LD->getSrcValueOffset(); 5694 return true; 5695 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5696 Ptr = ST->getBasePtr(); 5697 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5698 SrcValue = ST->getSrcValue(); 5699 SrcValueOffset = ST->getSrcValueOffset(); 5700 } else { 5701 assert(0 && "FindAliasInfo expected a memory operand"); 5702 } 5703 5704 return false; 5705} 5706 5707/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5708/// looking for aliasing nodes and adding them to the Aliases vector. 5709void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5710 SmallVector<SDValue, 8> &Aliases) { 5711 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5712 std::set<SDNode *> Visited; // Visited node set. 5713 5714 // Get alias information for node. 5715 SDValue Ptr; 5716 int64_t Size; 5717 const Value *SrcValue; 5718 int SrcValueOffset; 5719 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5720 5721 // Starting off. 5722 Chains.push_back(OriginalChain); 5723 5724 // Look at each chain and determine if it is an alias. If so, add it to the 5725 // aliases list. If not, then continue up the chain looking for the next 5726 // candidate. 5727 while (!Chains.empty()) { 5728 SDValue Chain = Chains.back(); 5729 Chains.pop_back(); 5730 5731 // Don't bother if we've been before. 5732 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5733 Visited.insert(Chain.getNode()); 5734 5735 switch (Chain.getOpcode()) { 5736 case ISD::EntryToken: 5737 // Entry token is ideal chain operand, but handled in FindBetterChain. 5738 break; 5739 5740 case ISD::LOAD: 5741 case ISD::STORE: { 5742 // Get alias information for Chain. 5743 SDValue OpPtr; 5744 int64_t OpSize; 5745 const Value *OpSrcValue; 5746 int OpSrcValueOffset; 5747 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5748 OpSrcValue, OpSrcValueOffset); 5749 5750 // If chain is alias then stop here. 5751 if (!(IsLoad && IsOpLoad) && 5752 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5753 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5754 Aliases.push_back(Chain); 5755 } else { 5756 // Look further up the chain. 5757 Chains.push_back(Chain.getOperand(0)); 5758 // Clean up old chain. 5759 AddToWorkList(Chain.getNode()); 5760 } 5761 break; 5762 } 5763 5764 case ISD::TokenFactor: 5765 // We have to check each of the operands of the token factor, so we queue 5766 // then up. Adding the operands to the queue (stack) in reverse order 5767 // maintains the original order and increases the likelihood that getNode 5768 // will find a matching token factor (CSE.) 5769 for (unsigned n = Chain.getNumOperands(); n;) 5770 Chains.push_back(Chain.getOperand(--n)); 5771 // Eliminate the token factor if we can. 5772 AddToWorkList(Chain.getNode()); 5773 break; 5774 5775 default: 5776 // For all other instructions we will just have to take what we can get. 5777 Aliases.push_back(Chain); 5778 break; 5779 } 5780 } 5781} 5782 5783/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5784/// for a better chain (aliasing node.) 5785SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5786 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5787 5788 // Accumulate all the aliases to this node. 5789 GatherAllAliases(N, OldChain, Aliases); 5790 5791 if (Aliases.size() == 0) { 5792 // If no operands then chain to entry token. 5793 return DAG.getEntryNode(); 5794 } else if (Aliases.size() == 1) { 5795 // If a single operand then chain to it. We don't need to revisit it. 5796 return Aliases[0]; 5797 } 5798 5799 // Construct a custom tailored token factor. 5800 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5801 &Aliases[0], Aliases.size()); 5802 5803 // Make sure the old chain gets cleaned up. 5804 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5805 5806 return NewChain; 5807} 5808 5809// SelectionDAG::Combine - This is the entry point for the file. 5810// 5811void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA, 5812 bool Fast) { 5813 /// run - This is the main entry point to this class. 5814 /// 5815 DAGCombiner(*this, AA, Fast).Run(RunningAfterLegalize); 5816} 5817