DAGCombiner.cpp revision 61a4c072b9407983df1a6c965ada57474766b282
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include "llvm/Target/TargetOptions.h" 39#include "llvm/Support/Compiler.h" 40#include "llvm/Support/CommandLine.h" 41#include <algorithm> 42using namespace llvm; 43 44STATISTIC(NodesCombined , "Number of dag nodes combined"); 45STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 46STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 47 48namespace { 49#ifndef NDEBUG 50 static cl::opt<bool> 51 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 52 cl::desc("Pop up a window to show dags before the first " 53 "dag combine pass")); 54 static cl::opt<bool> 55 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 56 cl::desc("Pop up a window to show dags before the second " 57 "dag combine pass")); 58#else 59 static const bool ViewDAGCombine1 = false; 60 static const bool ViewDAGCombine2 = false; 61#endif 62 63 static cl::opt<bool> 64 CombinerAA("combiner-alias-analysis", cl::Hidden, 65 cl::desc("Turn on alias analysis during testing")); 66 67 static cl::opt<bool> 68 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 69 cl::desc("Include global information in alias analysis")); 70 71//------------------------------ DAGCombiner ---------------------------------// 72 73 class VISIBILITY_HIDDEN DAGCombiner { 74 SelectionDAG &DAG; 75 TargetLowering &TLI; 76 bool AfterLegalize; 77 78 // Worklist of all of the nodes that need to be simplified. 79 std::vector<SDNode*> WorkList; 80 81 // AA - Used for DAG load/store alias analysis. 82 AliasAnalysis &AA; 83 84 /// AddUsersToWorkList - When an instruction is simplified, add all users of 85 /// the instruction to the work lists because they might get more simplified 86 /// now. 87 /// 88 void AddUsersToWorkList(SDNode *N) { 89 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 90 UI != UE; ++UI) 91 AddToWorkList(*UI); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 public: 102 /// AddToWorkList - Add to the work list making sure it's instance is at the 103 /// the back (next to be processed.) 104 void AddToWorkList(SDNode *N) { 105 removeFromWorkList(N); 106 WorkList.push_back(N); 107 } 108 109 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 110 bool AddTo = true) { 111 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 112 ++NodesCombined; 113 DOUT << "\nReplacing.1 "; DEBUG(N->dump()); 114 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 115 DOUT << " and " << NumTo-1 << " other values\n"; 116 std::vector<SDNode*> NowDead; 117 DAG.ReplaceAllUsesWith(N, To, &NowDead); 118 119 if (AddTo) { 120 // Push the new nodes and any users onto the worklist 121 for (unsigned i = 0, e = NumTo; i != e; ++i) { 122 AddToWorkList(To[i].Val); 123 AddUsersToWorkList(To[i].Val); 124 } 125 } 126 127 // Nodes can be reintroduced into the worklist. Make sure we do not 128 // process a node that has been replaced. 129 removeFromWorkList(N); 130 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 131 removeFromWorkList(NowDead[i]); 132 133 // Finally, since the node is now dead, remove it from the graph. 134 DAG.DeleteNode(N); 135 return SDOperand(N, 0); 136 } 137 138 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 139 return CombineTo(N, &Res, 1, AddTo); 140 } 141 142 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 143 bool AddTo = true) { 144 SDOperand To[] = { Res0, Res1 }; 145 return CombineTo(N, To, 2, AddTo); 146 } 147 private: 148 149 /// SimplifyDemandedBits - Check the specified integer node value to see if 150 /// it can be simplified or if things it uses can be simplified by bit 151 /// propagation. If so, return true. 152 bool SimplifyDemandedBits(SDOperand Op) { 153 TargetLowering::TargetLoweringOpt TLO(DAG); 154 uint64_t KnownZero, KnownOne; 155 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 156 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 157 return false; 158 159 // Revisit the node. 160 AddToWorkList(Op.Val); 161 162 // Replace the old value with the new one. 163 ++NodesCombined; 164 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump()); 165 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 166 DOUT << '\n'; 167 168 std::vector<SDNode*> NowDead; 169 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 170 171 // Push the new node and any (possibly new) users onto the worklist. 172 AddToWorkList(TLO.New.Val); 173 AddUsersToWorkList(TLO.New.Val); 174 175 // Nodes can end up on the worklist more than once. Make sure we do 176 // not process a node that has been replaced. 177 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 178 removeFromWorkList(NowDead[i]); 179 180 // Finally, if the node is now dead, remove it from the graph. The node 181 // may not be dead if the replacement process recursively simplified to 182 // something else needing this node. 183 if (TLO.Old.Val->use_empty()) { 184 removeFromWorkList(TLO.Old.Val); 185 186 // If the operands of this node are only used by the node, they will now 187 // be dead. Make sure to visit them first to delete dead nodes early. 188 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 189 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 190 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 191 192 DAG.DeleteNode(TLO.Old.Val); 193 } 194 return true; 195 } 196 197 bool CombineToPreIndexedLoadStore(SDNode *N); 198 bool CombineToPostIndexedLoadStore(SDNode *N); 199 200 201 /// visit - call the node-specific routine that knows how to fold each 202 /// particular type of node. 203 SDOperand visit(SDNode *N); 204 205 // Visitation implementation - Implement dag node combining for different 206 // node types. The semantics are as follows: 207 // Return Value: 208 // SDOperand.Val == 0 - No change was made 209 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 210 // otherwise - N should be replaced by the returned Operand. 211 // 212 SDOperand visitTokenFactor(SDNode *N); 213 SDOperand visitADD(SDNode *N); 214 SDOperand visitSUB(SDNode *N); 215 SDOperand visitADDC(SDNode *N); 216 SDOperand visitADDE(SDNode *N); 217 SDOperand visitMUL(SDNode *N); 218 SDOperand visitSDIV(SDNode *N); 219 SDOperand visitUDIV(SDNode *N); 220 SDOperand visitSREM(SDNode *N); 221 SDOperand visitUREM(SDNode *N); 222 SDOperand visitMULHU(SDNode *N); 223 SDOperand visitMULHS(SDNode *N); 224 SDOperand visitAND(SDNode *N); 225 SDOperand visitOR(SDNode *N); 226 SDOperand visitXOR(SDNode *N); 227 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 228 SDOperand visitSHL(SDNode *N); 229 SDOperand visitSRA(SDNode *N); 230 SDOperand visitSRL(SDNode *N); 231 SDOperand visitCTLZ(SDNode *N); 232 SDOperand visitCTTZ(SDNode *N); 233 SDOperand visitCTPOP(SDNode *N); 234 SDOperand visitSELECT(SDNode *N); 235 SDOperand visitSELECT_CC(SDNode *N); 236 SDOperand visitSETCC(SDNode *N); 237 SDOperand visitSIGN_EXTEND(SDNode *N); 238 SDOperand visitZERO_EXTEND(SDNode *N); 239 SDOperand visitANY_EXTEND(SDNode *N); 240 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 241 SDOperand visitTRUNCATE(SDNode *N); 242 SDOperand visitBIT_CONVERT(SDNode *N); 243 SDOperand visitVBIT_CONVERT(SDNode *N); 244 SDOperand visitFADD(SDNode *N); 245 SDOperand visitFSUB(SDNode *N); 246 SDOperand visitFMUL(SDNode *N); 247 SDOperand visitFDIV(SDNode *N); 248 SDOperand visitFREM(SDNode *N); 249 SDOperand visitFCOPYSIGN(SDNode *N); 250 SDOperand visitSINT_TO_FP(SDNode *N); 251 SDOperand visitUINT_TO_FP(SDNode *N); 252 SDOperand visitFP_TO_SINT(SDNode *N); 253 SDOperand visitFP_TO_UINT(SDNode *N); 254 SDOperand visitFP_ROUND(SDNode *N); 255 SDOperand visitFP_ROUND_INREG(SDNode *N); 256 SDOperand visitFP_EXTEND(SDNode *N); 257 SDOperand visitFNEG(SDNode *N); 258 SDOperand visitFABS(SDNode *N); 259 SDOperand visitBRCOND(SDNode *N); 260 SDOperand visitBR_CC(SDNode *N); 261 SDOperand visitLOAD(SDNode *N); 262 SDOperand visitSTORE(SDNode *N); 263 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 264 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 265 SDOperand visitVBUILD_VECTOR(SDNode *N); 266 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 267 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 268 269 SDOperand XformToShuffleWithZero(SDNode *N); 270 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 271 272 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 273 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 274 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 275 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 276 SDOperand N3, ISD::CondCode CC, 277 bool NotExtCompare = false); 278 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 279 ISD::CondCode Cond, bool foldBooleans = true); 280 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 281 SDOperand BuildSDIV(SDNode *N); 282 SDOperand BuildUDIV(SDNode *N); 283 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 284 SDOperand ReduceLoadWidth(SDNode *N); 285 286 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 287 /// looking for aliasing nodes and adding them to the Aliases vector. 288 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 289 SmallVector<SDOperand, 8> &Aliases); 290 291 /// isAlias - Return true if there is any possibility that the two addresses 292 /// overlap. 293 bool isAlias(SDOperand Ptr1, int64_t Size1, 294 const Value *SrcValue1, int SrcValueOffset1, 295 SDOperand Ptr2, int64_t Size2, 296 const Value *SrcValue2, int SrcValueOffset2); 297 298 /// FindAliasInfo - Extracts the relevant alias information from the memory 299 /// node. Returns true if the operand was a load. 300 bool FindAliasInfo(SDNode *N, 301 SDOperand &Ptr, int64_t &Size, 302 const Value *&SrcValue, int &SrcValueOffset); 303 304 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 305 /// looking for a better chain (aliasing node.) 306 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 307 308public: 309 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 310 : DAG(D), 311 TLI(D.getTargetLoweringInfo()), 312 AfterLegalize(false), 313 AA(A) {} 314 315 /// Run - runs the dag combiner on all nodes in the work list 316 void Run(bool RunningAfterLegalize); 317 }; 318} 319 320//===----------------------------------------------------------------------===// 321// TargetLowering::DAGCombinerInfo implementation 322//===----------------------------------------------------------------------===// 323 324void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 325 ((DAGCombiner*)DC)->AddToWorkList(N); 326} 327 328SDOperand TargetLowering::DAGCombinerInfo:: 329CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 330 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 331} 332 333SDOperand TargetLowering::DAGCombinerInfo:: 334CombineTo(SDNode *N, SDOperand Res) { 335 return ((DAGCombiner*)DC)->CombineTo(N, Res); 336} 337 338 339SDOperand TargetLowering::DAGCombinerInfo:: 340CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 341 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 342} 343 344 345 346 347//===----------------------------------------------------------------------===// 348 349 350// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 351// that selects between the values 1 and 0, making it equivalent to a setcc. 352// Also, set the incoming LHS, RHS, and CC references to the appropriate 353// nodes based on the type of node we are checking. This simplifies life a 354// bit for the callers. 355static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 356 SDOperand &CC) { 357 if (N.getOpcode() == ISD::SETCC) { 358 LHS = N.getOperand(0); 359 RHS = N.getOperand(1); 360 CC = N.getOperand(2); 361 return true; 362 } 363 if (N.getOpcode() == ISD::SELECT_CC && 364 N.getOperand(2).getOpcode() == ISD::Constant && 365 N.getOperand(3).getOpcode() == ISD::Constant && 366 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 367 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 368 LHS = N.getOperand(0); 369 RHS = N.getOperand(1); 370 CC = N.getOperand(4); 371 return true; 372 } 373 return false; 374} 375 376// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 377// one use. If this is true, it allows the users to invert the operation for 378// free when it is profitable to do so. 379static bool isOneUseSetCC(SDOperand N) { 380 SDOperand N0, N1, N2; 381 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 382 return true; 383 return false; 384} 385 386SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 387 MVT::ValueType VT = N0.getValueType(); 388 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 389 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 390 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 391 if (isa<ConstantSDNode>(N1)) { 392 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 393 AddToWorkList(OpNode.Val); 394 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 395 } else if (N0.hasOneUse()) { 396 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 397 AddToWorkList(OpNode.Val); 398 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 399 } 400 } 401 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 402 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 403 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 404 if (isa<ConstantSDNode>(N0)) { 405 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 406 AddToWorkList(OpNode.Val); 407 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 408 } else if (N1.hasOneUse()) { 409 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 410 AddToWorkList(OpNode.Val); 411 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 412 } 413 } 414 return SDOperand(); 415} 416 417void DAGCombiner::Run(bool RunningAfterLegalize) { 418 // set the instance variable, so that the various visit routines may use it. 419 AfterLegalize = RunningAfterLegalize; 420 421 // Add all the dag nodes to the worklist. 422 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 423 E = DAG.allnodes_end(); I != E; ++I) 424 WorkList.push_back(I); 425 426 // Create a dummy node (which is not added to allnodes), that adds a reference 427 // to the root node, preventing it from being deleted, and tracking any 428 // changes of the root. 429 HandleSDNode Dummy(DAG.getRoot()); 430 431 // The root of the dag may dangle to deleted nodes until the dag combiner is 432 // done. Set it to null to avoid confusion. 433 DAG.setRoot(SDOperand()); 434 435 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 436 TargetLowering::DAGCombinerInfo 437 DagCombineInfo(DAG, !RunningAfterLegalize, false, this); 438 439 // while the worklist isn't empty, inspect the node on the end of it and 440 // try and combine it. 441 while (!WorkList.empty()) { 442 SDNode *N = WorkList.back(); 443 WorkList.pop_back(); 444 445 // If N has no uses, it is dead. Make sure to revisit all N's operands once 446 // N is deleted from the DAG, since they too may now be dead or may have a 447 // reduced number of uses, allowing other xforms. 448 if (N->use_empty() && N != &Dummy) { 449 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 450 AddToWorkList(N->getOperand(i).Val); 451 452 DAG.DeleteNode(N); 453 continue; 454 } 455 456 SDOperand RV = visit(N); 457 458 // If nothing happened, try a target-specific DAG combine. 459 if (RV.Val == 0) { 460 assert(N->getOpcode() != ISD::DELETED_NODE && 461 "Node was deleted but visit returned NULL!"); 462 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 463 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 464 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 465 } 466 467 if (RV.Val) { 468 ++NodesCombined; 469 // If we get back the same node we passed in, rather than a new node or 470 // zero, we know that the node must have defined multiple values and 471 // CombineTo was used. Since CombineTo takes care of the worklist 472 // mechanics for us, we have no work to do in this case. 473 if (RV.Val != N) { 474 assert(N->getOpcode() != ISD::DELETED_NODE && 475 RV.Val->getOpcode() != ISD::DELETED_NODE && 476 "Node was deleted but visit returned new node!"); 477 478 DOUT << "\nReplacing.3 "; DEBUG(N->dump()); 479 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 480 DOUT << '\n'; 481 std::vector<SDNode*> NowDead; 482 if (N->getNumValues() == RV.Val->getNumValues()) 483 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 484 else { 485 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 486 SDOperand OpV = RV; 487 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 488 } 489 490 // Push the new node and any users onto the worklist 491 AddToWorkList(RV.Val); 492 AddUsersToWorkList(RV.Val); 493 494 // Nodes can be reintroduced into the worklist. Make sure we do not 495 // process a node that has been replaced. 496 removeFromWorkList(N); 497 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 498 removeFromWorkList(NowDead[i]); 499 500 // Finally, since the node is now dead, remove it from the graph. 501 DAG.DeleteNode(N); 502 } 503 } 504 } 505 506 // If the root changed (e.g. it was a dead load, update the root). 507 DAG.setRoot(Dummy.getValue()); 508} 509 510SDOperand DAGCombiner::visit(SDNode *N) { 511 switch(N->getOpcode()) { 512 default: break; 513 case ISD::TokenFactor: return visitTokenFactor(N); 514 case ISD::ADD: return visitADD(N); 515 case ISD::SUB: return visitSUB(N); 516 case ISD::ADDC: return visitADDC(N); 517 case ISD::ADDE: return visitADDE(N); 518 case ISD::MUL: return visitMUL(N); 519 case ISD::SDIV: return visitSDIV(N); 520 case ISD::UDIV: return visitUDIV(N); 521 case ISD::SREM: return visitSREM(N); 522 case ISD::UREM: return visitUREM(N); 523 case ISD::MULHU: return visitMULHU(N); 524 case ISD::MULHS: return visitMULHS(N); 525 case ISD::AND: return visitAND(N); 526 case ISD::OR: return visitOR(N); 527 case ISD::XOR: return visitXOR(N); 528 case ISD::SHL: return visitSHL(N); 529 case ISD::SRA: return visitSRA(N); 530 case ISD::SRL: return visitSRL(N); 531 case ISD::CTLZ: return visitCTLZ(N); 532 case ISD::CTTZ: return visitCTTZ(N); 533 case ISD::CTPOP: return visitCTPOP(N); 534 case ISD::SELECT: return visitSELECT(N); 535 case ISD::SELECT_CC: return visitSELECT_CC(N); 536 case ISD::SETCC: return visitSETCC(N); 537 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 538 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 539 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 540 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 541 case ISD::TRUNCATE: return visitTRUNCATE(N); 542 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 543 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 544 case ISD::FADD: return visitFADD(N); 545 case ISD::FSUB: return visitFSUB(N); 546 case ISD::FMUL: return visitFMUL(N); 547 case ISD::FDIV: return visitFDIV(N); 548 case ISD::FREM: return visitFREM(N); 549 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 550 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 551 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 552 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 553 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 554 case ISD::FP_ROUND: return visitFP_ROUND(N); 555 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 556 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 557 case ISD::FNEG: return visitFNEG(N); 558 case ISD::FABS: return visitFABS(N); 559 case ISD::BRCOND: return visitBRCOND(N); 560 case ISD::BR_CC: return visitBR_CC(N); 561 case ISD::LOAD: return visitLOAD(N); 562 case ISD::STORE: return visitSTORE(N); 563 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 564 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 565 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 566 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 567 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 568 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 569 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 570 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 571 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 572 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 573 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 574 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 575 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 576 } 577 return SDOperand(); 578} 579 580/// getInputChainForNode - Given a node, return its input chain if it has one, 581/// otherwise return a null sd operand. 582static SDOperand getInputChainForNode(SDNode *N) { 583 if (unsigned NumOps = N->getNumOperands()) { 584 if (N->getOperand(0).getValueType() == MVT::Other) 585 return N->getOperand(0); 586 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 587 return N->getOperand(NumOps-1); 588 for (unsigned i = 1; i < NumOps-1; ++i) 589 if (N->getOperand(i).getValueType() == MVT::Other) 590 return N->getOperand(i); 591 } 592 return SDOperand(0, 0); 593} 594 595SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 596 // If N has two operands, where one has an input chain equal to the other, 597 // the 'other' chain is redundant. 598 if (N->getNumOperands() == 2) { 599 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 600 return N->getOperand(0); 601 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 602 return N->getOperand(1); 603 } 604 605 606 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 607 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 608 bool Changed = false; // If we should replace this token factor. 609 610 // Start out with this token factor. 611 TFs.push_back(N); 612 613 // Iterate through token factors. The TFs grows when new token factors are 614 // encountered. 615 for (unsigned i = 0; i < TFs.size(); ++i) { 616 SDNode *TF = TFs[i]; 617 618 // Check each of the operands. 619 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 620 SDOperand Op = TF->getOperand(i); 621 622 switch (Op.getOpcode()) { 623 case ISD::EntryToken: 624 // Entry tokens don't need to be added to the list. They are 625 // rededundant. 626 Changed = true; 627 break; 628 629 case ISD::TokenFactor: 630 if ((CombinerAA || Op.hasOneUse()) && 631 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 632 // Queue up for processing. 633 TFs.push_back(Op.Val); 634 // Clean up in case the token factor is removed. 635 AddToWorkList(Op.Val); 636 Changed = true; 637 break; 638 } 639 // Fall thru 640 641 default: 642 // Only add if not there prior. 643 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end()) 644 Ops.push_back(Op); 645 break; 646 } 647 } 648 } 649 650 SDOperand Result; 651 652 // If we've change things around then replace token factor. 653 if (Changed) { 654 if (Ops.size() == 0) { 655 // The entry token is the only possible outcome. 656 Result = DAG.getEntryNode(); 657 } else { 658 // New and improved token factor. 659 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 660 } 661 662 // Don't add users to work list. 663 return CombineTo(N, Result, false); 664 } 665 666 return Result; 667} 668 669static 670SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 671 MVT::ValueType VT = N0.getValueType(); 672 SDOperand N00 = N0.getOperand(0); 673 SDOperand N01 = N0.getOperand(1); 674 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 675 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 676 isa<ConstantSDNode>(N00.getOperand(1))) { 677 N0 = DAG.getNode(ISD::ADD, VT, 678 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 679 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 680 return DAG.getNode(ISD::ADD, VT, N0, N1); 681 } 682 return SDOperand(); 683} 684 685SDOperand DAGCombiner::visitADD(SDNode *N) { 686 SDOperand N0 = N->getOperand(0); 687 SDOperand N1 = N->getOperand(1); 688 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 689 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 690 MVT::ValueType VT = N0.getValueType(); 691 692 // fold (add c1, c2) -> c1+c2 693 if (N0C && N1C) 694 return DAG.getNode(ISD::ADD, VT, N0, N1); 695 // canonicalize constant to RHS 696 if (N0C && !N1C) 697 return DAG.getNode(ISD::ADD, VT, N1, N0); 698 // fold (add x, 0) -> x 699 if (N1C && N1C->isNullValue()) 700 return N0; 701 // fold ((c1-A)+c2) -> (c1+c2)-A 702 if (N1C && N0.getOpcode() == ISD::SUB) 703 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 704 return DAG.getNode(ISD::SUB, VT, 705 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 706 N0.getOperand(1)); 707 // reassociate add 708 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 709 if (RADD.Val != 0) 710 return RADD; 711 // fold ((0-A) + B) -> B-A 712 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 713 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 714 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 715 // fold (A + (0-B)) -> A-B 716 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 717 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 718 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 719 // fold (A+(B-A)) -> B 720 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 721 return N1.getOperand(0); 722 723 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 724 return SDOperand(N, 0); 725 726 // fold (a+b) -> (a|b) iff a and b share no bits. 727 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 728 uint64_t LHSZero, LHSOne; 729 uint64_t RHSZero, RHSOne; 730 uint64_t Mask = MVT::getIntVTBitMask(VT); 731 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 732 if (LHSZero) { 733 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 734 735 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 736 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 737 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 738 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 739 return DAG.getNode(ISD::OR, VT, N0, N1); 740 } 741 } 742 743 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 744 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 745 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 746 if (Result.Val) return Result; 747 } 748 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 749 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 750 if (Result.Val) return Result; 751 } 752 753 return SDOperand(); 754} 755 756SDOperand DAGCombiner::visitADDC(SDNode *N) { 757 SDOperand N0 = N->getOperand(0); 758 SDOperand N1 = N->getOperand(1); 759 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 760 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 761 MVT::ValueType VT = N0.getValueType(); 762 763 // If the flag result is dead, turn this into an ADD. 764 if (N->hasNUsesOfValue(0, 1)) 765 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 766 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 767 768 // canonicalize constant to RHS. 769 if (N0C && !N1C) { 770 SDOperand Ops[] = { N1, N0 }; 771 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 772 } 773 774 // fold (addc x, 0) -> x + no carry out 775 if (N1C && N1C->isNullValue()) 776 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 777 778 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 779 uint64_t LHSZero, LHSOne; 780 uint64_t RHSZero, RHSOne; 781 uint64_t Mask = MVT::getIntVTBitMask(VT); 782 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 783 if (LHSZero) { 784 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 785 786 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 787 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 788 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 789 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 790 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 791 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 792 } 793 794 return SDOperand(); 795} 796 797SDOperand DAGCombiner::visitADDE(SDNode *N) { 798 SDOperand N0 = N->getOperand(0); 799 SDOperand N1 = N->getOperand(1); 800 SDOperand CarryIn = N->getOperand(2); 801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 803 //MVT::ValueType VT = N0.getValueType(); 804 805 // canonicalize constant to RHS 806 if (N0C && !N1C) { 807 SDOperand Ops[] = { N1, N0, CarryIn }; 808 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 809 } 810 811 // fold (adde x, y, false) -> (addc x, y) 812 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 813 SDOperand Ops[] = { N1, N0 }; 814 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 815 } 816 817 return SDOperand(); 818} 819 820 821 822SDOperand DAGCombiner::visitSUB(SDNode *N) { 823 SDOperand N0 = N->getOperand(0); 824 SDOperand N1 = N->getOperand(1); 825 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 826 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 827 MVT::ValueType VT = N0.getValueType(); 828 829 // fold (sub x, x) -> 0 830 if (N0 == N1) 831 return DAG.getConstant(0, N->getValueType(0)); 832 // fold (sub c1, c2) -> c1-c2 833 if (N0C && N1C) 834 return DAG.getNode(ISD::SUB, VT, N0, N1); 835 // fold (sub x, c) -> (add x, -c) 836 if (N1C) 837 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 838 // fold (A+B)-A -> B 839 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 840 return N0.getOperand(1); 841 // fold (A+B)-B -> A 842 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 843 return N0.getOperand(0); 844 return SDOperand(); 845} 846 847SDOperand DAGCombiner::visitMUL(SDNode *N) { 848 SDOperand N0 = N->getOperand(0); 849 SDOperand N1 = N->getOperand(1); 850 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 851 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 852 MVT::ValueType VT = N0.getValueType(); 853 854 // fold (mul c1, c2) -> c1*c2 855 if (N0C && N1C) 856 return DAG.getNode(ISD::MUL, VT, N0, N1); 857 // canonicalize constant to RHS 858 if (N0C && !N1C) 859 return DAG.getNode(ISD::MUL, VT, N1, N0); 860 // fold (mul x, 0) -> 0 861 if (N1C && N1C->isNullValue()) 862 return N1; 863 // fold (mul x, -1) -> 0-x 864 if (N1C && N1C->isAllOnesValue()) 865 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 866 // fold (mul x, (1 << c)) -> x << c 867 if (N1C && isPowerOf2_64(N1C->getValue())) 868 return DAG.getNode(ISD::SHL, VT, N0, 869 DAG.getConstant(Log2_64(N1C->getValue()), 870 TLI.getShiftAmountTy())); 871 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 872 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 873 // FIXME: If the input is something that is easily negated (e.g. a 874 // single-use add), we should put the negate there. 875 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 876 DAG.getNode(ISD::SHL, VT, N0, 877 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 878 TLI.getShiftAmountTy()))); 879 } 880 881 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 882 if (N1C && N0.getOpcode() == ISD::SHL && 883 isa<ConstantSDNode>(N0.getOperand(1))) { 884 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 885 AddToWorkList(C3.Val); 886 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 887 } 888 889 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 890 // use. 891 { 892 SDOperand Sh(0,0), Y(0,0); 893 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 894 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 895 N0.Val->hasOneUse()) { 896 Sh = N0; Y = N1; 897 } else if (N1.getOpcode() == ISD::SHL && 898 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 899 Sh = N1; Y = N0; 900 } 901 if (Sh.Val) { 902 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 903 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 904 } 905 } 906 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 907 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 908 isa<ConstantSDNode>(N0.getOperand(1))) { 909 return DAG.getNode(ISD::ADD, VT, 910 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 911 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 912 } 913 914 // reassociate mul 915 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 916 if (RMUL.Val != 0) 917 return RMUL; 918 return SDOperand(); 919} 920 921SDOperand DAGCombiner::visitSDIV(SDNode *N) { 922 SDOperand N0 = N->getOperand(0); 923 SDOperand N1 = N->getOperand(1); 924 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 925 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 926 MVT::ValueType VT = N->getValueType(0); 927 928 // fold (sdiv c1, c2) -> c1/c2 929 if (N0C && N1C && !N1C->isNullValue()) 930 return DAG.getNode(ISD::SDIV, VT, N0, N1); 931 // fold (sdiv X, 1) -> X 932 if (N1C && N1C->getSignExtended() == 1LL) 933 return N0; 934 // fold (sdiv X, -1) -> 0-X 935 if (N1C && N1C->isAllOnesValue()) 936 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 937 // If we know the sign bits of both operands are zero, strength reduce to a 938 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 939 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 940 if (TLI.MaskedValueIsZero(N1, SignBit) && 941 TLI.MaskedValueIsZero(N0, SignBit)) 942 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 943 // fold (sdiv X, pow2) -> simple ops after legalize 944 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 945 (isPowerOf2_64(N1C->getSignExtended()) || 946 isPowerOf2_64(-N1C->getSignExtended()))) { 947 // If dividing by powers of two is cheap, then don't perform the following 948 // fold. 949 if (TLI.isPow2DivCheap()) 950 return SDOperand(); 951 int64_t pow2 = N1C->getSignExtended(); 952 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 953 unsigned lg2 = Log2_64(abs2); 954 // Splat the sign bit into the register 955 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 956 DAG.getConstant(MVT::getSizeInBits(VT)-1, 957 TLI.getShiftAmountTy())); 958 AddToWorkList(SGN.Val); 959 // Add (N0 < 0) ? abs2 - 1 : 0; 960 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 961 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 962 TLI.getShiftAmountTy())); 963 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 964 AddToWorkList(SRL.Val); 965 AddToWorkList(ADD.Val); // Divide by pow2 966 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 967 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 968 // If we're dividing by a positive value, we're done. Otherwise, we must 969 // negate the result. 970 if (pow2 > 0) 971 return SRA; 972 AddToWorkList(SRA.Val); 973 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 974 } 975 // if integer divide is expensive and we satisfy the requirements, emit an 976 // alternate sequence. 977 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 978 !TLI.isIntDivCheap()) { 979 SDOperand Op = BuildSDIV(N); 980 if (Op.Val) return Op; 981 } 982 return SDOperand(); 983} 984 985SDOperand DAGCombiner::visitUDIV(SDNode *N) { 986 SDOperand N0 = N->getOperand(0); 987 SDOperand N1 = N->getOperand(1); 988 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 989 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 990 MVT::ValueType VT = N->getValueType(0); 991 992 // fold (udiv c1, c2) -> c1/c2 993 if (N0C && N1C && !N1C->isNullValue()) 994 return DAG.getNode(ISD::UDIV, VT, N0, N1); 995 // fold (udiv x, (1 << c)) -> x >>u c 996 if (N1C && isPowerOf2_64(N1C->getValue())) 997 return DAG.getNode(ISD::SRL, VT, N0, 998 DAG.getConstant(Log2_64(N1C->getValue()), 999 TLI.getShiftAmountTy())); 1000 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1001 if (N1.getOpcode() == ISD::SHL) { 1002 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1003 if (isPowerOf2_64(SHC->getValue())) { 1004 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1005 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1006 DAG.getConstant(Log2_64(SHC->getValue()), 1007 ADDVT)); 1008 AddToWorkList(Add.Val); 1009 return DAG.getNode(ISD::SRL, VT, N0, Add); 1010 } 1011 } 1012 } 1013 // fold (udiv x, c) -> alternate 1014 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1015 SDOperand Op = BuildUDIV(N); 1016 if (Op.Val) return Op; 1017 } 1018 return SDOperand(); 1019} 1020 1021SDOperand DAGCombiner::visitSREM(SDNode *N) { 1022 SDOperand N0 = N->getOperand(0); 1023 SDOperand N1 = N->getOperand(1); 1024 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1025 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1026 MVT::ValueType VT = N->getValueType(0); 1027 1028 // fold (srem c1, c2) -> c1%c2 1029 if (N0C && N1C && !N1C->isNullValue()) 1030 return DAG.getNode(ISD::SREM, VT, N0, N1); 1031 // If we know the sign bits of both operands are zero, strength reduce to a 1032 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1033 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1034 if (TLI.MaskedValueIsZero(N1, SignBit) && 1035 TLI.MaskedValueIsZero(N0, SignBit)) 1036 return DAG.getNode(ISD::UREM, VT, N0, N1); 1037 1038 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1039 // the remainder operation. 1040 if (N1C && !N1C->isNullValue()) { 1041 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1042 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1043 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1044 AddToWorkList(Div.Val); 1045 AddToWorkList(Mul.Val); 1046 return Sub; 1047 } 1048 1049 return SDOperand(); 1050} 1051 1052SDOperand DAGCombiner::visitUREM(SDNode *N) { 1053 SDOperand N0 = N->getOperand(0); 1054 SDOperand N1 = N->getOperand(1); 1055 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1056 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1057 MVT::ValueType VT = N->getValueType(0); 1058 1059 // fold (urem c1, c2) -> c1%c2 1060 if (N0C && N1C && !N1C->isNullValue()) 1061 return DAG.getNode(ISD::UREM, VT, N0, N1); 1062 // fold (urem x, pow2) -> (and x, pow2-1) 1063 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1064 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1065 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1066 if (N1.getOpcode() == ISD::SHL) { 1067 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1068 if (isPowerOf2_64(SHC->getValue())) { 1069 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1070 AddToWorkList(Add.Val); 1071 return DAG.getNode(ISD::AND, VT, N0, Add); 1072 } 1073 } 1074 } 1075 1076 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1077 // the remainder operation. 1078 if (N1C && !N1C->isNullValue()) { 1079 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1080 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1081 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1082 AddToWorkList(Div.Val); 1083 AddToWorkList(Mul.Val); 1084 return Sub; 1085 } 1086 1087 return SDOperand(); 1088} 1089 1090SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1091 SDOperand N0 = N->getOperand(0); 1092 SDOperand N1 = N->getOperand(1); 1093 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1094 1095 // fold (mulhs x, 0) -> 0 1096 if (N1C && N1C->isNullValue()) 1097 return N1; 1098 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1099 if (N1C && N1C->getValue() == 1) 1100 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1101 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1102 TLI.getShiftAmountTy())); 1103 return SDOperand(); 1104} 1105 1106SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1107 SDOperand N0 = N->getOperand(0); 1108 SDOperand N1 = N->getOperand(1); 1109 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1110 1111 // fold (mulhu x, 0) -> 0 1112 if (N1C && N1C->isNullValue()) 1113 return N1; 1114 // fold (mulhu x, 1) -> 0 1115 if (N1C && N1C->getValue() == 1) 1116 return DAG.getConstant(0, N0.getValueType()); 1117 return SDOperand(); 1118} 1119 1120/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1121/// two operands of the same opcode, try to simplify it. 1122SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1123 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1124 MVT::ValueType VT = N0.getValueType(); 1125 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1126 1127 // For each of OP in AND/OR/XOR: 1128 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1129 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1130 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1131 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1132 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1133 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1134 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1135 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1136 N0.getOperand(0).getValueType(), 1137 N0.getOperand(0), N1.getOperand(0)); 1138 AddToWorkList(ORNode.Val); 1139 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1140 } 1141 1142 // For each of OP in SHL/SRL/SRA/AND... 1143 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1144 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1145 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1146 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1147 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1148 N0.getOperand(1) == N1.getOperand(1)) { 1149 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1150 N0.getOperand(0).getValueType(), 1151 N0.getOperand(0), N1.getOperand(0)); 1152 AddToWorkList(ORNode.Val); 1153 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1154 } 1155 1156 return SDOperand(); 1157} 1158 1159SDOperand DAGCombiner::visitAND(SDNode *N) { 1160 SDOperand N0 = N->getOperand(0); 1161 SDOperand N1 = N->getOperand(1); 1162 SDOperand LL, LR, RL, RR, CC0, CC1; 1163 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1164 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1165 MVT::ValueType VT = N1.getValueType(); 1166 1167 // fold (and c1, c2) -> c1&c2 1168 if (N0C && N1C) 1169 return DAG.getNode(ISD::AND, VT, N0, N1); 1170 // canonicalize constant to RHS 1171 if (N0C && !N1C) 1172 return DAG.getNode(ISD::AND, VT, N1, N0); 1173 // fold (and x, -1) -> x 1174 if (N1C && N1C->isAllOnesValue()) 1175 return N0; 1176 // if (and x, c) is known to be zero, return 0 1177 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1178 return DAG.getConstant(0, VT); 1179 // reassociate and 1180 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1181 if (RAND.Val != 0) 1182 return RAND; 1183 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1184 if (N1C && N0.getOpcode() == ISD::OR) 1185 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1186 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1187 return N1; 1188 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1189 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1190 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1191 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1192 ~N1C->getValue() & InMask)) { 1193 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1194 N0.getOperand(0)); 1195 1196 // Replace uses of the AND with uses of the Zero extend node. 1197 CombineTo(N, Zext); 1198 1199 // We actually want to replace all uses of the any_extend with the 1200 // zero_extend, to avoid duplicating things. This will later cause this 1201 // AND to be folded. 1202 CombineTo(N0.Val, Zext); 1203 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1204 } 1205 } 1206 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1207 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1208 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1209 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1210 1211 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1212 MVT::isInteger(LL.getValueType())) { 1213 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1214 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1215 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1216 AddToWorkList(ORNode.Val); 1217 return DAG.getSetCC(VT, ORNode, LR, Op1); 1218 } 1219 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1220 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1221 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1222 AddToWorkList(ANDNode.Val); 1223 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1224 } 1225 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1226 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1227 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1228 AddToWorkList(ORNode.Val); 1229 return DAG.getSetCC(VT, ORNode, LR, Op1); 1230 } 1231 } 1232 // canonicalize equivalent to ll == rl 1233 if (LL == RR && LR == RL) { 1234 Op1 = ISD::getSetCCSwappedOperands(Op1); 1235 std::swap(RL, RR); 1236 } 1237 if (LL == RL && LR == RR) { 1238 bool isInteger = MVT::isInteger(LL.getValueType()); 1239 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1240 if (Result != ISD::SETCC_INVALID) 1241 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1242 } 1243 } 1244 1245 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1246 if (N0.getOpcode() == N1.getOpcode()) { 1247 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1248 if (Tmp.Val) return Tmp; 1249 } 1250 1251 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1252 // fold (and (sra)) -> (and (srl)) when possible. 1253 if (!MVT::isVector(VT) && 1254 SimplifyDemandedBits(SDOperand(N, 0))) 1255 return SDOperand(N, 0); 1256 // fold (zext_inreg (extload x)) -> (zextload x) 1257 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1258 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1259 MVT::ValueType EVT = LN0->getLoadedVT(); 1260 // If we zero all the possible extended bits, then we can turn this into 1261 // a zextload if we are running before legalize or the operation is legal. 1262 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1263 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1264 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1265 LN0->getBasePtr(), LN0->getSrcValue(), 1266 LN0->getSrcValueOffset(), EVT); 1267 AddToWorkList(N); 1268 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1269 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1270 } 1271 } 1272 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1273 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1274 N0.hasOneUse()) { 1275 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1276 MVT::ValueType EVT = LN0->getLoadedVT(); 1277 // If we zero all the possible extended bits, then we can turn this into 1278 // a zextload if we are running before legalize or the operation is legal. 1279 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1280 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1281 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1282 LN0->getBasePtr(), LN0->getSrcValue(), 1283 LN0->getSrcValueOffset(), EVT); 1284 AddToWorkList(N); 1285 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1286 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1287 } 1288 } 1289 1290 // fold (and (load x), 255) -> (zextload x, i8) 1291 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1292 if (N1C && N0.getOpcode() == ISD::LOAD) { 1293 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1294 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1295 LN0->getAddressingMode() == ISD::UNINDEXED && 1296 N0.hasOneUse()) { 1297 MVT::ValueType EVT, LoadedVT; 1298 if (N1C->getValue() == 255) 1299 EVT = MVT::i8; 1300 else if (N1C->getValue() == 65535) 1301 EVT = MVT::i16; 1302 else if (N1C->getValue() == ~0U) 1303 EVT = MVT::i32; 1304 else 1305 EVT = MVT::Other; 1306 1307 LoadedVT = LN0->getLoadedVT(); 1308 if (EVT != MVT::Other && LoadedVT > EVT && 1309 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1310 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1311 // For big endian targets, we need to add an offset to the pointer to 1312 // load the correct bytes. For little endian systems, we merely need to 1313 // read fewer bytes from the same pointer. 1314 unsigned PtrOff = 1315 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1316 SDOperand NewPtr = LN0->getBasePtr(); 1317 if (!TLI.isLittleEndian()) 1318 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1319 DAG.getConstant(PtrOff, PtrType)); 1320 AddToWorkList(NewPtr.Val); 1321 SDOperand Load = 1322 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1323 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT); 1324 AddToWorkList(N); 1325 CombineTo(N0.Val, Load, Load.getValue(1)); 1326 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1327 } 1328 } 1329 } 1330 1331 return SDOperand(); 1332} 1333 1334SDOperand DAGCombiner::visitOR(SDNode *N) { 1335 SDOperand N0 = N->getOperand(0); 1336 SDOperand N1 = N->getOperand(1); 1337 SDOperand LL, LR, RL, RR, CC0, CC1; 1338 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1339 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1340 MVT::ValueType VT = N1.getValueType(); 1341 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1342 1343 // fold (or c1, c2) -> c1|c2 1344 if (N0C && N1C) 1345 return DAG.getNode(ISD::OR, VT, N0, N1); 1346 // canonicalize constant to RHS 1347 if (N0C && !N1C) 1348 return DAG.getNode(ISD::OR, VT, N1, N0); 1349 // fold (or x, 0) -> x 1350 if (N1C && N1C->isNullValue()) 1351 return N0; 1352 // fold (or x, -1) -> -1 1353 if (N1C && N1C->isAllOnesValue()) 1354 return N1; 1355 // fold (or x, c) -> c iff (x & ~c) == 0 1356 if (N1C && 1357 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1358 return N1; 1359 // reassociate or 1360 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1361 if (ROR.Val != 0) 1362 return ROR; 1363 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1364 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1365 isa<ConstantSDNode>(N0.getOperand(1))) { 1366 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1367 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1368 N1), 1369 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1370 } 1371 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1372 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1373 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1374 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1375 1376 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1377 MVT::isInteger(LL.getValueType())) { 1378 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1379 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1380 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1381 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1382 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1383 AddToWorkList(ORNode.Val); 1384 return DAG.getSetCC(VT, ORNode, LR, Op1); 1385 } 1386 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1387 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1388 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1389 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1390 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1391 AddToWorkList(ANDNode.Val); 1392 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1393 } 1394 } 1395 // canonicalize equivalent to ll == rl 1396 if (LL == RR && LR == RL) { 1397 Op1 = ISD::getSetCCSwappedOperands(Op1); 1398 std::swap(RL, RR); 1399 } 1400 if (LL == RL && LR == RR) { 1401 bool isInteger = MVT::isInteger(LL.getValueType()); 1402 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1403 if (Result != ISD::SETCC_INVALID) 1404 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1405 } 1406 } 1407 1408 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1409 if (N0.getOpcode() == N1.getOpcode()) { 1410 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1411 if (Tmp.Val) return Tmp; 1412 } 1413 1414 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1415 if (N0.getOpcode() == ISD::AND && 1416 N1.getOpcode() == ISD::AND && 1417 N0.getOperand(1).getOpcode() == ISD::Constant && 1418 N1.getOperand(1).getOpcode() == ISD::Constant && 1419 // Don't increase # computations. 1420 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1421 // We can only do this xform if we know that bits from X that are set in C2 1422 // but not in C1 are already zero. Likewise for Y. 1423 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1424 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1425 1426 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1427 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1428 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1429 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1430 } 1431 } 1432 1433 1434 // See if this is some rotate idiom. 1435 if (SDNode *Rot = MatchRotate(N0, N1)) 1436 return SDOperand(Rot, 0); 1437 1438 return SDOperand(); 1439} 1440 1441 1442/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1443static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1444 if (Op.getOpcode() == ISD::AND) { 1445 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1446 Mask = Op.getOperand(1); 1447 Op = Op.getOperand(0); 1448 } else { 1449 return false; 1450 } 1451 } 1452 1453 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1454 Shift = Op; 1455 return true; 1456 } 1457 return false; 1458} 1459 1460 1461// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1462// idioms for rotate, and if the target supports rotation instructions, generate 1463// a rot[lr]. 1464SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1465 // Must be a legal type. Expanded an promoted things won't work with rotates. 1466 MVT::ValueType VT = LHS.getValueType(); 1467 if (!TLI.isTypeLegal(VT)) return 0; 1468 1469 // The target must have at least one rotate flavor. 1470 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1471 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1472 if (!HasROTL && !HasROTR) return 0; 1473 1474 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1475 SDOperand LHSShift; // The shift. 1476 SDOperand LHSMask; // AND value if any. 1477 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1478 return 0; // Not part of a rotate. 1479 1480 SDOperand RHSShift; // The shift. 1481 SDOperand RHSMask; // AND value if any. 1482 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1483 return 0; // Not part of a rotate. 1484 1485 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1486 return 0; // Not shifting the same value. 1487 1488 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1489 return 0; // Shifts must disagree. 1490 1491 // Canonicalize shl to left side in a shl/srl pair. 1492 if (RHSShift.getOpcode() == ISD::SHL) { 1493 std::swap(LHS, RHS); 1494 std::swap(LHSShift, RHSShift); 1495 std::swap(LHSMask , RHSMask ); 1496 } 1497 1498 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1499 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1500 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1501 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1502 1503 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1504 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1505 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1506 RHSShiftAmt.getOpcode() == ISD::Constant) { 1507 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1508 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1509 if ((LShVal + RShVal) != OpSizeInBits) 1510 return 0; 1511 1512 SDOperand Rot; 1513 if (HasROTL) 1514 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1515 else 1516 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1517 1518 // If there is an AND of either shifted operand, apply it to the result. 1519 if (LHSMask.Val || RHSMask.Val) { 1520 uint64_t Mask = MVT::getIntVTBitMask(VT); 1521 1522 if (LHSMask.Val) { 1523 uint64_t RHSBits = (1ULL << LShVal)-1; 1524 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1525 } 1526 if (RHSMask.Val) { 1527 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1528 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1529 } 1530 1531 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1532 } 1533 1534 return Rot.Val; 1535 } 1536 1537 // If there is a mask here, and we have a variable shift, we can't be sure 1538 // that we're masking out the right stuff. 1539 if (LHSMask.Val || RHSMask.Val) 1540 return 0; 1541 1542 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1543 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1544 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1545 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1546 if (ConstantSDNode *SUBC = 1547 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1548 if (SUBC->getValue() == OpSizeInBits) 1549 if (HasROTL) 1550 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1551 else 1552 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1553 } 1554 } 1555 1556 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1557 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1558 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1559 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1560 if (ConstantSDNode *SUBC = 1561 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1562 if (SUBC->getValue() == OpSizeInBits) 1563 if (HasROTL) 1564 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1565 else 1566 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1567 } 1568 } 1569 1570 // Look for sign/zext/any-extended cases: 1571 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1572 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1573 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1574 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1575 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1576 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1577 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1578 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1579 if (RExtOp0.getOpcode() == ISD::SUB && 1580 RExtOp0.getOperand(1) == LExtOp0) { 1581 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1582 // (rotr x, y) 1583 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1584 // (rotl x, (sub 32, y)) 1585 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1586 if (SUBC->getValue() == OpSizeInBits) { 1587 if (HasROTL) 1588 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1589 else 1590 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1591 } 1592 } 1593 } else if (LExtOp0.getOpcode() == ISD::SUB && 1594 RExtOp0 == LExtOp0.getOperand(1)) { 1595 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1596 // (rotl x, y) 1597 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1598 // (rotr x, (sub 32, y)) 1599 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 1600 if (SUBC->getValue() == OpSizeInBits) { 1601 if (HasROTL) 1602 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 1603 else 1604 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1605 } 1606 } 1607 } 1608 } 1609 1610 return 0; 1611} 1612 1613 1614SDOperand DAGCombiner::visitXOR(SDNode *N) { 1615 SDOperand N0 = N->getOperand(0); 1616 SDOperand N1 = N->getOperand(1); 1617 SDOperand LHS, RHS, CC; 1618 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1619 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1620 MVT::ValueType VT = N0.getValueType(); 1621 1622 // fold (xor c1, c2) -> c1^c2 1623 if (N0C && N1C) 1624 return DAG.getNode(ISD::XOR, VT, N0, N1); 1625 // canonicalize constant to RHS 1626 if (N0C && !N1C) 1627 return DAG.getNode(ISD::XOR, VT, N1, N0); 1628 // fold (xor x, 0) -> x 1629 if (N1C && N1C->isNullValue()) 1630 return N0; 1631 // reassociate xor 1632 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1633 if (RXOR.Val != 0) 1634 return RXOR; 1635 // fold !(x cc y) -> (x !cc y) 1636 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1637 bool isInt = MVT::isInteger(LHS.getValueType()); 1638 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1639 isInt); 1640 if (N0.getOpcode() == ISD::SETCC) 1641 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1642 if (N0.getOpcode() == ISD::SELECT_CC) 1643 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1644 assert(0 && "Unhandled SetCC Equivalent!"); 1645 abort(); 1646 } 1647 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1648 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 1649 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1650 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1651 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1652 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1653 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1654 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1655 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1656 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1657 } 1658 } 1659 // fold !(x or y) -> (!x and !y) iff x or y are constants 1660 if (N1C && N1C->isAllOnesValue() && 1661 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1662 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1663 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1664 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1665 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1666 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1667 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1668 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1669 } 1670 } 1671 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1672 if (N1C && N0.getOpcode() == ISD::XOR) { 1673 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1674 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1675 if (N00C) 1676 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1677 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1678 if (N01C) 1679 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1680 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1681 } 1682 // fold (xor x, x) -> 0 1683 if (N0 == N1) { 1684 if (!MVT::isVector(VT)) { 1685 return DAG.getConstant(0, VT); 1686 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1687 // Produce a vector of zeros. 1688 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1689 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1690 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1691 } 1692 } 1693 1694 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1695 if (N0.getOpcode() == N1.getOpcode()) { 1696 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1697 if (Tmp.Val) return Tmp; 1698 } 1699 1700 // Simplify the expression using non-local knowledge. 1701 if (!MVT::isVector(VT) && 1702 SimplifyDemandedBits(SDOperand(N, 0))) 1703 return SDOperand(N, 0); 1704 1705 return SDOperand(); 1706} 1707 1708SDOperand DAGCombiner::visitSHL(SDNode *N) { 1709 SDOperand N0 = N->getOperand(0); 1710 SDOperand N1 = N->getOperand(1); 1711 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1712 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1713 MVT::ValueType VT = N0.getValueType(); 1714 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1715 1716 // fold (shl c1, c2) -> c1<<c2 1717 if (N0C && N1C) 1718 return DAG.getNode(ISD::SHL, VT, N0, N1); 1719 // fold (shl 0, x) -> 0 1720 if (N0C && N0C->isNullValue()) 1721 return N0; 1722 // fold (shl x, c >= size(x)) -> undef 1723 if (N1C && N1C->getValue() >= OpSizeInBits) 1724 return DAG.getNode(ISD::UNDEF, VT); 1725 // fold (shl x, 0) -> x 1726 if (N1C && N1C->isNullValue()) 1727 return N0; 1728 // if (shl x, c) is known to be zero, return 0 1729 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1730 return DAG.getConstant(0, VT); 1731 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1732 return SDOperand(N, 0); 1733 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1734 if (N1C && N0.getOpcode() == ISD::SHL && 1735 N0.getOperand(1).getOpcode() == ISD::Constant) { 1736 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1737 uint64_t c2 = N1C->getValue(); 1738 if (c1 + c2 > OpSizeInBits) 1739 return DAG.getConstant(0, VT); 1740 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1741 DAG.getConstant(c1 + c2, N1.getValueType())); 1742 } 1743 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1744 // (srl (and x, -1 << c1), c1-c2) 1745 if (N1C && N0.getOpcode() == ISD::SRL && 1746 N0.getOperand(1).getOpcode() == ISD::Constant) { 1747 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1748 uint64_t c2 = N1C->getValue(); 1749 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1750 DAG.getConstant(~0ULL << c1, VT)); 1751 if (c2 > c1) 1752 return DAG.getNode(ISD::SHL, VT, Mask, 1753 DAG.getConstant(c2-c1, N1.getValueType())); 1754 else 1755 return DAG.getNode(ISD::SRL, VT, Mask, 1756 DAG.getConstant(c1-c2, N1.getValueType())); 1757 } 1758 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1759 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1760 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1761 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1762 return SDOperand(); 1763} 1764 1765SDOperand DAGCombiner::visitSRA(SDNode *N) { 1766 SDOperand N0 = N->getOperand(0); 1767 SDOperand N1 = N->getOperand(1); 1768 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1769 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1770 MVT::ValueType VT = N0.getValueType(); 1771 1772 // fold (sra c1, c2) -> c1>>c2 1773 if (N0C && N1C) 1774 return DAG.getNode(ISD::SRA, VT, N0, N1); 1775 // fold (sra 0, x) -> 0 1776 if (N0C && N0C->isNullValue()) 1777 return N0; 1778 // fold (sra -1, x) -> -1 1779 if (N0C && N0C->isAllOnesValue()) 1780 return N0; 1781 // fold (sra x, c >= size(x)) -> undef 1782 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1783 return DAG.getNode(ISD::UNDEF, VT); 1784 // fold (sra x, 0) -> x 1785 if (N1C && N1C->isNullValue()) 1786 return N0; 1787 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1788 // sext_inreg. 1789 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1790 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1791 MVT::ValueType EVT; 1792 switch (LowBits) { 1793 default: EVT = MVT::Other; break; 1794 case 1: EVT = MVT::i1; break; 1795 case 8: EVT = MVT::i8; break; 1796 case 16: EVT = MVT::i16; break; 1797 case 32: EVT = MVT::i32; break; 1798 } 1799 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1800 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1801 DAG.getValueType(EVT)); 1802 } 1803 1804 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1805 if (N1C && N0.getOpcode() == ISD::SRA) { 1806 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1807 unsigned Sum = N1C->getValue() + C1->getValue(); 1808 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1809 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1810 DAG.getConstant(Sum, N1C->getValueType(0))); 1811 } 1812 } 1813 1814 // Simplify, based on bits shifted out of the LHS. 1815 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1816 return SDOperand(N, 0); 1817 1818 1819 // If the sign bit is known to be zero, switch this to a SRL. 1820 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1821 return DAG.getNode(ISD::SRL, VT, N0, N1); 1822 return SDOperand(); 1823} 1824 1825SDOperand DAGCombiner::visitSRL(SDNode *N) { 1826 SDOperand N0 = N->getOperand(0); 1827 SDOperand N1 = N->getOperand(1); 1828 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1829 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1830 MVT::ValueType VT = N0.getValueType(); 1831 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1832 1833 // fold (srl c1, c2) -> c1 >>u c2 1834 if (N0C && N1C) 1835 return DAG.getNode(ISD::SRL, VT, N0, N1); 1836 // fold (srl 0, x) -> 0 1837 if (N0C && N0C->isNullValue()) 1838 return N0; 1839 // fold (srl x, c >= size(x)) -> undef 1840 if (N1C && N1C->getValue() >= OpSizeInBits) 1841 return DAG.getNode(ISD::UNDEF, VT); 1842 // fold (srl x, 0) -> x 1843 if (N1C && N1C->isNullValue()) 1844 return N0; 1845 // if (srl x, c) is known to be zero, return 0 1846 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1847 return DAG.getConstant(0, VT); 1848 1849 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1850 if (N1C && N0.getOpcode() == ISD::SRL && 1851 N0.getOperand(1).getOpcode() == ISD::Constant) { 1852 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1853 uint64_t c2 = N1C->getValue(); 1854 if (c1 + c2 > OpSizeInBits) 1855 return DAG.getConstant(0, VT); 1856 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1857 DAG.getConstant(c1 + c2, N1.getValueType())); 1858 } 1859 1860 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1861 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1862 // Shifting in all undef bits? 1863 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1864 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1865 return DAG.getNode(ISD::UNDEF, VT); 1866 1867 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1868 AddToWorkList(SmallShift.Val); 1869 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1870 } 1871 1872 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 1873 // bit, which is unmodified by sra. 1874 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 1875 if (N0.getOpcode() == ISD::SRA) 1876 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 1877 } 1878 1879 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1880 if (N1C && N0.getOpcode() == ISD::CTLZ && 1881 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1882 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1883 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1884 1885 // If any of the input bits are KnownOne, then the input couldn't be all 1886 // zeros, thus the result of the srl will always be zero. 1887 if (KnownOne) return DAG.getConstant(0, VT); 1888 1889 // If all of the bits input the to ctlz node are known to be zero, then 1890 // the result of the ctlz is "32" and the result of the shift is one. 1891 uint64_t UnknownBits = ~KnownZero & Mask; 1892 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1893 1894 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1895 if ((UnknownBits & (UnknownBits-1)) == 0) { 1896 // Okay, we know that only that the single bit specified by UnknownBits 1897 // could be set on input to the CTLZ node. If this bit is set, the SRL 1898 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1899 // to an SRL,XOR pair, which is likely to simplify more. 1900 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1901 SDOperand Op = N0.getOperand(0); 1902 if (ShAmt) { 1903 Op = DAG.getNode(ISD::SRL, VT, Op, 1904 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1905 AddToWorkList(Op.Val); 1906 } 1907 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1908 } 1909 } 1910 1911 // fold operands of srl based on knowledge that the low bits are not 1912 // demanded. 1913 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1914 return SDOperand(N, 0); 1915 1916 return SDOperand(); 1917} 1918 1919SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1920 SDOperand N0 = N->getOperand(0); 1921 MVT::ValueType VT = N->getValueType(0); 1922 1923 // fold (ctlz c1) -> c2 1924 if (isa<ConstantSDNode>(N0)) 1925 return DAG.getNode(ISD::CTLZ, VT, N0); 1926 return SDOperand(); 1927} 1928 1929SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1930 SDOperand N0 = N->getOperand(0); 1931 MVT::ValueType VT = N->getValueType(0); 1932 1933 // fold (cttz c1) -> c2 1934 if (isa<ConstantSDNode>(N0)) 1935 return DAG.getNode(ISD::CTTZ, VT, N0); 1936 return SDOperand(); 1937} 1938 1939SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1940 SDOperand N0 = N->getOperand(0); 1941 MVT::ValueType VT = N->getValueType(0); 1942 1943 // fold (ctpop c1) -> c2 1944 if (isa<ConstantSDNode>(N0)) 1945 return DAG.getNode(ISD::CTPOP, VT, N0); 1946 return SDOperand(); 1947} 1948 1949SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1950 SDOperand N0 = N->getOperand(0); 1951 SDOperand N1 = N->getOperand(1); 1952 SDOperand N2 = N->getOperand(2); 1953 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1954 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1955 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1956 MVT::ValueType VT = N->getValueType(0); 1957 1958 // fold select C, X, X -> X 1959 if (N1 == N2) 1960 return N1; 1961 // fold select true, X, Y -> X 1962 if (N0C && !N0C->isNullValue()) 1963 return N1; 1964 // fold select false, X, Y -> Y 1965 if (N0C && N0C->isNullValue()) 1966 return N2; 1967 // fold select C, 1, X -> C | X 1968 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1969 return DAG.getNode(ISD::OR, VT, N0, N2); 1970 // fold select C, 0, X -> ~C & X 1971 // FIXME: this should check for C type == X type, not i1? 1972 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1973 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1974 AddToWorkList(XORNode.Val); 1975 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1976 } 1977 // fold select C, X, 1 -> ~C | X 1978 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1979 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1980 AddToWorkList(XORNode.Val); 1981 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1982 } 1983 // fold select C, X, 0 -> C & X 1984 // FIXME: this should check for C type == X type, not i1? 1985 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1986 return DAG.getNode(ISD::AND, VT, N0, N1); 1987 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1988 if (MVT::i1 == VT && N0 == N1) 1989 return DAG.getNode(ISD::OR, VT, N0, N2); 1990 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1991 if (MVT::i1 == VT && N0 == N2) 1992 return DAG.getNode(ISD::AND, VT, N0, N1); 1993 1994 // If we can fold this based on the true/false value, do so. 1995 if (SimplifySelectOps(N, N1, N2)) 1996 return SDOperand(N, 0); // Don't revisit N. 1997 1998 // fold selects based on a setcc into other things, such as min/max/abs 1999 if (N0.getOpcode() == ISD::SETCC) 2000 // FIXME: 2001 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2002 // having to say they don't support SELECT_CC on every type the DAG knows 2003 // about, since there is no way to mark an opcode illegal at all value types 2004 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2005 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2006 N1, N2, N0.getOperand(2)); 2007 else 2008 return SimplifySelect(N0, N1, N2); 2009 return SDOperand(); 2010} 2011 2012SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2013 SDOperand N0 = N->getOperand(0); 2014 SDOperand N1 = N->getOperand(1); 2015 SDOperand N2 = N->getOperand(2); 2016 SDOperand N3 = N->getOperand(3); 2017 SDOperand N4 = N->getOperand(4); 2018 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2019 2020 // fold select_cc lhs, rhs, x, x, cc -> x 2021 if (N2 == N3) 2022 return N2; 2023 2024 // Determine if the condition we're dealing with is constant 2025 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2026 if (SCC.Val) AddToWorkList(SCC.Val); 2027 2028 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2029 if (SCCC->getValue()) 2030 return N2; // cond always true -> true val 2031 else 2032 return N3; // cond always false -> false val 2033 } 2034 2035 // Fold to a simpler select_cc 2036 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2037 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2038 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2039 SCC.getOperand(2)); 2040 2041 // If we can fold this based on the true/false value, do so. 2042 if (SimplifySelectOps(N, N2, N3)) 2043 return SDOperand(N, 0); // Don't revisit N. 2044 2045 // fold select_cc into other things, such as min/max/abs 2046 return SimplifySelectCC(N0, N1, N2, N3, CC); 2047} 2048 2049SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2050 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2051 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2052} 2053 2054SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2055 SDOperand N0 = N->getOperand(0); 2056 MVT::ValueType VT = N->getValueType(0); 2057 2058 // fold (sext c1) -> c1 2059 if (isa<ConstantSDNode>(N0)) 2060 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2061 2062 // fold (sext (sext x)) -> (sext x) 2063 // fold (sext (aext x)) -> (sext x) 2064 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2065 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2066 2067 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2068 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2069 if (N0.getOpcode() == ISD::TRUNCATE) { 2070 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2071 if (NarrowLoad.Val) { 2072 if (NarrowLoad.Val != N0.Val) 2073 CombineTo(N0.Val, NarrowLoad); 2074 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2075 } 2076 } 2077 2078 // See if the value being truncated is already sign extended. If so, just 2079 // eliminate the trunc/sext pair. 2080 if (N0.getOpcode() == ISD::TRUNCATE) { 2081 SDOperand Op = N0.getOperand(0); 2082 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2083 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2084 unsigned DestBits = MVT::getSizeInBits(VT); 2085 unsigned NumSignBits = TLI.ComputeNumSignBits(Op); 2086 2087 if (OpBits == DestBits) { 2088 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2089 // bits, it is already ready. 2090 if (NumSignBits > DestBits-MidBits) 2091 return Op; 2092 } else if (OpBits < DestBits) { 2093 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2094 // bits, just sext from i32. 2095 if (NumSignBits > OpBits-MidBits) 2096 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2097 } else { 2098 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2099 // bits, just truncate to i32. 2100 if (NumSignBits > OpBits-MidBits) 2101 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2102 } 2103 2104 // fold (sext (truncate x)) -> (sextinreg x). 2105 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2106 N0.getValueType())) { 2107 if (Op.getValueType() < VT) 2108 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2109 else if (Op.getValueType() > VT) 2110 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2111 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2112 DAG.getValueType(N0.getValueType())); 2113 } 2114 } 2115 2116 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2117 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2118 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2119 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2120 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2121 LN0->getBasePtr(), LN0->getSrcValue(), 2122 LN0->getSrcValueOffset(), 2123 N0.getValueType()); 2124 CombineTo(N, ExtLoad); 2125 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2126 ExtLoad.getValue(1)); 2127 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2128 } 2129 2130 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2131 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2132 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2133 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2134 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2135 MVT::ValueType EVT = LN0->getLoadedVT(); 2136 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2137 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2138 LN0->getBasePtr(), LN0->getSrcValue(), 2139 LN0->getSrcValueOffset(), EVT); 2140 CombineTo(N, ExtLoad); 2141 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2142 ExtLoad.getValue(1)); 2143 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2144 } 2145 } 2146 2147 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2148 if (N0.getOpcode() == ISD::SETCC) { 2149 SDOperand SCC = 2150 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2151 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2152 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2153 if (SCC.Val) return SCC; 2154 } 2155 2156 return SDOperand(); 2157} 2158 2159SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2160 SDOperand N0 = N->getOperand(0); 2161 MVT::ValueType VT = N->getValueType(0); 2162 2163 // fold (zext c1) -> c1 2164 if (isa<ConstantSDNode>(N0)) 2165 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2166 // fold (zext (zext x)) -> (zext x) 2167 // fold (zext (aext x)) -> (zext x) 2168 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2169 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2170 2171 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2172 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2173 if (N0.getOpcode() == ISD::TRUNCATE) { 2174 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2175 if (NarrowLoad.Val) { 2176 if (NarrowLoad.Val != N0.Val) 2177 CombineTo(N0.Val, NarrowLoad); 2178 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2179 } 2180 } 2181 2182 // fold (zext (truncate x)) -> (and x, mask) 2183 if (N0.getOpcode() == ISD::TRUNCATE && 2184 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2185 SDOperand Op = N0.getOperand(0); 2186 if (Op.getValueType() < VT) { 2187 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2188 } else if (Op.getValueType() > VT) { 2189 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2190 } 2191 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2192 } 2193 2194 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2195 if (N0.getOpcode() == ISD::AND && 2196 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2197 N0.getOperand(1).getOpcode() == ISD::Constant) { 2198 SDOperand X = N0.getOperand(0).getOperand(0); 2199 if (X.getValueType() < VT) { 2200 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2201 } else if (X.getValueType() > VT) { 2202 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2203 } 2204 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2205 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2206 } 2207 2208 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2209 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2210 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2211 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2212 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2213 LN0->getBasePtr(), LN0->getSrcValue(), 2214 LN0->getSrcValueOffset(), 2215 N0.getValueType()); 2216 CombineTo(N, ExtLoad); 2217 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2218 ExtLoad.getValue(1)); 2219 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2220 } 2221 2222 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2223 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2224 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2225 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2226 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2227 MVT::ValueType EVT = LN0->getLoadedVT(); 2228 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2229 LN0->getBasePtr(), LN0->getSrcValue(), 2230 LN0->getSrcValueOffset(), EVT); 2231 CombineTo(N, ExtLoad); 2232 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2233 ExtLoad.getValue(1)); 2234 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2235 } 2236 2237 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2238 if (N0.getOpcode() == ISD::SETCC) { 2239 SDOperand SCC = 2240 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2241 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2242 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2243 if (SCC.Val) return SCC; 2244 } 2245 2246 return SDOperand(); 2247} 2248 2249SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2250 SDOperand N0 = N->getOperand(0); 2251 MVT::ValueType VT = N->getValueType(0); 2252 2253 // fold (aext c1) -> c1 2254 if (isa<ConstantSDNode>(N0)) 2255 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2256 // fold (aext (aext x)) -> (aext x) 2257 // fold (aext (zext x)) -> (zext x) 2258 // fold (aext (sext x)) -> (sext x) 2259 if (N0.getOpcode() == ISD::ANY_EXTEND || 2260 N0.getOpcode() == ISD::ZERO_EXTEND || 2261 N0.getOpcode() == ISD::SIGN_EXTEND) 2262 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2263 2264 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2265 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2266 if (N0.getOpcode() == ISD::TRUNCATE) { 2267 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2268 if (NarrowLoad.Val) { 2269 if (NarrowLoad.Val != N0.Val) 2270 CombineTo(N0.Val, NarrowLoad); 2271 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2272 } 2273 } 2274 2275 // fold (aext (truncate x)) 2276 if (N0.getOpcode() == ISD::TRUNCATE) { 2277 SDOperand TruncOp = N0.getOperand(0); 2278 if (TruncOp.getValueType() == VT) 2279 return TruncOp; // x iff x size == zext size. 2280 if (TruncOp.getValueType() > VT) 2281 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2282 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2283 } 2284 2285 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2286 if (N0.getOpcode() == ISD::AND && 2287 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2288 N0.getOperand(1).getOpcode() == ISD::Constant) { 2289 SDOperand X = N0.getOperand(0).getOperand(0); 2290 if (X.getValueType() < VT) { 2291 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2292 } else if (X.getValueType() > VT) { 2293 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2294 } 2295 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2296 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2297 } 2298 2299 // fold (aext (load x)) -> (aext (truncate (extload x))) 2300 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2301 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2302 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2303 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2304 LN0->getBasePtr(), LN0->getSrcValue(), 2305 LN0->getSrcValueOffset(), 2306 N0.getValueType()); 2307 CombineTo(N, ExtLoad); 2308 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2309 ExtLoad.getValue(1)); 2310 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2311 } 2312 2313 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2314 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2315 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2316 if (N0.getOpcode() == ISD::LOAD && 2317 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2318 N0.hasOneUse()) { 2319 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2320 MVT::ValueType EVT = LN0->getLoadedVT(); 2321 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2322 LN0->getChain(), LN0->getBasePtr(), 2323 LN0->getSrcValue(), 2324 LN0->getSrcValueOffset(), EVT); 2325 CombineTo(N, ExtLoad); 2326 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2327 ExtLoad.getValue(1)); 2328 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2329 } 2330 2331 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2332 if (N0.getOpcode() == ISD::SETCC) { 2333 SDOperand SCC = 2334 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2335 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2336 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2337 if (SCC.Val) 2338 return SCC; 2339 } 2340 2341 return SDOperand(); 2342} 2343 2344/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2345/// bits and then truncated to a narrower type and where N is a multiple 2346/// of number of bits of the narrower type, transform it to a narrower load 2347/// from address + N / num of bits of new type. If the result is to be 2348/// extended, also fold the extension to form a extending load. 2349SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2350 unsigned Opc = N->getOpcode(); 2351 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2352 SDOperand N0 = N->getOperand(0); 2353 MVT::ValueType VT = N->getValueType(0); 2354 MVT::ValueType EVT = N->getValueType(0); 2355 2356 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2357 // extended to VT. 2358 if (Opc == ISD::SIGN_EXTEND_INREG) { 2359 ExtType = ISD::SEXTLOAD; 2360 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2361 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2362 return SDOperand(); 2363 } 2364 2365 unsigned EVTBits = MVT::getSizeInBits(EVT); 2366 unsigned ShAmt = 0; 2367 bool CombineSRL = false; 2368 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2369 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2370 ShAmt = N01->getValue(); 2371 // Is the shift amount a multiple of size of VT? 2372 if ((ShAmt & (EVTBits-1)) == 0) { 2373 N0 = N0.getOperand(0); 2374 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2375 return SDOperand(); 2376 CombineSRL = true; 2377 } 2378 } 2379 } 2380 2381 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2382 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2383 // zero extended form: by shrinking the load, we lose track of the fact 2384 // that it is already zero extended. 2385 // FIXME: This should be reevaluated. 2386 VT != MVT::i1) { 2387 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 2388 "Cannot truncate to larger type!"); 2389 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2390 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2391 // For big endian targets, we need to adjust the offset to the pointer to 2392 // load the correct bytes. 2393 if (!TLI.isLittleEndian()) 2394 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; 2395 uint64_t PtrOff = ShAmt / 8; 2396 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2397 DAG.getConstant(PtrOff, PtrType)); 2398 AddToWorkList(NewPtr.Val); 2399 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 2400 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 2401 LN0->getSrcValue(), LN0->getSrcValueOffset()) 2402 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 2403 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT); 2404 AddToWorkList(N); 2405 if (CombineSRL) { 2406 std::vector<SDNode*> NowDead; 2407 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead); 2408 CombineTo(N->getOperand(0).Val, Load); 2409 } else 2410 CombineTo(N0.Val, Load, Load.getValue(1)); 2411 if (ShAmt) { 2412 if (Opc == ISD::SIGN_EXTEND_INREG) 2413 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 2414 else 2415 return DAG.getNode(Opc, VT, Load); 2416 } 2417 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2418 } 2419 2420 return SDOperand(); 2421} 2422 2423 2424SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2425 SDOperand N0 = N->getOperand(0); 2426 SDOperand N1 = N->getOperand(1); 2427 MVT::ValueType VT = N->getValueType(0); 2428 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2429 unsigned EVTBits = MVT::getSizeInBits(EVT); 2430 2431 // fold (sext_in_reg c1) -> c1 2432 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2433 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2434 2435 // If the input is already sign extended, just drop the extension. 2436 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2437 return N0; 2438 2439 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2440 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2441 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2442 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2443 } 2444 2445 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 2446 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2447 return DAG.getZeroExtendInReg(N0, EVT); 2448 2449 // fold operands of sext_in_reg based on knowledge that the top bits are not 2450 // demanded. 2451 if (SimplifyDemandedBits(SDOperand(N, 0))) 2452 return SDOperand(N, 0); 2453 2454 // fold (sext_in_reg (load x)) -> (smaller sextload x) 2455 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 2456 SDOperand NarrowLoad = ReduceLoadWidth(N); 2457 if (NarrowLoad.Val) 2458 return NarrowLoad; 2459 2460 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2461 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2462 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2463 if (N0.getOpcode() == ISD::SRL) { 2464 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2465 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2466 // We can turn this into an SRA iff the input to the SRL is already sign 2467 // extended enough. 2468 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 2469 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2470 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2471 } 2472 } 2473 2474 // fold (sext_inreg (extload x)) -> (sextload x) 2475 if (ISD::isEXTLoad(N0.Val) && 2476 ISD::isUNINDEXEDLoad(N0.Val) && 2477 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2478 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2479 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2480 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2481 LN0->getBasePtr(), LN0->getSrcValue(), 2482 LN0->getSrcValueOffset(), EVT); 2483 CombineTo(N, ExtLoad); 2484 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2485 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2486 } 2487 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2488 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2489 N0.hasOneUse() && 2490 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2491 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2492 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2493 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2494 LN0->getBasePtr(), LN0->getSrcValue(), 2495 LN0->getSrcValueOffset(), EVT); 2496 CombineTo(N, ExtLoad); 2497 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2498 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2499 } 2500 return SDOperand(); 2501} 2502 2503SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2504 SDOperand N0 = N->getOperand(0); 2505 MVT::ValueType VT = N->getValueType(0); 2506 2507 // noop truncate 2508 if (N0.getValueType() == N->getValueType(0)) 2509 return N0; 2510 // fold (truncate c1) -> c1 2511 if (isa<ConstantSDNode>(N0)) 2512 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2513 // fold (truncate (truncate x)) -> (truncate x) 2514 if (N0.getOpcode() == ISD::TRUNCATE) 2515 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2516 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2517 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2518 N0.getOpcode() == ISD::ANY_EXTEND) { 2519 if (N0.getOperand(0).getValueType() < VT) 2520 // if the source is smaller than the dest, we still need an extend 2521 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2522 else if (N0.getOperand(0).getValueType() > VT) 2523 // if the source is larger than the dest, than we just need the truncate 2524 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2525 else 2526 // if the source and dest are the same type, we can drop both the extend 2527 // and the truncate 2528 return N0.getOperand(0); 2529 } 2530 2531 // fold (truncate (load x)) -> (smaller load x) 2532 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 2533 return ReduceLoadWidth(N); 2534} 2535 2536SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2537 SDOperand N0 = N->getOperand(0); 2538 MVT::ValueType VT = N->getValueType(0); 2539 2540 // If the input is a constant, let getNode() fold it. 2541 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2542 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2543 if (Res.Val != N) return Res; 2544 } 2545 2546 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2547 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2548 2549 // fold (conv (load x)) -> (load (conv*)x) 2550 // FIXME: These xforms need to know that the resultant load doesn't need a 2551 // higher alignment than the original! 2552 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) { 2553 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2554 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 2555 LN0->getSrcValue(), LN0->getSrcValueOffset()); 2556 AddToWorkList(N); 2557 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2558 Load.getValue(1)); 2559 return Load; 2560 } 2561 2562 return SDOperand(); 2563} 2564 2565SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2566 SDOperand N0 = N->getOperand(0); 2567 MVT::ValueType VT = N->getValueType(0); 2568 2569 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2570 // First check to see if this is all constant. 2571 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2572 VT == MVT::Vector) { 2573 bool isSimple = true; 2574 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2575 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2576 N0.getOperand(i).getOpcode() != ISD::Constant && 2577 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2578 isSimple = false; 2579 break; 2580 } 2581 2582 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2583 if (isSimple && !MVT::isVector(DestEltVT)) { 2584 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2585 } 2586 } 2587 2588 return SDOperand(); 2589} 2590 2591/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2592/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2593/// destination element value type. 2594SDOperand DAGCombiner:: 2595ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2596 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2597 2598 // If this is already the right type, we're done. 2599 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2600 2601 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2602 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2603 2604 // If this is a conversion of N elements of one type to N elements of another 2605 // type, convert each element. This handles FP<->INT cases. 2606 if (SrcBitSize == DstBitSize) { 2607 SmallVector<SDOperand, 8> Ops; 2608 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2609 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2610 AddToWorkList(Ops.back().Val); 2611 } 2612 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2613 Ops.push_back(DAG.getValueType(DstEltVT)); 2614 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2615 } 2616 2617 // Otherwise, we're growing or shrinking the elements. To avoid having to 2618 // handle annoying details of growing/shrinking FP values, we convert them to 2619 // int first. 2620 if (MVT::isFloatingPoint(SrcEltVT)) { 2621 // Convert the input float vector to a int vector where the elements are the 2622 // same sizes. 2623 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2624 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2625 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2626 SrcEltVT = IntVT; 2627 } 2628 2629 // Now we know the input is an integer vector. If the output is a FP type, 2630 // convert to integer first, then to FP of the right size. 2631 if (MVT::isFloatingPoint(DstEltVT)) { 2632 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2633 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2634 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2635 2636 // Next, convert to FP elements of the same size. 2637 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2638 } 2639 2640 // Okay, we know the src/dst types are both integers of differing types. 2641 // Handling growing first. 2642 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2643 if (SrcBitSize < DstBitSize) { 2644 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2645 2646 SmallVector<SDOperand, 8> Ops; 2647 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2648 i += NumInputsPerOutput) { 2649 bool isLE = TLI.isLittleEndian(); 2650 uint64_t NewBits = 0; 2651 bool EltIsUndef = true; 2652 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2653 // Shift the previously computed bits over. 2654 NewBits <<= SrcBitSize; 2655 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2656 if (Op.getOpcode() == ISD::UNDEF) continue; 2657 EltIsUndef = false; 2658 2659 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2660 } 2661 2662 if (EltIsUndef) 2663 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2664 else 2665 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2666 } 2667 2668 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2669 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2670 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2671 } 2672 2673 // Finally, this must be the case where we are shrinking elements: each input 2674 // turns into multiple outputs. 2675 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2676 SmallVector<SDOperand, 8> Ops; 2677 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2678 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2679 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2680 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2681 continue; 2682 } 2683 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2684 2685 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2686 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2687 OpVal >>= DstBitSize; 2688 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2689 } 2690 2691 // For big endian targets, swap the order of the pieces of each element. 2692 if (!TLI.isLittleEndian()) 2693 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2694 } 2695 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2696 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2697 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2698} 2699 2700 2701 2702SDOperand DAGCombiner::visitFADD(SDNode *N) { 2703 SDOperand N0 = N->getOperand(0); 2704 SDOperand N1 = N->getOperand(1); 2705 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2706 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2707 MVT::ValueType VT = N->getValueType(0); 2708 2709 // fold (fadd c1, c2) -> c1+c2 2710 if (N0CFP && N1CFP) 2711 return DAG.getNode(ISD::FADD, VT, N0, N1); 2712 // canonicalize constant to RHS 2713 if (N0CFP && !N1CFP) 2714 return DAG.getNode(ISD::FADD, VT, N1, N0); 2715 // fold (A + (-B)) -> A-B 2716 if (N1.getOpcode() == ISD::FNEG) 2717 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2718 // fold ((-A) + B) -> B-A 2719 if (N0.getOpcode() == ISD::FNEG) 2720 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2721 2722 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 2723 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 2724 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2725 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 2726 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 2727 2728 return SDOperand(); 2729} 2730 2731SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2732 SDOperand N0 = N->getOperand(0); 2733 SDOperand N1 = N->getOperand(1); 2734 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2735 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2736 MVT::ValueType VT = N->getValueType(0); 2737 2738 // fold (fsub c1, c2) -> c1-c2 2739 if (N0CFP && N1CFP) 2740 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2741 // fold (A-(-B)) -> A+B 2742 if (N1.getOpcode() == ISD::FNEG) 2743 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2744 return SDOperand(); 2745} 2746 2747SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2748 SDOperand N0 = N->getOperand(0); 2749 SDOperand N1 = N->getOperand(1); 2750 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2751 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2752 MVT::ValueType VT = N->getValueType(0); 2753 2754 // fold (fmul c1, c2) -> c1*c2 2755 if (N0CFP && N1CFP) 2756 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2757 // canonicalize constant to RHS 2758 if (N0CFP && !N1CFP) 2759 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2760 // fold (fmul X, 2.0) -> (fadd X, X) 2761 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2762 return DAG.getNode(ISD::FADD, VT, N0, N0); 2763 2764 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 2765 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 2766 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2767 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 2768 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 2769 2770 return SDOperand(); 2771} 2772 2773SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2774 SDOperand N0 = N->getOperand(0); 2775 SDOperand N1 = N->getOperand(1); 2776 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2777 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2778 MVT::ValueType VT = N->getValueType(0); 2779 2780 // fold (fdiv c1, c2) -> c1/c2 2781 if (N0CFP && N1CFP) 2782 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2783 return SDOperand(); 2784} 2785 2786SDOperand DAGCombiner::visitFREM(SDNode *N) { 2787 SDOperand N0 = N->getOperand(0); 2788 SDOperand N1 = N->getOperand(1); 2789 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2790 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2791 MVT::ValueType VT = N->getValueType(0); 2792 2793 // fold (frem c1, c2) -> fmod(c1,c2) 2794 if (N0CFP && N1CFP) 2795 return DAG.getNode(ISD::FREM, VT, N0, N1); 2796 return SDOperand(); 2797} 2798 2799SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2800 SDOperand N0 = N->getOperand(0); 2801 SDOperand N1 = N->getOperand(1); 2802 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2803 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2804 MVT::ValueType VT = N->getValueType(0); 2805 2806 if (N0CFP && N1CFP) // Constant fold 2807 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2808 2809 if (N1CFP) { 2810 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2811 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2812 union { 2813 double d; 2814 int64_t i; 2815 } u; 2816 u.d = N1CFP->getValue(); 2817 if (u.i >= 0) 2818 return DAG.getNode(ISD::FABS, VT, N0); 2819 else 2820 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2821 } 2822 2823 // copysign(fabs(x), y) -> copysign(x, y) 2824 // copysign(fneg(x), y) -> copysign(x, y) 2825 // copysign(copysign(x,z), y) -> copysign(x, y) 2826 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2827 N0.getOpcode() == ISD::FCOPYSIGN) 2828 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2829 2830 // copysign(x, abs(y)) -> abs(x) 2831 if (N1.getOpcode() == ISD::FABS) 2832 return DAG.getNode(ISD::FABS, VT, N0); 2833 2834 // copysign(x, copysign(y,z)) -> copysign(x, z) 2835 if (N1.getOpcode() == ISD::FCOPYSIGN) 2836 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2837 2838 // copysign(x, fp_extend(y)) -> copysign(x, y) 2839 // copysign(x, fp_round(y)) -> copysign(x, y) 2840 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2841 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2842 2843 return SDOperand(); 2844} 2845 2846 2847 2848SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2849 SDOperand N0 = N->getOperand(0); 2850 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2851 MVT::ValueType VT = N->getValueType(0); 2852 2853 // fold (sint_to_fp c1) -> c1fp 2854 if (N0C) 2855 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2856 return SDOperand(); 2857} 2858 2859SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2860 SDOperand N0 = N->getOperand(0); 2861 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2862 MVT::ValueType VT = N->getValueType(0); 2863 2864 // fold (uint_to_fp c1) -> c1fp 2865 if (N0C) 2866 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2867 return SDOperand(); 2868} 2869 2870SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2871 SDOperand N0 = N->getOperand(0); 2872 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2873 MVT::ValueType VT = N->getValueType(0); 2874 2875 // fold (fp_to_sint c1fp) -> c1 2876 if (N0CFP) 2877 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2878 return SDOperand(); 2879} 2880 2881SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2882 SDOperand N0 = N->getOperand(0); 2883 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2884 MVT::ValueType VT = N->getValueType(0); 2885 2886 // fold (fp_to_uint c1fp) -> c1 2887 if (N0CFP) 2888 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2889 return SDOperand(); 2890} 2891 2892SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2893 SDOperand N0 = N->getOperand(0); 2894 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2895 MVT::ValueType VT = N->getValueType(0); 2896 2897 // fold (fp_round c1fp) -> c1fp 2898 if (N0CFP) 2899 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2900 2901 // fold (fp_round (fp_extend x)) -> x 2902 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2903 return N0.getOperand(0); 2904 2905 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2906 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2907 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2908 AddToWorkList(Tmp.Val); 2909 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2910 } 2911 2912 return SDOperand(); 2913} 2914 2915SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2916 SDOperand N0 = N->getOperand(0); 2917 MVT::ValueType VT = N->getValueType(0); 2918 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2919 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2920 2921 // fold (fp_round_inreg c1fp) -> c1fp 2922 if (N0CFP) { 2923 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2924 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2925 } 2926 return SDOperand(); 2927} 2928 2929SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2930 SDOperand N0 = N->getOperand(0); 2931 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2932 MVT::ValueType VT = N->getValueType(0); 2933 2934 // fold (fp_extend c1fp) -> c1fp 2935 if (N0CFP) 2936 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2937 2938 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2939 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2940 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2941 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2942 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2943 LN0->getBasePtr(), LN0->getSrcValue(), 2944 LN0->getSrcValueOffset(), 2945 N0.getValueType()); 2946 CombineTo(N, ExtLoad); 2947 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2948 ExtLoad.getValue(1)); 2949 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2950 } 2951 2952 2953 return SDOperand(); 2954} 2955 2956SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2957 SDOperand N0 = N->getOperand(0); 2958 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2959 MVT::ValueType VT = N->getValueType(0); 2960 2961 // fold (fneg c1) -> -c1 2962 if (N0CFP) 2963 return DAG.getNode(ISD::FNEG, VT, N0); 2964 // fold (fneg (sub x, y)) -> (sub y, x) 2965 if (N0.getOpcode() == ISD::SUB) 2966 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2967 // fold (fneg (fneg x)) -> x 2968 if (N0.getOpcode() == ISD::FNEG) 2969 return N0.getOperand(0); 2970 return SDOperand(); 2971} 2972 2973SDOperand DAGCombiner::visitFABS(SDNode *N) { 2974 SDOperand N0 = N->getOperand(0); 2975 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2976 MVT::ValueType VT = N->getValueType(0); 2977 2978 // fold (fabs c1) -> fabs(c1) 2979 if (N0CFP) 2980 return DAG.getNode(ISD::FABS, VT, N0); 2981 // fold (fabs (fabs x)) -> (fabs x) 2982 if (N0.getOpcode() == ISD::FABS) 2983 return N->getOperand(0); 2984 // fold (fabs (fneg x)) -> (fabs x) 2985 // fold (fabs (fcopysign x, y)) -> (fabs x) 2986 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2987 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2988 2989 return SDOperand(); 2990} 2991 2992SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2993 SDOperand Chain = N->getOperand(0); 2994 SDOperand N1 = N->getOperand(1); 2995 SDOperand N2 = N->getOperand(2); 2996 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2997 2998 // never taken branch, fold to chain 2999 if (N1C && N1C->isNullValue()) 3000 return Chain; 3001 // unconditional branch 3002 if (N1C && N1C->getValue() == 1) 3003 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3004 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3005 // on the target. 3006 if (N1.getOpcode() == ISD::SETCC && 3007 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3008 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3009 N1.getOperand(0), N1.getOperand(1), N2); 3010 } 3011 return SDOperand(); 3012} 3013 3014// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3015// 3016SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3017 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3018 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3019 3020 // Use SimplifySetCC to simplify SETCC's. 3021 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3022 if (Simp.Val) AddToWorkList(Simp.Val); 3023 3024 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3025 3026 // fold br_cc true, dest -> br dest (unconditional branch) 3027 if (SCCC && SCCC->getValue()) 3028 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3029 N->getOperand(4)); 3030 // fold br_cc false, dest -> unconditional fall through 3031 if (SCCC && SCCC->isNullValue()) 3032 return N->getOperand(0); 3033 3034 // fold to a simpler setcc 3035 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3036 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3037 Simp.getOperand(2), Simp.getOperand(0), 3038 Simp.getOperand(1), N->getOperand(4)); 3039 return SDOperand(); 3040} 3041 3042 3043/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3044/// pre-indexed load / store when the base pointer is a add or subtract 3045/// and it has other uses besides the load / store. After the 3046/// transformation, the new indexed load / store has effectively folded 3047/// the add / subtract in and all of its other uses are redirected to the 3048/// new load / store. 3049bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3050 if (!AfterLegalize) 3051 return false; 3052 3053 bool isLoad = true; 3054 SDOperand Ptr; 3055 MVT::ValueType VT; 3056 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3057 if (LD->getAddressingMode() != ISD::UNINDEXED) 3058 return false; 3059 VT = LD->getLoadedVT(); 3060 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3061 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3062 return false; 3063 Ptr = LD->getBasePtr(); 3064 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3065 if (ST->getAddressingMode() != ISD::UNINDEXED) 3066 return false; 3067 VT = ST->getStoredVT(); 3068 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3069 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3070 return false; 3071 Ptr = ST->getBasePtr(); 3072 isLoad = false; 3073 } else 3074 return false; 3075 3076 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3077 // out. There is no reason to make this a preinc/predec. 3078 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3079 Ptr.Val->hasOneUse()) 3080 return false; 3081 3082 // Ask the target to do addressing mode selection. 3083 SDOperand BasePtr; 3084 SDOperand Offset; 3085 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3086 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3087 return false; 3088 3089 // Try turning it into a pre-indexed load / store except when: 3090 // 1) The base is a frame index. 3091 // 2) If N is a store and the ptr is either the same as or is a 3092 // predecessor of the value being stored. 3093 // 3) Another use of base ptr is a predecessor of N. If ptr is folded 3094 // that would create a cycle. 3095 // 4) All uses are load / store ops that use it as base ptr. 3096 3097 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3098 // (plus the implicit offset) to a register to preinc anyway. 3099 if (isa<FrameIndexSDNode>(BasePtr)) 3100 return false; 3101 3102 // Check #2. 3103 if (!isLoad) { 3104 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3105 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val)) 3106 return false; 3107 } 3108 3109 // Now check for #2 and #3. 3110 bool RealUse = false; 3111 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3112 E = Ptr.Val->use_end(); I != E; ++I) { 3113 SDNode *Use = *I; 3114 if (Use == N) 3115 continue; 3116 if (Use->isPredecessor(N)) 3117 return false; 3118 3119 if (!((Use->getOpcode() == ISD::LOAD && 3120 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3121 (Use->getOpcode() == ISD::STORE) && 3122 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3123 RealUse = true; 3124 } 3125 if (!RealUse) 3126 return false; 3127 3128 SDOperand Result; 3129 if (isLoad) 3130 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3131 else 3132 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3133 ++PreIndexedNodes; 3134 ++NodesCombined; 3135 DOUT << "\nReplacing.4 "; DEBUG(N->dump()); 3136 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3137 DOUT << '\n'; 3138 std::vector<SDNode*> NowDead; 3139 if (isLoad) { 3140 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3141 NowDead); 3142 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3143 NowDead); 3144 } else { 3145 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3146 NowDead); 3147 } 3148 3149 // Nodes can end up on the worklist more than once. Make sure we do 3150 // not process a node that has been replaced. 3151 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3152 removeFromWorkList(NowDead[i]); 3153 // Finally, since the node is now dead, remove it from the graph. 3154 DAG.DeleteNode(N); 3155 3156 // Replace the uses of Ptr with uses of the updated base value. 3157 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3158 NowDead); 3159 removeFromWorkList(Ptr.Val); 3160 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3161 removeFromWorkList(NowDead[i]); 3162 DAG.DeleteNode(Ptr.Val); 3163 3164 return true; 3165} 3166 3167/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3168/// add / sub of the base pointer node into a post-indexed load / store. 3169/// The transformation folded the add / subtract into the new indexed 3170/// load / store effectively and all of its uses are redirected to the 3171/// new load / store. 3172bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3173 if (!AfterLegalize) 3174 return false; 3175 3176 bool isLoad = true; 3177 SDOperand Ptr; 3178 MVT::ValueType VT; 3179 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3180 if (LD->getAddressingMode() != ISD::UNINDEXED) 3181 return false; 3182 VT = LD->getLoadedVT(); 3183 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3184 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3185 return false; 3186 Ptr = LD->getBasePtr(); 3187 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3188 if (ST->getAddressingMode() != ISD::UNINDEXED) 3189 return false; 3190 VT = ST->getStoredVT(); 3191 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3192 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3193 return false; 3194 Ptr = ST->getBasePtr(); 3195 isLoad = false; 3196 } else 3197 return false; 3198 3199 if (Ptr.Val->hasOneUse()) 3200 return false; 3201 3202 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3203 E = Ptr.Val->use_end(); I != E; ++I) { 3204 SDNode *Op = *I; 3205 if (Op == N || 3206 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3207 continue; 3208 3209 SDOperand BasePtr; 3210 SDOperand Offset; 3211 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3212 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3213 if (Ptr == Offset) 3214 std::swap(BasePtr, Offset); 3215 if (Ptr != BasePtr) 3216 continue; 3217 3218 // Try turning it into a post-indexed load / store except when 3219 // 1) All uses are load / store ops that use it as base ptr. 3220 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3221 // nor a successor of N. Otherwise, if Op is folded that would 3222 // create a cycle. 3223 3224 // Check for #1. 3225 bool TryNext = false; 3226 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3227 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3228 SDNode *Use = *II; 3229 if (Use == Ptr.Val) 3230 continue; 3231 3232 // If all the uses are load / store addresses, then don't do the 3233 // transformation. 3234 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3235 bool RealUse = false; 3236 for (SDNode::use_iterator III = Use->use_begin(), 3237 EEE = Use->use_end(); III != EEE; ++III) { 3238 SDNode *UseUse = *III; 3239 if (!((UseUse->getOpcode() == ISD::LOAD && 3240 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3241 (UseUse->getOpcode() == ISD::STORE) && 3242 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3243 RealUse = true; 3244 } 3245 3246 if (!RealUse) { 3247 TryNext = true; 3248 break; 3249 } 3250 } 3251 } 3252 if (TryNext) 3253 continue; 3254 3255 // Check for #2 3256 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3257 SDOperand Result = isLoad 3258 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3259 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3260 ++PostIndexedNodes; 3261 ++NodesCombined; 3262 DOUT << "\nReplacing.5 "; DEBUG(N->dump()); 3263 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3264 DOUT << '\n'; 3265 std::vector<SDNode*> NowDead; 3266 if (isLoad) { 3267 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3268 NowDead); 3269 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3270 NowDead); 3271 } else { 3272 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3273 NowDead); 3274 } 3275 3276 // Nodes can end up on the worklist more than once. Make sure we do 3277 // not process a node that has been replaced. 3278 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3279 removeFromWorkList(NowDead[i]); 3280 // Finally, since the node is now dead, remove it from the graph. 3281 DAG.DeleteNode(N); 3282 3283 // Replace the uses of Use with uses of the updated base value. 3284 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3285 Result.getValue(isLoad ? 1 : 0), 3286 NowDead); 3287 removeFromWorkList(Op); 3288 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3289 removeFromWorkList(NowDead[i]); 3290 DAG.DeleteNode(Op); 3291 3292 return true; 3293 } 3294 } 3295 } 3296 return false; 3297} 3298 3299 3300SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3301 LoadSDNode *LD = cast<LoadSDNode>(N); 3302 SDOperand Chain = LD->getChain(); 3303 SDOperand Ptr = LD->getBasePtr(); 3304 3305 // If there are no uses of the loaded value, change uses of the chain value 3306 // into uses of the chain input (i.e. delete the dead load). 3307 if (N->hasNUsesOfValue(0, 0)) 3308 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3309 3310 // If this load is directly stored, replace the load value with the stored 3311 // value. 3312 // TODO: Handle store large -> read small portion. 3313 // TODO: Handle TRUNCSTORE/LOADEXT 3314 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3315 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3316 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3317 if (PrevST->getBasePtr() == Ptr && 3318 PrevST->getValue().getValueType() == N->getValueType(0)) 3319 return CombineTo(N, Chain.getOperand(1), Chain); 3320 } 3321 } 3322 3323 if (CombinerAA) { 3324 // Walk up chain skipping non-aliasing memory nodes. 3325 SDOperand BetterChain = FindBetterChain(N, Chain); 3326 3327 // If there is a better chain. 3328 if (Chain != BetterChain) { 3329 SDOperand ReplLoad; 3330 3331 // Replace the chain to void dependency. 3332 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3333 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3334 LD->getSrcValue(), LD->getSrcValueOffset()); 3335 } else { 3336 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3337 LD->getValueType(0), 3338 BetterChain, Ptr, LD->getSrcValue(), 3339 LD->getSrcValueOffset(), 3340 LD->getLoadedVT()); 3341 } 3342 3343 // Create token factor to keep old chain connected. 3344 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3345 Chain, ReplLoad.getValue(1)); 3346 3347 // Replace uses with load result and token factor. Don't add users 3348 // to work list. 3349 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3350 } 3351 } 3352 3353 // Try transforming N to an indexed load. 3354 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3355 return SDOperand(N, 0); 3356 3357 return SDOperand(); 3358} 3359 3360SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3361 StoreSDNode *ST = cast<StoreSDNode>(N); 3362 SDOperand Chain = ST->getChain(); 3363 SDOperand Value = ST->getValue(); 3364 SDOperand Ptr = ST->getBasePtr(); 3365 3366 // If this is a store of a bit convert, store the input value. 3367 // FIXME: This needs to know that the resultant store does not need a 3368 // higher alignment than the original. 3369 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) { 3370 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3371 ST->getSrcValueOffset()); 3372 } 3373 3374 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3375 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3376 if (Value.getOpcode() != ISD::TargetConstantFP) { 3377 SDOperand Tmp; 3378 switch (CFP->getValueType(0)) { 3379 default: assert(0 && "Unknown FP type"); 3380 case MVT::f32: 3381 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3382 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 3383 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3384 ST->getSrcValueOffset()); 3385 } 3386 break; 3387 case MVT::f64: 3388 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3389 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 3390 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3391 ST->getSrcValueOffset()); 3392 } else if (TLI.isTypeLegal(MVT::i32)) { 3393 // Many FP stores are not make apparent until after legalize, e.g. for 3394 // argument passing. Since this is so common, custom legalize the 3395 // 64-bit integer store into two 32-bit stores. 3396 uint64_t Val = DoubleToBits(CFP->getValue()); 3397 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3398 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3399 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3400 3401 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3402 ST->getSrcValueOffset()); 3403 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3404 DAG.getConstant(4, Ptr.getValueType())); 3405 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 3406 ST->getSrcValueOffset()+4); 3407 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 3408 } 3409 break; 3410 } 3411 } 3412 } 3413 3414 if (CombinerAA) { 3415 // Walk up chain skipping non-aliasing memory nodes. 3416 SDOperand BetterChain = FindBetterChain(N, Chain); 3417 3418 // If there is a better chain. 3419 if (Chain != BetterChain) { 3420 // Replace the chain to avoid dependency. 3421 SDOperand ReplStore; 3422 if (ST->isTruncatingStore()) { 3423 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 3424 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT()); 3425 } else { 3426 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 3427 ST->getSrcValue(), ST->getSrcValueOffset()); 3428 } 3429 3430 // Create token to keep both nodes around. 3431 SDOperand Token = 3432 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 3433 3434 // Don't add users to work list. 3435 return CombineTo(N, Token, false); 3436 } 3437 } 3438 3439 // Try transforming N to an indexed store. 3440 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3441 return SDOperand(N, 0); 3442 3443 return SDOperand(); 3444} 3445 3446SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 3447 SDOperand InVec = N->getOperand(0); 3448 SDOperand InVal = N->getOperand(1); 3449 SDOperand EltNo = N->getOperand(2); 3450 3451 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 3452 // vector with the inserted element. 3453 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3454 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3455 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3456 if (Elt < Ops.size()) 3457 Ops[Elt] = InVal; 3458 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 3459 &Ops[0], Ops.size()); 3460 } 3461 3462 return SDOperand(); 3463} 3464 3465SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 3466 SDOperand InVec = N->getOperand(0); 3467 SDOperand InVal = N->getOperand(1); 3468 SDOperand EltNo = N->getOperand(2); 3469 SDOperand NumElts = N->getOperand(3); 3470 SDOperand EltType = N->getOperand(4); 3471 3472 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 3473 // vector with the inserted element. 3474 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3475 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3476 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3477 if (Elt < Ops.size()-2) 3478 Ops[Elt] = InVal; 3479 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), 3480 &Ops[0], Ops.size()); 3481 } 3482 3483 return SDOperand(); 3484} 3485 3486SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 3487 unsigned NumInScalars = N->getNumOperands()-2; 3488 SDOperand NumElts = N->getOperand(NumInScalars); 3489 SDOperand EltType = N->getOperand(NumInScalars+1); 3490 3491 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 3492 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 3493 // two distinct vectors, turn this into a shuffle node. 3494 SDOperand VecIn1, VecIn2; 3495 for (unsigned i = 0; i != NumInScalars; ++i) { 3496 // Ignore undef inputs. 3497 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3498 3499 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 3500 // constant index, bail out. 3501 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 3502 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 3503 VecIn1 = VecIn2 = SDOperand(0, 0); 3504 break; 3505 } 3506 3507 // If the input vector type disagrees with the result of the vbuild_vector, 3508 // we can't make a shuffle. 3509 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 3510 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 3511 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 3512 VecIn1 = VecIn2 = SDOperand(0, 0); 3513 break; 3514 } 3515 3516 // Otherwise, remember this. We allow up to two distinct input vectors. 3517 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 3518 continue; 3519 3520 if (VecIn1.Val == 0) { 3521 VecIn1 = ExtractedFromVec; 3522 } else if (VecIn2.Val == 0) { 3523 VecIn2 = ExtractedFromVec; 3524 } else { 3525 // Too many inputs. 3526 VecIn1 = VecIn2 = SDOperand(0, 0); 3527 break; 3528 } 3529 } 3530 3531 // If everything is good, we can make a shuffle operation. 3532 if (VecIn1.Val) { 3533 SmallVector<SDOperand, 8> BuildVecIndices; 3534 for (unsigned i = 0; i != NumInScalars; ++i) { 3535 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 3536 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 3537 continue; 3538 } 3539 3540 SDOperand Extract = N->getOperand(i); 3541 3542 // If extracting from the first vector, just use the index directly. 3543 if (Extract.getOperand(0) == VecIn1) { 3544 BuildVecIndices.push_back(Extract.getOperand(1)); 3545 continue; 3546 } 3547 3548 // Otherwise, use InIdx + VecSize 3549 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 3550 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 3551 TLI.getPointerTy())); 3552 } 3553 3554 // Add count and size info. 3555 BuildVecIndices.push_back(NumElts); 3556 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy())); 3557 3558 // Return the new VVECTOR_SHUFFLE node. 3559 SDOperand Ops[5]; 3560 Ops[0] = VecIn1; 3561 if (VecIn2.Val) { 3562 Ops[1] = VecIn2; 3563 } else { 3564 // Use an undef vbuild_vector as input for the second operand. 3565 std::vector<SDOperand> UnOps(NumInScalars, 3566 DAG.getNode(ISD::UNDEF, 3567 cast<VTSDNode>(EltType)->getVT())); 3568 UnOps.push_back(NumElts); 3569 UnOps.push_back(EltType); 3570 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3571 &UnOps[0], UnOps.size()); 3572 AddToWorkList(Ops[1].Val); 3573 } 3574 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3575 &BuildVecIndices[0], BuildVecIndices.size()); 3576 Ops[3] = NumElts; 3577 Ops[4] = EltType; 3578 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5); 3579 } 3580 3581 return SDOperand(); 3582} 3583 3584SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 3585 SDOperand ShufMask = N->getOperand(2); 3586 unsigned NumElts = ShufMask.getNumOperands(); 3587 3588 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3589 bool isIdentity = true; 3590 for (unsigned i = 0; i != NumElts; ++i) { 3591 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3592 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3593 isIdentity = false; 3594 break; 3595 } 3596 } 3597 if (isIdentity) return N->getOperand(0); 3598 3599 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3600 isIdentity = true; 3601 for (unsigned i = 0; i != NumElts; ++i) { 3602 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3603 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3604 isIdentity = false; 3605 break; 3606 } 3607 } 3608 if (isIdentity) return N->getOperand(1); 3609 3610 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3611 // needed at all. 3612 bool isUnary = true; 3613 bool isSplat = true; 3614 int VecNum = -1; 3615 unsigned BaseIdx = 0; 3616 for (unsigned i = 0; i != NumElts; ++i) 3617 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3618 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3619 int V = (Idx < NumElts) ? 0 : 1; 3620 if (VecNum == -1) { 3621 VecNum = V; 3622 BaseIdx = Idx; 3623 } else { 3624 if (BaseIdx != Idx) 3625 isSplat = false; 3626 if (VecNum != V) { 3627 isUnary = false; 3628 break; 3629 } 3630 } 3631 } 3632 3633 SDOperand N0 = N->getOperand(0); 3634 SDOperand N1 = N->getOperand(1); 3635 // Normalize unary shuffle so the RHS is undef. 3636 if (isUnary && VecNum == 1) 3637 std::swap(N0, N1); 3638 3639 // If it is a splat, check if the argument vector is a build_vector with 3640 // all scalar elements the same. 3641 if (isSplat) { 3642 SDNode *V = N0.Val; 3643 if (V->getOpcode() == ISD::BIT_CONVERT) 3644 V = V->getOperand(0).Val; 3645 if (V->getOpcode() == ISD::BUILD_VECTOR) { 3646 unsigned NumElems = V->getNumOperands()-2; 3647 if (NumElems > BaseIdx) { 3648 SDOperand Base; 3649 bool AllSame = true; 3650 for (unsigned i = 0; i != NumElems; ++i) { 3651 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3652 Base = V->getOperand(i); 3653 break; 3654 } 3655 } 3656 // Splat of <u, u, u, u>, return <u, u, u, u> 3657 if (!Base.Val) 3658 return N0; 3659 for (unsigned i = 0; i != NumElems; ++i) { 3660 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3661 V->getOperand(i) != Base) { 3662 AllSame = false; 3663 break; 3664 } 3665 } 3666 // Splat of <x, x, x, x>, return <x, x, x, x> 3667 if (AllSame) 3668 return N0; 3669 } 3670 } 3671 } 3672 3673 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3674 // into an undef. 3675 if (isUnary || N0 == N1) { 3676 if (N0.getOpcode() == ISD::UNDEF) 3677 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3678 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3679 // first operand. 3680 SmallVector<SDOperand, 8> MappedOps; 3681 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 3682 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3683 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3684 MappedOps.push_back(ShufMask.getOperand(i)); 3685 } else { 3686 unsigned NewIdx = 3687 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3688 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3689 } 3690 } 3691 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 3692 &MappedOps[0], MappedOps.size()); 3693 AddToWorkList(ShufMask.Val); 3694 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 3695 N0, 3696 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 3697 ShufMask); 3698 } 3699 3700 return SDOperand(); 3701} 3702 3703SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 3704 SDOperand ShufMask = N->getOperand(2); 3705 unsigned NumElts = ShufMask.getNumOperands()-2; 3706 3707 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3708 bool isIdentity = true; 3709 for (unsigned i = 0; i != NumElts; ++i) { 3710 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3711 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3712 isIdentity = false; 3713 break; 3714 } 3715 } 3716 if (isIdentity) return N->getOperand(0); 3717 3718 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3719 isIdentity = true; 3720 for (unsigned i = 0; i != NumElts; ++i) { 3721 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3722 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3723 isIdentity = false; 3724 break; 3725 } 3726 } 3727 if (isIdentity) return N->getOperand(1); 3728 3729 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3730 // needed at all. 3731 bool isUnary = true; 3732 bool isSplat = true; 3733 int VecNum = -1; 3734 unsigned BaseIdx = 0; 3735 for (unsigned i = 0; i != NumElts; ++i) 3736 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3737 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3738 int V = (Idx < NumElts) ? 0 : 1; 3739 if (VecNum == -1) { 3740 VecNum = V; 3741 BaseIdx = Idx; 3742 } else { 3743 if (BaseIdx != Idx) 3744 isSplat = false; 3745 if (VecNum != V) { 3746 isUnary = false; 3747 break; 3748 } 3749 } 3750 } 3751 3752 SDOperand N0 = N->getOperand(0); 3753 SDOperand N1 = N->getOperand(1); 3754 // Normalize unary shuffle so the RHS is undef. 3755 if (isUnary && VecNum == 1) 3756 std::swap(N0, N1); 3757 3758 // If it is a splat, check if the argument vector is a build_vector with 3759 // all scalar elements the same. 3760 if (isSplat) { 3761 SDNode *V = N0.Val; 3762 3763 // If this is a vbit convert that changes the element type of the vector but 3764 // not the number of vector elements, look through it. Be careful not to 3765 // look though conversions that change things like v4f32 to v2f64. 3766 if (V->getOpcode() == ISD::VBIT_CONVERT) { 3767 SDOperand ConvInput = V->getOperand(0); 3768 if (ConvInput.getValueType() == MVT::Vector && 3769 NumElts == 3770 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2)) 3771 V = ConvInput.Val; 3772 } 3773 3774 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 3775 unsigned NumElems = V->getNumOperands()-2; 3776 if (NumElems > BaseIdx) { 3777 SDOperand Base; 3778 bool AllSame = true; 3779 for (unsigned i = 0; i != NumElems; ++i) { 3780 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3781 Base = V->getOperand(i); 3782 break; 3783 } 3784 } 3785 // Splat of <u, u, u, u>, return <u, u, u, u> 3786 if (!Base.Val) 3787 return N0; 3788 for (unsigned i = 0; i != NumElems; ++i) { 3789 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3790 V->getOperand(i) != Base) { 3791 AllSame = false; 3792 break; 3793 } 3794 } 3795 // Splat of <x, x, x, x>, return <x, x, x, x> 3796 if (AllSame) 3797 return N0; 3798 } 3799 } 3800 } 3801 3802 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3803 // into an undef. 3804 if (isUnary || N0 == N1) { 3805 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3806 // first operand. 3807 SmallVector<SDOperand, 8> MappedOps; 3808 for (unsigned i = 0; i != NumElts; ++i) { 3809 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3810 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3811 MappedOps.push_back(ShufMask.getOperand(i)); 3812 } else { 3813 unsigned NewIdx = 3814 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3815 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3816 } 3817 } 3818 // Add the type/#elts values. 3819 MappedOps.push_back(ShufMask.getOperand(NumElts)); 3820 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 3821 3822 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 3823 &MappedOps[0], MappedOps.size()); 3824 AddToWorkList(ShufMask.Val); 3825 3826 // Build the undef vector. 3827 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 3828 for (unsigned i = 0; i != NumElts; ++i) 3829 MappedOps[i] = UDVal; 3830 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 3831 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 3832 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3833 &MappedOps[0], MappedOps.size()); 3834 3835 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3836 N0, UDVal, ShufMask, 3837 MappedOps[NumElts], MappedOps[NumElts+1]); 3838 } 3839 3840 return SDOperand(); 3841} 3842 3843/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 3844/// a VAND to a vector_shuffle with the destination vector and a zero vector. 3845/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 3846/// vector_shuffle V, Zero, <0, 4, 2, 4> 3847SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 3848 SDOperand LHS = N->getOperand(0); 3849 SDOperand RHS = N->getOperand(1); 3850 if (N->getOpcode() == ISD::VAND) { 3851 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 3852 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 3853 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 3854 RHS = RHS.getOperand(0); 3855 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3856 std::vector<SDOperand> IdxOps; 3857 unsigned NumOps = RHS.getNumOperands(); 3858 unsigned NumElts = NumOps-2; 3859 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 3860 for (unsigned i = 0; i != NumElts; ++i) { 3861 SDOperand Elt = RHS.getOperand(i); 3862 if (!isa<ConstantSDNode>(Elt)) 3863 return SDOperand(); 3864 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 3865 IdxOps.push_back(DAG.getConstant(i, EVT)); 3866 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 3867 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 3868 else 3869 return SDOperand(); 3870 } 3871 3872 // Let's see if the target supports this vector_shuffle. 3873 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 3874 return SDOperand(); 3875 3876 // Return the new VVECTOR_SHUFFLE node. 3877 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 3878 SDOperand EVTNode = DAG.getValueType(EVT); 3879 std::vector<SDOperand> Ops; 3880 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, 3881 EVTNode); 3882 Ops.push_back(LHS); 3883 AddToWorkList(LHS.Val); 3884 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 3885 ZeroOps.push_back(NumEltsNode); 3886 ZeroOps.push_back(EVTNode); 3887 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3888 &ZeroOps[0], ZeroOps.size())); 3889 IdxOps.push_back(NumEltsNode); 3890 IdxOps.push_back(EVTNode); 3891 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3892 &IdxOps[0], IdxOps.size())); 3893 Ops.push_back(NumEltsNode); 3894 Ops.push_back(EVTNode); 3895 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3896 &Ops[0], Ops.size()); 3897 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 3898 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 3899 DstVecSize, DstVecEVT); 3900 } 3901 return Result; 3902 } 3903 } 3904 return SDOperand(); 3905} 3906 3907/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 3908/// the scalar operation of the vop if it is operating on an integer vector 3909/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 3910SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 3911 ISD::NodeType FPOp) { 3912 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 3913 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 3914 SDOperand LHS = N->getOperand(0); 3915 SDOperand RHS = N->getOperand(1); 3916 SDOperand Shuffle = XformToShuffleWithZero(N); 3917 if (Shuffle.Val) return Shuffle; 3918 3919 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 3920 // this operation. 3921 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 3922 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3923 SmallVector<SDOperand, 8> Ops; 3924 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 3925 SDOperand LHSOp = LHS.getOperand(i); 3926 SDOperand RHSOp = RHS.getOperand(i); 3927 // If these two elements can't be folded, bail out. 3928 if ((LHSOp.getOpcode() != ISD::UNDEF && 3929 LHSOp.getOpcode() != ISD::Constant && 3930 LHSOp.getOpcode() != ISD::ConstantFP) || 3931 (RHSOp.getOpcode() != ISD::UNDEF && 3932 RHSOp.getOpcode() != ISD::Constant && 3933 RHSOp.getOpcode() != ISD::ConstantFP)) 3934 break; 3935 // Can't fold divide by zero. 3936 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 3937 if ((RHSOp.getOpcode() == ISD::Constant && 3938 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 3939 (RHSOp.getOpcode() == ISD::ConstantFP && 3940 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 3941 break; 3942 } 3943 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 3944 AddToWorkList(Ops.back().Val); 3945 assert((Ops.back().getOpcode() == ISD::UNDEF || 3946 Ops.back().getOpcode() == ISD::Constant || 3947 Ops.back().getOpcode() == ISD::ConstantFP) && 3948 "Scalar binop didn't fold!"); 3949 } 3950 3951 if (Ops.size() == LHS.getNumOperands()-2) { 3952 Ops.push_back(*(LHS.Val->op_end()-2)); 3953 Ops.push_back(*(LHS.Val->op_end()-1)); 3954 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 3955 } 3956 } 3957 3958 return SDOperand(); 3959} 3960 3961SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 3962 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 3963 3964 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 3965 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3966 // If we got a simplified select_cc node back from SimplifySelectCC, then 3967 // break it down into a new SETCC node, and a new SELECT node, and then return 3968 // the SELECT node, since we were called with a SELECT node. 3969 if (SCC.Val) { 3970 // Check to see if we got a select_cc back (to turn into setcc/select). 3971 // Otherwise, just return whatever node we got back, like fabs. 3972 if (SCC.getOpcode() == ISD::SELECT_CC) { 3973 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 3974 SCC.getOperand(0), SCC.getOperand(1), 3975 SCC.getOperand(4)); 3976 AddToWorkList(SETCC.Val); 3977 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 3978 SCC.getOperand(3), SETCC); 3979 } 3980 return SCC; 3981 } 3982 return SDOperand(); 3983} 3984 3985/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 3986/// are the two values being selected between, see if we can simplify the 3987/// select. Callers of this should assume that TheSelect is deleted if this 3988/// returns true. As such, they should return the appropriate thing (e.g. the 3989/// node) back to the top-level of the DAG combiner loop to avoid it being 3990/// looked at. 3991/// 3992bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 3993 SDOperand RHS) { 3994 3995 // If this is a select from two identical things, try to pull the operation 3996 // through the select. 3997 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 3998 // If this is a load and the token chain is identical, replace the select 3999 // of two loads with a load through a select of the address to load from. 4000 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4001 // constants have been dropped into the constant pool. 4002 if (LHS.getOpcode() == ISD::LOAD && 4003 // Token chains must be identical. 4004 LHS.getOperand(0) == RHS.getOperand(0)) { 4005 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4006 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4007 4008 // If this is an EXTLOAD, the VT's must match. 4009 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4010 // FIXME: this conflates two src values, discarding one. This is not 4011 // the right thing to do, but nothing uses srcvalues now. When they do, 4012 // turn SrcValue into a list of locations. 4013 SDOperand Addr; 4014 if (TheSelect->getOpcode() == ISD::SELECT) { 4015 // Check that the condition doesn't reach either load. If so, folding 4016 // this will induce a cycle into the DAG. 4017 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4018 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4019 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4020 TheSelect->getOperand(0), LLD->getBasePtr(), 4021 RLD->getBasePtr()); 4022 } 4023 } else { 4024 // Check that the condition doesn't reach either load. If so, folding 4025 // this will induce a cycle into the DAG. 4026 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4027 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4028 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4029 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4030 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4031 TheSelect->getOperand(0), 4032 TheSelect->getOperand(1), 4033 LLD->getBasePtr(), RLD->getBasePtr(), 4034 TheSelect->getOperand(4)); 4035 } 4036 } 4037 4038 if (Addr.Val) { 4039 SDOperand Load; 4040 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4041 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4042 Addr,LLD->getSrcValue(), 4043 LLD->getSrcValueOffset()); 4044 else { 4045 Load = DAG.getExtLoad(LLD->getExtensionType(), 4046 TheSelect->getValueType(0), 4047 LLD->getChain(), Addr, LLD->getSrcValue(), 4048 LLD->getSrcValueOffset(), 4049 LLD->getLoadedVT()); 4050 } 4051 // Users of the select now use the result of the load. 4052 CombineTo(TheSelect, Load); 4053 4054 // Users of the old loads now use the new load's chain. We know the 4055 // old-load value is dead now. 4056 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4057 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4058 return true; 4059 } 4060 } 4061 } 4062 } 4063 4064 return false; 4065} 4066 4067SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4068 SDOperand N2, SDOperand N3, 4069 ISD::CondCode CC, bool NotExtCompare) { 4070 4071 MVT::ValueType VT = N2.getValueType(); 4072 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4073 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4074 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4075 4076 // Determine if the condition we're dealing with is constant 4077 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4078 if (SCC.Val) AddToWorkList(SCC.Val); 4079 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4080 4081 // fold select_cc true, x, y -> x 4082 if (SCCC && SCCC->getValue()) 4083 return N2; 4084 // fold select_cc false, x, y -> y 4085 if (SCCC && SCCC->getValue() == 0) 4086 return N3; 4087 4088 // Check to see if we can simplify the select into an fabs node 4089 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4090 // Allow either -0.0 or 0.0 4091 if (CFP->getValue() == 0.0) { 4092 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4093 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4094 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4095 N2 == N3.getOperand(0)) 4096 return DAG.getNode(ISD::FABS, VT, N0); 4097 4098 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4099 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4100 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4101 N2.getOperand(0) == N3) 4102 return DAG.getNode(ISD::FABS, VT, N3); 4103 } 4104 } 4105 4106 // Check to see if we can perform the "gzip trick", transforming 4107 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4108 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4109 MVT::isInteger(N0.getValueType()) && 4110 MVT::isInteger(N2.getValueType()) && 4111 (N1C->isNullValue() || // (a < 0) ? b : 0 4112 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4113 MVT::ValueType XType = N0.getValueType(); 4114 MVT::ValueType AType = N2.getValueType(); 4115 if (XType >= AType) { 4116 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4117 // single-bit constant. 4118 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4119 unsigned ShCtV = Log2_64(N2C->getValue()); 4120 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4121 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4122 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4123 AddToWorkList(Shift.Val); 4124 if (XType > AType) { 4125 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4126 AddToWorkList(Shift.Val); 4127 } 4128 return DAG.getNode(ISD::AND, AType, Shift, N2); 4129 } 4130 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4131 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4132 TLI.getShiftAmountTy())); 4133 AddToWorkList(Shift.Val); 4134 if (XType > AType) { 4135 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4136 AddToWorkList(Shift.Val); 4137 } 4138 return DAG.getNode(ISD::AND, AType, Shift, N2); 4139 } 4140 } 4141 4142 // fold select C, 16, 0 -> shl C, 4 4143 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4144 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4145 4146 // If the caller doesn't want us to simplify this into a zext of a compare, 4147 // don't do it. 4148 if (NotExtCompare && N2C->getValue() == 1) 4149 return SDOperand(); 4150 4151 // Get a SetCC of the condition 4152 // FIXME: Should probably make sure that setcc is legal if we ever have a 4153 // target where it isn't. 4154 SDOperand Temp, SCC; 4155 // cast from setcc result type to select result type 4156 if (AfterLegalize) { 4157 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4158 if (N2.getValueType() < SCC.getValueType()) 4159 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4160 else 4161 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4162 } else { 4163 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4164 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4165 } 4166 AddToWorkList(SCC.Val); 4167 AddToWorkList(Temp.Val); 4168 4169 if (N2C->getValue() == 1) 4170 return Temp; 4171 // shl setcc result by log2 n2c 4172 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4173 DAG.getConstant(Log2_64(N2C->getValue()), 4174 TLI.getShiftAmountTy())); 4175 } 4176 4177 // Check to see if this is the equivalent of setcc 4178 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4179 // otherwise, go ahead with the folds. 4180 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4181 MVT::ValueType XType = N0.getValueType(); 4182 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4183 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4184 if (Res.getValueType() != VT) 4185 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4186 return Res; 4187 } 4188 4189 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4190 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4191 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4192 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4193 return DAG.getNode(ISD::SRL, XType, Ctlz, 4194 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4195 TLI.getShiftAmountTy())); 4196 } 4197 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4198 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4199 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4200 N0); 4201 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4202 DAG.getConstant(~0ULL, XType)); 4203 return DAG.getNode(ISD::SRL, XType, 4204 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4205 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4206 TLI.getShiftAmountTy())); 4207 } 4208 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4209 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4210 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4211 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4212 TLI.getShiftAmountTy())); 4213 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4214 } 4215 } 4216 4217 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4218 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4219 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4220 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4221 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4222 MVT::ValueType XType = N0.getValueType(); 4223 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4224 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4225 TLI.getShiftAmountTy())); 4226 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4227 AddToWorkList(Shift.Val); 4228 AddToWorkList(Add.Val); 4229 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4230 } 4231 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4232 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4233 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4234 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4235 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4236 MVT::ValueType XType = N0.getValueType(); 4237 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4238 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4239 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4240 TLI.getShiftAmountTy())); 4241 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4242 AddToWorkList(Shift.Val); 4243 AddToWorkList(Add.Val); 4244 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4245 } 4246 } 4247 } 4248 4249 return SDOperand(); 4250} 4251 4252/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4253SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4254 SDOperand N1, ISD::CondCode Cond, 4255 bool foldBooleans) { 4256 TargetLowering::DAGCombinerInfo 4257 DagCombineInfo(DAG, !AfterLegalize, false, this); 4258 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4259} 4260 4261/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4262/// return a DAG expression to select that will generate the same value by 4263/// multiplying by a magic number. See: 4264/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4265SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4266 std::vector<SDNode*> Built; 4267 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4268 4269 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4270 ii != ee; ++ii) 4271 AddToWorkList(*ii); 4272 return S; 4273} 4274 4275/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4276/// return a DAG expression to select that will generate the same value by 4277/// multiplying by a magic number. See: 4278/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4279SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4280 std::vector<SDNode*> Built; 4281 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4282 4283 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4284 ii != ee; ++ii) 4285 AddToWorkList(*ii); 4286 return S; 4287} 4288 4289/// FindBaseOffset - Return true if base is known not to alias with anything 4290/// but itself. Provides base object and offset as results. 4291static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4292 // Assume it is a primitive operation. 4293 Base = Ptr; Offset = 0; 4294 4295 // If it's an adding a simple constant then integrate the offset. 4296 if (Base.getOpcode() == ISD::ADD) { 4297 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4298 Base = Base.getOperand(0); 4299 Offset += C->getValue(); 4300 } 4301 } 4302 4303 // If it's any of the following then it can't alias with anything but itself. 4304 return isa<FrameIndexSDNode>(Base) || 4305 isa<ConstantPoolSDNode>(Base) || 4306 isa<GlobalAddressSDNode>(Base); 4307} 4308 4309/// isAlias - Return true if there is any possibility that the two addresses 4310/// overlap. 4311bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4312 const Value *SrcValue1, int SrcValueOffset1, 4313 SDOperand Ptr2, int64_t Size2, 4314 const Value *SrcValue2, int SrcValueOffset2) 4315{ 4316 // If they are the same then they must be aliases. 4317 if (Ptr1 == Ptr2) return true; 4318 4319 // Gather base node and offset information. 4320 SDOperand Base1, Base2; 4321 int64_t Offset1, Offset2; 4322 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4323 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4324 4325 // If they have a same base address then... 4326 if (Base1 == Base2) { 4327 // Check to see if the addresses overlap. 4328 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4329 } 4330 4331 // If we know both bases then they can't alias. 4332 if (KnownBase1 && KnownBase2) return false; 4333 4334 if (CombinerGlobalAA) { 4335 // Use alias analysis information. 4336 int Overlap1 = Size1 + SrcValueOffset1 + Offset1; 4337 int Overlap2 = Size2 + SrcValueOffset2 + Offset2; 4338 AliasAnalysis::AliasResult AAResult = 4339 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4340 if (AAResult == AliasAnalysis::NoAlias) 4341 return false; 4342 } 4343 4344 // Otherwise we have to assume they alias. 4345 return true; 4346} 4347 4348/// FindAliasInfo - Extracts the relevant alias information from the memory 4349/// node. Returns true if the operand was a load. 4350bool DAGCombiner::FindAliasInfo(SDNode *N, 4351 SDOperand &Ptr, int64_t &Size, 4352 const Value *&SrcValue, int &SrcValueOffset) { 4353 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4354 Ptr = LD->getBasePtr(); 4355 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4356 SrcValue = LD->getSrcValue(); 4357 SrcValueOffset = LD->getSrcValueOffset(); 4358 return true; 4359 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4360 Ptr = ST->getBasePtr(); 4361 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4362 SrcValue = ST->getSrcValue(); 4363 SrcValueOffset = ST->getSrcValueOffset(); 4364 } else { 4365 assert(0 && "FindAliasInfo expected a memory operand"); 4366 } 4367 4368 return false; 4369} 4370 4371/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4372/// looking for aliasing nodes and adding them to the Aliases vector. 4373void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4374 SmallVector<SDOperand, 8> &Aliases) { 4375 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4376 std::set<SDNode *> Visited; // Visited node set. 4377 4378 // Get alias information for node. 4379 SDOperand Ptr; 4380 int64_t Size; 4381 const Value *SrcValue; 4382 int SrcValueOffset; 4383 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4384 4385 // Starting off. 4386 Chains.push_back(OriginalChain); 4387 4388 // Look at each chain and determine if it is an alias. If so, add it to the 4389 // aliases list. If not, then continue up the chain looking for the next 4390 // candidate. 4391 while (!Chains.empty()) { 4392 SDOperand Chain = Chains.back(); 4393 Chains.pop_back(); 4394 4395 // Don't bother if we've been before. 4396 if (Visited.find(Chain.Val) != Visited.end()) continue; 4397 Visited.insert(Chain.Val); 4398 4399 switch (Chain.getOpcode()) { 4400 case ISD::EntryToken: 4401 // Entry token is ideal chain operand, but handled in FindBetterChain. 4402 break; 4403 4404 case ISD::LOAD: 4405 case ISD::STORE: { 4406 // Get alias information for Chain. 4407 SDOperand OpPtr; 4408 int64_t OpSize; 4409 const Value *OpSrcValue; 4410 int OpSrcValueOffset; 4411 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4412 OpSrcValue, OpSrcValueOffset); 4413 4414 // If chain is alias then stop here. 4415 if (!(IsLoad && IsOpLoad) && 4416 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4417 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4418 Aliases.push_back(Chain); 4419 } else { 4420 // Look further up the chain. 4421 Chains.push_back(Chain.getOperand(0)); 4422 // Clean up old chain. 4423 AddToWorkList(Chain.Val); 4424 } 4425 break; 4426 } 4427 4428 case ISD::TokenFactor: 4429 // We have to check each of the operands of the token factor, so we queue 4430 // then up. Adding the operands to the queue (stack) in reverse order 4431 // maintains the original order and increases the likelihood that getNode 4432 // will find a matching token factor (CSE.) 4433 for (unsigned n = Chain.getNumOperands(); n;) 4434 Chains.push_back(Chain.getOperand(--n)); 4435 // Eliminate the token factor if we can. 4436 AddToWorkList(Chain.Val); 4437 break; 4438 4439 default: 4440 // For all other instructions we will just have to take what we can get. 4441 Aliases.push_back(Chain); 4442 break; 4443 } 4444 } 4445} 4446 4447/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4448/// for a better chain (aliasing node.) 4449SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4450 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4451 4452 // Accumulate all the aliases to this node. 4453 GatherAllAliases(N, OldChain, Aliases); 4454 4455 if (Aliases.size() == 0) { 4456 // If no operands then chain to entry token. 4457 return DAG.getEntryNode(); 4458 } else if (Aliases.size() == 1) { 4459 // If a single operand then chain to it. We don't need to revisit it. 4460 return Aliases[0]; 4461 } 4462 4463 // Construct a custom tailored token factor. 4464 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4465 &Aliases[0], Aliases.size()); 4466 4467 // Make sure the old chain gets cleaned up. 4468 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4469 4470 return NewChain; 4471} 4472 4473// SelectionDAG::Combine - This is the entry point for the file. 4474// 4475void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4476 if (!RunningAfterLegalize && ViewDAGCombine1) 4477 viewGraph(); 4478 if (RunningAfterLegalize && ViewDAGCombine2) 4479 viewGraph(); 4480 /// run - This is the main entry point to this class. 4481 /// 4482 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 4483} 4484