DAGCombiner.cpp revision 61c5ff460b18b970aa651115c4ac78dfc0d602d7
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/CodeGen/SelectionDAG.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/Target/TargetData.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include "llvm/ADT/Statistic.h" 40#include "llvm/Support/Compiler.h" 41#include "llvm/Support/CommandLine.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Support/MathExtras.h" 44#include <algorithm> 45using namespace llvm; 46 47STATISTIC(NodesCombined , "Number of dag nodes combined"); 48STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 49STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 50 51namespace { 52#ifndef NDEBUG 53 static cl::opt<bool> 54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 55 cl::desc("Pop up a window to show dags before the first " 56 "dag combine pass")); 57 static cl::opt<bool> 58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 59 cl::desc("Pop up a window to show dags before the second " 60 "dag combine pass")); 61#else 62 static const bool ViewDAGCombine1 = false; 63 static const bool ViewDAGCombine2 = false; 64#endif 65 66 static cl::opt<bool> 67 CombinerAA("combiner-alias-analysis", cl::Hidden, 68 cl::desc("Turn on alias analysis during testing")); 69 70 static cl::opt<bool> 71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 72 cl::desc("Include global information in alias analysis")); 73 74//------------------------------ DAGCombiner ---------------------------------// 75 76 class VISIBILITY_HIDDEN DAGCombiner { 77 SelectionDAG &DAG; 78 TargetLowering &TLI; 79 bool AfterLegalize; 80 81 // Worklist of all of the nodes that need to be simplified. 82 std::vector<SDNode*> WorkList; 83 84 // AA - Used for DAG load/store alias analysis. 85 AliasAnalysis &AA; 86 87 /// AddUsersToWorkList - When an instruction is simplified, add all users of 88 /// the instruction to the work lists because they might get more simplified 89 /// now. 90 /// 91 void AddUsersToWorkList(SDNode *N) { 92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 93 UI != UE; ++UI) 94 AddToWorkList(*UI); 95 } 96 97 /// removeFromWorkList - remove all instances of N from the worklist. 98 /// 99 void removeFromWorkList(SDNode *N) { 100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 101 WorkList.end()); 102 } 103 104 public: 105 /// AddToWorkList - Add to the work list making sure it's instance is at the 106 /// the back (next to be processed.) 107 void AddToWorkList(SDNode *N) { 108 removeFromWorkList(N); 109 WorkList.push_back(N); 110 } 111 112 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 113 bool AddTo = true) { 114 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 115 ++NodesCombined; 116 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 117 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 118 DOUT << " and " << NumTo-1 << " other values\n"; 119 std::vector<SDNode*> NowDead; 120 DAG.ReplaceAllUsesWith(N, To, &NowDead); 121 122 if (AddTo) { 123 // Push the new nodes and any users onto the worklist 124 for (unsigned i = 0, e = NumTo; i != e; ++i) { 125 AddToWorkList(To[i].Val); 126 AddUsersToWorkList(To[i].Val); 127 } 128 } 129 130 // Nodes can be reintroduced into the worklist. Make sure we do not 131 // process a node that has been replaced. 132 removeFromWorkList(N); 133 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 134 removeFromWorkList(NowDead[i]); 135 136 // Finally, since the node is now dead, remove it from the graph. 137 DAG.DeleteNode(N); 138 return SDOperand(N, 0); 139 } 140 141 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 142 return CombineTo(N, &Res, 1, AddTo); 143 } 144 145 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 146 bool AddTo = true) { 147 SDOperand To[] = { Res0, Res1 }; 148 return CombineTo(N, To, 2, AddTo); 149 } 150 private: 151 152 /// SimplifyDemandedBits - Check the specified integer node value to see if 153 /// it can be simplified or if things it uses can be simplified by bit 154 /// propagation. If so, return true. 155 bool SimplifyDemandedBits(SDOperand Op) { 156 TargetLowering::TargetLoweringOpt TLO(DAG); 157 uint64_t KnownZero, KnownOne; 158 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 159 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 160 return false; 161 162 // Revisit the node. 163 AddToWorkList(Op.Val); 164 165 // Replace the old value with the new one. 166 ++NodesCombined; 167 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 168 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 169 DOUT << '\n'; 170 171 std::vector<SDNode*> NowDead; 172 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 173 174 // Push the new node and any (possibly new) users onto the worklist. 175 AddToWorkList(TLO.New.Val); 176 AddUsersToWorkList(TLO.New.Val); 177 178 // Nodes can end up on the worklist more than once. Make sure we do 179 // not process a node that has been replaced. 180 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 181 removeFromWorkList(NowDead[i]); 182 183 // Finally, if the node is now dead, remove it from the graph. The node 184 // may not be dead if the replacement process recursively simplified to 185 // something else needing this node. 186 if (TLO.Old.Val->use_empty()) { 187 removeFromWorkList(TLO.Old.Val); 188 189 // If the operands of this node are only used by the node, they will now 190 // be dead. Make sure to visit them first to delete dead nodes early. 191 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 192 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 193 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 194 195 DAG.DeleteNode(TLO.Old.Val); 196 } 197 return true; 198 } 199 200 bool CombineToPreIndexedLoadStore(SDNode *N); 201 bool CombineToPostIndexedLoadStore(SDNode *N); 202 203 204 /// visit - call the node-specific routine that knows how to fold each 205 /// particular type of node. 206 SDOperand visit(SDNode *N); 207 208 // Visitation implementation - Implement dag node combining for different 209 // node types. The semantics are as follows: 210 // Return Value: 211 // SDOperand.Val == 0 - No change was made 212 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 213 // otherwise - N should be replaced by the returned Operand. 214 // 215 SDOperand visitTokenFactor(SDNode *N); 216 SDOperand visitADD(SDNode *N); 217 SDOperand visitSUB(SDNode *N); 218 SDOperand visitADDC(SDNode *N); 219 SDOperand visitADDE(SDNode *N); 220 SDOperand visitMUL(SDNode *N); 221 SDOperand visitSDIV(SDNode *N); 222 SDOperand visitUDIV(SDNode *N); 223 SDOperand visitSREM(SDNode *N); 224 SDOperand visitUREM(SDNode *N); 225 SDOperand visitMULHU(SDNode *N); 226 SDOperand visitMULHS(SDNode *N); 227 SDOperand visitAND(SDNode *N); 228 SDOperand visitOR(SDNode *N); 229 SDOperand visitXOR(SDNode *N); 230 SDOperand SimplifyVBinOp(SDNode *N); 231 SDOperand visitSHL(SDNode *N); 232 SDOperand visitSRA(SDNode *N); 233 SDOperand visitSRL(SDNode *N); 234 SDOperand visitCTLZ(SDNode *N); 235 SDOperand visitCTTZ(SDNode *N); 236 SDOperand visitCTPOP(SDNode *N); 237 SDOperand visitSELECT(SDNode *N); 238 SDOperand visitSELECT_CC(SDNode *N); 239 SDOperand visitSETCC(SDNode *N); 240 SDOperand visitSIGN_EXTEND(SDNode *N); 241 SDOperand visitZERO_EXTEND(SDNode *N); 242 SDOperand visitANY_EXTEND(SDNode *N); 243 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 244 SDOperand visitTRUNCATE(SDNode *N); 245 SDOperand visitBIT_CONVERT(SDNode *N); 246 SDOperand visitFADD(SDNode *N); 247 SDOperand visitFSUB(SDNode *N); 248 SDOperand visitFMUL(SDNode *N); 249 SDOperand visitFDIV(SDNode *N); 250 SDOperand visitFREM(SDNode *N); 251 SDOperand visitFCOPYSIGN(SDNode *N); 252 SDOperand visitSINT_TO_FP(SDNode *N); 253 SDOperand visitUINT_TO_FP(SDNode *N); 254 SDOperand visitFP_TO_SINT(SDNode *N); 255 SDOperand visitFP_TO_UINT(SDNode *N); 256 SDOperand visitFP_ROUND(SDNode *N); 257 SDOperand visitFP_ROUND_INREG(SDNode *N); 258 SDOperand visitFP_EXTEND(SDNode *N); 259 SDOperand visitFNEG(SDNode *N); 260 SDOperand visitFABS(SDNode *N); 261 SDOperand visitBRCOND(SDNode *N); 262 SDOperand visitBR_CC(SDNode *N); 263 SDOperand visitLOAD(SDNode *N); 264 SDOperand visitSTORE(SDNode *N); 265 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 266 SDOperand visitBUILD_VECTOR(SDNode *N); 267 SDOperand visitCONCAT_VECTORS(SDNode *N); 268 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 269 270 SDOperand XformToShuffleWithZero(SDNode *N); 271 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 272 273 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 274 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 275 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 276 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 277 SDOperand N3, ISD::CondCode CC, 278 bool NotExtCompare = false); 279 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 280 ISD::CondCode Cond, bool foldBooleans = true); 281 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 282 SDOperand BuildSDIV(SDNode *N); 283 SDOperand BuildUDIV(SDNode *N); 284 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 285 SDOperand ReduceLoadWidth(SDNode *N); 286 287 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 288 /// looking for aliasing nodes and adding them to the Aliases vector. 289 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 290 SmallVector<SDOperand, 8> &Aliases); 291 292 /// isAlias - Return true if there is any possibility that the two addresses 293 /// overlap. 294 bool isAlias(SDOperand Ptr1, int64_t Size1, 295 const Value *SrcValue1, int SrcValueOffset1, 296 SDOperand Ptr2, int64_t Size2, 297 const Value *SrcValue2, int SrcValueOffset2); 298 299 /// FindAliasInfo - Extracts the relevant alias information from the memory 300 /// node. Returns true if the operand was a load. 301 bool FindAliasInfo(SDNode *N, 302 SDOperand &Ptr, int64_t &Size, 303 const Value *&SrcValue, int &SrcValueOffset); 304 305 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 306 /// looking for a better chain (aliasing node.) 307 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 308 309public: 310 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 311 : DAG(D), 312 TLI(D.getTargetLoweringInfo()), 313 AfterLegalize(false), 314 AA(A) {} 315 316 /// Run - runs the dag combiner on all nodes in the work list 317 void Run(bool RunningAfterLegalize); 318 }; 319} 320 321//===----------------------------------------------------------------------===// 322// TargetLowering::DAGCombinerInfo implementation 323//===----------------------------------------------------------------------===// 324 325void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 326 ((DAGCombiner*)DC)->AddToWorkList(N); 327} 328 329SDOperand TargetLowering::DAGCombinerInfo:: 330CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 331 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 332} 333 334SDOperand TargetLowering::DAGCombinerInfo:: 335CombineTo(SDNode *N, SDOperand Res) { 336 return ((DAGCombiner*)DC)->CombineTo(N, Res); 337} 338 339 340SDOperand TargetLowering::DAGCombinerInfo:: 341CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 342 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 343} 344 345 346//===----------------------------------------------------------------------===// 347// Helper Functions 348//===----------------------------------------------------------------------===// 349 350/// isNegatibleForFree - Return 1 if we can compute the negated form of the 351/// specified expression for the same cost as the expression itself, or 2 if we 352/// can compute the negated form more cheaply than the expression itself. 353static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 354 // fneg is removable even if it has multiple uses. 355 if (Op.getOpcode() == ISD::FNEG) return 2; 356 357 // Don't allow anything with multiple uses. 358 if (!Op.hasOneUse()) return 0; 359 360 // Don't recurse exponentially. 361 if (Depth > 6) return 0; 362 363 switch (Op.getOpcode()) { 364 default: return false; 365 case ISD::ConstantFP: 366 return 1; 367 case ISD::FADD: 368 // FIXME: determine better conditions for this xform. 369 if (!UnsafeFPMath) return 0; 370 371 // -(A+B) -> -A - B 372 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 373 return V; 374 // -(A+B) -> -B - A 375 return isNegatibleForFree(Op.getOperand(1), Depth+1); 376 case ISD::FSUB: 377 // We can't turn -(A-B) into B-A when we honor signed zeros. 378 if (!UnsafeFPMath) return 0; 379 380 // -(A-B) -> B-A 381 return 1; 382 383 case ISD::FMUL: 384 case ISD::FDIV: 385 if (HonorSignDependentRoundingFPMath()) return 0; 386 387 // -(X*Y) -> (-X * Y) or (X*-Y) 388 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 389 return V; 390 391 return isNegatibleForFree(Op.getOperand(1), Depth+1); 392 393 case ISD::FP_EXTEND: 394 case ISD::FP_ROUND: 395 case ISD::FSIN: 396 return isNegatibleForFree(Op.getOperand(0), Depth+1); 397 } 398} 399 400/// GetNegatedExpression - If isNegatibleForFree returns true, this function 401/// returns the newly negated expression. 402static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 403 unsigned Depth = 0) { 404 // fneg is removable even if it has multiple uses. 405 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 406 407 // Don't allow anything with multiple uses. 408 assert(Op.hasOneUse() && "Unknown reuse!"); 409 410 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 411 switch (Op.getOpcode()) { 412 default: assert(0 && "Unknown code"); 413 case ISD::ConstantFP: { 414 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 415 V.changeSign(); 416 return DAG.getConstantFP(V, Op.getValueType()); 417 } 418 case ISD::FADD: 419 // FIXME: determine better conditions for this xform. 420 assert(UnsafeFPMath); 421 422 // -(A+B) -> -A - B 423 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 424 return DAG.getNode(ISD::FSUB, Op.getValueType(), 425 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 426 Op.getOperand(1)); 427 // -(A+B) -> -B - A 428 return DAG.getNode(ISD::FSUB, Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 430 Op.getOperand(0)); 431 case ISD::FSUB: 432 // We can't turn -(A-B) into B-A when we honor signed zeros. 433 assert(UnsafeFPMath); 434 435 // -(0-B) -> B 436 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 437 if (N0CFP->getValueAPF().isZero()) 438 return Op.getOperand(1); 439 440 // -(A-B) -> B-A 441 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 442 Op.getOperand(0)); 443 444 case ISD::FMUL: 445 case ISD::FDIV: 446 assert(!HonorSignDependentRoundingFPMath()); 447 448 // -(X*Y) -> -X * Y 449 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 450 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 451 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 452 Op.getOperand(1)); 453 454 // -(X*Y) -> X * -Y 455 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 456 Op.getOperand(0), 457 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 458 459 case ISD::FP_EXTEND: 460 case ISD::FP_ROUND: 461 case ISD::FSIN: 462 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 463 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 464 } 465} 466 467 468// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 469// that selects between the values 1 and 0, making it equivalent to a setcc. 470// Also, set the incoming LHS, RHS, and CC references to the appropriate 471// nodes based on the type of node we are checking. This simplifies life a 472// bit for the callers. 473static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 474 SDOperand &CC) { 475 if (N.getOpcode() == ISD::SETCC) { 476 LHS = N.getOperand(0); 477 RHS = N.getOperand(1); 478 CC = N.getOperand(2); 479 return true; 480 } 481 if (N.getOpcode() == ISD::SELECT_CC && 482 N.getOperand(2).getOpcode() == ISD::Constant && 483 N.getOperand(3).getOpcode() == ISD::Constant && 484 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 485 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 486 LHS = N.getOperand(0); 487 RHS = N.getOperand(1); 488 CC = N.getOperand(4); 489 return true; 490 } 491 return false; 492} 493 494// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 495// one use. If this is true, it allows the users to invert the operation for 496// free when it is profitable to do so. 497static bool isOneUseSetCC(SDOperand N) { 498 SDOperand N0, N1, N2; 499 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 500 return true; 501 return false; 502} 503 504SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 505 MVT::ValueType VT = N0.getValueType(); 506 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 507 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 508 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 509 if (isa<ConstantSDNode>(N1)) { 510 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 511 AddToWorkList(OpNode.Val); 512 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 513 } else if (N0.hasOneUse()) { 514 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 515 AddToWorkList(OpNode.Val); 516 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 517 } 518 } 519 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 520 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 521 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 522 if (isa<ConstantSDNode>(N0)) { 523 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 524 AddToWorkList(OpNode.Val); 525 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 526 } else if (N1.hasOneUse()) { 527 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 528 AddToWorkList(OpNode.Val); 529 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 530 } 531 } 532 return SDOperand(); 533} 534 535//===----------------------------------------------------------------------===// 536// Main DAG Combiner implementation 537//===----------------------------------------------------------------------===// 538 539void DAGCombiner::Run(bool RunningAfterLegalize) { 540 // set the instance variable, so that the various visit routines may use it. 541 AfterLegalize = RunningAfterLegalize; 542 543 // Add all the dag nodes to the worklist. 544 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 545 E = DAG.allnodes_end(); I != E; ++I) 546 WorkList.push_back(I); 547 548 // Create a dummy node (which is not added to allnodes), that adds a reference 549 // to the root node, preventing it from being deleted, and tracking any 550 // changes of the root. 551 HandleSDNode Dummy(DAG.getRoot()); 552 553 // The root of the dag may dangle to deleted nodes until the dag combiner is 554 // done. Set it to null to avoid confusion. 555 DAG.setRoot(SDOperand()); 556 557 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 558 TargetLowering::DAGCombinerInfo 559 DagCombineInfo(DAG, !RunningAfterLegalize, false, this); 560 561 // while the worklist isn't empty, inspect the node on the end of it and 562 // try and combine it. 563 while (!WorkList.empty()) { 564 SDNode *N = WorkList.back(); 565 WorkList.pop_back(); 566 567 // If N has no uses, it is dead. Make sure to revisit all N's operands once 568 // N is deleted from the DAG, since they too may now be dead or may have a 569 // reduced number of uses, allowing other xforms. 570 if (N->use_empty() && N != &Dummy) { 571 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 572 AddToWorkList(N->getOperand(i).Val); 573 574 DAG.DeleteNode(N); 575 continue; 576 } 577 578 SDOperand RV = visit(N); 579 580 // If nothing happened, try a target-specific DAG combine. 581 if (RV.Val == 0) { 582 assert(N->getOpcode() != ISD::DELETED_NODE && 583 "Node was deleted but visit returned NULL!"); 584 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 585 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 586 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 587 } 588 589 if (RV.Val) { 590 ++NodesCombined; 591 // If we get back the same node we passed in, rather than a new node or 592 // zero, we know that the node must have defined multiple values and 593 // CombineTo was used. Since CombineTo takes care of the worklist 594 // mechanics for us, we have no work to do in this case. 595 if (RV.Val != N) { 596 assert(N->getOpcode() != ISD::DELETED_NODE && 597 RV.Val->getOpcode() != ISD::DELETED_NODE && 598 "Node was deleted but visit returned new node!"); 599 600 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 601 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 602 DOUT << '\n'; 603 std::vector<SDNode*> NowDead; 604 if (N->getNumValues() == RV.Val->getNumValues()) 605 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 606 else { 607 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 608 SDOperand OpV = RV; 609 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 610 } 611 612 // Push the new node and any users onto the worklist 613 AddToWorkList(RV.Val); 614 AddUsersToWorkList(RV.Val); 615 616 // Nodes can be reintroduced into the worklist. Make sure we do not 617 // process a node that has been replaced. 618 removeFromWorkList(N); 619 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 620 removeFromWorkList(NowDead[i]); 621 622 // Finally, since the node is now dead, remove it from the graph. 623 DAG.DeleteNode(N); 624 } 625 } 626 } 627 628 // If the root changed (e.g. it was a dead load, update the root). 629 DAG.setRoot(Dummy.getValue()); 630} 631 632SDOperand DAGCombiner::visit(SDNode *N) { 633 switch(N->getOpcode()) { 634 default: break; 635 case ISD::TokenFactor: return visitTokenFactor(N); 636 case ISD::ADD: return visitADD(N); 637 case ISD::SUB: return visitSUB(N); 638 case ISD::ADDC: return visitADDC(N); 639 case ISD::ADDE: return visitADDE(N); 640 case ISD::MUL: return visitMUL(N); 641 case ISD::SDIV: return visitSDIV(N); 642 case ISD::UDIV: return visitUDIV(N); 643 case ISD::SREM: return visitSREM(N); 644 case ISD::UREM: return visitUREM(N); 645 case ISD::MULHU: return visitMULHU(N); 646 case ISD::MULHS: return visitMULHS(N); 647 case ISD::AND: return visitAND(N); 648 case ISD::OR: return visitOR(N); 649 case ISD::XOR: return visitXOR(N); 650 case ISD::SHL: return visitSHL(N); 651 case ISD::SRA: return visitSRA(N); 652 case ISD::SRL: return visitSRL(N); 653 case ISD::CTLZ: return visitCTLZ(N); 654 case ISD::CTTZ: return visitCTTZ(N); 655 case ISD::CTPOP: return visitCTPOP(N); 656 case ISD::SELECT: return visitSELECT(N); 657 case ISD::SELECT_CC: return visitSELECT_CC(N); 658 case ISD::SETCC: return visitSETCC(N); 659 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 660 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 661 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 662 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 663 case ISD::TRUNCATE: return visitTRUNCATE(N); 664 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 665 case ISD::FADD: return visitFADD(N); 666 case ISD::FSUB: return visitFSUB(N); 667 case ISD::FMUL: return visitFMUL(N); 668 case ISD::FDIV: return visitFDIV(N); 669 case ISD::FREM: return visitFREM(N); 670 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 671 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 672 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 673 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 674 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 675 case ISD::FP_ROUND: return visitFP_ROUND(N); 676 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 677 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 678 case ISD::FNEG: return visitFNEG(N); 679 case ISD::FABS: return visitFABS(N); 680 case ISD::BRCOND: return visitBRCOND(N); 681 case ISD::BR_CC: return visitBR_CC(N); 682 case ISD::LOAD: return visitLOAD(N); 683 case ISD::STORE: return visitSTORE(N); 684 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 685 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 686 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 687 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 688 } 689 return SDOperand(); 690} 691 692/// getInputChainForNode - Given a node, return its input chain if it has one, 693/// otherwise return a null sd operand. 694static SDOperand getInputChainForNode(SDNode *N) { 695 if (unsigned NumOps = N->getNumOperands()) { 696 if (N->getOperand(0).getValueType() == MVT::Other) 697 return N->getOperand(0); 698 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 699 return N->getOperand(NumOps-1); 700 for (unsigned i = 1; i < NumOps-1; ++i) 701 if (N->getOperand(i).getValueType() == MVT::Other) 702 return N->getOperand(i); 703 } 704 return SDOperand(0, 0); 705} 706 707SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 708 // If N has two operands, where one has an input chain equal to the other, 709 // the 'other' chain is redundant. 710 if (N->getNumOperands() == 2) { 711 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 712 return N->getOperand(0); 713 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 714 return N->getOperand(1); 715 } 716 717 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 718 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 719 SmallPtrSet<SDNode*, 16> SeenOps; 720 bool Changed = false; // If we should replace this token factor. 721 722 // Start out with this token factor. 723 TFs.push_back(N); 724 725 // Iterate through token factors. The TFs grows when new token factors are 726 // encountered. 727 for (unsigned i = 0; i < TFs.size(); ++i) { 728 SDNode *TF = TFs[i]; 729 730 // Check each of the operands. 731 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 732 SDOperand Op = TF->getOperand(i); 733 734 switch (Op.getOpcode()) { 735 case ISD::EntryToken: 736 // Entry tokens don't need to be added to the list. They are 737 // rededundant. 738 Changed = true; 739 break; 740 741 case ISD::TokenFactor: 742 if ((CombinerAA || Op.hasOneUse()) && 743 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 744 // Queue up for processing. 745 TFs.push_back(Op.Val); 746 // Clean up in case the token factor is removed. 747 AddToWorkList(Op.Val); 748 Changed = true; 749 break; 750 } 751 // Fall thru 752 753 default: 754 // Only add if it isn't already in the list. 755 if (SeenOps.insert(Op.Val)) 756 Ops.push_back(Op); 757 else 758 Changed = true; 759 break; 760 } 761 } 762 } 763 764 SDOperand Result; 765 766 // If we've change things around then replace token factor. 767 if (Changed) { 768 if (Ops.size() == 0) { 769 // The entry token is the only possible outcome. 770 Result = DAG.getEntryNode(); 771 } else { 772 // New and improved token factor. 773 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 774 } 775 776 // Don't add users to work list. 777 return CombineTo(N, Result, false); 778 } 779 780 return Result; 781} 782 783static 784SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 785 MVT::ValueType VT = N0.getValueType(); 786 SDOperand N00 = N0.getOperand(0); 787 SDOperand N01 = N0.getOperand(1); 788 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 789 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 790 isa<ConstantSDNode>(N00.getOperand(1))) { 791 N0 = DAG.getNode(ISD::ADD, VT, 792 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 793 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 794 return DAG.getNode(ISD::ADD, VT, N0, N1); 795 } 796 return SDOperand(); 797} 798 799static 800SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 801 SelectionDAG &DAG) { 802 MVT::ValueType VT = N->getValueType(0); 803 unsigned Opc = N->getOpcode(); 804 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 805 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 806 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 807 ISD::CondCode CC = ISD::SETCC_INVALID; 808 if (isSlctCC) 809 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 810 else { 811 SDOperand CCOp = Slct.getOperand(0); 812 if (CCOp.getOpcode() == ISD::SETCC) 813 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 814 } 815 816 bool DoXform = false; 817 bool InvCC = false; 818 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 819 "Bad input!"); 820 if (LHS.getOpcode() == ISD::Constant && 821 cast<ConstantSDNode>(LHS)->isNullValue()) 822 DoXform = true; 823 else if (CC != ISD::SETCC_INVALID && 824 RHS.getOpcode() == ISD::Constant && 825 cast<ConstantSDNode>(RHS)->isNullValue()) { 826 std::swap(LHS, RHS); 827 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType() 828 : Slct.getOperand(0).getOperand(0).getValueType()); 829 CC = ISD::getSetCCInverse(CC, isInt); 830 DoXform = true; 831 InvCC = true; 832 } 833 834 if (DoXform) { 835 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 836 if (isSlctCC) 837 return DAG.getSelectCC(OtherOp, Result, 838 Slct.getOperand(0), Slct.getOperand(1), CC); 839 SDOperand CCOp = Slct.getOperand(0); 840 if (InvCC) 841 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 842 CCOp.getOperand(1), CC); 843 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 844 } 845 return SDOperand(); 846} 847 848SDOperand DAGCombiner::visitADD(SDNode *N) { 849 SDOperand N0 = N->getOperand(0); 850 SDOperand N1 = N->getOperand(1); 851 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 852 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 853 MVT::ValueType VT = N0.getValueType(); 854 855 // fold vector ops 856 if (MVT::isVector(VT)) { 857 SDOperand FoldedVOp = SimplifyVBinOp(N); 858 if (FoldedVOp.Val) return FoldedVOp; 859 } 860 861 // fold (add x, undef) -> undef 862 if (N0.getOpcode() == ISD::UNDEF) 863 return N0; 864 if (N1.getOpcode() == ISD::UNDEF) 865 return N1; 866 // fold (add c1, c2) -> c1+c2 867 if (N0C && N1C) 868 return DAG.getNode(ISD::ADD, VT, N0, N1); 869 // canonicalize constant to RHS 870 if (N0C && !N1C) 871 return DAG.getNode(ISD::ADD, VT, N1, N0); 872 // fold (add x, 0) -> x 873 if (N1C && N1C->isNullValue()) 874 return N0; 875 // fold ((c1-A)+c2) -> (c1+c2)-A 876 if (N1C && N0.getOpcode() == ISD::SUB) 877 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 878 return DAG.getNode(ISD::SUB, VT, 879 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 880 N0.getOperand(1)); 881 // reassociate add 882 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 883 if (RADD.Val != 0) 884 return RADD; 885 // fold ((0-A) + B) -> B-A 886 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 887 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 888 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 889 // fold (A + (0-B)) -> A-B 890 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 891 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 892 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 893 // fold (A+(B-A)) -> B 894 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 895 return N1.getOperand(0); 896 897 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 898 return SDOperand(N, 0); 899 900 // fold (a+b) -> (a|b) iff a and b share no bits. 901 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 902 uint64_t LHSZero, LHSOne; 903 uint64_t RHSZero, RHSOne; 904 uint64_t Mask = MVT::getIntVTBitMask(VT); 905 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 906 if (LHSZero) { 907 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 908 909 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 910 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 911 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 912 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 913 return DAG.getNode(ISD::OR, VT, N0, N1); 914 } 915 } 916 917 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 918 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 919 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 920 if (Result.Val) return Result; 921 } 922 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 923 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 924 if (Result.Val) return Result; 925 } 926 927 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 928 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 929 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 930 if (Result.Val) return Result; 931 } 932 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 933 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 934 if (Result.Val) return Result; 935 } 936 937 return SDOperand(); 938} 939 940SDOperand DAGCombiner::visitADDC(SDNode *N) { 941 SDOperand N0 = N->getOperand(0); 942 SDOperand N1 = N->getOperand(1); 943 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 944 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 945 MVT::ValueType VT = N0.getValueType(); 946 947 // If the flag result is dead, turn this into an ADD. 948 if (N->hasNUsesOfValue(0, 1)) 949 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 950 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 951 952 // canonicalize constant to RHS. 953 if (N0C && !N1C) { 954 SDOperand Ops[] = { N1, N0 }; 955 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 956 } 957 958 // fold (addc x, 0) -> x + no carry out 959 if (N1C && N1C->isNullValue()) 960 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 961 962 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 963 uint64_t LHSZero, LHSOne; 964 uint64_t RHSZero, RHSOne; 965 uint64_t Mask = MVT::getIntVTBitMask(VT); 966 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 967 if (LHSZero) { 968 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 969 970 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 971 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 972 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 973 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 974 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 975 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 976 } 977 978 return SDOperand(); 979} 980 981SDOperand DAGCombiner::visitADDE(SDNode *N) { 982 SDOperand N0 = N->getOperand(0); 983 SDOperand N1 = N->getOperand(1); 984 SDOperand CarryIn = N->getOperand(2); 985 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 986 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 987 //MVT::ValueType VT = N0.getValueType(); 988 989 // canonicalize constant to RHS 990 if (N0C && !N1C) { 991 SDOperand Ops[] = { N1, N0, CarryIn }; 992 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 993 } 994 995 // fold (adde x, y, false) -> (addc x, y) 996 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 997 SDOperand Ops[] = { N1, N0 }; 998 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 999 } 1000 1001 return SDOperand(); 1002} 1003 1004 1005 1006SDOperand DAGCombiner::visitSUB(SDNode *N) { 1007 SDOperand N0 = N->getOperand(0); 1008 SDOperand N1 = N->getOperand(1); 1009 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1010 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1011 MVT::ValueType VT = N0.getValueType(); 1012 1013 // fold vector ops 1014 if (MVT::isVector(VT)) { 1015 SDOperand FoldedVOp = SimplifyVBinOp(N); 1016 if (FoldedVOp.Val) return FoldedVOp; 1017 } 1018 1019 // fold (sub x, x) -> 0 1020 if (N0 == N1) 1021 return DAG.getConstant(0, N->getValueType(0)); 1022 // fold (sub c1, c2) -> c1-c2 1023 if (N0C && N1C) 1024 return DAG.getNode(ISD::SUB, VT, N0, N1); 1025 // fold (sub x, c) -> (add x, -c) 1026 if (N1C) 1027 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1028 // fold (A+B)-A -> B 1029 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1030 return N0.getOperand(1); 1031 // fold (A+B)-B -> A 1032 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1033 return N0.getOperand(0); 1034 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1035 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1036 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1037 if (Result.Val) return Result; 1038 } 1039 // If either operand of a sub is undef, the result is undef 1040 if (N0.getOpcode() == ISD::UNDEF) 1041 return N0; 1042 if (N1.getOpcode() == ISD::UNDEF) 1043 return N1; 1044 1045 return SDOperand(); 1046} 1047 1048SDOperand DAGCombiner::visitMUL(SDNode *N) { 1049 SDOperand N0 = N->getOperand(0); 1050 SDOperand N1 = N->getOperand(1); 1051 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1052 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1053 MVT::ValueType VT = N0.getValueType(); 1054 1055 // fold vector ops 1056 if (MVT::isVector(VT)) { 1057 SDOperand FoldedVOp = SimplifyVBinOp(N); 1058 if (FoldedVOp.Val) return FoldedVOp; 1059 } 1060 1061 // fold (mul x, undef) -> 0 1062 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1063 return DAG.getConstant(0, VT); 1064 // fold (mul c1, c2) -> c1*c2 1065 if (N0C && N1C) 1066 return DAG.getNode(ISD::MUL, VT, N0, N1); 1067 // canonicalize constant to RHS 1068 if (N0C && !N1C) 1069 return DAG.getNode(ISD::MUL, VT, N1, N0); 1070 // fold (mul x, 0) -> 0 1071 if (N1C && N1C->isNullValue()) 1072 return N1; 1073 // fold (mul x, -1) -> 0-x 1074 if (N1C && N1C->isAllOnesValue()) 1075 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1076 // fold (mul x, (1 << c)) -> x << c 1077 if (N1C && isPowerOf2_64(N1C->getValue())) 1078 return DAG.getNode(ISD::SHL, VT, N0, 1079 DAG.getConstant(Log2_64(N1C->getValue()), 1080 TLI.getShiftAmountTy())); 1081 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1082 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1083 // FIXME: If the input is something that is easily negated (e.g. a 1084 // single-use add), we should put the negate there. 1085 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1086 DAG.getNode(ISD::SHL, VT, N0, 1087 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1088 TLI.getShiftAmountTy()))); 1089 } 1090 1091 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1092 if (N1C && N0.getOpcode() == ISD::SHL && 1093 isa<ConstantSDNode>(N0.getOperand(1))) { 1094 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1095 AddToWorkList(C3.Val); 1096 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1097 } 1098 1099 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1100 // use. 1101 { 1102 SDOperand Sh(0,0), Y(0,0); 1103 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1104 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1105 N0.Val->hasOneUse()) { 1106 Sh = N0; Y = N1; 1107 } else if (N1.getOpcode() == ISD::SHL && 1108 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1109 Sh = N1; Y = N0; 1110 } 1111 if (Sh.Val) { 1112 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1113 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1114 } 1115 } 1116 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1117 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1118 isa<ConstantSDNode>(N0.getOperand(1))) { 1119 return DAG.getNode(ISD::ADD, VT, 1120 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1121 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1122 } 1123 1124 // reassociate mul 1125 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1126 if (RMUL.Val != 0) 1127 return RMUL; 1128 1129 return SDOperand(); 1130} 1131 1132SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1133 SDOperand N0 = N->getOperand(0); 1134 SDOperand N1 = N->getOperand(1); 1135 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1136 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1137 MVT::ValueType VT = N->getValueType(0); 1138 1139 // fold vector ops 1140 if (MVT::isVector(VT)) { 1141 SDOperand FoldedVOp = SimplifyVBinOp(N); 1142 if (FoldedVOp.Val) return FoldedVOp; 1143 } 1144 1145 // fold (sdiv c1, c2) -> c1/c2 1146 if (N0C && N1C && !N1C->isNullValue()) 1147 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1148 // fold (sdiv X, 1) -> X 1149 if (N1C && N1C->getSignExtended() == 1LL) 1150 return N0; 1151 // fold (sdiv X, -1) -> 0-X 1152 if (N1C && N1C->isAllOnesValue()) 1153 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1154 // If we know the sign bits of both operands are zero, strength reduce to a 1155 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1156 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1157 if (DAG.MaskedValueIsZero(N1, SignBit) && 1158 DAG.MaskedValueIsZero(N0, SignBit)) 1159 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1160 // fold (sdiv X, pow2) -> simple ops after legalize 1161 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1162 (isPowerOf2_64(N1C->getSignExtended()) || 1163 isPowerOf2_64(-N1C->getSignExtended()))) { 1164 // If dividing by powers of two is cheap, then don't perform the following 1165 // fold. 1166 if (TLI.isPow2DivCheap()) 1167 return SDOperand(); 1168 int64_t pow2 = N1C->getSignExtended(); 1169 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1170 unsigned lg2 = Log2_64(abs2); 1171 // Splat the sign bit into the register 1172 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1173 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1174 TLI.getShiftAmountTy())); 1175 AddToWorkList(SGN.Val); 1176 // Add (N0 < 0) ? abs2 - 1 : 0; 1177 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1178 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1179 TLI.getShiftAmountTy())); 1180 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1181 AddToWorkList(SRL.Val); 1182 AddToWorkList(ADD.Val); // Divide by pow2 1183 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1184 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1185 // If we're dividing by a positive value, we're done. Otherwise, we must 1186 // negate the result. 1187 if (pow2 > 0) 1188 return SRA; 1189 AddToWorkList(SRA.Val); 1190 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1191 } 1192 // if integer divide is expensive and we satisfy the requirements, emit an 1193 // alternate sequence. 1194 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1195 !TLI.isIntDivCheap()) { 1196 SDOperand Op = BuildSDIV(N); 1197 if (Op.Val) return Op; 1198 } 1199 1200 // undef / X -> 0 1201 if (N0.getOpcode() == ISD::UNDEF) 1202 return DAG.getConstant(0, VT); 1203 // X / undef -> undef 1204 if (N1.getOpcode() == ISD::UNDEF) 1205 return N1; 1206 1207 return SDOperand(); 1208} 1209 1210SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1211 SDOperand N0 = N->getOperand(0); 1212 SDOperand N1 = N->getOperand(1); 1213 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1214 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1215 MVT::ValueType VT = N->getValueType(0); 1216 1217 // fold vector ops 1218 if (MVT::isVector(VT)) { 1219 SDOperand FoldedVOp = SimplifyVBinOp(N); 1220 if (FoldedVOp.Val) return FoldedVOp; 1221 } 1222 1223 // fold (udiv c1, c2) -> c1/c2 1224 if (N0C && N1C && !N1C->isNullValue()) 1225 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1226 // fold (udiv x, (1 << c)) -> x >>u c 1227 if (N1C && isPowerOf2_64(N1C->getValue())) 1228 return DAG.getNode(ISD::SRL, VT, N0, 1229 DAG.getConstant(Log2_64(N1C->getValue()), 1230 TLI.getShiftAmountTy())); 1231 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1232 if (N1.getOpcode() == ISD::SHL) { 1233 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1234 if (isPowerOf2_64(SHC->getValue())) { 1235 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1236 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1237 DAG.getConstant(Log2_64(SHC->getValue()), 1238 ADDVT)); 1239 AddToWorkList(Add.Val); 1240 return DAG.getNode(ISD::SRL, VT, N0, Add); 1241 } 1242 } 1243 } 1244 // fold (udiv x, c) -> alternate 1245 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1246 SDOperand Op = BuildUDIV(N); 1247 if (Op.Val) return Op; 1248 } 1249 1250 // undef / X -> 0 1251 if (N0.getOpcode() == ISD::UNDEF) 1252 return DAG.getConstant(0, VT); 1253 // X / undef -> undef 1254 if (N1.getOpcode() == ISD::UNDEF) 1255 return N1; 1256 1257 return SDOperand(); 1258} 1259 1260SDOperand DAGCombiner::visitSREM(SDNode *N) { 1261 SDOperand N0 = N->getOperand(0); 1262 SDOperand N1 = N->getOperand(1); 1263 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1264 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1265 MVT::ValueType VT = N->getValueType(0); 1266 1267 // fold (srem c1, c2) -> c1%c2 1268 if (N0C && N1C && !N1C->isNullValue()) 1269 return DAG.getNode(ISD::SREM, VT, N0, N1); 1270 // If we know the sign bits of both operands are zero, strength reduce to a 1271 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1272 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1273 if (DAG.MaskedValueIsZero(N1, SignBit) && 1274 DAG.MaskedValueIsZero(N0, SignBit)) 1275 return DAG.getNode(ISD::UREM, VT, N0, N1); 1276 1277 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1278 // the remainder operation. 1279 if (N1C && !N1C->isNullValue()) { 1280 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1281 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1282 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1283 AddToWorkList(Div.Val); 1284 AddToWorkList(Mul.Val); 1285 return Sub; 1286 } 1287 1288 // undef % X -> 0 1289 if (N0.getOpcode() == ISD::UNDEF) 1290 return DAG.getConstant(0, VT); 1291 // X % undef -> undef 1292 if (N1.getOpcode() == ISD::UNDEF) 1293 return N1; 1294 1295 return SDOperand(); 1296} 1297 1298SDOperand DAGCombiner::visitUREM(SDNode *N) { 1299 SDOperand N0 = N->getOperand(0); 1300 SDOperand N1 = N->getOperand(1); 1301 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1302 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1303 MVT::ValueType VT = N->getValueType(0); 1304 1305 // fold (urem c1, c2) -> c1%c2 1306 if (N0C && N1C && !N1C->isNullValue()) 1307 return DAG.getNode(ISD::UREM, VT, N0, N1); 1308 // fold (urem x, pow2) -> (and x, pow2-1) 1309 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1310 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1311 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1312 if (N1.getOpcode() == ISD::SHL) { 1313 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1314 if (isPowerOf2_64(SHC->getValue())) { 1315 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1316 AddToWorkList(Add.Val); 1317 return DAG.getNode(ISD::AND, VT, N0, Add); 1318 } 1319 } 1320 } 1321 1322 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1323 // the remainder operation. 1324 if (N1C && !N1C->isNullValue()) { 1325 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1326 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1327 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1328 AddToWorkList(Div.Val); 1329 AddToWorkList(Mul.Val); 1330 return Sub; 1331 } 1332 1333 // undef % X -> 0 1334 if (N0.getOpcode() == ISD::UNDEF) 1335 return DAG.getConstant(0, VT); 1336 // X % undef -> undef 1337 if (N1.getOpcode() == ISD::UNDEF) 1338 return N1; 1339 1340 return SDOperand(); 1341} 1342 1343SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1344 SDOperand N0 = N->getOperand(0); 1345 SDOperand N1 = N->getOperand(1); 1346 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1347 MVT::ValueType VT = N->getValueType(0); 1348 1349 // fold (mulhs x, 0) -> 0 1350 if (N1C && N1C->isNullValue()) 1351 return N1; 1352 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1353 if (N1C && N1C->getValue() == 1) 1354 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1355 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1356 TLI.getShiftAmountTy())); 1357 // fold (mulhs x, undef) -> 0 1358 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1359 return DAG.getConstant(0, VT); 1360 1361 return SDOperand(); 1362} 1363 1364SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1365 SDOperand N0 = N->getOperand(0); 1366 SDOperand N1 = N->getOperand(1); 1367 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1368 MVT::ValueType VT = N->getValueType(0); 1369 1370 // fold (mulhu x, 0) -> 0 1371 if (N1C && N1C->isNullValue()) 1372 return N1; 1373 // fold (mulhu x, 1) -> 0 1374 if (N1C && N1C->getValue() == 1) 1375 return DAG.getConstant(0, N0.getValueType()); 1376 // fold (mulhu x, undef) -> 0 1377 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1378 return DAG.getConstant(0, VT); 1379 1380 return SDOperand(); 1381} 1382 1383/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1384/// two operands of the same opcode, try to simplify it. 1385SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1386 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1387 MVT::ValueType VT = N0.getValueType(); 1388 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1389 1390 // For each of OP in AND/OR/XOR: 1391 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1392 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1393 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1394 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1395 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1396 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1397 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1398 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1399 N0.getOperand(0).getValueType(), 1400 N0.getOperand(0), N1.getOperand(0)); 1401 AddToWorkList(ORNode.Val); 1402 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1403 } 1404 1405 // For each of OP in SHL/SRL/SRA/AND... 1406 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1407 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1408 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1409 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1410 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1411 N0.getOperand(1) == N1.getOperand(1)) { 1412 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1413 N0.getOperand(0).getValueType(), 1414 N0.getOperand(0), N1.getOperand(0)); 1415 AddToWorkList(ORNode.Val); 1416 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1417 } 1418 1419 return SDOperand(); 1420} 1421 1422SDOperand DAGCombiner::visitAND(SDNode *N) { 1423 SDOperand N0 = N->getOperand(0); 1424 SDOperand N1 = N->getOperand(1); 1425 SDOperand LL, LR, RL, RR, CC0, CC1; 1426 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1427 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1428 MVT::ValueType VT = N1.getValueType(); 1429 1430 // fold vector ops 1431 if (MVT::isVector(VT)) { 1432 SDOperand FoldedVOp = SimplifyVBinOp(N); 1433 if (FoldedVOp.Val) return FoldedVOp; 1434 } 1435 1436 // fold (and x, undef) -> 0 1437 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1438 return DAG.getConstant(0, VT); 1439 // fold (and c1, c2) -> c1&c2 1440 if (N0C && N1C) 1441 return DAG.getNode(ISD::AND, VT, N0, N1); 1442 // canonicalize constant to RHS 1443 if (N0C && !N1C) 1444 return DAG.getNode(ISD::AND, VT, N1, N0); 1445 // fold (and x, -1) -> x 1446 if (N1C && N1C->isAllOnesValue()) 1447 return N0; 1448 // if (and x, c) is known to be zero, return 0 1449 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1450 return DAG.getConstant(0, VT); 1451 // reassociate and 1452 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1453 if (RAND.Val != 0) 1454 return RAND; 1455 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1456 if (N1C && N0.getOpcode() == ISD::OR) 1457 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1458 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1459 return N1; 1460 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1461 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1462 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1463 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1464 ~N1C->getValue() & InMask)) { 1465 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1466 N0.getOperand(0)); 1467 1468 // Replace uses of the AND with uses of the Zero extend node. 1469 CombineTo(N, Zext); 1470 1471 // We actually want to replace all uses of the any_extend with the 1472 // zero_extend, to avoid duplicating things. This will later cause this 1473 // AND to be folded. 1474 CombineTo(N0.Val, Zext); 1475 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1476 } 1477 } 1478 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1479 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1480 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1481 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1482 1483 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1484 MVT::isInteger(LL.getValueType())) { 1485 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1486 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1487 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1488 AddToWorkList(ORNode.Val); 1489 return DAG.getSetCC(VT, ORNode, LR, Op1); 1490 } 1491 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1492 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1493 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1494 AddToWorkList(ANDNode.Val); 1495 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1496 } 1497 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1498 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1499 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1500 AddToWorkList(ORNode.Val); 1501 return DAG.getSetCC(VT, ORNode, LR, Op1); 1502 } 1503 } 1504 // canonicalize equivalent to ll == rl 1505 if (LL == RR && LR == RL) { 1506 Op1 = ISD::getSetCCSwappedOperands(Op1); 1507 std::swap(RL, RR); 1508 } 1509 if (LL == RL && LR == RR) { 1510 bool isInteger = MVT::isInteger(LL.getValueType()); 1511 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1512 if (Result != ISD::SETCC_INVALID) 1513 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1514 } 1515 } 1516 1517 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1518 if (N0.getOpcode() == N1.getOpcode()) { 1519 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1520 if (Tmp.Val) return Tmp; 1521 } 1522 1523 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1524 // fold (and (sra)) -> (and (srl)) when possible. 1525 if (!MVT::isVector(VT) && 1526 SimplifyDemandedBits(SDOperand(N, 0))) 1527 return SDOperand(N, 0); 1528 // fold (zext_inreg (extload x)) -> (zextload x) 1529 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1530 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1531 MVT::ValueType EVT = LN0->getLoadedVT(); 1532 // If we zero all the possible extended bits, then we can turn this into 1533 // a zextload if we are running before legalize or the operation is legal. 1534 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1535 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1536 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1537 LN0->getBasePtr(), LN0->getSrcValue(), 1538 LN0->getSrcValueOffset(), EVT, 1539 LN0->isVolatile(), 1540 LN0->getAlignment()); 1541 AddToWorkList(N); 1542 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1543 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1544 } 1545 } 1546 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1547 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1548 N0.hasOneUse()) { 1549 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1550 MVT::ValueType EVT = LN0->getLoadedVT(); 1551 // If we zero all the possible extended bits, then we can turn this into 1552 // a zextload if we are running before legalize or the operation is legal. 1553 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1554 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1555 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1556 LN0->getBasePtr(), LN0->getSrcValue(), 1557 LN0->getSrcValueOffset(), EVT, 1558 LN0->isVolatile(), 1559 LN0->getAlignment()); 1560 AddToWorkList(N); 1561 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1562 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1563 } 1564 } 1565 1566 // fold (and (load x), 255) -> (zextload x, i8) 1567 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1568 if (N1C && N0.getOpcode() == ISD::LOAD) { 1569 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1570 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1571 LN0->getAddressingMode() == ISD::UNINDEXED && 1572 N0.hasOneUse()) { 1573 MVT::ValueType EVT, LoadedVT; 1574 if (N1C->getValue() == 255) 1575 EVT = MVT::i8; 1576 else if (N1C->getValue() == 65535) 1577 EVT = MVT::i16; 1578 else if (N1C->getValue() == ~0U) 1579 EVT = MVT::i32; 1580 else 1581 EVT = MVT::Other; 1582 1583 LoadedVT = LN0->getLoadedVT(); 1584 if (EVT != MVT::Other && LoadedVT > EVT && 1585 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1586 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1587 // For big endian targets, we need to add an offset to the pointer to 1588 // load the correct bytes. For little endian systems, we merely need to 1589 // read fewer bytes from the same pointer. 1590 unsigned PtrOff = 1591 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1592 SDOperand NewPtr = LN0->getBasePtr(); 1593 if (!TLI.isLittleEndian()) 1594 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1595 DAG.getConstant(PtrOff, PtrType)); 1596 AddToWorkList(NewPtr.Val); 1597 SDOperand Load = 1598 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1599 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1600 LN0->isVolatile(), LN0->getAlignment()); 1601 AddToWorkList(N); 1602 CombineTo(N0.Val, Load, Load.getValue(1)); 1603 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1604 } 1605 } 1606 } 1607 1608 return SDOperand(); 1609} 1610 1611SDOperand DAGCombiner::visitOR(SDNode *N) { 1612 SDOperand N0 = N->getOperand(0); 1613 SDOperand N1 = N->getOperand(1); 1614 SDOperand LL, LR, RL, RR, CC0, CC1; 1615 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1616 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1617 MVT::ValueType VT = N1.getValueType(); 1618 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1619 1620 // fold vector ops 1621 if (MVT::isVector(VT)) { 1622 SDOperand FoldedVOp = SimplifyVBinOp(N); 1623 if (FoldedVOp.Val) return FoldedVOp; 1624 } 1625 1626 // fold (or x, undef) -> -1 1627 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1628 return DAG.getConstant(~0ULL, VT); 1629 // fold (or c1, c2) -> c1|c2 1630 if (N0C && N1C) 1631 return DAG.getNode(ISD::OR, VT, N0, N1); 1632 // canonicalize constant to RHS 1633 if (N0C && !N1C) 1634 return DAG.getNode(ISD::OR, VT, N1, N0); 1635 // fold (or x, 0) -> x 1636 if (N1C && N1C->isNullValue()) 1637 return N0; 1638 // fold (or x, -1) -> -1 1639 if (N1C && N1C->isAllOnesValue()) 1640 return N1; 1641 // fold (or x, c) -> c iff (x & ~c) == 0 1642 if (N1C && 1643 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1644 return N1; 1645 // reassociate or 1646 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1647 if (ROR.Val != 0) 1648 return ROR; 1649 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1650 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1651 isa<ConstantSDNode>(N0.getOperand(1))) { 1652 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1653 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1654 N1), 1655 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1656 } 1657 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1658 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1659 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1660 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1661 1662 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1663 MVT::isInteger(LL.getValueType())) { 1664 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1665 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1666 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1667 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1668 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1669 AddToWorkList(ORNode.Val); 1670 return DAG.getSetCC(VT, ORNode, LR, Op1); 1671 } 1672 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1673 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1674 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1675 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1676 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1677 AddToWorkList(ANDNode.Val); 1678 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1679 } 1680 } 1681 // canonicalize equivalent to ll == rl 1682 if (LL == RR && LR == RL) { 1683 Op1 = ISD::getSetCCSwappedOperands(Op1); 1684 std::swap(RL, RR); 1685 } 1686 if (LL == RL && LR == RR) { 1687 bool isInteger = MVT::isInteger(LL.getValueType()); 1688 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1689 if (Result != ISD::SETCC_INVALID) 1690 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1691 } 1692 } 1693 1694 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1695 if (N0.getOpcode() == N1.getOpcode()) { 1696 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1697 if (Tmp.Val) return Tmp; 1698 } 1699 1700 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1701 if (N0.getOpcode() == ISD::AND && 1702 N1.getOpcode() == ISD::AND && 1703 N0.getOperand(1).getOpcode() == ISD::Constant && 1704 N1.getOperand(1).getOpcode() == ISD::Constant && 1705 // Don't increase # computations. 1706 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1707 // We can only do this xform if we know that bits from X that are set in C2 1708 // but not in C1 are already zero. Likewise for Y. 1709 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1710 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1711 1712 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1713 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1714 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1715 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1716 } 1717 } 1718 1719 1720 // See if this is some rotate idiom. 1721 if (SDNode *Rot = MatchRotate(N0, N1)) 1722 return SDOperand(Rot, 0); 1723 1724 return SDOperand(); 1725} 1726 1727 1728/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1729static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1730 if (Op.getOpcode() == ISD::AND) { 1731 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1732 Mask = Op.getOperand(1); 1733 Op = Op.getOperand(0); 1734 } else { 1735 return false; 1736 } 1737 } 1738 1739 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1740 Shift = Op; 1741 return true; 1742 } 1743 return false; 1744} 1745 1746 1747// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1748// idioms for rotate, and if the target supports rotation instructions, generate 1749// a rot[lr]. 1750SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1751 // Must be a legal type. Expanded an promoted things won't work with rotates. 1752 MVT::ValueType VT = LHS.getValueType(); 1753 if (!TLI.isTypeLegal(VT)) return 0; 1754 1755 // The target must have at least one rotate flavor. 1756 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1757 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1758 if (!HasROTL && !HasROTR) return 0; 1759 1760 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1761 SDOperand LHSShift; // The shift. 1762 SDOperand LHSMask; // AND value if any. 1763 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1764 return 0; // Not part of a rotate. 1765 1766 SDOperand RHSShift; // The shift. 1767 SDOperand RHSMask; // AND value if any. 1768 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1769 return 0; // Not part of a rotate. 1770 1771 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1772 return 0; // Not shifting the same value. 1773 1774 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1775 return 0; // Shifts must disagree. 1776 1777 // Canonicalize shl to left side in a shl/srl pair. 1778 if (RHSShift.getOpcode() == ISD::SHL) { 1779 std::swap(LHS, RHS); 1780 std::swap(LHSShift, RHSShift); 1781 std::swap(LHSMask , RHSMask ); 1782 } 1783 1784 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1785 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1786 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1787 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1788 1789 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1790 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1791 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1792 RHSShiftAmt.getOpcode() == ISD::Constant) { 1793 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1794 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1795 if ((LShVal + RShVal) != OpSizeInBits) 1796 return 0; 1797 1798 SDOperand Rot; 1799 if (HasROTL) 1800 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1801 else 1802 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1803 1804 // If there is an AND of either shifted operand, apply it to the result. 1805 if (LHSMask.Val || RHSMask.Val) { 1806 uint64_t Mask = MVT::getIntVTBitMask(VT); 1807 1808 if (LHSMask.Val) { 1809 uint64_t RHSBits = (1ULL << LShVal)-1; 1810 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1811 } 1812 if (RHSMask.Val) { 1813 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1814 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1815 } 1816 1817 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1818 } 1819 1820 return Rot.Val; 1821 } 1822 1823 // If there is a mask here, and we have a variable shift, we can't be sure 1824 // that we're masking out the right stuff. 1825 if (LHSMask.Val || RHSMask.Val) 1826 return 0; 1827 1828 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1829 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1830 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1831 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1832 if (ConstantSDNode *SUBC = 1833 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1834 if (SUBC->getValue() == OpSizeInBits) 1835 if (HasROTL) 1836 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1837 else 1838 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1839 } 1840 } 1841 1842 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1843 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1844 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1845 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1846 if (ConstantSDNode *SUBC = 1847 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1848 if (SUBC->getValue() == OpSizeInBits) 1849 if (HasROTL) 1850 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1851 else 1852 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1853 } 1854 } 1855 1856 // Look for sign/zext/any-extended cases: 1857 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1858 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1859 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1860 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1861 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1862 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1863 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1864 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1865 if (RExtOp0.getOpcode() == ISD::SUB && 1866 RExtOp0.getOperand(1) == LExtOp0) { 1867 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1868 // (rotr x, y) 1869 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1870 // (rotl x, (sub 32, y)) 1871 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1872 if (SUBC->getValue() == OpSizeInBits) { 1873 if (HasROTL) 1874 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1875 else 1876 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1877 } 1878 } 1879 } else if (LExtOp0.getOpcode() == ISD::SUB && 1880 RExtOp0 == LExtOp0.getOperand(1)) { 1881 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1882 // (rotl x, y) 1883 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1884 // (rotr x, (sub 32, y)) 1885 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 1886 if (SUBC->getValue() == OpSizeInBits) { 1887 if (HasROTL) 1888 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 1889 else 1890 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1891 } 1892 } 1893 } 1894 } 1895 1896 return 0; 1897} 1898 1899 1900SDOperand DAGCombiner::visitXOR(SDNode *N) { 1901 SDOperand N0 = N->getOperand(0); 1902 SDOperand N1 = N->getOperand(1); 1903 SDOperand LHS, RHS, CC; 1904 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1905 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1906 MVT::ValueType VT = N0.getValueType(); 1907 1908 // fold vector ops 1909 if (MVT::isVector(VT)) { 1910 SDOperand FoldedVOp = SimplifyVBinOp(N); 1911 if (FoldedVOp.Val) return FoldedVOp; 1912 } 1913 1914 // fold (xor x, undef) -> undef 1915 if (N0.getOpcode() == ISD::UNDEF) 1916 return N0; 1917 if (N1.getOpcode() == ISD::UNDEF) 1918 return N1; 1919 // fold (xor c1, c2) -> c1^c2 1920 if (N0C && N1C) 1921 return DAG.getNode(ISD::XOR, VT, N0, N1); 1922 // canonicalize constant to RHS 1923 if (N0C && !N1C) 1924 return DAG.getNode(ISD::XOR, VT, N1, N0); 1925 // fold (xor x, 0) -> x 1926 if (N1C && N1C->isNullValue()) 1927 return N0; 1928 // reassociate xor 1929 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1930 if (RXOR.Val != 0) 1931 return RXOR; 1932 // fold !(x cc y) -> (x !cc y) 1933 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1934 bool isInt = MVT::isInteger(LHS.getValueType()); 1935 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1936 isInt); 1937 if (N0.getOpcode() == ISD::SETCC) 1938 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1939 if (N0.getOpcode() == ISD::SELECT_CC) 1940 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1941 assert(0 && "Unhandled SetCC Equivalent!"); 1942 abort(); 1943 } 1944 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 1945 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 1946 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 1947 SDOperand V = N0.getOperand(0); 1948 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 1949 DAG.getConstant(V.getValueType(), 1)); 1950 AddToWorkList(V.Val); 1951 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 1952 } 1953 1954 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1955 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 1956 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1957 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1958 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1959 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1960 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1961 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1962 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1963 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1964 } 1965 } 1966 // fold !(x or y) -> (!x and !y) iff x or y are constants 1967 if (N1C && N1C->isAllOnesValue() && 1968 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1969 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1970 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1971 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1972 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1973 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1974 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1975 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1976 } 1977 } 1978 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1979 if (N1C && N0.getOpcode() == ISD::XOR) { 1980 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1981 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1982 if (N00C) 1983 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1984 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1985 if (N01C) 1986 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1987 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1988 } 1989 // fold (xor x, x) -> 0 1990 if (N0 == N1) { 1991 if (!MVT::isVector(VT)) { 1992 return DAG.getConstant(0, VT); 1993 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1994 // Produce a vector of zeros. 1995 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 1996 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1997 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1998 } 1999 } 2000 2001 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2002 if (N0.getOpcode() == N1.getOpcode()) { 2003 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2004 if (Tmp.Val) return Tmp; 2005 } 2006 2007 // Simplify the expression using non-local knowledge. 2008 if (!MVT::isVector(VT) && 2009 SimplifyDemandedBits(SDOperand(N, 0))) 2010 return SDOperand(N, 0); 2011 2012 return SDOperand(); 2013} 2014 2015SDOperand DAGCombiner::visitSHL(SDNode *N) { 2016 SDOperand N0 = N->getOperand(0); 2017 SDOperand N1 = N->getOperand(1); 2018 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2019 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2020 MVT::ValueType VT = N0.getValueType(); 2021 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2022 2023 // fold (shl c1, c2) -> c1<<c2 2024 if (N0C && N1C) 2025 return DAG.getNode(ISD::SHL, VT, N0, N1); 2026 // fold (shl 0, x) -> 0 2027 if (N0C && N0C->isNullValue()) 2028 return N0; 2029 // fold (shl x, c >= size(x)) -> undef 2030 if (N1C && N1C->getValue() >= OpSizeInBits) 2031 return DAG.getNode(ISD::UNDEF, VT); 2032 // fold (shl x, 0) -> x 2033 if (N1C && N1C->isNullValue()) 2034 return N0; 2035 // if (shl x, c) is known to be zero, return 0 2036 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2037 return DAG.getConstant(0, VT); 2038 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2039 return SDOperand(N, 0); 2040 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2041 if (N1C && N0.getOpcode() == ISD::SHL && 2042 N0.getOperand(1).getOpcode() == ISD::Constant) { 2043 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2044 uint64_t c2 = N1C->getValue(); 2045 if (c1 + c2 > OpSizeInBits) 2046 return DAG.getConstant(0, VT); 2047 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2048 DAG.getConstant(c1 + c2, N1.getValueType())); 2049 } 2050 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2051 // (srl (and x, -1 << c1), c1-c2) 2052 if (N1C && N0.getOpcode() == ISD::SRL && 2053 N0.getOperand(1).getOpcode() == ISD::Constant) { 2054 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2055 uint64_t c2 = N1C->getValue(); 2056 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2057 DAG.getConstant(~0ULL << c1, VT)); 2058 if (c2 > c1) 2059 return DAG.getNode(ISD::SHL, VT, Mask, 2060 DAG.getConstant(c2-c1, N1.getValueType())); 2061 else 2062 return DAG.getNode(ISD::SRL, VT, Mask, 2063 DAG.getConstant(c1-c2, N1.getValueType())); 2064 } 2065 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2066 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2067 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2068 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2069 return SDOperand(); 2070} 2071 2072SDOperand DAGCombiner::visitSRA(SDNode *N) { 2073 SDOperand N0 = N->getOperand(0); 2074 SDOperand N1 = N->getOperand(1); 2075 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2076 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2077 MVT::ValueType VT = N0.getValueType(); 2078 2079 // fold (sra c1, c2) -> c1>>c2 2080 if (N0C && N1C) 2081 return DAG.getNode(ISD::SRA, VT, N0, N1); 2082 // fold (sra 0, x) -> 0 2083 if (N0C && N0C->isNullValue()) 2084 return N0; 2085 // fold (sra -1, x) -> -1 2086 if (N0C && N0C->isAllOnesValue()) 2087 return N0; 2088 // fold (sra x, c >= size(x)) -> undef 2089 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2090 return DAG.getNode(ISD::UNDEF, VT); 2091 // fold (sra x, 0) -> x 2092 if (N1C && N1C->isNullValue()) 2093 return N0; 2094 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2095 // sext_inreg. 2096 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2097 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2098 MVT::ValueType EVT; 2099 switch (LowBits) { 2100 default: EVT = MVT::Other; break; 2101 case 1: EVT = MVT::i1; break; 2102 case 8: EVT = MVT::i8; break; 2103 case 16: EVT = MVT::i16; break; 2104 case 32: EVT = MVT::i32; break; 2105 } 2106 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2107 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2108 DAG.getValueType(EVT)); 2109 } 2110 2111 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2112 if (N1C && N0.getOpcode() == ISD::SRA) { 2113 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2114 unsigned Sum = N1C->getValue() + C1->getValue(); 2115 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2116 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2117 DAG.getConstant(Sum, N1C->getValueType(0))); 2118 } 2119 } 2120 2121 // Simplify, based on bits shifted out of the LHS. 2122 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2123 return SDOperand(N, 0); 2124 2125 2126 // If the sign bit is known to be zero, switch this to a SRL. 2127 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2128 return DAG.getNode(ISD::SRL, VT, N0, N1); 2129 return SDOperand(); 2130} 2131 2132SDOperand DAGCombiner::visitSRL(SDNode *N) { 2133 SDOperand N0 = N->getOperand(0); 2134 SDOperand N1 = N->getOperand(1); 2135 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2136 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2137 MVT::ValueType VT = N0.getValueType(); 2138 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2139 2140 // fold (srl c1, c2) -> c1 >>u c2 2141 if (N0C && N1C) 2142 return DAG.getNode(ISD::SRL, VT, N0, N1); 2143 // fold (srl 0, x) -> 0 2144 if (N0C && N0C->isNullValue()) 2145 return N0; 2146 // fold (srl x, c >= size(x)) -> undef 2147 if (N1C && N1C->getValue() >= OpSizeInBits) 2148 return DAG.getNode(ISD::UNDEF, VT); 2149 // fold (srl x, 0) -> x 2150 if (N1C && N1C->isNullValue()) 2151 return N0; 2152 // if (srl x, c) is known to be zero, return 0 2153 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2154 return DAG.getConstant(0, VT); 2155 2156 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2157 if (N1C && N0.getOpcode() == ISD::SRL && 2158 N0.getOperand(1).getOpcode() == ISD::Constant) { 2159 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2160 uint64_t c2 = N1C->getValue(); 2161 if (c1 + c2 > OpSizeInBits) 2162 return DAG.getConstant(0, VT); 2163 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2164 DAG.getConstant(c1 + c2, N1.getValueType())); 2165 } 2166 2167 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2168 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2169 // Shifting in all undef bits? 2170 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2171 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2172 return DAG.getNode(ISD::UNDEF, VT); 2173 2174 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2175 AddToWorkList(SmallShift.Val); 2176 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2177 } 2178 2179 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2180 // bit, which is unmodified by sra. 2181 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2182 if (N0.getOpcode() == ISD::SRA) 2183 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2184 } 2185 2186 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2187 if (N1C && N0.getOpcode() == ISD::CTLZ && 2188 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2189 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2190 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2191 2192 // If any of the input bits are KnownOne, then the input couldn't be all 2193 // zeros, thus the result of the srl will always be zero. 2194 if (KnownOne) return DAG.getConstant(0, VT); 2195 2196 // If all of the bits input the to ctlz node are known to be zero, then 2197 // the result of the ctlz is "32" and the result of the shift is one. 2198 uint64_t UnknownBits = ~KnownZero & Mask; 2199 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2200 2201 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2202 if ((UnknownBits & (UnknownBits-1)) == 0) { 2203 // Okay, we know that only that the single bit specified by UnknownBits 2204 // could be set on input to the CTLZ node. If this bit is set, the SRL 2205 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2206 // to an SRL,XOR pair, which is likely to simplify more. 2207 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2208 SDOperand Op = N0.getOperand(0); 2209 if (ShAmt) { 2210 Op = DAG.getNode(ISD::SRL, VT, Op, 2211 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2212 AddToWorkList(Op.Val); 2213 } 2214 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2215 } 2216 } 2217 2218 // fold operands of srl based on knowledge that the low bits are not 2219 // demanded. 2220 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2221 return SDOperand(N, 0); 2222 2223 return SDOperand(); 2224} 2225 2226SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2227 SDOperand N0 = N->getOperand(0); 2228 MVT::ValueType VT = N->getValueType(0); 2229 2230 // fold (ctlz c1) -> c2 2231 if (isa<ConstantSDNode>(N0)) 2232 return DAG.getNode(ISD::CTLZ, VT, N0); 2233 return SDOperand(); 2234} 2235 2236SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2237 SDOperand N0 = N->getOperand(0); 2238 MVT::ValueType VT = N->getValueType(0); 2239 2240 // fold (cttz c1) -> c2 2241 if (isa<ConstantSDNode>(N0)) 2242 return DAG.getNode(ISD::CTTZ, VT, N0); 2243 return SDOperand(); 2244} 2245 2246SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2247 SDOperand N0 = N->getOperand(0); 2248 MVT::ValueType VT = N->getValueType(0); 2249 2250 // fold (ctpop c1) -> c2 2251 if (isa<ConstantSDNode>(N0)) 2252 return DAG.getNode(ISD::CTPOP, VT, N0); 2253 return SDOperand(); 2254} 2255 2256SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2257 SDOperand N0 = N->getOperand(0); 2258 SDOperand N1 = N->getOperand(1); 2259 SDOperand N2 = N->getOperand(2); 2260 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2261 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2262 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2263 MVT::ValueType VT = N->getValueType(0); 2264 MVT::ValueType VT0 = N0.getValueType(); 2265 2266 // fold select C, X, X -> X 2267 if (N1 == N2) 2268 return N1; 2269 // fold select true, X, Y -> X 2270 if (N0C && !N0C->isNullValue()) 2271 return N1; 2272 // fold select false, X, Y -> Y 2273 if (N0C && N0C->isNullValue()) 2274 return N2; 2275 // fold select C, 1, X -> C | X 2276 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2277 return DAG.getNode(ISD::OR, VT, N0, N2); 2278 // fold select C, 0, 1 -> ~C 2279 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2280 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2281 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2282 if (VT == VT0) 2283 return XORNode; 2284 AddToWorkList(XORNode.Val); 2285 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2286 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2287 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2288 } 2289 // fold select C, 0, X -> ~C & X 2290 if (VT == VT0 && N1C && N1C->isNullValue()) { 2291 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2292 AddToWorkList(XORNode.Val); 2293 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2294 } 2295 // fold select C, X, 1 -> ~C | X 2296 if (VT == VT0 && N2C && N2C->getValue() == 1) { 2297 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2298 AddToWorkList(XORNode.Val); 2299 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2300 } 2301 // fold select C, X, 0 -> C & X 2302 // FIXME: this should check for C type == X type, not i1? 2303 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2304 return DAG.getNode(ISD::AND, VT, N0, N1); 2305 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2306 if (MVT::i1 == VT && N0 == N1) 2307 return DAG.getNode(ISD::OR, VT, N0, N2); 2308 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2309 if (MVT::i1 == VT && N0 == N2) 2310 return DAG.getNode(ISD::AND, VT, N0, N1); 2311 2312 // If we can fold this based on the true/false value, do so. 2313 if (SimplifySelectOps(N, N1, N2)) 2314 return SDOperand(N, 0); // Don't revisit N. 2315 2316 // fold selects based on a setcc into other things, such as min/max/abs 2317 if (N0.getOpcode() == ISD::SETCC) 2318 // FIXME: 2319 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2320 // having to say they don't support SELECT_CC on every type the DAG knows 2321 // about, since there is no way to mark an opcode illegal at all value types 2322 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2323 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2324 N1, N2, N0.getOperand(2)); 2325 else 2326 return SimplifySelect(N0, N1, N2); 2327 return SDOperand(); 2328} 2329 2330SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2331 SDOperand N0 = N->getOperand(0); 2332 SDOperand N1 = N->getOperand(1); 2333 SDOperand N2 = N->getOperand(2); 2334 SDOperand N3 = N->getOperand(3); 2335 SDOperand N4 = N->getOperand(4); 2336 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2337 2338 // fold select_cc lhs, rhs, x, x, cc -> x 2339 if (N2 == N3) 2340 return N2; 2341 2342 // Determine if the condition we're dealing with is constant 2343 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2344 if (SCC.Val) AddToWorkList(SCC.Val); 2345 2346 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2347 if (SCCC->getValue()) 2348 return N2; // cond always true -> true val 2349 else 2350 return N3; // cond always false -> false val 2351 } 2352 2353 // Fold to a simpler select_cc 2354 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2355 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2356 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2357 SCC.getOperand(2)); 2358 2359 // If we can fold this based on the true/false value, do so. 2360 if (SimplifySelectOps(N, N2, N3)) 2361 return SDOperand(N, 0); // Don't revisit N. 2362 2363 // fold select_cc into other things, such as min/max/abs 2364 return SimplifySelectCC(N0, N1, N2, N3, CC); 2365} 2366 2367SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2368 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2369 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2370} 2371 2372SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2373 SDOperand N0 = N->getOperand(0); 2374 MVT::ValueType VT = N->getValueType(0); 2375 2376 // fold (sext c1) -> c1 2377 if (isa<ConstantSDNode>(N0)) 2378 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2379 2380 // fold (sext (sext x)) -> (sext x) 2381 // fold (sext (aext x)) -> (sext x) 2382 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2383 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2384 2385 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2386 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2387 if (N0.getOpcode() == ISD::TRUNCATE) { 2388 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2389 if (NarrowLoad.Val) { 2390 if (NarrowLoad.Val != N0.Val) 2391 CombineTo(N0.Val, NarrowLoad); 2392 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2393 } 2394 } 2395 2396 // See if the value being truncated is already sign extended. If so, just 2397 // eliminate the trunc/sext pair. 2398 if (N0.getOpcode() == ISD::TRUNCATE) { 2399 SDOperand Op = N0.getOperand(0); 2400 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2401 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2402 unsigned DestBits = MVT::getSizeInBits(VT); 2403 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2404 2405 if (OpBits == DestBits) { 2406 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2407 // bits, it is already ready. 2408 if (NumSignBits > DestBits-MidBits) 2409 return Op; 2410 } else if (OpBits < DestBits) { 2411 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2412 // bits, just sext from i32. 2413 if (NumSignBits > OpBits-MidBits) 2414 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2415 } else { 2416 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2417 // bits, just truncate to i32. 2418 if (NumSignBits > OpBits-MidBits) 2419 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2420 } 2421 2422 // fold (sext (truncate x)) -> (sextinreg x). 2423 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2424 N0.getValueType())) { 2425 if (Op.getValueType() < VT) 2426 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2427 else if (Op.getValueType() > VT) 2428 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2429 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2430 DAG.getValueType(N0.getValueType())); 2431 } 2432 } 2433 2434 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2435 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2436 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2437 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2438 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2439 LN0->getBasePtr(), LN0->getSrcValue(), 2440 LN0->getSrcValueOffset(), 2441 N0.getValueType(), 2442 LN0->isVolatile(), 2443 LN0->getAlignment()); 2444 CombineTo(N, ExtLoad); 2445 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2446 ExtLoad.getValue(1)); 2447 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2448 } 2449 2450 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2451 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2452 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2453 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2454 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2455 MVT::ValueType EVT = LN0->getLoadedVT(); 2456 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2457 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2458 LN0->getBasePtr(), LN0->getSrcValue(), 2459 LN0->getSrcValueOffset(), EVT, 2460 LN0->isVolatile(), 2461 LN0->getAlignment()); 2462 CombineTo(N, ExtLoad); 2463 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2464 ExtLoad.getValue(1)); 2465 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2466 } 2467 } 2468 2469 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2470 if (N0.getOpcode() == ISD::SETCC) { 2471 SDOperand SCC = 2472 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2473 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2474 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2475 if (SCC.Val) return SCC; 2476 } 2477 2478 return SDOperand(); 2479} 2480 2481SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2482 SDOperand N0 = N->getOperand(0); 2483 MVT::ValueType VT = N->getValueType(0); 2484 2485 // fold (zext c1) -> c1 2486 if (isa<ConstantSDNode>(N0)) 2487 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2488 // fold (zext (zext x)) -> (zext x) 2489 // fold (zext (aext x)) -> (zext x) 2490 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2491 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2492 2493 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2494 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2495 if (N0.getOpcode() == ISD::TRUNCATE) { 2496 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2497 if (NarrowLoad.Val) { 2498 if (NarrowLoad.Val != N0.Val) 2499 CombineTo(N0.Val, NarrowLoad); 2500 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2501 } 2502 } 2503 2504 // fold (zext (truncate x)) -> (and x, mask) 2505 if (N0.getOpcode() == ISD::TRUNCATE && 2506 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2507 SDOperand Op = N0.getOperand(0); 2508 if (Op.getValueType() < VT) { 2509 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2510 } else if (Op.getValueType() > VT) { 2511 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2512 } 2513 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2514 } 2515 2516 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2517 if (N0.getOpcode() == ISD::AND && 2518 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2519 N0.getOperand(1).getOpcode() == ISD::Constant) { 2520 SDOperand X = N0.getOperand(0).getOperand(0); 2521 if (X.getValueType() < VT) { 2522 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2523 } else if (X.getValueType() > VT) { 2524 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2525 } 2526 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2527 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2528 } 2529 2530 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2531 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2532 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2533 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2534 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2535 LN0->getBasePtr(), LN0->getSrcValue(), 2536 LN0->getSrcValueOffset(), 2537 N0.getValueType(), 2538 LN0->isVolatile(), 2539 LN0->getAlignment()); 2540 CombineTo(N, ExtLoad); 2541 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2542 ExtLoad.getValue(1)); 2543 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2544 } 2545 2546 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2547 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2548 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2549 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2550 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2551 MVT::ValueType EVT = LN0->getLoadedVT(); 2552 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2553 LN0->getBasePtr(), LN0->getSrcValue(), 2554 LN0->getSrcValueOffset(), EVT, 2555 LN0->isVolatile(), 2556 LN0->getAlignment()); 2557 CombineTo(N, ExtLoad); 2558 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2559 ExtLoad.getValue(1)); 2560 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2561 } 2562 2563 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2564 if (N0.getOpcode() == ISD::SETCC) { 2565 SDOperand SCC = 2566 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2567 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2568 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2569 if (SCC.Val) return SCC; 2570 } 2571 2572 return SDOperand(); 2573} 2574 2575SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2576 SDOperand N0 = N->getOperand(0); 2577 MVT::ValueType VT = N->getValueType(0); 2578 2579 // fold (aext c1) -> c1 2580 if (isa<ConstantSDNode>(N0)) 2581 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2582 // fold (aext (aext x)) -> (aext x) 2583 // fold (aext (zext x)) -> (zext x) 2584 // fold (aext (sext x)) -> (sext x) 2585 if (N0.getOpcode() == ISD::ANY_EXTEND || 2586 N0.getOpcode() == ISD::ZERO_EXTEND || 2587 N0.getOpcode() == ISD::SIGN_EXTEND) 2588 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2589 2590 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2591 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2592 if (N0.getOpcode() == ISD::TRUNCATE) { 2593 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2594 if (NarrowLoad.Val) { 2595 if (NarrowLoad.Val != N0.Val) 2596 CombineTo(N0.Val, NarrowLoad); 2597 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2598 } 2599 } 2600 2601 // fold (aext (truncate x)) 2602 if (N0.getOpcode() == ISD::TRUNCATE) { 2603 SDOperand TruncOp = N0.getOperand(0); 2604 if (TruncOp.getValueType() == VT) 2605 return TruncOp; // x iff x size == zext size. 2606 if (TruncOp.getValueType() > VT) 2607 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2608 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2609 } 2610 2611 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2612 if (N0.getOpcode() == ISD::AND && 2613 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2614 N0.getOperand(1).getOpcode() == ISD::Constant) { 2615 SDOperand X = N0.getOperand(0).getOperand(0); 2616 if (X.getValueType() < VT) { 2617 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2618 } else if (X.getValueType() > VT) { 2619 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2620 } 2621 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2622 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2623 } 2624 2625 // fold (aext (load x)) -> (aext (truncate (extload x))) 2626 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2627 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2628 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2629 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2630 LN0->getBasePtr(), LN0->getSrcValue(), 2631 LN0->getSrcValueOffset(), 2632 N0.getValueType(), 2633 LN0->isVolatile(), 2634 LN0->getAlignment()); 2635 CombineTo(N, ExtLoad); 2636 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2637 ExtLoad.getValue(1)); 2638 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2639 } 2640 2641 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2642 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2643 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2644 if (N0.getOpcode() == ISD::LOAD && 2645 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2646 N0.hasOneUse()) { 2647 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2648 MVT::ValueType EVT = LN0->getLoadedVT(); 2649 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2650 LN0->getChain(), LN0->getBasePtr(), 2651 LN0->getSrcValue(), 2652 LN0->getSrcValueOffset(), EVT, 2653 LN0->isVolatile(), 2654 LN0->getAlignment()); 2655 CombineTo(N, ExtLoad); 2656 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2657 ExtLoad.getValue(1)); 2658 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2659 } 2660 2661 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2662 if (N0.getOpcode() == ISD::SETCC) { 2663 SDOperand SCC = 2664 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2665 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2666 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2667 if (SCC.Val) 2668 return SCC; 2669 } 2670 2671 return SDOperand(); 2672} 2673 2674/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2675/// bits and then truncated to a narrower type and where N is a multiple 2676/// of number of bits of the narrower type, transform it to a narrower load 2677/// from address + N / num of bits of new type. If the result is to be 2678/// extended, also fold the extension to form a extending load. 2679SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2680 unsigned Opc = N->getOpcode(); 2681 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2682 SDOperand N0 = N->getOperand(0); 2683 MVT::ValueType VT = N->getValueType(0); 2684 MVT::ValueType EVT = N->getValueType(0); 2685 2686 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2687 // extended to VT. 2688 if (Opc == ISD::SIGN_EXTEND_INREG) { 2689 ExtType = ISD::SEXTLOAD; 2690 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2691 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2692 return SDOperand(); 2693 } 2694 2695 unsigned EVTBits = MVT::getSizeInBits(EVT); 2696 unsigned ShAmt = 0; 2697 bool CombineSRL = false; 2698 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2699 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2700 ShAmt = N01->getValue(); 2701 // Is the shift amount a multiple of size of VT? 2702 if ((ShAmt & (EVTBits-1)) == 0) { 2703 N0 = N0.getOperand(0); 2704 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2705 return SDOperand(); 2706 CombineSRL = true; 2707 } 2708 } 2709 } 2710 2711 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2712 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2713 // zero extended form: by shrinking the load, we lose track of the fact 2714 // that it is already zero extended. 2715 // FIXME: This should be reevaluated. 2716 VT != MVT::i1) { 2717 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 2718 "Cannot truncate to larger type!"); 2719 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2720 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2721 // For big endian targets, we need to adjust the offset to the pointer to 2722 // load the correct bytes. 2723 if (!TLI.isLittleEndian()) 2724 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; 2725 uint64_t PtrOff = ShAmt / 8; 2726 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2727 DAG.getConstant(PtrOff, PtrType)); 2728 AddToWorkList(NewPtr.Val); 2729 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 2730 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 2731 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2732 LN0->isVolatile(), LN0->getAlignment()) 2733 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 2734 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 2735 LN0->isVolatile(), LN0->getAlignment()); 2736 AddToWorkList(N); 2737 if (CombineSRL) { 2738 std::vector<SDNode*> NowDead; 2739 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead); 2740 CombineTo(N->getOperand(0).Val, Load); 2741 } else 2742 CombineTo(N0.Val, Load, Load.getValue(1)); 2743 if (ShAmt) { 2744 if (Opc == ISD::SIGN_EXTEND_INREG) 2745 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 2746 else 2747 return DAG.getNode(Opc, VT, Load); 2748 } 2749 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2750 } 2751 2752 return SDOperand(); 2753} 2754 2755 2756SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2757 SDOperand N0 = N->getOperand(0); 2758 SDOperand N1 = N->getOperand(1); 2759 MVT::ValueType VT = N->getValueType(0); 2760 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2761 unsigned EVTBits = MVT::getSizeInBits(EVT); 2762 2763 // fold (sext_in_reg c1) -> c1 2764 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2765 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2766 2767 // If the input is already sign extended, just drop the extension. 2768 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2769 return N0; 2770 2771 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2772 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2773 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2774 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2775 } 2776 2777 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 2778 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2779 return DAG.getZeroExtendInReg(N0, EVT); 2780 2781 // fold operands of sext_in_reg based on knowledge that the top bits are not 2782 // demanded. 2783 if (SimplifyDemandedBits(SDOperand(N, 0))) 2784 return SDOperand(N, 0); 2785 2786 // fold (sext_in_reg (load x)) -> (smaller sextload x) 2787 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 2788 SDOperand NarrowLoad = ReduceLoadWidth(N); 2789 if (NarrowLoad.Val) 2790 return NarrowLoad; 2791 2792 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2793 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2794 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2795 if (N0.getOpcode() == ISD::SRL) { 2796 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2797 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2798 // We can turn this into an SRA iff the input to the SRL is already sign 2799 // extended enough. 2800 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 2801 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2802 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2803 } 2804 } 2805 2806 // fold (sext_inreg (extload x)) -> (sextload x) 2807 if (ISD::isEXTLoad(N0.Val) && 2808 ISD::isUNINDEXEDLoad(N0.Val) && 2809 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2810 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2811 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2812 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2813 LN0->getBasePtr(), LN0->getSrcValue(), 2814 LN0->getSrcValueOffset(), EVT, 2815 LN0->isVolatile(), 2816 LN0->getAlignment()); 2817 CombineTo(N, ExtLoad); 2818 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2819 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2820 } 2821 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2822 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2823 N0.hasOneUse() && 2824 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2825 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2826 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2827 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2828 LN0->getBasePtr(), LN0->getSrcValue(), 2829 LN0->getSrcValueOffset(), EVT, 2830 LN0->isVolatile(), 2831 LN0->getAlignment()); 2832 CombineTo(N, ExtLoad); 2833 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2834 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2835 } 2836 return SDOperand(); 2837} 2838 2839SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2840 SDOperand N0 = N->getOperand(0); 2841 MVT::ValueType VT = N->getValueType(0); 2842 2843 // noop truncate 2844 if (N0.getValueType() == N->getValueType(0)) 2845 return N0; 2846 // fold (truncate c1) -> c1 2847 if (isa<ConstantSDNode>(N0)) 2848 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2849 // fold (truncate (truncate x)) -> (truncate x) 2850 if (N0.getOpcode() == ISD::TRUNCATE) 2851 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2852 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2853 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2854 N0.getOpcode() == ISD::ANY_EXTEND) { 2855 if (N0.getOperand(0).getValueType() < VT) 2856 // if the source is smaller than the dest, we still need an extend 2857 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2858 else if (N0.getOperand(0).getValueType() > VT) 2859 // if the source is larger than the dest, than we just need the truncate 2860 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2861 else 2862 // if the source and dest are the same type, we can drop both the extend 2863 // and the truncate 2864 return N0.getOperand(0); 2865 } 2866 2867 // fold (truncate (load x)) -> (smaller load x) 2868 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 2869 return ReduceLoadWidth(N); 2870} 2871 2872SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2873 SDOperand N0 = N->getOperand(0); 2874 MVT::ValueType VT = N->getValueType(0); 2875 2876 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 2877 // Only do this before legalize, since afterward the target may be depending 2878 // on the bitconvert. 2879 // First check to see if this is all constant. 2880 if (!AfterLegalize && 2881 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 2882 MVT::isVector(VT)) { 2883 bool isSimple = true; 2884 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 2885 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2886 N0.getOperand(i).getOpcode() != ISD::Constant && 2887 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2888 isSimple = false; 2889 break; 2890 } 2891 2892 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 2893 assert(!MVT::isVector(DestEltVT) && 2894 "Element type of vector ValueType must not be vector!"); 2895 if (isSimple) { 2896 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 2897 } 2898 } 2899 2900 // If the input is a constant, let getNode() fold it. 2901 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2902 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2903 if (Res.Val != N) return Res; 2904 } 2905 2906 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2907 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2908 2909 // fold (conv (load x)) -> (load (conv*)x) 2910 // If the resultant load doesn't need a higher alignment than the original! 2911 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2912 ISD::isUNINDEXEDLoad(N0.Val) && 2913 TLI.isOperationLegal(ISD::LOAD, VT)) { 2914 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2915 unsigned Align = TLI.getTargetMachine().getTargetData()-> 2916 getABITypeAlignment(MVT::getTypeForValueType(VT)); 2917 unsigned OrigAlign = LN0->getAlignment(); 2918 if (Align <= OrigAlign) { 2919 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 2920 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2921 LN0->isVolatile(), Align); 2922 AddToWorkList(N); 2923 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2924 Load.getValue(1)); 2925 return Load; 2926 } 2927 } 2928 2929 return SDOperand(); 2930} 2931 2932/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 2933/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2934/// destination element value type. 2935SDOperand DAGCombiner:: 2936ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2937 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2938 2939 // If this is already the right type, we're done. 2940 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2941 2942 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2943 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2944 2945 // If this is a conversion of N elements of one type to N elements of another 2946 // type, convert each element. This handles FP<->INT cases. 2947 if (SrcBitSize == DstBitSize) { 2948 SmallVector<SDOperand, 8> Ops; 2949 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 2950 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2951 AddToWorkList(Ops.back().Val); 2952 } 2953 MVT::ValueType VT = 2954 MVT::getVectorType(DstEltVT, 2955 MVT::getVectorNumElements(BV->getValueType(0))); 2956 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2957 } 2958 2959 // Otherwise, we're growing or shrinking the elements. To avoid having to 2960 // handle annoying details of growing/shrinking FP values, we convert them to 2961 // int first. 2962 if (MVT::isFloatingPoint(SrcEltVT)) { 2963 // Convert the input float vector to a int vector where the elements are the 2964 // same sizes. 2965 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2966 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2967 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 2968 SrcEltVT = IntVT; 2969 } 2970 2971 // Now we know the input is an integer vector. If the output is a FP type, 2972 // convert to integer first, then to FP of the right size. 2973 if (MVT::isFloatingPoint(DstEltVT)) { 2974 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2975 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2976 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 2977 2978 // Next, convert to FP elements of the same size. 2979 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 2980 } 2981 2982 // Okay, we know the src/dst types are both integers of differing types. 2983 // Handling growing first. 2984 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2985 if (SrcBitSize < DstBitSize) { 2986 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2987 2988 SmallVector<SDOperand, 8> Ops; 2989 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 2990 i += NumInputsPerOutput) { 2991 bool isLE = TLI.isLittleEndian(); 2992 uint64_t NewBits = 0; 2993 bool EltIsUndef = true; 2994 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2995 // Shift the previously computed bits over. 2996 NewBits <<= SrcBitSize; 2997 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2998 if (Op.getOpcode() == ISD::UNDEF) continue; 2999 EltIsUndef = false; 3000 3001 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3002 } 3003 3004 if (EltIsUndef) 3005 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3006 else 3007 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3008 } 3009 3010 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3011 Ops.size()); 3012 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3013 } 3014 3015 // Finally, this must be the case where we are shrinking elements: each input 3016 // turns into multiple outputs. 3017 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3018 SmallVector<SDOperand, 8> Ops; 3019 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3020 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3021 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3022 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3023 continue; 3024 } 3025 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3026 3027 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3028 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3029 OpVal >>= DstBitSize; 3030 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3031 } 3032 3033 // For big endian targets, swap the order of the pieces of each element. 3034 if (!TLI.isLittleEndian()) 3035 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3036 } 3037 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3038 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3039} 3040 3041 3042 3043SDOperand DAGCombiner::visitFADD(SDNode *N) { 3044 SDOperand N0 = N->getOperand(0); 3045 SDOperand N1 = N->getOperand(1); 3046 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3047 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3048 MVT::ValueType VT = N->getValueType(0); 3049 3050 // fold vector ops 3051 if (MVT::isVector(VT)) { 3052 SDOperand FoldedVOp = SimplifyVBinOp(N); 3053 if (FoldedVOp.Val) return FoldedVOp; 3054 } 3055 3056 // fold (fadd c1, c2) -> c1+c2 3057 if (N0CFP && N1CFP) 3058 return DAG.getNode(ISD::FADD, VT, N0, N1); 3059 // canonicalize constant to RHS 3060 if (N0CFP && !N1CFP) 3061 return DAG.getNode(ISD::FADD, VT, N1, N0); 3062 // fold (A + (-B)) -> A-B 3063 if (isNegatibleForFree(N1) == 2) 3064 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3065 // fold ((-A) + B) -> B-A 3066 if (isNegatibleForFree(N0) == 2) 3067 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3068 3069 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3070 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3071 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3072 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3073 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3074 3075 return SDOperand(); 3076} 3077 3078SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3079 SDOperand N0 = N->getOperand(0); 3080 SDOperand N1 = N->getOperand(1); 3081 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3082 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3083 MVT::ValueType VT = N->getValueType(0); 3084 3085 // fold vector ops 3086 if (MVT::isVector(VT)) { 3087 SDOperand FoldedVOp = SimplifyVBinOp(N); 3088 if (FoldedVOp.Val) return FoldedVOp; 3089 } 3090 3091 // fold (fsub c1, c2) -> c1-c2 3092 if (N0CFP && N1CFP) 3093 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3094 // fold (0-B) -> -B 3095 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3096 if (isNegatibleForFree(N1)) 3097 return GetNegatedExpression(N1, DAG); 3098 return DAG.getNode(ISD::FNEG, VT, N1); 3099 } 3100 // fold (A-(-B)) -> A+B 3101 if (isNegatibleForFree(N1)) 3102 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3103 3104 return SDOperand(); 3105} 3106 3107SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3108 SDOperand N0 = N->getOperand(0); 3109 SDOperand N1 = N->getOperand(1); 3110 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3111 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3112 MVT::ValueType VT = N->getValueType(0); 3113 3114 // fold vector ops 3115 if (MVT::isVector(VT)) { 3116 SDOperand FoldedVOp = SimplifyVBinOp(N); 3117 if (FoldedVOp.Val) return FoldedVOp; 3118 } 3119 3120 // fold (fmul c1, c2) -> c1*c2 3121 if (N0CFP && N1CFP) 3122 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3123 // canonicalize constant to RHS 3124 if (N0CFP && !N1CFP) 3125 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3126 // fold (fmul X, 2.0) -> (fadd X, X) 3127 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3128 return DAG.getNode(ISD::FADD, VT, N0, N0); 3129 // fold (fmul X, -1.0) -> (fneg X) 3130 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3131 return DAG.getNode(ISD::FNEG, VT, N0); 3132 3133 // -X * -Y -> X*Y 3134 if (char LHSNeg = isNegatibleForFree(N0)) { 3135 if (char RHSNeg = isNegatibleForFree(N1)) { 3136 // Both can be negated for free, check to see if at least one is cheaper 3137 // negated. 3138 if (LHSNeg == 2 || RHSNeg == 2) 3139 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3140 GetNegatedExpression(N1, DAG)); 3141 } 3142 } 3143 3144 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3145 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3146 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3147 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3148 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3149 3150 return SDOperand(); 3151} 3152 3153SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3154 SDOperand N0 = N->getOperand(0); 3155 SDOperand N1 = N->getOperand(1); 3156 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3157 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3158 MVT::ValueType VT = N->getValueType(0); 3159 3160 // fold vector ops 3161 if (MVT::isVector(VT)) { 3162 SDOperand FoldedVOp = SimplifyVBinOp(N); 3163 if (FoldedVOp.Val) return FoldedVOp; 3164 } 3165 3166 // fold (fdiv c1, c2) -> c1/c2 3167 if (N0CFP && N1CFP) 3168 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3169 3170 3171 // -X / -Y -> X*Y 3172 if (char LHSNeg = isNegatibleForFree(N0)) { 3173 if (char RHSNeg = isNegatibleForFree(N1)) { 3174 // Both can be negated for free, check to see if at least one is cheaper 3175 // negated. 3176 if (LHSNeg == 2 || RHSNeg == 2) 3177 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3178 GetNegatedExpression(N1, DAG)); 3179 } 3180 } 3181 3182 return SDOperand(); 3183} 3184 3185SDOperand DAGCombiner::visitFREM(SDNode *N) { 3186 SDOperand N0 = N->getOperand(0); 3187 SDOperand N1 = N->getOperand(1); 3188 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3189 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3190 MVT::ValueType VT = N->getValueType(0); 3191 3192 // fold (frem c1, c2) -> fmod(c1,c2) 3193 if (N0CFP && N1CFP) 3194 return DAG.getNode(ISD::FREM, VT, N0, N1); 3195 3196 return SDOperand(); 3197} 3198 3199SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3200 SDOperand N0 = N->getOperand(0); 3201 SDOperand N1 = N->getOperand(1); 3202 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3203 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3204 MVT::ValueType VT = N->getValueType(0); 3205 3206 if (N0CFP && N1CFP) // Constant fold 3207 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3208 3209 if (N1CFP) { 3210 const APFloat& V = N1CFP->getValueAPF(); 3211 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3212 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3213 if (!V.isNegative()) 3214 return DAG.getNode(ISD::FABS, VT, N0); 3215 else 3216 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3217 } 3218 3219 // copysign(fabs(x), y) -> copysign(x, y) 3220 // copysign(fneg(x), y) -> copysign(x, y) 3221 // copysign(copysign(x,z), y) -> copysign(x, y) 3222 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3223 N0.getOpcode() == ISD::FCOPYSIGN) 3224 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3225 3226 // copysign(x, abs(y)) -> abs(x) 3227 if (N1.getOpcode() == ISD::FABS) 3228 return DAG.getNode(ISD::FABS, VT, N0); 3229 3230 // copysign(x, copysign(y,z)) -> copysign(x, z) 3231 if (N1.getOpcode() == ISD::FCOPYSIGN) 3232 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3233 3234 // copysign(x, fp_extend(y)) -> copysign(x, y) 3235 // copysign(x, fp_round(y)) -> copysign(x, y) 3236 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3237 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3238 3239 return SDOperand(); 3240} 3241 3242 3243 3244SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3245 SDOperand N0 = N->getOperand(0); 3246 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3247 MVT::ValueType VT = N->getValueType(0); 3248 3249 // fold (sint_to_fp c1) -> c1fp 3250 if (N0C) 3251 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3252 return SDOperand(); 3253} 3254 3255SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3256 SDOperand N0 = N->getOperand(0); 3257 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3258 MVT::ValueType VT = N->getValueType(0); 3259 3260 // fold (uint_to_fp c1) -> c1fp 3261 if (N0C) 3262 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3263 return SDOperand(); 3264} 3265 3266SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3267 SDOperand N0 = N->getOperand(0); 3268 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3269 MVT::ValueType VT = N->getValueType(0); 3270 3271 // fold (fp_to_sint c1fp) -> c1 3272 if (N0CFP) 3273 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3274 return SDOperand(); 3275} 3276 3277SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3278 SDOperand N0 = N->getOperand(0); 3279 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3280 MVT::ValueType VT = N->getValueType(0); 3281 3282 // fold (fp_to_uint c1fp) -> c1 3283 if (N0CFP) 3284 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3285 return SDOperand(); 3286} 3287 3288SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3289 SDOperand N0 = N->getOperand(0); 3290 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3291 MVT::ValueType VT = N->getValueType(0); 3292 3293 // fold (fp_round c1fp) -> c1fp 3294 if (N0CFP) 3295 return DAG.getNode(ISD::FP_ROUND, VT, N0); 3296 3297 // fold (fp_round (fp_extend x)) -> x 3298 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3299 return N0.getOperand(0); 3300 3301 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3302 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3303 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 3304 AddToWorkList(Tmp.Val); 3305 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3306 } 3307 3308 return SDOperand(); 3309} 3310 3311SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3312 SDOperand N0 = N->getOperand(0); 3313 MVT::ValueType VT = N->getValueType(0); 3314 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3315 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3316 3317 // fold (fp_round_inreg c1fp) -> c1fp 3318 if (N0CFP) { 3319 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3320 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3321 } 3322 return SDOperand(); 3323} 3324 3325SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3326 SDOperand N0 = N->getOperand(0); 3327 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3328 MVT::ValueType VT = N->getValueType(0); 3329 3330 // fold (fp_extend c1fp) -> c1fp 3331 if (N0CFP) 3332 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3333 3334 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 3335 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3336 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3337 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3338 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3339 LN0->getBasePtr(), LN0->getSrcValue(), 3340 LN0->getSrcValueOffset(), 3341 N0.getValueType(), 3342 LN0->isVolatile(), 3343 LN0->getAlignment()); 3344 CombineTo(N, ExtLoad); 3345 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 3346 ExtLoad.getValue(1)); 3347 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3348 } 3349 3350 3351 return SDOperand(); 3352} 3353 3354SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3355 SDOperand N0 = N->getOperand(0); 3356 3357 if (isNegatibleForFree(N0)) 3358 return GetNegatedExpression(N0, DAG); 3359 3360 return SDOperand(); 3361} 3362 3363SDOperand DAGCombiner::visitFABS(SDNode *N) { 3364 SDOperand N0 = N->getOperand(0); 3365 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3366 MVT::ValueType VT = N->getValueType(0); 3367 3368 // fold (fabs c1) -> fabs(c1) 3369 if (N0CFP) 3370 return DAG.getNode(ISD::FABS, VT, N0); 3371 // fold (fabs (fabs x)) -> (fabs x) 3372 if (N0.getOpcode() == ISD::FABS) 3373 return N->getOperand(0); 3374 // fold (fabs (fneg x)) -> (fabs x) 3375 // fold (fabs (fcopysign x, y)) -> (fabs x) 3376 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3377 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3378 3379 return SDOperand(); 3380} 3381 3382SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3383 SDOperand Chain = N->getOperand(0); 3384 SDOperand N1 = N->getOperand(1); 3385 SDOperand N2 = N->getOperand(2); 3386 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3387 3388 // never taken branch, fold to chain 3389 if (N1C && N1C->isNullValue()) 3390 return Chain; 3391 // unconditional branch 3392 if (N1C && N1C->getValue() == 1) 3393 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3394 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3395 // on the target. 3396 if (N1.getOpcode() == ISD::SETCC && 3397 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3398 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3399 N1.getOperand(0), N1.getOperand(1), N2); 3400 } 3401 return SDOperand(); 3402} 3403 3404// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3405// 3406SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3407 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3408 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3409 3410 // Use SimplifySetCC to simplify SETCC's. 3411 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3412 if (Simp.Val) AddToWorkList(Simp.Val); 3413 3414 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3415 3416 // fold br_cc true, dest -> br dest (unconditional branch) 3417 if (SCCC && SCCC->getValue()) 3418 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3419 N->getOperand(4)); 3420 // fold br_cc false, dest -> unconditional fall through 3421 if (SCCC && SCCC->isNullValue()) 3422 return N->getOperand(0); 3423 3424 // fold to a simpler setcc 3425 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3426 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3427 Simp.getOperand(2), Simp.getOperand(0), 3428 Simp.getOperand(1), N->getOperand(4)); 3429 return SDOperand(); 3430} 3431 3432 3433/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3434/// pre-indexed load / store when the base pointer is a add or subtract 3435/// and it has other uses besides the load / store. After the 3436/// transformation, the new indexed load / store has effectively folded 3437/// the add / subtract in and all of its other uses are redirected to the 3438/// new load / store. 3439bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3440 if (!AfterLegalize) 3441 return false; 3442 3443 bool isLoad = true; 3444 SDOperand Ptr; 3445 MVT::ValueType VT; 3446 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3447 if (LD->getAddressingMode() != ISD::UNINDEXED) 3448 return false; 3449 VT = LD->getLoadedVT(); 3450 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3451 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3452 return false; 3453 Ptr = LD->getBasePtr(); 3454 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3455 if (ST->getAddressingMode() != ISD::UNINDEXED) 3456 return false; 3457 VT = ST->getStoredVT(); 3458 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3459 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3460 return false; 3461 Ptr = ST->getBasePtr(); 3462 isLoad = false; 3463 } else 3464 return false; 3465 3466 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3467 // out. There is no reason to make this a preinc/predec. 3468 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3469 Ptr.Val->hasOneUse()) 3470 return false; 3471 3472 // Ask the target to do addressing mode selection. 3473 SDOperand BasePtr; 3474 SDOperand Offset; 3475 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3476 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3477 return false; 3478 // Don't create a indexed load / store with zero offset. 3479 if (isa<ConstantSDNode>(Offset) && 3480 cast<ConstantSDNode>(Offset)->getValue() == 0) 3481 return false; 3482 3483 // Try turning it into a pre-indexed load / store except when: 3484 // 1) The new base ptr is a frame index. 3485 // 2) If N is a store and the new base ptr is either the same as or is a 3486 // predecessor of the value being stored. 3487 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3488 // that would create a cycle. 3489 // 4) All uses are load / store ops that use it as old base ptr. 3490 3491 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3492 // (plus the implicit offset) to a register to preinc anyway. 3493 if (isa<FrameIndexSDNode>(BasePtr)) 3494 return false; 3495 3496 // Check #2. 3497 if (!isLoad) { 3498 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3499 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3500 return false; 3501 } 3502 3503 // Now check for #3 and #4. 3504 bool RealUse = false; 3505 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3506 E = Ptr.Val->use_end(); I != E; ++I) { 3507 SDNode *Use = *I; 3508 if (Use == N) 3509 continue; 3510 if (Use->isPredecessor(N)) 3511 return false; 3512 3513 if (!((Use->getOpcode() == ISD::LOAD && 3514 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3515 (Use->getOpcode() == ISD::STORE) && 3516 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3517 RealUse = true; 3518 } 3519 if (!RealUse) 3520 return false; 3521 3522 SDOperand Result; 3523 if (isLoad) 3524 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3525 else 3526 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3527 ++PreIndexedNodes; 3528 ++NodesCombined; 3529 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 3530 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3531 DOUT << '\n'; 3532 std::vector<SDNode*> NowDead; 3533 if (isLoad) { 3534 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3535 NowDead); 3536 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3537 NowDead); 3538 } else { 3539 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3540 NowDead); 3541 } 3542 3543 // Nodes can end up on the worklist more than once. Make sure we do 3544 // not process a node that has been replaced. 3545 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3546 removeFromWorkList(NowDead[i]); 3547 // Finally, since the node is now dead, remove it from the graph. 3548 DAG.DeleteNode(N); 3549 3550 // Replace the uses of Ptr with uses of the updated base value. 3551 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3552 NowDead); 3553 removeFromWorkList(Ptr.Val); 3554 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3555 removeFromWorkList(NowDead[i]); 3556 DAG.DeleteNode(Ptr.Val); 3557 3558 return true; 3559} 3560 3561/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3562/// add / sub of the base pointer node into a post-indexed load / store. 3563/// The transformation folded the add / subtract into the new indexed 3564/// load / store effectively and all of its uses are redirected to the 3565/// new load / store. 3566bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3567 if (!AfterLegalize) 3568 return false; 3569 3570 bool isLoad = true; 3571 SDOperand Ptr; 3572 MVT::ValueType VT; 3573 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3574 if (LD->getAddressingMode() != ISD::UNINDEXED) 3575 return false; 3576 VT = LD->getLoadedVT(); 3577 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3578 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3579 return false; 3580 Ptr = LD->getBasePtr(); 3581 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3582 if (ST->getAddressingMode() != ISD::UNINDEXED) 3583 return false; 3584 VT = ST->getStoredVT(); 3585 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3586 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3587 return false; 3588 Ptr = ST->getBasePtr(); 3589 isLoad = false; 3590 } else 3591 return false; 3592 3593 if (Ptr.Val->hasOneUse()) 3594 return false; 3595 3596 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3597 E = Ptr.Val->use_end(); I != E; ++I) { 3598 SDNode *Op = *I; 3599 if (Op == N || 3600 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3601 continue; 3602 3603 SDOperand BasePtr; 3604 SDOperand Offset; 3605 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3606 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3607 if (Ptr == Offset) 3608 std::swap(BasePtr, Offset); 3609 if (Ptr != BasePtr) 3610 continue; 3611 // Don't create a indexed load / store with zero offset. 3612 if (isa<ConstantSDNode>(Offset) && 3613 cast<ConstantSDNode>(Offset)->getValue() == 0) 3614 continue; 3615 3616 // Try turning it into a post-indexed load / store except when 3617 // 1) All uses are load / store ops that use it as base ptr. 3618 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3619 // nor a successor of N. Otherwise, if Op is folded that would 3620 // create a cycle. 3621 3622 // Check for #1. 3623 bool TryNext = false; 3624 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3625 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3626 SDNode *Use = *II; 3627 if (Use == Ptr.Val) 3628 continue; 3629 3630 // If all the uses are load / store addresses, then don't do the 3631 // transformation. 3632 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3633 bool RealUse = false; 3634 for (SDNode::use_iterator III = Use->use_begin(), 3635 EEE = Use->use_end(); III != EEE; ++III) { 3636 SDNode *UseUse = *III; 3637 if (!((UseUse->getOpcode() == ISD::LOAD && 3638 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3639 (UseUse->getOpcode() == ISD::STORE) && 3640 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3641 RealUse = true; 3642 } 3643 3644 if (!RealUse) { 3645 TryNext = true; 3646 break; 3647 } 3648 } 3649 } 3650 if (TryNext) 3651 continue; 3652 3653 // Check for #2 3654 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3655 SDOperand Result = isLoad 3656 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3657 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3658 ++PostIndexedNodes; 3659 ++NodesCombined; 3660 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 3661 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3662 DOUT << '\n'; 3663 std::vector<SDNode*> NowDead; 3664 if (isLoad) { 3665 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3666 NowDead); 3667 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3668 NowDead); 3669 } else { 3670 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3671 NowDead); 3672 } 3673 3674 // Nodes can end up on the worklist more than once. Make sure we do 3675 // not process a node that has been replaced. 3676 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3677 removeFromWorkList(NowDead[i]); 3678 // Finally, since the node is now dead, remove it from the graph. 3679 DAG.DeleteNode(N); 3680 3681 // Replace the uses of Use with uses of the updated base value. 3682 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3683 Result.getValue(isLoad ? 1 : 0), 3684 NowDead); 3685 removeFromWorkList(Op); 3686 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3687 removeFromWorkList(NowDead[i]); 3688 DAG.DeleteNode(Op); 3689 3690 return true; 3691 } 3692 } 3693 } 3694 return false; 3695} 3696 3697 3698SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3699 LoadSDNode *LD = cast<LoadSDNode>(N); 3700 SDOperand Chain = LD->getChain(); 3701 SDOperand Ptr = LD->getBasePtr(); 3702 3703 // If load is not volatile and there are no uses of the loaded value (and 3704 // the updated indexed value in case of indexed loads), change uses of the 3705 // chain value into uses of the chain input (i.e. delete the dead load). 3706 if (!LD->isVolatile()) { 3707 if (N->getValueType(1) == MVT::Other) { 3708 // Unindexed loads. 3709 if (N->hasNUsesOfValue(0, 0)) 3710 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3711 } else { 3712 // Indexed loads. 3713 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 3714 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 3715 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3716 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1)); 3717 SDOperand To[] = { Undef0, Undef1, Chain }; 3718 return CombineTo(N, To, 3); 3719 } 3720 } 3721 } 3722 3723 // If this load is directly stored, replace the load value with the stored 3724 // value. 3725 // TODO: Handle store large -> read small portion. 3726 // TODO: Handle TRUNCSTORE/LOADEXT 3727 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3728 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3729 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3730 if (PrevST->getBasePtr() == Ptr && 3731 PrevST->getValue().getValueType() == N->getValueType(0)) 3732 return CombineTo(N, Chain.getOperand(1), Chain); 3733 } 3734 } 3735 3736 if (CombinerAA) { 3737 // Walk up chain skipping non-aliasing memory nodes. 3738 SDOperand BetterChain = FindBetterChain(N, Chain); 3739 3740 // If there is a better chain. 3741 if (Chain != BetterChain) { 3742 SDOperand ReplLoad; 3743 3744 // Replace the chain to void dependency. 3745 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3746 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3747 LD->getSrcValue(), LD->getSrcValueOffset(), 3748 LD->isVolatile(), LD->getAlignment()); 3749 } else { 3750 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3751 LD->getValueType(0), 3752 BetterChain, Ptr, LD->getSrcValue(), 3753 LD->getSrcValueOffset(), 3754 LD->getLoadedVT(), 3755 LD->isVolatile(), 3756 LD->getAlignment()); 3757 } 3758 3759 // Create token factor to keep old chain connected. 3760 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3761 Chain, ReplLoad.getValue(1)); 3762 3763 // Replace uses with load result and token factor. Don't add users 3764 // to work list. 3765 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3766 } 3767 } 3768 3769 // Try transforming N to an indexed load. 3770 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3771 return SDOperand(N, 0); 3772 3773 return SDOperand(); 3774} 3775 3776SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3777 StoreSDNode *ST = cast<StoreSDNode>(N); 3778 SDOperand Chain = ST->getChain(); 3779 SDOperand Value = ST->getValue(); 3780 SDOperand Ptr = ST->getBasePtr(); 3781 3782 // If this is a store of a bit convert, store the input value if the 3783 // resultant store does not need a higher alignment than the original. 3784 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 3785 ST->getAddressingMode() == ISD::UNINDEXED) { 3786 unsigned Align = ST->getAlignment(); 3787 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 3788 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 3789 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 3790 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 3791 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3792 ST->getSrcValueOffset(), ST->isVolatile(), Align); 3793 } 3794 3795 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3796 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3797 if (Value.getOpcode() != ISD::TargetConstantFP) { 3798 SDOperand Tmp; 3799 switch (CFP->getValueType(0)) { 3800 default: assert(0 && "Unknown FP type"); 3801 case MVT::f32: 3802 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3803 Tmp = DAG.getConstant(FloatToBits(CFP->getValueAPF().convertToFloat()), MVT::i32); 3804 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3805 ST->getSrcValueOffset(), ST->isVolatile(), 3806 ST->getAlignment()); 3807 } 3808 break; 3809 case MVT::f64: 3810 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3811 Tmp = DAG.getConstant(DoubleToBits(CFP->getValueAPF().convertToDouble()), MVT::i64); 3812 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3813 ST->getSrcValueOffset(), ST->isVolatile(), 3814 ST->getAlignment()); 3815 } else if (TLI.isTypeLegal(MVT::i32)) { 3816 // Many FP stores are not make apparent until after legalize, e.g. for 3817 // argument passing. Since this is so common, custom legalize the 3818 // 64-bit integer store into two 32-bit stores. 3819 uint64_t Val = DoubleToBits(CFP->getValueAPF().convertToDouble()); 3820 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3821 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3822 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3823 3824 int SVOffset = ST->getSrcValueOffset(); 3825 unsigned Alignment = ST->getAlignment(); 3826 bool isVolatile = ST->isVolatile(); 3827 3828 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3829 ST->getSrcValueOffset(), 3830 isVolatile, ST->getAlignment()); 3831 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3832 DAG.getConstant(4, Ptr.getValueType())); 3833 SVOffset += 4; 3834 if (Alignment > 4) 3835 Alignment = 4; 3836 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 3837 SVOffset, isVolatile, Alignment); 3838 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 3839 } 3840 break; 3841 } 3842 } 3843 } 3844 3845 if (CombinerAA) { 3846 // Walk up chain skipping non-aliasing memory nodes. 3847 SDOperand BetterChain = FindBetterChain(N, Chain); 3848 3849 // If there is a better chain. 3850 if (Chain != BetterChain) { 3851 // Replace the chain to avoid dependency. 3852 SDOperand ReplStore; 3853 if (ST->isTruncatingStore()) { 3854 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 3855 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(), 3856 ST->isVolatile(), ST->getAlignment()); 3857 } else { 3858 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 3859 ST->getSrcValue(), ST->getSrcValueOffset(), 3860 ST->isVolatile(), ST->getAlignment()); 3861 } 3862 3863 // Create token to keep both nodes around. 3864 SDOperand Token = 3865 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 3866 3867 // Don't add users to work list. 3868 return CombineTo(N, Token, false); 3869 } 3870 } 3871 3872 // Try transforming N to an indexed store. 3873 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3874 return SDOperand(N, 0); 3875 3876 return SDOperand(); 3877} 3878 3879SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 3880 SDOperand InVec = N->getOperand(0); 3881 SDOperand InVal = N->getOperand(1); 3882 SDOperand EltNo = N->getOperand(2); 3883 3884 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 3885 // vector with the inserted element. 3886 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3887 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3888 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3889 if (Elt < Ops.size()) 3890 Ops[Elt] = InVal; 3891 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 3892 &Ops[0], Ops.size()); 3893 } 3894 3895 return SDOperand(); 3896} 3897 3898SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 3899 unsigned NumInScalars = N->getNumOperands(); 3900 MVT::ValueType VT = N->getValueType(0); 3901 unsigned NumElts = MVT::getVectorNumElements(VT); 3902 MVT::ValueType EltType = MVT::getVectorElementType(VT); 3903 3904 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 3905 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 3906 // at most two distinct vectors, turn this into a shuffle node. 3907 SDOperand VecIn1, VecIn2; 3908 for (unsigned i = 0; i != NumInScalars; ++i) { 3909 // Ignore undef inputs. 3910 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3911 3912 // If this input is something other than a EXTRACT_VECTOR_ELT with a 3913 // constant index, bail out. 3914 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 3915 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 3916 VecIn1 = VecIn2 = SDOperand(0, 0); 3917 break; 3918 } 3919 3920 // If the input vector type disagrees with the result of the build_vector, 3921 // we can't make a shuffle. 3922 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 3923 if (ExtractedFromVec.getValueType() != VT) { 3924 VecIn1 = VecIn2 = SDOperand(0, 0); 3925 break; 3926 } 3927 3928 // Otherwise, remember this. We allow up to two distinct input vectors. 3929 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 3930 continue; 3931 3932 if (VecIn1.Val == 0) { 3933 VecIn1 = ExtractedFromVec; 3934 } else if (VecIn2.Val == 0) { 3935 VecIn2 = ExtractedFromVec; 3936 } else { 3937 // Too many inputs. 3938 VecIn1 = VecIn2 = SDOperand(0, 0); 3939 break; 3940 } 3941 } 3942 3943 // If everything is good, we can make a shuffle operation. 3944 if (VecIn1.Val) { 3945 SmallVector<SDOperand, 8> BuildVecIndices; 3946 for (unsigned i = 0; i != NumInScalars; ++i) { 3947 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 3948 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 3949 continue; 3950 } 3951 3952 SDOperand Extract = N->getOperand(i); 3953 3954 // If extracting from the first vector, just use the index directly. 3955 if (Extract.getOperand(0) == VecIn1) { 3956 BuildVecIndices.push_back(Extract.getOperand(1)); 3957 continue; 3958 } 3959 3960 // Otherwise, use InIdx + VecSize 3961 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 3962 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 3963 TLI.getPointerTy())); 3964 } 3965 3966 // Add count and size info. 3967 MVT::ValueType BuildVecVT = 3968 MVT::getVectorType(TLI.getPointerTy(), NumElts); 3969 3970 // Return the new VECTOR_SHUFFLE node. 3971 SDOperand Ops[5]; 3972 Ops[0] = VecIn1; 3973 if (VecIn2.Val) { 3974 Ops[1] = VecIn2; 3975 } else { 3976 // Use an undef build_vector as input for the second operand. 3977 std::vector<SDOperand> UnOps(NumInScalars, 3978 DAG.getNode(ISD::UNDEF, 3979 EltType)); 3980 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 3981 &UnOps[0], UnOps.size()); 3982 AddToWorkList(Ops[1].Val); 3983 } 3984 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 3985 &BuildVecIndices[0], BuildVecIndices.size()); 3986 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 3987 } 3988 3989 return SDOperand(); 3990} 3991 3992SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 3993 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 3994 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 3995 // inputs come from at most two distinct vectors, turn this into a shuffle 3996 // node. 3997 3998 // If we only have one input vector, we don't need to do any concatenation. 3999 if (N->getNumOperands() == 1) { 4000 return N->getOperand(0); 4001 } 4002 4003 return SDOperand(); 4004} 4005 4006SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4007 SDOperand ShufMask = N->getOperand(2); 4008 unsigned NumElts = ShufMask.getNumOperands(); 4009 4010 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4011 bool isIdentity = true; 4012 for (unsigned i = 0; i != NumElts; ++i) { 4013 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4014 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4015 isIdentity = false; 4016 break; 4017 } 4018 } 4019 if (isIdentity) return N->getOperand(0); 4020 4021 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4022 isIdentity = true; 4023 for (unsigned i = 0; i != NumElts; ++i) { 4024 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4025 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4026 isIdentity = false; 4027 break; 4028 } 4029 } 4030 if (isIdentity) return N->getOperand(1); 4031 4032 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4033 // needed at all. 4034 bool isUnary = true; 4035 bool isSplat = true; 4036 int VecNum = -1; 4037 unsigned BaseIdx = 0; 4038 for (unsigned i = 0; i != NumElts; ++i) 4039 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4040 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4041 int V = (Idx < NumElts) ? 0 : 1; 4042 if (VecNum == -1) { 4043 VecNum = V; 4044 BaseIdx = Idx; 4045 } else { 4046 if (BaseIdx != Idx) 4047 isSplat = false; 4048 if (VecNum != V) { 4049 isUnary = false; 4050 break; 4051 } 4052 } 4053 } 4054 4055 SDOperand N0 = N->getOperand(0); 4056 SDOperand N1 = N->getOperand(1); 4057 // Normalize unary shuffle so the RHS is undef. 4058 if (isUnary && VecNum == 1) 4059 std::swap(N0, N1); 4060 4061 // If it is a splat, check if the argument vector is a build_vector with 4062 // all scalar elements the same. 4063 if (isSplat) { 4064 SDNode *V = N0.Val; 4065 4066 // If this is a bit convert that changes the element type of the vector but 4067 // not the number of vector elements, look through it. Be careful not to 4068 // look though conversions that change things like v4f32 to v2f64. 4069 if (V->getOpcode() == ISD::BIT_CONVERT) { 4070 SDOperand ConvInput = V->getOperand(0); 4071 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4072 V = ConvInput.Val; 4073 } 4074 4075 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4076 unsigned NumElems = V->getNumOperands(); 4077 if (NumElems > BaseIdx) { 4078 SDOperand Base; 4079 bool AllSame = true; 4080 for (unsigned i = 0; i != NumElems; ++i) { 4081 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4082 Base = V->getOperand(i); 4083 break; 4084 } 4085 } 4086 // Splat of <u, u, u, u>, return <u, u, u, u> 4087 if (!Base.Val) 4088 return N0; 4089 for (unsigned i = 0; i != NumElems; ++i) { 4090 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 4091 V->getOperand(i) != Base) { 4092 AllSame = false; 4093 break; 4094 } 4095 } 4096 // Splat of <x, x, x, x>, return <x, x, x, x> 4097 if (AllSame) 4098 return N0; 4099 } 4100 } 4101 } 4102 4103 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4104 // into an undef. 4105 if (isUnary || N0 == N1) { 4106 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4107 // first operand. 4108 SmallVector<SDOperand, 8> MappedOps; 4109 for (unsigned i = 0; i != NumElts; ++i) { 4110 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4111 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4112 MappedOps.push_back(ShufMask.getOperand(i)); 4113 } else { 4114 unsigned NewIdx = 4115 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4116 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4117 } 4118 } 4119 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4120 &MappedOps[0], MappedOps.size()); 4121 AddToWorkList(ShufMask.Val); 4122 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4123 N0, 4124 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4125 ShufMask); 4126 } 4127 4128 return SDOperand(); 4129} 4130 4131/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4132/// an AND to a vector_shuffle with the destination vector and a zero vector. 4133/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4134/// vector_shuffle V, Zero, <0, 4, 2, 4> 4135SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4136 SDOperand LHS = N->getOperand(0); 4137 SDOperand RHS = N->getOperand(1); 4138 if (N->getOpcode() == ISD::AND) { 4139 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4140 RHS = RHS.getOperand(0); 4141 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4142 std::vector<SDOperand> IdxOps; 4143 unsigned NumOps = RHS.getNumOperands(); 4144 unsigned NumElts = NumOps; 4145 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4146 for (unsigned i = 0; i != NumElts; ++i) { 4147 SDOperand Elt = RHS.getOperand(i); 4148 if (!isa<ConstantSDNode>(Elt)) 4149 return SDOperand(); 4150 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4151 IdxOps.push_back(DAG.getConstant(i, EVT)); 4152 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4153 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4154 else 4155 return SDOperand(); 4156 } 4157 4158 // Let's see if the target supports this vector_shuffle. 4159 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4160 return SDOperand(); 4161 4162 // Return the new VECTOR_SHUFFLE node. 4163 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4164 std::vector<SDOperand> Ops; 4165 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4166 Ops.push_back(LHS); 4167 AddToWorkList(LHS.Val); 4168 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4169 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4170 &ZeroOps[0], ZeroOps.size())); 4171 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4172 &IdxOps[0], IdxOps.size())); 4173 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4174 &Ops[0], Ops.size()); 4175 if (VT != LHS.getValueType()) { 4176 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4177 } 4178 return Result; 4179 } 4180 } 4181 return SDOperand(); 4182} 4183 4184/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4185SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4186 // After legalize, the target may be depending on adds and other 4187 // binary ops to provide legal ways to construct constants or other 4188 // things. Simplifying them may result in a loss of legality. 4189 if (AfterLegalize) return SDOperand(); 4190 4191 MVT::ValueType VT = N->getValueType(0); 4192 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4193 4194 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4195 SDOperand LHS = N->getOperand(0); 4196 SDOperand RHS = N->getOperand(1); 4197 SDOperand Shuffle = XformToShuffleWithZero(N); 4198 if (Shuffle.Val) return Shuffle; 4199 4200 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4201 // this operation. 4202 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4203 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4204 SmallVector<SDOperand, 8> Ops; 4205 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4206 SDOperand LHSOp = LHS.getOperand(i); 4207 SDOperand RHSOp = RHS.getOperand(i); 4208 // If these two elements can't be folded, bail out. 4209 if ((LHSOp.getOpcode() != ISD::UNDEF && 4210 LHSOp.getOpcode() != ISD::Constant && 4211 LHSOp.getOpcode() != ISD::ConstantFP) || 4212 (RHSOp.getOpcode() != ISD::UNDEF && 4213 RHSOp.getOpcode() != ISD::Constant && 4214 RHSOp.getOpcode() != ISD::ConstantFP)) 4215 break; 4216 // Can't fold divide by zero. 4217 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4218 N->getOpcode() == ISD::FDIV) { 4219 if ((RHSOp.getOpcode() == ISD::Constant && 4220 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4221 (RHSOp.getOpcode() == ISD::ConstantFP && 4222 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4223 break; 4224 } 4225 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4226 AddToWorkList(Ops.back().Val); 4227 assert((Ops.back().getOpcode() == ISD::UNDEF || 4228 Ops.back().getOpcode() == ISD::Constant || 4229 Ops.back().getOpcode() == ISD::ConstantFP) && 4230 "Scalar binop didn't fold!"); 4231 } 4232 4233 if (Ops.size() == LHS.getNumOperands()) { 4234 MVT::ValueType VT = LHS.getValueType(); 4235 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4236 } 4237 } 4238 4239 return SDOperand(); 4240} 4241 4242SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4243 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4244 4245 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4246 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4247 // If we got a simplified select_cc node back from SimplifySelectCC, then 4248 // break it down into a new SETCC node, and a new SELECT node, and then return 4249 // the SELECT node, since we were called with a SELECT node. 4250 if (SCC.Val) { 4251 // Check to see if we got a select_cc back (to turn into setcc/select). 4252 // Otherwise, just return whatever node we got back, like fabs. 4253 if (SCC.getOpcode() == ISD::SELECT_CC) { 4254 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4255 SCC.getOperand(0), SCC.getOperand(1), 4256 SCC.getOperand(4)); 4257 AddToWorkList(SETCC.Val); 4258 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4259 SCC.getOperand(3), SETCC); 4260 } 4261 return SCC; 4262 } 4263 return SDOperand(); 4264} 4265 4266/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4267/// are the two values being selected between, see if we can simplify the 4268/// select. Callers of this should assume that TheSelect is deleted if this 4269/// returns true. As such, they should return the appropriate thing (e.g. the 4270/// node) back to the top-level of the DAG combiner loop to avoid it being 4271/// looked at. 4272/// 4273bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4274 SDOperand RHS) { 4275 4276 // If this is a select from two identical things, try to pull the operation 4277 // through the select. 4278 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4279 // If this is a load and the token chain is identical, replace the select 4280 // of two loads with a load through a select of the address to load from. 4281 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4282 // constants have been dropped into the constant pool. 4283 if (LHS.getOpcode() == ISD::LOAD && 4284 // Token chains must be identical. 4285 LHS.getOperand(0) == RHS.getOperand(0)) { 4286 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4287 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4288 4289 // If this is an EXTLOAD, the VT's must match. 4290 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4291 // FIXME: this conflates two src values, discarding one. This is not 4292 // the right thing to do, but nothing uses srcvalues now. When they do, 4293 // turn SrcValue into a list of locations. 4294 SDOperand Addr; 4295 if (TheSelect->getOpcode() == ISD::SELECT) { 4296 // Check that the condition doesn't reach either load. If so, folding 4297 // this will induce a cycle into the DAG. 4298 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4299 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4300 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4301 TheSelect->getOperand(0), LLD->getBasePtr(), 4302 RLD->getBasePtr()); 4303 } 4304 } else { 4305 // Check that the condition doesn't reach either load. If so, folding 4306 // this will induce a cycle into the DAG. 4307 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4308 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4309 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4310 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4311 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4312 TheSelect->getOperand(0), 4313 TheSelect->getOperand(1), 4314 LLD->getBasePtr(), RLD->getBasePtr(), 4315 TheSelect->getOperand(4)); 4316 } 4317 } 4318 4319 if (Addr.Val) { 4320 SDOperand Load; 4321 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4322 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4323 Addr,LLD->getSrcValue(), 4324 LLD->getSrcValueOffset(), 4325 LLD->isVolatile(), 4326 LLD->getAlignment()); 4327 else { 4328 Load = DAG.getExtLoad(LLD->getExtensionType(), 4329 TheSelect->getValueType(0), 4330 LLD->getChain(), Addr, LLD->getSrcValue(), 4331 LLD->getSrcValueOffset(), 4332 LLD->getLoadedVT(), 4333 LLD->isVolatile(), 4334 LLD->getAlignment()); 4335 } 4336 // Users of the select now use the result of the load. 4337 CombineTo(TheSelect, Load); 4338 4339 // Users of the old loads now use the new load's chain. We know the 4340 // old-load value is dead now. 4341 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4342 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4343 return true; 4344 } 4345 } 4346 } 4347 } 4348 4349 return false; 4350} 4351 4352SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4353 SDOperand N2, SDOperand N3, 4354 ISD::CondCode CC, bool NotExtCompare) { 4355 4356 MVT::ValueType VT = N2.getValueType(); 4357 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4358 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4359 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4360 4361 // Determine if the condition we're dealing with is constant 4362 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4363 if (SCC.Val) AddToWorkList(SCC.Val); 4364 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4365 4366 // fold select_cc true, x, y -> x 4367 if (SCCC && SCCC->getValue()) 4368 return N2; 4369 // fold select_cc false, x, y -> y 4370 if (SCCC && SCCC->getValue() == 0) 4371 return N3; 4372 4373 // Check to see if we can simplify the select into an fabs node 4374 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4375 // Allow either -0.0 or 0.0 4376 if (CFP->getValueAPF().isZero()) { 4377 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4378 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4379 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4380 N2 == N3.getOperand(0)) 4381 return DAG.getNode(ISD::FABS, VT, N0); 4382 4383 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4384 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4385 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4386 N2.getOperand(0) == N3) 4387 return DAG.getNode(ISD::FABS, VT, N3); 4388 } 4389 } 4390 4391 // Check to see if we can perform the "gzip trick", transforming 4392 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4393 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4394 MVT::isInteger(N0.getValueType()) && 4395 MVT::isInteger(N2.getValueType()) && 4396 (N1C->isNullValue() || // (a < 0) ? b : 0 4397 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4398 MVT::ValueType XType = N0.getValueType(); 4399 MVT::ValueType AType = N2.getValueType(); 4400 if (XType >= AType) { 4401 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4402 // single-bit constant. 4403 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4404 unsigned ShCtV = Log2_64(N2C->getValue()); 4405 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4406 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4407 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4408 AddToWorkList(Shift.Val); 4409 if (XType > AType) { 4410 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4411 AddToWorkList(Shift.Val); 4412 } 4413 return DAG.getNode(ISD::AND, AType, Shift, N2); 4414 } 4415 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4416 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4417 TLI.getShiftAmountTy())); 4418 AddToWorkList(Shift.Val); 4419 if (XType > AType) { 4420 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4421 AddToWorkList(Shift.Val); 4422 } 4423 return DAG.getNode(ISD::AND, AType, Shift, N2); 4424 } 4425 } 4426 4427 // fold select C, 16, 0 -> shl C, 4 4428 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4429 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4430 4431 // If the caller doesn't want us to simplify this into a zext of a compare, 4432 // don't do it. 4433 if (NotExtCompare && N2C->getValue() == 1) 4434 return SDOperand(); 4435 4436 // Get a SetCC of the condition 4437 // FIXME: Should probably make sure that setcc is legal if we ever have a 4438 // target where it isn't. 4439 SDOperand Temp, SCC; 4440 // cast from setcc result type to select result type 4441 if (AfterLegalize) { 4442 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4443 if (N2.getValueType() < SCC.getValueType()) 4444 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4445 else 4446 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4447 } else { 4448 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4449 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4450 } 4451 AddToWorkList(SCC.Val); 4452 AddToWorkList(Temp.Val); 4453 4454 if (N2C->getValue() == 1) 4455 return Temp; 4456 // shl setcc result by log2 n2c 4457 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4458 DAG.getConstant(Log2_64(N2C->getValue()), 4459 TLI.getShiftAmountTy())); 4460 } 4461 4462 // Check to see if this is the equivalent of setcc 4463 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4464 // otherwise, go ahead with the folds. 4465 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4466 MVT::ValueType XType = N0.getValueType(); 4467 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4468 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4469 if (Res.getValueType() != VT) 4470 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4471 return Res; 4472 } 4473 4474 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4475 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4476 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4477 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4478 return DAG.getNode(ISD::SRL, XType, Ctlz, 4479 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4480 TLI.getShiftAmountTy())); 4481 } 4482 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4483 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4484 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4485 N0); 4486 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4487 DAG.getConstant(~0ULL, XType)); 4488 return DAG.getNode(ISD::SRL, XType, 4489 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4490 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4491 TLI.getShiftAmountTy())); 4492 } 4493 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4494 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4495 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4496 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4497 TLI.getShiftAmountTy())); 4498 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4499 } 4500 } 4501 4502 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4503 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4504 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4505 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4506 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4507 MVT::ValueType XType = N0.getValueType(); 4508 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4509 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4510 TLI.getShiftAmountTy())); 4511 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4512 AddToWorkList(Shift.Val); 4513 AddToWorkList(Add.Val); 4514 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4515 } 4516 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4517 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4518 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4519 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4520 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4521 MVT::ValueType XType = N0.getValueType(); 4522 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4523 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4524 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4525 TLI.getShiftAmountTy())); 4526 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4527 AddToWorkList(Shift.Val); 4528 AddToWorkList(Add.Val); 4529 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4530 } 4531 } 4532 } 4533 4534 return SDOperand(); 4535} 4536 4537/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4538SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4539 SDOperand N1, ISD::CondCode Cond, 4540 bool foldBooleans) { 4541 TargetLowering::DAGCombinerInfo 4542 DagCombineInfo(DAG, !AfterLegalize, false, this); 4543 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4544} 4545 4546/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4547/// return a DAG expression to select that will generate the same value by 4548/// multiplying by a magic number. See: 4549/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4550SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4551 std::vector<SDNode*> Built; 4552 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4553 4554 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4555 ii != ee; ++ii) 4556 AddToWorkList(*ii); 4557 return S; 4558} 4559 4560/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4561/// return a DAG expression to select that will generate the same value by 4562/// multiplying by a magic number. See: 4563/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4564SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4565 std::vector<SDNode*> Built; 4566 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4567 4568 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4569 ii != ee; ++ii) 4570 AddToWorkList(*ii); 4571 return S; 4572} 4573 4574/// FindBaseOffset - Return true if base is known not to alias with anything 4575/// but itself. Provides base object and offset as results. 4576static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4577 // Assume it is a primitive operation. 4578 Base = Ptr; Offset = 0; 4579 4580 // If it's an adding a simple constant then integrate the offset. 4581 if (Base.getOpcode() == ISD::ADD) { 4582 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4583 Base = Base.getOperand(0); 4584 Offset += C->getValue(); 4585 } 4586 } 4587 4588 // If it's any of the following then it can't alias with anything but itself. 4589 return isa<FrameIndexSDNode>(Base) || 4590 isa<ConstantPoolSDNode>(Base) || 4591 isa<GlobalAddressSDNode>(Base); 4592} 4593 4594/// isAlias - Return true if there is any possibility that the two addresses 4595/// overlap. 4596bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4597 const Value *SrcValue1, int SrcValueOffset1, 4598 SDOperand Ptr2, int64_t Size2, 4599 const Value *SrcValue2, int SrcValueOffset2) 4600{ 4601 // If they are the same then they must be aliases. 4602 if (Ptr1 == Ptr2) return true; 4603 4604 // Gather base node and offset information. 4605 SDOperand Base1, Base2; 4606 int64_t Offset1, Offset2; 4607 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4608 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4609 4610 // If they have a same base address then... 4611 if (Base1 == Base2) { 4612 // Check to see if the addresses overlap. 4613 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4614 } 4615 4616 // If we know both bases then they can't alias. 4617 if (KnownBase1 && KnownBase2) return false; 4618 4619 if (CombinerGlobalAA) { 4620 // Use alias analysis information. 4621 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 4622 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 4623 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 4624 AliasAnalysis::AliasResult AAResult = 4625 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4626 if (AAResult == AliasAnalysis::NoAlias) 4627 return false; 4628 } 4629 4630 // Otherwise we have to assume they alias. 4631 return true; 4632} 4633 4634/// FindAliasInfo - Extracts the relevant alias information from the memory 4635/// node. Returns true if the operand was a load. 4636bool DAGCombiner::FindAliasInfo(SDNode *N, 4637 SDOperand &Ptr, int64_t &Size, 4638 const Value *&SrcValue, int &SrcValueOffset) { 4639 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4640 Ptr = LD->getBasePtr(); 4641 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4642 SrcValue = LD->getSrcValue(); 4643 SrcValueOffset = LD->getSrcValueOffset(); 4644 return true; 4645 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4646 Ptr = ST->getBasePtr(); 4647 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4648 SrcValue = ST->getSrcValue(); 4649 SrcValueOffset = ST->getSrcValueOffset(); 4650 } else { 4651 assert(0 && "FindAliasInfo expected a memory operand"); 4652 } 4653 4654 return false; 4655} 4656 4657/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4658/// looking for aliasing nodes and adding them to the Aliases vector. 4659void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4660 SmallVector<SDOperand, 8> &Aliases) { 4661 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4662 std::set<SDNode *> Visited; // Visited node set. 4663 4664 // Get alias information for node. 4665 SDOperand Ptr; 4666 int64_t Size; 4667 const Value *SrcValue; 4668 int SrcValueOffset; 4669 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4670 4671 // Starting off. 4672 Chains.push_back(OriginalChain); 4673 4674 // Look at each chain and determine if it is an alias. If so, add it to the 4675 // aliases list. If not, then continue up the chain looking for the next 4676 // candidate. 4677 while (!Chains.empty()) { 4678 SDOperand Chain = Chains.back(); 4679 Chains.pop_back(); 4680 4681 // Don't bother if we've been before. 4682 if (Visited.find(Chain.Val) != Visited.end()) continue; 4683 Visited.insert(Chain.Val); 4684 4685 switch (Chain.getOpcode()) { 4686 case ISD::EntryToken: 4687 // Entry token is ideal chain operand, but handled in FindBetterChain. 4688 break; 4689 4690 case ISD::LOAD: 4691 case ISD::STORE: { 4692 // Get alias information for Chain. 4693 SDOperand OpPtr; 4694 int64_t OpSize; 4695 const Value *OpSrcValue; 4696 int OpSrcValueOffset; 4697 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4698 OpSrcValue, OpSrcValueOffset); 4699 4700 // If chain is alias then stop here. 4701 if (!(IsLoad && IsOpLoad) && 4702 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4703 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4704 Aliases.push_back(Chain); 4705 } else { 4706 // Look further up the chain. 4707 Chains.push_back(Chain.getOperand(0)); 4708 // Clean up old chain. 4709 AddToWorkList(Chain.Val); 4710 } 4711 break; 4712 } 4713 4714 case ISD::TokenFactor: 4715 // We have to check each of the operands of the token factor, so we queue 4716 // then up. Adding the operands to the queue (stack) in reverse order 4717 // maintains the original order and increases the likelihood that getNode 4718 // will find a matching token factor (CSE.) 4719 for (unsigned n = Chain.getNumOperands(); n;) 4720 Chains.push_back(Chain.getOperand(--n)); 4721 // Eliminate the token factor if we can. 4722 AddToWorkList(Chain.Val); 4723 break; 4724 4725 default: 4726 // For all other instructions we will just have to take what we can get. 4727 Aliases.push_back(Chain); 4728 break; 4729 } 4730 } 4731} 4732 4733/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4734/// for a better chain (aliasing node.) 4735SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4736 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4737 4738 // Accumulate all the aliases to this node. 4739 GatherAllAliases(N, OldChain, Aliases); 4740 4741 if (Aliases.size() == 0) { 4742 // If no operands then chain to entry token. 4743 return DAG.getEntryNode(); 4744 } else if (Aliases.size() == 1) { 4745 // If a single operand then chain to it. We don't need to revisit it. 4746 return Aliases[0]; 4747 } 4748 4749 // Construct a custom tailored token factor. 4750 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4751 &Aliases[0], Aliases.size()); 4752 4753 // Make sure the old chain gets cleaned up. 4754 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4755 4756 return NewChain; 4757} 4758 4759// SelectionDAG::Combine - This is the entry point for the file. 4760// 4761void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4762 if (!RunningAfterLegalize && ViewDAGCombine1) 4763 viewGraph(); 4764 if (RunningAfterLegalize && ViewDAGCombine2) 4765 viewGraph(); 4766 /// run - This is the main entry point to this class. 4767 /// 4768 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 4769} 4770