DAGCombiner.cpp revision 65e800308932871350c3512e5a4861bfdc839126
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetFrameInfo.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Support/Compiler.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include <algorithm> 38#include <set> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class VISIBILITY_HIDDEN DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 std::vector<SDNode*> WorkList; 67 68 // AA - Used for DAG load/store alias analysis. 69 AliasAnalysis &AA; 70 71 /// AddUsersToWorkList - When an instruction is simplified, add all users of 72 /// the instruction to the work lists because they might get more simplified 73 /// now. 74 /// 75 void AddUsersToWorkList(SDNode *N) { 76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 77 UI != UE; ++UI) 78 AddToWorkList(*UI); 79 } 80 81 /// visit - call the node-specific routine that knows how to fold each 82 /// particular type of node. 83 SDValue visit(SDNode *N); 84 85 public: 86 /// AddToWorkList - Add to the work list making sure it's instance is at the 87 /// the back (next to be processed.) 88 void AddToWorkList(SDNode *N) { 89 removeFromWorkList(N); 90 WorkList.push_back(N); 91 } 92 93 /// removeFromWorkList - remove all instances of N from the worklist. 94 /// 95 void removeFromWorkList(SDNode *N) { 96 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 97 WorkList.end()); 98 } 99 100 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 101 bool AddTo = true); 102 103 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 104 return CombineTo(N, &Res, 1, AddTo); 105 } 106 107 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 108 bool AddTo = true) { 109 SDValue To[] = { Res0, Res1 }; 110 return CombineTo(N, To, 2, AddTo); 111 } 112 113 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 114 115 private: 116 117 /// SimplifyDemandedBits - Check the specified integer node value to see if 118 /// it can be simplified or if things it uses can be simplified by bit 119 /// propagation. If so, return true. 120 bool SimplifyDemandedBits(SDValue Op) { 121 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 122 return SimplifyDemandedBits(Op, Demanded); 123 } 124 125 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 126 127 bool CombineToPreIndexedLoadStore(SDNode *N); 128 bool CombineToPostIndexedLoadStore(SDNode *N); 129 130 131 /// combine - call the node-specific routine that knows how to fold each 132 /// particular type of node. If that doesn't do anything, try the 133 /// target-specific DAG combines. 134 SDValue combine(SDNode *N); 135 136 // Visitation implementation - Implement dag node combining for different 137 // node types. The semantics are as follows: 138 // Return Value: 139 // SDValue.getNode() == 0 - No change was made 140 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 141 // otherwise - N should be replaced by the returned Operand. 142 // 143 SDValue visitTokenFactor(SDNode *N); 144 SDValue visitMERGE_VALUES(SDNode *N); 145 SDValue visitADD(SDNode *N); 146 SDValue visitSUB(SDNode *N); 147 SDValue visitADDC(SDNode *N); 148 SDValue visitADDE(SDNode *N); 149 SDValue visitMUL(SDNode *N); 150 SDValue visitSDIV(SDNode *N); 151 SDValue visitUDIV(SDNode *N); 152 SDValue visitSREM(SDNode *N); 153 SDValue visitUREM(SDNode *N); 154 SDValue visitMULHU(SDNode *N); 155 SDValue visitMULHS(SDNode *N); 156 SDValue visitSMUL_LOHI(SDNode *N); 157 SDValue visitUMUL_LOHI(SDNode *N); 158 SDValue visitSDIVREM(SDNode *N); 159 SDValue visitUDIVREM(SDNode *N); 160 SDValue visitAND(SDNode *N); 161 SDValue visitOR(SDNode *N); 162 SDValue visitXOR(SDNode *N); 163 SDValue SimplifyVBinOp(SDNode *N); 164 SDValue visitSHL(SDNode *N); 165 SDValue visitSRA(SDNode *N); 166 SDValue visitSRL(SDNode *N); 167 SDValue visitCTLZ(SDNode *N); 168 SDValue visitCTTZ(SDNode *N); 169 SDValue visitCTPOP(SDNode *N); 170 SDValue visitSELECT(SDNode *N); 171 SDValue visitSELECT_CC(SDNode *N); 172 SDValue visitSETCC(SDNode *N); 173 SDValue visitSIGN_EXTEND(SDNode *N); 174 SDValue visitZERO_EXTEND(SDNode *N); 175 SDValue visitANY_EXTEND(SDNode *N); 176 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 177 SDValue visitTRUNCATE(SDNode *N); 178 SDValue visitBIT_CONVERT(SDNode *N); 179 SDValue visitBUILD_PAIR(SDNode *N); 180 SDValue visitFADD(SDNode *N); 181 SDValue visitFSUB(SDNode *N); 182 SDValue visitFMUL(SDNode *N); 183 SDValue visitFDIV(SDNode *N); 184 SDValue visitFREM(SDNode *N); 185 SDValue visitFCOPYSIGN(SDNode *N); 186 SDValue visitSINT_TO_FP(SDNode *N); 187 SDValue visitUINT_TO_FP(SDNode *N); 188 SDValue visitFP_TO_SINT(SDNode *N); 189 SDValue visitFP_TO_UINT(SDNode *N); 190 SDValue visitFP_ROUND(SDNode *N); 191 SDValue visitFP_ROUND_INREG(SDNode *N); 192 SDValue visitFP_EXTEND(SDNode *N); 193 SDValue visitFNEG(SDNode *N); 194 SDValue visitFABS(SDNode *N); 195 SDValue visitBRCOND(SDNode *N); 196 SDValue visitBR_CC(SDNode *N); 197 SDValue visitLOAD(SDNode *N); 198 SDValue visitSTORE(SDNode *N); 199 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 200 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 201 SDValue visitBUILD_VECTOR(SDNode *N); 202 SDValue visitCONCAT_VECTORS(SDNode *N); 203 SDValue visitVECTOR_SHUFFLE(SDNode *N); 204 205 SDValue XformToShuffleWithZero(SDNode *N); 206 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 207 208 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 209 210 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 211 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 212 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 213 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 214 SDValue N3, ISD::CondCode CC, 215 bool NotExtCompare = false); 216 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 217 DebugLoc DL, bool foldBooleans = true); 218 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 219 unsigned HiOp); 220 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 221 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 222 SDValue BuildSDIV(SDNode *N); 223 SDValue BuildUDIV(SDNode *N); 224 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 225 SDValue ReduceLoadWidth(SDNode *N); 226 SDValue ReduceLoadOpStoreWidth(SDNode *N); 227 228 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 229 230 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 231 /// looking for aliasing nodes and adding them to the Aliases vector. 232 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 233 SmallVector<SDValue, 8> &Aliases); 234 235 /// isAlias - Return true if there is any possibility that the two addresses 236 /// overlap. 237 bool isAlias(SDValue Ptr1, int64_t Size1, 238 const Value *SrcValue1, int SrcValueOffset1, 239 SDValue Ptr2, int64_t Size2, 240 const Value *SrcValue2, int SrcValueOffset2) const; 241 242 /// FindAliasInfo - Extracts the relevant alias information from the memory 243 /// node. Returns true if the operand was a load. 244 bool FindAliasInfo(SDNode *N, 245 SDValue &Ptr, int64_t &Size, 246 const Value *&SrcValue, int &SrcValueOffset) const; 247 248 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 249 /// looking for a better chain (aliasing node.) 250 SDValue FindBetterChain(SDNode *N, SDValue Chain); 251 252 /// getShiftAmountTy - Returns a type large enough to hold any valid 253 /// shift amount - before type legalization these can be huge. 254 MVT getShiftAmountTy() { 255 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 256 } 257 258public: 259 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 260 : DAG(D), 261 TLI(D.getTargetLoweringInfo()), 262 Level(Unrestricted), 263 OptLevel(OL), 264 LegalOperations(false), 265 LegalTypes(false), 266 AA(A) {} 267 268 /// Run - runs the dag combiner on all nodes in the work list 269 void Run(CombineLevel AtLevel); 270 }; 271} 272 273 274namespace { 275/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 276/// nodes from the worklist. 277class VISIBILITY_HIDDEN WorkListRemover : 278 public SelectionDAG::DAGUpdateListener { 279 DAGCombiner &DC; 280public: 281 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 282 283 virtual void NodeDeleted(SDNode *N, SDNode *E) { 284 DC.removeFromWorkList(N); 285 } 286 287 virtual void NodeUpdated(SDNode *N) { 288 // Ignore updates. 289 } 290}; 291} 292 293//===----------------------------------------------------------------------===// 294// TargetLowering::DAGCombinerInfo implementation 295//===----------------------------------------------------------------------===// 296 297void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 298 ((DAGCombiner*)DC)->AddToWorkList(N); 299} 300 301SDValue TargetLowering::DAGCombinerInfo:: 302CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 303 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 304} 305 306SDValue TargetLowering::DAGCombinerInfo:: 307CombineTo(SDNode *N, SDValue Res, bool AddTo) { 308 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 309} 310 311 312SDValue TargetLowering::DAGCombinerInfo:: 313CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 314 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 315} 316 317void TargetLowering::DAGCombinerInfo:: 318CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 319 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 320} 321 322//===----------------------------------------------------------------------===// 323// Helper Functions 324//===----------------------------------------------------------------------===// 325 326/// isNegatibleForFree - Return 1 if we can compute the negated form of the 327/// specified expression for the same cost as the expression itself, or 2 if we 328/// can compute the negated form more cheaply than the expression itself. 329static char isNegatibleForFree(SDValue Op, bool LegalOperations, 330 unsigned Depth = 0) { 331 // No compile time optimizations on this type. 332 if (Op.getValueType() == MVT::ppcf128) 333 return 0; 334 335 // fneg is removable even if it has multiple uses. 336 if (Op.getOpcode() == ISD::FNEG) return 2; 337 338 // Don't allow anything with multiple uses. 339 if (!Op.hasOneUse()) return 0; 340 341 // Don't recurse exponentially. 342 if (Depth > 6) return 0; 343 344 switch (Op.getOpcode()) { 345 default: return false; 346 case ISD::ConstantFP: 347 // Don't invert constant FP values after legalize. The negated constant 348 // isn't necessarily legal. 349 return LegalOperations ? 0 : 1; 350 case ISD::FADD: 351 // FIXME: determine better conditions for this xform. 352 if (!UnsafeFPMath) return 0; 353 354 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 355 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 356 return V; 357 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 358 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 359 case ISD::FSUB: 360 // We can't turn -(A-B) into B-A when we honor signed zeros. 361 if (!UnsafeFPMath) return 0; 362 363 // fold (fneg (fsub A, B)) -> (fsub B, A) 364 return 1; 365 366 case ISD::FMUL: 367 case ISD::FDIV: 368 if (HonorSignDependentRoundingFPMath()) return 0; 369 370 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 371 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 372 return V; 373 374 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 375 376 case ISD::FP_EXTEND: 377 case ISD::FP_ROUND: 378 case ISD::FSIN: 379 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 380 } 381} 382 383/// GetNegatedExpression - If isNegatibleForFree returns true, this function 384/// returns the newly negated expression. 385static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 386 bool LegalOperations, unsigned Depth = 0) { 387 // fneg is removable even if it has multiple uses. 388 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 389 390 // Don't allow anything with multiple uses. 391 assert(Op.hasOneUse() && "Unknown reuse!"); 392 393 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 394 switch (Op.getOpcode()) { 395 default: assert(0 && "Unknown code"); 396 case ISD::ConstantFP: { 397 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 398 V.changeSign(); 399 return DAG.getConstantFP(V, Op.getValueType()); 400 } 401 case ISD::FADD: 402 // FIXME: determine better conditions for this xform. 403 assert(UnsafeFPMath); 404 405 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 406 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 407 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 408 GetNegatedExpression(Op.getOperand(0), DAG, 409 LegalOperations, Depth+1), 410 Op.getOperand(1)); 411 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 412 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 413 GetNegatedExpression(Op.getOperand(1), DAG, 414 LegalOperations, Depth+1), 415 Op.getOperand(0)); 416 case ISD::FSUB: 417 // We can't turn -(A-B) into B-A when we honor signed zeros. 418 assert(UnsafeFPMath); 419 420 // fold (fneg (fsub 0, B)) -> B 421 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 422 if (N0CFP->getValueAPF().isZero()) 423 return Op.getOperand(1); 424 425 // fold (fneg (fsub A, B)) -> (fsub B, A) 426 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 427 Op.getOperand(1), Op.getOperand(0)); 428 429 case ISD::FMUL: 430 case ISD::FDIV: 431 assert(!HonorSignDependentRoundingFPMath()); 432 433 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 434 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 435 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 436 GetNegatedExpression(Op.getOperand(0), DAG, 437 LegalOperations, Depth+1), 438 Op.getOperand(1)); 439 440 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 441 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 442 Op.getOperand(0), 443 GetNegatedExpression(Op.getOperand(1), DAG, 444 LegalOperations, Depth+1)); 445 446 case ISD::FP_EXTEND: 447 case ISD::FSIN: 448 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 449 GetNegatedExpression(Op.getOperand(0), DAG, 450 LegalOperations, Depth+1)); 451 case ISD::FP_ROUND: 452 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1), 455 Op.getOperand(1)); 456 } 457} 458 459 460// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 461// that selects between the values 1 and 0, making it equivalent to a setcc. 462// Also, set the incoming LHS, RHS, and CC references to the appropriate 463// nodes based on the type of node we are checking. This simplifies life a 464// bit for the callers. 465static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 466 SDValue &CC) { 467 if (N.getOpcode() == ISD::SETCC) { 468 LHS = N.getOperand(0); 469 RHS = N.getOperand(1); 470 CC = N.getOperand(2); 471 return true; 472 } 473 if (N.getOpcode() == ISD::SELECT_CC && 474 N.getOperand(2).getOpcode() == ISD::Constant && 475 N.getOperand(3).getOpcode() == ISD::Constant && 476 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 477 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 478 LHS = N.getOperand(0); 479 RHS = N.getOperand(1); 480 CC = N.getOperand(4); 481 return true; 482 } 483 return false; 484} 485 486// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 487// one use. If this is true, it allows the users to invert the operation for 488// free when it is profitable to do so. 489static bool isOneUseSetCC(SDValue N) { 490 SDValue N0, N1, N2; 491 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 492 return true; 493 return false; 494} 495 496SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 497 SDValue N0, SDValue N1) { 498 MVT VT = N0.getValueType(); 499 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 500 if (isa<ConstantSDNode>(N1)) { 501 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 502 SDValue OpNode = 503 DAG.FoldConstantArithmetic(Opc, VT, 504 cast<ConstantSDNode>(N0.getOperand(1)), 505 cast<ConstantSDNode>(N1)); 506 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 507 } else if (N0.hasOneUse()) { 508 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 509 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 510 N0.getOperand(0), N1); 511 AddToWorkList(OpNode.getNode()); 512 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 513 } 514 } 515 516 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 517 if (isa<ConstantSDNode>(N0)) { 518 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 519 SDValue OpNode = 520 DAG.FoldConstantArithmetic(Opc, VT, 521 cast<ConstantSDNode>(N1.getOperand(1)), 522 cast<ConstantSDNode>(N0)); 523 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 524 } else if (N1.hasOneUse()) { 525 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 526 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 527 N1.getOperand(0), N0); 528 AddToWorkList(OpNode.getNode()); 529 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 530 } 531 } 532 533 return SDValue(); 534} 535 536SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 537 bool AddTo) { 538 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 539 ++NodesCombined; 540 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 541 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 542 DOUT << " and " << NumTo-1 << " other values\n"; 543 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 544 assert(N->getValueType(i) == To[i].getValueType() && 545 "Cannot combine value to value of different type!")); 546 WorkListRemover DeadNodes(*this); 547 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 548 549 if (AddTo) { 550 // Push the new nodes and any users onto the worklist 551 for (unsigned i = 0, e = NumTo; i != e; ++i) { 552 if (To[i].getNode()) { 553 AddToWorkList(To[i].getNode()); 554 AddUsersToWorkList(To[i].getNode()); 555 } 556 } 557 } 558 559 // Finally, if the node is now dead, remove it from the graph. The node 560 // may not be dead if the replacement process recursively simplified to 561 // something else needing this node. 562 if (N->use_empty()) { 563 // Nodes can be reintroduced into the worklist. Make sure we do not 564 // process a node that has been replaced. 565 removeFromWorkList(N); 566 567 // Finally, since the node is now dead, remove it from the graph. 568 DAG.DeleteNode(N); 569 } 570 return SDValue(N, 0); 571} 572 573void 574DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 575 TLO) { 576 // Replace all uses. If any nodes become isomorphic to other nodes and 577 // are deleted, make sure to remove them from our worklist. 578 WorkListRemover DeadNodes(*this); 579 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 580 581 // Push the new node and any (possibly new) users onto the worklist. 582 AddToWorkList(TLO.New.getNode()); 583 AddUsersToWorkList(TLO.New.getNode()); 584 585 // Finally, if the node is now dead, remove it from the graph. The node 586 // may not be dead if the replacement process recursively simplified to 587 // something else needing this node. 588 if (TLO.Old.getNode()->use_empty()) { 589 removeFromWorkList(TLO.Old.getNode()); 590 591 // If the operands of this node are only used by the node, they will now 592 // be dead. Make sure to visit them first to delete dead nodes early. 593 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 594 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 595 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 596 597 DAG.DeleteNode(TLO.Old.getNode()); 598 } 599} 600 601/// SimplifyDemandedBits - Check the specified integer node value to see if 602/// it can be simplified or if things it uses can be simplified by bit 603/// propagation. If so, return true. 604bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 605 TargetLowering::TargetLoweringOpt TLO(DAG); 606 APInt KnownZero, KnownOne; 607 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 608 return false; 609 610 // Revisit the node. 611 AddToWorkList(Op.getNode()); 612 613 // Replace the old value with the new one. 614 ++NodesCombined; 615 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 616 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 617 DOUT << '\n'; 618 619 CommitTargetLoweringOpt(TLO); 620 return true; 621} 622 623//===----------------------------------------------------------------------===// 624// Main DAG Combiner implementation 625//===----------------------------------------------------------------------===// 626 627void DAGCombiner::Run(CombineLevel AtLevel) { 628 // set the instance variables, so that the various visit routines may use it. 629 Level = AtLevel; 630 LegalOperations = Level >= NoIllegalOperations; 631 LegalTypes = Level >= NoIllegalTypes; 632 633 // Add all the dag nodes to the worklist. 634 WorkList.reserve(DAG.allnodes_size()); 635 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 636 E = DAG.allnodes_end(); I != E; ++I) 637 WorkList.push_back(I); 638 639 // Create a dummy node (which is not added to allnodes), that adds a reference 640 // to the root node, preventing it from being deleted, and tracking any 641 // changes of the root. 642 HandleSDNode Dummy(DAG.getRoot()); 643 644 // The root of the dag may dangle to deleted nodes until the dag combiner is 645 // done. Set it to null to avoid confusion. 646 DAG.setRoot(SDValue()); 647 648 // while the worklist isn't empty, inspect the node on the end of it and 649 // try and combine it. 650 while (!WorkList.empty()) { 651 SDNode *N = WorkList.back(); 652 WorkList.pop_back(); 653 654 // If N has no uses, it is dead. Make sure to revisit all N's operands once 655 // N is deleted from the DAG, since they too may now be dead or may have a 656 // reduced number of uses, allowing other xforms. 657 if (N->use_empty() && N != &Dummy) { 658 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 659 AddToWorkList(N->getOperand(i).getNode()); 660 661 DAG.DeleteNode(N); 662 continue; 663 } 664 665 SDValue RV = combine(N); 666 667 if (RV.getNode() == 0) 668 continue; 669 670 ++NodesCombined; 671 672 // If we get back the same node we passed in, rather than a new node or 673 // zero, we know that the node must have defined multiple values and 674 // CombineTo was used. Since CombineTo takes care of the worklist 675 // mechanics for us, we have no work to do in this case. 676 if (RV.getNode() == N) 677 continue; 678 679 assert(N->getOpcode() != ISD::DELETED_NODE && 680 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 681 "Node was deleted but visit returned new node!"); 682 683 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 684 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 685 DOUT << '\n'; 686 WorkListRemover DeadNodes(*this); 687 if (N->getNumValues() == RV.getNode()->getNumValues()) 688 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 689 else { 690 assert(N->getValueType(0) == RV.getValueType() && 691 N->getNumValues() == 1 && "Type mismatch"); 692 SDValue OpV = RV; 693 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 694 } 695 696 // Push the new node and any users onto the worklist 697 AddToWorkList(RV.getNode()); 698 AddUsersToWorkList(RV.getNode()); 699 700 // Add any uses of the old node to the worklist in case this node is the 701 // last one that uses them. They may become dead after this node is 702 // deleted. 703 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 704 AddToWorkList(N->getOperand(i).getNode()); 705 706 // Finally, if the node is now dead, remove it from the graph. The node 707 // may not be dead if the replacement process recursively simplified to 708 // something else needing this node. 709 if (N->use_empty()) { 710 // Nodes can be reintroduced into the worklist. Make sure we do not 711 // process a node that has been replaced. 712 removeFromWorkList(N); 713 714 // Finally, since the node is now dead, remove it from the graph. 715 DAG.DeleteNode(N); 716 } 717 } 718 719 // If the root changed (e.g. it was a dead load, update the root). 720 DAG.setRoot(Dummy.getValue()); 721} 722 723SDValue DAGCombiner::visit(SDNode *N) { 724 switch(N->getOpcode()) { 725 default: break; 726 case ISD::TokenFactor: return visitTokenFactor(N); 727 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 728 case ISD::ADD: return visitADD(N); 729 case ISD::SUB: return visitSUB(N); 730 case ISD::ADDC: return visitADDC(N); 731 case ISD::ADDE: return visitADDE(N); 732 case ISD::MUL: return visitMUL(N); 733 case ISD::SDIV: return visitSDIV(N); 734 case ISD::UDIV: return visitUDIV(N); 735 case ISD::SREM: return visitSREM(N); 736 case ISD::UREM: return visitUREM(N); 737 case ISD::MULHU: return visitMULHU(N); 738 case ISD::MULHS: return visitMULHS(N); 739 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 740 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 741 case ISD::SDIVREM: return visitSDIVREM(N); 742 case ISD::UDIVREM: return visitUDIVREM(N); 743 case ISD::AND: return visitAND(N); 744 case ISD::OR: return visitOR(N); 745 case ISD::XOR: return visitXOR(N); 746 case ISD::SHL: return visitSHL(N); 747 case ISD::SRA: return visitSRA(N); 748 case ISD::SRL: return visitSRL(N); 749 case ISD::CTLZ: return visitCTLZ(N); 750 case ISD::CTTZ: return visitCTTZ(N); 751 case ISD::CTPOP: return visitCTPOP(N); 752 case ISD::SELECT: return visitSELECT(N); 753 case ISD::SELECT_CC: return visitSELECT_CC(N); 754 case ISD::SETCC: return visitSETCC(N); 755 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 756 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 757 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 758 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 759 case ISD::TRUNCATE: return visitTRUNCATE(N); 760 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 761 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 762 case ISD::FADD: return visitFADD(N); 763 case ISD::FSUB: return visitFSUB(N); 764 case ISD::FMUL: return visitFMUL(N); 765 case ISD::FDIV: return visitFDIV(N); 766 case ISD::FREM: return visitFREM(N); 767 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 768 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 769 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 770 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 771 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 772 case ISD::FP_ROUND: return visitFP_ROUND(N); 773 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 774 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 775 case ISD::FNEG: return visitFNEG(N); 776 case ISD::FABS: return visitFABS(N); 777 case ISD::BRCOND: return visitBRCOND(N); 778 case ISD::BR_CC: return visitBR_CC(N); 779 case ISD::LOAD: return visitLOAD(N); 780 case ISD::STORE: return visitSTORE(N); 781 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 782 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 783 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 784 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 785 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 786 } 787 return SDValue(); 788} 789 790SDValue DAGCombiner::combine(SDNode *N) { 791 SDValue RV = visit(N); 792 793 // If nothing happened, try a target-specific DAG combine. 794 if (RV.getNode() == 0) { 795 assert(N->getOpcode() != ISD::DELETED_NODE && 796 "Node was deleted but visit returned NULL!"); 797 798 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 799 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 800 801 // Expose the DAG combiner to the target combiner impls. 802 TargetLowering::DAGCombinerInfo 803 DagCombineInfo(DAG, Level == Unrestricted, false, this); 804 805 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 806 } 807 } 808 809 // If N is a commutative binary node, try commuting it to enable more 810 // sdisel CSE. 811 if (RV.getNode() == 0 && 812 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 813 N->getNumValues() == 1) { 814 SDValue N0 = N->getOperand(0); 815 SDValue N1 = N->getOperand(1); 816 817 // Constant operands are canonicalized to RHS. 818 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 819 SDValue Ops[] = { N1, N0 }; 820 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 821 Ops, 2); 822 if (CSENode) 823 return SDValue(CSENode, 0); 824 } 825 } 826 827 return RV; 828} 829 830/// getInputChainForNode - Given a node, return its input chain if it has one, 831/// otherwise return a null sd operand. 832static SDValue getInputChainForNode(SDNode *N) { 833 if (unsigned NumOps = N->getNumOperands()) { 834 if (N->getOperand(0).getValueType() == MVT::Other) 835 return N->getOperand(0); 836 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 837 return N->getOperand(NumOps-1); 838 for (unsigned i = 1; i < NumOps-1; ++i) 839 if (N->getOperand(i).getValueType() == MVT::Other) 840 return N->getOperand(i); 841 } 842 return SDValue(); 843} 844 845SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 846 // If N has two operands, where one has an input chain equal to the other, 847 // the 'other' chain is redundant. 848 if (N->getNumOperands() == 2) { 849 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 850 return N->getOperand(0); 851 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 852 return N->getOperand(1); 853 } 854 855 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 856 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 857 SmallPtrSet<SDNode*, 16> SeenOps; 858 bool Changed = false; // If we should replace this token factor. 859 860 // Start out with this token factor. 861 TFs.push_back(N); 862 863 // Iterate through token factors. The TFs grows when new token factors are 864 // encountered. 865 for (unsigned i = 0; i < TFs.size(); ++i) { 866 SDNode *TF = TFs[i]; 867 868 // Check each of the operands. 869 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 870 SDValue Op = TF->getOperand(i); 871 872 switch (Op.getOpcode()) { 873 case ISD::EntryToken: 874 // Entry tokens don't need to be added to the list. They are 875 // rededundant. 876 Changed = true; 877 break; 878 879 case ISD::TokenFactor: 880 if ((CombinerAA || Op.hasOneUse()) && 881 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 882 // Queue up for processing. 883 TFs.push_back(Op.getNode()); 884 // Clean up in case the token factor is removed. 885 AddToWorkList(Op.getNode()); 886 Changed = true; 887 break; 888 } 889 // Fall thru 890 891 default: 892 // Only add if it isn't already in the list. 893 if (SeenOps.insert(Op.getNode())) 894 Ops.push_back(Op); 895 else 896 Changed = true; 897 break; 898 } 899 } 900 } 901 902 SDValue Result; 903 904 // If we've change things around then replace token factor. 905 if (Changed) { 906 if (Ops.empty()) { 907 // The entry token is the only possible outcome. 908 Result = DAG.getEntryNode(); 909 } else { 910 // New and improved token factor. 911 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 912 MVT::Other, &Ops[0], Ops.size()); 913 } 914 915 // Don't add users to work list. 916 return CombineTo(N, Result, false); 917 } 918 919 return Result; 920} 921 922/// MERGE_VALUES can always be eliminated. 923SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 924 WorkListRemover DeadNodes(*this); 925 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 926 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 927 &DeadNodes); 928 removeFromWorkList(N); 929 DAG.DeleteNode(N); 930 return SDValue(N, 0); // Return N so it doesn't get rechecked! 931} 932 933static 934SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 935 SelectionDAG &DAG) { 936 MVT VT = N0.getValueType(); 937 SDValue N00 = N0.getOperand(0); 938 SDValue N01 = N0.getOperand(1); 939 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 940 941 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 942 isa<ConstantSDNode>(N00.getOperand(1))) { 943 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 944 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 945 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 946 N00.getOperand(0), N01), 947 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 948 N00.getOperand(1), N01)); 949 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 950 } 951 952 return SDValue(); 953} 954 955SDValue DAGCombiner::visitADD(SDNode *N) { 956 SDValue N0 = N->getOperand(0); 957 SDValue N1 = N->getOperand(1); 958 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 959 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 960 MVT VT = N0.getValueType(); 961 962 // fold vector ops 963 if (VT.isVector()) { 964 SDValue FoldedVOp = SimplifyVBinOp(N); 965 if (FoldedVOp.getNode()) return FoldedVOp; 966 } 967 968 // fold (add x, undef) -> undef 969 if (N0.getOpcode() == ISD::UNDEF) 970 return N0; 971 if (N1.getOpcode() == ISD::UNDEF) 972 return N1; 973 // fold (add c1, c2) -> c1+c2 974 if (N0C && N1C) 975 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 976 // canonicalize constant to RHS 977 if (N0C && !N1C) 978 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 979 // fold (add x, 0) -> x 980 if (N1C && N1C->isNullValue()) 981 return N0; 982 // fold (add Sym, c) -> Sym+c 983 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 984 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 985 GA->getOpcode() == ISD::GlobalAddress) 986 return DAG.getGlobalAddress(GA->getGlobal(), VT, 987 GA->getOffset() + 988 (uint64_t)N1C->getSExtValue()); 989 // fold ((c1-A)+c2) -> (c1+c2)-A 990 if (N1C && N0.getOpcode() == ISD::SUB) 991 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 992 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 993 DAG.getConstant(N1C->getAPIntValue()+ 994 N0C->getAPIntValue(), VT), 995 N0.getOperand(1)); 996 // reassociate add 997 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 998 if (RADD.getNode() != 0) 999 return RADD; 1000 // fold ((0-A) + B) -> B-A 1001 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1002 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1003 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1004 // fold (A + (0-B)) -> A-B 1005 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1006 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1007 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1008 // fold (A+(B-A)) -> B 1009 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1010 return N1.getOperand(0); 1011 // fold ((B-A)+A) -> B 1012 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1013 return N0.getOperand(0); 1014 // fold (A+(B-(A+C))) to (B-C) 1015 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1016 N0 == N1.getOperand(1).getOperand(0)) 1017 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1018 N1.getOperand(1).getOperand(1)); 1019 // fold (A+(B-(C+A))) to (B-C) 1020 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1021 N0 == N1.getOperand(1).getOperand(1)) 1022 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1023 N1.getOperand(1).getOperand(0)); 1024 // fold (A+((B-A)+or-C)) to (B+or-C) 1025 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1026 N1.getOperand(0).getOpcode() == ISD::SUB && 1027 N0 == N1.getOperand(0).getOperand(1)) 1028 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1029 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1030 1031 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1032 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1033 SDValue N00 = N0.getOperand(0); 1034 SDValue N01 = N0.getOperand(1); 1035 SDValue N10 = N1.getOperand(0); 1036 SDValue N11 = N1.getOperand(1); 1037 1038 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1039 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1040 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1041 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1042 } 1043 1044 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1045 return SDValue(N, 0); 1046 1047 // fold (a+b) -> (a|b) iff a and b share no bits. 1048 if (VT.isInteger() && !VT.isVector()) { 1049 APInt LHSZero, LHSOne; 1050 APInt RHSZero, RHSOne; 1051 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1052 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1053 1054 if (LHSZero.getBoolValue()) { 1055 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1056 1057 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1058 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1059 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1060 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1061 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1062 } 1063 } 1064 1065 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1066 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1067 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1068 if (Result.getNode()) return Result; 1069 } 1070 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1071 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1072 if (Result.getNode()) return Result; 1073 } 1074 1075 return SDValue(); 1076} 1077 1078SDValue DAGCombiner::visitADDC(SDNode *N) { 1079 SDValue N0 = N->getOperand(0); 1080 SDValue N1 = N->getOperand(1); 1081 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1082 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1083 MVT VT = N0.getValueType(); 1084 1085 // If the flag result is dead, turn this into an ADD. 1086 if (N->hasNUsesOfValue(0, 1)) 1087 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1088 DAG.getNode(ISD::CARRY_FALSE, 1089 N->getDebugLoc(), MVT::Flag)); 1090 1091 // canonicalize constant to RHS. 1092 if (N0C && !N1C) 1093 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1094 1095 // fold (addc x, 0) -> x + no carry out 1096 if (N1C && N1C->isNullValue()) 1097 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1098 N->getDebugLoc(), MVT::Flag)); 1099 1100 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1101 APInt LHSZero, LHSOne; 1102 APInt RHSZero, RHSOne; 1103 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1104 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1105 1106 if (LHSZero.getBoolValue()) { 1107 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1108 1109 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1110 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1111 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1112 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1113 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1114 DAG.getNode(ISD::CARRY_FALSE, 1115 N->getDebugLoc(), MVT::Flag)); 1116 } 1117 1118 return SDValue(); 1119} 1120 1121SDValue DAGCombiner::visitADDE(SDNode *N) { 1122 SDValue N0 = N->getOperand(0); 1123 SDValue N1 = N->getOperand(1); 1124 SDValue CarryIn = N->getOperand(2); 1125 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1126 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1127 1128 // canonicalize constant to RHS 1129 if (N0C && !N1C) 1130 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1131 N1, N0, CarryIn); 1132 1133 // fold (adde x, y, false) -> (addc x, y) 1134 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1135 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1136 1137 return SDValue(); 1138} 1139 1140SDValue DAGCombiner::visitSUB(SDNode *N) { 1141 SDValue N0 = N->getOperand(0); 1142 SDValue N1 = N->getOperand(1); 1143 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1144 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1145 MVT VT = N0.getValueType(); 1146 1147 // fold vector ops 1148 if (VT.isVector()) { 1149 SDValue FoldedVOp = SimplifyVBinOp(N); 1150 if (FoldedVOp.getNode()) return FoldedVOp; 1151 } 1152 1153 // fold (sub x, x) -> 0 1154 if (N0 == N1) 1155 return DAG.getConstant(0, N->getValueType(0)); 1156 // fold (sub c1, c2) -> c1-c2 1157 if (N0C && N1C) 1158 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1159 // fold (sub x, c) -> (add x, -c) 1160 if (N1C) 1161 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1162 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1163 // fold (A+B)-A -> B 1164 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1165 return N0.getOperand(1); 1166 // fold (A+B)-B -> A 1167 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1168 return N0.getOperand(0); 1169 // fold ((A+(B+or-C))-B) -> A+or-C 1170 if (N0.getOpcode() == ISD::ADD && 1171 (N0.getOperand(1).getOpcode() == ISD::SUB || 1172 N0.getOperand(1).getOpcode() == ISD::ADD) && 1173 N0.getOperand(1).getOperand(0) == N1) 1174 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1175 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1176 // fold ((A+(C+B))-B) -> A+C 1177 if (N0.getOpcode() == ISD::ADD && 1178 N0.getOperand(1).getOpcode() == ISD::ADD && 1179 N0.getOperand(1).getOperand(1) == N1) 1180 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1181 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1182 // fold ((A-(B-C))-C) -> A-B 1183 if (N0.getOpcode() == ISD::SUB && 1184 N0.getOperand(1).getOpcode() == ISD::SUB && 1185 N0.getOperand(1).getOperand(1) == N1) 1186 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1187 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1188 1189 // If either operand of a sub is undef, the result is undef 1190 if (N0.getOpcode() == ISD::UNDEF) 1191 return N0; 1192 if (N1.getOpcode() == ISD::UNDEF) 1193 return N1; 1194 1195 // If the relocation model supports it, consider symbol offsets. 1196 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1197 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1198 // fold (sub Sym, c) -> Sym-c 1199 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1200 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1201 GA->getOffset() - 1202 (uint64_t)N1C->getSExtValue()); 1203 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1204 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1205 if (GA->getGlobal() == GB->getGlobal()) 1206 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1207 VT); 1208 } 1209 1210 return SDValue(); 1211} 1212 1213SDValue DAGCombiner::visitMUL(SDNode *N) { 1214 SDValue N0 = N->getOperand(0); 1215 SDValue N1 = N->getOperand(1); 1216 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1217 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1218 MVT VT = N0.getValueType(); 1219 1220 // fold vector ops 1221 if (VT.isVector()) { 1222 SDValue FoldedVOp = SimplifyVBinOp(N); 1223 if (FoldedVOp.getNode()) return FoldedVOp; 1224 } 1225 1226 // fold (mul x, undef) -> 0 1227 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1228 return DAG.getConstant(0, VT); 1229 // fold (mul c1, c2) -> c1*c2 1230 if (N0C && N1C) 1231 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1232 // canonicalize constant to RHS 1233 if (N0C && !N1C) 1234 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1235 // fold (mul x, 0) -> 0 1236 if (N1C && N1C->isNullValue()) 1237 return N1; 1238 // fold (mul x, -1) -> 0-x 1239 if (N1C && N1C->isAllOnesValue()) 1240 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1241 DAG.getConstant(0, VT), N0); 1242 // fold (mul x, (1 << c)) -> x << c 1243 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1244 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1245 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1246 getShiftAmountTy())); 1247 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1248 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1249 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1250 // FIXME: If the input is something that is easily negated (e.g. a 1251 // single-use add), we should put the negate there. 1252 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1253 DAG.getConstant(0, VT), 1254 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1255 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1256 } 1257 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1258 if (N1C && N0.getOpcode() == ISD::SHL && 1259 isa<ConstantSDNode>(N0.getOperand(1))) { 1260 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1261 N1, N0.getOperand(1)); 1262 AddToWorkList(C3.getNode()); 1263 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1264 N0.getOperand(0), C3); 1265 } 1266 1267 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1268 // use. 1269 { 1270 SDValue Sh(0,0), Y(0,0); 1271 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1272 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1273 N0.getNode()->hasOneUse()) { 1274 Sh = N0; Y = N1; 1275 } else if (N1.getOpcode() == ISD::SHL && 1276 isa<ConstantSDNode>(N1.getOperand(1)) && 1277 N1.getNode()->hasOneUse()) { 1278 Sh = N1; Y = N0; 1279 } 1280 1281 if (Sh.getNode()) { 1282 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1283 Sh.getOperand(0), Y); 1284 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1285 Mul, Sh.getOperand(1)); 1286 } 1287 } 1288 1289 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1290 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1291 isa<ConstantSDNode>(N0.getOperand(1))) 1292 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1293 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1294 N0.getOperand(0), N1), 1295 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1296 N0.getOperand(1), N1)); 1297 1298 // reassociate mul 1299 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1300 if (RMUL.getNode() != 0) 1301 return RMUL; 1302 1303 return SDValue(); 1304} 1305 1306SDValue DAGCombiner::visitSDIV(SDNode *N) { 1307 SDValue N0 = N->getOperand(0); 1308 SDValue N1 = N->getOperand(1); 1309 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1310 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1311 MVT VT = N->getValueType(0); 1312 1313 // fold vector ops 1314 if (VT.isVector()) { 1315 SDValue FoldedVOp = SimplifyVBinOp(N); 1316 if (FoldedVOp.getNode()) return FoldedVOp; 1317 } 1318 1319 // fold (sdiv c1, c2) -> c1/c2 1320 if (N0C && N1C && !N1C->isNullValue()) 1321 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1322 // fold (sdiv X, 1) -> X 1323 if (N1C && N1C->getSExtValue() == 1LL) 1324 return N0; 1325 // fold (sdiv X, -1) -> 0-X 1326 if (N1C && N1C->isAllOnesValue()) 1327 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1328 DAG.getConstant(0, VT), N0); 1329 // If we know the sign bits of both operands are zero, strength reduce to a 1330 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1331 if (!VT.isVector()) { 1332 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1333 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1334 N0, N1); 1335 } 1336 // fold (sdiv X, pow2) -> simple ops after legalize 1337 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1338 (isPowerOf2_64(N1C->getSExtValue()) || 1339 isPowerOf2_64(-N1C->getSExtValue()))) { 1340 // If dividing by powers of two is cheap, then don't perform the following 1341 // fold. 1342 if (TLI.isPow2DivCheap()) 1343 return SDValue(); 1344 1345 int64_t pow2 = N1C->getSExtValue(); 1346 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1347 unsigned lg2 = Log2_64(abs2); 1348 1349 // Splat the sign bit into the register 1350 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1351 DAG.getConstant(VT.getSizeInBits()-1, 1352 getShiftAmountTy())); 1353 AddToWorkList(SGN.getNode()); 1354 1355 // Add (N0 < 0) ? abs2 - 1 : 0; 1356 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1357 DAG.getConstant(VT.getSizeInBits() - lg2, 1358 getShiftAmountTy())); 1359 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1360 AddToWorkList(SRL.getNode()); 1361 AddToWorkList(ADD.getNode()); // Divide by pow2 1362 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1363 DAG.getConstant(lg2, getShiftAmountTy())); 1364 1365 // If we're dividing by a positive value, we're done. Otherwise, we must 1366 // negate the result. 1367 if (pow2 > 0) 1368 return SRA; 1369 1370 AddToWorkList(SRA.getNode()); 1371 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1372 DAG.getConstant(0, VT), SRA); 1373 } 1374 1375 // if integer divide is expensive and we satisfy the requirements, emit an 1376 // alternate sequence. 1377 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1378 !TLI.isIntDivCheap()) { 1379 SDValue Op = BuildSDIV(N); 1380 if (Op.getNode()) return Op; 1381 } 1382 1383 // undef / X -> 0 1384 if (N0.getOpcode() == ISD::UNDEF) 1385 return DAG.getConstant(0, VT); 1386 // X / undef -> undef 1387 if (N1.getOpcode() == ISD::UNDEF) 1388 return N1; 1389 1390 return SDValue(); 1391} 1392 1393SDValue DAGCombiner::visitUDIV(SDNode *N) { 1394 SDValue N0 = N->getOperand(0); 1395 SDValue N1 = N->getOperand(1); 1396 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1397 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1398 MVT VT = N->getValueType(0); 1399 1400 // fold vector ops 1401 if (VT.isVector()) { 1402 SDValue FoldedVOp = SimplifyVBinOp(N); 1403 if (FoldedVOp.getNode()) return FoldedVOp; 1404 } 1405 1406 // fold (udiv c1, c2) -> c1/c2 1407 if (N0C && N1C && !N1C->isNullValue()) 1408 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1409 // fold (udiv x, (1 << c)) -> x >>u c 1410 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1411 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1412 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1413 getShiftAmountTy())); 1414 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1415 if (N1.getOpcode() == ISD::SHL) { 1416 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1417 if (SHC->getAPIntValue().isPowerOf2()) { 1418 MVT ADDVT = N1.getOperand(1).getValueType(); 1419 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1420 N1.getOperand(1), 1421 DAG.getConstant(SHC->getAPIntValue() 1422 .logBase2(), 1423 ADDVT)); 1424 AddToWorkList(Add.getNode()); 1425 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1426 } 1427 } 1428 } 1429 // fold (udiv x, c) -> alternate 1430 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1431 SDValue Op = BuildUDIV(N); 1432 if (Op.getNode()) return Op; 1433 } 1434 1435 // undef / X -> 0 1436 if (N0.getOpcode() == ISD::UNDEF) 1437 return DAG.getConstant(0, VT); 1438 // X / undef -> undef 1439 if (N1.getOpcode() == ISD::UNDEF) 1440 return N1; 1441 1442 return SDValue(); 1443} 1444 1445SDValue DAGCombiner::visitSREM(SDNode *N) { 1446 SDValue N0 = N->getOperand(0); 1447 SDValue N1 = N->getOperand(1); 1448 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1449 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1450 MVT VT = N->getValueType(0); 1451 1452 // fold (srem c1, c2) -> c1%c2 1453 if (N0C && N1C && !N1C->isNullValue()) 1454 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1455 // If we know the sign bits of both operands are zero, strength reduce to a 1456 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1457 if (!VT.isVector()) { 1458 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1459 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1460 } 1461 1462 // If X/C can be simplified by the division-by-constant logic, lower 1463 // X%C to the equivalent of X-X/C*C. 1464 if (N1C && !N1C->isNullValue()) { 1465 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1466 AddToWorkList(Div.getNode()); 1467 SDValue OptimizedDiv = combine(Div.getNode()); 1468 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1469 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1470 OptimizedDiv, N1); 1471 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1472 AddToWorkList(Mul.getNode()); 1473 return Sub; 1474 } 1475 } 1476 1477 // undef % X -> 0 1478 if (N0.getOpcode() == ISD::UNDEF) 1479 return DAG.getConstant(0, VT); 1480 // X % undef -> undef 1481 if (N1.getOpcode() == ISD::UNDEF) 1482 return N1; 1483 1484 return SDValue(); 1485} 1486 1487SDValue DAGCombiner::visitUREM(SDNode *N) { 1488 SDValue N0 = N->getOperand(0); 1489 SDValue N1 = N->getOperand(1); 1490 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1491 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1492 MVT VT = N->getValueType(0); 1493 1494 // fold (urem c1, c2) -> c1%c2 1495 if (N0C && N1C && !N1C->isNullValue()) 1496 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1497 // fold (urem x, pow2) -> (and x, pow2-1) 1498 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1499 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1500 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1501 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1502 if (N1.getOpcode() == ISD::SHL) { 1503 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1504 if (SHC->getAPIntValue().isPowerOf2()) { 1505 SDValue Add = 1506 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1507 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1508 VT)); 1509 AddToWorkList(Add.getNode()); 1510 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1511 } 1512 } 1513 } 1514 1515 // If X/C can be simplified by the division-by-constant logic, lower 1516 // X%C to the equivalent of X-X/C*C. 1517 if (N1C && !N1C->isNullValue()) { 1518 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1519 AddToWorkList(Div.getNode()); 1520 SDValue OptimizedDiv = combine(Div.getNode()); 1521 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1522 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1523 OptimizedDiv, N1); 1524 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1525 AddToWorkList(Mul.getNode()); 1526 return Sub; 1527 } 1528 } 1529 1530 // undef % X -> 0 1531 if (N0.getOpcode() == ISD::UNDEF) 1532 return DAG.getConstant(0, VT); 1533 // X % undef -> undef 1534 if (N1.getOpcode() == ISD::UNDEF) 1535 return N1; 1536 1537 return SDValue(); 1538} 1539 1540SDValue DAGCombiner::visitMULHS(SDNode *N) { 1541 SDValue N0 = N->getOperand(0); 1542 SDValue N1 = N->getOperand(1); 1543 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1544 MVT VT = N->getValueType(0); 1545 1546 // fold (mulhs x, 0) -> 0 1547 if (N1C && N1C->isNullValue()) 1548 return N1; 1549 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1550 if (N1C && N1C->getAPIntValue() == 1) 1551 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1552 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1553 getShiftAmountTy())); 1554 // fold (mulhs x, undef) -> 0 1555 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1556 return DAG.getConstant(0, VT); 1557 1558 return SDValue(); 1559} 1560 1561SDValue DAGCombiner::visitMULHU(SDNode *N) { 1562 SDValue N0 = N->getOperand(0); 1563 SDValue N1 = N->getOperand(1); 1564 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1565 MVT VT = N->getValueType(0); 1566 1567 // fold (mulhu x, 0) -> 0 1568 if (N1C && N1C->isNullValue()) 1569 return N1; 1570 // fold (mulhu x, 1) -> 0 1571 if (N1C && N1C->getAPIntValue() == 1) 1572 return DAG.getConstant(0, N0.getValueType()); 1573 // fold (mulhu x, undef) -> 0 1574 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1575 return DAG.getConstant(0, VT); 1576 1577 return SDValue(); 1578} 1579 1580/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1581/// compute two values. LoOp and HiOp give the opcodes for the two computations 1582/// that are being performed. Return true if a simplification was made. 1583/// 1584SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1585 unsigned HiOp) { 1586 // If the high half is not needed, just compute the low half. 1587 bool HiExists = N->hasAnyUseOfValue(1); 1588 if (!HiExists && 1589 (!LegalOperations || 1590 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1591 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1592 N->op_begin(), N->getNumOperands()); 1593 return CombineTo(N, Res, Res); 1594 } 1595 1596 // If the low half is not needed, just compute the high half. 1597 bool LoExists = N->hasAnyUseOfValue(0); 1598 if (!LoExists && 1599 (!LegalOperations || 1600 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1601 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1602 N->op_begin(), N->getNumOperands()); 1603 return CombineTo(N, Res, Res); 1604 } 1605 1606 // If both halves are used, return as it is. 1607 if (LoExists && HiExists) 1608 return SDValue(); 1609 1610 // If the two computed results can be simplified separately, separate them. 1611 if (LoExists) { 1612 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1613 N->op_begin(), N->getNumOperands()); 1614 AddToWorkList(Lo.getNode()); 1615 SDValue LoOpt = combine(Lo.getNode()); 1616 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1617 (!LegalOperations || 1618 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1619 return CombineTo(N, LoOpt, LoOpt); 1620 } 1621 1622 if (HiExists) { 1623 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1624 N->op_begin(), N->getNumOperands()); 1625 AddToWorkList(Hi.getNode()); 1626 SDValue HiOpt = combine(Hi.getNode()); 1627 if (HiOpt.getNode() && HiOpt != Hi && 1628 (!LegalOperations || 1629 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1630 return CombineTo(N, HiOpt, HiOpt); 1631 } 1632 1633 return SDValue(); 1634} 1635 1636SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1637 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1638 if (Res.getNode()) return Res; 1639 1640 return SDValue(); 1641} 1642 1643SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1644 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1645 if (Res.getNode()) return Res; 1646 1647 return SDValue(); 1648} 1649 1650SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1651 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1652 if (Res.getNode()) return Res; 1653 1654 return SDValue(); 1655} 1656 1657SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1658 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1659 if (Res.getNode()) return Res; 1660 1661 return SDValue(); 1662} 1663 1664/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1665/// two operands of the same opcode, try to simplify it. 1666SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1667 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1668 MVT VT = N0.getValueType(); 1669 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1670 1671 // For each of OP in AND/OR/XOR: 1672 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1673 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1674 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1675 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1676 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1677 N0.getOpcode() == ISD::SIGN_EXTEND || 1678 (N0.getOpcode() == ISD::TRUNCATE && 1679 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1680 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1681 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1682 N0.getOperand(0).getValueType(), 1683 N0.getOperand(0), N1.getOperand(0)); 1684 AddToWorkList(ORNode.getNode()); 1685 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1686 } 1687 1688 // For each of OP in SHL/SRL/SRA/AND... 1689 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1690 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1691 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1692 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1693 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1694 N0.getOperand(1) == N1.getOperand(1)) { 1695 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1696 N0.getOperand(0).getValueType(), 1697 N0.getOperand(0), N1.getOperand(0)); 1698 AddToWorkList(ORNode.getNode()); 1699 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1700 ORNode, N0.getOperand(1)); 1701 } 1702 1703 return SDValue(); 1704} 1705 1706SDValue DAGCombiner::visitAND(SDNode *N) { 1707 SDValue N0 = N->getOperand(0); 1708 SDValue N1 = N->getOperand(1); 1709 SDValue LL, LR, RL, RR, CC0, CC1; 1710 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1711 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1712 MVT VT = N1.getValueType(); 1713 unsigned BitWidth = VT.getSizeInBits(); 1714 1715 // fold vector ops 1716 if (VT.isVector()) { 1717 SDValue FoldedVOp = SimplifyVBinOp(N); 1718 if (FoldedVOp.getNode()) return FoldedVOp; 1719 } 1720 1721 // fold (and x, undef) -> 0 1722 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1723 return DAG.getConstant(0, VT); 1724 // fold (and c1, c2) -> c1&c2 1725 if (N0C && N1C) 1726 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1727 // canonicalize constant to RHS 1728 if (N0C && !N1C) 1729 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1730 // fold (and x, -1) -> x 1731 if (N1C && N1C->isAllOnesValue()) 1732 return N0; 1733 // if (and x, c) is known to be zero, return 0 1734 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1735 APInt::getAllOnesValue(BitWidth))) 1736 return DAG.getConstant(0, VT); 1737 // reassociate and 1738 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1739 if (RAND.getNode() != 0) 1740 return RAND; 1741 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1742 if (N1C && N0.getOpcode() == ISD::OR) 1743 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1744 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1745 return N1; 1746 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1747 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1748 SDValue N0Op0 = N0.getOperand(0); 1749 APInt Mask = ~N1C->getAPIntValue(); 1750 Mask.trunc(N0Op0.getValueSizeInBits()); 1751 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1752 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1753 N0.getValueType(), N0Op0); 1754 1755 // Replace uses of the AND with uses of the Zero extend node. 1756 CombineTo(N, Zext); 1757 1758 // We actually want to replace all uses of the any_extend with the 1759 // zero_extend, to avoid duplicating things. This will later cause this 1760 // AND to be folded. 1761 CombineTo(N0.getNode(), Zext); 1762 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1763 } 1764 } 1765 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1766 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1767 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1768 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1769 1770 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1771 LL.getValueType().isInteger()) { 1772 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1773 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1774 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1775 LR.getValueType(), LL, RL); 1776 AddToWorkList(ORNode.getNode()); 1777 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1778 } 1779 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1780 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1781 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1782 LR.getValueType(), LL, RL); 1783 AddToWorkList(ANDNode.getNode()); 1784 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1785 } 1786 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1787 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1788 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1789 LR.getValueType(), LL, RL); 1790 AddToWorkList(ORNode.getNode()); 1791 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1792 } 1793 } 1794 // canonicalize equivalent to ll == rl 1795 if (LL == RR && LR == RL) { 1796 Op1 = ISD::getSetCCSwappedOperands(Op1); 1797 std::swap(RL, RR); 1798 } 1799 if (LL == RL && LR == RR) { 1800 bool isInteger = LL.getValueType().isInteger(); 1801 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1802 if (Result != ISD::SETCC_INVALID && 1803 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1804 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1805 LL, LR, Result); 1806 } 1807 } 1808 1809 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1810 if (N0.getOpcode() == N1.getOpcode()) { 1811 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1812 if (Tmp.getNode()) return Tmp; 1813 } 1814 1815 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1816 // fold (and (sra)) -> (and (srl)) when possible. 1817 if (!VT.isVector() && 1818 SimplifyDemandedBits(SDValue(N, 0))) 1819 return SDValue(N, 0); 1820 // fold (zext_inreg (extload x)) -> (zextload x) 1821 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1822 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1823 MVT EVT = LN0->getMemoryVT(); 1824 // If we zero all the possible extended bits, then we can turn this into 1825 // a zextload if we are running before legalize or the operation is legal. 1826 unsigned BitWidth = N1.getValueSizeInBits(); 1827 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1828 BitWidth - EVT.getSizeInBits())) && 1829 ((!LegalOperations && !LN0->isVolatile()) || 1830 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1831 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1832 LN0->getChain(), LN0->getBasePtr(), 1833 LN0->getSrcValue(), 1834 LN0->getSrcValueOffset(), EVT, 1835 LN0->isVolatile(), LN0->getAlignment()); 1836 AddToWorkList(N); 1837 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1838 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1839 } 1840 } 1841 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1842 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1843 N0.hasOneUse()) { 1844 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1845 MVT EVT = LN0->getMemoryVT(); 1846 // If we zero all the possible extended bits, then we can turn this into 1847 // a zextload if we are running before legalize or the operation is legal. 1848 unsigned BitWidth = N1.getValueSizeInBits(); 1849 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1850 BitWidth - EVT.getSizeInBits())) && 1851 ((!LegalOperations && !LN0->isVolatile()) || 1852 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1853 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1854 LN0->getChain(), 1855 LN0->getBasePtr(), LN0->getSrcValue(), 1856 LN0->getSrcValueOffset(), EVT, 1857 LN0->isVolatile(), LN0->getAlignment()); 1858 AddToWorkList(N); 1859 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1860 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1861 } 1862 } 1863 1864 // fold (and (load x), 255) -> (zextload x, i8) 1865 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1866 if (N1C && N0.getOpcode() == ISD::LOAD) { 1867 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1868 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1869 LN0->isUnindexed() && N0.hasOneUse() && 1870 // Do not change the width of a volatile load. 1871 !LN0->isVolatile()) { 1872 MVT EVT = MVT::Other; 1873 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1874 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1875 EVT = MVT::getIntegerVT(ActiveBits); 1876 1877 MVT LoadedVT = LN0->getMemoryVT(); 1878 1879 // Do not generate loads of non-round integer types since these can 1880 // be expensive (and would be wrong if the type is not byte sized). 1881 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1882 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1883 MVT PtrType = N0.getOperand(1).getValueType(); 1884 1885 // For big endian targets, we need to add an offset to the pointer to 1886 // load the correct bytes. For little endian systems, we merely need to 1887 // read fewer bytes from the same pointer. 1888 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1889 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1890 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1891 unsigned Alignment = LN0->getAlignment(); 1892 SDValue NewPtr = LN0->getBasePtr(); 1893 1894 if (TLI.isBigEndian()) { 1895 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1896 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1897 Alignment = MinAlign(Alignment, PtrOff); 1898 } 1899 1900 AddToWorkList(NewPtr.getNode()); 1901 SDValue Load = 1902 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1903 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1904 EVT, LN0->isVolatile(), Alignment); 1905 AddToWorkList(N); 1906 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1907 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1908 } 1909 } 1910 } 1911 1912 return SDValue(); 1913} 1914 1915SDValue DAGCombiner::visitOR(SDNode *N) { 1916 SDValue N0 = N->getOperand(0); 1917 SDValue N1 = N->getOperand(1); 1918 SDValue LL, LR, RL, RR, CC0, CC1; 1919 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1920 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1921 MVT VT = N1.getValueType(); 1922 1923 // fold vector ops 1924 if (VT.isVector()) { 1925 SDValue FoldedVOp = SimplifyVBinOp(N); 1926 if (FoldedVOp.getNode()) return FoldedVOp; 1927 } 1928 1929 // fold (or x, undef) -> -1 1930 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1931 return DAG.getConstant(~0ULL, VT); 1932 // fold (or c1, c2) -> c1|c2 1933 if (N0C && N1C) 1934 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1935 // canonicalize constant to RHS 1936 if (N0C && !N1C) 1937 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1938 // fold (or x, 0) -> x 1939 if (N1C && N1C->isNullValue()) 1940 return N0; 1941 // fold (or x, -1) -> -1 1942 if (N1C && N1C->isAllOnesValue()) 1943 return N1; 1944 // fold (or x, c) -> c iff (x & ~c) == 0 1945 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1946 return N1; 1947 // reassociate or 1948 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1949 if (ROR.getNode() != 0) 1950 return ROR; 1951 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1952 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1953 isa<ConstantSDNode>(N0.getOperand(1))) { 1954 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1955 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1956 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1957 N0.getOperand(0), N1), 1958 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1959 } 1960 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1961 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1962 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1963 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1964 1965 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1966 LL.getValueType().isInteger()) { 1967 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1968 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1969 if (cast<ConstantSDNode>(LR)->isNullValue() && 1970 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1971 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1972 LR.getValueType(), LL, RL); 1973 AddToWorkList(ORNode.getNode()); 1974 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1975 } 1976 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 1977 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 1978 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1979 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1980 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 1981 LR.getValueType(), LL, RL); 1982 AddToWorkList(ANDNode.getNode()); 1983 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1984 } 1985 } 1986 // canonicalize equivalent to ll == rl 1987 if (LL == RR && LR == RL) { 1988 Op1 = ISD::getSetCCSwappedOperands(Op1); 1989 std::swap(RL, RR); 1990 } 1991 if (LL == RL && LR == RR) { 1992 bool isInteger = LL.getValueType().isInteger(); 1993 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1994 if (Result != ISD::SETCC_INVALID && 1995 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1996 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1997 LL, LR, Result); 1998 } 1999 } 2000 2001 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2002 if (N0.getOpcode() == N1.getOpcode()) { 2003 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2004 if (Tmp.getNode()) return Tmp; 2005 } 2006 2007 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2008 if (N0.getOpcode() == ISD::AND && 2009 N1.getOpcode() == ISD::AND && 2010 N0.getOperand(1).getOpcode() == ISD::Constant && 2011 N1.getOperand(1).getOpcode() == ISD::Constant && 2012 // Don't increase # computations. 2013 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2014 // We can only do this xform if we know that bits from X that are set in C2 2015 // but not in C1 are already zero. Likewise for Y. 2016 const APInt &LHSMask = 2017 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2018 const APInt &RHSMask = 2019 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2020 2021 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2022 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2023 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2024 N0.getOperand(0), N1.getOperand(0)); 2025 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2026 DAG.getConstant(LHSMask | RHSMask, VT)); 2027 } 2028 } 2029 2030 // See if this is some rotate idiom. 2031 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2032 return SDValue(Rot, 0); 2033 2034 return SDValue(); 2035} 2036 2037/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2038static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2039 if (Op.getOpcode() == ISD::AND) { 2040 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2041 Mask = Op.getOperand(1); 2042 Op = Op.getOperand(0); 2043 } else { 2044 return false; 2045 } 2046 } 2047 2048 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2049 Shift = Op; 2050 return true; 2051 } 2052 2053 return false; 2054} 2055 2056// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2057// idioms for rotate, and if the target supports rotation instructions, generate 2058// a rot[lr]. 2059SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2060 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2061 MVT VT = LHS.getValueType(); 2062 if (!TLI.isTypeLegal(VT)) return 0; 2063 2064 // The target must have at least one rotate flavor. 2065 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2066 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2067 if (!HasROTL && !HasROTR) return 0; 2068 2069 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2070 SDValue LHSShift; // The shift. 2071 SDValue LHSMask; // AND value if any. 2072 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2073 return 0; // Not part of a rotate. 2074 2075 SDValue RHSShift; // The shift. 2076 SDValue RHSMask; // AND value if any. 2077 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2078 return 0; // Not part of a rotate. 2079 2080 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2081 return 0; // Not shifting the same value. 2082 2083 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2084 return 0; // Shifts must disagree. 2085 2086 // Canonicalize shl to left side in a shl/srl pair. 2087 if (RHSShift.getOpcode() == ISD::SHL) { 2088 std::swap(LHS, RHS); 2089 std::swap(LHSShift, RHSShift); 2090 std::swap(LHSMask , RHSMask ); 2091 } 2092 2093 unsigned OpSizeInBits = VT.getSizeInBits(); 2094 SDValue LHSShiftArg = LHSShift.getOperand(0); 2095 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2096 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2097 2098 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2099 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2100 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2101 RHSShiftAmt.getOpcode() == ISD::Constant) { 2102 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2103 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2104 if ((LShVal + RShVal) != OpSizeInBits) 2105 return 0; 2106 2107 SDValue Rot; 2108 if (HasROTL) 2109 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2110 else 2111 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2112 2113 // If there is an AND of either shifted operand, apply it to the result. 2114 if (LHSMask.getNode() || RHSMask.getNode()) { 2115 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2116 2117 if (LHSMask.getNode()) { 2118 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2119 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2120 } 2121 if (RHSMask.getNode()) { 2122 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2123 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2124 } 2125 2126 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2127 } 2128 2129 return Rot.getNode(); 2130 } 2131 2132 // If there is a mask here, and we have a variable shift, we can't be sure 2133 // that we're masking out the right stuff. 2134 if (LHSMask.getNode() || RHSMask.getNode()) 2135 return 0; 2136 2137 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2138 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2139 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2140 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2141 if (ConstantSDNode *SUBC = 2142 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2143 if (SUBC->getAPIntValue() == OpSizeInBits) { 2144 if (HasROTL) 2145 return DAG.getNode(ISD::ROTL, DL, VT, 2146 LHSShiftArg, LHSShiftAmt).getNode(); 2147 else 2148 return DAG.getNode(ISD::ROTR, DL, VT, 2149 LHSShiftArg, RHSShiftAmt).getNode(); 2150 } 2151 } 2152 } 2153 2154 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2155 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2156 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2157 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2158 if (ConstantSDNode *SUBC = 2159 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2160 if (SUBC->getAPIntValue() == OpSizeInBits) { 2161 if (HasROTR) 2162 return DAG.getNode(ISD::ROTR, DL, VT, 2163 LHSShiftArg, RHSShiftAmt).getNode(); 2164 else 2165 return DAG.getNode(ISD::ROTL, DL, VT, 2166 LHSShiftArg, LHSShiftAmt).getNode(); 2167 } 2168 } 2169 } 2170 2171 // Look for sign/zext/any-extended or truncate cases: 2172 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2173 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2174 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2175 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2176 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2177 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2178 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2179 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2180 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2181 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2182 if (RExtOp0.getOpcode() == ISD::SUB && 2183 RExtOp0.getOperand(1) == LExtOp0) { 2184 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2185 // (rotl x, y) 2186 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2187 // (rotr x, (sub 32, y)) 2188 if (ConstantSDNode *SUBC = 2189 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2190 if (SUBC->getAPIntValue() == OpSizeInBits) { 2191 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2192 LHSShiftArg, 2193 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2194 } 2195 } 2196 } else if (LExtOp0.getOpcode() == ISD::SUB && 2197 RExtOp0 == LExtOp0.getOperand(1)) { 2198 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2199 // (rotr x, y) 2200 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2201 // (rotl x, (sub 32, y)) 2202 if (ConstantSDNode *SUBC = 2203 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2204 if (SUBC->getAPIntValue() == OpSizeInBits) { 2205 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2206 LHSShiftArg, 2207 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2208 } 2209 } 2210 } 2211 } 2212 2213 return 0; 2214} 2215 2216SDValue DAGCombiner::visitXOR(SDNode *N) { 2217 SDValue N0 = N->getOperand(0); 2218 SDValue N1 = N->getOperand(1); 2219 SDValue LHS, RHS, CC; 2220 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2221 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2222 MVT VT = N0.getValueType(); 2223 2224 // fold vector ops 2225 if (VT.isVector()) { 2226 SDValue FoldedVOp = SimplifyVBinOp(N); 2227 if (FoldedVOp.getNode()) return FoldedVOp; 2228 } 2229 2230 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2231 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2232 return DAG.getConstant(0, VT); 2233 // fold (xor x, undef) -> undef 2234 if (N0.getOpcode() == ISD::UNDEF) 2235 return N0; 2236 if (N1.getOpcode() == ISD::UNDEF) 2237 return N1; 2238 // fold (xor c1, c2) -> c1^c2 2239 if (N0C && N1C) 2240 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2241 // canonicalize constant to RHS 2242 if (N0C && !N1C) 2243 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2244 // fold (xor x, 0) -> x 2245 if (N1C && N1C->isNullValue()) 2246 return N0; 2247 // reassociate xor 2248 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2249 if (RXOR.getNode() != 0) 2250 return RXOR; 2251 2252 // fold !(x cc y) -> (x !cc y) 2253 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2254 bool isInt = LHS.getValueType().isInteger(); 2255 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2256 isInt); 2257 2258 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2259 switch (N0.getOpcode()) { 2260 default: 2261 assert(0 && "Unhandled SetCC Equivalent!"); 2262 abort(); 2263 case ISD::SETCC: 2264 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2265 case ISD::SELECT_CC: 2266 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2267 N0.getOperand(3), NotCC); 2268 } 2269 } 2270 } 2271 2272 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2273 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2274 N0.getNode()->hasOneUse() && 2275 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2276 SDValue V = N0.getOperand(0); 2277 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2278 DAG.getConstant(1, V.getValueType())); 2279 AddToWorkList(V.getNode()); 2280 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2281 } 2282 2283 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2284 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2285 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2286 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2287 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2288 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2289 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2290 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2291 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2292 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2293 } 2294 } 2295 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2296 if (N1C && N1C->isAllOnesValue() && 2297 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2298 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2299 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2300 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2301 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2302 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2303 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2304 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2305 } 2306 } 2307 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2308 if (N1C && N0.getOpcode() == ISD::XOR) { 2309 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2310 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2311 if (N00C) 2312 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2313 DAG.getConstant(N1C->getAPIntValue() ^ 2314 N00C->getAPIntValue(), VT)); 2315 if (N01C) 2316 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2317 DAG.getConstant(N1C->getAPIntValue() ^ 2318 N01C->getAPIntValue(), VT)); 2319 } 2320 // fold (xor x, x) -> 0 2321 if (N0 == N1) { 2322 if (!VT.isVector()) { 2323 return DAG.getConstant(0, VT); 2324 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2325 // Produce a vector of zeros. 2326 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2327 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2328 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2329 &Ops[0], Ops.size()); 2330 } 2331 } 2332 2333 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2334 if (N0.getOpcode() == N1.getOpcode()) { 2335 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2336 if (Tmp.getNode()) return Tmp; 2337 } 2338 2339 // Simplify the expression using non-local knowledge. 2340 if (!VT.isVector() && 2341 SimplifyDemandedBits(SDValue(N, 0))) 2342 return SDValue(N, 0); 2343 2344 return SDValue(); 2345} 2346 2347/// visitShiftByConstant - Handle transforms common to the three shifts, when 2348/// the shift amount is a constant. 2349SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2350 SDNode *LHS = N->getOperand(0).getNode(); 2351 if (!LHS->hasOneUse()) return SDValue(); 2352 2353 // We want to pull some binops through shifts, so that we have (and (shift)) 2354 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2355 // thing happens with address calculations, so it's important to canonicalize 2356 // it. 2357 bool HighBitSet = false; // Can we transform this if the high bit is set? 2358 2359 switch (LHS->getOpcode()) { 2360 default: return SDValue(); 2361 case ISD::OR: 2362 case ISD::XOR: 2363 HighBitSet = false; // We can only transform sra if the high bit is clear. 2364 break; 2365 case ISD::AND: 2366 HighBitSet = true; // We can only transform sra if the high bit is set. 2367 break; 2368 case ISD::ADD: 2369 if (N->getOpcode() != ISD::SHL) 2370 return SDValue(); // only shl(add) not sr[al](add). 2371 HighBitSet = false; // We can only transform sra if the high bit is clear. 2372 break; 2373 } 2374 2375 // We require the RHS of the binop to be a constant as well. 2376 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2377 if (!BinOpCst) return SDValue(); 2378 2379 // FIXME: disable this unless the input to the binop is a shift by a constant. 2380 // If it is not a shift, it pessimizes some common cases like: 2381 // 2382 // void foo(int *X, int i) { X[i & 1235] = 1; } 2383 // int bar(int *X, int i) { return X[i & 255]; } 2384 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2385 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2386 BinOpLHSVal->getOpcode() != ISD::SRA && 2387 BinOpLHSVal->getOpcode() != ISD::SRL) || 2388 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2389 return SDValue(); 2390 2391 MVT VT = N->getValueType(0); 2392 2393 // If this is a signed shift right, and the high bit is modified by the 2394 // logical operation, do not perform the transformation. The highBitSet 2395 // boolean indicates the value of the high bit of the constant which would 2396 // cause it to be modified for this operation. 2397 if (N->getOpcode() == ISD::SRA) { 2398 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2399 if (BinOpRHSSignSet != HighBitSet) 2400 return SDValue(); 2401 } 2402 2403 // Fold the constants, shifting the binop RHS by the shift amount. 2404 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2405 N->getValueType(0), 2406 LHS->getOperand(1), N->getOperand(1)); 2407 2408 // Create the new shift. 2409 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2410 VT, LHS->getOperand(0), N->getOperand(1)); 2411 2412 // Create the new binop. 2413 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2414} 2415 2416SDValue DAGCombiner::visitSHL(SDNode *N) { 2417 SDValue N0 = N->getOperand(0); 2418 SDValue N1 = N->getOperand(1); 2419 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2420 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2421 MVT VT = N0.getValueType(); 2422 unsigned OpSizeInBits = VT.getSizeInBits(); 2423 2424 // fold (shl c1, c2) -> c1<<c2 2425 if (N0C && N1C) 2426 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2427 // fold (shl 0, x) -> 0 2428 if (N0C && N0C->isNullValue()) 2429 return N0; 2430 // fold (shl x, c >= size(x)) -> undef 2431 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2432 return DAG.getUNDEF(VT); 2433 // fold (shl x, 0) -> x 2434 if (N1C && N1C->isNullValue()) 2435 return N0; 2436 // if (shl x, c) is known to be zero, return 0 2437 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2438 APInt::getAllOnesValue(VT.getSizeInBits()))) 2439 return DAG.getConstant(0, VT); 2440 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2441 if (N1.getOpcode() == ISD::TRUNCATE && 2442 N1.getOperand(0).getOpcode() == ISD::AND && 2443 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2444 SDValue N101 = N1.getOperand(0).getOperand(1); 2445 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2446 MVT TruncVT = N1.getValueType(); 2447 SDValue N100 = N1.getOperand(0).getOperand(0); 2448 APInt TruncC = N101C->getAPIntValue(); 2449 TruncC.trunc(TruncVT.getSizeInBits()); 2450 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2451 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2452 DAG.getNode(ISD::TRUNCATE, 2453 N->getDebugLoc(), 2454 TruncVT, N100), 2455 DAG.getConstant(TruncC, TruncVT))); 2456 } 2457 } 2458 2459 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2460 return SDValue(N, 0); 2461 2462 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2463 if (N1C && N0.getOpcode() == ISD::SHL && 2464 N0.getOperand(1).getOpcode() == ISD::Constant) { 2465 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2466 uint64_t c2 = N1C->getZExtValue(); 2467 if (c1 + c2 > OpSizeInBits) 2468 return DAG.getConstant(0, VT); 2469 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2470 DAG.getConstant(c1 + c2, N1.getValueType())); 2471 } 2472 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2473 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2474 if (N1C && N0.getOpcode() == ISD::SRL && 2475 N0.getOperand(1).getOpcode() == ISD::Constant) { 2476 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2477 uint64_t c2 = N1C->getZExtValue(); 2478 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), 2479 DAG.getConstant(~0ULL << c1, VT)); 2480 if (c2 > c1) 2481 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2482 DAG.getConstant(c2-c1, N1.getValueType())); 2483 else 2484 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2485 DAG.getConstant(c1-c2, N1.getValueType())); 2486 } 2487 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2488 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2489 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2490 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2491 2492 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2493} 2494 2495SDValue DAGCombiner::visitSRA(SDNode *N) { 2496 SDValue N0 = N->getOperand(0); 2497 SDValue N1 = N->getOperand(1); 2498 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2499 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2500 MVT VT = N0.getValueType(); 2501 2502 // fold (sra c1, c2) -> (sra c1, c2) 2503 if (N0C && N1C) 2504 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2505 // fold (sra 0, x) -> 0 2506 if (N0C && N0C->isNullValue()) 2507 return N0; 2508 // fold (sra -1, x) -> -1 2509 if (N0C && N0C->isAllOnesValue()) 2510 return N0; 2511 // fold (sra x, (setge c, size(x))) -> undef 2512 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2513 return DAG.getUNDEF(VT); 2514 // fold (sra x, 0) -> x 2515 if (N1C && N1C->isNullValue()) 2516 return N0; 2517 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2518 // sext_inreg. 2519 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2520 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2521 MVT EVT = MVT::getIntegerVT(LowBits); 2522 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2523 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2524 N0.getOperand(0), DAG.getValueType(EVT)); 2525 } 2526 2527 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2528 if (N1C && N0.getOpcode() == ISD::SRA) { 2529 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2530 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2531 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2532 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2533 DAG.getConstant(Sum, N1C->getValueType(0))); 2534 } 2535 } 2536 2537 // fold (sra (shl X, m), (sub result_size, n)) 2538 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2539 // result_size - n != m. 2540 // If truncate is free for the target sext(shl) is likely to result in better 2541 // code. 2542 if (N0.getOpcode() == ISD::SHL) { 2543 // Get the two constanst of the shifts, CN0 = m, CN = n. 2544 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2545 if (N01C && N1C) { 2546 // Determine what the truncate's result bitsize and type would be. 2547 unsigned VTValSize = VT.getSizeInBits(); 2548 MVT TruncVT = 2549 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2550 // Determine the residual right-shift amount. 2551 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2552 2553 // If the shift is not a no-op (in which case this should be just a sign 2554 // extend already), the truncated to type is legal, sign_extend is legal 2555 // on that type, and the the truncate to that type is both legal and free, 2556 // perform the transform. 2557 if ((ShiftAmt > 0) && 2558 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2559 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2560 TLI.isTruncateFree(VT, TruncVT)) { 2561 2562 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2563 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2564 N0.getOperand(0), Amt); 2565 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2566 Shift); 2567 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2568 N->getValueType(0), Trunc); 2569 } 2570 } 2571 } 2572 2573 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2574 if (N1.getOpcode() == ISD::TRUNCATE && 2575 N1.getOperand(0).getOpcode() == ISD::AND && 2576 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2577 SDValue N101 = N1.getOperand(0).getOperand(1); 2578 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2579 MVT TruncVT = N1.getValueType(); 2580 SDValue N100 = N1.getOperand(0).getOperand(0); 2581 APInt TruncC = N101C->getAPIntValue(); 2582 TruncC.trunc(TruncVT.getSizeInBits()); 2583 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2584 DAG.getNode(ISD::AND, N->getDebugLoc(), 2585 TruncVT, 2586 DAG.getNode(ISD::TRUNCATE, 2587 N->getDebugLoc(), 2588 TruncVT, N100), 2589 DAG.getConstant(TruncC, TruncVT))); 2590 } 2591 } 2592 2593 // Simplify, based on bits shifted out of the LHS. 2594 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2595 return SDValue(N, 0); 2596 2597 2598 // If the sign bit is known to be zero, switch this to a SRL. 2599 if (DAG.SignBitIsZero(N0)) 2600 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2601 2602 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2603} 2604 2605SDValue DAGCombiner::visitSRL(SDNode *N) { 2606 SDValue N0 = N->getOperand(0); 2607 SDValue N1 = N->getOperand(1); 2608 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2609 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2610 MVT VT = N0.getValueType(); 2611 unsigned OpSizeInBits = VT.getSizeInBits(); 2612 2613 // fold (srl c1, c2) -> c1 >>u c2 2614 if (N0C && N1C) 2615 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2616 // fold (srl 0, x) -> 0 2617 if (N0C && N0C->isNullValue()) 2618 return N0; 2619 // fold (srl x, c >= size(x)) -> undef 2620 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2621 return DAG.getUNDEF(VT); 2622 // fold (srl x, 0) -> x 2623 if (N1C && N1C->isNullValue()) 2624 return N0; 2625 // if (srl x, c) is known to be zero, return 0 2626 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2627 APInt::getAllOnesValue(OpSizeInBits))) 2628 return DAG.getConstant(0, VT); 2629 2630 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2631 if (N1C && N0.getOpcode() == ISD::SRL && 2632 N0.getOperand(1).getOpcode() == ISD::Constant) { 2633 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2634 uint64_t c2 = N1C->getZExtValue(); 2635 if (c1 + c2 > OpSizeInBits) 2636 return DAG.getConstant(0, VT); 2637 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2638 DAG.getConstant(c1 + c2, N1.getValueType())); 2639 } 2640 2641 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2642 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2643 // Shifting in all undef bits? 2644 MVT SmallVT = N0.getOperand(0).getValueType(); 2645 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2646 return DAG.getUNDEF(VT); 2647 2648 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2649 N0.getOperand(0), N1); 2650 AddToWorkList(SmallShift.getNode()); 2651 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2652 } 2653 2654 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2655 // bit, which is unmodified by sra. 2656 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2657 if (N0.getOpcode() == ISD::SRA) 2658 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2659 } 2660 2661 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2662 if (N1C && N0.getOpcode() == ISD::CTLZ && 2663 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2664 APInt KnownZero, KnownOne; 2665 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2666 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2667 2668 // If any of the input bits are KnownOne, then the input couldn't be all 2669 // zeros, thus the result of the srl will always be zero. 2670 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2671 2672 // If all of the bits input the to ctlz node are known to be zero, then 2673 // the result of the ctlz is "32" and the result of the shift is one. 2674 APInt UnknownBits = ~KnownZero & Mask; 2675 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2676 2677 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2678 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2679 // Okay, we know that only that the single bit specified by UnknownBits 2680 // could be set on input to the CTLZ node. If this bit is set, the SRL 2681 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2682 // to an SRL/XOR pair, which is likely to simplify more. 2683 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2684 SDValue Op = N0.getOperand(0); 2685 2686 if (ShAmt) { 2687 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2688 DAG.getConstant(ShAmt, getShiftAmountTy())); 2689 AddToWorkList(Op.getNode()); 2690 } 2691 2692 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2693 Op, DAG.getConstant(1, VT)); 2694 } 2695 } 2696 2697 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2698 if (N1.getOpcode() == ISD::TRUNCATE && 2699 N1.getOperand(0).getOpcode() == ISD::AND && 2700 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2701 SDValue N101 = N1.getOperand(0).getOperand(1); 2702 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2703 MVT TruncVT = N1.getValueType(); 2704 SDValue N100 = N1.getOperand(0).getOperand(0); 2705 APInt TruncC = N101C->getAPIntValue(); 2706 TruncC.trunc(TruncVT.getSizeInBits()); 2707 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2708 DAG.getNode(ISD::AND, N->getDebugLoc(), 2709 TruncVT, 2710 DAG.getNode(ISD::TRUNCATE, 2711 N->getDebugLoc(), 2712 TruncVT, N100), 2713 DAG.getConstant(TruncC, TruncVT))); 2714 } 2715 } 2716 2717 // fold operands of srl based on knowledge that the low bits are not 2718 // demanded. 2719 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2720 return SDValue(N, 0); 2721 2722 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2723} 2724 2725SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2726 SDValue N0 = N->getOperand(0); 2727 MVT VT = N->getValueType(0); 2728 2729 // fold (ctlz c1) -> c2 2730 if (isa<ConstantSDNode>(N0)) 2731 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2732 return SDValue(); 2733} 2734 2735SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2736 SDValue N0 = N->getOperand(0); 2737 MVT VT = N->getValueType(0); 2738 2739 // fold (cttz c1) -> c2 2740 if (isa<ConstantSDNode>(N0)) 2741 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2742 return SDValue(); 2743} 2744 2745SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2746 SDValue N0 = N->getOperand(0); 2747 MVT VT = N->getValueType(0); 2748 2749 // fold (ctpop c1) -> c2 2750 if (isa<ConstantSDNode>(N0)) 2751 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2752 return SDValue(); 2753} 2754 2755SDValue DAGCombiner::visitSELECT(SDNode *N) { 2756 SDValue N0 = N->getOperand(0); 2757 SDValue N1 = N->getOperand(1); 2758 SDValue N2 = N->getOperand(2); 2759 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2760 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2761 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2762 MVT VT = N->getValueType(0); 2763 MVT VT0 = N0.getValueType(); 2764 2765 // fold (select C, X, X) -> X 2766 if (N1 == N2) 2767 return N1; 2768 // fold (select true, X, Y) -> X 2769 if (N0C && !N0C->isNullValue()) 2770 return N1; 2771 // fold (select false, X, Y) -> Y 2772 if (N0C && N0C->isNullValue()) 2773 return N2; 2774 // fold (select C, 1, X) -> (or C, X) 2775 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2776 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2777 // fold (select C, 0, 1) -> (xor C, 1) 2778 if (VT.isInteger() && 2779 (VT0 == MVT::i1 || 2780 (VT0.isInteger() && 2781 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2782 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2783 SDValue XORNode; 2784 if (VT == VT0) 2785 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2786 N0, DAG.getConstant(1, VT0)); 2787 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2788 N0, DAG.getConstant(1, VT0)); 2789 AddToWorkList(XORNode.getNode()); 2790 if (VT.bitsGT(VT0)) 2791 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2792 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2793 } 2794 // fold (select C, 0, X) -> (and (not C), X) 2795 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2796 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2797 AddToWorkList(NOTNode.getNode()); 2798 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2799 } 2800 // fold (select C, X, 1) -> (or (not C), X) 2801 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2802 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2803 AddToWorkList(NOTNode.getNode()); 2804 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2805 } 2806 // fold (select C, X, 0) -> (and C, X) 2807 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2808 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2809 // fold (select X, X, Y) -> (or X, Y) 2810 // fold (select X, 1, Y) -> (or X, Y) 2811 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2812 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2813 // fold (select X, Y, X) -> (and X, Y) 2814 // fold (select X, Y, 0) -> (and X, Y) 2815 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2816 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2817 2818 // If we can fold this based on the true/false value, do so. 2819 if (SimplifySelectOps(N, N1, N2)) 2820 return SDValue(N, 0); // Don't revisit N. 2821 2822 // fold selects based on a setcc into other things, such as min/max/abs 2823 if (N0.getOpcode() == ISD::SETCC) { 2824 // FIXME: 2825 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2826 // having to say they don't support SELECT_CC on every type the DAG knows 2827 // about, since there is no way to mark an opcode illegal at all value types 2828 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2829 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2830 N0.getOperand(0), N0.getOperand(1), 2831 N1, N2, N0.getOperand(2)); 2832 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2833 } 2834 2835 return SDValue(); 2836} 2837 2838SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2839 SDValue N0 = N->getOperand(0); 2840 SDValue N1 = N->getOperand(1); 2841 SDValue N2 = N->getOperand(2); 2842 SDValue N3 = N->getOperand(3); 2843 SDValue N4 = N->getOperand(4); 2844 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2845 2846 // fold select_cc lhs, rhs, x, x, cc -> x 2847 if (N2 == N3) 2848 return N2; 2849 2850 // Determine if the condition we're dealing with is constant 2851 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2852 N0, N1, CC, N->getDebugLoc(), false); 2853 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2854 2855 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2856 if (!SCCC->isNullValue()) 2857 return N2; // cond always true -> true val 2858 else 2859 return N3; // cond always false -> false val 2860 } 2861 2862 // Fold to a simpler select_cc 2863 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2864 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2865 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2866 SCC.getOperand(2)); 2867 2868 // If we can fold this based on the true/false value, do so. 2869 if (SimplifySelectOps(N, N2, N3)) 2870 return SDValue(N, 0); // Don't revisit N. 2871 2872 // fold select_cc into other things, such as min/max/abs 2873 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2874} 2875 2876SDValue DAGCombiner::visitSETCC(SDNode *N) { 2877 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2878 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2879 N->getDebugLoc()); 2880} 2881 2882// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2883// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2884// transformation. Returns true if extension are possible and the above 2885// mentioned transformation is profitable. 2886static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2887 unsigned ExtOpc, 2888 SmallVector<SDNode*, 4> &ExtendNodes, 2889 const TargetLowering &TLI) { 2890 bool HasCopyToRegUses = false; 2891 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2892 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2893 UE = N0.getNode()->use_end(); 2894 UI != UE; ++UI) { 2895 SDNode *User = *UI; 2896 if (User == N) 2897 continue; 2898 if (UI.getUse().getResNo() != N0.getResNo()) 2899 continue; 2900 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2901 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 2902 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2903 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2904 // Sign bits will be lost after a zext. 2905 return false; 2906 bool Add = false; 2907 for (unsigned i = 0; i != 2; ++i) { 2908 SDValue UseOp = User->getOperand(i); 2909 if (UseOp == N0) 2910 continue; 2911 if (!isa<ConstantSDNode>(UseOp)) 2912 return false; 2913 Add = true; 2914 } 2915 if (Add) 2916 ExtendNodes.push_back(User); 2917 continue; 2918 } 2919 // If truncates aren't free and there are users we can't 2920 // extend, it isn't worthwhile. 2921 if (!isTruncFree) 2922 return false; 2923 // Remember if this value is live-out. 2924 if (User->getOpcode() == ISD::CopyToReg) 2925 HasCopyToRegUses = true; 2926 } 2927 2928 if (HasCopyToRegUses) { 2929 bool BothLiveOut = false; 2930 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2931 UI != UE; ++UI) { 2932 SDUse &Use = UI.getUse(); 2933 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 2934 BothLiveOut = true; 2935 break; 2936 } 2937 } 2938 if (BothLiveOut) 2939 // Both unextended and extended values are live out. There had better be 2940 // good a reason for the transformation. 2941 return ExtendNodes.size(); 2942 } 2943 return true; 2944} 2945 2946SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2947 SDValue N0 = N->getOperand(0); 2948 MVT VT = N->getValueType(0); 2949 2950 // fold (sext c1) -> c1 2951 if (isa<ConstantSDNode>(N0)) 2952 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2953 2954 // fold (sext (sext x)) -> (sext x) 2955 // fold (sext (aext x)) -> (sext x) 2956 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2957 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2958 N0.getOperand(0)); 2959 2960 if (N0.getOpcode() == ISD::TRUNCATE) { 2961 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2962 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2963 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2964 if (NarrowLoad.getNode()) { 2965 if (NarrowLoad.getNode() != N0.getNode()) 2966 CombineTo(N0.getNode(), NarrowLoad); 2967 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2968 } 2969 2970 // See if the value being truncated is already sign extended. If so, just 2971 // eliminate the trunc/sext pair. 2972 SDValue Op = N0.getOperand(0); 2973 unsigned OpBits = Op.getValueType().getSizeInBits(); 2974 unsigned MidBits = N0.getValueType().getSizeInBits(); 2975 unsigned DestBits = VT.getSizeInBits(); 2976 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2977 2978 if (OpBits == DestBits) { 2979 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2980 // bits, it is already ready. 2981 if (NumSignBits > DestBits-MidBits) 2982 return Op; 2983 } else if (OpBits < DestBits) { 2984 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2985 // bits, just sext from i32. 2986 if (NumSignBits > OpBits-MidBits) 2987 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 2988 } else { 2989 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2990 // bits, just truncate to i32. 2991 if (NumSignBits > OpBits-MidBits) 2992 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 2993 } 2994 2995 // fold (sext (truncate x)) -> (sextinreg x). 2996 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2997 N0.getValueType())) { 2998 if (Op.getValueType().bitsLT(VT)) 2999 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3000 else if (Op.getValueType().bitsGT(VT)) 3001 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3002 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3003 DAG.getValueType(N0.getValueType())); 3004 } 3005 } 3006 3007 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3008 if (ISD::isNON_EXTLoad(N0.getNode()) && 3009 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3010 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3011 bool DoXform = true; 3012 SmallVector<SDNode*, 4> SetCCs; 3013 if (!N0.hasOneUse()) 3014 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3015 if (DoXform) { 3016 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3017 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3018 LN0->getChain(), 3019 LN0->getBasePtr(), LN0->getSrcValue(), 3020 LN0->getSrcValueOffset(), 3021 N0.getValueType(), 3022 LN0->isVolatile(), LN0->getAlignment()); 3023 CombineTo(N, ExtLoad); 3024 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3025 N0.getValueType(), ExtLoad); 3026 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3027 3028 // Extend SetCC uses if necessary. 3029 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3030 SDNode *SetCC = SetCCs[i]; 3031 SmallVector<SDValue, 4> Ops; 3032 3033 for (unsigned j = 0; j != 2; ++j) { 3034 SDValue SOp = SetCC->getOperand(j); 3035 if (SOp == Trunc) 3036 Ops.push_back(ExtLoad); 3037 else 3038 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3039 N->getDebugLoc(), VT, SOp)); 3040 } 3041 3042 Ops.push_back(SetCC->getOperand(2)); 3043 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3044 SetCC->getValueType(0), 3045 &Ops[0], Ops.size())); 3046 } 3047 3048 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3049 } 3050 } 3051 3052 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3053 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3054 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3055 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3056 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3057 MVT EVT = LN0->getMemoryVT(); 3058 if ((!LegalOperations && !LN0->isVolatile()) || 3059 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3060 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3061 LN0->getChain(), 3062 LN0->getBasePtr(), LN0->getSrcValue(), 3063 LN0->getSrcValueOffset(), EVT, 3064 LN0->isVolatile(), LN0->getAlignment()); 3065 CombineTo(N, ExtLoad); 3066 CombineTo(N0.getNode(), 3067 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3068 N0.getValueType(), ExtLoad), 3069 ExtLoad.getValue(1)); 3070 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3071 } 3072 } 3073 3074 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3075 if (N0.getOpcode() == ISD::SETCC) { 3076 SDValue SCC = 3077 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3078 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3079 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3080 if (SCC.getNode()) return SCC; 3081 } 3082 3083 // fold (sext x) -> (zext x) if the sign bit is known zero. 3084 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3085 DAG.SignBitIsZero(N0)) 3086 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3087 3088 return SDValue(); 3089} 3090 3091SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3092 SDValue N0 = N->getOperand(0); 3093 MVT VT = N->getValueType(0); 3094 3095 // fold (zext c1) -> c1 3096 if (isa<ConstantSDNode>(N0)) 3097 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3098 // fold (zext (zext x)) -> (zext x) 3099 // fold (zext (aext x)) -> (zext x) 3100 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3101 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3102 N0.getOperand(0)); 3103 3104 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3105 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3106 if (N0.getOpcode() == ISD::TRUNCATE) { 3107 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3108 if (NarrowLoad.getNode()) { 3109 if (NarrowLoad.getNode() != N0.getNode()) 3110 CombineTo(N0.getNode(), NarrowLoad); 3111 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3112 } 3113 } 3114 3115 // fold (zext (truncate x)) -> (and x, mask) 3116 if (N0.getOpcode() == ISD::TRUNCATE && 3117 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3118 SDValue Op = N0.getOperand(0); 3119 if (Op.getValueType().bitsLT(VT)) { 3120 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3121 } else if (Op.getValueType().bitsGT(VT)) { 3122 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3123 } 3124 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3125 } 3126 3127 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3128 // if either of the casts is not free. 3129 if (N0.getOpcode() == ISD::AND && 3130 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3131 N0.getOperand(1).getOpcode() == ISD::Constant && 3132 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3133 N0.getValueType()) || 3134 !TLI.isZExtFree(N0.getValueType(), VT))) { 3135 SDValue X = N0.getOperand(0).getOperand(0); 3136 if (X.getValueType().bitsLT(VT)) { 3137 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3138 } else if (X.getValueType().bitsGT(VT)) { 3139 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3140 } 3141 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3142 Mask.zext(VT.getSizeInBits()); 3143 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3144 X, DAG.getConstant(Mask, VT)); 3145 } 3146 3147 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3148 if (ISD::isNON_EXTLoad(N0.getNode()) && 3149 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3150 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3151 bool DoXform = true; 3152 SmallVector<SDNode*, 4> SetCCs; 3153 if (!N0.hasOneUse()) 3154 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3155 if (DoXform) { 3156 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3157 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3158 LN0->getChain(), 3159 LN0->getBasePtr(), LN0->getSrcValue(), 3160 LN0->getSrcValueOffset(), 3161 N0.getValueType(), 3162 LN0->isVolatile(), LN0->getAlignment()); 3163 CombineTo(N, ExtLoad); 3164 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3165 N0.getValueType(), ExtLoad); 3166 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3167 3168 // Extend SetCC uses if necessary. 3169 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3170 SDNode *SetCC = SetCCs[i]; 3171 SmallVector<SDValue, 4> Ops; 3172 3173 for (unsigned j = 0; j != 2; ++j) { 3174 SDValue SOp = SetCC->getOperand(j); 3175 if (SOp == Trunc) 3176 Ops.push_back(ExtLoad); 3177 else 3178 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3179 N->getDebugLoc(), VT, SOp)); 3180 } 3181 3182 Ops.push_back(SetCC->getOperand(2)); 3183 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3184 SetCC->getValueType(0), 3185 &Ops[0], Ops.size())); 3186 } 3187 3188 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3189 } 3190 } 3191 3192 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3193 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3194 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3195 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3196 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3197 MVT EVT = LN0->getMemoryVT(); 3198 if ((!LegalOperations && !LN0->isVolatile()) || 3199 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3200 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3201 LN0->getChain(), 3202 LN0->getBasePtr(), LN0->getSrcValue(), 3203 LN0->getSrcValueOffset(), EVT, 3204 LN0->isVolatile(), LN0->getAlignment()); 3205 CombineTo(N, ExtLoad); 3206 CombineTo(N0.getNode(), 3207 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3208 ExtLoad), 3209 ExtLoad.getValue(1)); 3210 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3211 } 3212 } 3213 3214 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3215 if (N0.getOpcode() == ISD::SETCC) { 3216 SDValue SCC = 3217 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3218 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3219 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3220 if (SCC.getNode()) return SCC; 3221 } 3222 3223 return SDValue(); 3224} 3225 3226SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3227 SDValue N0 = N->getOperand(0); 3228 MVT VT = N->getValueType(0); 3229 3230 // fold (aext c1) -> c1 3231 if (isa<ConstantSDNode>(N0)) 3232 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3233 // fold (aext (aext x)) -> (aext x) 3234 // fold (aext (zext x)) -> (zext x) 3235 // fold (aext (sext x)) -> (sext x) 3236 if (N0.getOpcode() == ISD::ANY_EXTEND || 3237 N0.getOpcode() == ISD::ZERO_EXTEND || 3238 N0.getOpcode() == ISD::SIGN_EXTEND) 3239 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3240 3241 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3242 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3243 if (N0.getOpcode() == ISD::TRUNCATE) { 3244 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3245 if (NarrowLoad.getNode()) { 3246 if (NarrowLoad.getNode() != N0.getNode()) 3247 CombineTo(N0.getNode(), NarrowLoad); 3248 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3249 } 3250 } 3251 3252 // fold (aext (truncate x)) 3253 if (N0.getOpcode() == ISD::TRUNCATE) { 3254 SDValue TruncOp = N0.getOperand(0); 3255 if (TruncOp.getValueType() == VT) 3256 return TruncOp; // x iff x size == zext size. 3257 if (TruncOp.getValueType().bitsGT(VT)) 3258 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3259 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3260 } 3261 3262 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3263 // if the trunc is not free. 3264 if (N0.getOpcode() == ISD::AND && 3265 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3266 N0.getOperand(1).getOpcode() == ISD::Constant && 3267 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3268 N0.getValueType())) { 3269 SDValue X = N0.getOperand(0).getOperand(0); 3270 if (X.getValueType().bitsLT(VT)) { 3271 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3272 } else if (X.getValueType().bitsGT(VT)) { 3273 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3274 } 3275 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3276 Mask.zext(VT.getSizeInBits()); 3277 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3278 X, DAG.getConstant(Mask, VT)); 3279 } 3280 3281 // fold (aext (load x)) -> (aext (truncate (extload x))) 3282 if (ISD::isNON_EXTLoad(N0.getNode()) && 3283 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3284 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3285 bool DoXform = true; 3286 SmallVector<SDNode*, 4> SetCCs; 3287 if (!N0.hasOneUse()) 3288 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3289 if (DoXform) { 3290 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3291 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3292 LN0->getChain(), 3293 LN0->getBasePtr(), LN0->getSrcValue(), 3294 LN0->getSrcValueOffset(), 3295 N0.getValueType(), 3296 LN0->isVolatile(), LN0->getAlignment()); 3297 CombineTo(N, ExtLoad); 3298 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3299 N0.getValueType(), ExtLoad); 3300 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3301 3302 // Extend SetCC uses if necessary. 3303 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3304 SDNode *SetCC = SetCCs[i]; 3305 SmallVector<SDValue, 4> Ops; 3306 3307 for (unsigned j = 0; j != 2; ++j) { 3308 SDValue SOp = SetCC->getOperand(j); 3309 if (SOp == Trunc) 3310 Ops.push_back(ExtLoad); 3311 else 3312 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3313 N->getDebugLoc(), VT, SOp)); 3314 } 3315 3316 Ops.push_back(SetCC->getOperand(2)); 3317 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3318 SetCC->getValueType(0), 3319 &Ops[0], Ops.size())); 3320 } 3321 3322 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3323 } 3324 } 3325 3326 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3327 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3328 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3329 if (N0.getOpcode() == ISD::LOAD && 3330 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3331 N0.hasOneUse()) { 3332 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3333 MVT EVT = LN0->getMemoryVT(); 3334 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3335 VT, LN0->getChain(), LN0->getBasePtr(), 3336 LN0->getSrcValue(), 3337 LN0->getSrcValueOffset(), EVT, 3338 LN0->isVolatile(), LN0->getAlignment()); 3339 CombineTo(N, ExtLoad); 3340 CombineTo(N0.getNode(), 3341 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3342 N0.getValueType(), ExtLoad), 3343 ExtLoad.getValue(1)); 3344 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3345 } 3346 3347 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3348 if (N0.getOpcode() == ISD::SETCC) { 3349 SDValue SCC = 3350 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3351 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3352 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3353 if (SCC.getNode()) 3354 return SCC; 3355 } 3356 3357 return SDValue(); 3358} 3359 3360/// GetDemandedBits - See if the specified operand can be simplified with the 3361/// knowledge that only the bits specified by Mask are used. If so, return the 3362/// simpler operand, otherwise return a null SDValue. 3363SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3364 switch (V.getOpcode()) { 3365 default: break; 3366 case ISD::OR: 3367 case ISD::XOR: 3368 // If the LHS or RHS don't contribute bits to the or, drop them. 3369 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3370 return V.getOperand(1); 3371 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3372 return V.getOperand(0); 3373 break; 3374 case ISD::SRL: 3375 // Only look at single-use SRLs. 3376 if (!V.getNode()->hasOneUse()) 3377 break; 3378 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3379 // See if we can recursively simplify the LHS. 3380 unsigned Amt = RHSC->getZExtValue(); 3381 3382 // Watch out for shift count overflow though. 3383 if (Amt >= Mask.getBitWidth()) break; 3384 APInt NewMask = Mask << Amt; 3385 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3386 if (SimplifyLHS.getNode()) 3387 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3388 SimplifyLHS, V.getOperand(1)); 3389 } 3390 } 3391 return SDValue(); 3392} 3393 3394/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3395/// bits and then truncated to a narrower type and where N is a multiple 3396/// of number of bits of the narrower type, transform it to a narrower load 3397/// from address + N / num of bits of new type. If the result is to be 3398/// extended, also fold the extension to form a extending load. 3399SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3400 unsigned Opc = N->getOpcode(); 3401 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3402 SDValue N0 = N->getOperand(0); 3403 MVT VT = N->getValueType(0); 3404 MVT EVT = VT; 3405 3406 // This transformation isn't valid for vector loads. 3407 if (VT.isVector()) 3408 return SDValue(); 3409 3410 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3411 // extended to VT. 3412 if (Opc == ISD::SIGN_EXTEND_INREG) { 3413 ExtType = ISD::SEXTLOAD; 3414 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3415 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3416 return SDValue(); 3417 } 3418 3419 unsigned EVTBits = EVT.getSizeInBits(); 3420 unsigned ShAmt = 0; 3421 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3422 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3423 ShAmt = N01->getZExtValue(); 3424 // Is the shift amount a multiple of size of VT? 3425 if ((ShAmt & (EVTBits-1)) == 0) { 3426 N0 = N0.getOperand(0); 3427 if (N0.getValueType().getSizeInBits() <= EVTBits) 3428 return SDValue(); 3429 } 3430 } 3431 } 3432 3433 // Do not generate loads of non-round integer types since these can 3434 // be expensive (and would be wrong if the type is not byte sized). 3435 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3436 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3437 // Do not change the width of a volatile load. 3438 !cast<LoadSDNode>(N0)->isVolatile()) { 3439 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3440 MVT PtrType = N0.getOperand(1).getValueType(); 3441 3442 // For big endian targets, we need to adjust the offset to the pointer to 3443 // load the correct bytes. 3444 if (TLI.isBigEndian()) { 3445 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3446 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3447 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3448 } 3449 3450 uint64_t PtrOff = ShAmt / 8; 3451 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3452 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3453 PtrType, LN0->getBasePtr(), 3454 DAG.getConstant(PtrOff, PtrType)); 3455 AddToWorkList(NewPtr.getNode()); 3456 3457 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3458 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3459 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3460 LN0->isVolatile(), NewAlign) 3461 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3462 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3463 EVT, LN0->isVolatile(), NewAlign); 3464 3465 // Replace the old load's chain with the new load's chain. 3466 WorkListRemover DeadNodes(*this); 3467 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3468 &DeadNodes); 3469 3470 // Return the new loaded value. 3471 return Load; 3472 } 3473 3474 return SDValue(); 3475} 3476 3477SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3478 SDValue N0 = N->getOperand(0); 3479 SDValue N1 = N->getOperand(1); 3480 MVT VT = N->getValueType(0); 3481 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3482 unsigned VTBits = VT.getSizeInBits(); 3483 unsigned EVTBits = EVT.getSizeInBits(); 3484 3485 // fold (sext_in_reg c1) -> c1 3486 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3487 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3488 3489 // If the input is already sign extended, just drop the extension. 3490 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3491 return N0; 3492 3493 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3494 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3495 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3496 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3497 N0.getOperand(0), N1); 3498 } 3499 3500 // fold (sext_in_reg (sext x)) -> (sext x) 3501 // fold (sext_in_reg (aext x)) -> (sext x) 3502 // if x is small enough. 3503 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3504 SDValue N00 = N0.getOperand(0); 3505 if (N00.getValueType().getSizeInBits() < EVTBits) 3506 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3507 } 3508 3509 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3510 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3511 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3512 3513 // fold operands of sext_in_reg based on knowledge that the top bits are not 3514 // demanded. 3515 if (SimplifyDemandedBits(SDValue(N, 0))) 3516 return SDValue(N, 0); 3517 3518 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3519 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3520 SDValue NarrowLoad = ReduceLoadWidth(N); 3521 if (NarrowLoad.getNode()) 3522 return NarrowLoad; 3523 3524 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3525 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3526 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3527 if (N0.getOpcode() == ISD::SRL) { 3528 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3529 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3530 // We can turn this into an SRA iff the input to the SRL is already sign 3531 // extended enough. 3532 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3533 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3534 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3535 N0.getOperand(0), N0.getOperand(1)); 3536 } 3537 } 3538 3539 // fold (sext_inreg (extload x)) -> (sextload x) 3540 if (ISD::isEXTLoad(N0.getNode()) && 3541 ISD::isUNINDEXEDLoad(N0.getNode()) && 3542 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3543 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3544 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3545 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3546 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3547 LN0->getChain(), 3548 LN0->getBasePtr(), LN0->getSrcValue(), 3549 LN0->getSrcValueOffset(), EVT, 3550 LN0->isVolatile(), LN0->getAlignment()); 3551 CombineTo(N, ExtLoad); 3552 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3553 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3554 } 3555 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3556 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3557 N0.hasOneUse() && 3558 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3559 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3560 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3561 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3562 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3563 LN0->getChain(), 3564 LN0->getBasePtr(), LN0->getSrcValue(), 3565 LN0->getSrcValueOffset(), EVT, 3566 LN0->isVolatile(), LN0->getAlignment()); 3567 CombineTo(N, ExtLoad); 3568 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3569 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3570 } 3571 return SDValue(); 3572} 3573 3574SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3575 SDValue N0 = N->getOperand(0); 3576 MVT VT = N->getValueType(0); 3577 3578 // noop truncate 3579 if (N0.getValueType() == N->getValueType(0)) 3580 return N0; 3581 // fold (truncate c1) -> c1 3582 if (isa<ConstantSDNode>(N0)) 3583 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3584 // fold (truncate (truncate x)) -> (truncate x) 3585 if (N0.getOpcode() == ISD::TRUNCATE) 3586 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3587 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3588 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3589 N0.getOpcode() == ISD::ANY_EXTEND) { 3590 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3591 // if the source is smaller than the dest, we still need an extend 3592 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3593 N0.getOperand(0)); 3594 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3595 // if the source is larger than the dest, than we just need the truncate 3596 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3597 else 3598 // if the source and dest are the same type, we can drop both the extend 3599 // and the truncate 3600 return N0.getOperand(0); 3601 } 3602 3603 // See if we can simplify the input to this truncate through knowledge that 3604 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3605 // -> trunc y 3606 SDValue Shorter = 3607 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3608 VT.getSizeInBits())); 3609 if (Shorter.getNode()) 3610 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3611 3612 // fold (truncate (load x)) -> (smaller load x) 3613 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3614 return ReduceLoadWidth(N); 3615} 3616 3617static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3618 SDValue Elt = N->getOperand(i); 3619 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3620 return Elt.getNode(); 3621 return Elt.getOperand(Elt.getResNo()).getNode(); 3622} 3623 3624/// CombineConsecutiveLoads - build_pair (load, load) -> load 3625/// if load locations are consecutive. 3626SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3627 assert(N->getOpcode() == ISD::BUILD_PAIR); 3628 3629 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3630 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3631 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3632 return SDValue(); 3633 MVT LD1VT = LD1->getValueType(0); 3634 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3635 3636 if (ISD::isNON_EXTLoad(LD2) && 3637 LD2->hasOneUse() && 3638 // If both are volatile this would reduce the number of volatile loads. 3639 // If one is volatile it might be ok, but play conservative and bail out. 3640 !LD1->isVolatile() && 3641 !LD2->isVolatile() && 3642 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3643 unsigned Align = LD1->getAlignment(); 3644 unsigned NewAlign = TLI.getTargetData()-> 3645 getABITypeAlignment(VT.getTypeForMVT()); 3646 3647 if (NewAlign <= Align && 3648 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3649 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3650 LD1->getBasePtr(), LD1->getSrcValue(), 3651 LD1->getSrcValueOffset(), false, Align); 3652 } 3653 3654 return SDValue(); 3655} 3656 3657SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3658 SDValue N0 = N->getOperand(0); 3659 MVT VT = N->getValueType(0); 3660 3661 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3662 // Only do this before legalize, since afterward the target may be depending 3663 // on the bitconvert. 3664 // First check to see if this is all constant. 3665 if (!LegalTypes && 3666 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3667 VT.isVector()) { 3668 bool isSimple = true; 3669 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3670 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3671 N0.getOperand(i).getOpcode() != ISD::Constant && 3672 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3673 isSimple = false; 3674 break; 3675 } 3676 3677 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3678 assert(!DestEltVT.isVector() && 3679 "Element type of vector ValueType must not be vector!"); 3680 if (isSimple) 3681 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3682 } 3683 3684 // If the input is a constant, let getNode fold it. 3685 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3686 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3687 if (Res.getNode() != N) return Res; 3688 } 3689 3690 // (conv (conv x, t1), t2) -> (conv x, t2) 3691 if (N0.getOpcode() == ISD::BIT_CONVERT) 3692 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3693 N0.getOperand(0)); 3694 3695 // fold (conv (load x)) -> (load (conv*)x) 3696 // If the resultant load doesn't need a higher alignment than the original! 3697 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3698 // Do not change the width of a volatile load. 3699 !cast<LoadSDNode>(N0)->isVolatile() && 3700 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3701 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3702 unsigned Align = TLI.getTargetData()-> 3703 getABITypeAlignment(VT.getTypeForMVT()); 3704 unsigned OrigAlign = LN0->getAlignment(); 3705 3706 if (Align <= OrigAlign) { 3707 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3708 LN0->getBasePtr(), 3709 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3710 LN0->isVolatile(), OrigAlign); 3711 AddToWorkList(N); 3712 CombineTo(N0.getNode(), 3713 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3714 N0.getValueType(), Load), 3715 Load.getValue(1)); 3716 return Load; 3717 } 3718 } 3719 3720 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3721 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3722 // This often reduces constant pool loads. 3723 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3724 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3725 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3726 N0.getOperand(0)); 3727 AddToWorkList(NewConv.getNode()); 3728 3729 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3730 if (N0.getOpcode() == ISD::FNEG) 3731 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3732 NewConv, DAG.getConstant(SignBit, VT)); 3733 assert(N0.getOpcode() == ISD::FABS); 3734 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3735 NewConv, DAG.getConstant(~SignBit, VT)); 3736 } 3737 3738 // fold (bitconvert (fcopysign cst, x)) -> 3739 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3740 // Note that we don't handle (copysign x, cst) because this can always be 3741 // folded to an fneg or fabs. 3742 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3743 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3744 VT.isInteger() && !VT.isVector()) { 3745 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3746 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3747 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3748 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3749 IntXVT, N0.getOperand(1)); 3750 AddToWorkList(X.getNode()); 3751 3752 // If X has a different width than the result/lhs, sext it or truncate it. 3753 unsigned VTWidth = VT.getSizeInBits(); 3754 if (OrigXWidth < VTWidth) { 3755 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3756 AddToWorkList(X.getNode()); 3757 } else if (OrigXWidth > VTWidth) { 3758 // To get the sign bit in the right place, we have to shift it right 3759 // before truncating. 3760 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3761 X.getValueType(), X, 3762 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3763 AddToWorkList(X.getNode()); 3764 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3765 AddToWorkList(X.getNode()); 3766 } 3767 3768 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3769 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3770 X, DAG.getConstant(SignBit, VT)); 3771 AddToWorkList(X.getNode()); 3772 3773 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3774 VT, N0.getOperand(0)); 3775 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3776 Cst, DAG.getConstant(~SignBit, VT)); 3777 AddToWorkList(Cst.getNode()); 3778 3779 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3780 } 3781 } 3782 3783 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3784 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3785 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3786 if (CombineLD.getNode()) 3787 return CombineLD; 3788 } 3789 3790 return SDValue(); 3791} 3792 3793SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3794 MVT VT = N->getValueType(0); 3795 return CombineConsecutiveLoads(N, VT); 3796} 3797 3798/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3799/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3800/// destination element value type. 3801SDValue DAGCombiner:: 3802ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3803 MVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3804 3805 // If this is already the right type, we're done. 3806 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3807 3808 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3809 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3810 3811 // If this is a conversion of N elements of one type to N elements of another 3812 // type, convert each element. This handles FP<->INT cases. 3813 if (SrcBitSize == DstBitSize) { 3814 SmallVector<SDValue, 8> Ops; 3815 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3816 SDValue Op = BV->getOperand(i); 3817 // If the vector element type is not legal, the BUILD_VECTOR operands 3818 // are promoted and implicitly truncated. Make that explicit here. 3819 if (Op.getValueType() != SrcEltVT) 3820 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3821 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3822 DstEltVT, Op)); 3823 AddToWorkList(Ops.back().getNode()); 3824 } 3825 MVT VT = MVT::getVectorVT(DstEltVT, 3826 BV->getValueType(0).getVectorNumElements()); 3827 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3828 &Ops[0], Ops.size()); 3829 } 3830 3831 // Otherwise, we're growing or shrinking the elements. To avoid having to 3832 // handle annoying details of growing/shrinking FP values, we convert them to 3833 // int first. 3834 if (SrcEltVT.isFloatingPoint()) { 3835 // Convert the input float vector to a int vector where the elements are the 3836 // same sizes. 3837 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3838 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3839 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3840 SrcEltVT = IntVT; 3841 } 3842 3843 // Now we know the input is an integer vector. If the output is a FP type, 3844 // convert to integer first, then to FP of the right size. 3845 if (DstEltVT.isFloatingPoint()) { 3846 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3847 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3848 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3849 3850 // Next, convert to FP elements of the same size. 3851 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3852 } 3853 3854 // Okay, we know the src/dst types are both integers of differing types. 3855 // Handling growing first. 3856 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3857 if (SrcBitSize < DstBitSize) { 3858 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3859 3860 SmallVector<SDValue, 8> Ops; 3861 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3862 i += NumInputsPerOutput) { 3863 bool isLE = TLI.isLittleEndian(); 3864 APInt NewBits = APInt(DstBitSize, 0); 3865 bool EltIsUndef = true; 3866 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3867 // Shift the previously computed bits over. 3868 NewBits <<= SrcBitSize; 3869 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3870 if (Op.getOpcode() == ISD::UNDEF) continue; 3871 EltIsUndef = false; 3872 3873 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 3874 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 3875 } 3876 3877 if (EltIsUndef) 3878 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3879 else 3880 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3881 } 3882 3883 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3884 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3885 &Ops[0], Ops.size()); 3886 } 3887 3888 // Finally, this must be the case where we are shrinking elements: each input 3889 // turns into multiple outputs. 3890 bool isS2V = ISD::isScalarToVector(BV); 3891 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3892 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3893 SmallVector<SDValue, 8> Ops; 3894 3895 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3896 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3897 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3898 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3899 continue; 3900 } 3901 3902 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 3903 getAPIntValue()).zextOrTrunc(SrcBitSize); 3904 3905 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3906 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3907 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3908 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3909 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3910 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3911 Ops[0]); 3912 OpVal = OpVal.lshr(DstBitSize); 3913 } 3914 3915 // For big endian targets, swap the order of the pieces of each element. 3916 if (TLI.isBigEndian()) 3917 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3918 } 3919 3920 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3921 &Ops[0], Ops.size()); 3922} 3923 3924SDValue DAGCombiner::visitFADD(SDNode *N) { 3925 SDValue N0 = N->getOperand(0); 3926 SDValue N1 = N->getOperand(1); 3927 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3928 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3929 MVT VT = N->getValueType(0); 3930 3931 // fold vector ops 3932 if (VT.isVector()) { 3933 SDValue FoldedVOp = SimplifyVBinOp(N); 3934 if (FoldedVOp.getNode()) return FoldedVOp; 3935 } 3936 3937 // fold (fadd c1, c2) -> (fadd c1, c2) 3938 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3939 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3940 // canonicalize constant to RHS 3941 if (N0CFP && !N1CFP) 3942 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3943 // fold (fadd A, 0) -> A 3944 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3945 return N0; 3946 // fold (fadd A, (fneg B)) -> (fsub A, B) 3947 if (isNegatibleForFree(N1, LegalOperations) == 2) 3948 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3949 GetNegatedExpression(N1, DAG, LegalOperations)); 3950 // fold (fadd (fneg A), B) -> (fsub B, A) 3951 if (isNegatibleForFree(N0, LegalOperations) == 2) 3952 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3953 GetNegatedExpression(N0, DAG, LegalOperations)); 3954 3955 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3956 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3957 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3958 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3959 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3960 N0.getOperand(1), N1)); 3961 3962 return SDValue(); 3963} 3964 3965SDValue DAGCombiner::visitFSUB(SDNode *N) { 3966 SDValue N0 = N->getOperand(0); 3967 SDValue N1 = N->getOperand(1); 3968 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3969 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3970 MVT VT = N->getValueType(0); 3971 3972 // fold vector ops 3973 if (VT.isVector()) { 3974 SDValue FoldedVOp = SimplifyVBinOp(N); 3975 if (FoldedVOp.getNode()) return FoldedVOp; 3976 } 3977 3978 // fold (fsub c1, c2) -> c1-c2 3979 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3980 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 3981 // fold (fsub A, 0) -> A 3982 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3983 return N0; 3984 // fold (fsub 0, B) -> -B 3985 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3986 if (isNegatibleForFree(N1, LegalOperations)) 3987 return GetNegatedExpression(N1, DAG, LegalOperations); 3988 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3989 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 3990 } 3991 // fold (fsub A, (fneg B)) -> (fadd A, B) 3992 if (isNegatibleForFree(N1, LegalOperations)) 3993 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 3994 GetNegatedExpression(N1, DAG, LegalOperations)); 3995 3996 return SDValue(); 3997} 3998 3999SDValue DAGCombiner::visitFMUL(SDNode *N) { 4000 SDValue N0 = N->getOperand(0); 4001 SDValue N1 = N->getOperand(1); 4002 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4003 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4004 MVT VT = N->getValueType(0); 4005 4006 // fold vector ops 4007 if (VT.isVector()) { 4008 SDValue FoldedVOp = SimplifyVBinOp(N); 4009 if (FoldedVOp.getNode()) return FoldedVOp; 4010 } 4011 4012 // fold (fmul c1, c2) -> c1*c2 4013 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4014 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4015 // canonicalize constant to RHS 4016 if (N0CFP && !N1CFP) 4017 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4018 // fold (fmul A, 0) -> 0 4019 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4020 return N1; 4021 // fold (fmul A, 0) -> 0, vector edition. 4022 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4023 return N1; 4024 // fold (fmul X, 2.0) -> (fadd X, X) 4025 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4026 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4027 // fold (fmul X, (fneg 1.0)) -> (fneg X) 4028 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4029 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4030 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4031 4032 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4033 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4034 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4035 // Both can be negated for free, check to see if at least one is cheaper 4036 // negated. 4037 if (LHSNeg == 2 || RHSNeg == 2) 4038 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4039 GetNegatedExpression(N0, DAG, LegalOperations), 4040 GetNegatedExpression(N1, DAG, LegalOperations)); 4041 } 4042 } 4043 4044 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4045 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4046 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4047 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4048 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4049 N0.getOperand(1), N1)); 4050 4051 return SDValue(); 4052} 4053 4054SDValue DAGCombiner::visitFDIV(SDNode *N) { 4055 SDValue N0 = N->getOperand(0); 4056 SDValue N1 = N->getOperand(1); 4057 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4058 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4059 MVT VT = N->getValueType(0); 4060 4061 // fold vector ops 4062 if (VT.isVector()) { 4063 SDValue FoldedVOp = SimplifyVBinOp(N); 4064 if (FoldedVOp.getNode()) return FoldedVOp; 4065 } 4066 4067 // fold (fdiv c1, c2) -> c1/c2 4068 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4069 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4070 4071 4072 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4073 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4074 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4075 // Both can be negated for free, check to see if at least one is cheaper 4076 // negated. 4077 if (LHSNeg == 2 || RHSNeg == 2) 4078 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4079 GetNegatedExpression(N0, DAG, LegalOperations), 4080 GetNegatedExpression(N1, DAG, LegalOperations)); 4081 } 4082 } 4083 4084 return SDValue(); 4085} 4086 4087SDValue DAGCombiner::visitFREM(SDNode *N) { 4088 SDValue N0 = N->getOperand(0); 4089 SDValue N1 = N->getOperand(1); 4090 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4091 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4092 MVT VT = N->getValueType(0); 4093 4094 // fold (frem c1, c2) -> fmod(c1,c2) 4095 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4096 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4097 4098 return SDValue(); 4099} 4100 4101SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4102 SDValue N0 = N->getOperand(0); 4103 SDValue N1 = N->getOperand(1); 4104 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4105 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4106 MVT VT = N->getValueType(0); 4107 4108 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4109 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4110 4111 if (N1CFP) { 4112 const APFloat& V = N1CFP->getValueAPF(); 4113 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4114 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4115 if (!V.isNegative()) { 4116 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4117 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4118 } else { 4119 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4120 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4121 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4122 } 4123 } 4124 4125 // copysign(fabs(x), y) -> copysign(x, y) 4126 // copysign(fneg(x), y) -> copysign(x, y) 4127 // copysign(copysign(x,z), y) -> copysign(x, y) 4128 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4129 N0.getOpcode() == ISD::FCOPYSIGN) 4130 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4131 N0.getOperand(0), N1); 4132 4133 // copysign(x, abs(y)) -> abs(x) 4134 if (N1.getOpcode() == ISD::FABS) 4135 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4136 4137 // copysign(x, copysign(y,z)) -> copysign(x, z) 4138 if (N1.getOpcode() == ISD::FCOPYSIGN) 4139 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4140 N0, N1.getOperand(1)); 4141 4142 // copysign(x, fp_extend(y)) -> copysign(x, y) 4143 // copysign(x, fp_round(y)) -> copysign(x, y) 4144 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4145 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4146 N0, N1.getOperand(0)); 4147 4148 return SDValue(); 4149} 4150 4151SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4152 SDValue N0 = N->getOperand(0); 4153 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4154 MVT VT = N->getValueType(0); 4155 MVT OpVT = N0.getValueType(); 4156 4157 // fold (sint_to_fp c1) -> c1fp 4158 if (N0C && OpVT != MVT::ppcf128) 4159 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4160 4161 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4162 // but UINT_TO_FP is legal on this target, try to convert. 4163 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4164 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4165 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4166 if (DAG.SignBitIsZero(N0)) 4167 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4168 } 4169 4170 return SDValue(); 4171} 4172 4173SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4174 SDValue N0 = N->getOperand(0); 4175 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4176 MVT VT = N->getValueType(0); 4177 MVT OpVT = N0.getValueType(); 4178 4179 // fold (uint_to_fp c1) -> c1fp 4180 if (N0C && OpVT != MVT::ppcf128) 4181 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4182 4183 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4184 // but SINT_TO_FP is legal on this target, try to convert. 4185 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4186 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4187 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4188 if (DAG.SignBitIsZero(N0)) 4189 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4190 } 4191 4192 return SDValue(); 4193} 4194 4195SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4196 SDValue N0 = N->getOperand(0); 4197 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4198 MVT VT = N->getValueType(0); 4199 4200 // fold (fp_to_sint c1fp) -> c1 4201 if (N0CFP) 4202 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4203 4204 return SDValue(); 4205} 4206 4207SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4208 SDValue N0 = N->getOperand(0); 4209 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4210 MVT VT = N->getValueType(0); 4211 4212 // fold (fp_to_uint c1fp) -> c1 4213 if (N0CFP && VT != MVT::ppcf128) 4214 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4215 4216 return SDValue(); 4217} 4218 4219SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4220 SDValue N0 = N->getOperand(0); 4221 SDValue N1 = N->getOperand(1); 4222 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4223 MVT VT = N->getValueType(0); 4224 4225 // fold (fp_round c1fp) -> c1fp 4226 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4227 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4228 4229 // fold (fp_round (fp_extend x)) -> x 4230 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4231 return N0.getOperand(0); 4232 4233 // fold (fp_round (fp_round x)) -> (fp_round x) 4234 if (N0.getOpcode() == ISD::FP_ROUND) { 4235 // This is a value preserving truncation if both round's are. 4236 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4237 N0.getNode()->getConstantOperandVal(1) == 1; 4238 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4239 DAG.getIntPtrConstant(IsTrunc)); 4240 } 4241 4242 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4243 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4244 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4245 N0.getOperand(0), N1); 4246 AddToWorkList(Tmp.getNode()); 4247 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4248 Tmp, N0.getOperand(1)); 4249 } 4250 4251 return SDValue(); 4252} 4253 4254SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4255 SDValue N0 = N->getOperand(0); 4256 MVT VT = N->getValueType(0); 4257 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4258 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4259 4260 // fold (fp_round_inreg c1fp) -> c1fp 4261 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4262 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4263 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4264 } 4265 4266 return SDValue(); 4267} 4268 4269SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4270 SDValue N0 = N->getOperand(0); 4271 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4272 MVT VT = N->getValueType(0); 4273 4274 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4275 if (N->hasOneUse() && 4276 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4277 return SDValue(); 4278 4279 // fold (fp_extend c1fp) -> c1fp 4280 if (N0CFP && VT != MVT::ppcf128) 4281 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4282 4283 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4284 // value of X. 4285 if (N0.getOpcode() == ISD::FP_ROUND 4286 && N0.getNode()->getConstantOperandVal(1) == 1) { 4287 SDValue In = N0.getOperand(0); 4288 if (In.getValueType() == VT) return In; 4289 if (VT.bitsLT(In.getValueType())) 4290 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4291 In, N0.getOperand(1)); 4292 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4293 } 4294 4295 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4296 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4297 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4298 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4299 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4300 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4301 LN0->getChain(), 4302 LN0->getBasePtr(), LN0->getSrcValue(), 4303 LN0->getSrcValueOffset(), 4304 N0.getValueType(), 4305 LN0->isVolatile(), LN0->getAlignment()); 4306 CombineTo(N, ExtLoad); 4307 CombineTo(N0.getNode(), 4308 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4309 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4310 ExtLoad.getValue(1)); 4311 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4312 } 4313 4314 return SDValue(); 4315} 4316 4317SDValue DAGCombiner::visitFNEG(SDNode *N) { 4318 SDValue N0 = N->getOperand(0); 4319 4320 if (isNegatibleForFree(N0, LegalOperations)) 4321 return GetNegatedExpression(N0, DAG, LegalOperations); 4322 4323 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4324 // constant pool values. 4325 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4326 N0.getOperand(0).getValueType().isInteger() && 4327 !N0.getOperand(0).getValueType().isVector()) { 4328 SDValue Int = N0.getOperand(0); 4329 MVT IntVT = Int.getValueType(); 4330 if (IntVT.isInteger() && !IntVT.isVector()) { 4331 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4332 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4333 AddToWorkList(Int.getNode()); 4334 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4335 N->getValueType(0), Int); 4336 } 4337 } 4338 4339 return SDValue(); 4340} 4341 4342SDValue DAGCombiner::visitFABS(SDNode *N) { 4343 SDValue N0 = N->getOperand(0); 4344 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4345 MVT VT = N->getValueType(0); 4346 4347 // fold (fabs c1) -> fabs(c1) 4348 if (N0CFP && VT != MVT::ppcf128) 4349 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4350 // fold (fabs (fabs x)) -> (fabs x) 4351 if (N0.getOpcode() == ISD::FABS) 4352 return N->getOperand(0); 4353 // fold (fabs (fneg x)) -> (fabs x) 4354 // fold (fabs (fcopysign x, y)) -> (fabs x) 4355 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4356 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4357 4358 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4359 // constant pool values. 4360 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4361 N0.getOperand(0).getValueType().isInteger() && 4362 !N0.getOperand(0).getValueType().isVector()) { 4363 SDValue Int = N0.getOperand(0); 4364 MVT IntVT = Int.getValueType(); 4365 if (IntVT.isInteger() && !IntVT.isVector()) { 4366 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4367 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4368 AddToWorkList(Int.getNode()); 4369 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4370 N->getValueType(0), Int); 4371 } 4372 } 4373 4374 return SDValue(); 4375} 4376 4377SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4378 SDValue Chain = N->getOperand(0); 4379 SDValue N1 = N->getOperand(1); 4380 SDValue N2 = N->getOperand(2); 4381 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4382 4383 // never taken branch, fold to chain 4384 if (N1C && N1C->isNullValue()) 4385 return Chain; 4386 // unconditional branch 4387 if (N1C && N1C->getAPIntValue() == 1) 4388 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4389 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4390 // on the target. 4391 if (N1.getOpcode() == ISD::SETCC && 4392 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4393 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4394 Chain, N1.getOperand(2), 4395 N1.getOperand(0), N1.getOperand(1), N2); 4396 } 4397 4398 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4399 // Match this pattern so that we can generate simpler code: 4400 // 4401 // %a = ... 4402 // %b = and i32 %a, 2 4403 // %c = srl i32 %b, 1 4404 // brcond i32 %c ... 4405 // 4406 // into 4407 // 4408 // %a = ... 4409 // %b = and %a, 2 4410 // %c = setcc eq %b, 0 4411 // brcond %c ... 4412 // 4413 // This applies only when the AND constant value has one bit set and the 4414 // SRL constant is equal to the log2 of the AND constant. The back-end is 4415 // smart enough to convert the result into a TEST/JMP sequence. 4416 SDValue Op0 = N1.getOperand(0); 4417 SDValue Op1 = N1.getOperand(1); 4418 4419 if (Op0.getOpcode() == ISD::AND && 4420 Op0.hasOneUse() && 4421 Op1.getOpcode() == ISD::Constant) { 4422 SDValue AndOp0 = Op0.getOperand(0); 4423 SDValue AndOp1 = Op0.getOperand(1); 4424 4425 if (AndOp1.getOpcode() == ISD::Constant) { 4426 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4427 4428 if (AndConst.isPowerOf2() && 4429 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4430 SDValue SetCC = 4431 DAG.getSetCC(N->getDebugLoc(), 4432 TLI.getSetCCResultType(Op0.getValueType()), 4433 Op0, DAG.getConstant(0, Op0.getValueType()), 4434 ISD::SETNE); 4435 4436 // Replace the uses of SRL with SETCC 4437 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4438 removeFromWorkList(N1.getNode()); 4439 DAG.DeleteNode(N1.getNode()); 4440 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4441 MVT::Other, Chain, SetCC, N2); 4442 } 4443 } 4444 } 4445 } 4446 4447 return SDValue(); 4448} 4449 4450// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4451// 4452SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4453 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4454 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4455 4456 // Use SimplifySetCC to simplify SETCC's. 4457 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4458 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4459 false); 4460 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4461 4462 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4463 4464 // fold br_cc true, dest -> br dest (unconditional branch) 4465 if (SCCC && !SCCC->isNullValue()) 4466 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4467 N->getOperand(0), N->getOperand(4)); 4468 // fold br_cc false, dest -> unconditional fall through 4469 if (SCCC && SCCC->isNullValue()) 4470 return N->getOperand(0); 4471 4472 // fold to a simpler setcc 4473 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4474 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4475 N->getOperand(0), Simp.getOperand(2), 4476 Simp.getOperand(0), Simp.getOperand(1), 4477 N->getOperand(4)); 4478 4479 return SDValue(); 4480} 4481 4482/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4483/// pre-indexed load / store when the base pointer is an add or subtract 4484/// and it has other uses besides the load / store. After the 4485/// transformation, the new indexed load / store has effectively folded 4486/// the add / subtract in and all of its other uses are redirected to the 4487/// new load / store. 4488bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4489 if (!LegalOperations) 4490 return false; 4491 4492 bool isLoad = true; 4493 SDValue Ptr; 4494 MVT VT; 4495 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4496 if (LD->isIndexed()) 4497 return false; 4498 VT = LD->getMemoryVT(); 4499 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4500 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4501 return false; 4502 Ptr = LD->getBasePtr(); 4503 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4504 if (ST->isIndexed()) 4505 return false; 4506 VT = ST->getMemoryVT(); 4507 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4508 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4509 return false; 4510 Ptr = ST->getBasePtr(); 4511 isLoad = false; 4512 } else { 4513 return false; 4514 } 4515 4516 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4517 // out. There is no reason to make this a preinc/predec. 4518 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4519 Ptr.getNode()->hasOneUse()) 4520 return false; 4521 4522 // Ask the target to do addressing mode selection. 4523 SDValue BasePtr; 4524 SDValue Offset; 4525 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4526 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4527 return false; 4528 // Don't create a indexed load / store with zero offset. 4529 if (isa<ConstantSDNode>(Offset) && 4530 cast<ConstantSDNode>(Offset)->isNullValue()) 4531 return false; 4532 4533 // Try turning it into a pre-indexed load / store except when: 4534 // 1) The new base ptr is a frame index. 4535 // 2) If N is a store and the new base ptr is either the same as or is a 4536 // predecessor of the value being stored. 4537 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4538 // that would create a cycle. 4539 // 4) All uses are load / store ops that use it as old base ptr. 4540 4541 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4542 // (plus the implicit offset) to a register to preinc anyway. 4543 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4544 return false; 4545 4546 // Check #2. 4547 if (!isLoad) { 4548 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4549 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4550 return false; 4551 } 4552 4553 // Now check for #3 and #4. 4554 bool RealUse = false; 4555 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4556 E = Ptr.getNode()->use_end(); I != E; ++I) { 4557 SDNode *Use = *I; 4558 if (Use == N) 4559 continue; 4560 if (Use->isPredecessorOf(N)) 4561 return false; 4562 4563 if (!((Use->getOpcode() == ISD::LOAD && 4564 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4565 (Use->getOpcode() == ISD::STORE && 4566 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4567 RealUse = true; 4568 } 4569 4570 if (!RealUse) 4571 return false; 4572 4573 SDValue Result; 4574 if (isLoad) 4575 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4576 BasePtr, Offset, AM); 4577 else 4578 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4579 BasePtr, Offset, AM); 4580 ++PreIndexedNodes; 4581 ++NodesCombined; 4582 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4583 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4584 DOUT << '\n'; 4585 WorkListRemover DeadNodes(*this); 4586 if (isLoad) { 4587 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4588 &DeadNodes); 4589 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4590 &DeadNodes); 4591 } else { 4592 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4593 &DeadNodes); 4594 } 4595 4596 // Finally, since the node is now dead, remove it from the graph. 4597 DAG.DeleteNode(N); 4598 4599 // Replace the uses of Ptr with uses of the updated base value. 4600 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4601 &DeadNodes); 4602 removeFromWorkList(Ptr.getNode()); 4603 DAG.DeleteNode(Ptr.getNode()); 4604 4605 return true; 4606} 4607 4608/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4609/// add / sub of the base pointer node into a post-indexed load / store. 4610/// The transformation folded the add / subtract into the new indexed 4611/// load / store effectively and all of its uses are redirected to the 4612/// new load / store. 4613bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4614 if (!LegalOperations) 4615 return false; 4616 4617 bool isLoad = true; 4618 SDValue Ptr; 4619 MVT VT; 4620 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4621 if (LD->isIndexed()) 4622 return false; 4623 VT = LD->getMemoryVT(); 4624 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4625 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4626 return false; 4627 Ptr = LD->getBasePtr(); 4628 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4629 if (ST->isIndexed()) 4630 return false; 4631 VT = ST->getMemoryVT(); 4632 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4633 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4634 return false; 4635 Ptr = ST->getBasePtr(); 4636 isLoad = false; 4637 } else { 4638 return false; 4639 } 4640 4641 if (Ptr.getNode()->hasOneUse()) 4642 return false; 4643 4644 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4645 E = Ptr.getNode()->use_end(); I != E; ++I) { 4646 SDNode *Op = *I; 4647 if (Op == N || 4648 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4649 continue; 4650 4651 SDValue BasePtr; 4652 SDValue Offset; 4653 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4654 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4655 if (Ptr == Offset) 4656 std::swap(BasePtr, Offset); 4657 if (Ptr != BasePtr) 4658 continue; 4659 // Don't create a indexed load / store with zero offset. 4660 if (isa<ConstantSDNode>(Offset) && 4661 cast<ConstantSDNode>(Offset)->isNullValue()) 4662 continue; 4663 4664 // Try turning it into a post-indexed load / store except when 4665 // 1) All uses are load / store ops that use it as base ptr. 4666 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4667 // nor a successor of N. Otherwise, if Op is folded that would 4668 // create a cycle. 4669 4670 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4671 continue; 4672 4673 // Check for #1. 4674 bool TryNext = false; 4675 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4676 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4677 SDNode *Use = *II; 4678 if (Use == Ptr.getNode()) 4679 continue; 4680 4681 // If all the uses are load / store addresses, then don't do the 4682 // transformation. 4683 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4684 bool RealUse = false; 4685 for (SDNode::use_iterator III = Use->use_begin(), 4686 EEE = Use->use_end(); III != EEE; ++III) { 4687 SDNode *UseUse = *III; 4688 if (!((UseUse->getOpcode() == ISD::LOAD && 4689 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4690 (UseUse->getOpcode() == ISD::STORE && 4691 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4692 RealUse = true; 4693 } 4694 4695 if (!RealUse) { 4696 TryNext = true; 4697 break; 4698 } 4699 } 4700 } 4701 4702 if (TryNext) 4703 continue; 4704 4705 // Check for #2 4706 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4707 SDValue Result = isLoad 4708 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4709 BasePtr, Offset, AM) 4710 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4711 BasePtr, Offset, AM); 4712 ++PostIndexedNodes; 4713 ++NodesCombined; 4714 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4715 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4716 DOUT << '\n'; 4717 WorkListRemover DeadNodes(*this); 4718 if (isLoad) { 4719 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4720 &DeadNodes); 4721 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4722 &DeadNodes); 4723 } else { 4724 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4725 &DeadNodes); 4726 } 4727 4728 // Finally, since the node is now dead, remove it from the graph. 4729 DAG.DeleteNode(N); 4730 4731 // Replace the uses of Use with uses of the updated base value. 4732 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4733 Result.getValue(isLoad ? 1 : 0), 4734 &DeadNodes); 4735 removeFromWorkList(Op); 4736 DAG.DeleteNode(Op); 4737 return true; 4738 } 4739 } 4740 } 4741 4742 return false; 4743} 4744 4745/// InferAlignment - If we can infer some alignment information from this 4746/// pointer, return it. 4747static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4748 // If this is a direct reference to a stack slot, use information about the 4749 // stack slot's alignment. 4750 int FrameIdx = 1 << 31; 4751 int64_t FrameOffset = 0; 4752 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4753 FrameIdx = FI->getIndex(); 4754 } else if (Ptr.getOpcode() == ISD::ADD && 4755 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4756 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4757 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4758 FrameOffset = Ptr.getConstantOperandVal(1); 4759 } 4760 4761 if (FrameIdx != (1 << 31)) { 4762 // FIXME: Handle FI+CST. 4763 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4764 if (MFI.isFixedObjectIndex(FrameIdx)) { 4765 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4766 4767 // The alignment of the frame index can be determined from its offset from 4768 // the incoming frame position. If the frame object is at offset 32 and 4769 // the stack is guaranteed to be 16-byte aligned, then we know that the 4770 // object is 16-byte aligned. 4771 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4772 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4773 4774 // Finally, the frame object itself may have a known alignment. Factor 4775 // the alignment + offset into a new alignment. For example, if we know 4776 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4777 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4778 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4779 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4780 FrameOffset); 4781 return std::max(Align, FIInfoAlign); 4782 } 4783 } 4784 4785 return 0; 4786} 4787 4788SDValue DAGCombiner::visitLOAD(SDNode *N) { 4789 LoadSDNode *LD = cast<LoadSDNode>(N); 4790 SDValue Chain = LD->getChain(); 4791 SDValue Ptr = LD->getBasePtr(); 4792 4793 // Try to infer better alignment information than the load already has. 4794 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4795 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4796 if (Align > LD->getAlignment()) 4797 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4798 LD->getValueType(0), 4799 Chain, Ptr, LD->getSrcValue(), 4800 LD->getSrcValueOffset(), LD->getMemoryVT(), 4801 LD->isVolatile(), Align); 4802 } 4803 } 4804 4805 // If load is not volatile and there are no uses of the loaded value (and 4806 // the updated indexed value in case of indexed loads), change uses of the 4807 // chain value into uses of the chain input (i.e. delete the dead load). 4808 if (!LD->isVolatile()) { 4809 if (N->getValueType(1) == MVT::Other) { 4810 // Unindexed loads. 4811 if (N->hasNUsesOfValue(0, 0)) { 4812 // It's not safe to use the two value CombineTo variant here. e.g. 4813 // v1, chain2 = load chain1, loc 4814 // v2, chain3 = load chain2, loc 4815 // v3 = add v2, c 4816 // Now we replace use of chain2 with chain1. This makes the second load 4817 // isomorphic to the one we are deleting, and thus makes this load live. 4818 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4819 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4820 DOUT << "\n"; 4821 WorkListRemover DeadNodes(*this); 4822 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4823 4824 if (N->use_empty()) { 4825 removeFromWorkList(N); 4826 DAG.DeleteNode(N); 4827 } 4828 4829 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4830 } 4831 } else { 4832 // Indexed loads. 4833 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4834 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4835 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4836 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4837 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4838 DOUT << " and 2 other values\n"; 4839 WorkListRemover DeadNodes(*this); 4840 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4841 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4842 DAG.getUNDEF(N->getValueType(1)), 4843 &DeadNodes); 4844 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4845 removeFromWorkList(N); 4846 DAG.DeleteNode(N); 4847 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4848 } 4849 } 4850 } 4851 4852 // If this load is directly stored, replace the load value with the stored 4853 // value. 4854 // TODO: Handle store large -> read small portion. 4855 // TODO: Handle TRUNCSTORE/LOADEXT 4856 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4857 !LD->isVolatile()) { 4858 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4859 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4860 if (PrevST->getBasePtr() == Ptr && 4861 PrevST->getValue().getValueType() == N->getValueType(0)) 4862 return CombineTo(N, Chain.getOperand(1), Chain); 4863 } 4864 } 4865 4866 if (CombinerAA) { 4867 // Walk up chain skipping non-aliasing memory nodes. 4868 SDValue BetterChain = FindBetterChain(N, Chain); 4869 4870 // If there is a better chain. 4871 if (Chain != BetterChain) { 4872 SDValue ReplLoad; 4873 4874 // Replace the chain to void dependency. 4875 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4876 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4877 BetterChain, Ptr, 4878 LD->getSrcValue(), LD->getSrcValueOffset(), 4879 LD->isVolatile(), LD->getAlignment()); 4880 } else { 4881 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4882 LD->getValueType(0), 4883 BetterChain, Ptr, LD->getSrcValue(), 4884 LD->getSrcValueOffset(), 4885 LD->getMemoryVT(), 4886 LD->isVolatile(), 4887 LD->getAlignment()); 4888 } 4889 4890 // Create token factor to keep old chain connected. 4891 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4892 MVT::Other, Chain, ReplLoad.getValue(1)); 4893 4894 // Replace uses with load result and token factor. Don't add users 4895 // to work list. 4896 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4897 } 4898 } 4899 4900 // Try transforming N to an indexed load. 4901 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4902 return SDValue(N, 0); 4903 4904 return SDValue(); 4905} 4906 4907 4908/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 4909/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 4910/// of the loaded bits, try narrowing the load and store if it would end up 4911/// being a win for performance or code size. 4912SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 4913 StoreSDNode *ST = cast<StoreSDNode>(N); 4914 if (ST->isVolatile()) 4915 return SDValue(); 4916 4917 SDValue Chain = ST->getChain(); 4918 SDValue Value = ST->getValue(); 4919 SDValue Ptr = ST->getBasePtr(); 4920 MVT VT = Value.getValueType(); 4921 4922 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 4923 return SDValue(); 4924 4925 unsigned Opc = Value.getOpcode(); 4926 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 4927 Value.getOperand(1).getOpcode() != ISD::Constant) 4928 return SDValue(); 4929 4930 SDValue N0 = Value.getOperand(0); 4931 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 4932 LoadSDNode *LD = cast<LoadSDNode>(N0); 4933 if (LD->getBasePtr() != Ptr) 4934 return SDValue(); 4935 4936 // Find the type to narrow it the load / op / store to. 4937 SDValue N1 = Value.getOperand(1); 4938 unsigned BitWidth = N1.getValueSizeInBits(); 4939 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 4940 if (Opc == ISD::AND) 4941 Imm ^= APInt::getAllOnesValue(BitWidth); 4942 if (Imm == 0 || Imm.isAllOnesValue()) 4943 return SDValue(); 4944 unsigned ShAmt = Imm.countTrailingZeros(); 4945 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 4946 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 4947 MVT NewVT = MVT::getIntegerVT(NewBW); 4948 while (NewBW < BitWidth && 4949 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 4950 TLI.isNarrowingProfitable(VT, NewVT))) { 4951 NewBW = NextPowerOf2(NewBW); 4952 NewVT = MVT::getIntegerVT(NewBW); 4953 } 4954 if (NewBW >= BitWidth) 4955 return SDValue(); 4956 4957 // If the lsb changed does not start at the type bitwidth boundary, 4958 // start at the previous one. 4959 if (ShAmt % NewBW) 4960 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 4961 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 4962 if ((Imm & Mask) == Imm) { 4963 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 4964 if (Opc == ISD::AND) 4965 NewImm ^= APInt::getAllOnesValue(NewBW); 4966 uint64_t PtrOff = ShAmt / 8; 4967 // For big endian targets, we need to adjust the offset to the pointer to 4968 // load the correct bytes. 4969 if (TLI.isBigEndian()) 4970 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 4971 4972 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 4973 if (NewAlign < 4974 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT())) 4975 return SDValue(); 4976 4977 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 4978 Ptr.getValueType(), Ptr, 4979 DAG.getConstant(PtrOff, Ptr.getValueType())); 4980 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 4981 LD->getChain(), NewPtr, 4982 LD->getSrcValue(), LD->getSrcValueOffset(), 4983 LD->isVolatile(), NewAlign); 4984 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 4985 DAG.getConstant(NewImm, NewVT)); 4986 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 4987 NewVal, NewPtr, 4988 ST->getSrcValue(), ST->getSrcValueOffset(), 4989 false, NewAlign); 4990 4991 AddToWorkList(NewPtr.getNode()); 4992 AddToWorkList(NewLD.getNode()); 4993 AddToWorkList(NewVal.getNode()); 4994 WorkListRemover DeadNodes(*this); 4995 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 4996 &DeadNodes); 4997 ++OpsNarrowed; 4998 return NewST; 4999 } 5000 } 5001 5002 return SDValue(); 5003} 5004 5005SDValue DAGCombiner::visitSTORE(SDNode *N) { 5006 StoreSDNode *ST = cast<StoreSDNode>(N); 5007 SDValue Chain = ST->getChain(); 5008 SDValue Value = ST->getValue(); 5009 SDValue Ptr = ST->getBasePtr(); 5010 5011 // Try to infer better alignment information than the store already has. 5012 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5013 if (unsigned Align = InferAlignment(Ptr, DAG)) { 5014 if (Align > ST->getAlignment()) 5015 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5016 Ptr, ST->getSrcValue(), 5017 ST->getSrcValueOffset(), ST->getMemoryVT(), 5018 ST->isVolatile(), Align); 5019 } 5020 } 5021 5022 // If this is a store of a bit convert, store the input value if the 5023 // resultant store does not need a higher alignment than the original. 5024 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5025 ST->isUnindexed()) { 5026 unsigned OrigAlign = ST->getAlignment(); 5027 MVT SVT = Value.getOperand(0).getValueType(); 5028 unsigned Align = TLI.getTargetData()-> 5029 getABITypeAlignment(SVT.getTypeForMVT()); 5030 if (Align <= OrigAlign && 5031 ((!LegalOperations && !ST->isVolatile()) || 5032 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5033 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5034 Ptr, ST->getSrcValue(), 5035 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5036 } 5037 5038 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5039 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5040 // NOTE: If the original store is volatile, this transform must not increase 5041 // the number of stores. For example, on x86-32 an f64 can be stored in one 5042 // processor operation but an i64 (which is not legal) requires two. So the 5043 // transform should not be done in this case. 5044 if (Value.getOpcode() != ISD::TargetConstantFP) { 5045 SDValue Tmp; 5046 switch (CFP->getValueType(0).getSimpleVT()) { 5047 default: assert(0 && "Unknown FP type"); 5048 case MVT::f80: // We don't do this for these yet. 5049 case MVT::f128: 5050 case MVT::ppcf128: 5051 break; 5052 case MVT::f32: 5053 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5054 !ST->isVolatile()) || 5055 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5056 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5057 bitcastToAPInt().getZExtValue(), MVT::i32); 5058 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5059 Ptr, ST->getSrcValue(), 5060 ST->getSrcValueOffset(), ST->isVolatile(), 5061 ST->getAlignment()); 5062 } 5063 break; 5064 case MVT::f64: 5065 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5066 !ST->isVolatile()) || 5067 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5068 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5069 getZExtValue(), MVT::i64); 5070 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5071 Ptr, ST->getSrcValue(), 5072 ST->getSrcValueOffset(), ST->isVolatile(), 5073 ST->getAlignment()); 5074 } else if (!ST->isVolatile() && 5075 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5076 // Many FP stores are not made apparent until after legalize, e.g. for 5077 // argument passing. Since this is so common, custom legalize the 5078 // 64-bit integer store into two 32-bit stores. 5079 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5080 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5081 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5082 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5083 5084 int SVOffset = ST->getSrcValueOffset(); 5085 unsigned Alignment = ST->getAlignment(); 5086 bool isVolatile = ST->isVolatile(); 5087 5088 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5089 Ptr, ST->getSrcValue(), 5090 ST->getSrcValueOffset(), 5091 isVolatile, ST->getAlignment()); 5092 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5093 DAG.getConstant(4, Ptr.getValueType())); 5094 SVOffset += 4; 5095 Alignment = MinAlign(Alignment, 4U); 5096 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5097 Ptr, ST->getSrcValue(), 5098 SVOffset, isVolatile, Alignment); 5099 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5100 St0, St1); 5101 } 5102 5103 break; 5104 } 5105 } 5106 } 5107 5108 if (CombinerAA) { 5109 // Walk up chain skipping non-aliasing memory nodes. 5110 SDValue BetterChain = FindBetterChain(N, Chain); 5111 5112 // If there is a better chain. 5113 if (Chain != BetterChain) { 5114 // Replace the chain to avoid dependency. 5115 SDValue ReplStore; 5116 if (ST->isTruncatingStore()) { 5117 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5118 ST->getSrcValue(),ST->getSrcValueOffset(), 5119 ST->getMemoryVT(), 5120 ST->isVolatile(), ST->getAlignment()); 5121 } else { 5122 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5123 ST->getSrcValue(), ST->getSrcValueOffset(), 5124 ST->isVolatile(), ST->getAlignment()); 5125 } 5126 5127 // Create token to keep both nodes around. 5128 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5129 MVT::Other, Chain, ReplStore); 5130 5131 // Don't add users to work list. 5132 return CombineTo(N, Token, false); 5133 } 5134 } 5135 5136 // Try transforming N to an indexed store. 5137 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5138 return SDValue(N, 0); 5139 5140 // FIXME: is there such a thing as a truncating indexed store? 5141 if (ST->isTruncatingStore() && ST->isUnindexed() && 5142 Value.getValueType().isInteger()) { 5143 // See if we can simplify the input to this truncstore with knowledge that 5144 // only the low bits are being used. For example: 5145 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5146 SDValue Shorter = 5147 GetDemandedBits(Value, 5148 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5149 ST->getMemoryVT().getSizeInBits())); 5150 AddToWorkList(Value.getNode()); 5151 if (Shorter.getNode()) 5152 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5153 Ptr, ST->getSrcValue(), 5154 ST->getSrcValueOffset(), ST->getMemoryVT(), 5155 ST->isVolatile(), ST->getAlignment()); 5156 5157 // Otherwise, see if we can simplify the operation with 5158 // SimplifyDemandedBits, which only works if the value has a single use. 5159 if (SimplifyDemandedBits(Value, 5160 APInt::getLowBitsSet( 5161 Value.getValueSizeInBits(), 5162 ST->getMemoryVT().getSizeInBits()))) 5163 return SDValue(N, 0); 5164 } 5165 5166 // If this is a load followed by a store to the same location, then the store 5167 // is dead/noop. 5168 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5169 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5170 ST->isUnindexed() && !ST->isVolatile() && 5171 // There can't be any side effects between the load and store, such as 5172 // a call or store. 5173 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5174 // The store is dead, remove it. 5175 return Chain; 5176 } 5177 } 5178 5179 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5180 // truncating store. We can do this even if this is already a truncstore. 5181 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5182 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5183 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5184 ST->getMemoryVT())) { 5185 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5186 Ptr, ST->getSrcValue(), 5187 ST->getSrcValueOffset(), ST->getMemoryVT(), 5188 ST->isVolatile(), ST->getAlignment()); 5189 } 5190 5191 return ReduceLoadOpStoreWidth(N); 5192} 5193 5194SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5195 SDValue InVec = N->getOperand(0); 5196 SDValue InVal = N->getOperand(1); 5197 SDValue EltNo = N->getOperand(2); 5198 5199 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5200 // vector with the inserted element. 5201 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5202 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5203 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5204 InVec.getNode()->op_end()); 5205 if (Elt < Ops.size()) 5206 Ops[Elt] = InVal; 5207 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5208 InVec.getValueType(), &Ops[0], Ops.size()); 5209 } 5210 // If the invec is an UNDEF and if EltNo is a constant, create a new 5211 // BUILD_VECTOR with undef elements and the inserted element. 5212 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5213 isa<ConstantSDNode>(EltNo)) { 5214 MVT VT = InVec.getValueType(); 5215 MVT EVT = VT.getVectorElementType(); 5216 unsigned NElts = VT.getVectorNumElements(); 5217 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT)); 5218 5219 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5220 if (Elt < Ops.size()) 5221 Ops[Elt] = InVal; 5222 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5223 InVec.getValueType(), &Ops[0], Ops.size()); 5224 } 5225 return SDValue(); 5226} 5227 5228SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5229 // (vextract (scalar_to_vector val, 0) -> val 5230 SDValue InVec = N->getOperand(0); 5231 5232 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5233 // If the operand is wider than the vector element type then it is implicitly 5234 // truncated. Make that explicit here. 5235 MVT EltVT = InVec.getValueType().getVectorElementType(); 5236 SDValue InOp = InVec.getOperand(0); 5237 if (InOp.getValueType() != EltVT) 5238 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5239 return InOp; 5240 } 5241 5242 // Perform only after legalization to ensure build_vector / vector_shuffle 5243 // optimizations have already been done. 5244 if (!LegalOperations) return SDValue(); 5245 5246 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5247 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5248 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5249 SDValue EltNo = N->getOperand(1); 5250 5251 if (isa<ConstantSDNode>(EltNo)) { 5252 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5253 bool NewLoad = false; 5254 bool BCNumEltsChanged = false; 5255 MVT VT = InVec.getValueType(); 5256 MVT EVT = VT.getVectorElementType(); 5257 MVT LVT = EVT; 5258 5259 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5260 MVT BCVT = InVec.getOperand(0).getValueType(); 5261 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5262 return SDValue(); 5263 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5264 BCNumEltsChanged = true; 5265 InVec = InVec.getOperand(0); 5266 EVT = BCVT.getVectorElementType(); 5267 NewLoad = true; 5268 } 5269 5270 LoadSDNode *LN0 = NULL; 5271 const ShuffleVectorSDNode *SVN = NULL; 5272 if (ISD::isNormalLoad(InVec.getNode())) { 5273 LN0 = cast<LoadSDNode>(InVec); 5274 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5275 InVec.getOperand(0).getValueType() == EVT && 5276 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5277 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5278 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5279 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5280 // => 5281 // (load $addr+1*size) 5282 5283 // If the bit convert changed the number of elements, it is unsafe 5284 // to examine the mask. 5285 if (BCNumEltsChanged) 5286 return SDValue(); 5287 5288 // Select the input vector, guarding against out of range extract vector. 5289 unsigned NumElems = VT.getVectorNumElements(); 5290 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5291 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5292 5293 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5294 InVec = InVec.getOperand(0); 5295 if (ISD::isNormalLoad(InVec.getNode())) { 5296 LN0 = cast<LoadSDNode>(InVec); 5297 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5298 } 5299 } 5300 5301 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5302 return SDValue(); 5303 5304 unsigned Align = LN0->getAlignment(); 5305 if (NewLoad) { 5306 // Check the resultant load doesn't need a higher alignment than the 5307 // original load. 5308 unsigned NewAlign = 5309 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); 5310 5311 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5312 return SDValue(); 5313 5314 Align = NewAlign; 5315 } 5316 5317 SDValue NewPtr = LN0->getBasePtr(); 5318 if (Elt) { 5319 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5320 MVT PtrType = NewPtr.getValueType(); 5321 if (TLI.isBigEndian()) 5322 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5323 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5324 DAG.getConstant(PtrOff, PtrType)); 5325 } 5326 5327 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5328 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5329 LN0->isVolatile(), Align); 5330 } 5331 5332 return SDValue(); 5333} 5334 5335SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5336 unsigned NumInScalars = N->getNumOperands(); 5337 MVT VT = N->getValueType(0); 5338 MVT EltType = VT.getVectorElementType(); 5339 5340 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5341 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5342 // at most two distinct vectors, turn this into a shuffle node. 5343 SDValue VecIn1, VecIn2; 5344 for (unsigned i = 0; i != NumInScalars; ++i) { 5345 // Ignore undef inputs. 5346 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5347 5348 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5349 // constant index, bail out. 5350 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5351 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5352 VecIn1 = VecIn2 = SDValue(0, 0); 5353 break; 5354 } 5355 5356 // If the input vector type disagrees with the result of the build_vector, 5357 // we can't make a shuffle. 5358 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5359 if (ExtractedFromVec.getValueType() != VT) { 5360 VecIn1 = VecIn2 = SDValue(0, 0); 5361 break; 5362 } 5363 5364 // Otherwise, remember this. We allow up to two distinct input vectors. 5365 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5366 continue; 5367 5368 if (VecIn1.getNode() == 0) { 5369 VecIn1 = ExtractedFromVec; 5370 } else if (VecIn2.getNode() == 0) { 5371 VecIn2 = ExtractedFromVec; 5372 } else { 5373 // Too many inputs. 5374 VecIn1 = VecIn2 = SDValue(0, 0); 5375 break; 5376 } 5377 } 5378 5379 // If everything is good, we can make a shuffle operation. 5380 if (VecIn1.getNode()) { 5381 SmallVector<int, 8> Mask; 5382 for (unsigned i = 0; i != NumInScalars; ++i) { 5383 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5384 Mask.push_back(-1); 5385 continue; 5386 } 5387 5388 // If extracting from the first vector, just use the index directly. 5389 SDValue Extract = N->getOperand(i); 5390 SDValue ExtVal = Extract.getOperand(1); 5391 if (Extract.getOperand(0) == VecIn1) { 5392 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5393 if (ExtIndex > VT.getVectorNumElements()) 5394 return SDValue(); 5395 5396 Mask.push_back(ExtIndex); 5397 continue; 5398 } 5399 5400 // Otherwise, use InIdx + VecSize 5401 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5402 Mask.push_back(Idx+NumInScalars); 5403 } 5404 5405 // Add count and size info. 5406 if (!TLI.isTypeLegal(VT) && LegalTypes) 5407 return SDValue(); 5408 5409 // Return the new VECTOR_SHUFFLE node. 5410 SDValue Ops[2]; 5411 Ops[0] = VecIn1; 5412 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5413 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5414 } 5415 5416 return SDValue(); 5417} 5418 5419SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5420 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5421 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5422 // inputs come from at most two distinct vectors, turn this into a shuffle 5423 // node. 5424 5425 // If we only have one input vector, we don't need to do any concatenation. 5426 if (N->getNumOperands() == 1) 5427 return N->getOperand(0); 5428 5429 return SDValue(); 5430} 5431 5432SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5433 return SDValue(); 5434 5435 MVT VT = N->getValueType(0); 5436 unsigned NumElts = VT.getVectorNumElements(); 5437 5438 SDValue N0 = N->getOperand(0); 5439 SDValue N1 = N->getOperand(1); 5440 5441 assert(N0.getValueType().getVectorNumElements() == NumElts && 5442 "Vector shuffle must be normalized in DAG"); 5443 5444 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5445 5446 // If it is a splat, check if the argument vector is a build_vector with 5447 // all scalar elements the same. 5448 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5449 SDNode *V = N0.getNode(); 5450 5451 5452 // If this is a bit convert that changes the element type of the vector but 5453 // not the number of vector elements, look through it. Be careful not to 5454 // look though conversions that change things like v4f32 to v2f64. 5455 if (V->getOpcode() == ISD::BIT_CONVERT) { 5456 SDValue ConvInput = V->getOperand(0); 5457 if (ConvInput.getValueType().isVector() && 5458 ConvInput.getValueType().getVectorNumElements() == NumElts) 5459 V = ConvInput.getNode(); 5460 } 5461 5462 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5463 unsigned NumElems = V->getNumOperands(); 5464 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5465 if (NumElems > BaseIdx) { 5466 SDValue Base; 5467 bool AllSame = true; 5468 for (unsigned i = 0; i != NumElems; ++i) { 5469 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5470 Base = V->getOperand(i); 5471 break; 5472 } 5473 } 5474 // Splat of <u, u, u, u>, return <u, u, u, u> 5475 if (!Base.getNode()) 5476 return N0; 5477 for (unsigned i = 0; i != NumElems; ++i) { 5478 if (V->getOperand(i) != Base) { 5479 AllSame = false; 5480 break; 5481 } 5482 } 5483 // Splat of <x, x, x, x>, return <x, x, x, x> 5484 if (AllSame) 5485 return N0; 5486 } 5487 } 5488 } 5489 return SDValue(); 5490} 5491 5492/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5493/// an AND to a vector_shuffle with the destination vector and a zero vector. 5494/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5495/// vector_shuffle V, Zero, <0, 4, 2, 4> 5496SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5497 MVT VT = N->getValueType(0); 5498 DebugLoc dl = N->getDebugLoc(); 5499 SDValue LHS = N->getOperand(0); 5500 SDValue RHS = N->getOperand(1); 5501 if (N->getOpcode() == ISD::AND) { 5502 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5503 RHS = RHS.getOperand(0); 5504 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5505 SmallVector<int, 8> Indices; 5506 unsigned NumElts = RHS.getNumOperands(); 5507 for (unsigned i = 0; i != NumElts; ++i) { 5508 SDValue Elt = RHS.getOperand(i); 5509 if (!isa<ConstantSDNode>(Elt)) 5510 return SDValue(); 5511 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5512 Indices.push_back(i); 5513 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5514 Indices.push_back(NumElts); 5515 else 5516 return SDValue(); 5517 } 5518 5519 // Let's see if the target supports this vector_shuffle. 5520 MVT RVT = RHS.getValueType(); 5521 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5522 return SDValue(); 5523 5524 // Return the new VECTOR_SHUFFLE node. 5525 MVT EVT = RVT.getVectorElementType(); 5526 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5527 DAG.getConstant(0, EVT)); 5528 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5529 RVT, &ZeroOps[0], ZeroOps.size()); 5530 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5531 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5532 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5533 } 5534 } 5535 5536 return SDValue(); 5537} 5538 5539/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5540SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5541 // After legalize, the target may be depending on adds and other 5542 // binary ops to provide legal ways to construct constants or other 5543 // things. Simplifying them may result in a loss of legality. 5544 if (LegalOperations) return SDValue(); 5545 5546 MVT VT = N->getValueType(0); 5547 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5548 5549 MVT EltType = VT.getVectorElementType(); 5550 SDValue LHS = N->getOperand(0); 5551 SDValue RHS = N->getOperand(1); 5552 SDValue Shuffle = XformToShuffleWithZero(N); 5553 if (Shuffle.getNode()) return Shuffle; 5554 5555 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5556 // this operation. 5557 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5558 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5559 SmallVector<SDValue, 8> Ops; 5560 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5561 SDValue LHSOp = LHS.getOperand(i); 5562 SDValue RHSOp = RHS.getOperand(i); 5563 // If these two elements can't be folded, bail out. 5564 if ((LHSOp.getOpcode() != ISD::UNDEF && 5565 LHSOp.getOpcode() != ISD::Constant && 5566 LHSOp.getOpcode() != ISD::ConstantFP) || 5567 (RHSOp.getOpcode() != ISD::UNDEF && 5568 RHSOp.getOpcode() != ISD::Constant && 5569 RHSOp.getOpcode() != ISD::ConstantFP)) 5570 break; 5571 5572 // Can't fold divide by zero. 5573 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5574 N->getOpcode() == ISD::FDIV) { 5575 if ((RHSOp.getOpcode() == ISD::Constant && 5576 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5577 (RHSOp.getOpcode() == ISD::ConstantFP && 5578 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5579 break; 5580 } 5581 5582 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5583 EltType, LHSOp, RHSOp)); 5584 AddToWorkList(Ops.back().getNode()); 5585 assert((Ops.back().getOpcode() == ISD::UNDEF || 5586 Ops.back().getOpcode() == ISD::Constant || 5587 Ops.back().getOpcode() == ISD::ConstantFP) && 5588 "Scalar binop didn't fold!"); 5589 } 5590 5591 if (Ops.size() == LHS.getNumOperands()) { 5592 MVT VT = LHS.getValueType(); 5593 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5594 &Ops[0], Ops.size()); 5595 } 5596 } 5597 5598 return SDValue(); 5599} 5600 5601SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5602 SDValue N1, SDValue N2){ 5603 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5604 5605 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5606 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5607 5608 // If we got a simplified select_cc node back from SimplifySelectCC, then 5609 // break it down into a new SETCC node, and a new SELECT node, and then return 5610 // the SELECT node, since we were called with a SELECT node. 5611 if (SCC.getNode()) { 5612 // Check to see if we got a select_cc back (to turn into setcc/select). 5613 // Otherwise, just return whatever node we got back, like fabs. 5614 if (SCC.getOpcode() == ISD::SELECT_CC) { 5615 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5616 N0.getValueType(), 5617 SCC.getOperand(0), SCC.getOperand(1), 5618 SCC.getOperand(4)); 5619 AddToWorkList(SETCC.getNode()); 5620 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5621 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5622 } 5623 5624 return SCC; 5625 } 5626 return SDValue(); 5627} 5628 5629/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5630/// are the two values being selected between, see if we can simplify the 5631/// select. Callers of this should assume that TheSelect is deleted if this 5632/// returns true. As such, they should return the appropriate thing (e.g. the 5633/// node) back to the top-level of the DAG combiner loop to avoid it being 5634/// looked at. 5635bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5636 SDValue RHS) { 5637 5638 // If this is a select from two identical things, try to pull the operation 5639 // through the select. 5640 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5641 // If this is a load and the token chain is identical, replace the select 5642 // of two loads with a load through a select of the address to load from. 5643 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5644 // constants have been dropped into the constant pool. 5645 if (LHS.getOpcode() == ISD::LOAD && 5646 // Do not let this transformation reduce the number of volatile loads. 5647 !cast<LoadSDNode>(LHS)->isVolatile() && 5648 !cast<LoadSDNode>(RHS)->isVolatile() && 5649 // Token chains must be identical. 5650 LHS.getOperand(0) == RHS.getOperand(0)) { 5651 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5652 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5653 5654 // If this is an EXTLOAD, the VT's must match. 5655 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5656 // FIXME: this conflates two src values, discarding one. This is not 5657 // the right thing to do, but nothing uses srcvalues now. When they do, 5658 // turn SrcValue into a list of locations. 5659 SDValue Addr; 5660 if (TheSelect->getOpcode() == ISD::SELECT) { 5661 // Check that the condition doesn't reach either load. If so, folding 5662 // this will induce a cycle into the DAG. 5663 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5664 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5665 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5666 LLD->getBasePtr().getValueType(), 5667 TheSelect->getOperand(0), LLD->getBasePtr(), 5668 RLD->getBasePtr()); 5669 } 5670 } else { 5671 // Check that the condition doesn't reach either load. If so, folding 5672 // this will induce a cycle into the DAG. 5673 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5674 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5675 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5676 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5677 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5678 LLD->getBasePtr().getValueType(), 5679 TheSelect->getOperand(0), 5680 TheSelect->getOperand(1), 5681 LLD->getBasePtr(), RLD->getBasePtr(), 5682 TheSelect->getOperand(4)); 5683 } 5684 } 5685 5686 if (Addr.getNode()) { 5687 SDValue Load; 5688 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5689 Load = DAG.getLoad(TheSelect->getValueType(0), 5690 TheSelect->getDebugLoc(), 5691 LLD->getChain(), 5692 Addr,LLD->getSrcValue(), 5693 LLD->getSrcValueOffset(), 5694 LLD->isVolatile(), 5695 LLD->getAlignment()); 5696 } else { 5697 Load = DAG.getExtLoad(LLD->getExtensionType(), 5698 TheSelect->getDebugLoc(), 5699 TheSelect->getValueType(0), 5700 LLD->getChain(), Addr, LLD->getSrcValue(), 5701 LLD->getSrcValueOffset(), 5702 LLD->getMemoryVT(), 5703 LLD->isVolatile(), 5704 LLD->getAlignment()); 5705 } 5706 5707 // Users of the select now use the result of the load. 5708 CombineTo(TheSelect, Load); 5709 5710 // Users of the old loads now use the new load's chain. We know the 5711 // old-load value is dead now. 5712 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5713 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5714 return true; 5715 } 5716 } 5717 } 5718 } 5719 5720 return false; 5721} 5722 5723/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5724/// where 'cond' is the comparison specified by CC. 5725SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5726 SDValue N2, SDValue N3, 5727 ISD::CondCode CC, bool NotExtCompare) { 5728 // (x ? y : y) -> y. 5729 if (N2 == N3) return N2; 5730 5731 MVT VT = N2.getValueType(); 5732 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5733 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5734 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5735 5736 // Determine if the condition we're dealing with is constant 5737 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5738 N0, N1, CC, DL, false); 5739 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5740 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5741 5742 // fold select_cc true, x, y -> x 5743 if (SCCC && !SCCC->isNullValue()) 5744 return N2; 5745 // fold select_cc false, x, y -> y 5746 if (SCCC && SCCC->isNullValue()) 5747 return N3; 5748 5749 // Check to see if we can simplify the select into an fabs node 5750 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5751 // Allow either -0.0 or 0.0 5752 if (CFP->getValueAPF().isZero()) { 5753 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5754 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5755 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5756 N2 == N3.getOperand(0)) 5757 return DAG.getNode(ISD::FABS, DL, VT, N0); 5758 5759 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5760 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5761 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5762 N2.getOperand(0) == N3) 5763 return DAG.getNode(ISD::FABS, DL, VT, N3); 5764 } 5765 } 5766 5767 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5768 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5769 // in it. This is a win when the constant is not otherwise available because 5770 // it replaces two constant pool loads with one. We only do this if the FP 5771 // type is known to be legal, because if it isn't, then we are before legalize 5772 // types an we want the other legalization to happen first (e.g. to avoid 5773 // messing with soft float) and if the ConstantFP is not legal, because if 5774 // it is legal, we may not need to store the FP constant in a constant pool. 5775 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5776 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5777 if (TLI.isTypeLegal(N2.getValueType()) && 5778 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5779 TargetLowering::Legal) && 5780 // If both constants have multiple uses, then we won't need to do an 5781 // extra load, they are likely around in registers for other users. 5782 (TV->hasOneUse() || FV->hasOneUse())) { 5783 Constant *Elts[] = { 5784 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5785 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5786 }; 5787 const Type *FPTy = Elts[0]->getType(); 5788 const TargetData &TD = *TLI.getTargetData(); 5789 5790 // Create a ConstantArray of the two constants. 5791 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5792 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5793 TD.getPrefTypeAlignment(FPTy)); 5794 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5795 5796 // Get the offsets to the 0 and 1 element of the array so that we can 5797 // select between them. 5798 SDValue Zero = DAG.getIntPtrConstant(0); 5799 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5800 SDValue One = DAG.getIntPtrConstant(EltSize); 5801 5802 SDValue Cond = DAG.getSetCC(DL, 5803 TLI.getSetCCResultType(N0.getValueType()), 5804 N0, N1, CC); 5805 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5806 Cond, One, Zero); 5807 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5808 CstOffset); 5809 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5810 PseudoSourceValue::getConstantPool(), 0, false, 5811 Alignment); 5812 5813 } 5814 } 5815 5816 // Check to see if we can perform the "gzip trick", transforming 5817 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5818 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5819 N0.getValueType().isInteger() && 5820 N2.getValueType().isInteger() && 5821 (N1C->isNullValue() || // (a < 0) ? b : 0 5822 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5823 MVT XType = N0.getValueType(); 5824 MVT AType = N2.getValueType(); 5825 if (XType.bitsGE(AType)) { 5826 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5827 // single-bit constant. 5828 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5829 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5830 ShCtV = XType.getSizeInBits()-ShCtV-1; 5831 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5832 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5833 XType, N0, ShCt); 5834 AddToWorkList(Shift.getNode()); 5835 5836 if (XType.bitsGT(AType)) { 5837 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5838 AddToWorkList(Shift.getNode()); 5839 } 5840 5841 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5842 } 5843 5844 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5845 XType, N0, 5846 DAG.getConstant(XType.getSizeInBits()-1, 5847 getShiftAmountTy())); 5848 AddToWorkList(Shift.getNode()); 5849 5850 if (XType.bitsGT(AType)) { 5851 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5852 AddToWorkList(Shift.getNode()); 5853 } 5854 5855 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5856 } 5857 } 5858 5859 // fold select C, 16, 0 -> shl C, 4 5860 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5861 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5862 5863 // If the caller doesn't want us to simplify this into a zext of a compare, 5864 // don't do it. 5865 if (NotExtCompare && N2C->getAPIntValue() == 1) 5866 return SDValue(); 5867 5868 // Get a SetCC of the condition 5869 // FIXME: Should probably make sure that setcc is legal if we ever have a 5870 // target where it isn't. 5871 SDValue Temp, SCC; 5872 // cast from setcc result type to select result type 5873 if (LegalTypes) { 5874 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5875 N0, N1, CC); 5876 if (N2.getValueType().bitsLT(SCC.getValueType())) 5877 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5878 else 5879 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5880 N2.getValueType(), SCC); 5881 } else { 5882 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5883 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5884 N2.getValueType(), SCC); 5885 } 5886 5887 AddToWorkList(SCC.getNode()); 5888 AddToWorkList(Temp.getNode()); 5889 5890 if (N2C->getAPIntValue() == 1) 5891 return Temp; 5892 5893 // shl setcc result by log2 n2c 5894 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5895 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5896 getShiftAmountTy())); 5897 } 5898 5899 // Check to see if this is the equivalent of setcc 5900 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5901 // otherwise, go ahead with the folds. 5902 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5903 MVT XType = N0.getValueType(); 5904 if (!LegalOperations || 5905 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5906 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5907 if (Res.getValueType() != VT) 5908 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5909 return Res; 5910 } 5911 5912 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5913 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5914 (!LegalOperations || 5915 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5916 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5917 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5918 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5919 getShiftAmountTy())); 5920 } 5921 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5922 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5923 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5924 XType, DAG.getConstant(0, XType), N0); 5925 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5926 return DAG.getNode(ISD::SRL, DL, XType, 5927 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5928 DAG.getConstant(XType.getSizeInBits()-1, 5929 getShiftAmountTy())); 5930 } 5931 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5932 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5933 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5934 DAG.getConstant(XType.getSizeInBits()-1, 5935 getShiftAmountTy())); 5936 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5937 } 5938 } 5939 5940 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5941 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5942 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5943 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5944 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5945 MVT XType = N0.getValueType(); 5946 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5947 DAG.getConstant(XType.getSizeInBits()-1, 5948 getShiftAmountTy())); 5949 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5950 N0, Shift); 5951 AddToWorkList(Shift.getNode()); 5952 AddToWorkList(Add.getNode()); 5953 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5954 } 5955 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5956 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5957 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5958 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5959 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5960 MVT XType = N0.getValueType(); 5961 if (SubC->isNullValue() && XType.isInteger()) { 5962 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5963 N0, 5964 DAG.getConstant(XType.getSizeInBits()-1, 5965 getShiftAmountTy())); 5966 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 5967 XType, N0, Shift); 5968 AddToWorkList(Shift.getNode()); 5969 AddToWorkList(Add.getNode()); 5970 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5971 } 5972 } 5973 } 5974 5975 return SDValue(); 5976} 5977 5978/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5979SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5980 SDValue N1, ISD::CondCode Cond, 5981 DebugLoc DL, bool foldBooleans) { 5982 TargetLowering::DAGCombinerInfo 5983 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5984 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 5985} 5986 5987/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5988/// return a DAG expression to select that will generate the same value by 5989/// multiplying by a magic number. See: 5990/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5991SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5992 std::vector<SDNode*> Built; 5993 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5994 5995 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5996 ii != ee; ++ii) 5997 AddToWorkList(*ii); 5998 return S; 5999} 6000 6001/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6002/// return a DAG expression to select that will generate the same value by 6003/// multiplying by a magic number. See: 6004/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6005SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6006 std::vector<SDNode*> Built; 6007 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6008 6009 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6010 ii != ee; ++ii) 6011 AddToWorkList(*ii); 6012 return S; 6013} 6014 6015/// FindBaseOffset - Return true if base is known not to alias with anything 6016/// but itself. Provides base object and offset as results. 6017static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 6018 // Assume it is a primitive operation. 6019 Base = Ptr; Offset = 0; 6020 6021 // If it's an adding a simple constant then integrate the offset. 6022 if (Base.getOpcode() == ISD::ADD) { 6023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6024 Base = Base.getOperand(0); 6025 Offset += C->getZExtValue(); 6026 } 6027 } 6028 6029 // If it's any of the following then it can't alias with anything but itself. 6030 return isa<FrameIndexSDNode>(Base) || 6031 isa<ConstantPoolSDNode>(Base) || 6032 isa<GlobalAddressSDNode>(Base); 6033} 6034 6035/// isAlias - Return true if there is any possibility that the two addresses 6036/// overlap. 6037bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6038 const Value *SrcValue1, int SrcValueOffset1, 6039 SDValue Ptr2, int64_t Size2, 6040 const Value *SrcValue2, int SrcValueOffset2) const { 6041 // If they are the same then they must be aliases. 6042 if (Ptr1 == Ptr2) return true; 6043 6044 // Gather base node and offset information. 6045 SDValue Base1, Base2; 6046 int64_t Offset1, Offset2; 6047 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 6048 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 6049 6050 // If they have a same base address then... 6051 if (Base1 == Base2) 6052 // Check to see if the addresses overlap. 6053 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6054 6055 // If we know both bases then they can't alias. 6056 if (KnownBase1 && KnownBase2) return false; 6057 6058 if (CombinerGlobalAA) { 6059 // Use alias analysis information. 6060 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6061 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6062 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6063 AliasAnalysis::AliasResult AAResult = 6064 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6065 if (AAResult == AliasAnalysis::NoAlias) 6066 return false; 6067 } 6068 6069 // Otherwise we have to assume they alias. 6070 return true; 6071} 6072 6073/// FindAliasInfo - Extracts the relevant alias information from the memory 6074/// node. Returns true if the operand was a load. 6075bool DAGCombiner::FindAliasInfo(SDNode *N, 6076 SDValue &Ptr, int64_t &Size, 6077 const Value *&SrcValue, int &SrcValueOffset) const { 6078 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6079 Ptr = LD->getBasePtr(); 6080 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6081 SrcValue = LD->getSrcValue(); 6082 SrcValueOffset = LD->getSrcValueOffset(); 6083 return true; 6084 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6085 Ptr = ST->getBasePtr(); 6086 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6087 SrcValue = ST->getSrcValue(); 6088 SrcValueOffset = ST->getSrcValueOffset(); 6089 } else { 6090 assert(0 && "FindAliasInfo expected a memory operand"); 6091 } 6092 6093 return false; 6094} 6095 6096/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6097/// looking for aliasing nodes and adding them to the Aliases vector. 6098void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6099 SmallVector<SDValue, 8> &Aliases) { 6100 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6101 std::set<SDNode *> Visited; // Visited node set. 6102 6103 // Get alias information for node. 6104 SDValue Ptr; 6105 int64_t Size = 0; 6106 const Value *SrcValue = 0; 6107 int SrcValueOffset = 0; 6108 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6109 6110 // Starting off. 6111 Chains.push_back(OriginalChain); 6112 6113 // Look at each chain and determine if it is an alias. If so, add it to the 6114 // aliases list. If not, then continue up the chain looking for the next 6115 // candidate. 6116 while (!Chains.empty()) { 6117 SDValue Chain = Chains.back(); 6118 Chains.pop_back(); 6119 6120 // Don't bother if we've been before. 6121 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6122 Visited.insert(Chain.getNode()); 6123 6124 switch (Chain.getOpcode()) { 6125 case ISD::EntryToken: 6126 // Entry token is ideal chain operand, but handled in FindBetterChain. 6127 break; 6128 6129 case ISD::LOAD: 6130 case ISD::STORE: { 6131 // Get alias information for Chain. 6132 SDValue OpPtr; 6133 int64_t OpSize = 0; 6134 const Value *OpSrcValue = 0; 6135 int OpSrcValueOffset = 0; 6136 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6137 OpSrcValue, OpSrcValueOffset); 6138 6139 // If chain is alias then stop here. 6140 if (!(IsLoad && IsOpLoad) && 6141 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6142 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6143 Aliases.push_back(Chain); 6144 } else { 6145 // Look further up the chain. 6146 Chains.push_back(Chain.getOperand(0)); 6147 // Clean up old chain. 6148 AddToWorkList(Chain.getNode()); 6149 } 6150 break; 6151 } 6152 6153 case ISD::TokenFactor: 6154 // We have to check each of the operands of the token factor, so we queue 6155 // then up. Adding the operands to the queue (stack) in reverse order 6156 // maintains the original order and increases the likelihood that getNode 6157 // will find a matching token factor (CSE.) 6158 for (unsigned n = Chain.getNumOperands(); n;) 6159 Chains.push_back(Chain.getOperand(--n)); 6160 // Eliminate the token factor if we can. 6161 AddToWorkList(Chain.getNode()); 6162 break; 6163 6164 default: 6165 // For all other instructions we will just have to take what we can get. 6166 Aliases.push_back(Chain); 6167 break; 6168 } 6169 } 6170} 6171 6172/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6173/// for a better chain (aliasing node.) 6174SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6175 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6176 6177 // Accumulate all the aliases to this node. 6178 GatherAllAliases(N, OldChain, Aliases); 6179 6180 if (Aliases.size() == 0) { 6181 // If no operands then chain to entry token. 6182 return DAG.getEntryNode(); 6183 } else if (Aliases.size() == 1) { 6184 // If a single operand then chain to it. We don't need to revisit it. 6185 return Aliases[0]; 6186 } 6187 6188 // Construct a custom tailored token factor. 6189 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6190 &Aliases[0], Aliases.size()); 6191 6192 // Make sure the old chain gets cleaned up. 6193 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6194 6195 return NewChain; 6196} 6197 6198// SelectionDAG::Combine - This is the entry point for the file. 6199// 6200void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6201 CodeGenOpt::Level OptLevel) { 6202 /// run - This is the main entry point to this class. 6203 /// 6204 DAGCombiner(*this, AA, OptLevel).Run(Level); 6205} 6206