DAGCombiner.cpp revision 683c95764aa519ba21686e631fa8d2231c8dbd74
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 const TargetLowering &TLI; 53 CombineLevel Level; 54 bool LegalOperations; 55 bool LegalTypes; 56 bool Fast; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 // AA - Used for DAG load/store alias analysis. 62 AliasAnalysis &AA; 63 64 /// AddUsersToWorkList - When an instruction is simplified, add all users of 65 /// the instruction to the work lists because they might get more simplified 66 /// now. 67 /// 68 void AddUsersToWorkList(SDNode *N) { 69 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 70 UI != UE; ++UI) 71 AddToWorkList(*UI); 72 } 73 74 /// visit - call the node-specific routine that knows how to fold each 75 /// particular type of node. 76 SDValue visit(SDNode *N); 77 78 public: 79 /// AddToWorkList - Add to the work list making sure it's instance is at the 80 /// the back (next to be processed.) 81 void AddToWorkList(SDNode *N) { 82 removeFromWorkList(N); 83 WorkList.push_back(N); 84 } 85 86 /// removeFromWorkList - remove all instances of N from the worklist. 87 /// 88 void removeFromWorkList(SDNode *N) { 89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 90 WorkList.end()); 91 } 92 93 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 94 bool AddTo = true); 95 96 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 97 return CombineTo(N, &Res, 1, AddTo); 98 } 99 100 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 101 bool AddTo = true) { 102 SDValue To[] = { Res0, Res1 }; 103 return CombineTo(N, To, 2, AddTo); 104 } 105 106 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 107 108 private: 109 110 /// SimplifyDemandedBits - Check the specified integer node value to see if 111 /// it can be simplified or if things it uses can be simplified by bit 112 /// propagation. If so, return true. 113 bool SimplifyDemandedBits(SDValue Op) { 114 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 115 return SimplifyDemandedBits(Op, Demanded); 116 } 117 118 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 119 120 bool CombineToPreIndexedLoadStore(SDNode *N); 121 bool CombineToPostIndexedLoadStore(SDNode *N); 122 123 124 /// combine - call the node-specific routine that knows how to fold each 125 /// particular type of node. If that doesn't do anything, try the 126 /// target-specific DAG combines. 127 SDValue combine(SDNode *N); 128 129 // Visitation implementation - Implement dag node combining for different 130 // node types. The semantics are as follows: 131 // Return Value: 132 // SDValue.getNode() == 0 - No change was made 133 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 134 // otherwise - N should be replaced by the returned Operand. 135 // 136 SDValue visitTokenFactor(SDNode *N); 137 SDValue visitMERGE_VALUES(SDNode *N); 138 SDValue visitADD(SDNode *N); 139 SDValue visitSUB(SDNode *N); 140 SDValue visitADDC(SDNode *N); 141 SDValue visitADDE(SDNode *N); 142 SDValue visitMUL(SDNode *N); 143 SDValue visitSDIV(SDNode *N); 144 SDValue visitUDIV(SDNode *N); 145 SDValue visitSREM(SDNode *N); 146 SDValue visitUREM(SDNode *N); 147 SDValue visitMULHU(SDNode *N); 148 SDValue visitMULHS(SDNode *N); 149 SDValue visitSMUL_LOHI(SDNode *N); 150 SDValue visitUMUL_LOHI(SDNode *N); 151 SDValue visitSDIVREM(SDNode *N); 152 SDValue visitUDIVREM(SDNode *N); 153 SDValue visitAND(SDNode *N); 154 SDValue visitOR(SDNode *N); 155 SDValue visitXOR(SDNode *N); 156 SDValue SimplifyVBinOp(SDNode *N); 157 SDValue visitSHL(SDNode *N); 158 SDValue visitSRA(SDNode *N); 159 SDValue visitSRL(SDNode *N); 160 SDValue visitCTLZ(SDNode *N); 161 SDValue visitCTTZ(SDNode *N); 162 SDValue visitCTPOP(SDNode *N); 163 SDValue visitSELECT(SDNode *N); 164 SDValue visitSELECT_CC(SDNode *N); 165 SDValue visitSETCC(SDNode *N); 166 SDValue visitSIGN_EXTEND(SDNode *N); 167 SDValue visitZERO_EXTEND(SDNode *N); 168 SDValue visitANY_EXTEND(SDNode *N); 169 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 170 SDValue visitTRUNCATE(SDNode *N); 171 SDValue visitBIT_CONVERT(SDNode *N); 172 SDValue visitBUILD_PAIR(SDNode *N); 173 SDValue visitFADD(SDNode *N); 174 SDValue visitFSUB(SDNode *N); 175 SDValue visitFMUL(SDNode *N); 176 SDValue visitFDIV(SDNode *N); 177 SDValue visitFREM(SDNode *N); 178 SDValue visitFCOPYSIGN(SDNode *N); 179 SDValue visitSINT_TO_FP(SDNode *N); 180 SDValue visitUINT_TO_FP(SDNode *N); 181 SDValue visitFP_TO_SINT(SDNode *N); 182 SDValue visitFP_TO_UINT(SDNode *N); 183 SDValue visitFP_ROUND(SDNode *N); 184 SDValue visitFP_ROUND_INREG(SDNode *N); 185 SDValue visitFP_EXTEND(SDNode *N); 186 SDValue visitFNEG(SDNode *N); 187 SDValue visitFABS(SDNode *N); 188 SDValue visitBRCOND(SDNode *N); 189 SDValue visitBR_CC(SDNode *N); 190 SDValue visitLOAD(SDNode *N); 191 SDValue visitSTORE(SDNode *N); 192 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 193 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 194 SDValue visitBUILD_VECTOR(SDNode *N); 195 SDValue visitCONCAT_VECTORS(SDNode *N); 196 SDValue visitVECTOR_SHUFFLE(SDNode *N); 197 198 SDValue XformToShuffleWithZero(SDNode *N); 199 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 200 201 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 202 203 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 204 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 205 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 206 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 207 SDValue N3, ISD::CondCode CC, 208 bool NotExtCompare = false); 209 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 210 bool foldBooleans = true); 211 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 212 unsigned HiOp); 213 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 214 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 215 SDValue BuildSDIV(SDNode *N); 216 SDValue BuildUDIV(SDNode *N); 217 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 218 SDValue ReduceLoadWidth(SDNode *N); 219 220 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 221 222 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 223 /// looking for aliasing nodes and adding them to the Aliases vector. 224 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 225 SmallVector<SDValue, 8> &Aliases); 226 227 /// isAlias - Return true if there is any possibility that the two addresses 228 /// overlap. 229 bool isAlias(SDValue Ptr1, int64_t Size1, 230 const Value *SrcValue1, int SrcValueOffset1, 231 SDValue Ptr2, int64_t Size2, 232 const Value *SrcValue2, int SrcValueOffset2); 233 234 /// FindAliasInfo - Extracts the relevant alias information from the memory 235 /// node. Returns true if the operand was a load. 236 bool FindAliasInfo(SDNode *N, 237 SDValue &Ptr, int64_t &Size, 238 const Value *&SrcValue, int &SrcValueOffset); 239 240 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 241 /// looking for a better chain (aliasing node.) 242 SDValue FindBetterChain(SDNode *N, SDValue Chain); 243 244public: 245 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 246 : DAG(D), 247 TLI(D.getTargetLoweringInfo()), 248 Level(Unrestricted), 249 LegalOperations(false), 250 LegalTypes(false), 251 Fast(fast), 252 AA(A) {} 253 254 /// Run - runs the dag combiner on all nodes in the work list 255 void Run(CombineLevel AtLevel); 256 }; 257} 258 259 260namespace { 261/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 262/// nodes from the worklist. 263class VISIBILITY_HIDDEN WorkListRemover : 264 public SelectionDAG::DAGUpdateListener { 265 DAGCombiner &DC; 266public: 267 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 268 269 virtual void NodeDeleted(SDNode *N, SDNode *E) { 270 DC.removeFromWorkList(N); 271 } 272 273 virtual void NodeUpdated(SDNode *N) { 274 // Ignore updates. 275 } 276}; 277} 278 279//===----------------------------------------------------------------------===// 280// TargetLowering::DAGCombinerInfo implementation 281//===----------------------------------------------------------------------===// 282 283void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 284 ((DAGCombiner*)DC)->AddToWorkList(N); 285} 286 287SDValue TargetLowering::DAGCombinerInfo:: 288CombineTo(SDNode *N, const std::vector<SDValue> &To) { 289 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 290} 291 292SDValue TargetLowering::DAGCombinerInfo:: 293CombineTo(SDNode *N, SDValue Res) { 294 return ((DAGCombiner*)DC)->CombineTo(N, Res); 295} 296 297 298SDValue TargetLowering::DAGCombinerInfo:: 299CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 300 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 301} 302 303void TargetLowering::DAGCombinerInfo:: 304CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 305 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 306} 307 308//===----------------------------------------------------------------------===// 309// Helper Functions 310//===----------------------------------------------------------------------===// 311 312/// isNegatibleForFree - Return 1 if we can compute the negated form of the 313/// specified expression for the same cost as the expression itself, or 2 if we 314/// can compute the negated form more cheaply than the expression itself. 315static char isNegatibleForFree(SDValue Op, bool LegalOperations, 316 unsigned Depth = 0) { 317 // No compile time optimizations on this type. 318 if (Op.getValueType() == MVT::ppcf128) 319 return 0; 320 321 // fneg is removable even if it has multiple uses. 322 if (Op.getOpcode() == ISD::FNEG) return 2; 323 324 // Don't allow anything with multiple uses. 325 if (!Op.hasOneUse()) return 0; 326 327 // Don't recurse exponentially. 328 if (Depth > 6) return 0; 329 330 switch (Op.getOpcode()) { 331 default: return false; 332 case ISD::ConstantFP: 333 // Don't invert constant FP values after legalize. The negated constant 334 // isn't necessarily legal. 335 return LegalOperations ? 0 : 1; 336 case ISD::FADD: 337 // FIXME: determine better conditions for this xform. 338 if (!UnsafeFPMath) return 0; 339 340 // -(A+B) -> -A - B 341 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 342 return V; 343 // -(A+B) -> -B - A 344 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 345 case ISD::FSUB: 346 // We can't turn -(A-B) into B-A when we honor signed zeros. 347 if (!UnsafeFPMath) return 0; 348 349 // -(A-B) -> B-A 350 return 1; 351 352 case ISD::FMUL: 353 case ISD::FDIV: 354 if (HonorSignDependentRoundingFPMath()) return 0; 355 356 // -(X*Y) -> (-X * Y) or (X*-Y) 357 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 358 return V; 359 360 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 361 362 case ISD::FP_EXTEND: 363 case ISD::FP_ROUND: 364 case ISD::FSIN: 365 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 366 } 367} 368 369/// GetNegatedExpression - If isNegatibleForFree returns true, this function 370/// returns the newly negated expression. 371static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 372 bool LegalOperations, unsigned Depth = 0) { 373 // fneg is removable even if it has multiple uses. 374 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 375 376 // Don't allow anything with multiple uses. 377 assert(Op.hasOneUse() && "Unknown reuse!"); 378 379 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 380 switch (Op.getOpcode()) { 381 default: assert(0 && "Unknown code"); 382 case ISD::ConstantFP: { 383 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 384 V.changeSign(); 385 return DAG.getConstantFP(V, Op.getValueType()); 386 } 387 case ISD::FADD: 388 // FIXME: determine better conditions for this xform. 389 assert(UnsafeFPMath); 390 391 // -(A+B) -> -A - B 392 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 393 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 394 GetNegatedExpression(Op.getOperand(0), DAG, 395 LegalOperations, Depth+1), 396 Op.getOperand(1)); 397 // -(A+B) -> -B - A 398 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 399 GetNegatedExpression(Op.getOperand(1), DAG, 400 LegalOperations, Depth+1), 401 Op.getOperand(0)); 402 case ISD::FSUB: 403 // We can't turn -(A-B) into B-A when we honor signed zeros. 404 assert(UnsafeFPMath); 405 406 // -(0-B) -> B 407 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 408 if (N0CFP->getValueAPF().isZero()) 409 return Op.getOperand(1); 410 411 // -(A-B) -> B-A 412 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 413 Op.getOperand(1), Op.getOperand(0)); 414 415 case ISD::FMUL: 416 case ISD::FDIV: 417 assert(!HonorSignDependentRoundingFPMath()); 418 419 // -(X*Y) -> -X * Y 420 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 421 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 422 GetNegatedExpression(Op.getOperand(0), DAG, 423 LegalOperations, Depth+1), 424 Op.getOperand(1)); 425 426 // -(X*Y) -> X * -Y 427 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 428 Op.getOperand(0), 429 GetNegatedExpression(Op.getOperand(1), DAG, 430 LegalOperations, Depth+1)); 431 432 case ISD::FP_EXTEND: 433 case ISD::FSIN: 434 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 435 GetNegatedExpression(Op.getOperand(0), DAG, 436 LegalOperations, Depth+1)); 437 case ISD::FP_ROUND: 438 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 439 GetNegatedExpression(Op.getOperand(0), DAG, 440 LegalOperations, Depth+1), 441 Op.getOperand(1)); 442 } 443} 444 445 446// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 447// that selects between the values 1 and 0, making it equivalent to a setcc. 448// Also, set the incoming LHS, RHS, and CC references to the appropriate 449// nodes based on the type of node we are checking. This simplifies life a 450// bit for the callers. 451static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 452 SDValue &CC) { 453 if (N.getOpcode() == ISD::SETCC) { 454 LHS = N.getOperand(0); 455 RHS = N.getOperand(1); 456 CC = N.getOperand(2); 457 return true; 458 } 459 if (N.getOpcode() == ISD::SELECT_CC && 460 N.getOperand(2).getOpcode() == ISD::Constant && 461 N.getOperand(3).getOpcode() == ISD::Constant && 462 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 463 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 464 LHS = N.getOperand(0); 465 RHS = N.getOperand(1); 466 CC = N.getOperand(4); 467 return true; 468 } 469 return false; 470} 471 472// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 473// one use. If this is true, it allows the users to invert the operation for 474// free when it is profitable to do so. 475static bool isOneUseSetCC(SDValue N) { 476 SDValue N0, N1, N2; 477 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 478 return true; 479 return false; 480} 481 482SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 483 SDValue N0, SDValue N1) { 484 MVT VT = N0.getValueType(); 485 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 486 if (isa<ConstantSDNode>(N1)) { 487 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 488 SDValue OpNode = 489 DAG.FoldConstantArithmetic(Opc, VT, 490 cast<ConstantSDNode>(N0.getOperand(1)), 491 cast<ConstantSDNode>(N1)); 492 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 493 } else if (N0.hasOneUse()) { 494 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 495 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 496 N0.getOperand(0), N1); 497 AddToWorkList(OpNode.getNode()); 498 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 499 } 500 } 501 502 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 503 if (isa<ConstantSDNode>(N0)) { 504 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 505 SDValue OpNode = 506 DAG.FoldConstantArithmetic(Opc, VT, 507 cast<ConstantSDNode>(N1.getOperand(1)), 508 cast<ConstantSDNode>(N0)); 509 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 510 } else if (N1.hasOneUse()) { 511 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 512 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 513 N1.getOperand(0), N0); 514 AddToWorkList(OpNode.getNode()); 515 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 516 } 517 } 518 519 return SDValue(); 520} 521 522SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 523 bool AddTo) { 524 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 525 ++NodesCombined; 526 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 527 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 528 DOUT << " and " << NumTo-1 << " other values\n"; 529 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 530 assert(N->getValueType(i) == To[i].getValueType() && 531 "Cannot combine value to value of different type!")); 532 WorkListRemover DeadNodes(*this); 533 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 534 535 if (AddTo) { 536 // Push the new nodes and any users onto the worklist 537 for (unsigned i = 0, e = NumTo; i != e; ++i) { 538 AddToWorkList(To[i].getNode()); 539 AddUsersToWorkList(To[i].getNode()); 540 } 541 } 542 543 // Finally, if the node is now dead, remove it from the graph. The node 544 // may not be dead if the replacement process recursively simplified to 545 // something else needing this node. 546 if (N->use_empty()) { 547 // Nodes can be reintroduced into the worklist. Make sure we do not 548 // process a node that has been replaced. 549 removeFromWorkList(N); 550 551 // Finally, since the node is now dead, remove it from the graph. 552 DAG.DeleteNode(N); 553 } 554 return SDValue(N, 0); 555} 556 557void 558DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 559 TLO) { 560 // Replace all uses. If any nodes become isomorphic to other nodes and 561 // are deleted, make sure to remove them from our worklist. 562 WorkListRemover DeadNodes(*this); 563 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 564 565 // Push the new node and any (possibly new) users onto the worklist. 566 AddToWorkList(TLO.New.getNode()); 567 AddUsersToWorkList(TLO.New.getNode()); 568 569 // Finally, if the node is now dead, remove it from the graph. The node 570 // may not be dead if the replacement process recursively simplified to 571 // something else needing this node. 572 if (TLO.Old.getNode()->use_empty()) { 573 removeFromWorkList(TLO.Old.getNode()); 574 575 // If the operands of this node are only used by the node, they will now 576 // be dead. Make sure to visit them first to delete dead nodes early. 577 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 578 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 579 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 580 581 DAG.DeleteNode(TLO.Old.getNode()); 582 } 583} 584 585/// SimplifyDemandedBits - Check the specified integer node value to see if 586/// it can be simplified or if things it uses can be simplified by bit 587/// propagation. If so, return true. 588bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 589 TargetLowering::TargetLoweringOpt TLO(DAG); 590 APInt KnownZero, KnownOne; 591 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 592 return false; 593 594 // Revisit the node. 595 AddToWorkList(Op.getNode()); 596 597 // Replace the old value with the new one. 598 ++NodesCombined; 599 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 600 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 601 DOUT << '\n'; 602 603 CommitTargetLoweringOpt(TLO); 604 return true; 605} 606 607//===----------------------------------------------------------------------===// 608// Main DAG Combiner implementation 609//===----------------------------------------------------------------------===// 610 611void DAGCombiner::Run(CombineLevel AtLevel) { 612 // set the instance variables, so that the various visit routines may use it. 613 Level = AtLevel; 614 LegalOperations = Level >= NoIllegalOperations; 615 LegalTypes = Level >= NoIllegalTypes; 616 617 // Add all the dag nodes to the worklist. 618 WorkList.reserve(DAG.allnodes_size()); 619 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 620 E = DAG.allnodes_end(); I != E; ++I) 621 WorkList.push_back(I); 622 623 // Create a dummy node (which is not added to allnodes), that adds a reference 624 // to the root node, preventing it from being deleted, and tracking any 625 // changes of the root. 626 HandleSDNode Dummy(DAG.getRoot()); 627 628 // The root of the dag may dangle to deleted nodes until the dag combiner is 629 // done. Set it to null to avoid confusion. 630 DAG.setRoot(SDValue()); 631 632 // while the worklist isn't empty, inspect the node on the end of it and 633 // try and combine it. 634 while (!WorkList.empty()) { 635 SDNode *N = WorkList.back(); 636 WorkList.pop_back(); 637 638 // If N has no uses, it is dead. Make sure to revisit all N's operands once 639 // N is deleted from the DAG, since they too may now be dead or may have a 640 // reduced number of uses, allowing other xforms. 641 if (N->use_empty() && N != &Dummy) { 642 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 643 AddToWorkList(N->getOperand(i).getNode()); 644 645 DAG.DeleteNode(N); 646 continue; 647 } 648 649 SDValue RV = combine(N); 650 651 if (RV.getNode() == 0) 652 continue; 653 654 ++NodesCombined; 655 656 // If we get back the same node we passed in, rather than a new node or 657 // zero, we know that the node must have defined multiple values and 658 // CombineTo was used. Since CombineTo takes care of the worklist 659 // mechanics for us, we have no work to do in this case. 660 if (RV.getNode() == N) 661 continue; 662 663 assert(N->getOpcode() != ISD::DELETED_NODE && 664 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 665 "Node was deleted but visit returned new node!"); 666 667 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 668 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 669 DOUT << '\n'; 670 WorkListRemover DeadNodes(*this); 671 if (N->getNumValues() == RV.getNode()->getNumValues()) 672 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 673 else { 674 assert(N->getValueType(0) == RV.getValueType() && 675 N->getNumValues() == 1 && "Type mismatch"); 676 SDValue OpV = RV; 677 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 678 } 679 680 // Push the new node and any users onto the worklist 681 AddToWorkList(RV.getNode()); 682 AddUsersToWorkList(RV.getNode()); 683 684 // Add any uses of the old node to the worklist in case this node is the 685 // last one that uses them. They may become dead after this node is 686 // deleted. 687 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 688 AddToWorkList(N->getOperand(i).getNode()); 689 690 // Finally, if the node is now dead, remove it from the graph. The node 691 // may not be dead if the replacement process recursively simplified to 692 // something else needing this node. 693 if (N->use_empty()) { 694 // Nodes can be reintroduced into the worklist. Make sure we do not 695 // process a node that has been replaced. 696 removeFromWorkList(N); 697 698 // Finally, since the node is now dead, remove it from the graph. 699 DAG.DeleteNode(N); 700 } 701 } 702 703 // If the root changed (e.g. it was a dead load, update the root). 704 DAG.setRoot(Dummy.getValue()); 705} 706 707SDValue DAGCombiner::visit(SDNode *N) { 708 switch(N->getOpcode()) { 709 default: break; 710 case ISD::TokenFactor: return visitTokenFactor(N); 711 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 712 case ISD::ADD: return visitADD(N); 713 case ISD::SUB: return visitSUB(N); 714 case ISD::ADDC: return visitADDC(N); 715 case ISD::ADDE: return visitADDE(N); 716 case ISD::MUL: return visitMUL(N); 717 case ISD::SDIV: return visitSDIV(N); 718 case ISD::UDIV: return visitUDIV(N); 719 case ISD::SREM: return visitSREM(N); 720 case ISD::UREM: return visitUREM(N); 721 case ISD::MULHU: return visitMULHU(N); 722 case ISD::MULHS: return visitMULHS(N); 723 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 724 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 725 case ISD::SDIVREM: return visitSDIVREM(N); 726 case ISD::UDIVREM: return visitUDIVREM(N); 727 case ISD::AND: return visitAND(N); 728 case ISD::OR: return visitOR(N); 729 case ISD::XOR: return visitXOR(N); 730 case ISD::SHL: return visitSHL(N); 731 case ISD::SRA: return visitSRA(N); 732 case ISD::SRL: return visitSRL(N); 733 case ISD::CTLZ: return visitCTLZ(N); 734 case ISD::CTTZ: return visitCTTZ(N); 735 case ISD::CTPOP: return visitCTPOP(N); 736 case ISD::SELECT: return visitSELECT(N); 737 case ISD::SELECT_CC: return visitSELECT_CC(N); 738 case ISD::SETCC: return visitSETCC(N); 739 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 740 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 741 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 742 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 743 case ISD::TRUNCATE: return visitTRUNCATE(N); 744 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 745 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 746 case ISD::FADD: return visitFADD(N); 747 case ISD::FSUB: return visitFSUB(N); 748 case ISD::FMUL: return visitFMUL(N); 749 case ISD::FDIV: return visitFDIV(N); 750 case ISD::FREM: return visitFREM(N); 751 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 752 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 753 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 754 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 755 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 756 case ISD::FP_ROUND: return visitFP_ROUND(N); 757 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 758 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 759 case ISD::FNEG: return visitFNEG(N); 760 case ISD::FABS: return visitFABS(N); 761 case ISD::BRCOND: return visitBRCOND(N); 762 case ISD::BR_CC: return visitBR_CC(N); 763 case ISD::LOAD: return visitLOAD(N); 764 case ISD::STORE: return visitSTORE(N); 765 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 766 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 767 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 768 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 769 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 770 } 771 return SDValue(); 772} 773 774SDValue DAGCombiner::combine(SDNode *N) { 775 SDValue RV = visit(N); 776 777 // If nothing happened, try a target-specific DAG combine. 778 if (RV.getNode() == 0) { 779 assert(N->getOpcode() != ISD::DELETED_NODE && 780 "Node was deleted but visit returned NULL!"); 781 782 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 783 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 784 785 // Expose the DAG combiner to the target combiner impls. 786 TargetLowering::DAGCombinerInfo 787 DagCombineInfo(DAG, Level == Unrestricted, false, this); 788 789 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 790 } 791 } 792 793 // If N is a commutative binary node, try commuting it to enable more 794 // sdisel CSE. 795 if (RV.getNode() == 0 && 796 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 797 N->getNumValues() == 1) { 798 SDValue N0 = N->getOperand(0); 799 SDValue N1 = N->getOperand(1); 800 801 // Constant operands are canonicalized to RHS. 802 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 803 SDValue Ops[] = { N1, N0 }; 804 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 805 Ops, 2); 806 if (CSENode) 807 return SDValue(CSENode, 0); 808 } 809 } 810 811 return RV; 812} 813 814/// getInputChainForNode - Given a node, return its input chain if it has one, 815/// otherwise return a null sd operand. 816static SDValue getInputChainForNode(SDNode *N) { 817 if (unsigned NumOps = N->getNumOperands()) { 818 if (N->getOperand(0).getValueType() == MVT::Other) 819 return N->getOperand(0); 820 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 821 return N->getOperand(NumOps-1); 822 for (unsigned i = 1; i < NumOps-1; ++i) 823 if (N->getOperand(i).getValueType() == MVT::Other) 824 return N->getOperand(i); 825 } 826 return SDValue(); 827} 828 829SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 830 // If N has two operands, where one has an input chain equal to the other, 831 // the 'other' chain is redundant. 832 if (N->getNumOperands() == 2) { 833 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 834 return N->getOperand(0); 835 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 836 return N->getOperand(1); 837 } 838 839 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 840 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 841 SmallPtrSet<SDNode*, 16> SeenOps; 842 bool Changed = false; // If we should replace this token factor. 843 844 // Start out with this token factor. 845 TFs.push_back(N); 846 847 // Iterate through token factors. The TFs grows when new token factors are 848 // encountered. 849 for (unsigned i = 0; i < TFs.size(); ++i) { 850 SDNode *TF = TFs[i]; 851 852 // Check each of the operands. 853 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 854 SDValue Op = TF->getOperand(i); 855 856 switch (Op.getOpcode()) { 857 case ISD::EntryToken: 858 // Entry tokens don't need to be added to the list. They are 859 // rededundant. 860 Changed = true; 861 break; 862 863 case ISD::TokenFactor: 864 if ((CombinerAA || Op.hasOneUse()) && 865 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 866 // Queue up for processing. 867 TFs.push_back(Op.getNode()); 868 // Clean up in case the token factor is removed. 869 AddToWorkList(Op.getNode()); 870 Changed = true; 871 break; 872 } 873 // Fall thru 874 875 default: 876 // Only add if it isn't already in the list. 877 if (SeenOps.insert(Op.getNode())) 878 Ops.push_back(Op); 879 else 880 Changed = true; 881 break; 882 } 883 } 884 } 885 886 SDValue Result; 887 888 // If we've change things around then replace token factor. 889 if (Changed) { 890 if (Ops.empty()) { 891 // The entry token is the only possible outcome. 892 Result = DAG.getEntryNode(); 893 } else { 894 // New and improved token factor. 895 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 896 MVT::Other, &Ops[0], Ops.size()); 897 } 898 899 // Don't add users to work list. 900 return CombineTo(N, Result, false); 901 } 902 903 return Result; 904} 905 906/// MERGE_VALUES can always be eliminated. 907SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 908 WorkListRemover DeadNodes(*this); 909 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 910 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 911 &DeadNodes); 912 removeFromWorkList(N); 913 DAG.DeleteNode(N); 914 return SDValue(N, 0); // Return N so it doesn't get rechecked! 915} 916 917static 918SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 919 SelectionDAG &DAG) { 920 MVT VT = N0.getValueType(); 921 SDValue N00 = N0.getOperand(0); 922 SDValue N01 = N0.getOperand(1); 923 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 924 925 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 926 isa<ConstantSDNode>(N00.getOperand(1))) { 927 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 928 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 929 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 930 N00.getOperand(0), N01), 931 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 932 N00.getOperand(1), N01)); 933 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 934 } 935 936 return SDValue(); 937} 938 939static 940SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 941 SelectionDAG &DAG, const TargetLowering &TLI, 942 bool LegalOperations) { 943 MVT VT = N->getValueType(0); 944 unsigned Opc = N->getOpcode(); 945 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 946 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 947 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 948 ISD::CondCode CC = ISD::SETCC_INVALID; 949 950 if (isSlctCC) { 951 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 952 } else { 953 SDValue CCOp = Slct.getOperand(0); 954 if (CCOp.getOpcode() == ISD::SETCC) 955 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 956 } 957 958 bool DoXform = false; 959 bool InvCC = false; 960 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 961 "Bad input!"); 962 963 if (LHS.getOpcode() == ISD::Constant && 964 cast<ConstantSDNode>(LHS)->isNullValue()) { 965 DoXform = true; 966 } else if (CC != ISD::SETCC_INVALID && 967 RHS.getOpcode() == ISD::Constant && 968 cast<ConstantSDNode>(RHS)->isNullValue()) { 969 std::swap(LHS, RHS); 970 SDValue Op0 = Slct.getOperand(0); 971 MVT OpVT = isSlctCC ? Op0.getValueType() : 972 Op0.getOperand(0).getValueType(); 973 bool isInt = OpVT.isInteger(); 974 CC = ISD::getSetCCInverse(CC, isInt); 975 976 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT)) 977 return SDValue(); // Inverse operator isn't legal. 978 979 DoXform = true; 980 InvCC = true; 981 } 982 983 if (DoXform) { 984 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 985 if (isSlctCC) 986 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 987 Slct.getOperand(0), Slct.getOperand(1), CC); 988 SDValue CCOp = Slct.getOperand(0); 989 if (InvCC) 990 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 991 CCOp.getOperand(0), CCOp.getOperand(1), CC); 992 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 993 CCOp, OtherOp, Result); 994 } 995 return SDValue(); 996} 997 998SDValue DAGCombiner::visitADD(SDNode *N) { 999 SDValue N0 = N->getOperand(0); 1000 SDValue N1 = N->getOperand(1); 1001 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1002 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1003 MVT VT = N0.getValueType(); 1004 1005 // fold vector ops 1006 if (VT.isVector()) { 1007 SDValue FoldedVOp = SimplifyVBinOp(N); 1008 if (FoldedVOp.getNode()) return FoldedVOp; 1009 } 1010 1011 // fold (add x, undef) -> undef 1012 if (N0.getOpcode() == ISD::UNDEF) 1013 return N0; 1014 if (N1.getOpcode() == ISD::UNDEF) 1015 return N1; 1016 // fold (add c1, c2) -> c1+c2 1017 if (N0C && N1C) 1018 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1019 // canonicalize constant to RHS 1020 if (N0C && !N1C) 1021 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1022 // fold (add x, 0) -> x 1023 if (N1C && N1C->isNullValue()) 1024 return N0; 1025 // fold (add Sym, c) -> Sym+c 1026 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1027 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1028 GA->getOpcode() == ISD::GlobalAddress) 1029 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1030 GA->getOffset() + 1031 (uint64_t)N1C->getSExtValue()); 1032 // fold ((c1-A)+c2) -> (c1+c2)-A 1033 if (N1C && N0.getOpcode() == ISD::SUB) 1034 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1035 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1036 DAG.getConstant(N1C->getAPIntValue()+ 1037 N0C->getAPIntValue(), VT), 1038 N0.getOperand(1)); 1039 // reassociate add 1040 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1041 if (RADD.getNode() != 0) 1042 return RADD; 1043 // fold ((0-A) + B) -> B-A 1044 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1045 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1046 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1047 // fold (A + (0-B)) -> A-B 1048 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1049 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1050 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1051 // fold (A+(B-A)) -> B 1052 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1053 return N1.getOperand(0); 1054 // fold ((B-A)+A) -> B 1055 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1056 return N0.getOperand(0); 1057 // fold (A+(B-(A+C))) to (B-C) 1058 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1059 N0 == N1.getOperand(1).getOperand(0)) 1060 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1061 N1.getOperand(1).getOperand(1)); 1062 // fold (A+(B-(C+A))) to (B-C) 1063 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1064 N0 == N1.getOperand(1).getOperand(1)) 1065 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1066 N1.getOperand(1).getOperand(0)); 1067 // fold (A+((B-A)+or-C)) to (B+or-C) 1068 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1069 N1.getOperand(0).getOpcode() == ISD::SUB && 1070 N0 == N1.getOperand(0).getOperand(1)) 1071 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1072 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1073 1074 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1075 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1076 SDValue N00 = N0.getOperand(0); 1077 SDValue N01 = N0.getOperand(1); 1078 SDValue N10 = N1.getOperand(0); 1079 SDValue N11 = N1.getOperand(1); 1080 1081 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1082 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1083 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1084 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1085 } 1086 1087 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1088 return SDValue(N, 0); 1089 1090 // fold (a+b) -> (a|b) iff a and b share no bits. 1091 if (VT.isInteger() && !VT.isVector()) { 1092 APInt LHSZero, LHSOne; 1093 APInt RHSZero, RHSOne; 1094 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1095 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1096 1097 if (LHSZero.getBoolValue()) { 1098 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1099 1100 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1101 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1102 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1103 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1104 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1105 } 1106 } 1107 1108 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1109 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1110 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1111 if (Result.getNode()) return Result; 1112 } 1113 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1114 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1115 if (Result.getNode()) return Result; 1116 } 1117 1118 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1119 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1120 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations); 1121 if (Result.getNode()) return Result; 1122 } 1123 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1124 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1125 if (Result.getNode()) return Result; 1126 } 1127 1128 return SDValue(); 1129} 1130 1131SDValue DAGCombiner::visitADDC(SDNode *N) { 1132 SDValue N0 = N->getOperand(0); 1133 SDValue N1 = N->getOperand(1); 1134 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1135 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1136 MVT VT = N0.getValueType(); 1137 1138 // If the flag result is dead, turn this into an ADD. 1139 if (N->hasNUsesOfValue(0, 1)) 1140 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1141 DAG.getNode(ISD::CARRY_FALSE, 1142 N->getDebugLoc(), MVT::Flag)); 1143 1144 // canonicalize constant to RHS. 1145 if (N0C && !N1C) 1146 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1147 1148 // fold (addc x, 0) -> x + no carry out 1149 if (N1C && N1C->isNullValue()) 1150 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1151 N->getDebugLoc(), MVT::Flag)); 1152 1153 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1154 APInt LHSZero, LHSOne; 1155 APInt RHSZero, RHSOne; 1156 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1157 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1158 1159 if (LHSZero.getBoolValue()) { 1160 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1161 1162 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1163 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1164 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1165 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1166 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1167 DAG.getNode(ISD::CARRY_FALSE, 1168 N->getDebugLoc(), MVT::Flag)); 1169 } 1170 1171 return SDValue(); 1172} 1173 1174SDValue DAGCombiner::visitADDE(SDNode *N) { 1175 SDValue N0 = N->getOperand(0); 1176 SDValue N1 = N->getOperand(1); 1177 SDValue CarryIn = N->getOperand(2); 1178 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1179 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1180 1181 // canonicalize constant to RHS 1182 if (N0C && !N1C) 1183 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1184 N1, N0, CarryIn); 1185 1186 // fold (adde x, y, false) -> (addc x, y) 1187 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1188 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1189 1190 return SDValue(); 1191} 1192 1193SDValue DAGCombiner::visitSUB(SDNode *N) { 1194 SDValue N0 = N->getOperand(0); 1195 SDValue N1 = N->getOperand(1); 1196 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1197 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1198 MVT VT = N0.getValueType(); 1199 1200 // fold vector ops 1201 if (VT.isVector()) { 1202 SDValue FoldedVOp = SimplifyVBinOp(N); 1203 if (FoldedVOp.getNode()) return FoldedVOp; 1204 } 1205 1206 // fold (sub x, x) -> 0 1207 if (N0 == N1) 1208 return DAG.getConstant(0, N->getValueType(0)); 1209 // fold (sub c1, c2) -> c1-c2 1210 if (N0C && N1C) 1211 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1212 // fold (sub x, c) -> (add x, -c) 1213 if (N1C) 1214 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1215 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1216 // fold (A+B)-A -> B 1217 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1218 return N0.getOperand(1); 1219 // fold (A+B)-B -> A 1220 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1221 return N0.getOperand(0); 1222 // fold ((A+(B+or-C))-B) -> A+or-C 1223 if (N0.getOpcode() == ISD::ADD && 1224 (N0.getOperand(1).getOpcode() == ISD::SUB || 1225 N0.getOperand(1).getOpcode() == ISD::ADD) && 1226 N0.getOperand(1).getOperand(0) == N1) 1227 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1228 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1229 // fold ((A+(C+B))-B) -> A+C 1230 if (N0.getOpcode() == ISD::ADD && 1231 N0.getOperand(1).getOpcode() == ISD::ADD && 1232 N0.getOperand(1).getOperand(1) == N1) 1233 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1234 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1235 // fold ((A-(B-C))-C) -> A-B 1236 if (N0.getOpcode() == ISD::SUB && 1237 N0.getOperand(1).getOpcode() == ISD::SUB && 1238 N0.getOperand(1).getOperand(1) == N1) 1239 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1240 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1241 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1242 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1243 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1244 if (Result.getNode()) return Result; 1245 } 1246 1247 // If either operand of a sub is undef, the result is undef 1248 if (N0.getOpcode() == ISD::UNDEF) 1249 return N0; 1250 if (N1.getOpcode() == ISD::UNDEF) 1251 return N1; 1252 1253 // If the relocation model supports it, consider symbol offsets. 1254 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1255 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1256 // fold (sub Sym, c) -> Sym-c 1257 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1258 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1259 GA->getOffset() - 1260 (uint64_t)N1C->getSExtValue()); 1261 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1262 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1263 if (GA->getGlobal() == GB->getGlobal()) 1264 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1265 VT); 1266 } 1267 1268 return SDValue(); 1269} 1270 1271SDValue DAGCombiner::visitMUL(SDNode *N) { 1272 SDValue N0 = N->getOperand(0); 1273 SDValue N1 = N->getOperand(1); 1274 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1275 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1276 MVT VT = N0.getValueType(); 1277 1278 // fold vector ops 1279 if (VT.isVector()) { 1280 SDValue FoldedVOp = SimplifyVBinOp(N); 1281 if (FoldedVOp.getNode()) return FoldedVOp; 1282 } 1283 1284 // fold (mul x, undef) -> 0 1285 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1286 return DAG.getConstant(0, VT); 1287 // fold (mul c1, c2) -> c1*c2 1288 if (N0C && N1C) 1289 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1290 // canonicalize constant to RHS 1291 if (N0C && !N1C) 1292 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1293 // fold (mul x, 0) -> 0 1294 if (N1C && N1C->isNullValue()) 1295 return N1; 1296 // fold (mul x, -1) -> 0-x 1297 if (N1C && N1C->isAllOnesValue()) 1298 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1299 DAG.getConstant(0, VT), N0); 1300 // fold (mul x, (1 << c)) -> x << c 1301 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1302 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1303 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1304 TLI.getShiftAmountTy())); 1305 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1306 if (N1C && isPowerOf2_64(-N1C->getSExtValue())) 1307 // FIXME: If the input is something that is easily negated (e.g. a 1308 // single-use add), we should put the negate there. 1309 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1310 DAG.getConstant(0, VT), 1311 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1312 DAG.getConstant(Log2_64(-N1C->getSExtValue()), 1313 TLI.getShiftAmountTy()))); 1314 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1315 if (N1C && N0.getOpcode() == ISD::SHL && 1316 isa<ConstantSDNode>(N0.getOperand(1))) { 1317 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1318 N1, N0.getOperand(1)); 1319 AddToWorkList(C3.getNode()); 1320 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1321 N0.getOperand(0), C3); 1322 } 1323 1324 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1325 // use. 1326 { 1327 SDValue Sh(0,0), Y(0,0); 1328 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1329 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1330 N0.getNode()->hasOneUse()) { 1331 Sh = N0; Y = N1; 1332 } else if (N1.getOpcode() == ISD::SHL && 1333 isa<ConstantSDNode>(N1.getOperand(1)) && 1334 N1.getNode()->hasOneUse()) { 1335 Sh = N1; Y = N0; 1336 } 1337 1338 if (Sh.getNode()) { 1339 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1340 Sh.getOperand(0), Y); 1341 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1342 Mul, Sh.getOperand(1)); 1343 } 1344 } 1345 1346 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1347 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1348 isa<ConstantSDNode>(N0.getOperand(1))) 1349 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1350 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1351 N0.getOperand(0), N1), 1352 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1353 N0.getOperand(1), N1)); 1354 1355 // reassociate mul 1356 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1357 if (RMUL.getNode() != 0) 1358 return RMUL; 1359 1360 return SDValue(); 1361} 1362 1363SDValue DAGCombiner::visitSDIV(SDNode *N) { 1364 SDValue N0 = N->getOperand(0); 1365 SDValue N1 = N->getOperand(1); 1366 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1367 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1368 MVT VT = N->getValueType(0); 1369 1370 // fold vector ops 1371 if (VT.isVector()) { 1372 SDValue FoldedVOp = SimplifyVBinOp(N); 1373 if (FoldedVOp.getNode()) return FoldedVOp; 1374 } 1375 1376 // fold (sdiv c1, c2) -> c1/c2 1377 if (N0C && N1C && !N1C->isNullValue()) 1378 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1379 // fold (sdiv X, 1) -> X 1380 if (N1C && N1C->getSExtValue() == 1LL) 1381 return N0; 1382 // fold (sdiv X, -1) -> 0-X 1383 if (N1C && N1C->isAllOnesValue()) 1384 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1385 DAG.getConstant(0, VT), N0); 1386 // If we know the sign bits of both operands are zero, strength reduce to a 1387 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1388 if (!VT.isVector()) { 1389 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1390 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1391 N0, N1); 1392 } 1393 // fold (sdiv X, pow2) -> simple ops after legalize 1394 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1395 (isPowerOf2_64(N1C->getSExtValue()) || 1396 isPowerOf2_64(-N1C->getSExtValue()))) { 1397 // If dividing by powers of two is cheap, then don't perform the following 1398 // fold. 1399 if (TLI.isPow2DivCheap()) 1400 return SDValue(); 1401 1402 int64_t pow2 = N1C->getSExtValue(); 1403 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1404 unsigned lg2 = Log2_64(abs2); 1405 1406 // Splat the sign bit into the register 1407 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1408 DAG.getConstant(VT.getSizeInBits()-1, 1409 TLI.getShiftAmountTy())); 1410 AddToWorkList(SGN.getNode()); 1411 1412 // Add (N0 < 0) ? abs2 - 1 : 0; 1413 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1414 DAG.getConstant(VT.getSizeInBits() - lg2, 1415 TLI.getShiftAmountTy())); 1416 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1417 AddToWorkList(SRL.getNode()); 1418 AddToWorkList(ADD.getNode()); // Divide by pow2 1419 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1420 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1421 1422 // If we're dividing by a positive value, we're done. Otherwise, we must 1423 // negate the result. 1424 if (pow2 > 0) 1425 return SRA; 1426 1427 AddToWorkList(SRA.getNode()); 1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1429 DAG.getConstant(0, VT), SRA); 1430 } 1431 1432 // if integer divide is expensive and we satisfy the requirements, emit an 1433 // alternate sequence. 1434 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1435 !TLI.isIntDivCheap()) { 1436 SDValue Op = BuildSDIV(N); 1437 if (Op.getNode()) return Op; 1438 } 1439 1440 // undef / X -> 0 1441 if (N0.getOpcode() == ISD::UNDEF) 1442 return DAG.getConstant(0, VT); 1443 // X / undef -> undef 1444 if (N1.getOpcode() == ISD::UNDEF) 1445 return N1; 1446 1447 return SDValue(); 1448} 1449 1450SDValue DAGCombiner::visitUDIV(SDNode *N) { 1451 SDValue N0 = N->getOperand(0); 1452 SDValue N1 = N->getOperand(1); 1453 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1454 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1455 MVT VT = N->getValueType(0); 1456 1457 // fold vector ops 1458 if (VT.isVector()) { 1459 SDValue FoldedVOp = SimplifyVBinOp(N); 1460 if (FoldedVOp.getNode()) return FoldedVOp; 1461 } 1462 1463 // fold (udiv c1, c2) -> c1/c2 1464 if (N0C && N1C && !N1C->isNullValue()) 1465 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1466 // fold (udiv x, (1 << c)) -> x >>u c 1467 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1468 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1469 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1470 TLI.getShiftAmountTy())); 1471 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1472 if (N1.getOpcode() == ISD::SHL) { 1473 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1474 if (SHC->getAPIntValue().isPowerOf2()) { 1475 MVT ADDVT = N1.getOperand(1).getValueType(); 1476 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1477 N1.getOperand(1), 1478 DAG.getConstant(SHC->getAPIntValue() 1479 .logBase2(), 1480 ADDVT)); 1481 AddToWorkList(Add.getNode()); 1482 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1483 } 1484 } 1485 } 1486 // fold (udiv x, c) -> alternate 1487 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1488 SDValue Op = BuildUDIV(N); 1489 if (Op.getNode()) return Op; 1490 } 1491 1492 // undef / X -> 0 1493 if (N0.getOpcode() == ISD::UNDEF) 1494 return DAG.getConstant(0, VT); 1495 // X / undef -> undef 1496 if (N1.getOpcode() == ISD::UNDEF) 1497 return N1; 1498 1499 return SDValue(); 1500} 1501 1502SDValue DAGCombiner::visitSREM(SDNode *N) { 1503 SDValue N0 = N->getOperand(0); 1504 SDValue N1 = N->getOperand(1); 1505 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1506 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1507 MVT VT = N->getValueType(0); 1508 1509 // fold (srem c1, c2) -> c1%c2 1510 if (N0C && N1C && !N1C->isNullValue()) 1511 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1512 // If we know the sign bits of both operands are zero, strength reduce to a 1513 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1514 if (!VT.isVector()) { 1515 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1516 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1517 } 1518 1519 // If X/C can be simplified by the division-by-constant logic, lower 1520 // X%C to the equivalent of X-X/C*C. 1521 if (N1C && !N1C->isNullValue()) { 1522 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1523 AddToWorkList(Div.getNode()); 1524 SDValue OptimizedDiv = combine(Div.getNode()); 1525 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1526 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1527 OptimizedDiv, N1); 1528 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1529 AddToWorkList(Mul.getNode()); 1530 return Sub; 1531 } 1532 } 1533 1534 // undef % X -> 0 1535 if (N0.getOpcode() == ISD::UNDEF) 1536 return DAG.getConstant(0, VT); 1537 // X % undef -> undef 1538 if (N1.getOpcode() == ISD::UNDEF) 1539 return N1; 1540 1541 return SDValue(); 1542} 1543 1544SDValue DAGCombiner::visitUREM(SDNode *N) { 1545 SDValue N0 = N->getOperand(0); 1546 SDValue N1 = N->getOperand(1); 1547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1549 MVT VT = N->getValueType(0); 1550 1551 // fold (urem c1, c2) -> c1%c2 1552 if (N0C && N1C && !N1C->isNullValue()) 1553 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1554 // fold (urem x, pow2) -> (and x, pow2-1) 1555 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1556 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1557 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1558 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1559 if (N1.getOpcode() == ISD::SHL) { 1560 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1561 if (SHC->getAPIntValue().isPowerOf2()) { 1562 SDValue Add = 1563 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1564 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1565 VT)); 1566 AddToWorkList(Add.getNode()); 1567 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1568 } 1569 } 1570 } 1571 1572 // If X/C can be simplified by the division-by-constant logic, lower 1573 // X%C to the equivalent of X-X/C*C. 1574 if (N1C && !N1C->isNullValue()) { 1575 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1576 AddToWorkList(Div.getNode()); 1577 SDValue OptimizedDiv = combine(Div.getNode()); 1578 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1579 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1580 OptimizedDiv, N1); 1581 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1582 AddToWorkList(Mul.getNode()); 1583 return Sub; 1584 } 1585 } 1586 1587 // undef % X -> 0 1588 if (N0.getOpcode() == ISD::UNDEF) 1589 return DAG.getConstant(0, VT); 1590 // X % undef -> undef 1591 if (N1.getOpcode() == ISD::UNDEF) 1592 return N1; 1593 1594 return SDValue(); 1595} 1596 1597SDValue DAGCombiner::visitMULHS(SDNode *N) { 1598 SDValue N0 = N->getOperand(0); 1599 SDValue N1 = N->getOperand(1); 1600 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1601 MVT VT = N->getValueType(0); 1602 1603 // fold (mulhs x, 0) -> 0 1604 if (N1C && N1C->isNullValue()) 1605 return N1; 1606 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1607 if (N1C && N1C->getAPIntValue() == 1) 1608 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1609 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1610 TLI.getShiftAmountTy())); 1611 // fold (mulhs x, undef) -> 0 1612 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1613 return DAG.getConstant(0, VT); 1614 1615 return SDValue(); 1616} 1617 1618SDValue DAGCombiner::visitMULHU(SDNode *N) { 1619 SDValue N0 = N->getOperand(0); 1620 SDValue N1 = N->getOperand(1); 1621 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1622 MVT VT = N->getValueType(0); 1623 1624 // fold (mulhu x, 0) -> 0 1625 if (N1C && N1C->isNullValue()) 1626 return N1; 1627 // fold (mulhu x, 1) -> 0 1628 if (N1C && N1C->getAPIntValue() == 1) 1629 return DAG.getConstant(0, N0.getValueType()); 1630 // fold (mulhu x, undef) -> 0 1631 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1632 return DAG.getConstant(0, VT); 1633 1634 return SDValue(); 1635} 1636 1637/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1638/// compute two values. LoOp and HiOp give the opcodes for the two computations 1639/// that are being performed. Return true if a simplification was made. 1640/// 1641SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1642 unsigned HiOp) { 1643 // If the high half is not needed, just compute the low half. 1644 bool HiExists = N->hasAnyUseOfValue(1); 1645 if (!HiExists && 1646 (!LegalOperations || 1647 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1648 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1649 N->op_begin(), N->getNumOperands()); 1650 return CombineTo(N, Res, Res); 1651 } 1652 1653 // If the low half is not needed, just compute the high half. 1654 bool LoExists = N->hasAnyUseOfValue(0); 1655 if (!LoExists && 1656 (!LegalOperations || 1657 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1658 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1659 N->op_begin(), N->getNumOperands()); 1660 return CombineTo(N, Res, Res); 1661 } 1662 1663 // If both halves are used, return as it is. 1664 if (LoExists && HiExists) 1665 return SDValue(); 1666 1667 // If the two computed results can be simplified separately, separate them. 1668 if (LoExists) { 1669 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1670 N->op_begin(), N->getNumOperands()); 1671 AddToWorkList(Lo.getNode()); 1672 SDValue LoOpt = combine(Lo.getNode()); 1673 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1674 (!LegalOperations || 1675 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1676 return CombineTo(N, LoOpt, LoOpt); 1677 } 1678 1679 if (HiExists) { 1680 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1681 N->op_begin(), N->getNumOperands()); 1682 AddToWorkList(Hi.getNode()); 1683 SDValue HiOpt = combine(Hi.getNode()); 1684 if (HiOpt.getNode() && HiOpt != Hi && 1685 (!LegalOperations || 1686 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1687 return CombineTo(N, HiOpt, HiOpt); 1688 } 1689 1690 return SDValue(); 1691} 1692 1693SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1694 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1695 if (Res.getNode()) return Res; 1696 1697 return SDValue(); 1698} 1699 1700SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1701 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1702 if (Res.getNode()) return Res; 1703 1704 return SDValue(); 1705} 1706 1707SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1708 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1709 if (Res.getNode()) return Res; 1710 1711 return SDValue(); 1712} 1713 1714SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1715 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1716 if (Res.getNode()) return Res; 1717 1718 return SDValue(); 1719} 1720 1721/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1722/// two operands of the same opcode, try to simplify it. 1723SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1724 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1725 MVT VT = N0.getValueType(); 1726 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1727 1728 // For each of OP in AND/OR/XOR: 1729 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1730 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1731 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1732 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1733 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1734 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1735 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1736 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1737 N0.getOperand(0).getValueType(), 1738 N0.getOperand(0), N1.getOperand(0)); 1739 AddToWorkList(ORNode.getNode()); 1740 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1741 } 1742 1743 // For each of OP in SHL/SRL/SRA/AND... 1744 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1745 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1746 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1747 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1748 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1749 N0.getOperand(1) == N1.getOperand(1)) { 1750 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1751 N0.getOperand(0).getValueType(), 1752 N0.getOperand(0), N1.getOperand(0)); 1753 AddToWorkList(ORNode.getNode()); 1754 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1755 ORNode, N0.getOperand(1)); 1756 } 1757 1758 return SDValue(); 1759} 1760 1761SDValue DAGCombiner::visitAND(SDNode *N) { 1762 SDValue N0 = N->getOperand(0); 1763 SDValue N1 = N->getOperand(1); 1764 SDValue LL, LR, RL, RR, CC0, CC1; 1765 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1767 MVT VT = N1.getValueType(); 1768 unsigned BitWidth = VT.getSizeInBits(); 1769 1770 // fold vector ops 1771 if (VT.isVector()) { 1772 SDValue FoldedVOp = SimplifyVBinOp(N); 1773 if (FoldedVOp.getNode()) return FoldedVOp; 1774 } 1775 1776 // fold (and x, undef) -> 0 1777 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1778 return DAG.getConstant(0, VT); 1779 // fold (and c1, c2) -> c1&c2 1780 if (N0C && N1C) 1781 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1782 // canonicalize constant to RHS 1783 if (N0C && !N1C) 1784 return DAG.getNode(ISD::AND, VT, N1, N0); 1785 // fold (and x, -1) -> x 1786 if (N1C && N1C->isAllOnesValue()) 1787 return N0; 1788 // if (and x, c) is known to be zero, return 0 1789 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1790 APInt::getAllOnesValue(BitWidth))) 1791 return DAG.getConstant(0, VT); 1792 // reassociate and 1793 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1794 if (RAND.getNode() != 0) 1795 return RAND; 1796 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1797 if (N1C && N0.getOpcode() == ISD::OR) 1798 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1799 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1800 return N1; 1801 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1802 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1803 SDValue N0Op0 = N0.getOperand(0); 1804 APInt Mask = ~N1C->getAPIntValue(); 1805 Mask.trunc(N0Op0.getValueSizeInBits()); 1806 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1807 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1808 N0.getValueType(), N0Op0); 1809 1810 // Replace uses of the AND with uses of the Zero extend node. 1811 CombineTo(N, Zext); 1812 1813 // We actually want to replace all uses of the any_extend with the 1814 // zero_extend, to avoid duplicating things. This will later cause this 1815 // AND to be folded. 1816 CombineTo(N0.getNode(), Zext); 1817 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1818 } 1819 } 1820 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1821 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1822 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1823 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1824 1825 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1826 LL.getValueType().isInteger()) { 1827 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1828 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1829 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1830 LR.getValueType(), LL, RL); 1831 AddToWorkList(ORNode.getNode()); 1832 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1833 } 1834 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1835 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1836 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1837 LR.getValueType(), LL, RL); 1838 AddToWorkList(ANDNode.getNode()); 1839 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1840 } 1841 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1842 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1843 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1844 LR.getValueType(), LL, RL); 1845 AddToWorkList(ORNode.getNode()); 1846 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1847 } 1848 } 1849 // canonicalize equivalent to ll == rl 1850 if (LL == RR && LR == RL) { 1851 Op1 = ISD::getSetCCSwappedOperands(Op1); 1852 std::swap(RL, RR); 1853 } 1854 if (LL == RL && LR == RR) { 1855 bool isInteger = LL.getValueType().isInteger(); 1856 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1857 if (Result != ISD::SETCC_INVALID && 1858 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1859 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1860 LL, LR, Result); 1861 } 1862 } 1863 1864 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1865 if (N0.getOpcode() == N1.getOpcode()) { 1866 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1867 if (Tmp.getNode()) return Tmp; 1868 } 1869 1870 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1871 // fold (and (sra)) -> (and (srl)) when possible. 1872 if (!VT.isVector() && 1873 SimplifyDemandedBits(SDValue(N, 0))) 1874 return SDValue(N, 0); 1875 // fold (zext_inreg (extload x)) -> (zextload x) 1876 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1877 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1878 MVT EVT = LN0->getMemoryVT(); 1879 // If we zero all the possible extended bits, then we can turn this into 1880 // a zextload if we are running before legalize or the operation is legal. 1881 unsigned BitWidth = N1.getValueSizeInBits(); 1882 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1883 BitWidth - EVT.getSizeInBits())) && 1884 ((!LegalOperations && !LN0->isVolatile()) || 1885 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1886 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1887 LN0->getChain(), LN0->getBasePtr(), 1888 LN0->getSrcValue(), 1889 LN0->getSrcValueOffset(), EVT, 1890 LN0->isVolatile(), LN0->getAlignment()); 1891 AddToWorkList(N); 1892 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1893 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1894 } 1895 } 1896 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1897 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1898 N0.hasOneUse()) { 1899 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1900 MVT EVT = LN0->getMemoryVT(); 1901 // If we zero all the possible extended bits, then we can turn this into 1902 // a zextload if we are running before legalize or the operation is legal. 1903 unsigned BitWidth = N1.getValueSizeInBits(); 1904 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1905 BitWidth - EVT.getSizeInBits())) && 1906 ((!LegalOperations && !LN0->isVolatile()) || 1907 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1908 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1909 LN0->getChain(), 1910 LN0->getBasePtr(), LN0->getSrcValue(), 1911 LN0->getSrcValueOffset(), EVT, 1912 LN0->isVolatile(), LN0->getAlignment()); 1913 AddToWorkList(N); 1914 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1915 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1916 } 1917 } 1918 1919 // fold (and (load x), 255) -> (zextload x, i8) 1920 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1921 if (N1C && N0.getOpcode() == ISD::LOAD) { 1922 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1923 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1924 LN0->isUnindexed() && N0.hasOneUse() && 1925 // Do not change the width of a volatile load. 1926 !LN0->isVolatile()) { 1927 MVT EVT = MVT::Other; 1928 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1929 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1930 EVT = MVT::getIntegerVT(ActiveBits); 1931 1932 MVT LoadedVT = LN0->getMemoryVT(); 1933 1934 // Do not generate loads of non-round integer types since these can 1935 // be expensive (and would be wrong if the type is not byte sized). 1936 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1937 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1938 MVT PtrType = N0.getOperand(1).getValueType(); 1939 1940 // For big endian targets, we need to add an offset to the pointer to 1941 // load the correct bytes. For little endian systems, we merely need to 1942 // read fewer bytes from the same pointer. 1943 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1944 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1945 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1946 unsigned Alignment = LN0->getAlignment(); 1947 SDValue NewPtr = LN0->getBasePtr(); 1948 1949 if (TLI.isBigEndian()) { 1950 NewPtr = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), PtrType, 1951 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1952 Alignment = MinAlign(Alignment, PtrOff); 1953 } 1954 1955 AddToWorkList(NewPtr.getNode()); 1956 SDValue Load = 1957 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1958 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1959 EVT, LN0->isVolatile(), Alignment); 1960 AddToWorkList(N); 1961 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1962 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1963 } 1964 } 1965 } 1966 1967 return SDValue(); 1968} 1969 1970SDValue DAGCombiner::visitOR(SDNode *N) { 1971 SDValue N0 = N->getOperand(0); 1972 SDValue N1 = N->getOperand(1); 1973 SDValue LL, LR, RL, RR, CC0, CC1; 1974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1976 MVT VT = N1.getValueType(); 1977 1978 // fold vector ops 1979 if (VT.isVector()) { 1980 SDValue FoldedVOp = SimplifyVBinOp(N); 1981 if (FoldedVOp.getNode()) return FoldedVOp; 1982 } 1983 1984 // fold (or x, undef) -> -1 1985 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1986 return DAG.getConstant(~0ULL, VT); 1987 // fold (or c1, c2) -> c1|c2 1988 if (N0C && N1C) 1989 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1990 // canonicalize constant to RHS 1991 if (N0C && !N1C) 1992 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1993 // fold (or x, 0) -> x 1994 if (N1C && N1C->isNullValue()) 1995 return N0; 1996 // fold (or x, -1) -> -1 1997 if (N1C && N1C->isAllOnesValue()) 1998 return N1; 1999 // fold (or x, c) -> c iff (x & ~c) == 0 2000 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2001 return N1; 2002 // reassociate or 2003 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2004 if (ROR.getNode() != 0) 2005 return ROR; 2006 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2007 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2008 isa<ConstantSDNode>(N0.getOperand(1))) { 2009 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2010 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2011 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2012 N0.getOperand(0), N1), 2013 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2014 } 2015 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2016 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2017 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2018 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2019 2020 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2021 LL.getValueType().isInteger()) { 2022 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2023 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2024 if (cast<ConstantSDNode>(LR)->isNullValue() && 2025 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2026 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2027 LR.getValueType(), LL, RL); 2028 AddToWorkList(ORNode.getNode()); 2029 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2030 } 2031 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2032 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2033 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2034 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2035 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2036 LR.getValueType(), LL, RL); 2037 AddToWorkList(ANDNode.getNode()); 2038 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2039 } 2040 } 2041 // canonicalize equivalent to ll == rl 2042 if (LL == RR && LR == RL) { 2043 Op1 = ISD::getSetCCSwappedOperands(Op1); 2044 std::swap(RL, RR); 2045 } 2046 if (LL == RL && LR == RR) { 2047 bool isInteger = LL.getValueType().isInteger(); 2048 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2049 if (Result != ISD::SETCC_INVALID && 2050 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2051 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2052 LL, LR, Result); 2053 } 2054 } 2055 2056 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2057 if (N0.getOpcode() == N1.getOpcode()) { 2058 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2059 if (Tmp.getNode()) return Tmp; 2060 } 2061 2062 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2063 if (N0.getOpcode() == ISD::AND && 2064 N1.getOpcode() == ISD::AND && 2065 N0.getOperand(1).getOpcode() == ISD::Constant && 2066 N1.getOperand(1).getOpcode() == ISD::Constant && 2067 // Don't increase # computations. 2068 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2069 // We can only do this xform if we know that bits from X that are set in C2 2070 // but not in C1 are already zero. Likewise for Y. 2071 const APInt &LHSMask = 2072 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2073 const APInt &RHSMask = 2074 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2075 2076 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2077 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2078 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2079 N0.getOperand(0), N1.getOperand(0)); 2080 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2081 DAG.getConstant(LHSMask | RHSMask, VT)); 2082 } 2083 } 2084 2085 // See if this is some rotate idiom. 2086 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2087 return SDValue(Rot, 0); 2088 2089 return SDValue(); 2090} 2091 2092/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2093static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2094 if (Op.getOpcode() == ISD::AND) { 2095 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2096 Mask = Op.getOperand(1); 2097 Op = Op.getOperand(0); 2098 } else { 2099 return false; 2100 } 2101 } 2102 2103 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2104 Shift = Op; 2105 return true; 2106 } 2107 2108 return false; 2109} 2110 2111// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2112// idioms for rotate, and if the target supports rotation instructions, generate 2113// a rot[lr]. 2114SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2115 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2116 MVT VT = LHS.getValueType(); 2117 if (!TLI.isTypeLegal(VT)) return 0; 2118 2119 // The target must have at least one rotate flavor. 2120 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2121 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2122 if (!HasROTL && !HasROTR) return 0; 2123 2124 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2125 SDValue LHSShift; // The shift. 2126 SDValue LHSMask; // AND value if any. 2127 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2128 return 0; // Not part of a rotate. 2129 2130 SDValue RHSShift; // The shift. 2131 SDValue RHSMask; // AND value if any. 2132 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2133 return 0; // Not part of a rotate. 2134 2135 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2136 return 0; // Not shifting the same value. 2137 2138 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2139 return 0; // Shifts must disagree. 2140 2141 // Canonicalize shl to left side in a shl/srl pair. 2142 if (RHSShift.getOpcode() == ISD::SHL) { 2143 std::swap(LHS, RHS); 2144 std::swap(LHSShift, RHSShift); 2145 std::swap(LHSMask , RHSMask ); 2146 } 2147 2148 unsigned OpSizeInBits = VT.getSizeInBits(); 2149 SDValue LHSShiftArg = LHSShift.getOperand(0); 2150 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2151 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2152 2153 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2154 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2155 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2156 RHSShiftAmt.getOpcode() == ISD::Constant) { 2157 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2158 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2159 if ((LShVal + RShVal) != OpSizeInBits) 2160 return 0; 2161 2162 SDValue Rot; 2163 if (HasROTL) 2164 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2165 else 2166 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2167 2168 // If there is an AND of either shifted operand, apply it to the result. 2169 if (LHSMask.getNode() || RHSMask.getNode()) { 2170 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2171 2172 if (LHSMask.getNode()) { 2173 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2174 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2175 } 2176 if (RHSMask.getNode()) { 2177 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2178 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2179 } 2180 2181 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2182 } 2183 2184 return Rot.getNode(); 2185 } 2186 2187 // If there is a mask here, and we have a variable shift, we can't be sure 2188 // that we're masking out the right stuff. 2189 if (LHSMask.getNode() || RHSMask.getNode()) 2190 return 0; 2191 2192 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2193 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2194 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2195 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2196 if (ConstantSDNode *SUBC = 2197 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2198 if (SUBC->getAPIntValue() == OpSizeInBits) { 2199 if (HasROTL) 2200 return DAG.getNode(ISD::ROTL, DL, VT, 2201 LHSShiftArg, LHSShiftAmt).getNode(); 2202 else 2203 return DAG.getNode(ISD::ROTR, DL, VT, 2204 LHSShiftArg, RHSShiftAmt).getNode(); 2205 } 2206 } 2207 } 2208 2209 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2210 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2211 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2212 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2213 if (ConstantSDNode *SUBC = 2214 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2215 if (SUBC->getAPIntValue() == OpSizeInBits) { 2216 if (HasROTR) 2217 return DAG.getNode(ISD::ROTR, DL, VT, 2218 LHSShiftArg, RHSShiftAmt).getNode(); 2219 else 2220 return DAG.getNode(ISD::ROTL, DL, VT, 2221 LHSShiftArg, LHSShiftAmt).getNode(); 2222 } 2223 } 2224 } 2225 2226 // Look for sign/zext/any-extended or truncate cases: 2227 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2228 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2229 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2230 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2231 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2232 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2233 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2234 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2235 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2236 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2237 if (RExtOp0.getOpcode() == ISD::SUB && 2238 RExtOp0.getOperand(1) == LExtOp0) { 2239 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2240 // (rotl x, y) 2241 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2242 // (rotr x, (sub 32, y)) 2243 if (ConstantSDNode *SUBC = 2244 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2245 if (SUBC->getAPIntValue() == OpSizeInBits) { 2246 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2247 LHSShiftArg, 2248 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2249 } 2250 } 2251 } else if (LExtOp0.getOpcode() == ISD::SUB && 2252 RExtOp0 == LExtOp0.getOperand(1)) { 2253 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2254 // (rotr x, y) 2255 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2256 // (rotl x, (sub 32, y)) 2257 if (ConstantSDNode *SUBC = 2258 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2259 if (SUBC->getAPIntValue() == OpSizeInBits) { 2260 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2261 LHSShiftArg, 2262 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2263 } 2264 } 2265 } 2266 } 2267 2268 return 0; 2269} 2270 2271SDValue DAGCombiner::visitXOR(SDNode *N) { 2272 SDValue N0 = N->getOperand(0); 2273 SDValue N1 = N->getOperand(1); 2274 SDValue LHS, RHS, CC; 2275 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2276 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2277 MVT VT = N0.getValueType(); 2278 2279 // fold vector ops 2280 if (VT.isVector()) { 2281 SDValue FoldedVOp = SimplifyVBinOp(N); 2282 if (FoldedVOp.getNode()) return FoldedVOp; 2283 } 2284 2285 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2286 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2287 return DAG.getConstant(0, VT); 2288 // fold (xor x, undef) -> undef 2289 if (N0.getOpcode() == ISD::UNDEF) 2290 return N0; 2291 if (N1.getOpcode() == ISD::UNDEF) 2292 return N1; 2293 // fold (xor c1, c2) -> c1^c2 2294 if (N0C && N1C) 2295 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2296 // canonicalize constant to RHS 2297 if (N0C && !N1C) 2298 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2299 // fold (xor x, 0) -> x 2300 if (N1C && N1C->isNullValue()) 2301 return N0; 2302 // reassociate xor 2303 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2304 if (RXOR.getNode() != 0) 2305 return RXOR; 2306 2307 // fold !(x cc y) -> (x !cc y) 2308 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2309 bool isInt = LHS.getValueType().isInteger(); 2310 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2311 isInt); 2312 2313 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2314 switch (N0.getOpcode()) { 2315 default: 2316 assert(0 && "Unhandled SetCC Equivalent!"); 2317 abort(); 2318 case ISD::SETCC: 2319 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2320 case ISD::SELECT_CC: 2321 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2322 N0.getOperand(3), NotCC); 2323 } 2324 } 2325 } 2326 2327 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2328 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2329 N0.getNode()->hasOneUse() && 2330 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2331 SDValue V = N0.getOperand(0); 2332 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2333 DAG.getConstant(1, V.getValueType())); 2334 AddToWorkList(V.getNode()); 2335 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2336 } 2337 2338 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2339 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2340 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2341 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2342 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2343 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2344 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2345 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2346 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2347 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2348 } 2349 } 2350 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2351 if (N1C && N1C->isAllOnesValue() && 2352 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2353 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2354 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2355 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2356 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2357 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2358 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2359 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2360 } 2361 } 2362 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2363 if (N1C && N0.getOpcode() == ISD::XOR) { 2364 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2365 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2366 if (N00C) 2367 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2368 DAG.getConstant(N1C->getAPIntValue() ^ 2369 N00C->getAPIntValue(), VT)); 2370 if (N01C) 2371 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2372 DAG.getConstant(N1C->getAPIntValue() ^ 2373 N01C->getAPIntValue(), VT)); 2374 } 2375 // fold (xor x, x) -> 0 2376 if (N0 == N1) { 2377 if (!VT.isVector()) { 2378 return DAG.getConstant(0, VT); 2379 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2380 // Produce a vector of zeros. 2381 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2382 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2383 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2384 &Ops[0], Ops.size()); 2385 } 2386 } 2387 2388 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2389 if (N0.getOpcode() == N1.getOpcode()) { 2390 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2391 if (Tmp.getNode()) return Tmp; 2392 } 2393 2394 // Simplify the expression using non-local knowledge. 2395 if (!VT.isVector() && 2396 SimplifyDemandedBits(SDValue(N, 0))) 2397 return SDValue(N, 0); 2398 2399 return SDValue(); 2400} 2401 2402/// visitShiftByConstant - Handle transforms common to the three shifts, when 2403/// the shift amount is a constant. 2404SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2405 SDNode *LHS = N->getOperand(0).getNode(); 2406 if (!LHS->hasOneUse()) return SDValue(); 2407 2408 // We want to pull some binops through shifts, so that we have (and (shift)) 2409 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2410 // thing happens with address calculations, so it's important to canonicalize 2411 // it. 2412 bool HighBitSet = false; // Can we transform this if the high bit is set? 2413 2414 switch (LHS->getOpcode()) { 2415 default: return SDValue(); 2416 case ISD::OR: 2417 case ISD::XOR: 2418 HighBitSet = false; // We can only transform sra if the high bit is clear. 2419 break; 2420 case ISD::AND: 2421 HighBitSet = true; // We can only transform sra if the high bit is set. 2422 break; 2423 case ISD::ADD: 2424 if (N->getOpcode() != ISD::SHL) 2425 return SDValue(); // only shl(add) not sr[al](add). 2426 HighBitSet = false; // We can only transform sra if the high bit is clear. 2427 break; 2428 } 2429 2430 // We require the RHS of the binop to be a constant as well. 2431 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2432 if (!BinOpCst) return SDValue(); 2433 2434 // FIXME: disable this unless the input to the binop is a shift by a constant. 2435 // If it is not a shift, it pessimizes some common cases like: 2436 // 2437 // void foo(int *X, int i) { X[i & 1235] = 1; } 2438 // int bar(int *X, int i) { return X[i & 255]; } 2439 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2440 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2441 BinOpLHSVal->getOpcode() != ISD::SRA && 2442 BinOpLHSVal->getOpcode() != ISD::SRL) || 2443 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2444 return SDValue(); 2445 2446 MVT VT = N->getValueType(0); 2447 2448 // If this is a signed shift right, and the high bit is modified by the 2449 // logical operation, do not perform the transformation. The highBitSet 2450 // boolean indicates the value of the high bit of the constant which would 2451 // cause it to be modified for this operation. 2452 if (N->getOpcode() == ISD::SRA) { 2453 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2454 if (BinOpRHSSignSet != HighBitSet) 2455 return SDValue(); 2456 } 2457 2458 // Fold the constants, shifting the binop RHS by the shift amount. 2459 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2460 N->getValueType(0), 2461 LHS->getOperand(1), N->getOperand(1)); 2462 2463 // Create the new shift. 2464 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2465 VT, LHS->getOperand(0), N->getOperand(1)); 2466 2467 // Create the new binop. 2468 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2469} 2470 2471SDValue DAGCombiner::visitSHL(SDNode *N) { 2472 SDValue N0 = N->getOperand(0); 2473 SDValue N1 = N->getOperand(1); 2474 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2475 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2476 MVT VT = N0.getValueType(); 2477 unsigned OpSizeInBits = VT.getSizeInBits(); 2478 2479 // fold (shl c1, c2) -> c1<<c2 2480 if (N0C && N1C) 2481 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2482 // fold (shl 0, x) -> 0 2483 if (N0C && N0C->isNullValue()) 2484 return N0; 2485 // fold (shl x, c >= size(x)) -> undef 2486 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2487 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); 2488 // fold (shl x, 0) -> x 2489 if (N1C && N1C->isNullValue()) 2490 return N0; 2491 // if (shl x, c) is known to be zero, return 0 2492 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2493 APInt::getAllOnesValue(VT.getSizeInBits()))) 2494 return DAG.getConstant(0, VT); 2495 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2496 // iff (trunc c) == c 2497 if (N1.getOpcode() == ISD::TRUNCATE && 2498 N1.getOperand(0).getOpcode() == ISD::AND && 2499 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2500 SDValue N101 = N1.getOperand(0).getOperand(1); 2501 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2502 MVT TruncVT = N1.getValueType(); 2503 SDValue N100 = N1.getOperand(0).getOperand(0); 2504 uint64_t TruncC = TruncVT.getIntegerVTBitMask() & 2505 N101C->getZExtValue(); 2506 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2507 DAG.getNode(ISD::AND, TruncVT, 2508 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2509 DAG.getConstant(TruncC, TruncVT))); 2510 } 2511 } 2512 2513 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2514 return SDValue(N, 0); 2515 2516 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2517 if (N1C && N0.getOpcode() == ISD::SHL && 2518 N0.getOperand(1).getOpcode() == ISD::Constant) { 2519 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2520 uint64_t c2 = N1C->getZExtValue(); 2521 if (c1 + c2 > OpSizeInBits) 2522 return DAG.getConstant(0, VT); 2523 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2524 DAG.getConstant(c1 + c2, N1.getValueType())); 2525 } 2526 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2527 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2528 if (N1C && N0.getOpcode() == ISD::SRL && 2529 N0.getOperand(1).getOpcode() == ISD::Constant) { 2530 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2531 uint64_t c2 = N1C->getZExtValue(); 2532 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), 2533 DAG.getConstant(~0ULL << c1, VT)); 2534 if (c2 > c1) 2535 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2536 DAG.getConstant(c2-c1, N1.getValueType())); 2537 else 2538 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2539 DAG.getConstant(c1-c2, N1.getValueType())); 2540 } 2541 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2542 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2543 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2544 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2545 2546 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2547} 2548 2549SDValue DAGCombiner::visitSRA(SDNode *N) { 2550 SDValue N0 = N->getOperand(0); 2551 SDValue N1 = N->getOperand(1); 2552 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2553 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2554 MVT VT = N0.getValueType(); 2555 2556 // fold (sra c1, c2) -> (sra c1, c2) 2557 if (N0C && N1C) 2558 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2559 // fold (sra 0, x) -> 0 2560 if (N0C && N0C->isNullValue()) 2561 return N0; 2562 // fold (sra -1, x) -> -1 2563 if (N0C && N0C->isAllOnesValue()) 2564 return N0; 2565 // fold (sra x, (setge c, size(x))) -> undef 2566 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2567 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); 2568 // fold (sra x, 0) -> x 2569 if (N1C && N1C->isNullValue()) 2570 return N0; 2571 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2572 // sext_inreg. 2573 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2574 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2575 MVT EVT = MVT::getIntegerVT(LowBits); 2576 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2577 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2578 N0.getOperand(0), DAG.getValueType(EVT)); 2579 } 2580 2581 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2582 if (N1C && N0.getOpcode() == ISD::SRA) { 2583 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2584 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2585 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2586 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2587 DAG.getConstant(Sum, N1C->getValueType(0))); 2588 } 2589 } 2590 2591 // fold (sra (shl X, m), (sub result_size, n)) 2592 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2593 // result_size - n != m. 2594 // If truncate is free for the target sext(shl) is likely to result in better 2595 // code. 2596 if (N0.getOpcode() == ISD::SHL) { 2597 // Get the two constanst of the shifts, CN0 = m, CN = n. 2598 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2599 if (N01C && N1C) { 2600 // Determine what the truncate's result bitsize and type would be. 2601 unsigned VTValSize = VT.getSizeInBits(); 2602 MVT TruncVT = 2603 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2604 // Determine the residual right-shift amount. 2605 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2606 2607 // If the shift is not a no-op (in which case this should be just a sign 2608 // extend already), the truncated to type is legal, sign_extend is legal 2609 // on that type, and the the truncate to that type is both legal and free, 2610 // perform the transform. 2611 if (ShiftAmt && 2612 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2613 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2614 TLI.isTruncateFree(VT, TruncVT)) { 2615 2616 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2617 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2618 N0.getOperand(0), Amt); 2619 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2620 Shift); 2621 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2622 N->getValueType(0), Trunc); 2623 } 2624 } 2625 } 2626 2627 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2628 // iff (trunc c) == c 2629 if (N1.getOpcode() == ISD::TRUNCATE && 2630 N1.getOperand(0).getOpcode() == ISD::AND && 2631 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2632 SDValue N101 = N1.getOperand(0).getOperand(1); 2633 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2634 MVT TruncVT = N1.getValueType(); 2635 SDValue N100 = N1.getOperand(0).getOperand(0); 2636 uint64_t TruncC = TruncVT.getIntegerVTBitMask() & 2637 N101C->getZExtValue(); 2638 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2639 DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), 2640 TruncVT, 2641 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2642 DAG.getConstant(TruncC, TruncVT))); 2643 } 2644 } 2645 2646 // Simplify, based on bits shifted out of the LHS. 2647 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2648 return SDValue(N, 0); 2649 2650 2651 // If the sign bit is known to be zero, switch this to a SRL. 2652 if (DAG.SignBitIsZero(N0)) 2653 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2654 2655 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2656} 2657 2658SDValue DAGCombiner::visitSRL(SDNode *N) { 2659 SDValue N0 = N->getOperand(0); 2660 SDValue N1 = N->getOperand(1); 2661 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2662 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2663 MVT VT = N0.getValueType(); 2664 unsigned OpSizeInBits = VT.getSizeInBits(); 2665 2666 // fold (srl c1, c2) -> c1 >>u c2 2667 if (N0C && N1C) 2668 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2669 // fold (srl 0, x) -> 0 2670 if (N0C && N0C->isNullValue()) 2671 return N0; 2672 // fold (srl x, c >= size(x)) -> undef 2673 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2674 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); 2675 // fold (srl x, 0) -> x 2676 if (N1C && N1C->isNullValue()) 2677 return N0; 2678 // if (srl x, c) is known to be zero, return 0 2679 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2680 APInt::getAllOnesValue(OpSizeInBits))) 2681 return DAG.getConstant(0, VT); 2682 2683 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2684 if (N1C && N0.getOpcode() == ISD::SRL && 2685 N0.getOperand(1).getOpcode() == ISD::Constant) { 2686 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2687 uint64_t c2 = N1C->getZExtValue(); 2688 if (c1 + c2 > OpSizeInBits) 2689 return DAG.getConstant(0, VT); 2690 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2691 DAG.getConstant(c1 + c2, N1.getValueType())); 2692 } 2693 2694 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2695 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2696 // Shifting in all undef bits? 2697 MVT SmallVT = N0.getOperand(0).getValueType(); 2698 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2699 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); 2700 2701 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2702 N0.getOperand(0), N1); 2703 AddToWorkList(SmallShift.getNode()); 2704 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2705 } 2706 2707 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2708 // bit, which is unmodified by sra. 2709 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2710 if (N0.getOpcode() == ISD::SRA) 2711 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2712 } 2713 2714 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2715 if (N1C && N0.getOpcode() == ISD::CTLZ && 2716 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2717 APInt KnownZero, KnownOne; 2718 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2719 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2720 2721 // If any of the input bits are KnownOne, then the input couldn't be all 2722 // zeros, thus the result of the srl will always be zero. 2723 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2724 2725 // If all of the bits input the to ctlz node are known to be zero, then 2726 // the result of the ctlz is "32" and the result of the shift is one. 2727 APInt UnknownBits = ~KnownZero & Mask; 2728 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2729 2730 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2731 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2732 // Okay, we know that only that the single bit specified by UnknownBits 2733 // could be set on input to the CTLZ node. If this bit is set, the SRL 2734 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2735 // to an SRL/XOR pair, which is likely to simplify more. 2736 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2737 SDValue Op = N0.getOperand(0); 2738 2739 if (ShAmt) { 2740 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2741 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2742 AddToWorkList(Op.getNode()); 2743 } 2744 2745 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2746 Op, DAG.getConstant(1, VT)); 2747 } 2748 } 2749 2750 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2751 // iff (trunc c) == c 2752 if (N1.getOpcode() == ISD::TRUNCATE && 2753 N1.getOperand(0).getOpcode() == ISD::AND && 2754 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2755 SDValue N101 = N1.getOperand(0).getOperand(1); 2756 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2757 MVT TruncVT = N1.getValueType(); 2758 SDValue N100 = N1.getOperand(0).getOperand(0); 2759 uint64_t TruncC = TruncVT.getIntegerVTBitMask() & 2760 N101C->getZExtValue(); 2761 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2762 DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), 2763 TruncVT, 2764 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2765 DAG.getConstant(TruncC, TruncVT))); 2766 } 2767 } 2768 2769 // fold operands of srl based on knowledge that the low bits are not 2770 // demanded. 2771 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2772 return SDValue(N, 0); 2773 2774 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2775} 2776 2777SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2778 SDValue N0 = N->getOperand(0); 2779 MVT VT = N->getValueType(0); 2780 2781 // fold (ctlz c1) -> c2 2782 if (isa<ConstantSDNode>(N0)) 2783 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2784 return SDValue(); 2785} 2786 2787SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2788 SDValue N0 = N->getOperand(0); 2789 MVT VT = N->getValueType(0); 2790 2791 // fold (cttz c1) -> c2 2792 if (isa<ConstantSDNode>(N0)) 2793 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2794 return SDValue(); 2795} 2796 2797SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2798 SDValue N0 = N->getOperand(0); 2799 MVT VT = N->getValueType(0); 2800 2801 // fold (ctpop c1) -> c2 2802 if (isa<ConstantSDNode>(N0)) 2803 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2804 return SDValue(); 2805} 2806 2807SDValue DAGCombiner::visitSELECT(SDNode *N) { 2808 SDValue N0 = N->getOperand(0); 2809 SDValue N1 = N->getOperand(1); 2810 SDValue N2 = N->getOperand(2); 2811 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2812 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2813 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2814 MVT VT = N->getValueType(0); 2815 MVT VT0 = N0.getValueType(); 2816 2817 // fold (select C, X, X) -> X 2818 if (N1 == N2) 2819 return N1; 2820 // fold (select true, X, Y) -> X 2821 if (N0C && !N0C->isNullValue()) 2822 return N1; 2823 // fold (select false, X, Y) -> Y 2824 if (N0C && N0C->isNullValue()) 2825 return N2; 2826 // fold (select C, 1, X) -> (or C, X) 2827 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2828 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2829 // fold (select C, 0, 1) -> (xor C, 1) 2830 if (VT.isInteger() && 2831 (VT0 == MVT::i1 || 2832 (VT0.isInteger() && 2833 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2834 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2835 SDValue XORNode; 2836 if (VT == VT0) 2837 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2838 N0, DAG.getConstant(1, VT0)); 2839 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2840 N0, DAG.getConstant(1, VT0)); 2841 AddToWorkList(XORNode.getNode()); 2842 if (VT.bitsGT(VT0)) 2843 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2844 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2845 } 2846 // fold (select C, 0, X) -> (and (not C), X) 2847 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2848 SDValue NOTNode = DAG.getNOT(N0, VT); 2849 AddToWorkList(NOTNode.getNode()); 2850 return DAG.getNode(ISD::AND, VT, NOTNode, N2); 2851 } 2852 // fold (select C, X, 1) -> (or (not C), X) 2853 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2854 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2855 AddToWorkList(NOTNode.getNode()); 2856 return DAG.getNode(ISD::OR, VT, NOTNode, N1); 2857 } 2858 // fold (select C, X, 0) -> (and C, X) 2859 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2860 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2861 // fold (select X, X, Y) -> (or X, Y) 2862 // fold (select X, 1, Y) -> (or X, Y) 2863 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2864 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2865 // fold (select X, Y, X) -> (and X, Y) 2866 // fold (select X, Y, 0) -> (and X, Y) 2867 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2868 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2869 2870 // If we can fold this based on the true/false value, do so. 2871 if (SimplifySelectOps(N, N1, N2)) 2872 return SDValue(N, 0); // Don't revisit N. 2873 2874 // fold selects based on a setcc into other things, such as min/max/abs 2875 if (N0.getOpcode() == ISD::SETCC) { 2876 // FIXME: 2877 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2878 // having to say they don't support SELECT_CC on every type the DAG knows 2879 // about, since there is no way to mark an opcode illegal at all value types 2880 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2881 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2882 N0.getOperand(0), N0.getOperand(1), 2883 N1, N2, N0.getOperand(2)); 2884 else 2885 return SimplifySelect(N0, N1, N2); 2886 } 2887 2888 return SDValue(); 2889} 2890 2891SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2892 SDValue N0 = N->getOperand(0); 2893 SDValue N1 = N->getOperand(1); 2894 SDValue N2 = N->getOperand(2); 2895 SDValue N3 = N->getOperand(3); 2896 SDValue N4 = N->getOperand(4); 2897 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2898 2899 // fold select_cc lhs, rhs, x, x, cc -> x 2900 if (N2 == N3) 2901 return N2; 2902 2903 // Determine if the condition we're dealing with is constant 2904 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2905 N0, N1, CC, false); 2906 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2907 2908 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2909 if (!SCCC->isNullValue()) 2910 return N2; // cond always true -> true val 2911 else 2912 return N3; // cond always false -> false val 2913 } 2914 2915 // Fold to a simpler select_cc 2916 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2917 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2918 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2919 SCC.getOperand(2)); 2920 2921 // If we can fold this based on the true/false value, do so. 2922 if (SimplifySelectOps(N, N2, N3)) 2923 return SDValue(N, 0); // Don't revisit N. 2924 2925 // fold select_cc into other things, such as min/max/abs 2926 return SimplifySelectCC(N0, N1, N2, N3, CC); 2927} 2928 2929SDValue DAGCombiner::visitSETCC(SDNode *N) { 2930 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2931 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2932} 2933 2934// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2935// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2936// transformation. Returns true if extension are possible and the above 2937// mentioned transformation is profitable. 2938static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2939 unsigned ExtOpc, 2940 SmallVector<SDNode*, 4> &ExtendNodes, 2941 const TargetLowering &TLI) { 2942 bool HasCopyToRegUses = false; 2943 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2944 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2945 UE = N0.getNode()->use_end(); 2946 UI != UE; ++UI) { 2947 SDNode *User = *UI; 2948 if (User == N) 2949 continue; 2950 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2951 if (User->getOpcode() == ISD::SETCC) { 2952 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2953 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2954 // Sign bits will be lost after a zext. 2955 return false; 2956 bool Add = false; 2957 for (unsigned i = 0; i != 2; ++i) { 2958 SDValue UseOp = User->getOperand(i); 2959 if (UseOp == N0) 2960 continue; 2961 if (!isa<ConstantSDNode>(UseOp)) 2962 return false; 2963 Add = true; 2964 } 2965 if (Add) 2966 ExtendNodes.push_back(User); 2967 } else { 2968 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2969 SDValue UseOp = User->getOperand(i); 2970 if (UseOp == N0) { 2971 // If truncate from extended type to original load type is free 2972 // on this target, then it's ok to extend a CopyToReg. 2973 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2974 HasCopyToRegUses = true; 2975 else 2976 return false; 2977 } 2978 } 2979 } 2980 } 2981 2982 if (HasCopyToRegUses) { 2983 bool BothLiveOut = false; 2984 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2985 UI != UE; ++UI) { 2986 SDNode *User = *UI; 2987 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2988 SDValue UseOp = User->getOperand(i); 2989 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2990 BothLiveOut = true; 2991 break; 2992 } 2993 } 2994 } 2995 if (BothLiveOut) 2996 // Both unextended and extended values are live out. There had better be 2997 // good a reason for the transformation. 2998 return ExtendNodes.size(); 2999 } 3000 return true; 3001} 3002 3003SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3004 SDValue N0 = N->getOperand(0); 3005 MVT VT = N->getValueType(0); 3006 3007 // fold (sext c1) -> c1 3008 if (isa<ConstantSDNode>(N0)) 3009 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3010 3011 // fold (sext (sext x)) -> (sext x) 3012 // fold (sext (aext x)) -> (sext x) 3013 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3014 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3015 N0.getOperand(0)); 3016 3017 if (N0.getOpcode() == ISD::TRUNCATE) { 3018 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3019 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3020 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3021 if (NarrowLoad.getNode()) { 3022 if (NarrowLoad.getNode() != N0.getNode()) 3023 CombineTo(N0.getNode(), NarrowLoad); 3024 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3025 } 3026 3027 // See if the value being truncated is already sign extended. If so, just 3028 // eliminate the trunc/sext pair. 3029 SDValue Op = N0.getOperand(0); 3030 unsigned OpBits = Op.getValueType().getSizeInBits(); 3031 unsigned MidBits = N0.getValueType().getSizeInBits(); 3032 unsigned DestBits = VT.getSizeInBits(); 3033 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3034 3035 if (OpBits == DestBits) { 3036 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3037 // bits, it is already ready. 3038 if (NumSignBits > DestBits-MidBits) 3039 return Op; 3040 } else if (OpBits < DestBits) { 3041 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3042 // bits, just sext from i32. 3043 if (NumSignBits > OpBits-MidBits) 3044 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3045 } else { 3046 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3047 // bits, just truncate to i32. 3048 if (NumSignBits > OpBits-MidBits) 3049 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3050 } 3051 3052 // fold (sext (truncate x)) -> (sextinreg x). 3053 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3054 N0.getValueType())) { 3055 if (Op.getValueType().bitsLT(VT)) 3056 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3057 else if (Op.getValueType().bitsGT(VT)) 3058 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3059 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3060 DAG.getValueType(N0.getValueType())); 3061 } 3062 } 3063 3064 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3065 if (ISD::isNON_EXTLoad(N0.getNode()) && 3066 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3067 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3068 bool DoXform = true; 3069 SmallVector<SDNode*, 4> SetCCs; 3070 if (!N0.hasOneUse()) 3071 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3072 if (DoXform) { 3073 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3074 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), 3075 VT, LN0->getChain(), 3076 LN0->getBasePtr(), LN0->getSrcValue(), 3077 LN0->getSrcValueOffset(), 3078 N0.getValueType(), 3079 LN0->isVolatile(), LN0->getAlignment()); 3080 CombineTo(N, ExtLoad); 3081 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3082 N0.getValueType(), ExtLoad); 3083 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3084 3085 // Extend SetCC uses if necessary. 3086 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3087 SDNode *SetCC = SetCCs[i]; 3088 SmallVector<SDValue, 4> Ops; 3089 3090 for (unsigned j = 0; j != 2; ++j) { 3091 SDValue SOp = SetCC->getOperand(j); 3092 if (SOp == Trunc) 3093 Ops.push_back(ExtLoad); 3094 else 3095 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, DebugLoc::getUnknownLoc(), 3096 VT, SOp)); 3097 } 3098 3099 Ops.push_back(SetCC->getOperand(2)); 3100 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), 3101 SetCC->getValueType(0), 3102 &Ops[0], Ops.size())); 3103 } 3104 3105 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3106 } 3107 } 3108 3109 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3110 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3111 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3112 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3113 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3114 MVT EVT = LN0->getMemoryVT(); 3115 if ((!LegalOperations && !LN0->isVolatile()) || 3116 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3117 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3118 LN0->getChain(), 3119 LN0->getBasePtr(), LN0->getSrcValue(), 3120 LN0->getSrcValueOffset(), EVT, 3121 LN0->isVolatile(), LN0->getAlignment()); 3122 CombineTo(N, ExtLoad); 3123 CombineTo(N0.getNode(), 3124 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3125 N0.getValueType(), ExtLoad), 3126 ExtLoad.getValue(1)); 3127 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3128 } 3129 } 3130 3131 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3132 if (N0.getOpcode() == ISD::SETCC) { 3133 SDValue SCC = 3134 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3135 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3136 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3137 if (SCC.getNode()) return SCC; 3138 } 3139 3140 // fold (sext x) -> (zext x) if the sign bit is known zero. 3141 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3142 DAG.SignBitIsZero(N0)) 3143 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3144 3145 return SDValue(); 3146} 3147 3148SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3149 SDValue N0 = N->getOperand(0); 3150 MVT VT = N->getValueType(0); 3151 3152 // fold (zext c1) -> c1 3153 if (isa<ConstantSDNode>(N0)) 3154 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3155 // fold (zext (zext x)) -> (zext x) 3156 // fold (zext (aext x)) -> (zext x) 3157 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3158 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3159 N0.getOperand(0)); 3160 3161 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3162 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3163 if (N0.getOpcode() == ISD::TRUNCATE) { 3164 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3165 if (NarrowLoad.getNode()) { 3166 if (NarrowLoad.getNode() != N0.getNode()) 3167 CombineTo(N0.getNode(), NarrowLoad); 3168 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3169 } 3170 } 3171 3172 // fold (zext (truncate x)) -> (and x, mask) 3173 if (N0.getOpcode() == ISD::TRUNCATE && 3174 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3175 SDValue Op = N0.getOperand(0); 3176 if (Op.getValueType().bitsLT(VT)) { 3177 Op = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, Op); 3178 } else if (Op.getValueType().bitsGT(VT)) { 3179 Op = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, Op); 3180 } 3181 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3182 } 3183 3184 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3185 if (N0.getOpcode() == ISD::AND && 3186 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3187 N0.getOperand(1).getOpcode() == ISD::Constant) { 3188 SDValue X = N0.getOperand(0).getOperand(0); 3189 if (X.getValueType().bitsLT(VT)) { 3190 X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X); 3191 } else if (X.getValueType().bitsGT(VT)) { 3192 X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X); 3193 } 3194 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3195 Mask.zext(VT.getSizeInBits()); 3196 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3197 X, DAG.getConstant(Mask, VT)); 3198 } 3199 3200 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3201 if (ISD::isNON_EXTLoad(N0.getNode()) && 3202 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3203 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3204 bool DoXform = true; 3205 SmallVector<SDNode*, 4> SetCCs; 3206 if (!N0.hasOneUse()) 3207 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3208 if (DoXform) { 3209 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3210 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3211 LN0->getChain(), 3212 LN0->getBasePtr(), LN0->getSrcValue(), 3213 LN0->getSrcValueOffset(), 3214 N0.getValueType(), 3215 LN0->isVolatile(), LN0->getAlignment()); 3216 CombineTo(N, ExtLoad); 3217 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3218 N0.getValueType(), ExtLoad); 3219 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3220 3221 // Extend SetCC uses if necessary. 3222 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3223 SDNode *SetCC = SetCCs[i]; 3224 SmallVector<SDValue, 4> Ops; 3225 3226 for (unsigned j = 0; j != 2; ++j) { 3227 SDValue SOp = SetCC->getOperand(j); 3228 if (SOp == Trunc) 3229 Ops.push_back(ExtLoad); 3230 else 3231 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3232 } 3233 3234 Ops.push_back(SetCC->getOperand(2)); 3235 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), 3236 SetCC->getValueType(0), 3237 &Ops[0], Ops.size())); 3238 } 3239 3240 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3241 } 3242 } 3243 3244 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3245 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3246 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3247 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3248 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3249 MVT EVT = LN0->getMemoryVT(); 3250 if ((!LegalOperations && !LN0->isVolatile()) || 3251 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3252 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3253 LN0->getChain(), 3254 LN0->getBasePtr(), LN0->getSrcValue(), 3255 LN0->getSrcValueOffset(), EVT, 3256 LN0->isVolatile(), LN0->getAlignment()); 3257 CombineTo(N, ExtLoad); 3258 CombineTo(N0.getNode(), 3259 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3260 ExtLoad), 3261 ExtLoad.getValue(1)); 3262 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3263 } 3264 } 3265 3266 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3267 if (N0.getOpcode() == ISD::SETCC) { 3268 SDValue SCC = 3269 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3270 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3271 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3272 if (SCC.getNode()) return SCC; 3273 } 3274 3275 return SDValue(); 3276} 3277 3278SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3279 SDValue N0 = N->getOperand(0); 3280 MVT VT = N->getValueType(0); 3281 3282 // fold (aext c1) -> c1 3283 if (isa<ConstantSDNode>(N0)) 3284 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3285 // fold (aext (aext x)) -> (aext x) 3286 // fold (aext (zext x)) -> (zext x) 3287 // fold (aext (sext x)) -> (sext x) 3288 if (N0.getOpcode() == ISD::ANY_EXTEND || 3289 N0.getOpcode() == ISD::ZERO_EXTEND || 3290 N0.getOpcode() == ISD::SIGN_EXTEND) 3291 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3292 3293 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3294 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3295 if (N0.getOpcode() == ISD::TRUNCATE) { 3296 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3297 if (NarrowLoad.getNode()) { 3298 if (NarrowLoad.getNode() != N0.getNode()) 3299 CombineTo(N0.getNode(), NarrowLoad); 3300 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3301 } 3302 } 3303 3304 // fold (aext (truncate x)) 3305 if (N0.getOpcode() == ISD::TRUNCATE) { 3306 SDValue TruncOp = N0.getOperand(0); 3307 if (TruncOp.getValueType() == VT) 3308 return TruncOp; // x iff x size == zext size. 3309 if (TruncOp.getValueType().bitsGT(VT)) 3310 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3311 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3312 } 3313 3314 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3315 if (N0.getOpcode() == ISD::AND && 3316 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3317 N0.getOperand(1).getOpcode() == ISD::Constant) { 3318 SDValue X = N0.getOperand(0).getOperand(0); 3319 if (X.getValueType().bitsLT(VT)) { 3320 X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X); 3321 } else if (X.getValueType().bitsGT(VT)) { 3322 X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X); 3323 } 3324 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3325 Mask.zext(VT.getSizeInBits()); 3326 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3327 X, DAG.getConstant(Mask, VT)); 3328 } 3329 3330 // fold (aext (load x)) -> (aext (truncate (extload x))) 3331 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3332 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3333 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3334 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3335 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3336 LN0->getChain(), 3337 LN0->getBasePtr(), LN0->getSrcValue(), 3338 LN0->getSrcValueOffset(), 3339 N0.getValueType(), 3340 LN0->isVolatile(), LN0->getAlignment()); 3341 CombineTo(N, ExtLoad); 3342 // Redirect any chain users to the new load. 3343 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3344 SDValue(ExtLoad.getNode(), 1)); 3345 // If any node needs the original loaded value, recompute it. 3346 if (!LN0->use_empty()) 3347 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3348 N0.getValueType(), ExtLoad), 3349 ExtLoad.getValue(1)); 3350 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3351 } 3352 3353 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3354 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3355 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3356 if (N0.getOpcode() == ISD::LOAD && 3357 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3358 N0.hasOneUse()) { 3359 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3360 MVT EVT = LN0->getMemoryVT(); 3361 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3362 VT, LN0->getChain(), LN0->getBasePtr(), 3363 LN0->getSrcValue(), 3364 LN0->getSrcValueOffset(), EVT, 3365 LN0->isVolatile(), LN0->getAlignment()); 3366 CombineTo(N, ExtLoad); 3367 CombineTo(N0.getNode(), 3368 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3369 N0.getValueType(), ExtLoad), 3370 ExtLoad.getValue(1)); 3371 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3372 } 3373 3374 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3375 if (N0.getOpcode() == ISD::SETCC) { 3376 SDValue SCC = 3377 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3378 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3379 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3380 if (SCC.getNode()) 3381 return SCC; 3382 } 3383 3384 return SDValue(); 3385} 3386 3387/// GetDemandedBits - See if the specified operand can be simplified with the 3388/// knowledge that only the bits specified by Mask are used. If so, return the 3389/// simpler operand, otherwise return a null SDValue. 3390SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3391 switch (V.getOpcode()) { 3392 default: break; 3393 case ISD::OR: 3394 case ISD::XOR: 3395 // If the LHS or RHS don't contribute bits to the or, drop them. 3396 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3397 return V.getOperand(1); 3398 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3399 return V.getOperand(0); 3400 break; 3401 case ISD::SRL: 3402 // Only look at single-use SRLs. 3403 if (!V.getNode()->hasOneUse()) 3404 break; 3405 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3406 // See if we can recursively simplify the LHS. 3407 unsigned Amt = RHSC->getZExtValue(); 3408 // Watch out for shift count overflow though. 3409 if (Amt >= Mask.getBitWidth()) break; 3410 APInt NewMask = Mask << Amt; 3411 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3412 if (SimplifyLHS.getNode()) { 3413 return DAG.getNode(ISD::SRL, V.getValueType(), 3414 SimplifyLHS, V.getOperand(1)); 3415 } 3416 } 3417 } 3418 return SDValue(); 3419} 3420 3421/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3422/// bits and then truncated to a narrower type and where N is a multiple 3423/// of number of bits of the narrower type, transform it to a narrower load 3424/// from address + N / num of bits of new type. If the result is to be 3425/// extended, also fold the extension to form a extending load. 3426SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3427 unsigned Opc = N->getOpcode(); 3428 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3429 SDValue N0 = N->getOperand(0); 3430 MVT VT = N->getValueType(0); 3431 MVT EVT = VT; 3432 3433 // This transformation isn't valid for vector loads. 3434 if (VT.isVector()) 3435 return SDValue(); 3436 3437 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3438 // extended to VT. 3439 if (Opc == ISD::SIGN_EXTEND_INREG) { 3440 ExtType = ISD::SEXTLOAD; 3441 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3442 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3443 return SDValue(); 3444 } 3445 3446 unsigned EVTBits = EVT.getSizeInBits(); 3447 unsigned ShAmt = 0; 3448 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3449 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3450 ShAmt = N01->getZExtValue(); 3451 // Is the shift amount a multiple of size of VT? 3452 if ((ShAmt & (EVTBits-1)) == 0) { 3453 N0 = N0.getOperand(0); 3454 if (N0.getValueType().getSizeInBits() <= EVTBits) 3455 return SDValue(); 3456 } 3457 } 3458 } 3459 3460 // Do not generate loads of non-round integer types since these can 3461 // be expensive (and would be wrong if the type is not byte sized). 3462 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3463 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3464 // Do not change the width of a volatile load. 3465 !cast<LoadSDNode>(N0)->isVolatile()) { 3466 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3467 MVT PtrType = N0.getOperand(1).getValueType(); 3468 // For big endian targets, we need to adjust the offset to the pointer to 3469 // load the correct bytes. 3470 if (TLI.isBigEndian()) { 3471 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3472 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3473 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3474 } 3475 uint64_t PtrOff = ShAmt / 8; 3476 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3477 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3478 DAG.getConstant(PtrOff, PtrType)); 3479 AddToWorkList(NewPtr.getNode()); 3480 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3481 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3482 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3483 LN0->isVolatile(), NewAlign) 3484 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3485 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3486 EVT, LN0->isVolatile(), NewAlign); 3487 // Replace the old load's chain with the new load's chain. 3488 WorkListRemover DeadNodes(*this); 3489 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3490 &DeadNodes); 3491 // Return the new loaded value. 3492 return Load; 3493 } 3494 3495 return SDValue(); 3496} 3497 3498 3499SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3500 SDValue N0 = N->getOperand(0); 3501 SDValue N1 = N->getOperand(1); 3502 MVT VT = N->getValueType(0); 3503 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3504 unsigned VTBits = VT.getSizeInBits(); 3505 unsigned EVTBits = EVT.getSizeInBits(); 3506 3507 // fold (sext_in_reg c1) -> c1 3508 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3509 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3510 3511 // If the input is already sign extended, just drop the extension. 3512 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3513 return N0; 3514 3515 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3516 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3517 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3518 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3519 } 3520 3521 // fold (sext_in_reg (sext x)) -> (sext x) 3522 // fold (sext_in_reg (aext x)) -> (sext x) 3523 // if x is small enough. 3524 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3525 SDValue N00 = N0.getOperand(0); 3526 if (N00.getValueType().getSizeInBits() < EVTBits) 3527 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3528 } 3529 3530 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3531 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3532 return DAG.getZeroExtendInReg(N0, EVT); 3533 3534 // fold operands of sext_in_reg based on knowledge that the top bits are not 3535 // demanded. 3536 if (SimplifyDemandedBits(SDValue(N, 0))) 3537 return SDValue(N, 0); 3538 3539 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3540 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3541 SDValue NarrowLoad = ReduceLoadWidth(N); 3542 if (NarrowLoad.getNode()) 3543 return NarrowLoad; 3544 3545 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3546 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3547 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3548 if (N0.getOpcode() == ISD::SRL) { 3549 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3550 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3551 // We can turn this into an SRA iff the input to the SRL is already sign 3552 // extended enough. 3553 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3554 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3555 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3556 } 3557 } 3558 3559 // fold (sext_inreg (extload x)) -> (sextload x) 3560 if (ISD::isEXTLoad(N0.getNode()) && 3561 ISD::isUNINDEXEDLoad(N0.getNode()) && 3562 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3563 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3564 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3565 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3566 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3567 LN0->getBasePtr(), LN0->getSrcValue(), 3568 LN0->getSrcValueOffset(), EVT, 3569 LN0->isVolatile(), LN0->getAlignment()); 3570 CombineTo(N, ExtLoad); 3571 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3572 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3573 } 3574 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3575 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3576 N0.hasOneUse() && 3577 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3578 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3579 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3580 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3581 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3582 LN0->getBasePtr(), LN0->getSrcValue(), 3583 LN0->getSrcValueOffset(), EVT, 3584 LN0->isVolatile(), LN0->getAlignment()); 3585 CombineTo(N, ExtLoad); 3586 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3587 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3588 } 3589 return SDValue(); 3590} 3591 3592SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3593 SDValue N0 = N->getOperand(0); 3594 MVT VT = N->getValueType(0); 3595 3596 // noop truncate 3597 if (N0.getValueType() == N->getValueType(0)) 3598 return N0; 3599 // fold (truncate c1) -> c1 3600 if (isa<ConstantSDNode>(N0)) 3601 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3602 // fold (truncate (truncate x)) -> (truncate x) 3603 if (N0.getOpcode() == ISD::TRUNCATE) 3604 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3605 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3606 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3607 N0.getOpcode() == ISD::ANY_EXTEND) { 3608 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3609 // if the source is smaller than the dest, we still need an extend 3610 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3611 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3612 // if the source is larger than the dest, than we just need the truncate 3613 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3614 else 3615 // if the source and dest are the same type, we can drop both the extend 3616 // and the truncate 3617 return N0.getOperand(0); 3618 } 3619 3620 // See if we can simplify the input to this truncate through knowledge that 3621 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3622 // -> trunc y 3623 SDValue Shorter = 3624 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3625 VT.getSizeInBits())); 3626 if (Shorter.getNode()) 3627 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3628 3629 // fold (truncate (load x)) -> (smaller load x) 3630 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3631 return ReduceLoadWidth(N); 3632} 3633 3634static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3635 SDValue Elt = N->getOperand(i); 3636 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3637 return Elt.getNode(); 3638 return Elt.getOperand(Elt.getResNo()).getNode(); 3639} 3640 3641/// CombineConsecutiveLoads - build_pair (load, load) -> load 3642/// if load locations are consecutive. 3643SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3644 assert(N->getOpcode() == ISD::BUILD_PAIR); 3645 3646 SDNode *LD1 = getBuildPairElt(N, 0); 3647 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3648 return SDValue(); 3649 MVT LD1VT = LD1->getValueType(0); 3650 SDNode *LD2 = getBuildPairElt(N, 1); 3651 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3652 if (ISD::isNON_EXTLoad(LD2) && 3653 LD2->hasOneUse() && 3654 // If both are volatile this would reduce the number of volatile loads. 3655 // If one is volatile it might be ok, but play conservative and bail out. 3656 !cast<LoadSDNode>(LD1)->isVolatile() && 3657 !cast<LoadSDNode>(LD2)->isVolatile() && 3658 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3659 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3660 unsigned Align = LD->getAlignment(); 3661 unsigned NewAlign = TLI.getTargetData()-> 3662 getABITypeAlignment(VT.getTypeForMVT()); 3663 if (NewAlign <= Align && 3664 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3665 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3666 LD->getSrcValue(), LD->getSrcValueOffset(), 3667 false, Align); 3668 } 3669 return SDValue(); 3670} 3671 3672SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3673 SDValue N0 = N->getOperand(0); 3674 MVT VT = N->getValueType(0); 3675 3676 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3677 // Only do this before legalize, since afterward the target may be depending 3678 // on the bitconvert. 3679 // First check to see if this is all constant. 3680 if (!LegalTypes && 3681 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3682 VT.isVector()) { 3683 bool isSimple = true; 3684 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3685 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3686 N0.getOperand(i).getOpcode() != ISD::Constant && 3687 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3688 isSimple = false; 3689 break; 3690 } 3691 3692 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3693 assert(!DestEltVT.isVector() && 3694 "Element type of vector ValueType must not be vector!"); 3695 if (isSimple) { 3696 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3697 } 3698 } 3699 3700 // If the input is a constant, let getNode fold it. 3701 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3702 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3703 if (Res.getNode() != N) return Res; 3704 } 3705 3706 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3707 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3708 3709 // fold (conv (load x)) -> (load (conv*)x) 3710 // If the resultant load doesn't need a higher alignment than the original! 3711 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3712 // Do not change the width of a volatile load. 3713 !cast<LoadSDNode>(N0)->isVolatile() && 3714 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3715 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3716 unsigned Align = TLI.getTargetData()-> 3717 getABITypeAlignment(VT.getTypeForMVT()); 3718 unsigned OrigAlign = LN0->getAlignment(); 3719 if (Align <= OrigAlign) { 3720 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3721 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3722 LN0->isVolatile(), OrigAlign); 3723 AddToWorkList(N); 3724 CombineTo(N0.getNode(), 3725 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3726 Load.getValue(1)); 3727 return Load; 3728 } 3729 } 3730 3731 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3732 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3733 // This often reduces constant pool loads. 3734 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3735 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3736 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3737 AddToWorkList(NewConv.getNode()); 3738 3739 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3740 if (N0.getOpcode() == ISD::FNEG) 3741 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3742 assert(N0.getOpcode() == ISD::FABS); 3743 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3744 } 3745 3746 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3747 // Note that we don't handle copysign(x,cst) because this can always be folded 3748 // to an fneg or fabs. 3749 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3750 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3751 VT.isInteger() && !VT.isVector()) { 3752 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3753 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3754 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3755 SDValue X = DAG.getNode(ISD::BIT_CONVERT, IntXVT, N0.getOperand(1)); 3756 AddToWorkList(X.getNode()); 3757 3758 // If X has a different width than the result/lhs, sext it or truncate it. 3759 unsigned VTWidth = VT.getSizeInBits(); 3760 if (OrigXWidth < VTWidth) { 3761 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3762 AddToWorkList(X.getNode()); 3763 } else if (OrigXWidth > VTWidth) { 3764 // To get the sign bit in the right place, we have to shift it right 3765 // before truncating. 3766 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3767 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3768 AddToWorkList(X.getNode()); 3769 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3770 AddToWorkList(X.getNode()); 3771 } 3772 3773 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3774 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3775 AddToWorkList(X.getNode()); 3776 3777 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3778 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3779 AddToWorkList(Cst.getNode()); 3780 3781 return DAG.getNode(ISD::OR, VT, X, Cst); 3782 } 3783 } 3784 3785 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3786 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3787 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3788 if (CombineLD.getNode()) 3789 return CombineLD; 3790 } 3791 3792 return SDValue(); 3793} 3794 3795SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3796 MVT VT = N->getValueType(0); 3797 return CombineConsecutiveLoads(N, VT); 3798} 3799 3800/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3801/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3802/// destination element value type. 3803SDValue DAGCombiner:: 3804ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3805 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3806 3807 // If this is already the right type, we're done. 3808 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3809 3810 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3811 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3812 3813 // If this is a conversion of N elements of one type to N elements of another 3814 // type, convert each element. This handles FP<->INT cases. 3815 if (SrcBitSize == DstBitSize) { 3816 SmallVector<SDValue, 8> Ops; 3817 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3818 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3819 AddToWorkList(Ops.back().getNode()); 3820 } 3821 MVT VT = MVT::getVectorVT(DstEltVT, 3822 BV->getValueType(0).getVectorNumElements()); 3823 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3824 } 3825 3826 // Otherwise, we're growing or shrinking the elements. To avoid having to 3827 // handle annoying details of growing/shrinking FP values, we convert them to 3828 // int first. 3829 if (SrcEltVT.isFloatingPoint()) { 3830 // Convert the input float vector to a int vector where the elements are the 3831 // same sizes. 3832 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3833 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3834 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3835 SrcEltVT = IntVT; 3836 } 3837 3838 // Now we know the input is an integer vector. If the output is a FP type, 3839 // convert to integer first, then to FP of the right size. 3840 if (DstEltVT.isFloatingPoint()) { 3841 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3842 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3843 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3844 3845 // Next, convert to FP elements of the same size. 3846 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3847 } 3848 3849 // Okay, we know the src/dst types are both integers of differing types. 3850 // Handling growing first. 3851 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3852 if (SrcBitSize < DstBitSize) { 3853 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3854 3855 SmallVector<SDValue, 8> Ops; 3856 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3857 i += NumInputsPerOutput) { 3858 bool isLE = TLI.isLittleEndian(); 3859 APInt NewBits = APInt(DstBitSize, 0); 3860 bool EltIsUndef = true; 3861 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3862 // Shift the previously computed bits over. 3863 NewBits <<= SrcBitSize; 3864 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3865 if (Op.getOpcode() == ISD::UNDEF) continue; 3866 EltIsUndef = false; 3867 3868 NewBits |= 3869 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3870 } 3871 3872 if (EltIsUndef) 3873 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3874 else 3875 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3876 } 3877 3878 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3879 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3880 } 3881 3882 // Finally, this must be the case where we are shrinking elements: each input 3883 // turns into multiple outputs. 3884 bool isS2V = ISD::isScalarToVector(BV); 3885 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3886 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3887 SmallVector<SDValue, 8> Ops; 3888 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3889 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3890 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3891 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3892 continue; 3893 } 3894 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3895 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3896 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3897 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3898 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3899 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3900 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3901 OpVal = OpVal.lshr(DstBitSize); 3902 } 3903 3904 // For big endian targets, swap the order of the pieces of each element. 3905 if (TLI.isBigEndian()) 3906 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3907 } 3908 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3909} 3910 3911 3912 3913SDValue DAGCombiner::visitFADD(SDNode *N) { 3914 SDValue N0 = N->getOperand(0); 3915 SDValue N1 = N->getOperand(1); 3916 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3917 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3918 MVT VT = N->getValueType(0); 3919 3920 // fold vector ops 3921 if (VT.isVector()) { 3922 SDValue FoldedVOp = SimplifyVBinOp(N); 3923 if (FoldedVOp.getNode()) return FoldedVOp; 3924 } 3925 3926 // fold (fadd c1, c2) -> c1+c2 3927 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3928 return DAG.getNode(ISD::FADD, VT, N0, N1); 3929 // canonicalize constant to RHS 3930 if (N0CFP && !N1CFP) 3931 return DAG.getNode(ISD::FADD, VT, N1, N0); 3932 // fold (A + 0) -> A 3933 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3934 return N0; 3935 // fold (A + (-B)) -> A-B 3936 if (isNegatibleForFree(N1, LegalOperations) == 2) 3937 return DAG.getNode(ISD::FSUB, VT, N0, 3938 GetNegatedExpression(N1, DAG, LegalOperations)); 3939 // fold ((-A) + B) -> B-A 3940 if (isNegatibleForFree(N0, LegalOperations) == 2) 3941 return DAG.getNode(ISD::FSUB, VT, N1, 3942 GetNegatedExpression(N0, DAG, LegalOperations)); 3943 3944 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3945 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3946 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3947 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3948 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3949 3950 return SDValue(); 3951} 3952 3953SDValue DAGCombiner::visitFSUB(SDNode *N) { 3954 SDValue N0 = N->getOperand(0); 3955 SDValue N1 = N->getOperand(1); 3956 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3957 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3958 MVT VT = N->getValueType(0); 3959 3960 // fold vector ops 3961 if (VT.isVector()) { 3962 SDValue FoldedVOp = SimplifyVBinOp(N); 3963 if (FoldedVOp.getNode()) return FoldedVOp; 3964 } 3965 3966 // fold (fsub c1, c2) -> c1-c2 3967 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3968 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3969 // fold (A-0) -> A 3970 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3971 return N0; 3972 // fold (0-B) -> -B 3973 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3974 if (isNegatibleForFree(N1, LegalOperations)) 3975 return GetNegatedExpression(N1, DAG, LegalOperations); 3976 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3977 return DAG.getNode(ISD::FNEG, VT, N1); 3978 } 3979 // fold (A-(-B)) -> A+B 3980 if (isNegatibleForFree(N1, LegalOperations)) 3981 return DAG.getNode(ISD::FADD, VT, N0, 3982 GetNegatedExpression(N1, DAG, LegalOperations)); 3983 3984 return SDValue(); 3985} 3986 3987SDValue DAGCombiner::visitFMUL(SDNode *N) { 3988 SDValue N0 = N->getOperand(0); 3989 SDValue N1 = N->getOperand(1); 3990 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3991 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3992 MVT VT = N->getValueType(0); 3993 3994 // fold vector ops 3995 if (VT.isVector()) { 3996 SDValue FoldedVOp = SimplifyVBinOp(N); 3997 if (FoldedVOp.getNode()) return FoldedVOp; 3998 } 3999 4000 // fold (fmul c1, c2) -> c1*c2 4001 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4002 return DAG.getNode(ISD::FMUL, VT, N0, N1); 4003 // canonicalize constant to RHS 4004 if (N0CFP && !N1CFP) 4005 return DAG.getNode(ISD::FMUL, VT, N1, N0); 4006 // fold (A * 0) -> 0 4007 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4008 return N1; 4009 // fold (fmul X, 2.0) -> (fadd X, X) 4010 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4011 return DAG.getNode(ISD::FADD, VT, N0, N0); 4012 // fold (fmul X, -1.0) -> (fneg X) 4013 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4014 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4015 return DAG.getNode(ISD::FNEG, VT, N0); 4016 4017 // -X * -Y -> X*Y 4018 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4019 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4020 // Both can be negated for free, check to see if at least one is cheaper 4021 // negated. 4022 if (LHSNeg == 2 || RHSNeg == 2) 4023 return DAG.getNode(ISD::FMUL, VT, 4024 GetNegatedExpression(N0, DAG, LegalOperations), 4025 GetNegatedExpression(N1, DAG, LegalOperations)); 4026 } 4027 } 4028 4029 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4030 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4031 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4032 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 4033 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 4034 4035 return SDValue(); 4036} 4037 4038SDValue DAGCombiner::visitFDIV(SDNode *N) { 4039 SDValue N0 = N->getOperand(0); 4040 SDValue N1 = N->getOperand(1); 4041 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4042 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4043 MVT VT = N->getValueType(0); 4044 4045 // fold vector ops 4046 if (VT.isVector()) { 4047 SDValue FoldedVOp = SimplifyVBinOp(N); 4048 if (FoldedVOp.getNode()) return FoldedVOp; 4049 } 4050 4051 // fold (fdiv c1, c2) -> c1/c2 4052 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4053 return DAG.getNode(ISD::FDIV, VT, N0, N1); 4054 4055 4056 // -X / -Y -> X*Y 4057 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4058 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4059 // Both can be negated for free, check to see if at least one is cheaper 4060 // negated. 4061 if (LHSNeg == 2 || RHSNeg == 2) 4062 return DAG.getNode(ISD::FDIV, VT, 4063 GetNegatedExpression(N0, DAG, LegalOperations), 4064 GetNegatedExpression(N1, DAG, LegalOperations)); 4065 } 4066 } 4067 4068 return SDValue(); 4069} 4070 4071SDValue DAGCombiner::visitFREM(SDNode *N) { 4072 SDValue N0 = N->getOperand(0); 4073 SDValue N1 = N->getOperand(1); 4074 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4075 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4076 MVT VT = N->getValueType(0); 4077 4078 // fold (frem c1, c2) -> fmod(c1,c2) 4079 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4080 return DAG.getNode(ISD::FREM, VT, N0, N1); 4081 4082 return SDValue(); 4083} 4084 4085SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4086 SDValue N0 = N->getOperand(0); 4087 SDValue N1 = N->getOperand(1); 4088 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4089 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4090 MVT VT = N->getValueType(0); 4091 4092 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4093 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 4094 4095 if (N1CFP) { 4096 const APFloat& V = N1CFP->getValueAPF(); 4097 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4098 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4099 if (!V.isNegative()) { 4100 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4101 return DAG.getNode(ISD::FABS, VT, N0); 4102 } else { 4103 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4104 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 4105 } 4106 } 4107 4108 // copysign(fabs(x), y) -> copysign(x, y) 4109 // copysign(fneg(x), y) -> copysign(x, y) 4110 // copysign(copysign(x,z), y) -> copysign(x, y) 4111 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4112 N0.getOpcode() == ISD::FCOPYSIGN) 4113 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 4114 4115 // copysign(x, abs(y)) -> abs(x) 4116 if (N1.getOpcode() == ISD::FABS) 4117 return DAG.getNode(ISD::FABS, VT, N0); 4118 4119 // copysign(x, copysign(y,z)) -> copysign(x, z) 4120 if (N1.getOpcode() == ISD::FCOPYSIGN) 4121 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 4122 4123 // copysign(x, fp_extend(y)) -> copysign(x, y) 4124 // copysign(x, fp_round(y)) -> copysign(x, y) 4125 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4126 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 4127 4128 return SDValue(); 4129} 4130 4131 4132 4133SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4134 SDValue N0 = N->getOperand(0); 4135 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4136 MVT VT = N->getValueType(0); 4137 MVT OpVT = N0.getValueType(); 4138 4139 // fold (sint_to_fp c1) -> c1fp 4140 if (N0C && OpVT != MVT::ppcf128) 4141 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 4142 4143 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4144 // but UINT_TO_FP is legal on this target, try to convert. 4145 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4146 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4147 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4148 if (DAG.SignBitIsZero(N0)) 4149 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4150 } 4151 4152 4153 return SDValue(); 4154} 4155 4156SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4157 SDValue N0 = N->getOperand(0); 4158 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4159 MVT VT = N->getValueType(0); 4160 MVT OpVT = N0.getValueType(); 4161 4162 // fold (uint_to_fp c1) -> c1fp 4163 if (N0C && OpVT != MVT::ppcf128) 4164 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4165 4166 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4167 // but SINT_TO_FP is legal on this target, try to convert. 4168 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4169 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4170 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4171 if (DAG.SignBitIsZero(N0)) 4172 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 4173 } 4174 4175 return SDValue(); 4176} 4177 4178SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4179 SDValue N0 = N->getOperand(0); 4180 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4181 MVT VT = N->getValueType(0); 4182 4183 // fold (fp_to_sint c1fp) -> c1 4184 if (N0CFP) 4185 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 4186 return SDValue(); 4187} 4188 4189SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4190 SDValue N0 = N->getOperand(0); 4191 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4192 MVT VT = N->getValueType(0); 4193 4194 // fold (fp_to_uint c1fp) -> c1 4195 if (N0CFP && VT != MVT::ppcf128) 4196 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 4197 return SDValue(); 4198} 4199 4200SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4201 SDValue N0 = N->getOperand(0); 4202 SDValue N1 = N->getOperand(1); 4203 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4204 MVT VT = N->getValueType(0); 4205 4206 // fold (fp_round c1fp) -> c1fp 4207 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4208 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 4209 4210 // fold (fp_round (fp_extend x)) -> x 4211 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4212 return N0.getOperand(0); 4213 4214 // fold (fp_round (fp_round x)) -> (fp_round x) 4215 if (N0.getOpcode() == ISD::FP_ROUND) { 4216 // This is a value preserving truncation if both round's are. 4217 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4218 N0.getNode()->getConstantOperandVal(1) == 1; 4219 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 4220 DAG.getIntPtrConstant(IsTrunc)); 4221 } 4222 4223 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4224 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4225 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 4226 AddToWorkList(Tmp.getNode()); 4227 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 4228 } 4229 4230 return SDValue(); 4231} 4232 4233SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4234 SDValue N0 = N->getOperand(0); 4235 MVT VT = N->getValueType(0); 4236 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4237 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4238 4239 // fold (fp_round_inreg c1fp) -> c1fp 4240 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4241 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4242 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4243 } 4244 return SDValue(); 4245} 4246 4247SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4248 SDValue N0 = N->getOperand(0); 4249 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4250 MVT VT = N->getValueType(0); 4251 4252 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4253 if (N->hasOneUse() && 4254 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4255 return SDValue(); 4256 4257 // fold (fp_extend c1fp) -> c1fp 4258 if (N0CFP && VT != MVT::ppcf128) 4259 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4260 4261 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4262 // value of X. 4263 if (N0.getOpcode() == ISD::FP_ROUND 4264 && N0.getNode()->getConstantOperandVal(1) == 1) { 4265 SDValue In = N0.getOperand(0); 4266 if (In.getValueType() == VT) return In; 4267 if (VT.bitsLT(In.getValueType())) 4268 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4269 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4270 } 4271 4272 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4273 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4274 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4275 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4276 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4277 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4278 LN0->getBasePtr(), LN0->getSrcValue(), 4279 LN0->getSrcValueOffset(), 4280 N0.getValueType(), 4281 LN0->isVolatile(), LN0->getAlignment()); 4282 CombineTo(N, ExtLoad); 4283 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4284 ExtLoad, DAG.getIntPtrConstant(1)), 4285 ExtLoad.getValue(1)); 4286 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4287 } 4288 4289 return SDValue(); 4290} 4291 4292SDValue DAGCombiner::visitFNEG(SDNode *N) { 4293 SDValue N0 = N->getOperand(0); 4294 4295 if (isNegatibleForFree(N0, LegalOperations)) 4296 return GetNegatedExpression(N0, DAG, LegalOperations); 4297 4298 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4299 // constant pool values. 4300 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4301 N0.getOperand(0).getValueType().isInteger() && 4302 !N0.getOperand(0).getValueType().isVector()) { 4303 SDValue Int = N0.getOperand(0); 4304 MVT IntVT = Int.getValueType(); 4305 if (IntVT.isInteger() && !IntVT.isVector()) { 4306 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4307 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4308 AddToWorkList(Int.getNode()); 4309 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4310 } 4311 } 4312 4313 return SDValue(); 4314} 4315 4316SDValue DAGCombiner::visitFABS(SDNode *N) { 4317 SDValue N0 = N->getOperand(0); 4318 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4319 MVT VT = N->getValueType(0); 4320 4321 // fold (fabs c1) -> fabs(c1) 4322 if (N0CFP && VT != MVT::ppcf128) 4323 return DAG.getNode(ISD::FABS, VT, N0); 4324 // fold (fabs (fabs x)) -> (fabs x) 4325 if (N0.getOpcode() == ISD::FABS) 4326 return N->getOperand(0); 4327 // fold (fabs (fneg x)) -> (fabs x) 4328 // fold (fabs (fcopysign x, y)) -> (fabs x) 4329 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4330 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4331 4332 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4333 // constant pool values. 4334 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4335 N0.getOperand(0).getValueType().isInteger() && 4336 !N0.getOperand(0).getValueType().isVector()) { 4337 SDValue Int = N0.getOperand(0); 4338 MVT IntVT = Int.getValueType(); 4339 if (IntVT.isInteger() && !IntVT.isVector()) { 4340 Int = DAG.getNode(ISD::AND, IntVT, Int, 4341 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4342 AddToWorkList(Int.getNode()); 4343 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4344 } 4345 } 4346 4347 return SDValue(); 4348} 4349 4350SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4351 SDValue Chain = N->getOperand(0); 4352 SDValue N1 = N->getOperand(1); 4353 SDValue N2 = N->getOperand(2); 4354 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4355 4356 // never taken branch, fold to chain 4357 if (N1C && N1C->isNullValue()) 4358 return Chain; 4359 // unconditional branch 4360 if (N1C && N1C->getAPIntValue() == 1) 4361 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4362 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4363 // on the target. 4364 if (N1.getOpcode() == ISD::SETCC && 4365 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4366 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4367 N1.getOperand(0), N1.getOperand(1), N2); 4368 } 4369 return SDValue(); 4370} 4371 4372// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4373// 4374SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4375 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4376 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4377 4378 // Use SimplifySetCC to simplify SETCC's. 4379 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4380 CondLHS, CondRHS, CC->get(), false); 4381 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4382 4383 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4384 4385 // fold br_cc true, dest -> br dest (unconditional branch) 4386 if (SCCC && !SCCC->isNullValue()) 4387 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4388 N->getOperand(4)); 4389 // fold br_cc false, dest -> unconditional fall through 4390 if (SCCC && SCCC->isNullValue()) 4391 return N->getOperand(0); 4392 4393 // fold to a simpler setcc 4394 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4395 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4396 Simp.getOperand(2), Simp.getOperand(0), 4397 Simp.getOperand(1), N->getOperand(4)); 4398 return SDValue(); 4399} 4400 4401 4402/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4403/// pre-indexed load / store when the base pointer is an add or subtract 4404/// and it has other uses besides the load / store. After the 4405/// transformation, the new indexed load / store has effectively folded 4406/// the add / subtract in and all of its other uses are redirected to the 4407/// new load / store. 4408bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4409 if (!LegalOperations) 4410 return false; 4411 4412 bool isLoad = true; 4413 SDValue Ptr; 4414 MVT VT; 4415 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4416 if (LD->isIndexed()) 4417 return false; 4418 VT = LD->getMemoryVT(); 4419 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4420 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4421 return false; 4422 Ptr = LD->getBasePtr(); 4423 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4424 if (ST->isIndexed()) 4425 return false; 4426 VT = ST->getMemoryVT(); 4427 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4428 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4429 return false; 4430 Ptr = ST->getBasePtr(); 4431 isLoad = false; 4432 } else 4433 return false; 4434 4435 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4436 // out. There is no reason to make this a preinc/predec. 4437 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4438 Ptr.getNode()->hasOneUse()) 4439 return false; 4440 4441 // Ask the target to do addressing mode selection. 4442 SDValue BasePtr; 4443 SDValue Offset; 4444 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4445 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4446 return false; 4447 // Don't create a indexed load / store with zero offset. 4448 if (isa<ConstantSDNode>(Offset) && 4449 cast<ConstantSDNode>(Offset)->isNullValue()) 4450 return false; 4451 4452 // Try turning it into a pre-indexed load / store except when: 4453 // 1) The new base ptr is a frame index. 4454 // 2) If N is a store and the new base ptr is either the same as or is a 4455 // predecessor of the value being stored. 4456 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4457 // that would create a cycle. 4458 // 4) All uses are load / store ops that use it as old base ptr. 4459 4460 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4461 // (plus the implicit offset) to a register to preinc anyway. 4462 if (isa<FrameIndexSDNode>(BasePtr)) 4463 return false; 4464 4465 // Check #2. 4466 if (!isLoad) { 4467 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4468 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4469 return false; 4470 } 4471 4472 // Now check for #3 and #4. 4473 bool RealUse = false; 4474 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4475 E = Ptr.getNode()->use_end(); I != E; ++I) { 4476 SDNode *Use = *I; 4477 if (Use == N) 4478 continue; 4479 if (Use->isPredecessorOf(N)) 4480 return false; 4481 4482 if (!((Use->getOpcode() == ISD::LOAD && 4483 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4484 (Use->getOpcode() == ISD::STORE && 4485 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4486 RealUse = true; 4487 } 4488 if (!RealUse) 4489 return false; 4490 4491 SDValue Result; 4492 if (isLoad) 4493 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4494 else 4495 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4496 ++PreIndexedNodes; 4497 ++NodesCombined; 4498 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4499 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4500 DOUT << '\n'; 4501 WorkListRemover DeadNodes(*this); 4502 if (isLoad) { 4503 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4504 &DeadNodes); 4505 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4506 &DeadNodes); 4507 } else { 4508 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4509 &DeadNodes); 4510 } 4511 4512 // Finally, since the node is now dead, remove it from the graph. 4513 DAG.DeleteNode(N); 4514 4515 // Replace the uses of Ptr with uses of the updated base value. 4516 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4517 &DeadNodes); 4518 removeFromWorkList(Ptr.getNode()); 4519 DAG.DeleteNode(Ptr.getNode()); 4520 4521 return true; 4522} 4523 4524/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4525/// add / sub of the base pointer node into a post-indexed load / store. 4526/// The transformation folded the add / subtract into the new indexed 4527/// load / store effectively and all of its uses are redirected to the 4528/// new load / store. 4529bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4530 if (!LegalOperations) 4531 return false; 4532 4533 bool isLoad = true; 4534 SDValue Ptr; 4535 MVT VT; 4536 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4537 if (LD->isIndexed()) 4538 return false; 4539 VT = LD->getMemoryVT(); 4540 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4541 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4542 return false; 4543 Ptr = LD->getBasePtr(); 4544 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4545 if (ST->isIndexed()) 4546 return false; 4547 VT = ST->getMemoryVT(); 4548 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4549 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4550 return false; 4551 Ptr = ST->getBasePtr(); 4552 isLoad = false; 4553 } else 4554 return false; 4555 4556 if (Ptr.getNode()->hasOneUse()) 4557 return false; 4558 4559 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4560 E = Ptr.getNode()->use_end(); I != E; ++I) { 4561 SDNode *Op = *I; 4562 if (Op == N || 4563 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4564 continue; 4565 4566 SDValue BasePtr; 4567 SDValue Offset; 4568 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4569 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4570 if (Ptr == Offset) 4571 std::swap(BasePtr, Offset); 4572 if (Ptr != BasePtr) 4573 continue; 4574 // Don't create a indexed load / store with zero offset. 4575 if (isa<ConstantSDNode>(Offset) && 4576 cast<ConstantSDNode>(Offset)->isNullValue()) 4577 continue; 4578 4579 // Try turning it into a post-indexed load / store except when 4580 // 1) All uses are load / store ops that use it as base ptr. 4581 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4582 // nor a successor of N. Otherwise, if Op is folded that would 4583 // create a cycle. 4584 4585 // Check for #1. 4586 bool TryNext = false; 4587 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4588 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4589 SDNode *Use = *II; 4590 if (Use == Ptr.getNode()) 4591 continue; 4592 4593 // If all the uses are load / store addresses, then don't do the 4594 // transformation. 4595 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4596 bool RealUse = false; 4597 for (SDNode::use_iterator III = Use->use_begin(), 4598 EEE = Use->use_end(); III != EEE; ++III) { 4599 SDNode *UseUse = *III; 4600 if (!((UseUse->getOpcode() == ISD::LOAD && 4601 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4602 (UseUse->getOpcode() == ISD::STORE && 4603 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4604 RealUse = true; 4605 } 4606 4607 if (!RealUse) { 4608 TryNext = true; 4609 break; 4610 } 4611 } 4612 } 4613 if (TryNext) 4614 continue; 4615 4616 // Check for #2 4617 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4618 SDValue Result = isLoad 4619 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4620 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4621 ++PostIndexedNodes; 4622 ++NodesCombined; 4623 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4624 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4625 DOUT << '\n'; 4626 WorkListRemover DeadNodes(*this); 4627 if (isLoad) { 4628 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4629 &DeadNodes); 4630 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4631 &DeadNodes); 4632 } else { 4633 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4634 &DeadNodes); 4635 } 4636 4637 // Finally, since the node is now dead, remove it from the graph. 4638 DAG.DeleteNode(N); 4639 4640 // Replace the uses of Use with uses of the updated base value. 4641 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4642 Result.getValue(isLoad ? 1 : 0), 4643 &DeadNodes); 4644 removeFromWorkList(Op); 4645 DAG.DeleteNode(Op); 4646 return true; 4647 } 4648 } 4649 } 4650 return false; 4651} 4652 4653/// InferAlignment - If we can infer some alignment information from this 4654/// pointer, return it. 4655static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4656 // If this is a direct reference to a stack slot, use information about the 4657 // stack slot's alignment. 4658 int FrameIdx = 1 << 31; 4659 int64_t FrameOffset = 0; 4660 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4661 FrameIdx = FI->getIndex(); 4662 } else if (Ptr.getOpcode() == ISD::ADD && 4663 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4664 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4665 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4666 FrameOffset = Ptr.getConstantOperandVal(1); 4667 } 4668 4669 if (FrameIdx != (1 << 31)) { 4670 // FIXME: Handle FI+CST. 4671 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4672 if (MFI.isFixedObjectIndex(FrameIdx)) { 4673 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4674 4675 // The alignment of the frame index can be determined from its offset from 4676 // the incoming frame position. If the frame object is at offset 32 and 4677 // the stack is guaranteed to be 16-byte aligned, then we know that the 4678 // object is 16-byte aligned. 4679 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4680 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4681 4682 // Finally, the frame object itself may have a known alignment. Factor 4683 // the alignment + offset into a new alignment. For example, if we know 4684 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4685 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4686 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4687 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4688 FrameOffset); 4689 return std::max(Align, FIInfoAlign); 4690 } 4691 } 4692 4693 return 0; 4694} 4695 4696SDValue DAGCombiner::visitLOAD(SDNode *N) { 4697 LoadSDNode *LD = cast<LoadSDNode>(N); 4698 SDValue Chain = LD->getChain(); 4699 SDValue Ptr = LD->getBasePtr(); 4700 4701 // Try to infer better alignment information than the load already has. 4702 if (!Fast && LD->isUnindexed()) { 4703 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4704 if (Align > LD->getAlignment()) 4705 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4706 Chain, Ptr, LD->getSrcValue(), 4707 LD->getSrcValueOffset(), LD->getMemoryVT(), 4708 LD->isVolatile(), Align); 4709 } 4710 } 4711 4712 4713 // If load is not volatile and there are no uses of the loaded value (and 4714 // the updated indexed value in case of indexed loads), change uses of the 4715 // chain value into uses of the chain input (i.e. delete the dead load). 4716 if (!LD->isVolatile()) { 4717 if (N->getValueType(1) == MVT::Other) { 4718 // Unindexed loads. 4719 if (N->hasNUsesOfValue(0, 0)) { 4720 // It's not safe to use the two value CombineTo variant here. e.g. 4721 // v1, chain2 = load chain1, loc 4722 // v2, chain3 = load chain2, loc 4723 // v3 = add v2, c 4724 // Now we replace use of chain2 with chain1. This makes the second load 4725 // isomorphic to the one we are deleting, and thus makes this load live. 4726 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4727 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4728 DOUT << "\n"; 4729 WorkListRemover DeadNodes(*this); 4730 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4731 if (N->use_empty()) { 4732 removeFromWorkList(N); 4733 DAG.DeleteNode(N); 4734 } 4735 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4736 } 4737 } else { 4738 // Indexed loads. 4739 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4740 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4741 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4742 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4743 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4744 DOUT << " and 2 other values\n"; 4745 WorkListRemover DeadNodes(*this); 4746 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4747 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4748 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4749 &DeadNodes); 4750 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4751 removeFromWorkList(N); 4752 DAG.DeleteNode(N); 4753 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4754 } 4755 } 4756 } 4757 4758 // If this load is directly stored, replace the load value with the stored 4759 // value. 4760 // TODO: Handle store large -> read small portion. 4761 // TODO: Handle TRUNCSTORE/LOADEXT 4762 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4763 !LD->isVolatile()) { 4764 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4765 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4766 if (PrevST->getBasePtr() == Ptr && 4767 PrevST->getValue().getValueType() == N->getValueType(0)) 4768 return CombineTo(N, Chain.getOperand(1), Chain); 4769 } 4770 } 4771 4772 if (CombinerAA) { 4773 // Walk up chain skipping non-aliasing memory nodes. 4774 SDValue BetterChain = FindBetterChain(N, Chain); 4775 4776 // If there is a better chain. 4777 if (Chain != BetterChain) { 4778 SDValue ReplLoad; 4779 4780 // Replace the chain to void dependency. 4781 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4782 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4783 LD->getSrcValue(), LD->getSrcValueOffset(), 4784 LD->isVolatile(), LD->getAlignment()); 4785 } else { 4786 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4787 LD->getValueType(0), 4788 BetterChain, Ptr, LD->getSrcValue(), 4789 LD->getSrcValueOffset(), 4790 LD->getMemoryVT(), 4791 LD->isVolatile(), 4792 LD->getAlignment()); 4793 } 4794 4795 // Create token factor to keep old chain connected. 4796 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4797 Chain, ReplLoad.getValue(1)); 4798 4799 // Replace uses with load result and token factor. Don't add users 4800 // to work list. 4801 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4802 } 4803 } 4804 4805 // Try transforming N to an indexed load. 4806 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4807 return SDValue(N, 0); 4808 4809 return SDValue(); 4810} 4811 4812 4813SDValue DAGCombiner::visitSTORE(SDNode *N) { 4814 StoreSDNode *ST = cast<StoreSDNode>(N); 4815 SDValue Chain = ST->getChain(); 4816 SDValue Value = ST->getValue(); 4817 SDValue Ptr = ST->getBasePtr(); 4818 4819 // Try to infer better alignment information than the store already has. 4820 if (!Fast && ST->isUnindexed()) { 4821 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4822 if (Align > ST->getAlignment()) 4823 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4824 ST->getSrcValueOffset(), ST->getMemoryVT(), 4825 ST->isVolatile(), Align); 4826 } 4827 } 4828 4829 // If this is a store of a bit convert, store the input value if the 4830 // resultant store does not need a higher alignment than the original. 4831 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4832 ST->isUnindexed()) { 4833 unsigned Align = ST->getAlignment(); 4834 MVT SVT = Value.getOperand(0).getValueType(); 4835 unsigned OrigAlign = TLI.getTargetData()-> 4836 getABITypeAlignment(SVT.getTypeForMVT()); 4837 if (Align <= OrigAlign && 4838 ((!LegalOperations && !ST->isVolatile()) || 4839 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 4840 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4841 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4842 } 4843 4844 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4845 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4846 // NOTE: If the original store is volatile, this transform must not increase 4847 // the number of stores. For example, on x86-32 an f64 can be stored in one 4848 // processor operation but an i64 (which is not legal) requires two. So the 4849 // transform should not be done in this case. 4850 if (Value.getOpcode() != ISD::TargetConstantFP) { 4851 SDValue Tmp; 4852 switch (CFP->getValueType(0).getSimpleVT()) { 4853 default: assert(0 && "Unknown FP type"); 4854 case MVT::f80: // We don't do this for these yet. 4855 case MVT::f128: 4856 case MVT::ppcf128: 4857 break; 4858 case MVT::f32: 4859 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 4860 !ST->isVolatile()) || 4861 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4862 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4863 bitcastToAPInt().getZExtValue(), MVT::i32); 4864 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4865 ST->getSrcValueOffset(), ST->isVolatile(), 4866 ST->getAlignment()); 4867 } 4868 break; 4869 case MVT::f64: 4870 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 4871 !ST->isVolatile()) || 4872 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 4873 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4874 getZExtValue(), MVT::i64); 4875 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4876 ST->getSrcValueOffset(), ST->isVolatile(), 4877 ST->getAlignment()); 4878 } else if (!ST->isVolatile() && 4879 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4880 // Many FP stores are not made apparent until after legalize, e.g. for 4881 // argument passing. Since this is so common, custom legalize the 4882 // 64-bit integer store into two 32-bit stores. 4883 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4884 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4885 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4886 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4887 4888 int SVOffset = ST->getSrcValueOffset(); 4889 unsigned Alignment = ST->getAlignment(); 4890 bool isVolatile = ST->isVolatile(); 4891 4892 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4893 ST->getSrcValueOffset(), 4894 isVolatile, ST->getAlignment()); 4895 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4896 DAG.getConstant(4, Ptr.getValueType())); 4897 SVOffset += 4; 4898 Alignment = MinAlign(Alignment, 4U); 4899 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4900 SVOffset, isVolatile, Alignment); 4901 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4902 } 4903 break; 4904 } 4905 } 4906 } 4907 4908 if (CombinerAA) { 4909 // Walk up chain skipping non-aliasing memory nodes. 4910 SDValue BetterChain = FindBetterChain(N, Chain); 4911 4912 // If there is a better chain. 4913 if (Chain != BetterChain) { 4914 // Replace the chain to avoid dependency. 4915 SDValue ReplStore; 4916 if (ST->isTruncatingStore()) { 4917 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4918 ST->getSrcValue(),ST->getSrcValueOffset(), 4919 ST->getMemoryVT(), 4920 ST->isVolatile(), ST->getAlignment()); 4921 } else { 4922 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4923 ST->getSrcValue(), ST->getSrcValueOffset(), 4924 ST->isVolatile(), ST->getAlignment()); 4925 } 4926 4927 // Create token to keep both nodes around. 4928 SDValue Token = 4929 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4930 4931 // Don't add users to work list. 4932 return CombineTo(N, Token, false); 4933 } 4934 } 4935 4936 // Try transforming N to an indexed store. 4937 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4938 return SDValue(N, 0); 4939 4940 // FIXME: is there such a thing as a truncating indexed store? 4941 if (ST->isTruncatingStore() && ST->isUnindexed() && 4942 Value.getValueType().isInteger()) { 4943 // See if we can simplify the input to this truncstore with knowledge that 4944 // only the low bits are being used. For example: 4945 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4946 SDValue Shorter = 4947 GetDemandedBits(Value, 4948 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4949 ST->getMemoryVT().getSizeInBits())); 4950 AddToWorkList(Value.getNode()); 4951 if (Shorter.getNode()) 4952 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4953 ST->getSrcValueOffset(), ST->getMemoryVT(), 4954 ST->isVolatile(), ST->getAlignment()); 4955 4956 // Otherwise, see if we can simplify the operation with 4957 // SimplifyDemandedBits, which only works if the value has a single use. 4958 if (SimplifyDemandedBits(Value, 4959 APInt::getLowBitsSet( 4960 Value.getValueSizeInBits(), 4961 ST->getMemoryVT().getSizeInBits()))) 4962 return SDValue(N, 0); 4963 } 4964 4965 // If this is a load followed by a store to the same location, then the store 4966 // is dead/noop. 4967 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4968 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4969 ST->isUnindexed() && !ST->isVolatile() && 4970 // There can't be any side effects between the load and store, such as 4971 // a call or store. 4972 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4973 // The store is dead, remove it. 4974 return Chain; 4975 } 4976 } 4977 4978 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4979 // truncating store. We can do this even if this is already a truncstore. 4980 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4981 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4982 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4983 ST->getMemoryVT())) { 4984 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4985 ST->getSrcValueOffset(), ST->getMemoryVT(), 4986 ST->isVolatile(), ST->getAlignment()); 4987 } 4988 4989 return SDValue(); 4990} 4991 4992SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4993 SDValue InVec = N->getOperand(0); 4994 SDValue InVal = N->getOperand(1); 4995 SDValue EltNo = N->getOperand(2); 4996 4997 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4998 // vector with the inserted element. 4999 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5000 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5001 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5002 InVec.getNode()->op_end()); 5003 if (Elt < Ops.size()) 5004 Ops[Elt] = InVal; 5005 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 5006 &Ops[0], Ops.size()); 5007 } 5008 5009 return SDValue(); 5010} 5011 5012SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5013 // (vextract (scalar_to_vector val, 0) -> val 5014 SDValue InVec = N->getOperand(0); 5015 5016 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) 5017 return InVec.getOperand(0); 5018 5019 // Perform only after legalization to ensure build_vector / vector_shuffle 5020 // optimizations have already been done. 5021 if (!LegalOperations) return SDValue(); 5022 5023 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5024 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5025 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5026 SDValue EltNo = N->getOperand(1); 5027 5028 if (isa<ConstantSDNode>(EltNo)) { 5029 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5030 bool NewLoad = false; 5031 bool BCNumEltsChanged = false; 5032 MVT VT = InVec.getValueType(); 5033 MVT EVT = VT.getVectorElementType(); 5034 MVT LVT = EVT; 5035 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5036 MVT BCVT = InVec.getOperand(0).getValueType(); 5037 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5038 return SDValue(); 5039 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5040 BCNumEltsChanged = true; 5041 InVec = InVec.getOperand(0); 5042 EVT = BCVT.getVectorElementType(); 5043 NewLoad = true; 5044 } 5045 5046 LoadSDNode *LN0 = NULL; 5047 if (ISD::isNormalLoad(InVec.getNode())) 5048 LN0 = cast<LoadSDNode>(InVec); 5049 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5050 InVec.getOperand(0).getValueType() == EVT && 5051 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5052 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5053 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 5054 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5055 // => 5056 // (load $addr+1*size) 5057 5058 // If the bit convert changed the number of elements, it is unsafe 5059 // to examine the mask. 5060 if (BCNumEltsChanged) 5061 return SDValue(); 5062 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 5063 getOperand(Elt))->getZExtValue(); 5064 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 5065 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5066 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5067 InVec = InVec.getOperand(0); 5068 if (ISD::isNormalLoad(InVec.getNode())) { 5069 LN0 = cast<LoadSDNode>(InVec); 5070 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 5071 } 5072 } 5073 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5074 return SDValue(); 5075 5076 unsigned Align = LN0->getAlignment(); 5077 if (NewLoad) { 5078 // Check the resultant load doesn't need a higher alignment than the 5079 // original load. 5080 unsigned NewAlign = TLI.getTargetData()-> 5081 getABITypeAlignment(LVT.getTypeForMVT()); 5082 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5083 return SDValue(); 5084 Align = NewAlign; 5085 } 5086 5087 SDValue NewPtr = LN0->getBasePtr(); 5088 if (Elt) { 5089 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5090 MVT PtrType = NewPtr.getValueType(); 5091 if (TLI.isBigEndian()) 5092 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5093 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 5094 DAG.getConstant(PtrOff, PtrType)); 5095 } 5096 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 5097 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5098 LN0->isVolatile(), Align); 5099 } 5100 return SDValue(); 5101} 5102 5103 5104SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5105 unsigned NumInScalars = N->getNumOperands(); 5106 MVT VT = N->getValueType(0); 5107 unsigned NumElts = VT.getVectorNumElements(); 5108 MVT EltType = VT.getVectorElementType(); 5109 5110 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5111 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5112 // at most two distinct vectors, turn this into a shuffle node. 5113 SDValue VecIn1, VecIn2; 5114 for (unsigned i = 0; i != NumInScalars; ++i) { 5115 // Ignore undef inputs. 5116 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5117 5118 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5119 // constant index, bail out. 5120 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5121 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5122 VecIn1 = VecIn2 = SDValue(0, 0); 5123 break; 5124 } 5125 5126 // If the input vector type disagrees with the result of the build_vector, 5127 // we can't make a shuffle. 5128 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5129 if (ExtractedFromVec.getValueType() != VT) { 5130 VecIn1 = VecIn2 = SDValue(0, 0); 5131 break; 5132 } 5133 5134 // Otherwise, remember this. We allow up to two distinct input vectors. 5135 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5136 continue; 5137 5138 if (VecIn1.getNode() == 0) { 5139 VecIn1 = ExtractedFromVec; 5140 } else if (VecIn2.getNode() == 0) { 5141 VecIn2 = ExtractedFromVec; 5142 } else { 5143 // Too many inputs. 5144 VecIn1 = VecIn2 = SDValue(0, 0); 5145 break; 5146 } 5147 } 5148 5149 // If everything is good, we can make a shuffle operation. 5150 if (VecIn1.getNode()) { 5151 SmallVector<SDValue, 8> BuildVecIndices; 5152 for (unsigned i = 0; i != NumInScalars; ++i) { 5153 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5154 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 5155 continue; 5156 } 5157 5158 SDValue Extract = N->getOperand(i); 5159 5160 // If extracting from the first vector, just use the index directly. 5161 if (Extract.getOperand(0) == VecIn1) { 5162 BuildVecIndices.push_back(Extract.getOperand(1)); 5163 continue; 5164 } 5165 5166 // Otherwise, use InIdx + VecSize 5167 unsigned Idx = 5168 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 5169 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 5170 } 5171 5172 // Add count and size info. 5173 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5174 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes) 5175 return SDValue(); 5176 5177 // Return the new VECTOR_SHUFFLE node. 5178 SDValue Ops[5]; 5179 Ops[0] = VecIn1; 5180 if (VecIn2.getNode()) { 5181 Ops[1] = VecIn2; 5182 } else { 5183 // Use an undef build_vector as input for the second operand. 5184 std::vector<SDValue> UnOps(NumInScalars, 5185 DAG.getNode(ISD::UNDEF, 5186 EltType)); 5187 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 5188 &UnOps[0], UnOps.size()); 5189 AddToWorkList(Ops[1].getNode()); 5190 } 5191 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 5192 &BuildVecIndices[0], BuildVecIndices.size()); 5193 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 5194 } 5195 5196 return SDValue(); 5197} 5198 5199SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5200 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5201 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5202 // inputs come from at most two distinct vectors, turn this into a shuffle 5203 // node. 5204 5205 // If we only have one input vector, we don't need to do any concatenation. 5206 if (N->getNumOperands() == 1) { 5207 return N->getOperand(0); 5208 } 5209 5210 return SDValue(); 5211} 5212 5213SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5214 SDValue ShufMask = N->getOperand(2); 5215 unsigned NumElts = ShufMask.getNumOperands(); 5216 5217 SDValue N0 = N->getOperand(0); 5218 SDValue N1 = N->getOperand(1); 5219 5220 assert(N0.getValueType().getVectorNumElements() == NumElts && 5221 "Vector shuffle must be normalized in DAG"); 5222 5223 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5224 bool isIdentity = true; 5225 for (unsigned i = 0; i != NumElts; ++i) { 5226 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5227 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5228 isIdentity = false; 5229 break; 5230 } 5231 } 5232 if (isIdentity) return N->getOperand(0); 5233 5234 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5235 isIdentity = true; 5236 for (unsigned i = 0; i != NumElts; ++i) { 5237 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5238 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5239 i+NumElts) { 5240 isIdentity = false; 5241 break; 5242 } 5243 } 5244 if (isIdentity) return N->getOperand(1); 5245 5246 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5247 // needed at all. 5248 bool isUnary = true; 5249 bool isSplat = true; 5250 int VecNum = -1; 5251 unsigned BaseIdx = 0; 5252 for (unsigned i = 0; i != NumElts; ++i) 5253 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5254 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5255 int V = (Idx < NumElts) ? 0 : 1; 5256 if (VecNum == -1) { 5257 VecNum = V; 5258 BaseIdx = Idx; 5259 } else { 5260 if (BaseIdx != Idx) 5261 isSplat = false; 5262 if (VecNum != V) { 5263 isUnary = false; 5264 break; 5265 } 5266 } 5267 } 5268 5269 // Normalize unary shuffle so the RHS is undef. 5270 if (isUnary && VecNum == 1) 5271 std::swap(N0, N1); 5272 5273 // If it is a splat, check if the argument vector is a build_vector with 5274 // all scalar elements the same. 5275 if (isSplat) { 5276 SDNode *V = N0.getNode(); 5277 5278 // If this is a bit convert that changes the element type of the vector but 5279 // not the number of vector elements, look through it. Be careful not to 5280 // look though conversions that change things like v4f32 to v2f64. 5281 if (V->getOpcode() == ISD::BIT_CONVERT) { 5282 SDValue ConvInput = V->getOperand(0); 5283 if (ConvInput.getValueType().isVector() && 5284 ConvInput.getValueType().getVectorNumElements() == NumElts) 5285 V = ConvInput.getNode(); 5286 } 5287 5288 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5289 unsigned NumElems = V->getNumOperands(); 5290 if (NumElems > BaseIdx) { 5291 SDValue Base; 5292 bool AllSame = true; 5293 for (unsigned i = 0; i != NumElems; ++i) { 5294 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5295 Base = V->getOperand(i); 5296 break; 5297 } 5298 } 5299 // Splat of <u, u, u, u>, return <u, u, u, u> 5300 if (!Base.getNode()) 5301 return N0; 5302 for (unsigned i = 0; i != NumElems; ++i) { 5303 if (V->getOperand(i) != Base) { 5304 AllSame = false; 5305 break; 5306 } 5307 } 5308 // Splat of <x, x, x, x>, return <x, x, x, x> 5309 if (AllSame) 5310 return N0; 5311 } 5312 } 5313 } 5314 5315 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5316 // into an undef. 5317 if (isUnary || N0 == N1) { 5318 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5319 // first operand. 5320 SmallVector<SDValue, 8> MappedOps; 5321 for (unsigned i = 0; i != NumElts; ++i) { 5322 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5323 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5324 NumElts) { 5325 MappedOps.push_back(ShufMask.getOperand(i)); 5326 } else { 5327 unsigned NewIdx = 5328 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5329 NumElts; 5330 MappedOps.push_back(DAG.getConstant(NewIdx, 5331 ShufMask.getOperand(i).getValueType())); 5332 } 5333 } 5334 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5335 &MappedOps[0], MappedOps.size()); 5336 AddToWorkList(ShufMask.getNode()); 5337 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5338 N0, 5339 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5340 ShufMask); 5341 } 5342 5343 return SDValue(); 5344} 5345 5346/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5347/// an AND to a vector_shuffle with the destination vector and a zero vector. 5348/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5349/// vector_shuffle V, Zero, <0, 4, 2, 4> 5350SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5351 SDValue LHS = N->getOperand(0); 5352 SDValue RHS = N->getOperand(1); 5353 if (N->getOpcode() == ISD::AND) { 5354 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5355 RHS = RHS.getOperand(0); 5356 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5357 std::vector<SDValue> IdxOps; 5358 unsigned NumOps = RHS.getNumOperands(); 5359 unsigned NumElts = NumOps; 5360 for (unsigned i = 0; i != NumElts; ++i) { 5361 SDValue Elt = RHS.getOperand(i); 5362 if (!isa<ConstantSDNode>(Elt)) 5363 return SDValue(); 5364 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5365 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5366 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5367 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5368 else 5369 return SDValue(); 5370 } 5371 5372 // Let's see if the target supports this vector_shuffle. 5373 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5374 return SDValue(); 5375 5376 // Return the new VECTOR_SHUFFLE node. 5377 MVT EVT = RHS.getValueType().getVectorElementType(); 5378 MVT VT = MVT::getVectorVT(EVT, NumElts); 5379 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5380 std::vector<SDValue> Ops; 5381 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5382 Ops.push_back(LHS); 5383 AddToWorkList(LHS.getNode()); 5384 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5385 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5386 &ZeroOps[0], ZeroOps.size())); 5387 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5388 &IdxOps[0], IdxOps.size())); 5389 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5390 &Ops[0], Ops.size()); 5391 if (VT != N->getValueType(0)) 5392 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5393 return Result; 5394 } 5395 } 5396 return SDValue(); 5397} 5398 5399/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5400SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5401 // After legalize, the target may be depending on adds and other 5402 // binary ops to provide legal ways to construct constants or other 5403 // things. Simplifying them may result in a loss of legality. 5404 if (LegalOperations) return SDValue(); 5405 5406 MVT VT = N->getValueType(0); 5407 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5408 5409 MVT EltType = VT.getVectorElementType(); 5410 SDValue LHS = N->getOperand(0); 5411 SDValue RHS = N->getOperand(1); 5412 SDValue Shuffle = XformToShuffleWithZero(N); 5413 if (Shuffle.getNode()) return Shuffle; 5414 5415 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5416 // this operation. 5417 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5418 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5419 SmallVector<SDValue, 8> Ops; 5420 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5421 SDValue LHSOp = LHS.getOperand(i); 5422 SDValue RHSOp = RHS.getOperand(i); 5423 // If these two elements can't be folded, bail out. 5424 if ((LHSOp.getOpcode() != ISD::UNDEF && 5425 LHSOp.getOpcode() != ISD::Constant && 5426 LHSOp.getOpcode() != ISD::ConstantFP) || 5427 (RHSOp.getOpcode() != ISD::UNDEF && 5428 RHSOp.getOpcode() != ISD::Constant && 5429 RHSOp.getOpcode() != ISD::ConstantFP)) 5430 break; 5431 // Can't fold divide by zero. 5432 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5433 N->getOpcode() == ISD::FDIV) { 5434 if ((RHSOp.getOpcode() == ISD::Constant && 5435 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5436 (RHSOp.getOpcode() == ISD::ConstantFP && 5437 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5438 break; 5439 } 5440 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5441 AddToWorkList(Ops.back().getNode()); 5442 assert((Ops.back().getOpcode() == ISD::UNDEF || 5443 Ops.back().getOpcode() == ISD::Constant || 5444 Ops.back().getOpcode() == ISD::ConstantFP) && 5445 "Scalar binop didn't fold!"); 5446 } 5447 5448 if (Ops.size() == LHS.getNumOperands()) { 5449 MVT VT = LHS.getValueType(); 5450 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5451 } 5452 } 5453 5454 return SDValue(); 5455} 5456 5457SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5458 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5459 5460 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5461 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5462 // If we got a simplified select_cc node back from SimplifySelectCC, then 5463 // break it down into a new SETCC node, and a new SELECT node, and then return 5464 // the SELECT node, since we were called with a SELECT node. 5465 if (SCC.getNode()) { 5466 // Check to see if we got a select_cc back (to turn into setcc/select). 5467 // Otherwise, just return whatever node we got back, like fabs. 5468 if (SCC.getOpcode() == ISD::SELECT_CC) { 5469 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5470 SCC.getOperand(0), SCC.getOperand(1), 5471 SCC.getOperand(4)); 5472 AddToWorkList(SETCC.getNode()); 5473 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5474 SCC.getOperand(3), SETCC); 5475 } 5476 return SCC; 5477 } 5478 return SDValue(); 5479} 5480 5481/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5482/// are the two values being selected between, see if we can simplify the 5483/// select. Callers of this should assume that TheSelect is deleted if this 5484/// returns true. As such, they should return the appropriate thing (e.g. the 5485/// node) back to the top-level of the DAG combiner loop to avoid it being 5486/// looked at. 5487/// 5488bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5489 SDValue RHS) { 5490 5491 // If this is a select from two identical things, try to pull the operation 5492 // through the select. 5493 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5494 // If this is a load and the token chain is identical, replace the select 5495 // of two loads with a load through a select of the address to load from. 5496 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5497 // constants have been dropped into the constant pool. 5498 if (LHS.getOpcode() == ISD::LOAD && 5499 // Do not let this transformation reduce the number of volatile loads. 5500 !cast<LoadSDNode>(LHS)->isVolatile() && 5501 !cast<LoadSDNode>(RHS)->isVolatile() && 5502 // Token chains must be identical. 5503 LHS.getOperand(0) == RHS.getOperand(0)) { 5504 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5505 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5506 5507 // If this is an EXTLOAD, the VT's must match. 5508 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5509 // FIXME: this conflates two src values, discarding one. This is not 5510 // the right thing to do, but nothing uses srcvalues now. When they do, 5511 // turn SrcValue into a list of locations. 5512 SDValue Addr; 5513 if (TheSelect->getOpcode() == ISD::SELECT) { 5514 // Check that the condition doesn't reach either load. If so, folding 5515 // this will induce a cycle into the DAG. 5516 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5517 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5518 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5519 TheSelect->getOperand(0), LLD->getBasePtr(), 5520 RLD->getBasePtr()); 5521 } 5522 } else { 5523 // Check that the condition doesn't reach either load. If so, folding 5524 // this will induce a cycle into the DAG. 5525 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5526 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5527 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5528 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5529 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5530 TheSelect->getOperand(0), 5531 TheSelect->getOperand(1), 5532 LLD->getBasePtr(), RLD->getBasePtr(), 5533 TheSelect->getOperand(4)); 5534 } 5535 } 5536 5537 if (Addr.getNode()) { 5538 SDValue Load; 5539 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5540 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5541 Addr,LLD->getSrcValue(), 5542 LLD->getSrcValueOffset(), 5543 LLD->isVolatile(), 5544 LLD->getAlignment()); 5545 else { 5546 Load = DAG.getExtLoad(LLD->getExtensionType(), 5547 TheSelect->getValueType(0), 5548 LLD->getChain(), Addr, LLD->getSrcValue(), 5549 LLD->getSrcValueOffset(), 5550 LLD->getMemoryVT(), 5551 LLD->isVolatile(), 5552 LLD->getAlignment()); 5553 } 5554 // Users of the select now use the result of the load. 5555 CombineTo(TheSelect, Load); 5556 5557 // Users of the old loads now use the new load's chain. We know the 5558 // old-load value is dead now. 5559 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5560 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5561 return true; 5562 } 5563 } 5564 } 5565 } 5566 5567 return false; 5568} 5569 5570SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5571 SDValue N2, SDValue N3, 5572 ISD::CondCode CC, bool NotExtCompare) { 5573 5574 MVT VT = N2.getValueType(); 5575 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5576 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5577 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5578 5579 // Determine if the condition we're dealing with is constant 5580 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5581 N0, N1, CC, false); 5582 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5583 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5584 5585 // fold select_cc true, x, y -> x 5586 if (SCCC && !SCCC->isNullValue()) 5587 return N2; 5588 // fold select_cc false, x, y -> y 5589 if (SCCC && SCCC->isNullValue()) 5590 return N3; 5591 5592 // Check to see if we can simplify the select into an fabs node 5593 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5594 // Allow either -0.0 or 0.0 5595 if (CFP->getValueAPF().isZero()) { 5596 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5597 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5598 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5599 N2 == N3.getOperand(0)) 5600 return DAG.getNode(ISD::FABS, VT, N0); 5601 5602 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5603 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5604 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5605 N2.getOperand(0) == N3) 5606 return DAG.getNode(ISD::FABS, VT, N3); 5607 } 5608 } 5609 5610 // Check to see if we can perform the "gzip trick", transforming 5611 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5612 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5613 N0.getValueType().isInteger() && 5614 N2.getValueType().isInteger() && 5615 (N1C->isNullValue() || // (a < 0) ? b : 0 5616 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5617 MVT XType = N0.getValueType(); 5618 MVT AType = N2.getValueType(); 5619 if (XType.bitsGE(AType)) { 5620 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5621 // single-bit constant. 5622 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5623 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5624 ShCtV = XType.getSizeInBits()-ShCtV-1; 5625 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5626 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5627 AddToWorkList(Shift.getNode()); 5628 if (XType.bitsGT(AType)) { 5629 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5630 AddToWorkList(Shift.getNode()); 5631 } 5632 return DAG.getNode(ISD::AND, AType, Shift, N2); 5633 } 5634 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5635 DAG.getConstant(XType.getSizeInBits()-1, 5636 TLI.getShiftAmountTy())); 5637 AddToWorkList(Shift.getNode()); 5638 if (XType.bitsGT(AType)) { 5639 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5640 AddToWorkList(Shift.getNode()); 5641 } 5642 return DAG.getNode(ISD::AND, AType, Shift, N2); 5643 } 5644 } 5645 5646 // fold select C, 16, 0 -> shl C, 4 5647 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5648 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5649 5650 // If the caller doesn't want us to simplify this into a zext of a compare, 5651 // don't do it. 5652 if (NotExtCompare && N2C->getAPIntValue() == 1) 5653 return SDValue(); 5654 5655 // Get a SetCC of the condition 5656 // FIXME: Should probably make sure that setcc is legal if we ever have a 5657 // target where it isn't. 5658 SDValue Temp, SCC; 5659 // cast from setcc result type to select result type 5660 if (LegalTypes) { 5661 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0.getValueType()), 5662 N0, N1, CC); 5663 if (N2.getValueType().bitsLT(SCC.getValueType())) 5664 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5665 else 5666 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5667 } else { 5668 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5669 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5670 } 5671 AddToWorkList(SCC.getNode()); 5672 AddToWorkList(Temp.getNode()); 5673 5674 if (N2C->getAPIntValue() == 1) 5675 return Temp; 5676 // shl setcc result by log2 n2c 5677 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5678 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5679 TLI.getShiftAmountTy())); 5680 } 5681 5682 // Check to see if this is the equivalent of setcc 5683 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5684 // otherwise, go ahead with the folds. 5685 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5686 MVT XType = N0.getValueType(); 5687 if (!LegalOperations || 5688 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5689 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(XType), N0, N1, CC); 5690 if (Res.getValueType() != VT) 5691 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5692 return Res; 5693 } 5694 5695 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5696 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5697 (!LegalOperations || 5698 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5699 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5700 return DAG.getNode(ISD::SRL, XType, Ctlz, 5701 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5702 TLI.getShiftAmountTy())); 5703 } 5704 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5705 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5706 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5707 N0); 5708 SDValue NotN0 = DAG.getNOT(N0, XType); 5709 return DAG.getNode(ISD::SRL, XType, 5710 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5711 DAG.getConstant(XType.getSizeInBits()-1, 5712 TLI.getShiftAmountTy())); 5713 } 5714 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5715 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5716 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5717 DAG.getConstant(XType.getSizeInBits()-1, 5718 TLI.getShiftAmountTy())); 5719 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5720 } 5721 } 5722 5723 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5724 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5725 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5726 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5727 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5728 MVT XType = N0.getValueType(); 5729 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5730 DAG.getConstant(XType.getSizeInBits()-1, 5731 TLI.getShiftAmountTy())); 5732 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5733 AddToWorkList(Shift.getNode()); 5734 AddToWorkList(Add.getNode()); 5735 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5736 } 5737 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5738 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5739 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5740 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5741 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5742 MVT XType = N0.getValueType(); 5743 if (SubC->isNullValue() && XType.isInteger()) { 5744 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5745 DAG.getConstant(XType.getSizeInBits()-1, 5746 TLI.getShiftAmountTy())); 5747 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5748 AddToWorkList(Shift.getNode()); 5749 AddToWorkList(Add.getNode()); 5750 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5751 } 5752 } 5753 } 5754 5755 return SDValue(); 5756} 5757 5758/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5759SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5760 SDValue N1, ISD::CondCode Cond, 5761 bool foldBooleans) { 5762 TargetLowering::DAGCombinerInfo 5763 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5764 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5765} 5766 5767/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5768/// return a DAG expression to select that will generate the same value by 5769/// multiplying by a magic number. See: 5770/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5771SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5772 std::vector<SDNode*> Built; 5773 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5774 5775 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5776 ii != ee; ++ii) 5777 AddToWorkList(*ii); 5778 return S; 5779} 5780 5781/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5782/// return a DAG expression to select that will generate the same value by 5783/// multiplying by a magic number. See: 5784/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5785SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5786 std::vector<SDNode*> Built; 5787 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5788 5789 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5790 ii != ee; ++ii) 5791 AddToWorkList(*ii); 5792 return S; 5793} 5794 5795/// FindBaseOffset - Return true if base is known not to alias with anything 5796/// but itself. Provides base object and offset as results. 5797static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5798 // Assume it is a primitive operation. 5799 Base = Ptr; Offset = 0; 5800 5801 // If it's an adding a simple constant then integrate the offset. 5802 if (Base.getOpcode() == ISD::ADD) { 5803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5804 Base = Base.getOperand(0); 5805 Offset += C->getZExtValue(); 5806 } 5807 } 5808 5809 // If it's any of the following then it can't alias with anything but itself. 5810 return isa<FrameIndexSDNode>(Base) || 5811 isa<ConstantPoolSDNode>(Base) || 5812 isa<GlobalAddressSDNode>(Base); 5813} 5814 5815/// isAlias - Return true if there is any possibility that the two addresses 5816/// overlap. 5817bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5818 const Value *SrcValue1, int SrcValueOffset1, 5819 SDValue Ptr2, int64_t Size2, 5820 const Value *SrcValue2, int SrcValueOffset2) 5821{ 5822 // If they are the same then they must be aliases. 5823 if (Ptr1 == Ptr2) return true; 5824 5825 // Gather base node and offset information. 5826 SDValue Base1, Base2; 5827 int64_t Offset1, Offset2; 5828 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5829 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5830 5831 // If they have a same base address then... 5832 if (Base1 == Base2) { 5833 // Check to see if the addresses overlap. 5834 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5835 } 5836 5837 // If we know both bases then they can't alias. 5838 if (KnownBase1 && KnownBase2) return false; 5839 5840 if (CombinerGlobalAA) { 5841 // Use alias analysis information. 5842 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5843 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5844 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5845 AliasAnalysis::AliasResult AAResult = 5846 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5847 if (AAResult == AliasAnalysis::NoAlias) 5848 return false; 5849 } 5850 5851 // Otherwise we have to assume they alias. 5852 return true; 5853} 5854 5855/// FindAliasInfo - Extracts the relevant alias information from the memory 5856/// node. Returns true if the operand was a load. 5857bool DAGCombiner::FindAliasInfo(SDNode *N, 5858 SDValue &Ptr, int64_t &Size, 5859 const Value *&SrcValue, int &SrcValueOffset) { 5860 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5861 Ptr = LD->getBasePtr(); 5862 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5863 SrcValue = LD->getSrcValue(); 5864 SrcValueOffset = LD->getSrcValueOffset(); 5865 return true; 5866 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5867 Ptr = ST->getBasePtr(); 5868 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5869 SrcValue = ST->getSrcValue(); 5870 SrcValueOffset = ST->getSrcValueOffset(); 5871 } else { 5872 assert(0 && "FindAliasInfo expected a memory operand"); 5873 } 5874 5875 return false; 5876} 5877 5878/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5879/// looking for aliasing nodes and adding them to the Aliases vector. 5880void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5881 SmallVector<SDValue, 8> &Aliases) { 5882 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5883 std::set<SDNode *> Visited; // Visited node set. 5884 5885 // Get alias information for node. 5886 SDValue Ptr; 5887 int64_t Size; 5888 const Value *SrcValue; 5889 int SrcValueOffset; 5890 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5891 5892 // Starting off. 5893 Chains.push_back(OriginalChain); 5894 5895 // Look at each chain and determine if it is an alias. If so, add it to the 5896 // aliases list. If not, then continue up the chain looking for the next 5897 // candidate. 5898 while (!Chains.empty()) { 5899 SDValue Chain = Chains.back(); 5900 Chains.pop_back(); 5901 5902 // Don't bother if we've been before. 5903 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5904 Visited.insert(Chain.getNode()); 5905 5906 switch (Chain.getOpcode()) { 5907 case ISD::EntryToken: 5908 // Entry token is ideal chain operand, but handled in FindBetterChain. 5909 break; 5910 5911 case ISD::LOAD: 5912 case ISD::STORE: { 5913 // Get alias information for Chain. 5914 SDValue OpPtr; 5915 int64_t OpSize; 5916 const Value *OpSrcValue; 5917 int OpSrcValueOffset; 5918 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5919 OpSrcValue, OpSrcValueOffset); 5920 5921 // If chain is alias then stop here. 5922 if (!(IsLoad && IsOpLoad) && 5923 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5924 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5925 Aliases.push_back(Chain); 5926 } else { 5927 // Look further up the chain. 5928 Chains.push_back(Chain.getOperand(0)); 5929 // Clean up old chain. 5930 AddToWorkList(Chain.getNode()); 5931 } 5932 break; 5933 } 5934 5935 case ISD::TokenFactor: 5936 // We have to check each of the operands of the token factor, so we queue 5937 // then up. Adding the operands to the queue (stack) in reverse order 5938 // maintains the original order and increases the likelihood that getNode 5939 // will find a matching token factor (CSE.) 5940 for (unsigned n = Chain.getNumOperands(); n;) 5941 Chains.push_back(Chain.getOperand(--n)); 5942 // Eliminate the token factor if we can. 5943 AddToWorkList(Chain.getNode()); 5944 break; 5945 5946 default: 5947 // For all other instructions we will just have to take what we can get. 5948 Aliases.push_back(Chain); 5949 break; 5950 } 5951 } 5952} 5953 5954/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5955/// for a better chain (aliasing node.) 5956SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5957 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5958 5959 // Accumulate all the aliases to this node. 5960 GatherAllAliases(N, OldChain, Aliases); 5961 5962 if (Aliases.size() == 0) { 5963 // If no operands then chain to entry token. 5964 return DAG.getEntryNode(); 5965 } else if (Aliases.size() == 1) { 5966 // If a single operand then chain to it. We don't need to revisit it. 5967 return Aliases[0]; 5968 } 5969 5970 // Construct a custom tailored token factor. 5971 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5972 &Aliases[0], Aliases.size()); 5973 5974 // Make sure the old chain gets cleaned up. 5975 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5976 5977 return NewChain; 5978} 5979 5980// SelectionDAG::Combine - This is the entry point for the file. 5981// 5982void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { 5983 /// run - This is the main entry point to this class. 5984 /// 5985 DAGCombiner(*this, AA, Fast).Run(Level); 5986} 5987