DAGCombiner.cpp revision 6c327f92a562d9d280bdbc3bde3c0ce269a4c65c
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/SmallPtrSet.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/Analysis/AliasAnalysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/IR/DataLayout.h" 27#include "llvm/IR/DerivedTypes.h" 28#include "llvm/IR/Function.h" 29#include "llvm/IR/LLVMContext.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include <algorithm> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 // 68 // This has the semantics that when adding to the worklist, 69 // the item added must be next to be processed. It should 70 // also only appear once. The naive approach to this takes 71 // linear time. 72 // 73 // To reduce the insert/remove time to logarithmic, we use 74 // a set and a vector to maintain our worklist. 75 // 76 // The set contains the items on the worklist, but does not 77 // maintain the order they should be visited. 78 // 79 // The vector maintains the order nodes should be visited, but may 80 // contain duplicate or removed nodes. When choosing a node to 81 // visit, we pop off the order stack until we find an item that is 82 // also in the contents set. All operations are O(log N). 83 SmallPtrSet<SDNode*, 64> WorkListContents; 84 SmallVector<SDNode*, 64> WorkListOrder; 85 86 // AA - Used for DAG load/store alias analysis. 87 AliasAnalysis &AA; 88 89 /// AddUsersToWorkList - When an instruction is simplified, add all users of 90 /// the instruction to the work lists because they might get more simplified 91 /// now. 92 /// 93 void AddUsersToWorkList(SDNode *N) { 94 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 95 UI != UE; ++UI) 96 AddToWorkList(*UI); 97 } 98 99 /// visit - call the node-specific routine that knows how to fold each 100 /// particular type of node. 101 SDValue visit(SDNode *N); 102 103 public: 104 /// AddToWorkList - Add to the work list making sure its instance is at the 105 /// back (next to be processed.) 106 void AddToWorkList(SDNode *N) { 107 WorkListContents.insert(N); 108 WorkListOrder.push_back(N); 109 } 110 111 /// removeFromWorkList - remove all instances of N from the worklist. 112 /// 113 void removeFromWorkList(SDNode *N) { 114 WorkListContents.erase(N); 115 } 116 117 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 118 bool AddTo = true); 119 120 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 121 return CombineTo(N, &Res, 1, AddTo); 122 } 123 124 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 125 bool AddTo = true) { 126 SDValue To[] = { Res0, Res1 }; 127 return CombineTo(N, To, 2, AddTo); 128 } 129 130 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 131 132 private: 133 134 /// SimplifyDemandedBits - Check the specified integer node value to see if 135 /// it can be simplified or if things it uses can be simplified by bit 136 /// propagation. If so, return true. 137 bool SimplifyDemandedBits(SDValue Op) { 138 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 139 APInt Demanded = APInt::getAllOnesValue(BitWidth); 140 return SimplifyDemandedBits(Op, Demanded); 141 } 142 143 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 144 145 bool CombineToPreIndexedLoadStore(SDNode *N); 146 bool CombineToPostIndexedLoadStore(SDNode *N); 147 148 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 149 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 150 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 152 SDValue PromoteIntBinOp(SDValue Op); 153 SDValue PromoteIntShiftOp(SDValue Op); 154 SDValue PromoteExtend(SDValue Op); 155 bool PromoteLoad(SDValue Op); 156 157 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 158 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 159 ISD::NodeType ExtType); 160 161 /// combine - call the node-specific routine that knows how to fold each 162 /// particular type of node. If that doesn't do anything, try the 163 /// target-specific DAG combines. 164 SDValue combine(SDNode *N); 165 166 // Visitation implementation - Implement dag node combining for different 167 // node types. The semantics are as follows: 168 // Return Value: 169 // SDValue.getNode() == 0 - No change was made 170 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 171 // otherwise - N should be replaced by the returned Operand. 172 // 173 SDValue visitTokenFactor(SDNode *N); 174 SDValue visitMERGE_VALUES(SDNode *N); 175 SDValue visitADD(SDNode *N); 176 SDValue visitSUB(SDNode *N); 177 SDValue visitADDC(SDNode *N); 178 SDValue visitSUBC(SDNode *N); 179 SDValue visitADDE(SDNode *N); 180 SDValue visitSUBE(SDNode *N); 181 SDValue visitMUL(SDNode *N); 182 SDValue visitSDIV(SDNode *N); 183 SDValue visitUDIV(SDNode *N); 184 SDValue visitSREM(SDNode *N); 185 SDValue visitUREM(SDNode *N); 186 SDValue visitMULHU(SDNode *N); 187 SDValue visitMULHS(SDNode *N); 188 SDValue visitSMUL_LOHI(SDNode *N); 189 SDValue visitUMUL_LOHI(SDNode *N); 190 SDValue visitSMULO(SDNode *N); 191 SDValue visitUMULO(SDNode *N); 192 SDValue visitSDIVREM(SDNode *N); 193 SDValue visitUDIVREM(SDNode *N); 194 SDValue visitAND(SDNode *N); 195 SDValue visitOR(SDNode *N); 196 SDValue visitXOR(SDNode *N); 197 SDValue SimplifyVBinOp(SDNode *N); 198 SDValue SimplifyVUnaryOp(SDNode *N); 199 SDValue visitSHL(SDNode *N); 200 SDValue visitSRA(SDNode *N); 201 SDValue visitSRL(SDNode *N); 202 SDValue visitCTLZ(SDNode *N); 203 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 204 SDValue visitCTTZ(SDNode *N); 205 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 206 SDValue visitCTPOP(SDNode *N); 207 SDValue visitSELECT(SDNode *N); 208 SDValue visitSELECT_CC(SDNode *N); 209 SDValue visitSETCC(SDNode *N); 210 SDValue visitSIGN_EXTEND(SDNode *N); 211 SDValue visitZERO_EXTEND(SDNode *N); 212 SDValue visitANY_EXTEND(SDNode *N); 213 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 214 SDValue visitTRUNCATE(SDNode *N); 215 SDValue visitBITCAST(SDNode *N); 216 SDValue visitBUILD_PAIR(SDNode *N); 217 SDValue visitFADD(SDNode *N); 218 SDValue visitFSUB(SDNode *N); 219 SDValue visitFMUL(SDNode *N); 220 SDValue visitFMA(SDNode *N); 221 SDValue visitFDIV(SDNode *N); 222 SDValue visitFREM(SDNode *N); 223 SDValue visitFCOPYSIGN(SDNode *N); 224 SDValue visitSINT_TO_FP(SDNode *N); 225 SDValue visitUINT_TO_FP(SDNode *N); 226 SDValue visitFP_TO_SINT(SDNode *N); 227 SDValue visitFP_TO_UINT(SDNode *N); 228 SDValue visitFP_ROUND(SDNode *N); 229 SDValue visitFP_ROUND_INREG(SDNode *N); 230 SDValue visitFP_EXTEND(SDNode *N); 231 SDValue visitFNEG(SDNode *N); 232 SDValue visitFABS(SDNode *N); 233 SDValue visitFCEIL(SDNode *N); 234 SDValue visitFTRUNC(SDNode *N); 235 SDValue visitFFLOOR(SDNode *N); 236 SDValue visitBRCOND(SDNode *N); 237 SDValue visitBR_CC(SDNode *N); 238 SDValue visitLOAD(SDNode *N); 239 SDValue visitSTORE(SDNode *N); 240 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 241 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 242 SDValue visitBUILD_VECTOR(SDNode *N); 243 SDValue visitCONCAT_VECTORS(SDNode *N); 244 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 245 SDValue visitVECTOR_SHUFFLE(SDNode *N); 246 SDValue visitMEMBARRIER(SDNode *N); 247 248 SDValue XformToShuffleWithZero(SDNode *N); 249 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 250 251 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 252 253 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 254 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 255 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 256 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 257 SDValue N3, ISD::CondCode CC, 258 bool NotExtCompare = false); 259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 260 DebugLoc DL, bool foldBooleans = true); 261 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 262 unsigned HiOp); 263 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 264 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 265 SDValue BuildSDIV(SDNode *N); 266 SDValue BuildUDIV(SDNode *N); 267 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 268 bool DemandHighBits = true); 269 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 270 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 271 SDValue ReduceLoadWidth(SDNode *N); 272 SDValue ReduceLoadOpStoreWidth(SDNode *N); 273 SDValue TransformFPLoadStorePair(SDNode *N); 274 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N); 275 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N); 276 277 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 278 279 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 280 /// looking for aliasing nodes and adding them to the Aliases vector. 281 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 282 SmallVector<SDValue, 8> &Aliases); 283 284 /// isAlias - Return true if there is any possibility that the two addresses 285 /// overlap. 286 bool isAlias(SDValue Ptr1, int64_t Size1, 287 const Value *SrcValue1, int SrcValueOffset1, 288 unsigned SrcValueAlign1, 289 const MDNode *TBAAInfo1, 290 SDValue Ptr2, int64_t Size2, 291 const Value *SrcValue2, int SrcValueOffset2, 292 unsigned SrcValueAlign2, 293 const MDNode *TBAAInfo2) const; 294 295 /// isAlias - Return true if there is any possibility that the two addresses 296 /// overlap. 297 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1); 298 299 /// FindAliasInfo - Extracts the relevant alias information from the memory 300 /// node. Returns true if the operand was a load. 301 bool FindAliasInfo(SDNode *N, 302 SDValue &Ptr, int64_t &Size, 303 const Value *&SrcValue, int &SrcValueOffset, 304 unsigned &SrcValueAlignment, 305 const MDNode *&TBAAInfo) const; 306 307 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 308 /// looking for a better chain (aliasing node.) 309 SDValue FindBetterChain(SDNode *N, SDValue Chain); 310 311 /// Merge consecutive store operations into a wide store. 312 /// This optimization uses wide integers or vectors when possible. 313 /// \return True if some memory operations were changed. 314 bool MergeConsecutiveStores(StoreSDNode *N); 315 316 public: 317 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 318 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 319 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 320 321 /// Run - runs the dag combiner on all nodes in the work list 322 void Run(CombineLevel AtLevel); 323 324 SelectionDAG &getDAG() const { return DAG; } 325 326 /// getShiftAmountTy - Returns a type large enough to hold any valid 327 /// shift amount - before type legalization these can be huge. 328 EVT getShiftAmountTy(EVT LHSTy) { 329 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 330 } 331 332 /// isTypeLegal - This method returns true if we are running before type 333 /// legalization or if the specified VT is legal. 334 bool isTypeLegal(const EVT &VT) { 335 if (!LegalTypes) return true; 336 return TLI.isTypeLegal(VT); 337 } 338 }; 339} 340 341 342namespace { 343/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 344/// nodes from the worklist. 345class WorkListRemover : public SelectionDAG::DAGUpdateListener { 346 DAGCombiner &DC; 347public: 348 explicit WorkListRemover(DAGCombiner &dc) 349 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 350 351 virtual void NodeDeleted(SDNode *N, SDNode *E) { 352 DC.removeFromWorkList(N); 353 } 354}; 355} 356 357//===----------------------------------------------------------------------===// 358// TargetLowering::DAGCombinerInfo implementation 359//===----------------------------------------------------------------------===// 360 361void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 362 ((DAGCombiner*)DC)->AddToWorkList(N); 363} 364 365void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 366 ((DAGCombiner*)DC)->removeFromWorkList(N); 367} 368 369SDValue TargetLowering::DAGCombinerInfo:: 370CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 371 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 372} 373 374SDValue TargetLowering::DAGCombinerInfo:: 375CombineTo(SDNode *N, SDValue Res, bool AddTo) { 376 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 377} 378 379 380SDValue TargetLowering::DAGCombinerInfo:: 381CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 382 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 383} 384 385void TargetLowering::DAGCombinerInfo:: 386CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 387 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 388} 389 390//===----------------------------------------------------------------------===// 391// Helper Functions 392//===----------------------------------------------------------------------===// 393 394/// isNegatibleForFree - Return 1 if we can compute the negated form of the 395/// specified expression for the same cost as the expression itself, or 2 if we 396/// can compute the negated form more cheaply than the expression itself. 397static char isNegatibleForFree(SDValue Op, bool LegalOperations, 398 const TargetLowering &TLI, 399 const TargetOptions *Options, 400 unsigned Depth = 0) { 401 // fneg is removable even if it has multiple uses. 402 if (Op.getOpcode() == ISD::FNEG) return 2; 403 404 // Don't allow anything with multiple uses. 405 if (!Op.hasOneUse()) return 0; 406 407 // Don't recurse exponentially. 408 if (Depth > 6) return 0; 409 410 switch (Op.getOpcode()) { 411 default: return false; 412 case ISD::ConstantFP: 413 // Don't invert constant FP values after legalize. The negated constant 414 // isn't necessarily legal. 415 return LegalOperations ? 0 : 1; 416 case ISD::FADD: 417 // FIXME: determine better conditions for this xform. 418 if (!Options->UnsafeFPMath) return 0; 419 420 // After operation legalization, it might not be legal to create new FSUBs. 421 if (LegalOperations && 422 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 423 return 0; 424 425 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 426 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 427 Options, Depth + 1)) 428 return V; 429 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 430 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 431 Depth + 1); 432 case ISD::FSUB: 433 // We can't turn -(A-B) into B-A when we honor signed zeros. 434 if (!Options->UnsafeFPMath) return 0; 435 436 // fold (fneg (fsub A, B)) -> (fsub B, A) 437 return 1; 438 439 case ISD::FMUL: 440 case ISD::FDIV: 441 if (Options->HonorSignDependentRoundingFPMath()) return 0; 442 443 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 444 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 445 Options, Depth + 1)) 446 return V; 447 448 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 449 Depth + 1); 450 451 case ISD::FP_EXTEND: 452 case ISD::FP_ROUND: 453 case ISD::FSIN: 454 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 455 Depth + 1); 456 } 457} 458 459/// GetNegatedExpression - If isNegatibleForFree returns true, this function 460/// returns the newly negated expression. 461static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 462 bool LegalOperations, unsigned Depth = 0) { 463 // fneg is removable even if it has multiple uses. 464 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 465 466 // Don't allow anything with multiple uses. 467 assert(Op.hasOneUse() && "Unknown reuse!"); 468 469 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 470 switch (Op.getOpcode()) { 471 default: llvm_unreachable("Unknown code"); 472 case ISD::ConstantFP: { 473 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 474 V.changeSign(); 475 return DAG.getConstantFP(V, Op.getValueType()); 476 } 477 case ISD::FADD: 478 // FIXME: determine better conditions for this xform. 479 assert(DAG.getTarget().Options.UnsafeFPMath); 480 481 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 482 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 483 DAG.getTargetLoweringInfo(), 484 &DAG.getTarget().Options, Depth+1)) 485 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 486 GetNegatedExpression(Op.getOperand(0), DAG, 487 LegalOperations, Depth+1), 488 Op.getOperand(1)); 489 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 490 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 491 GetNegatedExpression(Op.getOperand(1), DAG, 492 LegalOperations, Depth+1), 493 Op.getOperand(0)); 494 case ISD::FSUB: 495 // We can't turn -(A-B) into B-A when we honor signed zeros. 496 assert(DAG.getTarget().Options.UnsafeFPMath); 497 498 // fold (fneg (fsub 0, B)) -> B 499 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 500 if (N0CFP->getValueAPF().isZero()) 501 return Op.getOperand(1); 502 503 // fold (fneg (fsub A, B)) -> (fsub B, A) 504 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 505 Op.getOperand(1), Op.getOperand(0)); 506 507 case ISD::FMUL: 508 case ISD::FDIV: 509 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 510 511 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 512 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 513 DAG.getTargetLoweringInfo(), 514 &DAG.getTarget().Options, Depth+1)) 515 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 516 GetNegatedExpression(Op.getOperand(0), DAG, 517 LegalOperations, Depth+1), 518 Op.getOperand(1)); 519 520 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 521 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 522 Op.getOperand(0), 523 GetNegatedExpression(Op.getOperand(1), DAG, 524 LegalOperations, Depth+1)); 525 526 case ISD::FP_EXTEND: 527 case ISD::FSIN: 528 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 529 GetNegatedExpression(Op.getOperand(0), DAG, 530 LegalOperations, Depth+1)); 531 case ISD::FP_ROUND: 532 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 533 GetNegatedExpression(Op.getOperand(0), DAG, 534 LegalOperations, Depth+1), 535 Op.getOperand(1)); 536 } 537} 538 539 540// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 541// that selects between the values 1 and 0, making it equivalent to a setcc. 542// Also, set the incoming LHS, RHS, and CC references to the appropriate 543// nodes based on the type of node we are checking. This simplifies life a 544// bit for the callers. 545static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 546 SDValue &CC) { 547 if (N.getOpcode() == ISD::SETCC) { 548 LHS = N.getOperand(0); 549 RHS = N.getOperand(1); 550 CC = N.getOperand(2); 551 return true; 552 } 553 if (N.getOpcode() == ISD::SELECT_CC && 554 N.getOperand(2).getOpcode() == ISD::Constant && 555 N.getOperand(3).getOpcode() == ISD::Constant && 556 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 557 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 558 LHS = N.getOperand(0); 559 RHS = N.getOperand(1); 560 CC = N.getOperand(4); 561 return true; 562 } 563 return false; 564} 565 566// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 567// one use. If this is true, it allows the users to invert the operation for 568// free when it is profitable to do so. 569static bool isOneUseSetCC(SDValue N) { 570 SDValue N0, N1, N2; 571 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 572 return true; 573 return false; 574} 575 576SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 577 SDValue N0, SDValue N1) { 578 EVT VT = N0.getValueType(); 579 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 580 if (isa<ConstantSDNode>(N1)) { 581 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 582 SDValue OpNode = 583 DAG.FoldConstantArithmetic(Opc, VT, 584 cast<ConstantSDNode>(N0.getOperand(1)), 585 cast<ConstantSDNode>(N1)); 586 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 587 } 588 if (N0.hasOneUse()) { 589 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 590 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 591 N0.getOperand(0), N1); 592 AddToWorkList(OpNode.getNode()); 593 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 594 } 595 } 596 597 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 598 if (isa<ConstantSDNode>(N0)) { 599 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 600 SDValue OpNode = 601 DAG.FoldConstantArithmetic(Opc, VT, 602 cast<ConstantSDNode>(N1.getOperand(1)), 603 cast<ConstantSDNode>(N0)); 604 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 605 } 606 if (N1.hasOneUse()) { 607 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 608 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 609 N1.getOperand(0), N0); 610 AddToWorkList(OpNode.getNode()); 611 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 612 } 613 } 614 615 return SDValue(); 616} 617 618SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 619 bool AddTo) { 620 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 621 ++NodesCombined; 622 DEBUG(dbgs() << "\nReplacing.1 "; 623 N->dump(&DAG); 624 dbgs() << "\nWith: "; 625 To[0].getNode()->dump(&DAG); 626 dbgs() << " and " << NumTo-1 << " other values\n"; 627 for (unsigned i = 0, e = NumTo; i != e; ++i) 628 assert((!To[i].getNode() || 629 N->getValueType(i) == To[i].getValueType()) && 630 "Cannot combine value to value of different type!")); 631 WorkListRemover DeadNodes(*this); 632 DAG.ReplaceAllUsesWith(N, To); 633 if (AddTo) { 634 // Push the new nodes and any users onto the worklist 635 for (unsigned i = 0, e = NumTo; i != e; ++i) { 636 if (To[i].getNode()) { 637 AddToWorkList(To[i].getNode()); 638 AddUsersToWorkList(To[i].getNode()); 639 } 640 } 641 } 642 643 // Finally, if the node is now dead, remove it from the graph. The node 644 // may not be dead if the replacement process recursively simplified to 645 // something else needing this node. 646 if (N->use_empty()) { 647 // Nodes can be reintroduced into the worklist. Make sure we do not 648 // process a node that has been replaced. 649 removeFromWorkList(N); 650 651 // Finally, since the node is now dead, remove it from the graph. 652 DAG.DeleteNode(N); 653 } 654 return SDValue(N, 0); 655} 656 657void DAGCombiner:: 658CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 659 // Replace all uses. If any nodes become isomorphic to other nodes and 660 // are deleted, make sure to remove them from our worklist. 661 WorkListRemover DeadNodes(*this); 662 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 663 664 // Push the new node and any (possibly new) users onto the worklist. 665 AddToWorkList(TLO.New.getNode()); 666 AddUsersToWorkList(TLO.New.getNode()); 667 668 // Finally, if the node is now dead, remove it from the graph. The node 669 // may not be dead if the replacement process recursively simplified to 670 // something else needing this node. 671 if (TLO.Old.getNode()->use_empty()) { 672 removeFromWorkList(TLO.Old.getNode()); 673 674 // If the operands of this node are only used by the node, they will now 675 // be dead. Make sure to visit them first to delete dead nodes early. 676 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 677 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 678 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 679 680 DAG.DeleteNode(TLO.Old.getNode()); 681 } 682} 683 684/// SimplifyDemandedBits - Check the specified integer node value to see if 685/// it can be simplified or if things it uses can be simplified by bit 686/// propagation. If so, return true. 687bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 688 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 689 APInt KnownZero, KnownOne; 690 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 691 return false; 692 693 // Revisit the node. 694 AddToWorkList(Op.getNode()); 695 696 // Replace the old value with the new one. 697 ++NodesCombined; 698 DEBUG(dbgs() << "\nReplacing.2 "; 699 TLO.Old.getNode()->dump(&DAG); 700 dbgs() << "\nWith: "; 701 TLO.New.getNode()->dump(&DAG); 702 dbgs() << '\n'); 703 704 CommitTargetLoweringOpt(TLO); 705 return true; 706} 707 708void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 709 DebugLoc dl = Load->getDebugLoc(); 710 EVT VT = Load->getValueType(0); 711 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 712 713 DEBUG(dbgs() << "\nReplacing.9 "; 714 Load->dump(&DAG); 715 dbgs() << "\nWith: "; 716 Trunc.getNode()->dump(&DAG); 717 dbgs() << '\n'); 718 WorkListRemover DeadNodes(*this); 719 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 720 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 721 removeFromWorkList(Load); 722 DAG.DeleteNode(Load); 723 AddToWorkList(Trunc.getNode()); 724} 725 726SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 727 Replace = false; 728 DebugLoc dl = Op.getDebugLoc(); 729 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 730 EVT MemVT = LD->getMemoryVT(); 731 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 732 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 733 : ISD::EXTLOAD) 734 : LD->getExtensionType(); 735 Replace = true; 736 return DAG.getExtLoad(ExtType, dl, PVT, 737 LD->getChain(), LD->getBasePtr(), 738 LD->getPointerInfo(), 739 MemVT, LD->isVolatile(), 740 LD->isNonTemporal(), LD->getAlignment()); 741 } 742 743 unsigned Opc = Op.getOpcode(); 744 switch (Opc) { 745 default: break; 746 case ISD::AssertSext: 747 return DAG.getNode(ISD::AssertSext, dl, PVT, 748 SExtPromoteOperand(Op.getOperand(0), PVT), 749 Op.getOperand(1)); 750 case ISD::AssertZext: 751 return DAG.getNode(ISD::AssertZext, dl, PVT, 752 ZExtPromoteOperand(Op.getOperand(0), PVT), 753 Op.getOperand(1)); 754 case ISD::Constant: { 755 unsigned ExtOpc = 756 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 757 return DAG.getNode(ExtOpc, dl, PVT, Op); 758 } 759 } 760 761 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 762 return SDValue(); 763 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 764} 765 766SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 767 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 768 return SDValue(); 769 EVT OldVT = Op.getValueType(); 770 DebugLoc dl = Op.getDebugLoc(); 771 bool Replace = false; 772 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 773 if (NewOp.getNode() == 0) 774 return SDValue(); 775 AddToWorkList(NewOp.getNode()); 776 777 if (Replace) 778 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 779 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 780 DAG.getValueType(OldVT)); 781} 782 783SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 784 EVT OldVT = Op.getValueType(); 785 DebugLoc dl = Op.getDebugLoc(); 786 bool Replace = false; 787 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 788 if (NewOp.getNode() == 0) 789 return SDValue(); 790 AddToWorkList(NewOp.getNode()); 791 792 if (Replace) 793 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 794 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 795} 796 797/// PromoteIntBinOp - Promote the specified integer binary operation if the 798/// target indicates it is beneficial. e.g. On x86, it's usually better to 799/// promote i16 operations to i32 since i16 instructions are longer. 800SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 801 if (!LegalOperations) 802 return SDValue(); 803 804 EVT VT = Op.getValueType(); 805 if (VT.isVector() || !VT.isInteger()) 806 return SDValue(); 807 808 // If operation type is 'undesirable', e.g. i16 on x86, consider 809 // promoting it. 810 unsigned Opc = Op.getOpcode(); 811 if (TLI.isTypeDesirableForOp(Opc, VT)) 812 return SDValue(); 813 814 EVT PVT = VT; 815 // Consult target whether it is a good idea to promote this operation and 816 // what's the right type to promote it to. 817 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 818 assert(PVT != VT && "Don't know what type to promote to!"); 819 820 bool Replace0 = false; 821 SDValue N0 = Op.getOperand(0); 822 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 823 if (NN0.getNode() == 0) 824 return SDValue(); 825 826 bool Replace1 = false; 827 SDValue N1 = Op.getOperand(1); 828 SDValue NN1; 829 if (N0 == N1) 830 NN1 = NN0; 831 else { 832 NN1 = PromoteOperand(N1, PVT, Replace1); 833 if (NN1.getNode() == 0) 834 return SDValue(); 835 } 836 837 AddToWorkList(NN0.getNode()); 838 if (NN1.getNode()) 839 AddToWorkList(NN1.getNode()); 840 841 if (Replace0) 842 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 843 if (Replace1) 844 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 845 846 DEBUG(dbgs() << "\nPromoting "; 847 Op.getNode()->dump(&DAG)); 848 DebugLoc dl = Op.getDebugLoc(); 849 return DAG.getNode(ISD::TRUNCATE, dl, VT, 850 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 851 } 852 return SDValue(); 853} 854 855/// PromoteIntShiftOp - Promote the specified integer shift operation if the 856/// target indicates it is beneficial. e.g. On x86, it's usually better to 857/// promote i16 operations to i32 since i16 instructions are longer. 858SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 859 if (!LegalOperations) 860 return SDValue(); 861 862 EVT VT = Op.getValueType(); 863 if (VT.isVector() || !VT.isInteger()) 864 return SDValue(); 865 866 // If operation type is 'undesirable', e.g. i16 on x86, consider 867 // promoting it. 868 unsigned Opc = Op.getOpcode(); 869 if (TLI.isTypeDesirableForOp(Opc, VT)) 870 return SDValue(); 871 872 EVT PVT = VT; 873 // Consult target whether it is a good idea to promote this operation and 874 // what's the right type to promote it to. 875 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 876 assert(PVT != VT && "Don't know what type to promote to!"); 877 878 bool Replace = false; 879 SDValue N0 = Op.getOperand(0); 880 if (Opc == ISD::SRA) 881 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 882 else if (Opc == ISD::SRL) 883 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 884 else 885 N0 = PromoteOperand(N0, PVT, Replace); 886 if (N0.getNode() == 0) 887 return SDValue(); 888 889 AddToWorkList(N0.getNode()); 890 if (Replace) 891 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 892 893 DEBUG(dbgs() << "\nPromoting "; 894 Op.getNode()->dump(&DAG)); 895 DebugLoc dl = Op.getDebugLoc(); 896 return DAG.getNode(ISD::TRUNCATE, dl, VT, 897 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 898 } 899 return SDValue(); 900} 901 902SDValue DAGCombiner::PromoteExtend(SDValue Op) { 903 if (!LegalOperations) 904 return SDValue(); 905 906 EVT VT = Op.getValueType(); 907 if (VT.isVector() || !VT.isInteger()) 908 return SDValue(); 909 910 // If operation type is 'undesirable', e.g. i16 on x86, consider 911 // promoting it. 912 unsigned Opc = Op.getOpcode(); 913 if (TLI.isTypeDesirableForOp(Opc, VT)) 914 return SDValue(); 915 916 EVT PVT = VT; 917 // Consult target whether it is a good idea to promote this operation and 918 // what's the right type to promote it to. 919 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 920 assert(PVT != VT && "Don't know what type to promote to!"); 921 // fold (aext (aext x)) -> (aext x) 922 // fold (aext (zext x)) -> (zext x) 923 // fold (aext (sext x)) -> (sext x) 924 DEBUG(dbgs() << "\nPromoting "; 925 Op.getNode()->dump(&DAG)); 926 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 927 } 928 return SDValue(); 929} 930 931bool DAGCombiner::PromoteLoad(SDValue Op) { 932 if (!LegalOperations) 933 return false; 934 935 EVT VT = Op.getValueType(); 936 if (VT.isVector() || !VT.isInteger()) 937 return false; 938 939 // If operation type is 'undesirable', e.g. i16 on x86, consider 940 // promoting it. 941 unsigned Opc = Op.getOpcode(); 942 if (TLI.isTypeDesirableForOp(Opc, VT)) 943 return false; 944 945 EVT PVT = VT; 946 // Consult target whether it is a good idea to promote this operation and 947 // what's the right type to promote it to. 948 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 949 assert(PVT != VT && "Don't know what type to promote to!"); 950 951 DebugLoc dl = Op.getDebugLoc(); 952 SDNode *N = Op.getNode(); 953 LoadSDNode *LD = cast<LoadSDNode>(N); 954 EVT MemVT = LD->getMemoryVT(); 955 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 956 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 957 : ISD::EXTLOAD) 958 : LD->getExtensionType(); 959 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 960 LD->getChain(), LD->getBasePtr(), 961 LD->getPointerInfo(), 962 MemVT, LD->isVolatile(), 963 LD->isNonTemporal(), LD->getAlignment()); 964 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 965 966 DEBUG(dbgs() << "\nPromoting "; 967 N->dump(&DAG); 968 dbgs() << "\nTo: "; 969 Result.getNode()->dump(&DAG); 970 dbgs() << '\n'); 971 WorkListRemover DeadNodes(*this); 972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 973 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 974 removeFromWorkList(N); 975 DAG.DeleteNode(N); 976 AddToWorkList(Result.getNode()); 977 return true; 978 } 979 return false; 980} 981 982 983//===----------------------------------------------------------------------===// 984// Main DAG Combiner implementation 985//===----------------------------------------------------------------------===// 986 987void DAGCombiner::Run(CombineLevel AtLevel) { 988 // set the instance variables, so that the various visit routines may use it. 989 Level = AtLevel; 990 LegalOperations = Level >= AfterLegalizeVectorOps; 991 LegalTypes = Level >= AfterLegalizeTypes; 992 993 // Add all the dag nodes to the worklist. 994 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 995 E = DAG.allnodes_end(); I != E; ++I) 996 AddToWorkList(I); 997 998 // Create a dummy node (which is not added to allnodes), that adds a reference 999 // to the root node, preventing it from being deleted, and tracking any 1000 // changes of the root. 1001 HandleSDNode Dummy(DAG.getRoot()); 1002 1003 // The root of the dag may dangle to deleted nodes until the dag combiner is 1004 // done. Set it to null to avoid confusion. 1005 DAG.setRoot(SDValue()); 1006 1007 // while the worklist isn't empty, find a node and 1008 // try and combine it. 1009 while (!WorkListContents.empty()) { 1010 SDNode *N; 1011 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1012 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1013 // worklist *should* contain, and check the node we want to visit is should 1014 // actually be visited. 1015 do { 1016 N = WorkListOrder.pop_back_val(); 1017 } while (!WorkListContents.erase(N)); 1018 1019 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1020 // N is deleted from the DAG, since they too may now be dead or may have a 1021 // reduced number of uses, allowing other xforms. 1022 if (N->use_empty() && N != &Dummy) { 1023 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1024 AddToWorkList(N->getOperand(i).getNode()); 1025 1026 DAG.DeleteNode(N); 1027 continue; 1028 } 1029 1030 SDValue RV = combine(N); 1031 1032 if (RV.getNode() == 0) 1033 continue; 1034 1035 ++NodesCombined; 1036 1037 // If we get back the same node we passed in, rather than a new node or 1038 // zero, we know that the node must have defined multiple values and 1039 // CombineTo was used. Since CombineTo takes care of the worklist 1040 // mechanics for us, we have no work to do in this case. 1041 if (RV.getNode() == N) 1042 continue; 1043 1044 assert(N->getOpcode() != ISD::DELETED_NODE && 1045 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1046 "Node was deleted but visit returned new node!"); 1047 1048 DEBUG(dbgs() << "\nReplacing.3 "; 1049 N->dump(&DAG); 1050 dbgs() << "\nWith: "; 1051 RV.getNode()->dump(&DAG); 1052 dbgs() << '\n'); 1053 1054 // Transfer debug value. 1055 DAG.TransferDbgValues(SDValue(N, 0), RV); 1056 WorkListRemover DeadNodes(*this); 1057 if (N->getNumValues() == RV.getNode()->getNumValues()) 1058 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1059 else { 1060 assert(N->getValueType(0) == RV.getValueType() && 1061 N->getNumValues() == 1 && "Type mismatch"); 1062 SDValue OpV = RV; 1063 DAG.ReplaceAllUsesWith(N, &OpV); 1064 } 1065 1066 // Push the new node and any users onto the worklist 1067 AddToWorkList(RV.getNode()); 1068 AddUsersToWorkList(RV.getNode()); 1069 1070 // Add any uses of the old node to the worklist in case this node is the 1071 // last one that uses them. They may become dead after this node is 1072 // deleted. 1073 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1074 AddToWorkList(N->getOperand(i).getNode()); 1075 1076 // Finally, if the node is now dead, remove it from the graph. The node 1077 // may not be dead if the replacement process recursively simplified to 1078 // something else needing this node. 1079 if (N->use_empty()) { 1080 // Nodes can be reintroduced into the worklist. Make sure we do not 1081 // process a node that has been replaced. 1082 removeFromWorkList(N); 1083 1084 // Finally, since the node is now dead, remove it from the graph. 1085 DAG.DeleteNode(N); 1086 } 1087 } 1088 1089 // If the root changed (e.g. it was a dead load, update the root). 1090 DAG.setRoot(Dummy.getValue()); 1091 DAG.RemoveDeadNodes(); 1092} 1093 1094SDValue DAGCombiner::visit(SDNode *N) { 1095 switch (N->getOpcode()) { 1096 default: break; 1097 case ISD::TokenFactor: return visitTokenFactor(N); 1098 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1099 case ISD::ADD: return visitADD(N); 1100 case ISD::SUB: return visitSUB(N); 1101 case ISD::ADDC: return visitADDC(N); 1102 case ISD::SUBC: return visitSUBC(N); 1103 case ISD::ADDE: return visitADDE(N); 1104 case ISD::SUBE: return visitSUBE(N); 1105 case ISD::MUL: return visitMUL(N); 1106 case ISD::SDIV: return visitSDIV(N); 1107 case ISD::UDIV: return visitUDIV(N); 1108 case ISD::SREM: return visitSREM(N); 1109 case ISD::UREM: return visitUREM(N); 1110 case ISD::MULHU: return visitMULHU(N); 1111 case ISD::MULHS: return visitMULHS(N); 1112 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1113 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1114 case ISD::SMULO: return visitSMULO(N); 1115 case ISD::UMULO: return visitUMULO(N); 1116 case ISD::SDIVREM: return visitSDIVREM(N); 1117 case ISD::UDIVREM: return visitUDIVREM(N); 1118 case ISD::AND: return visitAND(N); 1119 case ISD::OR: return visitOR(N); 1120 case ISD::XOR: return visitXOR(N); 1121 case ISD::SHL: return visitSHL(N); 1122 case ISD::SRA: return visitSRA(N); 1123 case ISD::SRL: return visitSRL(N); 1124 case ISD::CTLZ: return visitCTLZ(N); 1125 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1126 case ISD::CTTZ: return visitCTTZ(N); 1127 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1128 case ISD::CTPOP: return visitCTPOP(N); 1129 case ISD::SELECT: return visitSELECT(N); 1130 case ISD::SELECT_CC: return visitSELECT_CC(N); 1131 case ISD::SETCC: return visitSETCC(N); 1132 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1133 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1134 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1135 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1136 case ISD::TRUNCATE: return visitTRUNCATE(N); 1137 case ISD::BITCAST: return visitBITCAST(N); 1138 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1139 case ISD::FADD: return visitFADD(N); 1140 case ISD::FSUB: return visitFSUB(N); 1141 case ISD::FMUL: return visitFMUL(N); 1142 case ISD::FMA: return visitFMA(N); 1143 case ISD::FDIV: return visitFDIV(N); 1144 case ISD::FREM: return visitFREM(N); 1145 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1146 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1147 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1148 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1149 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1150 case ISD::FP_ROUND: return visitFP_ROUND(N); 1151 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1152 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1153 case ISD::FNEG: return visitFNEG(N); 1154 case ISD::FABS: return visitFABS(N); 1155 case ISD::FFLOOR: return visitFFLOOR(N); 1156 case ISD::FCEIL: return visitFCEIL(N); 1157 case ISD::FTRUNC: return visitFTRUNC(N); 1158 case ISD::BRCOND: return visitBRCOND(N); 1159 case ISD::BR_CC: return visitBR_CC(N); 1160 case ISD::LOAD: return visitLOAD(N); 1161 case ISD::STORE: return visitSTORE(N); 1162 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1163 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1164 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1165 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1166 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1167 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1168 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1169 } 1170 return SDValue(); 1171} 1172 1173SDValue DAGCombiner::combine(SDNode *N) { 1174 SDValue RV = visit(N); 1175 1176 // If nothing happened, try a target-specific DAG combine. 1177 if (RV.getNode() == 0) { 1178 assert(N->getOpcode() != ISD::DELETED_NODE && 1179 "Node was deleted but visit returned NULL!"); 1180 1181 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1182 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1183 1184 // Expose the DAG combiner to the target combiner impls. 1185 TargetLowering::DAGCombinerInfo 1186 DagCombineInfo(DAG, Level, false, this); 1187 1188 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1189 } 1190 } 1191 1192 // If nothing happened still, try promoting the operation. 1193 if (RV.getNode() == 0) { 1194 switch (N->getOpcode()) { 1195 default: break; 1196 case ISD::ADD: 1197 case ISD::SUB: 1198 case ISD::MUL: 1199 case ISD::AND: 1200 case ISD::OR: 1201 case ISD::XOR: 1202 RV = PromoteIntBinOp(SDValue(N, 0)); 1203 break; 1204 case ISD::SHL: 1205 case ISD::SRA: 1206 case ISD::SRL: 1207 RV = PromoteIntShiftOp(SDValue(N, 0)); 1208 break; 1209 case ISD::SIGN_EXTEND: 1210 case ISD::ZERO_EXTEND: 1211 case ISD::ANY_EXTEND: 1212 RV = PromoteExtend(SDValue(N, 0)); 1213 break; 1214 case ISD::LOAD: 1215 if (PromoteLoad(SDValue(N, 0))) 1216 RV = SDValue(N, 0); 1217 break; 1218 } 1219 } 1220 1221 // If N is a commutative binary node, try commuting it to enable more 1222 // sdisel CSE. 1223 if (RV.getNode() == 0 && 1224 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1225 N->getNumValues() == 1) { 1226 SDValue N0 = N->getOperand(0); 1227 SDValue N1 = N->getOperand(1); 1228 1229 // Constant operands are canonicalized to RHS. 1230 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1231 SDValue Ops[] = { N1, N0 }; 1232 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1233 Ops, 2); 1234 if (CSENode) 1235 return SDValue(CSENode, 0); 1236 } 1237 } 1238 1239 return RV; 1240} 1241 1242/// getInputChainForNode - Given a node, return its input chain if it has one, 1243/// otherwise return a null sd operand. 1244static SDValue getInputChainForNode(SDNode *N) { 1245 if (unsigned NumOps = N->getNumOperands()) { 1246 if (N->getOperand(0).getValueType() == MVT::Other) 1247 return N->getOperand(0); 1248 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1249 return N->getOperand(NumOps-1); 1250 for (unsigned i = 1; i < NumOps-1; ++i) 1251 if (N->getOperand(i).getValueType() == MVT::Other) 1252 return N->getOperand(i); 1253 } 1254 return SDValue(); 1255} 1256 1257SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1258 // If N has two operands, where one has an input chain equal to the other, 1259 // the 'other' chain is redundant. 1260 if (N->getNumOperands() == 2) { 1261 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1262 return N->getOperand(0); 1263 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1264 return N->getOperand(1); 1265 } 1266 1267 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1268 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1269 SmallPtrSet<SDNode*, 16> SeenOps; 1270 bool Changed = false; // If we should replace this token factor. 1271 1272 // Start out with this token factor. 1273 TFs.push_back(N); 1274 1275 // Iterate through token factors. The TFs grows when new token factors are 1276 // encountered. 1277 for (unsigned i = 0; i < TFs.size(); ++i) { 1278 SDNode *TF = TFs[i]; 1279 1280 // Check each of the operands. 1281 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1282 SDValue Op = TF->getOperand(i); 1283 1284 switch (Op.getOpcode()) { 1285 case ISD::EntryToken: 1286 // Entry tokens don't need to be added to the list. They are 1287 // rededundant. 1288 Changed = true; 1289 break; 1290 1291 case ISD::TokenFactor: 1292 if (Op.hasOneUse() && 1293 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1294 // Queue up for processing. 1295 TFs.push_back(Op.getNode()); 1296 // Clean up in case the token factor is removed. 1297 AddToWorkList(Op.getNode()); 1298 Changed = true; 1299 break; 1300 } 1301 // Fall thru 1302 1303 default: 1304 // Only add if it isn't already in the list. 1305 if (SeenOps.insert(Op.getNode())) 1306 Ops.push_back(Op); 1307 else 1308 Changed = true; 1309 break; 1310 } 1311 } 1312 } 1313 1314 SDValue Result; 1315 1316 // If we've change things around then replace token factor. 1317 if (Changed) { 1318 if (Ops.empty()) { 1319 // The entry token is the only possible outcome. 1320 Result = DAG.getEntryNode(); 1321 } else { 1322 // New and improved token factor. 1323 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1324 MVT::Other, &Ops[0], Ops.size()); 1325 } 1326 1327 // Don't add users to work list. 1328 return CombineTo(N, Result, false); 1329 } 1330 1331 return Result; 1332} 1333 1334/// MERGE_VALUES can always be eliminated. 1335SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1336 WorkListRemover DeadNodes(*this); 1337 // Replacing results may cause a different MERGE_VALUES to suddenly 1338 // be CSE'd with N, and carry its uses with it. Iterate until no 1339 // uses remain, to ensure that the node can be safely deleted. 1340 // First add the users of this node to the work list so that they 1341 // can be tried again once they have new operands. 1342 AddUsersToWorkList(N); 1343 do { 1344 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1345 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1346 } while (!N->use_empty()); 1347 removeFromWorkList(N); 1348 DAG.DeleteNode(N); 1349 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1350} 1351 1352static 1353SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1354 SelectionDAG &DAG) { 1355 EVT VT = N0.getValueType(); 1356 SDValue N00 = N0.getOperand(0); 1357 SDValue N01 = N0.getOperand(1); 1358 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1359 1360 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1361 isa<ConstantSDNode>(N00.getOperand(1))) { 1362 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1363 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1364 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1365 N00.getOperand(0), N01), 1366 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1367 N00.getOperand(1), N01)); 1368 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1369 } 1370 1371 return SDValue(); 1372} 1373 1374SDValue DAGCombiner::visitADD(SDNode *N) { 1375 SDValue N0 = N->getOperand(0); 1376 SDValue N1 = N->getOperand(1); 1377 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1378 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1379 EVT VT = N0.getValueType(); 1380 1381 // fold vector ops 1382 if (VT.isVector()) { 1383 SDValue FoldedVOp = SimplifyVBinOp(N); 1384 if (FoldedVOp.getNode()) return FoldedVOp; 1385 1386 // fold (add x, 0) -> x, vector edition 1387 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1388 return N0; 1389 if (ISD::isBuildVectorAllZeros(N0.getNode())) 1390 return N1; 1391 } 1392 1393 // fold (add x, undef) -> undef 1394 if (N0.getOpcode() == ISD::UNDEF) 1395 return N0; 1396 if (N1.getOpcode() == ISD::UNDEF) 1397 return N1; 1398 // fold (add c1, c2) -> c1+c2 1399 if (N0C && N1C) 1400 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1401 // canonicalize constant to RHS 1402 if (N0C && !N1C) 1403 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1404 // fold (add x, 0) -> x 1405 if (N1C && N1C->isNullValue()) 1406 return N0; 1407 // fold (add Sym, c) -> Sym+c 1408 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1409 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1410 GA->getOpcode() == ISD::GlobalAddress) 1411 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1412 GA->getOffset() + 1413 (uint64_t)N1C->getSExtValue()); 1414 // fold ((c1-A)+c2) -> (c1+c2)-A 1415 if (N1C && N0.getOpcode() == ISD::SUB) 1416 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1417 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1418 DAG.getConstant(N1C->getAPIntValue()+ 1419 N0C->getAPIntValue(), VT), 1420 N0.getOperand(1)); 1421 // reassociate add 1422 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1423 if (RADD.getNode() != 0) 1424 return RADD; 1425 // fold ((0-A) + B) -> B-A 1426 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1427 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1429 // fold (A + (0-B)) -> A-B 1430 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1431 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1432 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1433 // fold (A+(B-A)) -> B 1434 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1435 return N1.getOperand(0); 1436 // fold ((B-A)+A) -> B 1437 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1438 return N0.getOperand(0); 1439 // fold (A+(B-(A+C))) to (B-C) 1440 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1441 N0 == N1.getOperand(1).getOperand(0)) 1442 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1443 N1.getOperand(1).getOperand(1)); 1444 // fold (A+(B-(C+A))) to (B-C) 1445 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1446 N0 == N1.getOperand(1).getOperand(1)) 1447 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1448 N1.getOperand(1).getOperand(0)); 1449 // fold (A+((B-A)+or-C)) to (B+or-C) 1450 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1451 N1.getOperand(0).getOpcode() == ISD::SUB && 1452 N0 == N1.getOperand(0).getOperand(1)) 1453 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1454 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1455 1456 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1457 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1458 SDValue N00 = N0.getOperand(0); 1459 SDValue N01 = N0.getOperand(1); 1460 SDValue N10 = N1.getOperand(0); 1461 SDValue N11 = N1.getOperand(1); 1462 1463 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1464 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1465 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1466 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1467 } 1468 1469 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1470 return SDValue(N, 0); 1471 1472 // fold (a+b) -> (a|b) iff a and b share no bits. 1473 if (VT.isInteger() && !VT.isVector()) { 1474 APInt LHSZero, LHSOne; 1475 APInt RHSZero, RHSOne; 1476 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1477 1478 if (LHSZero.getBoolValue()) { 1479 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1480 1481 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1482 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1483 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1484 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1485 } 1486 } 1487 1488 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1489 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1490 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1491 if (Result.getNode()) return Result; 1492 } 1493 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1494 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1495 if (Result.getNode()) return Result; 1496 } 1497 1498 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1499 if (N1.getOpcode() == ISD::SHL && 1500 N1.getOperand(0).getOpcode() == ISD::SUB) 1501 if (ConstantSDNode *C = 1502 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1503 if (C->getAPIntValue() == 0) 1504 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1505 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1506 N1.getOperand(0).getOperand(1), 1507 N1.getOperand(1))); 1508 if (N0.getOpcode() == ISD::SHL && 1509 N0.getOperand(0).getOpcode() == ISD::SUB) 1510 if (ConstantSDNode *C = 1511 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1512 if (C->getAPIntValue() == 0) 1513 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1514 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1515 N0.getOperand(0).getOperand(1), 1516 N0.getOperand(1))); 1517 1518 if (N1.getOpcode() == ISD::AND) { 1519 SDValue AndOp0 = N1.getOperand(0); 1520 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1521 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1522 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1523 1524 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1525 // and similar xforms where the inner op is either ~0 or 0. 1526 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1527 DebugLoc DL = N->getDebugLoc(); 1528 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1529 } 1530 } 1531 1532 // add (sext i1), X -> sub X, (zext i1) 1533 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1534 N0.getOperand(0).getValueType() == MVT::i1 && 1535 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1536 DebugLoc DL = N->getDebugLoc(); 1537 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1538 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1539 } 1540 1541 return SDValue(); 1542} 1543 1544SDValue DAGCombiner::visitADDC(SDNode *N) { 1545 SDValue N0 = N->getOperand(0); 1546 SDValue N1 = N->getOperand(1); 1547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1549 EVT VT = N0.getValueType(); 1550 1551 // If the flag result is dead, turn this into an ADD. 1552 if (!N->hasAnyUseOfValue(1)) 1553 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1554 DAG.getNode(ISD::CARRY_FALSE, 1555 N->getDebugLoc(), MVT::Glue)); 1556 1557 // canonicalize constant to RHS. 1558 if (N0C && !N1C) 1559 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1560 1561 // fold (addc x, 0) -> x + no carry out 1562 if (N1C && N1C->isNullValue()) 1563 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1564 N->getDebugLoc(), MVT::Glue)); 1565 1566 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1567 APInt LHSZero, LHSOne; 1568 APInt RHSZero, RHSOne; 1569 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1570 1571 if (LHSZero.getBoolValue()) { 1572 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1573 1574 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1575 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1576 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1577 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1578 DAG.getNode(ISD::CARRY_FALSE, 1579 N->getDebugLoc(), MVT::Glue)); 1580 } 1581 1582 return SDValue(); 1583} 1584 1585SDValue DAGCombiner::visitADDE(SDNode *N) { 1586 SDValue N0 = N->getOperand(0); 1587 SDValue N1 = N->getOperand(1); 1588 SDValue CarryIn = N->getOperand(2); 1589 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1590 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1591 1592 // canonicalize constant to RHS 1593 if (N0C && !N1C) 1594 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1595 N1, N0, CarryIn); 1596 1597 // fold (adde x, y, false) -> (addc x, y) 1598 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1599 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1600 1601 return SDValue(); 1602} 1603 1604// Since it may not be valid to emit a fold to zero for vector initializers 1605// check if we can before folding. 1606static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1607 SelectionDAG &DAG, bool LegalOperations) { 1608 if (!VT.isVector()) { 1609 return DAG.getConstant(0, VT); 1610 } 1611 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1612 // Produce a vector of zeros. 1613 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1614 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1615 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1616 &Ops[0], Ops.size()); 1617 } 1618 return SDValue(); 1619} 1620 1621SDValue DAGCombiner::visitSUB(SDNode *N) { 1622 SDValue N0 = N->getOperand(0); 1623 SDValue N1 = N->getOperand(1); 1624 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1626 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1627 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1628 EVT VT = N0.getValueType(); 1629 1630 // fold vector ops 1631 if (VT.isVector()) { 1632 SDValue FoldedVOp = SimplifyVBinOp(N); 1633 if (FoldedVOp.getNode()) return FoldedVOp; 1634 1635 // fold (sub x, 0) -> x, vector edition 1636 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1637 return N0; 1638 } 1639 1640 // fold (sub x, x) -> 0 1641 // FIXME: Refactor this and xor and other similar operations together. 1642 if (N0 == N1) 1643 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1644 // fold (sub c1, c2) -> c1-c2 1645 if (N0C && N1C) 1646 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1647 // fold (sub x, c) -> (add x, -c) 1648 if (N1C) 1649 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1650 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1651 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1652 if (N0C && N0C->isAllOnesValue()) 1653 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1654 // fold A-(A-B) -> B 1655 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1656 return N1.getOperand(1); 1657 // fold (A+B)-A -> B 1658 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1659 return N0.getOperand(1); 1660 // fold (A+B)-B -> A 1661 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1662 return N0.getOperand(0); 1663 // fold C2-(A+C1) -> (C2-C1)-A 1664 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1665 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), 1666 VT); 1667 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1668 N1.getOperand(0)); 1669 } 1670 // fold ((A+(B+or-C))-B) -> A+or-C 1671 if (N0.getOpcode() == ISD::ADD && 1672 (N0.getOperand(1).getOpcode() == ISD::SUB || 1673 N0.getOperand(1).getOpcode() == ISD::ADD) && 1674 N0.getOperand(1).getOperand(0) == N1) 1675 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1676 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1677 // fold ((A+(C+B))-B) -> A+C 1678 if (N0.getOpcode() == ISD::ADD && 1679 N0.getOperand(1).getOpcode() == ISD::ADD && 1680 N0.getOperand(1).getOperand(1) == N1) 1681 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1682 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1683 // fold ((A-(B-C))-C) -> A-B 1684 if (N0.getOpcode() == ISD::SUB && 1685 N0.getOperand(1).getOpcode() == ISD::SUB && 1686 N0.getOperand(1).getOperand(1) == N1) 1687 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1688 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1689 1690 // If either operand of a sub is undef, the result is undef 1691 if (N0.getOpcode() == ISD::UNDEF) 1692 return N0; 1693 if (N1.getOpcode() == ISD::UNDEF) 1694 return N1; 1695 1696 // If the relocation model supports it, consider symbol offsets. 1697 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1698 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1699 // fold (sub Sym, c) -> Sym-c 1700 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1701 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1702 GA->getOffset() - 1703 (uint64_t)N1C->getSExtValue()); 1704 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1705 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1706 if (GA->getGlobal() == GB->getGlobal()) 1707 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1708 VT); 1709 } 1710 1711 return SDValue(); 1712} 1713 1714SDValue DAGCombiner::visitSUBC(SDNode *N) { 1715 SDValue N0 = N->getOperand(0); 1716 SDValue N1 = N->getOperand(1); 1717 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1718 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1719 EVT VT = N0.getValueType(); 1720 1721 // If the flag result is dead, turn this into an SUB. 1722 if (!N->hasAnyUseOfValue(1)) 1723 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1724 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1725 MVT::Glue)); 1726 1727 // fold (subc x, x) -> 0 + no borrow 1728 if (N0 == N1) 1729 return CombineTo(N, DAG.getConstant(0, VT), 1730 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1731 MVT::Glue)); 1732 1733 // fold (subc x, 0) -> x + no borrow 1734 if (N1C && N1C->isNullValue()) 1735 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1736 MVT::Glue)); 1737 1738 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1739 if (N0C && N0C->isAllOnesValue()) 1740 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1741 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1742 MVT::Glue)); 1743 1744 return SDValue(); 1745} 1746 1747SDValue DAGCombiner::visitSUBE(SDNode *N) { 1748 SDValue N0 = N->getOperand(0); 1749 SDValue N1 = N->getOperand(1); 1750 SDValue CarryIn = N->getOperand(2); 1751 1752 // fold (sube x, y, false) -> (subc x, y) 1753 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1754 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1755 1756 return SDValue(); 1757} 1758 1759SDValue DAGCombiner::visitMUL(SDNode *N) { 1760 SDValue N0 = N->getOperand(0); 1761 SDValue N1 = N->getOperand(1); 1762 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1763 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1764 EVT VT = N0.getValueType(); 1765 1766 // fold vector ops 1767 if (VT.isVector()) { 1768 SDValue FoldedVOp = SimplifyVBinOp(N); 1769 if (FoldedVOp.getNode()) return FoldedVOp; 1770 } 1771 1772 // fold (mul x, undef) -> 0 1773 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1774 return DAG.getConstant(0, VT); 1775 // fold (mul c1, c2) -> c1*c2 1776 if (N0C && N1C) 1777 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1778 // canonicalize constant to RHS 1779 if (N0C && !N1C) 1780 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1781 // fold (mul x, 0) -> 0 1782 if (N1C && N1C->isNullValue()) 1783 return N1; 1784 // fold (mul x, -1) -> 0-x 1785 if (N1C && N1C->isAllOnesValue()) 1786 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1787 DAG.getConstant(0, VT), N0); 1788 // fold (mul x, (1 << c)) -> x << c 1789 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1790 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1791 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1792 getShiftAmountTy(N0.getValueType()))); 1793 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1794 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1795 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1796 // FIXME: If the input is something that is easily negated (e.g. a 1797 // single-use add), we should put the negate there. 1798 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1799 DAG.getConstant(0, VT), 1800 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1801 DAG.getConstant(Log2Val, 1802 getShiftAmountTy(N0.getValueType())))); 1803 } 1804 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1805 if (N1C && N0.getOpcode() == ISD::SHL && 1806 isa<ConstantSDNode>(N0.getOperand(1))) { 1807 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1808 N1, N0.getOperand(1)); 1809 AddToWorkList(C3.getNode()); 1810 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1811 N0.getOperand(0), C3); 1812 } 1813 1814 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1815 // use. 1816 { 1817 SDValue Sh(0,0), Y(0,0); 1818 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1819 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1820 N0.getNode()->hasOneUse()) { 1821 Sh = N0; Y = N1; 1822 } else if (N1.getOpcode() == ISD::SHL && 1823 isa<ConstantSDNode>(N1.getOperand(1)) && 1824 N1.getNode()->hasOneUse()) { 1825 Sh = N1; Y = N0; 1826 } 1827 1828 if (Sh.getNode()) { 1829 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1830 Sh.getOperand(0), Y); 1831 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1832 Mul, Sh.getOperand(1)); 1833 } 1834 } 1835 1836 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1837 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1838 isa<ConstantSDNode>(N0.getOperand(1))) 1839 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1840 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1841 N0.getOperand(0), N1), 1842 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1843 N0.getOperand(1), N1)); 1844 1845 // reassociate mul 1846 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1847 if (RMUL.getNode() != 0) 1848 return RMUL; 1849 1850 return SDValue(); 1851} 1852 1853SDValue DAGCombiner::visitSDIV(SDNode *N) { 1854 SDValue N0 = N->getOperand(0); 1855 SDValue N1 = N->getOperand(1); 1856 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1858 EVT VT = N->getValueType(0); 1859 1860 // fold vector ops 1861 if (VT.isVector()) { 1862 SDValue FoldedVOp = SimplifyVBinOp(N); 1863 if (FoldedVOp.getNode()) return FoldedVOp; 1864 } 1865 1866 // fold (sdiv c1, c2) -> c1/c2 1867 if (N0C && N1C && !N1C->isNullValue()) 1868 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1869 // fold (sdiv X, 1) -> X 1870 if (N1C && N1C->getAPIntValue() == 1LL) 1871 return N0; 1872 // fold (sdiv X, -1) -> 0-X 1873 if (N1C && N1C->isAllOnesValue()) 1874 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1875 DAG.getConstant(0, VT), N0); 1876 // If we know the sign bits of both operands are zero, strength reduce to a 1877 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1878 if (!VT.isVector()) { 1879 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1880 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1881 N0, N1); 1882 } 1883 // fold (sdiv X, pow2) -> simple ops after legalize 1884 if (N1C && !N1C->isNullValue() && 1885 (N1C->getAPIntValue().isPowerOf2() || 1886 (-N1C->getAPIntValue()).isPowerOf2())) { 1887 // If dividing by powers of two is cheap, then don't perform the following 1888 // fold. 1889 if (TLI.isPow2DivCheap()) 1890 return SDValue(); 1891 1892 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1893 1894 // Splat the sign bit into the register 1895 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1896 DAG.getConstant(VT.getSizeInBits()-1, 1897 getShiftAmountTy(N0.getValueType()))); 1898 AddToWorkList(SGN.getNode()); 1899 1900 // Add (N0 < 0) ? abs2 - 1 : 0; 1901 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1902 DAG.getConstant(VT.getSizeInBits() - lg2, 1903 getShiftAmountTy(SGN.getValueType()))); 1904 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1905 AddToWorkList(SRL.getNode()); 1906 AddToWorkList(ADD.getNode()); // Divide by pow2 1907 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1908 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1909 1910 // If we're dividing by a positive value, we're done. Otherwise, we must 1911 // negate the result. 1912 if (N1C->getAPIntValue().isNonNegative()) 1913 return SRA; 1914 1915 AddToWorkList(SRA.getNode()); 1916 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1917 DAG.getConstant(0, VT), SRA); 1918 } 1919 1920 // if integer divide is expensive and we satisfy the requirements, emit an 1921 // alternate sequence. 1922 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1923 SDValue Op = BuildSDIV(N); 1924 if (Op.getNode()) return Op; 1925 } 1926 1927 // undef / X -> 0 1928 if (N0.getOpcode() == ISD::UNDEF) 1929 return DAG.getConstant(0, VT); 1930 // X / undef -> undef 1931 if (N1.getOpcode() == ISD::UNDEF) 1932 return N1; 1933 1934 return SDValue(); 1935} 1936 1937SDValue DAGCombiner::visitUDIV(SDNode *N) { 1938 SDValue N0 = N->getOperand(0); 1939 SDValue N1 = N->getOperand(1); 1940 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1941 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1942 EVT VT = N->getValueType(0); 1943 1944 // fold vector ops 1945 if (VT.isVector()) { 1946 SDValue FoldedVOp = SimplifyVBinOp(N); 1947 if (FoldedVOp.getNode()) return FoldedVOp; 1948 } 1949 1950 // fold (udiv c1, c2) -> c1/c2 1951 if (N0C && N1C && !N1C->isNullValue()) 1952 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1953 // fold (udiv x, (1 << c)) -> x >>u c 1954 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1955 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1956 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1957 getShiftAmountTy(N0.getValueType()))); 1958 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1959 if (N1.getOpcode() == ISD::SHL) { 1960 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1961 if (SHC->getAPIntValue().isPowerOf2()) { 1962 EVT ADDVT = N1.getOperand(1).getValueType(); 1963 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1964 N1.getOperand(1), 1965 DAG.getConstant(SHC->getAPIntValue() 1966 .logBase2(), 1967 ADDVT)); 1968 AddToWorkList(Add.getNode()); 1969 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1970 } 1971 } 1972 } 1973 // fold (udiv x, c) -> alternate 1974 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1975 SDValue Op = BuildUDIV(N); 1976 if (Op.getNode()) return Op; 1977 } 1978 1979 // undef / X -> 0 1980 if (N0.getOpcode() == ISD::UNDEF) 1981 return DAG.getConstant(0, VT); 1982 // X / undef -> undef 1983 if (N1.getOpcode() == ISD::UNDEF) 1984 return N1; 1985 1986 return SDValue(); 1987} 1988 1989SDValue DAGCombiner::visitSREM(SDNode *N) { 1990 SDValue N0 = N->getOperand(0); 1991 SDValue N1 = N->getOperand(1); 1992 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1994 EVT VT = N->getValueType(0); 1995 1996 // fold (srem c1, c2) -> c1%c2 1997 if (N0C && N1C && !N1C->isNullValue()) 1998 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1999 // If we know the sign bits of both operands are zero, strength reduce to a 2000 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 2001 if (!VT.isVector()) { 2002 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 2003 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 2004 } 2005 2006 // If X/C can be simplified by the division-by-constant logic, lower 2007 // X%C to the equivalent of X-X/C*C. 2008 if (N1C && !N1C->isNullValue()) { 2009 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 2010 AddToWorkList(Div.getNode()); 2011 SDValue OptimizedDiv = combine(Div.getNode()); 2012 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2013 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2014 OptimizedDiv, N1); 2015 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2016 AddToWorkList(Mul.getNode()); 2017 return Sub; 2018 } 2019 } 2020 2021 // undef % X -> 0 2022 if (N0.getOpcode() == ISD::UNDEF) 2023 return DAG.getConstant(0, VT); 2024 // X % undef -> undef 2025 if (N1.getOpcode() == ISD::UNDEF) 2026 return N1; 2027 2028 return SDValue(); 2029} 2030 2031SDValue DAGCombiner::visitUREM(SDNode *N) { 2032 SDValue N0 = N->getOperand(0); 2033 SDValue N1 = N->getOperand(1); 2034 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2035 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2036 EVT VT = N->getValueType(0); 2037 2038 // fold (urem c1, c2) -> c1%c2 2039 if (N0C && N1C && !N1C->isNullValue()) 2040 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2041 // fold (urem x, pow2) -> (and x, pow2-1) 2042 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2043 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2044 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2045 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2046 if (N1.getOpcode() == ISD::SHL) { 2047 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2048 if (SHC->getAPIntValue().isPowerOf2()) { 2049 SDValue Add = 2050 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2051 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2052 VT)); 2053 AddToWorkList(Add.getNode()); 2054 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2055 } 2056 } 2057 } 2058 2059 // If X/C can be simplified by the division-by-constant logic, lower 2060 // X%C to the equivalent of X-X/C*C. 2061 if (N1C && !N1C->isNullValue()) { 2062 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2063 AddToWorkList(Div.getNode()); 2064 SDValue OptimizedDiv = combine(Div.getNode()); 2065 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2066 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2067 OptimizedDiv, N1); 2068 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2069 AddToWorkList(Mul.getNode()); 2070 return Sub; 2071 } 2072 } 2073 2074 // undef % X -> 0 2075 if (N0.getOpcode() == ISD::UNDEF) 2076 return DAG.getConstant(0, VT); 2077 // X % undef -> undef 2078 if (N1.getOpcode() == ISD::UNDEF) 2079 return N1; 2080 2081 return SDValue(); 2082} 2083 2084SDValue DAGCombiner::visitMULHS(SDNode *N) { 2085 SDValue N0 = N->getOperand(0); 2086 SDValue N1 = N->getOperand(1); 2087 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2088 EVT VT = N->getValueType(0); 2089 DebugLoc DL = N->getDebugLoc(); 2090 2091 // fold (mulhs x, 0) -> 0 2092 if (N1C && N1C->isNullValue()) 2093 return N1; 2094 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2095 if (N1C && N1C->getAPIntValue() == 1) 2096 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2097 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2098 getShiftAmountTy(N0.getValueType()))); 2099 // fold (mulhs x, undef) -> 0 2100 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2101 return DAG.getConstant(0, VT); 2102 2103 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2104 // plus a shift. 2105 if (VT.isSimple() && !VT.isVector()) { 2106 MVT Simple = VT.getSimpleVT(); 2107 unsigned SimpleSize = Simple.getSizeInBits(); 2108 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2109 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2110 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2111 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2112 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2113 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2114 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2115 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2116 } 2117 } 2118 2119 return SDValue(); 2120} 2121 2122SDValue DAGCombiner::visitMULHU(SDNode *N) { 2123 SDValue N0 = N->getOperand(0); 2124 SDValue N1 = N->getOperand(1); 2125 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2126 EVT VT = N->getValueType(0); 2127 DebugLoc DL = N->getDebugLoc(); 2128 2129 // fold (mulhu x, 0) -> 0 2130 if (N1C && N1C->isNullValue()) 2131 return N1; 2132 // fold (mulhu x, 1) -> 0 2133 if (N1C && N1C->getAPIntValue() == 1) 2134 return DAG.getConstant(0, N0.getValueType()); 2135 // fold (mulhu x, undef) -> 0 2136 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2137 return DAG.getConstant(0, VT); 2138 2139 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2140 // plus a shift. 2141 if (VT.isSimple() && !VT.isVector()) { 2142 MVT Simple = VT.getSimpleVT(); 2143 unsigned SimpleSize = Simple.getSizeInBits(); 2144 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2145 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2146 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2147 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2148 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2149 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2150 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2151 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2152 } 2153 } 2154 2155 return SDValue(); 2156} 2157 2158/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2159/// compute two values. LoOp and HiOp give the opcodes for the two computations 2160/// that are being performed. Return true if a simplification was made. 2161/// 2162SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2163 unsigned HiOp) { 2164 // If the high half is not needed, just compute the low half. 2165 bool HiExists = N->hasAnyUseOfValue(1); 2166 if (!HiExists && 2167 (!LegalOperations || 2168 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2169 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2170 N->op_begin(), N->getNumOperands()); 2171 return CombineTo(N, Res, Res); 2172 } 2173 2174 // If the low half is not needed, just compute the high half. 2175 bool LoExists = N->hasAnyUseOfValue(0); 2176 if (!LoExists && 2177 (!LegalOperations || 2178 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2179 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2180 N->op_begin(), N->getNumOperands()); 2181 return CombineTo(N, Res, Res); 2182 } 2183 2184 // If both halves are used, return as it is. 2185 if (LoExists && HiExists) 2186 return SDValue(); 2187 2188 // If the two computed results can be simplified separately, separate them. 2189 if (LoExists) { 2190 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2191 N->op_begin(), N->getNumOperands()); 2192 AddToWorkList(Lo.getNode()); 2193 SDValue LoOpt = combine(Lo.getNode()); 2194 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2195 (!LegalOperations || 2196 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2197 return CombineTo(N, LoOpt, LoOpt); 2198 } 2199 2200 if (HiExists) { 2201 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2202 N->op_begin(), N->getNumOperands()); 2203 AddToWorkList(Hi.getNode()); 2204 SDValue HiOpt = combine(Hi.getNode()); 2205 if (HiOpt.getNode() && HiOpt != Hi && 2206 (!LegalOperations || 2207 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2208 return CombineTo(N, HiOpt, HiOpt); 2209 } 2210 2211 return SDValue(); 2212} 2213 2214SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2215 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2216 if (Res.getNode()) return Res; 2217 2218 EVT VT = N->getValueType(0); 2219 DebugLoc DL = N->getDebugLoc(); 2220 2221 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2222 // plus a shift. 2223 if (VT.isSimple() && !VT.isVector()) { 2224 MVT Simple = VT.getSimpleVT(); 2225 unsigned SimpleSize = Simple.getSizeInBits(); 2226 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2227 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2228 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2229 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2230 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2231 // Compute the high part as N1. 2232 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2233 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2234 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2235 // Compute the low part as N0. 2236 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2237 return CombineTo(N, Lo, Hi); 2238 } 2239 } 2240 2241 return SDValue(); 2242} 2243 2244SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2245 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2246 if (Res.getNode()) return Res; 2247 2248 EVT VT = N->getValueType(0); 2249 DebugLoc DL = N->getDebugLoc(); 2250 2251 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2252 // plus a shift. 2253 if (VT.isSimple() && !VT.isVector()) { 2254 MVT Simple = VT.getSimpleVT(); 2255 unsigned SimpleSize = Simple.getSizeInBits(); 2256 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2257 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2258 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2259 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2260 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2261 // Compute the high part as N1. 2262 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2263 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2264 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2265 // Compute the low part as N0. 2266 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2267 return CombineTo(N, Lo, Hi); 2268 } 2269 } 2270 2271 return SDValue(); 2272} 2273 2274SDValue DAGCombiner::visitSMULO(SDNode *N) { 2275 // (smulo x, 2) -> (saddo x, x) 2276 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2277 if (C2->getAPIntValue() == 2) 2278 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2279 N->getOperand(0), N->getOperand(0)); 2280 2281 return SDValue(); 2282} 2283 2284SDValue DAGCombiner::visitUMULO(SDNode *N) { 2285 // (umulo x, 2) -> (uaddo x, x) 2286 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2287 if (C2->getAPIntValue() == 2) 2288 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2289 N->getOperand(0), N->getOperand(0)); 2290 2291 return SDValue(); 2292} 2293 2294SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2295 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2296 if (Res.getNode()) return Res; 2297 2298 return SDValue(); 2299} 2300 2301SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2302 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2303 if (Res.getNode()) return Res; 2304 2305 return SDValue(); 2306} 2307 2308/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2309/// two operands of the same opcode, try to simplify it. 2310SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2311 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2312 EVT VT = N0.getValueType(); 2313 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2314 2315 // Bail early if none of these transforms apply. 2316 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2317 2318 // For each of OP in AND/OR/XOR: 2319 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2320 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2321 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2322 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2323 // 2324 // do not sink logical op inside of a vector extend, since it may combine 2325 // into a vsetcc. 2326 EVT Op0VT = N0.getOperand(0).getValueType(); 2327 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2328 N0.getOpcode() == ISD::SIGN_EXTEND || 2329 // Avoid infinite looping with PromoteIntBinOp. 2330 (N0.getOpcode() == ISD::ANY_EXTEND && 2331 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2332 (N0.getOpcode() == ISD::TRUNCATE && 2333 (!TLI.isZExtFree(VT, Op0VT) || 2334 !TLI.isTruncateFree(Op0VT, VT)) && 2335 TLI.isTypeLegal(Op0VT))) && 2336 !VT.isVector() && 2337 Op0VT == N1.getOperand(0).getValueType() && 2338 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2339 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2340 N0.getOperand(0).getValueType(), 2341 N0.getOperand(0), N1.getOperand(0)); 2342 AddToWorkList(ORNode.getNode()); 2343 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2344 } 2345 2346 // For each of OP in SHL/SRL/SRA/AND... 2347 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2348 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2349 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2350 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2351 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2352 N0.getOperand(1) == N1.getOperand(1)) { 2353 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2354 N0.getOperand(0).getValueType(), 2355 N0.getOperand(0), N1.getOperand(0)); 2356 AddToWorkList(ORNode.getNode()); 2357 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2358 ORNode, N0.getOperand(1)); 2359 } 2360 2361 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2362 // Only perform this optimization after type legalization and before 2363 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2364 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2365 // we don't want to undo this promotion. 2366 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2367 // on scalars. 2368 if ((N0.getOpcode() == ISD::BITCAST || 2369 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && 2370 Level == AfterLegalizeTypes) { 2371 SDValue In0 = N0.getOperand(0); 2372 SDValue In1 = N1.getOperand(0); 2373 EVT In0Ty = In0.getValueType(); 2374 EVT In1Ty = In1.getValueType(); 2375 DebugLoc DL = N->getDebugLoc(); 2376 // If both incoming values are integers, and the original types are the 2377 // same. 2378 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2379 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1); 2380 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op); 2381 AddToWorkList(Op.getNode()); 2382 return BC; 2383 } 2384 } 2385 2386 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2387 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2388 // If both shuffles use the same mask, and both shuffle within a single 2389 // vector, then it is worthwhile to move the swizzle after the operation. 2390 // The type-legalizer generates this pattern when loading illegal 2391 // vector types from memory. In many cases this allows additional shuffle 2392 // optimizations. 2393 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2394 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2395 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2396 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2397 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2398 2399 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2400 "Inputs to shuffles are not the same type"); 2401 2402 unsigned NumElts = VT.getVectorNumElements(); 2403 2404 // Check that both shuffles use the same mask. The masks are known to be of 2405 // the same length because the result vector type is the same. 2406 bool SameMask = true; 2407 for (unsigned i = 0; i != NumElts; ++i) { 2408 int Idx0 = SVN0->getMaskElt(i); 2409 int Idx1 = SVN1->getMaskElt(i); 2410 if (Idx0 != Idx1) { 2411 SameMask = false; 2412 break; 2413 } 2414 } 2415 2416 if (SameMask) { 2417 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2418 N0.getOperand(0), N1.getOperand(0)); 2419 AddToWorkList(Op.getNode()); 2420 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2421 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2422 } 2423 } 2424 2425 return SDValue(); 2426} 2427 2428SDValue DAGCombiner::visitAND(SDNode *N) { 2429 SDValue N0 = N->getOperand(0); 2430 SDValue N1 = N->getOperand(1); 2431 SDValue LL, LR, RL, RR, CC0, CC1; 2432 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2433 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2434 EVT VT = N1.getValueType(); 2435 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2436 2437 // fold vector ops 2438 if (VT.isVector()) { 2439 SDValue FoldedVOp = SimplifyVBinOp(N); 2440 if (FoldedVOp.getNode()) return FoldedVOp; 2441 2442 // fold (and x, 0) -> 0, vector edition 2443 if (ISD::isBuildVectorAllZeros(N0.getNode())) 2444 return N0; 2445 if (ISD::isBuildVectorAllZeros(N1.getNode())) 2446 return N1; 2447 2448 // fold (and x, -1) -> x, vector edition 2449 if (ISD::isBuildVectorAllOnes(N0.getNode())) 2450 return N1; 2451 if (ISD::isBuildVectorAllOnes(N1.getNode())) 2452 return N0; 2453 } 2454 2455 // fold (and x, undef) -> 0 2456 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2457 return DAG.getConstant(0, VT); 2458 // fold (and c1, c2) -> c1&c2 2459 if (N0C && N1C) 2460 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2461 // canonicalize constant to RHS 2462 if (N0C && !N1C) 2463 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2464 // fold (and x, -1) -> x 2465 if (N1C && N1C->isAllOnesValue()) 2466 return N0; 2467 // if (and x, c) is known to be zero, return 0 2468 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2469 APInt::getAllOnesValue(BitWidth))) 2470 return DAG.getConstant(0, VT); 2471 // reassociate and 2472 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2473 if (RAND.getNode() != 0) 2474 return RAND; 2475 // fold (and (or x, C), D) -> D if (C & D) == D 2476 if (N1C && N0.getOpcode() == ISD::OR) 2477 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2478 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2479 return N1; 2480 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2481 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2482 SDValue N0Op0 = N0.getOperand(0); 2483 APInt Mask = ~N1C->getAPIntValue(); 2484 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2485 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2486 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2487 N0.getValueType(), N0Op0); 2488 2489 // Replace uses of the AND with uses of the Zero extend node. 2490 CombineTo(N, Zext); 2491 2492 // We actually want to replace all uses of the any_extend with the 2493 // zero_extend, to avoid duplicating things. This will later cause this 2494 // AND to be folded. 2495 CombineTo(N0.getNode(), Zext); 2496 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2497 } 2498 } 2499 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2500 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2501 // already be zero by virtue of the width of the base type of the load. 2502 // 2503 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2504 // more cases. 2505 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2506 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2507 N0.getOpcode() == ISD::LOAD) { 2508 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2509 N0 : N0.getOperand(0) ); 2510 2511 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2512 // This can be a pure constant or a vector splat, in which case we treat the 2513 // vector as a scalar and use the splat value. 2514 APInt Constant = APInt::getNullValue(1); 2515 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2516 Constant = C->getAPIntValue(); 2517 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2518 APInt SplatValue, SplatUndef; 2519 unsigned SplatBitSize; 2520 bool HasAnyUndefs; 2521 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2522 SplatBitSize, HasAnyUndefs); 2523 if (IsSplat) { 2524 // Undef bits can contribute to a possible optimisation if set, so 2525 // set them. 2526 SplatValue |= SplatUndef; 2527 2528 // The splat value may be something like "0x00FFFFFF", which means 0 for 2529 // the first vector value and FF for the rest, repeating. We need a mask 2530 // that will apply equally to all members of the vector, so AND all the 2531 // lanes of the constant together. 2532 EVT VT = Vector->getValueType(0); 2533 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2534 2535 // If the splat value has been compressed to a bitlength lower 2536 // than the size of the vector lane, we need to re-expand it to 2537 // the lane size. 2538 if (BitWidth > SplatBitSize) 2539 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2540 SplatBitSize < BitWidth; 2541 SplatBitSize = SplatBitSize * 2) 2542 SplatValue |= SplatValue.shl(SplatBitSize); 2543 2544 Constant = APInt::getAllOnesValue(BitWidth); 2545 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2546 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2547 } 2548 } 2549 2550 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2551 // actually legal and isn't going to get expanded, else this is a false 2552 // optimisation. 2553 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2554 Load->getMemoryVT()); 2555 2556 // Resize the constant to the same size as the original memory access before 2557 // extension. If it is still the AllOnesValue then this AND is completely 2558 // unneeded. 2559 Constant = 2560 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2561 2562 bool B; 2563 switch (Load->getExtensionType()) { 2564 default: B = false; break; 2565 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2566 case ISD::ZEXTLOAD: 2567 case ISD::NON_EXTLOAD: B = true; break; 2568 } 2569 2570 if (B && Constant.isAllOnesValue()) { 2571 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2572 // preserve semantics once we get rid of the AND. 2573 SDValue NewLoad(Load, 0); 2574 if (Load->getExtensionType() == ISD::EXTLOAD) { 2575 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2576 Load->getValueType(0), Load->getDebugLoc(), 2577 Load->getChain(), Load->getBasePtr(), 2578 Load->getOffset(), Load->getMemoryVT(), 2579 Load->getMemOperand()); 2580 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2581 if (Load->getNumValues() == 3) { 2582 // PRE/POST_INC loads have 3 values. 2583 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2584 NewLoad.getValue(2) }; 2585 CombineTo(Load, To, 3, true); 2586 } else { 2587 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2588 } 2589 } 2590 2591 // Fold the AND away, taking care not to fold to the old load node if we 2592 // replaced it. 2593 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2594 2595 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2596 } 2597 } 2598 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2599 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2600 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2601 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2602 2603 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2604 LL.getValueType().isInteger()) { 2605 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2606 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2607 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2608 LR.getValueType(), LL, RL); 2609 AddToWorkList(ORNode.getNode()); 2610 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2611 } 2612 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2613 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2614 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2615 LR.getValueType(), LL, RL); 2616 AddToWorkList(ANDNode.getNode()); 2617 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2618 } 2619 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2620 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2621 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2622 LR.getValueType(), LL, RL); 2623 AddToWorkList(ORNode.getNode()); 2624 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2625 } 2626 } 2627 // canonicalize equivalent to ll == rl 2628 if (LL == RR && LR == RL) { 2629 Op1 = ISD::getSetCCSwappedOperands(Op1); 2630 std::swap(RL, RR); 2631 } 2632 if (LL == RL && LR == RR) { 2633 bool isInteger = LL.getValueType().isInteger(); 2634 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2635 if (Result != ISD::SETCC_INVALID && 2636 (!LegalOperations || 2637 TLI.isCondCodeLegal(Result, LL.getSimpleValueType()))) 2638 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2639 LL, LR, Result); 2640 } 2641 } 2642 2643 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2644 if (N0.getOpcode() == N1.getOpcode()) { 2645 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2646 if (Tmp.getNode()) return Tmp; 2647 } 2648 2649 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2650 // fold (and (sra)) -> (and (srl)) when possible. 2651 if (!VT.isVector() && 2652 SimplifyDemandedBits(SDValue(N, 0))) 2653 return SDValue(N, 0); 2654 2655 // fold (zext_inreg (extload x)) -> (zextload x) 2656 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2657 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2658 EVT MemVT = LN0->getMemoryVT(); 2659 // If we zero all the possible extended bits, then we can turn this into 2660 // a zextload if we are running before legalize or the operation is legal. 2661 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2662 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2663 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2664 ((!LegalOperations && !LN0->isVolatile()) || 2665 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2666 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2667 LN0->getChain(), LN0->getBasePtr(), 2668 LN0->getPointerInfo(), MemVT, 2669 LN0->isVolatile(), LN0->isNonTemporal(), 2670 LN0->getAlignment()); 2671 AddToWorkList(N); 2672 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2673 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2674 } 2675 } 2676 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2677 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2678 N0.hasOneUse()) { 2679 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2680 EVT MemVT = LN0->getMemoryVT(); 2681 // If we zero all the possible extended bits, then we can turn this into 2682 // a zextload if we are running before legalize or the operation is legal. 2683 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2684 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2685 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2686 ((!LegalOperations && !LN0->isVolatile()) || 2687 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2688 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2689 LN0->getChain(), 2690 LN0->getBasePtr(), LN0->getPointerInfo(), 2691 MemVT, 2692 LN0->isVolatile(), LN0->isNonTemporal(), 2693 LN0->getAlignment()); 2694 AddToWorkList(N); 2695 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2696 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2697 } 2698 } 2699 2700 // fold (and (load x), 255) -> (zextload x, i8) 2701 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2702 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2703 if (N1C && (N0.getOpcode() == ISD::LOAD || 2704 (N0.getOpcode() == ISD::ANY_EXTEND && 2705 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2706 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2707 LoadSDNode *LN0 = HasAnyExt 2708 ? cast<LoadSDNode>(N0.getOperand(0)) 2709 : cast<LoadSDNode>(N0); 2710 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2711 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2712 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2713 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2714 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2715 EVT LoadedVT = LN0->getMemoryVT(); 2716 2717 if (ExtVT == LoadedVT && 2718 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2719 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2720 2721 SDValue NewLoad = 2722 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2723 LN0->getChain(), LN0->getBasePtr(), 2724 LN0->getPointerInfo(), 2725 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2726 LN0->getAlignment()); 2727 AddToWorkList(N); 2728 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2729 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2730 } 2731 2732 // Do not change the width of a volatile load. 2733 // Do not generate loads of non-round integer types since these can 2734 // be expensive (and would be wrong if the type is not byte sized). 2735 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2736 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2737 EVT PtrType = LN0->getOperand(1).getValueType(); 2738 2739 unsigned Alignment = LN0->getAlignment(); 2740 SDValue NewPtr = LN0->getBasePtr(); 2741 2742 // For big endian targets, we need to add an offset to the pointer 2743 // to load the correct bytes. For little endian systems, we merely 2744 // need to read fewer bytes from the same pointer. 2745 if (TLI.isBigEndian()) { 2746 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2747 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2748 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2749 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2750 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2751 Alignment = MinAlign(Alignment, PtrOff); 2752 } 2753 2754 AddToWorkList(NewPtr.getNode()); 2755 2756 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2757 SDValue Load = 2758 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2759 LN0->getChain(), NewPtr, 2760 LN0->getPointerInfo(), 2761 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2762 Alignment); 2763 AddToWorkList(N); 2764 CombineTo(LN0, Load, Load.getValue(1)); 2765 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2766 } 2767 } 2768 } 2769 } 2770 2771 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2772 VT.getSizeInBits() <= 64) { 2773 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2774 APInt ADDC = ADDI->getAPIntValue(); 2775 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2776 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2777 // immediate for an add, but it is legal if its top c2 bits are set, 2778 // transform the ADD so the immediate doesn't need to be materialized 2779 // in a register. 2780 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2781 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2782 SRLI->getZExtValue()); 2783 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2784 ADDC |= Mask; 2785 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2786 SDValue NewAdd = 2787 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 2788 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2789 CombineTo(N0.getNode(), NewAdd); 2790 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2791 } 2792 } 2793 } 2794 } 2795 } 2796 } 2797 2798 return SDValue(); 2799} 2800 2801/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2802/// 2803SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2804 bool DemandHighBits) { 2805 if (!LegalOperations) 2806 return SDValue(); 2807 2808 EVT VT = N->getValueType(0); 2809 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2810 return SDValue(); 2811 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2812 return SDValue(); 2813 2814 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2815 bool LookPassAnd0 = false; 2816 bool LookPassAnd1 = false; 2817 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2818 std::swap(N0, N1); 2819 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2820 std::swap(N0, N1); 2821 if (N0.getOpcode() == ISD::AND) { 2822 if (!N0.getNode()->hasOneUse()) 2823 return SDValue(); 2824 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2825 if (!N01C || N01C->getZExtValue() != 0xFF00) 2826 return SDValue(); 2827 N0 = N0.getOperand(0); 2828 LookPassAnd0 = true; 2829 } 2830 2831 if (N1.getOpcode() == ISD::AND) { 2832 if (!N1.getNode()->hasOneUse()) 2833 return SDValue(); 2834 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2835 if (!N11C || N11C->getZExtValue() != 0xFF) 2836 return SDValue(); 2837 N1 = N1.getOperand(0); 2838 LookPassAnd1 = true; 2839 } 2840 2841 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2842 std::swap(N0, N1); 2843 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2844 return SDValue(); 2845 if (!N0.getNode()->hasOneUse() || 2846 !N1.getNode()->hasOneUse()) 2847 return SDValue(); 2848 2849 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2850 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2851 if (!N01C || !N11C) 2852 return SDValue(); 2853 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2854 return SDValue(); 2855 2856 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2857 SDValue N00 = N0->getOperand(0); 2858 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2859 if (!N00.getNode()->hasOneUse()) 2860 return SDValue(); 2861 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2862 if (!N001C || N001C->getZExtValue() != 0xFF) 2863 return SDValue(); 2864 N00 = N00.getOperand(0); 2865 LookPassAnd0 = true; 2866 } 2867 2868 SDValue N10 = N1->getOperand(0); 2869 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2870 if (!N10.getNode()->hasOneUse()) 2871 return SDValue(); 2872 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2873 if (!N101C || N101C->getZExtValue() != 0xFF00) 2874 return SDValue(); 2875 N10 = N10.getOperand(0); 2876 LookPassAnd1 = true; 2877 } 2878 2879 if (N00 != N10) 2880 return SDValue(); 2881 2882 // Make sure everything beyond the low halfword is zero since the SRL 16 2883 // will clear the top bits. 2884 unsigned OpSizeInBits = VT.getSizeInBits(); 2885 if (DemandHighBits && OpSizeInBits > 16 && 2886 (!LookPassAnd0 || !LookPassAnd1) && 2887 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2888 return SDValue(); 2889 2890 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2891 if (OpSizeInBits > 16) 2892 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2893 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2894 return Res; 2895} 2896 2897/// isBSwapHWordElement - Return true if the specified node is an element 2898/// that makes up a 32-bit packed halfword byteswap. i.e. 2899/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2900static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2901 if (!N.getNode()->hasOneUse()) 2902 return false; 2903 2904 unsigned Opc = N.getOpcode(); 2905 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2906 return false; 2907 2908 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2909 if (!N1C) 2910 return false; 2911 2912 unsigned Num; 2913 switch (N1C->getZExtValue()) { 2914 default: 2915 return false; 2916 case 0xFF: Num = 0; break; 2917 case 0xFF00: Num = 1; break; 2918 case 0xFF0000: Num = 2; break; 2919 case 0xFF000000: Num = 3; break; 2920 } 2921 2922 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2923 SDValue N0 = N.getOperand(0); 2924 if (Opc == ISD::AND) { 2925 if (Num == 0 || Num == 2) { 2926 // (x >> 8) & 0xff 2927 // (x >> 8) & 0xff0000 2928 if (N0.getOpcode() != ISD::SRL) 2929 return false; 2930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2931 if (!C || C->getZExtValue() != 8) 2932 return false; 2933 } else { 2934 // (x << 8) & 0xff00 2935 // (x << 8) & 0xff000000 2936 if (N0.getOpcode() != ISD::SHL) 2937 return false; 2938 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2939 if (!C || C->getZExtValue() != 8) 2940 return false; 2941 } 2942 } else if (Opc == ISD::SHL) { 2943 // (x & 0xff) << 8 2944 // (x & 0xff0000) << 8 2945 if (Num != 0 && Num != 2) 2946 return false; 2947 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2948 if (!C || C->getZExtValue() != 8) 2949 return false; 2950 } else { // Opc == ISD::SRL 2951 // (x & 0xff00) >> 8 2952 // (x & 0xff000000) >> 8 2953 if (Num != 1 && Num != 3) 2954 return false; 2955 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2956 if (!C || C->getZExtValue() != 8) 2957 return false; 2958 } 2959 2960 if (Parts[Num]) 2961 return false; 2962 2963 Parts[Num] = N0.getOperand(0).getNode(); 2964 return true; 2965} 2966 2967/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2968/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2969/// => (rotl (bswap x), 16) 2970SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2971 if (!LegalOperations) 2972 return SDValue(); 2973 2974 EVT VT = N->getValueType(0); 2975 if (VT != MVT::i32) 2976 return SDValue(); 2977 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2978 return SDValue(); 2979 2980 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2981 // Look for either 2982 // (or (or (and), (and)), (or (and), (and))) 2983 // (or (or (or (and), (and)), (and)), (and)) 2984 if (N0.getOpcode() != ISD::OR) 2985 return SDValue(); 2986 SDValue N00 = N0.getOperand(0); 2987 SDValue N01 = N0.getOperand(1); 2988 2989 if (N1.getOpcode() == ISD::OR && 2990 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) { 2991 // (or (or (and), (and)), (or (and), (and))) 2992 SDValue N000 = N00.getOperand(0); 2993 if (!isBSwapHWordElement(N000, Parts)) 2994 return SDValue(); 2995 2996 SDValue N001 = N00.getOperand(1); 2997 if (!isBSwapHWordElement(N001, Parts)) 2998 return SDValue(); 2999 SDValue N010 = N01.getOperand(0); 3000 if (!isBSwapHWordElement(N010, Parts)) 3001 return SDValue(); 3002 SDValue N011 = N01.getOperand(1); 3003 if (!isBSwapHWordElement(N011, Parts)) 3004 return SDValue(); 3005 } else { 3006 // (or (or (or (and), (and)), (and)), (and)) 3007 if (!isBSwapHWordElement(N1, Parts)) 3008 return SDValue(); 3009 if (!isBSwapHWordElement(N01, Parts)) 3010 return SDValue(); 3011 if (N00.getOpcode() != ISD::OR) 3012 return SDValue(); 3013 SDValue N000 = N00.getOperand(0); 3014 if (!isBSwapHWordElement(N000, Parts)) 3015 return SDValue(); 3016 SDValue N001 = N00.getOperand(1); 3017 if (!isBSwapHWordElement(N001, Parts)) 3018 return SDValue(); 3019 } 3020 3021 // Make sure the parts are all coming from the same node. 3022 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 3023 return SDValue(); 3024 3025 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 3026 SDValue(Parts[0],0)); 3027 3028 // Result of the bswap should be rotated by 16. If it's not legal, than 3029 // do (x << 16) | (x >> 16). 3030 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 3031 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3032 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 3033 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3034 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 3035 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 3036 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 3037 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 3038} 3039 3040SDValue DAGCombiner::visitOR(SDNode *N) { 3041 SDValue N0 = N->getOperand(0); 3042 SDValue N1 = N->getOperand(1); 3043 SDValue LL, LR, RL, RR, CC0, CC1; 3044 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3045 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3046 EVT VT = N1.getValueType(); 3047 3048 // fold vector ops 3049 if (VT.isVector()) { 3050 SDValue FoldedVOp = SimplifyVBinOp(N); 3051 if (FoldedVOp.getNode()) return FoldedVOp; 3052 3053 // fold (or x, 0) -> x, vector edition 3054 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3055 return N1; 3056 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3057 return N0; 3058 3059 // fold (or x, -1) -> -1, vector edition 3060 if (ISD::isBuildVectorAllOnes(N0.getNode())) 3061 return N0; 3062 if (ISD::isBuildVectorAllOnes(N1.getNode())) 3063 return N1; 3064 } 3065 3066 // fold (or x, undef) -> -1 3067 if (!LegalOperations && 3068 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3069 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3070 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3071 } 3072 // fold (or c1, c2) -> c1|c2 3073 if (N0C && N1C) 3074 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3075 // canonicalize constant to RHS 3076 if (N0C && !N1C) 3077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 3078 // fold (or x, 0) -> x 3079 if (N1C && N1C->isNullValue()) 3080 return N0; 3081 // fold (or x, -1) -> -1 3082 if (N1C && N1C->isAllOnesValue()) 3083 return N1; 3084 // fold (or x, c) -> c iff (x & ~c) == 0 3085 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3086 return N1; 3087 3088 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3089 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3090 if (BSwap.getNode() != 0) 3091 return BSwap; 3092 BSwap = MatchBSwapHWordLow(N, N0, N1); 3093 if (BSwap.getNode() != 0) 3094 return BSwap; 3095 3096 // reassociate or 3097 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3098 if (ROR.getNode() != 0) 3099 return ROR; 3100 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3101 // iff (c1 & c2) == 0. 3102 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3103 isa<ConstantSDNode>(N0.getOperand(1))) { 3104 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3105 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3106 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3107 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3108 N0.getOperand(0), N1), 3109 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3110 } 3111 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3112 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3113 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3114 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3115 3116 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3117 LL.getValueType().isInteger()) { 3118 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3119 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3120 if (cast<ConstantSDNode>(LR)->isNullValue() && 3121 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3122 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3123 LR.getValueType(), LL, RL); 3124 AddToWorkList(ORNode.getNode()); 3125 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3126 } 3127 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3128 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3129 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3130 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3131 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3132 LR.getValueType(), LL, RL); 3133 AddToWorkList(ANDNode.getNode()); 3134 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3135 } 3136 } 3137 // canonicalize equivalent to ll == rl 3138 if (LL == RR && LR == RL) { 3139 Op1 = ISD::getSetCCSwappedOperands(Op1); 3140 std::swap(RL, RR); 3141 } 3142 if (LL == RL && LR == RR) { 3143 bool isInteger = LL.getValueType().isInteger(); 3144 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3145 if (Result != ISD::SETCC_INVALID && 3146 (!LegalOperations || 3147 TLI.isCondCodeLegal(Result, LL.getSimpleValueType()))) 3148 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3149 LL, LR, Result); 3150 } 3151 } 3152 3153 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3154 if (N0.getOpcode() == N1.getOpcode()) { 3155 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3156 if (Tmp.getNode()) return Tmp; 3157 } 3158 3159 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3160 if (N0.getOpcode() == ISD::AND && 3161 N1.getOpcode() == ISD::AND && 3162 N0.getOperand(1).getOpcode() == ISD::Constant && 3163 N1.getOperand(1).getOpcode() == ISD::Constant && 3164 // Don't increase # computations. 3165 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3166 // We can only do this xform if we know that bits from X that are set in C2 3167 // but not in C1 are already zero. Likewise for Y. 3168 const APInt &LHSMask = 3169 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3170 const APInt &RHSMask = 3171 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3172 3173 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3174 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3175 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3176 N0.getOperand(0), N1.getOperand(0)); 3177 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3178 DAG.getConstant(LHSMask | RHSMask, VT)); 3179 } 3180 } 3181 3182 // See if this is some rotate idiom. 3183 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3184 return SDValue(Rot, 0); 3185 3186 // Simplify the operands using demanded-bits information. 3187 if (!VT.isVector() && 3188 SimplifyDemandedBits(SDValue(N, 0))) 3189 return SDValue(N, 0); 3190 3191 return SDValue(); 3192} 3193 3194/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3195static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3196 if (Op.getOpcode() == ISD::AND) { 3197 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3198 Mask = Op.getOperand(1); 3199 Op = Op.getOperand(0); 3200 } else { 3201 return false; 3202 } 3203 } 3204 3205 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3206 Shift = Op; 3207 return true; 3208 } 3209 3210 return false; 3211} 3212 3213// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3214// idioms for rotate, and if the target supports rotation instructions, generate 3215// a rot[lr]. 3216SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3217 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3218 EVT VT = LHS.getValueType(); 3219 if (!TLI.isTypeLegal(VT)) return 0; 3220 3221 // The target must have at least one rotate flavor. 3222 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3223 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3224 if (!HasROTL && !HasROTR) return 0; 3225 3226 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3227 SDValue LHSShift; // The shift. 3228 SDValue LHSMask; // AND value if any. 3229 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3230 return 0; // Not part of a rotate. 3231 3232 SDValue RHSShift; // The shift. 3233 SDValue RHSMask; // AND value if any. 3234 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3235 return 0; // Not part of a rotate. 3236 3237 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3238 return 0; // Not shifting the same value. 3239 3240 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3241 return 0; // Shifts must disagree. 3242 3243 // Canonicalize shl to left side in a shl/srl pair. 3244 if (RHSShift.getOpcode() == ISD::SHL) { 3245 std::swap(LHS, RHS); 3246 std::swap(LHSShift, RHSShift); 3247 std::swap(LHSMask , RHSMask ); 3248 } 3249 3250 unsigned OpSizeInBits = VT.getSizeInBits(); 3251 SDValue LHSShiftArg = LHSShift.getOperand(0); 3252 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3253 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3254 3255 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3256 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3257 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3258 RHSShiftAmt.getOpcode() == ISD::Constant) { 3259 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3260 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3261 if ((LShVal + RShVal) != OpSizeInBits) 3262 return 0; 3263 3264 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3265 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt); 3266 3267 // If there is an AND of either shifted operand, apply it to the result. 3268 if (LHSMask.getNode() || RHSMask.getNode()) { 3269 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3270 3271 if (LHSMask.getNode()) { 3272 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3273 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3274 } 3275 if (RHSMask.getNode()) { 3276 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3277 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3278 } 3279 3280 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3281 } 3282 3283 return Rot.getNode(); 3284 } 3285 3286 // If there is a mask here, and we have a variable shift, we can't be sure 3287 // that we're masking out the right stuff. 3288 if (LHSMask.getNode() || RHSMask.getNode()) 3289 return 0; 3290 3291 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3292 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3293 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3294 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3295 if (ConstantSDNode *SUBC = 3296 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3297 if (SUBC->getAPIntValue() == OpSizeInBits) { 3298 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, 3299 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3300 } 3301 } 3302 } 3303 3304 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3305 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3306 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3307 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3308 if (ConstantSDNode *SUBC = 3309 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3310 if (SUBC->getAPIntValue() == OpSizeInBits) { 3311 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, 3312 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3313 } 3314 } 3315 } 3316 3317 // Look for sign/zext/any-extended or truncate cases: 3318 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3319 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3320 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3321 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3322 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3323 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3324 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3325 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3326 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3327 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3328 if (RExtOp0.getOpcode() == ISD::SUB && 3329 RExtOp0.getOperand(1) == LExtOp0) { 3330 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3331 // (rotl x, y) 3332 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3333 // (rotr x, (sub 32, y)) 3334 if (ConstantSDNode *SUBC = 3335 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3336 if (SUBC->getAPIntValue() == OpSizeInBits) { 3337 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3338 LHSShiftArg, 3339 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3340 } 3341 } 3342 } else if (LExtOp0.getOpcode() == ISD::SUB && 3343 RExtOp0 == LExtOp0.getOperand(1)) { 3344 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3345 // (rotr x, y) 3346 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3347 // (rotl x, (sub 32, y)) 3348 if (ConstantSDNode *SUBC = 3349 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3350 if (SUBC->getAPIntValue() == OpSizeInBits) { 3351 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3352 LHSShiftArg, 3353 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3354 } 3355 } 3356 } 3357 } 3358 3359 return 0; 3360} 3361 3362SDValue DAGCombiner::visitXOR(SDNode *N) { 3363 SDValue N0 = N->getOperand(0); 3364 SDValue N1 = N->getOperand(1); 3365 SDValue LHS, RHS, CC; 3366 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3367 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3368 EVT VT = N0.getValueType(); 3369 3370 // fold vector ops 3371 if (VT.isVector()) { 3372 SDValue FoldedVOp = SimplifyVBinOp(N); 3373 if (FoldedVOp.getNode()) return FoldedVOp; 3374 3375 // fold (xor x, 0) -> x, vector edition 3376 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3377 return N1; 3378 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3379 return N0; 3380 } 3381 3382 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3383 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3384 return DAG.getConstant(0, VT); 3385 // fold (xor x, undef) -> undef 3386 if (N0.getOpcode() == ISD::UNDEF) 3387 return N0; 3388 if (N1.getOpcode() == ISD::UNDEF) 3389 return N1; 3390 // fold (xor c1, c2) -> c1^c2 3391 if (N0C && N1C) 3392 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3393 // canonicalize constant to RHS 3394 if (N0C && !N1C) 3395 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3396 // fold (xor x, 0) -> x 3397 if (N1C && N1C->isNullValue()) 3398 return N0; 3399 // reassociate xor 3400 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3401 if (RXOR.getNode() != 0) 3402 return RXOR; 3403 3404 // fold !(x cc y) -> (x !cc y) 3405 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3406 bool isInt = LHS.getValueType().isInteger(); 3407 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3408 isInt); 3409 3410 if (!LegalOperations || 3411 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) { 3412 switch (N0.getOpcode()) { 3413 default: 3414 llvm_unreachable("Unhandled SetCC Equivalent!"); 3415 case ISD::SETCC: 3416 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3417 case ISD::SELECT_CC: 3418 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3419 N0.getOperand(3), NotCC); 3420 } 3421 } 3422 } 3423 3424 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3425 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3426 N0.getNode()->hasOneUse() && 3427 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3428 SDValue V = N0.getOperand(0); 3429 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3430 DAG.getConstant(1, V.getValueType())); 3431 AddToWorkList(V.getNode()); 3432 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3433 } 3434 3435 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3436 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3437 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3438 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3439 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3440 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3441 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3442 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3443 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3444 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3445 } 3446 } 3447 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3448 if (N1C && N1C->isAllOnesValue() && 3449 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3450 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3451 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3452 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3453 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3454 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3455 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3456 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3457 } 3458 } 3459 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3460 if (N1C && N0.getOpcode() == ISD::XOR) { 3461 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3462 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3463 if (N00C) 3464 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3465 DAG.getConstant(N1C->getAPIntValue() ^ 3466 N00C->getAPIntValue(), VT)); 3467 if (N01C) 3468 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3469 DAG.getConstant(N1C->getAPIntValue() ^ 3470 N01C->getAPIntValue(), VT)); 3471 } 3472 // fold (xor x, x) -> 0 3473 if (N0 == N1) 3474 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3475 3476 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3477 if (N0.getOpcode() == N1.getOpcode()) { 3478 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3479 if (Tmp.getNode()) return Tmp; 3480 } 3481 3482 // Simplify the expression using non-local knowledge. 3483 if (!VT.isVector() && 3484 SimplifyDemandedBits(SDValue(N, 0))) 3485 return SDValue(N, 0); 3486 3487 return SDValue(); 3488} 3489 3490/// visitShiftByConstant - Handle transforms common to the three shifts, when 3491/// the shift amount is a constant. 3492SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3493 SDNode *LHS = N->getOperand(0).getNode(); 3494 if (!LHS->hasOneUse()) return SDValue(); 3495 3496 // We want to pull some binops through shifts, so that we have (and (shift)) 3497 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3498 // thing happens with address calculations, so it's important to canonicalize 3499 // it. 3500 bool HighBitSet = false; // Can we transform this if the high bit is set? 3501 3502 switch (LHS->getOpcode()) { 3503 default: return SDValue(); 3504 case ISD::OR: 3505 case ISD::XOR: 3506 HighBitSet = false; // We can only transform sra if the high bit is clear. 3507 break; 3508 case ISD::AND: 3509 HighBitSet = true; // We can only transform sra if the high bit is set. 3510 break; 3511 case ISD::ADD: 3512 if (N->getOpcode() != ISD::SHL) 3513 return SDValue(); // only shl(add) not sr[al](add). 3514 HighBitSet = false; // We can only transform sra if the high bit is clear. 3515 break; 3516 } 3517 3518 // We require the RHS of the binop to be a constant as well. 3519 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3520 if (!BinOpCst) return SDValue(); 3521 3522 // FIXME: disable this unless the input to the binop is a shift by a constant. 3523 // If it is not a shift, it pessimizes some common cases like: 3524 // 3525 // void foo(int *X, int i) { X[i & 1235] = 1; } 3526 // int bar(int *X, int i) { return X[i & 255]; } 3527 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3528 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3529 BinOpLHSVal->getOpcode() != ISD::SRA && 3530 BinOpLHSVal->getOpcode() != ISD::SRL) || 3531 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3532 return SDValue(); 3533 3534 EVT VT = N->getValueType(0); 3535 3536 // If this is a signed shift right, and the high bit is modified by the 3537 // logical operation, do not perform the transformation. The highBitSet 3538 // boolean indicates the value of the high bit of the constant which would 3539 // cause it to be modified for this operation. 3540 if (N->getOpcode() == ISD::SRA) { 3541 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3542 if (BinOpRHSSignSet != HighBitSet) 3543 return SDValue(); 3544 } 3545 3546 // Fold the constants, shifting the binop RHS by the shift amount. 3547 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3548 N->getValueType(0), 3549 LHS->getOperand(1), N->getOperand(1)); 3550 3551 // Create the new shift. 3552 SDValue NewShift = DAG.getNode(N->getOpcode(), 3553 LHS->getOperand(0).getDebugLoc(), 3554 VT, LHS->getOperand(0), N->getOperand(1)); 3555 3556 // Create the new binop. 3557 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3558} 3559 3560SDValue DAGCombiner::visitSHL(SDNode *N) { 3561 SDValue N0 = N->getOperand(0); 3562 SDValue N1 = N->getOperand(1); 3563 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3564 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3565 EVT VT = N0.getValueType(); 3566 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3567 3568 // fold (shl c1, c2) -> c1<<c2 3569 if (N0C && N1C) 3570 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3571 // fold (shl 0, x) -> 0 3572 if (N0C && N0C->isNullValue()) 3573 return N0; 3574 // fold (shl x, c >= size(x)) -> undef 3575 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3576 return DAG.getUNDEF(VT); 3577 // fold (shl x, 0) -> x 3578 if (N1C && N1C->isNullValue()) 3579 return N0; 3580 // fold (shl undef, x) -> 0 3581 if (N0.getOpcode() == ISD::UNDEF) 3582 return DAG.getConstant(0, VT); 3583 // if (shl x, c) is known to be zero, return 0 3584 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3585 APInt::getAllOnesValue(OpSizeInBits))) 3586 return DAG.getConstant(0, VT); 3587 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3588 if (N1.getOpcode() == ISD::TRUNCATE && 3589 N1.getOperand(0).getOpcode() == ISD::AND && 3590 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3591 SDValue N101 = N1.getOperand(0).getOperand(1); 3592 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3593 EVT TruncVT = N1.getValueType(); 3594 SDValue N100 = N1.getOperand(0).getOperand(0); 3595 APInt TruncC = N101C->getAPIntValue(); 3596 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3597 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3598 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3599 DAG.getNode(ISD::TRUNCATE, 3600 N->getDebugLoc(), 3601 TruncVT, N100), 3602 DAG.getConstant(TruncC, TruncVT))); 3603 } 3604 } 3605 3606 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3607 return SDValue(N, 0); 3608 3609 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3610 if (N1C && N0.getOpcode() == ISD::SHL && 3611 N0.getOperand(1).getOpcode() == ISD::Constant) { 3612 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3613 uint64_t c2 = N1C->getZExtValue(); 3614 if (c1 + c2 >= OpSizeInBits) 3615 return DAG.getConstant(0, VT); 3616 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3617 DAG.getConstant(c1 + c2, N1.getValueType())); 3618 } 3619 3620 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3621 // For this to be valid, the second form must not preserve any of the bits 3622 // that are shifted out by the inner shift in the first form. This means 3623 // the outer shift size must be >= the number of bits added by the ext. 3624 // As a corollary, we don't care what kind of ext it is. 3625 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3626 N0.getOpcode() == ISD::ANY_EXTEND || 3627 N0.getOpcode() == ISD::SIGN_EXTEND) && 3628 N0.getOperand(0).getOpcode() == ISD::SHL && 3629 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3630 uint64_t c1 = 3631 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3632 uint64_t c2 = N1C->getZExtValue(); 3633 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3634 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3635 if (c2 >= OpSizeInBits - InnerShiftSize) { 3636 if (c1 + c2 >= OpSizeInBits) 3637 return DAG.getConstant(0, VT); 3638 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3639 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3640 N0.getOperand(0)->getOperand(0)), 3641 DAG.getConstant(c1 + c2, N1.getValueType())); 3642 } 3643 } 3644 3645 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3646 // (and (srl x, (sub c1, c2), MASK) 3647 // Only fold this if the inner shift has no other uses -- if it does, folding 3648 // this will increase the total number of instructions. 3649 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3650 N0.getOperand(1).getOpcode() == ISD::Constant) { 3651 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3652 if (c1 < VT.getSizeInBits()) { 3653 uint64_t c2 = N1C->getZExtValue(); 3654 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3655 VT.getSizeInBits() - c1); 3656 SDValue Shift; 3657 if (c2 > c1) { 3658 Mask = Mask.shl(c2-c1); 3659 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3660 DAG.getConstant(c2-c1, N1.getValueType())); 3661 } else { 3662 Mask = Mask.lshr(c1-c2); 3663 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3664 DAG.getConstant(c1-c2, N1.getValueType())); 3665 } 3666 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3667 DAG.getConstant(Mask, VT)); 3668 } 3669 } 3670 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3671 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3672 SDValue HiBitsMask = 3673 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3674 VT.getSizeInBits() - 3675 N1C->getZExtValue()), 3676 VT); 3677 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3678 HiBitsMask); 3679 } 3680 3681 if (N1C) { 3682 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3683 if (NewSHL.getNode()) 3684 return NewSHL; 3685 } 3686 3687 return SDValue(); 3688} 3689 3690SDValue DAGCombiner::visitSRA(SDNode *N) { 3691 SDValue N0 = N->getOperand(0); 3692 SDValue N1 = N->getOperand(1); 3693 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3694 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3695 EVT VT = N0.getValueType(); 3696 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3697 3698 // fold (sra c1, c2) -> (sra c1, c2) 3699 if (N0C && N1C) 3700 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3701 // fold (sra 0, x) -> 0 3702 if (N0C && N0C->isNullValue()) 3703 return N0; 3704 // fold (sra -1, x) -> -1 3705 if (N0C && N0C->isAllOnesValue()) 3706 return N0; 3707 // fold (sra x, (setge c, size(x))) -> undef 3708 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3709 return DAG.getUNDEF(VT); 3710 // fold (sra x, 0) -> x 3711 if (N1C && N1C->isNullValue()) 3712 return N0; 3713 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3714 // sext_inreg. 3715 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3716 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3717 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3718 if (VT.isVector()) 3719 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3720 ExtVT, VT.getVectorNumElements()); 3721 if ((!LegalOperations || 3722 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3723 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3724 N0.getOperand(0), DAG.getValueType(ExtVT)); 3725 } 3726 3727 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3728 if (N1C && N0.getOpcode() == ISD::SRA) { 3729 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3730 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3731 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3732 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3733 DAG.getConstant(Sum, N1C->getValueType(0))); 3734 } 3735 } 3736 3737 // fold (sra (shl X, m), (sub result_size, n)) 3738 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3739 // result_size - n != m. 3740 // If truncate is free for the target sext(shl) is likely to result in better 3741 // code. 3742 if (N0.getOpcode() == ISD::SHL) { 3743 // Get the two constanst of the shifts, CN0 = m, CN = n. 3744 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3745 if (N01C && N1C) { 3746 // Determine what the truncate's result bitsize and type would be. 3747 EVT TruncVT = 3748 EVT::getIntegerVT(*DAG.getContext(), 3749 OpSizeInBits - N1C->getZExtValue()); 3750 // Determine the residual right-shift amount. 3751 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3752 3753 // If the shift is not a no-op (in which case this should be just a sign 3754 // extend already), the truncated to type is legal, sign_extend is legal 3755 // on that type, and the truncate to that type is both legal and free, 3756 // perform the transform. 3757 if ((ShiftAmt > 0) && 3758 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3759 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3760 TLI.isTruncateFree(VT, TruncVT)) { 3761 3762 SDValue Amt = DAG.getConstant(ShiftAmt, 3763 getShiftAmountTy(N0.getOperand(0).getValueType())); 3764 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3765 N0.getOperand(0), Amt); 3766 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3767 Shift); 3768 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3769 N->getValueType(0), Trunc); 3770 } 3771 } 3772 } 3773 3774 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3775 if (N1.getOpcode() == ISD::TRUNCATE && 3776 N1.getOperand(0).getOpcode() == ISD::AND && 3777 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3778 SDValue N101 = N1.getOperand(0).getOperand(1); 3779 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3780 EVT TruncVT = N1.getValueType(); 3781 SDValue N100 = N1.getOperand(0).getOperand(0); 3782 APInt TruncC = N101C->getAPIntValue(); 3783 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3784 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3785 DAG.getNode(ISD::AND, N->getDebugLoc(), 3786 TruncVT, 3787 DAG.getNode(ISD::TRUNCATE, 3788 N->getDebugLoc(), 3789 TruncVT, N100), 3790 DAG.getConstant(TruncC, TruncVT))); 3791 } 3792 } 3793 3794 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3795 // if c1 is equal to the number of bits the trunc removes 3796 if (N0.getOpcode() == ISD::TRUNCATE && 3797 (N0.getOperand(0).getOpcode() == ISD::SRL || 3798 N0.getOperand(0).getOpcode() == ISD::SRA) && 3799 N0.getOperand(0).hasOneUse() && 3800 N0.getOperand(0).getOperand(1).hasOneUse() && 3801 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3802 EVT LargeVT = N0.getOperand(0).getValueType(); 3803 ConstantSDNode *LargeShiftAmt = 3804 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3805 3806 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3807 LargeShiftAmt->getZExtValue()) { 3808 SDValue Amt = 3809 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3810 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3811 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3812 N0.getOperand(0).getOperand(0), Amt); 3813 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3814 } 3815 } 3816 3817 // Simplify, based on bits shifted out of the LHS. 3818 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3819 return SDValue(N, 0); 3820 3821 3822 // If the sign bit is known to be zero, switch this to a SRL. 3823 if (DAG.SignBitIsZero(N0)) 3824 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3825 3826 if (N1C) { 3827 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3828 if (NewSRA.getNode()) 3829 return NewSRA; 3830 } 3831 3832 return SDValue(); 3833} 3834 3835SDValue DAGCombiner::visitSRL(SDNode *N) { 3836 SDValue N0 = N->getOperand(0); 3837 SDValue N1 = N->getOperand(1); 3838 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3839 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3840 EVT VT = N0.getValueType(); 3841 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3842 3843 // fold (srl c1, c2) -> c1 >>u c2 3844 if (N0C && N1C) 3845 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3846 // fold (srl 0, x) -> 0 3847 if (N0C && N0C->isNullValue()) 3848 return N0; 3849 // fold (srl x, c >= size(x)) -> undef 3850 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3851 return DAG.getUNDEF(VT); 3852 // fold (srl x, 0) -> x 3853 if (N1C && N1C->isNullValue()) 3854 return N0; 3855 // if (srl x, c) is known to be zero, return 0 3856 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3857 APInt::getAllOnesValue(OpSizeInBits))) 3858 return DAG.getConstant(0, VT); 3859 3860 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3861 if (N1C && N0.getOpcode() == ISD::SRL && 3862 N0.getOperand(1).getOpcode() == ISD::Constant) { 3863 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3864 uint64_t c2 = N1C->getZExtValue(); 3865 if (c1 + c2 >= OpSizeInBits) 3866 return DAG.getConstant(0, VT); 3867 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3868 DAG.getConstant(c1 + c2, N1.getValueType())); 3869 } 3870 3871 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3872 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3873 N0.getOperand(0).getOpcode() == ISD::SRL && 3874 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3875 uint64_t c1 = 3876 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3877 uint64_t c2 = N1C->getZExtValue(); 3878 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3879 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3880 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3881 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3882 if (c1 + OpSizeInBits == InnerShiftSize) { 3883 if (c1 + c2 >= InnerShiftSize) 3884 return DAG.getConstant(0, VT); 3885 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3886 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3887 N0.getOperand(0)->getOperand(0), 3888 DAG.getConstant(c1 + c2, ShiftCountVT))); 3889 } 3890 } 3891 3892 // fold (srl (shl x, c), c) -> (and x, cst2) 3893 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3894 N0.getValueSizeInBits() <= 64) { 3895 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3896 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3897 DAG.getConstant(~0ULL >> ShAmt, VT)); 3898 } 3899 3900 3901 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3902 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3903 // Shifting in all undef bits? 3904 EVT SmallVT = N0.getOperand(0).getValueType(); 3905 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3906 return DAG.getUNDEF(VT); 3907 3908 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3909 uint64_t ShiftAmt = N1C->getZExtValue(); 3910 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3911 N0.getOperand(0), 3912 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3913 AddToWorkList(SmallShift.getNode()); 3914 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3915 } 3916 } 3917 3918 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3919 // bit, which is unmodified by sra. 3920 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3921 if (N0.getOpcode() == ISD::SRA) 3922 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3923 } 3924 3925 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3926 if (N1C && N0.getOpcode() == ISD::CTLZ && 3927 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3928 APInt KnownZero, KnownOne; 3929 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3930 3931 // If any of the input bits are KnownOne, then the input couldn't be all 3932 // zeros, thus the result of the srl will always be zero. 3933 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3934 3935 // If all of the bits input the to ctlz node are known to be zero, then 3936 // the result of the ctlz is "32" and the result of the shift is one. 3937 APInt UnknownBits = ~KnownZero; 3938 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3939 3940 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3941 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3942 // Okay, we know that only that the single bit specified by UnknownBits 3943 // could be set on input to the CTLZ node. If this bit is set, the SRL 3944 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3945 // to an SRL/XOR pair, which is likely to simplify more. 3946 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3947 SDValue Op = N0.getOperand(0); 3948 3949 if (ShAmt) { 3950 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3951 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3952 AddToWorkList(Op.getNode()); 3953 } 3954 3955 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3956 Op, DAG.getConstant(1, VT)); 3957 } 3958 } 3959 3960 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3961 if (N1.getOpcode() == ISD::TRUNCATE && 3962 N1.getOperand(0).getOpcode() == ISD::AND && 3963 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3964 SDValue N101 = N1.getOperand(0).getOperand(1); 3965 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3966 EVT TruncVT = N1.getValueType(); 3967 SDValue N100 = N1.getOperand(0).getOperand(0); 3968 APInt TruncC = N101C->getAPIntValue(); 3969 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3970 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3971 DAG.getNode(ISD::AND, N->getDebugLoc(), 3972 TruncVT, 3973 DAG.getNode(ISD::TRUNCATE, 3974 N->getDebugLoc(), 3975 TruncVT, N100), 3976 DAG.getConstant(TruncC, TruncVT))); 3977 } 3978 } 3979 3980 // fold operands of srl based on knowledge that the low bits are not 3981 // demanded. 3982 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3983 return SDValue(N, 0); 3984 3985 if (N1C) { 3986 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3987 if (NewSRL.getNode()) 3988 return NewSRL; 3989 } 3990 3991 // Attempt to convert a srl of a load into a narrower zero-extending load. 3992 SDValue NarrowLoad = ReduceLoadWidth(N); 3993 if (NarrowLoad.getNode()) 3994 return NarrowLoad; 3995 3996 // Here is a common situation. We want to optimize: 3997 // 3998 // %a = ... 3999 // %b = and i32 %a, 2 4000 // %c = srl i32 %b, 1 4001 // brcond i32 %c ... 4002 // 4003 // into 4004 // 4005 // %a = ... 4006 // %b = and %a, 2 4007 // %c = setcc eq %b, 0 4008 // brcond %c ... 4009 // 4010 // However when after the source operand of SRL is optimized into AND, the SRL 4011 // itself may not be optimized further. Look for it and add the BRCOND into 4012 // the worklist. 4013 if (N->hasOneUse()) { 4014 SDNode *Use = *N->use_begin(); 4015 if (Use->getOpcode() == ISD::BRCOND) 4016 AddToWorkList(Use); 4017 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 4018 // Also look pass the truncate. 4019 Use = *Use->use_begin(); 4020 if (Use->getOpcode() == ISD::BRCOND) 4021 AddToWorkList(Use); 4022 } 4023 } 4024 4025 return SDValue(); 4026} 4027 4028SDValue DAGCombiner::visitCTLZ(SDNode *N) { 4029 SDValue N0 = N->getOperand(0); 4030 EVT VT = N->getValueType(0); 4031 4032 // fold (ctlz c1) -> c2 4033 if (isa<ConstantSDNode>(N0)) 4034 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 4035 return SDValue(); 4036} 4037 4038SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 4039 SDValue N0 = N->getOperand(0); 4040 EVT VT = N->getValueType(0); 4041 4042 // fold (ctlz_zero_undef c1) -> c2 4043 if (isa<ConstantSDNode>(N0)) 4044 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4045 return SDValue(); 4046} 4047 4048SDValue DAGCombiner::visitCTTZ(SDNode *N) { 4049 SDValue N0 = N->getOperand(0); 4050 EVT VT = N->getValueType(0); 4051 4052 // fold (cttz c1) -> c2 4053 if (isa<ConstantSDNode>(N0)) 4054 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 4055 return SDValue(); 4056} 4057 4058SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4059 SDValue N0 = N->getOperand(0); 4060 EVT VT = N->getValueType(0); 4061 4062 // fold (cttz_zero_undef c1) -> c2 4063 if (isa<ConstantSDNode>(N0)) 4064 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4065 return SDValue(); 4066} 4067 4068SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4069 SDValue N0 = N->getOperand(0); 4070 EVT VT = N->getValueType(0); 4071 4072 // fold (ctpop c1) -> c2 4073 if (isa<ConstantSDNode>(N0)) 4074 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 4075 return SDValue(); 4076} 4077 4078SDValue DAGCombiner::visitSELECT(SDNode *N) { 4079 SDValue N0 = N->getOperand(0); 4080 SDValue N1 = N->getOperand(1); 4081 SDValue N2 = N->getOperand(2); 4082 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4083 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4084 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4085 EVT VT = N->getValueType(0); 4086 EVT VT0 = N0.getValueType(); 4087 4088 // fold (select C, X, X) -> X 4089 if (N1 == N2) 4090 return N1; 4091 // fold (select true, X, Y) -> X 4092 if (N0C && !N0C->isNullValue()) 4093 return N1; 4094 // fold (select false, X, Y) -> Y 4095 if (N0C && N0C->isNullValue()) 4096 return N2; 4097 // fold (select C, 1, X) -> (or C, X) 4098 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4099 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4100 // fold (select C, 0, 1) -> (xor C, 1) 4101 if (VT.isInteger() && 4102 (VT0 == MVT::i1 || 4103 (VT0.isInteger() && 4104 TLI.getBooleanContents(false) == 4105 TargetLowering::ZeroOrOneBooleanContent)) && 4106 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4107 SDValue XORNode; 4108 if (VT == VT0) 4109 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4110 N0, DAG.getConstant(1, VT0)); 4111 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4112 N0, DAG.getConstant(1, VT0)); 4113 AddToWorkList(XORNode.getNode()); 4114 if (VT.bitsGT(VT0)) 4115 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4116 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4117 } 4118 // fold (select C, 0, X) -> (and (not C), X) 4119 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4120 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4121 AddToWorkList(NOTNode.getNode()); 4122 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4123 } 4124 // fold (select C, X, 1) -> (or (not C), X) 4125 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4126 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4127 AddToWorkList(NOTNode.getNode()); 4128 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4129 } 4130 // fold (select C, X, 0) -> (and C, X) 4131 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4132 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4133 // fold (select X, X, Y) -> (or X, Y) 4134 // fold (select X, 1, Y) -> (or X, Y) 4135 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4136 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4137 // fold (select X, Y, X) -> (and X, Y) 4138 // fold (select X, Y, 0) -> (and X, Y) 4139 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4140 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4141 4142 // If we can fold this based on the true/false value, do so. 4143 if (SimplifySelectOps(N, N1, N2)) 4144 return SDValue(N, 0); // Don't revisit N. 4145 4146 // fold selects based on a setcc into other things, such as min/max/abs 4147 if (N0.getOpcode() == ISD::SETCC) { 4148 // FIXME: 4149 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4150 // having to say they don't support SELECT_CC on every type the DAG knows 4151 // about, since there is no way to mark an opcode illegal at all value types 4152 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4153 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4154 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4155 N0.getOperand(0), N0.getOperand(1), 4156 N1, N2, N0.getOperand(2)); 4157 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4158 } 4159 4160 return SDValue(); 4161} 4162 4163SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4164 SDValue N0 = N->getOperand(0); 4165 SDValue N1 = N->getOperand(1); 4166 SDValue N2 = N->getOperand(2); 4167 SDValue N3 = N->getOperand(3); 4168 SDValue N4 = N->getOperand(4); 4169 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4170 4171 // fold select_cc lhs, rhs, x, x, cc -> x 4172 if (N2 == N3) 4173 return N2; 4174 4175 // Determine if the condition we're dealing with is constant 4176 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4177 N0, N1, CC, N->getDebugLoc(), false); 4178 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4179 4180 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4181 if (!SCCC->isNullValue()) 4182 return N2; // cond always true -> true val 4183 else 4184 return N3; // cond always false -> false val 4185 } 4186 4187 // Fold to a simpler select_cc 4188 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4189 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4190 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4191 SCC.getOperand(2)); 4192 4193 // If we can fold this based on the true/false value, do so. 4194 if (SimplifySelectOps(N, N2, N3)) 4195 return SDValue(N, 0); // Don't revisit N. 4196 4197 // fold select_cc into other things, such as min/max/abs 4198 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4199} 4200 4201SDValue DAGCombiner::visitSETCC(SDNode *N) { 4202 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4203 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4204 N->getDebugLoc()); 4205} 4206 4207// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4208// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4209// transformation. Returns true if extension are possible and the above 4210// mentioned transformation is profitable. 4211static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4212 unsigned ExtOpc, 4213 SmallVector<SDNode*, 4> &ExtendNodes, 4214 const TargetLowering &TLI) { 4215 bool HasCopyToRegUses = false; 4216 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4217 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4218 UE = N0.getNode()->use_end(); 4219 UI != UE; ++UI) { 4220 SDNode *User = *UI; 4221 if (User == N) 4222 continue; 4223 if (UI.getUse().getResNo() != N0.getResNo()) 4224 continue; 4225 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4226 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4227 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4228 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4229 // Sign bits will be lost after a zext. 4230 return false; 4231 bool Add = false; 4232 for (unsigned i = 0; i != 2; ++i) { 4233 SDValue UseOp = User->getOperand(i); 4234 if (UseOp == N0) 4235 continue; 4236 if (!isa<ConstantSDNode>(UseOp)) 4237 return false; 4238 Add = true; 4239 } 4240 if (Add) 4241 ExtendNodes.push_back(User); 4242 continue; 4243 } 4244 // If truncates aren't free and there are users we can't 4245 // extend, it isn't worthwhile. 4246 if (!isTruncFree) 4247 return false; 4248 // Remember if this value is live-out. 4249 if (User->getOpcode() == ISD::CopyToReg) 4250 HasCopyToRegUses = true; 4251 } 4252 4253 if (HasCopyToRegUses) { 4254 bool BothLiveOut = false; 4255 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4256 UI != UE; ++UI) { 4257 SDUse &Use = UI.getUse(); 4258 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4259 BothLiveOut = true; 4260 break; 4261 } 4262 } 4263 if (BothLiveOut) 4264 // Both unextended and extended values are live out. There had better be 4265 // a good reason for the transformation. 4266 return ExtendNodes.size(); 4267 } 4268 return true; 4269} 4270 4271void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4272 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4273 ISD::NodeType ExtType) { 4274 // Extend SetCC uses if necessary. 4275 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4276 SDNode *SetCC = SetCCs[i]; 4277 SmallVector<SDValue, 4> Ops; 4278 4279 for (unsigned j = 0; j != 2; ++j) { 4280 SDValue SOp = SetCC->getOperand(j); 4281 if (SOp == Trunc) 4282 Ops.push_back(ExtLoad); 4283 else 4284 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4285 } 4286 4287 Ops.push_back(SetCC->getOperand(2)); 4288 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4289 &Ops[0], Ops.size())); 4290 } 4291} 4292 4293SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4294 SDValue N0 = N->getOperand(0); 4295 EVT VT = N->getValueType(0); 4296 4297 // fold (sext c1) -> c1 4298 if (isa<ConstantSDNode>(N0)) 4299 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4300 4301 // Folding (sext (sext x)) is obvious, but we do it only after the type 4302 // legalization phase. When the sequence is like {(T1->T2), (T2->T3)} and 4303 // T1 or T3 (or the both) are illegal types, the TypeLegalizer may not 4304 // give a good sequence for the (T1->T3) pair. 4305 // So we give a chance to target specific combiner to optimize T1->T2 and T2->T3 4306 // separately and may be fold them in a preceding of subsequent instruction. 4307 if (Level >= AfterLegalizeTypes) { 4308 // fold (sext (sext x)) -> (sext x) 4309 // fold (sext (aext x)) -> (sext x) 4310 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4311 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4312 N0.getOperand(0)); 4313 } 4314 4315 if (N0.getOpcode() == ISD::TRUNCATE) { 4316 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4317 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4318 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4319 if (NarrowLoad.getNode()) { 4320 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4321 if (NarrowLoad.getNode() != N0.getNode()) { 4322 CombineTo(N0.getNode(), NarrowLoad); 4323 // CombineTo deleted the truncate, if needed, but not what's under it. 4324 AddToWorkList(oye); 4325 } 4326 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4327 } 4328 4329 // See if the value being truncated is already sign extended. If so, just 4330 // eliminate the trunc/sext pair. 4331 SDValue Op = N0.getOperand(0); 4332 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4333 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4334 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4335 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4336 4337 if (OpBits == DestBits) { 4338 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4339 // bits, it is already ready. 4340 if (NumSignBits > DestBits-MidBits) 4341 return Op; 4342 } else if (OpBits < DestBits) { 4343 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4344 // bits, just sext from i32. 4345 if (NumSignBits > OpBits-MidBits) 4346 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4347 } else { 4348 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4349 // bits, just truncate to i32. 4350 if (NumSignBits > OpBits-MidBits) 4351 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4352 } 4353 4354 // fold (sext (truncate x)) -> (sextinreg x). 4355 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4356 N0.getValueType())) { 4357 if (OpBits < DestBits) 4358 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4359 else if (OpBits > DestBits) 4360 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4361 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4362 DAG.getValueType(N0.getValueType())); 4363 } 4364 } 4365 4366 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4367 // None of the supported targets knows how to perform load and sign extend 4368 // on vectors in one instruction. We only perform this transformation on 4369 // scalars. 4370 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4371 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4372 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4373 bool DoXform = true; 4374 SmallVector<SDNode*, 4> SetCCs; 4375 if (!N0.hasOneUse()) 4376 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4377 if (DoXform) { 4378 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4379 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4380 LN0->getChain(), 4381 LN0->getBasePtr(), LN0->getPointerInfo(), 4382 N0.getValueType(), 4383 LN0->isVolatile(), LN0->isNonTemporal(), 4384 LN0->getAlignment()); 4385 CombineTo(N, ExtLoad); 4386 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4387 N0.getValueType(), ExtLoad); 4388 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4389 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4390 ISD::SIGN_EXTEND); 4391 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4392 } 4393 } 4394 4395 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4396 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4397 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4398 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4399 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4400 EVT MemVT = LN0->getMemoryVT(); 4401 if ((!LegalOperations && !LN0->isVolatile()) || 4402 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4403 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4404 LN0->getChain(), 4405 LN0->getBasePtr(), LN0->getPointerInfo(), 4406 MemVT, 4407 LN0->isVolatile(), LN0->isNonTemporal(), 4408 LN0->getAlignment()); 4409 CombineTo(N, ExtLoad); 4410 CombineTo(N0.getNode(), 4411 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4412 N0.getValueType(), ExtLoad), 4413 ExtLoad.getValue(1)); 4414 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4415 } 4416 } 4417 4418 // fold (sext (and/or/xor (load x), cst)) -> 4419 // (and/or/xor (sextload x), (sext cst)) 4420 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4421 N0.getOpcode() == ISD::XOR) && 4422 isa<LoadSDNode>(N0.getOperand(0)) && 4423 N0.getOperand(1).getOpcode() == ISD::Constant && 4424 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4425 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4426 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4427 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4428 bool DoXform = true; 4429 SmallVector<SDNode*, 4> SetCCs; 4430 if (!N0.hasOneUse()) 4431 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4432 SetCCs, TLI); 4433 if (DoXform) { 4434 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4435 LN0->getChain(), LN0->getBasePtr(), 4436 LN0->getPointerInfo(), 4437 LN0->getMemoryVT(), 4438 LN0->isVolatile(), 4439 LN0->isNonTemporal(), 4440 LN0->getAlignment()); 4441 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4442 Mask = Mask.sext(VT.getSizeInBits()); 4443 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4444 ExtLoad, DAG.getConstant(Mask, VT)); 4445 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4446 N0.getOperand(0).getDebugLoc(), 4447 N0.getOperand(0).getValueType(), ExtLoad); 4448 CombineTo(N, And); 4449 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4450 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4451 ISD::SIGN_EXTEND); 4452 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4453 } 4454 } 4455 } 4456 4457 if (N0.getOpcode() == ISD::SETCC) { 4458 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4459 // Only do this before legalize for now. 4460 if (VT.isVector() && !LegalOperations) { 4461 EVT N0VT = N0.getOperand(0).getValueType(); 4462 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4463 // of the same size as the compared operands. Only optimize sext(setcc()) 4464 // if this is the case. 4465 EVT SVT = TLI.getSetCCResultType(N0VT); 4466 4467 // We know that the # elements of the results is the same as the 4468 // # elements of the compare (and the # elements of the compare result 4469 // for that matter). Check to see that they are the same size. If so, 4470 // we know that the element size of the sext'd result matches the 4471 // element size of the compare operands. 4472 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4473 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4474 N0.getOperand(1), 4475 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4476 // If the desired elements are smaller or larger than the source 4477 // elements we can use a matching integer vector type and then 4478 // truncate/sign extend 4479 EVT MatchingElementType = 4480 EVT::getIntegerVT(*DAG.getContext(), 4481 N0VT.getScalarType().getSizeInBits()); 4482 EVT MatchingVectorType = 4483 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4484 N0VT.getVectorNumElements()); 4485 4486 if (SVT == MatchingVectorType) { 4487 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4488 N0.getOperand(0), N0.getOperand(1), 4489 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4490 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4491 } 4492 } 4493 4494 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4495 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4496 SDValue NegOne = 4497 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4498 SDValue SCC = 4499 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4500 NegOne, DAG.getConstant(0, VT), 4501 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4502 if (SCC.getNode()) return SCC; 4503 if (!LegalOperations || 4504 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4505 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4506 DAG.getSetCC(N->getDebugLoc(), 4507 TLI.getSetCCResultType(VT), 4508 N0.getOperand(0), N0.getOperand(1), 4509 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4510 NegOne, DAG.getConstant(0, VT)); 4511 } 4512 4513 // fold (sext x) -> (zext x) if the sign bit is known zero. 4514 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4515 DAG.SignBitIsZero(N0)) 4516 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4517 4518 return SDValue(); 4519} 4520 4521// isTruncateOf - If N is a truncate of some other value, return true, record 4522// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4523// This function computes KnownZero to avoid a duplicated call to 4524// ComputeMaskedBits in the caller. 4525static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4526 APInt &KnownZero) { 4527 APInt KnownOne; 4528 if (N->getOpcode() == ISD::TRUNCATE) { 4529 Op = N->getOperand(0); 4530 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4531 return true; 4532 } 4533 4534 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4535 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4536 return false; 4537 4538 SDValue Op0 = N->getOperand(0); 4539 SDValue Op1 = N->getOperand(1); 4540 assert(Op0.getValueType() == Op1.getValueType()); 4541 4542 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4543 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4544 if (COp0 && COp0->isNullValue()) 4545 Op = Op1; 4546 else if (COp1 && COp1->isNullValue()) 4547 Op = Op0; 4548 else 4549 return false; 4550 4551 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4552 4553 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4554 return false; 4555 4556 return true; 4557} 4558 4559SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4560 SDValue N0 = N->getOperand(0); 4561 EVT VT = N->getValueType(0); 4562 4563 // fold (zext c1) -> c1 4564 if (isa<ConstantSDNode>(N0)) 4565 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4566 // fold (zext (zext x)) -> (zext x) 4567 // fold (zext (aext x)) -> (zext x) 4568 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4569 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4570 N0.getOperand(0)); 4571 4572 // fold (zext (truncate x)) -> (zext x) or 4573 // (zext (truncate x)) -> (truncate x) 4574 // This is valid when the truncated bits of x are already zero. 4575 // FIXME: We should extend this to work for vectors too. 4576 SDValue Op; 4577 APInt KnownZero; 4578 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4579 APInt TruncatedBits = 4580 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4581 APInt(Op.getValueSizeInBits(), 0) : 4582 APInt::getBitsSet(Op.getValueSizeInBits(), 4583 N0.getValueSizeInBits(), 4584 std::min(Op.getValueSizeInBits(), 4585 VT.getSizeInBits())); 4586 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4587 if (VT.bitsGT(Op.getValueType())) 4588 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4589 if (VT.bitsLT(Op.getValueType())) 4590 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4591 4592 return Op; 4593 } 4594 } 4595 4596 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4597 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4598 if (N0.getOpcode() == ISD::TRUNCATE) { 4599 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4600 if (NarrowLoad.getNode()) { 4601 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4602 if (NarrowLoad.getNode() != N0.getNode()) { 4603 CombineTo(N0.getNode(), NarrowLoad); 4604 // CombineTo deleted the truncate, if needed, but not what's under it. 4605 AddToWorkList(oye); 4606 } 4607 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4608 } 4609 } 4610 4611 // fold (zext (truncate x)) -> (and x, mask) 4612 if (N0.getOpcode() == ISD::TRUNCATE && 4613 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4614 4615 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4616 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4617 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4618 if (NarrowLoad.getNode()) { 4619 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4620 if (NarrowLoad.getNode() != N0.getNode()) { 4621 CombineTo(N0.getNode(), NarrowLoad); 4622 // CombineTo deleted the truncate, if needed, but not what's under it. 4623 AddToWorkList(oye); 4624 } 4625 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4626 } 4627 4628 SDValue Op = N0.getOperand(0); 4629 if (Op.getValueType().bitsLT(VT)) { 4630 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4631 AddToWorkList(Op.getNode()); 4632 } else if (Op.getValueType().bitsGT(VT)) { 4633 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4634 AddToWorkList(Op.getNode()); 4635 } 4636 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4637 N0.getValueType().getScalarType()); 4638 } 4639 4640 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4641 // if either of the casts is not free. 4642 if (N0.getOpcode() == ISD::AND && 4643 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4644 N0.getOperand(1).getOpcode() == ISD::Constant && 4645 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4646 N0.getValueType()) || 4647 !TLI.isZExtFree(N0.getValueType(), VT))) { 4648 SDValue X = N0.getOperand(0).getOperand(0); 4649 if (X.getValueType().bitsLT(VT)) { 4650 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4651 } else if (X.getValueType().bitsGT(VT)) { 4652 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4653 } 4654 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4655 Mask = Mask.zext(VT.getSizeInBits()); 4656 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4657 X, DAG.getConstant(Mask, VT)); 4658 } 4659 4660 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4661 // None of the supported targets knows how to perform load and vector_zext 4662 // on vectors in one instruction. We only perform this transformation on 4663 // scalars. 4664 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4665 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4666 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4667 bool DoXform = true; 4668 SmallVector<SDNode*, 4> SetCCs; 4669 if (!N0.hasOneUse()) 4670 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4671 if (DoXform) { 4672 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4673 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4674 LN0->getChain(), 4675 LN0->getBasePtr(), LN0->getPointerInfo(), 4676 N0.getValueType(), 4677 LN0->isVolatile(), LN0->isNonTemporal(), 4678 LN0->getAlignment()); 4679 CombineTo(N, ExtLoad); 4680 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4681 N0.getValueType(), ExtLoad); 4682 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4683 4684 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4685 ISD::ZERO_EXTEND); 4686 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4687 } 4688 } 4689 4690 // fold (zext (and/or/xor (load x), cst)) -> 4691 // (and/or/xor (zextload x), (zext cst)) 4692 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4693 N0.getOpcode() == ISD::XOR) && 4694 isa<LoadSDNode>(N0.getOperand(0)) && 4695 N0.getOperand(1).getOpcode() == ISD::Constant && 4696 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4697 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4698 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4699 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4700 bool DoXform = true; 4701 SmallVector<SDNode*, 4> SetCCs; 4702 if (!N0.hasOneUse()) 4703 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4704 SetCCs, TLI); 4705 if (DoXform) { 4706 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4707 LN0->getChain(), LN0->getBasePtr(), 4708 LN0->getPointerInfo(), 4709 LN0->getMemoryVT(), 4710 LN0->isVolatile(), 4711 LN0->isNonTemporal(), 4712 LN0->getAlignment()); 4713 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4714 Mask = Mask.zext(VT.getSizeInBits()); 4715 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4716 ExtLoad, DAG.getConstant(Mask, VT)); 4717 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4718 N0.getOperand(0).getDebugLoc(), 4719 N0.getOperand(0).getValueType(), ExtLoad); 4720 CombineTo(N, And); 4721 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4722 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4723 ISD::ZERO_EXTEND); 4724 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4725 } 4726 } 4727 } 4728 4729 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4730 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4731 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4732 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4733 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4734 EVT MemVT = LN0->getMemoryVT(); 4735 if ((!LegalOperations && !LN0->isVolatile()) || 4736 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4737 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4738 LN0->getChain(), 4739 LN0->getBasePtr(), LN0->getPointerInfo(), 4740 MemVT, 4741 LN0->isVolatile(), LN0->isNonTemporal(), 4742 LN0->getAlignment()); 4743 CombineTo(N, ExtLoad); 4744 CombineTo(N0.getNode(), 4745 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4746 ExtLoad), 4747 ExtLoad.getValue(1)); 4748 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4749 } 4750 } 4751 4752 if (N0.getOpcode() == ISD::SETCC) { 4753 if (!LegalOperations && VT.isVector()) { 4754 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4755 // Only do this before legalize for now. 4756 EVT N0VT = N0.getOperand(0).getValueType(); 4757 EVT EltVT = VT.getVectorElementType(); 4758 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4759 DAG.getConstant(1, EltVT)); 4760 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4761 // We know that the # elements of the results is the same as the 4762 // # elements of the compare (and the # elements of the compare result 4763 // for that matter). Check to see that they are the same size. If so, 4764 // we know that the element size of the sext'd result matches the 4765 // element size of the compare operands. 4766 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4767 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4768 N0.getOperand(1), 4769 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4770 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4771 &OneOps[0], OneOps.size())); 4772 4773 // If the desired elements are smaller or larger than the source 4774 // elements we can use a matching integer vector type and then 4775 // truncate/sign extend 4776 EVT MatchingElementType = 4777 EVT::getIntegerVT(*DAG.getContext(), 4778 N0VT.getScalarType().getSizeInBits()); 4779 EVT MatchingVectorType = 4780 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4781 N0VT.getVectorNumElements()); 4782 SDValue VsetCC = 4783 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4784 N0.getOperand(1), 4785 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4786 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4787 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4788 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4789 &OneOps[0], OneOps.size())); 4790 } 4791 4792 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4793 SDValue SCC = 4794 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4795 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4796 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4797 if (SCC.getNode()) return SCC; 4798 } 4799 4800 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4801 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4802 isa<ConstantSDNode>(N0.getOperand(1)) && 4803 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4804 N0.hasOneUse()) { 4805 SDValue ShAmt = N0.getOperand(1); 4806 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4807 if (N0.getOpcode() == ISD::SHL) { 4808 SDValue InnerZExt = N0.getOperand(0); 4809 // If the original shl may be shifting out bits, do not perform this 4810 // transformation. 4811 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4812 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4813 if (ShAmtVal > KnownZeroBits) 4814 return SDValue(); 4815 } 4816 4817 DebugLoc DL = N->getDebugLoc(); 4818 4819 // Ensure that the shift amount is wide enough for the shifted value. 4820 if (VT.getSizeInBits() >= 256) 4821 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4822 4823 return DAG.getNode(N0.getOpcode(), DL, VT, 4824 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4825 ShAmt); 4826 } 4827 4828 return SDValue(); 4829} 4830 4831SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4832 SDValue N0 = N->getOperand(0); 4833 EVT VT = N->getValueType(0); 4834 4835 // fold (aext c1) -> c1 4836 if (isa<ConstantSDNode>(N0)) 4837 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4838 // fold (aext (aext x)) -> (aext x) 4839 // fold (aext (zext x)) -> (zext x) 4840 // fold (aext (sext x)) -> (sext x) 4841 if (N0.getOpcode() == ISD::ANY_EXTEND || 4842 N0.getOpcode() == ISD::ZERO_EXTEND || 4843 N0.getOpcode() == ISD::SIGN_EXTEND) 4844 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4845 4846 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4847 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4848 if (N0.getOpcode() == ISD::TRUNCATE) { 4849 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4850 if (NarrowLoad.getNode()) { 4851 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4852 if (NarrowLoad.getNode() != N0.getNode()) { 4853 CombineTo(N0.getNode(), NarrowLoad); 4854 // CombineTo deleted the truncate, if needed, but not what's under it. 4855 AddToWorkList(oye); 4856 } 4857 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4858 } 4859 } 4860 4861 // fold (aext (truncate x)) 4862 if (N0.getOpcode() == ISD::TRUNCATE) { 4863 SDValue TruncOp = N0.getOperand(0); 4864 if (TruncOp.getValueType() == VT) 4865 return TruncOp; // x iff x size == zext size. 4866 if (TruncOp.getValueType().bitsGT(VT)) 4867 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4868 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4869 } 4870 4871 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4872 // if the trunc is not free. 4873 if (N0.getOpcode() == ISD::AND && 4874 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4875 N0.getOperand(1).getOpcode() == ISD::Constant && 4876 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4877 N0.getValueType())) { 4878 SDValue X = N0.getOperand(0).getOperand(0); 4879 if (X.getValueType().bitsLT(VT)) { 4880 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4881 } else if (X.getValueType().bitsGT(VT)) { 4882 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4883 } 4884 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4885 Mask = Mask.zext(VT.getSizeInBits()); 4886 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4887 X, DAG.getConstant(Mask, VT)); 4888 } 4889 4890 // fold (aext (load x)) -> (aext (truncate (extload x))) 4891 // None of the supported targets knows how to perform load and any_ext 4892 // on vectors in one instruction. We only perform this transformation on 4893 // scalars. 4894 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4895 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4896 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4897 bool DoXform = true; 4898 SmallVector<SDNode*, 4> SetCCs; 4899 if (!N0.hasOneUse()) 4900 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4901 if (DoXform) { 4902 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4903 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4904 LN0->getChain(), 4905 LN0->getBasePtr(), LN0->getPointerInfo(), 4906 N0.getValueType(), 4907 LN0->isVolatile(), LN0->isNonTemporal(), 4908 LN0->getAlignment()); 4909 CombineTo(N, ExtLoad); 4910 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4911 N0.getValueType(), ExtLoad); 4912 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4913 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4914 ISD::ANY_EXTEND); 4915 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4916 } 4917 } 4918 4919 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4920 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4921 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4922 if (N0.getOpcode() == ISD::LOAD && 4923 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4924 N0.hasOneUse()) { 4925 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4926 EVT MemVT = LN0->getMemoryVT(); 4927 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4928 VT, LN0->getChain(), LN0->getBasePtr(), 4929 LN0->getPointerInfo(), MemVT, 4930 LN0->isVolatile(), LN0->isNonTemporal(), 4931 LN0->getAlignment()); 4932 CombineTo(N, ExtLoad); 4933 CombineTo(N0.getNode(), 4934 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4935 N0.getValueType(), ExtLoad), 4936 ExtLoad.getValue(1)); 4937 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4938 } 4939 4940 if (N0.getOpcode() == ISD::SETCC) { 4941 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4942 // Only do this before legalize for now. 4943 if (VT.isVector() && !LegalOperations) { 4944 EVT N0VT = N0.getOperand(0).getValueType(); 4945 // We know that the # elements of the results is the same as the 4946 // # elements of the compare (and the # elements of the compare result 4947 // for that matter). Check to see that they are the same size. If so, 4948 // we know that the element size of the sext'd result matches the 4949 // element size of the compare operands. 4950 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4951 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4952 N0.getOperand(1), 4953 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4954 // If the desired elements are smaller or larger than the source 4955 // elements we can use a matching integer vector type and then 4956 // truncate/sign extend 4957 else { 4958 EVT MatchingElementType = 4959 EVT::getIntegerVT(*DAG.getContext(), 4960 N0VT.getScalarType().getSizeInBits()); 4961 EVT MatchingVectorType = 4962 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4963 N0VT.getVectorNumElements()); 4964 SDValue VsetCC = 4965 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4966 N0.getOperand(1), 4967 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4968 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4969 } 4970 } 4971 4972 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4973 SDValue SCC = 4974 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4975 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4976 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4977 if (SCC.getNode()) 4978 return SCC; 4979 } 4980 4981 return SDValue(); 4982} 4983 4984/// GetDemandedBits - See if the specified operand can be simplified with the 4985/// knowledge that only the bits specified by Mask are used. If so, return the 4986/// simpler operand, otherwise return a null SDValue. 4987SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4988 switch (V.getOpcode()) { 4989 default: break; 4990 case ISD::Constant: { 4991 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4992 assert(CV != 0 && "Const value should be ConstSDNode."); 4993 const APInt &CVal = CV->getAPIntValue(); 4994 APInt NewVal = CVal & Mask; 4995 if (NewVal != CVal) { 4996 return DAG.getConstant(NewVal, V.getValueType()); 4997 } 4998 break; 4999 } 5000 case ISD::OR: 5001 case ISD::XOR: 5002 // If the LHS or RHS don't contribute bits to the or, drop them. 5003 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 5004 return V.getOperand(1); 5005 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 5006 return V.getOperand(0); 5007 break; 5008 case ISD::SRL: 5009 // Only look at single-use SRLs. 5010 if (!V.getNode()->hasOneUse()) 5011 break; 5012 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 5013 // See if we can recursively simplify the LHS. 5014 unsigned Amt = RHSC->getZExtValue(); 5015 5016 // Watch out for shift count overflow though. 5017 if (Amt >= Mask.getBitWidth()) break; 5018 APInt NewMask = Mask << Amt; 5019 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 5020 if (SimplifyLHS.getNode()) 5021 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 5022 SimplifyLHS, V.getOperand(1)); 5023 } 5024 } 5025 return SDValue(); 5026} 5027 5028/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 5029/// bits and then truncated to a narrower type and where N is a multiple 5030/// of number of bits of the narrower type, transform it to a narrower load 5031/// from address + N / num of bits of new type. If the result is to be 5032/// extended, also fold the extension to form a extending load. 5033SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 5034 unsigned Opc = N->getOpcode(); 5035 5036 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 5037 SDValue N0 = N->getOperand(0); 5038 EVT VT = N->getValueType(0); 5039 EVT ExtVT = VT; 5040 5041 // This transformation isn't valid for vector loads. 5042 if (VT.isVector()) 5043 return SDValue(); 5044 5045 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 5046 // extended to VT. 5047 if (Opc == ISD::SIGN_EXTEND_INREG) { 5048 ExtType = ISD::SEXTLOAD; 5049 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5050 } else if (Opc == ISD::SRL) { 5051 // Another special-case: SRL is basically zero-extending a narrower value. 5052 ExtType = ISD::ZEXTLOAD; 5053 N0 = SDValue(N, 0); 5054 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 5055 if (!N01) return SDValue(); 5056 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 5057 VT.getSizeInBits() - N01->getZExtValue()); 5058 } 5059 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5060 return SDValue(); 5061 5062 unsigned EVTBits = ExtVT.getSizeInBits(); 5063 5064 // Do not generate loads of non-round integer types since these can 5065 // be expensive (and would be wrong if the type is not byte sized). 5066 if (!ExtVT.isRound()) 5067 return SDValue(); 5068 5069 unsigned ShAmt = 0; 5070 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5071 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5072 ShAmt = N01->getZExtValue(); 5073 // Is the shift amount a multiple of size of VT? 5074 if ((ShAmt & (EVTBits-1)) == 0) { 5075 N0 = N0.getOperand(0); 5076 // Is the load width a multiple of size of VT? 5077 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5078 return SDValue(); 5079 } 5080 5081 // At this point, we must have a load or else we can't do the transform. 5082 if (!isa<LoadSDNode>(N0)) return SDValue(); 5083 5084 // Because a SRL must be assumed to *need* to zero-extend the high bits 5085 // (as opposed to anyext the high bits), we can't combine the zextload 5086 // lowering of SRL and an sextload. 5087 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD) 5088 return SDValue(); 5089 5090 // If the shift amount is larger than the input type then we're not 5091 // accessing any of the loaded bytes. If the load was a zextload/extload 5092 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5093 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5094 return SDValue(); 5095 } 5096 } 5097 5098 // If the load is shifted left (and the result isn't shifted back right), 5099 // we can fold the truncate through the shift. 5100 unsigned ShLeftAmt = 0; 5101 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5102 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5103 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5104 ShLeftAmt = N01->getZExtValue(); 5105 N0 = N0.getOperand(0); 5106 } 5107 } 5108 5109 // If we haven't found a load, we can't narrow it. Don't transform one with 5110 // multiple uses, this would require adding a new load. 5111 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse()) 5112 return SDValue(); 5113 5114 // Don't change the width of a volatile load. 5115 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5116 if (LN0->isVolatile()) 5117 return SDValue(); 5118 5119 // Verify that we are actually reducing a load width here. 5120 if (LN0->getMemoryVT().getSizeInBits() < EVTBits) 5121 return SDValue(); 5122 5123 // For the transform to be legal, the load must produce only two values 5124 // (the value loaded and the chain). Don't transform a pre-increment 5125 // load, for example, which produces an extra value. Otherwise the 5126 // transformation is not equivalent, and the downstream logic to replace 5127 // uses gets things wrong. 5128 if (LN0->getNumValues() > 2) 5129 return SDValue(); 5130 5131 EVT PtrType = N0.getOperand(1).getValueType(); 5132 5133 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5134 // It's not possible to generate a constant of extended or untyped type. 5135 return SDValue(); 5136 5137 // For big endian targets, we need to adjust the offset to the pointer to 5138 // load the correct bytes. 5139 if (TLI.isBigEndian()) { 5140 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5141 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5142 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5143 } 5144 5145 uint64_t PtrOff = ShAmt / 8; 5146 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5147 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5148 PtrType, LN0->getBasePtr(), 5149 DAG.getConstant(PtrOff, PtrType)); 5150 AddToWorkList(NewPtr.getNode()); 5151 5152 SDValue Load; 5153 if (ExtType == ISD::NON_EXTLOAD) 5154 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5155 LN0->getPointerInfo().getWithOffset(PtrOff), 5156 LN0->isVolatile(), LN0->isNonTemporal(), 5157 LN0->isInvariant(), NewAlign); 5158 else 5159 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5160 LN0->getPointerInfo().getWithOffset(PtrOff), 5161 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5162 NewAlign); 5163 5164 // Replace the old load's chain with the new load's chain. 5165 WorkListRemover DeadNodes(*this); 5166 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5167 5168 // Shift the result left, if we've swallowed a left shift. 5169 SDValue Result = Load; 5170 if (ShLeftAmt != 0) { 5171 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5172 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5173 ShImmTy = VT; 5174 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5175 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5176 } 5177 5178 // Return the new loaded value. 5179 return Result; 5180} 5181 5182SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5183 SDValue N0 = N->getOperand(0); 5184 SDValue N1 = N->getOperand(1); 5185 EVT VT = N->getValueType(0); 5186 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5187 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5188 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5189 5190 // fold (sext_in_reg c1) -> c1 5191 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5192 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5193 5194 // If the input is already sign extended, just drop the extension. 5195 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5196 return N0; 5197 5198 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5199 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5200 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5201 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5202 N0.getOperand(0), N1); 5203 } 5204 5205 // fold (sext_in_reg (sext x)) -> (sext x) 5206 // fold (sext_in_reg (aext x)) -> (sext x) 5207 // if x is small enough. 5208 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5209 SDValue N00 = N0.getOperand(0); 5210 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5211 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5212 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5213 } 5214 5215 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5216 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5217 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5218 5219 // fold operands of sext_in_reg based on knowledge that the top bits are not 5220 // demanded. 5221 if (SimplifyDemandedBits(SDValue(N, 0))) 5222 return SDValue(N, 0); 5223 5224 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5225 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5226 SDValue NarrowLoad = ReduceLoadWidth(N); 5227 if (NarrowLoad.getNode()) 5228 return NarrowLoad; 5229 5230 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5231 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5232 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5233 if (N0.getOpcode() == ISD::SRL) { 5234 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5235 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5236 // We can turn this into an SRA iff the input to the SRL is already sign 5237 // extended enough. 5238 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5239 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5240 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5241 N0.getOperand(0), N0.getOperand(1)); 5242 } 5243 } 5244 5245 // fold (sext_inreg (extload x)) -> (sextload x) 5246 if (ISD::isEXTLoad(N0.getNode()) && 5247 ISD::isUNINDEXEDLoad(N0.getNode()) && 5248 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5249 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5250 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5251 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5252 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5253 LN0->getChain(), 5254 LN0->getBasePtr(), LN0->getPointerInfo(), 5255 EVT, 5256 LN0->isVolatile(), LN0->isNonTemporal(), 5257 LN0->getAlignment()); 5258 CombineTo(N, ExtLoad); 5259 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5260 AddToWorkList(ExtLoad.getNode()); 5261 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5262 } 5263 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5264 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5265 N0.hasOneUse() && 5266 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5267 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5268 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5269 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5270 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5271 LN0->getChain(), 5272 LN0->getBasePtr(), LN0->getPointerInfo(), 5273 EVT, 5274 LN0->isVolatile(), LN0->isNonTemporal(), 5275 LN0->getAlignment()); 5276 CombineTo(N, ExtLoad); 5277 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5278 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5279 } 5280 5281 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5282 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5283 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5284 N0.getOperand(1), false); 5285 if (BSwap.getNode() != 0) 5286 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5287 BSwap, N1); 5288 } 5289 5290 return SDValue(); 5291} 5292 5293SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5294 SDValue N0 = N->getOperand(0); 5295 EVT VT = N->getValueType(0); 5296 bool isLE = TLI.isLittleEndian(); 5297 5298 // noop truncate 5299 if (N0.getValueType() == N->getValueType(0)) 5300 return N0; 5301 // fold (truncate c1) -> c1 5302 if (isa<ConstantSDNode>(N0)) 5303 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5304 // fold (truncate (truncate x)) -> (truncate x) 5305 if (N0.getOpcode() == ISD::TRUNCATE) 5306 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5307 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5308 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5309 N0.getOpcode() == ISD::SIGN_EXTEND || 5310 N0.getOpcode() == ISD::ANY_EXTEND) { 5311 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5312 // if the source is smaller than the dest, we still need an extend 5313 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5314 N0.getOperand(0)); 5315 if (N0.getOperand(0).getValueType().bitsGT(VT)) 5316 // if the source is larger than the dest, than we just need the truncate 5317 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5318 // if the source and dest are the same type, we can drop both the extend 5319 // and the truncate. 5320 return N0.getOperand(0); 5321 } 5322 5323 // Fold extract-and-trunc into a narrow extract. For example: 5324 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5325 // i32 y = TRUNCATE(i64 x) 5326 // -- becomes -- 5327 // v16i8 b = BITCAST (v2i64 val) 5328 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5329 // 5330 // Note: We only run this optimization after type legalization (which often 5331 // creates this pattern) and before operation legalization after which 5332 // we need to be more careful about the vector instructions that we generate. 5333 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5334 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5335 5336 EVT VecTy = N0.getOperand(0).getValueType(); 5337 EVT ExTy = N0.getValueType(); 5338 EVT TrTy = N->getValueType(0); 5339 5340 unsigned NumElem = VecTy.getVectorNumElements(); 5341 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5342 5343 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5344 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5345 5346 SDValue EltNo = N0->getOperand(1); 5347 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5348 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5349 EVT IndexTy = N0->getOperand(1).getValueType(); 5350 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5351 5352 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5353 NVT, N0.getOperand(0)); 5354 5355 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5356 N->getDebugLoc(), TrTy, V, 5357 DAG.getConstant(Index, IndexTy)); 5358 } 5359 } 5360 5361 // See if we can simplify the input to this truncate through knowledge that 5362 // only the low bits are being used. 5363 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5364 // Currently we only perform this optimization on scalars because vectors 5365 // may have different active low bits. 5366 if (!VT.isVector()) { 5367 SDValue Shorter = 5368 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5369 VT.getSizeInBits())); 5370 if (Shorter.getNode()) 5371 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5372 } 5373 // fold (truncate (load x)) -> (smaller load x) 5374 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5375 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5376 SDValue Reduced = ReduceLoadWidth(N); 5377 if (Reduced.getNode()) 5378 return Reduced; 5379 } 5380 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)), 5381 // where ... are all 'undef'. 5382 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { 5383 SmallVector<EVT, 8> VTs; 5384 SDValue V; 5385 unsigned Idx = 0; 5386 unsigned NumDefs = 0; 5387 5388 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 5389 SDValue X = N0.getOperand(i); 5390 if (X.getOpcode() != ISD::UNDEF) { 5391 V = X; 5392 Idx = i; 5393 NumDefs++; 5394 } 5395 // Stop if more than one members are non-undef. 5396 if (NumDefs > 1) 5397 break; 5398 VTs.push_back(EVT::getVectorVT(*DAG.getContext(), 5399 VT.getVectorElementType(), 5400 X.getValueType().getVectorNumElements())); 5401 } 5402 5403 if (NumDefs == 0) 5404 return DAG.getUNDEF(VT); 5405 5406 if (NumDefs == 1) { 5407 assert(V.getNode() && "The single defined operand is empty!"); 5408 SmallVector<SDValue, 8> Opnds; 5409 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 5410 if (i != Idx) { 5411 Opnds.push_back(DAG.getUNDEF(VTs[i])); 5412 continue; 5413 } 5414 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V); 5415 AddToWorkList(NV.getNode()); 5416 Opnds.push_back(NV); 5417 } 5418 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 5419 &Opnds[0], Opnds.size()); 5420 } 5421 } 5422 5423 // Simplify the operands using demanded-bits information. 5424 if (!VT.isVector() && 5425 SimplifyDemandedBits(SDValue(N, 0))) 5426 return SDValue(N, 0); 5427 5428 return SDValue(); 5429} 5430 5431static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5432 SDValue Elt = N->getOperand(i); 5433 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5434 return Elt.getNode(); 5435 return Elt.getOperand(Elt.getResNo()).getNode(); 5436} 5437 5438/// CombineConsecutiveLoads - build_pair (load, load) -> load 5439/// if load locations are consecutive. 5440SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5441 assert(N->getOpcode() == ISD::BUILD_PAIR); 5442 5443 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5444 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5445 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5446 LD1->getPointerInfo().getAddrSpace() != 5447 LD2->getPointerInfo().getAddrSpace()) 5448 return SDValue(); 5449 EVT LD1VT = LD1->getValueType(0); 5450 5451 if (ISD::isNON_EXTLoad(LD2) && 5452 LD2->hasOneUse() && 5453 // If both are volatile this would reduce the number of volatile loads. 5454 // If one is volatile it might be ok, but play conservative and bail out. 5455 !LD1->isVolatile() && 5456 !LD2->isVolatile() && 5457 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5458 unsigned Align = LD1->getAlignment(); 5459 unsigned NewAlign = TLI.getDataLayout()-> 5460 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5461 5462 if (NewAlign <= Align && 5463 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5464 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5465 LD1->getBasePtr(), LD1->getPointerInfo(), 5466 false, false, false, Align); 5467 } 5468 5469 return SDValue(); 5470} 5471 5472SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5473 SDValue N0 = N->getOperand(0); 5474 EVT VT = N->getValueType(0); 5475 5476 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5477 // Only do this before legalize, since afterward the target may be depending 5478 // on the bitconvert. 5479 // First check to see if this is all constant. 5480 if (!LegalTypes && 5481 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5482 VT.isVector()) { 5483 bool isSimple = true; 5484 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5485 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5486 N0.getOperand(i).getOpcode() != ISD::Constant && 5487 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5488 isSimple = false; 5489 break; 5490 } 5491 5492 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5493 assert(!DestEltVT.isVector() && 5494 "Element type of vector ValueType must not be vector!"); 5495 if (isSimple) 5496 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5497 } 5498 5499 // If the input is a constant, let getNode fold it. 5500 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5501 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5502 if (Res.getNode() != N) { 5503 if (!LegalOperations || 5504 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5505 return Res; 5506 5507 // Folding it resulted in an illegal node, and it's too late to 5508 // do that. Clean up the old node and forego the transformation. 5509 // Ideally this won't happen very often, because instcombine 5510 // and the earlier dagcombine runs (where illegal nodes are 5511 // permitted) should have folded most of them already. 5512 DAG.DeleteNode(Res.getNode()); 5513 } 5514 } 5515 5516 // (conv (conv x, t1), t2) -> (conv x, t2) 5517 if (N0.getOpcode() == ISD::BITCAST) 5518 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5519 N0.getOperand(0)); 5520 5521 // fold (conv (load x)) -> (load (conv*)x) 5522 // If the resultant load doesn't need a higher alignment than the original! 5523 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5524 // Do not change the width of a volatile load. 5525 !cast<LoadSDNode>(N0)->isVolatile() && 5526 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5527 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5528 unsigned Align = TLI.getDataLayout()-> 5529 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5530 unsigned OrigAlign = LN0->getAlignment(); 5531 5532 if (Align <= OrigAlign) { 5533 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5534 LN0->getBasePtr(), LN0->getPointerInfo(), 5535 LN0->isVolatile(), LN0->isNonTemporal(), 5536 LN0->isInvariant(), OrigAlign); 5537 AddToWorkList(N); 5538 CombineTo(N0.getNode(), 5539 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5540 N0.getValueType(), Load), 5541 Load.getValue(1)); 5542 return Load; 5543 } 5544 } 5545 5546 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5547 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5548 // This often reduces constant pool loads. 5549 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5550 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5551 N0.getNode()->hasOneUse() && VT.isInteger() && 5552 !VT.isVector() && !N0.getValueType().isVector()) { 5553 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5554 N0.getOperand(0)); 5555 AddToWorkList(NewConv.getNode()); 5556 5557 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5558 if (N0.getOpcode() == ISD::FNEG) 5559 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5560 NewConv, DAG.getConstant(SignBit, VT)); 5561 assert(N0.getOpcode() == ISD::FABS); 5562 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5563 NewConv, DAG.getConstant(~SignBit, VT)); 5564 } 5565 5566 // fold (bitconvert (fcopysign cst, x)) -> 5567 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5568 // Note that we don't handle (copysign x, cst) because this can always be 5569 // folded to an fneg or fabs. 5570 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5571 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5572 VT.isInteger() && !VT.isVector()) { 5573 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5574 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5575 if (isTypeLegal(IntXVT)) { 5576 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5577 IntXVT, N0.getOperand(1)); 5578 AddToWorkList(X.getNode()); 5579 5580 // If X has a different width than the result/lhs, sext it or truncate it. 5581 unsigned VTWidth = VT.getSizeInBits(); 5582 if (OrigXWidth < VTWidth) { 5583 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5584 AddToWorkList(X.getNode()); 5585 } else if (OrigXWidth > VTWidth) { 5586 // To get the sign bit in the right place, we have to shift it right 5587 // before truncating. 5588 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5589 X.getValueType(), X, 5590 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5591 AddToWorkList(X.getNode()); 5592 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5593 AddToWorkList(X.getNode()); 5594 } 5595 5596 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5597 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5598 X, DAG.getConstant(SignBit, VT)); 5599 AddToWorkList(X.getNode()); 5600 5601 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5602 VT, N0.getOperand(0)); 5603 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5604 Cst, DAG.getConstant(~SignBit, VT)); 5605 AddToWorkList(Cst.getNode()); 5606 5607 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5608 } 5609 } 5610 5611 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5612 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5613 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5614 if (CombineLD.getNode()) 5615 return CombineLD; 5616 } 5617 5618 return SDValue(); 5619} 5620 5621SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5622 EVT VT = N->getValueType(0); 5623 return CombineConsecutiveLoads(N, VT); 5624} 5625 5626/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5627/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5628/// destination element value type. 5629SDValue DAGCombiner:: 5630ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5631 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5632 5633 // If this is already the right type, we're done. 5634 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5635 5636 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5637 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5638 5639 // If this is a conversion of N elements of one type to N elements of another 5640 // type, convert each element. This handles FP<->INT cases. 5641 if (SrcBitSize == DstBitSize) { 5642 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5643 BV->getValueType(0).getVectorNumElements()); 5644 5645 // Due to the FP element handling below calling this routine recursively, 5646 // we can end up with a scalar-to-vector node here. 5647 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5648 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5649 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5650 DstEltVT, BV->getOperand(0))); 5651 5652 SmallVector<SDValue, 8> Ops; 5653 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5654 SDValue Op = BV->getOperand(i); 5655 // If the vector element type is not legal, the BUILD_VECTOR operands 5656 // are promoted and implicitly truncated. Make that explicit here. 5657 if (Op.getValueType() != SrcEltVT) 5658 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5659 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5660 DstEltVT, Op)); 5661 AddToWorkList(Ops.back().getNode()); 5662 } 5663 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5664 &Ops[0], Ops.size()); 5665 } 5666 5667 // Otherwise, we're growing or shrinking the elements. To avoid having to 5668 // handle annoying details of growing/shrinking FP values, we convert them to 5669 // int first. 5670 if (SrcEltVT.isFloatingPoint()) { 5671 // Convert the input float vector to a int vector where the elements are the 5672 // same sizes. 5673 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5674 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5675 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5676 SrcEltVT = IntVT; 5677 } 5678 5679 // Now we know the input is an integer vector. If the output is a FP type, 5680 // convert to integer first, then to FP of the right size. 5681 if (DstEltVT.isFloatingPoint()) { 5682 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5683 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5684 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5685 5686 // Next, convert to FP elements of the same size. 5687 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5688 } 5689 5690 // Okay, we know the src/dst types are both integers of differing types. 5691 // Handling growing first. 5692 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5693 if (SrcBitSize < DstBitSize) { 5694 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5695 5696 SmallVector<SDValue, 8> Ops; 5697 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5698 i += NumInputsPerOutput) { 5699 bool isLE = TLI.isLittleEndian(); 5700 APInt NewBits = APInt(DstBitSize, 0); 5701 bool EltIsUndef = true; 5702 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5703 // Shift the previously computed bits over. 5704 NewBits <<= SrcBitSize; 5705 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5706 if (Op.getOpcode() == ISD::UNDEF) continue; 5707 EltIsUndef = false; 5708 5709 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5710 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5711 } 5712 5713 if (EltIsUndef) 5714 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5715 else 5716 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5717 } 5718 5719 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5720 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5721 &Ops[0], Ops.size()); 5722 } 5723 5724 // Finally, this must be the case where we are shrinking elements: each input 5725 // turns into multiple outputs. 5726 bool isS2V = ISD::isScalarToVector(BV); 5727 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5728 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5729 NumOutputsPerInput*BV->getNumOperands()); 5730 SmallVector<SDValue, 8> Ops; 5731 5732 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5733 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5734 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5735 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5736 continue; 5737 } 5738 5739 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5740 getAPIntValue().zextOrTrunc(SrcBitSize); 5741 5742 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5743 APInt ThisVal = OpVal.trunc(DstBitSize); 5744 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5745 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5746 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5747 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5748 Ops[0]); 5749 OpVal = OpVal.lshr(DstBitSize); 5750 } 5751 5752 // For big endian targets, swap the order of the pieces of each element. 5753 if (TLI.isBigEndian()) 5754 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5755 } 5756 5757 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5758 &Ops[0], Ops.size()); 5759} 5760 5761SDValue DAGCombiner::visitFADD(SDNode *N) { 5762 SDValue N0 = N->getOperand(0); 5763 SDValue N1 = N->getOperand(1); 5764 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5765 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5766 EVT VT = N->getValueType(0); 5767 5768 // fold vector ops 5769 if (VT.isVector()) { 5770 SDValue FoldedVOp = SimplifyVBinOp(N); 5771 if (FoldedVOp.getNode()) return FoldedVOp; 5772 } 5773 5774 // fold (fadd c1, c2) -> c1 + c2 5775 if (N0CFP && N1CFP) 5776 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5777 // canonicalize constant to RHS 5778 if (N0CFP && !N1CFP) 5779 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5780 // fold (fadd A, 0) -> A 5781 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5782 N1CFP->getValueAPF().isZero()) 5783 return N0; 5784 // fold (fadd A, (fneg B)) -> (fsub A, B) 5785 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5786 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5787 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5788 GetNegatedExpression(N1, DAG, LegalOperations)); 5789 // fold (fadd (fneg A), B) -> (fsub B, A) 5790 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5791 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5792 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5793 GetNegatedExpression(N0, DAG, LegalOperations)); 5794 5795 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5796 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5797 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5798 isa<ConstantFPSDNode>(N0.getOperand(1))) 5799 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5800 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5801 N0.getOperand(1), N1)); 5802 5803 // If allow, fold (fadd (fneg x), x) -> 0.0 5804 if (DAG.getTarget().Options.UnsafeFPMath && 5805 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) { 5806 return DAG.getConstantFP(0.0, VT); 5807 } 5808 5809 // If allow, fold (fadd x, (fneg x)) -> 0.0 5810 if (DAG.getTarget().Options.UnsafeFPMath && 5811 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) { 5812 return DAG.getConstantFP(0.0, VT); 5813 } 5814 5815 // In unsafe math mode, we can fold chains of FADD's of the same value 5816 // into multiplications. This transform is not safe in general because 5817 // we are reducing the number of rounding steps. 5818 if (DAG.getTarget().Options.UnsafeFPMath && 5819 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5820 !N0CFP && !N1CFP) { 5821 if (N0.getOpcode() == ISD::FMUL) { 5822 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5823 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 5824 5825 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5826 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 5827 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5828 SDValue(CFP00, 0), 5829 DAG.getConstantFP(1.0, VT)); 5830 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5831 N1, NewCFP); 5832 } 5833 5834 // (fadd (fmul x, c), x) -> (fmul c+1, x) 5835 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 5836 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5837 SDValue(CFP01, 0), 5838 DAG.getConstantFP(1.0, VT)); 5839 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5840 N1, NewCFP); 5841 } 5842 5843 // (fadd (fadd x, x), x) -> (fmul 3.0, x) 5844 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) && 5845 N0.getOperand(0) == N1) { 5846 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5847 N1, DAG.getConstantFP(3.0, VT)); 5848 } 5849 5850 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x) 5851 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 5852 N1.getOperand(0) == N1.getOperand(1) && 5853 N0.getOperand(1) == N1.getOperand(0)) { 5854 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5855 SDValue(CFP00, 0), 5856 DAG.getConstantFP(2.0, VT)); 5857 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5858 N0.getOperand(1), NewCFP); 5859 } 5860 5861 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x) 5862 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 5863 N1.getOperand(0) == N1.getOperand(1) && 5864 N0.getOperand(0) == N1.getOperand(0)) { 5865 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5866 SDValue(CFP01, 0), 5867 DAG.getConstantFP(2.0, VT)); 5868 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5869 N0.getOperand(0), NewCFP); 5870 } 5871 } 5872 5873 if (N1.getOpcode() == ISD::FMUL) { 5874 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5875 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 5876 5877 // (fadd x, (fmul c, x)) -> (fmul c+1, x) 5878 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 5879 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5880 SDValue(CFP10, 0), 5881 DAG.getConstantFP(1.0, VT)); 5882 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5883 N0, NewCFP); 5884 } 5885 5886 // (fadd x, (fmul x, c)) -> (fmul c+1, x) 5887 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 5888 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5889 SDValue(CFP11, 0), 5890 DAG.getConstantFP(1.0, VT)); 5891 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5892 N0, NewCFP); 5893 } 5894 5895 // (fadd x, (fadd x, x)) -> (fmul 3.0, x) 5896 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) && 5897 N1.getOperand(0) == N0) { 5898 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5899 N0, DAG.getConstantFP(3.0, VT)); 5900 } 5901 5902 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x) 5903 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD && 5904 N1.getOperand(0) == N1.getOperand(1) && 5905 N0.getOperand(1) == N1.getOperand(0)) { 5906 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5907 SDValue(CFP10, 0), 5908 DAG.getConstantFP(2.0, VT)); 5909 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5910 N0.getOperand(1), NewCFP); 5911 } 5912 5913 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x) 5914 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD && 5915 N1.getOperand(0) == N1.getOperand(1) && 5916 N0.getOperand(0) == N1.getOperand(0)) { 5917 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5918 SDValue(CFP11, 0), 5919 DAG.getConstantFP(2.0, VT)); 5920 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5921 N0.getOperand(0), NewCFP); 5922 } 5923 } 5924 5925 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x) 5926 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 5927 N0.getOperand(0) == N0.getOperand(1) && 5928 N1.getOperand(0) == N1.getOperand(1) && 5929 N0.getOperand(0) == N1.getOperand(0)) { 5930 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5931 N0.getOperand(0), 5932 DAG.getConstantFP(4.0, VT)); 5933 } 5934 } 5935 5936 // FADD -> FMA combines: 5937 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5938 DAG.getTarget().Options.UnsafeFPMath) && 5939 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5940 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5941 5942 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 5943 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5944 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5945 N0.getOperand(0), N0.getOperand(1), N1); 5946 } 5947 5948 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 5949 // Note: Commutes FADD operands. 5950 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5951 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5952 N1.getOperand(0), N1.getOperand(1), N0); 5953 } 5954 } 5955 5956 return SDValue(); 5957} 5958 5959SDValue DAGCombiner::visitFSUB(SDNode *N) { 5960 SDValue N0 = N->getOperand(0); 5961 SDValue N1 = N->getOperand(1); 5962 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5963 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5964 EVT VT = N->getValueType(0); 5965 DebugLoc dl = N->getDebugLoc(); 5966 5967 // fold vector ops 5968 if (VT.isVector()) { 5969 SDValue FoldedVOp = SimplifyVBinOp(N); 5970 if (FoldedVOp.getNode()) return FoldedVOp; 5971 } 5972 5973 // fold (fsub c1, c2) -> c1-c2 5974 if (N0CFP && N1CFP) 5975 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5976 // fold (fsub A, 0) -> A 5977 if (DAG.getTarget().Options.UnsafeFPMath && 5978 N1CFP && N1CFP->getValueAPF().isZero()) 5979 return N0; 5980 // fold (fsub 0, B) -> -B 5981 if (DAG.getTarget().Options.UnsafeFPMath && 5982 N0CFP && N0CFP->getValueAPF().isZero()) { 5983 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5984 return GetNegatedExpression(N1, DAG, LegalOperations); 5985 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5986 return DAG.getNode(ISD::FNEG, dl, VT, N1); 5987 } 5988 // fold (fsub A, (fneg B)) -> (fadd A, B) 5989 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5990 return DAG.getNode(ISD::FADD, dl, VT, N0, 5991 GetNegatedExpression(N1, DAG, LegalOperations)); 5992 5993 // If 'unsafe math' is enabled, fold 5994 // (fsub x, x) -> 0.0 & 5995 // (fsub x, (fadd x, y)) -> (fneg y) & 5996 // (fsub x, (fadd y, x)) -> (fneg y) 5997 if (DAG.getTarget().Options.UnsafeFPMath) { 5998 if (N0 == N1) 5999 return DAG.getConstantFP(0.0f, VT); 6000 6001 if (N1.getOpcode() == ISD::FADD) { 6002 SDValue N10 = N1->getOperand(0); 6003 SDValue N11 = N1->getOperand(1); 6004 6005 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 6006 &DAG.getTarget().Options)) 6007 return GetNegatedExpression(N11, DAG, LegalOperations); 6008 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 6009 &DAG.getTarget().Options)) 6010 return GetNegatedExpression(N10, DAG, LegalOperations); 6011 } 6012 } 6013 6014 // FSUB -> FMA combines: 6015 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 6016 DAG.getTarget().Options.UnsafeFPMath) && 6017 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 6018 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 6019 6020 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 6021 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 6022 return DAG.getNode(ISD::FMA, dl, VT, 6023 N0.getOperand(0), N0.getOperand(1), 6024 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6025 } 6026 6027 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 6028 // Note: Commutes FSUB operands. 6029 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 6030 return DAG.getNode(ISD::FMA, dl, VT, 6031 DAG.getNode(ISD::FNEG, dl, VT, 6032 N1.getOperand(0)), 6033 N1.getOperand(1), N0); 6034 } 6035 6036 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 6037 if (N0.getOpcode() == ISD::FNEG && 6038 N0.getOperand(0).getOpcode() == ISD::FMUL && 6039 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 6040 SDValue N00 = N0.getOperand(0).getOperand(0); 6041 SDValue N01 = N0.getOperand(0).getOperand(1); 6042 return DAG.getNode(ISD::FMA, dl, VT, 6043 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 6044 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6045 } 6046 } 6047 6048 return SDValue(); 6049} 6050 6051SDValue DAGCombiner::visitFMUL(SDNode *N) { 6052 SDValue N0 = N->getOperand(0); 6053 SDValue N1 = N->getOperand(1); 6054 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6055 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6056 EVT VT = N->getValueType(0); 6057 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6058 6059 // fold vector ops 6060 if (VT.isVector()) { 6061 SDValue FoldedVOp = SimplifyVBinOp(N); 6062 if (FoldedVOp.getNode()) return FoldedVOp; 6063 } 6064 6065 // fold (fmul c1, c2) -> c1*c2 6066 if (N0CFP && N1CFP) 6067 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 6068 // canonicalize constant to RHS 6069 if (N0CFP && !N1CFP) 6070 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 6071 // fold (fmul A, 0) -> 0 6072 if (DAG.getTarget().Options.UnsafeFPMath && 6073 N1CFP && N1CFP->getValueAPF().isZero()) 6074 return N1; 6075 // fold (fmul A, 0) -> 0, vector edition. 6076 if (DAG.getTarget().Options.UnsafeFPMath && 6077 ISD::isBuildVectorAllZeros(N1.getNode())) 6078 return N1; 6079 // fold (fmul A, 1.0) -> A 6080 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6081 return N0; 6082 // fold (fmul X, 2.0) -> (fadd X, X) 6083 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 6084 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 6085 // fold (fmul X, -1.0) -> (fneg X) 6086 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 6087 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6088 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 6089 6090 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 6091 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6092 &DAG.getTarget().Options)) { 6093 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6094 &DAG.getTarget().Options)) { 6095 // Both can be negated for free, check to see if at least one is cheaper 6096 // negated. 6097 if (LHSNeg == 2 || RHSNeg == 2) 6098 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6099 GetNegatedExpression(N0, DAG, LegalOperations), 6100 GetNegatedExpression(N1, DAG, LegalOperations)); 6101 } 6102 } 6103 6104 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 6105 if (DAG.getTarget().Options.UnsafeFPMath && 6106 N1CFP && N0.getOpcode() == ISD::FMUL && 6107 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 6108 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 6109 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6110 N0.getOperand(1), N1)); 6111 6112 return SDValue(); 6113} 6114 6115SDValue DAGCombiner::visitFMA(SDNode *N) { 6116 SDValue N0 = N->getOperand(0); 6117 SDValue N1 = N->getOperand(1); 6118 SDValue N2 = N->getOperand(2); 6119 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6120 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6121 EVT VT = N->getValueType(0); 6122 DebugLoc dl = N->getDebugLoc(); 6123 6124 if (DAG.getTarget().Options.UnsafeFPMath) { 6125 if (N0CFP && N0CFP->isZero()) 6126 return N2; 6127 if (N1CFP && N1CFP->isZero()) 6128 return N2; 6129 } 6130 if (N0CFP && N0CFP->isExactlyValue(1.0)) 6131 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); 6132 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6133 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); 6134 6135 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6136 if (N0CFP && !N1CFP) 6137 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); 6138 6139 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6140 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6141 N2.getOpcode() == ISD::FMUL && 6142 N0 == N2.getOperand(0) && 6143 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6144 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6145 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6146 } 6147 6148 6149 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6150 if (DAG.getTarget().Options.UnsafeFPMath && 6151 N0.getOpcode() == ISD::FMUL && N1CFP && 6152 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6153 return DAG.getNode(ISD::FMA, dl, VT, 6154 N0.getOperand(0), 6155 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6156 N2); 6157 } 6158 6159 // (fma x, 1, y) -> (fadd x, y) 6160 // (fma x, -1, y) -> (fadd (fneg x), y) 6161 if (N1CFP) { 6162 if (N1CFP->isExactlyValue(1.0)) 6163 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6164 6165 if (N1CFP->isExactlyValue(-1.0) && 6166 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6167 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6168 AddToWorkList(RHSNeg.getNode()); 6169 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6170 } 6171 } 6172 6173 // (fma x, c, x) -> (fmul x, (c+1)) 6174 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) { 6175 return DAG.getNode(ISD::FMUL, dl, VT, 6176 N0, 6177 DAG.getNode(ISD::FADD, dl, VT, 6178 N1, DAG.getConstantFP(1.0, VT))); 6179 } 6180 6181 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6182 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6183 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { 6184 return DAG.getNode(ISD::FMUL, dl, VT, 6185 N0, 6186 DAG.getNode(ISD::FADD, dl, VT, 6187 N1, DAG.getConstantFP(-1.0, VT))); 6188 } 6189 6190 6191 return SDValue(); 6192} 6193 6194SDValue DAGCombiner::visitFDIV(SDNode *N) { 6195 SDValue N0 = N->getOperand(0); 6196 SDValue N1 = N->getOperand(1); 6197 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6198 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6199 EVT VT = N->getValueType(0); 6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6201 6202 // fold vector ops 6203 if (VT.isVector()) { 6204 SDValue FoldedVOp = SimplifyVBinOp(N); 6205 if (FoldedVOp.getNode()) return FoldedVOp; 6206 } 6207 6208 // fold (fdiv c1, c2) -> c1/c2 6209 if (N0CFP && N1CFP) 6210 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 6211 6212 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6213 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) { 6214 // Compute the reciprocal 1.0 / c2. 6215 APFloat N1APF = N1CFP->getValueAPF(); 6216 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6217 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6218 // Only do the transform if the reciprocal is a legal fp immediate that 6219 // isn't too nasty (eg NaN, denormal, ...). 6220 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6221 (!LegalOperations || 6222 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6223 // backend)... we should handle this gracefully after Legalize. 6224 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6225 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6226 TLI.isFPImmLegal(Recip, VT))) 6227 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 6228 DAG.getConstantFP(Recip, VT)); 6229 } 6230 6231 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6232 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6233 &DAG.getTarget().Options)) { 6234 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6235 &DAG.getTarget().Options)) { 6236 // Both can be negated for free, check to see if at least one is cheaper 6237 // negated. 6238 if (LHSNeg == 2 || RHSNeg == 2) 6239 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 6240 GetNegatedExpression(N0, DAG, LegalOperations), 6241 GetNegatedExpression(N1, DAG, LegalOperations)); 6242 } 6243 } 6244 6245 return SDValue(); 6246} 6247 6248SDValue DAGCombiner::visitFREM(SDNode *N) { 6249 SDValue N0 = N->getOperand(0); 6250 SDValue N1 = N->getOperand(1); 6251 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6252 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6253 EVT VT = N->getValueType(0); 6254 6255 // fold (frem c1, c2) -> fmod(c1,c2) 6256 if (N0CFP && N1CFP) 6257 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 6258 6259 return SDValue(); 6260} 6261 6262SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6263 SDValue N0 = N->getOperand(0); 6264 SDValue N1 = N->getOperand(1); 6265 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6266 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6267 EVT VT = N->getValueType(0); 6268 6269 if (N0CFP && N1CFP) // Constant fold 6270 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 6271 6272 if (N1CFP) { 6273 const APFloat& V = N1CFP->getValueAPF(); 6274 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6275 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6276 if (!V.isNegative()) { 6277 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6278 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6279 } else { 6280 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6281 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6282 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 6283 } 6284 } 6285 6286 // copysign(fabs(x), y) -> copysign(x, y) 6287 // copysign(fneg(x), y) -> copysign(x, y) 6288 // copysign(copysign(x,z), y) -> copysign(x, y) 6289 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6290 N0.getOpcode() == ISD::FCOPYSIGN) 6291 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6292 N0.getOperand(0), N1); 6293 6294 // copysign(x, abs(y)) -> abs(x) 6295 if (N1.getOpcode() == ISD::FABS) 6296 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6297 6298 // copysign(x, copysign(y,z)) -> copysign(x, z) 6299 if (N1.getOpcode() == ISD::FCOPYSIGN) 6300 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6301 N0, N1.getOperand(1)); 6302 6303 // copysign(x, fp_extend(y)) -> copysign(x, y) 6304 // copysign(x, fp_round(y)) -> copysign(x, y) 6305 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6306 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6307 N0, N1.getOperand(0)); 6308 6309 return SDValue(); 6310} 6311 6312SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6313 SDValue N0 = N->getOperand(0); 6314 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6315 EVT VT = N->getValueType(0); 6316 EVT OpVT = N0.getValueType(); 6317 6318 // fold (sint_to_fp c1) -> c1fp 6319 if (N0C && 6320 // ...but only if the target supports immediate floating-point values 6321 (!LegalOperations || 6322 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6323 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6324 6325 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6326 // but UINT_TO_FP is legal on this target, try to convert. 6327 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6328 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6329 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6330 if (DAG.SignBitIsZero(N0)) 6331 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6332 } 6333 6334 // The next optimizations are desireable only if SELECT_CC can be lowered. 6335 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6336 // having to say they don't support SELECT_CC on every type the DAG knows 6337 // about, since there is no way to mark an opcode illegal at all value types 6338 // (See also visitSELECT) 6339 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6340 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6341 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6342 !VT.isVector() && 6343 (!LegalOperations || 6344 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6345 SDValue Ops[] = 6346 { N0.getOperand(0), N0.getOperand(1), 6347 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6348 N0.getOperand(2) }; 6349 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6350 } 6351 6352 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6353 // (select_cc x, y, 1.0, 0.0,, cc) 6354 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6355 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6356 (!LegalOperations || 6357 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6358 SDValue Ops[] = 6359 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6360 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6361 N0.getOperand(0).getOperand(2) }; 6362 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6363 } 6364 } 6365 6366 return SDValue(); 6367} 6368 6369SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6370 SDValue N0 = N->getOperand(0); 6371 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6372 EVT VT = N->getValueType(0); 6373 EVT OpVT = N0.getValueType(); 6374 6375 // fold (uint_to_fp c1) -> c1fp 6376 if (N0C && 6377 // ...but only if the target supports immediate floating-point values 6378 (!LegalOperations || 6379 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6380 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6381 6382 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6383 // but SINT_TO_FP is legal on this target, try to convert. 6384 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6385 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6386 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6387 if (DAG.SignBitIsZero(N0)) 6388 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6389 } 6390 6391 // The next optimizations are desireable only if SELECT_CC can be lowered. 6392 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6393 // having to say they don't support SELECT_CC on every type the DAG knows 6394 // about, since there is no way to mark an opcode illegal at all value types 6395 // (See also visitSELECT) 6396 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6397 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6398 6399 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6400 (!LegalOperations || 6401 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6402 SDValue Ops[] = 6403 { N0.getOperand(0), N0.getOperand(1), 6404 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6405 N0.getOperand(2) }; 6406 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6407 } 6408 } 6409 6410 return SDValue(); 6411} 6412 6413SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6414 SDValue N0 = N->getOperand(0); 6415 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6416 EVT VT = N->getValueType(0); 6417 6418 // fold (fp_to_sint c1fp) -> c1 6419 if (N0CFP) 6420 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 6421 6422 return SDValue(); 6423} 6424 6425SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6426 SDValue N0 = N->getOperand(0); 6427 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6428 EVT VT = N->getValueType(0); 6429 6430 // fold (fp_to_uint c1fp) -> c1 6431 if (N0CFP) 6432 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 6433 6434 return SDValue(); 6435} 6436 6437SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6438 SDValue N0 = N->getOperand(0); 6439 SDValue N1 = N->getOperand(1); 6440 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6441 EVT VT = N->getValueType(0); 6442 6443 // fold (fp_round c1fp) -> c1fp 6444 if (N0CFP) 6445 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 6446 6447 // fold (fp_round (fp_extend x)) -> x 6448 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6449 return N0.getOperand(0); 6450 6451 // fold (fp_round (fp_round x)) -> (fp_round x) 6452 if (N0.getOpcode() == ISD::FP_ROUND) { 6453 // This is a value preserving truncation if both round's are. 6454 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6455 N0.getNode()->getConstantOperandVal(1) == 1; 6456 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 6457 DAG.getIntPtrConstant(IsTrunc)); 6458 } 6459 6460 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6461 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6462 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 6463 N0.getOperand(0), N1); 6464 AddToWorkList(Tmp.getNode()); 6465 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6466 Tmp, N0.getOperand(1)); 6467 } 6468 6469 return SDValue(); 6470} 6471 6472SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6473 SDValue N0 = N->getOperand(0); 6474 EVT VT = N->getValueType(0); 6475 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6476 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6477 6478 // fold (fp_round_inreg c1fp) -> c1fp 6479 if (N0CFP && isTypeLegal(EVT)) { 6480 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6481 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 6482 } 6483 6484 return SDValue(); 6485} 6486 6487SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6488 SDValue N0 = N->getOperand(0); 6489 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6490 EVT VT = N->getValueType(0); 6491 6492 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6493 if (N->hasOneUse() && 6494 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6495 return SDValue(); 6496 6497 // fold (fp_extend c1fp) -> c1fp 6498 if (N0CFP) 6499 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6500 6501 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6502 // value of X. 6503 if (N0.getOpcode() == ISD::FP_ROUND 6504 && N0.getNode()->getConstantOperandVal(1) == 1) { 6505 SDValue In = N0.getOperand(0); 6506 if (In.getValueType() == VT) return In; 6507 if (VT.bitsLT(In.getValueType())) 6508 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6509 In, N0.getOperand(1)); 6510 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6511 } 6512 6513 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6514 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6515 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6516 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6517 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6518 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6519 LN0->getChain(), 6520 LN0->getBasePtr(), LN0->getPointerInfo(), 6521 N0.getValueType(), 6522 LN0->isVolatile(), LN0->isNonTemporal(), 6523 LN0->getAlignment()); 6524 CombineTo(N, ExtLoad); 6525 CombineTo(N0.getNode(), 6526 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6527 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6528 ExtLoad.getValue(1)); 6529 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6530 } 6531 6532 return SDValue(); 6533} 6534 6535SDValue DAGCombiner::visitFNEG(SDNode *N) { 6536 SDValue N0 = N->getOperand(0); 6537 EVT VT = N->getValueType(0); 6538 6539 if (VT.isVector()) { 6540 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6541 if (FoldedVOp.getNode()) return FoldedVOp; 6542 } 6543 6544 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6545 &DAG.getTarget().Options)) 6546 return GetNegatedExpression(N0, DAG, LegalOperations); 6547 6548 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6549 // constant pool values. 6550 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6551 !VT.isVector() && 6552 N0.getNode()->hasOneUse() && 6553 N0.getOperand(0).getValueType().isInteger()) { 6554 SDValue Int = N0.getOperand(0); 6555 EVT IntVT = Int.getValueType(); 6556 if (IntVT.isInteger() && !IntVT.isVector()) { 6557 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6558 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6559 AddToWorkList(Int.getNode()); 6560 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6561 VT, Int); 6562 } 6563 } 6564 6565 // (fneg (fmul c, x)) -> (fmul -c, x) 6566 if (N0.getOpcode() == ISD::FMUL) { 6567 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6568 if (CFP1) { 6569 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6570 N0.getOperand(0), 6571 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6572 N0.getOperand(1))); 6573 } 6574 } 6575 6576 return SDValue(); 6577} 6578 6579SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6580 SDValue N0 = N->getOperand(0); 6581 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6582 EVT VT = N->getValueType(0); 6583 6584 // fold (fceil c1) -> fceil(c1) 6585 if (N0CFP) 6586 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0); 6587 6588 return SDValue(); 6589} 6590 6591SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6592 SDValue N0 = N->getOperand(0); 6593 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6594 EVT VT = N->getValueType(0); 6595 6596 // fold (ftrunc c1) -> ftrunc(c1) 6597 if (N0CFP) 6598 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0); 6599 6600 return SDValue(); 6601} 6602 6603SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6604 SDValue N0 = N->getOperand(0); 6605 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6606 EVT VT = N->getValueType(0); 6607 6608 // fold (ffloor c1) -> ffloor(c1) 6609 if (N0CFP) 6610 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0); 6611 6612 return SDValue(); 6613} 6614 6615SDValue DAGCombiner::visitFABS(SDNode *N) { 6616 SDValue N0 = N->getOperand(0); 6617 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6618 EVT VT = N->getValueType(0); 6619 6620 if (VT.isVector()) { 6621 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6622 if (FoldedVOp.getNode()) return FoldedVOp; 6623 } 6624 6625 // fold (fabs c1) -> fabs(c1) 6626 if (N0CFP) 6627 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6628 // fold (fabs (fabs x)) -> (fabs x) 6629 if (N0.getOpcode() == ISD::FABS) 6630 return N->getOperand(0); 6631 // fold (fabs (fneg x)) -> (fabs x) 6632 // fold (fabs (fcopysign x, y)) -> (fabs x) 6633 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6634 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6635 6636 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6637 // constant pool values. 6638 if (!TLI.isFAbsFree(VT) && 6639 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6640 N0.getOperand(0).getValueType().isInteger() && 6641 !N0.getOperand(0).getValueType().isVector()) { 6642 SDValue Int = N0.getOperand(0); 6643 EVT IntVT = Int.getValueType(); 6644 if (IntVT.isInteger() && !IntVT.isVector()) { 6645 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6646 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6647 AddToWorkList(Int.getNode()); 6648 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6649 N->getValueType(0), Int); 6650 } 6651 } 6652 6653 return SDValue(); 6654} 6655 6656SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6657 SDValue Chain = N->getOperand(0); 6658 SDValue N1 = N->getOperand(1); 6659 SDValue N2 = N->getOperand(2); 6660 6661 // If N is a constant we could fold this into a fallthrough or unconditional 6662 // branch. However that doesn't happen very often in normal code, because 6663 // Instcombine/SimplifyCFG should have handled the available opportunities. 6664 // If we did this folding here, it would be necessary to update the 6665 // MachineBasicBlock CFG, which is awkward. 6666 6667 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6668 // on the target. 6669 if (N1.getOpcode() == ISD::SETCC && 6670 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6671 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6672 Chain, N1.getOperand(2), 6673 N1.getOperand(0), N1.getOperand(1), N2); 6674 } 6675 6676 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6677 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6678 (N1.getOperand(0).hasOneUse() && 6679 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6680 SDNode *Trunc = 0; 6681 if (N1.getOpcode() == ISD::TRUNCATE) { 6682 // Look pass the truncate. 6683 Trunc = N1.getNode(); 6684 N1 = N1.getOperand(0); 6685 } 6686 6687 // Match this pattern so that we can generate simpler code: 6688 // 6689 // %a = ... 6690 // %b = and i32 %a, 2 6691 // %c = srl i32 %b, 1 6692 // brcond i32 %c ... 6693 // 6694 // into 6695 // 6696 // %a = ... 6697 // %b = and i32 %a, 2 6698 // %c = setcc eq %b, 0 6699 // brcond %c ... 6700 // 6701 // This applies only when the AND constant value has one bit set and the 6702 // SRL constant is equal to the log2 of the AND constant. The back-end is 6703 // smart enough to convert the result into a TEST/JMP sequence. 6704 SDValue Op0 = N1.getOperand(0); 6705 SDValue Op1 = N1.getOperand(1); 6706 6707 if (Op0.getOpcode() == ISD::AND && 6708 Op1.getOpcode() == ISD::Constant) { 6709 SDValue AndOp1 = Op0.getOperand(1); 6710 6711 if (AndOp1.getOpcode() == ISD::Constant) { 6712 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6713 6714 if (AndConst.isPowerOf2() && 6715 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6716 SDValue SetCC = 6717 DAG.getSetCC(N->getDebugLoc(), 6718 TLI.getSetCCResultType(Op0.getValueType()), 6719 Op0, DAG.getConstant(0, Op0.getValueType()), 6720 ISD::SETNE); 6721 6722 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6723 MVT::Other, Chain, SetCC, N2); 6724 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6725 // will convert it back to (X & C1) >> C2. 6726 CombineTo(N, NewBRCond, false); 6727 // Truncate is dead. 6728 if (Trunc) { 6729 removeFromWorkList(Trunc); 6730 DAG.DeleteNode(Trunc); 6731 } 6732 // Replace the uses of SRL with SETCC 6733 WorkListRemover DeadNodes(*this); 6734 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6735 removeFromWorkList(N1.getNode()); 6736 DAG.DeleteNode(N1.getNode()); 6737 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6738 } 6739 } 6740 } 6741 6742 if (Trunc) 6743 // Restore N1 if the above transformation doesn't match. 6744 N1 = N->getOperand(1); 6745 } 6746 6747 // Transform br(xor(x, y)) -> br(x != y) 6748 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6749 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6750 SDNode *TheXor = N1.getNode(); 6751 SDValue Op0 = TheXor->getOperand(0); 6752 SDValue Op1 = TheXor->getOperand(1); 6753 if (Op0.getOpcode() == Op1.getOpcode()) { 6754 // Avoid missing important xor optimizations. 6755 SDValue Tmp = visitXOR(TheXor); 6756 if (Tmp.getNode()) { 6757 if (Tmp.getNode() != TheXor) { 6758 DEBUG(dbgs() << "\nReplacing.8 "; 6759 TheXor->dump(&DAG); 6760 dbgs() << "\nWith: "; 6761 Tmp.getNode()->dump(&DAG); 6762 dbgs() << '\n'); 6763 WorkListRemover DeadNodes(*this); 6764 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6765 removeFromWorkList(TheXor); 6766 DAG.DeleteNode(TheXor); 6767 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6768 MVT::Other, Chain, Tmp, N2); 6769 } 6770 6771 // visitXOR has changed XOR's operands. 6772 Op0 = TheXor->getOperand(0); 6773 Op1 = TheXor->getOperand(1); 6774 } 6775 } 6776 6777 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6778 bool Equal = false; 6779 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6780 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6781 Op0.getOpcode() == ISD::XOR) { 6782 TheXor = Op0.getNode(); 6783 Equal = true; 6784 } 6785 6786 EVT SetCCVT = N1.getValueType(); 6787 if (LegalTypes) 6788 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6789 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6790 SetCCVT, 6791 Op0, Op1, 6792 Equal ? ISD::SETEQ : ISD::SETNE); 6793 // Replace the uses of XOR with SETCC 6794 WorkListRemover DeadNodes(*this); 6795 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6796 removeFromWorkList(N1.getNode()); 6797 DAG.DeleteNode(N1.getNode()); 6798 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6799 MVT::Other, Chain, SetCC, N2); 6800 } 6801 } 6802 6803 return SDValue(); 6804} 6805 6806// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6807// 6808SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6809 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6810 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6811 6812 // If N is a constant we could fold this into a fallthrough or unconditional 6813 // branch. However that doesn't happen very often in normal code, because 6814 // Instcombine/SimplifyCFG should have handled the available opportunities. 6815 // If we did this folding here, it would be necessary to update the 6816 // MachineBasicBlock CFG, which is awkward. 6817 6818 // Use SimplifySetCC to simplify SETCC's. 6819 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6820 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6821 false); 6822 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6823 6824 // fold to a simpler setcc 6825 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6826 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6827 N->getOperand(0), Simp.getOperand(2), 6828 Simp.getOperand(0), Simp.getOperand(1), 6829 N->getOperand(4)); 6830 6831 return SDValue(); 6832} 6833 6834/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6835/// uses N as its base pointer and that N may be folded in the load / store 6836/// addressing mode. 6837static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6838 SelectionDAG &DAG, 6839 const TargetLowering &TLI) { 6840 EVT VT; 6841 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6842 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6843 return false; 6844 VT = Use->getValueType(0); 6845 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6846 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6847 return false; 6848 VT = ST->getValue().getValueType(); 6849 } else 6850 return false; 6851 6852 TargetLowering::AddrMode AM; 6853 if (N->getOpcode() == ISD::ADD) { 6854 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6855 if (Offset) 6856 // [reg +/- imm] 6857 AM.BaseOffs = Offset->getSExtValue(); 6858 else 6859 // [reg +/- reg] 6860 AM.Scale = 1; 6861 } else if (N->getOpcode() == ISD::SUB) { 6862 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6863 if (Offset) 6864 // [reg +/- imm] 6865 AM.BaseOffs = -Offset->getSExtValue(); 6866 else 6867 // [reg +/- reg] 6868 AM.Scale = 1; 6869 } else 6870 return false; 6871 6872 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6873} 6874 6875/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6876/// pre-indexed load / store when the base pointer is an add or subtract 6877/// and it has other uses besides the load / store. After the 6878/// transformation, the new indexed load / store has effectively folded 6879/// the add / subtract in and all of its other uses are redirected to the 6880/// new load / store. 6881bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6882 if (Level < AfterLegalizeDAG) 6883 return false; 6884 6885 bool isLoad = true; 6886 SDValue Ptr; 6887 EVT VT; 6888 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6889 if (LD->isIndexed()) 6890 return false; 6891 VT = LD->getMemoryVT(); 6892 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6893 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6894 return false; 6895 Ptr = LD->getBasePtr(); 6896 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6897 if (ST->isIndexed()) 6898 return false; 6899 VT = ST->getMemoryVT(); 6900 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6901 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6902 return false; 6903 Ptr = ST->getBasePtr(); 6904 isLoad = false; 6905 } else { 6906 return false; 6907 } 6908 6909 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6910 // out. There is no reason to make this a preinc/predec. 6911 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6912 Ptr.getNode()->hasOneUse()) 6913 return false; 6914 6915 // Ask the target to do addressing mode selection. 6916 SDValue BasePtr; 6917 SDValue Offset; 6918 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6919 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6920 return false; 6921 // Don't create a indexed load / store with zero offset. 6922 if (isa<ConstantSDNode>(Offset) && 6923 cast<ConstantSDNode>(Offset)->isNullValue()) 6924 return false; 6925 6926 // Try turning it into a pre-indexed load / store except when: 6927 // 1) The new base ptr is a frame index. 6928 // 2) If N is a store and the new base ptr is either the same as or is a 6929 // predecessor of the value being stored. 6930 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6931 // that would create a cycle. 6932 // 4) All uses are load / store ops that use it as old base ptr. 6933 6934 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6935 // (plus the implicit offset) to a register to preinc anyway. 6936 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6937 return false; 6938 6939 // Check #2. 6940 if (!isLoad) { 6941 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6942 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6943 return false; 6944 } 6945 6946 // Now check for #3 and #4. 6947 bool RealUse = false; 6948 6949 // Caches for hasPredecessorHelper 6950 SmallPtrSet<const SDNode *, 32> Visited; 6951 SmallVector<const SDNode *, 16> Worklist; 6952 6953 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6954 E = Ptr.getNode()->use_end(); I != E; ++I) { 6955 SDNode *Use = *I; 6956 if (Use == N) 6957 continue; 6958 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6959 return false; 6960 6961 // If Ptr may be folded in addressing mode of other use, then it's 6962 // not profitable to do this transformation. 6963 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6964 RealUse = true; 6965 } 6966 6967 if (!RealUse) 6968 return false; 6969 6970 SDValue Result; 6971 if (isLoad) 6972 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6973 BasePtr, Offset, AM); 6974 else 6975 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6976 BasePtr, Offset, AM); 6977 ++PreIndexedNodes; 6978 ++NodesCombined; 6979 DEBUG(dbgs() << "\nReplacing.4 "; 6980 N->dump(&DAG); 6981 dbgs() << "\nWith: "; 6982 Result.getNode()->dump(&DAG); 6983 dbgs() << '\n'); 6984 WorkListRemover DeadNodes(*this); 6985 if (isLoad) { 6986 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6987 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6988 } else { 6989 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6990 } 6991 6992 // Finally, since the node is now dead, remove it from the graph. 6993 DAG.DeleteNode(N); 6994 6995 // Replace the uses of Ptr with uses of the updated base value. 6996 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 6997 removeFromWorkList(Ptr.getNode()); 6998 DAG.DeleteNode(Ptr.getNode()); 6999 7000 return true; 7001} 7002 7003/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 7004/// add / sub of the base pointer node into a post-indexed load / store. 7005/// The transformation folded the add / subtract into the new indexed 7006/// load / store effectively and all of its uses are redirected to the 7007/// new load / store. 7008bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 7009 if (Level < AfterLegalizeDAG) 7010 return false; 7011 7012 bool isLoad = true; 7013 SDValue Ptr; 7014 EVT VT; 7015 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7016 if (LD->isIndexed()) 7017 return false; 7018 VT = LD->getMemoryVT(); 7019 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 7020 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 7021 return false; 7022 Ptr = LD->getBasePtr(); 7023 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7024 if (ST->isIndexed()) 7025 return false; 7026 VT = ST->getMemoryVT(); 7027 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 7028 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 7029 return false; 7030 Ptr = ST->getBasePtr(); 7031 isLoad = false; 7032 } else { 7033 return false; 7034 } 7035 7036 if (Ptr.getNode()->hasOneUse()) 7037 return false; 7038 7039 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 7040 E = Ptr.getNode()->use_end(); I != E; ++I) { 7041 SDNode *Op = *I; 7042 if (Op == N || 7043 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 7044 continue; 7045 7046 SDValue BasePtr; 7047 SDValue Offset; 7048 ISD::MemIndexedMode AM = ISD::UNINDEXED; 7049 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 7050 // Don't create a indexed load / store with zero offset. 7051 if (isa<ConstantSDNode>(Offset) && 7052 cast<ConstantSDNode>(Offset)->isNullValue()) 7053 continue; 7054 7055 // Try turning it into a post-indexed load / store except when 7056 // 1) All uses are load / store ops that use it as base ptr (and 7057 // it may be folded as addressing mmode). 7058 // 2) Op must be independent of N, i.e. Op is neither a predecessor 7059 // nor a successor of N. Otherwise, if Op is folded that would 7060 // create a cycle. 7061 7062 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 7063 continue; 7064 7065 // Check for #1. 7066 bool TryNext = false; 7067 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 7068 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 7069 SDNode *Use = *II; 7070 if (Use == Ptr.getNode()) 7071 continue; 7072 7073 // If all the uses are load / store addresses, then don't do the 7074 // transformation. 7075 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 7076 bool RealUse = false; 7077 for (SDNode::use_iterator III = Use->use_begin(), 7078 EEE = Use->use_end(); III != EEE; ++III) { 7079 SDNode *UseUse = *III; 7080 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 7081 RealUse = true; 7082 } 7083 7084 if (!RealUse) { 7085 TryNext = true; 7086 break; 7087 } 7088 } 7089 } 7090 7091 if (TryNext) 7092 continue; 7093 7094 // Check for #2 7095 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 7096 SDValue Result = isLoad 7097 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 7098 BasePtr, Offset, AM) 7099 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 7100 BasePtr, Offset, AM); 7101 ++PostIndexedNodes; 7102 ++NodesCombined; 7103 DEBUG(dbgs() << "\nReplacing.5 "; 7104 N->dump(&DAG); 7105 dbgs() << "\nWith: "; 7106 Result.getNode()->dump(&DAG); 7107 dbgs() << '\n'); 7108 WorkListRemover DeadNodes(*this); 7109 if (isLoad) { 7110 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7111 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7112 } else { 7113 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7114 } 7115 7116 // Finally, since the node is now dead, remove it from the graph. 7117 DAG.DeleteNode(N); 7118 7119 // Replace the uses of Use with uses of the updated base value. 7120 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 7121 Result.getValue(isLoad ? 1 : 0)); 7122 removeFromWorkList(Op); 7123 DAG.DeleteNode(Op); 7124 return true; 7125 } 7126 } 7127 } 7128 7129 return false; 7130} 7131 7132SDValue DAGCombiner::visitLOAD(SDNode *N) { 7133 LoadSDNode *LD = cast<LoadSDNode>(N); 7134 SDValue Chain = LD->getChain(); 7135 SDValue Ptr = LD->getBasePtr(); 7136 7137 // If load is not volatile and there are no uses of the loaded value (and 7138 // the updated indexed value in case of indexed loads), change uses of the 7139 // chain value into uses of the chain input (i.e. delete the dead load). 7140 if (!LD->isVolatile()) { 7141 if (N->getValueType(1) == MVT::Other) { 7142 // Unindexed loads. 7143 if (!N->hasAnyUseOfValue(0)) { 7144 // It's not safe to use the two value CombineTo variant here. e.g. 7145 // v1, chain2 = load chain1, loc 7146 // v2, chain3 = load chain2, loc 7147 // v3 = add v2, c 7148 // Now we replace use of chain2 with chain1. This makes the second load 7149 // isomorphic to the one we are deleting, and thus makes this load live. 7150 DEBUG(dbgs() << "\nReplacing.6 "; 7151 N->dump(&DAG); 7152 dbgs() << "\nWith chain: "; 7153 Chain.getNode()->dump(&DAG); 7154 dbgs() << "\n"); 7155 WorkListRemover DeadNodes(*this); 7156 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7157 7158 if (N->use_empty()) { 7159 removeFromWorkList(N); 7160 DAG.DeleteNode(N); 7161 } 7162 7163 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7164 } 7165 } else { 7166 // Indexed loads. 7167 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7168 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7169 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7170 DEBUG(dbgs() << "\nReplacing.7 "; 7171 N->dump(&DAG); 7172 dbgs() << "\nWith: "; 7173 Undef.getNode()->dump(&DAG); 7174 dbgs() << " and 2 other values\n"); 7175 WorkListRemover DeadNodes(*this); 7176 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7177 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7178 DAG.getUNDEF(N->getValueType(1))); 7179 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7180 removeFromWorkList(N); 7181 DAG.DeleteNode(N); 7182 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7183 } 7184 } 7185 } 7186 7187 // If this load is directly stored, replace the load value with the stored 7188 // value. 7189 // TODO: Handle store large -> read small portion. 7190 // TODO: Handle TRUNCSTORE/LOADEXT 7191 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7192 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7193 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7194 if (PrevST->getBasePtr() == Ptr && 7195 PrevST->getValue().getValueType() == N->getValueType(0)) 7196 return CombineTo(N, Chain.getOperand(1), Chain); 7197 } 7198 } 7199 7200 // Try to infer better alignment information than the load already has. 7201 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7202 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7203 if (Align > LD->getAlignment()) 7204 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 7205 LD->getValueType(0), 7206 Chain, Ptr, LD->getPointerInfo(), 7207 LD->getMemoryVT(), 7208 LD->isVolatile(), LD->isNonTemporal(), Align); 7209 } 7210 } 7211 7212 if (CombinerAA) { 7213 // Walk up chain skipping non-aliasing memory nodes. 7214 SDValue BetterChain = FindBetterChain(N, Chain); 7215 7216 // If there is a better chain. 7217 if (Chain != BetterChain) { 7218 SDValue ReplLoad; 7219 7220 // Replace the chain to void dependency. 7221 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7222 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 7223 BetterChain, Ptr, LD->getPointerInfo(), 7224 LD->isVolatile(), LD->isNonTemporal(), 7225 LD->isInvariant(), LD->getAlignment()); 7226 } else { 7227 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 7228 LD->getValueType(0), 7229 BetterChain, Ptr, LD->getPointerInfo(), 7230 LD->getMemoryVT(), 7231 LD->isVolatile(), 7232 LD->isNonTemporal(), 7233 LD->getAlignment()); 7234 } 7235 7236 // Create token factor to keep old chain connected. 7237 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7238 MVT::Other, Chain, ReplLoad.getValue(1)); 7239 7240 // Make sure the new and old chains are cleaned up. 7241 AddToWorkList(Token.getNode()); 7242 7243 // Replace uses with load result and token factor. Don't add users 7244 // to work list. 7245 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7246 } 7247 } 7248 7249 // Try transforming N to an indexed load. 7250 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7251 return SDValue(N, 0); 7252 7253 return SDValue(); 7254} 7255 7256/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 7257/// load is having specific bytes cleared out. If so, return the byte size 7258/// being masked out and the shift amount. 7259static std::pair<unsigned, unsigned> 7260CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 7261 std::pair<unsigned, unsigned> Result(0, 0); 7262 7263 // Check for the structure we're looking for. 7264 if (V->getOpcode() != ISD::AND || 7265 !isa<ConstantSDNode>(V->getOperand(1)) || 7266 !ISD::isNormalLoad(V->getOperand(0).getNode())) 7267 return Result; 7268 7269 // Check the chain and pointer. 7270 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 7271 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 7272 7273 // The store should be chained directly to the load or be an operand of a 7274 // tokenfactor. 7275 if (LD == Chain.getNode()) 7276 ; // ok. 7277 else if (Chain->getOpcode() != ISD::TokenFactor) 7278 return Result; // Fail. 7279 else { 7280 bool isOk = false; 7281 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 7282 if (Chain->getOperand(i).getNode() == LD) { 7283 isOk = true; 7284 break; 7285 } 7286 if (!isOk) return Result; 7287 } 7288 7289 // This only handles simple types. 7290 if (V.getValueType() != MVT::i16 && 7291 V.getValueType() != MVT::i32 && 7292 V.getValueType() != MVT::i64) 7293 return Result; 7294 7295 // Check the constant mask. Invert it so that the bits being masked out are 7296 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 7297 // follow the sign bit for uniformity. 7298 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 7299 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 7300 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 7301 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 7302 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 7303 if (NotMaskLZ == 64) return Result; // All zero mask. 7304 7305 // See if we have a continuous run of bits. If so, we have 0*1+0* 7306 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 7307 return Result; 7308 7309 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 7310 if (V.getValueType() != MVT::i64 && NotMaskLZ) 7311 NotMaskLZ -= 64-V.getValueSizeInBits(); 7312 7313 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 7314 switch (MaskedBytes) { 7315 case 1: 7316 case 2: 7317 case 4: break; 7318 default: return Result; // All one mask, or 5-byte mask. 7319 } 7320 7321 // Verify that the first bit starts at a multiple of mask so that the access 7322 // is aligned the same as the access width. 7323 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 7324 7325 Result.first = MaskedBytes; 7326 Result.second = NotMaskTZ/8; 7327 return Result; 7328} 7329 7330 7331/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 7332/// provides a value as specified by MaskInfo. If so, replace the specified 7333/// store with a narrower store of truncated IVal. 7334static SDNode * 7335ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 7336 SDValue IVal, StoreSDNode *St, 7337 DAGCombiner *DC) { 7338 unsigned NumBytes = MaskInfo.first; 7339 unsigned ByteShift = MaskInfo.second; 7340 SelectionDAG &DAG = DC->getDAG(); 7341 7342 // Check to see if IVal is all zeros in the part being masked in by the 'or' 7343 // that uses this. If not, this is not a replacement. 7344 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 7345 ByteShift*8, (ByteShift+NumBytes)*8); 7346 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 7347 7348 // Check that it is legal on the target to do this. It is legal if the new 7349 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 7350 // legalization. 7351 MVT VT = MVT::getIntegerVT(NumBytes*8); 7352 if (!DC->isTypeLegal(VT)) 7353 return 0; 7354 7355 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 7356 // shifted by ByteShift and truncated down to NumBytes. 7357 if (ByteShift) 7358 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 7359 DAG.getConstant(ByteShift*8, 7360 DC->getShiftAmountTy(IVal.getValueType()))); 7361 7362 // Figure out the offset for the store and the alignment of the access. 7363 unsigned StOffset; 7364 unsigned NewAlign = St->getAlignment(); 7365 7366 if (DAG.getTargetLoweringInfo().isLittleEndian()) 7367 StOffset = ByteShift; 7368 else 7369 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 7370 7371 SDValue Ptr = St->getBasePtr(); 7372 if (StOffset) { 7373 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 7374 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 7375 NewAlign = MinAlign(NewAlign, StOffset); 7376 } 7377 7378 // Truncate down to the new size. 7379 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 7380 7381 ++OpsNarrowed; 7382 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 7383 St->getPointerInfo().getWithOffset(StOffset), 7384 false, false, NewAlign).getNode(); 7385} 7386 7387 7388/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 7389/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 7390/// of the loaded bits, try narrowing the load and store if it would end up 7391/// being a win for performance or code size. 7392SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 7393 StoreSDNode *ST = cast<StoreSDNode>(N); 7394 if (ST->isVolatile()) 7395 return SDValue(); 7396 7397 SDValue Chain = ST->getChain(); 7398 SDValue Value = ST->getValue(); 7399 SDValue Ptr = ST->getBasePtr(); 7400 EVT VT = Value.getValueType(); 7401 7402 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 7403 return SDValue(); 7404 7405 unsigned Opc = Value.getOpcode(); 7406 7407 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 7408 // is a byte mask indicating a consecutive number of bytes, check to see if 7409 // Y is known to provide just those bytes. If so, we try to replace the 7410 // load + replace + store sequence with a single (narrower) store, which makes 7411 // the load dead. 7412 if (Opc == ISD::OR) { 7413 std::pair<unsigned, unsigned> MaskedLoad; 7414 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 7415 if (MaskedLoad.first) 7416 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7417 Value.getOperand(1), ST,this)) 7418 return SDValue(NewST, 0); 7419 7420 // Or is commutative, so try swapping X and Y. 7421 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 7422 if (MaskedLoad.first) 7423 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7424 Value.getOperand(0), ST,this)) 7425 return SDValue(NewST, 0); 7426 } 7427 7428 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 7429 Value.getOperand(1).getOpcode() != ISD::Constant) 7430 return SDValue(); 7431 7432 SDValue N0 = Value.getOperand(0); 7433 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 7434 Chain == SDValue(N0.getNode(), 1)) { 7435 LoadSDNode *LD = cast<LoadSDNode>(N0); 7436 if (LD->getBasePtr() != Ptr || 7437 LD->getPointerInfo().getAddrSpace() != 7438 ST->getPointerInfo().getAddrSpace()) 7439 return SDValue(); 7440 7441 // Find the type to narrow it the load / op / store to. 7442 SDValue N1 = Value.getOperand(1); 7443 unsigned BitWidth = N1.getValueSizeInBits(); 7444 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 7445 if (Opc == ISD::AND) 7446 Imm ^= APInt::getAllOnesValue(BitWidth); 7447 if (Imm == 0 || Imm.isAllOnesValue()) 7448 return SDValue(); 7449 unsigned ShAmt = Imm.countTrailingZeros(); 7450 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 7451 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 7452 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7453 while (NewBW < BitWidth && 7454 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 7455 TLI.isNarrowingProfitable(VT, NewVT))) { 7456 NewBW = NextPowerOf2(NewBW); 7457 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7458 } 7459 if (NewBW >= BitWidth) 7460 return SDValue(); 7461 7462 // If the lsb changed does not start at the type bitwidth boundary, 7463 // start at the previous one. 7464 if (ShAmt % NewBW) 7465 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 7466 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, 7467 std::min(BitWidth, ShAmt + NewBW)); 7468 if ((Imm & Mask) == Imm) { 7469 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 7470 if (Opc == ISD::AND) 7471 NewImm ^= APInt::getAllOnesValue(NewBW); 7472 uint64_t PtrOff = ShAmt / 8; 7473 // For big endian targets, we need to adjust the offset to the pointer to 7474 // load the correct bytes. 7475 if (TLI.isBigEndian()) 7476 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 7477 7478 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 7479 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 7480 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy)) 7481 return SDValue(); 7482 7483 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 7484 Ptr.getValueType(), Ptr, 7485 DAG.getConstant(PtrOff, Ptr.getValueType())); 7486 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 7487 LD->getChain(), NewPtr, 7488 LD->getPointerInfo().getWithOffset(PtrOff), 7489 LD->isVolatile(), LD->isNonTemporal(), 7490 LD->isInvariant(), NewAlign); 7491 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 7492 DAG.getConstant(NewImm, NewVT)); 7493 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 7494 NewVal, NewPtr, 7495 ST->getPointerInfo().getWithOffset(PtrOff), 7496 false, false, NewAlign); 7497 7498 AddToWorkList(NewPtr.getNode()); 7499 AddToWorkList(NewLD.getNode()); 7500 AddToWorkList(NewVal.getNode()); 7501 WorkListRemover DeadNodes(*this); 7502 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7503 ++OpsNarrowed; 7504 return NewST; 7505 } 7506 } 7507 7508 return SDValue(); 7509} 7510 7511/// TransformFPLoadStorePair - For a given floating point load / store pair, 7512/// if the load value isn't used by any other operations, then consider 7513/// transforming the pair to integer load / store operations if the target 7514/// deems the transformation profitable. 7515SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7516 StoreSDNode *ST = cast<StoreSDNode>(N); 7517 SDValue Chain = ST->getChain(); 7518 SDValue Value = ST->getValue(); 7519 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7520 Value.hasOneUse() && 7521 Chain == SDValue(Value.getNode(), 1)) { 7522 LoadSDNode *LD = cast<LoadSDNode>(Value); 7523 EVT VT = LD->getMemoryVT(); 7524 if (!VT.isFloatingPoint() || 7525 VT != ST->getMemoryVT() || 7526 LD->isNonTemporal() || 7527 ST->isNonTemporal() || 7528 LD->getPointerInfo().getAddrSpace() != 0 || 7529 ST->getPointerInfo().getAddrSpace() != 0) 7530 return SDValue(); 7531 7532 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7533 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7534 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7535 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7536 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7537 return SDValue(); 7538 7539 unsigned LDAlign = LD->getAlignment(); 7540 unsigned STAlign = ST->getAlignment(); 7541 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7542 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy); 7543 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7544 return SDValue(); 7545 7546 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 7547 LD->getChain(), LD->getBasePtr(), 7548 LD->getPointerInfo(), 7549 false, false, false, LDAlign); 7550 7551 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 7552 NewLD, ST->getBasePtr(), 7553 ST->getPointerInfo(), 7554 false, false, STAlign); 7555 7556 AddToWorkList(NewLD.getNode()); 7557 AddToWorkList(NewST.getNode()); 7558 WorkListRemover DeadNodes(*this); 7559 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7560 ++LdStFP2Int; 7561 return NewST; 7562 } 7563 7564 return SDValue(); 7565} 7566 7567/// Returns the base pointer and an integer offset from that object. 7568static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) { 7569 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) { 7570 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue(); 7571 SDValue Base = Ptr->getOperand(0); 7572 return std::make_pair(Base, Offset); 7573 } 7574 7575 return std::make_pair(Ptr, 0); 7576} 7577 7578/// Holds a pointer to an LSBaseSDNode as well as information on where it 7579/// is located in a sequence of memory operations connected by a chain. 7580struct MemOpLink { 7581 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq): 7582 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { } 7583 // Ptr to the mem node. 7584 LSBaseSDNode *MemNode; 7585 // Offset from the base ptr. 7586 int64_t OffsetFromBase; 7587 // What is the sequence number of this mem node. 7588 // Lowest mem operand in the DAG starts at zero. 7589 unsigned SequenceNum; 7590}; 7591 7592/// Sorts store nodes in a link according to their offset from a shared 7593// base ptr. 7594struct ConsecutiveMemoryChainSorter { 7595 bool operator()(MemOpLink LHS, MemOpLink RHS) { 7596 return LHS.OffsetFromBase < RHS.OffsetFromBase; 7597 } 7598}; 7599 7600bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) { 7601 EVT MemVT = St->getMemoryVT(); 7602 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8; 7603 7604 // Don't merge vectors into wider inputs. 7605 if (MemVT.isVector() || !MemVT.isSimple()) 7606 return false; 7607 7608 // Perform an early exit check. Do not bother looking at stored values that 7609 // are not constants or loads. 7610 SDValue StoredVal = St->getValue(); 7611 bool IsLoadSrc = isa<LoadSDNode>(StoredVal); 7612 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) && 7613 !IsLoadSrc) 7614 return false; 7615 7616 // Only look at ends of store sequences. 7617 SDValue Chain = SDValue(St, 1); 7618 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE) 7619 return false; 7620 7621 // This holds the base pointer and the offset in bytes from the base pointer. 7622 std::pair<SDValue, int64_t> BasePtr = 7623 GetPointerBaseAndOffset(St->getBasePtr()); 7624 7625 // We must have a base and an offset. 7626 if (!BasePtr.first.getNode()) 7627 return false; 7628 7629 // Do not handle stores to undef base pointers. 7630 if (BasePtr.first.getOpcode() == ISD::UNDEF) 7631 return false; 7632 7633 // Save the LoadSDNodes that we find in the chain. 7634 // We need to make sure that these nodes do not interfere with 7635 // any of the store nodes. 7636 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes; 7637 7638 // Save the StoreSDNodes that we find in the chain. 7639 SmallVector<MemOpLink, 8> StoreNodes; 7640 7641 // Walk up the chain and look for nodes with offsets from the same 7642 // base pointer. Stop when reaching an instruction with a different kind 7643 // or instruction which has a different base pointer. 7644 unsigned Seq = 0; 7645 StoreSDNode *Index = St; 7646 while (Index) { 7647 // If the chain has more than one use, then we can't reorder the mem ops. 7648 if (Index != St && !SDValue(Index, 1)->hasOneUse()) 7649 break; 7650 7651 // Find the base pointer and offset for this memory node. 7652 std::pair<SDValue, int64_t> Ptr = 7653 GetPointerBaseAndOffset(Index->getBasePtr()); 7654 7655 // Check that the base pointer is the same as the original one. 7656 if (Ptr.first.getNode() != BasePtr.first.getNode()) 7657 break; 7658 7659 // Check that the alignment is the same. 7660 if (Index->getAlignment() != St->getAlignment()) 7661 break; 7662 7663 // The memory operands must not be volatile. 7664 if (Index->isVolatile() || Index->isIndexed()) 7665 break; 7666 7667 // No truncation. 7668 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index)) 7669 if (St->isTruncatingStore()) 7670 break; 7671 7672 // The stored memory type must be the same. 7673 if (Index->getMemoryVT() != MemVT) 7674 break; 7675 7676 // We do not allow unaligned stores because we want to prevent overriding 7677 // stores. 7678 if (Index->getAlignment()*8 != MemVT.getSizeInBits()) 7679 break; 7680 7681 // We found a potential memory operand to merge. 7682 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++)); 7683 7684 // Find the next memory operand in the chain. If the next operand in the 7685 // chain is a store then move up and continue the scan with the next 7686 // memory operand. If the next operand is a load save it and use alias 7687 // information to check if it interferes with anything. 7688 SDNode *NextInChain = Index->getChain().getNode(); 7689 while (1) { 7690 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) { 7691 // We found a store node. Use it for the next iteration. 7692 Index = STn; 7693 break; 7694 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) { 7695 // Save the load node for later. Continue the scan. 7696 AliasLoadNodes.push_back(Ldn); 7697 NextInChain = Ldn->getChain().getNode(); 7698 continue; 7699 } else { 7700 Index = NULL; 7701 break; 7702 } 7703 } 7704 } 7705 7706 // Check if there is anything to merge. 7707 if (StoreNodes.size() < 2) 7708 return false; 7709 7710 // Sort the memory operands according to their distance from the base pointer. 7711 std::sort(StoreNodes.begin(), StoreNodes.end(), 7712 ConsecutiveMemoryChainSorter()); 7713 7714 // Scan the memory operations on the chain and find the first non-consecutive 7715 // store memory address. 7716 unsigned LastConsecutiveStore = 0; 7717 int64_t StartAddress = StoreNodes[0].OffsetFromBase; 7718 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) { 7719 7720 // Check that the addresses are consecutive starting from the second 7721 // element in the list of stores. 7722 if (i > 0) { 7723 int64_t CurrAddress = StoreNodes[i].OffsetFromBase; 7724 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7725 break; 7726 } 7727 7728 bool Alias = false; 7729 // Check if this store interferes with any of the loads that we found. 7730 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld) 7731 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) { 7732 Alias = true; 7733 break; 7734 } 7735 // We found a load that alias with this store. Stop the sequence. 7736 if (Alias) 7737 break; 7738 7739 // Mark this node as useful. 7740 LastConsecutiveStore = i; 7741 } 7742 7743 // The node with the lowest store address. 7744 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; 7745 7746 // Store the constants into memory as one consecutive store. 7747 if (!IsLoadSrc) { 7748 unsigned LastLegalType = 0; 7749 unsigned LastLegalVectorType = 0; 7750 bool NonZero = false; 7751 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7752 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7753 SDValue StoredVal = St->getValue(); 7754 7755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) { 7756 NonZero |= !C->isNullValue(); 7757 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) { 7758 NonZero |= !C->getConstantFPValue()->isNullValue(); 7759 } else { 7760 // Non constant. 7761 break; 7762 } 7763 7764 // Find a legal type for the constant store. 7765 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7766 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7767 if (TLI.isTypeLegal(StoreTy)) 7768 LastLegalType = i+1; 7769 7770 // Find a legal type for the vector store. 7771 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7772 if (TLI.isTypeLegal(Ty)) 7773 LastLegalVectorType = i + 1; 7774 } 7775 7776 // We only use vectors if the constant is known to be zero and the 7777 // function is not marked with the noimplicitfloat attribute. 7778 if (NonZero || (DAG.getMachineFunction().getFunction()->getAttributes(). 7779 hasAttribute(AttributeSet::FunctionIndex, 7780 Attribute::NoImplicitFloat))) 7781 LastLegalVectorType = 0; 7782 7783 // Check if we found a legal integer type to store. 7784 if (LastLegalType == 0 && LastLegalVectorType == 0) 7785 return false; 7786 7787 bool UseVector = LastLegalVectorType > LastLegalType; 7788 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType; 7789 7790 // Make sure we have something to merge. 7791 if (NumElem < 2) 7792 return false; 7793 7794 unsigned EarliestNodeUsed = 0; 7795 for (unsigned i=0; i < NumElem; ++i) { 7796 // Find a chain for the new wide-store operand. Notice that some 7797 // of the store nodes that we found may not be selected for inclusion 7798 // in the wide store. The chain we use needs to be the chain of the 7799 // earliest store node which is *used* and replaced by the wide store. 7800 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7801 EarliestNodeUsed = i; 7802 } 7803 7804 // The earliest Node in the DAG. 7805 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7806 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc(); 7807 7808 SDValue StoredVal; 7809 if (UseVector) { 7810 // Find a legal type for the vector store. 7811 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7812 assert(TLI.isTypeLegal(Ty) && "Illegal vector store"); 7813 StoredVal = DAG.getConstant(0, Ty); 7814 } else { 7815 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7816 APInt StoreInt(StoreBW, 0); 7817 7818 // Construct a single integer constant which is made of the smaller 7819 // constant inputs. 7820 bool IsLE = TLI.isLittleEndian(); 7821 for (unsigned i = 0; i < NumElem ; ++i) { 7822 unsigned Idx = IsLE ?(NumElem - 1 - i) : i; 7823 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode); 7824 SDValue Val = St->getValue(); 7825 StoreInt<<=ElementSizeBytes*8; 7826 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) { 7827 StoreInt|=C->getAPIntValue().zext(StoreBW); 7828 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) { 7829 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW); 7830 } else { 7831 assert(false && "Invalid constant element type"); 7832 } 7833 } 7834 7835 // Create the new Load and Store operations. 7836 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7837 StoredVal = DAG.getConstant(StoreInt, StoreTy); 7838 } 7839 7840 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal, 7841 FirstInChain->getBasePtr(), 7842 FirstInChain->getPointerInfo(), 7843 false, false, 7844 FirstInChain->getAlignment()); 7845 7846 // Replace the first store with the new store 7847 CombineTo(EarliestOp, NewStore); 7848 // Erase all other stores. 7849 for (unsigned i = 0; i < NumElem ; ++i) { 7850 if (StoreNodes[i].MemNode == EarliestOp) 7851 continue; 7852 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7853 // ReplaceAllUsesWith will replace all uses that existed when it was 7854 // called, but graph optimizations may cause new ones to appear. For 7855 // example, the case in pr14333 looks like 7856 // 7857 // St's chain -> St -> another store -> X 7858 // 7859 // And the only difference from St to the other store is the chain. 7860 // When we change it's chain to be St's chain they become identical, 7861 // get CSEed and the net result is that X is now a use of St. 7862 // Since we know that St is redundant, just iterate. 7863 while (!St->use_empty()) 7864 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain()); 7865 removeFromWorkList(St); 7866 DAG.DeleteNode(St); 7867 } 7868 7869 return true; 7870 } 7871 7872 // Below we handle the case of multiple consecutive stores that 7873 // come from multiple consecutive loads. We merge them into a single 7874 // wide load and a single wide store. 7875 7876 // Look for load nodes which are used by the stored values. 7877 SmallVector<MemOpLink, 8> LoadNodes; 7878 7879 // Find acceptable loads. Loads need to have the same chain (token factor), 7880 // must not be zext, volatile, indexed, and they must be consecutive. 7881 SDValue LdBasePtr; 7882 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7883 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7884 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue()); 7885 if (!Ld) break; 7886 7887 // Loads must only have one use. 7888 if (!Ld->hasNUsesOfValue(1, 0)) 7889 break; 7890 7891 // Check that the alignment is the same as the stores. 7892 if (Ld->getAlignment() != St->getAlignment()) 7893 break; 7894 7895 // The memory operands must not be volatile. 7896 if (Ld->isVolatile() || Ld->isIndexed()) 7897 break; 7898 7899 // We do not accept ext loads. 7900 if (Ld->getExtensionType() != ISD::NON_EXTLOAD) 7901 break; 7902 7903 // The stored memory type must be the same. 7904 if (Ld->getMemoryVT() != MemVT) 7905 break; 7906 7907 std::pair<SDValue, int64_t> LdPtr = 7908 GetPointerBaseAndOffset(Ld->getBasePtr()); 7909 7910 // If this is not the first ptr that we check. 7911 if (LdBasePtr.getNode()) { 7912 // The base ptr must be the same. 7913 if (LdPtr.first != LdBasePtr) 7914 break; 7915 } else { 7916 // Check that all other base pointers are the same as this one. 7917 LdBasePtr = LdPtr.first; 7918 } 7919 7920 // We found a potential memory operand to merge. 7921 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0)); 7922 } 7923 7924 if (LoadNodes.size() < 2) 7925 return false; 7926 7927 // Scan the memory operations on the chain and find the first non-consecutive 7928 // load memory address. These variables hold the index in the store node 7929 // array. 7930 unsigned LastConsecutiveLoad = 0; 7931 // This variable refers to the size and not index in the array. 7932 unsigned LastLegalVectorType = 0; 7933 unsigned LastLegalIntegerType = 0; 7934 StartAddress = LoadNodes[0].OffsetFromBase; 7935 SDValue FirstChain = LoadNodes[0].MemNode->getChain(); 7936 for (unsigned i = 1; i < LoadNodes.size(); ++i) { 7937 // All loads much share the same chain. 7938 if (LoadNodes[i].MemNode->getChain() != FirstChain) 7939 break; 7940 7941 int64_t CurrAddress = LoadNodes[i].OffsetFromBase; 7942 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7943 break; 7944 LastConsecutiveLoad = i; 7945 7946 // Find a legal type for the vector store. 7947 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7948 if (TLI.isTypeLegal(StoreTy)) 7949 LastLegalVectorType = i + 1; 7950 7951 // Find a legal type for the integer store. 7952 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7953 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7954 if (TLI.isTypeLegal(StoreTy)) 7955 LastLegalIntegerType = i + 1; 7956 } 7957 7958 // Only use vector types if the vector type is larger than the integer type. 7959 // If they are the same, use integers. 7960 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType; 7961 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType); 7962 7963 // We add +1 here because the LastXXX variables refer to location while 7964 // the NumElem refers to array/index size. 7965 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1; 7966 NumElem = std::min(LastLegalType, NumElem); 7967 7968 if (NumElem < 2) 7969 return false; 7970 7971 // The earliest Node in the DAG. 7972 unsigned EarliestNodeUsed = 0; 7973 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7974 for (unsigned i=1; i<NumElem; ++i) { 7975 // Find a chain for the new wide-store operand. Notice that some 7976 // of the store nodes that we found may not be selected for inclusion 7977 // in the wide store. The chain we use needs to be the chain of the 7978 // earliest store node which is *used* and replaced by the wide store. 7979 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7980 EarliestNodeUsed = i; 7981 } 7982 7983 // Find if it is better to use vectors or integers to load and store 7984 // to memory. 7985 EVT JointMemOpVT; 7986 if (UseVectorTy) { 7987 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7988 } else { 7989 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7990 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7991 } 7992 7993 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc(); 7994 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc(); 7995 7996 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode); 7997 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL, 7998 FirstLoad->getChain(), 7999 FirstLoad->getBasePtr(), 8000 FirstLoad->getPointerInfo(), 8001 false, false, false, 8002 FirstLoad->getAlignment()); 8003 8004 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad, 8005 FirstInChain->getBasePtr(), 8006 FirstInChain->getPointerInfo(), false, false, 8007 FirstInChain->getAlignment()); 8008 8009 // Replace one of the loads with the new load. 8010 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode); 8011 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), 8012 SDValue(NewLoad.getNode(), 1)); 8013 8014 // Remove the rest of the load chains. 8015 for (unsigned i = 1; i < NumElem ; ++i) { 8016 // Replace all chain users of the old load nodes with the chain of the new 8017 // load node. 8018 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode); 8019 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain()); 8020 } 8021 8022 // Replace the first store with the new store. 8023 CombineTo(EarliestOp, NewStore); 8024 // Erase all other stores. 8025 for (unsigned i = 0; i < NumElem ; ++i) { 8026 // Remove all Store nodes. 8027 if (StoreNodes[i].MemNode == EarliestOp) 8028 continue; 8029 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8030 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain()); 8031 removeFromWorkList(St); 8032 DAG.DeleteNode(St); 8033 } 8034 8035 return true; 8036} 8037 8038SDValue DAGCombiner::visitSTORE(SDNode *N) { 8039 StoreSDNode *ST = cast<StoreSDNode>(N); 8040 SDValue Chain = ST->getChain(); 8041 SDValue Value = ST->getValue(); 8042 SDValue Ptr = ST->getBasePtr(); 8043 8044 // If this is a store of a bit convert, store the input value if the 8045 // resultant store does not need a higher alignment than the original. 8046 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 8047 ST->isUnindexed()) { 8048 unsigned OrigAlign = ST->getAlignment(); 8049 EVT SVT = Value.getOperand(0).getValueType(); 8050 unsigned Align = TLI.getDataLayout()-> 8051 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 8052 if (Align <= OrigAlign && 8053 ((!LegalOperations && !ST->isVolatile()) || 8054 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 8055 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8056 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8057 ST->isNonTemporal(), OrigAlign); 8058 } 8059 8060 // Turn 'store undef, Ptr' -> nothing. 8061 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 8062 return Chain; 8063 8064 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 8065 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 8066 // NOTE: If the original store is volatile, this transform must not increase 8067 // the number of stores. For example, on x86-32 an f64 can be stored in one 8068 // processor operation but an i64 (which is not legal) requires two. So the 8069 // transform should not be done in this case. 8070 if (Value.getOpcode() != ISD::TargetConstantFP) { 8071 SDValue Tmp; 8072 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 8073 default: llvm_unreachable("Unknown FP type"); 8074 case MVT::f16: // We don't do this for these yet. 8075 case MVT::f80: 8076 case MVT::f128: 8077 case MVT::ppcf128: 8078 break; 8079 case MVT::f32: 8080 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 8081 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8082 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 8083 bitcastToAPInt().getZExtValue(), MVT::i32); 8084 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 8085 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8086 ST->isNonTemporal(), ST->getAlignment()); 8087 } 8088 break; 8089 case MVT::f64: 8090 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 8091 !ST->isVolatile()) || 8092 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 8093 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 8094 getZExtValue(), MVT::i64); 8095 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 8096 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8097 ST->isNonTemporal(), ST->getAlignment()); 8098 } 8099 8100 if (!ST->isVolatile() && 8101 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8102 // Many FP stores are not made apparent until after legalize, e.g. for 8103 // argument passing. Since this is so common, custom legalize the 8104 // 64-bit integer store into two 32-bit stores. 8105 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 8106 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 8107 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 8108 if (TLI.isBigEndian()) std::swap(Lo, Hi); 8109 8110 unsigned Alignment = ST->getAlignment(); 8111 bool isVolatile = ST->isVolatile(); 8112 bool isNonTemporal = ST->isNonTemporal(); 8113 8114 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 8115 Ptr, ST->getPointerInfo(), 8116 isVolatile, isNonTemporal, 8117 ST->getAlignment()); 8118 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 8119 DAG.getConstant(4, Ptr.getValueType())); 8120 Alignment = MinAlign(Alignment, 4U); 8121 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 8122 Ptr, ST->getPointerInfo().getWithOffset(4), 8123 isVolatile, isNonTemporal, 8124 Alignment); 8125 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8126 St0, St1); 8127 } 8128 8129 break; 8130 } 8131 } 8132 } 8133 8134 // Try to infer better alignment information than the store already has. 8135 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 8136 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 8137 if (Align > ST->getAlignment()) 8138 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 8139 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8140 ST->isVolatile(), ST->isNonTemporal(), Align); 8141 } 8142 } 8143 8144 // Try transforming a pair floating point load / store ops to integer 8145 // load / store ops. 8146 SDValue NewST = TransformFPLoadStorePair(N); 8147 if (NewST.getNode()) 8148 return NewST; 8149 8150 if (CombinerAA) { 8151 // Walk up chain skipping non-aliasing memory nodes. 8152 SDValue BetterChain = FindBetterChain(N, Chain); 8153 8154 // If there is a better chain. 8155 if (Chain != BetterChain) { 8156 SDValue ReplStore; 8157 8158 // Replace the chain to avoid dependency. 8159 if (ST->isTruncatingStore()) { 8160 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8161 ST->getPointerInfo(), 8162 ST->getMemoryVT(), ST->isVolatile(), 8163 ST->isNonTemporal(), ST->getAlignment()); 8164 } else { 8165 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8166 ST->getPointerInfo(), 8167 ST->isVolatile(), ST->isNonTemporal(), 8168 ST->getAlignment()); 8169 } 8170 8171 // Create token to keep both nodes around. 8172 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 8173 MVT::Other, Chain, ReplStore); 8174 8175 // Make sure the new and old chains are cleaned up. 8176 AddToWorkList(Token.getNode()); 8177 8178 // Don't add users to work list. 8179 return CombineTo(N, Token, false); 8180 } 8181 } 8182 8183 // Try transforming N to an indexed store. 8184 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 8185 return SDValue(N, 0); 8186 8187 // FIXME: is there such a thing as a truncating indexed store? 8188 if (ST->isTruncatingStore() && ST->isUnindexed() && 8189 Value.getValueType().isInteger()) { 8190 // See if we can simplify the input to this truncstore with knowledge that 8191 // only the low bits are being used. For example: 8192 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 8193 SDValue Shorter = 8194 GetDemandedBits(Value, 8195 APInt::getLowBitsSet( 8196 Value.getValueType().getScalarType().getSizeInBits(), 8197 ST->getMemoryVT().getScalarType().getSizeInBits())); 8198 AddToWorkList(Value.getNode()); 8199 if (Shorter.getNode()) 8200 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 8201 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8202 ST->isVolatile(), ST->isNonTemporal(), 8203 ST->getAlignment()); 8204 8205 // Otherwise, see if we can simplify the operation with 8206 // SimplifyDemandedBits, which only works if the value has a single use. 8207 if (SimplifyDemandedBits(Value, 8208 APInt::getLowBitsSet( 8209 Value.getValueType().getScalarType().getSizeInBits(), 8210 ST->getMemoryVT().getScalarType().getSizeInBits()))) 8211 return SDValue(N, 0); 8212 } 8213 8214 // If this is a load followed by a store to the same location, then the store 8215 // is dead/noop. 8216 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 8217 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 8218 ST->isUnindexed() && !ST->isVolatile() && 8219 // There can't be any side effects between the load and store, such as 8220 // a call or store. 8221 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 8222 // The store is dead, remove it. 8223 return Chain; 8224 } 8225 } 8226 8227 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 8228 // truncating store. We can do this even if this is already a truncstore. 8229 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 8230 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 8231 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 8232 ST->getMemoryVT())) { 8233 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8234 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8235 ST->isVolatile(), ST->isNonTemporal(), 8236 ST->getAlignment()); 8237 } 8238 8239 // Only perform this optimization before the types are legal, because we 8240 // don't want to perform this optimization on every DAGCombine invocation. 8241 if (!LegalTypes) { 8242 bool EverChanged = false; 8243 8244 do { 8245 // There can be multiple store sequences on the same chain. 8246 // Keep trying to merge store sequences until we are unable to do so 8247 // or until we merge the last store on the chain. 8248 bool Changed = MergeConsecutiveStores(ST); 8249 EverChanged |= Changed; 8250 if (!Changed) break; 8251 } while (ST->getOpcode() != ISD::DELETED_NODE); 8252 8253 if (EverChanged) 8254 return SDValue(N, 0); 8255 } 8256 8257 return ReduceLoadOpStoreWidth(N); 8258} 8259 8260SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 8261 SDValue InVec = N->getOperand(0); 8262 SDValue InVal = N->getOperand(1); 8263 SDValue EltNo = N->getOperand(2); 8264 DebugLoc dl = N->getDebugLoc(); 8265 8266 // If the inserted element is an UNDEF, just use the input vector. 8267 if (InVal.getOpcode() == ISD::UNDEF) 8268 return InVec; 8269 8270 EVT VT = InVec.getValueType(); 8271 8272 // If we can't generate a legal BUILD_VECTOR, exit 8273 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 8274 return SDValue(); 8275 8276 // Check that we know which element is being inserted 8277 if (!isa<ConstantSDNode>(EltNo)) 8278 return SDValue(); 8279 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8280 8281 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 8282 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 8283 // vector elements. 8284 SmallVector<SDValue, 8> Ops; 8285 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 8286 Ops.append(InVec.getNode()->op_begin(), 8287 InVec.getNode()->op_end()); 8288 } else if (InVec.getOpcode() == ISD::UNDEF) { 8289 unsigned NElts = VT.getVectorNumElements(); 8290 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 8291 } else { 8292 return SDValue(); 8293 } 8294 8295 // Insert the element 8296 if (Elt < Ops.size()) { 8297 // All the operands of BUILD_VECTOR must have the same type; 8298 // we enforce that here. 8299 EVT OpVT = Ops[0].getValueType(); 8300 if (InVal.getValueType() != OpVT) 8301 InVal = OpVT.bitsGT(InVal.getValueType()) ? 8302 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 8303 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 8304 Ops[Elt] = InVal; 8305 } 8306 8307 // Return the new vector 8308 return DAG.getNode(ISD::BUILD_VECTOR, dl, 8309 VT, &Ops[0], Ops.size()); 8310} 8311 8312SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 8313 // (vextract (scalar_to_vector val, 0) -> val 8314 SDValue InVec = N->getOperand(0); 8315 EVT VT = InVec.getValueType(); 8316 EVT NVT = N->getValueType(0); 8317 8318 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 8319 // Check if the result type doesn't match the inserted element type. A 8320 // SCALAR_TO_VECTOR may truncate the inserted element and the 8321 // EXTRACT_VECTOR_ELT may widen the extracted vector. 8322 SDValue InOp = InVec.getOperand(0); 8323 if (InOp.getValueType() != NVT) { 8324 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 8325 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 8326 } 8327 return InOp; 8328 } 8329 8330 SDValue EltNo = N->getOperand(1); 8331 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 8332 8333 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 8334 // We only perform this optimization before the op legalization phase because 8335 // we may introduce new vector instructions which are not backed by TD 8336 // patterns. For example on AVX, extracting elements from a wide vector 8337 // without using extract_subvector. 8338 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 8339 && ConstEltNo && !LegalOperations) { 8340 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8341 int NumElem = VT.getVectorNumElements(); 8342 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 8343 // Find the new index to extract from. 8344 int OrigElt = SVOp->getMaskElt(Elt); 8345 8346 // Extracting an undef index is undef. 8347 if (OrigElt == -1) 8348 return DAG.getUNDEF(NVT); 8349 8350 // Select the right vector half to extract from. 8351 if (OrigElt < NumElem) { 8352 InVec = InVec->getOperand(0); 8353 } else { 8354 InVec = InVec->getOperand(1); 8355 OrigElt -= NumElem; 8356 } 8357 8358 EVT IndexTy = N->getOperand(1).getValueType(); 8359 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 8360 InVec, DAG.getConstant(OrigElt, IndexTy)); 8361 } 8362 8363 // Perform only after legalization to ensure build_vector / vector_shuffle 8364 // optimizations have already been done. 8365 if (!LegalOperations) return SDValue(); 8366 8367 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 8368 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 8369 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 8370 8371 if (ConstEltNo) { 8372 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8373 bool NewLoad = false; 8374 bool BCNumEltsChanged = false; 8375 EVT ExtVT = VT.getVectorElementType(); 8376 EVT LVT = ExtVT; 8377 8378 // If the result of load has to be truncated, then it's not necessarily 8379 // profitable. 8380 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 8381 return SDValue(); 8382 8383 if (InVec.getOpcode() == ISD::BITCAST) { 8384 // Don't duplicate a load with other uses. 8385 if (!InVec.hasOneUse()) 8386 return SDValue(); 8387 8388 EVT BCVT = InVec.getOperand(0).getValueType(); 8389 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 8390 return SDValue(); 8391 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 8392 BCNumEltsChanged = true; 8393 InVec = InVec.getOperand(0); 8394 ExtVT = BCVT.getVectorElementType(); 8395 NewLoad = true; 8396 } 8397 8398 LoadSDNode *LN0 = NULL; 8399 const ShuffleVectorSDNode *SVN = NULL; 8400 if (ISD::isNormalLoad(InVec.getNode())) { 8401 LN0 = cast<LoadSDNode>(InVec); 8402 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 8403 InVec.getOperand(0).getValueType() == ExtVT && 8404 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 8405 // Don't duplicate a load with other uses. 8406 if (!InVec.hasOneUse()) 8407 return SDValue(); 8408 8409 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 8410 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 8411 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 8412 // => 8413 // (load $addr+1*size) 8414 8415 // Don't duplicate a load with other uses. 8416 if (!InVec.hasOneUse()) 8417 return SDValue(); 8418 8419 // If the bit convert changed the number of elements, it is unsafe 8420 // to examine the mask. 8421 if (BCNumEltsChanged) 8422 return SDValue(); 8423 8424 // Select the input vector, guarding against out of range extract vector. 8425 unsigned NumElems = VT.getVectorNumElements(); 8426 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 8427 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 8428 8429 if (InVec.getOpcode() == ISD::BITCAST) { 8430 // Don't duplicate a load with other uses. 8431 if (!InVec.hasOneUse()) 8432 return SDValue(); 8433 8434 InVec = InVec.getOperand(0); 8435 } 8436 if (ISD::isNormalLoad(InVec.getNode())) { 8437 LN0 = cast<LoadSDNode>(InVec); 8438 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 8439 } 8440 } 8441 8442 // Make sure we found a non-volatile load and the extractelement is 8443 // the only use. 8444 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 8445 return SDValue(); 8446 8447 // If Idx was -1 above, Elt is going to be -1, so just return undef. 8448 if (Elt == -1) 8449 return DAG.getUNDEF(LVT); 8450 8451 unsigned Align = LN0->getAlignment(); 8452 if (NewLoad) { 8453 // Check the resultant load doesn't need a higher alignment than the 8454 // original load. 8455 unsigned NewAlign = 8456 TLI.getDataLayout() 8457 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 8458 8459 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 8460 return SDValue(); 8461 8462 Align = NewAlign; 8463 } 8464 8465 SDValue NewPtr = LN0->getBasePtr(); 8466 unsigned PtrOff = 0; 8467 8468 if (Elt) { 8469 PtrOff = LVT.getSizeInBits() * Elt / 8; 8470 EVT PtrType = NewPtr.getValueType(); 8471 if (TLI.isBigEndian()) 8472 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 8473 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 8474 DAG.getConstant(PtrOff, PtrType)); 8475 } 8476 8477 // The replacement we need to do here is a little tricky: we need to 8478 // replace an extractelement of a load with a load. 8479 // Use ReplaceAllUsesOfValuesWith to do the replacement. 8480 // Note that this replacement assumes that the extractvalue is the only 8481 // use of the load; that's okay because we don't want to perform this 8482 // transformation in other cases anyway. 8483 SDValue Load; 8484 SDValue Chain; 8485 if (NVT.bitsGT(LVT)) { 8486 // If the result type of vextract is wider than the load, then issue an 8487 // extending load instead. 8488 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 8489 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 8490 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 8491 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 8492 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 8493 Chain = Load.getValue(1); 8494 } else { 8495 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 8496 LN0->getPointerInfo().getWithOffset(PtrOff), 8497 LN0->isVolatile(), LN0->isNonTemporal(), 8498 LN0->isInvariant(), Align); 8499 Chain = Load.getValue(1); 8500 if (NVT.bitsLT(LVT)) 8501 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 8502 else 8503 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 8504 } 8505 WorkListRemover DeadNodes(*this); 8506 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 8507 SDValue To[] = { Load, Chain }; 8508 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 8509 // Since we're explcitly calling ReplaceAllUses, add the new node to the 8510 // worklist explicitly as well. 8511 AddToWorkList(Load.getNode()); 8512 AddUsersToWorkList(Load.getNode()); // Add users too 8513 // Make sure to revisit this node to clean it up; it will usually be dead. 8514 AddToWorkList(N); 8515 return SDValue(N, 0); 8516 } 8517 8518 return SDValue(); 8519} 8520 8521// Simplify (build_vec (ext )) to (bitcast (build_vec )) 8522SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) { 8523 // We perform this optimization post type-legalization because 8524 // the type-legalizer often scalarizes integer-promoted vectors. 8525 // Performing this optimization before may create bit-casts which 8526 // will be type-legalized to complex code sequences. 8527 // We perform this optimization only before the operation legalizer because we 8528 // may introduce illegal operations. 8529 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) 8530 return SDValue(); 8531 8532 unsigned NumInScalars = N->getNumOperands(); 8533 DebugLoc dl = N->getDebugLoc(); 8534 EVT VT = N->getValueType(0); 8535 8536 // Check to see if this is a BUILD_VECTOR of a bunch of values 8537 // which come from any_extend or zero_extend nodes. If so, we can create 8538 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 8539 // optimizations. We do not handle sign-extend because we can't fill the sign 8540 // using shuffles. 8541 EVT SourceType = MVT::Other; 8542 bool AllAnyExt = true; 8543 8544 for (unsigned i = 0; i != NumInScalars; ++i) { 8545 SDValue In = N->getOperand(i); 8546 // Ignore undef inputs. 8547 if (In.getOpcode() == ISD::UNDEF) continue; 8548 8549 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 8550 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 8551 8552 // Abort if the element is not an extension. 8553 if (!ZeroExt && !AnyExt) { 8554 SourceType = MVT::Other; 8555 break; 8556 } 8557 8558 // The input is a ZeroExt or AnyExt. Check the original type. 8559 EVT InTy = In.getOperand(0).getValueType(); 8560 8561 // Check that all of the widened source types are the same. 8562 if (SourceType == MVT::Other) 8563 // First time. 8564 SourceType = InTy; 8565 else if (InTy != SourceType) { 8566 // Multiple income types. Abort. 8567 SourceType = MVT::Other; 8568 break; 8569 } 8570 8571 // Check if all of the extends are ANY_EXTENDs. 8572 AllAnyExt &= AnyExt; 8573 } 8574 8575 // In order to have valid types, all of the inputs must be extended from the 8576 // same source type and all of the inputs must be any or zero extend. 8577 // Scalar sizes must be a power of two. 8578 EVT OutScalarTy = VT.getScalarType(); 8579 bool ValidTypes = SourceType != MVT::Other && 8580 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 8581 isPowerOf2_32(SourceType.getSizeInBits()); 8582 8583 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 8584 // turn into a single shuffle instruction. 8585 if (!ValidTypes) 8586 return SDValue(); 8587 8588 bool isLE = TLI.isLittleEndian(); 8589 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 8590 assert(ElemRatio > 1 && "Invalid element size ratio"); 8591 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 8592 DAG.getConstant(0, SourceType); 8593 8594 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements(); 8595 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 8596 8597 // Populate the new build_vector 8598 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 8599 SDValue Cast = N->getOperand(i); 8600 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 8601 Cast.getOpcode() == ISD::ZERO_EXTEND || 8602 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 8603 SDValue In; 8604 if (Cast.getOpcode() == ISD::UNDEF) 8605 In = DAG.getUNDEF(SourceType); 8606 else 8607 In = Cast->getOperand(0); 8608 unsigned Index = isLE ? (i * ElemRatio) : 8609 (i * ElemRatio + (ElemRatio - 1)); 8610 8611 assert(Index < Ops.size() && "Invalid index"); 8612 Ops[Index] = In; 8613 } 8614 8615 // The type of the new BUILD_VECTOR node. 8616 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 8617 assert(VecVT.getSizeInBits() == VT.getSizeInBits() && 8618 "Invalid vector size"); 8619 // Check if the new vector type is legal. 8620 if (!isTypeLegal(VecVT)) return SDValue(); 8621 8622 // Make the new BUILD_VECTOR. 8623 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size()); 8624 8625 // The new BUILD_VECTOR node has the potential to be further optimized. 8626 AddToWorkList(BV.getNode()); 8627 // Bitcast to the desired type. 8628 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 8629} 8630 8631SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) { 8632 EVT VT = N->getValueType(0); 8633 8634 unsigned NumInScalars = N->getNumOperands(); 8635 DebugLoc dl = N->getDebugLoc(); 8636 8637 EVT SrcVT = MVT::Other; 8638 unsigned Opcode = ISD::DELETED_NODE; 8639 unsigned NumDefs = 0; 8640 8641 for (unsigned i = 0; i != NumInScalars; ++i) { 8642 SDValue In = N->getOperand(i); 8643 unsigned Opc = In.getOpcode(); 8644 8645 if (Opc == ISD::UNDEF) 8646 continue; 8647 8648 // If all scalar values are floats and converted from integers. 8649 if (Opcode == ISD::DELETED_NODE && 8650 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { 8651 Opcode = Opc; 8652 } 8653 8654 if (Opc != Opcode) 8655 return SDValue(); 8656 8657 EVT InVT = In.getOperand(0).getValueType(); 8658 8659 // If all scalar values are typed differently, bail out. It's chosen to 8660 // simplify BUILD_VECTOR of integer types. 8661 if (SrcVT == MVT::Other) 8662 SrcVT = InVT; 8663 if (SrcVT != InVT) 8664 return SDValue(); 8665 NumDefs++; 8666 } 8667 8668 // If the vector has just one element defined, it's not worth to fold it into 8669 // a vectorized one. 8670 if (NumDefs < 2) 8671 return SDValue(); 8672 8673 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) 8674 && "Should only handle conversion from integer to float."); 8675 assert(SrcVT != MVT::Other && "Cannot determine source type!"); 8676 8677 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars); 8678 8679 if (!TLI.isOperationLegalOrCustom(Opcode, NVT)) 8680 return SDValue(); 8681 8682 SmallVector<SDValue, 8> Opnds; 8683 for (unsigned i = 0; i != NumInScalars; ++i) { 8684 SDValue In = N->getOperand(i); 8685 8686 if (In.getOpcode() == ISD::UNDEF) 8687 Opnds.push_back(DAG.getUNDEF(SrcVT)); 8688 else 8689 Opnds.push_back(In.getOperand(0)); 8690 } 8691 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, 8692 &Opnds[0], Opnds.size()); 8693 AddToWorkList(BV.getNode()); 8694 8695 return DAG.getNode(Opcode, dl, VT, BV); 8696} 8697 8698SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 8699 unsigned NumInScalars = N->getNumOperands(); 8700 DebugLoc dl = N->getDebugLoc(); 8701 EVT VT = N->getValueType(0); 8702 8703 // A vector built entirely of undefs is undef. 8704 if (ISD::allOperandsUndef(N)) 8705 return DAG.getUNDEF(VT); 8706 8707 SDValue V = reduceBuildVecExtToExtBuildVec(N); 8708 if (V.getNode()) 8709 return V; 8710 8711 V = reduceBuildVecConvertToConvertBuildVec(N); 8712 if (V.getNode()) 8713 return V; 8714 8715 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 8716 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 8717 // at most two distinct vectors, turn this into a shuffle node. 8718 8719 // May only combine to shuffle after legalize if shuffle is legal. 8720 if (LegalOperations && 8721 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 8722 return SDValue(); 8723 8724 SDValue VecIn1, VecIn2; 8725 for (unsigned i = 0; i != NumInScalars; ++i) { 8726 // Ignore undef inputs. 8727 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 8728 8729 // If this input is something other than a EXTRACT_VECTOR_ELT with a 8730 // constant index, bail out. 8731 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 8732 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 8733 VecIn1 = VecIn2 = SDValue(0, 0); 8734 break; 8735 } 8736 8737 // We allow up to two distinct input vectors. 8738 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 8739 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 8740 continue; 8741 8742 if (VecIn1.getNode() == 0) { 8743 VecIn1 = ExtractedFromVec; 8744 } else if (VecIn2.getNode() == 0) { 8745 VecIn2 = ExtractedFromVec; 8746 } else { 8747 // Too many inputs. 8748 VecIn1 = VecIn2 = SDValue(0, 0); 8749 break; 8750 } 8751 } 8752 8753 // If everything is good, we can make a shuffle operation. 8754 if (VecIn1.getNode()) { 8755 SmallVector<int, 8> Mask; 8756 for (unsigned i = 0; i != NumInScalars; ++i) { 8757 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 8758 Mask.push_back(-1); 8759 continue; 8760 } 8761 8762 // If extracting from the first vector, just use the index directly. 8763 SDValue Extract = N->getOperand(i); 8764 SDValue ExtVal = Extract.getOperand(1); 8765 if (Extract.getOperand(0) == VecIn1) { 8766 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8767 if (ExtIndex > VT.getVectorNumElements()) 8768 return SDValue(); 8769 8770 Mask.push_back(ExtIndex); 8771 continue; 8772 } 8773 8774 // Otherwise, use InIdx + VecSize 8775 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8776 Mask.push_back(Idx+NumInScalars); 8777 } 8778 8779 // We can't generate a shuffle node with mismatched input and output types. 8780 // Attempt to transform a single input vector to the correct type. 8781 if ((VT != VecIn1.getValueType())) { 8782 // We don't support shuffeling between TWO values of different types. 8783 if (VecIn2.getNode() != 0) 8784 return SDValue(); 8785 8786 // We only support widening of vectors which are half the size of the 8787 // output registers. For example XMM->YMM widening on X86 with AVX. 8788 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 8789 return SDValue(); 8790 8791 // If the input vector type has a different base type to the output 8792 // vector type, bail out. 8793 if (VecIn1.getValueType().getVectorElementType() != 8794 VT.getVectorElementType()) 8795 return SDValue(); 8796 8797 // Widen the input vector by adding undef values. 8798 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8799 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 8800 } 8801 8802 // If VecIn2 is unused then change it to undef. 8803 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 8804 8805 // Check that we were able to transform all incoming values to the same 8806 // type. 8807 if (VecIn2.getValueType() != VecIn1.getValueType() || 8808 VecIn1.getValueType() != VT) 8809 return SDValue(); 8810 8811 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 8812 if (!isTypeLegal(VT)) 8813 return SDValue(); 8814 8815 // Return the new VECTOR_SHUFFLE node. 8816 SDValue Ops[2]; 8817 Ops[0] = VecIn1; 8818 Ops[1] = VecIn2; 8819 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]); 8820 } 8821 8822 return SDValue(); 8823} 8824 8825SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 8826 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 8827 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 8828 // inputs come from at most two distinct vectors, turn this into a shuffle 8829 // node. 8830 8831 // If we only have one input vector, we don't need to do any concatenation. 8832 if (N->getNumOperands() == 1) 8833 return N->getOperand(0); 8834 8835 // Check if all of the operands are undefs. 8836 if (ISD::allOperandsUndef(N)) 8837 return DAG.getUNDEF(N->getValueType(0)); 8838 8839 return SDValue(); 8840} 8841 8842SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 8843 EVT NVT = N->getValueType(0); 8844 SDValue V = N->getOperand(0); 8845 8846 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 8847 // Handle only simple case where vector being inserted and vector 8848 // being extracted are of same type, and are half size of larger vectors. 8849 EVT BigVT = V->getOperand(0).getValueType(); 8850 EVT SmallVT = V->getOperand(1).getValueType(); 8851 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 8852 return SDValue(); 8853 8854 // Only handle cases where both indexes are constants with the same type. 8855 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8856 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 8857 8858 if (InsIdx && ExtIdx && 8859 InsIdx->getValueType(0).getSizeInBits() <= 64 && 8860 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 8861 // Combine: 8862 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 8863 // Into: 8864 // indices are equal => V1 8865 // otherwise => (extract_subvec V1, ExtIdx) 8866 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 8867 return V->getOperand(1); 8868 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 8869 V->getOperand(0), N->getOperand(1)); 8870 } 8871 } 8872 8873 if (V->getOpcode() == ISD::CONCAT_VECTORS) { 8874 // Combine: 8875 // (extract_subvec (concat V1, V2, ...), i) 8876 // Into: 8877 // Vi if possible 8878 // Only operand 0 is checked as 'concat' assumes all inputs of the same type. 8879 if (V->getOperand(0).getValueType() != NVT) 8880 return SDValue(); 8881 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 8882 unsigned NumElems = NVT.getVectorNumElements(); 8883 assert((Idx % NumElems) == 0 && 8884 "IDX in concat is not a multiple of the result vector length."); 8885 return V->getOperand(Idx / NumElems); 8886 } 8887 8888 return SDValue(); 8889} 8890 8891SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 8892 EVT VT = N->getValueType(0); 8893 unsigned NumElts = VT.getVectorNumElements(); 8894 8895 SDValue N0 = N->getOperand(0); 8896 SDValue N1 = N->getOperand(1); 8897 8898 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 8899 8900 // Canonicalize shuffle undef, undef -> undef 8901 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 8902 return DAG.getUNDEF(VT); 8903 8904 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8905 8906 // Canonicalize shuffle v, v -> v, undef 8907 if (N0 == N1) { 8908 SmallVector<int, 8> NewMask; 8909 for (unsigned i = 0; i != NumElts; ++i) { 8910 int Idx = SVN->getMaskElt(i); 8911 if (Idx >= (int)NumElts) Idx -= NumElts; 8912 NewMask.push_back(Idx); 8913 } 8914 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 8915 &NewMask[0]); 8916 } 8917 8918 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 8919 if (N0.getOpcode() == ISD::UNDEF) { 8920 SmallVector<int, 8> NewMask; 8921 for (unsigned i = 0; i != NumElts; ++i) { 8922 int Idx = SVN->getMaskElt(i); 8923 if (Idx >= 0) { 8924 if (Idx < (int)NumElts) 8925 Idx += NumElts; 8926 else 8927 Idx -= NumElts; 8928 } 8929 NewMask.push_back(Idx); 8930 } 8931 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 8932 &NewMask[0]); 8933 } 8934 8935 // Remove references to rhs if it is undef 8936 if (N1.getOpcode() == ISD::UNDEF) { 8937 bool Changed = false; 8938 SmallVector<int, 8> NewMask; 8939 for (unsigned i = 0; i != NumElts; ++i) { 8940 int Idx = SVN->getMaskElt(i); 8941 if (Idx >= (int)NumElts) { 8942 Idx = -1; 8943 Changed = true; 8944 } 8945 NewMask.push_back(Idx); 8946 } 8947 if (Changed) 8948 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 8949 } 8950 8951 // If it is a splat, check if the argument vector is another splat or a 8952 // build_vector with all scalar elements the same. 8953 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 8954 SDNode *V = N0.getNode(); 8955 8956 // If this is a bit convert that changes the element type of the vector but 8957 // not the number of vector elements, look through it. Be careful not to 8958 // look though conversions that change things like v4f32 to v2f64. 8959 if (V->getOpcode() == ISD::BITCAST) { 8960 SDValue ConvInput = V->getOperand(0); 8961 if (ConvInput.getValueType().isVector() && 8962 ConvInput.getValueType().getVectorNumElements() == NumElts) 8963 V = ConvInput.getNode(); 8964 } 8965 8966 if (V->getOpcode() == ISD::BUILD_VECTOR) { 8967 assert(V->getNumOperands() == NumElts && 8968 "BUILD_VECTOR has wrong number of operands"); 8969 SDValue Base; 8970 bool AllSame = true; 8971 for (unsigned i = 0; i != NumElts; ++i) { 8972 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 8973 Base = V->getOperand(i); 8974 break; 8975 } 8976 } 8977 // Splat of <u, u, u, u>, return <u, u, u, u> 8978 if (!Base.getNode()) 8979 return N0; 8980 for (unsigned i = 0; i != NumElts; ++i) { 8981 if (V->getOperand(i) != Base) { 8982 AllSame = false; 8983 break; 8984 } 8985 } 8986 // Splat of <x, x, x, x>, return <x, x, x, x> 8987 if (AllSame) 8988 return N0; 8989 } 8990 } 8991 8992 // If this shuffle node is simply a swizzle of another shuffle node, 8993 // and it reverses the swizzle of the previous shuffle then we can 8994 // optimize shuffle(shuffle(x, undef), undef) -> x. 8995 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 8996 N1.getOpcode() == ISD::UNDEF) { 8997 8998 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 8999 9000 // Shuffle nodes can only reverse shuffles with a single non-undef value. 9001 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 9002 return SDValue(); 9003 9004 // The incoming shuffle must be of the same type as the result of the 9005 // current shuffle. 9006 assert(OtherSV->getOperand(0).getValueType() == VT && 9007 "Shuffle types don't match"); 9008 9009 for (unsigned i = 0; i != NumElts; ++i) { 9010 int Idx = SVN->getMaskElt(i); 9011 assert(Idx < (int)NumElts && "Index references undef operand"); 9012 // Next, this index comes from the first value, which is the incoming 9013 // shuffle. Adopt the incoming index. 9014 if (Idx >= 0) 9015 Idx = OtherSV->getMaskElt(Idx); 9016 9017 // The combined shuffle must map each index to itself. 9018 if (Idx >= 0 && (unsigned)Idx != i) 9019 return SDValue(); 9020 } 9021 9022 return OtherSV->getOperand(0); 9023 } 9024 9025 return SDValue(); 9026} 9027 9028SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 9029 if (!TLI.getShouldFoldAtomicFences()) 9030 return SDValue(); 9031 9032 SDValue atomic = N->getOperand(0); 9033 switch (atomic.getOpcode()) { 9034 case ISD::ATOMIC_CMP_SWAP: 9035 case ISD::ATOMIC_SWAP: 9036 case ISD::ATOMIC_LOAD_ADD: 9037 case ISD::ATOMIC_LOAD_SUB: 9038 case ISD::ATOMIC_LOAD_AND: 9039 case ISD::ATOMIC_LOAD_OR: 9040 case ISD::ATOMIC_LOAD_XOR: 9041 case ISD::ATOMIC_LOAD_NAND: 9042 case ISD::ATOMIC_LOAD_MIN: 9043 case ISD::ATOMIC_LOAD_MAX: 9044 case ISD::ATOMIC_LOAD_UMIN: 9045 case ISD::ATOMIC_LOAD_UMAX: 9046 break; 9047 default: 9048 return SDValue(); 9049 } 9050 9051 SDValue fence = atomic.getOperand(0); 9052 if (fence.getOpcode() != ISD::MEMBARRIER) 9053 return SDValue(); 9054 9055 switch (atomic.getOpcode()) { 9056 case ISD::ATOMIC_CMP_SWAP: 9057 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 9058 fence.getOperand(0), 9059 atomic.getOperand(1), atomic.getOperand(2), 9060 atomic.getOperand(3)), atomic.getResNo()); 9061 case ISD::ATOMIC_SWAP: 9062 case ISD::ATOMIC_LOAD_ADD: 9063 case ISD::ATOMIC_LOAD_SUB: 9064 case ISD::ATOMIC_LOAD_AND: 9065 case ISD::ATOMIC_LOAD_OR: 9066 case ISD::ATOMIC_LOAD_XOR: 9067 case ISD::ATOMIC_LOAD_NAND: 9068 case ISD::ATOMIC_LOAD_MIN: 9069 case ISD::ATOMIC_LOAD_MAX: 9070 case ISD::ATOMIC_LOAD_UMIN: 9071 case ISD::ATOMIC_LOAD_UMAX: 9072 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 9073 fence.getOperand(0), 9074 atomic.getOperand(1), atomic.getOperand(2)), 9075 atomic.getResNo()); 9076 default: 9077 return SDValue(); 9078 } 9079} 9080 9081/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 9082/// an AND to a vector_shuffle with the destination vector and a zero vector. 9083/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 9084/// vector_shuffle V, Zero, <0, 4, 2, 4> 9085SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 9086 EVT VT = N->getValueType(0); 9087 DebugLoc dl = N->getDebugLoc(); 9088 SDValue LHS = N->getOperand(0); 9089 SDValue RHS = N->getOperand(1); 9090 if (N->getOpcode() == ISD::AND) { 9091 if (RHS.getOpcode() == ISD::BITCAST) 9092 RHS = RHS.getOperand(0); 9093 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 9094 SmallVector<int, 8> Indices; 9095 unsigned NumElts = RHS.getNumOperands(); 9096 for (unsigned i = 0; i != NumElts; ++i) { 9097 SDValue Elt = RHS.getOperand(i); 9098 if (!isa<ConstantSDNode>(Elt)) 9099 return SDValue(); 9100 9101 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 9102 Indices.push_back(i); 9103 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 9104 Indices.push_back(NumElts); 9105 else 9106 return SDValue(); 9107 } 9108 9109 // Let's see if the target supports this vector_shuffle. 9110 EVT RVT = RHS.getValueType(); 9111 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 9112 return SDValue(); 9113 9114 // Return the new VECTOR_SHUFFLE node. 9115 EVT EltVT = RVT.getVectorElementType(); 9116 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 9117 DAG.getConstant(0, EltVT)); 9118 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9119 RVT, &ZeroOps[0], ZeroOps.size()); 9120 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 9121 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 9122 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 9123 } 9124 } 9125 9126 return SDValue(); 9127} 9128 9129/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 9130SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 9131 // After legalize, the target may be depending on adds and other 9132 // binary ops to provide legal ways to construct constants or other 9133 // things. Simplifying them may result in a loss of legality. 9134 if (LegalOperations) return SDValue(); 9135 9136 assert(N->getValueType(0).isVector() && 9137 "SimplifyVBinOp only works on vectors!"); 9138 9139 SDValue LHS = N->getOperand(0); 9140 SDValue RHS = N->getOperand(1); 9141 SDValue Shuffle = XformToShuffleWithZero(N); 9142 if (Shuffle.getNode()) return Shuffle; 9143 9144 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 9145 // this operation. 9146 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 9147 RHS.getOpcode() == ISD::BUILD_VECTOR) { 9148 SmallVector<SDValue, 8> Ops; 9149 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 9150 SDValue LHSOp = LHS.getOperand(i); 9151 SDValue RHSOp = RHS.getOperand(i); 9152 // If these two elements can't be folded, bail out. 9153 if ((LHSOp.getOpcode() != ISD::UNDEF && 9154 LHSOp.getOpcode() != ISD::Constant && 9155 LHSOp.getOpcode() != ISD::ConstantFP) || 9156 (RHSOp.getOpcode() != ISD::UNDEF && 9157 RHSOp.getOpcode() != ISD::Constant && 9158 RHSOp.getOpcode() != ISD::ConstantFP)) 9159 break; 9160 9161 // Can't fold divide by zero. 9162 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 9163 N->getOpcode() == ISD::FDIV) { 9164 if ((RHSOp.getOpcode() == ISD::Constant && 9165 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 9166 (RHSOp.getOpcode() == ISD::ConstantFP && 9167 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 9168 break; 9169 } 9170 9171 EVT VT = LHSOp.getValueType(); 9172 EVT RVT = RHSOp.getValueType(); 9173 if (RVT != VT) { 9174 // Integer BUILD_VECTOR operands may have types larger than the element 9175 // size (e.g., when the element type is not legal). Prior to type 9176 // legalization, the types may not match between the two BUILD_VECTORS. 9177 // Truncate one of the operands to make them match. 9178 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 9179 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 9180 } else { 9181 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 9182 VT = RVT; 9183 } 9184 } 9185 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 9186 LHSOp, RHSOp); 9187 if (FoldOp.getOpcode() != ISD::UNDEF && 9188 FoldOp.getOpcode() != ISD::Constant && 9189 FoldOp.getOpcode() != ISD::ConstantFP) 9190 break; 9191 Ops.push_back(FoldOp); 9192 AddToWorkList(FoldOp.getNode()); 9193 } 9194 9195 if (Ops.size() == LHS.getNumOperands()) 9196 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9197 LHS.getValueType(), &Ops[0], Ops.size()); 9198 } 9199 9200 return SDValue(); 9201} 9202 9203/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 9204SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 9205 // After legalize, the target may be depending on adds and other 9206 // binary ops to provide legal ways to construct constants or other 9207 // things. Simplifying them may result in a loss of legality. 9208 if (LegalOperations) return SDValue(); 9209 9210 assert(N->getValueType(0).isVector() && 9211 "SimplifyVUnaryOp only works on vectors!"); 9212 9213 SDValue N0 = N->getOperand(0); 9214 9215 if (N0.getOpcode() != ISD::BUILD_VECTOR) 9216 return SDValue(); 9217 9218 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 9219 SmallVector<SDValue, 8> Ops; 9220 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 9221 SDValue Op = N0.getOperand(i); 9222 if (Op.getOpcode() != ISD::UNDEF && 9223 Op.getOpcode() != ISD::ConstantFP) 9224 break; 9225 EVT EltVT = Op.getValueType(); 9226 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op); 9227 if (FoldOp.getOpcode() != ISD::UNDEF && 9228 FoldOp.getOpcode() != ISD::ConstantFP) 9229 break; 9230 Ops.push_back(FoldOp); 9231 AddToWorkList(FoldOp.getNode()); 9232 } 9233 9234 if (Ops.size() != N0.getNumOperands()) 9235 return SDValue(); 9236 9237 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9238 N0.getValueType(), &Ops[0], Ops.size()); 9239} 9240 9241SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 9242 SDValue N1, SDValue N2){ 9243 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 9244 9245 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 9246 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 9247 9248 // If we got a simplified select_cc node back from SimplifySelectCC, then 9249 // break it down into a new SETCC node, and a new SELECT node, and then return 9250 // the SELECT node, since we were called with a SELECT node. 9251 if (SCC.getNode()) { 9252 // Check to see if we got a select_cc back (to turn into setcc/select). 9253 // Otherwise, just return whatever node we got back, like fabs. 9254 if (SCC.getOpcode() == ISD::SELECT_CC) { 9255 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 9256 N0.getValueType(), 9257 SCC.getOperand(0), SCC.getOperand(1), 9258 SCC.getOperand(4)); 9259 AddToWorkList(SETCC.getNode()); 9260 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 9261 SCC.getOperand(2), SCC.getOperand(3), SETCC); 9262 } 9263 9264 return SCC; 9265 } 9266 return SDValue(); 9267} 9268 9269/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 9270/// are the two values being selected between, see if we can simplify the 9271/// select. Callers of this should assume that TheSelect is deleted if this 9272/// returns true. As such, they should return the appropriate thing (e.g. the 9273/// node) back to the top-level of the DAG combiner loop to avoid it being 9274/// looked at. 9275bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 9276 SDValue RHS) { 9277 9278 // Cannot simplify select with vector condition 9279 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 9280 9281 // If this is a select from two identical things, try to pull the operation 9282 // through the select. 9283 if (LHS.getOpcode() != RHS.getOpcode() || 9284 !LHS.hasOneUse() || !RHS.hasOneUse()) 9285 return false; 9286 9287 // If this is a load and the token chain is identical, replace the select 9288 // of two loads with a load through a select of the address to load from. 9289 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 9290 // constants have been dropped into the constant pool. 9291 if (LHS.getOpcode() == ISD::LOAD) { 9292 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 9293 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 9294 9295 // Token chains must be identical. 9296 if (LHS.getOperand(0) != RHS.getOperand(0) || 9297 // Do not let this transformation reduce the number of volatile loads. 9298 LLD->isVolatile() || RLD->isVolatile() || 9299 // If this is an EXTLOAD, the VT's must match. 9300 LLD->getMemoryVT() != RLD->getMemoryVT() || 9301 // If this is an EXTLOAD, the kind of extension must match. 9302 (LLD->getExtensionType() != RLD->getExtensionType() && 9303 // The only exception is if one of the extensions is anyext. 9304 LLD->getExtensionType() != ISD::EXTLOAD && 9305 RLD->getExtensionType() != ISD::EXTLOAD) || 9306 // FIXME: this discards src value information. This is 9307 // over-conservative. It would be beneficial to be able to remember 9308 // both potential memory locations. Since we are discarding 9309 // src value info, don't do the transformation if the memory 9310 // locations are not in the default address space. 9311 LLD->getPointerInfo().getAddrSpace() != 0 || 9312 RLD->getPointerInfo().getAddrSpace() != 0) 9313 return false; 9314 9315 // Check that the select condition doesn't reach either load. If so, 9316 // folding this will induce a cycle into the DAG. If not, this is safe to 9317 // xform, so create a select of the addresses. 9318 SDValue Addr; 9319 if (TheSelect->getOpcode() == ISD::SELECT) { 9320 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 9321 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 9322 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 9323 return false; 9324 // The loads must not depend on one another. 9325 if (LLD->isPredecessorOf(RLD) || 9326 RLD->isPredecessorOf(LLD)) 9327 return false; 9328 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 9329 LLD->getBasePtr().getValueType(), 9330 TheSelect->getOperand(0), LLD->getBasePtr(), 9331 RLD->getBasePtr()); 9332 } else { // Otherwise SELECT_CC 9333 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 9334 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 9335 9336 if ((LLD->hasAnyUseOfValue(1) && 9337 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 9338 (RLD->hasAnyUseOfValue(1) && 9339 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 9340 return false; 9341 9342 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 9343 LLD->getBasePtr().getValueType(), 9344 TheSelect->getOperand(0), 9345 TheSelect->getOperand(1), 9346 LLD->getBasePtr(), RLD->getBasePtr(), 9347 TheSelect->getOperand(4)); 9348 } 9349 9350 SDValue Load; 9351 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 9352 Load = DAG.getLoad(TheSelect->getValueType(0), 9353 TheSelect->getDebugLoc(), 9354 // FIXME: Discards pointer info. 9355 LLD->getChain(), Addr, MachinePointerInfo(), 9356 LLD->isVolatile(), LLD->isNonTemporal(), 9357 LLD->isInvariant(), LLD->getAlignment()); 9358 } else { 9359 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 9360 RLD->getExtensionType() : LLD->getExtensionType(), 9361 TheSelect->getDebugLoc(), 9362 TheSelect->getValueType(0), 9363 // FIXME: Discards pointer info. 9364 LLD->getChain(), Addr, MachinePointerInfo(), 9365 LLD->getMemoryVT(), LLD->isVolatile(), 9366 LLD->isNonTemporal(), LLD->getAlignment()); 9367 } 9368 9369 // Users of the select now use the result of the load. 9370 CombineTo(TheSelect, Load); 9371 9372 // Users of the old loads now use the new load's chain. We know the 9373 // old-load value is dead now. 9374 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 9375 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 9376 return true; 9377 } 9378 9379 return false; 9380} 9381 9382/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 9383/// where 'cond' is the comparison specified by CC. 9384SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 9385 SDValue N2, SDValue N3, 9386 ISD::CondCode CC, bool NotExtCompare) { 9387 // (x ? y : y) -> y. 9388 if (N2 == N3) return N2; 9389 9390 EVT VT = N2.getValueType(); 9391 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 9392 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 9393 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 9394 9395 // Determine if the condition we're dealing with is constant 9396 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 9397 N0, N1, CC, DL, false); 9398 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 9399 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 9400 9401 // fold select_cc true, x, y -> x 9402 if (SCCC && !SCCC->isNullValue()) 9403 return N2; 9404 // fold select_cc false, x, y -> y 9405 if (SCCC && SCCC->isNullValue()) 9406 return N3; 9407 9408 // Check to see if we can simplify the select into an fabs node 9409 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 9410 // Allow either -0.0 or 0.0 9411 if (CFP->getValueAPF().isZero()) { 9412 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 9413 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 9414 N0 == N2 && N3.getOpcode() == ISD::FNEG && 9415 N2 == N3.getOperand(0)) 9416 return DAG.getNode(ISD::FABS, DL, VT, N0); 9417 9418 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 9419 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 9420 N0 == N3 && N2.getOpcode() == ISD::FNEG && 9421 N2.getOperand(0) == N3) 9422 return DAG.getNode(ISD::FABS, DL, VT, N3); 9423 } 9424 } 9425 9426 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 9427 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 9428 // in it. This is a win when the constant is not otherwise available because 9429 // it replaces two constant pool loads with one. We only do this if the FP 9430 // type is known to be legal, because if it isn't, then we are before legalize 9431 // types an we want the other legalization to happen first (e.g. to avoid 9432 // messing with soft float) and if the ConstantFP is not legal, because if 9433 // it is legal, we may not need to store the FP constant in a constant pool. 9434 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 9435 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 9436 if (TLI.isTypeLegal(N2.getValueType()) && 9437 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 9438 TargetLowering::Legal) && 9439 // If both constants have multiple uses, then we won't need to do an 9440 // extra load, they are likely around in registers for other users. 9441 (TV->hasOneUse() || FV->hasOneUse())) { 9442 Constant *Elts[] = { 9443 const_cast<ConstantFP*>(FV->getConstantFPValue()), 9444 const_cast<ConstantFP*>(TV->getConstantFPValue()) 9445 }; 9446 Type *FPTy = Elts[0]->getType(); 9447 const DataLayout &TD = *TLI.getDataLayout(); 9448 9449 // Create a ConstantArray of the two constants. 9450 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 9451 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 9452 TD.getPrefTypeAlignment(FPTy)); 9453 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 9454 9455 // Get the offsets to the 0 and 1 element of the array so that we can 9456 // select between them. 9457 SDValue Zero = DAG.getIntPtrConstant(0); 9458 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 9459 SDValue One = DAG.getIntPtrConstant(EltSize); 9460 9461 SDValue Cond = DAG.getSetCC(DL, 9462 TLI.getSetCCResultType(N0.getValueType()), 9463 N0, N1, CC); 9464 AddToWorkList(Cond.getNode()); 9465 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 9466 Cond, One, Zero); 9467 AddToWorkList(CstOffset.getNode()); 9468 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 9469 CstOffset); 9470 AddToWorkList(CPIdx.getNode()); 9471 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 9472 MachinePointerInfo::getConstantPool(), false, 9473 false, false, Alignment); 9474 9475 } 9476 } 9477 9478 // Check to see if we can perform the "gzip trick", transforming 9479 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 9480 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 9481 (N1C->isNullValue() || // (a < 0) ? b : 0 9482 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 9483 EVT XType = N0.getValueType(); 9484 EVT AType = N2.getValueType(); 9485 if (XType.bitsGE(AType)) { 9486 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 9487 // single-bit constant. 9488 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 9489 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 9490 ShCtV = XType.getSizeInBits()-ShCtV-1; 9491 SDValue ShCt = DAG.getConstant(ShCtV, 9492 getShiftAmountTy(N0.getValueType())); 9493 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 9494 XType, N0, ShCt); 9495 AddToWorkList(Shift.getNode()); 9496 9497 if (XType.bitsGT(AType)) { 9498 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9499 AddToWorkList(Shift.getNode()); 9500 } 9501 9502 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9503 } 9504 9505 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 9506 XType, N0, 9507 DAG.getConstant(XType.getSizeInBits()-1, 9508 getShiftAmountTy(N0.getValueType()))); 9509 AddToWorkList(Shift.getNode()); 9510 9511 if (XType.bitsGT(AType)) { 9512 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9513 AddToWorkList(Shift.getNode()); 9514 } 9515 9516 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9517 } 9518 } 9519 9520 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 9521 // where y is has a single bit set. 9522 // A plaintext description would be, we can turn the SELECT_CC into an AND 9523 // when the condition can be materialized as an all-ones register. Any 9524 // single bit-test can be materialized as an all-ones register with 9525 // shift-left and shift-right-arith. 9526 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 9527 N0->getValueType(0) == VT && 9528 N1C && N1C->isNullValue() && 9529 N2C && N2C->isNullValue()) { 9530 SDValue AndLHS = N0->getOperand(0); 9531 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 9532 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 9533 // Shift the tested bit over the sign bit. 9534 APInt AndMask = ConstAndRHS->getAPIntValue(); 9535 SDValue ShlAmt = 9536 DAG.getConstant(AndMask.countLeadingZeros(), 9537 getShiftAmountTy(AndLHS.getValueType())); 9538 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 9539 9540 // Now arithmetic right shift it all the way over, so the result is either 9541 // all-ones, or zero. 9542 SDValue ShrAmt = 9543 DAG.getConstant(AndMask.getBitWidth()-1, 9544 getShiftAmountTy(Shl.getValueType())); 9545 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 9546 9547 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 9548 } 9549 } 9550 9551 // fold select C, 16, 0 -> shl C, 4 9552 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 9553 TLI.getBooleanContents(N0.getValueType().isVector()) == 9554 TargetLowering::ZeroOrOneBooleanContent) { 9555 9556 // If the caller doesn't want us to simplify this into a zext of a compare, 9557 // don't do it. 9558 if (NotExtCompare && N2C->getAPIntValue() == 1) 9559 return SDValue(); 9560 9561 // Get a SetCC of the condition 9562 // NOTE: Don't create a SETCC if it's not legal on this target. 9563 if (!LegalOperations || 9564 TLI.isOperationLegal(ISD::SETCC, 9565 LegalTypes ? TLI.getSetCCResultType(N0.getValueType()) : MVT::i1)) { 9566 SDValue Temp, SCC; 9567 // cast from setcc result type to select result type 9568 if (LegalTypes) { 9569 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 9570 N0, N1, CC); 9571 if (N2.getValueType().bitsLT(SCC.getValueType())) 9572 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), 9573 N2.getValueType()); 9574 else 9575 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9576 N2.getValueType(), SCC); 9577 } else { 9578 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 9579 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9580 N2.getValueType(), SCC); 9581 } 9582 9583 AddToWorkList(SCC.getNode()); 9584 AddToWorkList(Temp.getNode()); 9585 9586 if (N2C->getAPIntValue() == 1) 9587 return Temp; 9588 9589 // shl setcc result by log2 n2c 9590 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 9591 DAG.getConstant(N2C->getAPIntValue().logBase2(), 9592 getShiftAmountTy(Temp.getValueType()))); 9593 } 9594 } 9595 9596 // Check to see if this is the equivalent of setcc 9597 // FIXME: Turn all of these into setcc if setcc if setcc is legal 9598 // otherwise, go ahead with the folds. 9599 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 9600 EVT XType = N0.getValueType(); 9601 if (!LegalOperations || 9602 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 9603 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 9604 if (Res.getValueType() != VT) 9605 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 9606 return Res; 9607 } 9608 9609 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 9610 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 9611 (!LegalOperations || 9612 TLI.isOperationLegal(ISD::CTLZ, XType))) { 9613 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 9614 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 9615 DAG.getConstant(Log2_32(XType.getSizeInBits()), 9616 getShiftAmountTy(Ctlz.getValueType()))); 9617 } 9618 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 9619 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 9620 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 9621 XType, DAG.getConstant(0, XType), N0); 9622 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 9623 return DAG.getNode(ISD::SRL, DL, XType, 9624 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 9625 DAG.getConstant(XType.getSizeInBits()-1, 9626 getShiftAmountTy(XType))); 9627 } 9628 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 9629 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 9630 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 9631 DAG.getConstant(XType.getSizeInBits()-1, 9632 getShiftAmountTy(N0.getValueType()))); 9633 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 9634 } 9635 } 9636 9637 // Check to see if this is an integer abs. 9638 // select_cc setg[te] X, 0, X, -X -> 9639 // select_cc setgt X, -1, X, -X -> 9640 // select_cc setl[te] X, 0, -X, X -> 9641 // select_cc setlt X, 1, -X, X -> 9642 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 9643 if (N1C) { 9644 ConstantSDNode *SubC = NULL; 9645 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 9646 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 9647 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 9648 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 9649 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 9650 (N1C->isOne() && CC == ISD::SETLT)) && 9651 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 9652 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 9653 9654 EVT XType = N0.getValueType(); 9655 if (SubC && SubC->isNullValue() && XType.isInteger()) { 9656 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 9657 N0, 9658 DAG.getConstant(XType.getSizeInBits()-1, 9659 getShiftAmountTy(N0.getValueType()))); 9660 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 9661 XType, N0, Shift); 9662 AddToWorkList(Shift.getNode()); 9663 AddToWorkList(Add.getNode()); 9664 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 9665 } 9666 } 9667 9668 return SDValue(); 9669} 9670 9671/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 9672SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 9673 SDValue N1, ISD::CondCode Cond, 9674 DebugLoc DL, bool foldBooleans) { 9675 TargetLowering::DAGCombinerInfo 9676 DagCombineInfo(DAG, Level, false, this); 9677 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 9678} 9679 9680/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 9681/// return a DAG expression to select that will generate the same value by 9682/// multiplying by a magic number. See: 9683/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9684SDValue DAGCombiner::BuildSDIV(SDNode *N) { 9685 std::vector<SDNode*> Built; 9686 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 9687 9688 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9689 ii != ee; ++ii) 9690 AddToWorkList(*ii); 9691 return S; 9692} 9693 9694/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 9695/// return a DAG expression to select that will generate the same value by 9696/// multiplying by a magic number. See: 9697/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9698SDValue DAGCombiner::BuildUDIV(SDNode *N) { 9699 std::vector<SDNode*> Built; 9700 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 9701 9702 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9703 ii != ee; ++ii) 9704 AddToWorkList(*ii); 9705 return S; 9706} 9707 9708/// FindBaseOffset - Return true if base is a frame index, which is known not 9709// to alias with anything but itself. Provides base object and offset as 9710// results. 9711static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 9712 const GlobalValue *&GV, const void *&CV) { 9713 // Assume it is a primitive operation. 9714 Base = Ptr; Offset = 0; GV = 0; CV = 0; 9715 9716 // If it's an adding a simple constant then integrate the offset. 9717 if (Base.getOpcode() == ISD::ADD) { 9718 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 9719 Base = Base.getOperand(0); 9720 Offset += C->getZExtValue(); 9721 } 9722 } 9723 9724 // Return the underlying GlobalValue, and update the Offset. Return false 9725 // for GlobalAddressSDNode since the same GlobalAddress may be represented 9726 // by multiple nodes with different offsets. 9727 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 9728 GV = G->getGlobal(); 9729 Offset += G->getOffset(); 9730 return false; 9731 } 9732 9733 // Return the underlying Constant value, and update the Offset. Return false 9734 // for ConstantSDNodes since the same constant pool entry may be represented 9735 // by multiple nodes with different offsets. 9736 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 9737 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 9738 : (const void *)C->getConstVal(); 9739 Offset += C->getOffset(); 9740 return false; 9741 } 9742 // If it's any of the following then it can't alias with anything but itself. 9743 return isa<FrameIndexSDNode>(Base); 9744} 9745 9746/// isAlias - Return true if there is any possibility that the two addresses 9747/// overlap. 9748bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 9749 const Value *SrcValue1, int SrcValueOffset1, 9750 unsigned SrcValueAlign1, 9751 const MDNode *TBAAInfo1, 9752 SDValue Ptr2, int64_t Size2, 9753 const Value *SrcValue2, int SrcValueOffset2, 9754 unsigned SrcValueAlign2, 9755 const MDNode *TBAAInfo2) const { 9756 // If they are the same then they must be aliases. 9757 if (Ptr1 == Ptr2) return true; 9758 9759 // Gather base node and offset information. 9760 SDValue Base1, Base2; 9761 int64_t Offset1, Offset2; 9762 const GlobalValue *GV1, *GV2; 9763 const void *CV1, *CV2; 9764 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 9765 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 9766 9767 // If they have a same base address then check to see if they overlap. 9768 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 9769 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9770 9771 // It is possible for different frame indices to alias each other, mostly 9772 // when tail call optimization reuses return address slots for arguments. 9773 // To catch this case, look up the actual index of frame indices to compute 9774 // the real alias relationship. 9775 if (isFrameIndex1 && isFrameIndex2) { 9776 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9777 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 9778 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 9779 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9780 } 9781 9782 // Otherwise, if we know what the bases are, and they aren't identical, then 9783 // we know they cannot alias. 9784 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 9785 return false; 9786 9787 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 9788 // compared to the size and offset of the access, we may be able to prove they 9789 // do not alias. This check is conservative for now to catch cases created by 9790 // splitting vector types. 9791 if ((SrcValueAlign1 == SrcValueAlign2) && 9792 (SrcValueOffset1 != SrcValueOffset2) && 9793 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 9794 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 9795 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 9796 9797 // There is no overlap between these relatively aligned accesses of similar 9798 // size, return no alias. 9799 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 9800 return false; 9801 } 9802 9803 if (CombinerGlobalAA) { 9804 // Use alias analysis information. 9805 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 9806 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 9807 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 9808 AliasAnalysis::AliasResult AAResult = 9809 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 9810 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 9811 if (AAResult == AliasAnalysis::NoAlias) 9812 return false; 9813 } 9814 9815 // Otherwise we have to assume they alias. 9816 return true; 9817} 9818 9819bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) { 9820 SDValue Ptr0, Ptr1; 9821 int64_t Size0, Size1; 9822 const Value *SrcValue0, *SrcValue1; 9823 int SrcValueOffset0, SrcValueOffset1; 9824 unsigned SrcValueAlign0, SrcValueAlign1; 9825 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1; 9826 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0, 9827 SrcValueAlign0, SrcTBAAInfo0); 9828 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1, 9829 SrcValueAlign1, SrcTBAAInfo1); 9830 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0, 9831 SrcValueAlign0, SrcTBAAInfo0, 9832 Ptr1, Size1, SrcValue1, SrcValueOffset1, 9833 SrcValueAlign1, SrcTBAAInfo1); 9834} 9835 9836/// FindAliasInfo - Extracts the relevant alias information from the memory 9837/// node. Returns true if the operand was a load. 9838bool DAGCombiner::FindAliasInfo(SDNode *N, 9839 SDValue &Ptr, int64_t &Size, 9840 const Value *&SrcValue, 9841 int &SrcValueOffset, 9842 unsigned &SrcValueAlign, 9843 const MDNode *&TBAAInfo) const { 9844 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 9845 9846 Ptr = LS->getBasePtr(); 9847 Size = LS->getMemoryVT().getSizeInBits() >> 3; 9848 SrcValue = LS->getSrcValue(); 9849 SrcValueOffset = LS->getSrcValueOffset(); 9850 SrcValueAlign = LS->getOriginalAlignment(); 9851 TBAAInfo = LS->getTBAAInfo(); 9852 return isa<LoadSDNode>(LS); 9853} 9854 9855/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 9856/// looking for aliasing nodes and adding them to the Aliases vector. 9857void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 9858 SmallVector<SDValue, 8> &Aliases) { 9859 SmallVector<SDValue, 8> Chains; // List of chains to visit. 9860 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 9861 9862 // Get alias information for node. 9863 SDValue Ptr; 9864 int64_t Size; 9865 const Value *SrcValue; 9866 int SrcValueOffset; 9867 unsigned SrcValueAlign; 9868 const MDNode *SrcTBAAInfo; 9869 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 9870 SrcValueAlign, SrcTBAAInfo); 9871 9872 // Starting off. 9873 Chains.push_back(OriginalChain); 9874 unsigned Depth = 0; 9875 9876 // Look at each chain and determine if it is an alias. If so, add it to the 9877 // aliases list. If not, then continue up the chain looking for the next 9878 // candidate. 9879 while (!Chains.empty()) { 9880 SDValue Chain = Chains.back(); 9881 Chains.pop_back(); 9882 9883 // For TokenFactor nodes, look at each operand and only continue up the 9884 // chain until we find two aliases. If we've seen two aliases, assume we'll 9885 // find more and revert to original chain since the xform is unlikely to be 9886 // profitable. 9887 // 9888 // FIXME: The depth check could be made to return the last non-aliasing 9889 // chain we found before we hit a tokenfactor rather than the original 9890 // chain. 9891 if (Depth > 6 || Aliases.size() == 2) { 9892 Aliases.clear(); 9893 Aliases.push_back(OriginalChain); 9894 break; 9895 } 9896 9897 // Don't bother if we've been before. 9898 if (!Visited.insert(Chain.getNode())) 9899 continue; 9900 9901 switch (Chain.getOpcode()) { 9902 case ISD::EntryToken: 9903 // Entry token is ideal chain operand, but handled in FindBetterChain. 9904 break; 9905 9906 case ISD::LOAD: 9907 case ISD::STORE: { 9908 // Get alias information for Chain. 9909 SDValue OpPtr; 9910 int64_t OpSize; 9911 const Value *OpSrcValue; 9912 int OpSrcValueOffset; 9913 unsigned OpSrcValueAlign; 9914 const MDNode *OpSrcTBAAInfo; 9915 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 9916 OpSrcValue, OpSrcValueOffset, 9917 OpSrcValueAlign, 9918 OpSrcTBAAInfo); 9919 9920 // If chain is alias then stop here. 9921 if (!(IsLoad && IsOpLoad) && 9922 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 9923 SrcTBAAInfo, 9924 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 9925 OpSrcValueAlign, OpSrcTBAAInfo)) { 9926 Aliases.push_back(Chain); 9927 } else { 9928 // Look further up the chain. 9929 Chains.push_back(Chain.getOperand(0)); 9930 ++Depth; 9931 } 9932 break; 9933 } 9934 9935 case ISD::TokenFactor: 9936 // We have to check each of the operands of the token factor for "small" 9937 // token factors, so we queue them up. Adding the operands to the queue 9938 // (stack) in reverse order maintains the original order and increases the 9939 // likelihood that getNode will find a matching token factor (CSE.) 9940 if (Chain.getNumOperands() > 16) { 9941 Aliases.push_back(Chain); 9942 break; 9943 } 9944 for (unsigned n = Chain.getNumOperands(); n;) 9945 Chains.push_back(Chain.getOperand(--n)); 9946 ++Depth; 9947 break; 9948 9949 default: 9950 // For all other instructions we will just have to take what we can get. 9951 Aliases.push_back(Chain); 9952 break; 9953 } 9954 } 9955} 9956 9957/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 9958/// for a better chain (aliasing node.) 9959SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 9960 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 9961 9962 // Accumulate all the aliases to this node. 9963 GatherAllAliases(N, OldChain, Aliases); 9964 9965 // If no operands then chain to entry token. 9966 if (Aliases.size() == 0) 9967 return DAG.getEntryNode(); 9968 9969 // If a single operand then chain to it. We don't need to revisit it. 9970 if (Aliases.size() == 1) 9971 return Aliases[0]; 9972 9973 // Construct a custom tailored token factor. 9974 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 9975 &Aliases[0], Aliases.size()); 9976} 9977 9978// SelectionDAG::Combine - This is the entry point for the file. 9979// 9980void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 9981 CodeGenOpt::Level OptLevel) { 9982 /// run - This is the main entry point to this class. 9983 /// 9984 DAGCombiner(*this, AA, OptLevel).Run(Level); 9985} 9986