DAGCombiner.cpp revision 7196cb17f2a16ed5c57325c7eddef90b25ad306b
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 unsigned SrcValueAlign1, 242 SDValue Ptr2, int64_t Size2, 243 const Value *SrcValue2, int SrcValueOffset2, 244 unsigned SrcValueAlign2) const; 245 246 /// FindAliasInfo - Extracts the relevant alias information from the memory 247 /// node. Returns true if the operand was a load. 248 bool FindAliasInfo(SDNode *N, 249 SDValue &Ptr, int64_t &Size, 250 const Value *&SrcValue, int &SrcValueOffset, 251 unsigned &SrcValueAlignment) const; 252 253 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 254 /// looking for a better chain (aliasing node.) 255 SDValue FindBetterChain(SDNode *N, SDValue Chain); 256 257 /// getShiftAmountTy - Returns a type large enough to hold any valid 258 /// shift amount - before type legalization these can be huge. 259 EVT getShiftAmountTy() { 260 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 261 } 262 263public: 264 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 265 : DAG(D), 266 TLI(D.getTargetLoweringInfo()), 267 Level(Unrestricted), 268 OptLevel(OL), 269 LegalOperations(false), 270 LegalTypes(false), 271 AA(A) {} 272 273 /// Run - runs the dag combiner on all nodes in the work list 274 void Run(CombineLevel AtLevel); 275 }; 276} 277 278 279namespace { 280/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 281/// nodes from the worklist. 282class WorkListRemover : public SelectionDAG::DAGUpdateListener { 283 DAGCombiner &DC; 284public: 285 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 286 287 virtual void NodeDeleted(SDNode *N, SDNode *E) { 288 DC.removeFromWorkList(N); 289 } 290 291 virtual void NodeUpdated(SDNode *N) { 292 // Ignore updates. 293 } 294}; 295} 296 297//===----------------------------------------------------------------------===// 298// TargetLowering::DAGCombinerInfo implementation 299//===----------------------------------------------------------------------===// 300 301void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 302 ((DAGCombiner*)DC)->AddToWorkList(N); 303} 304 305SDValue TargetLowering::DAGCombinerInfo:: 306CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 307 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 308} 309 310SDValue TargetLowering::DAGCombinerInfo:: 311CombineTo(SDNode *N, SDValue Res, bool AddTo) { 312 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 313} 314 315 316SDValue TargetLowering::DAGCombinerInfo:: 317CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 318 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 319} 320 321void TargetLowering::DAGCombinerInfo:: 322CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 323 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 324} 325 326//===----------------------------------------------------------------------===// 327// Helper Functions 328//===----------------------------------------------------------------------===// 329 330/// isNegatibleForFree - Return 1 if we can compute the negated form of the 331/// specified expression for the same cost as the expression itself, or 2 if we 332/// can compute the negated form more cheaply than the expression itself. 333static char isNegatibleForFree(SDValue Op, bool LegalOperations, 334 unsigned Depth = 0) { 335 // No compile time optimizations on this type. 336 if (Op.getValueType() == MVT::ppcf128) 337 return 0; 338 339 // fneg is removable even if it has multiple uses. 340 if (Op.getOpcode() == ISD::FNEG) return 2; 341 342 // Don't allow anything with multiple uses. 343 if (!Op.hasOneUse()) return 0; 344 345 // Don't recurse exponentially. 346 if (Depth > 6) return 0; 347 348 switch (Op.getOpcode()) { 349 default: return false; 350 case ISD::ConstantFP: 351 // Don't invert constant FP values after legalize. The negated constant 352 // isn't necessarily legal. 353 return LegalOperations ? 0 : 1; 354 case ISD::FADD: 355 // FIXME: determine better conditions for this xform. 356 if (!UnsafeFPMath) return 0; 357 358 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 359 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 360 return V; 361 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 362 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 363 case ISD::FSUB: 364 // We can't turn -(A-B) into B-A when we honor signed zeros. 365 if (!UnsafeFPMath) return 0; 366 367 // fold (fneg (fsub A, B)) -> (fsub B, A) 368 return 1; 369 370 case ISD::FMUL: 371 case ISD::FDIV: 372 if (HonorSignDependentRoundingFPMath()) return 0; 373 374 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 376 return V; 377 378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 379 380 case ISD::FP_EXTEND: 381 case ISD::FP_ROUND: 382 case ISD::FSIN: 383 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 384 } 385} 386 387/// GetNegatedExpression - If isNegatibleForFree returns true, this function 388/// returns the newly negated expression. 389static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 390 bool LegalOperations, unsigned Depth = 0) { 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 393 394 // Don't allow anything with multiple uses. 395 assert(Op.hasOneUse() && "Unknown reuse!"); 396 397 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 398 switch (Op.getOpcode()) { 399 default: llvm_unreachable("Unknown code"); 400 case ISD::ConstantFP: { 401 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 402 V.changeSign(); 403 return DAG.getConstantFP(V, Op.getValueType()); 404 } 405 case ISD::FADD: 406 // FIXME: determine better conditions for this xform. 407 assert(UnsafeFPMath); 408 409 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 410 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 411 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 LegalOperations, Depth+1), 414 Op.getOperand(1)); 415 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 416 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 417 GetNegatedExpression(Op.getOperand(1), DAG, 418 LegalOperations, Depth+1), 419 Op.getOperand(0)); 420 case ISD::FSUB: 421 // We can't turn -(A-B) into B-A when we honor signed zeros. 422 assert(UnsafeFPMath); 423 424 // fold (fneg (fsub 0, B)) -> B 425 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 426 if (N0CFP->getValueAPF().isZero()) 427 return Op.getOperand(1); 428 429 // fold (fneg (fsub A, B)) -> (fsub B, A) 430 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 431 Op.getOperand(1), Op.getOperand(0)); 432 433 case ISD::FMUL: 434 case ISD::FDIV: 435 assert(!HonorSignDependentRoundingFPMath()); 436 437 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 438 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 439 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 440 GetNegatedExpression(Op.getOperand(0), DAG, 441 LegalOperations, Depth+1), 442 Op.getOperand(1)); 443 444 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 445 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 446 Op.getOperand(0), 447 GetNegatedExpression(Op.getOperand(1), DAG, 448 LegalOperations, Depth+1)); 449 450 case ISD::FP_EXTEND: 451 case ISD::FSIN: 452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1)); 455 case ISD::FP_ROUND: 456 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 457 GetNegatedExpression(Op.getOperand(0), DAG, 458 LegalOperations, Depth+1), 459 Op.getOperand(1)); 460 } 461} 462 463 464// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 465// that selects between the values 1 and 0, making it equivalent to a setcc. 466// Also, set the incoming LHS, RHS, and CC references to the appropriate 467// nodes based on the type of node we are checking. This simplifies life a 468// bit for the callers. 469static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 470 SDValue &CC) { 471 if (N.getOpcode() == ISD::SETCC) { 472 LHS = N.getOperand(0); 473 RHS = N.getOperand(1); 474 CC = N.getOperand(2); 475 return true; 476 } 477 if (N.getOpcode() == ISD::SELECT_CC && 478 N.getOperand(2).getOpcode() == ISD::Constant && 479 N.getOperand(3).getOpcode() == ISD::Constant && 480 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 481 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 482 LHS = N.getOperand(0); 483 RHS = N.getOperand(1); 484 CC = N.getOperand(4); 485 return true; 486 } 487 return false; 488} 489 490// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 491// one use. If this is true, it allows the users to invert the operation for 492// free when it is profitable to do so. 493static bool isOneUseSetCC(SDValue N) { 494 SDValue N0, N1, N2; 495 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 496 return true; 497 return false; 498} 499 500SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 501 SDValue N0, SDValue N1) { 502 EVT VT = N0.getValueType(); 503 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 504 if (isa<ConstantSDNode>(N1)) { 505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 506 SDValue OpNode = 507 DAG.FoldConstantArithmetic(Opc, VT, 508 cast<ConstantSDNode>(N0.getOperand(1)), 509 cast<ConstantSDNode>(N1)); 510 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 511 } else if (N0.hasOneUse()) { 512 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 513 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 514 N0.getOperand(0), N1); 515 AddToWorkList(OpNode.getNode()); 516 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 517 } 518 } 519 520 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 521 if (isa<ConstantSDNode>(N0)) { 522 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 523 SDValue OpNode = 524 DAG.FoldConstantArithmetic(Opc, VT, 525 cast<ConstantSDNode>(N1.getOperand(1)), 526 cast<ConstantSDNode>(N0)); 527 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 528 } else if (N1.hasOneUse()) { 529 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 530 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 531 N1.getOperand(0), N0); 532 AddToWorkList(OpNode.getNode()); 533 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 534 } 535 } 536 537 return SDValue(); 538} 539 540SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 541 bool AddTo) { 542 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 543 ++NodesCombined; 544 DEBUG(dbgs() << "\nReplacing.1 "; 545 N->dump(&DAG); 546 dbgs() << "\nWith: "; 547 To[0].getNode()->dump(&DAG); 548 dbgs() << " and " << NumTo-1 << " other values\n"; 549 for (unsigned i = 0, e = NumTo; i != e; ++i) 550 assert((!To[i].getNode() || 551 N->getValueType(i) == To[i].getValueType()) && 552 "Cannot combine value to value of different type!")); 553 WorkListRemover DeadNodes(*this); 554 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 555 556 if (AddTo) { 557 // Push the new nodes and any users onto the worklist 558 for (unsigned i = 0, e = NumTo; i != e; ++i) { 559 if (To[i].getNode()) { 560 AddToWorkList(To[i].getNode()); 561 AddUsersToWorkList(To[i].getNode()); 562 } 563 } 564 } 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (N->use_empty()) { 570 // Nodes can be reintroduced into the worklist. Make sure we do not 571 // process a node that has been replaced. 572 removeFromWorkList(N); 573 574 // Finally, since the node is now dead, remove it from the graph. 575 DAG.DeleteNode(N); 576 } 577 return SDValue(N, 0); 578} 579 580void 581DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 582 TLO) { 583 // Replace all uses. If any nodes become isomorphic to other nodes and 584 // are deleted, make sure to remove them from our worklist. 585 WorkListRemover DeadNodes(*this); 586 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 587 588 // Push the new node and any (possibly new) users onto the worklist. 589 AddToWorkList(TLO.New.getNode()); 590 AddUsersToWorkList(TLO.New.getNode()); 591 592 // Finally, if the node is now dead, remove it from the graph. The node 593 // may not be dead if the replacement process recursively simplified to 594 // something else needing this node. 595 if (TLO.Old.getNode()->use_empty()) { 596 removeFromWorkList(TLO.Old.getNode()); 597 598 // If the operands of this node are only used by the node, they will now 599 // be dead. Make sure to visit them first to delete dead nodes early. 600 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 601 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 602 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 603 604 DAG.DeleteNode(TLO.Old.getNode()); 605 } 606} 607 608/// SimplifyDemandedBits - Check the specified integer node value to see if 609/// it can be simplified or if things it uses can be simplified by bit 610/// propagation. If so, return true. 611bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 612 TargetLowering::TargetLoweringOpt TLO(DAG); 613 APInt KnownZero, KnownOne; 614 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 615 return false; 616 617 // Revisit the node. 618 AddToWorkList(Op.getNode()); 619 620 // Replace the old value with the new one. 621 ++NodesCombined; 622 DEBUG(dbgs() << "\nReplacing.2 "; 623 TLO.Old.getNode()->dump(&DAG); 624 dbgs() << "\nWith: "; 625 TLO.New.getNode()->dump(&DAG); 626 dbgs() << '\n'); 627 628 CommitTargetLoweringOpt(TLO); 629 return true; 630} 631 632//===----------------------------------------------------------------------===// 633// Main DAG Combiner implementation 634//===----------------------------------------------------------------------===// 635 636void DAGCombiner::Run(CombineLevel AtLevel) { 637 // set the instance variables, so that the various visit routines may use it. 638 Level = AtLevel; 639 LegalOperations = Level >= NoIllegalOperations; 640 LegalTypes = Level >= NoIllegalTypes; 641 642 // Add all the dag nodes to the worklist. 643 WorkList.reserve(DAG.allnodes_size()); 644 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 645 E = DAG.allnodes_end(); I != E; ++I) 646 WorkList.push_back(I); 647 648 // Create a dummy node (which is not added to allnodes), that adds a reference 649 // to the root node, preventing it from being deleted, and tracking any 650 // changes of the root. 651 HandleSDNode Dummy(DAG.getRoot()); 652 653 // The root of the dag may dangle to deleted nodes until the dag combiner is 654 // done. Set it to null to avoid confusion. 655 DAG.setRoot(SDValue()); 656 657 // while the worklist isn't empty, inspect the node on the end of it and 658 // try and combine it. 659 while (!WorkList.empty()) { 660 SDNode *N = WorkList.back(); 661 WorkList.pop_back(); 662 663 // If N has no uses, it is dead. Make sure to revisit all N's operands once 664 // N is deleted from the DAG, since they too may now be dead or may have a 665 // reduced number of uses, allowing other xforms. 666 if (N->use_empty() && N != &Dummy) { 667 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 668 AddToWorkList(N->getOperand(i).getNode()); 669 670 DAG.DeleteNode(N); 671 continue; 672 } 673 674 SDValue RV = combine(N); 675 676 if (RV.getNode() == 0) 677 continue; 678 679 ++NodesCombined; 680 681 // If we get back the same node we passed in, rather than a new node or 682 // zero, we know that the node must have defined multiple values and 683 // CombineTo was used. Since CombineTo takes care of the worklist 684 // mechanics for us, we have no work to do in this case. 685 if (RV.getNode() == N) 686 continue; 687 688 assert(N->getOpcode() != ISD::DELETED_NODE && 689 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 690 "Node was deleted but visit returned new node!"); 691 692 DEBUG(dbgs() << "\nReplacing.3 "; 693 N->dump(&DAG); 694 dbgs() << "\nWith: "; 695 RV.getNode()->dump(&DAG); 696 dbgs() << '\n'); 697 WorkListRemover DeadNodes(*this); 698 if (N->getNumValues() == RV.getNode()->getNumValues()) 699 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 700 else { 701 assert(N->getValueType(0) == RV.getValueType() && 702 N->getNumValues() == 1 && "Type mismatch"); 703 SDValue OpV = RV; 704 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 705 } 706 707 // Push the new node and any users onto the worklist 708 AddToWorkList(RV.getNode()); 709 AddUsersToWorkList(RV.getNode()); 710 711 // Add any uses of the old node to the worklist in case this node is the 712 // last one that uses them. They may become dead after this node is 713 // deleted. 714 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 715 AddToWorkList(N->getOperand(i).getNode()); 716 717 // Finally, if the node is now dead, remove it from the graph. The node 718 // may not be dead if the replacement process recursively simplified to 719 // something else needing this node. 720 if (N->use_empty()) { 721 // Nodes can be reintroduced into the worklist. Make sure we do not 722 // process a node that has been replaced. 723 removeFromWorkList(N); 724 725 // Finally, since the node is now dead, remove it from the graph. 726 DAG.DeleteNode(N); 727 } 728 } 729 730 // If the root changed (e.g. it was a dead load, update the root). 731 DAG.setRoot(Dummy.getValue()); 732} 733 734SDValue DAGCombiner::visit(SDNode *N) { 735 switch(N->getOpcode()) { 736 default: break; 737 case ISD::TokenFactor: return visitTokenFactor(N); 738 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 739 case ISD::ADD: return visitADD(N); 740 case ISD::SUB: return visitSUB(N); 741 case ISD::ADDC: return visitADDC(N); 742 case ISD::ADDE: return visitADDE(N); 743 case ISD::MUL: return visitMUL(N); 744 case ISD::SDIV: return visitSDIV(N); 745 case ISD::UDIV: return visitUDIV(N); 746 case ISD::SREM: return visitSREM(N); 747 case ISD::UREM: return visitUREM(N); 748 case ISD::MULHU: return visitMULHU(N); 749 case ISD::MULHS: return visitMULHS(N); 750 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 751 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 752 case ISD::SDIVREM: return visitSDIVREM(N); 753 case ISD::UDIVREM: return visitUDIVREM(N); 754 case ISD::AND: return visitAND(N); 755 case ISD::OR: return visitOR(N); 756 case ISD::XOR: return visitXOR(N); 757 case ISD::SHL: return visitSHL(N); 758 case ISD::SRA: return visitSRA(N); 759 case ISD::SRL: return visitSRL(N); 760 case ISD::CTLZ: return visitCTLZ(N); 761 case ISD::CTTZ: return visitCTTZ(N); 762 case ISD::CTPOP: return visitCTPOP(N); 763 case ISD::SELECT: return visitSELECT(N); 764 case ISD::SELECT_CC: return visitSELECT_CC(N); 765 case ISD::SETCC: return visitSETCC(N); 766 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 767 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 768 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 769 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 770 case ISD::TRUNCATE: return visitTRUNCATE(N); 771 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 772 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 773 case ISD::FADD: return visitFADD(N); 774 case ISD::FSUB: return visitFSUB(N); 775 case ISD::FMUL: return visitFMUL(N); 776 case ISD::FDIV: return visitFDIV(N); 777 case ISD::FREM: return visitFREM(N); 778 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 779 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 780 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 781 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 782 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 783 case ISD::FP_ROUND: return visitFP_ROUND(N); 784 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 785 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 786 case ISD::FNEG: return visitFNEG(N); 787 case ISD::FABS: return visitFABS(N); 788 case ISD::BRCOND: return visitBRCOND(N); 789 case ISD::BR_CC: return visitBR_CC(N); 790 case ISD::LOAD: return visitLOAD(N); 791 case ISD::STORE: return visitSTORE(N); 792 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 793 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 794 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 795 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 796 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 797 } 798 return SDValue(); 799} 800 801SDValue DAGCombiner::combine(SDNode *N) { 802 SDValue RV = visit(N); 803 804 // If nothing happened, try a target-specific DAG combine. 805 if (RV.getNode() == 0) { 806 assert(N->getOpcode() != ISD::DELETED_NODE && 807 "Node was deleted but visit returned NULL!"); 808 809 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 810 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 811 812 // Expose the DAG combiner to the target combiner impls. 813 TargetLowering::DAGCombinerInfo 814 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 815 816 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 817 } 818 } 819 820 // If N is a commutative binary node, try commuting it to enable more 821 // sdisel CSE. 822 if (RV.getNode() == 0 && 823 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 824 N->getNumValues() == 1) { 825 SDValue N0 = N->getOperand(0); 826 SDValue N1 = N->getOperand(1); 827 828 // Constant operands are canonicalized to RHS. 829 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 830 SDValue Ops[] = { N1, N0 }; 831 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 832 Ops, 2); 833 if (CSENode) 834 return SDValue(CSENode, 0); 835 } 836 } 837 838 return RV; 839} 840 841/// getInputChainForNode - Given a node, return its input chain if it has one, 842/// otherwise return a null sd operand. 843static SDValue getInputChainForNode(SDNode *N) { 844 if (unsigned NumOps = N->getNumOperands()) { 845 if (N->getOperand(0).getValueType() == MVT::Other) 846 return N->getOperand(0); 847 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 848 return N->getOperand(NumOps-1); 849 for (unsigned i = 1; i < NumOps-1; ++i) 850 if (N->getOperand(i).getValueType() == MVT::Other) 851 return N->getOperand(i); 852 } 853 return SDValue(); 854} 855 856SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 857 // If N has two operands, where one has an input chain equal to the other, 858 // the 'other' chain is redundant. 859 if (N->getNumOperands() == 2) { 860 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 861 return N->getOperand(0); 862 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 863 return N->getOperand(1); 864 } 865 866 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 867 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 868 SmallPtrSet<SDNode*, 16> SeenOps; 869 bool Changed = false; // If we should replace this token factor. 870 871 // Start out with this token factor. 872 TFs.push_back(N); 873 874 // Iterate through token factors. The TFs grows when new token factors are 875 // encountered. 876 for (unsigned i = 0; i < TFs.size(); ++i) { 877 SDNode *TF = TFs[i]; 878 879 // Check each of the operands. 880 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 881 SDValue Op = TF->getOperand(i); 882 883 switch (Op.getOpcode()) { 884 case ISD::EntryToken: 885 // Entry tokens don't need to be added to the list. They are 886 // rededundant. 887 Changed = true; 888 break; 889 890 case ISD::TokenFactor: 891 if (Op.hasOneUse() && 892 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 893 // Queue up for processing. 894 TFs.push_back(Op.getNode()); 895 // Clean up in case the token factor is removed. 896 AddToWorkList(Op.getNode()); 897 Changed = true; 898 break; 899 } 900 // Fall thru 901 902 default: 903 // Only add if it isn't already in the list. 904 if (SeenOps.insert(Op.getNode())) 905 Ops.push_back(Op); 906 else 907 Changed = true; 908 break; 909 } 910 } 911 } 912 913 SDValue Result; 914 915 // If we've change things around then replace token factor. 916 if (Changed) { 917 if (Ops.empty()) { 918 // The entry token is the only possible outcome. 919 Result = DAG.getEntryNode(); 920 } else { 921 // New and improved token factor. 922 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 923 MVT::Other, &Ops[0], Ops.size()); 924 } 925 926 // Don't add users to work list. 927 return CombineTo(N, Result, false); 928 } 929 930 return Result; 931} 932 933/// MERGE_VALUES can always be eliminated. 934SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 935 WorkListRemover DeadNodes(*this); 936 // Replacing results may cause a different MERGE_VALUES to suddenly 937 // be CSE'd with N, and carry its uses with it. Iterate until no 938 // uses remain, to ensure that the node can be safely deleted. 939 do { 940 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 942 &DeadNodes); 943 } while (!N->use_empty()); 944 removeFromWorkList(N); 945 DAG.DeleteNode(N); 946 return SDValue(N, 0); // Return N so it doesn't get rechecked! 947} 948 949static 950SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 951 SelectionDAG &DAG) { 952 EVT VT = N0.getValueType(); 953 SDValue N00 = N0.getOperand(0); 954 SDValue N01 = N0.getOperand(1); 955 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 956 957 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 958 isa<ConstantSDNode>(N00.getOperand(1))) { 959 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 960 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 961 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 962 N00.getOperand(0), N01), 963 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 964 N00.getOperand(1), N01)); 965 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 966 } 967 968 return SDValue(); 969} 970 971SDValue DAGCombiner::visitADD(SDNode *N) { 972 SDValue N0 = N->getOperand(0); 973 SDValue N1 = N->getOperand(1); 974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 976 EVT VT = N0.getValueType(); 977 978 // fold vector ops 979 if (VT.isVector()) { 980 SDValue FoldedVOp = SimplifyVBinOp(N); 981 if (FoldedVOp.getNode()) return FoldedVOp; 982 } 983 984 // fold (add x, undef) -> undef 985 if (N0.getOpcode() == ISD::UNDEF) 986 return N0; 987 if (N1.getOpcode() == ISD::UNDEF) 988 return N1; 989 // fold (add c1, c2) -> c1+c2 990 if (N0C && N1C) 991 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 992 // canonicalize constant to RHS 993 if (N0C && !N1C) 994 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 995 // fold (add x, 0) -> x 996 if (N1C && N1C->isNullValue()) 997 return N0; 998 // fold (add Sym, c) -> Sym+c 999 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1000 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1001 GA->getOpcode() == ISD::GlobalAddress) 1002 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1003 GA->getOffset() + 1004 (uint64_t)N1C->getSExtValue()); 1005 // fold ((c1-A)+c2) -> (c1+c2)-A 1006 if (N1C && N0.getOpcode() == ISD::SUB) 1007 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1008 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1009 DAG.getConstant(N1C->getAPIntValue()+ 1010 N0C->getAPIntValue(), VT), 1011 N0.getOperand(1)); 1012 // reassociate add 1013 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1014 if (RADD.getNode() != 0) 1015 return RADD; 1016 // fold ((0-A) + B) -> B-A 1017 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1018 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1020 // fold (A + (0-B)) -> A-B 1021 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1022 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1023 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1024 // fold (A+(B-A)) -> B 1025 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1026 return N1.getOperand(0); 1027 // fold ((B-A)+A) -> B 1028 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1029 return N0.getOperand(0); 1030 // fold (A+(B-(A+C))) to (B-C) 1031 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1032 N0 == N1.getOperand(1).getOperand(0)) 1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1034 N1.getOperand(1).getOperand(1)); 1035 // fold (A+(B-(C+A))) to (B-C) 1036 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1037 N0 == N1.getOperand(1).getOperand(1)) 1038 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1039 N1.getOperand(1).getOperand(0)); 1040 // fold (A+((B-A)+or-C)) to (B+or-C) 1041 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1042 N1.getOperand(0).getOpcode() == ISD::SUB && 1043 N0 == N1.getOperand(0).getOperand(1)) 1044 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1045 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1046 1047 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1048 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1049 SDValue N00 = N0.getOperand(0); 1050 SDValue N01 = N0.getOperand(1); 1051 SDValue N10 = N1.getOperand(0); 1052 SDValue N11 = N1.getOperand(1); 1053 1054 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1055 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1056 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1057 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1058 } 1059 1060 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1061 return SDValue(N, 0); 1062 1063 // fold (a+b) -> (a|b) iff a and b share no bits. 1064 if (VT.isInteger() && !VT.isVector()) { 1065 APInt LHSZero, LHSOne; 1066 APInt RHSZero, RHSOne; 1067 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1068 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1069 1070 if (LHSZero.getBoolValue()) { 1071 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1072 1073 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1074 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1075 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1076 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1078 } 1079 } 1080 1081 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1082 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1083 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1084 if (Result.getNode()) return Result; 1085 } 1086 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1087 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1088 if (Result.getNode()) return Result; 1089 } 1090 1091 return SDValue(); 1092} 1093 1094SDValue DAGCombiner::visitADDC(SDNode *N) { 1095 SDValue N0 = N->getOperand(0); 1096 SDValue N1 = N->getOperand(1); 1097 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1098 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1099 EVT VT = N0.getValueType(); 1100 1101 // If the flag result is dead, turn this into an ADD. 1102 if (N->hasNUsesOfValue(0, 1)) 1103 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1104 DAG.getNode(ISD::CARRY_FALSE, 1105 N->getDebugLoc(), MVT::Flag)); 1106 1107 // canonicalize constant to RHS. 1108 if (N0C && !N1C) 1109 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1110 1111 // fold (addc x, 0) -> x + no carry out 1112 if (N1C && N1C->isNullValue()) 1113 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1114 N->getDebugLoc(), MVT::Flag)); 1115 1116 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1117 APInt LHSZero, LHSOne; 1118 APInt RHSZero, RHSOne; 1119 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1120 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1121 1122 if (LHSZero.getBoolValue()) { 1123 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1124 1125 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1126 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1127 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1128 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1129 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1130 DAG.getNode(ISD::CARRY_FALSE, 1131 N->getDebugLoc(), MVT::Flag)); 1132 } 1133 1134 return SDValue(); 1135} 1136 1137SDValue DAGCombiner::visitADDE(SDNode *N) { 1138 SDValue N0 = N->getOperand(0); 1139 SDValue N1 = N->getOperand(1); 1140 SDValue CarryIn = N->getOperand(2); 1141 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1142 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1143 1144 // canonicalize constant to RHS 1145 if (N0C && !N1C) 1146 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1147 N1, N0, CarryIn); 1148 1149 // fold (adde x, y, false) -> (addc x, y) 1150 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1151 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1152 1153 return SDValue(); 1154} 1155 1156SDValue DAGCombiner::visitSUB(SDNode *N) { 1157 SDValue N0 = N->getOperand(0); 1158 SDValue N1 = N->getOperand(1); 1159 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1160 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1161 EVT VT = N0.getValueType(); 1162 1163 // fold vector ops 1164 if (VT.isVector()) { 1165 SDValue FoldedVOp = SimplifyVBinOp(N); 1166 if (FoldedVOp.getNode()) return FoldedVOp; 1167 } 1168 1169 // fold (sub x, x) -> 0 1170 if (N0 == N1) 1171 return DAG.getConstant(0, N->getValueType(0)); 1172 // fold (sub c1, c2) -> c1-c2 1173 if (N0C && N1C) 1174 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1175 // fold (sub x, c) -> (add x, -c) 1176 if (N1C) 1177 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1178 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1179 // fold (A+B)-A -> B 1180 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1181 return N0.getOperand(1); 1182 // fold (A+B)-B -> A 1183 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1184 return N0.getOperand(0); 1185 // fold ((A+(B+or-C))-B) -> A+or-C 1186 if (N0.getOpcode() == ISD::ADD && 1187 (N0.getOperand(1).getOpcode() == ISD::SUB || 1188 N0.getOperand(1).getOpcode() == ISD::ADD) && 1189 N0.getOperand(1).getOperand(0) == N1) 1190 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1191 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1192 // fold ((A+(C+B))-B) -> A+C 1193 if (N0.getOpcode() == ISD::ADD && 1194 N0.getOperand(1).getOpcode() == ISD::ADD && 1195 N0.getOperand(1).getOperand(1) == N1) 1196 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1197 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1198 // fold ((A-(B-C))-C) -> A-B 1199 if (N0.getOpcode() == ISD::SUB && 1200 N0.getOperand(1).getOpcode() == ISD::SUB && 1201 N0.getOperand(1).getOperand(1) == N1) 1202 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1203 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1204 1205 // If either operand of a sub is undef, the result is undef 1206 if (N0.getOpcode() == ISD::UNDEF) 1207 return N0; 1208 if (N1.getOpcode() == ISD::UNDEF) 1209 return N1; 1210 1211 // If the relocation model supports it, consider symbol offsets. 1212 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1213 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1214 // fold (sub Sym, c) -> Sym-c 1215 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1216 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1217 GA->getOffset() - 1218 (uint64_t)N1C->getSExtValue()); 1219 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1220 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1221 if (GA->getGlobal() == GB->getGlobal()) 1222 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1223 VT); 1224 } 1225 1226 return SDValue(); 1227} 1228 1229SDValue DAGCombiner::visitMUL(SDNode *N) { 1230 SDValue N0 = N->getOperand(0); 1231 SDValue N1 = N->getOperand(1); 1232 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1233 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1234 EVT VT = N0.getValueType(); 1235 1236 // fold vector ops 1237 if (VT.isVector()) { 1238 SDValue FoldedVOp = SimplifyVBinOp(N); 1239 if (FoldedVOp.getNode()) return FoldedVOp; 1240 } 1241 1242 // fold (mul x, undef) -> 0 1243 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1244 return DAG.getConstant(0, VT); 1245 // fold (mul c1, c2) -> c1*c2 1246 if (N0C && N1C) 1247 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1248 // canonicalize constant to RHS 1249 if (N0C && !N1C) 1250 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1251 // fold (mul x, 0) -> 0 1252 if (N1C && N1C->isNullValue()) 1253 return N1; 1254 // fold (mul x, -1) -> 0-x 1255 if (N1C && N1C->isAllOnesValue()) 1256 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1257 DAG.getConstant(0, VT), N0); 1258 // fold (mul x, (1 << c)) -> x << c 1259 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1260 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1261 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1262 getShiftAmountTy())); 1263 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1264 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1265 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1266 // FIXME: If the input is something that is easily negated (e.g. a 1267 // single-use add), we should put the negate there. 1268 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1269 DAG.getConstant(0, VT), 1270 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1271 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1272 } 1273 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1274 if (N1C && N0.getOpcode() == ISD::SHL && 1275 isa<ConstantSDNode>(N0.getOperand(1))) { 1276 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1277 N1, N0.getOperand(1)); 1278 AddToWorkList(C3.getNode()); 1279 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1280 N0.getOperand(0), C3); 1281 } 1282 1283 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1284 // use. 1285 { 1286 SDValue Sh(0,0), Y(0,0); 1287 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1288 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1289 N0.getNode()->hasOneUse()) { 1290 Sh = N0; Y = N1; 1291 } else if (N1.getOpcode() == ISD::SHL && 1292 isa<ConstantSDNode>(N1.getOperand(1)) && 1293 N1.getNode()->hasOneUse()) { 1294 Sh = N1; Y = N0; 1295 } 1296 1297 if (Sh.getNode()) { 1298 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1299 Sh.getOperand(0), Y); 1300 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1301 Mul, Sh.getOperand(1)); 1302 } 1303 } 1304 1305 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1306 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1307 isa<ConstantSDNode>(N0.getOperand(1))) 1308 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1309 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1310 N0.getOperand(0), N1), 1311 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1312 N0.getOperand(1), N1)); 1313 1314 // reassociate mul 1315 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1316 if (RMUL.getNode() != 0) 1317 return RMUL; 1318 1319 return SDValue(); 1320} 1321 1322SDValue DAGCombiner::visitSDIV(SDNode *N) { 1323 SDValue N0 = N->getOperand(0); 1324 SDValue N1 = N->getOperand(1); 1325 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1326 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1327 EVT VT = N->getValueType(0); 1328 1329 // fold vector ops 1330 if (VT.isVector()) { 1331 SDValue FoldedVOp = SimplifyVBinOp(N); 1332 if (FoldedVOp.getNode()) return FoldedVOp; 1333 } 1334 1335 // fold (sdiv c1, c2) -> c1/c2 1336 if (N0C && N1C && !N1C->isNullValue()) 1337 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1338 // fold (sdiv X, 1) -> X 1339 if (N1C && N1C->getSExtValue() == 1LL) 1340 return N0; 1341 // fold (sdiv X, -1) -> 0-X 1342 if (N1C && N1C->isAllOnesValue()) 1343 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1344 DAG.getConstant(0, VT), N0); 1345 // If we know the sign bits of both operands are zero, strength reduce to a 1346 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1347 if (!VT.isVector()) { 1348 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1349 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1350 N0, N1); 1351 } 1352 // fold (sdiv X, pow2) -> simple ops after legalize 1353 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1354 (isPowerOf2_64(N1C->getSExtValue()) || 1355 isPowerOf2_64(-N1C->getSExtValue()))) { 1356 // If dividing by powers of two is cheap, then don't perform the following 1357 // fold. 1358 if (TLI.isPow2DivCheap()) 1359 return SDValue(); 1360 1361 int64_t pow2 = N1C->getSExtValue(); 1362 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1363 unsigned lg2 = Log2_64(abs2); 1364 1365 // Splat the sign bit into the register 1366 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1367 DAG.getConstant(VT.getSizeInBits()-1, 1368 getShiftAmountTy())); 1369 AddToWorkList(SGN.getNode()); 1370 1371 // Add (N0 < 0) ? abs2 - 1 : 0; 1372 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1373 DAG.getConstant(VT.getSizeInBits() - lg2, 1374 getShiftAmountTy())); 1375 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1376 AddToWorkList(SRL.getNode()); 1377 AddToWorkList(ADD.getNode()); // Divide by pow2 1378 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1379 DAG.getConstant(lg2, getShiftAmountTy())); 1380 1381 // If we're dividing by a positive value, we're done. Otherwise, we must 1382 // negate the result. 1383 if (pow2 > 0) 1384 return SRA; 1385 1386 AddToWorkList(SRA.getNode()); 1387 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1388 DAG.getConstant(0, VT), SRA); 1389 } 1390 1391 // if integer divide is expensive and we satisfy the requirements, emit an 1392 // alternate sequence. 1393 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1394 !TLI.isIntDivCheap()) { 1395 SDValue Op = BuildSDIV(N); 1396 if (Op.getNode()) return Op; 1397 } 1398 1399 // undef / X -> 0 1400 if (N0.getOpcode() == ISD::UNDEF) 1401 return DAG.getConstant(0, VT); 1402 // X / undef -> undef 1403 if (N1.getOpcode() == ISD::UNDEF) 1404 return N1; 1405 1406 return SDValue(); 1407} 1408 1409SDValue DAGCombiner::visitUDIV(SDNode *N) { 1410 SDValue N0 = N->getOperand(0); 1411 SDValue N1 = N->getOperand(1); 1412 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1414 EVT VT = N->getValueType(0); 1415 1416 // fold vector ops 1417 if (VT.isVector()) { 1418 SDValue FoldedVOp = SimplifyVBinOp(N); 1419 if (FoldedVOp.getNode()) return FoldedVOp; 1420 } 1421 1422 // fold (udiv c1, c2) -> c1/c2 1423 if (N0C && N1C && !N1C->isNullValue()) 1424 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1425 // fold (udiv x, (1 << c)) -> x >>u c 1426 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1427 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1428 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1429 getShiftAmountTy())); 1430 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1431 if (N1.getOpcode() == ISD::SHL) { 1432 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1433 if (SHC->getAPIntValue().isPowerOf2()) { 1434 EVT ADDVT = N1.getOperand(1).getValueType(); 1435 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1436 N1.getOperand(1), 1437 DAG.getConstant(SHC->getAPIntValue() 1438 .logBase2(), 1439 ADDVT)); 1440 AddToWorkList(Add.getNode()); 1441 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1442 } 1443 } 1444 } 1445 // fold (udiv x, c) -> alternate 1446 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1447 SDValue Op = BuildUDIV(N); 1448 if (Op.getNode()) return Op; 1449 } 1450 1451 // undef / X -> 0 1452 if (N0.getOpcode() == ISD::UNDEF) 1453 return DAG.getConstant(0, VT); 1454 // X / undef -> undef 1455 if (N1.getOpcode() == ISD::UNDEF) 1456 return N1; 1457 1458 return SDValue(); 1459} 1460 1461SDValue DAGCombiner::visitSREM(SDNode *N) { 1462 SDValue N0 = N->getOperand(0); 1463 SDValue N1 = N->getOperand(1); 1464 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1465 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1466 EVT VT = N->getValueType(0); 1467 1468 // fold (srem c1, c2) -> c1%c2 1469 if (N0C && N1C && !N1C->isNullValue()) 1470 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1471 // If we know the sign bits of both operands are zero, strength reduce to a 1472 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1473 if (!VT.isVector()) { 1474 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1475 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1476 } 1477 1478 // If X/C can be simplified by the division-by-constant logic, lower 1479 // X%C to the equivalent of X-X/C*C. 1480 if (N1C && !N1C->isNullValue()) { 1481 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1482 AddToWorkList(Div.getNode()); 1483 SDValue OptimizedDiv = combine(Div.getNode()); 1484 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1485 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1486 OptimizedDiv, N1); 1487 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1488 AddToWorkList(Mul.getNode()); 1489 return Sub; 1490 } 1491 } 1492 1493 // undef % X -> 0 1494 if (N0.getOpcode() == ISD::UNDEF) 1495 return DAG.getConstant(0, VT); 1496 // X % undef -> undef 1497 if (N1.getOpcode() == ISD::UNDEF) 1498 return N1; 1499 1500 return SDValue(); 1501} 1502 1503SDValue DAGCombiner::visitUREM(SDNode *N) { 1504 SDValue N0 = N->getOperand(0); 1505 SDValue N1 = N->getOperand(1); 1506 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1507 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1508 EVT VT = N->getValueType(0); 1509 1510 // fold (urem c1, c2) -> c1%c2 1511 if (N0C && N1C && !N1C->isNullValue()) 1512 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1513 // fold (urem x, pow2) -> (and x, pow2-1) 1514 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1515 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1516 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1517 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1518 if (N1.getOpcode() == ISD::SHL) { 1519 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1520 if (SHC->getAPIntValue().isPowerOf2()) { 1521 SDValue Add = 1522 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1523 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1524 VT)); 1525 AddToWorkList(Add.getNode()); 1526 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1527 } 1528 } 1529 } 1530 1531 // If X/C can be simplified by the division-by-constant logic, lower 1532 // X%C to the equivalent of X-X/C*C. 1533 if (N1C && !N1C->isNullValue()) { 1534 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1535 AddToWorkList(Div.getNode()); 1536 SDValue OptimizedDiv = combine(Div.getNode()); 1537 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1538 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1539 OptimizedDiv, N1); 1540 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1541 AddToWorkList(Mul.getNode()); 1542 return Sub; 1543 } 1544 } 1545 1546 // undef % X -> 0 1547 if (N0.getOpcode() == ISD::UNDEF) 1548 return DAG.getConstant(0, VT); 1549 // X % undef -> undef 1550 if (N1.getOpcode() == ISD::UNDEF) 1551 return N1; 1552 1553 return SDValue(); 1554} 1555 1556SDValue DAGCombiner::visitMULHS(SDNode *N) { 1557 SDValue N0 = N->getOperand(0); 1558 SDValue N1 = N->getOperand(1); 1559 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1560 EVT VT = N->getValueType(0); 1561 1562 // fold (mulhs x, 0) -> 0 1563 if (N1C && N1C->isNullValue()) 1564 return N1; 1565 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1566 if (N1C && N1C->getAPIntValue() == 1) 1567 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1568 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1569 getShiftAmountTy())); 1570 // fold (mulhs x, undef) -> 0 1571 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1572 return DAG.getConstant(0, VT); 1573 1574 return SDValue(); 1575} 1576 1577SDValue DAGCombiner::visitMULHU(SDNode *N) { 1578 SDValue N0 = N->getOperand(0); 1579 SDValue N1 = N->getOperand(1); 1580 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1581 EVT VT = N->getValueType(0); 1582 1583 // fold (mulhu x, 0) -> 0 1584 if (N1C && N1C->isNullValue()) 1585 return N1; 1586 // fold (mulhu x, 1) -> 0 1587 if (N1C && N1C->getAPIntValue() == 1) 1588 return DAG.getConstant(0, N0.getValueType()); 1589 // fold (mulhu x, undef) -> 0 1590 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1591 return DAG.getConstant(0, VT); 1592 1593 return SDValue(); 1594} 1595 1596/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1597/// compute two values. LoOp and HiOp give the opcodes for the two computations 1598/// that are being performed. Return true if a simplification was made. 1599/// 1600SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1601 unsigned HiOp) { 1602 // If the high half is not needed, just compute the low half. 1603 bool HiExists = N->hasAnyUseOfValue(1); 1604 if (!HiExists && 1605 (!LegalOperations || 1606 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1607 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1608 N->op_begin(), N->getNumOperands()); 1609 return CombineTo(N, Res, Res); 1610 } 1611 1612 // If the low half is not needed, just compute the high half. 1613 bool LoExists = N->hasAnyUseOfValue(0); 1614 if (!LoExists && 1615 (!LegalOperations || 1616 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1617 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1618 N->op_begin(), N->getNumOperands()); 1619 return CombineTo(N, Res, Res); 1620 } 1621 1622 // If both halves are used, return as it is. 1623 if (LoExists && HiExists) 1624 return SDValue(); 1625 1626 // If the two computed results can be simplified separately, separate them. 1627 if (LoExists) { 1628 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1629 N->op_begin(), N->getNumOperands()); 1630 AddToWorkList(Lo.getNode()); 1631 SDValue LoOpt = combine(Lo.getNode()); 1632 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1633 (!LegalOperations || 1634 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1635 return CombineTo(N, LoOpt, LoOpt); 1636 } 1637 1638 if (HiExists) { 1639 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1640 N->op_begin(), N->getNumOperands()); 1641 AddToWorkList(Hi.getNode()); 1642 SDValue HiOpt = combine(Hi.getNode()); 1643 if (HiOpt.getNode() && HiOpt != Hi && 1644 (!LegalOperations || 1645 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1646 return CombineTo(N, HiOpt, HiOpt); 1647 } 1648 1649 return SDValue(); 1650} 1651 1652SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1653 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1654 if (Res.getNode()) return Res; 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1660 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1661 if (Res.getNode()) return Res; 1662 1663 return SDValue(); 1664} 1665 1666SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1667 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1668 if (Res.getNode()) return Res; 1669 1670 return SDValue(); 1671} 1672 1673SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1674 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1675 if (Res.getNode()) return Res; 1676 1677 return SDValue(); 1678} 1679 1680/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1681/// two operands of the same opcode, try to simplify it. 1682SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1683 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1684 EVT VT = N0.getValueType(); 1685 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1686 1687 // For each of OP in AND/OR/XOR: 1688 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1689 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1690 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1691 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1692 // 1693 // do not sink logical op inside of a vector extend, since it may combine 1694 // into a vsetcc. 1695 EVT Op0VT = N0.getOperand(0).getValueType(); 1696 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 1697 N0.getOpcode() == ISD::ANY_EXTEND || 1698 N0.getOpcode() == ISD::SIGN_EXTEND || 1699 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) && 1700 !VT.isVector() && 1701 Op0VT == N1.getOperand(0).getValueType() && 1702 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 1703 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1704 N0.getOperand(0).getValueType(), 1705 N0.getOperand(0), N1.getOperand(0)); 1706 AddToWorkList(ORNode.getNode()); 1707 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1708 } 1709 1710 // For each of OP in SHL/SRL/SRA/AND... 1711 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1712 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1713 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1714 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1715 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1716 N0.getOperand(1) == N1.getOperand(1)) { 1717 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1718 N0.getOperand(0).getValueType(), 1719 N0.getOperand(0), N1.getOperand(0)); 1720 AddToWorkList(ORNode.getNode()); 1721 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1722 ORNode, N0.getOperand(1)); 1723 } 1724 1725 return SDValue(); 1726} 1727 1728SDValue DAGCombiner::visitAND(SDNode *N) { 1729 SDValue N0 = N->getOperand(0); 1730 SDValue N1 = N->getOperand(1); 1731 SDValue LL, LR, RL, RR, CC0, CC1; 1732 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1733 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1734 EVT VT = N1.getValueType(); 1735 unsigned BitWidth = VT.getSizeInBits(); 1736 1737 // fold vector ops 1738 if (VT.isVector()) { 1739 SDValue FoldedVOp = SimplifyVBinOp(N); 1740 if (FoldedVOp.getNode()) return FoldedVOp; 1741 } 1742 1743 // fold (and x, undef) -> 0 1744 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1745 return DAG.getConstant(0, VT); 1746 // fold (and c1, c2) -> c1&c2 1747 if (N0C && N1C) 1748 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1749 // canonicalize constant to RHS 1750 if (N0C && !N1C) 1751 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1752 // fold (and x, -1) -> x 1753 if (N1C && N1C->isAllOnesValue()) 1754 return N0; 1755 // if (and x, c) is known to be zero, return 0 1756 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1757 APInt::getAllOnesValue(BitWidth))) 1758 return DAG.getConstant(0, VT); 1759 // reassociate and 1760 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1761 if (RAND.getNode() != 0) 1762 return RAND; 1763 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1764 if (N1C && N0.getOpcode() == ISD::OR) 1765 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1766 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1767 return N1; 1768 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1769 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1770 SDValue N0Op0 = N0.getOperand(0); 1771 APInt Mask = ~N1C->getAPIntValue(); 1772 Mask.trunc(N0Op0.getValueSizeInBits()); 1773 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1774 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1775 N0.getValueType(), N0Op0); 1776 1777 // Replace uses of the AND with uses of the Zero extend node. 1778 CombineTo(N, Zext); 1779 1780 // We actually want to replace all uses of the any_extend with the 1781 // zero_extend, to avoid duplicating things. This will later cause this 1782 // AND to be folded. 1783 CombineTo(N0.getNode(), Zext); 1784 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1785 } 1786 } 1787 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1788 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1789 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1790 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1791 1792 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1793 LL.getValueType().isInteger()) { 1794 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1795 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1796 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1797 LR.getValueType(), LL, RL); 1798 AddToWorkList(ORNode.getNode()); 1799 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1800 } 1801 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1802 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1803 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1804 LR.getValueType(), LL, RL); 1805 AddToWorkList(ANDNode.getNode()); 1806 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1807 } 1808 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1809 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1810 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1811 LR.getValueType(), LL, RL); 1812 AddToWorkList(ORNode.getNode()); 1813 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1814 } 1815 } 1816 // canonicalize equivalent to ll == rl 1817 if (LL == RR && LR == RL) { 1818 Op1 = ISD::getSetCCSwappedOperands(Op1); 1819 std::swap(RL, RR); 1820 } 1821 if (LL == RL && LR == RR) { 1822 bool isInteger = LL.getValueType().isInteger(); 1823 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1824 if (Result != ISD::SETCC_INVALID && 1825 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1826 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1827 LL, LR, Result); 1828 } 1829 } 1830 1831 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1832 if (N0.getOpcode() == N1.getOpcode()) { 1833 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1834 if (Tmp.getNode()) return Tmp; 1835 } 1836 1837 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1838 // fold (and (sra)) -> (and (srl)) when possible. 1839 if (!VT.isVector() && 1840 SimplifyDemandedBits(SDValue(N, 0))) 1841 return SDValue(N, 0); 1842 1843 // fold (zext_inreg (extload x)) -> (zextload x) 1844 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1845 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1846 EVT MemVT = LN0->getMemoryVT(); 1847 // If we zero all the possible extended bits, then we can turn this into 1848 // a zextload if we are running before legalize or the operation is legal. 1849 unsigned BitWidth = N1.getValueSizeInBits(); 1850 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1851 BitWidth - MemVT.getSizeInBits())) && 1852 ((!LegalOperations && !LN0->isVolatile()) || 1853 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1854 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1855 LN0->getChain(), LN0->getBasePtr(), 1856 LN0->getSrcValue(), 1857 LN0->getSrcValueOffset(), MemVT, 1858 LN0->isVolatile(), LN0->getAlignment()); 1859 AddToWorkList(N); 1860 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1861 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1862 } 1863 } 1864 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1865 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1866 N0.hasOneUse()) { 1867 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1868 EVT MemVT = LN0->getMemoryVT(); 1869 // If we zero all the possible extended bits, then we can turn this into 1870 // a zextload if we are running before legalize or the operation is legal. 1871 unsigned BitWidth = N1.getValueSizeInBits(); 1872 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1873 BitWidth - MemVT.getSizeInBits())) && 1874 ((!LegalOperations && !LN0->isVolatile()) || 1875 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1876 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1877 LN0->getChain(), 1878 LN0->getBasePtr(), LN0->getSrcValue(), 1879 LN0->getSrcValueOffset(), MemVT, 1880 LN0->isVolatile(), LN0->getAlignment()); 1881 AddToWorkList(N); 1882 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1883 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1884 } 1885 } 1886 1887 // fold (and (load x), 255) -> (zextload x, i8) 1888 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1889 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 1890 if (N1C && (N0.getOpcode() == ISD::LOAD || 1891 (N0.getOpcode() == ISD::ANY_EXTEND && 1892 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 1893 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 1894 LoadSDNode *LN0 = HasAnyExt 1895 ? cast<LoadSDNode>(N0.getOperand(0)) 1896 : cast<LoadSDNode>(N0); 1897 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1898 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 1899 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1900 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 1901 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 1902 EVT LoadedVT = LN0->getMemoryVT(); 1903 1904 if (ExtVT == LoadedVT && 1905 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1906 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1907 1908 SDValue NewLoad = 1909 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1910 LN0->getChain(), LN0->getBasePtr(), 1911 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1912 ExtVT, LN0->isVolatile(), LN0->getAlignment()); 1913 AddToWorkList(N); 1914 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 1915 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1916 } 1917 1918 // Do not change the width of a volatile load. 1919 // Do not generate loads of non-round integer types since these can 1920 // be expensive (and would be wrong if the type is not byte sized). 1921 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 1922 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1923 EVT PtrType = LN0->getOperand(1).getValueType(); 1924 1925 unsigned Alignment = LN0->getAlignment(); 1926 SDValue NewPtr = LN0->getBasePtr(); 1927 1928 // For big endian targets, we need to add an offset to the pointer 1929 // to load the correct bytes. For little endian systems, we merely 1930 // need to read fewer bytes from the same pointer. 1931 if (TLI.isBigEndian()) { 1932 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 1933 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 1934 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1935 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1936 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1937 Alignment = MinAlign(Alignment, PtrOff); 1938 } 1939 1940 AddToWorkList(NewPtr.getNode()); 1941 1942 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1943 SDValue Load = 1944 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1945 LN0->getChain(), NewPtr, 1946 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1947 ExtVT, LN0->isVolatile(), Alignment); 1948 AddToWorkList(N); 1949 CombineTo(LN0, Load, Load.getValue(1)); 1950 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1951 } 1952 } 1953 } 1954 } 1955 1956 return SDValue(); 1957} 1958 1959SDValue DAGCombiner::visitOR(SDNode *N) { 1960 SDValue N0 = N->getOperand(0); 1961 SDValue N1 = N->getOperand(1); 1962 SDValue LL, LR, RL, RR, CC0, CC1; 1963 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1964 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1965 EVT VT = N1.getValueType(); 1966 1967 // fold vector ops 1968 if (VT.isVector()) { 1969 SDValue FoldedVOp = SimplifyVBinOp(N); 1970 if (FoldedVOp.getNode()) return FoldedVOp; 1971 } 1972 1973 // fold (or x, undef) -> -1 1974 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 1975 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 1976 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 1977 } 1978 // fold (or c1, c2) -> c1|c2 1979 if (N0C && N1C) 1980 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1981 // canonicalize constant to RHS 1982 if (N0C && !N1C) 1983 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1984 // fold (or x, 0) -> x 1985 if (N1C && N1C->isNullValue()) 1986 return N0; 1987 // fold (or x, -1) -> -1 1988 if (N1C && N1C->isAllOnesValue()) 1989 return N1; 1990 // fold (or x, c) -> c iff (x & ~c) == 0 1991 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1992 return N1; 1993 // reassociate or 1994 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1995 if (ROR.getNode() != 0) 1996 return ROR; 1997 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1998 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1999 isa<ConstantSDNode>(N0.getOperand(1))) { 2000 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2001 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2002 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2003 N0.getOperand(0), N1), 2004 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2005 } 2006 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2007 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2008 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2009 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2010 2011 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2012 LL.getValueType().isInteger()) { 2013 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2014 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2015 if (cast<ConstantSDNode>(LR)->isNullValue() && 2016 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2017 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2018 LR.getValueType(), LL, RL); 2019 AddToWorkList(ORNode.getNode()); 2020 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2021 } 2022 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2023 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2024 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2025 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2026 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2027 LR.getValueType(), LL, RL); 2028 AddToWorkList(ANDNode.getNode()); 2029 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2030 } 2031 } 2032 // canonicalize equivalent to ll == rl 2033 if (LL == RR && LR == RL) { 2034 Op1 = ISD::getSetCCSwappedOperands(Op1); 2035 std::swap(RL, RR); 2036 } 2037 if (LL == RL && LR == RR) { 2038 bool isInteger = LL.getValueType().isInteger(); 2039 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2040 if (Result != ISD::SETCC_INVALID && 2041 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2042 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2043 LL, LR, Result); 2044 } 2045 } 2046 2047 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2048 if (N0.getOpcode() == N1.getOpcode()) { 2049 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2050 if (Tmp.getNode()) return Tmp; 2051 } 2052 2053 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2054 if (N0.getOpcode() == ISD::AND && 2055 N1.getOpcode() == ISD::AND && 2056 N0.getOperand(1).getOpcode() == ISD::Constant && 2057 N1.getOperand(1).getOpcode() == ISD::Constant && 2058 // Don't increase # computations. 2059 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2060 // We can only do this xform if we know that bits from X that are set in C2 2061 // but not in C1 are already zero. Likewise for Y. 2062 const APInt &LHSMask = 2063 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2064 const APInt &RHSMask = 2065 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2066 2067 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2068 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2069 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2070 N0.getOperand(0), N1.getOperand(0)); 2071 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2072 DAG.getConstant(LHSMask | RHSMask, VT)); 2073 } 2074 } 2075 2076 // See if this is some rotate idiom. 2077 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2078 return SDValue(Rot, 0); 2079 2080 return SDValue(); 2081} 2082 2083/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2084static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2085 if (Op.getOpcode() == ISD::AND) { 2086 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2087 Mask = Op.getOperand(1); 2088 Op = Op.getOperand(0); 2089 } else { 2090 return false; 2091 } 2092 } 2093 2094 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2095 Shift = Op; 2096 return true; 2097 } 2098 2099 return false; 2100} 2101 2102// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2103// idioms for rotate, and if the target supports rotation instructions, generate 2104// a rot[lr]. 2105SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2106 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2107 EVT VT = LHS.getValueType(); 2108 if (!TLI.isTypeLegal(VT)) return 0; 2109 2110 // The target must have at least one rotate flavor. 2111 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2112 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2113 if (!HasROTL && !HasROTR) return 0; 2114 2115 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2116 SDValue LHSShift; // The shift. 2117 SDValue LHSMask; // AND value if any. 2118 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2119 return 0; // Not part of a rotate. 2120 2121 SDValue RHSShift; // The shift. 2122 SDValue RHSMask; // AND value if any. 2123 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2124 return 0; // Not part of a rotate. 2125 2126 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2127 return 0; // Not shifting the same value. 2128 2129 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2130 return 0; // Shifts must disagree. 2131 2132 // Canonicalize shl to left side in a shl/srl pair. 2133 if (RHSShift.getOpcode() == ISD::SHL) { 2134 std::swap(LHS, RHS); 2135 std::swap(LHSShift, RHSShift); 2136 std::swap(LHSMask , RHSMask ); 2137 } 2138 2139 unsigned OpSizeInBits = VT.getSizeInBits(); 2140 SDValue LHSShiftArg = LHSShift.getOperand(0); 2141 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2142 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2143 2144 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2145 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2146 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2147 RHSShiftAmt.getOpcode() == ISD::Constant) { 2148 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2149 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2150 if ((LShVal + RShVal) != OpSizeInBits) 2151 return 0; 2152 2153 SDValue Rot; 2154 if (HasROTL) 2155 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2156 else 2157 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2158 2159 // If there is an AND of either shifted operand, apply it to the result. 2160 if (LHSMask.getNode() || RHSMask.getNode()) { 2161 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2162 2163 if (LHSMask.getNode()) { 2164 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2165 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2166 } 2167 if (RHSMask.getNode()) { 2168 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2169 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2170 } 2171 2172 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2173 } 2174 2175 return Rot.getNode(); 2176 } 2177 2178 // If there is a mask here, and we have a variable shift, we can't be sure 2179 // that we're masking out the right stuff. 2180 if (LHSMask.getNode() || RHSMask.getNode()) 2181 return 0; 2182 2183 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2184 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2185 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2186 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2187 if (ConstantSDNode *SUBC = 2188 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2189 if (SUBC->getAPIntValue() == OpSizeInBits) { 2190 if (HasROTL) 2191 return DAG.getNode(ISD::ROTL, DL, VT, 2192 LHSShiftArg, LHSShiftAmt).getNode(); 2193 else 2194 return DAG.getNode(ISD::ROTR, DL, VT, 2195 LHSShiftArg, RHSShiftAmt).getNode(); 2196 } 2197 } 2198 } 2199 2200 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2201 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2202 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2203 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2204 if (ConstantSDNode *SUBC = 2205 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2206 if (SUBC->getAPIntValue() == OpSizeInBits) { 2207 if (HasROTR) 2208 return DAG.getNode(ISD::ROTR, DL, VT, 2209 LHSShiftArg, RHSShiftAmt).getNode(); 2210 else 2211 return DAG.getNode(ISD::ROTL, DL, VT, 2212 LHSShiftArg, LHSShiftAmt).getNode(); 2213 } 2214 } 2215 } 2216 2217 // Look for sign/zext/any-extended or truncate cases: 2218 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2219 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2220 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2221 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2222 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2223 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2224 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2225 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2226 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2227 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2228 if (RExtOp0.getOpcode() == ISD::SUB && 2229 RExtOp0.getOperand(1) == LExtOp0) { 2230 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2231 // (rotl x, y) 2232 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2233 // (rotr x, (sub 32, y)) 2234 if (ConstantSDNode *SUBC = 2235 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2236 if (SUBC->getAPIntValue() == OpSizeInBits) { 2237 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2238 LHSShiftArg, 2239 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2240 } 2241 } 2242 } else if (LExtOp0.getOpcode() == ISD::SUB && 2243 RExtOp0 == LExtOp0.getOperand(1)) { 2244 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2245 // (rotr x, y) 2246 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2247 // (rotl x, (sub 32, y)) 2248 if (ConstantSDNode *SUBC = 2249 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2250 if (SUBC->getAPIntValue() == OpSizeInBits) { 2251 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2252 LHSShiftArg, 2253 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2254 } 2255 } 2256 } 2257 } 2258 2259 return 0; 2260} 2261 2262SDValue DAGCombiner::visitXOR(SDNode *N) { 2263 SDValue N0 = N->getOperand(0); 2264 SDValue N1 = N->getOperand(1); 2265 SDValue LHS, RHS, CC; 2266 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2267 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2268 EVT VT = N0.getValueType(); 2269 2270 // fold vector ops 2271 if (VT.isVector()) { 2272 SDValue FoldedVOp = SimplifyVBinOp(N); 2273 if (FoldedVOp.getNode()) return FoldedVOp; 2274 } 2275 2276 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2277 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2278 return DAG.getConstant(0, VT); 2279 // fold (xor x, undef) -> undef 2280 if (N0.getOpcode() == ISD::UNDEF) 2281 return N0; 2282 if (N1.getOpcode() == ISD::UNDEF) 2283 return N1; 2284 // fold (xor c1, c2) -> c1^c2 2285 if (N0C && N1C) 2286 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2287 // canonicalize constant to RHS 2288 if (N0C && !N1C) 2289 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2290 // fold (xor x, 0) -> x 2291 if (N1C && N1C->isNullValue()) 2292 return N0; 2293 // reassociate xor 2294 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2295 if (RXOR.getNode() != 0) 2296 return RXOR; 2297 2298 // fold !(x cc y) -> (x !cc y) 2299 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2300 bool isInt = LHS.getValueType().isInteger(); 2301 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2302 isInt); 2303 2304 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2305 switch (N0.getOpcode()) { 2306 default: 2307 llvm_unreachable("Unhandled SetCC Equivalent!"); 2308 case ISD::SETCC: 2309 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2310 case ISD::SELECT_CC: 2311 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2312 N0.getOperand(3), NotCC); 2313 } 2314 } 2315 } 2316 2317 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2318 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2319 N0.getNode()->hasOneUse() && 2320 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2321 SDValue V = N0.getOperand(0); 2322 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2323 DAG.getConstant(1, V.getValueType())); 2324 AddToWorkList(V.getNode()); 2325 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2326 } 2327 2328 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2329 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2330 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2331 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2332 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2333 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2334 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2335 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2336 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2337 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2338 } 2339 } 2340 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2341 if (N1C && N1C->isAllOnesValue() && 2342 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2343 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2344 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2345 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2346 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2347 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2348 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2349 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2350 } 2351 } 2352 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2353 if (N1C && N0.getOpcode() == ISD::XOR) { 2354 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2355 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2356 if (N00C) 2357 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2358 DAG.getConstant(N1C->getAPIntValue() ^ 2359 N00C->getAPIntValue(), VT)); 2360 if (N01C) 2361 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2362 DAG.getConstant(N1C->getAPIntValue() ^ 2363 N01C->getAPIntValue(), VT)); 2364 } 2365 // fold (xor x, x) -> 0 2366 if (N0 == N1) { 2367 if (!VT.isVector()) { 2368 return DAG.getConstant(0, VT); 2369 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2370 // Produce a vector of zeros. 2371 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2372 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2373 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2374 &Ops[0], Ops.size()); 2375 } 2376 } 2377 2378 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2379 if (N0.getOpcode() == N1.getOpcode()) { 2380 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2381 if (Tmp.getNode()) return Tmp; 2382 } 2383 2384 // Simplify the expression using non-local knowledge. 2385 if (!VT.isVector() && 2386 SimplifyDemandedBits(SDValue(N, 0))) 2387 return SDValue(N, 0); 2388 2389 return SDValue(); 2390} 2391 2392/// visitShiftByConstant - Handle transforms common to the three shifts, when 2393/// the shift amount is a constant. 2394SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2395 SDNode *LHS = N->getOperand(0).getNode(); 2396 if (!LHS->hasOneUse()) return SDValue(); 2397 2398 // We want to pull some binops through shifts, so that we have (and (shift)) 2399 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2400 // thing happens with address calculations, so it's important to canonicalize 2401 // it. 2402 bool HighBitSet = false; // Can we transform this if the high bit is set? 2403 2404 switch (LHS->getOpcode()) { 2405 default: return SDValue(); 2406 case ISD::OR: 2407 case ISD::XOR: 2408 HighBitSet = false; // We can only transform sra if the high bit is clear. 2409 break; 2410 case ISD::AND: 2411 HighBitSet = true; // We can only transform sra if the high bit is set. 2412 break; 2413 case ISD::ADD: 2414 if (N->getOpcode() != ISD::SHL) 2415 return SDValue(); // only shl(add) not sr[al](add). 2416 HighBitSet = false; // We can only transform sra if the high bit is clear. 2417 break; 2418 } 2419 2420 // We require the RHS of the binop to be a constant as well. 2421 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2422 if (!BinOpCst) return SDValue(); 2423 2424 // FIXME: disable this unless the input to the binop is a shift by a constant. 2425 // If it is not a shift, it pessimizes some common cases like: 2426 // 2427 // void foo(int *X, int i) { X[i & 1235] = 1; } 2428 // int bar(int *X, int i) { return X[i & 255]; } 2429 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2430 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2431 BinOpLHSVal->getOpcode() != ISD::SRA && 2432 BinOpLHSVal->getOpcode() != ISD::SRL) || 2433 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2434 return SDValue(); 2435 2436 EVT VT = N->getValueType(0); 2437 2438 // If this is a signed shift right, and the high bit is modified by the 2439 // logical operation, do not perform the transformation. The highBitSet 2440 // boolean indicates the value of the high bit of the constant which would 2441 // cause it to be modified for this operation. 2442 if (N->getOpcode() == ISD::SRA) { 2443 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2444 if (BinOpRHSSignSet != HighBitSet) 2445 return SDValue(); 2446 } 2447 2448 // Fold the constants, shifting the binop RHS by the shift amount. 2449 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2450 N->getValueType(0), 2451 LHS->getOperand(1), N->getOperand(1)); 2452 2453 // Create the new shift. 2454 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2455 VT, LHS->getOperand(0), N->getOperand(1)); 2456 2457 // Create the new binop. 2458 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2459} 2460 2461SDValue DAGCombiner::visitSHL(SDNode *N) { 2462 SDValue N0 = N->getOperand(0); 2463 SDValue N1 = N->getOperand(1); 2464 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2465 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2466 EVT VT = N0.getValueType(); 2467 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2468 2469 // fold (shl c1, c2) -> c1<<c2 2470 if (N0C && N1C) 2471 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2472 // fold (shl 0, x) -> 0 2473 if (N0C && N0C->isNullValue()) 2474 return N0; 2475 // fold (shl x, c >= size(x)) -> undef 2476 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2477 return DAG.getUNDEF(VT); 2478 // fold (shl x, 0) -> x 2479 if (N1C && N1C->isNullValue()) 2480 return N0; 2481 // if (shl x, c) is known to be zero, return 0 2482 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2483 APInt::getAllOnesValue(OpSizeInBits))) 2484 return DAG.getConstant(0, VT); 2485 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2486 if (N1.getOpcode() == ISD::TRUNCATE && 2487 N1.getOperand(0).getOpcode() == ISD::AND && 2488 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2489 SDValue N101 = N1.getOperand(0).getOperand(1); 2490 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2491 EVT TruncVT = N1.getValueType(); 2492 SDValue N100 = N1.getOperand(0).getOperand(0); 2493 APInt TruncC = N101C->getAPIntValue(); 2494 TruncC.trunc(TruncVT.getSizeInBits()); 2495 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2496 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2497 DAG.getNode(ISD::TRUNCATE, 2498 N->getDebugLoc(), 2499 TruncVT, N100), 2500 DAG.getConstant(TruncC, TruncVT))); 2501 } 2502 } 2503 2504 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2505 return SDValue(N, 0); 2506 2507 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2508 if (N1C && N0.getOpcode() == ISD::SHL && 2509 N0.getOperand(1).getOpcode() == ISD::Constant) { 2510 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2511 uint64_t c2 = N1C->getZExtValue(); 2512 if (c1 + c2 > OpSizeInBits) 2513 return DAG.getConstant(0, VT); 2514 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2515 DAG.getConstant(c1 + c2, N1.getValueType())); 2516 } 2517 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2518 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2519 if (N1C && N0.getOpcode() == ISD::SRL && 2520 N0.getOperand(1).getOpcode() == ISD::Constant) { 2521 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2522 if (c1 < VT.getSizeInBits()) { 2523 uint64_t c2 = N1C->getZExtValue(); 2524 SDValue HiBitsMask = 2525 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2526 VT.getSizeInBits() - c1), 2527 VT); 2528 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2529 N0.getOperand(0), 2530 HiBitsMask); 2531 if (c2 > c1) 2532 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2533 DAG.getConstant(c2-c1, N1.getValueType())); 2534 else 2535 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2536 DAG.getConstant(c1-c2, N1.getValueType())); 2537 } 2538 } 2539 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2540 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2541 SDValue HiBitsMask = 2542 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2543 VT.getSizeInBits() - 2544 N1C->getZExtValue()), 2545 VT); 2546 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2547 HiBitsMask); 2548 } 2549 2550 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2551} 2552 2553SDValue DAGCombiner::visitSRA(SDNode *N) { 2554 SDValue N0 = N->getOperand(0); 2555 SDValue N1 = N->getOperand(1); 2556 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2557 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2558 EVT VT = N0.getValueType(); 2559 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2560 2561 // fold (sra c1, c2) -> (sra c1, c2) 2562 if (N0C && N1C) 2563 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2564 // fold (sra 0, x) -> 0 2565 if (N0C && N0C->isNullValue()) 2566 return N0; 2567 // fold (sra -1, x) -> -1 2568 if (N0C && N0C->isAllOnesValue()) 2569 return N0; 2570 // fold (sra x, (setge c, size(x))) -> undef 2571 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2572 return DAG.getUNDEF(VT); 2573 // fold (sra x, 0) -> x 2574 if (N1C && N1C->isNullValue()) 2575 return N0; 2576 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2577 // sext_inreg. 2578 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2579 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2580 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2581 if (VT.isVector()) 2582 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2583 ExtVT, VT.getVectorNumElements()); 2584 if ((!LegalOperations || 2585 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2586 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2587 N0.getOperand(0), DAG.getValueType(ExtVT)); 2588 } 2589 2590 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2591 if (N1C && N0.getOpcode() == ISD::SRA) { 2592 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2593 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2594 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2595 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2596 DAG.getConstant(Sum, N1C->getValueType(0))); 2597 } 2598 } 2599 2600 // fold (sra (shl X, m), (sub result_size, n)) 2601 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2602 // result_size - n != m. 2603 // If truncate is free for the target sext(shl) is likely to result in better 2604 // code. 2605 if (N0.getOpcode() == ISD::SHL) { 2606 // Get the two constanst of the shifts, CN0 = m, CN = n. 2607 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2608 if (N01C && N1C) { 2609 // Determine what the truncate's result bitsize and type would be. 2610 EVT TruncVT = 2611 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2612 // Determine the residual right-shift amount. 2613 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2614 2615 // If the shift is not a no-op (in which case this should be just a sign 2616 // extend already), the truncated to type is legal, sign_extend is legal 2617 // on that type, and the the truncate to that type is both legal and free, 2618 // perform the transform. 2619 if ((ShiftAmt > 0) && 2620 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2621 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2622 TLI.isTruncateFree(VT, TruncVT)) { 2623 2624 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2625 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2626 N0.getOperand(0), Amt); 2627 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2628 Shift); 2629 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2630 N->getValueType(0), Trunc); 2631 } 2632 } 2633 } 2634 2635 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2636 if (N1.getOpcode() == ISD::TRUNCATE && 2637 N1.getOperand(0).getOpcode() == ISD::AND && 2638 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2639 SDValue N101 = N1.getOperand(0).getOperand(1); 2640 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2641 EVT TruncVT = N1.getValueType(); 2642 SDValue N100 = N1.getOperand(0).getOperand(0); 2643 APInt TruncC = N101C->getAPIntValue(); 2644 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 2645 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2646 DAG.getNode(ISD::AND, N->getDebugLoc(), 2647 TruncVT, 2648 DAG.getNode(ISD::TRUNCATE, 2649 N->getDebugLoc(), 2650 TruncVT, N100), 2651 DAG.getConstant(TruncC, TruncVT))); 2652 } 2653 } 2654 2655 // Simplify, based on bits shifted out of the LHS. 2656 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2657 return SDValue(N, 0); 2658 2659 2660 // If the sign bit is known to be zero, switch this to a SRL. 2661 if (DAG.SignBitIsZero(N0)) 2662 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2663 2664 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2665} 2666 2667SDValue DAGCombiner::visitSRL(SDNode *N) { 2668 SDValue N0 = N->getOperand(0); 2669 SDValue N1 = N->getOperand(1); 2670 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2671 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2672 EVT VT = N0.getValueType(); 2673 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2674 2675 // fold (srl c1, c2) -> c1 >>u c2 2676 if (N0C && N1C) 2677 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2678 // fold (srl 0, x) -> 0 2679 if (N0C && N0C->isNullValue()) 2680 return N0; 2681 // fold (srl x, c >= size(x)) -> undef 2682 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2683 return DAG.getUNDEF(VT); 2684 // fold (srl x, 0) -> x 2685 if (N1C && N1C->isNullValue()) 2686 return N0; 2687 // if (srl x, c) is known to be zero, return 0 2688 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2689 APInt::getAllOnesValue(OpSizeInBits))) 2690 return DAG.getConstant(0, VT); 2691 2692 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2693 if (N1C && N0.getOpcode() == ISD::SRL && 2694 N0.getOperand(1).getOpcode() == ISD::Constant) { 2695 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2696 uint64_t c2 = N1C->getZExtValue(); 2697 if (c1 + c2 > OpSizeInBits) 2698 return DAG.getConstant(0, VT); 2699 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2700 DAG.getConstant(c1 + c2, N1.getValueType())); 2701 } 2702 2703 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2704 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2705 // Shifting in all undef bits? 2706 EVT SmallVT = N0.getOperand(0).getValueType(); 2707 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2708 return DAG.getUNDEF(VT); 2709 2710 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2711 N0.getOperand(0), N1); 2712 AddToWorkList(SmallShift.getNode()); 2713 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2714 } 2715 2716 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2717 // bit, which is unmodified by sra. 2718 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2719 if (N0.getOpcode() == ISD::SRA) 2720 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2721 } 2722 2723 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2724 if (N1C && N0.getOpcode() == ISD::CTLZ && 2725 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2726 APInt KnownZero, KnownOne; 2727 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2728 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2729 2730 // If any of the input bits are KnownOne, then the input couldn't be all 2731 // zeros, thus the result of the srl will always be zero. 2732 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2733 2734 // If all of the bits input the to ctlz node are known to be zero, then 2735 // the result of the ctlz is "32" and the result of the shift is one. 2736 APInt UnknownBits = ~KnownZero & Mask; 2737 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2738 2739 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2740 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2741 // Okay, we know that only that the single bit specified by UnknownBits 2742 // could be set on input to the CTLZ node. If this bit is set, the SRL 2743 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2744 // to an SRL/XOR pair, which is likely to simplify more. 2745 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2746 SDValue Op = N0.getOperand(0); 2747 2748 if (ShAmt) { 2749 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2750 DAG.getConstant(ShAmt, getShiftAmountTy())); 2751 AddToWorkList(Op.getNode()); 2752 } 2753 2754 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2755 Op, DAG.getConstant(1, VT)); 2756 } 2757 } 2758 2759 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2760 if (N1.getOpcode() == ISD::TRUNCATE && 2761 N1.getOperand(0).getOpcode() == ISD::AND && 2762 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2763 SDValue N101 = N1.getOperand(0).getOperand(1); 2764 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2765 EVT TruncVT = N1.getValueType(); 2766 SDValue N100 = N1.getOperand(0).getOperand(0); 2767 APInt TruncC = N101C->getAPIntValue(); 2768 TruncC.trunc(TruncVT.getSizeInBits()); 2769 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2770 DAG.getNode(ISD::AND, N->getDebugLoc(), 2771 TruncVT, 2772 DAG.getNode(ISD::TRUNCATE, 2773 N->getDebugLoc(), 2774 TruncVT, N100), 2775 DAG.getConstant(TruncC, TruncVT))); 2776 } 2777 } 2778 2779 // fold operands of srl based on knowledge that the low bits are not 2780 // demanded. 2781 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2782 return SDValue(N, 0); 2783 2784 if (N1C) { 2785 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 2786 if (NewSRL.getNode()) 2787 return NewSRL; 2788 } 2789 2790 // Here is a common situation. We want to optimize: 2791 // 2792 // %a = ... 2793 // %b = and i32 %a, 2 2794 // %c = srl i32 %b, 1 2795 // brcond i32 %c ... 2796 // 2797 // into 2798 // 2799 // %a = ... 2800 // %b = and %a, 2 2801 // %c = setcc eq %b, 0 2802 // brcond %c ... 2803 // 2804 // However when after the source operand of SRL is optimized into AND, the SRL 2805 // itself may not be optimized further. Look for it and add the BRCOND into 2806 // the worklist. 2807 if (N->hasOneUse()) { 2808 SDNode *Use = *N->use_begin(); 2809 if (Use->getOpcode() == ISD::BRCOND) 2810 AddToWorkList(Use); 2811 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 2812 // Also look pass the truncate. 2813 Use = *Use->use_begin(); 2814 if (Use->getOpcode() == ISD::BRCOND) 2815 AddToWorkList(Use); 2816 } 2817 } 2818 2819 return SDValue(); 2820} 2821 2822SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2823 SDValue N0 = N->getOperand(0); 2824 EVT VT = N->getValueType(0); 2825 2826 // fold (ctlz c1) -> c2 2827 if (isa<ConstantSDNode>(N0)) 2828 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2829 return SDValue(); 2830} 2831 2832SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2833 SDValue N0 = N->getOperand(0); 2834 EVT VT = N->getValueType(0); 2835 2836 // fold (cttz c1) -> c2 2837 if (isa<ConstantSDNode>(N0)) 2838 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2839 return SDValue(); 2840} 2841 2842SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2843 SDValue N0 = N->getOperand(0); 2844 EVT VT = N->getValueType(0); 2845 2846 // fold (ctpop c1) -> c2 2847 if (isa<ConstantSDNode>(N0)) 2848 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2849 return SDValue(); 2850} 2851 2852SDValue DAGCombiner::visitSELECT(SDNode *N) { 2853 SDValue N0 = N->getOperand(0); 2854 SDValue N1 = N->getOperand(1); 2855 SDValue N2 = N->getOperand(2); 2856 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2858 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2859 EVT VT = N->getValueType(0); 2860 EVT VT0 = N0.getValueType(); 2861 2862 // fold (select C, X, X) -> X 2863 if (N1 == N2) 2864 return N1; 2865 // fold (select true, X, Y) -> X 2866 if (N0C && !N0C->isNullValue()) 2867 return N1; 2868 // fold (select false, X, Y) -> Y 2869 if (N0C && N0C->isNullValue()) 2870 return N2; 2871 // fold (select C, 1, X) -> (or C, X) 2872 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2873 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2874 // fold (select C, 0, 1) -> (xor C, 1) 2875 if (VT.isInteger() && 2876 (VT0 == MVT::i1 || 2877 (VT0.isInteger() && 2878 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2879 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2880 SDValue XORNode; 2881 if (VT == VT0) 2882 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2883 N0, DAG.getConstant(1, VT0)); 2884 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2885 N0, DAG.getConstant(1, VT0)); 2886 AddToWorkList(XORNode.getNode()); 2887 if (VT.bitsGT(VT0)) 2888 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2889 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2890 } 2891 // fold (select C, 0, X) -> (and (not C), X) 2892 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2893 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2894 AddToWorkList(NOTNode.getNode()); 2895 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2896 } 2897 // fold (select C, X, 1) -> (or (not C), X) 2898 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2899 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2900 AddToWorkList(NOTNode.getNode()); 2901 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2902 } 2903 // fold (select C, X, 0) -> (and C, X) 2904 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2905 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2906 // fold (select X, X, Y) -> (or X, Y) 2907 // fold (select X, 1, Y) -> (or X, Y) 2908 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2909 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2910 // fold (select X, Y, X) -> (and X, Y) 2911 // fold (select X, Y, 0) -> (and X, Y) 2912 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2913 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2914 2915 // If we can fold this based on the true/false value, do so. 2916 if (SimplifySelectOps(N, N1, N2)) 2917 return SDValue(N, 0); // Don't revisit N. 2918 2919 // fold selects based on a setcc into other things, such as min/max/abs 2920 if (N0.getOpcode() == ISD::SETCC) { 2921 // FIXME: 2922 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2923 // having to say they don't support SELECT_CC on every type the DAG knows 2924 // about, since there is no way to mark an opcode illegal at all value types 2925 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2926 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2927 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2928 N0.getOperand(0), N0.getOperand(1), 2929 N1, N2, N0.getOperand(2)); 2930 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2931 } 2932 2933 return SDValue(); 2934} 2935 2936SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2937 SDValue N0 = N->getOperand(0); 2938 SDValue N1 = N->getOperand(1); 2939 SDValue N2 = N->getOperand(2); 2940 SDValue N3 = N->getOperand(3); 2941 SDValue N4 = N->getOperand(4); 2942 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2943 2944 // fold select_cc lhs, rhs, x, x, cc -> x 2945 if (N2 == N3) 2946 return N2; 2947 2948 // Determine if the condition we're dealing with is constant 2949 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2950 N0, N1, CC, N->getDebugLoc(), false); 2951 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2952 2953 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2954 if (!SCCC->isNullValue()) 2955 return N2; // cond always true -> true val 2956 else 2957 return N3; // cond always false -> false val 2958 } 2959 2960 // Fold to a simpler select_cc 2961 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2962 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2963 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2964 SCC.getOperand(2)); 2965 2966 // If we can fold this based on the true/false value, do so. 2967 if (SimplifySelectOps(N, N2, N3)) 2968 return SDValue(N, 0); // Don't revisit N. 2969 2970 // fold select_cc into other things, such as min/max/abs 2971 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2972} 2973 2974SDValue DAGCombiner::visitSETCC(SDNode *N) { 2975 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2976 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2977 N->getDebugLoc()); 2978} 2979 2980// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2981// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2982// transformation. Returns true if extension are possible and the above 2983// mentioned transformation is profitable. 2984static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2985 unsigned ExtOpc, 2986 SmallVector<SDNode*, 4> &ExtendNodes, 2987 const TargetLowering &TLI) { 2988 bool HasCopyToRegUses = false; 2989 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2990 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2991 UE = N0.getNode()->use_end(); 2992 UI != UE; ++UI) { 2993 SDNode *User = *UI; 2994 if (User == N) 2995 continue; 2996 if (UI.getUse().getResNo() != N0.getResNo()) 2997 continue; 2998 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2999 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3000 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3001 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3002 // Sign bits will be lost after a zext. 3003 return false; 3004 bool Add = false; 3005 for (unsigned i = 0; i != 2; ++i) { 3006 SDValue UseOp = User->getOperand(i); 3007 if (UseOp == N0) 3008 continue; 3009 if (!isa<ConstantSDNode>(UseOp)) 3010 return false; 3011 Add = true; 3012 } 3013 if (Add) 3014 ExtendNodes.push_back(User); 3015 continue; 3016 } 3017 // If truncates aren't free and there are users we can't 3018 // extend, it isn't worthwhile. 3019 if (!isTruncFree) 3020 return false; 3021 // Remember if this value is live-out. 3022 if (User->getOpcode() == ISD::CopyToReg) 3023 HasCopyToRegUses = true; 3024 } 3025 3026 if (HasCopyToRegUses) { 3027 bool BothLiveOut = false; 3028 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3029 UI != UE; ++UI) { 3030 SDUse &Use = UI.getUse(); 3031 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3032 BothLiveOut = true; 3033 break; 3034 } 3035 } 3036 if (BothLiveOut) 3037 // Both unextended and extended values are live out. There had better be 3038 // good a reason for the transformation. 3039 return ExtendNodes.size(); 3040 } 3041 return true; 3042} 3043 3044SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3045 SDValue N0 = N->getOperand(0); 3046 EVT VT = N->getValueType(0); 3047 3048 // fold (sext c1) -> c1 3049 if (isa<ConstantSDNode>(N0)) 3050 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3051 3052 // fold (sext (sext x)) -> (sext x) 3053 // fold (sext (aext x)) -> (sext x) 3054 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3055 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3056 N0.getOperand(0)); 3057 3058 if (N0.getOpcode() == ISD::TRUNCATE) { 3059 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3060 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3061 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3062 if (NarrowLoad.getNode()) { 3063 if (NarrowLoad.getNode() != N0.getNode()) 3064 CombineTo(N0.getNode(), NarrowLoad); 3065 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3066 } 3067 3068 // See if the value being truncated is already sign extended. If so, just 3069 // eliminate the trunc/sext pair. 3070 SDValue Op = N0.getOperand(0); 3071 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3072 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3073 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3074 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3075 3076 if (OpBits == DestBits) { 3077 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3078 // bits, it is already ready. 3079 if (NumSignBits > DestBits-MidBits) 3080 return Op; 3081 } else if (OpBits < DestBits) { 3082 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3083 // bits, just sext from i32. 3084 if (NumSignBits > OpBits-MidBits) 3085 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3086 } else { 3087 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3088 // bits, just truncate to i32. 3089 if (NumSignBits > OpBits-MidBits) 3090 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3091 } 3092 3093 // fold (sext (truncate x)) -> (sextinreg x). 3094 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3095 N0.getValueType())) { 3096 if (OpBits < DestBits) 3097 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3098 else if (OpBits > DestBits) 3099 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3100 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3101 DAG.getValueType(N0.getValueType())); 3102 } 3103 } 3104 3105 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3106 if (ISD::isNON_EXTLoad(N0.getNode()) && 3107 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3108 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3109 bool DoXform = true; 3110 SmallVector<SDNode*, 4> SetCCs; 3111 if (!N0.hasOneUse()) 3112 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3113 if (DoXform) { 3114 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3115 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3116 LN0->getChain(), 3117 LN0->getBasePtr(), LN0->getSrcValue(), 3118 LN0->getSrcValueOffset(), 3119 N0.getValueType(), 3120 LN0->isVolatile(), LN0->getAlignment()); 3121 CombineTo(N, ExtLoad); 3122 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3123 N0.getValueType(), ExtLoad); 3124 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3125 3126 // Extend SetCC uses if necessary. 3127 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3128 SDNode *SetCC = SetCCs[i]; 3129 SmallVector<SDValue, 4> Ops; 3130 3131 for (unsigned j = 0; j != 2; ++j) { 3132 SDValue SOp = SetCC->getOperand(j); 3133 if (SOp == Trunc) 3134 Ops.push_back(ExtLoad); 3135 else 3136 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3137 N->getDebugLoc(), VT, SOp)); 3138 } 3139 3140 Ops.push_back(SetCC->getOperand(2)); 3141 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3142 SetCC->getValueType(0), 3143 &Ops[0], Ops.size())); 3144 } 3145 3146 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3147 } 3148 } 3149 3150 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3151 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3152 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3153 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3154 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3155 EVT MemVT = LN0->getMemoryVT(); 3156 if ((!LegalOperations && !LN0->isVolatile()) || 3157 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3158 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3159 LN0->getChain(), 3160 LN0->getBasePtr(), LN0->getSrcValue(), 3161 LN0->getSrcValueOffset(), MemVT, 3162 LN0->isVolatile(), LN0->getAlignment()); 3163 CombineTo(N, ExtLoad); 3164 CombineTo(N0.getNode(), 3165 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3166 N0.getValueType(), ExtLoad), 3167 ExtLoad.getValue(1)); 3168 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3169 } 3170 } 3171 3172 if (N0.getOpcode() == ISD::SETCC) { 3173 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3174 if (VT.isVector() && 3175 // We know that the # elements of the results is the same as the 3176 // # elements of the compare (and the # elements of the compare result 3177 // for that matter). Check to see that they are the same size. If so, 3178 // we know that the element size of the sext'd result matches the 3179 // element size of the compare operands. 3180 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3181 3182 // Only do this before legalize for now. 3183 !LegalOperations) { 3184 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3185 N0.getOperand(1), 3186 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3187 } 3188 3189 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3190 SDValue NegOne = 3191 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3192 SDValue SCC = 3193 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3194 NegOne, DAG.getConstant(0, VT), 3195 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3196 if (SCC.getNode()) return SCC; 3197 } 3198 3199 3200 3201 // fold (sext x) -> (zext x) if the sign bit is known zero. 3202 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3203 DAG.SignBitIsZero(N0)) 3204 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3205 3206 return SDValue(); 3207} 3208 3209SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3210 SDValue N0 = N->getOperand(0); 3211 EVT VT = N->getValueType(0); 3212 3213 // fold (zext c1) -> c1 3214 if (isa<ConstantSDNode>(N0)) 3215 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3216 // fold (zext (zext x)) -> (zext x) 3217 // fold (zext (aext x)) -> (zext x) 3218 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3219 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3220 N0.getOperand(0)); 3221 3222 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3223 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3224 if (N0.getOpcode() == ISD::TRUNCATE) { 3225 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3226 if (NarrowLoad.getNode()) { 3227 if (NarrowLoad.getNode() != N0.getNode()) 3228 CombineTo(N0.getNode(), NarrowLoad); 3229 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3230 } 3231 } 3232 3233 // fold (zext (truncate x)) -> (and x, mask) 3234 if (N0.getOpcode() == ISD::TRUNCATE && 3235 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) && 3236 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(), 3237 N0.getValueType()) || 3238 !TLI.isZExtFree(N0.getValueType(), VT))) { 3239 SDValue Op = N0.getOperand(0); 3240 if (Op.getValueType().bitsLT(VT)) { 3241 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3242 } else if (Op.getValueType().bitsGT(VT)) { 3243 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3244 } 3245 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3246 N0.getValueType().getScalarType()); 3247 } 3248 3249 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3250 // if either of the casts is not free. 3251 if (N0.getOpcode() == ISD::AND && 3252 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3253 N0.getOperand(1).getOpcode() == ISD::Constant && 3254 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3255 N0.getValueType()) || 3256 !TLI.isZExtFree(N0.getValueType(), VT))) { 3257 SDValue X = N0.getOperand(0).getOperand(0); 3258 if (X.getValueType().bitsLT(VT)) { 3259 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3260 } else if (X.getValueType().bitsGT(VT)) { 3261 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3262 } 3263 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3264 Mask.zext(VT.getSizeInBits()); 3265 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3266 X, DAG.getConstant(Mask, VT)); 3267 } 3268 3269 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3270 if (ISD::isNON_EXTLoad(N0.getNode()) && 3271 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3272 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3273 bool DoXform = true; 3274 SmallVector<SDNode*, 4> SetCCs; 3275 if (!N0.hasOneUse()) 3276 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3277 if (DoXform) { 3278 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3279 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3280 LN0->getChain(), 3281 LN0->getBasePtr(), LN0->getSrcValue(), 3282 LN0->getSrcValueOffset(), 3283 N0.getValueType(), 3284 LN0->isVolatile(), LN0->getAlignment()); 3285 CombineTo(N, ExtLoad); 3286 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3287 N0.getValueType(), ExtLoad); 3288 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3289 3290 // Extend SetCC uses if necessary. 3291 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3292 SDNode *SetCC = SetCCs[i]; 3293 SmallVector<SDValue, 4> Ops; 3294 3295 for (unsigned j = 0; j != 2; ++j) { 3296 SDValue SOp = SetCC->getOperand(j); 3297 if (SOp == Trunc) 3298 Ops.push_back(ExtLoad); 3299 else 3300 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3301 N->getDebugLoc(), VT, SOp)); 3302 } 3303 3304 Ops.push_back(SetCC->getOperand(2)); 3305 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3306 SetCC->getValueType(0), 3307 &Ops[0], Ops.size())); 3308 } 3309 3310 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3311 } 3312 } 3313 3314 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3315 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3316 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3317 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3318 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3319 EVT MemVT = LN0->getMemoryVT(); 3320 if ((!LegalOperations && !LN0->isVolatile()) || 3321 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3322 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3323 LN0->getChain(), 3324 LN0->getBasePtr(), LN0->getSrcValue(), 3325 LN0->getSrcValueOffset(), MemVT, 3326 LN0->isVolatile(), LN0->getAlignment()); 3327 CombineTo(N, ExtLoad); 3328 CombineTo(N0.getNode(), 3329 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3330 ExtLoad), 3331 ExtLoad.getValue(1)); 3332 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3333 } 3334 } 3335 3336 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3337 if (N0.getOpcode() == ISD::SETCC) { 3338 SDValue SCC = 3339 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3340 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3341 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3342 if (SCC.getNode()) return SCC; 3343 } 3344 3345 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3346 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3347 isa<ConstantSDNode>(N0.getOperand(1)) && 3348 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3349 N0.hasOneUse()) { 3350 if (N0.getOpcode() == ISD::SHL) { 3351 // If the original shl may be shifting out bits, do not perform this 3352 // transformation. 3353 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3354 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3355 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3356 if (ShAmt > KnownZeroBits) 3357 return SDValue(); 3358 } 3359 DebugLoc dl = N->getDebugLoc(); 3360 return DAG.getNode(N0.getOpcode(), dl, VT, 3361 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3362 DAG.getNode(ISD::ZERO_EXTEND, dl, 3363 N0.getOperand(1).getValueType(), 3364 N0.getOperand(1))); 3365 } 3366 3367 return SDValue(); 3368} 3369 3370SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3371 SDValue N0 = N->getOperand(0); 3372 EVT VT = N->getValueType(0); 3373 3374 // fold (aext c1) -> c1 3375 if (isa<ConstantSDNode>(N0)) 3376 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3377 // fold (aext (aext x)) -> (aext x) 3378 // fold (aext (zext x)) -> (zext x) 3379 // fold (aext (sext x)) -> (sext x) 3380 if (N0.getOpcode() == ISD::ANY_EXTEND || 3381 N0.getOpcode() == ISD::ZERO_EXTEND || 3382 N0.getOpcode() == ISD::SIGN_EXTEND) 3383 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3384 3385 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3386 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3387 if (N0.getOpcode() == ISD::TRUNCATE) { 3388 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3389 if (NarrowLoad.getNode()) { 3390 if (NarrowLoad.getNode() != N0.getNode()) 3391 CombineTo(N0.getNode(), NarrowLoad); 3392 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3393 } 3394 } 3395 3396 // fold (aext (truncate x)) 3397 if (N0.getOpcode() == ISD::TRUNCATE) { 3398 SDValue TruncOp = N0.getOperand(0); 3399 if (TruncOp.getValueType() == VT) 3400 return TruncOp; // x iff x size == zext size. 3401 if (TruncOp.getValueType().bitsGT(VT)) 3402 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3403 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3404 } 3405 3406 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3407 // if the trunc is not free. 3408 if (N0.getOpcode() == ISD::AND && 3409 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3410 N0.getOperand(1).getOpcode() == ISD::Constant && 3411 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3412 N0.getValueType())) { 3413 SDValue X = N0.getOperand(0).getOperand(0); 3414 if (X.getValueType().bitsLT(VT)) { 3415 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3416 } else if (X.getValueType().bitsGT(VT)) { 3417 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3418 } 3419 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3420 Mask.zext(VT.getSizeInBits()); 3421 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3422 X, DAG.getConstant(Mask, VT)); 3423 } 3424 3425 // fold (aext (load x)) -> (aext (truncate (extload x))) 3426 if (ISD::isNON_EXTLoad(N0.getNode()) && 3427 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3428 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3429 bool DoXform = true; 3430 SmallVector<SDNode*, 4> SetCCs; 3431 if (!N0.hasOneUse()) 3432 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3433 if (DoXform) { 3434 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3435 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3436 LN0->getChain(), 3437 LN0->getBasePtr(), LN0->getSrcValue(), 3438 LN0->getSrcValueOffset(), 3439 N0.getValueType(), 3440 LN0->isVolatile(), LN0->getAlignment()); 3441 CombineTo(N, ExtLoad); 3442 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3443 N0.getValueType(), ExtLoad); 3444 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3445 3446 // Extend SetCC uses if necessary. 3447 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3448 SDNode *SetCC = SetCCs[i]; 3449 SmallVector<SDValue, 4> Ops; 3450 3451 for (unsigned j = 0; j != 2; ++j) { 3452 SDValue SOp = SetCC->getOperand(j); 3453 if (SOp == Trunc) 3454 Ops.push_back(ExtLoad); 3455 else 3456 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3457 N->getDebugLoc(), VT, SOp)); 3458 } 3459 3460 Ops.push_back(SetCC->getOperand(2)); 3461 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3462 SetCC->getValueType(0), 3463 &Ops[0], Ops.size())); 3464 } 3465 3466 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3467 } 3468 } 3469 3470 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3471 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3472 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3473 if (N0.getOpcode() == ISD::LOAD && 3474 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3475 N0.hasOneUse()) { 3476 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3477 EVT MemVT = LN0->getMemoryVT(); 3478 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3479 VT, LN0->getChain(), LN0->getBasePtr(), 3480 LN0->getSrcValue(), 3481 LN0->getSrcValueOffset(), MemVT, 3482 LN0->isVolatile(), LN0->getAlignment()); 3483 CombineTo(N, ExtLoad); 3484 CombineTo(N0.getNode(), 3485 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3486 N0.getValueType(), ExtLoad), 3487 ExtLoad.getValue(1)); 3488 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3489 } 3490 3491 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3492 if (N0.getOpcode() == ISD::SETCC) { 3493 SDValue SCC = 3494 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3495 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3496 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3497 if (SCC.getNode()) 3498 return SCC; 3499 } 3500 3501 return SDValue(); 3502} 3503 3504/// GetDemandedBits - See if the specified operand can be simplified with the 3505/// knowledge that only the bits specified by Mask are used. If so, return the 3506/// simpler operand, otherwise return a null SDValue. 3507SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3508 switch (V.getOpcode()) { 3509 default: break; 3510 case ISD::OR: 3511 case ISD::XOR: 3512 // If the LHS or RHS don't contribute bits to the or, drop them. 3513 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3514 return V.getOperand(1); 3515 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3516 return V.getOperand(0); 3517 break; 3518 case ISD::SRL: 3519 // Only look at single-use SRLs. 3520 if (!V.getNode()->hasOneUse()) 3521 break; 3522 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3523 // See if we can recursively simplify the LHS. 3524 unsigned Amt = RHSC->getZExtValue(); 3525 3526 // Watch out for shift count overflow though. 3527 if (Amt >= Mask.getBitWidth()) break; 3528 APInt NewMask = Mask << Amt; 3529 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3530 if (SimplifyLHS.getNode()) 3531 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3532 SimplifyLHS, V.getOperand(1)); 3533 } 3534 } 3535 return SDValue(); 3536} 3537 3538/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3539/// bits and then truncated to a narrower type and where N is a multiple 3540/// of number of bits of the narrower type, transform it to a narrower load 3541/// from address + N / num of bits of new type. If the result is to be 3542/// extended, also fold the extension to form a extending load. 3543SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3544 unsigned Opc = N->getOpcode(); 3545 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3546 SDValue N0 = N->getOperand(0); 3547 EVT VT = N->getValueType(0); 3548 EVT ExtVT = VT; 3549 3550 // This transformation isn't valid for vector loads. 3551 if (VT.isVector()) 3552 return SDValue(); 3553 3554 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 3555 // extended to VT. 3556 if (Opc == ISD::SIGN_EXTEND_INREG) { 3557 ExtType = ISD::SEXTLOAD; 3558 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3559 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 3560 return SDValue(); 3561 } 3562 3563 unsigned EVTBits = ExtVT.getSizeInBits(); 3564 unsigned ShAmt = 0; 3565 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 3566 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3567 ShAmt = N01->getZExtValue(); 3568 // Is the shift amount a multiple of size of VT? 3569 if ((ShAmt & (EVTBits-1)) == 0) { 3570 N0 = N0.getOperand(0); 3571 // Is the load width a multiple of size of VT? 3572 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 3573 return SDValue(); 3574 } 3575 } 3576 } 3577 3578 // Do not generate loads of non-round integer types since these can 3579 // be expensive (and would be wrong if the type is not byte sized). 3580 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 3581 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3582 // Do not change the width of a volatile load. 3583 !cast<LoadSDNode>(N0)->isVolatile()) { 3584 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3585 EVT PtrType = N0.getOperand(1).getValueType(); 3586 3587 // For big endian targets, we need to adjust the offset to the pointer to 3588 // load the correct bytes. 3589 if (TLI.isBigEndian()) { 3590 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3591 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 3592 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3593 } 3594 3595 uint64_t PtrOff = ShAmt / 8; 3596 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3597 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3598 PtrType, LN0->getBasePtr(), 3599 DAG.getConstant(PtrOff, PtrType)); 3600 AddToWorkList(NewPtr.getNode()); 3601 3602 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3603 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3604 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3605 LN0->isVolatile(), NewAlign) 3606 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3607 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3608 ExtVT, LN0->isVolatile(), NewAlign); 3609 3610 // Replace the old load's chain with the new load's chain. 3611 WorkListRemover DeadNodes(*this); 3612 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3613 &DeadNodes); 3614 3615 // Return the new loaded value. 3616 return Load; 3617 } 3618 3619 return SDValue(); 3620} 3621 3622SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3623 SDValue N0 = N->getOperand(0); 3624 SDValue N1 = N->getOperand(1); 3625 EVT VT = N->getValueType(0); 3626 EVT EVT = cast<VTSDNode>(N1)->getVT(); 3627 unsigned VTBits = VT.getScalarType().getSizeInBits(); 3628 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 3629 3630 // fold (sext_in_reg c1) -> c1 3631 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3632 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3633 3634 // If the input is already sign extended, just drop the extension. 3635 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 3636 return N0; 3637 3638 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3639 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3640 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3641 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3642 N0.getOperand(0), N1); 3643 } 3644 3645 // fold (sext_in_reg (sext x)) -> (sext x) 3646 // fold (sext_in_reg (aext x)) -> (sext x) 3647 // if x is small enough. 3648 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3649 SDValue N00 = N0.getOperand(0); 3650 if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits) 3651 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3652 } 3653 3654 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3655 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3656 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3657 3658 // fold operands of sext_in_reg based on knowledge that the top bits are not 3659 // demanded. 3660 if (SimplifyDemandedBits(SDValue(N, 0))) 3661 return SDValue(N, 0); 3662 3663 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3664 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3665 SDValue NarrowLoad = ReduceLoadWidth(N); 3666 if (NarrowLoad.getNode()) 3667 return NarrowLoad; 3668 3669 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3670 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3671 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3672 if (N0.getOpcode() == ISD::SRL) { 3673 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3674 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 3675 // We can turn this into an SRA iff the input to the SRL is already sign 3676 // extended enough. 3677 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3678 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3679 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3680 N0.getOperand(0), N0.getOperand(1)); 3681 } 3682 } 3683 3684 // fold (sext_inreg (extload x)) -> (sextload x) 3685 if (ISD::isEXTLoad(N0.getNode()) && 3686 ISD::isUNINDEXEDLoad(N0.getNode()) && 3687 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3688 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3689 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3690 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3691 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3692 LN0->getChain(), 3693 LN0->getBasePtr(), LN0->getSrcValue(), 3694 LN0->getSrcValueOffset(), EVT, 3695 LN0->isVolatile(), LN0->getAlignment()); 3696 CombineTo(N, ExtLoad); 3697 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3698 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3699 } 3700 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3701 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3702 N0.hasOneUse() && 3703 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3704 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3705 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3706 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3707 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3708 LN0->getChain(), 3709 LN0->getBasePtr(), LN0->getSrcValue(), 3710 LN0->getSrcValueOffset(), EVT, 3711 LN0->isVolatile(), LN0->getAlignment()); 3712 CombineTo(N, ExtLoad); 3713 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3714 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3715 } 3716 return SDValue(); 3717} 3718 3719SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3720 SDValue N0 = N->getOperand(0); 3721 EVT VT = N->getValueType(0); 3722 3723 // noop truncate 3724 if (N0.getValueType() == N->getValueType(0)) 3725 return N0; 3726 // fold (truncate c1) -> c1 3727 if (isa<ConstantSDNode>(N0)) 3728 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3729 // fold (truncate (truncate x)) -> (truncate x) 3730 if (N0.getOpcode() == ISD::TRUNCATE) 3731 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3732 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3733 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3734 N0.getOpcode() == ISD::ANY_EXTEND) { 3735 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3736 // if the source is smaller than the dest, we still need an extend 3737 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3738 N0.getOperand(0)); 3739 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3740 // if the source is larger than the dest, than we just need the truncate 3741 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3742 else 3743 // if the source and dest are the same type, we can drop both the extend 3744 // and the truncate. 3745 return N0.getOperand(0); 3746 } 3747 3748 // See if we can simplify the input to this truncate through knowledge that 3749 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3750 // -> trunc y 3751 SDValue Shorter = 3752 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3753 VT.getSizeInBits())); 3754 if (Shorter.getNode()) 3755 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3756 3757 // fold (truncate (load x)) -> (smaller load x) 3758 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3759 return ReduceLoadWidth(N); 3760} 3761 3762static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3763 SDValue Elt = N->getOperand(i); 3764 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3765 return Elt.getNode(); 3766 return Elt.getOperand(Elt.getResNo()).getNode(); 3767} 3768 3769/// CombineConsecutiveLoads - build_pair (load, load) -> load 3770/// if load locations are consecutive. 3771SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 3772 assert(N->getOpcode() == ISD::BUILD_PAIR); 3773 3774 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3775 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3776 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3777 return SDValue(); 3778 EVT LD1VT = LD1->getValueType(0); 3779 3780 if (ISD::isNON_EXTLoad(LD2) && 3781 LD2->hasOneUse() && 3782 // If both are volatile this would reduce the number of volatile loads. 3783 // If one is volatile it might be ok, but play conservative and bail out. 3784 !LD1->isVolatile() && 3785 !LD2->isVolatile() && 3786 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 3787 unsigned Align = LD1->getAlignment(); 3788 unsigned NewAlign = TLI.getTargetData()-> 3789 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3790 3791 if (NewAlign <= Align && 3792 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3793 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3794 LD1->getBasePtr(), LD1->getSrcValue(), 3795 LD1->getSrcValueOffset(), false, Align); 3796 } 3797 3798 return SDValue(); 3799} 3800 3801SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3802 SDValue N0 = N->getOperand(0); 3803 EVT VT = N->getValueType(0); 3804 3805 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3806 // Only do this before legalize, since afterward the target may be depending 3807 // on the bitconvert. 3808 // First check to see if this is all constant. 3809 if (!LegalTypes && 3810 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3811 VT.isVector()) { 3812 bool isSimple = true; 3813 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3814 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3815 N0.getOperand(i).getOpcode() != ISD::Constant && 3816 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3817 isSimple = false; 3818 break; 3819 } 3820 3821 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 3822 assert(!DestEltVT.isVector() && 3823 "Element type of vector ValueType must not be vector!"); 3824 if (isSimple) 3825 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3826 } 3827 3828 // If the input is a constant, let getNode fold it. 3829 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3830 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3831 if (Res.getNode() != N) { 3832 if (!LegalOperations || 3833 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 3834 return Res; 3835 3836 // Folding it resulted in an illegal node, and it's too late to 3837 // do that. Clean up the old node and forego the transformation. 3838 // Ideally this won't happen very often, because instcombine 3839 // and the earlier dagcombine runs (where illegal nodes are 3840 // permitted) should have folded most of them already. 3841 DAG.DeleteNode(Res.getNode()); 3842 } 3843 } 3844 3845 // (conv (conv x, t1), t2) -> (conv x, t2) 3846 if (N0.getOpcode() == ISD::BIT_CONVERT) 3847 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3848 N0.getOperand(0)); 3849 3850 // fold (conv (load x)) -> (load (conv*)x) 3851 // If the resultant load doesn't need a higher alignment than the original! 3852 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3853 // Do not change the width of a volatile load. 3854 !cast<LoadSDNode>(N0)->isVolatile() && 3855 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3856 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3857 unsigned Align = TLI.getTargetData()-> 3858 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3859 unsigned OrigAlign = LN0->getAlignment(); 3860 3861 if (Align <= OrigAlign) { 3862 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3863 LN0->getBasePtr(), 3864 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3865 LN0->isVolatile(), OrigAlign); 3866 AddToWorkList(N); 3867 CombineTo(N0.getNode(), 3868 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3869 N0.getValueType(), Load), 3870 Load.getValue(1)); 3871 return Load; 3872 } 3873 } 3874 3875 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3876 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3877 // This often reduces constant pool loads. 3878 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3879 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3880 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3881 N0.getOperand(0)); 3882 AddToWorkList(NewConv.getNode()); 3883 3884 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3885 if (N0.getOpcode() == ISD::FNEG) 3886 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3887 NewConv, DAG.getConstant(SignBit, VT)); 3888 assert(N0.getOpcode() == ISD::FABS); 3889 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3890 NewConv, DAG.getConstant(~SignBit, VT)); 3891 } 3892 3893 // fold (bitconvert (fcopysign cst, x)) -> 3894 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3895 // Note that we don't handle (copysign x, cst) because this can always be 3896 // folded to an fneg or fabs. 3897 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3898 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3899 VT.isInteger() && !VT.isVector()) { 3900 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3901 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 3902 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3903 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3904 IntXVT, N0.getOperand(1)); 3905 AddToWorkList(X.getNode()); 3906 3907 // If X has a different width than the result/lhs, sext it or truncate it. 3908 unsigned VTWidth = VT.getSizeInBits(); 3909 if (OrigXWidth < VTWidth) { 3910 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3911 AddToWorkList(X.getNode()); 3912 } else if (OrigXWidth > VTWidth) { 3913 // To get the sign bit in the right place, we have to shift it right 3914 // before truncating. 3915 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3916 X.getValueType(), X, 3917 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3918 AddToWorkList(X.getNode()); 3919 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3920 AddToWorkList(X.getNode()); 3921 } 3922 3923 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3924 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3925 X, DAG.getConstant(SignBit, VT)); 3926 AddToWorkList(X.getNode()); 3927 3928 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3929 VT, N0.getOperand(0)); 3930 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3931 Cst, DAG.getConstant(~SignBit, VT)); 3932 AddToWorkList(Cst.getNode()); 3933 3934 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3935 } 3936 } 3937 3938 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3939 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3940 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3941 if (CombineLD.getNode()) 3942 return CombineLD; 3943 } 3944 3945 return SDValue(); 3946} 3947 3948SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3949 EVT VT = N->getValueType(0); 3950 return CombineConsecutiveLoads(N, VT); 3951} 3952 3953/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3954/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3955/// destination element value type. 3956SDValue DAGCombiner:: 3957ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 3958 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3959 3960 // If this is already the right type, we're done. 3961 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3962 3963 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3964 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3965 3966 // If this is a conversion of N elements of one type to N elements of another 3967 // type, convert each element. This handles FP<->INT cases. 3968 if (SrcBitSize == DstBitSize) { 3969 SmallVector<SDValue, 8> Ops; 3970 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3971 SDValue Op = BV->getOperand(i); 3972 // If the vector element type is not legal, the BUILD_VECTOR operands 3973 // are promoted and implicitly truncated. Make that explicit here. 3974 if (Op.getValueType() != SrcEltVT) 3975 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3976 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3977 DstEltVT, Op)); 3978 AddToWorkList(Ops.back().getNode()); 3979 } 3980 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 3981 BV->getValueType(0).getVectorNumElements()); 3982 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3983 &Ops[0], Ops.size()); 3984 } 3985 3986 // Otherwise, we're growing or shrinking the elements. To avoid having to 3987 // handle annoying details of growing/shrinking FP values, we convert them to 3988 // int first. 3989 if (SrcEltVT.isFloatingPoint()) { 3990 // Convert the input float vector to a int vector where the elements are the 3991 // same sizes. 3992 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3993 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 3994 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3995 SrcEltVT = IntVT; 3996 } 3997 3998 // Now we know the input is an integer vector. If the output is a FP type, 3999 // convert to integer first, then to FP of the right size. 4000 if (DstEltVT.isFloatingPoint()) { 4001 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4002 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4003 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4004 4005 // Next, convert to FP elements of the same size. 4006 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4007 } 4008 4009 // Okay, we know the src/dst types are both integers of differing types. 4010 // Handling growing first. 4011 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4012 if (SrcBitSize < DstBitSize) { 4013 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4014 4015 SmallVector<SDValue, 8> Ops; 4016 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4017 i += NumInputsPerOutput) { 4018 bool isLE = TLI.isLittleEndian(); 4019 APInt NewBits = APInt(DstBitSize, 0); 4020 bool EltIsUndef = true; 4021 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4022 // Shift the previously computed bits over. 4023 NewBits <<= SrcBitSize; 4024 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4025 if (Op.getOpcode() == ISD::UNDEF) continue; 4026 EltIsUndef = false; 4027 4028 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4029 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 4030 } 4031 4032 if (EltIsUndef) 4033 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4034 else 4035 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4036 } 4037 4038 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4039 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4040 &Ops[0], Ops.size()); 4041 } 4042 4043 // Finally, this must be the case where we are shrinking elements: each input 4044 // turns into multiple outputs. 4045 bool isS2V = ISD::isScalarToVector(BV); 4046 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4047 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4048 NumOutputsPerInput*BV->getNumOperands()); 4049 SmallVector<SDValue, 8> Ops; 4050 4051 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4052 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4053 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4054 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4055 continue; 4056 } 4057 4058 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4059 getAPIntValue()).zextOrTrunc(SrcBitSize); 4060 4061 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4062 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4063 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4064 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4065 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4066 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4067 Ops[0]); 4068 OpVal = OpVal.lshr(DstBitSize); 4069 } 4070 4071 // For big endian targets, swap the order of the pieces of each element. 4072 if (TLI.isBigEndian()) 4073 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4074 } 4075 4076 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4077 &Ops[0], Ops.size()); 4078} 4079 4080SDValue DAGCombiner::visitFADD(SDNode *N) { 4081 SDValue N0 = N->getOperand(0); 4082 SDValue N1 = N->getOperand(1); 4083 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4084 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4085 EVT VT = N->getValueType(0); 4086 4087 // fold vector ops 4088 if (VT.isVector()) { 4089 SDValue FoldedVOp = SimplifyVBinOp(N); 4090 if (FoldedVOp.getNode()) return FoldedVOp; 4091 } 4092 4093 // fold (fadd c1, c2) -> (fadd c1, c2) 4094 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4095 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4096 // canonicalize constant to RHS 4097 if (N0CFP && !N1CFP) 4098 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4099 // fold (fadd A, 0) -> A 4100 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4101 return N0; 4102 // fold (fadd A, (fneg B)) -> (fsub A, B) 4103 if (isNegatibleForFree(N1, LegalOperations) == 2) 4104 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4105 GetNegatedExpression(N1, DAG, LegalOperations)); 4106 // fold (fadd (fneg A), B) -> (fsub B, A) 4107 if (isNegatibleForFree(N0, LegalOperations) == 2) 4108 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4109 GetNegatedExpression(N0, DAG, LegalOperations)); 4110 4111 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4112 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4113 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4114 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4115 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4116 N0.getOperand(1), N1)); 4117 4118 return SDValue(); 4119} 4120 4121SDValue DAGCombiner::visitFSUB(SDNode *N) { 4122 SDValue N0 = N->getOperand(0); 4123 SDValue N1 = N->getOperand(1); 4124 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4125 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4126 EVT VT = N->getValueType(0); 4127 4128 // fold vector ops 4129 if (VT.isVector()) { 4130 SDValue FoldedVOp = SimplifyVBinOp(N); 4131 if (FoldedVOp.getNode()) return FoldedVOp; 4132 } 4133 4134 // fold (fsub c1, c2) -> c1-c2 4135 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4136 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4137 // fold (fsub A, 0) -> A 4138 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4139 return N0; 4140 // fold (fsub 0, B) -> -B 4141 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4142 if (isNegatibleForFree(N1, LegalOperations)) 4143 return GetNegatedExpression(N1, DAG, LegalOperations); 4144 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4145 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4146 } 4147 // fold (fsub A, (fneg B)) -> (fadd A, B) 4148 if (isNegatibleForFree(N1, LegalOperations)) 4149 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4150 GetNegatedExpression(N1, DAG, LegalOperations)); 4151 4152 return SDValue(); 4153} 4154 4155SDValue DAGCombiner::visitFMUL(SDNode *N) { 4156 SDValue N0 = N->getOperand(0); 4157 SDValue N1 = N->getOperand(1); 4158 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4159 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4160 EVT VT = N->getValueType(0); 4161 4162 // fold vector ops 4163 if (VT.isVector()) { 4164 SDValue FoldedVOp = SimplifyVBinOp(N); 4165 if (FoldedVOp.getNode()) return FoldedVOp; 4166 } 4167 4168 // fold (fmul c1, c2) -> c1*c2 4169 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4170 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4171 // canonicalize constant to RHS 4172 if (N0CFP && !N1CFP) 4173 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4174 // fold (fmul A, 0) -> 0 4175 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4176 return N1; 4177 // fold (fmul A, 0) -> 0, vector edition. 4178 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4179 return N1; 4180 // fold (fmul X, 2.0) -> (fadd X, X) 4181 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4182 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4183 // fold (fmul X, -1.0) -> (fneg X) 4184 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4185 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4186 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4187 4188 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4189 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4190 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4191 // Both can be negated for free, check to see if at least one is cheaper 4192 // negated. 4193 if (LHSNeg == 2 || RHSNeg == 2) 4194 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4195 GetNegatedExpression(N0, DAG, LegalOperations), 4196 GetNegatedExpression(N1, DAG, LegalOperations)); 4197 } 4198 } 4199 4200 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4201 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4202 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4203 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4204 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4205 N0.getOperand(1), N1)); 4206 4207 return SDValue(); 4208} 4209 4210SDValue DAGCombiner::visitFDIV(SDNode *N) { 4211 SDValue N0 = N->getOperand(0); 4212 SDValue N1 = N->getOperand(1); 4213 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4214 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4215 EVT VT = N->getValueType(0); 4216 4217 // fold vector ops 4218 if (VT.isVector()) { 4219 SDValue FoldedVOp = SimplifyVBinOp(N); 4220 if (FoldedVOp.getNode()) return FoldedVOp; 4221 } 4222 4223 // fold (fdiv c1, c2) -> c1/c2 4224 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4225 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4226 4227 4228 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4229 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4230 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4231 // Both can be negated for free, check to see if at least one is cheaper 4232 // negated. 4233 if (LHSNeg == 2 || RHSNeg == 2) 4234 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4235 GetNegatedExpression(N0, DAG, LegalOperations), 4236 GetNegatedExpression(N1, DAG, LegalOperations)); 4237 } 4238 } 4239 4240 return SDValue(); 4241} 4242 4243SDValue DAGCombiner::visitFREM(SDNode *N) { 4244 SDValue N0 = N->getOperand(0); 4245 SDValue N1 = N->getOperand(1); 4246 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4247 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4248 EVT VT = N->getValueType(0); 4249 4250 // fold (frem c1, c2) -> fmod(c1,c2) 4251 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4252 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4253 4254 return SDValue(); 4255} 4256 4257SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4258 SDValue N0 = N->getOperand(0); 4259 SDValue N1 = N->getOperand(1); 4260 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4261 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4262 EVT VT = N->getValueType(0); 4263 4264 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4265 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4266 4267 if (N1CFP) { 4268 const APFloat& V = N1CFP->getValueAPF(); 4269 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4270 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4271 if (!V.isNegative()) { 4272 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4273 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4274 } else { 4275 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4276 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4277 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4278 } 4279 } 4280 4281 // copysign(fabs(x), y) -> copysign(x, y) 4282 // copysign(fneg(x), y) -> copysign(x, y) 4283 // copysign(copysign(x,z), y) -> copysign(x, y) 4284 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4285 N0.getOpcode() == ISD::FCOPYSIGN) 4286 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4287 N0.getOperand(0), N1); 4288 4289 // copysign(x, abs(y)) -> abs(x) 4290 if (N1.getOpcode() == ISD::FABS) 4291 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4292 4293 // copysign(x, copysign(y,z)) -> copysign(x, z) 4294 if (N1.getOpcode() == ISD::FCOPYSIGN) 4295 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4296 N0, N1.getOperand(1)); 4297 4298 // copysign(x, fp_extend(y)) -> copysign(x, y) 4299 // copysign(x, fp_round(y)) -> copysign(x, y) 4300 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4301 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4302 N0, N1.getOperand(0)); 4303 4304 return SDValue(); 4305} 4306 4307SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4308 SDValue N0 = N->getOperand(0); 4309 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4310 EVT VT = N->getValueType(0); 4311 EVT OpVT = N0.getValueType(); 4312 4313 // fold (sint_to_fp c1) -> c1fp 4314 if (N0C && OpVT != MVT::ppcf128) 4315 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4316 4317 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4318 // but UINT_TO_FP is legal on this target, try to convert. 4319 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4320 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4321 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4322 if (DAG.SignBitIsZero(N0)) 4323 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4324 } 4325 4326 return SDValue(); 4327} 4328 4329SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4330 SDValue N0 = N->getOperand(0); 4331 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4332 EVT VT = N->getValueType(0); 4333 EVT OpVT = N0.getValueType(); 4334 4335 // fold (uint_to_fp c1) -> c1fp 4336 if (N0C && OpVT != MVT::ppcf128) 4337 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4338 4339 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4340 // but SINT_TO_FP is legal on this target, try to convert. 4341 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4342 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4343 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4344 if (DAG.SignBitIsZero(N0)) 4345 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4346 } 4347 4348 return SDValue(); 4349} 4350 4351SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4352 SDValue N0 = N->getOperand(0); 4353 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4354 EVT VT = N->getValueType(0); 4355 4356 // fold (fp_to_sint c1fp) -> c1 4357 if (N0CFP) 4358 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4359 4360 return SDValue(); 4361} 4362 4363SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4364 SDValue N0 = N->getOperand(0); 4365 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4366 EVT VT = N->getValueType(0); 4367 4368 // fold (fp_to_uint c1fp) -> c1 4369 if (N0CFP && VT != MVT::ppcf128) 4370 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4371 4372 return SDValue(); 4373} 4374 4375SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4376 SDValue N0 = N->getOperand(0); 4377 SDValue N1 = N->getOperand(1); 4378 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4379 EVT VT = N->getValueType(0); 4380 4381 // fold (fp_round c1fp) -> c1fp 4382 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4383 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4384 4385 // fold (fp_round (fp_extend x)) -> x 4386 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4387 return N0.getOperand(0); 4388 4389 // fold (fp_round (fp_round x)) -> (fp_round x) 4390 if (N0.getOpcode() == ISD::FP_ROUND) { 4391 // This is a value preserving truncation if both round's are. 4392 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4393 N0.getNode()->getConstantOperandVal(1) == 1; 4394 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4395 DAG.getIntPtrConstant(IsTrunc)); 4396 } 4397 4398 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4399 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4400 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4401 N0.getOperand(0), N1); 4402 AddToWorkList(Tmp.getNode()); 4403 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4404 Tmp, N0.getOperand(1)); 4405 } 4406 4407 return SDValue(); 4408} 4409 4410SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4411 SDValue N0 = N->getOperand(0); 4412 EVT VT = N->getValueType(0); 4413 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4414 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4415 4416 // fold (fp_round_inreg c1fp) -> c1fp 4417 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4418 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4419 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4420 } 4421 4422 return SDValue(); 4423} 4424 4425SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4426 SDValue N0 = N->getOperand(0); 4427 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4428 EVT VT = N->getValueType(0); 4429 4430 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4431 if (N->hasOneUse() && 4432 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4433 return SDValue(); 4434 4435 // fold (fp_extend c1fp) -> c1fp 4436 if (N0CFP && VT != MVT::ppcf128) 4437 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4438 4439 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4440 // value of X. 4441 if (N0.getOpcode() == ISD::FP_ROUND 4442 && N0.getNode()->getConstantOperandVal(1) == 1) { 4443 SDValue In = N0.getOperand(0); 4444 if (In.getValueType() == VT) return In; 4445 if (VT.bitsLT(In.getValueType())) 4446 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4447 In, N0.getOperand(1)); 4448 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4449 } 4450 4451 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4452 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4453 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4454 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4455 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4456 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4457 LN0->getChain(), 4458 LN0->getBasePtr(), LN0->getSrcValue(), 4459 LN0->getSrcValueOffset(), 4460 N0.getValueType(), 4461 LN0->isVolatile(), LN0->getAlignment()); 4462 CombineTo(N, ExtLoad); 4463 CombineTo(N0.getNode(), 4464 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4465 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4466 ExtLoad.getValue(1)); 4467 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4468 } 4469 4470 return SDValue(); 4471} 4472 4473SDValue DAGCombiner::visitFNEG(SDNode *N) { 4474 SDValue N0 = N->getOperand(0); 4475 EVT VT = N->getValueType(0); 4476 4477 if (isNegatibleForFree(N0, LegalOperations)) 4478 return GetNegatedExpression(N0, DAG, LegalOperations); 4479 4480 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4481 // constant pool values. 4482 if (N0.getOpcode() == ISD::BIT_CONVERT && 4483 !VT.isVector() && 4484 N0.getNode()->hasOneUse() && 4485 N0.getOperand(0).getValueType().isInteger()) { 4486 SDValue Int = N0.getOperand(0); 4487 EVT IntVT = Int.getValueType(); 4488 if (IntVT.isInteger() && !IntVT.isVector()) { 4489 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4490 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4491 AddToWorkList(Int.getNode()); 4492 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4493 VT, Int); 4494 } 4495 } 4496 4497 return SDValue(); 4498} 4499 4500SDValue DAGCombiner::visitFABS(SDNode *N) { 4501 SDValue N0 = N->getOperand(0); 4502 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4503 EVT VT = N->getValueType(0); 4504 4505 // fold (fabs c1) -> fabs(c1) 4506 if (N0CFP && VT != MVT::ppcf128) 4507 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4508 // fold (fabs (fabs x)) -> (fabs x) 4509 if (N0.getOpcode() == ISD::FABS) 4510 return N->getOperand(0); 4511 // fold (fabs (fneg x)) -> (fabs x) 4512 // fold (fabs (fcopysign x, y)) -> (fabs x) 4513 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4514 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4515 4516 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4517 // constant pool values. 4518 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4519 N0.getOperand(0).getValueType().isInteger() && 4520 !N0.getOperand(0).getValueType().isVector()) { 4521 SDValue Int = N0.getOperand(0); 4522 EVT IntVT = Int.getValueType(); 4523 if (IntVT.isInteger() && !IntVT.isVector()) { 4524 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4525 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4526 AddToWorkList(Int.getNode()); 4527 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4528 N->getValueType(0), Int); 4529 } 4530 } 4531 4532 return SDValue(); 4533} 4534 4535SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4536 SDValue Chain = N->getOperand(0); 4537 SDValue N1 = N->getOperand(1); 4538 SDValue N2 = N->getOperand(2); 4539 4540 // If N is a constant we could fold this into a fallthrough or unconditional 4541 // branch. However that doesn't happen very often in normal code, because 4542 // Instcombine/SimplifyCFG should have handled the available opportunities. 4543 // If we did this folding here, it would be necessary to update the 4544 // MachineBasicBlock CFG, which is awkward. 4545 4546 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4547 // on the target. 4548 if (N1.getOpcode() == ISD::SETCC && 4549 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4550 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4551 Chain, N1.getOperand(2), 4552 N1.getOperand(0), N1.getOperand(1), N2); 4553 } 4554 4555 SDNode *Trunc = 0; 4556 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 4557 // Look pass truncate. 4558 Trunc = N1.getNode(); 4559 N1 = N1.getOperand(0); 4560 } 4561 4562 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4563 // Match this pattern so that we can generate simpler code: 4564 // 4565 // %a = ... 4566 // %b = and i32 %a, 2 4567 // %c = srl i32 %b, 1 4568 // brcond i32 %c ... 4569 // 4570 // into 4571 // 4572 // %a = ... 4573 // %b = and i32 %a, 2 4574 // %c = setcc eq %b, 0 4575 // brcond %c ... 4576 // 4577 // This applies only when the AND constant value has one bit set and the 4578 // SRL constant is equal to the log2 of the AND constant. The back-end is 4579 // smart enough to convert the result into a TEST/JMP sequence. 4580 SDValue Op0 = N1.getOperand(0); 4581 SDValue Op1 = N1.getOperand(1); 4582 4583 if (Op0.getOpcode() == ISD::AND && 4584 Op1.getOpcode() == ISD::Constant) { 4585 SDValue AndOp1 = Op0.getOperand(1); 4586 4587 if (AndOp1.getOpcode() == ISD::Constant) { 4588 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4589 4590 if (AndConst.isPowerOf2() && 4591 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4592 SDValue SetCC = 4593 DAG.getSetCC(N->getDebugLoc(), 4594 TLI.getSetCCResultType(Op0.getValueType()), 4595 Op0, DAG.getConstant(0, Op0.getValueType()), 4596 ISD::SETNE); 4597 4598 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4599 MVT::Other, Chain, SetCC, N2); 4600 // Don't add the new BRCond into the worklist or else SimplifySelectCC 4601 // will convert it back to (X & C1) >> C2. 4602 CombineTo(N, NewBRCond, false); 4603 // Truncate is dead. 4604 if (Trunc) { 4605 removeFromWorkList(Trunc); 4606 DAG.DeleteNode(Trunc); 4607 } 4608 // Replace the uses of SRL with SETCC 4609 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4610 removeFromWorkList(N1.getNode()); 4611 DAG.DeleteNode(N1.getNode()); 4612 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4613 } 4614 } 4615 } 4616 } 4617 4618 return SDValue(); 4619} 4620 4621// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4622// 4623SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4624 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4625 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4626 4627 // If N is a constant we could fold this into a fallthrough or unconditional 4628 // branch. However that doesn't happen very often in normal code, because 4629 // Instcombine/SimplifyCFG should have handled the available opportunities. 4630 // If we did this folding here, it would be necessary to update the 4631 // MachineBasicBlock CFG, which is awkward. 4632 4633 // Use SimplifySetCC to simplify SETCC's. 4634 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4635 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4636 false); 4637 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4638 4639 // fold to a simpler setcc 4640 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4641 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4642 N->getOperand(0), Simp.getOperand(2), 4643 Simp.getOperand(0), Simp.getOperand(1), 4644 N->getOperand(4)); 4645 4646 return SDValue(); 4647} 4648 4649/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4650/// pre-indexed load / store when the base pointer is an add or subtract 4651/// and it has other uses besides the load / store. After the 4652/// transformation, the new indexed load / store has effectively folded 4653/// the add / subtract in and all of its other uses are redirected to the 4654/// new load / store. 4655bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4656 if (!LegalOperations) 4657 return false; 4658 4659 bool isLoad = true; 4660 SDValue Ptr; 4661 EVT VT; 4662 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4663 if (LD->isIndexed()) 4664 return false; 4665 VT = LD->getMemoryVT(); 4666 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4667 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4668 return false; 4669 Ptr = LD->getBasePtr(); 4670 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4671 if (ST->isIndexed()) 4672 return false; 4673 VT = ST->getMemoryVT(); 4674 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4675 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4676 return false; 4677 Ptr = ST->getBasePtr(); 4678 isLoad = false; 4679 } else { 4680 return false; 4681 } 4682 4683 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4684 // out. There is no reason to make this a preinc/predec. 4685 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4686 Ptr.getNode()->hasOneUse()) 4687 return false; 4688 4689 // Ask the target to do addressing mode selection. 4690 SDValue BasePtr; 4691 SDValue Offset; 4692 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4693 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4694 return false; 4695 // Don't create a indexed load / store with zero offset. 4696 if (isa<ConstantSDNode>(Offset) && 4697 cast<ConstantSDNode>(Offset)->isNullValue()) 4698 return false; 4699 4700 // Try turning it into a pre-indexed load / store except when: 4701 // 1) The new base ptr is a frame index. 4702 // 2) If N is a store and the new base ptr is either the same as or is a 4703 // predecessor of the value being stored. 4704 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4705 // that would create a cycle. 4706 // 4) All uses are load / store ops that use it as old base ptr. 4707 4708 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4709 // (plus the implicit offset) to a register to preinc anyway. 4710 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4711 return false; 4712 4713 // Check #2. 4714 if (!isLoad) { 4715 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4716 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4717 return false; 4718 } 4719 4720 // Now check for #3 and #4. 4721 bool RealUse = false; 4722 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4723 E = Ptr.getNode()->use_end(); I != E; ++I) { 4724 SDNode *Use = *I; 4725 if (Use == N) 4726 continue; 4727 if (Use->isPredecessorOf(N)) 4728 return false; 4729 4730 if (!((Use->getOpcode() == ISD::LOAD && 4731 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4732 (Use->getOpcode() == ISD::STORE && 4733 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4734 RealUse = true; 4735 } 4736 4737 if (!RealUse) 4738 return false; 4739 4740 SDValue Result; 4741 if (isLoad) 4742 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4743 BasePtr, Offset, AM); 4744 else 4745 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4746 BasePtr, Offset, AM); 4747 ++PreIndexedNodes; 4748 ++NodesCombined; 4749 DEBUG(dbgs() << "\nReplacing.4 "; 4750 N->dump(&DAG); 4751 dbgs() << "\nWith: "; 4752 Result.getNode()->dump(&DAG); 4753 dbgs() << '\n'); 4754 WorkListRemover DeadNodes(*this); 4755 if (isLoad) { 4756 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4757 &DeadNodes); 4758 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4759 &DeadNodes); 4760 } else { 4761 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4762 &DeadNodes); 4763 } 4764 4765 // Finally, since the node is now dead, remove it from the graph. 4766 DAG.DeleteNode(N); 4767 4768 // Replace the uses of Ptr with uses of the updated base value. 4769 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4770 &DeadNodes); 4771 removeFromWorkList(Ptr.getNode()); 4772 DAG.DeleteNode(Ptr.getNode()); 4773 4774 return true; 4775} 4776 4777/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4778/// add / sub of the base pointer node into a post-indexed load / store. 4779/// The transformation folded the add / subtract into the new indexed 4780/// load / store effectively and all of its uses are redirected to the 4781/// new load / store. 4782bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4783 if (!LegalOperations) 4784 return false; 4785 4786 bool isLoad = true; 4787 SDValue Ptr; 4788 EVT VT; 4789 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4790 if (LD->isIndexed()) 4791 return false; 4792 VT = LD->getMemoryVT(); 4793 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4794 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4795 return false; 4796 Ptr = LD->getBasePtr(); 4797 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4798 if (ST->isIndexed()) 4799 return false; 4800 VT = ST->getMemoryVT(); 4801 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4802 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4803 return false; 4804 Ptr = ST->getBasePtr(); 4805 isLoad = false; 4806 } else { 4807 return false; 4808 } 4809 4810 if (Ptr.getNode()->hasOneUse()) 4811 return false; 4812 4813 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4814 E = Ptr.getNode()->use_end(); I != E; ++I) { 4815 SDNode *Op = *I; 4816 if (Op == N || 4817 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4818 continue; 4819 4820 SDValue BasePtr; 4821 SDValue Offset; 4822 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4823 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4824 if (Ptr == Offset && Op->getOpcode() == ISD::ADD) 4825 std::swap(BasePtr, Offset); 4826 if (Ptr != BasePtr) 4827 continue; 4828 // Don't create a indexed load / store with zero offset. 4829 if (isa<ConstantSDNode>(Offset) && 4830 cast<ConstantSDNode>(Offset)->isNullValue()) 4831 continue; 4832 4833 // Try turning it into a post-indexed load / store except when 4834 // 1) All uses are load / store ops that use it as base ptr. 4835 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4836 // nor a successor of N. Otherwise, if Op is folded that would 4837 // create a cycle. 4838 4839 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4840 continue; 4841 4842 // Check for #1. 4843 bool TryNext = false; 4844 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4845 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4846 SDNode *Use = *II; 4847 if (Use == Ptr.getNode()) 4848 continue; 4849 4850 // If all the uses are load / store addresses, then don't do the 4851 // transformation. 4852 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4853 bool RealUse = false; 4854 for (SDNode::use_iterator III = Use->use_begin(), 4855 EEE = Use->use_end(); III != EEE; ++III) { 4856 SDNode *UseUse = *III; 4857 if (!((UseUse->getOpcode() == ISD::LOAD && 4858 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4859 (UseUse->getOpcode() == ISD::STORE && 4860 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4861 RealUse = true; 4862 } 4863 4864 if (!RealUse) { 4865 TryNext = true; 4866 break; 4867 } 4868 } 4869 } 4870 4871 if (TryNext) 4872 continue; 4873 4874 // Check for #2 4875 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4876 SDValue Result = isLoad 4877 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4878 BasePtr, Offset, AM) 4879 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4880 BasePtr, Offset, AM); 4881 ++PostIndexedNodes; 4882 ++NodesCombined; 4883 DEBUG(dbgs() << "\nReplacing.5 "; 4884 N->dump(&DAG); 4885 dbgs() << "\nWith: "; 4886 Result.getNode()->dump(&DAG); 4887 dbgs() << '\n'); 4888 WorkListRemover DeadNodes(*this); 4889 if (isLoad) { 4890 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4891 &DeadNodes); 4892 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4893 &DeadNodes); 4894 } else { 4895 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4896 &DeadNodes); 4897 } 4898 4899 // Finally, since the node is now dead, remove it from the graph. 4900 DAG.DeleteNode(N); 4901 4902 // Replace the uses of Use with uses of the updated base value. 4903 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4904 Result.getValue(isLoad ? 1 : 0), 4905 &DeadNodes); 4906 removeFromWorkList(Op); 4907 DAG.DeleteNode(Op); 4908 return true; 4909 } 4910 } 4911 } 4912 4913 return false; 4914} 4915 4916SDValue DAGCombiner::visitLOAD(SDNode *N) { 4917 LoadSDNode *LD = cast<LoadSDNode>(N); 4918 SDValue Chain = LD->getChain(); 4919 SDValue Ptr = LD->getBasePtr(); 4920 4921 // Try to infer better alignment information than the load already has. 4922 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4923 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 4924 if (Align > LD->getAlignment()) 4925 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4926 LD->getValueType(0), 4927 Chain, Ptr, LD->getSrcValue(), 4928 LD->getSrcValueOffset(), LD->getMemoryVT(), 4929 LD->isVolatile(), Align); 4930 } 4931 } 4932 4933 // If load is not volatile and there are no uses of the loaded value (and 4934 // the updated indexed value in case of indexed loads), change uses of the 4935 // chain value into uses of the chain input (i.e. delete the dead load). 4936 if (!LD->isVolatile()) { 4937 if (N->getValueType(1) == MVT::Other) { 4938 // Unindexed loads. 4939 if (N->hasNUsesOfValue(0, 0)) { 4940 // It's not safe to use the two value CombineTo variant here. e.g. 4941 // v1, chain2 = load chain1, loc 4942 // v2, chain3 = load chain2, loc 4943 // v3 = add v2, c 4944 // Now we replace use of chain2 with chain1. This makes the second load 4945 // isomorphic to the one we are deleting, and thus makes this load live. 4946 DEBUG(dbgs() << "\nReplacing.6 "; 4947 N->dump(&DAG); 4948 dbgs() << "\nWith chain: "; 4949 Chain.getNode()->dump(&DAG); 4950 dbgs() << "\n"); 4951 WorkListRemover DeadNodes(*this); 4952 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4953 4954 if (N->use_empty()) { 4955 removeFromWorkList(N); 4956 DAG.DeleteNode(N); 4957 } 4958 4959 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4960 } 4961 } else { 4962 // Indexed loads. 4963 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4964 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4965 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4966 DEBUG(dbgs() << "\nReplacing.6 "; 4967 N->dump(&DAG); 4968 dbgs() << "\nWith: "; 4969 Undef.getNode()->dump(&DAG); 4970 dbgs() << " and 2 other values\n"); 4971 WorkListRemover DeadNodes(*this); 4972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4973 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4974 DAG.getUNDEF(N->getValueType(1)), 4975 &DeadNodes); 4976 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4977 removeFromWorkList(N); 4978 DAG.DeleteNode(N); 4979 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4980 } 4981 } 4982 } 4983 4984 // If this load is directly stored, replace the load value with the stored 4985 // value. 4986 // TODO: Handle store large -> read small portion. 4987 // TODO: Handle TRUNCSTORE/LOADEXT 4988 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4989 !LD->isVolatile()) { 4990 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4991 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4992 if (PrevST->getBasePtr() == Ptr && 4993 PrevST->getValue().getValueType() == N->getValueType(0)) 4994 return CombineTo(N, Chain.getOperand(1), Chain); 4995 } 4996 } 4997 4998 if (CombinerAA) { 4999 // Walk up chain skipping non-aliasing memory nodes. 5000 SDValue BetterChain = FindBetterChain(N, Chain); 5001 5002 // If there is a better chain. 5003 if (Chain != BetterChain) { 5004 SDValue ReplLoad; 5005 5006 // Replace the chain to void dependency. 5007 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5008 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5009 BetterChain, Ptr, 5010 LD->getSrcValue(), LD->getSrcValueOffset(), 5011 LD->isVolatile(), LD->getAlignment()); 5012 } else { 5013 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5014 LD->getValueType(0), 5015 BetterChain, Ptr, LD->getSrcValue(), 5016 LD->getSrcValueOffset(), 5017 LD->getMemoryVT(), 5018 LD->isVolatile(), 5019 LD->getAlignment()); 5020 } 5021 5022 // Create token factor to keep old chain connected. 5023 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5024 MVT::Other, Chain, ReplLoad.getValue(1)); 5025 5026 // Make sure the new and old chains are cleaned up. 5027 AddToWorkList(Token.getNode()); 5028 5029 // Replace uses with load result and token factor. Don't add users 5030 // to work list. 5031 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5032 } 5033 } 5034 5035 // Try transforming N to an indexed load. 5036 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5037 return SDValue(N, 0); 5038 5039 return SDValue(); 5040} 5041 5042 5043/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5044/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5045/// of the loaded bits, try narrowing the load and store if it would end up 5046/// being a win for performance or code size. 5047SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5048 StoreSDNode *ST = cast<StoreSDNode>(N); 5049 if (ST->isVolatile()) 5050 return SDValue(); 5051 5052 SDValue Chain = ST->getChain(); 5053 SDValue Value = ST->getValue(); 5054 SDValue Ptr = ST->getBasePtr(); 5055 EVT VT = Value.getValueType(); 5056 5057 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5058 return SDValue(); 5059 5060 unsigned Opc = Value.getOpcode(); 5061 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5062 Value.getOperand(1).getOpcode() != ISD::Constant) 5063 return SDValue(); 5064 5065 SDValue N0 = Value.getOperand(0); 5066 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5067 LoadSDNode *LD = cast<LoadSDNode>(N0); 5068 if (LD->getBasePtr() != Ptr) 5069 return SDValue(); 5070 5071 // Find the type to narrow it the load / op / store to. 5072 SDValue N1 = Value.getOperand(1); 5073 unsigned BitWidth = N1.getValueSizeInBits(); 5074 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5075 if (Opc == ISD::AND) 5076 Imm ^= APInt::getAllOnesValue(BitWidth); 5077 if (Imm == 0 || Imm.isAllOnesValue()) 5078 return SDValue(); 5079 unsigned ShAmt = Imm.countTrailingZeros(); 5080 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5081 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5082 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5083 while (NewBW < BitWidth && 5084 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5085 TLI.isNarrowingProfitable(VT, NewVT))) { 5086 NewBW = NextPowerOf2(NewBW); 5087 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5088 } 5089 if (NewBW >= BitWidth) 5090 return SDValue(); 5091 5092 // If the lsb changed does not start at the type bitwidth boundary, 5093 // start at the previous one. 5094 if (ShAmt % NewBW) 5095 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5096 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5097 if ((Imm & Mask) == Imm) { 5098 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5099 if (Opc == ISD::AND) 5100 NewImm ^= APInt::getAllOnesValue(NewBW); 5101 uint64_t PtrOff = ShAmt / 8; 5102 // For big endian targets, we need to adjust the offset to the pointer to 5103 // load the correct bytes. 5104 if (TLI.isBigEndian()) 5105 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5106 5107 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5108 if (NewAlign < 5109 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext()))) 5110 return SDValue(); 5111 5112 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5113 Ptr.getValueType(), Ptr, 5114 DAG.getConstant(PtrOff, Ptr.getValueType())); 5115 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5116 LD->getChain(), NewPtr, 5117 LD->getSrcValue(), LD->getSrcValueOffset(), 5118 LD->isVolatile(), NewAlign); 5119 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5120 DAG.getConstant(NewImm, NewVT)); 5121 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5122 NewVal, NewPtr, 5123 ST->getSrcValue(), ST->getSrcValueOffset(), 5124 false, NewAlign); 5125 5126 AddToWorkList(NewPtr.getNode()); 5127 AddToWorkList(NewLD.getNode()); 5128 AddToWorkList(NewVal.getNode()); 5129 WorkListRemover DeadNodes(*this); 5130 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5131 &DeadNodes); 5132 ++OpsNarrowed; 5133 return NewST; 5134 } 5135 } 5136 5137 return SDValue(); 5138} 5139 5140SDValue DAGCombiner::visitSTORE(SDNode *N) { 5141 StoreSDNode *ST = cast<StoreSDNode>(N); 5142 SDValue Chain = ST->getChain(); 5143 SDValue Value = ST->getValue(); 5144 SDValue Ptr = ST->getBasePtr(); 5145 5146 // Try to infer better alignment information than the store already has. 5147 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5148 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5149 if (Align > ST->getAlignment()) 5150 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5151 Ptr, ST->getSrcValue(), 5152 ST->getSrcValueOffset(), ST->getMemoryVT(), 5153 ST->isVolatile(), Align); 5154 } 5155 } 5156 5157 // If this is a store of a bit convert, store the input value if the 5158 // resultant store does not need a higher alignment than the original. 5159 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5160 ST->isUnindexed()) { 5161 unsigned OrigAlign = ST->getAlignment(); 5162 EVT SVT = Value.getOperand(0).getValueType(); 5163 unsigned Align = TLI.getTargetData()-> 5164 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5165 if (Align <= OrigAlign && 5166 ((!LegalOperations && !ST->isVolatile()) || 5167 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5168 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5169 Ptr, ST->getSrcValue(), 5170 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5171 } 5172 5173 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5174 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5175 // NOTE: If the original store is volatile, this transform must not increase 5176 // the number of stores. For example, on x86-32 an f64 can be stored in one 5177 // processor operation but an i64 (which is not legal) requires two. So the 5178 // transform should not be done in this case. 5179 if (Value.getOpcode() != ISD::TargetConstantFP) { 5180 SDValue Tmp; 5181 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5182 default: llvm_unreachable("Unknown FP type"); 5183 case MVT::f80: // We don't do this for these yet. 5184 case MVT::f128: 5185 case MVT::ppcf128: 5186 break; 5187 case MVT::f32: 5188 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5189 !ST->isVolatile()) || 5190 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5191 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5192 bitcastToAPInt().getZExtValue(), MVT::i32); 5193 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5194 Ptr, ST->getSrcValue(), 5195 ST->getSrcValueOffset(), ST->isVolatile(), 5196 ST->getAlignment()); 5197 } 5198 break; 5199 case MVT::f64: 5200 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5201 !ST->isVolatile()) || 5202 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5203 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5204 getZExtValue(), MVT::i64); 5205 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5206 Ptr, ST->getSrcValue(), 5207 ST->getSrcValueOffset(), ST->isVolatile(), 5208 ST->getAlignment()); 5209 } else if (!ST->isVolatile() && 5210 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5211 // Many FP stores are not made apparent until after legalize, e.g. for 5212 // argument passing. Since this is so common, custom legalize the 5213 // 64-bit integer store into two 32-bit stores. 5214 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5215 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5216 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5217 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5218 5219 int SVOffset = ST->getSrcValueOffset(); 5220 unsigned Alignment = ST->getAlignment(); 5221 bool isVolatile = ST->isVolatile(); 5222 5223 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5224 Ptr, ST->getSrcValue(), 5225 ST->getSrcValueOffset(), 5226 isVolatile, ST->getAlignment()); 5227 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5228 DAG.getConstant(4, Ptr.getValueType())); 5229 SVOffset += 4; 5230 Alignment = MinAlign(Alignment, 4U); 5231 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5232 Ptr, ST->getSrcValue(), 5233 SVOffset, isVolatile, Alignment); 5234 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5235 St0, St1); 5236 } 5237 5238 break; 5239 } 5240 } 5241 } 5242 5243 if (CombinerAA) { 5244 // Walk up chain skipping non-aliasing memory nodes. 5245 SDValue BetterChain = FindBetterChain(N, Chain); 5246 5247 // If there is a better chain. 5248 if (Chain != BetterChain) { 5249 SDValue ReplStore; 5250 5251 // Replace the chain to avoid dependency. 5252 if (ST->isTruncatingStore()) { 5253 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5254 ST->getSrcValue(),ST->getSrcValueOffset(), 5255 ST->getMemoryVT(), 5256 ST->isVolatile(), ST->getAlignment()); 5257 } else { 5258 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5259 ST->getSrcValue(), ST->getSrcValueOffset(), 5260 ST->isVolatile(), ST->getAlignment()); 5261 } 5262 5263 // Create token to keep both nodes around. 5264 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5265 MVT::Other, Chain, ReplStore); 5266 5267 // Make sure the new and old chains are cleaned up. 5268 AddToWorkList(Token.getNode()); 5269 5270 // Don't add users to work list. 5271 return CombineTo(N, Token, false); 5272 } 5273 } 5274 5275 // Try transforming N to an indexed store. 5276 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5277 return SDValue(N, 0); 5278 5279 // FIXME: is there such a thing as a truncating indexed store? 5280 if (ST->isTruncatingStore() && ST->isUnindexed() && 5281 Value.getValueType().isInteger()) { 5282 // See if we can simplify the input to this truncstore with knowledge that 5283 // only the low bits are being used. For example: 5284 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5285 SDValue Shorter = 5286 GetDemandedBits(Value, 5287 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5288 ST->getMemoryVT().getSizeInBits())); 5289 AddToWorkList(Value.getNode()); 5290 if (Shorter.getNode()) 5291 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5292 Ptr, ST->getSrcValue(), 5293 ST->getSrcValueOffset(), ST->getMemoryVT(), 5294 ST->isVolatile(), ST->getAlignment()); 5295 5296 // Otherwise, see if we can simplify the operation with 5297 // SimplifyDemandedBits, which only works if the value has a single use. 5298 if (SimplifyDemandedBits(Value, 5299 APInt::getLowBitsSet( 5300 Value.getValueType().getScalarType().getSizeInBits(), 5301 ST->getMemoryVT().getSizeInBits()))) 5302 return SDValue(N, 0); 5303 } 5304 5305 // If this is a load followed by a store to the same location, then the store 5306 // is dead/noop. 5307 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5308 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5309 ST->isUnindexed() && !ST->isVolatile() && 5310 // There can't be any side effects between the load and store, such as 5311 // a call or store. 5312 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5313 // The store is dead, remove it. 5314 return Chain; 5315 } 5316 } 5317 5318 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5319 // truncating store. We can do this even if this is already a truncstore. 5320 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5321 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5322 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5323 ST->getMemoryVT())) { 5324 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5325 Ptr, ST->getSrcValue(), 5326 ST->getSrcValueOffset(), ST->getMemoryVT(), 5327 ST->isVolatile(), ST->getAlignment()); 5328 } 5329 5330 return ReduceLoadOpStoreWidth(N); 5331} 5332 5333SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5334 SDValue InVec = N->getOperand(0); 5335 SDValue InVal = N->getOperand(1); 5336 SDValue EltNo = N->getOperand(2); 5337 5338 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5339 // vector with the inserted element. 5340 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5341 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5342 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5343 InVec.getNode()->op_end()); 5344 if (Elt < Ops.size()) 5345 Ops[Elt] = InVal; 5346 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5347 InVec.getValueType(), &Ops[0], Ops.size()); 5348 } 5349 // If the invec is an UNDEF and if EltNo is a constant, create a new 5350 // BUILD_VECTOR with undef elements and the inserted element. 5351 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5352 isa<ConstantSDNode>(EltNo)) { 5353 EVT VT = InVec.getValueType(); 5354 EVT EltVT = VT.getVectorElementType(); 5355 unsigned NElts = VT.getVectorNumElements(); 5356 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 5357 5358 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5359 if (Elt < Ops.size()) 5360 Ops[Elt] = InVal; 5361 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5362 InVec.getValueType(), &Ops[0], Ops.size()); 5363 } 5364 return SDValue(); 5365} 5366 5367SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5368 // (vextract (scalar_to_vector val, 0) -> val 5369 SDValue InVec = N->getOperand(0); 5370 5371 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5372 // If the operand is wider than the vector element type then it is implicitly 5373 // truncated. Make that explicit here. 5374 EVT EltVT = InVec.getValueType().getVectorElementType(); 5375 SDValue InOp = InVec.getOperand(0); 5376 if (InOp.getValueType() != EltVT) 5377 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5378 return InOp; 5379 } 5380 5381 // Perform only after legalization to ensure build_vector / vector_shuffle 5382 // optimizations have already been done. 5383 if (!LegalOperations) return SDValue(); 5384 5385 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5386 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5387 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5388 SDValue EltNo = N->getOperand(1); 5389 5390 if (isa<ConstantSDNode>(EltNo)) { 5391 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5392 bool NewLoad = false; 5393 bool BCNumEltsChanged = false; 5394 EVT VT = InVec.getValueType(); 5395 EVT ExtVT = VT.getVectorElementType(); 5396 EVT LVT = ExtVT; 5397 5398 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5399 EVT BCVT = InVec.getOperand(0).getValueType(); 5400 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 5401 return SDValue(); 5402 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5403 BCNumEltsChanged = true; 5404 InVec = InVec.getOperand(0); 5405 ExtVT = BCVT.getVectorElementType(); 5406 NewLoad = true; 5407 } 5408 5409 LoadSDNode *LN0 = NULL; 5410 const ShuffleVectorSDNode *SVN = NULL; 5411 if (ISD::isNormalLoad(InVec.getNode())) { 5412 LN0 = cast<LoadSDNode>(InVec); 5413 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5414 InVec.getOperand(0).getValueType() == ExtVT && 5415 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5416 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5417 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5418 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5419 // => 5420 // (load $addr+1*size) 5421 5422 // If the bit convert changed the number of elements, it is unsafe 5423 // to examine the mask. 5424 if (BCNumEltsChanged) 5425 return SDValue(); 5426 5427 // Select the input vector, guarding against out of range extract vector. 5428 unsigned NumElems = VT.getVectorNumElements(); 5429 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5430 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5431 5432 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5433 InVec = InVec.getOperand(0); 5434 if (ISD::isNormalLoad(InVec.getNode())) { 5435 LN0 = cast<LoadSDNode>(InVec); 5436 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5437 } 5438 } 5439 5440 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5441 return SDValue(); 5442 5443 unsigned Align = LN0->getAlignment(); 5444 if (NewLoad) { 5445 // Check the resultant load doesn't need a higher alignment than the 5446 // original load. 5447 unsigned NewAlign = 5448 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 5449 5450 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5451 return SDValue(); 5452 5453 Align = NewAlign; 5454 } 5455 5456 SDValue NewPtr = LN0->getBasePtr(); 5457 if (Elt) { 5458 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5459 EVT PtrType = NewPtr.getValueType(); 5460 if (TLI.isBigEndian()) 5461 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5462 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5463 DAG.getConstant(PtrOff, PtrType)); 5464 } 5465 5466 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5467 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5468 LN0->isVolatile(), Align); 5469 } 5470 5471 return SDValue(); 5472} 5473 5474SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5475 unsigned NumInScalars = N->getNumOperands(); 5476 EVT VT = N->getValueType(0); 5477 5478 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5479 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5480 // at most two distinct vectors, turn this into a shuffle node. 5481 SDValue VecIn1, VecIn2; 5482 for (unsigned i = 0; i != NumInScalars; ++i) { 5483 // Ignore undef inputs. 5484 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5485 5486 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5487 // constant index, bail out. 5488 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5489 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5490 VecIn1 = VecIn2 = SDValue(0, 0); 5491 break; 5492 } 5493 5494 // If the input vector type disagrees with the result of the build_vector, 5495 // we can't make a shuffle. 5496 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5497 if (ExtractedFromVec.getValueType() != VT) { 5498 VecIn1 = VecIn2 = SDValue(0, 0); 5499 break; 5500 } 5501 5502 // Otherwise, remember this. We allow up to two distinct input vectors. 5503 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5504 continue; 5505 5506 if (VecIn1.getNode() == 0) { 5507 VecIn1 = ExtractedFromVec; 5508 } else if (VecIn2.getNode() == 0) { 5509 VecIn2 = ExtractedFromVec; 5510 } else { 5511 // Too many inputs. 5512 VecIn1 = VecIn2 = SDValue(0, 0); 5513 break; 5514 } 5515 } 5516 5517 // If everything is good, we can make a shuffle operation. 5518 if (VecIn1.getNode()) { 5519 SmallVector<int, 8> Mask; 5520 for (unsigned i = 0; i != NumInScalars; ++i) { 5521 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5522 Mask.push_back(-1); 5523 continue; 5524 } 5525 5526 // If extracting from the first vector, just use the index directly. 5527 SDValue Extract = N->getOperand(i); 5528 SDValue ExtVal = Extract.getOperand(1); 5529 if (Extract.getOperand(0) == VecIn1) { 5530 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5531 if (ExtIndex > VT.getVectorNumElements()) 5532 return SDValue(); 5533 5534 Mask.push_back(ExtIndex); 5535 continue; 5536 } 5537 5538 // Otherwise, use InIdx + VecSize 5539 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5540 Mask.push_back(Idx+NumInScalars); 5541 } 5542 5543 // Add count and size info. 5544 if (!TLI.isTypeLegal(VT) && LegalTypes) 5545 return SDValue(); 5546 5547 // Return the new VECTOR_SHUFFLE node. 5548 SDValue Ops[2]; 5549 Ops[0] = VecIn1; 5550 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5551 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5552 } 5553 5554 return SDValue(); 5555} 5556 5557SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5558 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5559 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5560 // inputs come from at most two distinct vectors, turn this into a shuffle 5561 // node. 5562 5563 // If we only have one input vector, we don't need to do any concatenation. 5564 if (N->getNumOperands() == 1) 5565 return N->getOperand(0); 5566 5567 return SDValue(); 5568} 5569 5570SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5571 return SDValue(); 5572 5573 EVT VT = N->getValueType(0); 5574 unsigned NumElts = VT.getVectorNumElements(); 5575 5576 SDValue N0 = N->getOperand(0); 5577 5578 assert(N0.getValueType().getVectorNumElements() == NumElts && 5579 "Vector shuffle must be normalized in DAG"); 5580 5581 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5582 5583 // If it is a splat, check if the argument vector is a build_vector with 5584 // all scalar elements the same. 5585 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5586 SDNode *V = N0.getNode(); 5587 5588 5589 // If this is a bit convert that changes the element type of the vector but 5590 // not the number of vector elements, look through it. Be careful not to 5591 // look though conversions that change things like v4f32 to v2f64. 5592 if (V->getOpcode() == ISD::BIT_CONVERT) { 5593 SDValue ConvInput = V->getOperand(0); 5594 if (ConvInput.getValueType().isVector() && 5595 ConvInput.getValueType().getVectorNumElements() == NumElts) 5596 V = ConvInput.getNode(); 5597 } 5598 5599 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5600 unsigned NumElems = V->getNumOperands(); 5601 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5602 if (NumElems > BaseIdx) { 5603 SDValue Base; 5604 bool AllSame = true; 5605 for (unsigned i = 0; i != NumElems; ++i) { 5606 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5607 Base = V->getOperand(i); 5608 break; 5609 } 5610 } 5611 // Splat of <u, u, u, u>, return <u, u, u, u> 5612 if (!Base.getNode()) 5613 return N0; 5614 for (unsigned i = 0; i != NumElems; ++i) { 5615 if (V->getOperand(i) != Base) { 5616 AllSame = false; 5617 break; 5618 } 5619 } 5620 // Splat of <x, x, x, x>, return <x, x, x, x> 5621 if (AllSame) 5622 return N0; 5623 } 5624 } 5625 } 5626 return SDValue(); 5627} 5628 5629/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5630/// an AND to a vector_shuffle with the destination vector and a zero vector. 5631/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5632/// vector_shuffle V, Zero, <0, 4, 2, 4> 5633SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5634 EVT VT = N->getValueType(0); 5635 DebugLoc dl = N->getDebugLoc(); 5636 SDValue LHS = N->getOperand(0); 5637 SDValue RHS = N->getOperand(1); 5638 if (N->getOpcode() == ISD::AND) { 5639 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5640 RHS = RHS.getOperand(0); 5641 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5642 SmallVector<int, 8> Indices; 5643 unsigned NumElts = RHS.getNumOperands(); 5644 for (unsigned i = 0; i != NumElts; ++i) { 5645 SDValue Elt = RHS.getOperand(i); 5646 if (!isa<ConstantSDNode>(Elt)) 5647 return SDValue(); 5648 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5649 Indices.push_back(i); 5650 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5651 Indices.push_back(NumElts); 5652 else 5653 return SDValue(); 5654 } 5655 5656 // Let's see if the target supports this vector_shuffle. 5657 EVT RVT = RHS.getValueType(); 5658 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5659 return SDValue(); 5660 5661 // Return the new VECTOR_SHUFFLE node. 5662 EVT EltVT = RVT.getVectorElementType(); 5663 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5664 DAG.getConstant(0, EltVT)); 5665 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5666 RVT, &ZeroOps[0], ZeroOps.size()); 5667 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5668 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5669 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5670 } 5671 } 5672 5673 return SDValue(); 5674} 5675 5676/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5677SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5678 // After legalize, the target may be depending on adds and other 5679 // binary ops to provide legal ways to construct constants or other 5680 // things. Simplifying them may result in a loss of legality. 5681 if (LegalOperations) return SDValue(); 5682 5683 EVT VT = N->getValueType(0); 5684 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5685 5686 EVT EltType = VT.getVectorElementType(); 5687 SDValue LHS = N->getOperand(0); 5688 SDValue RHS = N->getOperand(1); 5689 SDValue Shuffle = XformToShuffleWithZero(N); 5690 if (Shuffle.getNode()) return Shuffle; 5691 5692 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5693 // this operation. 5694 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5695 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5696 SmallVector<SDValue, 8> Ops; 5697 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5698 SDValue LHSOp = LHS.getOperand(i); 5699 SDValue RHSOp = RHS.getOperand(i); 5700 // If these two elements can't be folded, bail out. 5701 if ((LHSOp.getOpcode() != ISD::UNDEF && 5702 LHSOp.getOpcode() != ISD::Constant && 5703 LHSOp.getOpcode() != ISD::ConstantFP) || 5704 (RHSOp.getOpcode() != ISD::UNDEF && 5705 RHSOp.getOpcode() != ISD::Constant && 5706 RHSOp.getOpcode() != ISD::ConstantFP)) 5707 break; 5708 5709 // Can't fold divide by zero. 5710 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5711 N->getOpcode() == ISD::FDIV) { 5712 if ((RHSOp.getOpcode() == ISD::Constant && 5713 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5714 (RHSOp.getOpcode() == ISD::ConstantFP && 5715 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5716 break; 5717 } 5718 5719 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5720 EltType, LHSOp, RHSOp)); 5721 AddToWorkList(Ops.back().getNode()); 5722 assert((Ops.back().getOpcode() == ISD::UNDEF || 5723 Ops.back().getOpcode() == ISD::Constant || 5724 Ops.back().getOpcode() == ISD::ConstantFP) && 5725 "Scalar binop didn't fold!"); 5726 } 5727 5728 if (Ops.size() == LHS.getNumOperands()) { 5729 EVT VT = LHS.getValueType(); 5730 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5731 &Ops[0], Ops.size()); 5732 } 5733 } 5734 5735 return SDValue(); 5736} 5737 5738SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5739 SDValue N1, SDValue N2){ 5740 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5741 5742 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5743 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5744 5745 // If we got a simplified select_cc node back from SimplifySelectCC, then 5746 // break it down into a new SETCC node, and a new SELECT node, and then return 5747 // the SELECT node, since we were called with a SELECT node. 5748 if (SCC.getNode()) { 5749 // Check to see if we got a select_cc back (to turn into setcc/select). 5750 // Otherwise, just return whatever node we got back, like fabs. 5751 if (SCC.getOpcode() == ISD::SELECT_CC) { 5752 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5753 N0.getValueType(), 5754 SCC.getOperand(0), SCC.getOperand(1), 5755 SCC.getOperand(4)); 5756 AddToWorkList(SETCC.getNode()); 5757 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5758 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5759 } 5760 5761 return SCC; 5762 } 5763 return SDValue(); 5764} 5765 5766/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5767/// are the two values being selected between, see if we can simplify the 5768/// select. Callers of this should assume that TheSelect is deleted if this 5769/// returns true. As such, they should return the appropriate thing (e.g. the 5770/// node) back to the top-level of the DAG combiner loop to avoid it being 5771/// looked at. 5772bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5773 SDValue RHS) { 5774 5775 // If this is a select from two identical things, try to pull the operation 5776 // through the select. 5777 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5778 // If this is a load and the token chain is identical, replace the select 5779 // of two loads with a load through a select of the address to load from. 5780 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5781 // constants have been dropped into the constant pool. 5782 if (LHS.getOpcode() == ISD::LOAD && 5783 // Do not let this transformation reduce the number of volatile loads. 5784 !cast<LoadSDNode>(LHS)->isVolatile() && 5785 !cast<LoadSDNode>(RHS)->isVolatile() && 5786 // Token chains must be identical. 5787 LHS.getOperand(0) == RHS.getOperand(0)) { 5788 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5789 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5790 5791 // If this is an EXTLOAD, the VT's must match. 5792 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5793 // FIXME: this discards src value information. This is 5794 // over-conservative. It would be beneficial to be able to remember 5795 // both potential memory locations. 5796 SDValue Addr; 5797 if (TheSelect->getOpcode() == ISD::SELECT) { 5798 // Check that the condition doesn't reach either load. If so, folding 5799 // this will induce a cycle into the DAG. 5800 if ((!LLD->hasAnyUseOfValue(1) || 5801 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 5802 (!RLD->hasAnyUseOfValue(1) || 5803 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 5804 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5805 LLD->getBasePtr().getValueType(), 5806 TheSelect->getOperand(0), LLD->getBasePtr(), 5807 RLD->getBasePtr()); 5808 } 5809 } else { 5810 // Check that the condition doesn't reach either load. If so, folding 5811 // this will induce a cycle into the DAG. 5812 if ((!LLD->hasAnyUseOfValue(1) || 5813 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5814 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 5815 (!RLD->hasAnyUseOfValue(1) || 5816 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5817 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 5818 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5819 LLD->getBasePtr().getValueType(), 5820 TheSelect->getOperand(0), 5821 TheSelect->getOperand(1), 5822 LLD->getBasePtr(), RLD->getBasePtr(), 5823 TheSelect->getOperand(4)); 5824 } 5825 } 5826 5827 if (Addr.getNode()) { 5828 SDValue Load; 5829 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5830 Load = DAG.getLoad(TheSelect->getValueType(0), 5831 TheSelect->getDebugLoc(), 5832 LLD->getChain(), 5833 Addr, 0, 0, 5834 LLD->isVolatile(), 5835 LLD->getAlignment()); 5836 } else { 5837 Load = DAG.getExtLoad(LLD->getExtensionType(), 5838 TheSelect->getDebugLoc(), 5839 TheSelect->getValueType(0), 5840 LLD->getChain(), Addr, 0, 0, 5841 LLD->getMemoryVT(), 5842 LLD->isVolatile(), 5843 LLD->getAlignment()); 5844 } 5845 5846 // Users of the select now use the result of the load. 5847 CombineTo(TheSelect, Load); 5848 5849 // Users of the old loads now use the new load's chain. We know the 5850 // old-load value is dead now. 5851 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5852 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5853 return true; 5854 } 5855 } 5856 } 5857 } 5858 5859 return false; 5860} 5861 5862/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5863/// where 'cond' is the comparison specified by CC. 5864SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5865 SDValue N2, SDValue N3, 5866 ISD::CondCode CC, bool NotExtCompare) { 5867 // (x ? y : y) -> y. 5868 if (N2 == N3) return N2; 5869 5870 EVT VT = N2.getValueType(); 5871 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5872 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5873 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5874 5875 // Determine if the condition we're dealing with is constant 5876 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5877 N0, N1, CC, DL, false); 5878 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5879 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5880 5881 // fold select_cc true, x, y -> x 5882 if (SCCC && !SCCC->isNullValue()) 5883 return N2; 5884 // fold select_cc false, x, y -> y 5885 if (SCCC && SCCC->isNullValue()) 5886 return N3; 5887 5888 // Check to see if we can simplify the select into an fabs node 5889 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5890 // Allow either -0.0 or 0.0 5891 if (CFP->getValueAPF().isZero()) { 5892 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5893 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5894 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5895 N2 == N3.getOperand(0)) 5896 return DAG.getNode(ISD::FABS, DL, VT, N0); 5897 5898 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5899 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5900 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5901 N2.getOperand(0) == N3) 5902 return DAG.getNode(ISD::FABS, DL, VT, N3); 5903 } 5904 } 5905 5906 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5907 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5908 // in it. This is a win when the constant is not otherwise available because 5909 // it replaces two constant pool loads with one. We only do this if the FP 5910 // type is known to be legal, because if it isn't, then we are before legalize 5911 // types an we want the other legalization to happen first (e.g. to avoid 5912 // messing with soft float) and if the ConstantFP is not legal, because if 5913 // it is legal, we may not need to store the FP constant in a constant pool. 5914 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5915 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5916 if (TLI.isTypeLegal(N2.getValueType()) && 5917 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5918 TargetLowering::Legal) && 5919 // If both constants have multiple uses, then we won't need to do an 5920 // extra load, they are likely around in registers for other users. 5921 (TV->hasOneUse() || FV->hasOneUse())) { 5922 Constant *Elts[] = { 5923 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5924 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5925 }; 5926 const Type *FPTy = Elts[0]->getType(); 5927 const TargetData &TD = *TLI.getTargetData(); 5928 5929 // Create a ConstantArray of the two constants. 5930 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5931 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5932 TD.getPrefTypeAlignment(FPTy)); 5933 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5934 5935 // Get the offsets to the 0 and 1 element of the array so that we can 5936 // select between them. 5937 SDValue Zero = DAG.getIntPtrConstant(0); 5938 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5939 SDValue One = DAG.getIntPtrConstant(EltSize); 5940 5941 SDValue Cond = DAG.getSetCC(DL, 5942 TLI.getSetCCResultType(N0.getValueType()), 5943 N0, N1, CC); 5944 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5945 Cond, One, Zero); 5946 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5947 CstOffset); 5948 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5949 PseudoSourceValue::getConstantPool(), 0, false, 5950 Alignment); 5951 5952 } 5953 } 5954 5955 // Check to see if we can perform the "gzip trick", transforming 5956 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5957 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5958 N0.getValueType().isInteger() && 5959 N2.getValueType().isInteger() && 5960 (N1C->isNullValue() || // (a < 0) ? b : 0 5961 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5962 EVT XType = N0.getValueType(); 5963 EVT AType = N2.getValueType(); 5964 if (XType.bitsGE(AType)) { 5965 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5966 // single-bit constant. 5967 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5968 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5969 ShCtV = XType.getSizeInBits()-ShCtV-1; 5970 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5971 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5972 XType, N0, ShCt); 5973 AddToWorkList(Shift.getNode()); 5974 5975 if (XType.bitsGT(AType)) { 5976 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5977 AddToWorkList(Shift.getNode()); 5978 } 5979 5980 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5981 } 5982 5983 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5984 XType, N0, 5985 DAG.getConstant(XType.getSizeInBits()-1, 5986 getShiftAmountTy())); 5987 AddToWorkList(Shift.getNode()); 5988 5989 if (XType.bitsGT(AType)) { 5990 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5991 AddToWorkList(Shift.getNode()); 5992 } 5993 5994 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5995 } 5996 } 5997 5998 // fold select C, 16, 0 -> shl C, 4 5999 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6000 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6001 6002 // If the caller doesn't want us to simplify this into a zext of a compare, 6003 // don't do it. 6004 if (NotExtCompare && N2C->getAPIntValue() == 1) 6005 return SDValue(); 6006 6007 // Get a SetCC of the condition 6008 // FIXME: Should probably make sure that setcc is legal if we ever have a 6009 // target where it isn't. 6010 SDValue Temp, SCC; 6011 // cast from setcc result type to select result type 6012 if (LegalTypes) { 6013 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6014 N0, N1, CC); 6015 if (N2.getValueType().bitsLT(SCC.getValueType())) 6016 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6017 else 6018 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6019 N2.getValueType(), SCC); 6020 } else { 6021 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6022 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6023 N2.getValueType(), SCC); 6024 } 6025 6026 AddToWorkList(SCC.getNode()); 6027 AddToWorkList(Temp.getNode()); 6028 6029 if (N2C->getAPIntValue() == 1) 6030 return Temp; 6031 6032 // shl setcc result by log2 n2c 6033 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6034 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6035 getShiftAmountTy())); 6036 } 6037 6038 // Check to see if this is the equivalent of setcc 6039 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6040 // otherwise, go ahead with the folds. 6041 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6042 EVT XType = N0.getValueType(); 6043 if (!LegalOperations || 6044 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6045 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6046 if (Res.getValueType() != VT) 6047 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6048 return Res; 6049 } 6050 6051 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6052 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6053 (!LegalOperations || 6054 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6055 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6056 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6057 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6058 getShiftAmountTy())); 6059 } 6060 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6061 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6062 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6063 XType, DAG.getConstant(0, XType), N0); 6064 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6065 return DAG.getNode(ISD::SRL, DL, XType, 6066 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6067 DAG.getConstant(XType.getSizeInBits()-1, 6068 getShiftAmountTy())); 6069 } 6070 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6071 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6072 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6073 DAG.getConstant(XType.getSizeInBits()-1, 6074 getShiftAmountTy())); 6075 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6076 } 6077 } 6078 6079 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6080 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6081 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6082 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6083 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6084 EVT XType = N0.getValueType(); 6085 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6086 DAG.getConstant(XType.getSizeInBits()-1, 6087 getShiftAmountTy())); 6088 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6089 N0, Shift); 6090 AddToWorkList(Shift.getNode()); 6091 AddToWorkList(Add.getNode()); 6092 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6093 } 6094 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6095 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6096 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6097 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6098 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6099 EVT XType = N0.getValueType(); 6100 if (SubC->isNullValue() && XType.isInteger()) { 6101 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6102 N0, 6103 DAG.getConstant(XType.getSizeInBits()-1, 6104 getShiftAmountTy())); 6105 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6106 XType, N0, Shift); 6107 AddToWorkList(Shift.getNode()); 6108 AddToWorkList(Add.getNode()); 6109 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6110 } 6111 } 6112 } 6113 6114 return SDValue(); 6115} 6116 6117/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6118SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6119 SDValue N1, ISD::CondCode Cond, 6120 DebugLoc DL, bool foldBooleans) { 6121 TargetLowering::DAGCombinerInfo 6122 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6123 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6124} 6125 6126/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6127/// return a DAG expression to select that will generate the same value by 6128/// multiplying by a magic number. See: 6129/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6130SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6131 std::vector<SDNode*> Built; 6132 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6133 6134 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6135 ii != ee; ++ii) 6136 AddToWorkList(*ii); 6137 return S; 6138} 6139 6140/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6141/// return a DAG expression to select that will generate the same value by 6142/// multiplying by a magic number. See: 6143/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6144SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6145 std::vector<SDNode*> Built; 6146 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6147 6148 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6149 ii != ee; ++ii) 6150 AddToWorkList(*ii); 6151 return S; 6152} 6153 6154/// FindBaseOffset - Return true if base is a frame index, which is known not 6155// to alias with anything but itself. Provides base object and offset as results. 6156static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6157 GlobalValue *&GV, void *&CV) { 6158 // Assume it is a primitive operation. 6159 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6160 6161 // If it's an adding a simple constant then integrate the offset. 6162 if (Base.getOpcode() == ISD::ADD) { 6163 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6164 Base = Base.getOperand(0); 6165 Offset += C->getZExtValue(); 6166 } 6167 } 6168 6169 // Return the underlying GlobalValue, and update the Offset. Return false 6170 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6171 // by multiple nodes with different offsets. 6172 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6173 GV = G->getGlobal(); 6174 Offset += G->getOffset(); 6175 return false; 6176 } 6177 6178 // Return the underlying Constant value, and update the Offset. Return false 6179 // for ConstantSDNodes since the same constant pool entry may be represented 6180 // by multiple nodes with different offsets. 6181 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6182 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6183 : (void *)C->getConstVal(); 6184 Offset += C->getOffset(); 6185 return false; 6186 } 6187 // If it's any of the following then it can't alias with anything but itself. 6188 return isa<FrameIndexSDNode>(Base); 6189} 6190 6191/// isAlias - Return true if there is any possibility that the two addresses 6192/// overlap. 6193bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6194 const Value *SrcValue1, int SrcValueOffset1, 6195 unsigned SrcValueAlign1, 6196 SDValue Ptr2, int64_t Size2, 6197 const Value *SrcValue2, int SrcValueOffset2, 6198 unsigned SrcValueAlign2) const { 6199 // If they are the same then they must be aliases. 6200 if (Ptr1 == Ptr2) return true; 6201 6202 // Gather base node and offset information. 6203 SDValue Base1, Base2; 6204 int64_t Offset1, Offset2; 6205 GlobalValue *GV1, *GV2; 6206 void *CV1, *CV2; 6207 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6208 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6209 6210 // If they have a same base address then check to see if they overlap. 6211 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6212 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6213 6214 // If we know what the bases are, and they aren't identical, then we know they 6215 // cannot alias. 6216 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6217 return false; 6218 6219 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6220 // compared to the size and offset of the access, we may be able to prove they 6221 // do not alias. This check is conservative for now to catch cases created by 6222 // splitting vector types. 6223 if ((SrcValueAlign1 == SrcValueAlign2) && 6224 (SrcValueOffset1 != SrcValueOffset2) && 6225 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6226 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6227 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6228 6229 // There is no overlap between these relatively aligned accesses of similar 6230 // size, return no alias. 6231 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6232 return false; 6233 } 6234 6235 if (CombinerGlobalAA) { 6236 // Use alias analysis information. 6237 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6238 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6239 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6240 AliasAnalysis::AliasResult AAResult = 6241 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6242 if (AAResult == AliasAnalysis::NoAlias) 6243 return false; 6244 } 6245 6246 // Otherwise we have to assume they alias. 6247 return true; 6248} 6249 6250/// FindAliasInfo - Extracts the relevant alias information from the memory 6251/// node. Returns true if the operand was a load. 6252bool DAGCombiner::FindAliasInfo(SDNode *N, 6253 SDValue &Ptr, int64_t &Size, 6254 const Value *&SrcValue, 6255 int &SrcValueOffset, 6256 unsigned &SrcValueAlign) const { 6257 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6258 Ptr = LD->getBasePtr(); 6259 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6260 SrcValue = LD->getSrcValue(); 6261 SrcValueOffset = LD->getSrcValueOffset(); 6262 SrcValueAlign = LD->getOriginalAlignment(); 6263 return true; 6264 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6265 Ptr = ST->getBasePtr(); 6266 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6267 SrcValue = ST->getSrcValue(); 6268 SrcValueOffset = ST->getSrcValueOffset(); 6269 SrcValueAlign = ST->getOriginalAlignment(); 6270 } else { 6271 llvm_unreachable("FindAliasInfo expected a memory operand"); 6272 } 6273 6274 return false; 6275} 6276 6277/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6278/// looking for aliasing nodes and adding them to the Aliases vector. 6279void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6280 SmallVector<SDValue, 8> &Aliases) { 6281 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6282 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 6283 6284 // Get alias information for node. 6285 SDValue Ptr; 6286 int64_t Size; 6287 const Value *SrcValue; 6288 int SrcValueOffset; 6289 unsigned SrcValueAlign; 6290 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 6291 SrcValueAlign); 6292 6293 // Starting off. 6294 Chains.push_back(OriginalChain); 6295 unsigned Depth = 0; 6296 6297 // Look at each chain and determine if it is an alias. If so, add it to the 6298 // aliases list. If not, then continue up the chain looking for the next 6299 // candidate. 6300 while (!Chains.empty()) { 6301 SDValue Chain = Chains.back(); 6302 Chains.pop_back(); 6303 6304 // For TokenFactor nodes, look at each operand and only continue up the 6305 // chain until we find two aliases. If we've seen two aliases, assume we'll 6306 // find more and revert to original chain since the xform is unlikely to be 6307 // profitable. 6308 // 6309 // FIXME: The depth check could be made to return the last non-aliasing 6310 // chain we found before we hit a tokenfactor rather than the original 6311 // chain. 6312 if (Depth > 6 || Aliases.size() == 2) { 6313 Aliases.clear(); 6314 Aliases.push_back(OriginalChain); 6315 break; 6316 } 6317 6318 // Don't bother if we've been before. 6319 if (!Visited.insert(Chain.getNode())) 6320 continue; 6321 6322 switch (Chain.getOpcode()) { 6323 case ISD::EntryToken: 6324 // Entry token is ideal chain operand, but handled in FindBetterChain. 6325 break; 6326 6327 case ISD::LOAD: 6328 case ISD::STORE: { 6329 // Get alias information for Chain. 6330 SDValue OpPtr; 6331 int64_t OpSize; 6332 const Value *OpSrcValue; 6333 int OpSrcValueOffset; 6334 unsigned OpSrcValueAlign; 6335 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6336 OpSrcValue, OpSrcValueOffset, 6337 OpSrcValueAlign); 6338 6339 // If chain is alias then stop here. 6340 if (!(IsLoad && IsOpLoad) && 6341 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 6342 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 6343 OpSrcValueAlign)) { 6344 Aliases.push_back(Chain); 6345 } else { 6346 // Look further up the chain. 6347 Chains.push_back(Chain.getOperand(0)); 6348 ++Depth; 6349 } 6350 break; 6351 } 6352 6353 case ISD::TokenFactor: 6354 // We have to check each of the operands of the token factor for "small" 6355 // token factors, so we queue them up. Adding the operands to the queue 6356 // (stack) in reverse order maintains the original order and increases the 6357 // likelihood that getNode will find a matching token factor (CSE.) 6358 if (Chain.getNumOperands() > 16) { 6359 Aliases.push_back(Chain); 6360 break; 6361 } 6362 for (unsigned n = Chain.getNumOperands(); n;) 6363 Chains.push_back(Chain.getOperand(--n)); 6364 ++Depth; 6365 break; 6366 6367 default: 6368 // For all other instructions we will just have to take what we can get. 6369 Aliases.push_back(Chain); 6370 break; 6371 } 6372 } 6373} 6374 6375/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6376/// for a better chain (aliasing node.) 6377SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6378 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6379 6380 // Accumulate all the aliases to this node. 6381 GatherAllAliases(N, OldChain, Aliases); 6382 6383 if (Aliases.size() == 0) { 6384 // If no operands then chain to entry token. 6385 return DAG.getEntryNode(); 6386 } else if (Aliases.size() == 1) { 6387 // If a single operand then chain to it. We don't need to revisit it. 6388 return Aliases[0]; 6389 } 6390 6391 // Construct a custom tailored token factor. 6392 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6393 &Aliases[0], Aliases.size()); 6394} 6395 6396// SelectionDAG::Combine - This is the entry point for the file. 6397// 6398void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6399 CodeGenOpt::Level OptLevel) { 6400 /// run - This is the main entry point to this class. 6401 /// 6402 DAGCombiner(*this, AA, OptLevel).Run(Level); 6403} 6404