DAGCombiner.cpp revision 73e16b2869fbc75ccb3506620b0342b6085fe843
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 const TargetLowering &TLI; 53 CombineLevel Level; 54 bool LegalOperations; 55 bool LegalTypes; 56 bool Fast; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 // AA - Used for DAG load/store alias analysis. 62 AliasAnalysis &AA; 63 64 /// AddUsersToWorkList - When an instruction is simplified, add all users of 65 /// the instruction to the work lists because they might get more simplified 66 /// now. 67 /// 68 void AddUsersToWorkList(SDNode *N) { 69 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 70 UI != UE; ++UI) 71 AddToWorkList(*UI); 72 } 73 74 /// visit - call the node-specific routine that knows how to fold each 75 /// particular type of node. 76 SDValue visit(SDNode *N); 77 78 public: 79 /// AddToWorkList - Add to the work list making sure it's instance is at the 80 /// the back (next to be processed.) 81 void AddToWorkList(SDNode *N) { 82 removeFromWorkList(N); 83 WorkList.push_back(N); 84 } 85 86 /// removeFromWorkList - remove all instances of N from the worklist. 87 /// 88 void removeFromWorkList(SDNode *N) { 89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 90 WorkList.end()); 91 } 92 93 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 94 bool AddTo = true); 95 96 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 97 return CombineTo(N, &Res, 1, AddTo); 98 } 99 100 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 101 bool AddTo = true) { 102 SDValue To[] = { Res0, Res1 }; 103 return CombineTo(N, To, 2, AddTo); 104 } 105 106 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 107 108 private: 109 110 /// SimplifyDemandedBits - Check the specified integer node value to see if 111 /// it can be simplified or if things it uses can be simplified by bit 112 /// propagation. If so, return true. 113 bool SimplifyDemandedBits(SDValue Op) { 114 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 115 return SimplifyDemandedBits(Op, Demanded); 116 } 117 118 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 119 120 bool CombineToPreIndexedLoadStore(SDNode *N); 121 bool CombineToPostIndexedLoadStore(SDNode *N); 122 123 124 /// combine - call the node-specific routine that knows how to fold each 125 /// particular type of node. If that doesn't do anything, try the 126 /// target-specific DAG combines. 127 SDValue combine(SDNode *N); 128 129 // Visitation implementation - Implement dag node combining for different 130 // node types. The semantics are as follows: 131 // Return Value: 132 // SDValue.getNode() == 0 - No change was made 133 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 134 // otherwise - N should be replaced by the returned Operand. 135 // 136 SDValue visitTokenFactor(SDNode *N); 137 SDValue visitMERGE_VALUES(SDNode *N); 138 SDValue visitADD(SDNode *N); 139 SDValue visitSUB(SDNode *N); 140 SDValue visitADDC(SDNode *N); 141 SDValue visitADDE(SDNode *N); 142 SDValue visitMUL(SDNode *N); 143 SDValue visitSDIV(SDNode *N); 144 SDValue visitUDIV(SDNode *N); 145 SDValue visitSREM(SDNode *N); 146 SDValue visitUREM(SDNode *N); 147 SDValue visitMULHU(SDNode *N); 148 SDValue visitMULHS(SDNode *N); 149 SDValue visitSMUL_LOHI(SDNode *N); 150 SDValue visitUMUL_LOHI(SDNode *N); 151 SDValue visitSDIVREM(SDNode *N); 152 SDValue visitUDIVREM(SDNode *N); 153 SDValue visitAND(SDNode *N); 154 SDValue visitOR(SDNode *N); 155 SDValue visitXOR(SDNode *N); 156 SDValue SimplifyVBinOp(SDNode *N); 157 SDValue visitSHL(SDNode *N); 158 SDValue visitSRA(SDNode *N); 159 SDValue visitSRL(SDNode *N); 160 SDValue visitCTLZ(SDNode *N); 161 SDValue visitCTTZ(SDNode *N); 162 SDValue visitCTPOP(SDNode *N); 163 SDValue visitSELECT(SDNode *N); 164 SDValue visitSELECT_CC(SDNode *N); 165 SDValue visitSETCC(SDNode *N); 166 SDValue visitSIGN_EXTEND(SDNode *N); 167 SDValue visitZERO_EXTEND(SDNode *N); 168 SDValue visitANY_EXTEND(SDNode *N); 169 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 170 SDValue visitTRUNCATE(SDNode *N); 171 SDValue visitBIT_CONVERT(SDNode *N); 172 SDValue visitBUILD_PAIR(SDNode *N); 173 SDValue visitFADD(SDNode *N); 174 SDValue visitFSUB(SDNode *N); 175 SDValue visitFMUL(SDNode *N); 176 SDValue visitFDIV(SDNode *N); 177 SDValue visitFREM(SDNode *N); 178 SDValue visitFCOPYSIGN(SDNode *N); 179 SDValue visitSINT_TO_FP(SDNode *N); 180 SDValue visitUINT_TO_FP(SDNode *N); 181 SDValue visitFP_TO_SINT(SDNode *N); 182 SDValue visitFP_TO_UINT(SDNode *N); 183 SDValue visitFP_ROUND(SDNode *N); 184 SDValue visitFP_ROUND_INREG(SDNode *N); 185 SDValue visitFP_EXTEND(SDNode *N); 186 SDValue visitFNEG(SDNode *N); 187 SDValue visitFABS(SDNode *N); 188 SDValue visitBRCOND(SDNode *N); 189 SDValue visitBR_CC(SDNode *N); 190 SDValue visitLOAD(SDNode *N); 191 SDValue visitSTORE(SDNode *N); 192 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 193 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 194 SDValue visitBUILD_VECTOR(SDNode *N); 195 SDValue visitCONCAT_VECTORS(SDNode *N); 196 SDValue visitVECTOR_SHUFFLE(SDNode *N); 197 198 SDValue XformToShuffleWithZero(SDNode *N); 199 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 200 201 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 202 203 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 204 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 205 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 206 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 207 SDValue N3, ISD::CondCode CC, 208 bool NotExtCompare = false); 209 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 210 bool foldBooleans = true); 211 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 212 unsigned HiOp); 213 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 214 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 215 SDValue BuildSDIV(SDNode *N); 216 SDValue BuildUDIV(SDNode *N); 217 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 218 SDValue ReduceLoadWidth(SDNode *N); 219 220 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 221 222 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 223 /// looking for aliasing nodes and adding them to the Aliases vector. 224 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 225 SmallVector<SDValue, 8> &Aliases); 226 227 /// isAlias - Return true if there is any possibility that the two addresses 228 /// overlap. 229 bool isAlias(SDValue Ptr1, int64_t Size1, 230 const Value *SrcValue1, int SrcValueOffset1, 231 SDValue Ptr2, int64_t Size2, 232 const Value *SrcValue2, int SrcValueOffset2); 233 234 /// FindAliasInfo - Extracts the relevant alias information from the memory 235 /// node. Returns true if the operand was a load. 236 bool FindAliasInfo(SDNode *N, 237 SDValue &Ptr, int64_t &Size, 238 const Value *&SrcValue, int &SrcValueOffset); 239 240 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 241 /// looking for a better chain (aliasing node.) 242 SDValue FindBetterChain(SDNode *N, SDValue Chain); 243 244public: 245 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 246 : DAG(D), 247 TLI(D.getTargetLoweringInfo()), 248 Level(Unrestricted), 249 LegalOperations(false), 250 LegalTypes(false), 251 Fast(fast), 252 AA(A) {} 253 254 /// Run - runs the dag combiner on all nodes in the work list 255 void Run(CombineLevel AtLevel); 256 }; 257} 258 259 260namespace { 261/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 262/// nodes from the worklist. 263class VISIBILITY_HIDDEN WorkListRemover : 264 public SelectionDAG::DAGUpdateListener { 265 DAGCombiner &DC; 266public: 267 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 268 269 virtual void NodeDeleted(SDNode *N, SDNode *E) { 270 DC.removeFromWorkList(N); 271 } 272 273 virtual void NodeUpdated(SDNode *N) { 274 // Ignore updates. 275 } 276}; 277} 278 279//===----------------------------------------------------------------------===// 280// TargetLowering::DAGCombinerInfo implementation 281//===----------------------------------------------------------------------===// 282 283void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 284 ((DAGCombiner*)DC)->AddToWorkList(N); 285} 286 287SDValue TargetLowering::DAGCombinerInfo:: 288CombineTo(SDNode *N, const std::vector<SDValue> &To) { 289 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 290} 291 292SDValue TargetLowering::DAGCombinerInfo:: 293CombineTo(SDNode *N, SDValue Res) { 294 return ((DAGCombiner*)DC)->CombineTo(N, Res); 295} 296 297 298SDValue TargetLowering::DAGCombinerInfo:: 299CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 300 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 301} 302 303void TargetLowering::DAGCombinerInfo:: 304CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 305 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 306} 307 308//===----------------------------------------------------------------------===// 309// Helper Functions 310//===----------------------------------------------------------------------===// 311 312/// isNegatibleForFree - Return 1 if we can compute the negated form of the 313/// specified expression for the same cost as the expression itself, or 2 if we 314/// can compute the negated form more cheaply than the expression itself. 315static char isNegatibleForFree(SDValue Op, bool LegalOperations, 316 unsigned Depth = 0) { 317 // No compile time optimizations on this type. 318 if (Op.getValueType() == MVT::ppcf128) 319 return 0; 320 321 // fneg is removable even if it has multiple uses. 322 if (Op.getOpcode() == ISD::FNEG) return 2; 323 324 // Don't allow anything with multiple uses. 325 if (!Op.hasOneUse()) return 0; 326 327 // Don't recurse exponentially. 328 if (Depth > 6) return 0; 329 330 switch (Op.getOpcode()) { 331 default: return false; 332 case ISD::ConstantFP: 333 // Don't invert constant FP values after legalize. The negated constant 334 // isn't necessarily legal. 335 return LegalOperations ? 0 : 1; 336 case ISD::FADD: 337 // FIXME: determine better conditions for this xform. 338 if (!UnsafeFPMath) return 0; 339 340 // -(A+B) -> -A - B 341 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 342 return V; 343 // -(A+B) -> -B - A 344 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 345 case ISD::FSUB: 346 // We can't turn -(A-B) into B-A when we honor signed zeros. 347 if (!UnsafeFPMath) return 0; 348 349 // -(A-B) -> B-A 350 return 1; 351 352 case ISD::FMUL: 353 case ISD::FDIV: 354 if (HonorSignDependentRoundingFPMath()) return 0; 355 356 // -(X*Y) -> (-X * Y) or (X*-Y) 357 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 358 return V; 359 360 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 361 362 case ISD::FP_EXTEND: 363 case ISD::FP_ROUND: 364 case ISD::FSIN: 365 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 366 } 367} 368 369/// GetNegatedExpression - If isNegatibleForFree returns true, this function 370/// returns the newly negated expression. 371static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 372 bool LegalOperations, unsigned Depth = 0) { 373 // fneg is removable even if it has multiple uses. 374 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 375 376 // Don't allow anything with multiple uses. 377 assert(Op.hasOneUse() && "Unknown reuse!"); 378 379 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 380 switch (Op.getOpcode()) { 381 default: assert(0 && "Unknown code"); 382 case ISD::ConstantFP: { 383 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 384 V.changeSign(); 385 return DAG.getConstantFP(V, Op.getValueType()); 386 } 387 case ISD::FADD: 388 // FIXME: determine better conditions for this xform. 389 assert(UnsafeFPMath); 390 391 // -(A+B) -> -A - B 392 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 393 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 394 GetNegatedExpression(Op.getOperand(0), DAG, 395 LegalOperations, Depth+1), 396 Op.getOperand(1)); 397 // -(A+B) -> -B - A 398 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 399 GetNegatedExpression(Op.getOperand(1), DAG, 400 LegalOperations, Depth+1), 401 Op.getOperand(0)); 402 case ISD::FSUB: 403 // We can't turn -(A-B) into B-A when we honor signed zeros. 404 assert(UnsafeFPMath); 405 406 // -(0-B) -> B 407 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 408 if (N0CFP->getValueAPF().isZero()) 409 return Op.getOperand(1); 410 411 // -(A-B) -> B-A 412 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 413 Op.getOperand(1), Op.getOperand(0)); 414 415 case ISD::FMUL: 416 case ISD::FDIV: 417 assert(!HonorSignDependentRoundingFPMath()); 418 419 // -(X*Y) -> -X * Y 420 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 421 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 422 GetNegatedExpression(Op.getOperand(0), DAG, 423 LegalOperations, Depth+1), 424 Op.getOperand(1)); 425 426 // -(X*Y) -> X * -Y 427 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 428 Op.getOperand(0), 429 GetNegatedExpression(Op.getOperand(1), DAG, 430 LegalOperations, Depth+1)); 431 432 case ISD::FP_EXTEND: 433 case ISD::FSIN: 434 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 435 GetNegatedExpression(Op.getOperand(0), DAG, 436 LegalOperations, Depth+1)); 437 case ISD::FP_ROUND: 438 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 439 GetNegatedExpression(Op.getOperand(0), DAG, 440 LegalOperations, Depth+1), 441 Op.getOperand(1)); 442 } 443} 444 445 446// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 447// that selects between the values 1 and 0, making it equivalent to a setcc. 448// Also, set the incoming LHS, RHS, and CC references to the appropriate 449// nodes based on the type of node we are checking. This simplifies life a 450// bit for the callers. 451static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 452 SDValue &CC) { 453 if (N.getOpcode() == ISD::SETCC) { 454 LHS = N.getOperand(0); 455 RHS = N.getOperand(1); 456 CC = N.getOperand(2); 457 return true; 458 } 459 if (N.getOpcode() == ISD::SELECT_CC && 460 N.getOperand(2).getOpcode() == ISD::Constant && 461 N.getOperand(3).getOpcode() == ISD::Constant && 462 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 463 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 464 LHS = N.getOperand(0); 465 RHS = N.getOperand(1); 466 CC = N.getOperand(4); 467 return true; 468 } 469 return false; 470} 471 472// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 473// one use. If this is true, it allows the users to invert the operation for 474// free when it is profitable to do so. 475static bool isOneUseSetCC(SDValue N) { 476 SDValue N0, N1, N2; 477 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 478 return true; 479 return false; 480} 481 482SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 483 SDValue N0, SDValue N1) { 484 MVT VT = N0.getValueType(); 485 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 486 if (isa<ConstantSDNode>(N1)) { 487 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 488 SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT, 489 N0.getOperand(1), N1); 490 AddToWorkList(OpNode.getNode()); 491 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 492 } else if (N0.hasOneUse()) { 493 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 494 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 495 N0.getOperand(0), N1); 496 AddToWorkList(OpNode.getNode()); 497 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 498 } 499 } 500 501 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 502 if (isa<ConstantSDNode>(N0)) { 503 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 504 SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT, 505 N1.getOperand(1), N0); 506 AddToWorkList(OpNode.getNode()); 507 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 508 } else if (N1.hasOneUse()) { 509 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 510 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 511 N1.getOperand(0), N0); 512 AddToWorkList(OpNode.getNode()); 513 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 514 } 515 } 516 517 return SDValue(); 518} 519 520SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 521 bool AddTo) { 522 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 523 ++NodesCombined; 524 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 525 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 526 DOUT << " and " << NumTo-1 << " other values\n"; 527 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 528 assert(N->getValueType(i) == To[i].getValueType() && 529 "Cannot combine value to value of different type!")); 530 WorkListRemover DeadNodes(*this); 531 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 532 533 if (AddTo) { 534 // Push the new nodes and any users onto the worklist 535 for (unsigned i = 0, e = NumTo; i != e; ++i) { 536 AddToWorkList(To[i].getNode()); 537 AddUsersToWorkList(To[i].getNode()); 538 } 539 } 540 541 // Finally, if the node is now dead, remove it from the graph. The node 542 // may not be dead if the replacement process recursively simplified to 543 // something else needing this node. 544 if (N->use_empty()) { 545 // Nodes can be reintroduced into the worklist. Make sure we do not 546 // process a node that has been replaced. 547 removeFromWorkList(N); 548 549 // Finally, since the node is now dead, remove it from the graph. 550 DAG.DeleteNode(N); 551 } 552 return SDValue(N, 0); 553} 554 555void 556DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 557 TLO) { 558 // Replace all uses. If any nodes become isomorphic to other nodes and 559 // are deleted, make sure to remove them from our worklist. 560 WorkListRemover DeadNodes(*this); 561 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 562 563 // Push the new node and any (possibly new) users onto the worklist. 564 AddToWorkList(TLO.New.getNode()); 565 AddUsersToWorkList(TLO.New.getNode()); 566 567 // Finally, if the node is now dead, remove it from the graph. The node 568 // may not be dead if the replacement process recursively simplified to 569 // something else needing this node. 570 if (TLO.Old.getNode()->use_empty()) { 571 removeFromWorkList(TLO.Old.getNode()); 572 573 // If the operands of this node are only used by the node, they will now 574 // be dead. Make sure to visit them first to delete dead nodes early. 575 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 576 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 577 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 578 579 DAG.DeleteNode(TLO.Old.getNode()); 580 } 581} 582 583/// SimplifyDemandedBits - Check the specified integer node value to see if 584/// it can be simplified or if things it uses can be simplified by bit 585/// propagation. If so, return true. 586bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 587 TargetLowering::TargetLoweringOpt TLO(DAG); 588 APInt KnownZero, KnownOne; 589 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 590 return false; 591 592 // Revisit the node. 593 AddToWorkList(Op.getNode()); 594 595 // Replace the old value with the new one. 596 ++NodesCombined; 597 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 598 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 599 DOUT << '\n'; 600 601 CommitTargetLoweringOpt(TLO); 602 return true; 603} 604 605//===----------------------------------------------------------------------===// 606// Main DAG Combiner implementation 607//===----------------------------------------------------------------------===// 608 609void DAGCombiner::Run(CombineLevel AtLevel) { 610 // set the instance variables, so that the various visit routines may use it. 611 Level = AtLevel; 612 LegalOperations = Level >= NoIllegalOperations; 613 LegalTypes = Level >= NoIllegalTypes; 614 615 // Add all the dag nodes to the worklist. 616 WorkList.reserve(DAG.allnodes_size()); 617 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 618 E = DAG.allnodes_end(); I != E; ++I) 619 WorkList.push_back(I); 620 621 // Create a dummy node (which is not added to allnodes), that adds a reference 622 // to the root node, preventing it from being deleted, and tracking any 623 // changes of the root. 624 HandleSDNode Dummy(DAG.getRoot()); 625 626 // The root of the dag may dangle to deleted nodes until the dag combiner is 627 // done. Set it to null to avoid confusion. 628 DAG.setRoot(SDValue()); 629 630 // while the worklist isn't empty, inspect the node on the end of it and 631 // try and combine it. 632 while (!WorkList.empty()) { 633 SDNode *N = WorkList.back(); 634 WorkList.pop_back(); 635 636 // If N has no uses, it is dead. Make sure to revisit all N's operands once 637 // N is deleted from the DAG, since they too may now be dead or may have a 638 // reduced number of uses, allowing other xforms. 639 if (N->use_empty() && N != &Dummy) { 640 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 641 AddToWorkList(N->getOperand(i).getNode()); 642 643 DAG.DeleteNode(N); 644 continue; 645 } 646 647 SDValue RV = combine(N); 648 649 if (RV.getNode() == 0) 650 continue; 651 652 ++NodesCombined; 653 654 // If we get back the same node we passed in, rather than a new node or 655 // zero, we know that the node must have defined multiple values and 656 // CombineTo was used. Since CombineTo takes care of the worklist 657 // mechanics for us, we have no work to do in this case. 658 if (RV.getNode() == N) 659 continue; 660 661 assert(N->getOpcode() != ISD::DELETED_NODE && 662 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 663 "Node was deleted but visit returned new node!"); 664 665 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 666 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 667 DOUT << '\n'; 668 WorkListRemover DeadNodes(*this); 669 if (N->getNumValues() == RV.getNode()->getNumValues()) 670 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 671 else { 672 assert(N->getValueType(0) == RV.getValueType() && 673 N->getNumValues() == 1 && "Type mismatch"); 674 SDValue OpV = RV; 675 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 676 } 677 678 // Push the new node and any users onto the worklist 679 AddToWorkList(RV.getNode()); 680 AddUsersToWorkList(RV.getNode()); 681 682 // Add any uses of the old node to the worklist in case this node is the 683 // last one that uses them. They may become dead after this node is 684 // deleted. 685 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 686 AddToWorkList(N->getOperand(i).getNode()); 687 688 // Finally, if the node is now dead, remove it from the graph. The node 689 // may not be dead if the replacement process recursively simplified to 690 // something else needing this node. 691 if (N->use_empty()) { 692 // Nodes can be reintroduced into the worklist. Make sure we do not 693 // process a node that has been replaced. 694 removeFromWorkList(N); 695 696 // Finally, since the node is now dead, remove it from the graph. 697 DAG.DeleteNode(N); 698 } 699 } 700 701 // If the root changed (e.g. it was a dead load, update the root). 702 DAG.setRoot(Dummy.getValue()); 703} 704 705SDValue DAGCombiner::visit(SDNode *N) { 706 switch(N->getOpcode()) { 707 default: break; 708 case ISD::TokenFactor: return visitTokenFactor(N); 709 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 710 case ISD::ADD: return visitADD(N); 711 case ISD::SUB: return visitSUB(N); 712 case ISD::ADDC: return visitADDC(N); 713 case ISD::ADDE: return visitADDE(N); 714 case ISD::MUL: return visitMUL(N); 715 case ISD::SDIV: return visitSDIV(N); 716 case ISD::UDIV: return visitUDIV(N); 717 case ISD::SREM: return visitSREM(N); 718 case ISD::UREM: return visitUREM(N); 719 case ISD::MULHU: return visitMULHU(N); 720 case ISD::MULHS: return visitMULHS(N); 721 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 722 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 723 case ISD::SDIVREM: return visitSDIVREM(N); 724 case ISD::UDIVREM: return visitUDIVREM(N); 725 case ISD::AND: return visitAND(N); 726 case ISD::OR: return visitOR(N); 727 case ISD::XOR: return visitXOR(N); 728 case ISD::SHL: return visitSHL(N); 729 case ISD::SRA: return visitSRA(N); 730 case ISD::SRL: return visitSRL(N); 731 case ISD::CTLZ: return visitCTLZ(N); 732 case ISD::CTTZ: return visitCTTZ(N); 733 case ISD::CTPOP: return visitCTPOP(N); 734 case ISD::SELECT: return visitSELECT(N); 735 case ISD::SELECT_CC: return visitSELECT_CC(N); 736 case ISD::SETCC: return visitSETCC(N); 737 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 738 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 739 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 740 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 741 case ISD::TRUNCATE: return visitTRUNCATE(N); 742 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 743 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 744 case ISD::FADD: return visitFADD(N); 745 case ISD::FSUB: return visitFSUB(N); 746 case ISD::FMUL: return visitFMUL(N); 747 case ISD::FDIV: return visitFDIV(N); 748 case ISD::FREM: return visitFREM(N); 749 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 750 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 751 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 752 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 753 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 754 case ISD::FP_ROUND: return visitFP_ROUND(N); 755 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 756 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 757 case ISD::FNEG: return visitFNEG(N); 758 case ISD::FABS: return visitFABS(N); 759 case ISD::BRCOND: return visitBRCOND(N); 760 case ISD::BR_CC: return visitBR_CC(N); 761 case ISD::LOAD: return visitLOAD(N); 762 case ISD::STORE: return visitSTORE(N); 763 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 764 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 765 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 766 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 767 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 768 } 769 return SDValue(); 770} 771 772SDValue DAGCombiner::combine(SDNode *N) { 773 SDValue RV = visit(N); 774 775 // If nothing happened, try a target-specific DAG combine. 776 if (RV.getNode() == 0) { 777 assert(N->getOpcode() != ISD::DELETED_NODE && 778 "Node was deleted but visit returned NULL!"); 779 780 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 781 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 782 783 // Expose the DAG combiner to the target combiner impls. 784 TargetLowering::DAGCombinerInfo 785 DagCombineInfo(DAG, Level == Unrestricted, false, this); 786 787 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 788 } 789 } 790 791 // If N is a commutative binary node, try commuting it to enable more 792 // sdisel CSE. 793 if (RV.getNode() == 0 && 794 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 795 N->getNumValues() == 1) { 796 SDValue N0 = N->getOperand(0); 797 SDValue N1 = N->getOperand(1); 798 799 // Constant operands are canonicalized to RHS. 800 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 801 SDValue Ops[] = { N1, N0 }; 802 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 803 Ops, 2); 804 if (CSENode) 805 return SDValue(CSENode, 0); 806 } 807 } 808 809 return RV; 810} 811 812/// getInputChainForNode - Given a node, return its input chain if it has one, 813/// otherwise return a null sd operand. 814static SDValue getInputChainForNode(SDNode *N) { 815 if (unsigned NumOps = N->getNumOperands()) { 816 if (N->getOperand(0).getValueType() == MVT::Other) 817 return N->getOperand(0); 818 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 819 return N->getOperand(NumOps-1); 820 for (unsigned i = 1; i < NumOps-1; ++i) 821 if (N->getOperand(i).getValueType() == MVT::Other) 822 return N->getOperand(i); 823 } 824 return SDValue(); 825} 826 827SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 828 // If N has two operands, where one has an input chain equal to the other, 829 // the 'other' chain is redundant. 830 if (N->getNumOperands() == 2) { 831 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 832 return N->getOperand(0); 833 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 834 return N->getOperand(1); 835 } 836 837 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 838 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 839 SmallPtrSet<SDNode*, 16> SeenOps; 840 bool Changed = false; // If we should replace this token factor. 841 842 // Start out with this token factor. 843 TFs.push_back(N); 844 845 // Iterate through token factors. The TFs grows when new token factors are 846 // encountered. 847 for (unsigned i = 0; i < TFs.size(); ++i) { 848 SDNode *TF = TFs[i]; 849 850 // Check each of the operands. 851 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 852 SDValue Op = TF->getOperand(i); 853 854 switch (Op.getOpcode()) { 855 case ISD::EntryToken: 856 // Entry tokens don't need to be added to the list. They are 857 // rededundant. 858 Changed = true; 859 break; 860 861 case ISD::TokenFactor: 862 if ((CombinerAA || Op.hasOneUse()) && 863 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 864 // Queue up for processing. 865 TFs.push_back(Op.getNode()); 866 // Clean up in case the token factor is removed. 867 AddToWorkList(Op.getNode()); 868 Changed = true; 869 break; 870 } 871 // Fall thru 872 873 default: 874 // Only add if it isn't already in the list. 875 if (SeenOps.insert(Op.getNode())) 876 Ops.push_back(Op); 877 else 878 Changed = true; 879 break; 880 } 881 } 882 } 883 884 SDValue Result; 885 886 // If we've change things around then replace token factor. 887 if (Changed) { 888 if (Ops.empty()) { 889 // The entry token is the only possible outcome. 890 Result = DAG.getEntryNode(); 891 } else { 892 // New and improved token factor. 893 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 894 MVT::Other, &Ops[0], Ops.size()); 895 } 896 897 // Don't add users to work list. 898 return CombineTo(N, Result, false); 899 } 900 901 return Result; 902} 903 904/// MERGE_VALUES can always be eliminated. 905SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 906 WorkListRemover DeadNodes(*this); 907 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 908 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 909 &DeadNodes); 910 removeFromWorkList(N); 911 DAG.DeleteNode(N); 912 return SDValue(N, 0); // Return N so it doesn't get rechecked! 913} 914 915static 916SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 917 SelectionDAG &DAG) { 918 MVT VT = N0.getValueType(); 919 SDValue N00 = N0.getOperand(0); 920 SDValue N01 = N0.getOperand(1); 921 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 922 923 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 924 isa<ConstantSDNode>(N00.getOperand(1))) { 925 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 926 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 927 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 928 N00.getOperand(0), N01), 929 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 930 N00.getOperand(1), N01)); 931 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 932 } 933 934 return SDValue(); 935} 936 937static 938SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 939 SelectionDAG &DAG, const TargetLowering &TLI, 940 bool LegalOperations) { 941 MVT VT = N->getValueType(0); 942 unsigned Opc = N->getOpcode(); 943 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 944 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 945 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 946 ISD::CondCode CC = ISD::SETCC_INVALID; 947 948 if (isSlctCC) { 949 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 950 } else { 951 SDValue CCOp = Slct.getOperand(0); 952 if (CCOp.getOpcode() == ISD::SETCC) 953 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 954 } 955 956 bool DoXform = false; 957 bool InvCC = false; 958 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 959 "Bad input!"); 960 961 if (LHS.getOpcode() == ISD::Constant && 962 cast<ConstantSDNode>(LHS)->isNullValue()) { 963 DoXform = true; 964 } else if (CC != ISD::SETCC_INVALID && 965 RHS.getOpcode() == ISD::Constant && 966 cast<ConstantSDNode>(RHS)->isNullValue()) { 967 std::swap(LHS, RHS); 968 SDValue Op0 = Slct.getOperand(0); 969 MVT OpVT = isSlctCC ? Op0.getValueType() : 970 Op0.getOperand(0).getValueType(); 971 bool isInt = OpVT.isInteger(); 972 CC = ISD::getSetCCInverse(CC, isInt); 973 974 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT)) 975 return SDValue(); // Inverse operator isn't legal. 976 977 DoXform = true; 978 InvCC = true; 979 } 980 981 if (DoXform) { 982 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 983 if (isSlctCC) 984 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 985 Slct.getOperand(0), Slct.getOperand(1), CC); 986 SDValue CCOp = Slct.getOperand(0); 987 if (InvCC) 988 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 989 CCOp.getOperand(0), CCOp.getOperand(1), CC); 990 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 991 CCOp, OtherOp, Result); 992 } 993 return SDValue(); 994} 995 996SDValue DAGCombiner::visitADD(SDNode *N) { 997 SDValue N0 = N->getOperand(0); 998 SDValue N1 = N->getOperand(1); 999 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1000 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1001 MVT VT = N0.getValueType(); 1002 1003 // fold vector ops 1004 if (VT.isVector()) { 1005 SDValue FoldedVOp = SimplifyVBinOp(N); 1006 if (FoldedVOp.getNode()) return FoldedVOp; 1007 } 1008 1009 // fold (add x, undef) -> undef 1010 if (N0.getOpcode() == ISD::UNDEF) 1011 return N0; 1012 if (N1.getOpcode() == ISD::UNDEF) 1013 return N1; 1014 // fold (add c1, c2) -> c1+c2 1015 if (N0C && N1C) 1016 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1017 // canonicalize constant to RHS 1018 if (N0C && !N1C) 1019 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1020 // fold (add x, 0) -> x 1021 if (N1C && N1C->isNullValue()) 1022 return N0; 1023 // fold (add Sym, c) -> Sym+c 1024 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1025 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1026 GA->getOpcode() == ISD::GlobalAddress) 1027 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1028 GA->getOffset() + 1029 (uint64_t)N1C->getSExtValue()); 1030 // fold ((c1-A)+c2) -> (c1+c2)-A 1031 if (N1C && N0.getOpcode() == ISD::SUB) 1032 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1034 DAG.getConstant(N1C->getAPIntValue()+ 1035 N0C->getAPIntValue(), VT), 1036 N0.getOperand(1)); 1037 // reassociate add 1038 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1039 if (RADD.getNode() != 0) 1040 return RADD; 1041 // fold ((0-A) + B) -> B-A 1042 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1043 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1044 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1045 // fold (A + (0-B)) -> A-B 1046 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1047 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1048 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1049 // fold (A+(B-A)) -> B 1050 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1051 return N1.getOperand(0); 1052 // fold ((B-A)+A) -> B 1053 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1054 return N0.getOperand(0); 1055 // fold (A+(B-(A+C))) to (B-C) 1056 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1057 N0 == N1.getOperand(1).getOperand(0)) 1058 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1059 N1.getOperand(1).getOperand(1)); 1060 // fold (A+(B-(C+A))) to (B-C) 1061 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1062 N0 == N1.getOperand(1).getOperand(1)) 1063 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1064 N1.getOperand(1).getOperand(0)); 1065 // fold (A+((B-A)+or-C)) to (B+or-C) 1066 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1067 N1.getOperand(0).getOpcode() == ISD::SUB && 1068 N0 == N1.getOperand(0).getOperand(1)) 1069 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1070 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1071 1072 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1073 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1074 SDValue N00 = N0.getOperand(0); 1075 SDValue N01 = N0.getOperand(1); 1076 SDValue N10 = N1.getOperand(0); 1077 SDValue N11 = N1.getOperand(1); 1078 1079 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1080 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1081 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1082 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1083 } 1084 1085 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1086 return SDValue(N, 0); 1087 1088 // fold (a+b) -> (a|b) iff a and b share no bits. 1089 if (VT.isInteger() && !VT.isVector()) { 1090 APInt LHSZero, LHSOne; 1091 APInt RHSZero, RHSOne; 1092 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1093 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1094 1095 if (LHSZero.getBoolValue()) { 1096 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1097 1098 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1099 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1100 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1101 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1102 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1103 } 1104 } 1105 1106 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1107 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1108 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1109 if (Result.getNode()) return Result; 1110 } 1111 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1112 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1113 if (Result.getNode()) return Result; 1114 } 1115 1116 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1117 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1118 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations); 1119 if (Result.getNode()) return Result; 1120 } 1121 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1122 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1123 if (Result.getNode()) return Result; 1124 } 1125 1126 return SDValue(); 1127} 1128 1129SDValue DAGCombiner::visitADDC(SDNode *N) { 1130 SDValue N0 = N->getOperand(0); 1131 SDValue N1 = N->getOperand(1); 1132 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1133 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1134 MVT VT = N0.getValueType(); 1135 1136 // If the flag result is dead, turn this into an ADD. 1137 if (N->hasNUsesOfValue(0, 1)) 1138 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1139 DAG.getNode(ISD::CARRY_FALSE, 1140 N->getDebugLoc(), MVT::Flag)); 1141 1142 // canonicalize constant to RHS. 1143 if (N0C && !N1C) 1144 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1145 1146 // fold (addc x, 0) -> x + no carry out 1147 if (N1C && N1C->isNullValue()) 1148 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1149 N->getDebugLoc(), MVT::Flag)); 1150 1151 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1152 APInt LHSZero, LHSOne; 1153 APInt RHSZero, RHSOne; 1154 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1155 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1156 1157 if (LHSZero.getBoolValue()) { 1158 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1159 1160 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1161 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1162 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1163 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1164 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1165 DAG.getNode(ISD::CARRY_FALSE, 1166 N->getDebugLoc(), MVT::Flag)); 1167 } 1168 1169 return SDValue(); 1170} 1171 1172SDValue DAGCombiner::visitADDE(SDNode *N) { 1173 SDValue N0 = N->getOperand(0); 1174 SDValue N1 = N->getOperand(1); 1175 SDValue CarryIn = N->getOperand(2); 1176 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1177 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1178 1179 // canonicalize constant to RHS 1180 if (N0C && !N1C) 1181 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1182 N1, N0, CarryIn); 1183 1184 // fold (adde x, y, false) -> (addc x, y) 1185 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1186 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1187 1188 return SDValue(); 1189} 1190 1191SDValue DAGCombiner::visitSUB(SDNode *N) { 1192 SDValue N0 = N->getOperand(0); 1193 SDValue N1 = N->getOperand(1); 1194 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1195 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1196 MVT VT = N0.getValueType(); 1197 1198 // fold vector ops 1199 if (VT.isVector()) { 1200 SDValue FoldedVOp = SimplifyVBinOp(N); 1201 if (FoldedVOp.getNode()) return FoldedVOp; 1202 } 1203 1204 // fold (sub x, x) -> 0 1205 if (N0 == N1) 1206 return DAG.getConstant(0, N->getValueType(0)); 1207 // fold (sub c1, c2) -> c1-c2 1208 if (N0C && N1C) 1209 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1210 // fold (sub x, c) -> (add x, -c) 1211 if (N1C) 1212 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1213 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1214 // fold (A+B)-A -> B 1215 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1216 return N0.getOperand(1); 1217 // fold (A+B)-B -> A 1218 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1219 return N0.getOperand(0); 1220 // fold ((A+(B+or-C))-B) -> A+or-C 1221 if (N0.getOpcode() == ISD::ADD && 1222 (N0.getOperand(1).getOpcode() == ISD::SUB || 1223 N0.getOperand(1).getOpcode() == ISD::ADD) && 1224 N0.getOperand(1).getOperand(0) == N1) 1225 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1226 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1227 // fold ((A+(C+B))-B) -> A+C 1228 if (N0.getOpcode() == ISD::ADD && 1229 N0.getOperand(1).getOpcode() == ISD::ADD && 1230 N0.getOperand(1).getOperand(1) == N1) 1231 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1232 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1233 // fold ((A-(B-C))-C) -> A-B 1234 if (N0.getOpcode() == ISD::SUB && 1235 N0.getOperand(1).getOpcode() == ISD::SUB && 1236 N0.getOperand(1).getOperand(1) == N1) 1237 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1238 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1239 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1240 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1241 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1242 if (Result.getNode()) return Result; 1243 } 1244 1245 // If either operand of a sub is undef, the result is undef 1246 if (N0.getOpcode() == ISD::UNDEF) 1247 return N0; 1248 if (N1.getOpcode() == ISD::UNDEF) 1249 return N1; 1250 1251 // If the relocation model supports it, consider symbol offsets. 1252 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1253 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1254 // fold (sub Sym, c) -> Sym-c 1255 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1256 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1257 GA->getOffset() - 1258 (uint64_t)N1C->getSExtValue()); 1259 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1260 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1261 if (GA->getGlobal() == GB->getGlobal()) 1262 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1263 VT); 1264 } 1265 1266 return SDValue(); 1267} 1268 1269SDValue DAGCombiner::visitMUL(SDNode *N) { 1270 SDValue N0 = N->getOperand(0); 1271 SDValue N1 = N->getOperand(1); 1272 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1273 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1274 MVT VT = N0.getValueType(); 1275 1276 // fold vector ops 1277 if (VT.isVector()) { 1278 SDValue FoldedVOp = SimplifyVBinOp(N); 1279 if (FoldedVOp.getNode()) return FoldedVOp; 1280 } 1281 1282 // fold (mul x, undef) -> 0 1283 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1284 return DAG.getConstant(0, VT); 1285 // fold (mul c1, c2) -> c1*c2 1286 if (N0C && N1C) 1287 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1288 // canonicalize constant to RHS 1289 if (N0C && !N1C) 1290 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1291 // fold (mul x, 0) -> 0 1292 if (N1C && N1C->isNullValue()) 1293 return N1; 1294 // fold (mul x, -1) -> 0-x 1295 if (N1C && N1C->isAllOnesValue()) 1296 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1297 DAG.getConstant(0, VT), N0); 1298 // fold (mul x, (1 << c)) -> x << c 1299 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1300 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1301 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1302 TLI.getShiftAmountTy())); 1303 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1304 if (N1C && isPowerOf2_64(-N1C->getSExtValue())) 1305 // FIXME: If the input is something that is easily negated (e.g. a 1306 // single-use add), we should put the negate there. 1307 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1308 DAG.getConstant(0, VT), 1309 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1310 DAG.getConstant(Log2_64(-N1C->getSExtValue()), 1311 TLI.getShiftAmountTy()))); 1312 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1313 if (N1C && N0.getOpcode() == ISD::SHL && 1314 isa<ConstantSDNode>(N0.getOperand(1))) { 1315 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1316 N1, N0.getOperand(1)); 1317 AddToWorkList(C3.getNode()); 1318 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1319 N0.getOperand(0), C3); 1320 } 1321 1322 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1323 // use. 1324 { 1325 SDValue Sh(0,0), Y(0,0); 1326 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1327 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1328 N0.getNode()->hasOneUse()) { 1329 Sh = N0; Y = N1; 1330 } else if (N1.getOpcode() == ISD::SHL && 1331 isa<ConstantSDNode>(N1.getOperand(1)) && 1332 N1.getNode()->hasOneUse()) { 1333 Sh = N1; Y = N0; 1334 } 1335 1336 if (Sh.getNode()) { 1337 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1338 Sh.getOperand(0), Y); 1339 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1340 Mul, Sh.getOperand(1)); 1341 } 1342 } 1343 1344 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1345 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1346 isa<ConstantSDNode>(N0.getOperand(1))) 1347 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1348 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1349 N0.getOperand(0), N1), 1350 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1351 N0.getOperand(1), N1)); 1352 1353 // reassociate mul 1354 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1355 if (RMUL.getNode() != 0) 1356 return RMUL; 1357 1358 return SDValue(); 1359} 1360 1361SDValue DAGCombiner::visitSDIV(SDNode *N) { 1362 SDValue N0 = N->getOperand(0); 1363 SDValue N1 = N->getOperand(1); 1364 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1365 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1366 MVT VT = N->getValueType(0); 1367 1368 // fold vector ops 1369 if (VT.isVector()) { 1370 SDValue FoldedVOp = SimplifyVBinOp(N); 1371 if (FoldedVOp.getNode()) return FoldedVOp; 1372 } 1373 1374 // fold (sdiv c1, c2) -> c1/c2 1375 if (N0C && N1C && !N1C->isNullValue()) 1376 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1377 // fold (sdiv X, 1) -> X 1378 if (N1C && N1C->getSExtValue() == 1LL) 1379 return N0; 1380 // fold (sdiv X, -1) -> 0-X 1381 if (N1C && N1C->isAllOnesValue()) 1382 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1383 // If we know the sign bits of both operands are zero, strength reduce to a 1384 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1385 if (!VT.isVector()) { 1386 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1387 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1388 } 1389 // fold (sdiv X, pow2) -> simple ops after legalize 1390 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1391 (isPowerOf2_64(N1C->getSExtValue()) || 1392 isPowerOf2_64(-N1C->getSExtValue()))) { 1393 // If dividing by powers of two is cheap, then don't perform the following 1394 // fold. 1395 if (TLI.isPow2DivCheap()) 1396 return SDValue(); 1397 int64_t pow2 = N1C->getSExtValue(); 1398 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1399 unsigned lg2 = Log2_64(abs2); 1400 // Splat the sign bit into the register 1401 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1402 DAG.getConstant(VT.getSizeInBits()-1, 1403 TLI.getShiftAmountTy())); 1404 AddToWorkList(SGN.getNode()); 1405 // Add (N0 < 0) ? abs2 - 1 : 0; 1406 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1407 DAG.getConstant(VT.getSizeInBits()-lg2, 1408 TLI.getShiftAmountTy())); 1409 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1410 AddToWorkList(SRL.getNode()); 1411 AddToWorkList(ADD.getNode()); // Divide by pow2 1412 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1413 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1414 // If we're dividing by a positive value, we're done. Otherwise, we must 1415 // negate the result. 1416 if (pow2 > 0) 1417 return SRA; 1418 AddToWorkList(SRA.getNode()); 1419 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1420 } 1421 // if integer divide is expensive and we satisfy the requirements, emit an 1422 // alternate sequence. 1423 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1424 !TLI.isIntDivCheap()) { 1425 SDValue Op = BuildSDIV(N); 1426 if (Op.getNode()) return Op; 1427 } 1428 1429 // undef / X -> 0 1430 if (N0.getOpcode() == ISD::UNDEF) 1431 return DAG.getConstant(0, VT); 1432 // X / undef -> undef 1433 if (N1.getOpcode() == ISD::UNDEF) 1434 return N1; 1435 1436 return SDValue(); 1437} 1438 1439SDValue DAGCombiner::visitUDIV(SDNode *N) { 1440 SDValue N0 = N->getOperand(0); 1441 SDValue N1 = N->getOperand(1); 1442 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1443 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1444 MVT VT = N->getValueType(0); 1445 1446 // fold vector ops 1447 if (VT.isVector()) { 1448 SDValue FoldedVOp = SimplifyVBinOp(N); 1449 if (FoldedVOp.getNode()) return FoldedVOp; 1450 } 1451 1452 // fold (udiv c1, c2) -> c1/c2 1453 if (N0C && N1C && !N1C->isNullValue()) 1454 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1455 // fold (udiv x, (1 << c)) -> x >>u c 1456 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1457 return DAG.getNode(ISD::SRL, VT, N0, 1458 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1459 TLI.getShiftAmountTy())); 1460 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1461 if (N1.getOpcode() == ISD::SHL) { 1462 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1463 if (SHC->getAPIntValue().isPowerOf2()) { 1464 MVT ADDVT = N1.getOperand(1).getValueType(); 1465 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1466 DAG.getConstant(SHC->getAPIntValue() 1467 .logBase2(), 1468 ADDVT)); 1469 AddToWorkList(Add.getNode()); 1470 return DAG.getNode(ISD::SRL, VT, N0, Add); 1471 } 1472 } 1473 } 1474 // fold (udiv x, c) -> alternate 1475 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1476 SDValue Op = BuildUDIV(N); 1477 if (Op.getNode()) return Op; 1478 } 1479 1480 // undef / X -> 0 1481 if (N0.getOpcode() == ISD::UNDEF) 1482 return DAG.getConstant(0, VT); 1483 // X / undef -> undef 1484 if (N1.getOpcode() == ISD::UNDEF) 1485 return N1; 1486 1487 return SDValue(); 1488} 1489 1490SDValue DAGCombiner::visitSREM(SDNode *N) { 1491 SDValue N0 = N->getOperand(0); 1492 SDValue N1 = N->getOperand(1); 1493 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1494 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1495 MVT VT = N->getValueType(0); 1496 1497 // fold (srem c1, c2) -> c1%c2 1498 if (N0C && N1C && !N1C->isNullValue()) 1499 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1500 // If we know the sign bits of both operands are zero, strength reduce to a 1501 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1502 if (!VT.isVector()) { 1503 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1504 return DAG.getNode(ISD::UREM, VT, N0, N1); 1505 } 1506 1507 // If X/C can be simplified by the division-by-constant logic, lower 1508 // X%C to the equivalent of X-X/C*C. 1509 if (N1C && !N1C->isNullValue()) { 1510 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1511 AddToWorkList(Div.getNode()); 1512 SDValue OptimizedDiv = combine(Div.getNode()); 1513 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1514 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1515 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1516 AddToWorkList(Mul.getNode()); 1517 return Sub; 1518 } 1519 } 1520 1521 // undef % X -> 0 1522 if (N0.getOpcode() == ISD::UNDEF) 1523 return DAG.getConstant(0, VT); 1524 // X % undef -> undef 1525 if (N1.getOpcode() == ISD::UNDEF) 1526 return N1; 1527 1528 return SDValue(); 1529} 1530 1531SDValue DAGCombiner::visitUREM(SDNode *N) { 1532 SDValue N0 = N->getOperand(0); 1533 SDValue N1 = N->getOperand(1); 1534 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1535 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1536 MVT VT = N->getValueType(0); 1537 1538 // fold (urem c1, c2) -> c1%c2 1539 if (N0C && N1C && !N1C->isNullValue()) 1540 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1541 // fold (urem x, pow2) -> (and x, pow2-1) 1542 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1543 return DAG.getNode(ISD::AND, VT, N0, 1544 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1545 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1546 if (N1.getOpcode() == ISD::SHL) { 1547 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1548 if (SHC->getAPIntValue().isPowerOf2()) { 1549 SDValue Add = 1550 DAG.getNode(ISD::ADD, VT, N1, 1551 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1552 VT)); 1553 AddToWorkList(Add.getNode()); 1554 return DAG.getNode(ISD::AND, VT, N0, Add); 1555 } 1556 } 1557 } 1558 1559 // If X/C can be simplified by the division-by-constant logic, lower 1560 // X%C to the equivalent of X-X/C*C. 1561 if (N1C && !N1C->isNullValue()) { 1562 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1563 AddToWorkList(Div.getNode()); 1564 SDValue OptimizedDiv = combine(Div.getNode()); 1565 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1566 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1567 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1568 AddToWorkList(Mul.getNode()); 1569 return Sub; 1570 } 1571 } 1572 1573 // undef % X -> 0 1574 if (N0.getOpcode() == ISD::UNDEF) 1575 return DAG.getConstant(0, VT); 1576 // X % undef -> undef 1577 if (N1.getOpcode() == ISD::UNDEF) 1578 return N1; 1579 1580 return SDValue(); 1581} 1582 1583SDValue DAGCombiner::visitMULHS(SDNode *N) { 1584 SDValue N0 = N->getOperand(0); 1585 SDValue N1 = N->getOperand(1); 1586 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1587 MVT VT = N->getValueType(0); 1588 1589 // fold (mulhs x, 0) -> 0 1590 if (N1C && N1C->isNullValue()) 1591 return N1; 1592 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1593 if (N1C && N1C->getAPIntValue() == 1) 1594 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1595 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1596 TLI.getShiftAmountTy())); 1597 // fold (mulhs x, undef) -> 0 1598 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1599 return DAG.getConstant(0, VT); 1600 1601 return SDValue(); 1602} 1603 1604SDValue DAGCombiner::visitMULHU(SDNode *N) { 1605 SDValue N0 = N->getOperand(0); 1606 SDValue N1 = N->getOperand(1); 1607 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1608 MVT VT = N->getValueType(0); 1609 1610 // fold (mulhu x, 0) -> 0 1611 if (N1C && N1C->isNullValue()) 1612 return N1; 1613 // fold (mulhu x, 1) -> 0 1614 if (N1C && N1C->getAPIntValue() == 1) 1615 return DAG.getConstant(0, N0.getValueType()); 1616 // fold (mulhu x, undef) -> 0 1617 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1618 return DAG.getConstant(0, VT); 1619 1620 return SDValue(); 1621} 1622 1623/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1624/// compute two values. LoOp and HiOp give the opcodes for the two computations 1625/// that are being performed. Return true if a simplification was made. 1626/// 1627SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1628 unsigned HiOp) { 1629 // If the high half is not needed, just compute the low half. 1630 bool HiExists = N->hasAnyUseOfValue(1); 1631 if (!HiExists && 1632 (!LegalOperations || 1633 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1634 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1635 N->getNumOperands()); 1636 return CombineTo(N, Res, Res); 1637 } 1638 1639 // If the low half is not needed, just compute the high half. 1640 bool LoExists = N->hasAnyUseOfValue(0); 1641 if (!LoExists && 1642 (!LegalOperations || 1643 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1644 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1645 N->getNumOperands()); 1646 return CombineTo(N, Res, Res); 1647 } 1648 1649 // If both halves are used, return as it is. 1650 if (LoExists && HiExists) 1651 return SDValue(); 1652 1653 // If the two computed results can be simplified separately, separate them. 1654 if (LoExists) { 1655 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1656 N->op_begin(), N->getNumOperands()); 1657 AddToWorkList(Lo.getNode()); 1658 SDValue LoOpt = combine(Lo.getNode()); 1659 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1660 (!LegalOperations || 1661 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1662 return CombineTo(N, LoOpt, LoOpt); 1663 } 1664 1665 if (HiExists) { 1666 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1667 N->op_begin(), N->getNumOperands()); 1668 AddToWorkList(Hi.getNode()); 1669 SDValue HiOpt = combine(Hi.getNode()); 1670 if (HiOpt.getNode() && HiOpt != Hi && 1671 (!LegalOperations || 1672 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1673 return CombineTo(N, HiOpt, HiOpt); 1674 } 1675 return SDValue(); 1676} 1677 1678SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1679 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1680 if (Res.getNode()) return Res; 1681 1682 return SDValue(); 1683} 1684 1685SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1686 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1687 if (Res.getNode()) return Res; 1688 1689 return SDValue(); 1690} 1691 1692SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1693 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1694 if (Res.getNode()) return Res; 1695 1696 return SDValue(); 1697} 1698 1699SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1700 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1701 if (Res.getNode()) return Res; 1702 1703 return SDValue(); 1704} 1705 1706/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1707/// two operands of the same opcode, try to simplify it. 1708SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1709 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1710 MVT VT = N0.getValueType(); 1711 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1712 1713 // For each of OP in AND/OR/XOR: 1714 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1715 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1716 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1717 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1718 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1719 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1720 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1721 SDValue ORNode = DAG.getNode(N->getOpcode(), 1722 N0.getOperand(0).getValueType(), 1723 N0.getOperand(0), N1.getOperand(0)); 1724 AddToWorkList(ORNode.getNode()); 1725 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1726 } 1727 1728 // For each of OP in SHL/SRL/SRA/AND... 1729 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1730 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1731 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1732 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1733 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1734 N0.getOperand(1) == N1.getOperand(1)) { 1735 SDValue ORNode = DAG.getNode(N->getOpcode(), 1736 N0.getOperand(0).getValueType(), 1737 N0.getOperand(0), N1.getOperand(0)); 1738 AddToWorkList(ORNode.getNode()); 1739 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1740 } 1741 1742 return SDValue(); 1743} 1744 1745SDValue DAGCombiner::visitAND(SDNode *N) { 1746 SDValue N0 = N->getOperand(0); 1747 SDValue N1 = N->getOperand(1); 1748 SDValue LL, LR, RL, RR, CC0, CC1; 1749 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1750 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1751 MVT VT = N1.getValueType(); 1752 unsigned BitWidth = VT.getSizeInBits(); 1753 1754 // fold vector ops 1755 if (VT.isVector()) { 1756 SDValue FoldedVOp = SimplifyVBinOp(N); 1757 if (FoldedVOp.getNode()) return FoldedVOp; 1758 } 1759 1760 // fold (and x, undef) -> 0 1761 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1762 return DAG.getConstant(0, VT); 1763 // fold (and c1, c2) -> c1&c2 1764 if (N0C && N1C) 1765 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1766 // canonicalize constant to RHS 1767 if (N0C && !N1C) 1768 return DAG.getNode(ISD::AND, VT, N1, N0); 1769 // fold (and x, -1) -> x 1770 if (N1C && N1C->isAllOnesValue()) 1771 return N0; 1772 // if (and x, c) is known to be zero, return 0 1773 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1774 APInt::getAllOnesValue(BitWidth))) 1775 return DAG.getConstant(0, VT); 1776 // reassociate and 1777 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1778 if (RAND.getNode() != 0) 1779 return RAND; 1780 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1781 if (N1C && N0.getOpcode() == ISD::OR) 1782 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1783 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1784 return N1; 1785 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1786 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1787 SDValue N0Op0 = N0.getOperand(0); 1788 APInt Mask = ~N1C->getAPIntValue(); 1789 Mask.trunc(N0Op0.getValueSizeInBits()); 1790 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1791 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1792 N0Op0); 1793 1794 // Replace uses of the AND with uses of the Zero extend node. 1795 CombineTo(N, Zext); 1796 1797 // We actually want to replace all uses of the any_extend with the 1798 // zero_extend, to avoid duplicating things. This will later cause this 1799 // AND to be folded. 1800 CombineTo(N0.getNode(), Zext); 1801 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1802 } 1803 } 1804 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1805 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1806 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1807 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1808 1809 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1810 LL.getValueType().isInteger()) { 1811 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1812 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1813 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1814 AddToWorkList(ORNode.getNode()); 1815 return DAG.getSetCC(VT, ORNode, LR, Op1); 1816 } 1817 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1818 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1819 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1820 AddToWorkList(ANDNode.getNode()); 1821 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1822 } 1823 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1824 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1825 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1826 AddToWorkList(ORNode.getNode()); 1827 return DAG.getSetCC(VT, ORNode, LR, Op1); 1828 } 1829 } 1830 // canonicalize equivalent to ll == rl 1831 if (LL == RR && LR == RL) { 1832 Op1 = ISD::getSetCCSwappedOperands(Op1); 1833 std::swap(RL, RR); 1834 } 1835 if (LL == RL && LR == RR) { 1836 bool isInteger = LL.getValueType().isInteger(); 1837 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1838 if (Result != ISD::SETCC_INVALID && 1839 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1840 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1841 } 1842 } 1843 1844 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1845 if (N0.getOpcode() == N1.getOpcode()) { 1846 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1847 if (Tmp.getNode()) return Tmp; 1848 } 1849 1850 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1851 // fold (and (sra)) -> (and (srl)) when possible. 1852 if (!VT.isVector() && 1853 SimplifyDemandedBits(SDValue(N, 0))) 1854 return SDValue(N, 0); 1855 // fold (zext_inreg (extload x)) -> (zextload x) 1856 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1857 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1858 MVT EVT = LN0->getMemoryVT(); 1859 // If we zero all the possible extended bits, then we can turn this into 1860 // a zextload if we are running before legalize or the operation is legal. 1861 unsigned BitWidth = N1.getValueSizeInBits(); 1862 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1863 BitWidth - EVT.getSizeInBits())) && 1864 ((!LegalOperations && !LN0->isVolatile()) || 1865 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1866 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1867 LN0->getBasePtr(), LN0->getSrcValue(), 1868 LN0->getSrcValueOffset(), EVT, 1869 LN0->isVolatile(), LN0->getAlignment()); 1870 AddToWorkList(N); 1871 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1872 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1873 } 1874 } 1875 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1876 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1877 N0.hasOneUse()) { 1878 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1879 MVT EVT = LN0->getMemoryVT(); 1880 // If we zero all the possible extended bits, then we can turn this into 1881 // a zextload if we are running before legalize or the operation is legal. 1882 unsigned BitWidth = N1.getValueSizeInBits(); 1883 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1884 BitWidth - EVT.getSizeInBits())) && 1885 ((!LegalOperations && !LN0->isVolatile()) || 1886 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1887 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1888 LN0->getBasePtr(), LN0->getSrcValue(), 1889 LN0->getSrcValueOffset(), EVT, 1890 LN0->isVolatile(), LN0->getAlignment()); 1891 AddToWorkList(N); 1892 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1893 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1894 } 1895 } 1896 1897 // fold (and (load x), 255) -> (zextload x, i8) 1898 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1899 if (N1C && N0.getOpcode() == ISD::LOAD) { 1900 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1901 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1902 LN0->isUnindexed() && N0.hasOneUse() && 1903 // Do not change the width of a volatile load. 1904 !LN0->isVolatile()) { 1905 MVT EVT = MVT::Other; 1906 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1907 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1908 EVT = MVT::getIntegerVT(ActiveBits); 1909 1910 MVT LoadedVT = LN0->getMemoryVT(); 1911 // Do not generate loads of non-round integer types since these can 1912 // be expensive (and would be wrong if the type is not byte sized). 1913 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1914 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1915 MVT PtrType = N0.getOperand(1).getValueType(); 1916 // For big endian targets, we need to add an offset to the pointer to 1917 // load the correct bytes. For little endian systems, we merely need to 1918 // read fewer bytes from the same pointer. 1919 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1920 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1921 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1922 unsigned Alignment = LN0->getAlignment(); 1923 SDValue NewPtr = LN0->getBasePtr(); 1924 if (TLI.isBigEndian()) { 1925 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1926 DAG.getConstant(PtrOff, PtrType)); 1927 Alignment = MinAlign(Alignment, PtrOff); 1928 } 1929 AddToWorkList(NewPtr.getNode()); 1930 SDValue Load = 1931 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1932 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1933 LN0->isVolatile(), Alignment); 1934 AddToWorkList(N); 1935 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1936 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1937 } 1938 } 1939 } 1940 1941 return SDValue(); 1942} 1943 1944SDValue DAGCombiner::visitOR(SDNode *N) { 1945 SDValue N0 = N->getOperand(0); 1946 SDValue N1 = N->getOperand(1); 1947 SDValue LL, LR, RL, RR, CC0, CC1; 1948 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1949 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1950 MVT VT = N1.getValueType(); 1951 1952 // fold vector ops 1953 if (VT.isVector()) { 1954 SDValue FoldedVOp = SimplifyVBinOp(N); 1955 if (FoldedVOp.getNode()) return FoldedVOp; 1956 } 1957 1958 // fold (or x, undef) -> -1 1959 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1960 return DAG.getConstant(~0ULL, VT); 1961 // fold (or c1, c2) -> c1|c2 1962 if (N0C && N1C) 1963 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1964 // canonicalize constant to RHS 1965 if (N0C && !N1C) 1966 return DAG.getNode(ISD::OR, VT, N1, N0); 1967 // fold (or x, 0) -> x 1968 if (N1C && N1C->isNullValue()) 1969 return N0; 1970 // fold (or x, -1) -> -1 1971 if (N1C && N1C->isAllOnesValue()) 1972 return N1; 1973 // fold (or x, c) -> c iff (x & ~c) == 0 1974 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1975 return N1; 1976 // reassociate or 1977 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1978 if (ROR.getNode() != 0) 1979 return ROR; 1980 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1981 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1982 isa<ConstantSDNode>(N0.getOperand(1))) { 1983 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1984 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1985 N1), 1986 DAG.getConstant(N1C->getAPIntValue() | 1987 C1->getAPIntValue(), VT)); 1988 } 1989 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1990 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1991 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1992 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1993 1994 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1995 LL.getValueType().isInteger()) { 1996 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1997 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1998 if (cast<ConstantSDNode>(LR)->isNullValue() && 1999 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2000 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 2001 AddToWorkList(ORNode.getNode()); 2002 return DAG.getSetCC(VT, ORNode, LR, Op1); 2003 } 2004 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 2005 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 2006 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2007 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2008 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 2009 AddToWorkList(ANDNode.getNode()); 2010 return DAG.getSetCC(VT, ANDNode, LR, Op1); 2011 } 2012 } 2013 // canonicalize equivalent to ll == rl 2014 if (LL == RR && LR == RL) { 2015 Op1 = ISD::getSetCCSwappedOperands(Op1); 2016 std::swap(RL, RR); 2017 } 2018 if (LL == RL && LR == RR) { 2019 bool isInteger = LL.getValueType().isInteger(); 2020 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2021 if (Result != ISD::SETCC_INVALID && 2022 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2023 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 2024 } 2025 } 2026 2027 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 2028 if (N0.getOpcode() == N1.getOpcode()) { 2029 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2030 if (Tmp.getNode()) return Tmp; 2031 } 2032 2033 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 2034 if (N0.getOpcode() == ISD::AND && 2035 N1.getOpcode() == ISD::AND && 2036 N0.getOperand(1).getOpcode() == ISD::Constant && 2037 N1.getOperand(1).getOpcode() == ISD::Constant && 2038 // Don't increase # computations. 2039 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2040 // We can only do this xform if we know that bits from X that are set in C2 2041 // but not in C1 are already zero. Likewise for Y. 2042 const APInt &LHSMask = 2043 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2044 const APInt &RHSMask = 2045 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2046 2047 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2048 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2049 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 2050 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 2051 } 2052 } 2053 2054 2055 // See if this is some rotate idiom. 2056 if (SDNode *Rot = MatchRotate(N0, N1)) 2057 return SDValue(Rot, 0); 2058 2059 return SDValue(); 2060} 2061 2062 2063/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2064static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2065 if (Op.getOpcode() == ISD::AND) { 2066 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2067 Mask = Op.getOperand(1); 2068 Op = Op.getOperand(0); 2069 } else { 2070 return false; 2071 } 2072 } 2073 2074 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2075 Shift = Op; 2076 return true; 2077 } 2078 return false; 2079} 2080 2081 2082// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2083// idioms for rotate, and if the target supports rotation instructions, generate 2084// a rot[lr]. 2085SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 2086 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2087 MVT VT = LHS.getValueType(); 2088 if (!TLI.isTypeLegal(VT)) return 0; 2089 2090 // The target must have at least one rotate flavor. 2091 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2092 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2093 if (!HasROTL && !HasROTR) return 0; 2094 2095 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2096 SDValue LHSShift; // The shift. 2097 SDValue LHSMask; // AND value if any. 2098 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2099 return 0; // Not part of a rotate. 2100 2101 SDValue RHSShift; // The shift. 2102 SDValue RHSMask; // AND value if any. 2103 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2104 return 0; // Not part of a rotate. 2105 2106 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2107 return 0; // Not shifting the same value. 2108 2109 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2110 return 0; // Shifts must disagree. 2111 2112 // Canonicalize shl to left side in a shl/srl pair. 2113 if (RHSShift.getOpcode() == ISD::SHL) { 2114 std::swap(LHS, RHS); 2115 std::swap(LHSShift, RHSShift); 2116 std::swap(LHSMask , RHSMask ); 2117 } 2118 2119 unsigned OpSizeInBits = VT.getSizeInBits(); 2120 SDValue LHSShiftArg = LHSShift.getOperand(0); 2121 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2122 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2123 2124 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2125 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2126 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2127 RHSShiftAmt.getOpcode() == ISD::Constant) { 2128 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2129 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2130 if ((LShVal + RShVal) != OpSizeInBits) 2131 return 0; 2132 2133 SDValue Rot; 2134 if (HasROTL) 2135 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2136 else 2137 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2138 2139 // If there is an AND of either shifted operand, apply it to the result. 2140 if (LHSMask.getNode() || RHSMask.getNode()) { 2141 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2142 2143 if (LHSMask.getNode()) { 2144 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2145 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2146 } 2147 if (RHSMask.getNode()) { 2148 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2149 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2150 } 2151 2152 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2153 } 2154 2155 return Rot.getNode(); 2156 } 2157 2158 // If there is a mask here, and we have a variable shift, we can't be sure 2159 // that we're masking out the right stuff. 2160 if (LHSMask.getNode() || RHSMask.getNode()) 2161 return 0; 2162 2163 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2164 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2165 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2166 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2167 if (ConstantSDNode *SUBC = 2168 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2169 if (SUBC->getAPIntValue() == OpSizeInBits) { 2170 if (HasROTL) 2171 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2172 else 2173 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2174 } 2175 } 2176 } 2177 2178 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2179 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2180 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2181 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2182 if (ConstantSDNode *SUBC = 2183 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2184 if (SUBC->getAPIntValue() == OpSizeInBits) { 2185 if (HasROTR) 2186 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2187 else 2188 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2189 } 2190 } 2191 } 2192 2193 // Look for sign/zext/any-extended or truncate cases: 2194 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2195 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2196 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2197 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2198 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2199 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2200 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2201 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2202 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2203 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2204 if (RExtOp0.getOpcode() == ISD::SUB && 2205 RExtOp0.getOperand(1) == LExtOp0) { 2206 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2207 // (rotl x, y) 2208 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2209 // (rotr x, (sub 32, y)) 2210 if (ConstantSDNode *SUBC = 2211 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2212 if (SUBC->getAPIntValue() == OpSizeInBits) { 2213 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, 2214 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2215 } 2216 } 2217 } else if (LExtOp0.getOpcode() == ISD::SUB && 2218 RExtOp0 == LExtOp0.getOperand(1)) { 2219 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2220 // (rotr x, y) 2221 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2222 // (rotl x, (sub 32, y)) 2223 if (ConstantSDNode *SUBC = 2224 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2225 if (SUBC->getAPIntValue() == OpSizeInBits) { 2226 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, 2227 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2228 } 2229 } 2230 } 2231 } 2232 2233 return 0; 2234} 2235 2236 2237SDValue DAGCombiner::visitXOR(SDNode *N) { 2238 SDValue N0 = N->getOperand(0); 2239 SDValue N1 = N->getOperand(1); 2240 SDValue LHS, RHS, CC; 2241 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2242 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2243 MVT VT = N0.getValueType(); 2244 2245 // fold vector ops 2246 if (VT.isVector()) { 2247 SDValue FoldedVOp = SimplifyVBinOp(N); 2248 if (FoldedVOp.getNode()) return FoldedVOp; 2249 } 2250 2251 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2252 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2253 return DAG.getConstant(0, VT); 2254 // fold (xor x, undef) -> undef 2255 if (N0.getOpcode() == ISD::UNDEF) 2256 return N0; 2257 if (N1.getOpcode() == ISD::UNDEF) 2258 return N1; 2259 // fold (xor c1, c2) -> c1^c2 2260 if (N0C && N1C) 2261 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2262 // canonicalize constant to RHS 2263 if (N0C && !N1C) 2264 return DAG.getNode(ISD::XOR, VT, N1, N0); 2265 // fold (xor x, 0) -> x 2266 if (N1C && N1C->isNullValue()) 2267 return N0; 2268 // reassociate xor 2269 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2270 if (RXOR.getNode() != 0) 2271 return RXOR; 2272 2273 // fold !(x cc y) -> (x !cc y) 2274 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2275 bool isInt = LHS.getValueType().isInteger(); 2276 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2277 isInt); 2278 2279 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2280 switch (N0.getOpcode()) { 2281 default: 2282 assert(0 && "Unhandled SetCC Equivalent!"); 2283 abort(); 2284 case ISD::SETCC: 2285 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2286 case ISD::SELECT_CC: 2287 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2), 2288 N0.getOperand(3), NotCC); 2289 } 2290 } 2291 } 2292 2293 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2294 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2295 N0.getNode()->hasOneUse() && 2296 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2297 SDValue V = N0.getOperand(0); 2298 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2299 DAG.getConstant(1, V.getValueType())); 2300 AddToWorkList(V.getNode()); 2301 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2302 } 2303 2304 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2305 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2306 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2307 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2308 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2309 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2310 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2311 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2312 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2313 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2314 } 2315 } 2316 // fold !(x or y) -> (!x and !y) iff x or y are constants 2317 if (N1C && N1C->isAllOnesValue() && 2318 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2319 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2320 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2321 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2322 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2323 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2324 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2325 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2326 } 2327 } 2328 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2329 if (N1C && N0.getOpcode() == ISD::XOR) { 2330 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2331 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2332 if (N00C) 2333 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2334 DAG.getConstant(N1C->getAPIntValue()^ 2335 N00C->getAPIntValue(), VT)); 2336 if (N01C) 2337 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2338 DAG.getConstant(N1C->getAPIntValue()^ 2339 N01C->getAPIntValue(), VT)); 2340 } 2341 // fold (xor x, x) -> 0 2342 if (N0 == N1) { 2343 if (!VT.isVector()) { 2344 return DAG.getConstant(0, VT); 2345 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2346 // Produce a vector of zeros. 2347 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2348 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2349 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2350 } 2351 } 2352 2353 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2354 if (N0.getOpcode() == N1.getOpcode()) { 2355 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2356 if (Tmp.getNode()) return Tmp; 2357 } 2358 2359 // Simplify the expression using non-local knowledge. 2360 if (!VT.isVector() && 2361 SimplifyDemandedBits(SDValue(N, 0))) 2362 return SDValue(N, 0); 2363 2364 return SDValue(); 2365} 2366 2367/// visitShiftByConstant - Handle transforms common to the three shifts, when 2368/// the shift amount is a constant. 2369SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2370 SDNode *LHS = N->getOperand(0).getNode(); 2371 if (!LHS->hasOneUse()) return SDValue(); 2372 2373 // We want to pull some binops through shifts, so that we have (and (shift)) 2374 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2375 // thing happens with address calculations, so it's important to canonicalize 2376 // it. 2377 bool HighBitSet = false; // Can we transform this if the high bit is set? 2378 2379 switch (LHS->getOpcode()) { 2380 default: return SDValue(); 2381 case ISD::OR: 2382 case ISD::XOR: 2383 HighBitSet = false; // We can only transform sra if the high bit is clear. 2384 break; 2385 case ISD::AND: 2386 HighBitSet = true; // We can only transform sra if the high bit is set. 2387 break; 2388 case ISD::ADD: 2389 if (N->getOpcode() != ISD::SHL) 2390 return SDValue(); // only shl(add) not sr[al](add). 2391 HighBitSet = false; // We can only transform sra if the high bit is clear. 2392 break; 2393 } 2394 2395 // We require the RHS of the binop to be a constant as well. 2396 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2397 if (!BinOpCst) return SDValue(); 2398 2399 2400 // FIXME: disable this for unless the input to the binop is a shift by a 2401 // constant. If it is not a shift, it pessimizes some common cases like: 2402 // 2403 //void foo(int *X, int i) { X[i & 1235] = 1; } 2404 //int bar(int *X, int i) { return X[i & 255]; } 2405 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2406 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2407 BinOpLHSVal->getOpcode() != ISD::SRA && 2408 BinOpLHSVal->getOpcode() != ISD::SRL) || 2409 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2410 return SDValue(); 2411 2412 MVT VT = N->getValueType(0); 2413 2414 // If this is a signed shift right, and the high bit is modified 2415 // by the logical operation, do not perform the transformation. 2416 // The highBitSet boolean indicates the value of the high bit of 2417 // the constant which would cause it to be modified for this 2418 // operation. 2419 if (N->getOpcode() == ISD::SRA) { 2420 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2421 if (BinOpRHSSignSet != HighBitSet) 2422 return SDValue(); 2423 } 2424 2425 // Fold the constants, shifting the binop RHS by the shift amount. 2426 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2427 LHS->getOperand(1), N->getOperand(1)); 2428 2429 // Create the new shift. 2430 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2431 N->getOperand(1)); 2432 2433 // Create the new binop. 2434 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2435} 2436 2437 2438SDValue DAGCombiner::visitSHL(SDNode *N) { 2439 SDValue N0 = N->getOperand(0); 2440 SDValue N1 = N->getOperand(1); 2441 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2442 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2443 MVT VT = N0.getValueType(); 2444 unsigned OpSizeInBits = VT.getSizeInBits(); 2445 2446 // fold (shl c1, c2) -> c1<<c2 2447 if (N0C && N1C) 2448 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2449 // fold (shl 0, x) -> 0 2450 if (N0C && N0C->isNullValue()) 2451 return N0; 2452 // fold (shl x, c >= size(x)) -> undef 2453 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2454 return DAG.getNode(ISD::UNDEF, VT); 2455 // fold (shl x, 0) -> x 2456 if (N1C && N1C->isNullValue()) 2457 return N0; 2458 // if (shl x, c) is known to be zero, return 0 2459 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2460 APInt::getAllOnesValue(VT.getSizeInBits()))) 2461 return DAG.getConstant(0, VT); 2462 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2463 // iff (trunc c) == c 2464 if (N1.getOpcode() == ISD::TRUNCATE && 2465 N1.getOperand(0).getOpcode() == ISD::AND && 2466 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2467 SDValue N101 = N1.getOperand(0).getOperand(1); 2468 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2469 MVT TruncVT = N1.getValueType(); 2470 SDValue N100 = N1.getOperand(0).getOperand(0); 2471 uint64_t TruncC = TruncVT.getIntegerVTBitMask() & 2472 N101C->getZExtValue(); 2473 return DAG.getNode(ISD::SHL, VT, N0, 2474 DAG.getNode(ISD::AND, TruncVT, 2475 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2476 DAG.getConstant(TruncC, TruncVT))); 2477 } 2478 } 2479 2480 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2481 return SDValue(N, 0); 2482 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2483 if (N1C && N0.getOpcode() == ISD::SHL && 2484 N0.getOperand(1).getOpcode() == ISD::Constant) { 2485 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2486 uint64_t c2 = N1C->getZExtValue(); 2487 if (c1 + c2 > OpSizeInBits) 2488 return DAG.getConstant(0, VT); 2489 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2490 DAG.getConstant(c1 + c2, N1.getValueType())); 2491 } 2492 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2493 // (srl (and x, -1 << c1), c1-c2) 2494 if (N1C && N0.getOpcode() == ISD::SRL && 2495 N0.getOperand(1).getOpcode() == ISD::Constant) { 2496 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2497 uint64_t c2 = N1C->getZExtValue(); 2498 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2499 DAG.getConstant(~0ULL << c1, VT)); 2500 if (c2 > c1) 2501 return DAG.getNode(ISD::SHL, VT, Mask, 2502 DAG.getConstant(c2-c1, N1.getValueType())); 2503 else 2504 return DAG.getNode(ISD::SRL, VT, Mask, 2505 DAG.getConstant(c1-c2, N1.getValueType())); 2506 } 2507 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2508 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2509 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2510 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2511 2512 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2513} 2514 2515SDValue DAGCombiner::visitSRA(SDNode *N) { 2516 SDValue N0 = N->getOperand(0); 2517 SDValue N1 = N->getOperand(1); 2518 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2519 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2520 MVT VT = N0.getValueType(); 2521 2522 // fold (sra c1, c2) -> c1>>c2 2523 if (N0C && N1C) 2524 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2525 // fold (sra 0, x) -> 0 2526 if (N0C && N0C->isNullValue()) 2527 return N0; 2528 // fold (sra -1, x) -> -1 2529 if (N0C && N0C->isAllOnesValue()) 2530 return N0; 2531 // fold (sra x, c >= size(x)) -> undef 2532 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2533 return DAG.getNode(ISD::UNDEF, VT); 2534 // fold (sra x, 0) -> x 2535 if (N1C && N1C->isNullValue()) 2536 return N0; 2537 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2538 // sext_inreg. 2539 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2540 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2541 MVT EVT = MVT::getIntegerVT(LowBits); 2542 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2543 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2544 DAG.getValueType(EVT)); 2545 } 2546 2547 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2548 if (N1C && N0.getOpcode() == ISD::SRA) { 2549 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2550 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2551 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2552 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2553 DAG.getConstant(Sum, N1C->getValueType(0))); 2554 } 2555 } 2556 2557 // fold sra (shl X, m), result_size - n 2558 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2559 // result_size - n != m. 2560 // If truncate is free for the target sext(shl) is likely to result in better 2561 // code. 2562 if (N0.getOpcode() == ISD::SHL) { 2563 // Get the two constanst of the shifts, CN0 = m, CN = n. 2564 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2565 if (N01C && N1C) { 2566 // Determine what the truncate's result bitsize and type would be. 2567 unsigned VTValSize = VT.getSizeInBits(); 2568 MVT TruncVT = 2569 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2570 // Determine the residual right-shift amount. 2571 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2572 2573 // If the shift is not a no-op (in which case this should be just a sign 2574 // extend already), the truncated to type is legal, sign_extend is legal 2575 // on that type, and the the truncate to that type is both legal and free, 2576 // perform the transform. 2577 if (ShiftAmt && 2578 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2579 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2580 TLI.isTruncateFree(VT, TruncVT)) { 2581 2582 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2583 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2584 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2585 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2586 } 2587 } 2588 } 2589 2590 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2591 // iff (trunc c) == c 2592 if (N1.getOpcode() == ISD::TRUNCATE && 2593 N1.getOperand(0).getOpcode() == ISD::AND && 2594 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2595 SDValue N101 = N1.getOperand(0).getOperand(1); 2596 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2597 MVT TruncVT = N1.getValueType(); 2598 SDValue N100 = N1.getOperand(0).getOperand(0); 2599 uint64_t TruncC = TruncVT.getIntegerVTBitMask() & 2600 N101C->getZExtValue(); 2601 return DAG.getNode(ISD::SRA, VT, N0, 2602 DAG.getNode(ISD::AND, TruncVT, 2603 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2604 DAG.getConstant(TruncC, TruncVT))); 2605 } 2606 } 2607 2608 // Simplify, based on bits shifted out of the LHS. 2609 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2610 return SDValue(N, 0); 2611 2612 2613 // If the sign bit is known to be zero, switch this to a SRL. 2614 if (DAG.SignBitIsZero(N0)) 2615 return DAG.getNode(ISD::SRL, VT, N0, N1); 2616 2617 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2618} 2619 2620SDValue DAGCombiner::visitSRL(SDNode *N) { 2621 SDValue N0 = N->getOperand(0); 2622 SDValue N1 = N->getOperand(1); 2623 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2624 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2625 MVT VT = N0.getValueType(); 2626 unsigned OpSizeInBits = VT.getSizeInBits(); 2627 2628 // fold (srl c1, c2) -> c1 >>u c2 2629 if (N0C && N1C) 2630 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2631 // fold (srl 0, x) -> 0 2632 if (N0C && N0C->isNullValue()) 2633 return N0; 2634 // fold (srl x, c >= size(x)) -> undef 2635 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2636 return DAG.getNode(ISD::UNDEF, VT); 2637 // fold (srl x, 0) -> x 2638 if (N1C && N1C->isNullValue()) 2639 return N0; 2640 // if (srl x, c) is known to be zero, return 0 2641 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2642 APInt::getAllOnesValue(OpSizeInBits))) 2643 return DAG.getConstant(0, VT); 2644 2645 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2646 if (N1C && N0.getOpcode() == ISD::SRL && 2647 N0.getOperand(1).getOpcode() == ISD::Constant) { 2648 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2649 uint64_t c2 = N1C->getZExtValue(); 2650 if (c1 + c2 > OpSizeInBits) 2651 return DAG.getConstant(0, VT); 2652 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2653 DAG.getConstant(c1 + c2, N1.getValueType())); 2654 } 2655 2656 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2657 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2658 // Shifting in all undef bits? 2659 MVT SmallVT = N0.getOperand(0).getValueType(); 2660 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2661 return DAG.getNode(ISD::UNDEF, VT); 2662 2663 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2664 AddToWorkList(SmallShift.getNode()); 2665 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2666 } 2667 2668 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2669 // bit, which is unmodified by sra. 2670 if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { 2671 if (N0.getOpcode() == ISD::SRA) 2672 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2673 } 2674 2675 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2676 if (N1C && N0.getOpcode() == ISD::CTLZ && 2677 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2678 APInt KnownZero, KnownOne; 2679 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2680 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2681 2682 // If any of the input bits are KnownOne, then the input couldn't be all 2683 // zeros, thus the result of the srl will always be zero. 2684 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2685 2686 // If all of the bits input the to ctlz node are known to be zero, then 2687 // the result of the ctlz is "32" and the result of the shift is one. 2688 APInt UnknownBits = ~KnownZero & Mask; 2689 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2690 2691 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2692 if ((UnknownBits & (UnknownBits-1)) == 0) { 2693 // Okay, we know that only that the single bit specified by UnknownBits 2694 // could be set on input to the CTLZ node. If this bit is set, the SRL 2695 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2696 // to an SRL,XOR pair, which is likely to simplify more. 2697 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2698 SDValue Op = N0.getOperand(0); 2699 if (ShAmt) { 2700 Op = DAG.getNode(ISD::SRL, VT, Op, 2701 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2702 AddToWorkList(Op.getNode()); 2703 } 2704 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2705 } 2706 } 2707 2708 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2709 // iff (trunc c) == c 2710 if (N1.getOpcode() == ISD::TRUNCATE && 2711 N1.getOperand(0).getOpcode() == ISD::AND && 2712 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2713 SDValue N101 = N1.getOperand(0).getOperand(1); 2714 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2715 MVT TruncVT = N1.getValueType(); 2716 SDValue N100 = N1.getOperand(0).getOperand(0); 2717 uint64_t TruncC = TruncVT.getIntegerVTBitMask() & 2718 N101C->getZExtValue(); 2719 return DAG.getNode(ISD::SRL, VT, N0, 2720 DAG.getNode(ISD::AND, TruncVT, 2721 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2722 DAG.getConstant(TruncC, TruncVT))); 2723 } 2724 } 2725 2726 // fold operands of srl based on knowledge that the low bits are not 2727 // demanded. 2728 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2729 return SDValue(N, 0); 2730 2731 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2732} 2733 2734SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2735 SDValue N0 = N->getOperand(0); 2736 MVT VT = N->getValueType(0); 2737 2738 // fold (ctlz c1) -> c2 2739 if (isa<ConstantSDNode>(N0)) 2740 return DAG.getNode(ISD::CTLZ, VT, N0); 2741 return SDValue(); 2742} 2743 2744SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2745 SDValue N0 = N->getOperand(0); 2746 MVT VT = N->getValueType(0); 2747 2748 // fold (cttz c1) -> c2 2749 if (isa<ConstantSDNode>(N0)) 2750 return DAG.getNode(ISD::CTTZ, VT, N0); 2751 return SDValue(); 2752} 2753 2754SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2755 SDValue N0 = N->getOperand(0); 2756 MVT VT = N->getValueType(0); 2757 2758 // fold (ctpop c1) -> c2 2759 if (isa<ConstantSDNode>(N0)) 2760 return DAG.getNode(ISD::CTPOP, VT, N0); 2761 return SDValue(); 2762} 2763 2764SDValue DAGCombiner::visitSELECT(SDNode *N) { 2765 SDValue N0 = N->getOperand(0); 2766 SDValue N1 = N->getOperand(1); 2767 SDValue N2 = N->getOperand(2); 2768 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2769 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2770 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2771 MVT VT = N->getValueType(0); 2772 MVT VT0 = N0.getValueType(); 2773 2774 // fold select C, X, X -> X 2775 if (N1 == N2) 2776 return N1; 2777 // fold select true, X, Y -> X 2778 if (N0C && !N0C->isNullValue()) 2779 return N1; 2780 // fold select false, X, Y -> Y 2781 if (N0C && N0C->isNullValue()) 2782 return N2; 2783 // fold select C, 1, X -> C | X 2784 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2785 return DAG.getNode(ISD::OR, VT, N0, N2); 2786 // fold select C, 0, 1 -> C ^ 1 2787 if (VT.isInteger() && 2788 (VT0 == MVT::i1 || 2789 (VT0.isInteger() && 2790 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2791 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2792 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2793 if (VT == VT0) 2794 return XORNode; 2795 AddToWorkList(XORNode.getNode()); 2796 if (VT.bitsGT(VT0)) 2797 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2798 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2799 } 2800 // fold select C, 0, X -> ~C & X 2801 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2802 SDValue NOTNode = DAG.getNOT(N0, VT); 2803 AddToWorkList(NOTNode.getNode()); 2804 return DAG.getNode(ISD::AND, VT, NOTNode, N2); 2805 } 2806 // fold select C, X, 1 -> ~C | X 2807 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2808 SDValue NOTNode = DAG.getNOT(N0, VT); 2809 AddToWorkList(NOTNode.getNode()); 2810 return DAG.getNode(ISD::OR, VT, NOTNode, N1); 2811 } 2812 // fold select C, X, 0 -> C & X 2813 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2814 return DAG.getNode(ISD::AND, VT, N0, N1); 2815 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2816 if (VT == MVT::i1 && N0 == N1) 2817 return DAG.getNode(ISD::OR, VT, N0, N2); 2818 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2819 if (VT == MVT::i1 && N0 == N2) 2820 return DAG.getNode(ISD::AND, VT, N0, N1); 2821 2822 // If we can fold this based on the true/false value, do so. 2823 if (SimplifySelectOps(N, N1, N2)) 2824 return SDValue(N, 0); // Don't revisit N. 2825 2826 // fold selects based on a setcc into other things, such as min/max/abs 2827 if (N0.getOpcode() == ISD::SETCC) { 2828 // FIXME: 2829 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2830 // having to say they don't support SELECT_CC on every type the DAG knows 2831 // about, since there is no way to mark an opcode illegal at all value types 2832 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2833 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2834 N1, N2, N0.getOperand(2)); 2835 else 2836 return SimplifySelect(N0, N1, N2); 2837 } 2838 return SDValue(); 2839} 2840 2841SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2842 SDValue N0 = N->getOperand(0); 2843 SDValue N1 = N->getOperand(1); 2844 SDValue N2 = N->getOperand(2); 2845 SDValue N3 = N->getOperand(3); 2846 SDValue N4 = N->getOperand(4); 2847 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2848 2849 // fold select_cc lhs, rhs, x, x, cc -> x 2850 if (N2 == N3) 2851 return N2; 2852 2853 // Determine if the condition we're dealing with is constant 2854 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2855 N0, N1, CC, false); 2856 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2857 2858 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2859 if (!SCCC->isNullValue()) 2860 return N2; // cond always true -> true val 2861 else 2862 return N3; // cond always false -> false val 2863 } 2864 2865 // Fold to a simpler select_cc 2866 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2867 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2868 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2869 SCC.getOperand(2)); 2870 2871 // If we can fold this based on the true/false value, do so. 2872 if (SimplifySelectOps(N, N2, N3)) 2873 return SDValue(N, 0); // Don't revisit N. 2874 2875 // fold select_cc into other things, such as min/max/abs 2876 return SimplifySelectCC(N0, N1, N2, N3, CC); 2877} 2878 2879SDValue DAGCombiner::visitSETCC(SDNode *N) { 2880 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2881 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2882} 2883 2884// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2885// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2886// transformation. Returns true if extension are possible and the above 2887// mentioned transformation is profitable. 2888static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2889 unsigned ExtOpc, 2890 SmallVector<SDNode*, 4> &ExtendNodes, 2891 const TargetLowering &TLI) { 2892 bool HasCopyToRegUses = false; 2893 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2894 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2895 UE = N0.getNode()->use_end(); 2896 UI != UE; ++UI) { 2897 SDNode *User = *UI; 2898 if (User == N) 2899 continue; 2900 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2901 if (User->getOpcode() == ISD::SETCC) { 2902 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2903 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2904 // Sign bits will be lost after a zext. 2905 return false; 2906 bool Add = false; 2907 for (unsigned i = 0; i != 2; ++i) { 2908 SDValue UseOp = User->getOperand(i); 2909 if (UseOp == N0) 2910 continue; 2911 if (!isa<ConstantSDNode>(UseOp)) 2912 return false; 2913 Add = true; 2914 } 2915 if (Add) 2916 ExtendNodes.push_back(User); 2917 } else { 2918 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2919 SDValue UseOp = User->getOperand(i); 2920 if (UseOp == N0) { 2921 // If truncate from extended type to original load type is free 2922 // on this target, then it's ok to extend a CopyToReg. 2923 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2924 HasCopyToRegUses = true; 2925 else 2926 return false; 2927 } 2928 } 2929 } 2930 } 2931 2932 if (HasCopyToRegUses) { 2933 bool BothLiveOut = false; 2934 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2935 UI != UE; ++UI) { 2936 SDNode *User = *UI; 2937 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2938 SDValue UseOp = User->getOperand(i); 2939 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2940 BothLiveOut = true; 2941 break; 2942 } 2943 } 2944 } 2945 if (BothLiveOut) 2946 // Both unextended and extended values are live out. There had better be 2947 // good a reason for the transformation. 2948 return ExtendNodes.size(); 2949 } 2950 return true; 2951} 2952 2953SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2954 SDValue N0 = N->getOperand(0); 2955 MVT VT = N->getValueType(0); 2956 2957 // fold (sext c1) -> c1 2958 if (isa<ConstantSDNode>(N0)) 2959 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2960 2961 // fold (sext (sext x)) -> (sext x) 2962 // fold (sext (aext x)) -> (sext x) 2963 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2964 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2965 2966 if (N0.getOpcode() == ISD::TRUNCATE) { 2967 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2968 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2969 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2970 if (NarrowLoad.getNode()) { 2971 if (NarrowLoad.getNode() != N0.getNode()) 2972 CombineTo(N0.getNode(), NarrowLoad); 2973 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2974 } 2975 2976 // See if the value being truncated is already sign extended. If so, just 2977 // eliminate the trunc/sext pair. 2978 SDValue Op = N0.getOperand(0); 2979 unsigned OpBits = Op.getValueType().getSizeInBits(); 2980 unsigned MidBits = N0.getValueType().getSizeInBits(); 2981 unsigned DestBits = VT.getSizeInBits(); 2982 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2983 2984 if (OpBits == DestBits) { 2985 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2986 // bits, it is already ready. 2987 if (NumSignBits > DestBits-MidBits) 2988 return Op; 2989 } else if (OpBits < DestBits) { 2990 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2991 // bits, just sext from i32. 2992 if (NumSignBits > OpBits-MidBits) 2993 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2994 } else { 2995 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2996 // bits, just truncate to i32. 2997 if (NumSignBits > OpBits-MidBits) 2998 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2999 } 3000 3001 // fold (sext (truncate x)) -> (sextinreg x). 3002 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3003 N0.getValueType())) { 3004 if (Op.getValueType().bitsLT(VT)) 3005 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 3006 else if (Op.getValueType().bitsGT(VT)) 3007 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3008 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 3009 DAG.getValueType(N0.getValueType())); 3010 } 3011 } 3012 3013 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3014 if (ISD::isNON_EXTLoad(N0.getNode()) && 3015 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3016 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3017 bool DoXform = true; 3018 SmallVector<SDNode*, 4> SetCCs; 3019 if (!N0.hasOneUse()) 3020 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3021 if (DoXform) { 3022 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3023 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3024 LN0->getBasePtr(), LN0->getSrcValue(), 3025 LN0->getSrcValueOffset(), 3026 N0.getValueType(), 3027 LN0->isVolatile(), LN0->getAlignment()); 3028 CombineTo(N, ExtLoad); 3029 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3030 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3031 // Extend SetCC uses if necessary. 3032 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3033 SDNode *SetCC = SetCCs[i]; 3034 SmallVector<SDValue, 4> Ops; 3035 for (unsigned j = 0; j != 2; ++j) { 3036 SDValue SOp = SetCC->getOperand(j); 3037 if (SOp == Trunc) 3038 Ops.push_back(ExtLoad); 3039 else 3040 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 3041 } 3042 Ops.push_back(SetCC->getOperand(2)); 3043 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3044 &Ops[0], Ops.size())); 3045 } 3046 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3047 } 3048 } 3049 3050 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3051 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3052 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3053 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3054 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3055 MVT EVT = LN0->getMemoryVT(); 3056 if ((!LegalOperations && !LN0->isVolatile()) || 3057 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3058 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3059 LN0->getBasePtr(), LN0->getSrcValue(), 3060 LN0->getSrcValueOffset(), EVT, 3061 LN0->isVolatile(), LN0->getAlignment()); 3062 CombineTo(N, ExtLoad); 3063 CombineTo(N0.getNode(), 3064 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3065 ExtLoad.getValue(1)); 3066 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3067 } 3068 } 3069 3070 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 3071 if (N0.getOpcode() == ISD::SETCC) { 3072 SDValue SCC = 3073 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3074 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3075 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3076 if (SCC.getNode()) return SCC; 3077 } 3078 3079 // fold (sext x) -> (zext x) if the sign bit is known zero. 3080 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3081 DAG.SignBitIsZero(N0)) 3082 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3083 3084 return SDValue(); 3085} 3086 3087SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3088 SDValue N0 = N->getOperand(0); 3089 MVT VT = N->getValueType(0); 3090 3091 // fold (zext c1) -> c1 3092 if (isa<ConstantSDNode>(N0)) 3093 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3094 // fold (zext (zext x)) -> (zext x) 3095 // fold (zext (aext x)) -> (zext x) 3096 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3097 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 3098 3099 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3100 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3101 if (N0.getOpcode() == ISD::TRUNCATE) { 3102 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3103 if (NarrowLoad.getNode()) { 3104 if (NarrowLoad.getNode() != N0.getNode()) 3105 CombineTo(N0.getNode(), NarrowLoad); 3106 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 3107 } 3108 } 3109 3110 // fold (zext (truncate x)) -> (and x, mask) 3111 if (N0.getOpcode() == ISD::TRUNCATE && 3112 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3113 SDValue Op = N0.getOperand(0); 3114 if (Op.getValueType().bitsLT(VT)) { 3115 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 3116 } else if (Op.getValueType().bitsGT(VT)) { 3117 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3118 } 3119 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 3120 } 3121 3122 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3123 if (N0.getOpcode() == ISD::AND && 3124 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3125 N0.getOperand(1).getOpcode() == ISD::Constant) { 3126 SDValue X = N0.getOperand(0).getOperand(0); 3127 if (X.getValueType().bitsLT(VT)) { 3128 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3129 } else if (X.getValueType().bitsGT(VT)) { 3130 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3131 } 3132 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3133 Mask.zext(VT.getSizeInBits()); 3134 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3135 } 3136 3137 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3138 if (ISD::isNON_EXTLoad(N0.getNode()) && 3139 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3140 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3141 bool DoXform = true; 3142 SmallVector<SDNode*, 4> SetCCs; 3143 if (!N0.hasOneUse()) 3144 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3145 if (DoXform) { 3146 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3147 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3148 LN0->getBasePtr(), LN0->getSrcValue(), 3149 LN0->getSrcValueOffset(), 3150 N0.getValueType(), 3151 LN0->isVolatile(), LN0->getAlignment()); 3152 CombineTo(N, ExtLoad); 3153 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3154 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3155 // Extend SetCC uses if necessary. 3156 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3157 SDNode *SetCC = SetCCs[i]; 3158 SmallVector<SDValue, 4> Ops; 3159 for (unsigned j = 0; j != 2; ++j) { 3160 SDValue SOp = SetCC->getOperand(j); 3161 if (SOp == Trunc) 3162 Ops.push_back(ExtLoad); 3163 else 3164 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3165 } 3166 Ops.push_back(SetCC->getOperand(2)); 3167 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3168 &Ops[0], Ops.size())); 3169 } 3170 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3171 } 3172 } 3173 3174 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3175 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3176 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3177 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3178 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3179 MVT EVT = LN0->getMemoryVT(); 3180 if ((!LegalOperations && !LN0->isVolatile()) || 3181 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3182 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3183 LN0->getBasePtr(), LN0->getSrcValue(), 3184 LN0->getSrcValueOffset(), EVT, 3185 LN0->isVolatile(), LN0->getAlignment()); 3186 CombineTo(N, ExtLoad); 3187 CombineTo(N0.getNode(), 3188 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3189 ExtLoad.getValue(1)); 3190 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3191 } 3192 } 3193 3194 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3195 if (N0.getOpcode() == ISD::SETCC) { 3196 SDValue SCC = 3197 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3198 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3199 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3200 if (SCC.getNode()) return SCC; 3201 } 3202 3203 return SDValue(); 3204} 3205 3206SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3207 SDValue N0 = N->getOperand(0); 3208 MVT VT = N->getValueType(0); 3209 3210 // fold (aext c1) -> c1 3211 if (isa<ConstantSDNode>(N0)) 3212 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3213 // fold (aext (aext x)) -> (aext x) 3214 // fold (aext (zext x)) -> (zext x) 3215 // fold (aext (sext x)) -> (sext x) 3216 if (N0.getOpcode() == ISD::ANY_EXTEND || 3217 N0.getOpcode() == ISD::ZERO_EXTEND || 3218 N0.getOpcode() == ISD::SIGN_EXTEND) 3219 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3220 3221 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3222 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3223 if (N0.getOpcode() == ISD::TRUNCATE) { 3224 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3225 if (NarrowLoad.getNode()) { 3226 if (NarrowLoad.getNode() != N0.getNode()) 3227 CombineTo(N0.getNode(), NarrowLoad); 3228 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3229 } 3230 } 3231 3232 // fold (aext (truncate x)) 3233 if (N0.getOpcode() == ISD::TRUNCATE) { 3234 SDValue TruncOp = N0.getOperand(0); 3235 if (TruncOp.getValueType() == VT) 3236 return TruncOp; // x iff x size == zext size. 3237 if (TruncOp.getValueType().bitsGT(VT)) 3238 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3239 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3240 } 3241 3242 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3243 if (N0.getOpcode() == ISD::AND && 3244 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3245 N0.getOperand(1).getOpcode() == ISD::Constant) { 3246 SDValue X = N0.getOperand(0).getOperand(0); 3247 if (X.getValueType().bitsLT(VT)) { 3248 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3249 } else if (X.getValueType().bitsGT(VT)) { 3250 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3251 } 3252 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3253 Mask.zext(VT.getSizeInBits()); 3254 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3255 } 3256 3257 // fold (aext (load x)) -> (aext (truncate (extload x))) 3258 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3259 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3260 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3261 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3262 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3263 LN0->getBasePtr(), LN0->getSrcValue(), 3264 LN0->getSrcValueOffset(), 3265 N0.getValueType(), 3266 LN0->isVolatile(), LN0->getAlignment()); 3267 CombineTo(N, ExtLoad); 3268 // Redirect any chain users to the new load. 3269 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3270 SDValue(ExtLoad.getNode(), 1)); 3271 // If any node needs the original loaded value, recompute it. 3272 if (!LN0->use_empty()) 3273 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3274 ExtLoad.getValue(1)); 3275 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3276 } 3277 3278 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3279 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3280 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3281 if (N0.getOpcode() == ISD::LOAD && 3282 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3283 N0.hasOneUse()) { 3284 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3285 MVT EVT = LN0->getMemoryVT(); 3286 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3287 LN0->getChain(), LN0->getBasePtr(), 3288 LN0->getSrcValue(), 3289 LN0->getSrcValueOffset(), EVT, 3290 LN0->isVolatile(), LN0->getAlignment()); 3291 CombineTo(N, ExtLoad); 3292 CombineTo(N0.getNode(), 3293 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3294 ExtLoad.getValue(1)); 3295 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3296 } 3297 3298 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3299 if (N0.getOpcode() == ISD::SETCC) { 3300 SDValue SCC = 3301 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3302 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3303 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3304 if (SCC.getNode()) 3305 return SCC; 3306 } 3307 3308 return SDValue(); 3309} 3310 3311/// GetDemandedBits - See if the specified operand can be simplified with the 3312/// knowledge that only the bits specified by Mask are used. If so, return the 3313/// simpler operand, otherwise return a null SDValue. 3314SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3315 switch (V.getOpcode()) { 3316 default: break; 3317 case ISD::OR: 3318 case ISD::XOR: 3319 // If the LHS or RHS don't contribute bits to the or, drop them. 3320 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3321 return V.getOperand(1); 3322 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3323 return V.getOperand(0); 3324 break; 3325 case ISD::SRL: 3326 // Only look at single-use SRLs. 3327 if (!V.getNode()->hasOneUse()) 3328 break; 3329 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3330 // See if we can recursively simplify the LHS. 3331 unsigned Amt = RHSC->getZExtValue(); 3332 // Watch out for shift count overflow though. 3333 if (Amt >= Mask.getBitWidth()) break; 3334 APInt NewMask = Mask << Amt; 3335 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3336 if (SimplifyLHS.getNode()) { 3337 return DAG.getNode(ISD::SRL, V.getValueType(), 3338 SimplifyLHS, V.getOperand(1)); 3339 } 3340 } 3341 } 3342 return SDValue(); 3343} 3344 3345/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3346/// bits and then truncated to a narrower type and where N is a multiple 3347/// of number of bits of the narrower type, transform it to a narrower load 3348/// from address + N / num of bits of new type. If the result is to be 3349/// extended, also fold the extension to form a extending load. 3350SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3351 unsigned Opc = N->getOpcode(); 3352 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3353 SDValue N0 = N->getOperand(0); 3354 MVT VT = N->getValueType(0); 3355 MVT EVT = VT; 3356 3357 // This transformation isn't valid for vector loads. 3358 if (VT.isVector()) 3359 return SDValue(); 3360 3361 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3362 // extended to VT. 3363 if (Opc == ISD::SIGN_EXTEND_INREG) { 3364 ExtType = ISD::SEXTLOAD; 3365 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3366 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3367 return SDValue(); 3368 } 3369 3370 unsigned EVTBits = EVT.getSizeInBits(); 3371 unsigned ShAmt = 0; 3372 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3373 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3374 ShAmt = N01->getZExtValue(); 3375 // Is the shift amount a multiple of size of VT? 3376 if ((ShAmt & (EVTBits-1)) == 0) { 3377 N0 = N0.getOperand(0); 3378 if (N0.getValueType().getSizeInBits() <= EVTBits) 3379 return SDValue(); 3380 } 3381 } 3382 } 3383 3384 // Do not generate loads of non-round integer types since these can 3385 // be expensive (and would be wrong if the type is not byte sized). 3386 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3387 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3388 // Do not change the width of a volatile load. 3389 !cast<LoadSDNode>(N0)->isVolatile()) { 3390 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3391 MVT PtrType = N0.getOperand(1).getValueType(); 3392 // For big endian targets, we need to adjust the offset to the pointer to 3393 // load the correct bytes. 3394 if (TLI.isBigEndian()) { 3395 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3396 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3397 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3398 } 3399 uint64_t PtrOff = ShAmt / 8; 3400 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3401 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3402 DAG.getConstant(PtrOff, PtrType)); 3403 AddToWorkList(NewPtr.getNode()); 3404 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3405 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3406 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3407 LN0->isVolatile(), NewAlign) 3408 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3409 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3410 EVT, LN0->isVolatile(), NewAlign); 3411 // Replace the old load's chain with the new load's chain. 3412 WorkListRemover DeadNodes(*this); 3413 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3414 &DeadNodes); 3415 // Return the new loaded value. 3416 return Load; 3417 } 3418 3419 return SDValue(); 3420} 3421 3422 3423SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3424 SDValue N0 = N->getOperand(0); 3425 SDValue N1 = N->getOperand(1); 3426 MVT VT = N->getValueType(0); 3427 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3428 unsigned VTBits = VT.getSizeInBits(); 3429 unsigned EVTBits = EVT.getSizeInBits(); 3430 3431 // fold (sext_in_reg c1) -> c1 3432 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3433 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3434 3435 // If the input is already sign extended, just drop the extension. 3436 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3437 return N0; 3438 3439 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3440 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3441 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3442 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3443 } 3444 3445 // fold (sext_in_reg (sext x)) -> (sext x) 3446 // fold (sext_in_reg (aext x)) -> (sext x) 3447 // if x is small enough. 3448 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3449 SDValue N00 = N0.getOperand(0); 3450 if (N00.getValueType().getSizeInBits() < EVTBits) 3451 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3452 } 3453 3454 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3455 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3456 return DAG.getZeroExtendInReg(N0, EVT); 3457 3458 // fold operands of sext_in_reg based on knowledge that the top bits are not 3459 // demanded. 3460 if (SimplifyDemandedBits(SDValue(N, 0))) 3461 return SDValue(N, 0); 3462 3463 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3464 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3465 SDValue NarrowLoad = ReduceLoadWidth(N); 3466 if (NarrowLoad.getNode()) 3467 return NarrowLoad; 3468 3469 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3470 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3471 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3472 if (N0.getOpcode() == ISD::SRL) { 3473 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3474 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3475 // We can turn this into an SRA iff the input to the SRL is already sign 3476 // extended enough. 3477 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3478 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3479 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3480 } 3481 } 3482 3483 // fold (sext_inreg (extload x)) -> (sextload x) 3484 if (ISD::isEXTLoad(N0.getNode()) && 3485 ISD::isUNINDEXEDLoad(N0.getNode()) && 3486 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3487 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3488 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3489 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3490 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3491 LN0->getBasePtr(), LN0->getSrcValue(), 3492 LN0->getSrcValueOffset(), EVT, 3493 LN0->isVolatile(), LN0->getAlignment()); 3494 CombineTo(N, ExtLoad); 3495 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3496 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3497 } 3498 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3499 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3500 N0.hasOneUse() && 3501 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3502 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3503 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3504 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3505 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3506 LN0->getBasePtr(), LN0->getSrcValue(), 3507 LN0->getSrcValueOffset(), EVT, 3508 LN0->isVolatile(), LN0->getAlignment()); 3509 CombineTo(N, ExtLoad); 3510 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3511 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3512 } 3513 return SDValue(); 3514} 3515 3516SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3517 SDValue N0 = N->getOperand(0); 3518 MVT VT = N->getValueType(0); 3519 3520 // noop truncate 3521 if (N0.getValueType() == N->getValueType(0)) 3522 return N0; 3523 // fold (truncate c1) -> c1 3524 if (isa<ConstantSDNode>(N0)) 3525 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3526 // fold (truncate (truncate x)) -> (truncate x) 3527 if (N0.getOpcode() == ISD::TRUNCATE) 3528 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3529 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3530 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3531 N0.getOpcode() == ISD::ANY_EXTEND) { 3532 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3533 // if the source is smaller than the dest, we still need an extend 3534 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3535 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3536 // if the source is larger than the dest, than we just need the truncate 3537 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3538 else 3539 // if the source and dest are the same type, we can drop both the extend 3540 // and the truncate 3541 return N0.getOperand(0); 3542 } 3543 3544 // See if we can simplify the input to this truncate through knowledge that 3545 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3546 // -> trunc y 3547 SDValue Shorter = 3548 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3549 VT.getSizeInBits())); 3550 if (Shorter.getNode()) 3551 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3552 3553 // fold (truncate (load x)) -> (smaller load x) 3554 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3555 return ReduceLoadWidth(N); 3556} 3557 3558static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3559 SDValue Elt = N->getOperand(i); 3560 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3561 return Elt.getNode(); 3562 return Elt.getOperand(Elt.getResNo()).getNode(); 3563} 3564 3565/// CombineConsecutiveLoads - build_pair (load, load) -> load 3566/// if load locations are consecutive. 3567SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3568 assert(N->getOpcode() == ISD::BUILD_PAIR); 3569 3570 SDNode *LD1 = getBuildPairElt(N, 0); 3571 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3572 return SDValue(); 3573 MVT LD1VT = LD1->getValueType(0); 3574 SDNode *LD2 = getBuildPairElt(N, 1); 3575 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3576 if (ISD::isNON_EXTLoad(LD2) && 3577 LD2->hasOneUse() && 3578 // If both are volatile this would reduce the number of volatile loads. 3579 // If one is volatile it might be ok, but play conservative and bail out. 3580 !cast<LoadSDNode>(LD1)->isVolatile() && 3581 !cast<LoadSDNode>(LD2)->isVolatile() && 3582 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3583 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3584 unsigned Align = LD->getAlignment(); 3585 unsigned NewAlign = TLI.getTargetData()-> 3586 getABITypeAlignment(VT.getTypeForMVT()); 3587 if (NewAlign <= Align && 3588 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3589 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3590 LD->getSrcValue(), LD->getSrcValueOffset(), 3591 false, Align); 3592 } 3593 return SDValue(); 3594} 3595 3596SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3597 SDValue N0 = N->getOperand(0); 3598 MVT VT = N->getValueType(0); 3599 3600 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3601 // Only do this before legalize, since afterward the target may be depending 3602 // on the bitconvert. 3603 // First check to see if this is all constant. 3604 if (!LegalTypes && 3605 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3606 VT.isVector()) { 3607 bool isSimple = true; 3608 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3609 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3610 N0.getOperand(i).getOpcode() != ISD::Constant && 3611 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3612 isSimple = false; 3613 break; 3614 } 3615 3616 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3617 assert(!DestEltVT.isVector() && 3618 "Element type of vector ValueType must not be vector!"); 3619 if (isSimple) { 3620 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3621 } 3622 } 3623 3624 // If the input is a constant, let getNode fold it. 3625 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3626 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3627 if (Res.getNode() != N) return Res; 3628 } 3629 3630 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3631 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3632 3633 // fold (conv (load x)) -> (load (conv*)x) 3634 // If the resultant load doesn't need a higher alignment than the original! 3635 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3636 // Do not change the width of a volatile load. 3637 !cast<LoadSDNode>(N0)->isVolatile() && 3638 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3639 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3640 unsigned Align = TLI.getTargetData()-> 3641 getABITypeAlignment(VT.getTypeForMVT()); 3642 unsigned OrigAlign = LN0->getAlignment(); 3643 if (Align <= OrigAlign) { 3644 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3645 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3646 LN0->isVolatile(), OrigAlign); 3647 AddToWorkList(N); 3648 CombineTo(N0.getNode(), 3649 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3650 Load.getValue(1)); 3651 return Load; 3652 } 3653 } 3654 3655 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3656 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3657 // This often reduces constant pool loads. 3658 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3659 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3660 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3661 AddToWorkList(NewConv.getNode()); 3662 3663 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3664 if (N0.getOpcode() == ISD::FNEG) 3665 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3666 assert(N0.getOpcode() == ISD::FABS); 3667 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3668 } 3669 3670 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3671 // Note that we don't handle copysign(x,cst) because this can always be folded 3672 // to an fneg or fabs. 3673 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3674 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3675 VT.isInteger() && !VT.isVector()) { 3676 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3677 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3678 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3679 SDValue X = DAG.getNode(ISD::BIT_CONVERT, IntXVT, N0.getOperand(1)); 3680 AddToWorkList(X.getNode()); 3681 3682 // If X has a different width than the result/lhs, sext it or truncate it. 3683 unsigned VTWidth = VT.getSizeInBits(); 3684 if (OrigXWidth < VTWidth) { 3685 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3686 AddToWorkList(X.getNode()); 3687 } else if (OrigXWidth > VTWidth) { 3688 // To get the sign bit in the right place, we have to shift it right 3689 // before truncating. 3690 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3691 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3692 AddToWorkList(X.getNode()); 3693 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3694 AddToWorkList(X.getNode()); 3695 } 3696 3697 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3698 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3699 AddToWorkList(X.getNode()); 3700 3701 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3702 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3703 AddToWorkList(Cst.getNode()); 3704 3705 return DAG.getNode(ISD::OR, VT, X, Cst); 3706 } 3707 } 3708 3709 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3710 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3711 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3712 if (CombineLD.getNode()) 3713 return CombineLD; 3714 } 3715 3716 return SDValue(); 3717} 3718 3719SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3720 MVT VT = N->getValueType(0); 3721 return CombineConsecutiveLoads(N, VT); 3722} 3723 3724/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3725/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3726/// destination element value type. 3727SDValue DAGCombiner:: 3728ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3729 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3730 3731 // If this is already the right type, we're done. 3732 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3733 3734 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3735 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3736 3737 // If this is a conversion of N elements of one type to N elements of another 3738 // type, convert each element. This handles FP<->INT cases. 3739 if (SrcBitSize == DstBitSize) { 3740 SmallVector<SDValue, 8> Ops; 3741 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3742 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3743 AddToWorkList(Ops.back().getNode()); 3744 } 3745 MVT VT = MVT::getVectorVT(DstEltVT, 3746 BV->getValueType(0).getVectorNumElements()); 3747 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3748 } 3749 3750 // Otherwise, we're growing or shrinking the elements. To avoid having to 3751 // handle annoying details of growing/shrinking FP values, we convert them to 3752 // int first. 3753 if (SrcEltVT.isFloatingPoint()) { 3754 // Convert the input float vector to a int vector where the elements are the 3755 // same sizes. 3756 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3757 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3758 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3759 SrcEltVT = IntVT; 3760 } 3761 3762 // Now we know the input is an integer vector. If the output is a FP type, 3763 // convert to integer first, then to FP of the right size. 3764 if (DstEltVT.isFloatingPoint()) { 3765 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3766 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3767 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3768 3769 // Next, convert to FP elements of the same size. 3770 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3771 } 3772 3773 // Okay, we know the src/dst types are both integers of differing types. 3774 // Handling growing first. 3775 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3776 if (SrcBitSize < DstBitSize) { 3777 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3778 3779 SmallVector<SDValue, 8> Ops; 3780 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3781 i += NumInputsPerOutput) { 3782 bool isLE = TLI.isLittleEndian(); 3783 APInt NewBits = APInt(DstBitSize, 0); 3784 bool EltIsUndef = true; 3785 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3786 // Shift the previously computed bits over. 3787 NewBits <<= SrcBitSize; 3788 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3789 if (Op.getOpcode() == ISD::UNDEF) continue; 3790 EltIsUndef = false; 3791 3792 NewBits |= 3793 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3794 } 3795 3796 if (EltIsUndef) 3797 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3798 else 3799 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3800 } 3801 3802 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3803 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3804 } 3805 3806 // Finally, this must be the case where we are shrinking elements: each input 3807 // turns into multiple outputs. 3808 bool isS2V = ISD::isScalarToVector(BV); 3809 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3810 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3811 SmallVector<SDValue, 8> Ops; 3812 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3813 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3814 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3815 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3816 continue; 3817 } 3818 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3819 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3820 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3821 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3822 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3823 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3824 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3825 OpVal = OpVal.lshr(DstBitSize); 3826 } 3827 3828 // For big endian targets, swap the order of the pieces of each element. 3829 if (TLI.isBigEndian()) 3830 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3831 } 3832 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3833} 3834 3835 3836 3837SDValue DAGCombiner::visitFADD(SDNode *N) { 3838 SDValue N0 = N->getOperand(0); 3839 SDValue N1 = N->getOperand(1); 3840 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3841 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3842 MVT VT = N->getValueType(0); 3843 3844 // fold vector ops 3845 if (VT.isVector()) { 3846 SDValue FoldedVOp = SimplifyVBinOp(N); 3847 if (FoldedVOp.getNode()) return FoldedVOp; 3848 } 3849 3850 // fold (fadd c1, c2) -> c1+c2 3851 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3852 return DAG.getNode(ISD::FADD, VT, N0, N1); 3853 // canonicalize constant to RHS 3854 if (N0CFP && !N1CFP) 3855 return DAG.getNode(ISD::FADD, VT, N1, N0); 3856 // fold (A + 0) -> A 3857 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3858 return N0; 3859 // fold (A + (-B)) -> A-B 3860 if (isNegatibleForFree(N1, LegalOperations) == 2) 3861 return DAG.getNode(ISD::FSUB, VT, N0, 3862 GetNegatedExpression(N1, DAG, LegalOperations)); 3863 // fold ((-A) + B) -> B-A 3864 if (isNegatibleForFree(N0, LegalOperations) == 2) 3865 return DAG.getNode(ISD::FSUB, VT, N1, 3866 GetNegatedExpression(N0, DAG, LegalOperations)); 3867 3868 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3869 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3870 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3871 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3872 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3873 3874 return SDValue(); 3875} 3876 3877SDValue DAGCombiner::visitFSUB(SDNode *N) { 3878 SDValue N0 = N->getOperand(0); 3879 SDValue N1 = N->getOperand(1); 3880 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3881 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3882 MVT VT = N->getValueType(0); 3883 3884 // fold vector ops 3885 if (VT.isVector()) { 3886 SDValue FoldedVOp = SimplifyVBinOp(N); 3887 if (FoldedVOp.getNode()) return FoldedVOp; 3888 } 3889 3890 // fold (fsub c1, c2) -> c1-c2 3891 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3892 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3893 // fold (A-0) -> A 3894 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3895 return N0; 3896 // fold (0-B) -> -B 3897 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3898 if (isNegatibleForFree(N1, LegalOperations)) 3899 return GetNegatedExpression(N1, DAG, LegalOperations); 3900 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3901 return DAG.getNode(ISD::FNEG, VT, N1); 3902 } 3903 // fold (A-(-B)) -> A+B 3904 if (isNegatibleForFree(N1, LegalOperations)) 3905 return DAG.getNode(ISD::FADD, VT, N0, 3906 GetNegatedExpression(N1, DAG, LegalOperations)); 3907 3908 return SDValue(); 3909} 3910 3911SDValue DAGCombiner::visitFMUL(SDNode *N) { 3912 SDValue N0 = N->getOperand(0); 3913 SDValue N1 = N->getOperand(1); 3914 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3915 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3916 MVT VT = N->getValueType(0); 3917 3918 // fold vector ops 3919 if (VT.isVector()) { 3920 SDValue FoldedVOp = SimplifyVBinOp(N); 3921 if (FoldedVOp.getNode()) return FoldedVOp; 3922 } 3923 3924 // fold (fmul c1, c2) -> c1*c2 3925 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3926 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3927 // canonicalize constant to RHS 3928 if (N0CFP && !N1CFP) 3929 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3930 // fold (A * 0) -> 0 3931 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3932 return N1; 3933 // fold (fmul X, 2.0) -> (fadd X, X) 3934 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3935 return DAG.getNode(ISD::FADD, VT, N0, N0); 3936 // fold (fmul X, -1.0) -> (fneg X) 3937 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3938 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3939 return DAG.getNode(ISD::FNEG, VT, N0); 3940 3941 // -X * -Y -> X*Y 3942 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3943 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3944 // Both can be negated for free, check to see if at least one is cheaper 3945 // negated. 3946 if (LHSNeg == 2 || RHSNeg == 2) 3947 return DAG.getNode(ISD::FMUL, VT, 3948 GetNegatedExpression(N0, DAG, LegalOperations), 3949 GetNegatedExpression(N1, DAG, LegalOperations)); 3950 } 3951 } 3952 3953 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3954 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3955 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3956 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3957 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3958 3959 return SDValue(); 3960} 3961 3962SDValue DAGCombiner::visitFDIV(SDNode *N) { 3963 SDValue N0 = N->getOperand(0); 3964 SDValue N1 = N->getOperand(1); 3965 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3966 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3967 MVT VT = N->getValueType(0); 3968 3969 // fold vector ops 3970 if (VT.isVector()) { 3971 SDValue FoldedVOp = SimplifyVBinOp(N); 3972 if (FoldedVOp.getNode()) return FoldedVOp; 3973 } 3974 3975 // fold (fdiv c1, c2) -> c1/c2 3976 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3977 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3978 3979 3980 // -X / -Y -> X*Y 3981 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3982 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3983 // Both can be negated for free, check to see if at least one is cheaper 3984 // negated. 3985 if (LHSNeg == 2 || RHSNeg == 2) 3986 return DAG.getNode(ISD::FDIV, VT, 3987 GetNegatedExpression(N0, DAG, LegalOperations), 3988 GetNegatedExpression(N1, DAG, LegalOperations)); 3989 } 3990 } 3991 3992 return SDValue(); 3993} 3994 3995SDValue DAGCombiner::visitFREM(SDNode *N) { 3996 SDValue N0 = N->getOperand(0); 3997 SDValue N1 = N->getOperand(1); 3998 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3999 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4000 MVT VT = N->getValueType(0); 4001 4002 // fold (frem c1, c2) -> fmod(c1,c2) 4003 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4004 return DAG.getNode(ISD::FREM, VT, N0, N1); 4005 4006 return SDValue(); 4007} 4008 4009SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4010 SDValue N0 = N->getOperand(0); 4011 SDValue N1 = N->getOperand(1); 4012 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4013 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4014 MVT VT = N->getValueType(0); 4015 4016 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4017 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 4018 4019 if (N1CFP) { 4020 const APFloat& V = N1CFP->getValueAPF(); 4021 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4022 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4023 if (!V.isNegative()) { 4024 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4025 return DAG.getNode(ISD::FABS, VT, N0); 4026 } else { 4027 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4028 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 4029 } 4030 } 4031 4032 // copysign(fabs(x), y) -> copysign(x, y) 4033 // copysign(fneg(x), y) -> copysign(x, y) 4034 // copysign(copysign(x,z), y) -> copysign(x, y) 4035 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4036 N0.getOpcode() == ISD::FCOPYSIGN) 4037 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 4038 4039 // copysign(x, abs(y)) -> abs(x) 4040 if (N1.getOpcode() == ISD::FABS) 4041 return DAG.getNode(ISD::FABS, VT, N0); 4042 4043 // copysign(x, copysign(y,z)) -> copysign(x, z) 4044 if (N1.getOpcode() == ISD::FCOPYSIGN) 4045 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 4046 4047 // copysign(x, fp_extend(y)) -> copysign(x, y) 4048 // copysign(x, fp_round(y)) -> copysign(x, y) 4049 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4050 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 4051 4052 return SDValue(); 4053} 4054 4055 4056 4057SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4058 SDValue N0 = N->getOperand(0); 4059 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4060 MVT VT = N->getValueType(0); 4061 MVT OpVT = N0.getValueType(); 4062 4063 // fold (sint_to_fp c1) -> c1fp 4064 if (N0C && OpVT != MVT::ppcf128) 4065 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 4066 4067 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4068 // but UINT_TO_FP is legal on this target, try to convert. 4069 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4070 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4071 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4072 if (DAG.SignBitIsZero(N0)) 4073 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4074 } 4075 4076 4077 return SDValue(); 4078} 4079 4080SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4081 SDValue N0 = N->getOperand(0); 4082 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4083 MVT VT = N->getValueType(0); 4084 MVT OpVT = N0.getValueType(); 4085 4086 // fold (uint_to_fp c1) -> c1fp 4087 if (N0C && OpVT != MVT::ppcf128) 4088 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4089 4090 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4091 // but SINT_TO_FP is legal on this target, try to convert. 4092 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4093 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4094 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4095 if (DAG.SignBitIsZero(N0)) 4096 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 4097 } 4098 4099 return SDValue(); 4100} 4101 4102SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4103 SDValue N0 = N->getOperand(0); 4104 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4105 MVT VT = N->getValueType(0); 4106 4107 // fold (fp_to_sint c1fp) -> c1 4108 if (N0CFP) 4109 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 4110 return SDValue(); 4111} 4112 4113SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4114 SDValue N0 = N->getOperand(0); 4115 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4116 MVT VT = N->getValueType(0); 4117 4118 // fold (fp_to_uint c1fp) -> c1 4119 if (N0CFP && VT != MVT::ppcf128) 4120 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 4121 return SDValue(); 4122} 4123 4124SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4125 SDValue N0 = N->getOperand(0); 4126 SDValue N1 = N->getOperand(1); 4127 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4128 MVT VT = N->getValueType(0); 4129 4130 // fold (fp_round c1fp) -> c1fp 4131 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4132 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 4133 4134 // fold (fp_round (fp_extend x)) -> x 4135 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4136 return N0.getOperand(0); 4137 4138 // fold (fp_round (fp_round x)) -> (fp_round x) 4139 if (N0.getOpcode() == ISD::FP_ROUND) { 4140 // This is a value preserving truncation if both round's are. 4141 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4142 N0.getNode()->getConstantOperandVal(1) == 1; 4143 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 4144 DAG.getIntPtrConstant(IsTrunc)); 4145 } 4146 4147 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4148 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4149 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 4150 AddToWorkList(Tmp.getNode()); 4151 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 4152 } 4153 4154 return SDValue(); 4155} 4156 4157SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4158 SDValue N0 = N->getOperand(0); 4159 MVT VT = N->getValueType(0); 4160 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4161 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4162 4163 // fold (fp_round_inreg c1fp) -> c1fp 4164 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4165 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4166 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4167 } 4168 return SDValue(); 4169} 4170 4171SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4172 SDValue N0 = N->getOperand(0); 4173 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4174 MVT VT = N->getValueType(0); 4175 4176 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4177 if (N->hasOneUse() && 4178 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4179 return SDValue(); 4180 4181 // fold (fp_extend c1fp) -> c1fp 4182 if (N0CFP && VT != MVT::ppcf128) 4183 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4184 4185 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4186 // value of X. 4187 if (N0.getOpcode() == ISD::FP_ROUND 4188 && N0.getNode()->getConstantOperandVal(1) == 1) { 4189 SDValue In = N0.getOperand(0); 4190 if (In.getValueType() == VT) return In; 4191 if (VT.bitsLT(In.getValueType())) 4192 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4193 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4194 } 4195 4196 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4197 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4198 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4199 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4200 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4201 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4202 LN0->getBasePtr(), LN0->getSrcValue(), 4203 LN0->getSrcValueOffset(), 4204 N0.getValueType(), 4205 LN0->isVolatile(), LN0->getAlignment()); 4206 CombineTo(N, ExtLoad); 4207 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4208 ExtLoad, DAG.getIntPtrConstant(1)), 4209 ExtLoad.getValue(1)); 4210 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4211 } 4212 4213 return SDValue(); 4214} 4215 4216SDValue DAGCombiner::visitFNEG(SDNode *N) { 4217 SDValue N0 = N->getOperand(0); 4218 4219 if (isNegatibleForFree(N0, LegalOperations)) 4220 return GetNegatedExpression(N0, DAG, LegalOperations); 4221 4222 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4223 // constant pool values. 4224 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4225 N0.getOperand(0).getValueType().isInteger() && 4226 !N0.getOperand(0).getValueType().isVector()) { 4227 SDValue Int = N0.getOperand(0); 4228 MVT IntVT = Int.getValueType(); 4229 if (IntVT.isInteger() && !IntVT.isVector()) { 4230 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4231 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4232 AddToWorkList(Int.getNode()); 4233 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4234 } 4235 } 4236 4237 return SDValue(); 4238} 4239 4240SDValue DAGCombiner::visitFABS(SDNode *N) { 4241 SDValue N0 = N->getOperand(0); 4242 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4243 MVT VT = N->getValueType(0); 4244 4245 // fold (fabs c1) -> fabs(c1) 4246 if (N0CFP && VT != MVT::ppcf128) 4247 return DAG.getNode(ISD::FABS, VT, N0); 4248 // fold (fabs (fabs x)) -> (fabs x) 4249 if (N0.getOpcode() == ISD::FABS) 4250 return N->getOperand(0); 4251 // fold (fabs (fneg x)) -> (fabs x) 4252 // fold (fabs (fcopysign x, y)) -> (fabs x) 4253 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4254 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4255 4256 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4257 // constant pool values. 4258 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4259 N0.getOperand(0).getValueType().isInteger() && 4260 !N0.getOperand(0).getValueType().isVector()) { 4261 SDValue Int = N0.getOperand(0); 4262 MVT IntVT = Int.getValueType(); 4263 if (IntVT.isInteger() && !IntVT.isVector()) { 4264 Int = DAG.getNode(ISD::AND, IntVT, Int, 4265 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4266 AddToWorkList(Int.getNode()); 4267 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4268 } 4269 } 4270 4271 return SDValue(); 4272} 4273 4274SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4275 SDValue Chain = N->getOperand(0); 4276 SDValue N1 = N->getOperand(1); 4277 SDValue N2 = N->getOperand(2); 4278 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4279 4280 // never taken branch, fold to chain 4281 if (N1C && N1C->isNullValue()) 4282 return Chain; 4283 // unconditional branch 4284 if (N1C && N1C->getAPIntValue() == 1) 4285 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4286 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4287 // on the target. 4288 if (N1.getOpcode() == ISD::SETCC && 4289 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4290 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4291 N1.getOperand(0), N1.getOperand(1), N2); 4292 } 4293 return SDValue(); 4294} 4295 4296// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4297// 4298SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4299 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4300 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4301 4302 // Use SimplifySetCC to simplify SETCC's. 4303 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4304 CondLHS, CondRHS, CC->get(), false); 4305 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4306 4307 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4308 4309 // fold br_cc true, dest -> br dest (unconditional branch) 4310 if (SCCC && !SCCC->isNullValue()) 4311 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4312 N->getOperand(4)); 4313 // fold br_cc false, dest -> unconditional fall through 4314 if (SCCC && SCCC->isNullValue()) 4315 return N->getOperand(0); 4316 4317 // fold to a simpler setcc 4318 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4319 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4320 Simp.getOperand(2), Simp.getOperand(0), 4321 Simp.getOperand(1), N->getOperand(4)); 4322 return SDValue(); 4323} 4324 4325 4326/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4327/// pre-indexed load / store when the base pointer is an add or subtract 4328/// and it has other uses besides the load / store. After the 4329/// transformation, the new indexed load / store has effectively folded 4330/// the add / subtract in and all of its other uses are redirected to the 4331/// new load / store. 4332bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4333 if (!LegalOperations) 4334 return false; 4335 4336 bool isLoad = true; 4337 SDValue Ptr; 4338 MVT VT; 4339 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4340 if (LD->isIndexed()) 4341 return false; 4342 VT = LD->getMemoryVT(); 4343 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4344 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4345 return false; 4346 Ptr = LD->getBasePtr(); 4347 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4348 if (ST->isIndexed()) 4349 return false; 4350 VT = ST->getMemoryVT(); 4351 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4352 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4353 return false; 4354 Ptr = ST->getBasePtr(); 4355 isLoad = false; 4356 } else 4357 return false; 4358 4359 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4360 // out. There is no reason to make this a preinc/predec. 4361 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4362 Ptr.getNode()->hasOneUse()) 4363 return false; 4364 4365 // Ask the target to do addressing mode selection. 4366 SDValue BasePtr; 4367 SDValue Offset; 4368 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4369 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4370 return false; 4371 // Don't create a indexed load / store with zero offset. 4372 if (isa<ConstantSDNode>(Offset) && 4373 cast<ConstantSDNode>(Offset)->isNullValue()) 4374 return false; 4375 4376 // Try turning it into a pre-indexed load / store except when: 4377 // 1) The new base ptr is a frame index. 4378 // 2) If N is a store and the new base ptr is either the same as or is a 4379 // predecessor of the value being stored. 4380 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4381 // that would create a cycle. 4382 // 4) All uses are load / store ops that use it as old base ptr. 4383 4384 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4385 // (plus the implicit offset) to a register to preinc anyway. 4386 if (isa<FrameIndexSDNode>(BasePtr)) 4387 return false; 4388 4389 // Check #2. 4390 if (!isLoad) { 4391 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4392 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4393 return false; 4394 } 4395 4396 // Now check for #3 and #4. 4397 bool RealUse = false; 4398 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4399 E = Ptr.getNode()->use_end(); I != E; ++I) { 4400 SDNode *Use = *I; 4401 if (Use == N) 4402 continue; 4403 if (Use->isPredecessorOf(N)) 4404 return false; 4405 4406 if (!((Use->getOpcode() == ISD::LOAD && 4407 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4408 (Use->getOpcode() == ISD::STORE && 4409 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4410 RealUse = true; 4411 } 4412 if (!RealUse) 4413 return false; 4414 4415 SDValue Result; 4416 if (isLoad) 4417 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4418 else 4419 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4420 ++PreIndexedNodes; 4421 ++NodesCombined; 4422 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4423 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4424 DOUT << '\n'; 4425 WorkListRemover DeadNodes(*this); 4426 if (isLoad) { 4427 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4428 &DeadNodes); 4429 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4430 &DeadNodes); 4431 } else { 4432 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4433 &DeadNodes); 4434 } 4435 4436 // Finally, since the node is now dead, remove it from the graph. 4437 DAG.DeleteNode(N); 4438 4439 // Replace the uses of Ptr with uses of the updated base value. 4440 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4441 &DeadNodes); 4442 removeFromWorkList(Ptr.getNode()); 4443 DAG.DeleteNode(Ptr.getNode()); 4444 4445 return true; 4446} 4447 4448/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4449/// add / sub of the base pointer node into a post-indexed load / store. 4450/// The transformation folded the add / subtract into the new indexed 4451/// load / store effectively and all of its uses are redirected to the 4452/// new load / store. 4453bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4454 if (!LegalOperations) 4455 return false; 4456 4457 bool isLoad = true; 4458 SDValue Ptr; 4459 MVT VT; 4460 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4461 if (LD->isIndexed()) 4462 return false; 4463 VT = LD->getMemoryVT(); 4464 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4465 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4466 return false; 4467 Ptr = LD->getBasePtr(); 4468 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4469 if (ST->isIndexed()) 4470 return false; 4471 VT = ST->getMemoryVT(); 4472 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4473 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4474 return false; 4475 Ptr = ST->getBasePtr(); 4476 isLoad = false; 4477 } else 4478 return false; 4479 4480 if (Ptr.getNode()->hasOneUse()) 4481 return false; 4482 4483 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4484 E = Ptr.getNode()->use_end(); I != E; ++I) { 4485 SDNode *Op = *I; 4486 if (Op == N || 4487 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4488 continue; 4489 4490 SDValue BasePtr; 4491 SDValue Offset; 4492 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4493 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4494 if (Ptr == Offset) 4495 std::swap(BasePtr, Offset); 4496 if (Ptr != BasePtr) 4497 continue; 4498 // Don't create a indexed load / store with zero offset. 4499 if (isa<ConstantSDNode>(Offset) && 4500 cast<ConstantSDNode>(Offset)->isNullValue()) 4501 continue; 4502 4503 // Try turning it into a post-indexed load / store except when 4504 // 1) All uses are load / store ops that use it as base ptr. 4505 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4506 // nor a successor of N. Otherwise, if Op is folded that would 4507 // create a cycle. 4508 4509 // Check for #1. 4510 bool TryNext = false; 4511 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4512 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4513 SDNode *Use = *II; 4514 if (Use == Ptr.getNode()) 4515 continue; 4516 4517 // If all the uses are load / store addresses, then don't do the 4518 // transformation. 4519 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4520 bool RealUse = false; 4521 for (SDNode::use_iterator III = Use->use_begin(), 4522 EEE = Use->use_end(); III != EEE; ++III) { 4523 SDNode *UseUse = *III; 4524 if (!((UseUse->getOpcode() == ISD::LOAD && 4525 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4526 (UseUse->getOpcode() == ISD::STORE && 4527 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4528 RealUse = true; 4529 } 4530 4531 if (!RealUse) { 4532 TryNext = true; 4533 break; 4534 } 4535 } 4536 } 4537 if (TryNext) 4538 continue; 4539 4540 // Check for #2 4541 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4542 SDValue Result = isLoad 4543 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4544 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4545 ++PostIndexedNodes; 4546 ++NodesCombined; 4547 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4548 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4549 DOUT << '\n'; 4550 WorkListRemover DeadNodes(*this); 4551 if (isLoad) { 4552 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4553 &DeadNodes); 4554 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4555 &DeadNodes); 4556 } else { 4557 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4558 &DeadNodes); 4559 } 4560 4561 // Finally, since the node is now dead, remove it from the graph. 4562 DAG.DeleteNode(N); 4563 4564 // Replace the uses of Use with uses of the updated base value. 4565 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4566 Result.getValue(isLoad ? 1 : 0), 4567 &DeadNodes); 4568 removeFromWorkList(Op); 4569 DAG.DeleteNode(Op); 4570 return true; 4571 } 4572 } 4573 } 4574 return false; 4575} 4576 4577/// InferAlignment - If we can infer some alignment information from this 4578/// pointer, return it. 4579static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4580 // If this is a direct reference to a stack slot, use information about the 4581 // stack slot's alignment. 4582 int FrameIdx = 1 << 31; 4583 int64_t FrameOffset = 0; 4584 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4585 FrameIdx = FI->getIndex(); 4586 } else if (Ptr.getOpcode() == ISD::ADD && 4587 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4588 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4589 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4590 FrameOffset = Ptr.getConstantOperandVal(1); 4591 } 4592 4593 if (FrameIdx != (1 << 31)) { 4594 // FIXME: Handle FI+CST. 4595 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4596 if (MFI.isFixedObjectIndex(FrameIdx)) { 4597 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4598 4599 // The alignment of the frame index can be determined from its offset from 4600 // the incoming frame position. If the frame object is at offset 32 and 4601 // the stack is guaranteed to be 16-byte aligned, then we know that the 4602 // object is 16-byte aligned. 4603 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4604 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4605 4606 // Finally, the frame object itself may have a known alignment. Factor 4607 // the alignment + offset into a new alignment. For example, if we know 4608 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4609 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4610 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4611 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4612 FrameOffset); 4613 return std::max(Align, FIInfoAlign); 4614 } 4615 } 4616 4617 return 0; 4618} 4619 4620SDValue DAGCombiner::visitLOAD(SDNode *N) { 4621 LoadSDNode *LD = cast<LoadSDNode>(N); 4622 SDValue Chain = LD->getChain(); 4623 SDValue Ptr = LD->getBasePtr(); 4624 4625 // Try to infer better alignment information than the load already has. 4626 if (!Fast && LD->isUnindexed()) { 4627 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4628 if (Align > LD->getAlignment()) 4629 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4630 Chain, Ptr, LD->getSrcValue(), 4631 LD->getSrcValueOffset(), LD->getMemoryVT(), 4632 LD->isVolatile(), Align); 4633 } 4634 } 4635 4636 4637 // If load is not volatile and there are no uses of the loaded value (and 4638 // the updated indexed value in case of indexed loads), change uses of the 4639 // chain value into uses of the chain input (i.e. delete the dead load). 4640 if (!LD->isVolatile()) { 4641 if (N->getValueType(1) == MVT::Other) { 4642 // Unindexed loads. 4643 if (N->hasNUsesOfValue(0, 0)) { 4644 // It's not safe to use the two value CombineTo variant here. e.g. 4645 // v1, chain2 = load chain1, loc 4646 // v2, chain3 = load chain2, loc 4647 // v3 = add v2, c 4648 // Now we replace use of chain2 with chain1. This makes the second load 4649 // isomorphic to the one we are deleting, and thus makes this load live. 4650 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4651 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4652 DOUT << "\n"; 4653 WorkListRemover DeadNodes(*this); 4654 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4655 if (N->use_empty()) { 4656 removeFromWorkList(N); 4657 DAG.DeleteNode(N); 4658 } 4659 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4660 } 4661 } else { 4662 // Indexed loads. 4663 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4664 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4665 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4666 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4667 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4668 DOUT << " and 2 other values\n"; 4669 WorkListRemover DeadNodes(*this); 4670 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4671 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4672 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4673 &DeadNodes); 4674 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4675 removeFromWorkList(N); 4676 DAG.DeleteNode(N); 4677 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4678 } 4679 } 4680 } 4681 4682 // If this load is directly stored, replace the load value with the stored 4683 // value. 4684 // TODO: Handle store large -> read small portion. 4685 // TODO: Handle TRUNCSTORE/LOADEXT 4686 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4687 !LD->isVolatile()) { 4688 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4689 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4690 if (PrevST->getBasePtr() == Ptr && 4691 PrevST->getValue().getValueType() == N->getValueType(0)) 4692 return CombineTo(N, Chain.getOperand(1), Chain); 4693 } 4694 } 4695 4696 if (CombinerAA) { 4697 // Walk up chain skipping non-aliasing memory nodes. 4698 SDValue BetterChain = FindBetterChain(N, Chain); 4699 4700 // If there is a better chain. 4701 if (Chain != BetterChain) { 4702 SDValue ReplLoad; 4703 4704 // Replace the chain to void dependency. 4705 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4706 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4707 LD->getSrcValue(), LD->getSrcValueOffset(), 4708 LD->isVolatile(), LD->getAlignment()); 4709 } else { 4710 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4711 LD->getValueType(0), 4712 BetterChain, Ptr, LD->getSrcValue(), 4713 LD->getSrcValueOffset(), 4714 LD->getMemoryVT(), 4715 LD->isVolatile(), 4716 LD->getAlignment()); 4717 } 4718 4719 // Create token factor to keep old chain connected. 4720 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4721 Chain, ReplLoad.getValue(1)); 4722 4723 // Replace uses with load result and token factor. Don't add users 4724 // to work list. 4725 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4726 } 4727 } 4728 4729 // Try transforming N to an indexed load. 4730 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4731 return SDValue(N, 0); 4732 4733 return SDValue(); 4734} 4735 4736 4737SDValue DAGCombiner::visitSTORE(SDNode *N) { 4738 StoreSDNode *ST = cast<StoreSDNode>(N); 4739 SDValue Chain = ST->getChain(); 4740 SDValue Value = ST->getValue(); 4741 SDValue Ptr = ST->getBasePtr(); 4742 4743 // Try to infer better alignment information than the store already has. 4744 if (!Fast && ST->isUnindexed()) { 4745 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4746 if (Align > ST->getAlignment()) 4747 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4748 ST->getSrcValueOffset(), ST->getMemoryVT(), 4749 ST->isVolatile(), Align); 4750 } 4751 } 4752 4753 // If this is a store of a bit convert, store the input value if the 4754 // resultant store does not need a higher alignment than the original. 4755 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4756 ST->isUnindexed()) { 4757 unsigned Align = ST->getAlignment(); 4758 MVT SVT = Value.getOperand(0).getValueType(); 4759 unsigned OrigAlign = TLI.getTargetData()-> 4760 getABITypeAlignment(SVT.getTypeForMVT()); 4761 if (Align <= OrigAlign && 4762 ((!LegalOperations && !ST->isVolatile()) || 4763 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 4764 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4765 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4766 } 4767 4768 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4769 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4770 // NOTE: If the original store is volatile, this transform must not increase 4771 // the number of stores. For example, on x86-32 an f64 can be stored in one 4772 // processor operation but an i64 (which is not legal) requires two. So the 4773 // transform should not be done in this case. 4774 if (Value.getOpcode() != ISD::TargetConstantFP) { 4775 SDValue Tmp; 4776 switch (CFP->getValueType(0).getSimpleVT()) { 4777 default: assert(0 && "Unknown FP type"); 4778 case MVT::f80: // We don't do this for these yet. 4779 case MVT::f128: 4780 case MVT::ppcf128: 4781 break; 4782 case MVT::f32: 4783 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 4784 !ST->isVolatile()) || 4785 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4786 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4787 bitcastToAPInt().getZExtValue(), MVT::i32); 4788 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4789 ST->getSrcValueOffset(), ST->isVolatile(), 4790 ST->getAlignment()); 4791 } 4792 break; 4793 case MVT::f64: 4794 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 4795 !ST->isVolatile()) || 4796 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 4797 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4798 getZExtValue(), MVT::i64); 4799 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4800 ST->getSrcValueOffset(), ST->isVolatile(), 4801 ST->getAlignment()); 4802 } else if (!ST->isVolatile() && 4803 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4804 // Many FP stores are not made apparent until after legalize, e.g. for 4805 // argument passing. Since this is so common, custom legalize the 4806 // 64-bit integer store into two 32-bit stores. 4807 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4808 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4809 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4810 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4811 4812 int SVOffset = ST->getSrcValueOffset(); 4813 unsigned Alignment = ST->getAlignment(); 4814 bool isVolatile = ST->isVolatile(); 4815 4816 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4817 ST->getSrcValueOffset(), 4818 isVolatile, ST->getAlignment()); 4819 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4820 DAG.getConstant(4, Ptr.getValueType())); 4821 SVOffset += 4; 4822 Alignment = MinAlign(Alignment, 4U); 4823 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4824 SVOffset, isVolatile, Alignment); 4825 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4826 } 4827 break; 4828 } 4829 } 4830 } 4831 4832 if (CombinerAA) { 4833 // Walk up chain skipping non-aliasing memory nodes. 4834 SDValue BetterChain = FindBetterChain(N, Chain); 4835 4836 // If there is a better chain. 4837 if (Chain != BetterChain) { 4838 // Replace the chain to avoid dependency. 4839 SDValue ReplStore; 4840 if (ST->isTruncatingStore()) { 4841 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4842 ST->getSrcValue(),ST->getSrcValueOffset(), 4843 ST->getMemoryVT(), 4844 ST->isVolatile(), ST->getAlignment()); 4845 } else { 4846 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4847 ST->getSrcValue(), ST->getSrcValueOffset(), 4848 ST->isVolatile(), ST->getAlignment()); 4849 } 4850 4851 // Create token to keep both nodes around. 4852 SDValue Token = 4853 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4854 4855 // Don't add users to work list. 4856 return CombineTo(N, Token, false); 4857 } 4858 } 4859 4860 // Try transforming N to an indexed store. 4861 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4862 return SDValue(N, 0); 4863 4864 // FIXME: is there such a thing as a truncating indexed store? 4865 if (ST->isTruncatingStore() && ST->isUnindexed() && 4866 Value.getValueType().isInteger()) { 4867 // See if we can simplify the input to this truncstore with knowledge that 4868 // only the low bits are being used. For example: 4869 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4870 SDValue Shorter = 4871 GetDemandedBits(Value, 4872 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4873 ST->getMemoryVT().getSizeInBits())); 4874 AddToWorkList(Value.getNode()); 4875 if (Shorter.getNode()) 4876 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4877 ST->getSrcValueOffset(), ST->getMemoryVT(), 4878 ST->isVolatile(), ST->getAlignment()); 4879 4880 // Otherwise, see if we can simplify the operation with 4881 // SimplifyDemandedBits, which only works if the value has a single use. 4882 if (SimplifyDemandedBits(Value, 4883 APInt::getLowBitsSet( 4884 Value.getValueSizeInBits(), 4885 ST->getMemoryVT().getSizeInBits()))) 4886 return SDValue(N, 0); 4887 } 4888 4889 // If this is a load followed by a store to the same location, then the store 4890 // is dead/noop. 4891 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4892 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4893 ST->isUnindexed() && !ST->isVolatile() && 4894 // There can't be any side effects between the load and store, such as 4895 // a call or store. 4896 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4897 // The store is dead, remove it. 4898 return Chain; 4899 } 4900 } 4901 4902 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4903 // truncating store. We can do this even if this is already a truncstore. 4904 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4905 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4906 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4907 ST->getMemoryVT())) { 4908 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4909 ST->getSrcValueOffset(), ST->getMemoryVT(), 4910 ST->isVolatile(), ST->getAlignment()); 4911 } 4912 4913 return SDValue(); 4914} 4915 4916SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4917 SDValue InVec = N->getOperand(0); 4918 SDValue InVal = N->getOperand(1); 4919 SDValue EltNo = N->getOperand(2); 4920 4921 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4922 // vector with the inserted element. 4923 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4924 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4925 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 4926 InVec.getNode()->op_end()); 4927 if (Elt < Ops.size()) 4928 Ops[Elt] = InVal; 4929 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4930 &Ops[0], Ops.size()); 4931 } 4932 4933 return SDValue(); 4934} 4935 4936SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4937 // (vextract (scalar_to_vector val, 0) -> val 4938 SDValue InVec = N->getOperand(0); 4939 4940 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) 4941 return InVec.getOperand(0); 4942 4943 // Perform only after legalization to ensure build_vector / vector_shuffle 4944 // optimizations have already been done. 4945 if (!LegalOperations) return SDValue(); 4946 4947 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4948 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4949 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4950 SDValue EltNo = N->getOperand(1); 4951 4952 if (isa<ConstantSDNode>(EltNo)) { 4953 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4954 bool NewLoad = false; 4955 bool BCNumEltsChanged = false; 4956 MVT VT = InVec.getValueType(); 4957 MVT EVT = VT.getVectorElementType(); 4958 MVT LVT = EVT; 4959 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4960 MVT BCVT = InVec.getOperand(0).getValueType(); 4961 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4962 return SDValue(); 4963 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 4964 BCNumEltsChanged = true; 4965 InVec = InVec.getOperand(0); 4966 EVT = BCVT.getVectorElementType(); 4967 NewLoad = true; 4968 } 4969 4970 LoadSDNode *LN0 = NULL; 4971 if (ISD::isNormalLoad(InVec.getNode())) 4972 LN0 = cast<LoadSDNode>(InVec); 4973 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4974 InVec.getOperand(0).getValueType() == EVT && 4975 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 4976 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4977 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4978 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4979 // => 4980 // (load $addr+1*size) 4981 4982 // If the bit convert changed the number of elements, it is unsafe 4983 // to examine the mask. 4984 if (BCNumEltsChanged) 4985 return SDValue(); 4986 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4987 getOperand(Elt))->getZExtValue(); 4988 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4989 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4990 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4991 InVec = InVec.getOperand(0); 4992 if (ISD::isNormalLoad(InVec.getNode())) { 4993 LN0 = cast<LoadSDNode>(InVec); 4994 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4995 } 4996 } 4997 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4998 return SDValue(); 4999 5000 unsigned Align = LN0->getAlignment(); 5001 if (NewLoad) { 5002 // Check the resultant load doesn't need a higher alignment than the 5003 // original load. 5004 unsigned NewAlign = TLI.getTargetData()-> 5005 getABITypeAlignment(LVT.getTypeForMVT()); 5006 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5007 return SDValue(); 5008 Align = NewAlign; 5009 } 5010 5011 SDValue NewPtr = LN0->getBasePtr(); 5012 if (Elt) { 5013 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5014 MVT PtrType = NewPtr.getValueType(); 5015 if (TLI.isBigEndian()) 5016 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5017 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 5018 DAG.getConstant(PtrOff, PtrType)); 5019 } 5020 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 5021 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5022 LN0->isVolatile(), Align); 5023 } 5024 return SDValue(); 5025} 5026 5027 5028SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5029 unsigned NumInScalars = N->getNumOperands(); 5030 MVT VT = N->getValueType(0); 5031 unsigned NumElts = VT.getVectorNumElements(); 5032 MVT EltType = VT.getVectorElementType(); 5033 5034 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5035 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5036 // at most two distinct vectors, turn this into a shuffle node. 5037 SDValue VecIn1, VecIn2; 5038 for (unsigned i = 0; i != NumInScalars; ++i) { 5039 // Ignore undef inputs. 5040 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5041 5042 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5043 // constant index, bail out. 5044 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5045 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5046 VecIn1 = VecIn2 = SDValue(0, 0); 5047 break; 5048 } 5049 5050 // If the input vector type disagrees with the result of the build_vector, 5051 // we can't make a shuffle. 5052 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5053 if (ExtractedFromVec.getValueType() != VT) { 5054 VecIn1 = VecIn2 = SDValue(0, 0); 5055 break; 5056 } 5057 5058 // Otherwise, remember this. We allow up to two distinct input vectors. 5059 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5060 continue; 5061 5062 if (VecIn1.getNode() == 0) { 5063 VecIn1 = ExtractedFromVec; 5064 } else if (VecIn2.getNode() == 0) { 5065 VecIn2 = ExtractedFromVec; 5066 } else { 5067 // Too many inputs. 5068 VecIn1 = VecIn2 = SDValue(0, 0); 5069 break; 5070 } 5071 } 5072 5073 // If everything is good, we can make a shuffle operation. 5074 if (VecIn1.getNode()) { 5075 SmallVector<SDValue, 8> BuildVecIndices; 5076 for (unsigned i = 0; i != NumInScalars; ++i) { 5077 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5078 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 5079 continue; 5080 } 5081 5082 SDValue Extract = N->getOperand(i); 5083 5084 // If extracting from the first vector, just use the index directly. 5085 if (Extract.getOperand(0) == VecIn1) { 5086 BuildVecIndices.push_back(Extract.getOperand(1)); 5087 continue; 5088 } 5089 5090 // Otherwise, use InIdx + VecSize 5091 unsigned Idx = 5092 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 5093 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 5094 } 5095 5096 // Add count and size info. 5097 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5098 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes) 5099 return SDValue(); 5100 5101 // Return the new VECTOR_SHUFFLE node. 5102 SDValue Ops[5]; 5103 Ops[0] = VecIn1; 5104 if (VecIn2.getNode()) { 5105 Ops[1] = VecIn2; 5106 } else { 5107 // Use an undef build_vector as input for the second operand. 5108 std::vector<SDValue> UnOps(NumInScalars, 5109 DAG.getNode(ISD::UNDEF, 5110 EltType)); 5111 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 5112 &UnOps[0], UnOps.size()); 5113 AddToWorkList(Ops[1].getNode()); 5114 } 5115 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 5116 &BuildVecIndices[0], BuildVecIndices.size()); 5117 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 5118 } 5119 5120 return SDValue(); 5121} 5122 5123SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5124 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5125 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5126 // inputs come from at most two distinct vectors, turn this into a shuffle 5127 // node. 5128 5129 // If we only have one input vector, we don't need to do any concatenation. 5130 if (N->getNumOperands() == 1) { 5131 return N->getOperand(0); 5132 } 5133 5134 return SDValue(); 5135} 5136 5137SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5138 SDValue ShufMask = N->getOperand(2); 5139 unsigned NumElts = ShufMask.getNumOperands(); 5140 5141 SDValue N0 = N->getOperand(0); 5142 SDValue N1 = N->getOperand(1); 5143 5144 assert(N0.getValueType().getVectorNumElements() == NumElts && 5145 "Vector shuffle must be normalized in DAG"); 5146 5147 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5148 bool isIdentity = true; 5149 for (unsigned i = 0; i != NumElts; ++i) { 5150 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5151 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5152 isIdentity = false; 5153 break; 5154 } 5155 } 5156 if (isIdentity) return N->getOperand(0); 5157 5158 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5159 isIdentity = true; 5160 for (unsigned i = 0; i != NumElts; ++i) { 5161 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5162 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5163 i+NumElts) { 5164 isIdentity = false; 5165 break; 5166 } 5167 } 5168 if (isIdentity) return N->getOperand(1); 5169 5170 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5171 // needed at all. 5172 bool isUnary = true; 5173 bool isSplat = true; 5174 int VecNum = -1; 5175 unsigned BaseIdx = 0; 5176 for (unsigned i = 0; i != NumElts; ++i) 5177 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5178 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5179 int V = (Idx < NumElts) ? 0 : 1; 5180 if (VecNum == -1) { 5181 VecNum = V; 5182 BaseIdx = Idx; 5183 } else { 5184 if (BaseIdx != Idx) 5185 isSplat = false; 5186 if (VecNum != V) { 5187 isUnary = false; 5188 break; 5189 } 5190 } 5191 } 5192 5193 // Normalize unary shuffle so the RHS is undef. 5194 if (isUnary && VecNum == 1) 5195 std::swap(N0, N1); 5196 5197 // If it is a splat, check if the argument vector is a build_vector with 5198 // all scalar elements the same. 5199 if (isSplat) { 5200 SDNode *V = N0.getNode(); 5201 5202 // If this is a bit convert that changes the element type of the vector but 5203 // not the number of vector elements, look through it. Be careful not to 5204 // look though conversions that change things like v4f32 to v2f64. 5205 if (V->getOpcode() == ISD::BIT_CONVERT) { 5206 SDValue ConvInput = V->getOperand(0); 5207 if (ConvInput.getValueType().isVector() && 5208 ConvInput.getValueType().getVectorNumElements() == NumElts) 5209 V = ConvInput.getNode(); 5210 } 5211 5212 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5213 unsigned NumElems = V->getNumOperands(); 5214 if (NumElems > BaseIdx) { 5215 SDValue Base; 5216 bool AllSame = true; 5217 for (unsigned i = 0; i != NumElems; ++i) { 5218 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5219 Base = V->getOperand(i); 5220 break; 5221 } 5222 } 5223 // Splat of <u, u, u, u>, return <u, u, u, u> 5224 if (!Base.getNode()) 5225 return N0; 5226 for (unsigned i = 0; i != NumElems; ++i) { 5227 if (V->getOperand(i) != Base) { 5228 AllSame = false; 5229 break; 5230 } 5231 } 5232 // Splat of <x, x, x, x>, return <x, x, x, x> 5233 if (AllSame) 5234 return N0; 5235 } 5236 } 5237 } 5238 5239 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5240 // into an undef. 5241 if (isUnary || N0 == N1) { 5242 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5243 // first operand. 5244 SmallVector<SDValue, 8> MappedOps; 5245 for (unsigned i = 0; i != NumElts; ++i) { 5246 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5247 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5248 NumElts) { 5249 MappedOps.push_back(ShufMask.getOperand(i)); 5250 } else { 5251 unsigned NewIdx = 5252 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5253 NumElts; 5254 MappedOps.push_back(DAG.getConstant(NewIdx, 5255 ShufMask.getOperand(i).getValueType())); 5256 } 5257 } 5258 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5259 &MappedOps[0], MappedOps.size()); 5260 AddToWorkList(ShufMask.getNode()); 5261 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5262 N0, 5263 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5264 ShufMask); 5265 } 5266 5267 return SDValue(); 5268} 5269 5270/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5271/// an AND to a vector_shuffle with the destination vector and a zero vector. 5272/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5273/// vector_shuffle V, Zero, <0, 4, 2, 4> 5274SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5275 SDValue LHS = N->getOperand(0); 5276 SDValue RHS = N->getOperand(1); 5277 if (N->getOpcode() == ISD::AND) { 5278 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5279 RHS = RHS.getOperand(0); 5280 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5281 std::vector<SDValue> IdxOps; 5282 unsigned NumOps = RHS.getNumOperands(); 5283 unsigned NumElts = NumOps; 5284 for (unsigned i = 0; i != NumElts; ++i) { 5285 SDValue Elt = RHS.getOperand(i); 5286 if (!isa<ConstantSDNode>(Elt)) 5287 return SDValue(); 5288 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5289 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5290 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5291 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5292 else 5293 return SDValue(); 5294 } 5295 5296 // Let's see if the target supports this vector_shuffle. 5297 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5298 return SDValue(); 5299 5300 // Return the new VECTOR_SHUFFLE node. 5301 MVT EVT = RHS.getValueType().getVectorElementType(); 5302 MVT VT = MVT::getVectorVT(EVT, NumElts); 5303 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5304 std::vector<SDValue> Ops; 5305 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5306 Ops.push_back(LHS); 5307 AddToWorkList(LHS.getNode()); 5308 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5309 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5310 &ZeroOps[0], ZeroOps.size())); 5311 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5312 &IdxOps[0], IdxOps.size())); 5313 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5314 &Ops[0], Ops.size()); 5315 if (VT != N->getValueType(0)) 5316 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5317 return Result; 5318 } 5319 } 5320 return SDValue(); 5321} 5322 5323/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5324SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5325 // After legalize, the target may be depending on adds and other 5326 // binary ops to provide legal ways to construct constants or other 5327 // things. Simplifying them may result in a loss of legality. 5328 if (LegalOperations) return SDValue(); 5329 5330 MVT VT = N->getValueType(0); 5331 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5332 5333 MVT EltType = VT.getVectorElementType(); 5334 SDValue LHS = N->getOperand(0); 5335 SDValue RHS = N->getOperand(1); 5336 SDValue Shuffle = XformToShuffleWithZero(N); 5337 if (Shuffle.getNode()) return Shuffle; 5338 5339 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5340 // this operation. 5341 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5342 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5343 SmallVector<SDValue, 8> Ops; 5344 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5345 SDValue LHSOp = LHS.getOperand(i); 5346 SDValue RHSOp = RHS.getOperand(i); 5347 // If these two elements can't be folded, bail out. 5348 if ((LHSOp.getOpcode() != ISD::UNDEF && 5349 LHSOp.getOpcode() != ISD::Constant && 5350 LHSOp.getOpcode() != ISD::ConstantFP) || 5351 (RHSOp.getOpcode() != ISD::UNDEF && 5352 RHSOp.getOpcode() != ISD::Constant && 5353 RHSOp.getOpcode() != ISD::ConstantFP)) 5354 break; 5355 // Can't fold divide by zero. 5356 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5357 N->getOpcode() == ISD::FDIV) { 5358 if ((RHSOp.getOpcode() == ISD::Constant && 5359 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5360 (RHSOp.getOpcode() == ISD::ConstantFP && 5361 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5362 break; 5363 } 5364 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5365 AddToWorkList(Ops.back().getNode()); 5366 assert((Ops.back().getOpcode() == ISD::UNDEF || 5367 Ops.back().getOpcode() == ISD::Constant || 5368 Ops.back().getOpcode() == ISD::ConstantFP) && 5369 "Scalar binop didn't fold!"); 5370 } 5371 5372 if (Ops.size() == LHS.getNumOperands()) { 5373 MVT VT = LHS.getValueType(); 5374 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5375 } 5376 } 5377 5378 return SDValue(); 5379} 5380 5381SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5382 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5383 5384 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5385 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5386 // If we got a simplified select_cc node back from SimplifySelectCC, then 5387 // break it down into a new SETCC node, and a new SELECT node, and then return 5388 // the SELECT node, since we were called with a SELECT node. 5389 if (SCC.getNode()) { 5390 // Check to see if we got a select_cc back (to turn into setcc/select). 5391 // Otherwise, just return whatever node we got back, like fabs. 5392 if (SCC.getOpcode() == ISD::SELECT_CC) { 5393 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5394 SCC.getOperand(0), SCC.getOperand(1), 5395 SCC.getOperand(4)); 5396 AddToWorkList(SETCC.getNode()); 5397 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5398 SCC.getOperand(3), SETCC); 5399 } 5400 return SCC; 5401 } 5402 return SDValue(); 5403} 5404 5405/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5406/// are the two values being selected between, see if we can simplify the 5407/// select. Callers of this should assume that TheSelect is deleted if this 5408/// returns true. As such, they should return the appropriate thing (e.g. the 5409/// node) back to the top-level of the DAG combiner loop to avoid it being 5410/// looked at. 5411/// 5412bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5413 SDValue RHS) { 5414 5415 // If this is a select from two identical things, try to pull the operation 5416 // through the select. 5417 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5418 // If this is a load and the token chain is identical, replace the select 5419 // of two loads with a load through a select of the address to load from. 5420 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5421 // constants have been dropped into the constant pool. 5422 if (LHS.getOpcode() == ISD::LOAD && 5423 // Do not let this transformation reduce the number of volatile loads. 5424 !cast<LoadSDNode>(LHS)->isVolatile() && 5425 !cast<LoadSDNode>(RHS)->isVolatile() && 5426 // Token chains must be identical. 5427 LHS.getOperand(0) == RHS.getOperand(0)) { 5428 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5429 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5430 5431 // If this is an EXTLOAD, the VT's must match. 5432 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5433 // FIXME: this conflates two src values, discarding one. This is not 5434 // the right thing to do, but nothing uses srcvalues now. When they do, 5435 // turn SrcValue into a list of locations. 5436 SDValue Addr; 5437 if (TheSelect->getOpcode() == ISD::SELECT) { 5438 // Check that the condition doesn't reach either load. If so, folding 5439 // this will induce a cycle into the DAG. 5440 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5441 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5442 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5443 TheSelect->getOperand(0), LLD->getBasePtr(), 5444 RLD->getBasePtr()); 5445 } 5446 } else { 5447 // Check that the condition doesn't reach either load. If so, folding 5448 // this will induce a cycle into the DAG. 5449 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5450 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5451 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5452 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5453 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5454 TheSelect->getOperand(0), 5455 TheSelect->getOperand(1), 5456 LLD->getBasePtr(), RLD->getBasePtr(), 5457 TheSelect->getOperand(4)); 5458 } 5459 } 5460 5461 if (Addr.getNode()) { 5462 SDValue Load; 5463 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5464 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5465 Addr,LLD->getSrcValue(), 5466 LLD->getSrcValueOffset(), 5467 LLD->isVolatile(), 5468 LLD->getAlignment()); 5469 else { 5470 Load = DAG.getExtLoad(LLD->getExtensionType(), 5471 TheSelect->getValueType(0), 5472 LLD->getChain(), Addr, LLD->getSrcValue(), 5473 LLD->getSrcValueOffset(), 5474 LLD->getMemoryVT(), 5475 LLD->isVolatile(), 5476 LLD->getAlignment()); 5477 } 5478 // Users of the select now use the result of the load. 5479 CombineTo(TheSelect, Load); 5480 5481 // Users of the old loads now use the new load's chain. We know the 5482 // old-load value is dead now. 5483 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5484 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5485 return true; 5486 } 5487 } 5488 } 5489 } 5490 5491 return false; 5492} 5493 5494SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5495 SDValue N2, SDValue N3, 5496 ISD::CondCode CC, bool NotExtCompare) { 5497 5498 MVT VT = N2.getValueType(); 5499 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5500 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5501 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5502 5503 // Determine if the condition we're dealing with is constant 5504 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5505 N0, N1, CC, false); 5506 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5507 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5508 5509 // fold select_cc true, x, y -> x 5510 if (SCCC && !SCCC->isNullValue()) 5511 return N2; 5512 // fold select_cc false, x, y -> y 5513 if (SCCC && SCCC->isNullValue()) 5514 return N3; 5515 5516 // Check to see if we can simplify the select into an fabs node 5517 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5518 // Allow either -0.0 or 0.0 5519 if (CFP->getValueAPF().isZero()) { 5520 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5521 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5522 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5523 N2 == N3.getOperand(0)) 5524 return DAG.getNode(ISD::FABS, VT, N0); 5525 5526 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5527 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5528 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5529 N2.getOperand(0) == N3) 5530 return DAG.getNode(ISD::FABS, VT, N3); 5531 } 5532 } 5533 5534 // Check to see if we can perform the "gzip trick", transforming 5535 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5536 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5537 N0.getValueType().isInteger() && 5538 N2.getValueType().isInteger() && 5539 (N1C->isNullValue() || // (a < 0) ? b : 0 5540 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5541 MVT XType = N0.getValueType(); 5542 MVT AType = N2.getValueType(); 5543 if (XType.bitsGE(AType)) { 5544 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5545 // single-bit constant. 5546 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5547 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5548 ShCtV = XType.getSizeInBits()-ShCtV-1; 5549 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5550 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5551 AddToWorkList(Shift.getNode()); 5552 if (XType.bitsGT(AType)) { 5553 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5554 AddToWorkList(Shift.getNode()); 5555 } 5556 return DAG.getNode(ISD::AND, AType, Shift, N2); 5557 } 5558 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5559 DAG.getConstant(XType.getSizeInBits()-1, 5560 TLI.getShiftAmountTy())); 5561 AddToWorkList(Shift.getNode()); 5562 if (XType.bitsGT(AType)) { 5563 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5564 AddToWorkList(Shift.getNode()); 5565 } 5566 return DAG.getNode(ISD::AND, AType, Shift, N2); 5567 } 5568 } 5569 5570 // fold select C, 16, 0 -> shl C, 4 5571 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5572 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5573 5574 // If the caller doesn't want us to simplify this into a zext of a compare, 5575 // don't do it. 5576 if (NotExtCompare && N2C->getAPIntValue() == 1) 5577 return SDValue(); 5578 5579 // Get a SetCC of the condition 5580 // FIXME: Should probably make sure that setcc is legal if we ever have a 5581 // target where it isn't. 5582 SDValue Temp, SCC; 5583 // cast from setcc result type to select result type 5584 if (LegalTypes) { 5585 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0.getValueType()), 5586 N0, N1, CC); 5587 if (N2.getValueType().bitsLT(SCC.getValueType())) 5588 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5589 else 5590 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5591 } else { 5592 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5593 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5594 } 5595 AddToWorkList(SCC.getNode()); 5596 AddToWorkList(Temp.getNode()); 5597 5598 if (N2C->getAPIntValue() == 1) 5599 return Temp; 5600 // shl setcc result by log2 n2c 5601 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5602 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5603 TLI.getShiftAmountTy())); 5604 } 5605 5606 // Check to see if this is the equivalent of setcc 5607 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5608 // otherwise, go ahead with the folds. 5609 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5610 MVT XType = N0.getValueType(); 5611 if (!LegalOperations || 5612 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5613 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(XType), N0, N1, CC); 5614 if (Res.getValueType() != VT) 5615 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5616 return Res; 5617 } 5618 5619 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5620 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5621 (!LegalOperations || 5622 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5623 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5624 return DAG.getNode(ISD::SRL, XType, Ctlz, 5625 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5626 TLI.getShiftAmountTy())); 5627 } 5628 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5629 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5630 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5631 N0); 5632 SDValue NotN0 = DAG.getNOT(N0, XType); 5633 return DAG.getNode(ISD::SRL, XType, 5634 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5635 DAG.getConstant(XType.getSizeInBits()-1, 5636 TLI.getShiftAmountTy())); 5637 } 5638 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5639 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5640 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5641 DAG.getConstant(XType.getSizeInBits()-1, 5642 TLI.getShiftAmountTy())); 5643 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5644 } 5645 } 5646 5647 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5648 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5649 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5650 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5651 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5652 MVT XType = N0.getValueType(); 5653 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5654 DAG.getConstant(XType.getSizeInBits()-1, 5655 TLI.getShiftAmountTy())); 5656 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5657 AddToWorkList(Shift.getNode()); 5658 AddToWorkList(Add.getNode()); 5659 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5660 } 5661 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5662 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5663 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5664 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5665 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5666 MVT XType = N0.getValueType(); 5667 if (SubC->isNullValue() && XType.isInteger()) { 5668 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5669 DAG.getConstant(XType.getSizeInBits()-1, 5670 TLI.getShiftAmountTy())); 5671 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5672 AddToWorkList(Shift.getNode()); 5673 AddToWorkList(Add.getNode()); 5674 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5675 } 5676 } 5677 } 5678 5679 return SDValue(); 5680} 5681 5682/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5683SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5684 SDValue N1, ISD::CondCode Cond, 5685 bool foldBooleans) { 5686 TargetLowering::DAGCombinerInfo 5687 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5688 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5689} 5690 5691/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5692/// return a DAG expression to select that will generate the same value by 5693/// multiplying by a magic number. See: 5694/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5695SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5696 std::vector<SDNode*> Built; 5697 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5698 5699 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5700 ii != ee; ++ii) 5701 AddToWorkList(*ii); 5702 return S; 5703} 5704 5705/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5706/// return a DAG expression to select that will generate the same value by 5707/// multiplying by a magic number. See: 5708/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5709SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5710 std::vector<SDNode*> Built; 5711 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5712 5713 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5714 ii != ee; ++ii) 5715 AddToWorkList(*ii); 5716 return S; 5717} 5718 5719/// FindBaseOffset - Return true if base is known not to alias with anything 5720/// but itself. Provides base object and offset as results. 5721static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5722 // Assume it is a primitive operation. 5723 Base = Ptr; Offset = 0; 5724 5725 // If it's an adding a simple constant then integrate the offset. 5726 if (Base.getOpcode() == ISD::ADD) { 5727 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5728 Base = Base.getOperand(0); 5729 Offset += C->getZExtValue(); 5730 } 5731 } 5732 5733 // If it's any of the following then it can't alias with anything but itself. 5734 return isa<FrameIndexSDNode>(Base) || 5735 isa<ConstantPoolSDNode>(Base) || 5736 isa<GlobalAddressSDNode>(Base); 5737} 5738 5739/// isAlias - Return true if there is any possibility that the two addresses 5740/// overlap. 5741bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5742 const Value *SrcValue1, int SrcValueOffset1, 5743 SDValue Ptr2, int64_t Size2, 5744 const Value *SrcValue2, int SrcValueOffset2) 5745{ 5746 // If they are the same then they must be aliases. 5747 if (Ptr1 == Ptr2) return true; 5748 5749 // Gather base node and offset information. 5750 SDValue Base1, Base2; 5751 int64_t Offset1, Offset2; 5752 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5753 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5754 5755 // If they have a same base address then... 5756 if (Base1 == Base2) { 5757 // Check to see if the addresses overlap. 5758 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5759 } 5760 5761 // If we know both bases then they can't alias. 5762 if (KnownBase1 && KnownBase2) return false; 5763 5764 if (CombinerGlobalAA) { 5765 // Use alias analysis information. 5766 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5767 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5768 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5769 AliasAnalysis::AliasResult AAResult = 5770 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5771 if (AAResult == AliasAnalysis::NoAlias) 5772 return false; 5773 } 5774 5775 // Otherwise we have to assume they alias. 5776 return true; 5777} 5778 5779/// FindAliasInfo - Extracts the relevant alias information from the memory 5780/// node. Returns true if the operand was a load. 5781bool DAGCombiner::FindAliasInfo(SDNode *N, 5782 SDValue &Ptr, int64_t &Size, 5783 const Value *&SrcValue, int &SrcValueOffset) { 5784 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5785 Ptr = LD->getBasePtr(); 5786 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5787 SrcValue = LD->getSrcValue(); 5788 SrcValueOffset = LD->getSrcValueOffset(); 5789 return true; 5790 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5791 Ptr = ST->getBasePtr(); 5792 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5793 SrcValue = ST->getSrcValue(); 5794 SrcValueOffset = ST->getSrcValueOffset(); 5795 } else { 5796 assert(0 && "FindAliasInfo expected a memory operand"); 5797 } 5798 5799 return false; 5800} 5801 5802/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5803/// looking for aliasing nodes and adding them to the Aliases vector. 5804void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5805 SmallVector<SDValue, 8> &Aliases) { 5806 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5807 std::set<SDNode *> Visited; // Visited node set. 5808 5809 // Get alias information for node. 5810 SDValue Ptr; 5811 int64_t Size; 5812 const Value *SrcValue; 5813 int SrcValueOffset; 5814 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5815 5816 // Starting off. 5817 Chains.push_back(OriginalChain); 5818 5819 // Look at each chain and determine if it is an alias. If so, add it to the 5820 // aliases list. If not, then continue up the chain looking for the next 5821 // candidate. 5822 while (!Chains.empty()) { 5823 SDValue Chain = Chains.back(); 5824 Chains.pop_back(); 5825 5826 // Don't bother if we've been before. 5827 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5828 Visited.insert(Chain.getNode()); 5829 5830 switch (Chain.getOpcode()) { 5831 case ISD::EntryToken: 5832 // Entry token is ideal chain operand, but handled in FindBetterChain. 5833 break; 5834 5835 case ISD::LOAD: 5836 case ISD::STORE: { 5837 // Get alias information for Chain. 5838 SDValue OpPtr; 5839 int64_t OpSize; 5840 const Value *OpSrcValue; 5841 int OpSrcValueOffset; 5842 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5843 OpSrcValue, OpSrcValueOffset); 5844 5845 // If chain is alias then stop here. 5846 if (!(IsLoad && IsOpLoad) && 5847 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5848 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5849 Aliases.push_back(Chain); 5850 } else { 5851 // Look further up the chain. 5852 Chains.push_back(Chain.getOperand(0)); 5853 // Clean up old chain. 5854 AddToWorkList(Chain.getNode()); 5855 } 5856 break; 5857 } 5858 5859 case ISD::TokenFactor: 5860 // We have to check each of the operands of the token factor, so we queue 5861 // then up. Adding the operands to the queue (stack) in reverse order 5862 // maintains the original order and increases the likelihood that getNode 5863 // will find a matching token factor (CSE.) 5864 for (unsigned n = Chain.getNumOperands(); n;) 5865 Chains.push_back(Chain.getOperand(--n)); 5866 // Eliminate the token factor if we can. 5867 AddToWorkList(Chain.getNode()); 5868 break; 5869 5870 default: 5871 // For all other instructions we will just have to take what we can get. 5872 Aliases.push_back(Chain); 5873 break; 5874 } 5875 } 5876} 5877 5878/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5879/// for a better chain (aliasing node.) 5880SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5881 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5882 5883 // Accumulate all the aliases to this node. 5884 GatherAllAliases(N, OldChain, Aliases); 5885 5886 if (Aliases.size() == 0) { 5887 // If no operands then chain to entry token. 5888 return DAG.getEntryNode(); 5889 } else if (Aliases.size() == 1) { 5890 // If a single operand then chain to it. We don't need to revisit it. 5891 return Aliases[0]; 5892 } 5893 5894 // Construct a custom tailored token factor. 5895 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5896 &Aliases[0], Aliases.size()); 5897 5898 // Make sure the old chain gets cleaned up. 5899 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5900 5901 return NewChain; 5902} 5903 5904// SelectionDAG::Combine - This is the entry point for the file. 5905// 5906void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { 5907 /// run - This is the main entry point to this class. 5908 /// 5909 DAGCombiner(*this, AA, Fast).Run(Level); 5910} 5911