DAGCombiner.cpp revision 77f0b7a50a08614b5ffd58f1864b68a9a30d0cb0
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32using namespace llvm; 33 34STATISTIC(NodesCombined , "Number of dag nodes combined"); 35STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 36STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 37 38namespace { 39#ifndef NDEBUG 40 static cl::opt<bool> 41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 42 cl::desc("Pop up a window to show dags before the first " 43 "dag combine pass")); 44 static cl::opt<bool> 45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 46 cl::desc("Pop up a window to show dags before the second " 47 "dag combine pass")); 48#else 49 static const bool ViewDAGCombine1 = false; 50 static const bool ViewDAGCombine2 = false; 51#endif 52 53 static cl::opt<bool> 54 CombinerAA("combiner-alias-analysis", cl::Hidden, 55 cl::desc("Turn on alias analysis during testing")); 56 57 static cl::opt<bool> 58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 59 cl::desc("Include global information in alias analysis")); 60 61//------------------------------ DAGCombiner ---------------------------------// 62 63 class VISIBILITY_HIDDEN DAGCombiner { 64 SelectionDAG &DAG; 65 TargetLowering &TLI; 66 bool AfterLegalize; 67 68 // Worklist of all of the nodes that need to be simplified. 69 std::vector<SDNode*> WorkList; 70 71 // AA - Used for DAG load/store alias analysis. 72 AliasAnalysis &AA; 73 74 /// AddUsersToWorkList - When an instruction is simplified, add all users of 75 /// the instruction to the work lists because they might get more simplified 76 /// now. 77 /// 78 void AddUsersToWorkList(SDNode *N) { 79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 80 UI != UE; ++UI) 81 AddToWorkList(UI->getUser()); 82 } 83 84 /// visit - call the node-specific routine that knows how to fold each 85 /// particular type of node. 86 SDOperand visit(SDNode *N); 87 88 public: 89 /// AddToWorkList - Add to the work list making sure it's instance is at the 90 /// the back (next to be processed.) 91 void AddToWorkList(SDNode *N) { 92 removeFromWorkList(N); 93 WorkList.push_back(N); 94 } 95 96 /// removeFromWorkList - remove all instances of N from the worklist. 97 /// 98 void removeFromWorkList(SDNode *N) { 99 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 100 WorkList.end()); 101 } 102 103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 104 bool AddTo = true); 105 106 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 107 return CombineTo(N, &Res, 1, AddTo); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 111 bool AddTo = true) { 112 SDOperand To[] = { Res0, Res1 }; 113 return CombineTo(N, To, 2, AddTo); 114 } 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDOperand Op) { 122 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 123 return SimplifyDemandedBits(Op, Demanded); 124 } 125 126 bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded); 127 128 bool CombineToPreIndexedLoadStore(SDNode *N); 129 bool CombineToPostIndexedLoadStore(SDNode *N); 130 131 132 /// combine - call the node-specific routine that knows how to fold each 133 /// particular type of node. If that doesn't do anything, try the 134 /// target-specific DAG combines. 135 SDOperand combine(SDNode *N); 136 137 // Visitation implementation - Implement dag node combining for different 138 // node types. The semantics are as follows: 139 // Return Value: 140 // SDOperand.Val == 0 - No change was made 141 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 142 // otherwise - N should be replaced by the returned Operand. 143 // 144 SDOperand visitTokenFactor(SDNode *N); 145 SDOperand visitMERGE_VALUES(SDNode *N); 146 SDOperand visitADD(SDNode *N); 147 SDOperand visitSUB(SDNode *N); 148 SDOperand visitADDC(SDNode *N); 149 SDOperand visitADDE(SDNode *N); 150 SDOperand visitMUL(SDNode *N); 151 SDOperand visitSDIV(SDNode *N); 152 SDOperand visitUDIV(SDNode *N); 153 SDOperand visitSREM(SDNode *N); 154 SDOperand visitUREM(SDNode *N); 155 SDOperand visitMULHU(SDNode *N); 156 SDOperand visitMULHS(SDNode *N); 157 SDOperand visitSMUL_LOHI(SDNode *N); 158 SDOperand visitUMUL_LOHI(SDNode *N); 159 SDOperand visitSDIVREM(SDNode *N); 160 SDOperand visitUDIVREM(SDNode *N); 161 SDOperand visitAND(SDNode *N); 162 SDOperand visitOR(SDNode *N); 163 SDOperand visitXOR(SDNode *N); 164 SDOperand SimplifyVBinOp(SDNode *N); 165 SDOperand visitSHL(SDNode *N); 166 SDOperand visitSRA(SDNode *N); 167 SDOperand visitSRL(SDNode *N); 168 SDOperand visitCTLZ(SDNode *N); 169 SDOperand visitCTTZ(SDNode *N); 170 SDOperand visitCTPOP(SDNode *N); 171 SDOperand visitSELECT(SDNode *N); 172 SDOperand visitSELECT_CC(SDNode *N); 173 SDOperand visitSETCC(SDNode *N); 174 SDOperand visitSIGN_EXTEND(SDNode *N); 175 SDOperand visitZERO_EXTEND(SDNode *N); 176 SDOperand visitANY_EXTEND(SDNode *N); 177 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 178 SDOperand visitTRUNCATE(SDNode *N); 179 SDOperand visitBIT_CONVERT(SDNode *N); 180 SDOperand visitBUILD_PAIR(SDNode *N); 181 SDOperand visitFADD(SDNode *N); 182 SDOperand visitFSUB(SDNode *N); 183 SDOperand visitFMUL(SDNode *N); 184 SDOperand visitFDIV(SDNode *N); 185 SDOperand visitFREM(SDNode *N); 186 SDOperand visitFCOPYSIGN(SDNode *N); 187 SDOperand visitSINT_TO_FP(SDNode *N); 188 SDOperand visitUINT_TO_FP(SDNode *N); 189 SDOperand visitFP_TO_SINT(SDNode *N); 190 SDOperand visitFP_TO_UINT(SDNode *N); 191 SDOperand visitFP_ROUND(SDNode *N); 192 SDOperand visitFP_ROUND_INREG(SDNode *N); 193 SDOperand visitFP_EXTEND(SDNode *N); 194 SDOperand visitFNEG(SDNode *N); 195 SDOperand visitFABS(SDNode *N); 196 SDOperand visitBRCOND(SDNode *N); 197 SDOperand visitBR_CC(SDNode *N); 198 SDOperand visitLOAD(SDNode *N); 199 SDOperand visitSTORE(SDNode *N); 200 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 201 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 202 SDOperand visitBUILD_VECTOR(SDNode *N); 203 SDOperand visitCONCAT_VECTORS(SDNode *N); 204 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 205 206 SDOperand XformToShuffleWithZero(SDNode *N); 207 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 208 209 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 210 211 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 212 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 213 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 214 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 215 SDOperand N3, ISD::CondCode CC, 216 bool NotExtCompare = false); 217 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 218 ISD::CondCode Cond, bool foldBooleans = true); 219 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 220 unsigned HiOp); 221 SDOperand CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT); 222 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 223 SDOperand BuildSDIV(SDNode *N); 224 SDOperand BuildUDIV(SDNode *N); 225 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 226 SDOperand ReduceLoadWidth(SDNode *N); 227 228 SDOperand GetDemandedBits(SDOperand V, const APInt &Mask); 229 230 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 231 /// looking for aliasing nodes and adding them to the Aliases vector. 232 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 233 SmallVector<SDOperand, 8> &Aliases); 234 235 /// isAlias - Return true if there is any possibility that the two addresses 236 /// overlap. 237 bool isAlias(SDOperand Ptr1, int64_t Size1, 238 const Value *SrcValue1, int SrcValueOffset1, 239 SDOperand Ptr2, int64_t Size2, 240 const Value *SrcValue2, int SrcValueOffset2); 241 242 /// FindAliasInfo - Extracts the relevant alias information from the memory 243 /// node. Returns true if the operand was a load. 244 bool FindAliasInfo(SDNode *N, 245 SDOperand &Ptr, int64_t &Size, 246 const Value *&SrcValue, int &SrcValueOffset); 247 248 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 249 /// looking for a better chain (aliasing node.) 250 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 251 252public: 253 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 254 : DAG(D), 255 TLI(D.getTargetLoweringInfo()), 256 AfterLegalize(false), 257 AA(A) {} 258 259 /// Run - runs the dag combiner on all nodes in the work list 260 void Run(bool RunningAfterLegalize); 261 }; 262} 263 264 265namespace { 266/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 267/// nodes from the worklist. 268class VISIBILITY_HIDDEN WorkListRemover : 269 public SelectionDAG::DAGUpdateListener { 270 DAGCombiner &DC; 271public: 272 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 273 274 virtual void NodeDeleted(SDNode *N) { 275 DC.removeFromWorkList(N); 276 } 277 278 virtual void NodeUpdated(SDNode *N) { 279 // Ignore updates. 280 } 281}; 282} 283 284//===----------------------------------------------------------------------===// 285// TargetLowering::DAGCombinerInfo implementation 286//===----------------------------------------------------------------------===// 287 288void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 289 ((DAGCombiner*)DC)->AddToWorkList(N); 290} 291 292SDOperand TargetLowering::DAGCombinerInfo:: 293CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 294 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 295} 296 297SDOperand TargetLowering::DAGCombinerInfo:: 298CombineTo(SDNode *N, SDOperand Res) { 299 return ((DAGCombiner*)DC)->CombineTo(N, Res); 300} 301 302 303SDOperand TargetLowering::DAGCombinerInfo:: 304CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 305 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 306} 307 308 309//===----------------------------------------------------------------------===// 310// Helper Functions 311//===----------------------------------------------------------------------===// 312 313/// isNegatibleForFree - Return 1 if we can compute the negated form of the 314/// specified expression for the same cost as the expression itself, or 2 if we 315/// can compute the negated form more cheaply than the expression itself. 316static char isNegatibleForFree(SDOperand Op, bool AfterLegalize, 317 unsigned Depth = 0) { 318 // No compile time optimizations on this type. 319 if (Op.getValueType() == MVT::ppcf128) 320 return 0; 321 322 // fneg is removable even if it has multiple uses. 323 if (Op.getOpcode() == ISD::FNEG) return 2; 324 325 // Don't allow anything with multiple uses. 326 if (!Op.hasOneUse()) return 0; 327 328 // Don't recurse exponentially. 329 if (Depth > 6) return 0; 330 331 switch (Op.getOpcode()) { 332 default: return false; 333 case ISD::ConstantFP: 334 // Don't invert constant FP values after legalize. The negated constant 335 // isn't necessarily legal. 336 return AfterLegalize ? 0 : 1; 337 case ISD::FADD: 338 // FIXME: determine better conditions for this xform. 339 if (!UnsafeFPMath) return 0; 340 341 // -(A+B) -> -A - B 342 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 343 return V; 344 // -(A+B) -> -B - A 345 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 346 case ISD::FSUB: 347 // We can't turn -(A-B) into B-A when we honor signed zeros. 348 if (!UnsafeFPMath) return 0; 349 350 // -(A-B) -> B-A 351 return 1; 352 353 case ISD::FMUL: 354 case ISD::FDIV: 355 if (HonorSignDependentRoundingFPMath()) return 0; 356 357 // -(X*Y) -> (-X * Y) or (X*-Y) 358 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 359 return V; 360 361 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 362 363 case ISD::FP_EXTEND: 364 case ISD::FP_ROUND: 365 case ISD::FSIN: 366 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 367 } 368} 369 370/// GetNegatedExpression - If isNegatibleForFree returns true, this function 371/// returns the newly negated expression. 372static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 373 bool AfterLegalize, unsigned Depth = 0) { 374 // fneg is removable even if it has multiple uses. 375 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 376 377 // Don't allow anything with multiple uses. 378 assert(Op.hasOneUse() && "Unknown reuse!"); 379 380 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 381 switch (Op.getOpcode()) { 382 default: assert(0 && "Unknown code"); 383 case ISD::ConstantFP: { 384 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 385 V.changeSign(); 386 return DAG.getConstantFP(V, Op.getValueType()); 387 } 388 case ISD::FADD: 389 // FIXME: determine better conditions for this xform. 390 assert(UnsafeFPMath); 391 392 // -(A+B) -> -A - B 393 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 394 return DAG.getNode(ISD::FSUB, Op.getValueType(), 395 GetNegatedExpression(Op.getOperand(0), DAG, 396 AfterLegalize, Depth+1), 397 Op.getOperand(1)); 398 // -(A+B) -> -B - A 399 return DAG.getNode(ISD::FSUB, Op.getValueType(), 400 GetNegatedExpression(Op.getOperand(1), DAG, 401 AfterLegalize, Depth+1), 402 Op.getOperand(0)); 403 case ISD::FSUB: 404 // We can't turn -(A-B) into B-A when we honor signed zeros. 405 assert(UnsafeFPMath); 406 407 // -(0-B) -> B 408 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 409 if (N0CFP->getValueAPF().isZero()) 410 return Op.getOperand(1); 411 412 // -(A-B) -> B-A 413 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 414 Op.getOperand(0)); 415 416 case ISD::FMUL: 417 case ISD::FDIV: 418 assert(!HonorSignDependentRoundingFPMath()); 419 420 // -(X*Y) -> -X * Y 421 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 422 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 423 GetNegatedExpression(Op.getOperand(0), DAG, 424 AfterLegalize, Depth+1), 425 Op.getOperand(1)); 426 427 // -(X*Y) -> X * -Y 428 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 429 Op.getOperand(0), 430 GetNegatedExpression(Op.getOperand(1), DAG, 431 AfterLegalize, Depth+1)); 432 433 case ISD::FP_EXTEND: 434 case ISD::FSIN: 435 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 436 GetNegatedExpression(Op.getOperand(0), DAG, 437 AfterLegalize, Depth+1)); 438 case ISD::FP_ROUND: 439 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 440 GetNegatedExpression(Op.getOperand(0), DAG, 441 AfterLegalize, Depth+1), 442 Op.getOperand(1)); 443 } 444} 445 446 447// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 448// that selects between the values 1 and 0, making it equivalent to a setcc. 449// Also, set the incoming LHS, RHS, and CC references to the appropriate 450// nodes based on the type of node we are checking. This simplifies life a 451// bit for the callers. 452static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 453 SDOperand &CC) { 454 if (N.getOpcode() == ISD::SETCC) { 455 LHS = N.getOperand(0); 456 RHS = N.getOperand(1); 457 CC = N.getOperand(2); 458 return true; 459 } 460 if (N.getOpcode() == ISD::SELECT_CC && 461 N.getOperand(2).getOpcode() == ISD::Constant && 462 N.getOperand(3).getOpcode() == ISD::Constant && 463 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 464 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 465 LHS = N.getOperand(0); 466 RHS = N.getOperand(1); 467 CC = N.getOperand(4); 468 return true; 469 } 470 return false; 471} 472 473// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 474// one use. If this is true, it allows the users to invert the operation for 475// free when it is profitable to do so. 476static bool isOneUseSetCC(SDOperand N) { 477 SDOperand N0, N1, N2; 478 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 479 return true; 480 return false; 481} 482 483SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 484 MVT::ValueType VT = N0.getValueType(); 485 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 486 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 487 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 488 if (isa<ConstantSDNode>(N1)) { 489 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 490 AddToWorkList(OpNode.Val); 491 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 492 } else if (N0.hasOneUse()) { 493 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 494 AddToWorkList(OpNode.Val); 495 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 496 } 497 } 498 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 499 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 500 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 501 if (isa<ConstantSDNode>(N0)) { 502 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 503 AddToWorkList(OpNode.Val); 504 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 505 } else if (N1.hasOneUse()) { 506 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 507 AddToWorkList(OpNode.Val); 508 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 509 } 510 } 511 return SDOperand(); 512} 513 514SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 515 bool AddTo) { 516 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 517 ++NodesCombined; 518 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 519 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 520 DOUT << " and " << NumTo-1 << " other values\n"; 521 WorkListRemover DeadNodes(*this); 522 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 523 524 if (AddTo) { 525 // Push the new nodes and any users onto the worklist 526 for (unsigned i = 0, e = NumTo; i != e; ++i) { 527 AddToWorkList(To[i].Val); 528 AddUsersToWorkList(To[i].Val); 529 } 530 } 531 532 // Nodes can be reintroduced into the worklist. Make sure we do not 533 // process a node that has been replaced. 534 removeFromWorkList(N); 535 536 // Finally, since the node is now dead, remove it from the graph. 537 DAG.DeleteNode(N); 538 return SDOperand(N, 0); 539} 540 541/// SimplifyDemandedBits - Check the specified integer node value to see if 542/// it can be simplified or if things it uses can be simplified by bit 543/// propagation. If so, return true. 544bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) { 545 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 546 APInt KnownZero, KnownOne; 547 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 548 return false; 549 550 // Revisit the node. 551 AddToWorkList(Op.Val); 552 553 // Replace the old value with the new one. 554 ++NodesCombined; 555 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 556 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 557 DOUT << '\n'; 558 559 // Replace all uses. If any nodes become isomorphic to other nodes and 560 // are deleted, make sure to remove them from our worklist. 561 WorkListRemover DeadNodes(*this); 562 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 563 564 // Push the new node and any (possibly new) users onto the worklist. 565 AddToWorkList(TLO.New.Val); 566 AddUsersToWorkList(TLO.New.Val); 567 568 // Finally, if the node is now dead, remove it from the graph. The node 569 // may not be dead if the replacement process recursively simplified to 570 // something else needing this node. 571 if (TLO.Old.Val->use_empty()) { 572 removeFromWorkList(TLO.Old.Val); 573 574 // If the operands of this node are only used by the node, they will now 575 // be dead. Make sure to visit them first to delete dead nodes early. 576 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 577 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 578 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 579 580 DAG.DeleteNode(TLO.Old.Val); 581 } 582 return true; 583} 584 585//===----------------------------------------------------------------------===// 586// Main DAG Combiner implementation 587//===----------------------------------------------------------------------===// 588 589void DAGCombiner::Run(bool RunningAfterLegalize) { 590 // set the instance variable, so that the various visit routines may use it. 591 AfterLegalize = RunningAfterLegalize; 592 593 // Add all the dag nodes to the worklist. 594 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 595 E = DAG.allnodes_end(); I != E; ++I) 596 WorkList.push_back(I); 597 598 // Create a dummy node (which is not added to allnodes), that adds a reference 599 // to the root node, preventing it from being deleted, and tracking any 600 // changes of the root. 601 HandleSDNode Dummy(DAG.getRoot()); 602 603 // The root of the dag may dangle to deleted nodes until the dag combiner is 604 // done. Set it to null to avoid confusion. 605 DAG.setRoot(SDOperand()); 606 607 // while the worklist isn't empty, inspect the node on the end of it and 608 // try and combine it. 609 while (!WorkList.empty()) { 610 SDNode *N = WorkList.back(); 611 WorkList.pop_back(); 612 613 // If N has no uses, it is dead. Make sure to revisit all N's operands once 614 // N is deleted from the DAG, since they too may now be dead or may have a 615 // reduced number of uses, allowing other xforms. 616 if (N->use_empty() && N != &Dummy) { 617 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 618 AddToWorkList(N->getOperand(i).Val); 619 620 DAG.DeleteNode(N); 621 continue; 622 } 623 624 SDOperand RV = combine(N); 625 626 if (RV.Val == 0) 627 continue; 628 629 ++NodesCombined; 630 631 // If we get back the same node we passed in, rather than a new node or 632 // zero, we know that the node must have defined multiple values and 633 // CombineTo was used. Since CombineTo takes care of the worklist 634 // mechanics for us, we have no work to do in this case. 635 if (RV.Val == N) 636 continue; 637 638 assert(N->getOpcode() != ISD::DELETED_NODE && 639 RV.Val->getOpcode() != ISD::DELETED_NODE && 640 "Node was deleted but visit returned new node!"); 641 642 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 643 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 644 DOUT << '\n'; 645 WorkListRemover DeadNodes(*this); 646 if (N->getNumValues() == RV.Val->getNumValues()) 647 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes); 648 else { 649 assert(N->getValueType(0) == RV.getValueType() && 650 N->getNumValues() == 1 && "Type mismatch"); 651 SDOperand OpV = RV; 652 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 653 } 654 655 // Push the new node and any users onto the worklist 656 AddToWorkList(RV.Val); 657 AddUsersToWorkList(RV.Val); 658 659 // Add any uses of the old node to the worklist in case this node is the 660 // last one that uses them. They may become dead after this node is 661 // deleted. 662 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 663 AddToWorkList(N->getOperand(i).Val); 664 665 // Nodes can be reintroduced into the worklist. Make sure we do not 666 // process a node that has been replaced. 667 removeFromWorkList(N); 668 669 // Finally, since the node is now dead, remove it from the graph. 670 DAG.DeleteNode(N); 671 } 672 673 // If the root changed (e.g. it was a dead load, update the root). 674 DAG.setRoot(Dummy.getValue()); 675} 676 677SDOperand DAGCombiner::visit(SDNode *N) { 678 switch(N->getOpcode()) { 679 default: break; 680 case ISD::TokenFactor: return visitTokenFactor(N); 681 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 682 case ISD::ADD: return visitADD(N); 683 case ISD::SUB: return visitSUB(N); 684 case ISD::ADDC: return visitADDC(N); 685 case ISD::ADDE: return visitADDE(N); 686 case ISD::MUL: return visitMUL(N); 687 case ISD::SDIV: return visitSDIV(N); 688 case ISD::UDIV: return visitUDIV(N); 689 case ISD::SREM: return visitSREM(N); 690 case ISD::UREM: return visitUREM(N); 691 case ISD::MULHU: return visitMULHU(N); 692 case ISD::MULHS: return visitMULHS(N); 693 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 694 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 695 case ISD::SDIVREM: return visitSDIVREM(N); 696 case ISD::UDIVREM: return visitUDIVREM(N); 697 case ISD::AND: return visitAND(N); 698 case ISD::OR: return visitOR(N); 699 case ISD::XOR: return visitXOR(N); 700 case ISD::SHL: return visitSHL(N); 701 case ISD::SRA: return visitSRA(N); 702 case ISD::SRL: return visitSRL(N); 703 case ISD::CTLZ: return visitCTLZ(N); 704 case ISD::CTTZ: return visitCTTZ(N); 705 case ISD::CTPOP: return visitCTPOP(N); 706 case ISD::SELECT: return visitSELECT(N); 707 case ISD::SELECT_CC: return visitSELECT_CC(N); 708 case ISD::SETCC: return visitSETCC(N); 709 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 710 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 711 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 712 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 713 case ISD::TRUNCATE: return visitTRUNCATE(N); 714 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 715 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 716 case ISD::FADD: return visitFADD(N); 717 case ISD::FSUB: return visitFSUB(N); 718 case ISD::FMUL: return visitFMUL(N); 719 case ISD::FDIV: return visitFDIV(N); 720 case ISD::FREM: return visitFREM(N); 721 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 722 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 723 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 724 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 725 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 726 case ISD::FP_ROUND: return visitFP_ROUND(N); 727 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 728 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 729 case ISD::FNEG: return visitFNEG(N); 730 case ISD::FABS: return visitFABS(N); 731 case ISD::BRCOND: return visitBRCOND(N); 732 case ISD::BR_CC: return visitBR_CC(N); 733 case ISD::LOAD: return visitLOAD(N); 734 case ISD::STORE: return visitSTORE(N); 735 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 736 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 737 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 738 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 739 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 740 } 741 return SDOperand(); 742} 743 744SDOperand DAGCombiner::combine(SDNode *N) { 745 746 SDOperand RV = visit(N); 747 748 // If nothing happened, try a target-specific DAG combine. 749 if (RV.Val == 0) { 750 assert(N->getOpcode() != ISD::DELETED_NODE && 751 "Node was deleted but visit returned NULL!"); 752 753 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 754 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 755 756 // Expose the DAG combiner to the target combiner impls. 757 TargetLowering::DAGCombinerInfo 758 DagCombineInfo(DAG, !AfterLegalize, false, this); 759 760 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 761 } 762 } 763 764 // If N is a commutative binary node, try commuting it to enable more 765 // sdisel CSE. 766 if (RV.Val == 0 && 767 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 768 N->getNumValues() == 1) { 769 SDOperand N0 = N->getOperand(0); 770 SDOperand N1 = N->getOperand(1); 771 // Constant operands are canonicalized to RHS. 772 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 773 SDOperand Ops[] = { N1, N0 }; 774 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 775 Ops, 2); 776 if (CSENode) 777 return SDOperand(CSENode, 0); 778 } 779 } 780 781 return RV; 782} 783 784/// getInputChainForNode - Given a node, return its input chain if it has one, 785/// otherwise return a null sd operand. 786static SDOperand getInputChainForNode(SDNode *N) { 787 if (unsigned NumOps = N->getNumOperands()) { 788 if (N->getOperand(0).getValueType() == MVT::Other) 789 return N->getOperand(0); 790 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 791 return N->getOperand(NumOps-1); 792 for (unsigned i = 1; i < NumOps-1; ++i) 793 if (N->getOperand(i).getValueType() == MVT::Other) 794 return N->getOperand(i); 795 } 796 return SDOperand(0, 0); 797} 798 799SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 800 // If N has two operands, where one has an input chain equal to the other, 801 // the 'other' chain is redundant. 802 if (N->getNumOperands() == 2) { 803 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 804 return N->getOperand(0); 805 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 806 return N->getOperand(1); 807 } 808 809 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 810 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 811 SmallPtrSet<SDNode*, 16> SeenOps; 812 bool Changed = false; // If we should replace this token factor. 813 814 // Start out with this token factor. 815 TFs.push_back(N); 816 817 // Iterate through token factors. The TFs grows when new token factors are 818 // encountered. 819 for (unsigned i = 0; i < TFs.size(); ++i) { 820 SDNode *TF = TFs[i]; 821 822 // Check each of the operands. 823 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 824 SDOperand Op = TF->getOperand(i); 825 826 switch (Op.getOpcode()) { 827 case ISD::EntryToken: 828 // Entry tokens don't need to be added to the list. They are 829 // rededundant. 830 Changed = true; 831 break; 832 833 case ISD::TokenFactor: 834 if ((CombinerAA || Op.hasOneUse()) && 835 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 836 // Queue up for processing. 837 TFs.push_back(Op.Val); 838 // Clean up in case the token factor is removed. 839 AddToWorkList(Op.Val); 840 Changed = true; 841 break; 842 } 843 // Fall thru 844 845 default: 846 // Only add if it isn't already in the list. 847 if (SeenOps.insert(Op.Val)) 848 Ops.push_back(Op); 849 else 850 Changed = true; 851 break; 852 } 853 } 854 } 855 856 SDOperand Result; 857 858 // If we've change things around then replace token factor. 859 if (Changed) { 860 if (Ops.empty()) { 861 // The entry token is the only possible outcome. 862 Result = DAG.getEntryNode(); 863 } else { 864 // New and improved token factor. 865 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 866 } 867 868 // Don't add users to work list. 869 return CombineTo(N, Result, false); 870 } 871 872 return Result; 873} 874 875/// MERGE_VALUES can always be eliminated. 876SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) { 877 WorkListRemover DeadNodes(*this); 878 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 879 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i), 880 &DeadNodes); 881 removeFromWorkList(N); 882 DAG.DeleteNode(N); 883 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 884} 885 886 887static 888SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 889 MVT::ValueType VT = N0.getValueType(); 890 SDOperand N00 = N0.getOperand(0); 891 SDOperand N01 = N0.getOperand(1); 892 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 893 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 894 isa<ConstantSDNode>(N00.getOperand(1))) { 895 N0 = DAG.getNode(ISD::ADD, VT, 896 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 897 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 898 return DAG.getNode(ISD::ADD, VT, N0, N1); 899 } 900 return SDOperand(); 901} 902 903static 904SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 905 SelectionDAG &DAG) { 906 MVT::ValueType VT = N->getValueType(0); 907 unsigned Opc = N->getOpcode(); 908 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 909 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 910 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 911 ISD::CondCode CC = ISD::SETCC_INVALID; 912 if (isSlctCC) 913 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 914 else { 915 SDOperand CCOp = Slct.getOperand(0); 916 if (CCOp.getOpcode() == ISD::SETCC) 917 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 918 } 919 920 bool DoXform = false; 921 bool InvCC = false; 922 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 923 "Bad input!"); 924 if (LHS.getOpcode() == ISD::Constant && 925 cast<ConstantSDNode>(LHS)->isNullValue()) 926 DoXform = true; 927 else if (CC != ISD::SETCC_INVALID && 928 RHS.getOpcode() == ISD::Constant && 929 cast<ConstantSDNode>(RHS)->isNullValue()) { 930 std::swap(LHS, RHS); 931 SDOperand Op0 = Slct.getOperand(0); 932 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() 933 : Op0.getOperand(0).getValueType()); 934 CC = ISD::getSetCCInverse(CC, isInt); 935 DoXform = true; 936 InvCC = true; 937 } 938 939 if (DoXform) { 940 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 941 if (isSlctCC) 942 return DAG.getSelectCC(OtherOp, Result, 943 Slct.getOperand(0), Slct.getOperand(1), CC); 944 SDOperand CCOp = Slct.getOperand(0); 945 if (InvCC) 946 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 947 CCOp.getOperand(1), CC); 948 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 949 } 950 return SDOperand(); 951} 952 953SDOperand DAGCombiner::visitADD(SDNode *N) { 954 SDOperand N0 = N->getOperand(0); 955 SDOperand N1 = N->getOperand(1); 956 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 957 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 958 MVT::ValueType VT = N0.getValueType(); 959 960 // fold vector ops 961 if (MVT::isVector(VT)) { 962 SDOperand FoldedVOp = SimplifyVBinOp(N); 963 if (FoldedVOp.Val) return FoldedVOp; 964 } 965 966 // fold (add x, undef) -> undef 967 if (N0.getOpcode() == ISD::UNDEF) 968 return N0; 969 if (N1.getOpcode() == ISD::UNDEF) 970 return N1; 971 // fold (add c1, c2) -> c1+c2 972 if (N0C && N1C) 973 return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT); 974 // canonicalize constant to RHS 975 if (N0C && !N1C) 976 return DAG.getNode(ISD::ADD, VT, N1, N0); 977 // fold (add x, 0) -> x 978 if (N1C && N1C->isNullValue()) 979 return N0; 980 // fold ((c1-A)+c2) -> (c1+c2)-A 981 if (N1C && N0.getOpcode() == ISD::SUB) 982 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 983 return DAG.getNode(ISD::SUB, VT, 984 DAG.getConstant(N1C->getAPIntValue()+ 985 N0C->getAPIntValue(), VT), 986 N0.getOperand(1)); 987 // reassociate add 988 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 989 if (RADD.Val != 0) 990 return RADD; 991 // fold ((0-A) + B) -> B-A 992 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 993 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 994 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 995 // fold (A + (0-B)) -> A-B 996 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 997 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 998 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 999 // fold (A+(B-A)) -> B 1000 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1001 return N1.getOperand(0); 1002 1003 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 1004 return SDOperand(N, 0); 1005 1006 // fold (a+b) -> (a|b) iff a and b share no bits. 1007 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 1008 APInt LHSZero, LHSOne; 1009 APInt RHSZero, RHSOne; 1010 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 1011 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1012 if (LHSZero.getBoolValue()) { 1013 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1014 1015 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1016 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1017 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1018 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1019 return DAG.getNode(ISD::OR, VT, N0, N1); 1020 } 1021 } 1022 1023 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1024 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 1025 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 1026 if (Result.Val) return Result; 1027 } 1028 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 1029 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 1030 if (Result.Val) return Result; 1031 } 1032 1033 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1034 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 1035 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 1036 if (Result.Val) return Result; 1037 } 1038 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1039 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1040 if (Result.Val) return Result; 1041 } 1042 1043 return SDOperand(); 1044} 1045 1046SDOperand DAGCombiner::visitADDC(SDNode *N) { 1047 SDOperand N0 = N->getOperand(0); 1048 SDOperand N1 = N->getOperand(1); 1049 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1050 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1051 MVT::ValueType VT = N0.getValueType(); 1052 1053 // If the flag result is dead, turn this into an ADD. 1054 if (N->hasNUsesOfValue(0, 1)) 1055 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1056 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1057 1058 // canonicalize constant to RHS. 1059 if (N0C && !N1C) { 1060 SDOperand Ops[] = { N1, N0 }; 1061 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1062 } 1063 1064 // fold (addc x, 0) -> x + no carry out 1065 if (N1C && N1C->isNullValue()) 1066 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1067 1068 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1069 APInt LHSZero, LHSOne; 1070 APInt RHSZero, RHSOne; 1071 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 1072 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1073 if (LHSZero.getBoolValue()) { 1074 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1075 1076 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1077 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1078 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1079 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1080 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1081 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1082 } 1083 1084 return SDOperand(); 1085} 1086 1087SDOperand DAGCombiner::visitADDE(SDNode *N) { 1088 SDOperand N0 = N->getOperand(0); 1089 SDOperand N1 = N->getOperand(1); 1090 SDOperand CarryIn = N->getOperand(2); 1091 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1092 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1093 //MVT::ValueType VT = N0.getValueType(); 1094 1095 // canonicalize constant to RHS 1096 if (N0C && !N1C) { 1097 SDOperand Ops[] = { N1, N0, CarryIn }; 1098 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1099 } 1100 1101 // fold (adde x, y, false) -> (addc x, y) 1102 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1103 SDOperand Ops[] = { N1, N0 }; 1104 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1105 } 1106 1107 return SDOperand(); 1108} 1109 1110 1111 1112SDOperand DAGCombiner::visitSUB(SDNode *N) { 1113 SDOperand N0 = N->getOperand(0); 1114 SDOperand N1 = N->getOperand(1); 1115 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1116 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1117 MVT::ValueType VT = N0.getValueType(); 1118 1119 // fold vector ops 1120 if (MVT::isVector(VT)) { 1121 SDOperand FoldedVOp = SimplifyVBinOp(N); 1122 if (FoldedVOp.Val) return FoldedVOp; 1123 } 1124 1125 // fold (sub x, x) -> 0 1126 if (N0 == N1) 1127 return DAG.getConstant(0, N->getValueType(0)); 1128 // fold (sub c1, c2) -> c1-c2 1129 if (N0C && N1C) 1130 return DAG.getNode(ISD::SUB, VT, N0, N1); 1131 // fold (sub x, c) -> (add x, -c) 1132 if (N1C) 1133 return DAG.getNode(ISD::ADD, VT, N0, 1134 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1135 // fold (A+B)-A -> B 1136 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1137 return N0.getOperand(1); 1138 // fold (A+B)-B -> A 1139 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1140 return N0.getOperand(0); 1141 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1142 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1143 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1144 if (Result.Val) return Result; 1145 } 1146 // If either operand of a sub is undef, the result is undef 1147 if (N0.getOpcode() == ISD::UNDEF) 1148 return N0; 1149 if (N1.getOpcode() == ISD::UNDEF) 1150 return N1; 1151 1152 return SDOperand(); 1153} 1154 1155SDOperand DAGCombiner::visitMUL(SDNode *N) { 1156 SDOperand N0 = N->getOperand(0); 1157 SDOperand N1 = N->getOperand(1); 1158 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1159 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1160 MVT::ValueType VT = N0.getValueType(); 1161 1162 // fold vector ops 1163 if (MVT::isVector(VT)) { 1164 SDOperand FoldedVOp = SimplifyVBinOp(N); 1165 if (FoldedVOp.Val) return FoldedVOp; 1166 } 1167 1168 // fold (mul x, undef) -> 0 1169 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1170 return DAG.getConstant(0, VT); 1171 // fold (mul c1, c2) -> c1*c2 1172 if (N0C && N1C) 1173 return DAG.getNode(ISD::MUL, VT, N0, N1); 1174 // canonicalize constant to RHS 1175 if (N0C && !N1C) 1176 return DAG.getNode(ISD::MUL, VT, N1, N0); 1177 // fold (mul x, 0) -> 0 1178 if (N1C && N1C->isNullValue()) 1179 return N1; 1180 // fold (mul x, -1) -> 0-x 1181 if (N1C && N1C->isAllOnesValue()) 1182 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1183 // fold (mul x, (1 << c)) -> x << c 1184 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1185 return DAG.getNode(ISD::SHL, VT, N0, 1186 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1187 TLI.getShiftAmountTy())); 1188 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1189 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1190 // FIXME: If the input is something that is easily negated (e.g. a 1191 // single-use add), we should put the negate there. 1192 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1193 DAG.getNode(ISD::SHL, VT, N0, 1194 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1195 TLI.getShiftAmountTy()))); 1196 } 1197 1198 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1199 if (N1C && N0.getOpcode() == ISD::SHL && 1200 isa<ConstantSDNode>(N0.getOperand(1))) { 1201 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1202 AddToWorkList(C3.Val); 1203 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1204 } 1205 1206 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1207 // use. 1208 { 1209 SDOperand Sh(0,0), Y(0,0); 1210 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1211 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1212 N0.Val->hasOneUse()) { 1213 Sh = N0; Y = N1; 1214 } else if (N1.getOpcode() == ISD::SHL && 1215 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1216 Sh = N1; Y = N0; 1217 } 1218 if (Sh.Val) { 1219 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1220 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1221 } 1222 } 1223 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1224 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1225 isa<ConstantSDNode>(N0.getOperand(1))) { 1226 return DAG.getNode(ISD::ADD, VT, 1227 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1228 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1229 } 1230 1231 // reassociate mul 1232 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1233 if (RMUL.Val != 0) 1234 return RMUL; 1235 1236 return SDOperand(); 1237} 1238 1239SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1240 SDOperand N0 = N->getOperand(0); 1241 SDOperand N1 = N->getOperand(1); 1242 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1243 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1244 MVT::ValueType VT = N->getValueType(0); 1245 1246 // fold vector ops 1247 if (MVT::isVector(VT)) { 1248 SDOperand FoldedVOp = SimplifyVBinOp(N); 1249 if (FoldedVOp.Val) return FoldedVOp; 1250 } 1251 1252 // fold (sdiv c1, c2) -> c1/c2 1253 if (N0C && N1C && !N1C->isNullValue()) 1254 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1255 // fold (sdiv X, 1) -> X 1256 if (N1C && N1C->getSignExtended() == 1LL) 1257 return N0; 1258 // fold (sdiv X, -1) -> 0-X 1259 if (N1C && N1C->isAllOnesValue()) 1260 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1261 // If we know the sign bits of both operands are zero, strength reduce to a 1262 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1263 if (!MVT::isVector(VT)) { 1264 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1265 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1266 } 1267 // fold (sdiv X, pow2) -> simple ops after legalize 1268 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1269 (isPowerOf2_64(N1C->getSignExtended()) || 1270 isPowerOf2_64(-N1C->getSignExtended()))) { 1271 // If dividing by powers of two is cheap, then don't perform the following 1272 // fold. 1273 if (TLI.isPow2DivCheap()) 1274 return SDOperand(); 1275 int64_t pow2 = N1C->getSignExtended(); 1276 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1277 unsigned lg2 = Log2_64(abs2); 1278 // Splat the sign bit into the register 1279 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1280 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1281 TLI.getShiftAmountTy())); 1282 AddToWorkList(SGN.Val); 1283 // Add (N0 < 0) ? abs2 - 1 : 0; 1284 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1285 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1286 TLI.getShiftAmountTy())); 1287 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1288 AddToWorkList(SRL.Val); 1289 AddToWorkList(ADD.Val); // Divide by pow2 1290 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1291 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1292 // If we're dividing by a positive value, we're done. Otherwise, we must 1293 // negate the result. 1294 if (pow2 > 0) 1295 return SRA; 1296 AddToWorkList(SRA.Val); 1297 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1298 } 1299 // if integer divide is expensive and we satisfy the requirements, emit an 1300 // alternate sequence. 1301 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1302 !TLI.isIntDivCheap()) { 1303 SDOperand Op = BuildSDIV(N); 1304 if (Op.Val) return Op; 1305 } 1306 1307 // undef / X -> 0 1308 if (N0.getOpcode() == ISD::UNDEF) 1309 return DAG.getConstant(0, VT); 1310 // X / undef -> undef 1311 if (N1.getOpcode() == ISD::UNDEF) 1312 return N1; 1313 1314 return SDOperand(); 1315} 1316 1317SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1318 SDOperand N0 = N->getOperand(0); 1319 SDOperand N1 = N->getOperand(1); 1320 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1321 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1322 MVT::ValueType VT = N->getValueType(0); 1323 1324 // fold vector ops 1325 if (MVT::isVector(VT)) { 1326 SDOperand FoldedVOp = SimplifyVBinOp(N); 1327 if (FoldedVOp.Val) return FoldedVOp; 1328 } 1329 1330 // fold (udiv c1, c2) -> c1/c2 1331 if (N0C && N1C && !N1C->isNullValue()) 1332 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1333 // fold (udiv x, (1 << c)) -> x >>u c 1334 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1335 return DAG.getNode(ISD::SRL, VT, N0, 1336 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1337 TLI.getShiftAmountTy())); 1338 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1339 if (N1.getOpcode() == ISD::SHL) { 1340 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1341 if (SHC->getAPIntValue().isPowerOf2()) { 1342 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1343 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1344 DAG.getConstant(SHC->getAPIntValue() 1345 .logBase2(), 1346 ADDVT)); 1347 AddToWorkList(Add.Val); 1348 return DAG.getNode(ISD::SRL, VT, N0, Add); 1349 } 1350 } 1351 } 1352 // fold (udiv x, c) -> alternate 1353 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1354 SDOperand Op = BuildUDIV(N); 1355 if (Op.Val) return Op; 1356 } 1357 1358 // undef / X -> 0 1359 if (N0.getOpcode() == ISD::UNDEF) 1360 return DAG.getConstant(0, VT); 1361 // X / undef -> undef 1362 if (N1.getOpcode() == ISD::UNDEF) 1363 return N1; 1364 1365 return SDOperand(); 1366} 1367 1368SDOperand DAGCombiner::visitSREM(SDNode *N) { 1369 SDOperand N0 = N->getOperand(0); 1370 SDOperand N1 = N->getOperand(1); 1371 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1372 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1373 MVT::ValueType VT = N->getValueType(0); 1374 1375 // fold (srem c1, c2) -> c1%c2 1376 if (N0C && N1C && !N1C->isNullValue()) 1377 return DAG.getNode(ISD::SREM, VT, N0, N1); 1378 // If we know the sign bits of both operands are zero, strength reduce to a 1379 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1380 if (!MVT::isVector(VT)) { 1381 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1382 return DAG.getNode(ISD::UREM, VT, N0, N1); 1383 } 1384 1385 // If X/C can be simplified by the division-by-constant logic, lower 1386 // X%C to the equivalent of X-X/C*C. 1387 if (N1C && !N1C->isNullValue()) { 1388 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1389 AddToWorkList(Div.Val); 1390 SDOperand OptimizedDiv = combine(Div.Val); 1391 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1392 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1393 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1394 AddToWorkList(Mul.Val); 1395 return Sub; 1396 } 1397 } 1398 1399 // undef % X -> 0 1400 if (N0.getOpcode() == ISD::UNDEF) 1401 return DAG.getConstant(0, VT); 1402 // X % undef -> undef 1403 if (N1.getOpcode() == ISD::UNDEF) 1404 return N1; 1405 1406 return SDOperand(); 1407} 1408 1409SDOperand DAGCombiner::visitUREM(SDNode *N) { 1410 SDOperand N0 = N->getOperand(0); 1411 SDOperand N1 = N->getOperand(1); 1412 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1414 MVT::ValueType VT = N->getValueType(0); 1415 1416 // fold (urem c1, c2) -> c1%c2 1417 if (N0C && N1C && !N1C->isNullValue()) 1418 return DAG.getNode(ISD::UREM, VT, N0, N1); 1419 // fold (urem x, pow2) -> (and x, pow2-1) 1420 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1421 return DAG.getNode(ISD::AND, VT, N0, 1422 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1423 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1424 if (N1.getOpcode() == ISD::SHL) { 1425 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1426 if (SHC->getAPIntValue().isPowerOf2()) { 1427 SDOperand Add = 1428 DAG.getNode(ISD::ADD, VT, N1, 1429 DAG.getConstant(APInt::getAllOnesValue(MVT::getSizeInBits(VT)), 1430 VT)); 1431 AddToWorkList(Add.Val); 1432 return DAG.getNode(ISD::AND, VT, N0, Add); 1433 } 1434 } 1435 } 1436 1437 // If X/C can be simplified by the division-by-constant logic, lower 1438 // X%C to the equivalent of X-X/C*C. 1439 if (N1C && !N1C->isNullValue()) { 1440 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1441 SDOperand OptimizedDiv = combine(Div.Val); 1442 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1443 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1444 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1445 AddToWorkList(Mul.Val); 1446 return Sub; 1447 } 1448 } 1449 1450 // undef % X -> 0 1451 if (N0.getOpcode() == ISD::UNDEF) 1452 return DAG.getConstant(0, VT); 1453 // X % undef -> undef 1454 if (N1.getOpcode() == ISD::UNDEF) 1455 return N1; 1456 1457 return SDOperand(); 1458} 1459 1460SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1461 SDOperand N0 = N->getOperand(0); 1462 SDOperand N1 = N->getOperand(1); 1463 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1464 MVT::ValueType VT = N->getValueType(0); 1465 1466 // fold (mulhs x, 0) -> 0 1467 if (N1C && N1C->isNullValue()) 1468 return N1; 1469 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1470 if (N1C && N1C->getAPIntValue() == 1) 1471 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1472 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1473 TLI.getShiftAmountTy())); 1474 // fold (mulhs x, undef) -> 0 1475 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1476 return DAG.getConstant(0, VT); 1477 1478 return SDOperand(); 1479} 1480 1481SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1482 SDOperand N0 = N->getOperand(0); 1483 SDOperand N1 = N->getOperand(1); 1484 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1485 MVT::ValueType VT = N->getValueType(0); 1486 1487 // fold (mulhu x, 0) -> 0 1488 if (N1C && N1C->isNullValue()) 1489 return N1; 1490 // fold (mulhu x, 1) -> 0 1491 if (N1C && N1C->getAPIntValue() == 1) 1492 return DAG.getConstant(0, N0.getValueType()); 1493 // fold (mulhu x, undef) -> 0 1494 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1495 return DAG.getConstant(0, VT); 1496 1497 return SDOperand(); 1498} 1499 1500/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1501/// compute two values. LoOp and HiOp give the opcodes for the two computations 1502/// that are being performed. Return true if a simplification was made. 1503/// 1504SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1505 unsigned HiOp) { 1506 // If the high half is not needed, just compute the low half. 1507 bool HiExists = N->hasAnyUseOfValue(1); 1508 if (!HiExists && 1509 (!AfterLegalize || 1510 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1511 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1512 N->getNumOperands()); 1513 return CombineTo(N, Res, Res); 1514 } 1515 1516 // If the low half is not needed, just compute the high half. 1517 bool LoExists = N->hasAnyUseOfValue(0); 1518 if (!LoExists && 1519 (!AfterLegalize || 1520 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1521 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1522 N->getNumOperands()); 1523 return CombineTo(N, Res, Res); 1524 } 1525 1526 // If both halves are used, return as it is. 1527 if (LoExists && HiExists) 1528 return SDOperand(); 1529 1530 // If the two computed results can be simplified separately, separate them. 1531 if (LoExists) { 1532 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1533 N->op_begin(), N->getNumOperands()); 1534 AddToWorkList(Lo.Val); 1535 SDOperand LoOpt = combine(Lo.Val); 1536 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1537 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) 1538 return CombineTo(N, LoOpt, LoOpt); 1539 } 1540 1541 if (HiExists) { 1542 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1543 N->op_begin(), N->getNumOperands()); 1544 AddToWorkList(Hi.Val); 1545 SDOperand HiOpt = combine(Hi.Val); 1546 if (HiOpt.Val && HiOpt != Hi && 1547 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) 1548 return CombineTo(N, HiOpt, HiOpt); 1549 } 1550 return SDOperand(); 1551} 1552 1553SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1554 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1555 if (Res.Val) return Res; 1556 1557 return SDOperand(); 1558} 1559 1560SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1561 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1562 if (Res.Val) return Res; 1563 1564 return SDOperand(); 1565} 1566 1567SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1568 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1569 if (Res.Val) return Res; 1570 1571 return SDOperand(); 1572} 1573 1574SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1575 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1576 if (Res.Val) return Res; 1577 1578 return SDOperand(); 1579} 1580 1581/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1582/// two operands of the same opcode, try to simplify it. 1583SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1584 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1585 MVT::ValueType VT = N0.getValueType(); 1586 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1587 1588 // For each of OP in AND/OR/XOR: 1589 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1590 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1591 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1592 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1593 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1594 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1595 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1596 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1597 N0.getOperand(0).getValueType(), 1598 N0.getOperand(0), N1.getOperand(0)); 1599 AddToWorkList(ORNode.Val); 1600 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1601 } 1602 1603 // For each of OP in SHL/SRL/SRA/AND... 1604 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1605 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1606 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1607 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1608 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1609 N0.getOperand(1) == N1.getOperand(1)) { 1610 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1611 N0.getOperand(0).getValueType(), 1612 N0.getOperand(0), N1.getOperand(0)); 1613 AddToWorkList(ORNode.Val); 1614 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1615 } 1616 1617 return SDOperand(); 1618} 1619 1620SDOperand DAGCombiner::visitAND(SDNode *N) { 1621 SDOperand N0 = N->getOperand(0); 1622 SDOperand N1 = N->getOperand(1); 1623 SDOperand LL, LR, RL, RR, CC0, CC1; 1624 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1626 MVT::ValueType VT = N1.getValueType(); 1627 unsigned BitWidth = MVT::getSizeInBits(VT); 1628 1629 // fold vector ops 1630 if (MVT::isVector(VT)) { 1631 SDOperand FoldedVOp = SimplifyVBinOp(N); 1632 if (FoldedVOp.Val) return FoldedVOp; 1633 } 1634 1635 // fold (and x, undef) -> 0 1636 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1637 return DAG.getConstant(0, VT); 1638 // fold (and c1, c2) -> c1&c2 1639 if (N0C && N1C) 1640 return DAG.getNode(ISD::AND, VT, N0, N1); 1641 // canonicalize constant to RHS 1642 if (N0C && !N1C) 1643 return DAG.getNode(ISD::AND, VT, N1, N0); 1644 // fold (and x, -1) -> x 1645 if (N1C && N1C->isAllOnesValue()) 1646 return N0; 1647 // if (and x, c) is known to be zero, return 0 1648 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 1649 APInt::getAllOnesValue(BitWidth))) 1650 return DAG.getConstant(0, VT); 1651 // reassociate and 1652 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1653 if (RAND.Val != 0) 1654 return RAND; 1655 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1656 if (N1C && N0.getOpcode() == ISD::OR) 1657 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1658 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1659 return N1; 1660 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1661 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1662 SDOperand N0Op0 = N0.getOperand(0); 1663 APInt Mask = ~N1C->getAPIntValue(); 1664 Mask.trunc(N0Op0.getValueSizeInBits()); 1665 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1666 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1667 N0Op0); 1668 1669 // Replace uses of the AND with uses of the Zero extend node. 1670 CombineTo(N, Zext); 1671 1672 // We actually want to replace all uses of the any_extend with the 1673 // zero_extend, to avoid duplicating things. This will later cause this 1674 // AND to be folded. 1675 CombineTo(N0.Val, Zext); 1676 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1677 } 1678 } 1679 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1680 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1681 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1682 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1683 1684 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1685 MVT::isInteger(LL.getValueType())) { 1686 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1687 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1688 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1689 AddToWorkList(ORNode.Val); 1690 return DAG.getSetCC(VT, ORNode, LR, Op1); 1691 } 1692 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1693 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1694 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1695 AddToWorkList(ANDNode.Val); 1696 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1697 } 1698 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1699 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1700 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1701 AddToWorkList(ORNode.Val); 1702 return DAG.getSetCC(VT, ORNode, LR, Op1); 1703 } 1704 } 1705 // canonicalize equivalent to ll == rl 1706 if (LL == RR && LR == RL) { 1707 Op1 = ISD::getSetCCSwappedOperands(Op1); 1708 std::swap(RL, RR); 1709 } 1710 if (LL == RL && LR == RR) { 1711 bool isInteger = MVT::isInteger(LL.getValueType()); 1712 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1713 if (Result != ISD::SETCC_INVALID) 1714 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1715 } 1716 } 1717 1718 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1719 if (N0.getOpcode() == N1.getOpcode()) { 1720 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1721 if (Tmp.Val) return Tmp; 1722 } 1723 1724 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1725 // fold (and (sra)) -> (and (srl)) when possible. 1726 if (!MVT::isVector(VT) && 1727 SimplifyDemandedBits(SDOperand(N, 0))) 1728 return SDOperand(N, 0); 1729 // fold (zext_inreg (extload x)) -> (zextload x) 1730 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1731 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1732 MVT::ValueType EVT = LN0->getMemoryVT(); 1733 // If we zero all the possible extended bits, then we can turn this into 1734 // a zextload if we are running before legalize or the operation is legal. 1735 unsigned BitWidth = N1.getValueSizeInBits(); 1736 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1737 BitWidth - MVT::getSizeInBits(EVT))) && 1738 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1739 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1740 LN0->getBasePtr(), LN0->getSrcValue(), 1741 LN0->getSrcValueOffset(), EVT, 1742 LN0->isVolatile(), 1743 LN0->getAlignment()); 1744 AddToWorkList(N); 1745 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1746 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1747 } 1748 } 1749 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1750 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1751 N0.hasOneUse()) { 1752 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1753 MVT::ValueType EVT = LN0->getMemoryVT(); 1754 // If we zero all the possible extended bits, then we can turn this into 1755 // a zextload if we are running before legalize or the operation is legal. 1756 unsigned BitWidth = N1.getValueSizeInBits(); 1757 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1758 BitWidth - MVT::getSizeInBits(EVT))) && 1759 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1760 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1761 LN0->getBasePtr(), LN0->getSrcValue(), 1762 LN0->getSrcValueOffset(), EVT, 1763 LN0->isVolatile(), 1764 LN0->getAlignment()); 1765 AddToWorkList(N); 1766 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1767 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1768 } 1769 } 1770 1771 // fold (and (load x), 255) -> (zextload x, i8) 1772 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1773 if (N1C && N0.getOpcode() == ISD::LOAD) { 1774 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1775 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1776 LN0->isUnindexed() && N0.hasOneUse()) { 1777 MVT::ValueType EVT, LoadedVT; 1778 if (N1C->getAPIntValue() == 255) 1779 EVT = MVT::i8; 1780 else if (N1C->getAPIntValue() == 65535) 1781 EVT = MVT::i16; 1782 else if (N1C->getAPIntValue() == ~0U) 1783 EVT = MVT::i32; 1784 else 1785 EVT = MVT::Other; 1786 1787 LoadedVT = LN0->getMemoryVT(); 1788 if (EVT != MVT::Other && LoadedVT > EVT && 1789 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1790 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1791 // For big endian targets, we need to add an offset to the pointer to 1792 // load the correct bytes. For little endian systems, we merely need to 1793 // read fewer bytes from the same pointer. 1794 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1795 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1796 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1797 unsigned Alignment = LN0->getAlignment(); 1798 SDOperand NewPtr = LN0->getBasePtr(); 1799 if (TLI.isBigEndian()) { 1800 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1801 DAG.getConstant(PtrOff, PtrType)); 1802 Alignment = MinAlign(Alignment, PtrOff); 1803 } 1804 AddToWorkList(NewPtr.Val); 1805 SDOperand Load = 1806 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1807 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1808 LN0->isVolatile(), Alignment); 1809 AddToWorkList(N); 1810 CombineTo(N0.Val, Load, Load.getValue(1)); 1811 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1812 } 1813 } 1814 } 1815 1816 return SDOperand(); 1817} 1818 1819SDOperand DAGCombiner::visitOR(SDNode *N) { 1820 SDOperand N0 = N->getOperand(0); 1821 SDOperand N1 = N->getOperand(1); 1822 SDOperand LL, LR, RL, RR, CC0, CC1; 1823 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1824 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1825 MVT::ValueType VT = N1.getValueType(); 1826 1827 // fold vector ops 1828 if (MVT::isVector(VT)) { 1829 SDOperand FoldedVOp = SimplifyVBinOp(N); 1830 if (FoldedVOp.Val) return FoldedVOp; 1831 } 1832 1833 // fold (or x, undef) -> -1 1834 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1835 return DAG.getConstant(~0ULL, VT); 1836 // fold (or c1, c2) -> c1|c2 1837 if (N0C && N1C) 1838 return DAG.getNode(ISD::OR, VT, N0, N1); 1839 // canonicalize constant to RHS 1840 if (N0C && !N1C) 1841 return DAG.getNode(ISD::OR, VT, N1, N0); 1842 // fold (or x, 0) -> x 1843 if (N1C && N1C->isNullValue()) 1844 return N0; 1845 // fold (or x, -1) -> -1 1846 if (N1C && N1C->isAllOnesValue()) 1847 return N1; 1848 // fold (or x, c) -> c iff (x & ~c) == 0 1849 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1850 return N1; 1851 // reassociate or 1852 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1853 if (ROR.Val != 0) 1854 return ROR; 1855 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1856 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1857 isa<ConstantSDNode>(N0.getOperand(1))) { 1858 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1859 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1860 N1), 1861 DAG.getConstant(N1C->getAPIntValue() | 1862 C1->getAPIntValue(), VT)); 1863 } 1864 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1865 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1866 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1867 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1868 1869 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1870 MVT::isInteger(LL.getValueType())) { 1871 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1872 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1873 if (cast<ConstantSDNode>(LR)->isNullValue() && 1874 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1875 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1876 AddToWorkList(ORNode.Val); 1877 return DAG.getSetCC(VT, ORNode, LR, Op1); 1878 } 1879 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1880 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1881 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1882 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1883 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1884 AddToWorkList(ANDNode.Val); 1885 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1886 } 1887 } 1888 // canonicalize equivalent to ll == rl 1889 if (LL == RR && LR == RL) { 1890 Op1 = ISD::getSetCCSwappedOperands(Op1); 1891 std::swap(RL, RR); 1892 } 1893 if (LL == RL && LR == RR) { 1894 bool isInteger = MVT::isInteger(LL.getValueType()); 1895 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1896 if (Result != ISD::SETCC_INVALID) 1897 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1898 } 1899 } 1900 1901 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1902 if (N0.getOpcode() == N1.getOpcode()) { 1903 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1904 if (Tmp.Val) return Tmp; 1905 } 1906 1907 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1908 if (N0.getOpcode() == ISD::AND && 1909 N1.getOpcode() == ISD::AND && 1910 N0.getOperand(1).getOpcode() == ISD::Constant && 1911 N1.getOperand(1).getOpcode() == ISD::Constant && 1912 // Don't increase # computations. 1913 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1914 // We can only do this xform if we know that bits from X that are set in C2 1915 // but not in C1 are already zero. Likewise for Y. 1916 const APInt &LHSMask = 1917 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1918 const APInt &RHSMask = 1919 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1920 1921 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1922 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1923 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1924 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1925 } 1926 } 1927 1928 1929 // See if this is some rotate idiom. 1930 if (SDNode *Rot = MatchRotate(N0, N1)) 1931 return SDOperand(Rot, 0); 1932 1933 return SDOperand(); 1934} 1935 1936 1937/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1938static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1939 if (Op.getOpcode() == ISD::AND) { 1940 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1941 Mask = Op.getOperand(1); 1942 Op = Op.getOperand(0); 1943 } else { 1944 return false; 1945 } 1946 } 1947 1948 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1949 Shift = Op; 1950 return true; 1951 } 1952 return false; 1953} 1954 1955 1956// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1957// idioms for rotate, and if the target supports rotation instructions, generate 1958// a rot[lr]. 1959SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1960 // Must be a legal type. Expanded an promoted things won't work with rotates. 1961 MVT::ValueType VT = LHS.getValueType(); 1962 if (!TLI.isTypeLegal(VT)) return 0; 1963 1964 // The target must have at least one rotate flavor. 1965 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1966 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1967 if (!HasROTL && !HasROTR) return 0; 1968 1969 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1970 SDOperand LHSShift; // The shift. 1971 SDOperand LHSMask; // AND value if any. 1972 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1973 return 0; // Not part of a rotate. 1974 1975 SDOperand RHSShift; // The shift. 1976 SDOperand RHSMask; // AND value if any. 1977 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1978 return 0; // Not part of a rotate. 1979 1980 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1981 return 0; // Not shifting the same value. 1982 1983 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1984 return 0; // Shifts must disagree. 1985 1986 // Canonicalize shl to left side in a shl/srl pair. 1987 if (RHSShift.getOpcode() == ISD::SHL) { 1988 std::swap(LHS, RHS); 1989 std::swap(LHSShift, RHSShift); 1990 std::swap(LHSMask , RHSMask ); 1991 } 1992 1993 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1994 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1995 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1996 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1997 1998 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1999 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2000 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2001 RHSShiftAmt.getOpcode() == ISD::Constant) { 2002 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 2003 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 2004 if ((LShVal + RShVal) != OpSizeInBits) 2005 return 0; 2006 2007 SDOperand Rot; 2008 if (HasROTL) 2009 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2010 else 2011 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2012 2013 // If there is an AND of either shifted operand, apply it to the result. 2014 if (LHSMask.Val || RHSMask.Val) { 2015 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2016 2017 if (LHSMask.Val) { 2018 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2019 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2020 } 2021 if (RHSMask.Val) { 2022 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2023 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2024 } 2025 2026 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2027 } 2028 2029 return Rot.Val; 2030 } 2031 2032 // If there is a mask here, and we have a variable shift, we can't be sure 2033 // that we're masking out the right stuff. 2034 if (LHSMask.Val || RHSMask.Val) 2035 return 0; 2036 2037 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2038 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2039 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2040 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2041 if (ConstantSDNode *SUBC = 2042 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2043 if (SUBC->getAPIntValue() == OpSizeInBits) { 2044 if (HasROTL) 2045 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2046 else 2047 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2048 } 2049 } 2050 } 2051 2052 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2053 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2054 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2055 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2056 if (ConstantSDNode *SUBC = 2057 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2058 if (SUBC->getAPIntValue() == OpSizeInBits) { 2059 if (HasROTL) 2060 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2061 else 2062 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2063 } 2064 } 2065 } 2066 2067 // Look for sign/zext/any-extended cases: 2068 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2069 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2070 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2071 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2072 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2073 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2074 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 2075 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 2076 if (RExtOp0.getOpcode() == ISD::SUB && 2077 RExtOp0.getOperand(1) == LExtOp0) { 2078 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2079 // (rotr x, y) 2080 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2081 // (rotl x, (sub 32, y)) 2082 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2083 if (SUBC->getAPIntValue() == OpSizeInBits) { 2084 if (HasROTL) 2085 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2086 else 2087 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2088 } 2089 } 2090 } else if (LExtOp0.getOpcode() == ISD::SUB && 2091 RExtOp0 == LExtOp0.getOperand(1)) { 2092 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2093 // (rotl x, y) 2094 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2095 // (rotr x, (sub 32, y)) 2096 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2097 if (SUBC->getAPIntValue() == OpSizeInBits) { 2098 if (HasROTL) 2099 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2100 else 2101 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2102 } 2103 } 2104 } 2105 } 2106 2107 return 0; 2108} 2109 2110 2111SDOperand DAGCombiner::visitXOR(SDNode *N) { 2112 SDOperand N0 = N->getOperand(0); 2113 SDOperand N1 = N->getOperand(1); 2114 SDOperand LHS, RHS, CC; 2115 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2116 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2117 MVT::ValueType VT = N0.getValueType(); 2118 2119 // fold vector ops 2120 if (MVT::isVector(VT)) { 2121 SDOperand FoldedVOp = SimplifyVBinOp(N); 2122 if (FoldedVOp.Val) return FoldedVOp; 2123 } 2124 2125 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2126 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2127 return DAG.getConstant(0, VT); 2128 // fold (xor x, undef) -> undef 2129 if (N0.getOpcode() == ISD::UNDEF) 2130 return N0; 2131 if (N1.getOpcode() == ISD::UNDEF) 2132 return N1; 2133 // fold (xor c1, c2) -> c1^c2 2134 if (N0C && N1C) 2135 return DAG.getNode(ISD::XOR, VT, N0, N1); 2136 // canonicalize constant to RHS 2137 if (N0C && !N1C) 2138 return DAG.getNode(ISD::XOR, VT, N1, N0); 2139 // fold (xor x, 0) -> x 2140 if (N1C && N1C->isNullValue()) 2141 return N0; 2142 // reassociate xor 2143 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2144 if (RXOR.Val != 0) 2145 return RXOR; 2146 // fold !(x cc y) -> (x !cc y) 2147 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2148 bool isInt = MVT::isInteger(LHS.getValueType()); 2149 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2150 isInt); 2151 if (N0.getOpcode() == ISD::SETCC) 2152 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2153 if (N0.getOpcode() == ISD::SELECT_CC) 2154 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2155 assert(0 && "Unhandled SetCC Equivalent!"); 2156 abort(); 2157 } 2158 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2159 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2160 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2161 SDOperand V = N0.getOperand(0); 2162 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2163 DAG.getConstant(1, V.getValueType())); 2164 AddToWorkList(V.Val); 2165 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2166 } 2167 2168 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2169 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2170 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2171 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2172 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2173 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2174 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2175 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2176 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2177 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2178 } 2179 } 2180 // fold !(x or y) -> (!x and !y) iff x or y are constants 2181 if (N1C && N1C->isAllOnesValue() && 2182 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2183 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2184 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2185 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2186 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2187 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2188 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2189 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2190 } 2191 } 2192 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2193 if (N1C && N0.getOpcode() == ISD::XOR) { 2194 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2195 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2196 if (N00C) 2197 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2198 DAG.getConstant(N1C->getAPIntValue()^ 2199 N00C->getAPIntValue(), VT)); 2200 if (N01C) 2201 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2202 DAG.getConstant(N1C->getAPIntValue()^ 2203 N01C->getAPIntValue(), VT)); 2204 } 2205 // fold (xor x, x) -> 0 2206 if (N0 == N1) { 2207 if (!MVT::isVector(VT)) { 2208 return DAG.getConstant(0, VT); 2209 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2210 // Produce a vector of zeros. 2211 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2212 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2213 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2214 } 2215 } 2216 2217 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2218 if (N0.getOpcode() == N1.getOpcode()) { 2219 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2220 if (Tmp.Val) return Tmp; 2221 } 2222 2223 // Simplify the expression using non-local knowledge. 2224 if (!MVT::isVector(VT) && 2225 SimplifyDemandedBits(SDOperand(N, 0))) 2226 return SDOperand(N, 0); 2227 2228 return SDOperand(); 2229} 2230 2231/// visitShiftByConstant - Handle transforms common to the three shifts, when 2232/// the shift amount is a constant. 2233SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2234 SDNode *LHS = N->getOperand(0).Val; 2235 if (!LHS->hasOneUse()) return SDOperand(); 2236 2237 // We want to pull some binops through shifts, so that we have (and (shift)) 2238 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2239 // thing happens with address calculations, so it's important to canonicalize 2240 // it. 2241 bool HighBitSet = false; // Can we transform this if the high bit is set? 2242 2243 switch (LHS->getOpcode()) { 2244 default: return SDOperand(); 2245 case ISD::OR: 2246 case ISD::XOR: 2247 HighBitSet = false; // We can only transform sra if the high bit is clear. 2248 break; 2249 case ISD::AND: 2250 HighBitSet = true; // We can only transform sra if the high bit is set. 2251 break; 2252 case ISD::ADD: 2253 if (N->getOpcode() != ISD::SHL) 2254 return SDOperand(); // only shl(add) not sr[al](add). 2255 HighBitSet = false; // We can only transform sra if the high bit is clear. 2256 break; 2257 } 2258 2259 // We require the RHS of the binop to be a constant as well. 2260 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2261 if (!BinOpCst) return SDOperand(); 2262 2263 2264 // FIXME: disable this for unless the input to the binop is a shift by a 2265 // constant. If it is not a shift, it pessimizes some common cases like: 2266 // 2267 //void foo(int *X, int i) { X[i & 1235] = 1; } 2268 //int bar(int *X, int i) { return X[i & 255]; } 2269 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2270 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2271 BinOpLHSVal->getOpcode() != ISD::SRA && 2272 BinOpLHSVal->getOpcode() != ISD::SRL) || 2273 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2274 return SDOperand(); 2275 2276 MVT::ValueType VT = N->getValueType(0); 2277 2278 // If this is a signed shift right, and the high bit is modified 2279 // by the logical operation, do not perform the transformation. 2280 // The highBitSet boolean indicates the value of the high bit of 2281 // the constant which would cause it to be modified for this 2282 // operation. 2283 if (N->getOpcode() == ISD::SRA) { 2284 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2285 if (BinOpRHSSignSet != HighBitSet) 2286 return SDOperand(); 2287 } 2288 2289 // Fold the constants, shifting the binop RHS by the shift amount. 2290 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2291 LHS->getOperand(1), N->getOperand(1)); 2292 2293 // Create the new shift. 2294 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2295 N->getOperand(1)); 2296 2297 // Create the new binop. 2298 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2299} 2300 2301 2302SDOperand DAGCombiner::visitSHL(SDNode *N) { 2303 SDOperand N0 = N->getOperand(0); 2304 SDOperand N1 = N->getOperand(1); 2305 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2306 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2307 MVT::ValueType VT = N0.getValueType(); 2308 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2309 2310 // fold (shl c1, c2) -> c1<<c2 2311 if (N0C && N1C) 2312 return DAG.getNode(ISD::SHL, VT, N0, N1); 2313 // fold (shl 0, x) -> 0 2314 if (N0C && N0C->isNullValue()) 2315 return N0; 2316 // fold (shl x, c >= size(x)) -> undef 2317 if (N1C && N1C->getValue() >= OpSizeInBits) 2318 return DAG.getNode(ISD::UNDEF, VT); 2319 // fold (shl x, 0) -> x 2320 if (N1C && N1C->isNullValue()) 2321 return N0; 2322 // if (shl x, c) is known to be zero, return 0 2323 if (DAG.MaskedValueIsZero(SDOperand(N, 0), 2324 APInt::getAllOnesValue(MVT::getSizeInBits(VT)))) 2325 return DAG.getConstant(0, VT); 2326 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2327 return SDOperand(N, 0); 2328 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2329 if (N1C && N0.getOpcode() == ISD::SHL && 2330 N0.getOperand(1).getOpcode() == ISD::Constant) { 2331 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2332 uint64_t c2 = N1C->getValue(); 2333 if (c1 + c2 > OpSizeInBits) 2334 return DAG.getConstant(0, VT); 2335 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2336 DAG.getConstant(c1 + c2, N1.getValueType())); 2337 } 2338 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2339 // (srl (and x, -1 << c1), c1-c2) 2340 if (N1C && N0.getOpcode() == ISD::SRL && 2341 N0.getOperand(1).getOpcode() == ISD::Constant) { 2342 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2343 uint64_t c2 = N1C->getValue(); 2344 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2345 DAG.getConstant(~0ULL << c1, VT)); 2346 if (c2 > c1) 2347 return DAG.getNode(ISD::SHL, VT, Mask, 2348 DAG.getConstant(c2-c1, N1.getValueType())); 2349 else 2350 return DAG.getNode(ISD::SRL, VT, Mask, 2351 DAG.getConstant(c1-c2, N1.getValueType())); 2352 } 2353 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2354 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2355 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2356 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2357 2358 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2359} 2360 2361SDOperand DAGCombiner::visitSRA(SDNode *N) { 2362 SDOperand N0 = N->getOperand(0); 2363 SDOperand N1 = N->getOperand(1); 2364 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2365 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2366 MVT::ValueType VT = N0.getValueType(); 2367 2368 // fold (sra c1, c2) -> c1>>c2 2369 if (N0C && N1C) 2370 return DAG.getNode(ISD::SRA, VT, N0, N1); 2371 // fold (sra 0, x) -> 0 2372 if (N0C && N0C->isNullValue()) 2373 return N0; 2374 // fold (sra -1, x) -> -1 2375 if (N0C && N0C->isAllOnesValue()) 2376 return N0; 2377 // fold (sra x, c >= size(x)) -> undef 2378 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2379 return DAG.getNode(ISD::UNDEF, VT); 2380 // fold (sra x, 0) -> x 2381 if (N1C && N1C->isNullValue()) 2382 return N0; 2383 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2384 // sext_inreg. 2385 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2386 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2387 MVT::ValueType EVT; 2388 switch (LowBits) { 2389 default: EVT = MVT::Other; break; 2390 case 1: EVT = MVT::i1; break; 2391 case 8: EVT = MVT::i8; break; 2392 case 16: EVT = MVT::i16; break; 2393 case 32: EVT = MVT::i32; break; 2394 } 2395 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2396 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2397 DAG.getValueType(EVT)); 2398 } 2399 2400 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2401 if (N1C && N0.getOpcode() == ISD::SRA) { 2402 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2403 unsigned Sum = N1C->getValue() + C1->getValue(); 2404 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2405 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2406 DAG.getConstant(Sum, N1C->getValueType(0))); 2407 } 2408 } 2409 2410 // fold sra (shl X, m), result_size - n 2411 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2412 // result_size - n != m. 2413 // If truncate is free for the target sext(shl) is likely to result in better 2414 // code. 2415 if (N0.getOpcode() == ISD::SHL) { 2416 // Get the two constanst of the shifts, CN0 = m, CN = n. 2417 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2418 if (N01C && N1C) { 2419 // Determine what the truncate's result bitsize and type would be. 2420 unsigned VTValSize = MVT::getSizeInBits(VT); 2421 MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue()); 2422 // Determine the residual right-shift amount. 2423 unsigned ShiftAmt = N1C->getValue() - N01C->getValue(); 2424 2425 // If the shift is not a no-op (in which case this should be just a sign 2426 // extend already), the truncated to type is legal, sign_extend is legal 2427 // on that type, and the the truncate to that type is both legal and free, 2428 // perform the transform. 2429 if (ShiftAmt && 2430 TLI.isTypeLegal(TruncVT) && 2431 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2432 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2433 TLI.isTruncateFree(VT, TruncVT)) { 2434 2435 SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2436 SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2437 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2438 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2439 } 2440 } 2441 } 2442 2443 // Simplify, based on bits shifted out of the LHS. 2444 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2445 return SDOperand(N, 0); 2446 2447 2448 // If the sign bit is known to be zero, switch this to a SRL. 2449 if (DAG.SignBitIsZero(N0)) 2450 return DAG.getNode(ISD::SRL, VT, N0, N1); 2451 2452 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2453} 2454 2455SDOperand DAGCombiner::visitSRL(SDNode *N) { 2456 SDOperand N0 = N->getOperand(0); 2457 SDOperand N1 = N->getOperand(1); 2458 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2459 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2460 MVT::ValueType VT = N0.getValueType(); 2461 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2462 2463 // fold (srl c1, c2) -> c1 >>u c2 2464 if (N0C && N1C) 2465 return DAG.getNode(ISD::SRL, VT, N0, N1); 2466 // fold (srl 0, x) -> 0 2467 if (N0C && N0C->isNullValue()) 2468 return N0; 2469 // fold (srl x, c >= size(x)) -> undef 2470 if (N1C && N1C->getValue() >= OpSizeInBits) 2471 return DAG.getNode(ISD::UNDEF, VT); 2472 // fold (srl x, 0) -> x 2473 if (N1C && N1C->isNullValue()) 2474 return N0; 2475 // if (srl x, c) is known to be zero, return 0 2476 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 2477 APInt::getAllOnesValue(OpSizeInBits))) 2478 return DAG.getConstant(0, VT); 2479 2480 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2481 if (N1C && N0.getOpcode() == ISD::SRL && 2482 N0.getOperand(1).getOpcode() == ISD::Constant) { 2483 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2484 uint64_t c2 = N1C->getValue(); 2485 if (c1 + c2 > OpSizeInBits) 2486 return DAG.getConstant(0, VT); 2487 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2488 DAG.getConstant(c1 + c2, N1.getValueType())); 2489 } 2490 2491 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2492 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2493 // Shifting in all undef bits? 2494 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2495 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2496 return DAG.getNode(ISD::UNDEF, VT); 2497 2498 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2499 AddToWorkList(SmallShift.Val); 2500 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2501 } 2502 2503 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2504 // bit, which is unmodified by sra. 2505 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2506 if (N0.getOpcode() == ISD::SRA) 2507 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2508 } 2509 2510 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2511 if (N1C && N0.getOpcode() == ISD::CTLZ && 2512 N1C->getAPIntValue() == Log2_32(MVT::getSizeInBits(VT))) { 2513 APInt KnownZero, KnownOne; 2514 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); 2515 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2516 2517 // If any of the input bits are KnownOne, then the input couldn't be all 2518 // zeros, thus the result of the srl will always be zero. 2519 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2520 2521 // If all of the bits input the to ctlz node are known to be zero, then 2522 // the result of the ctlz is "32" and the result of the shift is one. 2523 APInt UnknownBits = ~KnownZero & Mask; 2524 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2525 2526 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2527 if ((UnknownBits & (UnknownBits-1)) == 0) { 2528 // Okay, we know that only that the single bit specified by UnknownBits 2529 // could be set on input to the CTLZ node. If this bit is set, the SRL 2530 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2531 // to an SRL,XOR pair, which is likely to simplify more. 2532 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2533 SDOperand Op = N0.getOperand(0); 2534 if (ShAmt) { 2535 Op = DAG.getNode(ISD::SRL, VT, Op, 2536 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2537 AddToWorkList(Op.Val); 2538 } 2539 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2540 } 2541 } 2542 2543 // fold operands of srl based on knowledge that the low bits are not 2544 // demanded. 2545 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2546 return SDOperand(N, 0); 2547 2548 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2549} 2550 2551SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2552 SDOperand N0 = N->getOperand(0); 2553 MVT::ValueType VT = N->getValueType(0); 2554 2555 // fold (ctlz c1) -> c2 2556 if (isa<ConstantSDNode>(N0)) 2557 return DAG.getNode(ISD::CTLZ, VT, N0); 2558 return SDOperand(); 2559} 2560 2561SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2562 SDOperand N0 = N->getOperand(0); 2563 MVT::ValueType VT = N->getValueType(0); 2564 2565 // fold (cttz c1) -> c2 2566 if (isa<ConstantSDNode>(N0)) 2567 return DAG.getNode(ISD::CTTZ, VT, N0); 2568 return SDOperand(); 2569} 2570 2571SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2572 SDOperand N0 = N->getOperand(0); 2573 MVT::ValueType VT = N->getValueType(0); 2574 2575 // fold (ctpop c1) -> c2 2576 if (isa<ConstantSDNode>(N0)) 2577 return DAG.getNode(ISD::CTPOP, VT, N0); 2578 return SDOperand(); 2579} 2580 2581SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2582 SDOperand N0 = N->getOperand(0); 2583 SDOperand N1 = N->getOperand(1); 2584 SDOperand N2 = N->getOperand(2); 2585 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2586 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2587 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2588 MVT::ValueType VT = N->getValueType(0); 2589 MVT::ValueType VT0 = N0.getValueType(); 2590 2591 // fold select C, X, X -> X 2592 if (N1 == N2) 2593 return N1; 2594 // fold select true, X, Y -> X 2595 if (N0C && !N0C->isNullValue()) 2596 return N1; 2597 // fold select false, X, Y -> Y 2598 if (N0C && N0C->isNullValue()) 2599 return N2; 2600 // fold select C, 1, X -> C | X 2601 if (MVT::i1 == VT && N1C && N1C->getAPIntValue() == 1) 2602 return DAG.getNode(ISD::OR, VT, N0, N2); 2603 // fold select C, 0, 1 -> ~C 2604 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2605 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2606 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2607 if (VT == VT0) 2608 return XORNode; 2609 AddToWorkList(XORNode.Val); 2610 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2611 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2612 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2613 } 2614 // fold select C, 0, X -> ~C & X 2615 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2616 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2617 AddToWorkList(XORNode.Val); 2618 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2619 } 2620 // fold select C, X, 1 -> ~C | X 2621 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2622 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2623 AddToWorkList(XORNode.Val); 2624 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2625 } 2626 // fold select C, X, 0 -> C & X 2627 // FIXME: this should check for C type == X type, not i1? 2628 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2629 return DAG.getNode(ISD::AND, VT, N0, N1); 2630 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2631 if (MVT::i1 == VT && N0 == N1) 2632 return DAG.getNode(ISD::OR, VT, N0, N2); 2633 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2634 if (MVT::i1 == VT && N0 == N2) 2635 return DAG.getNode(ISD::AND, VT, N0, N1); 2636 2637 // If we can fold this based on the true/false value, do so. 2638 if (SimplifySelectOps(N, N1, N2)) 2639 return SDOperand(N, 0); // Don't revisit N. 2640 2641 // fold selects based on a setcc into other things, such as min/max/abs 2642 if (N0.getOpcode() == ISD::SETCC) { 2643 // FIXME: 2644 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2645 // having to say they don't support SELECT_CC on every type the DAG knows 2646 // about, since there is no way to mark an opcode illegal at all value types 2647 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2648 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2649 N1, N2, N0.getOperand(2)); 2650 else 2651 return SimplifySelect(N0, N1, N2); 2652 } 2653 return SDOperand(); 2654} 2655 2656SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2657 SDOperand N0 = N->getOperand(0); 2658 SDOperand N1 = N->getOperand(1); 2659 SDOperand N2 = N->getOperand(2); 2660 SDOperand N3 = N->getOperand(3); 2661 SDOperand N4 = N->getOperand(4); 2662 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2663 2664 // fold select_cc lhs, rhs, x, x, cc -> x 2665 if (N2 == N3) 2666 return N2; 2667 2668 // Determine if the condition we're dealing with is constant 2669 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2670 if (SCC.Val) AddToWorkList(SCC.Val); 2671 2672 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2673 if (!SCCC->isNullValue()) 2674 return N2; // cond always true -> true val 2675 else 2676 return N3; // cond always false -> false val 2677 } 2678 2679 // Fold to a simpler select_cc 2680 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2681 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2682 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2683 SCC.getOperand(2)); 2684 2685 // If we can fold this based on the true/false value, do so. 2686 if (SimplifySelectOps(N, N2, N3)) 2687 return SDOperand(N, 0); // Don't revisit N. 2688 2689 // fold select_cc into other things, such as min/max/abs 2690 return SimplifySelectCC(N0, N1, N2, N3, CC); 2691} 2692 2693SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2694 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2695 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2696} 2697 2698// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2699// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2700// transformation. Returns true if extension are possible and the above 2701// mentioned transformation is profitable. 2702static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2703 unsigned ExtOpc, 2704 SmallVector<SDNode*, 4> &ExtendNodes, 2705 TargetLowering &TLI) { 2706 bool HasCopyToRegUses = false; 2707 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2708 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2709 UI != UE; ++UI) { 2710 SDNode *User = UI->getUser(); 2711 if (User == N) 2712 continue; 2713 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2714 if (User->getOpcode() == ISD::SETCC) { 2715 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2716 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2717 // Sign bits will be lost after a zext. 2718 return false; 2719 bool Add = false; 2720 for (unsigned i = 0; i != 2; ++i) { 2721 SDOperand UseOp = User->getOperand(i); 2722 if (UseOp == N0) 2723 continue; 2724 if (!isa<ConstantSDNode>(UseOp)) 2725 return false; 2726 Add = true; 2727 } 2728 if (Add) 2729 ExtendNodes.push_back(User); 2730 } else { 2731 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2732 SDOperand UseOp = User->getOperand(i); 2733 if (UseOp == N0) { 2734 // If truncate from extended type to original load type is free 2735 // on this target, then it's ok to extend a CopyToReg. 2736 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2737 HasCopyToRegUses = true; 2738 else 2739 return false; 2740 } 2741 } 2742 } 2743 } 2744 2745 if (HasCopyToRegUses) { 2746 bool BothLiveOut = false; 2747 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2748 UI != UE; ++UI) { 2749 SDNode *User = UI->getUser(); 2750 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2751 SDOperand UseOp = User->getOperand(i); 2752 if (UseOp.Val == N && UseOp.ResNo == 0) { 2753 BothLiveOut = true; 2754 break; 2755 } 2756 } 2757 } 2758 if (BothLiveOut) 2759 // Both unextended and extended values are live out. There had better be 2760 // good a reason for the transformation. 2761 return ExtendNodes.size(); 2762 } 2763 return true; 2764} 2765 2766SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2767 SDOperand N0 = N->getOperand(0); 2768 MVT::ValueType VT = N->getValueType(0); 2769 2770 // fold (sext c1) -> c1 2771 if (isa<ConstantSDNode>(N0)) 2772 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2773 2774 // fold (sext (sext x)) -> (sext x) 2775 // fold (sext (aext x)) -> (sext x) 2776 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2777 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2778 2779 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2780 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2781 if (N0.getOpcode() == ISD::TRUNCATE) { 2782 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2783 if (NarrowLoad.Val) { 2784 if (NarrowLoad.Val != N0.Val) 2785 CombineTo(N0.Val, NarrowLoad); 2786 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2787 } 2788 } 2789 2790 // See if the value being truncated is already sign extended. If so, just 2791 // eliminate the trunc/sext pair. 2792 if (N0.getOpcode() == ISD::TRUNCATE) { 2793 SDOperand Op = N0.getOperand(0); 2794 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2795 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2796 unsigned DestBits = MVT::getSizeInBits(VT); 2797 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2798 2799 if (OpBits == DestBits) { 2800 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2801 // bits, it is already ready. 2802 if (NumSignBits > DestBits-MidBits) 2803 return Op; 2804 } else if (OpBits < DestBits) { 2805 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2806 // bits, just sext from i32. 2807 if (NumSignBits > OpBits-MidBits) 2808 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2809 } else { 2810 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2811 // bits, just truncate to i32. 2812 if (NumSignBits > OpBits-MidBits) 2813 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2814 } 2815 2816 // fold (sext (truncate x)) -> (sextinreg x). 2817 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2818 N0.getValueType())) { 2819 if (Op.getValueType() < VT) 2820 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2821 else if (Op.getValueType() > VT) 2822 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2823 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2824 DAG.getValueType(N0.getValueType())); 2825 } 2826 } 2827 2828 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2829 if (ISD::isNON_EXTLoad(N0.Val) && 2830 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2831 bool DoXform = true; 2832 SmallVector<SDNode*, 4> SetCCs; 2833 if (!N0.hasOneUse()) 2834 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2835 if (DoXform) { 2836 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2837 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2838 LN0->getBasePtr(), LN0->getSrcValue(), 2839 LN0->getSrcValueOffset(), 2840 N0.getValueType(), 2841 LN0->isVolatile(), 2842 LN0->getAlignment()); 2843 CombineTo(N, ExtLoad); 2844 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2845 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2846 // Extend SetCC uses if necessary. 2847 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2848 SDNode *SetCC = SetCCs[i]; 2849 SmallVector<SDOperand, 4> Ops; 2850 for (unsigned j = 0; j != 2; ++j) { 2851 SDOperand SOp = SetCC->getOperand(j); 2852 if (SOp == Trunc) 2853 Ops.push_back(ExtLoad); 2854 else 2855 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2856 } 2857 Ops.push_back(SetCC->getOperand(2)); 2858 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2859 &Ops[0], Ops.size())); 2860 } 2861 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2862 } 2863 } 2864 2865 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2866 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2867 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2868 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2869 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2870 MVT::ValueType EVT = LN0->getMemoryVT(); 2871 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2872 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2873 LN0->getBasePtr(), LN0->getSrcValue(), 2874 LN0->getSrcValueOffset(), EVT, 2875 LN0->isVolatile(), 2876 LN0->getAlignment()); 2877 CombineTo(N, ExtLoad); 2878 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2879 ExtLoad.getValue(1)); 2880 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2881 } 2882 } 2883 2884 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2885 if (N0.getOpcode() == ISD::SETCC) { 2886 SDOperand SCC = 2887 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2888 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2889 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2890 if (SCC.Val) return SCC; 2891 } 2892 2893 // fold (sext x) -> (zext x) if the sign bit is known zero. 2894 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 2895 DAG.SignBitIsZero(N0)) 2896 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2897 2898 return SDOperand(); 2899} 2900 2901SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2902 SDOperand N0 = N->getOperand(0); 2903 MVT::ValueType VT = N->getValueType(0); 2904 2905 // fold (zext c1) -> c1 2906 if (isa<ConstantSDNode>(N0)) 2907 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2908 // fold (zext (zext x)) -> (zext x) 2909 // fold (zext (aext x)) -> (zext x) 2910 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2911 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2912 2913 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2914 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2915 if (N0.getOpcode() == ISD::TRUNCATE) { 2916 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2917 if (NarrowLoad.Val) { 2918 if (NarrowLoad.Val != N0.Val) 2919 CombineTo(N0.Val, NarrowLoad); 2920 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2921 } 2922 } 2923 2924 // fold (zext (truncate x)) -> (and x, mask) 2925 if (N0.getOpcode() == ISD::TRUNCATE && 2926 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2927 SDOperand Op = N0.getOperand(0); 2928 if (Op.getValueType() < VT) { 2929 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2930 } else if (Op.getValueType() > VT) { 2931 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2932 } 2933 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2934 } 2935 2936 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2937 if (N0.getOpcode() == ISD::AND && 2938 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2939 N0.getOperand(1).getOpcode() == ISD::Constant) { 2940 SDOperand X = N0.getOperand(0).getOperand(0); 2941 if (X.getValueType() < VT) { 2942 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2943 } else if (X.getValueType() > VT) { 2944 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2945 } 2946 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2947 Mask.zext(MVT::getSizeInBits(VT)); 2948 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2949 } 2950 2951 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2952 if (ISD::isNON_EXTLoad(N0.Val) && 2953 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2954 bool DoXform = true; 2955 SmallVector<SDNode*, 4> SetCCs; 2956 if (!N0.hasOneUse()) 2957 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2958 if (DoXform) { 2959 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2960 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2961 LN0->getBasePtr(), LN0->getSrcValue(), 2962 LN0->getSrcValueOffset(), 2963 N0.getValueType(), 2964 LN0->isVolatile(), 2965 LN0->getAlignment()); 2966 CombineTo(N, ExtLoad); 2967 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2968 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2969 // Extend SetCC uses if necessary. 2970 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2971 SDNode *SetCC = SetCCs[i]; 2972 SmallVector<SDOperand, 4> Ops; 2973 for (unsigned j = 0; j != 2; ++j) { 2974 SDOperand SOp = SetCC->getOperand(j); 2975 if (SOp == Trunc) 2976 Ops.push_back(ExtLoad); 2977 else 2978 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2979 } 2980 Ops.push_back(SetCC->getOperand(2)); 2981 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2982 &Ops[0], Ops.size())); 2983 } 2984 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2985 } 2986 } 2987 2988 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2989 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2990 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2991 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2992 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2993 MVT::ValueType EVT = LN0->getMemoryVT(); 2994 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2995 LN0->getBasePtr(), LN0->getSrcValue(), 2996 LN0->getSrcValueOffset(), EVT, 2997 LN0->isVolatile(), 2998 LN0->getAlignment()); 2999 CombineTo(N, ExtLoad); 3000 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3001 ExtLoad.getValue(1)); 3002 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3003 } 3004 3005 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3006 if (N0.getOpcode() == ISD::SETCC) { 3007 SDOperand SCC = 3008 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3009 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3010 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3011 if (SCC.Val) return SCC; 3012 } 3013 3014 return SDOperand(); 3015} 3016 3017SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 3018 SDOperand N0 = N->getOperand(0); 3019 MVT::ValueType VT = N->getValueType(0); 3020 3021 // fold (aext c1) -> c1 3022 if (isa<ConstantSDNode>(N0)) 3023 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3024 // fold (aext (aext x)) -> (aext x) 3025 // fold (aext (zext x)) -> (zext x) 3026 // fold (aext (sext x)) -> (sext x) 3027 if (N0.getOpcode() == ISD::ANY_EXTEND || 3028 N0.getOpcode() == ISD::ZERO_EXTEND || 3029 N0.getOpcode() == ISD::SIGN_EXTEND) 3030 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3031 3032 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3033 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3034 if (N0.getOpcode() == ISD::TRUNCATE) { 3035 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 3036 if (NarrowLoad.Val) { 3037 if (NarrowLoad.Val != N0.Val) 3038 CombineTo(N0.Val, NarrowLoad); 3039 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3040 } 3041 } 3042 3043 // fold (aext (truncate x)) 3044 if (N0.getOpcode() == ISD::TRUNCATE) { 3045 SDOperand TruncOp = N0.getOperand(0); 3046 if (TruncOp.getValueType() == VT) 3047 return TruncOp; // x iff x size == zext size. 3048 if (TruncOp.getValueType() > VT) 3049 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3050 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3051 } 3052 3053 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3054 if (N0.getOpcode() == ISD::AND && 3055 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3056 N0.getOperand(1).getOpcode() == ISD::Constant) { 3057 SDOperand X = N0.getOperand(0).getOperand(0); 3058 if (X.getValueType() < VT) { 3059 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3060 } else if (X.getValueType() > VT) { 3061 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3062 } 3063 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3064 Mask.zext(MVT::getSizeInBits(VT)); 3065 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3066 } 3067 3068 // fold (aext (load x)) -> (aext (truncate (extload x))) 3069 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3070 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3071 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3072 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3073 LN0->getBasePtr(), LN0->getSrcValue(), 3074 LN0->getSrcValueOffset(), 3075 N0.getValueType(), 3076 LN0->isVolatile(), 3077 LN0->getAlignment()); 3078 CombineTo(N, ExtLoad); 3079 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3080 ExtLoad.getValue(1)); 3081 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3082 } 3083 3084 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3085 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3086 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3087 if (N0.getOpcode() == ISD::LOAD && 3088 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3089 N0.hasOneUse()) { 3090 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3091 MVT::ValueType EVT = LN0->getMemoryVT(); 3092 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3093 LN0->getChain(), LN0->getBasePtr(), 3094 LN0->getSrcValue(), 3095 LN0->getSrcValueOffset(), EVT, 3096 LN0->isVolatile(), 3097 LN0->getAlignment()); 3098 CombineTo(N, ExtLoad); 3099 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3100 ExtLoad.getValue(1)); 3101 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3102 } 3103 3104 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3105 if (N0.getOpcode() == ISD::SETCC) { 3106 SDOperand SCC = 3107 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3108 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3109 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3110 if (SCC.Val) 3111 return SCC; 3112 } 3113 3114 return SDOperand(); 3115} 3116 3117/// GetDemandedBits - See if the specified operand can be simplified with the 3118/// knowledge that only the bits specified by Mask are used. If so, return the 3119/// simpler operand, otherwise return a null SDOperand. 3120SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) { 3121 switch (V.getOpcode()) { 3122 default: break; 3123 case ISD::OR: 3124 case ISD::XOR: 3125 // If the LHS or RHS don't contribute bits to the or, drop them. 3126 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3127 return V.getOperand(1); 3128 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3129 return V.getOperand(0); 3130 break; 3131 case ISD::SRL: 3132 // Only look at single-use SRLs. 3133 if (!V.Val->hasOneUse()) 3134 break; 3135 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3136 // See if we can recursively simplify the LHS. 3137 unsigned Amt = RHSC->getValue(); 3138 APInt NewMask = Mask << Amt; 3139 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3140 if (SimplifyLHS.Val) { 3141 return DAG.getNode(ISD::SRL, V.getValueType(), 3142 SimplifyLHS, V.getOperand(1)); 3143 } 3144 } 3145 } 3146 return SDOperand(); 3147} 3148 3149/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3150/// bits and then truncated to a narrower type and where N is a multiple 3151/// of number of bits of the narrower type, transform it to a narrower load 3152/// from address + N / num of bits of new type. If the result is to be 3153/// extended, also fold the extension to form a extending load. 3154SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3155 unsigned Opc = N->getOpcode(); 3156 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3157 SDOperand N0 = N->getOperand(0); 3158 MVT::ValueType VT = N->getValueType(0); 3159 MVT::ValueType EVT = N->getValueType(0); 3160 3161 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3162 // extended to VT. 3163 if (Opc == ISD::SIGN_EXTEND_INREG) { 3164 ExtType = ISD::SEXTLOAD; 3165 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3166 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3167 return SDOperand(); 3168 } 3169 3170 unsigned EVTBits = MVT::getSizeInBits(EVT); 3171 unsigned ShAmt = 0; 3172 bool CombineSRL = false; 3173 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3174 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3175 ShAmt = N01->getValue(); 3176 // Is the shift amount a multiple of size of VT? 3177 if ((ShAmt & (EVTBits-1)) == 0) { 3178 N0 = N0.getOperand(0); 3179 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3180 return SDOperand(); 3181 CombineSRL = true; 3182 } 3183 } 3184 } 3185 3186 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3187 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3188 // zero extended form: by shrinking the load, we lose track of the fact 3189 // that it is already zero extended. 3190 // FIXME: This should be reevaluated. 3191 VT != MVT::i1) { 3192 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3193 "Cannot truncate to larger type!"); 3194 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3195 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3196 // For big endian targets, we need to adjust the offset to the pointer to 3197 // load the correct bytes. 3198 if (TLI.isBigEndian()) { 3199 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3200 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3201 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3202 } 3203 uint64_t PtrOff = ShAmt / 8; 3204 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3205 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3206 DAG.getConstant(PtrOff, PtrType)); 3207 AddToWorkList(NewPtr.Val); 3208 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3209 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3210 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3211 LN0->isVolatile(), NewAlign) 3212 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3213 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3214 LN0->isVolatile(), NewAlign); 3215 AddToWorkList(N); 3216 if (CombineSRL) { 3217 WorkListRemover DeadNodes(*this); 3218 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3219 &DeadNodes); 3220 CombineTo(N->getOperand(0).Val, Load); 3221 } else 3222 CombineTo(N0.Val, Load, Load.getValue(1)); 3223 if (ShAmt) { 3224 if (Opc == ISD::SIGN_EXTEND_INREG) 3225 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3226 else 3227 return DAG.getNode(Opc, VT, Load); 3228 } 3229 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3230 } 3231 3232 return SDOperand(); 3233} 3234 3235 3236SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3237 SDOperand N0 = N->getOperand(0); 3238 SDOperand N1 = N->getOperand(1); 3239 MVT::ValueType VT = N->getValueType(0); 3240 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3241 unsigned VTBits = MVT::getSizeInBits(VT); 3242 unsigned EVTBits = MVT::getSizeInBits(EVT); 3243 3244 // fold (sext_in_reg c1) -> c1 3245 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3246 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3247 3248 // If the input is already sign extended, just drop the extension. 3249 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3250 return N0; 3251 3252 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3253 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3254 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3255 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3256 } 3257 3258 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3259 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3260 return DAG.getZeroExtendInReg(N0, EVT); 3261 3262 // fold operands of sext_in_reg based on knowledge that the top bits are not 3263 // demanded. 3264 if (SimplifyDemandedBits(SDOperand(N, 0))) 3265 return SDOperand(N, 0); 3266 3267 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3268 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3269 SDOperand NarrowLoad = ReduceLoadWidth(N); 3270 if (NarrowLoad.Val) 3271 return NarrowLoad; 3272 3273 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3274 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3275 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3276 if (N0.getOpcode() == ISD::SRL) { 3277 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3278 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3279 // We can turn this into an SRA iff the input to the SRL is already sign 3280 // extended enough. 3281 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3282 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3283 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3284 } 3285 } 3286 3287 // fold (sext_inreg (extload x)) -> (sextload x) 3288 if (ISD::isEXTLoad(N0.Val) && 3289 ISD::isUNINDEXEDLoad(N0.Val) && 3290 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3291 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3292 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3293 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3294 LN0->getBasePtr(), LN0->getSrcValue(), 3295 LN0->getSrcValueOffset(), EVT, 3296 LN0->isVolatile(), 3297 LN0->getAlignment()); 3298 CombineTo(N, ExtLoad); 3299 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3300 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3301 } 3302 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3303 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3304 N0.hasOneUse() && 3305 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3306 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3307 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3308 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3309 LN0->getBasePtr(), LN0->getSrcValue(), 3310 LN0->getSrcValueOffset(), EVT, 3311 LN0->isVolatile(), 3312 LN0->getAlignment()); 3313 CombineTo(N, ExtLoad); 3314 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3315 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3316 } 3317 return SDOperand(); 3318} 3319 3320SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3321 SDOperand N0 = N->getOperand(0); 3322 MVT::ValueType VT = N->getValueType(0); 3323 3324 // noop truncate 3325 if (N0.getValueType() == N->getValueType(0)) 3326 return N0; 3327 // fold (truncate c1) -> c1 3328 if (isa<ConstantSDNode>(N0)) 3329 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3330 // fold (truncate (truncate x)) -> (truncate x) 3331 if (N0.getOpcode() == ISD::TRUNCATE) 3332 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3333 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3334 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3335 N0.getOpcode() == ISD::ANY_EXTEND) { 3336 if (N0.getOperand(0).getValueType() < VT) 3337 // if the source is smaller than the dest, we still need an extend 3338 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3339 else if (N0.getOperand(0).getValueType() > VT) 3340 // if the source is larger than the dest, than we just need the truncate 3341 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3342 else 3343 // if the source and dest are the same type, we can drop both the extend 3344 // and the truncate 3345 return N0.getOperand(0); 3346 } 3347 3348 // See if we can simplify the input to this truncate through knowledge that 3349 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3350 // -> trunc y 3351 SDOperand Shorter = 3352 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3353 MVT::getSizeInBits(VT))); 3354 if (Shorter.Val) 3355 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3356 3357 // fold (truncate (load x)) -> (smaller load x) 3358 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3359 return ReduceLoadWidth(N); 3360} 3361 3362static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3363 SDOperand Elt = N->getOperand(i); 3364 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3365 return Elt.Val; 3366 return Elt.getOperand(Elt.ResNo).Val; 3367} 3368 3369/// CombineConsecutiveLoads - build_pair (load, load) -> load 3370/// if load locations are consecutive. 3371SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT) { 3372 assert(N->getOpcode() == ISD::BUILD_PAIR); 3373 3374 SDNode *LD1 = getBuildPairElt(N, 0); 3375 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3376 return SDOperand(); 3377 MVT::ValueType LD1VT = LD1->getValueType(0); 3378 SDNode *LD2 = getBuildPairElt(N, 1); 3379 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3380 if (ISD::isNON_EXTLoad(LD2) && 3381 LD2->hasOneUse() && 3382 TLI.isConsecutiveLoad(LD2, LD1, MVT::getSizeInBits(LD1VT)/8, 1, MFI)) { 3383 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3384 unsigned Align = LD->getAlignment(); 3385 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 3386 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3387 if ((!AfterLegalize || TLI.isTypeLegal(VT)) && 3388 TLI.isOperationLegal(ISD::LOAD, VT) && NewAlign <= Align) 3389 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3390 LD->getSrcValue(), LD->getSrcValueOffset(), 3391 LD->isVolatile(), Align); 3392 } 3393 return SDOperand(); 3394} 3395 3396SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3397 SDOperand N0 = N->getOperand(0); 3398 MVT::ValueType VT = N->getValueType(0); 3399 3400 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3401 // Only do this before legalize, since afterward the target may be depending 3402 // on the bitconvert. 3403 // First check to see if this is all constant. 3404 if (!AfterLegalize && 3405 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3406 MVT::isVector(VT)) { 3407 bool isSimple = true; 3408 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3409 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3410 N0.getOperand(i).getOpcode() != ISD::Constant && 3411 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3412 isSimple = false; 3413 break; 3414 } 3415 3416 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3417 assert(!MVT::isVector(DestEltVT) && 3418 "Element type of vector ValueType must not be vector!"); 3419 if (isSimple) { 3420 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3421 } 3422 } 3423 3424 // If the input is a constant, let getNode() fold it. 3425 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3426 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3427 if (Res.Val != N) return Res; 3428 } 3429 3430 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3431 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3432 3433 // fold (conv (load x)) -> (load (conv*)x) 3434 // If the resultant load doesn't need a higher alignment than the original! 3435 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3436 TLI.isOperationLegal(ISD::LOAD, VT)) { 3437 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3438 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3439 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3440 unsigned OrigAlign = LN0->getAlignment(); 3441 if (Align <= OrigAlign) { 3442 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3443 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3444 LN0->isVolatile(), Align); 3445 AddToWorkList(N); 3446 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3447 Load.getValue(1)); 3448 return Load; 3449 } 3450 } 3451 3452 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3453 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3454 // This often reduces constant pool loads. 3455 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3456 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) { 3457 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3458 AddToWorkList(NewConv.Val); 3459 3460 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); 3461 if (N0.getOpcode() == ISD::FNEG) 3462 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3463 assert(N0.getOpcode() == ISD::FABS); 3464 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3465 } 3466 3467 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3468 // Note that we don't handle copysign(x,cst) because this can always be folded 3469 // to an fneg or fabs. 3470 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3471 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3472 MVT::isInteger(VT) && !MVT::isVector(VT)) { 3473 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType()); 3474 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth), 3475 N0.getOperand(1)); 3476 AddToWorkList(X.Val); 3477 3478 // If X has a different width than the result/lhs, sext it or truncate it. 3479 unsigned VTWidth = MVT::getSizeInBits(VT); 3480 if (OrigXWidth < VTWidth) { 3481 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3482 AddToWorkList(X.Val); 3483 } else if (OrigXWidth > VTWidth) { 3484 // To get the sign bit in the right place, we have to shift it right 3485 // before truncating. 3486 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3487 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3488 AddToWorkList(X.Val); 3489 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3490 AddToWorkList(X.Val); 3491 } 3492 3493 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); 3494 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3495 AddToWorkList(X.Val); 3496 3497 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3498 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3499 AddToWorkList(Cst.Val); 3500 3501 return DAG.getNode(ISD::OR, VT, X, Cst); 3502 } 3503 3504 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3505 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3506 SDOperand CombineLD = CombineConsecutiveLoads(N0.Val, VT); 3507 if (CombineLD.Val) 3508 return CombineLD; 3509 } 3510 3511 return SDOperand(); 3512} 3513 3514SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3515 MVT::ValueType VT = N->getValueType(0); 3516 return CombineConsecutiveLoads(N, VT); 3517} 3518 3519/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3520/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3521/// destination element value type. 3522SDOperand DAGCombiner:: 3523ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3524 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3525 3526 // If this is already the right type, we're done. 3527 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3528 3529 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3530 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3531 3532 // If this is a conversion of N elements of one type to N elements of another 3533 // type, convert each element. This handles FP<->INT cases. 3534 if (SrcBitSize == DstBitSize) { 3535 SmallVector<SDOperand, 8> Ops; 3536 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3537 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3538 AddToWorkList(Ops.back().Val); 3539 } 3540 MVT::ValueType VT = 3541 MVT::getVectorType(DstEltVT, 3542 MVT::getVectorNumElements(BV->getValueType(0))); 3543 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3544 } 3545 3546 // Otherwise, we're growing or shrinking the elements. To avoid having to 3547 // handle annoying details of growing/shrinking FP values, we convert them to 3548 // int first. 3549 if (MVT::isFloatingPoint(SrcEltVT)) { 3550 // Convert the input float vector to a int vector where the elements are the 3551 // same sizes. 3552 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3553 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3554 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3555 SrcEltVT = IntVT; 3556 } 3557 3558 // Now we know the input is an integer vector. If the output is a FP type, 3559 // convert to integer first, then to FP of the right size. 3560 if (MVT::isFloatingPoint(DstEltVT)) { 3561 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3562 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3563 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3564 3565 // Next, convert to FP elements of the same size. 3566 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3567 } 3568 3569 // Okay, we know the src/dst types are both integers of differing types. 3570 // Handling growing first. 3571 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3572 if (SrcBitSize < DstBitSize) { 3573 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3574 3575 SmallVector<SDOperand, 8> Ops; 3576 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3577 i += NumInputsPerOutput) { 3578 bool isLE = TLI.isLittleEndian(); 3579 APInt NewBits = APInt(DstBitSize, 0); 3580 bool EltIsUndef = true; 3581 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3582 // Shift the previously computed bits over. 3583 NewBits <<= SrcBitSize; 3584 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3585 if (Op.getOpcode() == ISD::UNDEF) continue; 3586 EltIsUndef = false; 3587 3588 NewBits |= 3589 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3590 } 3591 3592 if (EltIsUndef) 3593 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3594 else 3595 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3596 } 3597 3598 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3599 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3600 } 3601 3602 // Finally, this must be the case where we are shrinking elements: each input 3603 // turns into multiple outputs. 3604 bool isS2V = ISD::isScalarToVector(BV); 3605 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3606 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3607 NumOutputsPerInput * BV->getNumOperands()); 3608 SmallVector<SDOperand, 8> Ops; 3609 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3610 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3611 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3612 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3613 continue; 3614 } 3615 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3616 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3617 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3618 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3619 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3620 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3621 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3622 OpVal = OpVal.lshr(DstBitSize); 3623 } 3624 3625 // For big endian targets, swap the order of the pieces of each element. 3626 if (TLI.isBigEndian()) 3627 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3628 } 3629 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3630} 3631 3632 3633 3634SDOperand DAGCombiner::visitFADD(SDNode *N) { 3635 SDOperand N0 = N->getOperand(0); 3636 SDOperand N1 = N->getOperand(1); 3637 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3638 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3639 MVT::ValueType VT = N->getValueType(0); 3640 3641 // fold vector ops 3642 if (MVT::isVector(VT)) { 3643 SDOperand FoldedVOp = SimplifyVBinOp(N); 3644 if (FoldedVOp.Val) return FoldedVOp; 3645 } 3646 3647 // fold (fadd c1, c2) -> c1+c2 3648 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3649 return DAG.getNode(ISD::FADD, VT, N0, N1); 3650 // canonicalize constant to RHS 3651 if (N0CFP && !N1CFP) 3652 return DAG.getNode(ISD::FADD, VT, N1, N0); 3653 // fold (A + (-B)) -> A-B 3654 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3655 return DAG.getNode(ISD::FSUB, VT, N0, 3656 GetNegatedExpression(N1, DAG, AfterLegalize)); 3657 // fold ((-A) + B) -> B-A 3658 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3659 return DAG.getNode(ISD::FSUB, VT, N1, 3660 GetNegatedExpression(N0, DAG, AfterLegalize)); 3661 3662 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3663 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3664 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3665 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3666 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3667 3668 return SDOperand(); 3669} 3670 3671SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3672 SDOperand N0 = N->getOperand(0); 3673 SDOperand N1 = N->getOperand(1); 3674 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3675 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3676 MVT::ValueType VT = N->getValueType(0); 3677 3678 // fold vector ops 3679 if (MVT::isVector(VT)) { 3680 SDOperand FoldedVOp = SimplifyVBinOp(N); 3681 if (FoldedVOp.Val) return FoldedVOp; 3682 } 3683 3684 // fold (fsub c1, c2) -> c1-c2 3685 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3686 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3687 // fold (0-B) -> -B 3688 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3689 if (isNegatibleForFree(N1, AfterLegalize)) 3690 return GetNegatedExpression(N1, DAG, AfterLegalize); 3691 return DAG.getNode(ISD::FNEG, VT, N1); 3692 } 3693 // fold (A-(-B)) -> A+B 3694 if (isNegatibleForFree(N1, AfterLegalize)) 3695 return DAG.getNode(ISD::FADD, VT, N0, 3696 GetNegatedExpression(N1, DAG, AfterLegalize)); 3697 3698 return SDOperand(); 3699} 3700 3701SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3702 SDOperand N0 = N->getOperand(0); 3703 SDOperand N1 = N->getOperand(1); 3704 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3705 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3706 MVT::ValueType VT = N->getValueType(0); 3707 3708 // fold vector ops 3709 if (MVT::isVector(VT)) { 3710 SDOperand FoldedVOp = SimplifyVBinOp(N); 3711 if (FoldedVOp.Val) return FoldedVOp; 3712 } 3713 3714 // fold (fmul c1, c2) -> c1*c2 3715 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3716 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3717 // canonicalize constant to RHS 3718 if (N0CFP && !N1CFP) 3719 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3720 // fold (fmul X, 2.0) -> (fadd X, X) 3721 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3722 return DAG.getNode(ISD::FADD, VT, N0, N0); 3723 // fold (fmul X, -1.0) -> (fneg X) 3724 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3725 return DAG.getNode(ISD::FNEG, VT, N0); 3726 3727 // -X * -Y -> X*Y 3728 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3729 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3730 // Both can be negated for free, check to see if at least one is cheaper 3731 // negated. 3732 if (LHSNeg == 2 || RHSNeg == 2) 3733 return DAG.getNode(ISD::FMUL, VT, 3734 GetNegatedExpression(N0, DAG, AfterLegalize), 3735 GetNegatedExpression(N1, DAG, AfterLegalize)); 3736 } 3737 } 3738 3739 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3740 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3741 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3742 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3743 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3744 3745 return SDOperand(); 3746} 3747 3748SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3749 SDOperand N0 = N->getOperand(0); 3750 SDOperand N1 = N->getOperand(1); 3751 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3752 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3753 MVT::ValueType VT = N->getValueType(0); 3754 3755 // fold vector ops 3756 if (MVT::isVector(VT)) { 3757 SDOperand FoldedVOp = SimplifyVBinOp(N); 3758 if (FoldedVOp.Val) return FoldedVOp; 3759 } 3760 3761 // fold (fdiv c1, c2) -> c1/c2 3762 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3763 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3764 3765 3766 // -X / -Y -> X*Y 3767 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3768 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3769 // Both can be negated for free, check to see if at least one is cheaper 3770 // negated. 3771 if (LHSNeg == 2 || RHSNeg == 2) 3772 return DAG.getNode(ISD::FDIV, VT, 3773 GetNegatedExpression(N0, DAG, AfterLegalize), 3774 GetNegatedExpression(N1, DAG, AfterLegalize)); 3775 } 3776 } 3777 3778 return SDOperand(); 3779} 3780 3781SDOperand DAGCombiner::visitFREM(SDNode *N) { 3782 SDOperand N0 = N->getOperand(0); 3783 SDOperand N1 = N->getOperand(1); 3784 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3785 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3786 MVT::ValueType VT = N->getValueType(0); 3787 3788 // fold (frem c1, c2) -> fmod(c1,c2) 3789 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3790 return DAG.getNode(ISD::FREM, VT, N0, N1); 3791 3792 return SDOperand(); 3793} 3794 3795SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3796 SDOperand N0 = N->getOperand(0); 3797 SDOperand N1 = N->getOperand(1); 3798 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3799 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3800 MVT::ValueType VT = N->getValueType(0); 3801 3802 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3803 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3804 3805 if (N1CFP) { 3806 const APFloat& V = N1CFP->getValueAPF(); 3807 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3808 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3809 if (!V.isNegative()) 3810 return DAG.getNode(ISD::FABS, VT, N0); 3811 else 3812 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3813 } 3814 3815 // copysign(fabs(x), y) -> copysign(x, y) 3816 // copysign(fneg(x), y) -> copysign(x, y) 3817 // copysign(copysign(x,z), y) -> copysign(x, y) 3818 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3819 N0.getOpcode() == ISD::FCOPYSIGN) 3820 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3821 3822 // copysign(x, abs(y)) -> abs(x) 3823 if (N1.getOpcode() == ISD::FABS) 3824 return DAG.getNode(ISD::FABS, VT, N0); 3825 3826 // copysign(x, copysign(y,z)) -> copysign(x, z) 3827 if (N1.getOpcode() == ISD::FCOPYSIGN) 3828 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3829 3830 // copysign(x, fp_extend(y)) -> copysign(x, y) 3831 // copysign(x, fp_round(y)) -> copysign(x, y) 3832 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3833 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3834 3835 return SDOperand(); 3836} 3837 3838 3839 3840SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3841 SDOperand N0 = N->getOperand(0); 3842 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3843 MVT::ValueType VT = N->getValueType(0); 3844 3845 // fold (sint_to_fp c1) -> c1fp 3846 if (N0C && N0.getValueType() != MVT::ppcf128) 3847 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3848 return SDOperand(); 3849} 3850 3851SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3852 SDOperand N0 = N->getOperand(0); 3853 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3854 MVT::ValueType VT = N->getValueType(0); 3855 3856 // fold (uint_to_fp c1) -> c1fp 3857 if (N0C && N0.getValueType() != MVT::ppcf128) 3858 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3859 return SDOperand(); 3860} 3861 3862SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3863 SDOperand N0 = N->getOperand(0); 3864 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3865 MVT::ValueType VT = N->getValueType(0); 3866 3867 // fold (fp_to_sint c1fp) -> c1 3868 if (N0CFP) 3869 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3870 return SDOperand(); 3871} 3872 3873SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3874 SDOperand N0 = N->getOperand(0); 3875 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3876 MVT::ValueType VT = N->getValueType(0); 3877 3878 // fold (fp_to_uint c1fp) -> c1 3879 if (N0CFP && VT != MVT::ppcf128) 3880 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3881 return SDOperand(); 3882} 3883 3884SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3885 SDOperand N0 = N->getOperand(0); 3886 SDOperand N1 = N->getOperand(1); 3887 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3888 MVT::ValueType VT = N->getValueType(0); 3889 3890 // fold (fp_round c1fp) -> c1fp 3891 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3892 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3893 3894 // fold (fp_round (fp_extend x)) -> x 3895 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3896 return N0.getOperand(0); 3897 3898 // fold (fp_round (fp_round x)) -> (fp_round x) 3899 if (N0.getOpcode() == ISD::FP_ROUND) { 3900 // This is a value preserving truncation if both round's are. 3901 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3902 N0.Val->getConstantOperandVal(1) == 1; 3903 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3904 DAG.getIntPtrConstant(IsTrunc)); 3905 } 3906 3907 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3908 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3909 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3910 AddToWorkList(Tmp.Val); 3911 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3912 } 3913 3914 return SDOperand(); 3915} 3916 3917SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3918 SDOperand N0 = N->getOperand(0); 3919 MVT::ValueType VT = N->getValueType(0); 3920 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3921 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3922 3923 // fold (fp_round_inreg c1fp) -> c1fp 3924 if (N0CFP) { 3925 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3926 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3927 } 3928 return SDOperand(); 3929} 3930 3931SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3932 SDOperand N0 = N->getOperand(0); 3933 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3934 MVT::ValueType VT = N->getValueType(0); 3935 3936 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3937 if (N->hasOneUse() && 3938 N->use_begin()->getSDOperand().getOpcode() == ISD::FP_ROUND) 3939 return SDOperand(); 3940 3941 // fold (fp_extend c1fp) -> c1fp 3942 if (N0CFP && VT != MVT::ppcf128) 3943 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3944 3945 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3946 // value of X. 3947 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3948 SDOperand In = N0.getOperand(0); 3949 if (In.getValueType() == VT) return In; 3950 if (VT < In.getValueType()) 3951 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3952 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3953 } 3954 3955 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3956 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3957 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3958 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3959 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3960 LN0->getBasePtr(), LN0->getSrcValue(), 3961 LN0->getSrcValueOffset(), 3962 N0.getValueType(), 3963 LN0->isVolatile(), 3964 LN0->getAlignment()); 3965 CombineTo(N, ExtLoad); 3966 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3967 DAG.getIntPtrConstant(1)), 3968 ExtLoad.getValue(1)); 3969 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3970 } 3971 3972 3973 return SDOperand(); 3974} 3975 3976SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3977 SDOperand N0 = N->getOperand(0); 3978 3979 if (isNegatibleForFree(N0, AfterLegalize)) 3980 return GetNegatedExpression(N0, DAG, AfterLegalize); 3981 3982 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 3983 // constant pool values. 3984 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3985 MVT::isInteger(N0.getOperand(0).getValueType()) && 3986 !MVT::isVector(N0.getOperand(0).getValueType())) { 3987 SDOperand Int = N0.getOperand(0); 3988 MVT::ValueType IntVT = Int.getValueType(); 3989 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3990 Int = DAG.getNode(ISD::XOR, IntVT, Int, 3991 DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT)); 3992 AddToWorkList(Int.Val); 3993 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3994 } 3995 } 3996 3997 return SDOperand(); 3998} 3999 4000SDOperand DAGCombiner::visitFABS(SDNode *N) { 4001 SDOperand N0 = N->getOperand(0); 4002 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4003 MVT::ValueType VT = N->getValueType(0); 4004 4005 // fold (fabs c1) -> fabs(c1) 4006 if (N0CFP && VT != MVT::ppcf128) 4007 return DAG.getNode(ISD::FABS, VT, N0); 4008 // fold (fabs (fabs x)) -> (fabs x) 4009 if (N0.getOpcode() == ISD::FABS) 4010 return N->getOperand(0); 4011 // fold (fabs (fneg x)) -> (fabs x) 4012 // fold (fabs (fcopysign x, y)) -> (fabs x) 4013 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4014 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4015 4016 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4017 // constant pool values. 4018 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 4019 MVT::isInteger(N0.getOperand(0).getValueType()) && 4020 !MVT::isVector(N0.getOperand(0).getValueType())) { 4021 SDOperand Int = N0.getOperand(0); 4022 MVT::ValueType IntVT = Int.getValueType(); 4023 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 4024 Int = DAG.getNode(ISD::AND, IntVT, Int, 4025 DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT)); 4026 AddToWorkList(Int.Val); 4027 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4028 } 4029 } 4030 4031 return SDOperand(); 4032} 4033 4034SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 4035 SDOperand Chain = N->getOperand(0); 4036 SDOperand N1 = N->getOperand(1); 4037 SDOperand N2 = N->getOperand(2); 4038 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4039 4040 // never taken branch, fold to chain 4041 if (N1C && N1C->isNullValue()) 4042 return Chain; 4043 // unconditional branch 4044 if (N1C && N1C->getAPIntValue() == 1) 4045 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4046 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4047 // on the target. 4048 if (N1.getOpcode() == ISD::SETCC && 4049 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4050 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4051 N1.getOperand(0), N1.getOperand(1), N2); 4052 } 4053 return SDOperand(); 4054} 4055 4056// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4057// 4058SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 4059 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4060 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4061 4062 // Use SimplifySetCC to simplify SETCC's. 4063 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 4064 if (Simp.Val) AddToWorkList(Simp.Val); 4065 4066 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 4067 4068 // fold br_cc true, dest -> br dest (unconditional branch) 4069 if (SCCC && !SCCC->isNullValue()) 4070 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4071 N->getOperand(4)); 4072 // fold br_cc false, dest -> unconditional fall through 4073 if (SCCC && SCCC->isNullValue()) 4074 return N->getOperand(0); 4075 4076 // fold to a simpler setcc 4077 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 4078 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4079 Simp.getOperand(2), Simp.getOperand(0), 4080 Simp.getOperand(1), N->getOperand(4)); 4081 return SDOperand(); 4082} 4083 4084 4085/// CombineToPreIndexedLoadStore - Try turning a load / store and a 4086/// pre-indexed load / store when the base pointer is a add or subtract 4087/// and it has other uses besides the load / store. After the 4088/// transformation, the new indexed load / store has effectively folded 4089/// the add / subtract in and all of its other uses are redirected to the 4090/// new load / store. 4091bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4092 if (!AfterLegalize) 4093 return false; 4094 4095 bool isLoad = true; 4096 SDOperand Ptr; 4097 MVT::ValueType VT; 4098 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4099 if (LD->isIndexed()) 4100 return false; 4101 VT = LD->getMemoryVT(); 4102 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4103 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4104 return false; 4105 Ptr = LD->getBasePtr(); 4106 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4107 if (ST->isIndexed()) 4108 return false; 4109 VT = ST->getMemoryVT(); 4110 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4111 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4112 return false; 4113 Ptr = ST->getBasePtr(); 4114 isLoad = false; 4115 } else 4116 return false; 4117 4118 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4119 // out. There is no reason to make this a preinc/predec. 4120 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4121 Ptr.Val->hasOneUse()) 4122 return false; 4123 4124 // Ask the target to do addressing mode selection. 4125 SDOperand BasePtr; 4126 SDOperand Offset; 4127 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4128 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4129 return false; 4130 // Don't create a indexed load / store with zero offset. 4131 if (isa<ConstantSDNode>(Offset) && 4132 cast<ConstantSDNode>(Offset)->isNullValue()) 4133 return false; 4134 4135 // Try turning it into a pre-indexed load / store except when: 4136 // 1) The new base ptr is a frame index. 4137 // 2) If N is a store and the new base ptr is either the same as or is a 4138 // predecessor of the value being stored. 4139 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4140 // that would create a cycle. 4141 // 4) All uses are load / store ops that use it as old base ptr. 4142 4143 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4144 // (plus the implicit offset) to a register to preinc anyway. 4145 if (isa<FrameIndexSDNode>(BasePtr)) 4146 return false; 4147 4148 // Check #2. 4149 if (!isLoad) { 4150 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 4151 if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val)) 4152 return false; 4153 } 4154 4155 // Now check for #3 and #4. 4156 bool RealUse = false; 4157 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4158 E = Ptr.Val->use_end(); I != E; ++I) { 4159 SDNode *Use = I->getUser(); 4160 if (Use == N) 4161 continue; 4162 if (Use->isPredecessorOf(N)) 4163 return false; 4164 4165 if (!((Use->getOpcode() == ISD::LOAD && 4166 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4167 (Use->getOpcode() == ISD::STORE && 4168 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4169 RealUse = true; 4170 } 4171 if (!RealUse) 4172 return false; 4173 4174 SDOperand Result; 4175 if (isLoad) 4176 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 4177 else 4178 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4179 ++PreIndexedNodes; 4180 ++NodesCombined; 4181 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4182 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4183 DOUT << '\n'; 4184 WorkListRemover DeadNodes(*this); 4185 if (isLoad) { 4186 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4187 &DeadNodes); 4188 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4189 &DeadNodes); 4190 } else { 4191 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4192 &DeadNodes); 4193 } 4194 4195 // Finally, since the node is now dead, remove it from the graph. 4196 DAG.DeleteNode(N); 4197 4198 // Replace the uses of Ptr with uses of the updated base value. 4199 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4200 &DeadNodes); 4201 removeFromWorkList(Ptr.Val); 4202 DAG.DeleteNode(Ptr.Val); 4203 4204 return true; 4205} 4206 4207/// CombineToPostIndexedLoadStore - Try combine a load / store with a 4208/// add / sub of the base pointer node into a post-indexed load / store. 4209/// The transformation folded the add / subtract into the new indexed 4210/// load / store effectively and all of its uses are redirected to the 4211/// new load / store. 4212bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4213 if (!AfterLegalize) 4214 return false; 4215 4216 bool isLoad = true; 4217 SDOperand Ptr; 4218 MVT::ValueType VT; 4219 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4220 if (LD->isIndexed()) 4221 return false; 4222 VT = LD->getMemoryVT(); 4223 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4224 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4225 return false; 4226 Ptr = LD->getBasePtr(); 4227 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4228 if (ST->isIndexed()) 4229 return false; 4230 VT = ST->getMemoryVT(); 4231 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4232 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4233 return false; 4234 Ptr = ST->getBasePtr(); 4235 isLoad = false; 4236 } else 4237 return false; 4238 4239 if (Ptr.Val->hasOneUse()) 4240 return false; 4241 4242 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4243 E = Ptr.Val->use_end(); I != E; ++I) { 4244 SDNode *Op = I->getUser(); 4245 if (Op == N || 4246 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4247 continue; 4248 4249 SDOperand BasePtr; 4250 SDOperand Offset; 4251 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4252 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4253 if (Ptr == Offset) 4254 std::swap(BasePtr, Offset); 4255 if (Ptr != BasePtr) 4256 continue; 4257 // Don't create a indexed load / store with zero offset. 4258 if (isa<ConstantSDNode>(Offset) && 4259 cast<ConstantSDNode>(Offset)->isNullValue()) 4260 continue; 4261 4262 // Try turning it into a post-indexed load / store except when 4263 // 1) All uses are load / store ops that use it as base ptr. 4264 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4265 // nor a successor of N. Otherwise, if Op is folded that would 4266 // create a cycle. 4267 4268 // Check for #1. 4269 bool TryNext = false; 4270 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4271 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4272 SDNode *Use = II->getUser(); 4273 if (Use == Ptr.Val) 4274 continue; 4275 4276 // If all the uses are load / store addresses, then don't do the 4277 // transformation. 4278 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4279 bool RealUse = false; 4280 for (SDNode::use_iterator III = Use->use_begin(), 4281 EEE = Use->use_end(); III != EEE; ++III) { 4282 SDNode *UseUse = III->getUser(); 4283 if (!((UseUse->getOpcode() == ISD::LOAD && 4284 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4285 (UseUse->getOpcode() == ISD::STORE && 4286 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))) 4287 RealUse = true; 4288 } 4289 4290 if (!RealUse) { 4291 TryNext = true; 4292 break; 4293 } 4294 } 4295 } 4296 if (TryNext) 4297 continue; 4298 4299 // Check for #2 4300 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4301 SDOperand Result = isLoad 4302 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4303 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4304 ++PostIndexedNodes; 4305 ++NodesCombined; 4306 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4307 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4308 DOUT << '\n'; 4309 WorkListRemover DeadNodes(*this); 4310 if (isLoad) { 4311 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4312 &DeadNodes); 4313 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4314 &DeadNodes); 4315 } else { 4316 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4317 &DeadNodes); 4318 } 4319 4320 // Finally, since the node is now dead, remove it from the graph. 4321 DAG.DeleteNode(N); 4322 4323 // Replace the uses of Use with uses of the updated base value. 4324 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4325 Result.getValue(isLoad ? 1 : 0), 4326 &DeadNodes); 4327 removeFromWorkList(Op); 4328 DAG.DeleteNode(Op); 4329 return true; 4330 } 4331 } 4332 } 4333 return false; 4334} 4335 4336/// InferAlignment - If we can infer some alignment information from this 4337/// pointer, return it. 4338static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4339 // If this is a direct reference to a stack slot, use information about the 4340 // stack slot's alignment. 4341 int FrameIdx = 1 << 31; 4342 int64_t FrameOffset = 0; 4343 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4344 FrameIdx = FI->getIndex(); 4345 } else if (Ptr.getOpcode() == ISD::ADD && 4346 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4347 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4348 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4349 FrameOffset = Ptr.getConstantOperandVal(1); 4350 } 4351 4352 if (FrameIdx != (1 << 31)) { 4353 // FIXME: Handle FI+CST. 4354 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4355 if (MFI.isFixedObjectIndex(FrameIdx)) { 4356 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4357 4358 // The alignment of the frame index can be determined from its offset from 4359 // the incoming frame position. If the frame object is at offset 32 and 4360 // the stack is guaranteed to be 16-byte aligned, then we know that the 4361 // object is 16-byte aligned. 4362 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4363 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4364 4365 // Finally, the frame object itself may have a known alignment. Factor 4366 // the alignment + offset into a new alignment. For example, if we know 4367 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4368 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4369 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4370 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4371 FrameOffset); 4372 return std::max(Align, FIInfoAlign); 4373 } 4374 } 4375 4376 return 0; 4377} 4378 4379SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4380 LoadSDNode *LD = cast<LoadSDNode>(N); 4381 SDOperand Chain = LD->getChain(); 4382 SDOperand Ptr = LD->getBasePtr(); 4383 4384 // Try to infer better alignment information than the load already has. 4385 if (LD->isUnindexed()) { 4386 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4387 if (Align > LD->getAlignment()) 4388 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4389 Chain, Ptr, LD->getSrcValue(), 4390 LD->getSrcValueOffset(), LD->getMemoryVT(), 4391 LD->isVolatile(), Align); 4392 } 4393 } 4394 4395 4396 // If load is not volatile and there are no uses of the loaded value (and 4397 // the updated indexed value in case of indexed loads), change uses of the 4398 // chain value into uses of the chain input (i.e. delete the dead load). 4399 if (!LD->isVolatile()) { 4400 if (N->getValueType(1) == MVT::Other) { 4401 // Unindexed loads. 4402 if (N->hasNUsesOfValue(0, 0)) { 4403 // It's not safe to use the two value CombineTo variant here. e.g. 4404 // v1, chain2 = load chain1, loc 4405 // v2, chain3 = load chain2, loc 4406 // v3 = add v2, c 4407 // Now we replace use of chain2 with chain1. This makes the second load 4408 // isomorphic to the one we are deleting, and thus makes this load live. 4409 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4410 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4411 DOUT << "\n"; 4412 WorkListRemover DeadNodes(*this); 4413 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes); 4414 if (N->use_empty()) { 4415 removeFromWorkList(N); 4416 DAG.DeleteNode(N); 4417 } 4418 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4419 } 4420 } else { 4421 // Indexed loads. 4422 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4423 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4424 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4425 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4426 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4427 DOUT << " and 2 other values\n"; 4428 WorkListRemover DeadNodes(*this); 4429 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes); 4430 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4431 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4432 &DeadNodes); 4433 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes); 4434 removeFromWorkList(N); 4435 DAG.DeleteNode(N); 4436 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4437 } 4438 } 4439 } 4440 4441 // If this load is directly stored, replace the load value with the stored 4442 // value. 4443 // TODO: Handle store large -> read small portion. 4444 // TODO: Handle TRUNCSTORE/LOADEXT 4445 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4446 !LD->isVolatile()) { 4447 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4448 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4449 if (PrevST->getBasePtr() == Ptr && 4450 PrevST->getValue().getValueType() == N->getValueType(0)) 4451 return CombineTo(N, Chain.getOperand(1), Chain); 4452 } 4453 } 4454 4455 if (CombinerAA) { 4456 // Walk up chain skipping non-aliasing memory nodes. 4457 SDOperand BetterChain = FindBetterChain(N, Chain); 4458 4459 // If there is a better chain. 4460 if (Chain != BetterChain) { 4461 SDOperand ReplLoad; 4462 4463 // Replace the chain to void dependency. 4464 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4465 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4466 LD->getSrcValue(), LD->getSrcValueOffset(), 4467 LD->isVolatile(), LD->getAlignment()); 4468 } else { 4469 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4470 LD->getValueType(0), 4471 BetterChain, Ptr, LD->getSrcValue(), 4472 LD->getSrcValueOffset(), 4473 LD->getMemoryVT(), 4474 LD->isVolatile(), 4475 LD->getAlignment()); 4476 } 4477 4478 // Create token factor to keep old chain connected. 4479 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4480 Chain, ReplLoad.getValue(1)); 4481 4482 // Replace uses with load result and token factor. Don't add users 4483 // to work list. 4484 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4485 } 4486 } 4487 4488 // Try transforming N to an indexed load. 4489 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4490 return SDOperand(N, 0); 4491 4492 return SDOperand(); 4493} 4494 4495 4496SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4497 StoreSDNode *ST = cast<StoreSDNode>(N); 4498 SDOperand Chain = ST->getChain(); 4499 SDOperand Value = ST->getValue(); 4500 SDOperand Ptr = ST->getBasePtr(); 4501 4502 // Try to infer better alignment information than the store already has. 4503 if (ST->isUnindexed()) { 4504 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4505 if (Align > ST->getAlignment()) 4506 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4507 ST->getSrcValueOffset(), ST->getMemoryVT(), 4508 ST->isVolatile(), Align); 4509 } 4510 } 4511 4512 // If this is a store of a bit convert, store the input value if the 4513 // resultant store does not need a higher alignment than the original. 4514 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4515 ST->isUnindexed()) { 4516 unsigned Align = ST->getAlignment(); 4517 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4518 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4519 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4520 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4521 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4522 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4523 } 4524 4525 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4526 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4527 if (Value.getOpcode() != ISD::TargetConstantFP) { 4528 SDOperand Tmp; 4529 switch (CFP->getValueType(0)) { 4530 default: assert(0 && "Unknown FP type"); 4531 case MVT::f80: // We don't do this for these yet. 4532 case MVT::f128: 4533 case MVT::ppcf128: 4534 break; 4535 case MVT::f32: 4536 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4537 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4538 convertToAPInt().getZExtValue(), MVT::i32); 4539 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4540 ST->getSrcValueOffset(), ST->isVolatile(), 4541 ST->getAlignment()); 4542 } 4543 break; 4544 case MVT::f64: 4545 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4546 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4547 getZExtValue(), MVT::i64); 4548 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4549 ST->getSrcValueOffset(), ST->isVolatile(), 4550 ST->getAlignment()); 4551 } else if (TLI.isTypeLegal(MVT::i32)) { 4552 // Many FP stores are not made apparent until after legalize, e.g. for 4553 // argument passing. Since this is so common, custom legalize the 4554 // 64-bit integer store into two 32-bit stores. 4555 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4556 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4557 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4558 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4559 4560 int SVOffset = ST->getSrcValueOffset(); 4561 unsigned Alignment = ST->getAlignment(); 4562 bool isVolatile = ST->isVolatile(); 4563 4564 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4565 ST->getSrcValueOffset(), 4566 isVolatile, ST->getAlignment()); 4567 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4568 DAG.getConstant(4, Ptr.getValueType())); 4569 SVOffset += 4; 4570 Alignment = MinAlign(Alignment, 4U); 4571 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4572 SVOffset, isVolatile, Alignment); 4573 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4574 } 4575 break; 4576 } 4577 } 4578 } 4579 4580 if (CombinerAA) { 4581 // Walk up chain skipping non-aliasing memory nodes. 4582 SDOperand BetterChain = FindBetterChain(N, Chain); 4583 4584 // If there is a better chain. 4585 if (Chain != BetterChain) { 4586 // Replace the chain to avoid dependency. 4587 SDOperand ReplStore; 4588 if (ST->isTruncatingStore()) { 4589 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4590 ST->getSrcValue(),ST->getSrcValueOffset(), 4591 ST->getMemoryVT(), 4592 ST->isVolatile(), ST->getAlignment()); 4593 } else { 4594 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4595 ST->getSrcValue(), ST->getSrcValueOffset(), 4596 ST->isVolatile(), ST->getAlignment()); 4597 } 4598 4599 // Create token to keep both nodes around. 4600 SDOperand Token = 4601 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4602 4603 // Don't add users to work list. 4604 return CombineTo(N, Token, false); 4605 } 4606 } 4607 4608 // Try transforming N to an indexed store. 4609 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4610 return SDOperand(N, 0); 4611 4612 // FIXME: is there such a thing as a truncating indexed store? 4613 if (ST->isTruncatingStore() && ST->isUnindexed() && 4614 MVT::isInteger(Value.getValueType())) { 4615 // See if we can simplify the input to this truncstore with knowledge that 4616 // only the low bits are being used. For example: 4617 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4618 SDOperand Shorter = 4619 GetDemandedBits(Value, 4620 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4621 MVT::getSizeInBits(ST->getMemoryVT()))); 4622 AddToWorkList(Value.Val); 4623 if (Shorter.Val) 4624 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4625 ST->getSrcValueOffset(), ST->getMemoryVT(), 4626 ST->isVolatile(), ST->getAlignment()); 4627 4628 // Otherwise, see if we can simplify the operation with 4629 // SimplifyDemandedBits, which only works if the value has a single use. 4630 if (SimplifyDemandedBits(Value, 4631 APInt::getLowBitsSet( 4632 Value.getValueSizeInBits(), 4633 MVT::getSizeInBits(ST->getMemoryVT())))) 4634 return SDOperand(N, 0); 4635 } 4636 4637 // If this is a load followed by a store to the same location, then the store 4638 // is dead/noop. 4639 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4640 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4641 ST->isUnindexed() && !ST->isVolatile() && 4642 // There can't be any side effects between the load and store, such as 4643 // a call or store. 4644 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4645 // The store is dead, remove it. 4646 return Chain; 4647 } 4648 } 4649 4650 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4651 // truncating store. We can do this even if this is already a truncstore. 4652 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4653 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) && 4654 Value.Val->hasOneUse() && ST->isUnindexed() && 4655 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4656 ST->getMemoryVT())) { 4657 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4658 ST->getSrcValueOffset(), ST->getMemoryVT(), 4659 ST->isVolatile(), ST->getAlignment()); 4660 } 4661 4662 return SDOperand(); 4663} 4664 4665SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4666 SDOperand InVec = N->getOperand(0); 4667 SDOperand InVal = N->getOperand(1); 4668 SDOperand EltNo = N->getOperand(2); 4669 4670 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4671 // vector with the inserted element. 4672 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4673 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4674 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4675 if (Elt < Ops.size()) 4676 Ops[Elt] = InVal; 4677 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4678 &Ops[0], Ops.size()); 4679 } 4680 4681 return SDOperand(); 4682} 4683 4684SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4685 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4686 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4687 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4688 4689 // Perform only after legalization to ensure build_vector / vector_shuffle 4690 // optimizations have already been done. 4691 if (!AfterLegalize) return SDOperand(); 4692 4693 SDOperand InVec = N->getOperand(0); 4694 SDOperand EltNo = N->getOperand(1); 4695 4696 if (isa<ConstantSDNode>(EltNo)) { 4697 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4698 bool NewLoad = false; 4699 MVT::ValueType VT = InVec.getValueType(); 4700 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4701 MVT::ValueType LVT = EVT; 4702 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4703 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4704 if (!MVT::isVector(BCVT) 4705 || (MVT::getSizeInBits(EVT) > 4706 MVT::getSizeInBits(MVT::getVectorElementType(BCVT)))) 4707 return SDOperand(); 4708 InVec = InVec.getOperand(0); 4709 EVT = MVT::getVectorElementType(BCVT); 4710 NewLoad = true; 4711 } 4712 4713 LoadSDNode *LN0 = NULL; 4714 if (ISD::isNormalLoad(InVec.Val)) 4715 LN0 = cast<LoadSDNode>(InVec); 4716 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4717 InVec.getOperand(0).getValueType() == EVT && 4718 ISD::isNormalLoad(InVec.getOperand(0).Val)) { 4719 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4720 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4721 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4722 // => 4723 // (load $addr+1*size) 4724 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4725 getOperand(Elt))->getValue(); 4726 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4727 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4728 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4729 InVec = InVec.getOperand(0); 4730 if (ISD::isNormalLoad(InVec.Val)) { 4731 LN0 = cast<LoadSDNode>(InVec); 4732 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4733 } 4734 } 4735 if (!LN0 || !LN0->hasOneUse()) 4736 return SDOperand(); 4737 4738 unsigned Align = LN0->getAlignment(); 4739 if (NewLoad) { 4740 // Check the resultant load doesn't need a higher alignment than the 4741 // original load. 4742 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4743 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4744 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4745 return SDOperand(); 4746 Align = NewAlign; 4747 } 4748 4749 SDOperand NewPtr = LN0->getBasePtr(); 4750 if (Elt) { 4751 unsigned PtrOff = MVT::getSizeInBits(LVT) * Elt / 8; 4752 MVT::ValueType PtrType = NewPtr.getValueType(); 4753 if (TLI.isBigEndian()) 4754 PtrOff = MVT::getSizeInBits(VT) / 8 - PtrOff; 4755 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4756 DAG.getConstant(PtrOff, PtrType)); 4757 } 4758 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4759 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4760 LN0->isVolatile(), Align); 4761 } 4762 return SDOperand(); 4763} 4764 4765 4766SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4767 unsigned NumInScalars = N->getNumOperands(); 4768 MVT::ValueType VT = N->getValueType(0); 4769 unsigned NumElts = MVT::getVectorNumElements(VT); 4770 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4771 4772 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4773 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4774 // at most two distinct vectors, turn this into a shuffle node. 4775 SDOperand VecIn1, VecIn2; 4776 for (unsigned i = 0; i != NumInScalars; ++i) { 4777 // Ignore undef inputs. 4778 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4779 4780 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4781 // constant index, bail out. 4782 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4783 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4784 VecIn1 = VecIn2 = SDOperand(0, 0); 4785 break; 4786 } 4787 4788 // If the input vector type disagrees with the result of the build_vector, 4789 // we can't make a shuffle. 4790 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4791 if (ExtractedFromVec.getValueType() != VT) { 4792 VecIn1 = VecIn2 = SDOperand(0, 0); 4793 break; 4794 } 4795 4796 // Otherwise, remember this. We allow up to two distinct input vectors. 4797 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4798 continue; 4799 4800 if (VecIn1.Val == 0) { 4801 VecIn1 = ExtractedFromVec; 4802 } else if (VecIn2.Val == 0) { 4803 VecIn2 = ExtractedFromVec; 4804 } else { 4805 // Too many inputs. 4806 VecIn1 = VecIn2 = SDOperand(0, 0); 4807 break; 4808 } 4809 } 4810 4811 // If everything is good, we can make a shuffle operation. 4812 if (VecIn1.Val) { 4813 SmallVector<SDOperand, 8> BuildVecIndices; 4814 for (unsigned i = 0; i != NumInScalars; ++i) { 4815 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4816 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4817 continue; 4818 } 4819 4820 SDOperand Extract = N->getOperand(i); 4821 4822 // If extracting from the first vector, just use the index directly. 4823 if (Extract.getOperand(0) == VecIn1) { 4824 BuildVecIndices.push_back(Extract.getOperand(1)); 4825 continue; 4826 } 4827 4828 // Otherwise, use InIdx + VecSize 4829 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4830 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4831 } 4832 4833 // Add count and size info. 4834 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); 4835 4836 // Return the new VECTOR_SHUFFLE node. 4837 SDOperand Ops[5]; 4838 Ops[0] = VecIn1; 4839 if (VecIn2.Val) { 4840 Ops[1] = VecIn2; 4841 } else { 4842 // Use an undef build_vector as input for the second operand. 4843 std::vector<SDOperand> UnOps(NumInScalars, 4844 DAG.getNode(ISD::UNDEF, 4845 EltType)); 4846 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4847 &UnOps[0], UnOps.size()); 4848 AddToWorkList(Ops[1].Val); 4849 } 4850 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4851 &BuildVecIndices[0], BuildVecIndices.size()); 4852 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4853 } 4854 4855 return SDOperand(); 4856} 4857 4858SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4859 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4860 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4861 // inputs come from at most two distinct vectors, turn this into a shuffle 4862 // node. 4863 4864 // If we only have one input vector, we don't need to do any concatenation. 4865 if (N->getNumOperands() == 1) { 4866 return N->getOperand(0); 4867 } 4868 4869 return SDOperand(); 4870} 4871 4872SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4873 SDOperand ShufMask = N->getOperand(2); 4874 unsigned NumElts = ShufMask.getNumOperands(); 4875 4876 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4877 bool isIdentity = true; 4878 for (unsigned i = 0; i != NumElts; ++i) { 4879 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4880 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4881 isIdentity = false; 4882 break; 4883 } 4884 } 4885 if (isIdentity) return N->getOperand(0); 4886 4887 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4888 isIdentity = true; 4889 for (unsigned i = 0; i != NumElts; ++i) { 4890 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4891 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4892 isIdentity = false; 4893 break; 4894 } 4895 } 4896 if (isIdentity) return N->getOperand(1); 4897 4898 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4899 // needed at all. 4900 bool isUnary = true; 4901 bool isSplat = true; 4902 int VecNum = -1; 4903 unsigned BaseIdx = 0; 4904 for (unsigned i = 0; i != NumElts; ++i) 4905 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4906 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4907 int V = (Idx < NumElts) ? 0 : 1; 4908 if (VecNum == -1) { 4909 VecNum = V; 4910 BaseIdx = Idx; 4911 } else { 4912 if (BaseIdx != Idx) 4913 isSplat = false; 4914 if (VecNum != V) { 4915 isUnary = false; 4916 break; 4917 } 4918 } 4919 } 4920 4921 SDOperand N0 = N->getOperand(0); 4922 SDOperand N1 = N->getOperand(1); 4923 // Normalize unary shuffle so the RHS is undef. 4924 if (isUnary && VecNum == 1) 4925 std::swap(N0, N1); 4926 4927 // If it is a splat, check if the argument vector is a build_vector with 4928 // all scalar elements the same. 4929 if (isSplat) { 4930 SDNode *V = N0.Val; 4931 4932 // If this is a bit convert that changes the element type of the vector but 4933 // not the number of vector elements, look through it. Be careful not to 4934 // look though conversions that change things like v4f32 to v2f64. 4935 if (V->getOpcode() == ISD::BIT_CONVERT) { 4936 SDOperand ConvInput = V->getOperand(0); 4937 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4938 V = ConvInput.Val; 4939 } 4940 4941 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4942 unsigned NumElems = V->getNumOperands(); 4943 if (NumElems > BaseIdx) { 4944 SDOperand Base; 4945 bool AllSame = true; 4946 for (unsigned i = 0; i != NumElems; ++i) { 4947 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4948 Base = V->getOperand(i); 4949 break; 4950 } 4951 } 4952 // Splat of <u, u, u, u>, return <u, u, u, u> 4953 if (!Base.Val) 4954 return N0; 4955 for (unsigned i = 0; i != NumElems; ++i) { 4956 if (V->getOperand(i) != Base) { 4957 AllSame = false; 4958 break; 4959 } 4960 } 4961 // Splat of <x, x, x, x>, return <x, x, x, x> 4962 if (AllSame) 4963 return N0; 4964 } 4965 } 4966 } 4967 4968 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4969 // into an undef. 4970 if (isUnary || N0 == N1) { 4971 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4972 // first operand. 4973 SmallVector<SDOperand, 8> MappedOps; 4974 for (unsigned i = 0; i != NumElts; ++i) { 4975 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4976 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4977 MappedOps.push_back(ShufMask.getOperand(i)); 4978 } else { 4979 unsigned NewIdx = 4980 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4981 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4982 } 4983 } 4984 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4985 &MappedOps[0], MappedOps.size()); 4986 AddToWorkList(ShufMask.Val); 4987 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4988 N0, 4989 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4990 ShufMask); 4991 } 4992 4993 return SDOperand(); 4994} 4995 4996/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4997/// an AND to a vector_shuffle with the destination vector and a zero vector. 4998/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4999/// vector_shuffle V, Zero, <0, 4, 2, 4> 5000SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5001 SDOperand LHS = N->getOperand(0); 5002 SDOperand RHS = N->getOperand(1); 5003 if (N->getOpcode() == ISD::AND) { 5004 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5005 RHS = RHS.getOperand(0); 5006 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5007 std::vector<SDOperand> IdxOps; 5008 unsigned NumOps = RHS.getNumOperands(); 5009 unsigned NumElts = NumOps; 5010 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 5011 for (unsigned i = 0; i != NumElts; ++i) { 5012 SDOperand Elt = RHS.getOperand(i); 5013 if (!isa<ConstantSDNode>(Elt)) 5014 return SDOperand(); 5015 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5016 IdxOps.push_back(DAG.getConstant(i, EVT)); 5017 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5018 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 5019 else 5020 return SDOperand(); 5021 } 5022 5023 // Let's see if the target supports this vector_shuffle. 5024 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 5025 return SDOperand(); 5026 5027 // Return the new VECTOR_SHUFFLE node. 5028 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 5029 std::vector<SDOperand> Ops; 5030 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5031 Ops.push_back(LHS); 5032 AddToWorkList(LHS.Val); 5033 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5034 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5035 &ZeroOps[0], ZeroOps.size())); 5036 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5037 &IdxOps[0], IdxOps.size())); 5038 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5039 &Ops[0], Ops.size()); 5040 if (VT != LHS.getValueType()) { 5041 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 5042 } 5043 return Result; 5044 } 5045 } 5046 return SDOperand(); 5047} 5048 5049/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5050SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 5051 // After legalize, the target may be depending on adds and other 5052 // binary ops to provide legal ways to construct constants or other 5053 // things. Simplifying them may result in a loss of legality. 5054 if (AfterLegalize) return SDOperand(); 5055 5056 MVT::ValueType VT = N->getValueType(0); 5057 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 5058 5059 MVT::ValueType EltType = MVT::getVectorElementType(VT); 5060 SDOperand LHS = N->getOperand(0); 5061 SDOperand RHS = N->getOperand(1); 5062 SDOperand Shuffle = XformToShuffleWithZero(N); 5063 if (Shuffle.Val) return Shuffle; 5064 5065 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5066 // this operation. 5067 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5068 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5069 SmallVector<SDOperand, 8> Ops; 5070 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5071 SDOperand LHSOp = LHS.getOperand(i); 5072 SDOperand RHSOp = RHS.getOperand(i); 5073 // If these two elements can't be folded, bail out. 5074 if ((LHSOp.getOpcode() != ISD::UNDEF && 5075 LHSOp.getOpcode() != ISD::Constant && 5076 LHSOp.getOpcode() != ISD::ConstantFP) || 5077 (RHSOp.getOpcode() != ISD::UNDEF && 5078 RHSOp.getOpcode() != ISD::Constant && 5079 RHSOp.getOpcode() != ISD::ConstantFP)) 5080 break; 5081 // Can't fold divide by zero. 5082 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5083 N->getOpcode() == ISD::FDIV) { 5084 if ((RHSOp.getOpcode() == ISD::Constant && 5085 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 5086 (RHSOp.getOpcode() == ISD::ConstantFP && 5087 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 5088 break; 5089 } 5090 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5091 AddToWorkList(Ops.back().Val); 5092 assert((Ops.back().getOpcode() == ISD::UNDEF || 5093 Ops.back().getOpcode() == ISD::Constant || 5094 Ops.back().getOpcode() == ISD::ConstantFP) && 5095 "Scalar binop didn't fold!"); 5096 } 5097 5098 if (Ops.size() == LHS.getNumOperands()) { 5099 MVT::ValueType VT = LHS.getValueType(); 5100 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5101 } 5102 } 5103 5104 return SDOperand(); 5105} 5106 5107SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 5108 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5109 5110 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5111 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5112 // If we got a simplified select_cc node back from SimplifySelectCC, then 5113 // break it down into a new SETCC node, and a new SELECT node, and then return 5114 // the SELECT node, since we were called with a SELECT node. 5115 if (SCC.Val) { 5116 // Check to see if we got a select_cc back (to turn into setcc/select). 5117 // Otherwise, just return whatever node we got back, like fabs. 5118 if (SCC.getOpcode() == ISD::SELECT_CC) { 5119 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5120 SCC.getOperand(0), SCC.getOperand(1), 5121 SCC.getOperand(4)); 5122 AddToWorkList(SETCC.Val); 5123 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5124 SCC.getOperand(3), SETCC); 5125 } 5126 return SCC; 5127 } 5128 return SDOperand(); 5129} 5130 5131/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5132/// are the two values being selected between, see if we can simplify the 5133/// select. Callers of this should assume that TheSelect is deleted if this 5134/// returns true. As such, they should return the appropriate thing (e.g. the 5135/// node) back to the top-level of the DAG combiner loop to avoid it being 5136/// looked at. 5137/// 5138bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 5139 SDOperand RHS) { 5140 5141 // If this is a select from two identical things, try to pull the operation 5142 // through the select. 5143 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5144 // If this is a load and the token chain is identical, replace the select 5145 // of two loads with a load through a select of the address to load from. 5146 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5147 // constants have been dropped into the constant pool. 5148 if (LHS.getOpcode() == ISD::LOAD && 5149 // Token chains must be identical. 5150 LHS.getOperand(0) == RHS.getOperand(0)) { 5151 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5152 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5153 5154 // If this is an EXTLOAD, the VT's must match. 5155 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5156 // FIXME: this conflates two src values, discarding one. This is not 5157 // the right thing to do, but nothing uses srcvalues now. When they do, 5158 // turn SrcValue into a list of locations. 5159 SDOperand Addr; 5160 if (TheSelect->getOpcode() == ISD::SELECT) { 5161 // Check that the condition doesn't reach either load. If so, folding 5162 // this will induce a cycle into the DAG. 5163 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5164 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) { 5165 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5166 TheSelect->getOperand(0), LLD->getBasePtr(), 5167 RLD->getBasePtr()); 5168 } 5169 } else { 5170 // Check that the condition doesn't reach either load. If so, folding 5171 // this will induce a cycle into the DAG. 5172 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5173 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5174 !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) && 5175 !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) { 5176 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5177 TheSelect->getOperand(0), 5178 TheSelect->getOperand(1), 5179 LLD->getBasePtr(), RLD->getBasePtr(), 5180 TheSelect->getOperand(4)); 5181 } 5182 } 5183 5184 if (Addr.Val) { 5185 SDOperand Load; 5186 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5187 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5188 Addr,LLD->getSrcValue(), 5189 LLD->getSrcValueOffset(), 5190 LLD->isVolatile(), 5191 LLD->getAlignment()); 5192 else { 5193 Load = DAG.getExtLoad(LLD->getExtensionType(), 5194 TheSelect->getValueType(0), 5195 LLD->getChain(), Addr, LLD->getSrcValue(), 5196 LLD->getSrcValueOffset(), 5197 LLD->getMemoryVT(), 5198 LLD->isVolatile(), 5199 LLD->getAlignment()); 5200 } 5201 // Users of the select now use the result of the load. 5202 CombineTo(TheSelect, Load); 5203 5204 // Users of the old loads now use the new load's chain. We know the 5205 // old-load value is dead now. 5206 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 5207 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 5208 return true; 5209 } 5210 } 5211 } 5212 } 5213 5214 return false; 5215} 5216 5217SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 5218 SDOperand N2, SDOperand N3, 5219 ISD::CondCode CC, bool NotExtCompare) { 5220 5221 MVT::ValueType VT = N2.getValueType(); 5222 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5223 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5224 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5225 5226 // Determine if the condition we're dealing with is constant 5227 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5228 if (SCC.Val) AddToWorkList(SCC.Val); 5229 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5230 5231 // fold select_cc true, x, y -> x 5232 if (SCCC && !SCCC->isNullValue()) 5233 return N2; 5234 // fold select_cc false, x, y -> y 5235 if (SCCC && SCCC->isNullValue()) 5236 return N3; 5237 5238 // Check to see if we can simplify the select into an fabs node 5239 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5240 // Allow either -0.0 or 0.0 5241 if (CFP->getValueAPF().isZero()) { 5242 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5243 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5244 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5245 N2 == N3.getOperand(0)) 5246 return DAG.getNode(ISD::FABS, VT, N0); 5247 5248 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5249 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5250 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5251 N2.getOperand(0) == N3) 5252 return DAG.getNode(ISD::FABS, VT, N3); 5253 } 5254 } 5255 5256 // Check to see if we can perform the "gzip trick", transforming 5257 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5258 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5259 MVT::isInteger(N0.getValueType()) && 5260 MVT::isInteger(N2.getValueType()) && 5261 (N1C->isNullValue() || // (a < 0) ? b : 0 5262 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5263 MVT::ValueType XType = N0.getValueType(); 5264 MVT::ValueType AType = N2.getValueType(); 5265 if (XType >= AType) { 5266 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5267 // single-bit constant. 5268 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5269 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5270 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 5271 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5272 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5273 AddToWorkList(Shift.Val); 5274 if (XType > AType) { 5275 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5276 AddToWorkList(Shift.Val); 5277 } 5278 return DAG.getNode(ISD::AND, AType, Shift, N2); 5279 } 5280 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5281 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5282 TLI.getShiftAmountTy())); 5283 AddToWorkList(Shift.Val); 5284 if (XType > AType) { 5285 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5286 AddToWorkList(Shift.Val); 5287 } 5288 return DAG.getNode(ISD::AND, AType, Shift, N2); 5289 } 5290 } 5291 5292 // fold select C, 16, 0 -> shl C, 4 5293 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5294 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5295 5296 // If the caller doesn't want us to simplify this into a zext of a compare, 5297 // don't do it. 5298 if (NotExtCompare && N2C->getAPIntValue() == 1) 5299 return SDOperand(); 5300 5301 // Get a SetCC of the condition 5302 // FIXME: Should probably make sure that setcc is legal if we ever have a 5303 // target where it isn't. 5304 SDOperand Temp, SCC; 5305 // cast from setcc result type to select result type 5306 if (AfterLegalize) { 5307 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5308 if (N2.getValueType() < SCC.getValueType()) 5309 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5310 else 5311 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5312 } else { 5313 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5314 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5315 } 5316 AddToWorkList(SCC.Val); 5317 AddToWorkList(Temp.Val); 5318 5319 if (N2C->getAPIntValue() == 1) 5320 return Temp; 5321 // shl setcc result by log2 n2c 5322 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5323 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5324 TLI.getShiftAmountTy())); 5325 } 5326 5327 // Check to see if this is the equivalent of setcc 5328 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5329 // otherwise, go ahead with the folds. 5330 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5331 MVT::ValueType XType = N0.getValueType(); 5332 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5333 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5334 if (Res.getValueType() != VT) 5335 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5336 return Res; 5337 } 5338 5339 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5340 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5341 TLI.isOperationLegal(ISD::CTLZ, XType)) { 5342 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5343 return DAG.getNode(ISD::SRL, XType, Ctlz, 5344 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 5345 TLI.getShiftAmountTy())); 5346 } 5347 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5348 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5349 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5350 N0); 5351 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5352 DAG.getConstant(~0ULL, XType)); 5353 return DAG.getNode(ISD::SRL, XType, 5354 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5355 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5356 TLI.getShiftAmountTy())); 5357 } 5358 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5359 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5360 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5361 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5362 TLI.getShiftAmountTy())); 5363 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5364 } 5365 } 5366 5367 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5368 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5369 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5370 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5371 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 5372 MVT::ValueType XType = N0.getValueType(); 5373 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5374 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5375 TLI.getShiftAmountTy())); 5376 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5377 AddToWorkList(Shift.Val); 5378 AddToWorkList(Add.Val); 5379 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5380 } 5381 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5382 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5383 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5384 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5385 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5386 MVT::ValueType XType = N0.getValueType(); 5387 if (SubC->isNullValue() && MVT::isInteger(XType)) { 5388 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5389 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5390 TLI.getShiftAmountTy())); 5391 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5392 AddToWorkList(Shift.Val); 5393 AddToWorkList(Add.Val); 5394 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5395 } 5396 } 5397 } 5398 5399 return SDOperand(); 5400} 5401 5402/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5403SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 5404 SDOperand N1, ISD::CondCode Cond, 5405 bool foldBooleans) { 5406 TargetLowering::DAGCombinerInfo 5407 DagCombineInfo(DAG, !AfterLegalize, false, this); 5408 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5409} 5410 5411/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5412/// return a DAG expression to select that will generate the same value by 5413/// multiplying by a magic number. See: 5414/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5415SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5416 std::vector<SDNode*> Built; 5417 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5418 5419 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5420 ii != ee; ++ii) 5421 AddToWorkList(*ii); 5422 return S; 5423} 5424 5425/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5426/// return a DAG expression to select that will generate the same value by 5427/// multiplying by a magic number. See: 5428/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5429SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5430 std::vector<SDNode*> Built; 5431 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5432 5433 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5434 ii != ee; ++ii) 5435 AddToWorkList(*ii); 5436 return S; 5437} 5438 5439/// FindBaseOffset - Return true if base is known not to alias with anything 5440/// but itself. Provides base object and offset as results. 5441static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5442 // Assume it is a primitive operation. 5443 Base = Ptr; Offset = 0; 5444 5445 // If it's an adding a simple constant then integrate the offset. 5446 if (Base.getOpcode() == ISD::ADD) { 5447 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5448 Base = Base.getOperand(0); 5449 Offset += C->getValue(); 5450 } 5451 } 5452 5453 // If it's any of the following then it can't alias with anything but itself. 5454 return isa<FrameIndexSDNode>(Base) || 5455 isa<ConstantPoolSDNode>(Base) || 5456 isa<GlobalAddressSDNode>(Base); 5457} 5458 5459/// isAlias - Return true if there is any possibility that the two addresses 5460/// overlap. 5461bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5462 const Value *SrcValue1, int SrcValueOffset1, 5463 SDOperand Ptr2, int64_t Size2, 5464 const Value *SrcValue2, int SrcValueOffset2) 5465{ 5466 // If they are the same then they must be aliases. 5467 if (Ptr1 == Ptr2) return true; 5468 5469 // Gather base node and offset information. 5470 SDOperand Base1, Base2; 5471 int64_t Offset1, Offset2; 5472 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5473 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5474 5475 // If they have a same base address then... 5476 if (Base1 == Base2) { 5477 // Check to see if the addresses overlap. 5478 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5479 } 5480 5481 // If we know both bases then they can't alias. 5482 if (KnownBase1 && KnownBase2) return false; 5483 5484 if (CombinerGlobalAA) { 5485 // Use alias analysis information. 5486 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5487 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5488 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5489 AliasAnalysis::AliasResult AAResult = 5490 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5491 if (AAResult == AliasAnalysis::NoAlias) 5492 return false; 5493 } 5494 5495 // Otherwise we have to assume they alias. 5496 return true; 5497} 5498 5499/// FindAliasInfo - Extracts the relevant alias information from the memory 5500/// node. Returns true if the operand was a load. 5501bool DAGCombiner::FindAliasInfo(SDNode *N, 5502 SDOperand &Ptr, int64_t &Size, 5503 const Value *&SrcValue, int &SrcValueOffset) { 5504 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5505 Ptr = LD->getBasePtr(); 5506 Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3; 5507 SrcValue = LD->getSrcValue(); 5508 SrcValueOffset = LD->getSrcValueOffset(); 5509 return true; 5510 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5511 Ptr = ST->getBasePtr(); 5512 Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3; 5513 SrcValue = ST->getSrcValue(); 5514 SrcValueOffset = ST->getSrcValueOffset(); 5515 } else { 5516 assert(0 && "FindAliasInfo expected a memory operand"); 5517 } 5518 5519 return false; 5520} 5521 5522/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5523/// looking for aliasing nodes and adding them to the Aliases vector. 5524void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5525 SmallVector<SDOperand, 8> &Aliases) { 5526 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5527 std::set<SDNode *> Visited; // Visited node set. 5528 5529 // Get alias information for node. 5530 SDOperand Ptr; 5531 int64_t Size; 5532 const Value *SrcValue; 5533 int SrcValueOffset; 5534 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5535 5536 // Starting off. 5537 Chains.push_back(OriginalChain); 5538 5539 // Look at each chain and determine if it is an alias. If so, add it to the 5540 // aliases list. If not, then continue up the chain looking for the next 5541 // candidate. 5542 while (!Chains.empty()) { 5543 SDOperand Chain = Chains.back(); 5544 Chains.pop_back(); 5545 5546 // Don't bother if we've been before. 5547 if (Visited.find(Chain.Val) != Visited.end()) continue; 5548 Visited.insert(Chain.Val); 5549 5550 switch (Chain.getOpcode()) { 5551 case ISD::EntryToken: 5552 // Entry token is ideal chain operand, but handled in FindBetterChain. 5553 break; 5554 5555 case ISD::LOAD: 5556 case ISD::STORE: { 5557 // Get alias information for Chain. 5558 SDOperand OpPtr; 5559 int64_t OpSize; 5560 const Value *OpSrcValue; 5561 int OpSrcValueOffset; 5562 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5563 OpSrcValue, OpSrcValueOffset); 5564 5565 // If chain is alias then stop here. 5566 if (!(IsLoad && IsOpLoad) && 5567 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5568 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5569 Aliases.push_back(Chain); 5570 } else { 5571 // Look further up the chain. 5572 Chains.push_back(Chain.getOperand(0)); 5573 // Clean up old chain. 5574 AddToWorkList(Chain.Val); 5575 } 5576 break; 5577 } 5578 5579 case ISD::TokenFactor: 5580 // We have to check each of the operands of the token factor, so we queue 5581 // then up. Adding the operands to the queue (stack) in reverse order 5582 // maintains the original order and increases the likelihood that getNode 5583 // will find a matching token factor (CSE.) 5584 for (unsigned n = Chain.getNumOperands(); n;) 5585 Chains.push_back(Chain.getOperand(--n)); 5586 // Eliminate the token factor if we can. 5587 AddToWorkList(Chain.Val); 5588 break; 5589 5590 default: 5591 // For all other instructions we will just have to take what we can get. 5592 Aliases.push_back(Chain); 5593 break; 5594 } 5595 } 5596} 5597 5598/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5599/// for a better chain (aliasing node.) 5600SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5601 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5602 5603 // Accumulate all the aliases to this node. 5604 GatherAllAliases(N, OldChain, Aliases); 5605 5606 if (Aliases.size() == 0) { 5607 // If no operands then chain to entry token. 5608 return DAG.getEntryNode(); 5609 } else if (Aliases.size() == 1) { 5610 // If a single operand then chain to it. We don't need to revisit it. 5611 return Aliases[0]; 5612 } 5613 5614 // Construct a custom tailored token factor. 5615 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5616 &Aliases[0], Aliases.size()); 5617 5618 // Make sure the old chain gets cleaned up. 5619 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5620 5621 return NewChain; 5622} 5623 5624// SelectionDAG::Combine - This is the entry point for the file. 5625// 5626void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5627 if (!RunningAfterLegalize && ViewDAGCombine1) 5628 viewGraph(); 5629 if (RunningAfterLegalize && ViewDAGCombine2) 5630 viewGraph(); 5631 /// run - This is the main entry point to this class. 5632 /// 5633 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5634} 5635