DAGCombiner.cpp revision 78f006acdfda52f7250929e1c2fea8afbb9a5b07
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 /// combine - call the node-specific routine that knows how to fold each 142 /// particular type of node. If that doesn't do anything, try the 143 /// target-specific DAG combines. 144 SDValue combine(SDNode *N); 145 146 // Visitation implementation - Implement dag node combining for different 147 // node types. The semantics are as follows: 148 // Return Value: 149 // SDValue.getNode() == 0 - No change was made 150 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151 // otherwise - N should be replaced by the returned Operand. 152 // 153 SDValue visitTokenFactor(SDNode *N); 154 SDValue visitMERGE_VALUES(SDNode *N); 155 SDValue visitADD(SDNode *N); 156 SDValue visitSUB(SDNode *N); 157 SDValue visitADDC(SDNode *N); 158 SDValue visitADDE(SDNode *N); 159 SDValue visitMUL(SDNode *N); 160 SDValue visitSDIV(SDNode *N); 161 SDValue visitUDIV(SDNode *N); 162 SDValue visitSREM(SDNode *N); 163 SDValue visitUREM(SDNode *N); 164 SDValue visitMULHU(SDNode *N); 165 SDValue visitMULHS(SDNode *N); 166 SDValue visitSMUL_LOHI(SDNode *N); 167 SDValue visitUMUL_LOHI(SDNode *N); 168 SDValue visitSDIVREM(SDNode *N); 169 SDValue visitUDIVREM(SDNode *N); 170 SDValue visitAND(SDNode *N); 171 SDValue visitOR(SDNode *N); 172 SDValue visitXOR(SDNode *N); 173 SDValue SimplifyVBinOp(SDNode *N); 174 SDValue visitSHL(SDNode *N); 175 SDValue visitSRA(SDNode *N); 176 SDValue visitSRL(SDNode *N); 177 SDValue visitCTLZ(SDNode *N); 178 SDValue visitCTTZ(SDNode *N); 179 SDValue visitCTPOP(SDNode *N); 180 SDValue visitSELECT(SDNode *N); 181 SDValue visitSELECT_CC(SDNode *N); 182 SDValue visitSETCC(SDNode *N); 183 SDValue visitSIGN_EXTEND(SDNode *N); 184 SDValue visitZERO_EXTEND(SDNode *N); 185 SDValue visitANY_EXTEND(SDNode *N); 186 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 187 SDValue visitTRUNCATE(SDNode *N); 188 SDValue visitBIT_CONVERT(SDNode *N); 189 SDValue visitBUILD_PAIR(SDNode *N); 190 SDValue visitFADD(SDNode *N); 191 SDValue visitFSUB(SDNode *N); 192 SDValue visitFMUL(SDNode *N); 193 SDValue visitFDIV(SDNode *N); 194 SDValue visitFREM(SDNode *N); 195 SDValue visitFCOPYSIGN(SDNode *N); 196 SDValue visitSINT_TO_FP(SDNode *N); 197 SDValue visitUINT_TO_FP(SDNode *N); 198 SDValue visitFP_TO_SINT(SDNode *N); 199 SDValue visitFP_TO_UINT(SDNode *N); 200 SDValue visitFP_ROUND(SDNode *N); 201 SDValue visitFP_ROUND_INREG(SDNode *N); 202 SDValue visitFP_EXTEND(SDNode *N); 203 SDValue visitFNEG(SDNode *N); 204 SDValue visitFABS(SDNode *N); 205 SDValue visitBRCOND(SDNode *N); 206 SDValue visitBR_CC(SDNode *N); 207 SDValue visitLOAD(SDNode *N); 208 SDValue visitSTORE(SDNode *N); 209 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 211 SDValue visitBUILD_VECTOR(SDNode *N); 212 SDValue visitCONCAT_VECTORS(SDNode *N); 213 SDValue visitVECTOR_SHUFFLE(SDNode *N); 214 215 SDValue XformToShuffleWithZero(SDNode *N); 216 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 217 218 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 219 220 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 221 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 222 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 223 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 224 SDValue N3, ISD::CondCode CC, 225 bool NotExtCompare = false); 226 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 227 DebugLoc DL, bool foldBooleans = true); 228 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 229 unsigned HiOp); 230 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 231 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 232 SDValue BuildSDIV(SDNode *N); 233 SDValue BuildUDIV(SDNode *N); 234 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 235 SDValue ReduceLoadWidth(SDNode *N); 236 SDValue ReduceLoadOpStoreWidth(SDNode *N); 237 238 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 239 240 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 241 /// looking for aliasing nodes and adding them to the Aliases vector. 242 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 243 SmallVector<SDValue, 8> &Aliases); 244 245 /// isAlias - Return true if there is any possibility that the two addresses 246 /// overlap. 247 bool isAlias(SDValue Ptr1, int64_t Size1, 248 const Value *SrcValue1, int SrcValueOffset1, 249 unsigned SrcValueAlign1, 250 SDValue Ptr2, int64_t Size2, 251 const Value *SrcValue2, int SrcValueOffset2, 252 unsigned SrcValueAlign2) const; 253 254 /// FindAliasInfo - Extracts the relevant alias information from the memory 255 /// node. Returns true if the operand was a load. 256 bool FindAliasInfo(SDNode *N, 257 SDValue &Ptr, int64_t &Size, 258 const Value *&SrcValue, int &SrcValueOffset, 259 unsigned &SrcValueAlignment) const; 260 261 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 262 /// looking for a better chain (aliasing node.) 263 SDValue FindBetterChain(SDNode *N, SDValue Chain); 264 265 public: 266 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 267 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 268 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 269 270 /// Run - runs the dag combiner on all nodes in the work list 271 void Run(CombineLevel AtLevel); 272 273 SelectionDAG &getDAG() const { return DAG; } 274 275 /// getShiftAmountTy - Returns a type large enough to hold any valid 276 /// shift amount - before type legalization these can be huge. 277 EVT getShiftAmountTy() { 278 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 279 } 280 281 /// isTypeLegal - This method returns true if we are running before type 282 /// legalization or if the specified VT is legal. 283 bool isTypeLegal(const EVT &VT) { 284 if (!LegalTypes) return true; 285 return TLI.isTypeLegal(VT); 286 } 287 }; 288} 289 290 291namespace { 292/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 293/// nodes from the worklist. 294class WorkListRemover : public SelectionDAG::DAGUpdateListener { 295 DAGCombiner &DC; 296public: 297 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 298 299 virtual void NodeDeleted(SDNode *N, SDNode *E) { 300 DC.removeFromWorkList(N); 301 } 302 303 virtual void NodeUpdated(SDNode *N) { 304 // Ignore updates. 305 } 306}; 307} 308 309//===----------------------------------------------------------------------===// 310// TargetLowering::DAGCombinerInfo implementation 311//===----------------------------------------------------------------------===// 312 313void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 314 ((DAGCombiner*)DC)->AddToWorkList(N); 315} 316 317SDValue TargetLowering::DAGCombinerInfo:: 318CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 319 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 320} 321 322SDValue TargetLowering::DAGCombinerInfo:: 323CombineTo(SDNode *N, SDValue Res, bool AddTo) { 324 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 325} 326 327 328SDValue TargetLowering::DAGCombinerInfo:: 329CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 330 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 331} 332 333void TargetLowering::DAGCombinerInfo:: 334CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 335 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 336} 337 338//===----------------------------------------------------------------------===// 339// Helper Functions 340//===----------------------------------------------------------------------===// 341 342/// isNegatibleForFree - Return 1 if we can compute the negated form of the 343/// specified expression for the same cost as the expression itself, or 2 if we 344/// can compute the negated form more cheaply than the expression itself. 345static char isNegatibleForFree(SDValue Op, bool LegalOperations, 346 unsigned Depth = 0) { 347 // No compile time optimizations on this type. 348 if (Op.getValueType() == MVT::ppcf128) 349 return 0; 350 351 // fneg is removable even if it has multiple uses. 352 if (Op.getOpcode() == ISD::FNEG) return 2; 353 354 // Don't allow anything with multiple uses. 355 if (!Op.hasOneUse()) return 0; 356 357 // Don't recurse exponentially. 358 if (Depth > 6) return 0; 359 360 switch (Op.getOpcode()) { 361 default: return false; 362 case ISD::ConstantFP: 363 // Don't invert constant FP values after legalize. The negated constant 364 // isn't necessarily legal. 365 return LegalOperations ? 0 : 1; 366 case ISD::FADD: 367 // FIXME: determine better conditions for this xform. 368 if (!UnsafeFPMath) return 0; 369 370 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 371 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 372 return V; 373 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 374 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 375 case ISD::FSUB: 376 // We can't turn -(A-B) into B-A when we honor signed zeros. 377 if (!UnsafeFPMath) return 0; 378 379 // fold (fneg (fsub A, B)) -> (fsub B, A) 380 return 1; 381 382 case ISD::FMUL: 383 case ISD::FDIV: 384 if (HonorSignDependentRoundingFPMath()) return 0; 385 386 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 387 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 388 return V; 389 390 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 391 392 case ISD::FP_EXTEND: 393 case ISD::FP_ROUND: 394 case ISD::FSIN: 395 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 396 } 397} 398 399/// GetNegatedExpression - If isNegatibleForFree returns true, this function 400/// returns the newly negated expression. 401static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 402 bool LegalOperations, unsigned Depth = 0) { 403 // fneg is removable even if it has multiple uses. 404 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 405 406 // Don't allow anything with multiple uses. 407 assert(Op.hasOneUse() && "Unknown reuse!"); 408 409 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 410 switch (Op.getOpcode()) { 411 default: llvm_unreachable("Unknown code"); 412 case ISD::ConstantFP: { 413 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 414 V.changeSign(); 415 return DAG.getConstantFP(V, Op.getValueType()); 416 } 417 case ISD::FADD: 418 // FIXME: determine better conditions for this xform. 419 assert(UnsafeFPMath); 420 421 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 422 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 423 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 424 GetNegatedExpression(Op.getOperand(0), DAG, 425 LegalOperations, Depth+1), 426 Op.getOperand(1)); 427 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 428 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(1), DAG, 430 LegalOperations, Depth+1), 431 Op.getOperand(0)); 432 case ISD::FSUB: 433 // We can't turn -(A-B) into B-A when we honor signed zeros. 434 assert(UnsafeFPMath); 435 436 // fold (fneg (fsub 0, B)) -> B 437 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 438 if (N0CFP->getValueAPF().isZero()) 439 return Op.getOperand(1); 440 441 // fold (fneg (fsub A, B)) -> (fsub B, A) 442 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 443 Op.getOperand(1), Op.getOperand(0)); 444 445 case ISD::FMUL: 446 case ISD::FDIV: 447 assert(!HonorSignDependentRoundingFPMath()); 448 449 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 450 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 451 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 452 GetNegatedExpression(Op.getOperand(0), DAG, 453 LegalOperations, Depth+1), 454 Op.getOperand(1)); 455 456 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 457 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 458 Op.getOperand(0), 459 GetNegatedExpression(Op.getOperand(1), DAG, 460 LegalOperations, Depth+1)); 461 462 case ISD::FP_EXTEND: 463 case ISD::FSIN: 464 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 465 GetNegatedExpression(Op.getOperand(0), DAG, 466 LegalOperations, Depth+1)); 467 case ISD::FP_ROUND: 468 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 469 GetNegatedExpression(Op.getOperand(0), DAG, 470 LegalOperations, Depth+1), 471 Op.getOperand(1)); 472 } 473} 474 475 476// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 477// that selects between the values 1 and 0, making it equivalent to a setcc. 478// Also, set the incoming LHS, RHS, and CC references to the appropriate 479// nodes based on the type of node we are checking. This simplifies life a 480// bit for the callers. 481static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 482 SDValue &CC) { 483 if (N.getOpcode() == ISD::SETCC) { 484 LHS = N.getOperand(0); 485 RHS = N.getOperand(1); 486 CC = N.getOperand(2); 487 return true; 488 } 489 if (N.getOpcode() == ISD::SELECT_CC && 490 N.getOperand(2).getOpcode() == ISD::Constant && 491 N.getOperand(3).getOpcode() == ISD::Constant && 492 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 493 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 494 LHS = N.getOperand(0); 495 RHS = N.getOperand(1); 496 CC = N.getOperand(4); 497 return true; 498 } 499 return false; 500} 501 502// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 503// one use. If this is true, it allows the users to invert the operation for 504// free when it is profitable to do so. 505static bool isOneUseSetCC(SDValue N) { 506 SDValue N0, N1, N2; 507 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 508 return true; 509 return false; 510} 511 512SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 513 SDValue N0, SDValue N1) { 514 EVT VT = N0.getValueType(); 515 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 516 if (isa<ConstantSDNode>(N1)) { 517 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 518 SDValue OpNode = 519 DAG.FoldConstantArithmetic(Opc, VT, 520 cast<ConstantSDNode>(N0.getOperand(1)), 521 cast<ConstantSDNode>(N1)); 522 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 523 } else if (N0.hasOneUse()) { 524 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 525 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 526 N0.getOperand(0), N1); 527 AddToWorkList(OpNode.getNode()); 528 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 529 } 530 } 531 532 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 533 if (isa<ConstantSDNode>(N0)) { 534 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 535 SDValue OpNode = 536 DAG.FoldConstantArithmetic(Opc, VT, 537 cast<ConstantSDNode>(N1.getOperand(1)), 538 cast<ConstantSDNode>(N0)); 539 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 540 } else if (N1.hasOneUse()) { 541 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 542 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 543 N1.getOperand(0), N0); 544 AddToWorkList(OpNode.getNode()); 545 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 546 } 547 } 548 549 return SDValue(); 550} 551 552SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 553 bool AddTo) { 554 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 555 ++NodesCombined; 556 DEBUG(dbgs() << "\nReplacing.1 "; 557 N->dump(&DAG); 558 dbgs() << "\nWith: "; 559 To[0].getNode()->dump(&DAG); 560 dbgs() << " and " << NumTo-1 << " other values\n"; 561 for (unsigned i = 0, e = NumTo; i != e; ++i) 562 assert((!To[i].getNode() || 563 N->getValueType(i) == To[i].getValueType()) && 564 "Cannot combine value to value of different type!")); 565 WorkListRemover DeadNodes(*this); 566 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 567 568 if (AddTo) { 569 // Push the new nodes and any users onto the worklist 570 for (unsigned i = 0, e = NumTo; i != e; ++i) { 571 if (To[i].getNode()) { 572 AddToWorkList(To[i].getNode()); 573 AddUsersToWorkList(To[i].getNode()); 574 } 575 } 576 } 577 578 // Finally, if the node is now dead, remove it from the graph. The node 579 // may not be dead if the replacement process recursively simplified to 580 // something else needing this node. 581 if (N->use_empty()) { 582 // Nodes can be reintroduced into the worklist. Make sure we do not 583 // process a node that has been replaced. 584 removeFromWorkList(N); 585 586 // Finally, since the node is now dead, remove it from the graph. 587 DAG.DeleteNode(N); 588 } 589 return SDValue(N, 0); 590} 591 592void DAGCombiner:: 593CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 594 // Replace all uses. If any nodes become isomorphic to other nodes and 595 // are deleted, make sure to remove them from our worklist. 596 WorkListRemover DeadNodes(*this); 597 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 598 599 // Push the new node and any (possibly new) users onto the worklist. 600 AddToWorkList(TLO.New.getNode()); 601 AddUsersToWorkList(TLO.New.getNode()); 602 603 // Finally, if the node is now dead, remove it from the graph. The node 604 // may not be dead if the replacement process recursively simplified to 605 // something else needing this node. 606 if (TLO.Old.getNode()->use_empty()) { 607 removeFromWorkList(TLO.Old.getNode()); 608 609 // If the operands of this node are only used by the node, they will now 610 // be dead. Make sure to visit them first to delete dead nodes early. 611 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 612 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 613 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 614 615 DAG.DeleteNode(TLO.Old.getNode()); 616 } 617} 618 619/// SimplifyDemandedBits - Check the specified integer node value to see if 620/// it can be simplified or if things it uses can be simplified by bit 621/// propagation. If so, return true. 622bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 623 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 624 APInt KnownZero, KnownOne; 625 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 626 return false; 627 628 // Revisit the node. 629 AddToWorkList(Op.getNode()); 630 631 // Replace the old value with the new one. 632 ++NodesCombined; 633 DEBUG(dbgs() << "\nReplacing.2 "; 634 TLO.Old.getNode()->dump(&DAG); 635 dbgs() << "\nWith: "; 636 TLO.New.getNode()->dump(&DAG); 637 dbgs() << '\n'); 638 639 CommitTargetLoweringOpt(TLO); 640 return true; 641} 642 643void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 644 DebugLoc dl = Load->getDebugLoc(); 645 EVT VT = Load->getValueType(0); 646 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 647 648 DEBUG(dbgs() << "\nReplacing.9 "; 649 Load->dump(&DAG); 650 dbgs() << "\nWith: "; 651 Trunc.getNode()->dump(&DAG); 652 dbgs() << '\n'); 653 WorkListRemover DeadNodes(*this); 654 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 655 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 656 &DeadNodes); 657 removeFromWorkList(Load); 658 DAG.DeleteNode(Load); 659 AddToWorkList(Trunc.getNode()); 660} 661 662SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 663 Replace = false; 664 DebugLoc dl = Op.getDebugLoc(); 665 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 666 EVT MemVT = LD->getMemoryVT(); 667 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 668 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD) 669 : LD->getExtensionType(); 670 Replace = true; 671 return DAG.getExtLoad(ExtType, dl, PVT, 672 LD->getChain(), LD->getBasePtr(), 673 LD->getSrcValue(), LD->getSrcValueOffset(), 674 MemVT, LD->isVolatile(), 675 LD->isNonTemporal(), LD->getAlignment()); 676 } 677 678 unsigned Opc = Op.getOpcode(); 679 switch (Opc) { 680 default: break; 681 case ISD::AssertSext: 682 return DAG.getNode(ISD::AssertSext, dl, PVT, 683 SExtPromoteOperand(Op.getOperand(0), PVT), 684 Op.getOperand(1)); 685 case ISD::AssertZext: 686 return DAG.getNode(ISD::AssertZext, dl, PVT, 687 ZExtPromoteOperand(Op.getOperand(0), PVT), 688 Op.getOperand(1)); 689 case ISD::Constant: { 690 unsigned ExtOpc = 691 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 692 return DAG.getNode(ExtOpc, dl, PVT, Op); 693 } 694 } 695 696 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 697 return SDValue(); 698 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 699} 700 701SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 702 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 703 return SDValue(); 704 EVT OldVT = Op.getValueType(); 705 DebugLoc dl = Op.getDebugLoc(); 706 bool Replace = false; 707 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 708 if (NewOp.getNode() == 0) 709 return SDValue(); 710 AddToWorkList(NewOp.getNode()); 711 712 if (Replace) 713 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 714 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 715 DAG.getValueType(OldVT)); 716} 717 718SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 719 EVT OldVT = Op.getValueType(); 720 DebugLoc dl = Op.getDebugLoc(); 721 bool Replace = false; 722 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 723 if (NewOp.getNode() == 0) 724 return SDValue(); 725 AddToWorkList(NewOp.getNode()); 726 727 if (Replace) 728 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 729 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 730} 731 732/// PromoteIntBinOp - Promote the specified integer binary operation if the 733/// target indicates it is beneficial. e.g. On x86, it's usually better to 734/// promote i16 operations to i32 since i16 instructions are longer. 735SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 736 if (!LegalOperations) 737 return SDValue(); 738 739 EVT VT = Op.getValueType(); 740 if (VT.isVector() || !VT.isInteger()) 741 return SDValue(); 742 743 // If operation type is 'undesirable', e.g. i16 on x86, consider 744 // promoting it. 745 unsigned Opc = Op.getOpcode(); 746 if (TLI.isTypeDesirableForOp(Opc, VT)) 747 return SDValue(); 748 749 EVT PVT = VT; 750 // Consult target whether it is a good idea to promote this operation and 751 // what's the right type to promote it to. 752 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 753 assert(PVT != VT && "Don't know what type to promote to!"); 754 755 bool Replace0 = false; 756 SDValue N0 = Op.getOperand(0); 757 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 758 if (NN0.getNode() == 0) 759 return SDValue(); 760 761 bool Replace1 = false; 762 SDValue N1 = Op.getOperand(1); 763 SDValue NN1; 764 if (N0 == N1) 765 NN1 = NN0; 766 else { 767 NN1 = PromoteOperand(N1, PVT, Replace1); 768 if (NN1.getNode() == 0) 769 return SDValue(); 770 } 771 772 AddToWorkList(NN0.getNode()); 773 if (NN1.getNode()) 774 AddToWorkList(NN1.getNode()); 775 776 if (Replace0) 777 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 778 if (Replace1) 779 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 780 781 DEBUG(dbgs() << "\nPromoting "; 782 Op.getNode()->dump(&DAG)); 783 DebugLoc dl = Op.getDebugLoc(); 784 return DAG.getNode(ISD::TRUNCATE, dl, VT, 785 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 786 } 787 return SDValue(); 788} 789 790/// PromoteIntShiftOp - Promote the specified integer shift operation if the 791/// target indicates it is beneficial. e.g. On x86, it's usually better to 792/// promote i16 operations to i32 since i16 instructions are longer. 793SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 794 if (!LegalOperations) 795 return SDValue(); 796 797 EVT VT = Op.getValueType(); 798 if (VT.isVector() || !VT.isInteger()) 799 return SDValue(); 800 801 // If operation type is 'undesirable', e.g. i16 on x86, consider 802 // promoting it. 803 unsigned Opc = Op.getOpcode(); 804 if (TLI.isTypeDesirableForOp(Opc, VT)) 805 return SDValue(); 806 807 EVT PVT = VT; 808 // Consult target whether it is a good idea to promote this operation and 809 // what's the right type to promote it to. 810 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 811 assert(PVT != VT && "Don't know what type to promote to!"); 812 813 bool Replace = false; 814 SDValue N0 = Op.getOperand(0); 815 if (Opc == ISD::SRA) 816 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 817 else if (Opc == ISD::SRL) 818 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 819 else 820 N0 = PromoteOperand(N0, PVT, Replace); 821 if (N0.getNode() == 0) 822 return SDValue(); 823 824 AddToWorkList(N0.getNode()); 825 if (Replace) 826 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 827 828 DEBUG(dbgs() << "\nPromoting "; 829 Op.getNode()->dump(&DAG)); 830 DebugLoc dl = Op.getDebugLoc(); 831 return DAG.getNode(ISD::TRUNCATE, dl, VT, 832 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 833 } 834 return SDValue(); 835} 836 837SDValue DAGCombiner::PromoteExtend(SDValue Op) { 838 if (!LegalOperations) 839 return SDValue(); 840 841 EVT VT = Op.getValueType(); 842 if (VT.isVector() || !VT.isInteger()) 843 return SDValue(); 844 845 // If operation type is 'undesirable', e.g. i16 on x86, consider 846 // promoting it. 847 unsigned Opc = Op.getOpcode(); 848 if (TLI.isTypeDesirableForOp(Opc, VT)) 849 return SDValue(); 850 851 EVT PVT = VT; 852 // Consult target whether it is a good idea to promote this operation and 853 // what's the right type to promote it to. 854 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 855 assert(PVT != VT && "Don't know what type to promote to!"); 856 // fold (aext (aext x)) -> (aext x) 857 // fold (aext (zext x)) -> (zext x) 858 // fold (aext (sext x)) -> (sext x) 859 DEBUG(dbgs() << "\nPromoting "; 860 Op.getNode()->dump(&DAG)); 861 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 862 } 863 return SDValue(); 864} 865 866bool DAGCombiner::PromoteLoad(SDValue Op) { 867 if (!LegalOperations) 868 return false; 869 870 EVT VT = Op.getValueType(); 871 if (VT.isVector() || !VT.isInteger()) 872 return false; 873 874 // If operation type is 'undesirable', e.g. i16 on x86, consider 875 // promoting it. 876 unsigned Opc = Op.getOpcode(); 877 if (TLI.isTypeDesirableForOp(Opc, VT)) 878 return false; 879 880 EVT PVT = VT; 881 // Consult target whether it is a good idea to promote this operation and 882 // what's the right type to promote it to. 883 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 884 assert(PVT != VT && "Don't know what type to promote to!"); 885 886 DebugLoc dl = Op.getDebugLoc(); 887 SDNode *N = Op.getNode(); 888 LoadSDNode *LD = cast<LoadSDNode>(N); 889 EVT MemVT = LD->getMemoryVT(); 890 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 891 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD) 892 : LD->getExtensionType(); 893 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 894 LD->getChain(), LD->getBasePtr(), 895 LD->getSrcValue(), LD->getSrcValueOffset(), 896 MemVT, LD->isVolatile(), 897 LD->isNonTemporal(), LD->getAlignment()); 898 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 899 900 DEBUG(dbgs() << "\nPromoting "; 901 N->dump(&DAG); 902 dbgs() << "\nTo: "; 903 Result.getNode()->dump(&DAG); 904 dbgs() << '\n'); 905 WorkListRemover DeadNodes(*this); 906 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 907 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 908 removeFromWorkList(N); 909 DAG.DeleteNode(N); 910 AddToWorkList(Result.getNode()); 911 return true; 912 } 913 return false; 914} 915 916 917//===----------------------------------------------------------------------===// 918// Main DAG Combiner implementation 919//===----------------------------------------------------------------------===// 920 921void DAGCombiner::Run(CombineLevel AtLevel) { 922 // set the instance variables, so that the various visit routines may use it. 923 Level = AtLevel; 924 LegalOperations = Level >= NoIllegalOperations; 925 LegalTypes = Level >= NoIllegalTypes; 926 927 // Add all the dag nodes to the worklist. 928 WorkList.reserve(DAG.allnodes_size()); 929 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 930 E = DAG.allnodes_end(); I != E; ++I) 931 WorkList.push_back(I); 932 933 // Create a dummy node (which is not added to allnodes), that adds a reference 934 // to the root node, preventing it from being deleted, and tracking any 935 // changes of the root. 936 HandleSDNode Dummy(DAG.getRoot()); 937 938 // The root of the dag may dangle to deleted nodes until the dag combiner is 939 // done. Set it to null to avoid confusion. 940 DAG.setRoot(SDValue()); 941 942 // while the worklist isn't empty, inspect the node on the end of it and 943 // try and combine it. 944 while (!WorkList.empty()) { 945 SDNode *N = WorkList.back(); 946 WorkList.pop_back(); 947 948 // If N has no uses, it is dead. Make sure to revisit all N's operands once 949 // N is deleted from the DAG, since they too may now be dead or may have a 950 // reduced number of uses, allowing other xforms. 951 if (N->use_empty() && N != &Dummy) { 952 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 953 AddToWorkList(N->getOperand(i).getNode()); 954 955 DAG.DeleteNode(N); 956 continue; 957 } 958 959 SDValue RV = combine(N); 960 961 if (RV.getNode() == 0) 962 continue; 963 964 ++NodesCombined; 965 966 // If we get back the same node we passed in, rather than a new node or 967 // zero, we know that the node must have defined multiple values and 968 // CombineTo was used. Since CombineTo takes care of the worklist 969 // mechanics for us, we have no work to do in this case. 970 if (RV.getNode() == N) 971 continue; 972 973 assert(N->getOpcode() != ISD::DELETED_NODE && 974 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 975 "Node was deleted but visit returned new node!"); 976 977 DEBUG(dbgs() << "\nReplacing.3 "; 978 N->dump(&DAG); 979 dbgs() << "\nWith: "; 980 RV.getNode()->dump(&DAG); 981 dbgs() << '\n'); 982 WorkListRemover DeadNodes(*this); 983 if (N->getNumValues() == RV.getNode()->getNumValues()) 984 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 985 else { 986 assert(N->getValueType(0) == RV.getValueType() && 987 N->getNumValues() == 1 && "Type mismatch"); 988 SDValue OpV = RV; 989 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 990 } 991 992 // Push the new node and any users onto the worklist 993 AddToWorkList(RV.getNode()); 994 AddUsersToWorkList(RV.getNode()); 995 996 // Add any uses of the old node to the worklist in case this node is the 997 // last one that uses them. They may become dead after this node is 998 // deleted. 999 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1000 AddToWorkList(N->getOperand(i).getNode()); 1001 1002 // Finally, if the node is now dead, remove it from the graph. The node 1003 // may not be dead if the replacement process recursively simplified to 1004 // something else needing this node. 1005 if (N->use_empty()) { 1006 // Nodes can be reintroduced into the worklist. Make sure we do not 1007 // process a node that has been replaced. 1008 removeFromWorkList(N); 1009 1010 // Finally, since the node is now dead, remove it from the graph. 1011 DAG.DeleteNode(N); 1012 } 1013 } 1014 1015 // If the root changed (e.g. it was a dead load, update the root). 1016 DAG.setRoot(Dummy.getValue()); 1017} 1018 1019SDValue DAGCombiner::visit(SDNode *N) { 1020 switch (N->getOpcode()) { 1021 default: break; 1022 case ISD::TokenFactor: return visitTokenFactor(N); 1023 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1024 case ISD::ADD: return visitADD(N); 1025 case ISD::SUB: return visitSUB(N); 1026 case ISD::ADDC: return visitADDC(N); 1027 case ISD::ADDE: return visitADDE(N); 1028 case ISD::MUL: return visitMUL(N); 1029 case ISD::SDIV: return visitSDIV(N); 1030 case ISD::UDIV: return visitUDIV(N); 1031 case ISD::SREM: return visitSREM(N); 1032 case ISD::UREM: return visitUREM(N); 1033 case ISD::MULHU: return visitMULHU(N); 1034 case ISD::MULHS: return visitMULHS(N); 1035 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1036 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1037 case ISD::SDIVREM: return visitSDIVREM(N); 1038 case ISD::UDIVREM: return visitUDIVREM(N); 1039 case ISD::AND: return visitAND(N); 1040 case ISD::OR: return visitOR(N); 1041 case ISD::XOR: return visitXOR(N); 1042 case ISD::SHL: return visitSHL(N); 1043 case ISD::SRA: return visitSRA(N); 1044 case ISD::SRL: return visitSRL(N); 1045 case ISD::CTLZ: return visitCTLZ(N); 1046 case ISD::CTTZ: return visitCTTZ(N); 1047 case ISD::CTPOP: return visitCTPOP(N); 1048 case ISD::SELECT: return visitSELECT(N); 1049 case ISD::SELECT_CC: return visitSELECT_CC(N); 1050 case ISD::SETCC: return visitSETCC(N); 1051 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1052 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1053 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1054 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1055 case ISD::TRUNCATE: return visitTRUNCATE(N); 1056 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 1057 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1058 case ISD::FADD: return visitFADD(N); 1059 case ISD::FSUB: return visitFSUB(N); 1060 case ISD::FMUL: return visitFMUL(N); 1061 case ISD::FDIV: return visitFDIV(N); 1062 case ISD::FREM: return visitFREM(N); 1063 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1064 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1065 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1066 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1067 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1068 case ISD::FP_ROUND: return visitFP_ROUND(N); 1069 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1070 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1071 case ISD::FNEG: return visitFNEG(N); 1072 case ISD::FABS: return visitFABS(N); 1073 case ISD::BRCOND: return visitBRCOND(N); 1074 case ISD::BR_CC: return visitBR_CC(N); 1075 case ISD::LOAD: return visitLOAD(N); 1076 case ISD::STORE: return visitSTORE(N); 1077 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1078 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1079 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1080 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1081 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1082 } 1083 return SDValue(); 1084} 1085 1086SDValue DAGCombiner::combine(SDNode *N) { 1087 SDValue RV = visit(N); 1088 1089 // If nothing happened, try a target-specific DAG combine. 1090 if (RV.getNode() == 0) { 1091 assert(N->getOpcode() != ISD::DELETED_NODE && 1092 "Node was deleted but visit returned NULL!"); 1093 1094 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1095 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1096 1097 // Expose the DAG combiner to the target combiner impls. 1098 TargetLowering::DAGCombinerInfo 1099 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1100 1101 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1102 } 1103 } 1104 1105 // If nothing happened still, try promoting the operation. 1106 if (RV.getNode() == 0) { 1107 switch (N->getOpcode()) { 1108 default: break; 1109 case ISD::ADD: 1110 case ISD::SUB: 1111 case ISD::MUL: 1112 case ISD::AND: 1113 case ISD::OR: 1114 case ISD::XOR: 1115 RV = PromoteIntBinOp(SDValue(N, 0)); 1116 break; 1117 case ISD::SHL: 1118 case ISD::SRA: 1119 case ISD::SRL: 1120 RV = PromoteIntShiftOp(SDValue(N, 0)); 1121 break; 1122 case ISD::SIGN_EXTEND: 1123 case ISD::ZERO_EXTEND: 1124 case ISD::ANY_EXTEND: 1125 RV = PromoteExtend(SDValue(N, 0)); 1126 break; 1127 case ISD::LOAD: 1128 if (PromoteLoad(SDValue(N, 0))) 1129 RV = SDValue(N, 0); 1130 break; 1131 } 1132 } 1133 1134 // If N is a commutative binary node, try commuting it to enable more 1135 // sdisel CSE. 1136 if (RV.getNode() == 0 && 1137 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1138 N->getNumValues() == 1) { 1139 SDValue N0 = N->getOperand(0); 1140 SDValue N1 = N->getOperand(1); 1141 1142 // Constant operands are canonicalized to RHS. 1143 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1144 SDValue Ops[] = { N1, N0 }; 1145 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1146 Ops, 2); 1147 if (CSENode) 1148 return SDValue(CSENode, 0); 1149 } 1150 } 1151 1152 return RV; 1153} 1154 1155/// getInputChainForNode - Given a node, return its input chain if it has one, 1156/// otherwise return a null sd operand. 1157static SDValue getInputChainForNode(SDNode *N) { 1158 if (unsigned NumOps = N->getNumOperands()) { 1159 if (N->getOperand(0).getValueType() == MVT::Other) 1160 return N->getOperand(0); 1161 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1162 return N->getOperand(NumOps-1); 1163 for (unsigned i = 1; i < NumOps-1; ++i) 1164 if (N->getOperand(i).getValueType() == MVT::Other) 1165 return N->getOperand(i); 1166 } 1167 return SDValue(); 1168} 1169 1170SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1171 // If N has two operands, where one has an input chain equal to the other, 1172 // the 'other' chain is redundant. 1173 if (N->getNumOperands() == 2) { 1174 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1175 return N->getOperand(0); 1176 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1177 return N->getOperand(1); 1178 } 1179 1180 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1181 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1182 SmallPtrSet<SDNode*, 16> SeenOps; 1183 bool Changed = false; // If we should replace this token factor. 1184 1185 // Start out with this token factor. 1186 TFs.push_back(N); 1187 1188 // Iterate through token factors. The TFs grows when new token factors are 1189 // encountered. 1190 for (unsigned i = 0; i < TFs.size(); ++i) { 1191 SDNode *TF = TFs[i]; 1192 1193 // Check each of the operands. 1194 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1195 SDValue Op = TF->getOperand(i); 1196 1197 switch (Op.getOpcode()) { 1198 case ISD::EntryToken: 1199 // Entry tokens don't need to be added to the list. They are 1200 // rededundant. 1201 Changed = true; 1202 break; 1203 1204 case ISD::TokenFactor: 1205 if (Op.hasOneUse() && 1206 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1207 // Queue up for processing. 1208 TFs.push_back(Op.getNode()); 1209 // Clean up in case the token factor is removed. 1210 AddToWorkList(Op.getNode()); 1211 Changed = true; 1212 break; 1213 } 1214 // Fall thru 1215 1216 default: 1217 // Only add if it isn't already in the list. 1218 if (SeenOps.insert(Op.getNode())) 1219 Ops.push_back(Op); 1220 else 1221 Changed = true; 1222 break; 1223 } 1224 } 1225 } 1226 1227 SDValue Result; 1228 1229 // If we've change things around then replace token factor. 1230 if (Changed) { 1231 if (Ops.empty()) { 1232 // The entry token is the only possible outcome. 1233 Result = DAG.getEntryNode(); 1234 } else { 1235 // New and improved token factor. 1236 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1237 MVT::Other, &Ops[0], Ops.size()); 1238 } 1239 1240 // Don't add users to work list. 1241 return CombineTo(N, Result, false); 1242 } 1243 1244 return Result; 1245} 1246 1247/// MERGE_VALUES can always be eliminated. 1248SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1249 WorkListRemover DeadNodes(*this); 1250 // Replacing results may cause a different MERGE_VALUES to suddenly 1251 // be CSE'd with N, and carry its uses with it. Iterate until no 1252 // uses remain, to ensure that the node can be safely deleted. 1253 do { 1254 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1255 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1256 &DeadNodes); 1257 } while (!N->use_empty()); 1258 removeFromWorkList(N); 1259 DAG.DeleteNode(N); 1260 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1261} 1262 1263static 1264SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1265 SelectionDAG &DAG) { 1266 EVT VT = N0.getValueType(); 1267 SDValue N00 = N0.getOperand(0); 1268 SDValue N01 = N0.getOperand(1); 1269 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1270 1271 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1272 isa<ConstantSDNode>(N00.getOperand(1))) { 1273 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1274 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1275 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1276 N00.getOperand(0), N01), 1277 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1278 N00.getOperand(1), N01)); 1279 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1280 } 1281 1282 return SDValue(); 1283} 1284 1285SDValue DAGCombiner::visitADD(SDNode *N) { 1286 SDValue N0 = N->getOperand(0); 1287 SDValue N1 = N->getOperand(1); 1288 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1289 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1290 EVT VT = N0.getValueType(); 1291 1292 // fold vector ops 1293 if (VT.isVector()) { 1294 SDValue FoldedVOp = SimplifyVBinOp(N); 1295 if (FoldedVOp.getNode()) return FoldedVOp; 1296 } 1297 1298 // fold (add x, undef) -> undef 1299 if (N0.getOpcode() == ISD::UNDEF) 1300 return N0; 1301 if (N1.getOpcode() == ISD::UNDEF) 1302 return N1; 1303 // fold (add c1, c2) -> c1+c2 1304 if (N0C && N1C) 1305 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1306 // canonicalize constant to RHS 1307 if (N0C && !N1C) 1308 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1309 // fold (add x, 0) -> x 1310 if (N1C && N1C->isNullValue()) 1311 return N0; 1312 // fold (add Sym, c) -> Sym+c 1313 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1314 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1315 GA->getOpcode() == ISD::GlobalAddress) 1316 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1317 GA->getOffset() + 1318 (uint64_t)N1C->getSExtValue()); 1319 // fold ((c1-A)+c2) -> (c1+c2)-A 1320 if (N1C && N0.getOpcode() == ISD::SUB) 1321 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1322 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1323 DAG.getConstant(N1C->getAPIntValue()+ 1324 N0C->getAPIntValue(), VT), 1325 N0.getOperand(1)); 1326 // reassociate add 1327 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1328 if (RADD.getNode() != 0) 1329 return RADD; 1330 // fold ((0-A) + B) -> B-A 1331 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1332 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1333 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1334 // fold (A + (0-B)) -> A-B 1335 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1336 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1337 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1338 // fold (A+(B-A)) -> B 1339 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1340 return N1.getOperand(0); 1341 // fold ((B-A)+A) -> B 1342 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1343 return N0.getOperand(0); 1344 // fold (A+(B-(A+C))) to (B-C) 1345 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1346 N0 == N1.getOperand(1).getOperand(0)) 1347 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1348 N1.getOperand(1).getOperand(1)); 1349 // fold (A+(B-(C+A))) to (B-C) 1350 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1351 N0 == N1.getOperand(1).getOperand(1)) 1352 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1353 N1.getOperand(1).getOperand(0)); 1354 // fold (A+((B-A)+or-C)) to (B+or-C) 1355 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1356 N1.getOperand(0).getOpcode() == ISD::SUB && 1357 N0 == N1.getOperand(0).getOperand(1)) 1358 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1359 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1360 1361 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1362 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1363 SDValue N00 = N0.getOperand(0); 1364 SDValue N01 = N0.getOperand(1); 1365 SDValue N10 = N1.getOperand(0); 1366 SDValue N11 = N1.getOperand(1); 1367 1368 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1369 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1370 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1371 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1372 } 1373 1374 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1375 return SDValue(N, 0); 1376 1377 // fold (a+b) -> (a|b) iff a and b share no bits. 1378 if (VT.isInteger() && !VT.isVector()) { 1379 APInt LHSZero, LHSOne; 1380 APInt RHSZero, RHSOne; 1381 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1382 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1383 1384 if (LHSZero.getBoolValue()) { 1385 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1386 1387 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1388 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1389 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1390 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1391 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1392 } 1393 } 1394 1395 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1396 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1397 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1398 if (Result.getNode()) return Result; 1399 } 1400 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1401 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1402 if (Result.getNode()) return Result; 1403 } 1404 1405 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1406 if (N1.getOpcode() == ISD::SHL && 1407 N1.getOperand(0).getOpcode() == ISD::SUB) 1408 if (ConstantSDNode *C = 1409 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1410 if (C->getAPIntValue() == 0) 1411 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1412 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1413 N1.getOperand(0).getOperand(1), 1414 N1.getOperand(1))); 1415 if (N0.getOpcode() == ISD::SHL && 1416 N0.getOperand(0).getOpcode() == ISD::SUB) 1417 if (ConstantSDNode *C = 1418 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1419 if (C->getAPIntValue() == 0) 1420 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1421 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1422 N0.getOperand(0).getOperand(1), 1423 N0.getOperand(1))); 1424 1425 return SDValue(); 1426} 1427 1428SDValue DAGCombiner::visitADDC(SDNode *N) { 1429 SDValue N0 = N->getOperand(0); 1430 SDValue N1 = N->getOperand(1); 1431 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1432 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1433 EVT VT = N0.getValueType(); 1434 1435 // If the flag result is dead, turn this into an ADD. 1436 if (N->hasNUsesOfValue(0, 1)) 1437 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1438 DAG.getNode(ISD::CARRY_FALSE, 1439 N->getDebugLoc(), MVT::Flag)); 1440 1441 // canonicalize constant to RHS. 1442 if (N0C && !N1C) 1443 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1444 1445 // fold (addc x, 0) -> x + no carry out 1446 if (N1C && N1C->isNullValue()) 1447 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1448 N->getDebugLoc(), MVT::Flag)); 1449 1450 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1451 APInt LHSZero, LHSOne; 1452 APInt RHSZero, RHSOne; 1453 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1454 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1455 1456 if (LHSZero.getBoolValue()) { 1457 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1458 1459 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1460 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1461 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1462 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1463 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1464 DAG.getNode(ISD::CARRY_FALSE, 1465 N->getDebugLoc(), MVT::Flag)); 1466 } 1467 1468 return SDValue(); 1469} 1470 1471SDValue DAGCombiner::visitADDE(SDNode *N) { 1472 SDValue N0 = N->getOperand(0); 1473 SDValue N1 = N->getOperand(1); 1474 SDValue CarryIn = N->getOperand(2); 1475 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1476 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1477 1478 // canonicalize constant to RHS 1479 if (N0C && !N1C) 1480 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1481 N1, N0, CarryIn); 1482 1483 // fold (adde x, y, false) -> (addc x, y) 1484 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1485 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1486 1487 return SDValue(); 1488} 1489 1490SDValue DAGCombiner::visitSUB(SDNode *N) { 1491 SDValue N0 = N->getOperand(0); 1492 SDValue N1 = N->getOperand(1); 1493 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1494 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1495 EVT VT = N0.getValueType(); 1496 1497 // fold vector ops 1498 if (VT.isVector()) { 1499 SDValue FoldedVOp = SimplifyVBinOp(N); 1500 if (FoldedVOp.getNode()) return FoldedVOp; 1501 } 1502 1503 // fold (sub x, x) -> 0 1504 if (N0 == N1) 1505 return DAG.getConstant(0, N->getValueType(0)); 1506 // fold (sub c1, c2) -> c1-c2 1507 if (N0C && N1C) 1508 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1509 // fold (sub x, c) -> (add x, -c) 1510 if (N1C) 1511 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1512 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1513 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1514 if (N0C && N0C->isAllOnesValue()) 1515 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1516 // fold (A+B)-A -> B 1517 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1518 return N0.getOperand(1); 1519 // fold (A+B)-B -> A 1520 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1521 return N0.getOperand(0); 1522 // fold ((A+(B+or-C))-B) -> A+or-C 1523 if (N0.getOpcode() == ISD::ADD && 1524 (N0.getOperand(1).getOpcode() == ISD::SUB || 1525 N0.getOperand(1).getOpcode() == ISD::ADD) && 1526 N0.getOperand(1).getOperand(0) == N1) 1527 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1528 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1529 // fold ((A+(C+B))-B) -> A+C 1530 if (N0.getOpcode() == ISD::ADD && 1531 N0.getOperand(1).getOpcode() == ISD::ADD && 1532 N0.getOperand(1).getOperand(1) == N1) 1533 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1534 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1535 // fold ((A-(B-C))-C) -> A-B 1536 if (N0.getOpcode() == ISD::SUB && 1537 N0.getOperand(1).getOpcode() == ISD::SUB && 1538 N0.getOperand(1).getOperand(1) == N1) 1539 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1540 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1541 1542 // If either operand of a sub is undef, the result is undef 1543 if (N0.getOpcode() == ISD::UNDEF) 1544 return N0; 1545 if (N1.getOpcode() == ISD::UNDEF) 1546 return N1; 1547 1548 // If the relocation model supports it, consider symbol offsets. 1549 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1550 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1551 // fold (sub Sym, c) -> Sym-c 1552 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1553 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1554 GA->getOffset() - 1555 (uint64_t)N1C->getSExtValue()); 1556 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1557 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1558 if (GA->getGlobal() == GB->getGlobal()) 1559 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1560 VT); 1561 } 1562 1563 return SDValue(); 1564} 1565 1566SDValue DAGCombiner::visitMUL(SDNode *N) { 1567 SDValue N0 = N->getOperand(0); 1568 SDValue N1 = N->getOperand(1); 1569 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1570 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1571 EVT VT = N0.getValueType(); 1572 1573 // fold vector ops 1574 if (VT.isVector()) { 1575 SDValue FoldedVOp = SimplifyVBinOp(N); 1576 if (FoldedVOp.getNode()) return FoldedVOp; 1577 } 1578 1579 // fold (mul x, undef) -> 0 1580 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1581 return DAG.getConstant(0, VT); 1582 // fold (mul c1, c2) -> c1*c2 1583 if (N0C && N1C) 1584 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1585 // canonicalize constant to RHS 1586 if (N0C && !N1C) 1587 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1588 // fold (mul x, 0) -> 0 1589 if (N1C && N1C->isNullValue()) 1590 return N1; 1591 // fold (mul x, -1) -> 0-x 1592 if (N1C && N1C->isAllOnesValue()) 1593 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1594 DAG.getConstant(0, VT), N0); 1595 // fold (mul x, (1 << c)) -> x << c 1596 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1597 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1598 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1599 getShiftAmountTy())); 1600 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1601 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1602 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1603 // FIXME: If the input is something that is easily negated (e.g. a 1604 // single-use add), we should put the negate there. 1605 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1606 DAG.getConstant(0, VT), 1607 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1608 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1609 } 1610 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1611 if (N1C && N0.getOpcode() == ISD::SHL && 1612 isa<ConstantSDNode>(N0.getOperand(1))) { 1613 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1614 N1, N0.getOperand(1)); 1615 AddToWorkList(C3.getNode()); 1616 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1617 N0.getOperand(0), C3); 1618 } 1619 1620 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1621 // use. 1622 { 1623 SDValue Sh(0,0), Y(0,0); 1624 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1625 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1626 N0.getNode()->hasOneUse()) { 1627 Sh = N0; Y = N1; 1628 } else if (N1.getOpcode() == ISD::SHL && 1629 isa<ConstantSDNode>(N1.getOperand(1)) && 1630 N1.getNode()->hasOneUse()) { 1631 Sh = N1; Y = N0; 1632 } 1633 1634 if (Sh.getNode()) { 1635 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1636 Sh.getOperand(0), Y); 1637 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1638 Mul, Sh.getOperand(1)); 1639 } 1640 } 1641 1642 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1643 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1644 isa<ConstantSDNode>(N0.getOperand(1))) 1645 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1646 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1647 N0.getOperand(0), N1), 1648 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1649 N0.getOperand(1), N1)); 1650 1651 // reassociate mul 1652 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1653 if (RMUL.getNode() != 0) 1654 return RMUL; 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitSDIV(SDNode *N) { 1660 SDValue N0 = N->getOperand(0); 1661 SDValue N1 = N->getOperand(1); 1662 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1663 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1664 EVT VT = N->getValueType(0); 1665 1666 // fold vector ops 1667 if (VT.isVector()) { 1668 SDValue FoldedVOp = SimplifyVBinOp(N); 1669 if (FoldedVOp.getNode()) return FoldedVOp; 1670 } 1671 1672 // fold (sdiv c1, c2) -> c1/c2 1673 if (N0C && N1C && !N1C->isNullValue()) 1674 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1675 // fold (sdiv X, 1) -> X 1676 if (N1C && N1C->getSExtValue() == 1LL) 1677 return N0; 1678 // fold (sdiv X, -1) -> 0-X 1679 if (N1C && N1C->isAllOnesValue()) 1680 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1681 DAG.getConstant(0, VT), N0); 1682 // If we know the sign bits of both operands are zero, strength reduce to a 1683 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1684 if (!VT.isVector()) { 1685 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1686 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1687 N0, N1); 1688 } 1689 // fold (sdiv X, pow2) -> simple ops after legalize 1690 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1691 (isPowerOf2_64(N1C->getSExtValue()) || 1692 isPowerOf2_64(-N1C->getSExtValue()))) { 1693 // If dividing by powers of two is cheap, then don't perform the following 1694 // fold. 1695 if (TLI.isPow2DivCheap()) 1696 return SDValue(); 1697 1698 int64_t pow2 = N1C->getSExtValue(); 1699 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1700 unsigned lg2 = Log2_64(abs2); 1701 1702 // Splat the sign bit into the register 1703 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1704 DAG.getConstant(VT.getSizeInBits()-1, 1705 getShiftAmountTy())); 1706 AddToWorkList(SGN.getNode()); 1707 1708 // Add (N0 < 0) ? abs2 - 1 : 0; 1709 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1710 DAG.getConstant(VT.getSizeInBits() - lg2, 1711 getShiftAmountTy())); 1712 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1713 AddToWorkList(SRL.getNode()); 1714 AddToWorkList(ADD.getNode()); // Divide by pow2 1715 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1716 DAG.getConstant(lg2, getShiftAmountTy())); 1717 1718 // If we're dividing by a positive value, we're done. Otherwise, we must 1719 // negate the result. 1720 if (pow2 > 0) 1721 return SRA; 1722 1723 AddToWorkList(SRA.getNode()); 1724 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1725 DAG.getConstant(0, VT), SRA); 1726 } 1727 1728 // if integer divide is expensive and we satisfy the requirements, emit an 1729 // alternate sequence. 1730 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1731 !TLI.isIntDivCheap()) { 1732 SDValue Op = BuildSDIV(N); 1733 if (Op.getNode()) return Op; 1734 } 1735 1736 // undef / X -> 0 1737 if (N0.getOpcode() == ISD::UNDEF) 1738 return DAG.getConstant(0, VT); 1739 // X / undef -> undef 1740 if (N1.getOpcode() == ISD::UNDEF) 1741 return N1; 1742 1743 return SDValue(); 1744} 1745 1746SDValue DAGCombiner::visitUDIV(SDNode *N) { 1747 SDValue N0 = N->getOperand(0); 1748 SDValue N1 = N->getOperand(1); 1749 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1750 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1751 EVT VT = N->getValueType(0); 1752 1753 // fold vector ops 1754 if (VT.isVector()) { 1755 SDValue FoldedVOp = SimplifyVBinOp(N); 1756 if (FoldedVOp.getNode()) return FoldedVOp; 1757 } 1758 1759 // fold (udiv c1, c2) -> c1/c2 1760 if (N0C && N1C && !N1C->isNullValue()) 1761 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1762 // fold (udiv x, (1 << c)) -> x >>u c 1763 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1764 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1765 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1766 getShiftAmountTy())); 1767 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1768 if (N1.getOpcode() == ISD::SHL) { 1769 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1770 if (SHC->getAPIntValue().isPowerOf2()) { 1771 EVT ADDVT = N1.getOperand(1).getValueType(); 1772 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1773 N1.getOperand(1), 1774 DAG.getConstant(SHC->getAPIntValue() 1775 .logBase2(), 1776 ADDVT)); 1777 AddToWorkList(Add.getNode()); 1778 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1779 } 1780 } 1781 } 1782 // fold (udiv x, c) -> alternate 1783 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1784 SDValue Op = BuildUDIV(N); 1785 if (Op.getNode()) return Op; 1786 } 1787 1788 // undef / X -> 0 1789 if (N0.getOpcode() == ISD::UNDEF) 1790 return DAG.getConstant(0, VT); 1791 // X / undef -> undef 1792 if (N1.getOpcode() == ISD::UNDEF) 1793 return N1; 1794 1795 return SDValue(); 1796} 1797 1798SDValue DAGCombiner::visitSREM(SDNode *N) { 1799 SDValue N0 = N->getOperand(0); 1800 SDValue N1 = N->getOperand(1); 1801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1803 EVT VT = N->getValueType(0); 1804 1805 // fold (srem c1, c2) -> c1%c2 1806 if (N0C && N1C && !N1C->isNullValue()) 1807 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1808 // If we know the sign bits of both operands are zero, strength reduce to a 1809 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1810 if (!VT.isVector()) { 1811 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1812 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1813 } 1814 1815 // If X/C can be simplified by the division-by-constant logic, lower 1816 // X%C to the equivalent of X-X/C*C. 1817 if (N1C && !N1C->isNullValue()) { 1818 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1819 AddToWorkList(Div.getNode()); 1820 SDValue OptimizedDiv = combine(Div.getNode()); 1821 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1822 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1823 OptimizedDiv, N1); 1824 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1825 AddToWorkList(Mul.getNode()); 1826 return Sub; 1827 } 1828 } 1829 1830 // undef % X -> 0 1831 if (N0.getOpcode() == ISD::UNDEF) 1832 return DAG.getConstant(0, VT); 1833 // X % undef -> undef 1834 if (N1.getOpcode() == ISD::UNDEF) 1835 return N1; 1836 1837 return SDValue(); 1838} 1839 1840SDValue DAGCombiner::visitUREM(SDNode *N) { 1841 SDValue N0 = N->getOperand(0); 1842 SDValue N1 = N->getOperand(1); 1843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1845 EVT VT = N->getValueType(0); 1846 1847 // fold (urem c1, c2) -> c1%c2 1848 if (N0C && N1C && !N1C->isNullValue()) 1849 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1850 // fold (urem x, pow2) -> (and x, pow2-1) 1851 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1852 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1853 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1854 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1855 if (N1.getOpcode() == ISD::SHL) { 1856 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1857 if (SHC->getAPIntValue().isPowerOf2()) { 1858 SDValue Add = 1859 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1860 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1861 VT)); 1862 AddToWorkList(Add.getNode()); 1863 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1864 } 1865 } 1866 } 1867 1868 // If X/C can be simplified by the division-by-constant logic, lower 1869 // X%C to the equivalent of X-X/C*C. 1870 if (N1C && !N1C->isNullValue()) { 1871 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1872 AddToWorkList(Div.getNode()); 1873 SDValue OptimizedDiv = combine(Div.getNode()); 1874 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1875 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1876 OptimizedDiv, N1); 1877 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1878 AddToWorkList(Mul.getNode()); 1879 return Sub; 1880 } 1881 } 1882 1883 // undef % X -> 0 1884 if (N0.getOpcode() == ISD::UNDEF) 1885 return DAG.getConstant(0, VT); 1886 // X % undef -> undef 1887 if (N1.getOpcode() == ISD::UNDEF) 1888 return N1; 1889 1890 return SDValue(); 1891} 1892 1893SDValue DAGCombiner::visitMULHS(SDNode *N) { 1894 SDValue N0 = N->getOperand(0); 1895 SDValue N1 = N->getOperand(1); 1896 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1897 EVT VT = N->getValueType(0); 1898 1899 // fold (mulhs x, 0) -> 0 1900 if (N1C && N1C->isNullValue()) 1901 return N1; 1902 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1903 if (N1C && N1C->getAPIntValue() == 1) 1904 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1905 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1906 getShiftAmountTy())); 1907 // fold (mulhs x, undef) -> 0 1908 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1909 return DAG.getConstant(0, VT); 1910 1911 return SDValue(); 1912} 1913 1914SDValue DAGCombiner::visitMULHU(SDNode *N) { 1915 SDValue N0 = N->getOperand(0); 1916 SDValue N1 = N->getOperand(1); 1917 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1918 EVT VT = N->getValueType(0); 1919 1920 // fold (mulhu x, 0) -> 0 1921 if (N1C && N1C->isNullValue()) 1922 return N1; 1923 // fold (mulhu x, 1) -> 0 1924 if (N1C && N1C->getAPIntValue() == 1) 1925 return DAG.getConstant(0, N0.getValueType()); 1926 // fold (mulhu x, undef) -> 0 1927 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1928 return DAG.getConstant(0, VT); 1929 1930 return SDValue(); 1931} 1932 1933/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1934/// compute two values. LoOp and HiOp give the opcodes for the two computations 1935/// that are being performed. Return true if a simplification was made. 1936/// 1937SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1938 unsigned HiOp) { 1939 // If the high half is not needed, just compute the low half. 1940 bool HiExists = N->hasAnyUseOfValue(1); 1941 if (!HiExists && 1942 (!LegalOperations || 1943 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1944 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1945 N->op_begin(), N->getNumOperands()); 1946 return CombineTo(N, Res, Res); 1947 } 1948 1949 // If the low half is not needed, just compute the high half. 1950 bool LoExists = N->hasAnyUseOfValue(0); 1951 if (!LoExists && 1952 (!LegalOperations || 1953 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1954 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1955 N->op_begin(), N->getNumOperands()); 1956 return CombineTo(N, Res, Res); 1957 } 1958 1959 // If both halves are used, return as it is. 1960 if (LoExists && HiExists) 1961 return SDValue(); 1962 1963 // If the two computed results can be simplified separately, separate them. 1964 if (LoExists) { 1965 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1966 N->op_begin(), N->getNumOperands()); 1967 AddToWorkList(Lo.getNode()); 1968 SDValue LoOpt = combine(Lo.getNode()); 1969 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1970 (!LegalOperations || 1971 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1972 return CombineTo(N, LoOpt, LoOpt); 1973 } 1974 1975 if (HiExists) { 1976 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1977 N->op_begin(), N->getNumOperands()); 1978 AddToWorkList(Hi.getNode()); 1979 SDValue HiOpt = combine(Hi.getNode()); 1980 if (HiOpt.getNode() && HiOpt != Hi && 1981 (!LegalOperations || 1982 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1983 return CombineTo(N, HiOpt, HiOpt); 1984 } 1985 1986 return SDValue(); 1987} 1988 1989SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1990 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1991 if (Res.getNode()) return Res; 1992 1993 return SDValue(); 1994} 1995 1996SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1997 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1998 if (Res.getNode()) return Res; 1999 2000 return SDValue(); 2001} 2002 2003SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2004 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2005 if (Res.getNode()) return Res; 2006 2007 return SDValue(); 2008} 2009 2010SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2011 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2012 if (Res.getNode()) return Res; 2013 2014 return SDValue(); 2015} 2016 2017/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2018/// two operands of the same opcode, try to simplify it. 2019SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2020 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2021 EVT VT = N0.getValueType(); 2022 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2023 2024 // Bail early if none of these transforms apply. 2025 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2026 2027 // For each of OP in AND/OR/XOR: 2028 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2029 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2030 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2031 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 2032 // 2033 // do not sink logical op inside of a vector extend, since it may combine 2034 // into a vsetcc. 2035 EVT Op0VT = N0.getOperand(0).getValueType(); 2036 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2037 N0.getOpcode() == ISD::SIGN_EXTEND || 2038 // Avoid infinite looping with PromoteIntBinOp. 2039 (N0.getOpcode() == ISD::ANY_EXTEND && 2040 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2041 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) && 2042 !VT.isVector() && 2043 Op0VT == N1.getOperand(0).getValueType() && 2044 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2045 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2046 N0.getOperand(0).getValueType(), 2047 N0.getOperand(0), N1.getOperand(0)); 2048 AddToWorkList(ORNode.getNode()); 2049 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2050 } 2051 2052 // For each of OP in SHL/SRL/SRA/AND... 2053 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2054 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2055 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2056 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2057 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2058 N0.getOperand(1) == N1.getOperand(1)) { 2059 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2060 N0.getOperand(0).getValueType(), 2061 N0.getOperand(0), N1.getOperand(0)); 2062 AddToWorkList(ORNode.getNode()); 2063 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2064 ORNode, N0.getOperand(1)); 2065 } 2066 2067 return SDValue(); 2068} 2069 2070SDValue DAGCombiner::visitAND(SDNode *N) { 2071 SDValue N0 = N->getOperand(0); 2072 SDValue N1 = N->getOperand(1); 2073 SDValue LL, LR, RL, RR, CC0, CC1; 2074 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2075 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2076 EVT VT = N1.getValueType(); 2077 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2078 2079 // fold vector ops 2080 if (VT.isVector()) { 2081 SDValue FoldedVOp = SimplifyVBinOp(N); 2082 if (FoldedVOp.getNode()) return FoldedVOp; 2083 } 2084 2085 // fold (and x, undef) -> 0 2086 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2087 return DAG.getConstant(0, VT); 2088 // fold (and c1, c2) -> c1&c2 2089 if (N0C && N1C) 2090 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2091 // canonicalize constant to RHS 2092 if (N0C && !N1C) 2093 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2094 // fold (and x, -1) -> x 2095 if (N1C && N1C->isAllOnesValue()) 2096 return N0; 2097 // if (and x, c) is known to be zero, return 0 2098 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2099 APInt::getAllOnesValue(BitWidth))) 2100 return DAG.getConstant(0, VT); 2101 // reassociate and 2102 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2103 if (RAND.getNode() != 0) 2104 return RAND; 2105 // fold (and (or x, C), D) -> D if (C & D) == D 2106 if (N1C && N0.getOpcode() == ISD::OR) 2107 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2108 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2109 return N1; 2110 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2111 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2112 SDValue N0Op0 = N0.getOperand(0); 2113 APInt Mask = ~N1C->getAPIntValue(); 2114 Mask.trunc(N0Op0.getValueSizeInBits()); 2115 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2116 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2117 N0.getValueType(), N0Op0); 2118 2119 // Replace uses of the AND with uses of the Zero extend node. 2120 CombineTo(N, Zext); 2121 2122 // We actually want to replace all uses of the any_extend with the 2123 // zero_extend, to avoid duplicating things. This will later cause this 2124 // AND to be folded. 2125 CombineTo(N0.getNode(), Zext); 2126 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2127 } 2128 } 2129 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2130 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2131 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2132 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2133 2134 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2135 LL.getValueType().isInteger()) { 2136 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2137 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2138 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2139 LR.getValueType(), LL, RL); 2140 AddToWorkList(ORNode.getNode()); 2141 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2142 } 2143 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2144 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2145 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2146 LR.getValueType(), LL, RL); 2147 AddToWorkList(ANDNode.getNode()); 2148 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2149 } 2150 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2151 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2152 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2153 LR.getValueType(), LL, RL); 2154 AddToWorkList(ORNode.getNode()); 2155 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2156 } 2157 } 2158 // canonicalize equivalent to ll == rl 2159 if (LL == RR && LR == RL) { 2160 Op1 = ISD::getSetCCSwappedOperands(Op1); 2161 std::swap(RL, RR); 2162 } 2163 if (LL == RL && LR == RR) { 2164 bool isInteger = LL.getValueType().isInteger(); 2165 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2166 if (Result != ISD::SETCC_INVALID && 2167 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2168 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2169 LL, LR, Result); 2170 } 2171 } 2172 2173 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2174 if (N0.getOpcode() == N1.getOpcode()) { 2175 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2176 if (Tmp.getNode()) return Tmp; 2177 } 2178 2179 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2180 // fold (and (sra)) -> (and (srl)) when possible. 2181 if (!VT.isVector() && 2182 SimplifyDemandedBits(SDValue(N, 0))) 2183 return SDValue(N, 0); 2184 2185 // fold (zext_inreg (extload x)) -> (zextload x) 2186 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2187 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2188 EVT MemVT = LN0->getMemoryVT(); 2189 // If we zero all the possible extended bits, then we can turn this into 2190 // a zextload if we are running before legalize or the operation is legal. 2191 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2192 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2193 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2194 ((!LegalOperations && !LN0->isVolatile()) || 2195 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2196 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2197 LN0->getChain(), LN0->getBasePtr(), 2198 LN0->getSrcValue(), 2199 LN0->getSrcValueOffset(), MemVT, 2200 LN0->isVolatile(), LN0->isNonTemporal(), 2201 LN0->getAlignment()); 2202 AddToWorkList(N); 2203 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2204 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2205 } 2206 } 2207 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2208 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2209 N0.hasOneUse()) { 2210 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2211 EVT MemVT = LN0->getMemoryVT(); 2212 // If we zero all the possible extended bits, then we can turn this into 2213 // a zextload if we are running before legalize or the operation is legal. 2214 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2215 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2216 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2217 ((!LegalOperations && !LN0->isVolatile()) || 2218 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2219 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2220 LN0->getChain(), 2221 LN0->getBasePtr(), LN0->getSrcValue(), 2222 LN0->getSrcValueOffset(), MemVT, 2223 LN0->isVolatile(), LN0->isNonTemporal(), 2224 LN0->getAlignment()); 2225 AddToWorkList(N); 2226 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2227 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2228 } 2229 } 2230 2231 // fold (and (load x), 255) -> (zextload x, i8) 2232 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2233 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2234 if (N1C && (N0.getOpcode() == ISD::LOAD || 2235 (N0.getOpcode() == ISD::ANY_EXTEND && 2236 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2237 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2238 LoadSDNode *LN0 = HasAnyExt 2239 ? cast<LoadSDNode>(N0.getOperand(0)) 2240 : cast<LoadSDNode>(N0); 2241 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2242 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2243 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2244 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2245 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2246 EVT LoadedVT = LN0->getMemoryVT(); 2247 2248 if (ExtVT == LoadedVT && 2249 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2250 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2251 2252 SDValue NewLoad = 2253 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2254 LN0->getChain(), LN0->getBasePtr(), 2255 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2256 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2257 LN0->getAlignment()); 2258 AddToWorkList(N); 2259 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2260 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2261 } 2262 2263 // Do not change the width of a volatile load. 2264 // Do not generate loads of non-round integer types since these can 2265 // be expensive (and would be wrong if the type is not byte sized). 2266 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2267 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2268 EVT PtrType = LN0->getOperand(1).getValueType(); 2269 2270 unsigned Alignment = LN0->getAlignment(); 2271 SDValue NewPtr = LN0->getBasePtr(); 2272 2273 // For big endian targets, we need to add an offset to the pointer 2274 // to load the correct bytes. For little endian systems, we merely 2275 // need to read fewer bytes from the same pointer. 2276 if (TLI.isBigEndian()) { 2277 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2278 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2279 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2280 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2281 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2282 Alignment = MinAlign(Alignment, PtrOff); 2283 } 2284 2285 AddToWorkList(NewPtr.getNode()); 2286 2287 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2288 SDValue Load = 2289 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2290 LN0->getChain(), NewPtr, 2291 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2292 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2293 Alignment); 2294 AddToWorkList(N); 2295 CombineTo(LN0, Load, Load.getValue(1)); 2296 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2297 } 2298 } 2299 } 2300 } 2301 2302 return SDValue(); 2303} 2304 2305SDValue DAGCombiner::visitOR(SDNode *N) { 2306 SDValue N0 = N->getOperand(0); 2307 SDValue N1 = N->getOperand(1); 2308 SDValue LL, LR, RL, RR, CC0, CC1; 2309 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2310 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2311 EVT VT = N1.getValueType(); 2312 2313 // fold vector ops 2314 if (VT.isVector()) { 2315 SDValue FoldedVOp = SimplifyVBinOp(N); 2316 if (FoldedVOp.getNode()) return FoldedVOp; 2317 } 2318 2319 // fold (or x, undef) -> -1 2320 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 2321 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2322 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2323 } 2324 // fold (or c1, c2) -> c1|c2 2325 if (N0C && N1C) 2326 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2327 // canonicalize constant to RHS 2328 if (N0C && !N1C) 2329 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2330 // fold (or x, 0) -> x 2331 if (N1C && N1C->isNullValue()) 2332 return N0; 2333 // fold (or x, -1) -> -1 2334 if (N1C && N1C->isAllOnesValue()) 2335 return N1; 2336 // fold (or x, c) -> c iff (x & ~c) == 0 2337 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2338 return N1; 2339 // reassociate or 2340 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2341 if (ROR.getNode() != 0) 2342 return ROR; 2343 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2344 // iff (c1 & c2) == 0. 2345 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2346 isa<ConstantSDNode>(N0.getOperand(1))) { 2347 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2348 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2349 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2350 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2351 N0.getOperand(0), N1), 2352 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2353 } 2354 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2355 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2356 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2357 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2358 2359 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2360 LL.getValueType().isInteger()) { 2361 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2362 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2363 if (cast<ConstantSDNode>(LR)->isNullValue() && 2364 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2365 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2366 LR.getValueType(), LL, RL); 2367 AddToWorkList(ORNode.getNode()); 2368 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2369 } 2370 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2371 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2372 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2373 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2374 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2375 LR.getValueType(), LL, RL); 2376 AddToWorkList(ANDNode.getNode()); 2377 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2378 } 2379 } 2380 // canonicalize equivalent to ll == rl 2381 if (LL == RR && LR == RL) { 2382 Op1 = ISD::getSetCCSwappedOperands(Op1); 2383 std::swap(RL, RR); 2384 } 2385 if (LL == RL && LR == RR) { 2386 bool isInteger = LL.getValueType().isInteger(); 2387 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2388 if (Result != ISD::SETCC_INVALID && 2389 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2390 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2391 LL, LR, Result); 2392 } 2393 } 2394 2395 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2396 if (N0.getOpcode() == N1.getOpcode()) { 2397 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2398 if (Tmp.getNode()) return Tmp; 2399 } 2400 2401 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2402 if (N0.getOpcode() == ISD::AND && 2403 N1.getOpcode() == ISD::AND && 2404 N0.getOperand(1).getOpcode() == ISD::Constant && 2405 N1.getOperand(1).getOpcode() == ISD::Constant && 2406 // Don't increase # computations. 2407 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2408 // We can only do this xform if we know that bits from X that are set in C2 2409 // but not in C1 are already zero. Likewise for Y. 2410 const APInt &LHSMask = 2411 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2412 const APInt &RHSMask = 2413 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2414 2415 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2416 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2417 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2418 N0.getOperand(0), N1.getOperand(0)); 2419 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2420 DAG.getConstant(LHSMask | RHSMask, VT)); 2421 } 2422 } 2423 2424 // See if this is some rotate idiom. 2425 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2426 return SDValue(Rot, 0); 2427 2428 return SDValue(); 2429} 2430 2431/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2432static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2433 if (Op.getOpcode() == ISD::AND) { 2434 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2435 Mask = Op.getOperand(1); 2436 Op = Op.getOperand(0); 2437 } else { 2438 return false; 2439 } 2440 } 2441 2442 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2443 Shift = Op; 2444 return true; 2445 } 2446 2447 return false; 2448} 2449 2450// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2451// idioms for rotate, and if the target supports rotation instructions, generate 2452// a rot[lr]. 2453SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2454 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2455 EVT VT = LHS.getValueType(); 2456 if (!TLI.isTypeLegal(VT)) return 0; 2457 2458 // The target must have at least one rotate flavor. 2459 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2460 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2461 if (!HasROTL && !HasROTR) return 0; 2462 2463 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2464 SDValue LHSShift; // The shift. 2465 SDValue LHSMask; // AND value if any. 2466 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2467 return 0; // Not part of a rotate. 2468 2469 SDValue RHSShift; // The shift. 2470 SDValue RHSMask; // AND value if any. 2471 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2472 return 0; // Not part of a rotate. 2473 2474 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2475 return 0; // Not shifting the same value. 2476 2477 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2478 return 0; // Shifts must disagree. 2479 2480 // Canonicalize shl to left side in a shl/srl pair. 2481 if (RHSShift.getOpcode() == ISD::SHL) { 2482 std::swap(LHS, RHS); 2483 std::swap(LHSShift, RHSShift); 2484 std::swap(LHSMask , RHSMask ); 2485 } 2486 2487 unsigned OpSizeInBits = VT.getSizeInBits(); 2488 SDValue LHSShiftArg = LHSShift.getOperand(0); 2489 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2490 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2491 2492 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2493 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2494 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2495 RHSShiftAmt.getOpcode() == ISD::Constant) { 2496 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2497 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2498 if ((LShVal + RShVal) != OpSizeInBits) 2499 return 0; 2500 2501 SDValue Rot; 2502 if (HasROTL) 2503 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2504 else 2505 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2506 2507 // If there is an AND of either shifted operand, apply it to the result. 2508 if (LHSMask.getNode() || RHSMask.getNode()) { 2509 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2510 2511 if (LHSMask.getNode()) { 2512 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2513 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2514 } 2515 if (RHSMask.getNode()) { 2516 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2517 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2518 } 2519 2520 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2521 } 2522 2523 return Rot.getNode(); 2524 } 2525 2526 // If there is a mask here, and we have a variable shift, we can't be sure 2527 // that we're masking out the right stuff. 2528 if (LHSMask.getNode() || RHSMask.getNode()) 2529 return 0; 2530 2531 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2532 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2533 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2534 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2535 if (ConstantSDNode *SUBC = 2536 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2537 if (SUBC->getAPIntValue() == OpSizeInBits) { 2538 if (HasROTL) 2539 return DAG.getNode(ISD::ROTL, DL, VT, 2540 LHSShiftArg, LHSShiftAmt).getNode(); 2541 else 2542 return DAG.getNode(ISD::ROTR, DL, VT, 2543 LHSShiftArg, RHSShiftAmt).getNode(); 2544 } 2545 } 2546 } 2547 2548 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2549 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2550 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2551 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2552 if (ConstantSDNode *SUBC = 2553 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2554 if (SUBC->getAPIntValue() == OpSizeInBits) { 2555 if (HasROTR) 2556 return DAG.getNode(ISD::ROTR, DL, VT, 2557 LHSShiftArg, RHSShiftAmt).getNode(); 2558 else 2559 return DAG.getNode(ISD::ROTL, DL, VT, 2560 LHSShiftArg, LHSShiftAmt).getNode(); 2561 } 2562 } 2563 } 2564 2565 // Look for sign/zext/any-extended or truncate cases: 2566 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2567 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2568 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2569 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2570 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2571 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2572 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2573 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2574 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2575 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2576 if (RExtOp0.getOpcode() == ISD::SUB && 2577 RExtOp0.getOperand(1) == LExtOp0) { 2578 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2579 // (rotl x, y) 2580 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2581 // (rotr x, (sub 32, y)) 2582 if (ConstantSDNode *SUBC = 2583 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2584 if (SUBC->getAPIntValue() == OpSizeInBits) { 2585 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2586 LHSShiftArg, 2587 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2588 } 2589 } 2590 } else if (LExtOp0.getOpcode() == ISD::SUB && 2591 RExtOp0 == LExtOp0.getOperand(1)) { 2592 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2593 // (rotr x, y) 2594 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2595 // (rotl x, (sub 32, y)) 2596 if (ConstantSDNode *SUBC = 2597 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2598 if (SUBC->getAPIntValue() == OpSizeInBits) { 2599 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2600 LHSShiftArg, 2601 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2602 } 2603 } 2604 } 2605 } 2606 2607 return 0; 2608} 2609 2610SDValue DAGCombiner::visitXOR(SDNode *N) { 2611 SDValue N0 = N->getOperand(0); 2612 SDValue N1 = N->getOperand(1); 2613 SDValue LHS, RHS, CC; 2614 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2615 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2616 EVT VT = N0.getValueType(); 2617 2618 // fold vector ops 2619 if (VT.isVector()) { 2620 SDValue FoldedVOp = SimplifyVBinOp(N); 2621 if (FoldedVOp.getNode()) return FoldedVOp; 2622 } 2623 2624 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2625 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2626 return DAG.getConstant(0, VT); 2627 // fold (xor x, undef) -> undef 2628 if (N0.getOpcode() == ISD::UNDEF) 2629 return N0; 2630 if (N1.getOpcode() == ISD::UNDEF) 2631 return N1; 2632 // fold (xor c1, c2) -> c1^c2 2633 if (N0C && N1C) 2634 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2635 // canonicalize constant to RHS 2636 if (N0C && !N1C) 2637 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2638 // fold (xor x, 0) -> x 2639 if (N1C && N1C->isNullValue()) 2640 return N0; 2641 // reassociate xor 2642 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2643 if (RXOR.getNode() != 0) 2644 return RXOR; 2645 2646 // fold !(x cc y) -> (x !cc y) 2647 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2648 bool isInt = LHS.getValueType().isInteger(); 2649 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2650 isInt); 2651 2652 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2653 switch (N0.getOpcode()) { 2654 default: 2655 llvm_unreachable("Unhandled SetCC Equivalent!"); 2656 case ISD::SETCC: 2657 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2658 case ISD::SELECT_CC: 2659 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2660 N0.getOperand(3), NotCC); 2661 } 2662 } 2663 } 2664 2665 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2666 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2667 N0.getNode()->hasOneUse() && 2668 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2669 SDValue V = N0.getOperand(0); 2670 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2671 DAG.getConstant(1, V.getValueType())); 2672 AddToWorkList(V.getNode()); 2673 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2674 } 2675 2676 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2677 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2678 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2679 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2680 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2681 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2682 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2683 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2684 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2685 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2686 } 2687 } 2688 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2689 if (N1C && N1C->isAllOnesValue() && 2690 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2691 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2692 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2693 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2694 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2695 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2696 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2697 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2698 } 2699 } 2700 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2701 if (N1C && N0.getOpcode() == ISD::XOR) { 2702 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2703 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2704 if (N00C) 2705 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2706 DAG.getConstant(N1C->getAPIntValue() ^ 2707 N00C->getAPIntValue(), VT)); 2708 if (N01C) 2709 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2710 DAG.getConstant(N1C->getAPIntValue() ^ 2711 N01C->getAPIntValue(), VT)); 2712 } 2713 // fold (xor x, x) -> 0 2714 if (N0 == N1) { 2715 if (!VT.isVector()) { 2716 return DAG.getConstant(0, VT); 2717 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2718 // Produce a vector of zeros. 2719 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2720 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2721 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2722 &Ops[0], Ops.size()); 2723 } 2724 } 2725 2726 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2727 if (N0.getOpcode() == N1.getOpcode()) { 2728 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2729 if (Tmp.getNode()) return Tmp; 2730 } 2731 2732 // Simplify the expression using non-local knowledge. 2733 if (!VT.isVector() && 2734 SimplifyDemandedBits(SDValue(N, 0))) 2735 return SDValue(N, 0); 2736 2737 return SDValue(); 2738} 2739 2740/// visitShiftByConstant - Handle transforms common to the three shifts, when 2741/// the shift amount is a constant. 2742SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2743 SDNode *LHS = N->getOperand(0).getNode(); 2744 if (!LHS->hasOneUse()) return SDValue(); 2745 2746 // We want to pull some binops through shifts, so that we have (and (shift)) 2747 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2748 // thing happens with address calculations, so it's important to canonicalize 2749 // it. 2750 bool HighBitSet = false; // Can we transform this if the high bit is set? 2751 2752 switch (LHS->getOpcode()) { 2753 default: return SDValue(); 2754 case ISD::OR: 2755 case ISD::XOR: 2756 HighBitSet = false; // We can only transform sra if the high bit is clear. 2757 break; 2758 case ISD::AND: 2759 HighBitSet = true; // We can only transform sra if the high bit is set. 2760 break; 2761 case ISD::ADD: 2762 if (N->getOpcode() != ISD::SHL) 2763 return SDValue(); // only shl(add) not sr[al](add). 2764 HighBitSet = false; // We can only transform sra if the high bit is clear. 2765 break; 2766 } 2767 2768 // We require the RHS of the binop to be a constant as well. 2769 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2770 if (!BinOpCst) return SDValue(); 2771 2772 // FIXME: disable this unless the input to the binop is a shift by a constant. 2773 // If it is not a shift, it pessimizes some common cases like: 2774 // 2775 // void foo(int *X, int i) { X[i & 1235] = 1; } 2776 // int bar(int *X, int i) { return X[i & 255]; } 2777 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2778 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2779 BinOpLHSVal->getOpcode() != ISD::SRA && 2780 BinOpLHSVal->getOpcode() != ISD::SRL) || 2781 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2782 return SDValue(); 2783 2784 EVT VT = N->getValueType(0); 2785 2786 // If this is a signed shift right, and the high bit is modified by the 2787 // logical operation, do not perform the transformation. The highBitSet 2788 // boolean indicates the value of the high bit of the constant which would 2789 // cause it to be modified for this operation. 2790 if (N->getOpcode() == ISD::SRA) { 2791 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2792 if (BinOpRHSSignSet != HighBitSet) 2793 return SDValue(); 2794 } 2795 2796 // Fold the constants, shifting the binop RHS by the shift amount. 2797 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2798 N->getValueType(0), 2799 LHS->getOperand(1), N->getOperand(1)); 2800 2801 // Create the new shift. 2802 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2803 VT, LHS->getOperand(0), N->getOperand(1)); 2804 2805 // Create the new binop. 2806 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2807} 2808 2809SDValue DAGCombiner::visitSHL(SDNode *N) { 2810 SDValue N0 = N->getOperand(0); 2811 SDValue N1 = N->getOperand(1); 2812 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2813 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2814 EVT VT = N0.getValueType(); 2815 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2816 2817 // fold (shl c1, c2) -> c1<<c2 2818 if (N0C && N1C) 2819 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2820 // fold (shl 0, x) -> 0 2821 if (N0C && N0C->isNullValue()) 2822 return N0; 2823 // fold (shl x, c >= size(x)) -> undef 2824 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2825 return DAG.getUNDEF(VT); 2826 // fold (shl x, 0) -> x 2827 if (N1C && N1C->isNullValue()) 2828 return N0; 2829 // if (shl x, c) is known to be zero, return 0 2830 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2831 APInt::getAllOnesValue(OpSizeInBits))) 2832 return DAG.getConstant(0, VT); 2833 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2834 if (N1.getOpcode() == ISD::TRUNCATE && 2835 N1.getOperand(0).getOpcode() == ISD::AND && 2836 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2837 SDValue N101 = N1.getOperand(0).getOperand(1); 2838 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2839 EVT TruncVT = N1.getValueType(); 2840 SDValue N100 = N1.getOperand(0).getOperand(0); 2841 APInt TruncC = N101C->getAPIntValue(); 2842 TruncC.trunc(TruncVT.getSizeInBits()); 2843 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2844 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2845 DAG.getNode(ISD::TRUNCATE, 2846 N->getDebugLoc(), 2847 TruncVT, N100), 2848 DAG.getConstant(TruncC, TruncVT))); 2849 } 2850 } 2851 2852 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2853 return SDValue(N, 0); 2854 2855 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2856 if (N1C && N0.getOpcode() == ISD::SHL && 2857 N0.getOperand(1).getOpcode() == ISD::Constant) { 2858 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2859 uint64_t c2 = N1C->getZExtValue(); 2860 if (c1 + c2 > OpSizeInBits) 2861 return DAG.getConstant(0, VT); 2862 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2863 DAG.getConstant(c1 + c2, N1.getValueType())); 2864 } 2865 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2866 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2867 if (N1C && N0.getOpcode() == ISD::SRL && 2868 N0.getOperand(1).getOpcode() == ISD::Constant) { 2869 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2870 if (c1 < VT.getSizeInBits()) { 2871 uint64_t c2 = N1C->getZExtValue(); 2872 SDValue HiBitsMask = 2873 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2874 VT.getSizeInBits() - c1), 2875 VT); 2876 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2877 N0.getOperand(0), 2878 HiBitsMask); 2879 if (c2 > c1) 2880 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2881 DAG.getConstant(c2-c1, N1.getValueType())); 2882 else 2883 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2884 DAG.getConstant(c1-c2, N1.getValueType())); 2885 } 2886 } 2887 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2888 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2889 SDValue HiBitsMask = 2890 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2891 VT.getSizeInBits() - 2892 N1C->getZExtValue()), 2893 VT); 2894 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2895 HiBitsMask); 2896 } 2897 2898 if (N1C) { 2899 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 2900 if (NewSHL.getNode()) 2901 return NewSHL; 2902 } 2903 2904 return SDValue(); 2905} 2906 2907SDValue DAGCombiner::visitSRA(SDNode *N) { 2908 SDValue N0 = N->getOperand(0); 2909 SDValue N1 = N->getOperand(1); 2910 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2911 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2912 EVT VT = N0.getValueType(); 2913 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2914 2915 // fold (sra c1, c2) -> (sra c1, c2) 2916 if (N0C && N1C) 2917 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2918 // fold (sra 0, x) -> 0 2919 if (N0C && N0C->isNullValue()) 2920 return N0; 2921 // fold (sra -1, x) -> -1 2922 if (N0C && N0C->isAllOnesValue()) 2923 return N0; 2924 // fold (sra x, (setge c, size(x))) -> undef 2925 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2926 return DAG.getUNDEF(VT); 2927 // fold (sra x, 0) -> x 2928 if (N1C && N1C->isNullValue()) 2929 return N0; 2930 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2931 // sext_inreg. 2932 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2933 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2934 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2935 if (VT.isVector()) 2936 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2937 ExtVT, VT.getVectorNumElements()); 2938 if ((!LegalOperations || 2939 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2940 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2941 N0.getOperand(0), DAG.getValueType(ExtVT)); 2942 } 2943 2944 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2945 if (N1C && N0.getOpcode() == ISD::SRA) { 2946 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2947 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2948 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2949 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2950 DAG.getConstant(Sum, N1C->getValueType(0))); 2951 } 2952 } 2953 2954 // fold (sra (shl X, m), (sub result_size, n)) 2955 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2956 // result_size - n != m. 2957 // If truncate is free for the target sext(shl) is likely to result in better 2958 // code. 2959 if (N0.getOpcode() == ISD::SHL) { 2960 // Get the two constanst of the shifts, CN0 = m, CN = n. 2961 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2962 if (N01C && N1C) { 2963 // Determine what the truncate's result bitsize and type would be. 2964 EVT TruncVT = 2965 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2966 // Determine the residual right-shift amount. 2967 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2968 2969 // If the shift is not a no-op (in which case this should be just a sign 2970 // extend already), the truncated to type is legal, sign_extend is legal 2971 // on that type, and the truncate to that type is both legal and free, 2972 // perform the transform. 2973 if ((ShiftAmt > 0) && 2974 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2975 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2976 TLI.isTruncateFree(VT, TruncVT)) { 2977 2978 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2979 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2980 N0.getOperand(0), Amt); 2981 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2982 Shift); 2983 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2984 N->getValueType(0), Trunc); 2985 } 2986 } 2987 } 2988 2989 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2990 if (N1.getOpcode() == ISD::TRUNCATE && 2991 N1.getOperand(0).getOpcode() == ISD::AND && 2992 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2993 SDValue N101 = N1.getOperand(0).getOperand(1); 2994 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2995 EVT TruncVT = N1.getValueType(); 2996 SDValue N100 = N1.getOperand(0).getOperand(0); 2997 APInt TruncC = N101C->getAPIntValue(); 2998 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 2999 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3000 DAG.getNode(ISD::AND, N->getDebugLoc(), 3001 TruncVT, 3002 DAG.getNode(ISD::TRUNCATE, 3003 N->getDebugLoc(), 3004 TruncVT, N100), 3005 DAG.getConstant(TruncC, TruncVT))); 3006 } 3007 } 3008 3009 // Simplify, based on bits shifted out of the LHS. 3010 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3011 return SDValue(N, 0); 3012 3013 3014 // If the sign bit is known to be zero, switch this to a SRL. 3015 if (DAG.SignBitIsZero(N0)) 3016 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3017 3018 if (N1C) { 3019 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3020 if (NewSRA.getNode()) 3021 return NewSRA; 3022 } 3023 3024 return SDValue(); 3025} 3026 3027SDValue DAGCombiner::visitSRL(SDNode *N) { 3028 SDValue N0 = N->getOperand(0); 3029 SDValue N1 = N->getOperand(1); 3030 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3031 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3032 EVT VT = N0.getValueType(); 3033 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3034 3035 // fold (srl c1, c2) -> c1 >>u c2 3036 if (N0C && N1C) 3037 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3038 // fold (srl 0, x) -> 0 3039 if (N0C && N0C->isNullValue()) 3040 return N0; 3041 // fold (srl x, c >= size(x)) -> undef 3042 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3043 return DAG.getUNDEF(VT); 3044 // fold (srl x, 0) -> x 3045 if (N1C && N1C->isNullValue()) 3046 return N0; 3047 // if (srl x, c) is known to be zero, return 0 3048 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3049 APInt::getAllOnesValue(OpSizeInBits))) 3050 return DAG.getConstant(0, VT); 3051 3052 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3053 if (N1C && N0.getOpcode() == ISD::SRL && 3054 N0.getOperand(1).getOpcode() == ISD::Constant) { 3055 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3056 uint64_t c2 = N1C->getZExtValue(); 3057 if (c1 + c2 > OpSizeInBits) 3058 return DAG.getConstant(0, VT); 3059 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3060 DAG.getConstant(c1 + c2, N1.getValueType())); 3061 } 3062 3063 // fold (srl (shl x, c), c) -> (and x, cst2) 3064 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3065 N0.getValueSizeInBits() <= 64) { 3066 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3067 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3068 DAG.getConstant(~0ULL >> ShAmt, VT)); 3069 } 3070 3071 3072 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3073 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3074 // Shifting in all undef bits? 3075 EVT SmallVT = N0.getOperand(0).getValueType(); 3076 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3077 return DAG.getUNDEF(VT); 3078 3079 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3080 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3081 N0.getOperand(0), N1); 3082 AddToWorkList(SmallShift.getNode()); 3083 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3084 } 3085 } 3086 3087 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3088 // bit, which is unmodified by sra. 3089 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3090 if (N0.getOpcode() == ISD::SRA) 3091 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3092 } 3093 3094 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3095 if (N1C && N0.getOpcode() == ISD::CTLZ && 3096 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3097 APInt KnownZero, KnownOne; 3098 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3099 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3100 3101 // If any of the input bits are KnownOne, then the input couldn't be all 3102 // zeros, thus the result of the srl will always be zero. 3103 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3104 3105 // If all of the bits input the to ctlz node are known to be zero, then 3106 // the result of the ctlz is "32" and the result of the shift is one. 3107 APInt UnknownBits = ~KnownZero & Mask; 3108 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3109 3110 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3111 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3112 // Okay, we know that only that the single bit specified by UnknownBits 3113 // could be set on input to the CTLZ node. If this bit is set, the SRL 3114 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3115 // to an SRL/XOR pair, which is likely to simplify more. 3116 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3117 SDValue Op = N0.getOperand(0); 3118 3119 if (ShAmt) { 3120 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3121 DAG.getConstant(ShAmt, getShiftAmountTy())); 3122 AddToWorkList(Op.getNode()); 3123 } 3124 3125 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3126 Op, DAG.getConstant(1, VT)); 3127 } 3128 } 3129 3130 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3131 if (N1.getOpcode() == ISD::TRUNCATE && 3132 N1.getOperand(0).getOpcode() == ISD::AND && 3133 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3134 SDValue N101 = N1.getOperand(0).getOperand(1); 3135 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3136 EVT TruncVT = N1.getValueType(); 3137 SDValue N100 = N1.getOperand(0).getOperand(0); 3138 APInt TruncC = N101C->getAPIntValue(); 3139 TruncC.trunc(TruncVT.getSizeInBits()); 3140 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3141 DAG.getNode(ISD::AND, N->getDebugLoc(), 3142 TruncVT, 3143 DAG.getNode(ISD::TRUNCATE, 3144 N->getDebugLoc(), 3145 TruncVT, N100), 3146 DAG.getConstant(TruncC, TruncVT))); 3147 } 3148 } 3149 3150 // fold operands of srl based on knowledge that the low bits are not 3151 // demanded. 3152 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3153 return SDValue(N, 0); 3154 3155 if (N1C) { 3156 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3157 if (NewSRL.getNode()) 3158 return NewSRL; 3159 } 3160 3161 // Here is a common situation. We want to optimize: 3162 // 3163 // %a = ... 3164 // %b = and i32 %a, 2 3165 // %c = srl i32 %b, 1 3166 // brcond i32 %c ... 3167 // 3168 // into 3169 // 3170 // %a = ... 3171 // %b = and %a, 2 3172 // %c = setcc eq %b, 0 3173 // brcond %c ... 3174 // 3175 // However when after the source operand of SRL is optimized into AND, the SRL 3176 // itself may not be optimized further. Look for it and add the BRCOND into 3177 // the worklist. 3178 if (N->hasOneUse()) { 3179 SDNode *Use = *N->use_begin(); 3180 if (Use->getOpcode() == ISD::BRCOND) 3181 AddToWorkList(Use); 3182 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3183 // Also look pass the truncate. 3184 Use = *Use->use_begin(); 3185 if (Use->getOpcode() == ISD::BRCOND) 3186 AddToWorkList(Use); 3187 } 3188 } 3189 3190 return SDValue(); 3191} 3192 3193SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3194 SDValue N0 = N->getOperand(0); 3195 EVT VT = N->getValueType(0); 3196 3197 // fold (ctlz c1) -> c2 3198 if (isa<ConstantSDNode>(N0)) 3199 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3200 return SDValue(); 3201} 3202 3203SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3204 SDValue N0 = N->getOperand(0); 3205 EVT VT = N->getValueType(0); 3206 3207 // fold (cttz c1) -> c2 3208 if (isa<ConstantSDNode>(N0)) 3209 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3210 return SDValue(); 3211} 3212 3213SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3214 SDValue N0 = N->getOperand(0); 3215 EVT VT = N->getValueType(0); 3216 3217 // fold (ctpop c1) -> c2 3218 if (isa<ConstantSDNode>(N0)) 3219 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3220 return SDValue(); 3221} 3222 3223SDValue DAGCombiner::visitSELECT(SDNode *N) { 3224 SDValue N0 = N->getOperand(0); 3225 SDValue N1 = N->getOperand(1); 3226 SDValue N2 = N->getOperand(2); 3227 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3228 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3229 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3230 EVT VT = N->getValueType(0); 3231 EVT VT0 = N0.getValueType(); 3232 3233 // fold (select C, X, X) -> X 3234 if (N1 == N2) 3235 return N1; 3236 // fold (select true, X, Y) -> X 3237 if (N0C && !N0C->isNullValue()) 3238 return N1; 3239 // fold (select false, X, Y) -> Y 3240 if (N0C && N0C->isNullValue()) 3241 return N2; 3242 // fold (select C, 1, X) -> (or C, X) 3243 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3244 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3245 // fold (select C, 0, 1) -> (xor C, 1) 3246 if (VT.isInteger() && 3247 (VT0 == MVT::i1 || 3248 (VT0.isInteger() && 3249 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3250 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3251 SDValue XORNode; 3252 if (VT == VT0) 3253 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3254 N0, DAG.getConstant(1, VT0)); 3255 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3256 N0, DAG.getConstant(1, VT0)); 3257 AddToWorkList(XORNode.getNode()); 3258 if (VT.bitsGT(VT0)) 3259 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3260 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3261 } 3262 // fold (select C, 0, X) -> (and (not C), X) 3263 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3264 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3265 AddToWorkList(NOTNode.getNode()); 3266 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3267 } 3268 // fold (select C, X, 1) -> (or (not C), X) 3269 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3270 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3271 AddToWorkList(NOTNode.getNode()); 3272 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3273 } 3274 // fold (select C, X, 0) -> (and C, X) 3275 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3276 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3277 // fold (select X, X, Y) -> (or X, Y) 3278 // fold (select X, 1, Y) -> (or X, Y) 3279 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3280 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3281 // fold (select X, Y, X) -> (and X, Y) 3282 // fold (select X, Y, 0) -> (and X, Y) 3283 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3284 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3285 3286 // If we can fold this based on the true/false value, do so. 3287 if (SimplifySelectOps(N, N1, N2)) 3288 return SDValue(N, 0); // Don't revisit N. 3289 3290 // fold selects based on a setcc into other things, such as min/max/abs 3291 if (N0.getOpcode() == ISD::SETCC) { 3292 // FIXME: 3293 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3294 // having to say they don't support SELECT_CC on every type the DAG knows 3295 // about, since there is no way to mark an opcode illegal at all value types 3296 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3297 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3298 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3299 N0.getOperand(0), N0.getOperand(1), 3300 N1, N2, N0.getOperand(2)); 3301 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3302 } 3303 3304 return SDValue(); 3305} 3306 3307SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3308 SDValue N0 = N->getOperand(0); 3309 SDValue N1 = N->getOperand(1); 3310 SDValue N2 = N->getOperand(2); 3311 SDValue N3 = N->getOperand(3); 3312 SDValue N4 = N->getOperand(4); 3313 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3314 3315 // fold select_cc lhs, rhs, x, x, cc -> x 3316 if (N2 == N3) 3317 return N2; 3318 3319 // Determine if the condition we're dealing with is constant 3320 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3321 N0, N1, CC, N->getDebugLoc(), false); 3322 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3323 3324 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3325 if (!SCCC->isNullValue()) 3326 return N2; // cond always true -> true val 3327 else 3328 return N3; // cond always false -> false val 3329 } 3330 3331 // Fold to a simpler select_cc 3332 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3333 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3334 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3335 SCC.getOperand(2)); 3336 3337 // If we can fold this based on the true/false value, do so. 3338 if (SimplifySelectOps(N, N2, N3)) 3339 return SDValue(N, 0); // Don't revisit N. 3340 3341 // fold select_cc into other things, such as min/max/abs 3342 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3343} 3344 3345SDValue DAGCombiner::visitSETCC(SDNode *N) { 3346 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3347 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3348 N->getDebugLoc()); 3349} 3350 3351// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3352// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3353// transformation. Returns true if extension are possible and the above 3354// mentioned transformation is profitable. 3355static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3356 unsigned ExtOpc, 3357 SmallVector<SDNode*, 4> &ExtendNodes, 3358 const TargetLowering &TLI) { 3359 bool HasCopyToRegUses = false; 3360 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3361 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3362 UE = N0.getNode()->use_end(); 3363 UI != UE; ++UI) { 3364 SDNode *User = *UI; 3365 if (User == N) 3366 continue; 3367 if (UI.getUse().getResNo() != N0.getResNo()) 3368 continue; 3369 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3370 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3371 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3372 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3373 // Sign bits will be lost after a zext. 3374 return false; 3375 bool Add = false; 3376 for (unsigned i = 0; i != 2; ++i) { 3377 SDValue UseOp = User->getOperand(i); 3378 if (UseOp == N0) 3379 continue; 3380 if (!isa<ConstantSDNode>(UseOp)) 3381 return false; 3382 Add = true; 3383 } 3384 if (Add) 3385 ExtendNodes.push_back(User); 3386 continue; 3387 } 3388 // If truncates aren't free and there are users we can't 3389 // extend, it isn't worthwhile. 3390 if (!isTruncFree) 3391 return false; 3392 // Remember if this value is live-out. 3393 if (User->getOpcode() == ISD::CopyToReg) 3394 HasCopyToRegUses = true; 3395 } 3396 3397 if (HasCopyToRegUses) { 3398 bool BothLiveOut = false; 3399 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3400 UI != UE; ++UI) { 3401 SDUse &Use = UI.getUse(); 3402 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3403 BothLiveOut = true; 3404 break; 3405 } 3406 } 3407 if (BothLiveOut) 3408 // Both unextended and extended values are live out. There had better be 3409 // good a reason for the transformation. 3410 return ExtendNodes.size(); 3411 } 3412 return true; 3413} 3414 3415SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3416 SDValue N0 = N->getOperand(0); 3417 EVT VT = N->getValueType(0); 3418 3419 // fold (sext c1) -> c1 3420 if (isa<ConstantSDNode>(N0)) 3421 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3422 3423 // fold (sext (sext x)) -> (sext x) 3424 // fold (sext (aext x)) -> (sext x) 3425 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3426 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3427 N0.getOperand(0)); 3428 3429 if (N0.getOpcode() == ISD::TRUNCATE) { 3430 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3431 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3432 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3433 if (NarrowLoad.getNode()) { 3434 if (NarrowLoad.getNode() != N0.getNode()) 3435 CombineTo(N0.getNode(), NarrowLoad); 3436 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3437 } 3438 3439 // See if the value being truncated is already sign extended. If so, just 3440 // eliminate the trunc/sext pair. 3441 SDValue Op = N0.getOperand(0); 3442 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3443 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3444 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3445 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3446 3447 if (OpBits == DestBits) { 3448 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3449 // bits, it is already ready. 3450 if (NumSignBits > DestBits-MidBits) 3451 return Op; 3452 } else if (OpBits < DestBits) { 3453 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3454 // bits, just sext from i32. 3455 if (NumSignBits > OpBits-MidBits) 3456 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3457 } else { 3458 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3459 // bits, just truncate to i32. 3460 if (NumSignBits > OpBits-MidBits) 3461 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3462 } 3463 3464 // fold (sext (truncate x)) -> (sextinreg x). 3465 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3466 N0.getValueType())) { 3467 if (OpBits < DestBits) 3468 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3469 else if (OpBits > DestBits) 3470 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3471 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3472 DAG.getValueType(N0.getValueType())); 3473 } 3474 } 3475 3476 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3477 if (ISD::isNON_EXTLoad(N0.getNode()) && 3478 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3479 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3480 bool DoXform = true; 3481 SmallVector<SDNode*, 4> SetCCs; 3482 if (!N0.hasOneUse()) 3483 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3484 if (DoXform) { 3485 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3486 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3487 LN0->getChain(), 3488 LN0->getBasePtr(), LN0->getSrcValue(), 3489 LN0->getSrcValueOffset(), 3490 N0.getValueType(), 3491 LN0->isVolatile(), LN0->isNonTemporal(), 3492 LN0->getAlignment()); 3493 CombineTo(N, ExtLoad); 3494 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3495 N0.getValueType(), ExtLoad); 3496 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3497 3498 // Extend SetCC uses if necessary. 3499 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3500 SDNode *SetCC = SetCCs[i]; 3501 SmallVector<SDValue, 4> Ops; 3502 3503 for (unsigned j = 0; j != 2; ++j) { 3504 SDValue SOp = SetCC->getOperand(j); 3505 if (SOp == Trunc) 3506 Ops.push_back(ExtLoad); 3507 else 3508 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3509 N->getDebugLoc(), VT, SOp)); 3510 } 3511 3512 Ops.push_back(SetCC->getOperand(2)); 3513 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3514 SetCC->getValueType(0), 3515 &Ops[0], Ops.size())); 3516 } 3517 3518 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3519 } 3520 } 3521 3522 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3523 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3524 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3525 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3526 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3527 EVT MemVT = LN0->getMemoryVT(); 3528 if ((!LegalOperations && !LN0->isVolatile()) || 3529 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3530 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3531 LN0->getChain(), 3532 LN0->getBasePtr(), LN0->getSrcValue(), 3533 LN0->getSrcValueOffset(), MemVT, 3534 LN0->isVolatile(), LN0->isNonTemporal(), 3535 LN0->getAlignment()); 3536 CombineTo(N, ExtLoad); 3537 CombineTo(N0.getNode(), 3538 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3539 N0.getValueType(), ExtLoad), 3540 ExtLoad.getValue(1)); 3541 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3542 } 3543 } 3544 3545 if (N0.getOpcode() == ISD::SETCC) { 3546 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3547 // Only do this before legalize for now. 3548 if (VT.isVector() && !LegalOperations) { 3549 EVT N0VT = N0.getOperand(0).getValueType(); 3550 // We know that the # elements of the results is the same as the 3551 // # elements of the compare (and the # elements of the compare result 3552 // for that matter). Check to see that they are the same size. If so, 3553 // we know that the element size of the sext'd result matches the 3554 // element size of the compare operands. 3555 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3556 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3557 N0.getOperand(1), 3558 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3559 // If the desired elements are smaller or larger than the source 3560 // elements we can use a matching integer vector type and then 3561 // truncate/sign extend 3562 else { 3563 EVT MatchingElementType = 3564 EVT::getIntegerVT(*DAG.getContext(), 3565 N0VT.getScalarType().getSizeInBits()); 3566 EVT MatchingVectorType = 3567 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3568 N0VT.getVectorNumElements()); 3569 SDValue VsetCC = 3570 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3571 N0.getOperand(1), 3572 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3573 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3574 } 3575 } 3576 3577 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3578 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3579 SDValue NegOne = 3580 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3581 SDValue SCC = 3582 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3583 NegOne, DAG.getConstant(0, VT), 3584 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3585 if (SCC.getNode()) return SCC; 3586 if (!LegalOperations || 3587 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3588 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3589 DAG.getSetCC(N->getDebugLoc(), 3590 TLI.getSetCCResultType(VT), 3591 N0.getOperand(0), N0.getOperand(1), 3592 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3593 NegOne, DAG.getConstant(0, VT)); 3594 } 3595 3596 // fold (sext x) -> (zext x) if the sign bit is known zero. 3597 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3598 DAG.SignBitIsZero(N0)) 3599 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3600 3601 return SDValue(); 3602} 3603 3604SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3605 SDValue N0 = N->getOperand(0); 3606 EVT VT = N->getValueType(0); 3607 3608 // fold (zext c1) -> c1 3609 if (isa<ConstantSDNode>(N0)) 3610 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3611 // fold (zext (zext x)) -> (zext x) 3612 // fold (zext (aext x)) -> (zext x) 3613 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3614 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3615 N0.getOperand(0)); 3616 3617 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3618 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3619 if (N0.getOpcode() == ISD::TRUNCATE) { 3620 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3621 if (NarrowLoad.getNode()) { 3622 if (NarrowLoad.getNode() != N0.getNode()) 3623 CombineTo(N0.getNode(), NarrowLoad); 3624 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3625 } 3626 } 3627 3628 // fold (zext (truncate x)) -> (and x, mask) 3629 if (N0.getOpcode() == ISD::TRUNCATE && 3630 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) && 3631 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(), 3632 N0.getValueType()) || 3633 !TLI.isZExtFree(N0.getValueType(), VT))) { 3634 SDValue Op = N0.getOperand(0); 3635 if (Op.getValueType().bitsLT(VT)) { 3636 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3637 } else if (Op.getValueType().bitsGT(VT)) { 3638 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3639 } 3640 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3641 N0.getValueType().getScalarType()); 3642 } 3643 3644 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3645 // if either of the casts is not free. 3646 if (N0.getOpcode() == ISD::AND && 3647 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3648 N0.getOperand(1).getOpcode() == ISD::Constant && 3649 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3650 N0.getValueType()) || 3651 !TLI.isZExtFree(N0.getValueType(), VT))) { 3652 SDValue X = N0.getOperand(0).getOperand(0); 3653 if (X.getValueType().bitsLT(VT)) { 3654 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3655 } else if (X.getValueType().bitsGT(VT)) { 3656 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3657 } 3658 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3659 Mask.zext(VT.getSizeInBits()); 3660 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3661 X, DAG.getConstant(Mask, VT)); 3662 } 3663 3664 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3665 if (ISD::isNON_EXTLoad(N0.getNode()) && 3666 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3667 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3668 bool DoXform = true; 3669 SmallVector<SDNode*, 4> SetCCs; 3670 if (!N0.hasOneUse()) 3671 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3672 if (DoXform) { 3673 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3674 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3675 LN0->getChain(), 3676 LN0->getBasePtr(), LN0->getSrcValue(), 3677 LN0->getSrcValueOffset(), 3678 N0.getValueType(), 3679 LN0->isVolatile(), LN0->isNonTemporal(), 3680 LN0->getAlignment()); 3681 CombineTo(N, ExtLoad); 3682 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3683 N0.getValueType(), ExtLoad); 3684 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3685 3686 // Extend SetCC uses if necessary. 3687 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3688 SDNode *SetCC = SetCCs[i]; 3689 SmallVector<SDValue, 4> Ops; 3690 3691 for (unsigned j = 0; j != 2; ++j) { 3692 SDValue SOp = SetCC->getOperand(j); 3693 if (SOp == Trunc) 3694 Ops.push_back(ExtLoad); 3695 else 3696 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3697 N->getDebugLoc(), VT, SOp)); 3698 } 3699 3700 Ops.push_back(SetCC->getOperand(2)); 3701 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3702 SetCC->getValueType(0), 3703 &Ops[0], Ops.size())); 3704 } 3705 3706 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3707 } 3708 } 3709 3710 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3711 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3712 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3713 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3714 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3715 EVT MemVT = LN0->getMemoryVT(); 3716 if ((!LegalOperations && !LN0->isVolatile()) || 3717 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3718 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3719 LN0->getChain(), 3720 LN0->getBasePtr(), LN0->getSrcValue(), 3721 LN0->getSrcValueOffset(), MemVT, 3722 LN0->isVolatile(), LN0->isNonTemporal(), 3723 LN0->getAlignment()); 3724 CombineTo(N, ExtLoad); 3725 CombineTo(N0.getNode(), 3726 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3727 ExtLoad), 3728 ExtLoad.getValue(1)); 3729 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3730 } 3731 } 3732 3733 if (N0.getOpcode() == ISD::SETCC) { 3734 if (!LegalOperations && VT.isVector()) { 3735 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 3736 // Only do this before legalize for now. 3737 EVT N0VT = N0.getOperand(0).getValueType(); 3738 EVT EltVT = VT.getVectorElementType(); 3739 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 3740 DAG.getConstant(1, EltVT)); 3741 if (VT.getSizeInBits() == N0VT.getSizeInBits()) { 3742 // We know that the # elements of the results is the same as the 3743 // # elements of the compare (and the # elements of the compare result 3744 // for that matter). Check to see that they are the same size. If so, 3745 // we know that the element size of the sext'd result matches the 3746 // element size of the compare operands. 3747 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3748 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3749 N0.getOperand(1), 3750 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3751 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3752 &OneOps[0], OneOps.size())); 3753 } else { 3754 // If the desired elements are smaller or larger than the source 3755 // elements we can use a matching integer vector type and then 3756 // truncate/sign extend 3757 EVT MatchingElementType = 3758 EVT::getIntegerVT(*DAG.getContext(), 3759 N0VT.getScalarType().getSizeInBits()); 3760 EVT MatchingVectorType = 3761 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3762 N0VT.getVectorNumElements()); 3763 SDValue VsetCC = 3764 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3765 N0.getOperand(1), 3766 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3767 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3768 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 3769 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3770 &OneOps[0], OneOps.size())); 3771 } 3772 } 3773 3774 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3775 SDValue SCC = 3776 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3777 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3778 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3779 if (SCC.getNode()) return SCC; 3780 } 3781 3782 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3783 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3784 isa<ConstantSDNode>(N0.getOperand(1)) && 3785 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3786 N0.hasOneUse()) { 3787 if (N0.getOpcode() == ISD::SHL) { 3788 // If the original shl may be shifting out bits, do not perform this 3789 // transformation. 3790 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3791 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3792 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3793 if (ShAmt > KnownZeroBits) 3794 return SDValue(); 3795 } 3796 DebugLoc dl = N->getDebugLoc(); 3797 return DAG.getNode(N0.getOpcode(), dl, VT, 3798 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3799 DAG.getNode(ISD::ZERO_EXTEND, dl, 3800 N0.getOperand(1).getValueType(), 3801 N0.getOperand(1))); 3802 } 3803 3804 return SDValue(); 3805} 3806 3807SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3808 SDValue N0 = N->getOperand(0); 3809 EVT VT = N->getValueType(0); 3810 3811 // fold (aext c1) -> c1 3812 if (isa<ConstantSDNode>(N0)) 3813 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3814 // fold (aext (aext x)) -> (aext x) 3815 // fold (aext (zext x)) -> (zext x) 3816 // fold (aext (sext x)) -> (sext x) 3817 if (N0.getOpcode() == ISD::ANY_EXTEND || 3818 N0.getOpcode() == ISD::ZERO_EXTEND || 3819 N0.getOpcode() == ISD::SIGN_EXTEND) 3820 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3821 3822 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3823 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3824 if (N0.getOpcode() == ISD::TRUNCATE) { 3825 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3826 if (NarrowLoad.getNode()) { 3827 if (NarrowLoad.getNode() != N0.getNode()) 3828 CombineTo(N0.getNode(), NarrowLoad); 3829 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3830 } 3831 } 3832 3833 // fold (aext (truncate x)) 3834 if (N0.getOpcode() == ISD::TRUNCATE) { 3835 SDValue TruncOp = N0.getOperand(0); 3836 if (TruncOp.getValueType() == VT) 3837 return TruncOp; // x iff x size == zext size. 3838 if (TruncOp.getValueType().bitsGT(VT)) 3839 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3840 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3841 } 3842 3843 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3844 // if the trunc is not free. 3845 if (N0.getOpcode() == ISD::AND && 3846 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3847 N0.getOperand(1).getOpcode() == ISD::Constant && 3848 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3849 N0.getValueType())) { 3850 SDValue X = N0.getOperand(0).getOperand(0); 3851 if (X.getValueType().bitsLT(VT)) { 3852 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3853 } else if (X.getValueType().bitsGT(VT)) { 3854 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3855 } 3856 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3857 Mask.zext(VT.getSizeInBits()); 3858 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3859 X, DAG.getConstant(Mask, VT)); 3860 } 3861 3862 // fold (aext (load x)) -> (aext (truncate (extload x))) 3863 if (ISD::isNON_EXTLoad(N0.getNode()) && 3864 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3865 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3866 bool DoXform = true; 3867 SmallVector<SDNode*, 4> SetCCs; 3868 if (!N0.hasOneUse()) 3869 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3870 if (DoXform) { 3871 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3872 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3873 LN0->getChain(), 3874 LN0->getBasePtr(), LN0->getSrcValue(), 3875 LN0->getSrcValueOffset(), 3876 N0.getValueType(), 3877 LN0->isVolatile(), LN0->isNonTemporal(), 3878 LN0->getAlignment()); 3879 CombineTo(N, ExtLoad); 3880 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3881 N0.getValueType(), ExtLoad); 3882 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3883 3884 // Extend SetCC uses if necessary. 3885 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3886 SDNode *SetCC = SetCCs[i]; 3887 SmallVector<SDValue, 4> Ops; 3888 3889 for (unsigned j = 0; j != 2; ++j) { 3890 SDValue SOp = SetCC->getOperand(j); 3891 if (SOp == Trunc) 3892 Ops.push_back(ExtLoad); 3893 else 3894 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3895 N->getDebugLoc(), VT, SOp)); 3896 } 3897 3898 Ops.push_back(SetCC->getOperand(2)); 3899 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3900 SetCC->getValueType(0), 3901 &Ops[0], Ops.size())); 3902 } 3903 3904 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3905 } 3906 } 3907 3908 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3909 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3910 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3911 if (N0.getOpcode() == ISD::LOAD && 3912 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3913 N0.hasOneUse()) { 3914 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3915 EVT MemVT = LN0->getMemoryVT(); 3916 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3917 VT, LN0->getChain(), LN0->getBasePtr(), 3918 LN0->getSrcValue(), 3919 LN0->getSrcValueOffset(), MemVT, 3920 LN0->isVolatile(), LN0->isNonTemporal(), 3921 LN0->getAlignment()); 3922 CombineTo(N, ExtLoad); 3923 CombineTo(N0.getNode(), 3924 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3925 N0.getValueType(), ExtLoad), 3926 ExtLoad.getValue(1)); 3927 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3928 } 3929 3930 if (N0.getOpcode() == ISD::SETCC) { 3931 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 3932 // Only do this before legalize for now. 3933 if (VT.isVector() && !LegalOperations) { 3934 EVT N0VT = N0.getOperand(0).getValueType(); 3935 // We know that the # elements of the results is the same as the 3936 // # elements of the compare (and the # elements of the compare result 3937 // for that matter). Check to see that they are the same size. If so, 3938 // we know that the element size of the sext'd result matches the 3939 // element size of the compare operands. 3940 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3941 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3942 N0.getOperand(1), 3943 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3944 // If the desired elements are smaller or larger than the source 3945 // elements we can use a matching integer vector type and then 3946 // truncate/sign extend 3947 else { 3948 EVT MatchingElementType = 3949 EVT::getIntegerVT(*DAG.getContext(), 3950 N0VT.getScalarType().getSizeInBits()); 3951 EVT MatchingVectorType = 3952 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3953 N0VT.getVectorNumElements()); 3954 SDValue VsetCC = 3955 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3956 N0.getOperand(1), 3957 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3958 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3959 } 3960 } 3961 3962 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3963 SDValue SCC = 3964 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3965 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3966 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3967 if (SCC.getNode()) 3968 return SCC; 3969 } 3970 3971 return SDValue(); 3972} 3973 3974/// GetDemandedBits - See if the specified operand can be simplified with the 3975/// knowledge that only the bits specified by Mask are used. If so, return the 3976/// simpler operand, otherwise return a null SDValue. 3977SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3978 switch (V.getOpcode()) { 3979 default: break; 3980 case ISD::OR: 3981 case ISD::XOR: 3982 // If the LHS or RHS don't contribute bits to the or, drop them. 3983 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3984 return V.getOperand(1); 3985 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3986 return V.getOperand(0); 3987 break; 3988 case ISD::SRL: 3989 // Only look at single-use SRLs. 3990 if (!V.getNode()->hasOneUse()) 3991 break; 3992 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3993 // See if we can recursively simplify the LHS. 3994 unsigned Amt = RHSC->getZExtValue(); 3995 3996 // Watch out for shift count overflow though. 3997 if (Amt >= Mask.getBitWidth()) break; 3998 APInt NewMask = Mask << Amt; 3999 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4000 if (SimplifyLHS.getNode()) 4001 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4002 SimplifyLHS, V.getOperand(1)); 4003 } 4004 } 4005 return SDValue(); 4006} 4007 4008/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4009/// bits and then truncated to a narrower type and where N is a multiple 4010/// of number of bits of the narrower type, transform it to a narrower load 4011/// from address + N / num of bits of new type. If the result is to be 4012/// extended, also fold the extension to form a extending load. 4013SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4014 unsigned Opc = N->getOpcode(); 4015 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4016 SDValue N0 = N->getOperand(0); 4017 EVT VT = N->getValueType(0); 4018 EVT ExtVT = VT; 4019 4020 // This transformation isn't valid for vector loads. 4021 if (VT.isVector()) 4022 return SDValue(); 4023 4024 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4025 // extended to VT. 4026 if (Opc == ISD::SIGN_EXTEND_INREG) { 4027 ExtType = ISD::SEXTLOAD; 4028 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4029 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 4030 return SDValue(); 4031 } 4032 4033 unsigned EVTBits = ExtVT.getSizeInBits(); 4034 unsigned ShAmt = 0; 4035 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 4036 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4037 ShAmt = N01->getZExtValue(); 4038 // Is the shift amount a multiple of size of VT? 4039 if ((ShAmt & (EVTBits-1)) == 0) { 4040 N0 = N0.getOperand(0); 4041 // Is the load width a multiple of size of VT? 4042 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4043 return SDValue(); 4044 } 4045 } 4046 } 4047 4048 // Do not generate loads of non-round integer types since these can 4049 // be expensive (and would be wrong if the type is not byte sized). 4050 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 4051 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits && 4052 // Do not change the width of a volatile load. 4053 !cast<LoadSDNode>(N0)->isVolatile()) { 4054 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4055 EVT PtrType = N0.getOperand(1).getValueType(); 4056 4057 // For big endian targets, we need to adjust the offset to the pointer to 4058 // load the correct bytes. 4059 if (TLI.isBigEndian()) { 4060 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4061 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4062 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4063 } 4064 4065 uint64_t PtrOff = ShAmt / 8; 4066 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4067 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4068 PtrType, LN0->getBasePtr(), 4069 DAG.getConstant(PtrOff, PtrType)); 4070 AddToWorkList(NewPtr.getNode()); 4071 4072 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 4073 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4074 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 4075 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign) 4076 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 4077 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 4078 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4079 NewAlign); 4080 4081 // Replace the old load's chain with the new load's chain. 4082 WorkListRemover DeadNodes(*this); 4083 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4084 &DeadNodes); 4085 4086 // Return the new loaded value. 4087 return Load; 4088 } 4089 4090 return SDValue(); 4091} 4092 4093SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4094 SDValue N0 = N->getOperand(0); 4095 SDValue N1 = N->getOperand(1); 4096 EVT VT = N->getValueType(0); 4097 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4098 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4099 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4100 4101 // fold (sext_in_reg c1) -> c1 4102 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4103 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4104 4105 // If the input is already sign extended, just drop the extension. 4106 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4107 return N0; 4108 4109 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4110 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4111 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4112 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4113 N0.getOperand(0), N1); 4114 } 4115 4116 // fold (sext_in_reg (sext x)) -> (sext x) 4117 // fold (sext_in_reg (aext x)) -> (sext x) 4118 // if x is small enough. 4119 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4120 SDValue N00 = N0.getOperand(0); 4121 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4122 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4123 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4124 } 4125 4126 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4127 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4128 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4129 4130 // fold operands of sext_in_reg based on knowledge that the top bits are not 4131 // demanded. 4132 if (SimplifyDemandedBits(SDValue(N, 0))) 4133 return SDValue(N, 0); 4134 4135 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4136 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4137 SDValue NarrowLoad = ReduceLoadWidth(N); 4138 if (NarrowLoad.getNode()) 4139 return NarrowLoad; 4140 4141 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4142 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4143 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4144 if (N0.getOpcode() == ISD::SRL) { 4145 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4146 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4147 // We can turn this into an SRA iff the input to the SRL is already sign 4148 // extended enough. 4149 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4150 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4151 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4152 N0.getOperand(0), N0.getOperand(1)); 4153 } 4154 } 4155 4156 // fold (sext_inreg (extload x)) -> (sextload x) 4157 if (ISD::isEXTLoad(N0.getNode()) && 4158 ISD::isUNINDEXEDLoad(N0.getNode()) && 4159 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4160 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4161 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4162 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4163 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4164 LN0->getChain(), 4165 LN0->getBasePtr(), LN0->getSrcValue(), 4166 LN0->getSrcValueOffset(), EVT, 4167 LN0->isVolatile(), LN0->isNonTemporal(), 4168 LN0->getAlignment()); 4169 CombineTo(N, ExtLoad); 4170 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4171 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4172 } 4173 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4174 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4175 N0.hasOneUse() && 4176 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4177 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4178 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4179 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4180 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4181 LN0->getChain(), 4182 LN0->getBasePtr(), LN0->getSrcValue(), 4183 LN0->getSrcValueOffset(), EVT, 4184 LN0->isVolatile(), LN0->isNonTemporal(), 4185 LN0->getAlignment()); 4186 CombineTo(N, ExtLoad); 4187 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4188 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4189 } 4190 return SDValue(); 4191} 4192 4193SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4194 SDValue N0 = N->getOperand(0); 4195 EVT VT = N->getValueType(0); 4196 4197 // noop truncate 4198 if (N0.getValueType() == N->getValueType(0)) 4199 return N0; 4200 // fold (truncate c1) -> c1 4201 if (isa<ConstantSDNode>(N0)) 4202 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4203 // fold (truncate (truncate x)) -> (truncate x) 4204 if (N0.getOpcode() == ISD::TRUNCATE) 4205 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4206 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4207 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4208 N0.getOpcode() == ISD::SIGN_EXTEND || 4209 N0.getOpcode() == ISD::ANY_EXTEND) { 4210 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4211 // if the source is smaller than the dest, we still need an extend 4212 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4213 N0.getOperand(0)); 4214 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4215 // if the source is larger than the dest, than we just need the truncate 4216 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4217 else 4218 // if the source and dest are the same type, we can drop both the extend 4219 // and the truncate. 4220 return N0.getOperand(0); 4221 } 4222 4223 // See if we can simplify the input to this truncate through knowledge that 4224 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 4225 // -> trunc y 4226 SDValue Shorter = 4227 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4228 VT.getSizeInBits())); 4229 if (Shorter.getNode()) 4230 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4231 4232 // fold (truncate (load x)) -> (smaller load x) 4233 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4234 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) 4235 return ReduceLoadWidth(N); 4236 return SDValue(); 4237} 4238 4239static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4240 SDValue Elt = N->getOperand(i); 4241 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4242 return Elt.getNode(); 4243 return Elt.getOperand(Elt.getResNo()).getNode(); 4244} 4245 4246/// CombineConsecutiveLoads - build_pair (load, load) -> load 4247/// if load locations are consecutive. 4248SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4249 assert(N->getOpcode() == ISD::BUILD_PAIR); 4250 4251 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4252 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4253 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 4254 return SDValue(); 4255 EVT LD1VT = LD1->getValueType(0); 4256 4257 if (ISD::isNON_EXTLoad(LD2) && 4258 LD2->hasOneUse() && 4259 // If both are volatile this would reduce the number of volatile loads. 4260 // If one is volatile it might be ok, but play conservative and bail out. 4261 !LD1->isVolatile() && 4262 !LD2->isVolatile() && 4263 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4264 unsigned Align = LD1->getAlignment(); 4265 unsigned NewAlign = TLI.getTargetData()-> 4266 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4267 4268 if (NewAlign <= Align && 4269 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4270 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4271 LD1->getBasePtr(), LD1->getSrcValue(), 4272 LD1->getSrcValueOffset(), false, false, Align); 4273 } 4274 4275 return SDValue(); 4276} 4277 4278SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 4279 SDValue N0 = N->getOperand(0); 4280 EVT VT = N->getValueType(0); 4281 4282 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4283 // Only do this before legalize, since afterward the target may be depending 4284 // on the bitconvert. 4285 // First check to see if this is all constant. 4286 if (!LegalTypes && 4287 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4288 VT.isVector()) { 4289 bool isSimple = true; 4290 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4291 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4292 N0.getOperand(i).getOpcode() != ISD::Constant && 4293 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4294 isSimple = false; 4295 break; 4296 } 4297 4298 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4299 assert(!DestEltVT.isVector() && 4300 "Element type of vector ValueType must not be vector!"); 4301 if (isSimple) 4302 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4303 } 4304 4305 // If the input is a constant, let getNode fold it. 4306 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4307 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 4308 if (Res.getNode() != N) { 4309 if (!LegalOperations || 4310 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4311 return Res; 4312 4313 // Folding it resulted in an illegal node, and it's too late to 4314 // do that. Clean up the old node and forego the transformation. 4315 // Ideally this won't happen very often, because instcombine 4316 // and the earlier dagcombine runs (where illegal nodes are 4317 // permitted) should have folded most of them already. 4318 DAG.DeleteNode(Res.getNode()); 4319 } 4320 } 4321 4322 // (conv (conv x, t1), t2) -> (conv x, t2) 4323 if (N0.getOpcode() == ISD::BIT_CONVERT) 4324 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 4325 N0.getOperand(0)); 4326 4327 // fold (conv (load x)) -> (load (conv*)x) 4328 // If the resultant load doesn't need a higher alignment than the original! 4329 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4330 // Do not change the width of a volatile load. 4331 !cast<LoadSDNode>(N0)->isVolatile() && 4332 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4333 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4334 unsigned Align = TLI.getTargetData()-> 4335 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4336 unsigned OrigAlign = LN0->getAlignment(); 4337 4338 if (Align <= OrigAlign) { 4339 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4340 LN0->getBasePtr(), 4341 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4342 LN0->isVolatile(), LN0->isNonTemporal(), 4343 OrigAlign); 4344 AddToWorkList(N); 4345 CombineTo(N0.getNode(), 4346 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4347 N0.getValueType(), Load), 4348 Load.getValue(1)); 4349 return Load; 4350 } 4351 } 4352 4353 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4354 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4355 // This often reduces constant pool loads. 4356 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4357 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4358 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 4359 N0.getOperand(0)); 4360 AddToWorkList(NewConv.getNode()); 4361 4362 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4363 if (N0.getOpcode() == ISD::FNEG) 4364 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4365 NewConv, DAG.getConstant(SignBit, VT)); 4366 assert(N0.getOpcode() == ISD::FABS); 4367 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4368 NewConv, DAG.getConstant(~SignBit, VT)); 4369 } 4370 4371 // fold (bitconvert (fcopysign cst, x)) -> 4372 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4373 // Note that we don't handle (copysign x, cst) because this can always be 4374 // folded to an fneg or fabs. 4375 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4376 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4377 VT.isInteger() && !VT.isVector()) { 4378 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4379 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4380 if (isTypeLegal(IntXVT)) { 4381 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4382 IntXVT, N0.getOperand(1)); 4383 AddToWorkList(X.getNode()); 4384 4385 // If X has a different width than the result/lhs, sext it or truncate it. 4386 unsigned VTWidth = VT.getSizeInBits(); 4387 if (OrigXWidth < VTWidth) { 4388 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4389 AddToWorkList(X.getNode()); 4390 } else if (OrigXWidth > VTWidth) { 4391 // To get the sign bit in the right place, we have to shift it right 4392 // before truncating. 4393 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4394 X.getValueType(), X, 4395 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4396 AddToWorkList(X.getNode()); 4397 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4398 AddToWorkList(X.getNode()); 4399 } 4400 4401 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4402 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4403 X, DAG.getConstant(SignBit, VT)); 4404 AddToWorkList(X.getNode()); 4405 4406 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4407 VT, N0.getOperand(0)); 4408 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4409 Cst, DAG.getConstant(~SignBit, VT)); 4410 AddToWorkList(Cst.getNode()); 4411 4412 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4413 } 4414 } 4415 4416 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4417 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4418 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4419 if (CombineLD.getNode()) 4420 return CombineLD; 4421 } 4422 4423 return SDValue(); 4424} 4425 4426SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4427 EVT VT = N->getValueType(0); 4428 return CombineConsecutiveLoads(N, VT); 4429} 4430 4431/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 4432/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4433/// destination element value type. 4434SDValue DAGCombiner:: 4435ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4436 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4437 4438 // If this is already the right type, we're done. 4439 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4440 4441 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4442 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4443 4444 // If this is a conversion of N elements of one type to N elements of another 4445 // type, convert each element. This handles FP<->INT cases. 4446 if (SrcBitSize == DstBitSize) { 4447 SmallVector<SDValue, 8> Ops; 4448 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4449 SDValue Op = BV->getOperand(i); 4450 // If the vector element type is not legal, the BUILD_VECTOR operands 4451 // are promoted and implicitly truncated. Make that explicit here. 4452 if (Op.getValueType() != SrcEltVT) 4453 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4454 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 4455 DstEltVT, Op)); 4456 AddToWorkList(Ops.back().getNode()); 4457 } 4458 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4459 BV->getValueType(0).getVectorNumElements()); 4460 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4461 &Ops[0], Ops.size()); 4462 } 4463 4464 // Otherwise, we're growing or shrinking the elements. To avoid having to 4465 // handle annoying details of growing/shrinking FP values, we convert them to 4466 // int first. 4467 if (SrcEltVT.isFloatingPoint()) { 4468 // Convert the input float vector to a int vector where the elements are the 4469 // same sizes. 4470 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4471 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4472 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 4473 SrcEltVT = IntVT; 4474 } 4475 4476 // Now we know the input is an integer vector. If the output is a FP type, 4477 // convert to integer first, then to FP of the right size. 4478 if (DstEltVT.isFloatingPoint()) { 4479 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4480 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4481 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4482 4483 // Next, convert to FP elements of the same size. 4484 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4485 } 4486 4487 // Okay, we know the src/dst types are both integers of differing types. 4488 // Handling growing first. 4489 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4490 if (SrcBitSize < DstBitSize) { 4491 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4492 4493 SmallVector<SDValue, 8> Ops; 4494 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4495 i += NumInputsPerOutput) { 4496 bool isLE = TLI.isLittleEndian(); 4497 APInt NewBits = APInt(DstBitSize, 0); 4498 bool EltIsUndef = true; 4499 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4500 // Shift the previously computed bits over. 4501 NewBits <<= SrcBitSize; 4502 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4503 if (Op.getOpcode() == ISD::UNDEF) continue; 4504 EltIsUndef = false; 4505 4506 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4507 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4508 } 4509 4510 if (EltIsUndef) 4511 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4512 else 4513 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4514 } 4515 4516 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4517 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4518 &Ops[0], Ops.size()); 4519 } 4520 4521 // Finally, this must be the case where we are shrinking elements: each input 4522 // turns into multiple outputs. 4523 bool isS2V = ISD::isScalarToVector(BV); 4524 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4525 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4526 NumOutputsPerInput*BV->getNumOperands()); 4527 SmallVector<SDValue, 8> Ops; 4528 4529 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4530 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4531 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4532 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4533 continue; 4534 } 4535 4536 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4537 getAPIntValue()).zextOrTrunc(SrcBitSize); 4538 4539 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4540 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4541 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4542 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4543 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4544 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4545 Ops[0]); 4546 OpVal = OpVal.lshr(DstBitSize); 4547 } 4548 4549 // For big endian targets, swap the order of the pieces of each element. 4550 if (TLI.isBigEndian()) 4551 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4552 } 4553 4554 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4555 &Ops[0], Ops.size()); 4556} 4557 4558SDValue DAGCombiner::visitFADD(SDNode *N) { 4559 SDValue N0 = N->getOperand(0); 4560 SDValue N1 = N->getOperand(1); 4561 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4562 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4563 EVT VT = N->getValueType(0); 4564 4565 // fold vector ops 4566 if (VT.isVector()) { 4567 SDValue FoldedVOp = SimplifyVBinOp(N); 4568 if (FoldedVOp.getNode()) return FoldedVOp; 4569 } 4570 4571 // fold (fadd c1, c2) -> (fadd c1, c2) 4572 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4573 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4574 // canonicalize constant to RHS 4575 if (N0CFP && !N1CFP) 4576 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4577 // fold (fadd A, 0) -> A 4578 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4579 return N0; 4580 // fold (fadd A, (fneg B)) -> (fsub A, B) 4581 if (isNegatibleForFree(N1, LegalOperations) == 2) 4582 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4583 GetNegatedExpression(N1, DAG, LegalOperations)); 4584 // fold (fadd (fneg A), B) -> (fsub B, A) 4585 if (isNegatibleForFree(N0, LegalOperations) == 2) 4586 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4587 GetNegatedExpression(N0, DAG, LegalOperations)); 4588 4589 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4590 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4591 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4592 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4593 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4594 N0.getOperand(1), N1)); 4595 4596 return SDValue(); 4597} 4598 4599SDValue DAGCombiner::visitFSUB(SDNode *N) { 4600 SDValue N0 = N->getOperand(0); 4601 SDValue N1 = N->getOperand(1); 4602 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4603 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4604 EVT VT = N->getValueType(0); 4605 4606 // fold vector ops 4607 if (VT.isVector()) { 4608 SDValue FoldedVOp = SimplifyVBinOp(N); 4609 if (FoldedVOp.getNode()) return FoldedVOp; 4610 } 4611 4612 // fold (fsub c1, c2) -> c1-c2 4613 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4614 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4615 // fold (fsub A, 0) -> A 4616 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4617 return N0; 4618 // fold (fsub 0, B) -> -B 4619 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4620 if (isNegatibleForFree(N1, LegalOperations)) 4621 return GetNegatedExpression(N1, DAG, LegalOperations); 4622 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4623 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4624 } 4625 // fold (fsub A, (fneg B)) -> (fadd A, B) 4626 if (isNegatibleForFree(N1, LegalOperations)) 4627 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4628 GetNegatedExpression(N1, DAG, LegalOperations)); 4629 4630 return SDValue(); 4631} 4632 4633SDValue DAGCombiner::visitFMUL(SDNode *N) { 4634 SDValue N0 = N->getOperand(0); 4635 SDValue N1 = N->getOperand(1); 4636 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4637 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4638 EVT VT = N->getValueType(0); 4639 4640 // fold vector ops 4641 if (VT.isVector()) { 4642 SDValue FoldedVOp = SimplifyVBinOp(N); 4643 if (FoldedVOp.getNode()) return FoldedVOp; 4644 } 4645 4646 // fold (fmul c1, c2) -> c1*c2 4647 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4648 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4649 // canonicalize constant to RHS 4650 if (N0CFP && !N1CFP) 4651 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4652 // fold (fmul A, 0) -> 0 4653 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4654 return N1; 4655 // fold (fmul A, 0) -> 0, vector edition. 4656 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4657 return N1; 4658 // fold (fmul X, 2.0) -> (fadd X, X) 4659 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4660 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4661 // fold (fmul X, -1.0) -> (fneg X) 4662 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4663 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4664 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4665 4666 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4667 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4668 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4669 // Both can be negated for free, check to see if at least one is cheaper 4670 // negated. 4671 if (LHSNeg == 2 || RHSNeg == 2) 4672 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4673 GetNegatedExpression(N0, DAG, LegalOperations), 4674 GetNegatedExpression(N1, DAG, LegalOperations)); 4675 } 4676 } 4677 4678 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4679 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4680 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4681 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4682 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4683 N0.getOperand(1), N1)); 4684 4685 return SDValue(); 4686} 4687 4688SDValue DAGCombiner::visitFDIV(SDNode *N) { 4689 SDValue N0 = N->getOperand(0); 4690 SDValue N1 = N->getOperand(1); 4691 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4692 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4693 EVT VT = N->getValueType(0); 4694 4695 // fold vector ops 4696 if (VT.isVector()) { 4697 SDValue FoldedVOp = SimplifyVBinOp(N); 4698 if (FoldedVOp.getNode()) return FoldedVOp; 4699 } 4700 4701 // fold (fdiv c1, c2) -> c1/c2 4702 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4703 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4704 4705 4706 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4707 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4708 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4709 // Both can be negated for free, check to see if at least one is cheaper 4710 // negated. 4711 if (LHSNeg == 2 || RHSNeg == 2) 4712 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4713 GetNegatedExpression(N0, DAG, LegalOperations), 4714 GetNegatedExpression(N1, DAG, LegalOperations)); 4715 } 4716 } 4717 4718 return SDValue(); 4719} 4720 4721SDValue DAGCombiner::visitFREM(SDNode *N) { 4722 SDValue N0 = N->getOperand(0); 4723 SDValue N1 = N->getOperand(1); 4724 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4725 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4726 EVT VT = N->getValueType(0); 4727 4728 // fold (frem c1, c2) -> fmod(c1,c2) 4729 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4730 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4731 4732 return SDValue(); 4733} 4734 4735SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4736 SDValue N0 = N->getOperand(0); 4737 SDValue N1 = N->getOperand(1); 4738 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4739 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4740 EVT VT = N->getValueType(0); 4741 4742 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4743 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4744 4745 if (N1CFP) { 4746 const APFloat& V = N1CFP->getValueAPF(); 4747 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4748 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4749 if (!V.isNegative()) { 4750 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4751 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4752 } else { 4753 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4754 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4755 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4756 } 4757 } 4758 4759 // copysign(fabs(x), y) -> copysign(x, y) 4760 // copysign(fneg(x), y) -> copysign(x, y) 4761 // copysign(copysign(x,z), y) -> copysign(x, y) 4762 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4763 N0.getOpcode() == ISD::FCOPYSIGN) 4764 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4765 N0.getOperand(0), N1); 4766 4767 // copysign(x, abs(y)) -> abs(x) 4768 if (N1.getOpcode() == ISD::FABS) 4769 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4770 4771 // copysign(x, copysign(y,z)) -> copysign(x, z) 4772 if (N1.getOpcode() == ISD::FCOPYSIGN) 4773 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4774 N0, N1.getOperand(1)); 4775 4776 // copysign(x, fp_extend(y)) -> copysign(x, y) 4777 // copysign(x, fp_round(y)) -> copysign(x, y) 4778 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4779 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4780 N0, N1.getOperand(0)); 4781 4782 return SDValue(); 4783} 4784 4785SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4786 SDValue N0 = N->getOperand(0); 4787 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4788 EVT VT = N->getValueType(0); 4789 EVT OpVT = N0.getValueType(); 4790 4791 // fold (sint_to_fp c1) -> c1fp 4792 if (N0C && OpVT != MVT::ppcf128) 4793 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4794 4795 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4796 // but UINT_TO_FP is legal on this target, try to convert. 4797 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4798 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4799 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4800 if (DAG.SignBitIsZero(N0)) 4801 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4802 } 4803 4804 return SDValue(); 4805} 4806 4807SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4808 SDValue N0 = N->getOperand(0); 4809 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4810 EVT VT = N->getValueType(0); 4811 EVT OpVT = N0.getValueType(); 4812 4813 // fold (uint_to_fp c1) -> c1fp 4814 if (N0C && OpVT != MVT::ppcf128) 4815 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4816 4817 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4818 // but SINT_TO_FP is legal on this target, try to convert. 4819 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4820 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4821 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4822 if (DAG.SignBitIsZero(N0)) 4823 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4824 } 4825 4826 return SDValue(); 4827} 4828 4829SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4830 SDValue N0 = N->getOperand(0); 4831 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4832 EVT VT = N->getValueType(0); 4833 4834 // fold (fp_to_sint c1fp) -> c1 4835 if (N0CFP) 4836 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4837 4838 return SDValue(); 4839} 4840 4841SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4842 SDValue N0 = N->getOperand(0); 4843 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4844 EVT VT = N->getValueType(0); 4845 4846 // fold (fp_to_uint c1fp) -> c1 4847 if (N0CFP && VT != MVT::ppcf128) 4848 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4849 4850 return SDValue(); 4851} 4852 4853SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4854 SDValue N0 = N->getOperand(0); 4855 SDValue N1 = N->getOperand(1); 4856 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4857 EVT VT = N->getValueType(0); 4858 4859 // fold (fp_round c1fp) -> c1fp 4860 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4861 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4862 4863 // fold (fp_round (fp_extend x)) -> x 4864 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4865 return N0.getOperand(0); 4866 4867 // fold (fp_round (fp_round x)) -> (fp_round x) 4868 if (N0.getOpcode() == ISD::FP_ROUND) { 4869 // This is a value preserving truncation if both round's are. 4870 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4871 N0.getNode()->getConstantOperandVal(1) == 1; 4872 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4873 DAG.getIntPtrConstant(IsTrunc)); 4874 } 4875 4876 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4877 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4878 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4879 N0.getOperand(0), N1); 4880 AddToWorkList(Tmp.getNode()); 4881 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4882 Tmp, N0.getOperand(1)); 4883 } 4884 4885 return SDValue(); 4886} 4887 4888SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4889 SDValue N0 = N->getOperand(0); 4890 EVT VT = N->getValueType(0); 4891 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4892 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4893 4894 // fold (fp_round_inreg c1fp) -> c1fp 4895 if (N0CFP && isTypeLegal(EVT)) { 4896 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4897 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4898 } 4899 4900 return SDValue(); 4901} 4902 4903SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4904 SDValue N0 = N->getOperand(0); 4905 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4906 EVT VT = N->getValueType(0); 4907 4908 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4909 if (N->hasOneUse() && 4910 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4911 return SDValue(); 4912 4913 // fold (fp_extend c1fp) -> c1fp 4914 if (N0CFP && VT != MVT::ppcf128) 4915 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4916 4917 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4918 // value of X. 4919 if (N0.getOpcode() == ISD::FP_ROUND 4920 && N0.getNode()->getConstantOperandVal(1) == 1) { 4921 SDValue In = N0.getOperand(0); 4922 if (In.getValueType() == VT) return In; 4923 if (VT.bitsLT(In.getValueType())) 4924 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4925 In, N0.getOperand(1)); 4926 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4927 } 4928 4929 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4930 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4931 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4932 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4933 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4934 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4935 LN0->getChain(), 4936 LN0->getBasePtr(), LN0->getSrcValue(), 4937 LN0->getSrcValueOffset(), 4938 N0.getValueType(), 4939 LN0->isVolatile(), LN0->isNonTemporal(), 4940 LN0->getAlignment()); 4941 CombineTo(N, ExtLoad); 4942 CombineTo(N0.getNode(), 4943 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4944 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4945 ExtLoad.getValue(1)); 4946 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4947 } 4948 4949 return SDValue(); 4950} 4951 4952SDValue DAGCombiner::visitFNEG(SDNode *N) { 4953 SDValue N0 = N->getOperand(0); 4954 EVT VT = N->getValueType(0); 4955 4956 if (isNegatibleForFree(N0, LegalOperations)) 4957 return GetNegatedExpression(N0, DAG, LegalOperations); 4958 4959 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4960 // constant pool values. 4961 if (N0.getOpcode() == ISD::BIT_CONVERT && 4962 !VT.isVector() && 4963 N0.getNode()->hasOneUse() && 4964 N0.getOperand(0).getValueType().isInteger()) { 4965 SDValue Int = N0.getOperand(0); 4966 EVT IntVT = Int.getValueType(); 4967 if (IntVT.isInteger() && !IntVT.isVector()) { 4968 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4969 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4970 AddToWorkList(Int.getNode()); 4971 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4972 VT, Int); 4973 } 4974 } 4975 4976 return SDValue(); 4977} 4978 4979SDValue DAGCombiner::visitFABS(SDNode *N) { 4980 SDValue N0 = N->getOperand(0); 4981 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4982 EVT VT = N->getValueType(0); 4983 4984 // fold (fabs c1) -> fabs(c1) 4985 if (N0CFP && VT != MVT::ppcf128) 4986 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4987 // fold (fabs (fabs x)) -> (fabs x) 4988 if (N0.getOpcode() == ISD::FABS) 4989 return N->getOperand(0); 4990 // fold (fabs (fneg x)) -> (fabs x) 4991 // fold (fabs (fcopysign x, y)) -> (fabs x) 4992 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4993 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4994 4995 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4996 // constant pool values. 4997 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4998 N0.getOperand(0).getValueType().isInteger() && 4999 !N0.getOperand(0).getValueType().isVector()) { 5000 SDValue Int = N0.getOperand(0); 5001 EVT IntVT = Int.getValueType(); 5002 if (IntVT.isInteger() && !IntVT.isVector()) { 5003 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5004 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5005 AddToWorkList(Int.getNode()); 5006 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5007 N->getValueType(0), Int); 5008 } 5009 } 5010 5011 return SDValue(); 5012} 5013 5014SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5015 SDValue Chain = N->getOperand(0); 5016 SDValue N1 = N->getOperand(1); 5017 SDValue N2 = N->getOperand(2); 5018 5019 // If N is a constant we could fold this into a fallthrough or unconditional 5020 // branch. However that doesn't happen very often in normal code, because 5021 // Instcombine/SimplifyCFG should have handled the available opportunities. 5022 // If we did this folding here, it would be necessary to update the 5023 // MachineBasicBlock CFG, which is awkward. 5024 5025 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5026 // on the target. 5027 if (N1.getOpcode() == ISD::SETCC && 5028 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5029 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5030 Chain, N1.getOperand(2), 5031 N1.getOperand(0), N1.getOperand(1), N2); 5032 } 5033 5034 SDNode *Trunc = 0; 5035 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 5036 // Look past truncate. 5037 Trunc = N1.getNode(); 5038 N1 = N1.getOperand(0); 5039 } 5040 5041 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 5042 // Match this pattern so that we can generate simpler code: 5043 // 5044 // %a = ... 5045 // %b = and i32 %a, 2 5046 // %c = srl i32 %b, 1 5047 // brcond i32 %c ... 5048 // 5049 // into 5050 // 5051 // %a = ... 5052 // %b = and i32 %a, 2 5053 // %c = setcc eq %b, 0 5054 // brcond %c ... 5055 // 5056 // This applies only when the AND constant value has one bit set and the 5057 // SRL constant is equal to the log2 of the AND constant. The back-end is 5058 // smart enough to convert the result into a TEST/JMP sequence. 5059 SDValue Op0 = N1.getOperand(0); 5060 SDValue Op1 = N1.getOperand(1); 5061 5062 if (Op0.getOpcode() == ISD::AND && 5063 Op1.getOpcode() == ISD::Constant) { 5064 SDValue AndOp1 = Op0.getOperand(1); 5065 5066 if (AndOp1.getOpcode() == ISD::Constant) { 5067 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5068 5069 if (AndConst.isPowerOf2() && 5070 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5071 SDValue SetCC = 5072 DAG.getSetCC(N->getDebugLoc(), 5073 TLI.getSetCCResultType(Op0.getValueType()), 5074 Op0, DAG.getConstant(0, Op0.getValueType()), 5075 ISD::SETNE); 5076 5077 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5078 MVT::Other, Chain, SetCC, N2); 5079 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5080 // will convert it back to (X & C1) >> C2. 5081 CombineTo(N, NewBRCond, false); 5082 // Truncate is dead. 5083 if (Trunc) { 5084 removeFromWorkList(Trunc); 5085 DAG.DeleteNode(Trunc); 5086 } 5087 // Replace the uses of SRL with SETCC 5088 WorkListRemover DeadNodes(*this); 5089 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5090 removeFromWorkList(N1.getNode()); 5091 DAG.DeleteNode(N1.getNode()); 5092 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5093 } 5094 } 5095 } 5096 } 5097 5098 // Transform br(xor(x, y)) -> br(x != y) 5099 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5100 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5101 SDNode *TheXor = N1.getNode(); 5102 SDValue Op0 = TheXor->getOperand(0); 5103 SDValue Op1 = TheXor->getOperand(1); 5104 if (Op0.getOpcode() == Op1.getOpcode()) { 5105 // Avoid missing important xor optimizations. 5106 SDValue Tmp = visitXOR(TheXor); 5107 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5108 DEBUG(dbgs() << "\nReplacing.8 "; 5109 TheXor->dump(&DAG); 5110 dbgs() << "\nWith: "; 5111 Tmp.getNode()->dump(&DAG); 5112 dbgs() << '\n'); 5113 WorkListRemover DeadNodes(*this); 5114 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5115 removeFromWorkList(TheXor); 5116 DAG.DeleteNode(TheXor); 5117 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5118 MVT::Other, Chain, Tmp, N2); 5119 } 5120 } 5121 5122 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5123 bool Equal = false; 5124 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5125 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5126 Op0.getOpcode() == ISD::XOR) { 5127 TheXor = Op0.getNode(); 5128 Equal = true; 5129 } 5130 5131 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; 5132 5133 EVT SetCCVT = NodeToReplace.getValueType(); 5134 if (LegalTypes) 5135 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5136 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5137 SetCCVT, 5138 Op0, Op1, 5139 Equal ? ISD::SETEQ : ISD::SETNE); 5140 // Replace the uses of XOR with SETCC 5141 WorkListRemover DeadNodes(*this); 5142 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes); 5143 removeFromWorkList(NodeToReplace.getNode()); 5144 DAG.DeleteNode(NodeToReplace.getNode()); 5145 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5146 MVT::Other, Chain, SetCC, N2); 5147 } 5148 } 5149 5150 return SDValue(); 5151} 5152 5153// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5154// 5155SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5156 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5157 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5158 5159 // If N is a constant we could fold this into a fallthrough or unconditional 5160 // branch. However that doesn't happen very often in normal code, because 5161 // Instcombine/SimplifyCFG should have handled the available opportunities. 5162 // If we did this folding here, it would be necessary to update the 5163 // MachineBasicBlock CFG, which is awkward. 5164 5165 // Use SimplifySetCC to simplify SETCC's. 5166 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5167 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5168 false); 5169 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5170 5171 // fold to a simpler setcc 5172 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5173 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5174 N->getOperand(0), Simp.getOperand(2), 5175 Simp.getOperand(0), Simp.getOperand(1), 5176 N->getOperand(4)); 5177 5178 return SDValue(); 5179} 5180 5181/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5182/// pre-indexed load / store when the base pointer is an add or subtract 5183/// and it has other uses besides the load / store. After the 5184/// transformation, the new indexed load / store has effectively folded 5185/// the add / subtract in and all of its other uses are redirected to the 5186/// new load / store. 5187bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5188 if (!LegalOperations) 5189 return false; 5190 5191 bool isLoad = true; 5192 SDValue Ptr; 5193 EVT VT; 5194 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5195 if (LD->isIndexed()) 5196 return false; 5197 VT = LD->getMemoryVT(); 5198 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5199 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5200 return false; 5201 Ptr = LD->getBasePtr(); 5202 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5203 if (ST->isIndexed()) 5204 return false; 5205 VT = ST->getMemoryVT(); 5206 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5207 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5208 return false; 5209 Ptr = ST->getBasePtr(); 5210 isLoad = false; 5211 } else { 5212 return false; 5213 } 5214 5215 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5216 // out. There is no reason to make this a preinc/predec. 5217 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5218 Ptr.getNode()->hasOneUse()) 5219 return false; 5220 5221 // Ask the target to do addressing mode selection. 5222 SDValue BasePtr; 5223 SDValue Offset; 5224 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5225 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5226 return false; 5227 // Don't create a indexed load / store with zero offset. 5228 if (isa<ConstantSDNode>(Offset) && 5229 cast<ConstantSDNode>(Offset)->isNullValue()) 5230 return false; 5231 5232 // Try turning it into a pre-indexed load / store except when: 5233 // 1) The new base ptr is a frame index. 5234 // 2) If N is a store and the new base ptr is either the same as or is a 5235 // predecessor of the value being stored. 5236 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5237 // that would create a cycle. 5238 // 4) All uses are load / store ops that use it as old base ptr. 5239 5240 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5241 // (plus the implicit offset) to a register to preinc anyway. 5242 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5243 return false; 5244 5245 // Check #2. 5246 if (!isLoad) { 5247 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5248 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5249 return false; 5250 } 5251 5252 // Now check for #3 and #4. 5253 bool RealUse = false; 5254 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5255 E = Ptr.getNode()->use_end(); I != E; ++I) { 5256 SDNode *Use = *I; 5257 if (Use == N) 5258 continue; 5259 if (Use->isPredecessorOf(N)) 5260 return false; 5261 5262 if (!((Use->getOpcode() == ISD::LOAD && 5263 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5264 (Use->getOpcode() == ISD::STORE && 5265 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5266 RealUse = true; 5267 } 5268 5269 if (!RealUse) 5270 return false; 5271 5272 SDValue Result; 5273 if (isLoad) 5274 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5275 BasePtr, Offset, AM); 5276 else 5277 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5278 BasePtr, Offset, AM); 5279 ++PreIndexedNodes; 5280 ++NodesCombined; 5281 DEBUG(dbgs() << "\nReplacing.4 "; 5282 N->dump(&DAG); 5283 dbgs() << "\nWith: "; 5284 Result.getNode()->dump(&DAG); 5285 dbgs() << '\n'); 5286 WorkListRemover DeadNodes(*this); 5287 if (isLoad) { 5288 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5289 &DeadNodes); 5290 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5291 &DeadNodes); 5292 } else { 5293 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5294 &DeadNodes); 5295 } 5296 5297 // Finally, since the node is now dead, remove it from the graph. 5298 DAG.DeleteNode(N); 5299 5300 // Replace the uses of Ptr with uses of the updated base value. 5301 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5302 &DeadNodes); 5303 removeFromWorkList(Ptr.getNode()); 5304 DAG.DeleteNode(Ptr.getNode()); 5305 5306 return true; 5307} 5308 5309/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5310/// add / sub of the base pointer node into a post-indexed load / store. 5311/// The transformation folded the add / subtract into the new indexed 5312/// load / store effectively and all of its uses are redirected to the 5313/// new load / store. 5314bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5315 if (!LegalOperations) 5316 return false; 5317 5318 bool isLoad = true; 5319 SDValue Ptr; 5320 EVT VT; 5321 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5322 if (LD->isIndexed()) 5323 return false; 5324 VT = LD->getMemoryVT(); 5325 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5326 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5327 return false; 5328 Ptr = LD->getBasePtr(); 5329 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5330 if (ST->isIndexed()) 5331 return false; 5332 VT = ST->getMemoryVT(); 5333 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5334 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5335 return false; 5336 Ptr = ST->getBasePtr(); 5337 isLoad = false; 5338 } else { 5339 return false; 5340 } 5341 5342 if (Ptr.getNode()->hasOneUse()) 5343 return false; 5344 5345 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5346 E = Ptr.getNode()->use_end(); I != E; ++I) { 5347 SDNode *Op = *I; 5348 if (Op == N || 5349 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5350 continue; 5351 5352 SDValue BasePtr; 5353 SDValue Offset; 5354 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5355 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5356 // Don't create a indexed load / store with zero offset. 5357 if (isa<ConstantSDNode>(Offset) && 5358 cast<ConstantSDNode>(Offset)->isNullValue()) 5359 continue; 5360 5361 // Try turning it into a post-indexed load / store except when 5362 // 1) All uses are load / store ops that use it as base ptr. 5363 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5364 // nor a successor of N. Otherwise, if Op is folded that would 5365 // create a cycle. 5366 5367 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5368 continue; 5369 5370 // Check for #1. 5371 bool TryNext = false; 5372 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5373 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5374 SDNode *Use = *II; 5375 if (Use == Ptr.getNode()) 5376 continue; 5377 5378 // If all the uses are load / store addresses, then don't do the 5379 // transformation. 5380 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5381 bool RealUse = false; 5382 for (SDNode::use_iterator III = Use->use_begin(), 5383 EEE = Use->use_end(); III != EEE; ++III) { 5384 SDNode *UseUse = *III; 5385 if (!((UseUse->getOpcode() == ISD::LOAD && 5386 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5387 (UseUse->getOpcode() == ISD::STORE && 5388 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5389 RealUse = true; 5390 } 5391 5392 if (!RealUse) { 5393 TryNext = true; 5394 break; 5395 } 5396 } 5397 } 5398 5399 if (TryNext) 5400 continue; 5401 5402 // Check for #2 5403 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5404 SDValue Result = isLoad 5405 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5406 BasePtr, Offset, AM) 5407 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5408 BasePtr, Offset, AM); 5409 ++PostIndexedNodes; 5410 ++NodesCombined; 5411 DEBUG(dbgs() << "\nReplacing.5 "; 5412 N->dump(&DAG); 5413 dbgs() << "\nWith: "; 5414 Result.getNode()->dump(&DAG); 5415 dbgs() << '\n'); 5416 WorkListRemover DeadNodes(*this); 5417 if (isLoad) { 5418 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5419 &DeadNodes); 5420 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5421 &DeadNodes); 5422 } else { 5423 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5424 &DeadNodes); 5425 } 5426 5427 // Finally, since the node is now dead, remove it from the graph. 5428 DAG.DeleteNode(N); 5429 5430 // Replace the uses of Use with uses of the updated base value. 5431 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5432 Result.getValue(isLoad ? 1 : 0), 5433 &DeadNodes); 5434 removeFromWorkList(Op); 5435 DAG.DeleteNode(Op); 5436 return true; 5437 } 5438 } 5439 } 5440 5441 return false; 5442} 5443 5444SDValue DAGCombiner::visitLOAD(SDNode *N) { 5445 LoadSDNode *LD = cast<LoadSDNode>(N); 5446 SDValue Chain = LD->getChain(); 5447 SDValue Ptr = LD->getBasePtr(); 5448 5449 // If load is not volatile and there are no uses of the loaded value (and 5450 // the updated indexed value in case of indexed loads), change uses of the 5451 // chain value into uses of the chain input (i.e. delete the dead load). 5452 if (!LD->isVolatile()) { 5453 if (N->getValueType(1) == MVT::Other) { 5454 // Unindexed loads. 5455 if (N->hasNUsesOfValue(0, 0)) { 5456 // It's not safe to use the two value CombineTo variant here. e.g. 5457 // v1, chain2 = load chain1, loc 5458 // v2, chain3 = load chain2, loc 5459 // v3 = add v2, c 5460 // Now we replace use of chain2 with chain1. This makes the second load 5461 // isomorphic to the one we are deleting, and thus makes this load live. 5462 DEBUG(dbgs() << "\nReplacing.6 "; 5463 N->dump(&DAG); 5464 dbgs() << "\nWith chain: "; 5465 Chain.getNode()->dump(&DAG); 5466 dbgs() << "\n"); 5467 WorkListRemover DeadNodes(*this); 5468 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5469 5470 if (N->use_empty()) { 5471 removeFromWorkList(N); 5472 DAG.DeleteNode(N); 5473 } 5474 5475 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5476 } 5477 } else { 5478 // Indexed loads. 5479 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5480 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5481 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5482 DEBUG(dbgs() << "\nReplacing.7 "; 5483 N->dump(&DAG); 5484 dbgs() << "\nWith: "; 5485 Undef.getNode()->dump(&DAG); 5486 dbgs() << " and 2 other values\n"); 5487 WorkListRemover DeadNodes(*this); 5488 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5489 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5490 DAG.getUNDEF(N->getValueType(1)), 5491 &DeadNodes); 5492 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5493 removeFromWorkList(N); 5494 DAG.DeleteNode(N); 5495 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5496 } 5497 } 5498 } 5499 5500 // If this load is directly stored, replace the load value with the stored 5501 // value. 5502 // TODO: Handle store large -> read small portion. 5503 // TODO: Handle TRUNCSTORE/LOADEXT 5504 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5505 !LD->isVolatile()) { 5506 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5507 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5508 if (PrevST->getBasePtr() == Ptr && 5509 PrevST->getValue().getValueType() == N->getValueType(0)) 5510 return CombineTo(N, Chain.getOperand(1), Chain); 5511 } 5512 } 5513 5514 // Try to infer better alignment information than the load already has. 5515 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5516 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5517 if (Align > LD->getAlignment()) 5518 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5519 LD->getValueType(0), 5520 Chain, Ptr, LD->getSrcValue(), 5521 LD->getSrcValueOffset(), LD->getMemoryVT(), 5522 LD->isVolatile(), LD->isNonTemporal(), Align); 5523 } 5524 } 5525 5526 if (CombinerAA) { 5527 // Walk up chain skipping non-aliasing memory nodes. 5528 SDValue BetterChain = FindBetterChain(N, Chain); 5529 5530 // If there is a better chain. 5531 if (Chain != BetterChain) { 5532 SDValue ReplLoad; 5533 5534 // Replace the chain to void dependency. 5535 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5536 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5537 BetterChain, Ptr, 5538 LD->getSrcValue(), LD->getSrcValueOffset(), 5539 LD->isVolatile(), LD->isNonTemporal(), 5540 LD->getAlignment()); 5541 } else { 5542 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5543 LD->getValueType(0), 5544 BetterChain, Ptr, LD->getSrcValue(), 5545 LD->getSrcValueOffset(), 5546 LD->getMemoryVT(), 5547 LD->isVolatile(), 5548 LD->isNonTemporal(), 5549 LD->getAlignment()); 5550 } 5551 5552 // Create token factor to keep old chain connected. 5553 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5554 MVT::Other, Chain, ReplLoad.getValue(1)); 5555 5556 // Make sure the new and old chains are cleaned up. 5557 AddToWorkList(Token.getNode()); 5558 5559 // Replace uses with load result and token factor. Don't add users 5560 // to work list. 5561 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5562 } 5563 } 5564 5565 // Try transforming N to an indexed load. 5566 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5567 return SDValue(N, 0); 5568 5569 return SDValue(); 5570} 5571 5572/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5573/// load is having specific bytes cleared out. If so, return the byte size 5574/// being masked out and the shift amount. 5575static std::pair<unsigned, unsigned> 5576CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5577 std::pair<unsigned, unsigned> Result(0, 0); 5578 5579 // Check for the structure we're looking for. 5580 if (V->getOpcode() != ISD::AND || 5581 !isa<ConstantSDNode>(V->getOperand(1)) || 5582 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5583 return Result; 5584 5585 // Check the chain and pointer. 5586 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5587 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5588 5589 // The store should be chained directly to the load or be an operand of a 5590 // tokenfactor. 5591 if (LD == Chain.getNode()) 5592 ; // ok. 5593 else if (Chain->getOpcode() != ISD::TokenFactor) 5594 return Result; // Fail. 5595 else { 5596 bool isOk = false; 5597 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5598 if (Chain->getOperand(i).getNode() == LD) { 5599 isOk = true; 5600 break; 5601 } 5602 if (!isOk) return Result; 5603 } 5604 5605 // This only handles simple types. 5606 if (V.getValueType() != MVT::i16 && 5607 V.getValueType() != MVT::i32 && 5608 V.getValueType() != MVT::i64) 5609 return Result; 5610 5611 // Check the constant mask. Invert it so that the bits being masked out are 5612 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5613 // follow the sign bit for uniformity. 5614 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5615 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5616 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5617 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5618 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5619 if (NotMaskLZ == 64) return Result; // All zero mask. 5620 5621 // See if we have a continuous run of bits. If so, we have 0*1+0* 5622 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5623 return Result; 5624 5625 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5626 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5627 NotMaskLZ -= 64-V.getValueSizeInBits(); 5628 5629 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5630 switch (MaskedBytes) { 5631 case 1: 5632 case 2: 5633 case 4: break; 5634 default: return Result; // All one mask, or 5-byte mask. 5635 } 5636 5637 // Verify that the first bit starts at a multiple of mask so that the access 5638 // is aligned the same as the access width. 5639 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 5640 5641 Result.first = MaskedBytes; 5642 Result.second = NotMaskTZ/8; 5643 return Result; 5644} 5645 5646 5647/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 5648/// provides a value as specified by MaskInfo. If so, replace the specified 5649/// store with a narrower store of truncated IVal. 5650static SDNode * 5651ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 5652 SDValue IVal, StoreSDNode *St, 5653 DAGCombiner *DC) { 5654 unsigned NumBytes = MaskInfo.first; 5655 unsigned ByteShift = MaskInfo.second; 5656 SelectionDAG &DAG = DC->getDAG(); 5657 5658 // Check to see if IVal is all zeros in the part being masked in by the 'or' 5659 // that uses this. If not, this is not a replacement. 5660 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 5661 ByteShift*8, (ByteShift+NumBytes)*8); 5662 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 5663 5664 // Check that it is legal on the target to do this. It is legal if the new 5665 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 5666 // legalization. 5667 MVT VT = MVT::getIntegerVT(NumBytes*8); 5668 if (!DC->isTypeLegal(VT)) 5669 return 0; 5670 5671 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 5672 // shifted by ByteShift and truncated down to NumBytes. 5673 if (ByteShift) 5674 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 5675 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy())); 5676 5677 // Figure out the offset for the store and the alignment of the access. 5678 unsigned StOffset; 5679 unsigned NewAlign = St->getAlignment(); 5680 5681 if (DAG.getTargetLoweringInfo().isLittleEndian()) 5682 StOffset = ByteShift; 5683 else 5684 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 5685 5686 SDValue Ptr = St->getBasePtr(); 5687 if (StOffset) { 5688 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 5689 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 5690 NewAlign = MinAlign(NewAlign, StOffset); 5691 } 5692 5693 // Truncate down to the new size. 5694 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 5695 5696 ++OpsNarrowed; 5697 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 5698 St->getSrcValue(), St->getSrcValueOffset()+StOffset, 5699 false, false, NewAlign).getNode(); 5700} 5701 5702 5703/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5704/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5705/// of the loaded bits, try narrowing the load and store if it would end up 5706/// being a win for performance or code size. 5707SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5708 StoreSDNode *ST = cast<StoreSDNode>(N); 5709 if (ST->isVolatile()) 5710 return SDValue(); 5711 5712 SDValue Chain = ST->getChain(); 5713 SDValue Value = ST->getValue(); 5714 SDValue Ptr = ST->getBasePtr(); 5715 EVT VT = Value.getValueType(); 5716 5717 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5718 return SDValue(); 5719 5720 unsigned Opc = Value.getOpcode(); 5721 5722 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 5723 // is a byte mask indicating a consecutive number of bytes, check to see if 5724 // Y is known to provide just those bytes. If so, we try to replace the 5725 // load + replace + store sequence with a single (narrower) store, which makes 5726 // the load dead. 5727 if (Opc == ISD::OR) { 5728 std::pair<unsigned, unsigned> MaskedLoad; 5729 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 5730 if (MaskedLoad.first) 5731 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5732 Value.getOperand(1), ST,this)) 5733 return SDValue(NewST, 0); 5734 5735 // Or is commutative, so try swapping X and Y. 5736 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 5737 if (MaskedLoad.first) 5738 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5739 Value.getOperand(0), ST,this)) 5740 return SDValue(NewST, 0); 5741 } 5742 5743 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5744 Value.getOperand(1).getOpcode() != ISD::Constant) 5745 return SDValue(); 5746 5747 SDValue N0 = Value.getOperand(0); 5748 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5749 LoadSDNode *LD = cast<LoadSDNode>(N0); 5750 if (LD->getBasePtr() != Ptr) 5751 return SDValue(); 5752 5753 // Find the type to narrow it the load / op / store to. 5754 SDValue N1 = Value.getOperand(1); 5755 unsigned BitWidth = N1.getValueSizeInBits(); 5756 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5757 if (Opc == ISD::AND) 5758 Imm ^= APInt::getAllOnesValue(BitWidth); 5759 if (Imm == 0 || Imm.isAllOnesValue()) 5760 return SDValue(); 5761 unsigned ShAmt = Imm.countTrailingZeros(); 5762 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5763 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5764 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5765 while (NewBW < BitWidth && 5766 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5767 TLI.isNarrowingProfitable(VT, NewVT))) { 5768 NewBW = NextPowerOf2(NewBW); 5769 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5770 } 5771 if (NewBW >= BitWidth) 5772 return SDValue(); 5773 5774 // If the lsb changed does not start at the type bitwidth boundary, 5775 // start at the previous one. 5776 if (ShAmt % NewBW) 5777 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5778 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5779 if ((Imm & Mask) == Imm) { 5780 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5781 if (Opc == ISD::AND) 5782 NewImm ^= APInt::getAllOnesValue(NewBW); 5783 uint64_t PtrOff = ShAmt / 8; 5784 // For big endian targets, we need to adjust the offset to the pointer to 5785 // load the correct bytes. 5786 if (TLI.isBigEndian()) 5787 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5788 5789 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5790 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 5791 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 5792 return SDValue(); 5793 5794 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5795 Ptr.getValueType(), Ptr, 5796 DAG.getConstant(PtrOff, Ptr.getValueType())); 5797 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5798 LD->getChain(), NewPtr, 5799 LD->getSrcValue(), LD->getSrcValueOffset(), 5800 LD->isVolatile(), LD->isNonTemporal(), 5801 NewAlign); 5802 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5803 DAG.getConstant(NewImm, NewVT)); 5804 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5805 NewVal, NewPtr, 5806 ST->getSrcValue(), ST->getSrcValueOffset(), 5807 false, false, NewAlign); 5808 5809 AddToWorkList(NewPtr.getNode()); 5810 AddToWorkList(NewLD.getNode()); 5811 AddToWorkList(NewVal.getNode()); 5812 WorkListRemover DeadNodes(*this); 5813 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5814 &DeadNodes); 5815 ++OpsNarrowed; 5816 return NewST; 5817 } 5818 } 5819 5820 return SDValue(); 5821} 5822 5823SDValue DAGCombiner::visitSTORE(SDNode *N) { 5824 StoreSDNode *ST = cast<StoreSDNode>(N); 5825 SDValue Chain = ST->getChain(); 5826 SDValue Value = ST->getValue(); 5827 SDValue Ptr = ST->getBasePtr(); 5828 5829 // If this is a store of a bit convert, store the input value if the 5830 // resultant store does not need a higher alignment than the original. 5831 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5832 ST->isUnindexed()) { 5833 unsigned OrigAlign = ST->getAlignment(); 5834 EVT SVT = Value.getOperand(0).getValueType(); 5835 unsigned Align = TLI.getTargetData()-> 5836 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5837 if (Align <= OrigAlign && 5838 ((!LegalOperations && !ST->isVolatile()) || 5839 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5840 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5841 Ptr, ST->getSrcValue(), 5842 ST->getSrcValueOffset(), ST->isVolatile(), 5843 ST->isNonTemporal(), OrigAlign); 5844 } 5845 5846 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5847 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5848 // NOTE: If the original store is volatile, this transform must not increase 5849 // the number of stores. For example, on x86-32 an f64 can be stored in one 5850 // processor operation but an i64 (which is not legal) requires two. So the 5851 // transform should not be done in this case. 5852 if (Value.getOpcode() != ISD::TargetConstantFP) { 5853 SDValue Tmp; 5854 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5855 default: llvm_unreachable("Unknown FP type"); 5856 case MVT::f80: // We don't do this for these yet. 5857 case MVT::f128: 5858 case MVT::ppcf128: 5859 break; 5860 case MVT::f32: 5861 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 5862 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5863 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5864 bitcastToAPInt().getZExtValue(), MVT::i32); 5865 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5866 Ptr, ST->getSrcValue(), 5867 ST->getSrcValueOffset(), ST->isVolatile(), 5868 ST->isNonTemporal(), ST->getAlignment()); 5869 } 5870 break; 5871 case MVT::f64: 5872 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 5873 !ST->isVolatile()) || 5874 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5875 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5876 getZExtValue(), MVT::i64); 5877 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5878 Ptr, ST->getSrcValue(), 5879 ST->getSrcValueOffset(), ST->isVolatile(), 5880 ST->isNonTemporal(), ST->getAlignment()); 5881 } else if (!ST->isVolatile() && 5882 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5883 // Many FP stores are not made apparent until after legalize, e.g. for 5884 // argument passing. Since this is so common, custom legalize the 5885 // 64-bit integer store into two 32-bit stores. 5886 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5887 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5888 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5889 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5890 5891 int SVOffset = ST->getSrcValueOffset(); 5892 unsigned Alignment = ST->getAlignment(); 5893 bool isVolatile = ST->isVolatile(); 5894 bool isNonTemporal = ST->isNonTemporal(); 5895 5896 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5897 Ptr, ST->getSrcValue(), 5898 ST->getSrcValueOffset(), 5899 isVolatile, isNonTemporal, 5900 ST->getAlignment()); 5901 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5902 DAG.getConstant(4, Ptr.getValueType())); 5903 SVOffset += 4; 5904 Alignment = MinAlign(Alignment, 4U); 5905 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5906 Ptr, ST->getSrcValue(), 5907 SVOffset, isVolatile, isNonTemporal, 5908 Alignment); 5909 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5910 St0, St1); 5911 } 5912 5913 break; 5914 } 5915 } 5916 } 5917 5918 // Try to infer better alignment information than the store already has. 5919 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5920 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5921 if (Align > ST->getAlignment()) 5922 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5923 Ptr, ST->getSrcValue(), 5924 ST->getSrcValueOffset(), ST->getMemoryVT(), 5925 ST->isVolatile(), ST->isNonTemporal(), Align); 5926 } 5927 } 5928 5929 if (CombinerAA) { 5930 // Walk up chain skipping non-aliasing memory nodes. 5931 SDValue BetterChain = FindBetterChain(N, Chain); 5932 5933 // If there is a better chain. 5934 if (Chain != BetterChain) { 5935 SDValue ReplStore; 5936 5937 // Replace the chain to avoid dependency. 5938 if (ST->isTruncatingStore()) { 5939 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5940 ST->getSrcValue(),ST->getSrcValueOffset(), 5941 ST->getMemoryVT(), ST->isVolatile(), 5942 ST->isNonTemporal(), ST->getAlignment()); 5943 } else { 5944 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5945 ST->getSrcValue(), ST->getSrcValueOffset(), 5946 ST->isVolatile(), ST->isNonTemporal(), 5947 ST->getAlignment()); 5948 } 5949 5950 // Create token to keep both nodes around. 5951 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5952 MVT::Other, Chain, ReplStore); 5953 5954 // Make sure the new and old chains are cleaned up. 5955 AddToWorkList(Token.getNode()); 5956 5957 // Don't add users to work list. 5958 return CombineTo(N, Token, false); 5959 } 5960 } 5961 5962 // Try transforming N to an indexed store. 5963 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5964 return SDValue(N, 0); 5965 5966 // FIXME: is there such a thing as a truncating indexed store? 5967 if (ST->isTruncatingStore() && ST->isUnindexed() && 5968 Value.getValueType().isInteger()) { 5969 // See if we can simplify the input to this truncstore with knowledge that 5970 // only the low bits are being used. For example: 5971 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5972 SDValue Shorter = 5973 GetDemandedBits(Value, 5974 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5975 ST->getMemoryVT().getSizeInBits())); 5976 AddToWorkList(Value.getNode()); 5977 if (Shorter.getNode()) 5978 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5979 Ptr, ST->getSrcValue(), 5980 ST->getSrcValueOffset(), ST->getMemoryVT(), 5981 ST->isVolatile(), ST->isNonTemporal(), 5982 ST->getAlignment()); 5983 5984 // Otherwise, see if we can simplify the operation with 5985 // SimplifyDemandedBits, which only works if the value has a single use. 5986 if (SimplifyDemandedBits(Value, 5987 APInt::getLowBitsSet( 5988 Value.getValueType().getScalarType().getSizeInBits(), 5989 ST->getMemoryVT().getScalarType().getSizeInBits()))) 5990 return SDValue(N, 0); 5991 } 5992 5993 // If this is a load followed by a store to the same location, then the store 5994 // is dead/noop. 5995 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5996 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5997 ST->isUnindexed() && !ST->isVolatile() && 5998 // There can't be any side effects between the load and store, such as 5999 // a call or store. 6000 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6001 // The store is dead, remove it. 6002 return Chain; 6003 } 6004 } 6005 6006 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6007 // truncating store. We can do this even if this is already a truncstore. 6008 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6009 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6010 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6011 ST->getMemoryVT())) { 6012 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6013 Ptr, ST->getSrcValue(), 6014 ST->getSrcValueOffset(), ST->getMemoryVT(), 6015 ST->isVolatile(), ST->isNonTemporal(), 6016 ST->getAlignment()); 6017 } 6018 6019 return ReduceLoadOpStoreWidth(N); 6020} 6021 6022SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6023 SDValue InVec = N->getOperand(0); 6024 SDValue InVal = N->getOperand(1); 6025 SDValue EltNo = N->getOperand(2); 6026 6027 // If the inserted element is an UNDEF, just use the input vector. 6028 if (InVal.getOpcode() == ISD::UNDEF) 6029 return InVec; 6030 6031 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6032 // vector with the inserted element. 6033 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6034 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6035 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6036 InVec.getNode()->op_end()); 6037 if (Elt < Ops.size()) 6038 Ops[Elt] = InVal; 6039 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6040 InVec.getValueType(), &Ops[0], Ops.size()); 6041 } 6042 // If the invec is an UNDEF and if EltNo is a constant, create a new 6043 // BUILD_VECTOR with undef elements and the inserted element. 6044 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 6045 isa<ConstantSDNode>(EltNo)) { 6046 EVT VT = InVec.getValueType(); 6047 EVT EltVT = VT.getVectorElementType(); 6048 unsigned NElts = VT.getVectorNumElements(); 6049 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6050 6051 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6052 if (Elt < Ops.size()) 6053 Ops[Elt] = InVal; 6054 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6055 InVec.getValueType(), &Ops[0], Ops.size()); 6056 } 6057 return SDValue(); 6058} 6059 6060SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6061 // (vextract (scalar_to_vector val, 0) -> val 6062 SDValue InVec = N->getOperand(0); 6063 6064 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6065 // Check if the result type doesn't match the inserted element type. A 6066 // SCALAR_TO_VECTOR may truncate the inserted element and the 6067 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6068 EVT EltVT = InVec.getValueType().getVectorElementType(); 6069 SDValue InOp = InVec.getOperand(0); 6070 EVT NVT = N->getValueType(0); 6071 if (InOp.getValueType() != NVT) { 6072 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6073 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6074 } 6075 return InOp; 6076 } 6077 6078 // Perform only after legalization to ensure build_vector / vector_shuffle 6079 // optimizations have already been done. 6080 if (!LegalOperations) return SDValue(); 6081 6082 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6083 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6084 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6085 SDValue EltNo = N->getOperand(1); 6086 6087 if (isa<ConstantSDNode>(EltNo)) { 6088 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6089 bool NewLoad = false; 6090 bool BCNumEltsChanged = false; 6091 EVT VT = InVec.getValueType(); 6092 EVT ExtVT = VT.getVectorElementType(); 6093 EVT LVT = ExtVT; 6094 6095 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 6096 EVT BCVT = InVec.getOperand(0).getValueType(); 6097 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6098 return SDValue(); 6099 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6100 BCNumEltsChanged = true; 6101 InVec = InVec.getOperand(0); 6102 ExtVT = BCVT.getVectorElementType(); 6103 NewLoad = true; 6104 } 6105 6106 LoadSDNode *LN0 = NULL; 6107 const ShuffleVectorSDNode *SVN = NULL; 6108 if (ISD::isNormalLoad(InVec.getNode())) { 6109 LN0 = cast<LoadSDNode>(InVec); 6110 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6111 InVec.getOperand(0).getValueType() == ExtVT && 6112 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6113 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6114 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6115 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6116 // => 6117 // (load $addr+1*size) 6118 6119 // If the bit convert changed the number of elements, it is unsafe 6120 // to examine the mask. 6121 if (BCNumEltsChanged) 6122 return SDValue(); 6123 6124 // Select the input vector, guarding against out of range extract vector. 6125 unsigned NumElems = VT.getVectorNumElements(); 6126 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 6127 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6128 6129 if (InVec.getOpcode() == ISD::BIT_CONVERT) 6130 InVec = InVec.getOperand(0); 6131 if (ISD::isNormalLoad(InVec.getNode())) { 6132 LN0 = cast<LoadSDNode>(InVec); 6133 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6134 } 6135 } 6136 6137 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 6138 return SDValue(); 6139 6140 unsigned Align = LN0->getAlignment(); 6141 if (NewLoad) { 6142 // Check the resultant load doesn't need a higher alignment than the 6143 // original load. 6144 unsigned NewAlign = 6145 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6146 6147 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6148 return SDValue(); 6149 6150 Align = NewAlign; 6151 } 6152 6153 SDValue NewPtr = LN0->getBasePtr(); 6154 if (Elt) { 6155 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 6156 EVT PtrType = NewPtr.getValueType(); 6157 if (TLI.isBigEndian()) 6158 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6159 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6160 DAG.getConstant(PtrOff, PtrType)); 6161 } 6162 6163 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6164 LN0->getSrcValue(), LN0->getSrcValueOffset(), 6165 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6166 } 6167 6168 return SDValue(); 6169} 6170 6171SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6172 unsigned NumInScalars = N->getNumOperands(); 6173 EVT VT = N->getValueType(0); 6174 6175 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6176 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6177 // at most two distinct vectors, turn this into a shuffle node. 6178 SDValue VecIn1, VecIn2; 6179 for (unsigned i = 0; i != NumInScalars; ++i) { 6180 // Ignore undef inputs. 6181 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6182 6183 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6184 // constant index, bail out. 6185 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6186 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6187 VecIn1 = VecIn2 = SDValue(0, 0); 6188 break; 6189 } 6190 6191 // If the input vector type disagrees with the result of the build_vector, 6192 // we can't make a shuffle. 6193 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6194 if (ExtractedFromVec.getValueType() != VT) { 6195 VecIn1 = VecIn2 = SDValue(0, 0); 6196 break; 6197 } 6198 6199 // Otherwise, remember this. We allow up to two distinct input vectors. 6200 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6201 continue; 6202 6203 if (VecIn1.getNode() == 0) { 6204 VecIn1 = ExtractedFromVec; 6205 } else if (VecIn2.getNode() == 0) { 6206 VecIn2 = ExtractedFromVec; 6207 } else { 6208 // Too many inputs. 6209 VecIn1 = VecIn2 = SDValue(0, 0); 6210 break; 6211 } 6212 } 6213 6214 // If everything is good, we can make a shuffle operation. 6215 if (VecIn1.getNode()) { 6216 SmallVector<int, 8> Mask; 6217 for (unsigned i = 0; i != NumInScalars; ++i) { 6218 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6219 Mask.push_back(-1); 6220 continue; 6221 } 6222 6223 // If extracting from the first vector, just use the index directly. 6224 SDValue Extract = N->getOperand(i); 6225 SDValue ExtVal = Extract.getOperand(1); 6226 if (Extract.getOperand(0) == VecIn1) { 6227 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6228 if (ExtIndex > VT.getVectorNumElements()) 6229 return SDValue(); 6230 6231 Mask.push_back(ExtIndex); 6232 continue; 6233 } 6234 6235 // Otherwise, use InIdx + VecSize 6236 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6237 Mask.push_back(Idx+NumInScalars); 6238 } 6239 6240 // Add count and size info. 6241 if (!isTypeLegal(VT)) 6242 return SDValue(); 6243 6244 // Return the new VECTOR_SHUFFLE node. 6245 SDValue Ops[2]; 6246 Ops[0] = VecIn1; 6247 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6248 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6249 } 6250 6251 return SDValue(); 6252} 6253 6254SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6255 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6256 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6257 // inputs come from at most two distinct vectors, turn this into a shuffle 6258 // node. 6259 6260 // If we only have one input vector, we don't need to do any concatenation. 6261 if (N->getNumOperands() == 1) 6262 return N->getOperand(0); 6263 6264 return SDValue(); 6265} 6266 6267SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6268 return SDValue(); 6269 6270 EVT VT = N->getValueType(0); 6271 unsigned NumElts = VT.getVectorNumElements(); 6272 6273 SDValue N0 = N->getOperand(0); 6274 6275 assert(N0.getValueType().getVectorNumElements() == NumElts && 6276 "Vector shuffle must be normalized in DAG"); 6277 6278 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6279 6280 // If it is a splat, check if the argument vector is a build_vector with 6281 // all scalar elements the same. 6282 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 6283 SDNode *V = N0.getNode(); 6284 6285 6286 // If this is a bit convert that changes the element type of the vector but 6287 // not the number of vector elements, look through it. Be careful not to 6288 // look though conversions that change things like v4f32 to v2f64. 6289 if (V->getOpcode() == ISD::BIT_CONVERT) { 6290 SDValue ConvInput = V->getOperand(0); 6291 if (ConvInput.getValueType().isVector() && 6292 ConvInput.getValueType().getVectorNumElements() == NumElts) 6293 V = ConvInput.getNode(); 6294 } 6295 6296 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6297 unsigned NumElems = V->getNumOperands(); 6298 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 6299 if (NumElems > BaseIdx) { 6300 SDValue Base; 6301 bool AllSame = true; 6302 for (unsigned i = 0; i != NumElems; ++i) { 6303 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6304 Base = V->getOperand(i); 6305 break; 6306 } 6307 } 6308 // Splat of <u, u, u, u>, return <u, u, u, u> 6309 if (!Base.getNode()) 6310 return N0; 6311 for (unsigned i = 0; i != NumElems; ++i) { 6312 if (V->getOperand(i) != Base) { 6313 AllSame = false; 6314 break; 6315 } 6316 } 6317 // Splat of <x, x, x, x>, return <x, x, x, x> 6318 if (AllSame) 6319 return N0; 6320 } 6321 } 6322 } 6323 return SDValue(); 6324} 6325 6326/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6327/// an AND to a vector_shuffle with the destination vector and a zero vector. 6328/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6329/// vector_shuffle V, Zero, <0, 4, 2, 4> 6330SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6331 EVT VT = N->getValueType(0); 6332 DebugLoc dl = N->getDebugLoc(); 6333 SDValue LHS = N->getOperand(0); 6334 SDValue RHS = N->getOperand(1); 6335 if (N->getOpcode() == ISD::AND) { 6336 if (RHS.getOpcode() == ISD::BIT_CONVERT) 6337 RHS = RHS.getOperand(0); 6338 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6339 SmallVector<int, 8> Indices; 6340 unsigned NumElts = RHS.getNumOperands(); 6341 for (unsigned i = 0; i != NumElts; ++i) { 6342 SDValue Elt = RHS.getOperand(i); 6343 if (!isa<ConstantSDNode>(Elt)) 6344 return SDValue(); 6345 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6346 Indices.push_back(i); 6347 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6348 Indices.push_back(NumElts); 6349 else 6350 return SDValue(); 6351 } 6352 6353 // Let's see if the target supports this vector_shuffle. 6354 EVT RVT = RHS.getValueType(); 6355 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6356 return SDValue(); 6357 6358 // Return the new VECTOR_SHUFFLE node. 6359 EVT EltVT = RVT.getVectorElementType(); 6360 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6361 DAG.getConstant(0, EltVT)); 6362 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6363 RVT, &ZeroOps[0], ZeroOps.size()); 6364 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 6365 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6366 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 6367 } 6368 } 6369 6370 return SDValue(); 6371} 6372 6373/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6374SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6375 // After legalize, the target may be depending on adds and other 6376 // binary ops to provide legal ways to construct constants or other 6377 // things. Simplifying them may result in a loss of legality. 6378 if (LegalOperations) return SDValue(); 6379 6380 EVT VT = N->getValueType(0); 6381 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 6382 6383 EVT EltType = VT.getVectorElementType(); 6384 SDValue LHS = N->getOperand(0); 6385 SDValue RHS = N->getOperand(1); 6386 SDValue Shuffle = XformToShuffleWithZero(N); 6387 if (Shuffle.getNode()) return Shuffle; 6388 6389 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6390 // this operation. 6391 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6392 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6393 SmallVector<SDValue, 8> Ops; 6394 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6395 SDValue LHSOp = LHS.getOperand(i); 6396 SDValue RHSOp = RHS.getOperand(i); 6397 // If these two elements can't be folded, bail out. 6398 if ((LHSOp.getOpcode() != ISD::UNDEF && 6399 LHSOp.getOpcode() != ISD::Constant && 6400 LHSOp.getOpcode() != ISD::ConstantFP) || 6401 (RHSOp.getOpcode() != ISD::UNDEF && 6402 RHSOp.getOpcode() != ISD::Constant && 6403 RHSOp.getOpcode() != ISD::ConstantFP)) 6404 break; 6405 6406 // Can't fold divide by zero. 6407 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6408 N->getOpcode() == ISD::FDIV) { 6409 if ((RHSOp.getOpcode() == ISD::Constant && 6410 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6411 (RHSOp.getOpcode() == ISD::ConstantFP && 6412 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6413 break; 6414 } 6415 6416 // If the vector element type is not legal, the BUILD_VECTOR operands 6417 // are promoted and implicitly truncated. Make that explicit here. 6418 if (LHSOp.getValueType() != EltType) 6419 LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp); 6420 if (RHSOp.getValueType() != EltType) 6421 RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp); 6422 6423 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType, 6424 LHSOp, RHSOp); 6425 if (FoldOp.getOpcode() != ISD::UNDEF && 6426 FoldOp.getOpcode() != ISD::Constant && 6427 FoldOp.getOpcode() != ISD::ConstantFP) 6428 break; 6429 Ops.push_back(FoldOp); 6430 AddToWorkList(FoldOp.getNode()); 6431 } 6432 6433 if (Ops.size() == LHS.getNumOperands()) { 6434 EVT VT = LHS.getValueType(); 6435 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 6436 &Ops[0], Ops.size()); 6437 } 6438 } 6439 6440 return SDValue(); 6441} 6442 6443SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6444 SDValue N1, SDValue N2){ 6445 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6446 6447 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6448 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6449 6450 // If we got a simplified select_cc node back from SimplifySelectCC, then 6451 // break it down into a new SETCC node, and a new SELECT node, and then return 6452 // the SELECT node, since we were called with a SELECT node. 6453 if (SCC.getNode()) { 6454 // Check to see if we got a select_cc back (to turn into setcc/select). 6455 // Otherwise, just return whatever node we got back, like fabs. 6456 if (SCC.getOpcode() == ISD::SELECT_CC) { 6457 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6458 N0.getValueType(), 6459 SCC.getOperand(0), SCC.getOperand(1), 6460 SCC.getOperand(4)); 6461 AddToWorkList(SETCC.getNode()); 6462 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6463 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6464 } 6465 6466 return SCC; 6467 } 6468 return SDValue(); 6469} 6470 6471/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6472/// are the two values being selected between, see if we can simplify the 6473/// select. Callers of this should assume that TheSelect is deleted if this 6474/// returns true. As such, they should return the appropriate thing (e.g. the 6475/// node) back to the top-level of the DAG combiner loop to avoid it being 6476/// looked at. 6477bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6478 SDValue RHS) { 6479 6480 // If this is a select from two identical things, try to pull the operation 6481 // through the select. 6482 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 6483 // If this is a load and the token chain is identical, replace the select 6484 // of two loads with a load through a select of the address to load from. 6485 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6486 // constants have been dropped into the constant pool. 6487 if (LHS.getOpcode() == ISD::LOAD && 6488 // Do not let this transformation reduce the number of volatile loads. 6489 !cast<LoadSDNode>(LHS)->isVolatile() && 6490 !cast<LoadSDNode>(RHS)->isVolatile() && 6491 // Token chains must be identical. 6492 LHS.getOperand(0) == RHS.getOperand(0)) { 6493 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6494 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6495 6496 // If this is an EXTLOAD, the VT's must match. 6497 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 6498 // FIXME: this discards src value information. This is 6499 // over-conservative. It would be beneficial to be able to remember 6500 // both potential memory locations. Since we are discarding 6501 // src value info, don't do the transformation if the memory 6502 // locations are not in the default address space. 6503 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0; 6504 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) { 6505 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType())) 6506 LLDAddrSpace = PT->getAddressSpace(); 6507 } 6508 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) { 6509 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType())) 6510 RLDAddrSpace = PT->getAddressSpace(); 6511 } 6512 SDValue Addr; 6513 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) { 6514 if (TheSelect->getOpcode() == ISD::SELECT) { 6515 // Check that the condition doesn't reach either load. If so, folding 6516 // this will induce a cycle into the DAG. 6517 if ((!LLD->hasAnyUseOfValue(1) || 6518 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 6519 (!RLD->hasAnyUseOfValue(1) || 6520 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 6521 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 6522 LLD->getBasePtr().getValueType(), 6523 TheSelect->getOperand(0), LLD->getBasePtr(), 6524 RLD->getBasePtr()); 6525 } 6526 } else { 6527 // Check that the condition doesn't reach either load. If so, folding 6528 // this will induce a cycle into the DAG. 6529 if ((!LLD->hasAnyUseOfValue(1) || 6530 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 6531 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 6532 (!RLD->hasAnyUseOfValue(1) || 6533 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 6534 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 6535 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 6536 LLD->getBasePtr().getValueType(), 6537 TheSelect->getOperand(0), 6538 TheSelect->getOperand(1), 6539 LLD->getBasePtr(), RLD->getBasePtr(), 6540 TheSelect->getOperand(4)); 6541 } 6542 } 6543 } 6544 6545 if (Addr.getNode()) { 6546 SDValue Load; 6547 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 6548 Load = DAG.getLoad(TheSelect->getValueType(0), 6549 TheSelect->getDebugLoc(), 6550 LLD->getChain(), 6551 Addr, 0, 0, 6552 LLD->isVolatile(), 6553 LLD->isNonTemporal(), 6554 LLD->getAlignment()); 6555 } else { 6556 Load = DAG.getExtLoad(LLD->getExtensionType(), 6557 TheSelect->getDebugLoc(), 6558 TheSelect->getValueType(0), 6559 LLD->getChain(), Addr, 0, 0, 6560 LLD->getMemoryVT(), 6561 LLD->isVolatile(), 6562 LLD->isNonTemporal(), 6563 LLD->getAlignment()); 6564 } 6565 6566 // Users of the select now use the result of the load. 6567 CombineTo(TheSelect, Load); 6568 6569 // Users of the old loads now use the new load's chain. We know the 6570 // old-load value is dead now. 6571 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 6572 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 6573 return true; 6574 } 6575 } 6576 } 6577 } 6578 6579 return false; 6580} 6581 6582/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 6583/// where 'cond' is the comparison specified by CC. 6584SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 6585 SDValue N2, SDValue N3, 6586 ISD::CondCode CC, bool NotExtCompare) { 6587 // (x ? y : y) -> y. 6588 if (N2 == N3) return N2; 6589 6590 EVT VT = N2.getValueType(); 6591 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 6592 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 6593 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 6594 6595 // Determine if the condition we're dealing with is constant 6596 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 6597 N0, N1, CC, DL, false); 6598 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 6599 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 6600 6601 // fold select_cc true, x, y -> x 6602 if (SCCC && !SCCC->isNullValue()) 6603 return N2; 6604 // fold select_cc false, x, y -> y 6605 if (SCCC && SCCC->isNullValue()) 6606 return N3; 6607 6608 // Check to see if we can simplify the select into an fabs node 6609 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 6610 // Allow either -0.0 or 0.0 6611 if (CFP->getValueAPF().isZero()) { 6612 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 6613 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 6614 N0 == N2 && N3.getOpcode() == ISD::FNEG && 6615 N2 == N3.getOperand(0)) 6616 return DAG.getNode(ISD::FABS, DL, VT, N0); 6617 6618 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 6619 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 6620 N0 == N3 && N2.getOpcode() == ISD::FNEG && 6621 N2.getOperand(0) == N3) 6622 return DAG.getNode(ISD::FABS, DL, VT, N3); 6623 } 6624 } 6625 6626 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 6627 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 6628 // in it. This is a win when the constant is not otherwise available because 6629 // it replaces two constant pool loads with one. We only do this if the FP 6630 // type is known to be legal, because if it isn't, then we are before legalize 6631 // types an we want the other legalization to happen first (e.g. to avoid 6632 // messing with soft float) and if the ConstantFP is not legal, because if 6633 // it is legal, we may not need to store the FP constant in a constant pool. 6634 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 6635 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 6636 if (TLI.isTypeLegal(N2.getValueType()) && 6637 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 6638 TargetLowering::Legal) && 6639 // If both constants have multiple uses, then we won't need to do an 6640 // extra load, they are likely around in registers for other users. 6641 (TV->hasOneUse() || FV->hasOneUse())) { 6642 Constant *Elts[] = { 6643 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6644 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6645 }; 6646 const Type *FPTy = Elts[0]->getType(); 6647 const TargetData &TD = *TLI.getTargetData(); 6648 6649 // Create a ConstantArray of the two constants. 6650 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6651 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6652 TD.getPrefTypeAlignment(FPTy)); 6653 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6654 6655 // Get the offsets to the 0 and 1 element of the array so that we can 6656 // select between them. 6657 SDValue Zero = DAG.getIntPtrConstant(0); 6658 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6659 SDValue One = DAG.getIntPtrConstant(EltSize); 6660 6661 SDValue Cond = DAG.getSetCC(DL, 6662 TLI.getSetCCResultType(N0.getValueType()), 6663 N0, N1, CC); 6664 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6665 Cond, One, Zero); 6666 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6667 CstOffset); 6668 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6669 PseudoSourceValue::getConstantPool(), 0, false, 6670 false, Alignment); 6671 6672 } 6673 } 6674 6675 // Check to see if we can perform the "gzip trick", transforming 6676 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6677 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6678 N0.getValueType().isInteger() && 6679 N2.getValueType().isInteger() && 6680 (N1C->isNullValue() || // (a < 0) ? b : 0 6681 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6682 EVT XType = N0.getValueType(); 6683 EVT AType = N2.getValueType(); 6684 if (XType.bitsGE(AType)) { 6685 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6686 // single-bit constant. 6687 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6688 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6689 ShCtV = XType.getSizeInBits()-ShCtV-1; 6690 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6691 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6692 XType, N0, ShCt); 6693 AddToWorkList(Shift.getNode()); 6694 6695 if (XType.bitsGT(AType)) { 6696 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6697 AddToWorkList(Shift.getNode()); 6698 } 6699 6700 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6701 } 6702 6703 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6704 XType, N0, 6705 DAG.getConstant(XType.getSizeInBits()-1, 6706 getShiftAmountTy())); 6707 AddToWorkList(Shift.getNode()); 6708 6709 if (XType.bitsGT(AType)) { 6710 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6711 AddToWorkList(Shift.getNode()); 6712 } 6713 6714 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6715 } 6716 } 6717 6718 // fold select C, 16, 0 -> shl C, 4 6719 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6720 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6721 6722 // If the caller doesn't want us to simplify this into a zext of a compare, 6723 // don't do it. 6724 if (NotExtCompare && N2C->getAPIntValue() == 1) 6725 return SDValue(); 6726 6727 // Get a SetCC of the condition 6728 // FIXME: Should probably make sure that setcc is legal if we ever have a 6729 // target where it isn't. 6730 SDValue Temp, SCC; 6731 // cast from setcc result type to select result type 6732 if (LegalTypes) { 6733 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6734 N0, N1, CC); 6735 if (N2.getValueType().bitsLT(SCC.getValueType())) 6736 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6737 else 6738 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6739 N2.getValueType(), SCC); 6740 } else { 6741 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6742 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6743 N2.getValueType(), SCC); 6744 } 6745 6746 AddToWorkList(SCC.getNode()); 6747 AddToWorkList(Temp.getNode()); 6748 6749 if (N2C->getAPIntValue() == 1) 6750 return Temp; 6751 6752 // shl setcc result by log2 n2c 6753 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6754 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6755 getShiftAmountTy())); 6756 } 6757 6758 // Check to see if this is the equivalent of setcc 6759 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6760 // otherwise, go ahead with the folds. 6761 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6762 EVT XType = N0.getValueType(); 6763 if (!LegalOperations || 6764 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6765 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6766 if (Res.getValueType() != VT) 6767 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6768 return Res; 6769 } 6770 6771 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6772 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6773 (!LegalOperations || 6774 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6775 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6776 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6777 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6778 getShiftAmountTy())); 6779 } 6780 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6781 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6782 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6783 XType, DAG.getConstant(0, XType), N0); 6784 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6785 return DAG.getNode(ISD::SRL, DL, XType, 6786 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6787 DAG.getConstant(XType.getSizeInBits()-1, 6788 getShiftAmountTy())); 6789 } 6790 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6791 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6792 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6793 DAG.getConstant(XType.getSizeInBits()-1, 6794 getShiftAmountTy())); 6795 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6796 } 6797 } 6798 6799 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6800 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6801 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6802 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6803 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6804 EVT XType = N0.getValueType(); 6805 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6806 DAG.getConstant(XType.getSizeInBits()-1, 6807 getShiftAmountTy())); 6808 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6809 N0, Shift); 6810 AddToWorkList(Shift.getNode()); 6811 AddToWorkList(Add.getNode()); 6812 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6813 } 6814 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6815 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6816 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6817 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6818 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6819 EVT XType = N0.getValueType(); 6820 if (SubC->isNullValue() && XType.isInteger()) { 6821 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6822 N0, 6823 DAG.getConstant(XType.getSizeInBits()-1, 6824 getShiftAmountTy())); 6825 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6826 XType, N0, Shift); 6827 AddToWorkList(Shift.getNode()); 6828 AddToWorkList(Add.getNode()); 6829 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6830 } 6831 } 6832 } 6833 6834 return SDValue(); 6835} 6836 6837/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6838SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6839 SDValue N1, ISD::CondCode Cond, 6840 DebugLoc DL, bool foldBooleans) { 6841 TargetLowering::DAGCombinerInfo 6842 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6843 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6844} 6845 6846/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6847/// return a DAG expression to select that will generate the same value by 6848/// multiplying by a magic number. See: 6849/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6850SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6851 std::vector<SDNode*> Built; 6852 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6853 6854 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6855 ii != ee; ++ii) 6856 AddToWorkList(*ii); 6857 return S; 6858} 6859 6860/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6861/// return a DAG expression to select that will generate the same value by 6862/// multiplying by a magic number. See: 6863/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6864SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6865 std::vector<SDNode*> Built; 6866 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6867 6868 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6869 ii != ee; ++ii) 6870 AddToWorkList(*ii); 6871 return S; 6872} 6873 6874/// FindBaseOffset - Return true if base is a frame index, which is known not 6875// to alias with anything but itself. Provides base object and offset as results. 6876static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6877 const GlobalValue *&GV, void *&CV) { 6878 // Assume it is a primitive operation. 6879 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6880 6881 // If it's an adding a simple constant then integrate the offset. 6882 if (Base.getOpcode() == ISD::ADD) { 6883 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6884 Base = Base.getOperand(0); 6885 Offset += C->getZExtValue(); 6886 } 6887 } 6888 6889 // Return the underlying GlobalValue, and update the Offset. Return false 6890 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6891 // by multiple nodes with different offsets. 6892 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6893 GV = G->getGlobal(); 6894 Offset += G->getOffset(); 6895 return false; 6896 } 6897 6898 // Return the underlying Constant value, and update the Offset. Return false 6899 // for ConstantSDNodes since the same constant pool entry may be represented 6900 // by multiple nodes with different offsets. 6901 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6902 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6903 : (void *)C->getConstVal(); 6904 Offset += C->getOffset(); 6905 return false; 6906 } 6907 // If it's any of the following then it can't alias with anything but itself. 6908 return isa<FrameIndexSDNode>(Base); 6909} 6910 6911/// isAlias - Return true if there is any possibility that the two addresses 6912/// overlap. 6913bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6914 const Value *SrcValue1, int SrcValueOffset1, 6915 unsigned SrcValueAlign1, 6916 SDValue Ptr2, int64_t Size2, 6917 const Value *SrcValue2, int SrcValueOffset2, 6918 unsigned SrcValueAlign2) const { 6919 // If they are the same then they must be aliases. 6920 if (Ptr1 == Ptr2) return true; 6921 6922 // Gather base node and offset information. 6923 SDValue Base1, Base2; 6924 int64_t Offset1, Offset2; 6925 const GlobalValue *GV1, *GV2; 6926 void *CV1, *CV2; 6927 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6928 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6929 6930 // If they have a same base address then check to see if they overlap. 6931 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6932 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6933 6934 // If we know what the bases are, and they aren't identical, then we know they 6935 // cannot alias. 6936 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6937 return false; 6938 6939 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6940 // compared to the size and offset of the access, we may be able to prove they 6941 // do not alias. This check is conservative for now to catch cases created by 6942 // splitting vector types. 6943 if ((SrcValueAlign1 == SrcValueAlign2) && 6944 (SrcValueOffset1 != SrcValueOffset2) && 6945 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6946 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6947 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6948 6949 // There is no overlap between these relatively aligned accesses of similar 6950 // size, return no alias. 6951 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6952 return false; 6953 } 6954 6955 if (CombinerGlobalAA) { 6956 // Use alias analysis information. 6957 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6958 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6959 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6960 AliasAnalysis::AliasResult AAResult = 6961 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6962 if (AAResult == AliasAnalysis::NoAlias) 6963 return false; 6964 } 6965 6966 // Otherwise we have to assume they alias. 6967 return true; 6968} 6969 6970/// FindAliasInfo - Extracts the relevant alias information from the memory 6971/// node. Returns true if the operand was a load. 6972bool DAGCombiner::FindAliasInfo(SDNode *N, 6973 SDValue &Ptr, int64_t &Size, 6974 const Value *&SrcValue, 6975 int &SrcValueOffset, 6976 unsigned &SrcValueAlign) const { 6977 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6978 Ptr = LD->getBasePtr(); 6979 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6980 SrcValue = LD->getSrcValue(); 6981 SrcValueOffset = LD->getSrcValueOffset(); 6982 SrcValueAlign = LD->getOriginalAlignment(); 6983 return true; 6984 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6985 Ptr = ST->getBasePtr(); 6986 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6987 SrcValue = ST->getSrcValue(); 6988 SrcValueOffset = ST->getSrcValueOffset(); 6989 SrcValueAlign = ST->getOriginalAlignment(); 6990 } else { 6991 llvm_unreachable("FindAliasInfo expected a memory operand"); 6992 } 6993 6994 return false; 6995} 6996 6997/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6998/// looking for aliasing nodes and adding them to the Aliases vector. 6999void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7000 SmallVector<SDValue, 8> &Aliases) { 7001 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7002 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7003 7004 // Get alias information for node. 7005 SDValue Ptr; 7006 int64_t Size; 7007 const Value *SrcValue; 7008 int SrcValueOffset; 7009 unsigned SrcValueAlign; 7010 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7011 SrcValueAlign); 7012 7013 // Starting off. 7014 Chains.push_back(OriginalChain); 7015 unsigned Depth = 0; 7016 7017 // Look at each chain and determine if it is an alias. If so, add it to the 7018 // aliases list. If not, then continue up the chain looking for the next 7019 // candidate. 7020 while (!Chains.empty()) { 7021 SDValue Chain = Chains.back(); 7022 Chains.pop_back(); 7023 7024 // For TokenFactor nodes, look at each operand and only continue up the 7025 // chain until we find two aliases. If we've seen two aliases, assume we'll 7026 // find more and revert to original chain since the xform is unlikely to be 7027 // profitable. 7028 // 7029 // FIXME: The depth check could be made to return the last non-aliasing 7030 // chain we found before we hit a tokenfactor rather than the original 7031 // chain. 7032 if (Depth > 6 || Aliases.size() == 2) { 7033 Aliases.clear(); 7034 Aliases.push_back(OriginalChain); 7035 break; 7036 } 7037 7038 // Don't bother if we've been before. 7039 if (!Visited.insert(Chain.getNode())) 7040 continue; 7041 7042 switch (Chain.getOpcode()) { 7043 case ISD::EntryToken: 7044 // Entry token is ideal chain operand, but handled in FindBetterChain. 7045 break; 7046 7047 case ISD::LOAD: 7048 case ISD::STORE: { 7049 // Get alias information for Chain. 7050 SDValue OpPtr; 7051 int64_t OpSize; 7052 const Value *OpSrcValue; 7053 int OpSrcValueOffset; 7054 unsigned OpSrcValueAlign; 7055 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7056 OpSrcValue, OpSrcValueOffset, 7057 OpSrcValueAlign); 7058 7059 // If chain is alias then stop here. 7060 if (!(IsLoad && IsOpLoad) && 7061 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7062 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7063 OpSrcValueAlign)) { 7064 Aliases.push_back(Chain); 7065 } else { 7066 // Look further up the chain. 7067 Chains.push_back(Chain.getOperand(0)); 7068 ++Depth; 7069 } 7070 break; 7071 } 7072 7073 case ISD::TokenFactor: 7074 // We have to check each of the operands of the token factor for "small" 7075 // token factors, so we queue them up. Adding the operands to the queue 7076 // (stack) in reverse order maintains the original order and increases the 7077 // likelihood that getNode will find a matching token factor (CSE.) 7078 if (Chain.getNumOperands() > 16) { 7079 Aliases.push_back(Chain); 7080 break; 7081 } 7082 for (unsigned n = Chain.getNumOperands(); n;) 7083 Chains.push_back(Chain.getOperand(--n)); 7084 ++Depth; 7085 break; 7086 7087 default: 7088 // For all other instructions we will just have to take what we can get. 7089 Aliases.push_back(Chain); 7090 break; 7091 } 7092 } 7093} 7094 7095/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7096/// for a better chain (aliasing node.) 7097SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7098 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7099 7100 // Accumulate all the aliases to this node. 7101 GatherAllAliases(N, OldChain, Aliases); 7102 7103 if (Aliases.size() == 0) { 7104 // If no operands then chain to entry token. 7105 return DAG.getEntryNode(); 7106 } else if (Aliases.size() == 1) { 7107 // If a single operand then chain to it. We don't need to revisit it. 7108 return Aliases[0]; 7109 } 7110 7111 // Construct a custom tailored token factor. 7112 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7113 &Aliases[0], Aliases.size()); 7114} 7115 7116// SelectionDAG::Combine - This is the entry point for the file. 7117// 7118void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7119 CodeGenOpt::Level OptLevel) { 7120 /// run - This is the main entry point to this class. 7121 /// 7122 DAGCombiner(*this, AA, OptLevel).Run(Level); 7123} 7124