DAGCombiner.cpp revision 8a7f7426eeb18fef58c3471db23fc829b67bc350
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 /// combine - call the node-specific routine that knows how to fold each 142 /// particular type of node. If that doesn't do anything, try the 143 /// target-specific DAG combines. 144 SDValue combine(SDNode *N); 145 146 // Visitation implementation - Implement dag node combining for different 147 // node types. The semantics are as follows: 148 // Return Value: 149 // SDValue.getNode() == 0 - No change was made 150 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151 // otherwise - N should be replaced by the returned Operand. 152 // 153 SDValue visitTokenFactor(SDNode *N); 154 SDValue visitMERGE_VALUES(SDNode *N); 155 SDValue visitADD(SDNode *N); 156 SDValue visitSUB(SDNode *N); 157 SDValue visitADDC(SDNode *N); 158 SDValue visitADDE(SDNode *N); 159 SDValue visitMUL(SDNode *N); 160 SDValue visitSDIV(SDNode *N); 161 SDValue visitUDIV(SDNode *N); 162 SDValue visitSREM(SDNode *N); 163 SDValue visitUREM(SDNode *N); 164 SDValue visitMULHU(SDNode *N); 165 SDValue visitMULHS(SDNode *N); 166 SDValue visitSMUL_LOHI(SDNode *N); 167 SDValue visitUMUL_LOHI(SDNode *N); 168 SDValue visitSDIVREM(SDNode *N); 169 SDValue visitUDIVREM(SDNode *N); 170 SDValue visitAND(SDNode *N); 171 SDValue visitOR(SDNode *N); 172 SDValue visitXOR(SDNode *N); 173 SDValue SimplifyVBinOp(SDNode *N); 174 SDValue visitSHL(SDNode *N); 175 SDValue visitSRA(SDNode *N); 176 SDValue visitSRL(SDNode *N); 177 SDValue visitCTLZ(SDNode *N); 178 SDValue visitCTTZ(SDNode *N); 179 SDValue visitCTPOP(SDNode *N); 180 SDValue visitSELECT(SDNode *N); 181 SDValue visitSELECT_CC(SDNode *N); 182 SDValue visitSETCC(SDNode *N); 183 SDValue visitSIGN_EXTEND(SDNode *N); 184 SDValue visitZERO_EXTEND(SDNode *N); 185 SDValue visitANY_EXTEND(SDNode *N); 186 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 187 SDValue visitTRUNCATE(SDNode *N); 188 SDValue visitBIT_CONVERT(SDNode *N); 189 SDValue visitBUILD_PAIR(SDNode *N); 190 SDValue visitFADD(SDNode *N); 191 SDValue visitFSUB(SDNode *N); 192 SDValue visitFMUL(SDNode *N); 193 SDValue visitFDIV(SDNode *N); 194 SDValue visitFREM(SDNode *N); 195 SDValue visitFCOPYSIGN(SDNode *N); 196 SDValue visitSINT_TO_FP(SDNode *N); 197 SDValue visitUINT_TO_FP(SDNode *N); 198 SDValue visitFP_TO_SINT(SDNode *N); 199 SDValue visitFP_TO_UINT(SDNode *N); 200 SDValue visitFP_ROUND(SDNode *N); 201 SDValue visitFP_ROUND_INREG(SDNode *N); 202 SDValue visitFP_EXTEND(SDNode *N); 203 SDValue visitFNEG(SDNode *N); 204 SDValue visitFABS(SDNode *N); 205 SDValue visitBRCOND(SDNode *N); 206 SDValue visitBR_CC(SDNode *N); 207 SDValue visitLOAD(SDNode *N); 208 SDValue visitSTORE(SDNode *N); 209 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 211 SDValue visitBUILD_VECTOR(SDNode *N); 212 SDValue visitCONCAT_VECTORS(SDNode *N); 213 SDValue visitVECTOR_SHUFFLE(SDNode *N); 214 215 SDValue XformToShuffleWithZero(SDNode *N); 216 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 217 218 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 219 220 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 221 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 222 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 223 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 224 SDValue N3, ISD::CondCode CC, 225 bool NotExtCompare = false); 226 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 227 DebugLoc DL, bool foldBooleans = true); 228 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 229 unsigned HiOp); 230 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 231 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 232 SDValue BuildSDIV(SDNode *N); 233 SDValue BuildUDIV(SDNode *N); 234 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 235 SDValue ReduceLoadWidth(SDNode *N); 236 SDValue ReduceLoadOpStoreWidth(SDNode *N); 237 238 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 239 240 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 241 /// looking for aliasing nodes and adding them to the Aliases vector. 242 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 243 SmallVector<SDValue, 8> &Aliases); 244 245 /// isAlias - Return true if there is any possibility that the two addresses 246 /// overlap. 247 bool isAlias(SDValue Ptr1, int64_t Size1, 248 const Value *SrcValue1, int SrcValueOffset1, 249 unsigned SrcValueAlign1, 250 SDValue Ptr2, int64_t Size2, 251 const Value *SrcValue2, int SrcValueOffset2, 252 unsigned SrcValueAlign2) const; 253 254 /// FindAliasInfo - Extracts the relevant alias information from the memory 255 /// node. Returns true if the operand was a load. 256 bool FindAliasInfo(SDNode *N, 257 SDValue &Ptr, int64_t &Size, 258 const Value *&SrcValue, int &SrcValueOffset, 259 unsigned &SrcValueAlignment) const; 260 261 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 262 /// looking for a better chain (aliasing node.) 263 SDValue FindBetterChain(SDNode *N, SDValue Chain); 264 265 public: 266 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 267 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 268 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 269 270 /// Run - runs the dag combiner on all nodes in the work list 271 void Run(CombineLevel AtLevel); 272 273 SelectionDAG &getDAG() const { return DAG; } 274 275 /// getShiftAmountTy - Returns a type large enough to hold any valid 276 /// shift amount - before type legalization these can be huge. 277 EVT getShiftAmountTy() { 278 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 279 } 280 281 /// isTypeLegal - This method returns true if we are running before type 282 /// legalization or if the specified VT is legal. 283 bool isTypeLegal(const EVT &VT) { 284 if (!LegalTypes) return true; 285 return TLI.isTypeLegal(VT); 286 } 287 }; 288} 289 290 291namespace { 292/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 293/// nodes from the worklist. 294class WorkListRemover : public SelectionDAG::DAGUpdateListener { 295 DAGCombiner &DC; 296public: 297 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 298 299 virtual void NodeDeleted(SDNode *N, SDNode *E) { 300 DC.removeFromWorkList(N); 301 } 302 303 virtual void NodeUpdated(SDNode *N) { 304 // Ignore updates. 305 } 306}; 307} 308 309//===----------------------------------------------------------------------===// 310// TargetLowering::DAGCombinerInfo implementation 311//===----------------------------------------------------------------------===// 312 313void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 314 ((DAGCombiner*)DC)->AddToWorkList(N); 315} 316 317SDValue TargetLowering::DAGCombinerInfo:: 318CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 319 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 320} 321 322SDValue TargetLowering::DAGCombinerInfo:: 323CombineTo(SDNode *N, SDValue Res, bool AddTo) { 324 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 325} 326 327 328SDValue TargetLowering::DAGCombinerInfo:: 329CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 330 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 331} 332 333void TargetLowering::DAGCombinerInfo:: 334CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 335 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 336} 337 338//===----------------------------------------------------------------------===// 339// Helper Functions 340//===----------------------------------------------------------------------===// 341 342/// isNegatibleForFree - Return 1 if we can compute the negated form of the 343/// specified expression for the same cost as the expression itself, or 2 if we 344/// can compute the negated form more cheaply than the expression itself. 345static char isNegatibleForFree(SDValue Op, bool LegalOperations, 346 unsigned Depth = 0) { 347 // No compile time optimizations on this type. 348 if (Op.getValueType() == MVT::ppcf128) 349 return 0; 350 351 // fneg is removable even if it has multiple uses. 352 if (Op.getOpcode() == ISD::FNEG) return 2; 353 354 // Don't allow anything with multiple uses. 355 if (!Op.hasOneUse()) return 0; 356 357 // Don't recurse exponentially. 358 if (Depth > 6) return 0; 359 360 switch (Op.getOpcode()) { 361 default: return false; 362 case ISD::ConstantFP: 363 // Don't invert constant FP values after legalize. The negated constant 364 // isn't necessarily legal. 365 return LegalOperations ? 0 : 1; 366 case ISD::FADD: 367 // FIXME: determine better conditions for this xform. 368 if (!UnsafeFPMath) return 0; 369 370 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 371 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 372 return V; 373 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 374 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 375 case ISD::FSUB: 376 // We can't turn -(A-B) into B-A when we honor signed zeros. 377 if (!UnsafeFPMath) return 0; 378 379 // fold (fneg (fsub A, B)) -> (fsub B, A) 380 return 1; 381 382 case ISD::FMUL: 383 case ISD::FDIV: 384 if (HonorSignDependentRoundingFPMath()) return 0; 385 386 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 387 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 388 return V; 389 390 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 391 392 case ISD::FP_EXTEND: 393 case ISD::FP_ROUND: 394 case ISD::FSIN: 395 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 396 } 397} 398 399/// GetNegatedExpression - If isNegatibleForFree returns true, this function 400/// returns the newly negated expression. 401static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 402 bool LegalOperations, unsigned Depth = 0) { 403 // fneg is removable even if it has multiple uses. 404 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 405 406 // Don't allow anything with multiple uses. 407 assert(Op.hasOneUse() && "Unknown reuse!"); 408 409 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 410 switch (Op.getOpcode()) { 411 default: llvm_unreachable("Unknown code"); 412 case ISD::ConstantFP: { 413 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 414 V.changeSign(); 415 return DAG.getConstantFP(V, Op.getValueType()); 416 } 417 case ISD::FADD: 418 // FIXME: determine better conditions for this xform. 419 assert(UnsafeFPMath); 420 421 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 422 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 423 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 424 GetNegatedExpression(Op.getOperand(0), DAG, 425 LegalOperations, Depth+1), 426 Op.getOperand(1)); 427 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 428 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(1), DAG, 430 LegalOperations, Depth+1), 431 Op.getOperand(0)); 432 case ISD::FSUB: 433 // We can't turn -(A-B) into B-A when we honor signed zeros. 434 assert(UnsafeFPMath); 435 436 // fold (fneg (fsub 0, B)) -> B 437 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 438 if (N0CFP->getValueAPF().isZero()) 439 return Op.getOperand(1); 440 441 // fold (fneg (fsub A, B)) -> (fsub B, A) 442 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 443 Op.getOperand(1), Op.getOperand(0)); 444 445 case ISD::FMUL: 446 case ISD::FDIV: 447 assert(!HonorSignDependentRoundingFPMath()); 448 449 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 450 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 451 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 452 GetNegatedExpression(Op.getOperand(0), DAG, 453 LegalOperations, Depth+1), 454 Op.getOperand(1)); 455 456 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 457 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 458 Op.getOperand(0), 459 GetNegatedExpression(Op.getOperand(1), DAG, 460 LegalOperations, Depth+1)); 461 462 case ISD::FP_EXTEND: 463 case ISD::FSIN: 464 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 465 GetNegatedExpression(Op.getOperand(0), DAG, 466 LegalOperations, Depth+1)); 467 case ISD::FP_ROUND: 468 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 469 GetNegatedExpression(Op.getOperand(0), DAG, 470 LegalOperations, Depth+1), 471 Op.getOperand(1)); 472 } 473} 474 475 476// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 477// that selects between the values 1 and 0, making it equivalent to a setcc. 478// Also, set the incoming LHS, RHS, and CC references to the appropriate 479// nodes based on the type of node we are checking. This simplifies life a 480// bit for the callers. 481static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 482 SDValue &CC) { 483 if (N.getOpcode() == ISD::SETCC) { 484 LHS = N.getOperand(0); 485 RHS = N.getOperand(1); 486 CC = N.getOperand(2); 487 return true; 488 } 489 if (N.getOpcode() == ISD::SELECT_CC && 490 N.getOperand(2).getOpcode() == ISD::Constant && 491 N.getOperand(3).getOpcode() == ISD::Constant && 492 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 493 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 494 LHS = N.getOperand(0); 495 RHS = N.getOperand(1); 496 CC = N.getOperand(4); 497 return true; 498 } 499 return false; 500} 501 502// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 503// one use. If this is true, it allows the users to invert the operation for 504// free when it is profitable to do so. 505static bool isOneUseSetCC(SDValue N) { 506 SDValue N0, N1, N2; 507 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 508 return true; 509 return false; 510} 511 512SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 513 SDValue N0, SDValue N1) { 514 EVT VT = N0.getValueType(); 515 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 516 if (isa<ConstantSDNode>(N1)) { 517 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 518 SDValue OpNode = 519 DAG.FoldConstantArithmetic(Opc, VT, 520 cast<ConstantSDNode>(N0.getOperand(1)), 521 cast<ConstantSDNode>(N1)); 522 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 523 } else if (N0.hasOneUse()) { 524 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 525 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 526 N0.getOperand(0), N1); 527 AddToWorkList(OpNode.getNode()); 528 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 529 } 530 } 531 532 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 533 if (isa<ConstantSDNode>(N0)) { 534 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 535 SDValue OpNode = 536 DAG.FoldConstantArithmetic(Opc, VT, 537 cast<ConstantSDNode>(N1.getOperand(1)), 538 cast<ConstantSDNode>(N0)); 539 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 540 } else if (N1.hasOneUse()) { 541 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 542 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 543 N1.getOperand(0), N0); 544 AddToWorkList(OpNode.getNode()); 545 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 546 } 547 } 548 549 return SDValue(); 550} 551 552SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 553 bool AddTo) { 554 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 555 ++NodesCombined; 556 DEBUG(dbgs() << "\nReplacing.1 "; 557 N->dump(&DAG); 558 dbgs() << "\nWith: "; 559 To[0].getNode()->dump(&DAG); 560 dbgs() << " and " << NumTo-1 << " other values\n"; 561 for (unsigned i = 0, e = NumTo; i != e; ++i) 562 assert((!To[i].getNode() || 563 N->getValueType(i) == To[i].getValueType()) && 564 "Cannot combine value to value of different type!")); 565 WorkListRemover DeadNodes(*this); 566 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 567 568 if (AddTo) { 569 // Push the new nodes and any users onto the worklist 570 for (unsigned i = 0, e = NumTo; i != e; ++i) { 571 if (To[i].getNode()) { 572 AddToWorkList(To[i].getNode()); 573 AddUsersToWorkList(To[i].getNode()); 574 } 575 } 576 } 577 578 // Finally, if the node is now dead, remove it from the graph. The node 579 // may not be dead if the replacement process recursively simplified to 580 // something else needing this node. 581 if (N->use_empty()) { 582 // Nodes can be reintroduced into the worklist. Make sure we do not 583 // process a node that has been replaced. 584 removeFromWorkList(N); 585 586 // Finally, since the node is now dead, remove it from the graph. 587 DAG.DeleteNode(N); 588 } 589 return SDValue(N, 0); 590} 591 592void DAGCombiner:: 593CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 594 // Replace all uses. If any nodes become isomorphic to other nodes and 595 // are deleted, make sure to remove them from our worklist. 596 WorkListRemover DeadNodes(*this); 597 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 598 599 // Push the new node and any (possibly new) users onto the worklist. 600 AddToWorkList(TLO.New.getNode()); 601 AddUsersToWorkList(TLO.New.getNode()); 602 603 // Finally, if the node is now dead, remove it from the graph. The node 604 // may not be dead if the replacement process recursively simplified to 605 // something else needing this node. 606 if (TLO.Old.getNode()->use_empty()) { 607 removeFromWorkList(TLO.Old.getNode()); 608 609 // If the operands of this node are only used by the node, they will now 610 // be dead. Make sure to visit them first to delete dead nodes early. 611 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 612 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 613 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 614 615 DAG.DeleteNode(TLO.Old.getNode()); 616 } 617} 618 619/// SimplifyDemandedBits - Check the specified integer node value to see if 620/// it can be simplified or if things it uses can be simplified by bit 621/// propagation. If so, return true. 622bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 623 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 624 APInt KnownZero, KnownOne; 625 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 626 return false; 627 628 // Revisit the node. 629 AddToWorkList(Op.getNode()); 630 631 // Replace the old value with the new one. 632 ++NodesCombined; 633 DEBUG(dbgs() << "\nReplacing.2 "; 634 TLO.Old.getNode()->dump(&DAG); 635 dbgs() << "\nWith: "; 636 TLO.New.getNode()->dump(&DAG); 637 dbgs() << '\n'); 638 639 CommitTargetLoweringOpt(TLO); 640 return true; 641} 642 643void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 644 DebugLoc dl = Load->getDebugLoc(); 645 EVT VT = Load->getValueType(0); 646 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 647 648 DEBUG(dbgs() << "\nReplacing.9 "; 649 Load->dump(&DAG); 650 dbgs() << "\nWith: "; 651 Trunc.getNode()->dump(&DAG); 652 dbgs() << '\n'); 653 WorkListRemover DeadNodes(*this); 654 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 655 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 656 &DeadNodes); 657 removeFromWorkList(Load); 658 DAG.DeleteNode(Load); 659 AddToWorkList(Trunc.getNode()); 660} 661 662SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 663 Replace = false; 664 DebugLoc dl = Op.getDebugLoc(); 665 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 666 EVT MemVT = LD->getMemoryVT(); 667 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 668 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD) 669 : LD->getExtensionType(); 670 Replace = true; 671 return DAG.getExtLoad(ExtType, dl, PVT, 672 LD->getChain(), LD->getBasePtr(), 673 LD->getSrcValue(), LD->getSrcValueOffset(), 674 MemVT, LD->isVolatile(), 675 LD->isNonTemporal(), LD->getAlignment()); 676 } 677 678 unsigned Opc = Op.getOpcode(); 679 switch (Opc) { 680 default: break; 681 case ISD::AssertSext: 682 return DAG.getNode(ISD::AssertSext, dl, PVT, 683 SExtPromoteOperand(Op.getOperand(0), PVT), 684 Op.getOperand(1)); 685 case ISD::AssertZext: 686 return DAG.getNode(ISD::AssertZext, dl, PVT, 687 ZExtPromoteOperand(Op.getOperand(0), PVT), 688 Op.getOperand(1)); 689 case ISD::Constant: { 690 unsigned ExtOpc = 691 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 692 return DAG.getNode(ExtOpc, dl, PVT, Op); 693 } 694 } 695 696 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 697 return SDValue(); 698 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 699} 700 701SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 702 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 703 return SDValue(); 704 EVT OldVT = Op.getValueType(); 705 DebugLoc dl = Op.getDebugLoc(); 706 bool Replace = false; 707 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 708 if (NewOp.getNode() == 0) 709 return SDValue(); 710 AddToWorkList(NewOp.getNode()); 711 712 if (Replace) 713 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 714 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 715 DAG.getValueType(OldVT)); 716} 717 718SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 719 EVT OldVT = Op.getValueType(); 720 DebugLoc dl = Op.getDebugLoc(); 721 bool Replace = false; 722 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 723 if (NewOp.getNode() == 0) 724 return SDValue(); 725 AddToWorkList(NewOp.getNode()); 726 727 if (Replace) 728 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 729 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 730} 731 732/// PromoteIntBinOp - Promote the specified integer binary operation if the 733/// target indicates it is beneficial. e.g. On x86, it's usually better to 734/// promote i16 operations to i32 since i16 instructions are longer. 735SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 736 if (!LegalOperations) 737 return SDValue(); 738 739 EVT VT = Op.getValueType(); 740 if (VT.isVector() || !VT.isInteger()) 741 return SDValue(); 742 743 // If operation type is 'undesirable', e.g. i16 on x86, consider 744 // promoting it. 745 unsigned Opc = Op.getOpcode(); 746 if (TLI.isTypeDesirableForOp(Opc, VT)) 747 return SDValue(); 748 749 EVT PVT = VT; 750 // Consult target whether it is a good idea to promote this operation and 751 // what's the right type to promote it to. 752 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 753 assert(PVT != VT && "Don't know what type to promote to!"); 754 755 bool Replace0 = false; 756 SDValue N0 = Op.getOperand(0); 757 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 758 if (NN0.getNode() == 0) 759 return SDValue(); 760 761 bool Replace1 = false; 762 SDValue N1 = Op.getOperand(1); 763 SDValue NN1; 764 if (N0 == N1) 765 NN1 = NN0; 766 else { 767 NN1 = PromoteOperand(N1, PVT, Replace1); 768 if (NN1.getNode() == 0) 769 return SDValue(); 770 } 771 772 AddToWorkList(NN0.getNode()); 773 if (NN1.getNode()) 774 AddToWorkList(NN1.getNode()); 775 776 if (Replace0) 777 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 778 if (Replace1) 779 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 780 781 DEBUG(dbgs() << "\nPromoting "; 782 Op.getNode()->dump(&DAG)); 783 DebugLoc dl = Op.getDebugLoc(); 784 return DAG.getNode(ISD::TRUNCATE, dl, VT, 785 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 786 } 787 return SDValue(); 788} 789 790/// PromoteIntShiftOp - Promote the specified integer shift operation if the 791/// target indicates it is beneficial. e.g. On x86, it's usually better to 792/// promote i16 operations to i32 since i16 instructions are longer. 793SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 794 if (!LegalOperations) 795 return SDValue(); 796 797 EVT VT = Op.getValueType(); 798 if (VT.isVector() || !VT.isInteger()) 799 return SDValue(); 800 801 // If operation type is 'undesirable', e.g. i16 on x86, consider 802 // promoting it. 803 unsigned Opc = Op.getOpcode(); 804 if (TLI.isTypeDesirableForOp(Opc, VT)) 805 return SDValue(); 806 807 EVT PVT = VT; 808 // Consult target whether it is a good idea to promote this operation and 809 // what's the right type to promote it to. 810 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 811 assert(PVT != VT && "Don't know what type to promote to!"); 812 813 bool Replace = false; 814 SDValue N0 = Op.getOperand(0); 815 if (Opc == ISD::SRA) 816 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 817 else if (Opc == ISD::SRL) 818 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 819 else 820 N0 = PromoteOperand(N0, PVT, Replace); 821 if (N0.getNode() == 0) 822 return SDValue(); 823 824 AddToWorkList(N0.getNode()); 825 if (Replace) 826 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 827 828 DEBUG(dbgs() << "\nPromoting "; 829 Op.getNode()->dump(&DAG)); 830 DebugLoc dl = Op.getDebugLoc(); 831 return DAG.getNode(ISD::TRUNCATE, dl, VT, 832 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 833 } 834 return SDValue(); 835} 836 837SDValue DAGCombiner::PromoteExtend(SDValue Op) { 838 if (!LegalOperations) 839 return SDValue(); 840 841 EVT VT = Op.getValueType(); 842 if (VT.isVector() || !VT.isInteger()) 843 return SDValue(); 844 845 // If operation type is 'undesirable', e.g. i16 on x86, consider 846 // promoting it. 847 unsigned Opc = Op.getOpcode(); 848 if (TLI.isTypeDesirableForOp(Opc, VT)) 849 return SDValue(); 850 851 EVT PVT = VT; 852 // Consult target whether it is a good idea to promote this operation and 853 // what's the right type to promote it to. 854 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 855 assert(PVT != VT && "Don't know what type to promote to!"); 856 // fold (aext (aext x)) -> (aext x) 857 // fold (aext (zext x)) -> (zext x) 858 // fold (aext (sext x)) -> (sext x) 859 DEBUG(dbgs() << "\nPromoting "; 860 Op.getNode()->dump(&DAG)); 861 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 862 } 863 return SDValue(); 864} 865 866bool DAGCombiner::PromoteLoad(SDValue Op) { 867 if (!LegalOperations) 868 return false; 869 870 EVT VT = Op.getValueType(); 871 if (VT.isVector() || !VT.isInteger()) 872 return false; 873 874 // If operation type is 'undesirable', e.g. i16 on x86, consider 875 // promoting it. 876 unsigned Opc = Op.getOpcode(); 877 if (TLI.isTypeDesirableForOp(Opc, VT)) 878 return false; 879 880 EVT PVT = VT; 881 // Consult target whether it is a good idea to promote this operation and 882 // what's the right type to promote it to. 883 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 884 assert(PVT != VT && "Don't know what type to promote to!"); 885 886 DebugLoc dl = Op.getDebugLoc(); 887 SDNode *N = Op.getNode(); 888 LoadSDNode *LD = cast<LoadSDNode>(N); 889 EVT MemVT = LD->getMemoryVT(); 890 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 891 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD) 892 : LD->getExtensionType(); 893 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 894 LD->getChain(), LD->getBasePtr(), 895 LD->getSrcValue(), LD->getSrcValueOffset(), 896 MemVT, LD->isVolatile(), 897 LD->isNonTemporal(), LD->getAlignment()); 898 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 899 900 DEBUG(dbgs() << "\nPromoting "; 901 N->dump(&DAG); 902 dbgs() << "\nTo: "; 903 Result.getNode()->dump(&DAG); 904 dbgs() << '\n'); 905 WorkListRemover DeadNodes(*this); 906 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 907 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 908 removeFromWorkList(N); 909 DAG.DeleteNode(N); 910 AddToWorkList(Result.getNode()); 911 return true; 912 } 913 return false; 914} 915 916 917//===----------------------------------------------------------------------===// 918// Main DAG Combiner implementation 919//===----------------------------------------------------------------------===// 920 921void DAGCombiner::Run(CombineLevel AtLevel) { 922 // set the instance variables, so that the various visit routines may use it. 923 Level = AtLevel; 924 LegalOperations = Level >= NoIllegalOperations; 925 LegalTypes = Level >= NoIllegalTypes; 926 927 // Add all the dag nodes to the worklist. 928 WorkList.reserve(DAG.allnodes_size()); 929 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 930 E = DAG.allnodes_end(); I != E; ++I) 931 WorkList.push_back(I); 932 933 // Create a dummy node (which is not added to allnodes), that adds a reference 934 // to the root node, preventing it from being deleted, and tracking any 935 // changes of the root. 936 HandleSDNode Dummy(DAG.getRoot()); 937 938 // The root of the dag may dangle to deleted nodes until the dag combiner is 939 // done. Set it to null to avoid confusion. 940 DAG.setRoot(SDValue()); 941 942 // while the worklist isn't empty, inspect the node on the end of it and 943 // try and combine it. 944 while (!WorkList.empty()) { 945 SDNode *N = WorkList.back(); 946 WorkList.pop_back(); 947 948 // If N has no uses, it is dead. Make sure to revisit all N's operands once 949 // N is deleted from the DAG, since they too may now be dead or may have a 950 // reduced number of uses, allowing other xforms. 951 if (N->use_empty() && N != &Dummy) { 952 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 953 AddToWorkList(N->getOperand(i).getNode()); 954 955 DAG.DeleteNode(N); 956 continue; 957 } 958 959 SDValue RV = combine(N); 960 961 if (RV.getNode() == 0) 962 continue; 963 964 ++NodesCombined; 965 966 // If we get back the same node we passed in, rather than a new node or 967 // zero, we know that the node must have defined multiple values and 968 // CombineTo was used. Since CombineTo takes care of the worklist 969 // mechanics for us, we have no work to do in this case. 970 if (RV.getNode() == N) 971 continue; 972 973 assert(N->getOpcode() != ISD::DELETED_NODE && 974 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 975 "Node was deleted but visit returned new node!"); 976 977 DEBUG(dbgs() << "\nReplacing.3 "; 978 N->dump(&DAG); 979 dbgs() << "\nWith: "; 980 RV.getNode()->dump(&DAG); 981 dbgs() << '\n'); 982 WorkListRemover DeadNodes(*this); 983 if (N->getNumValues() == RV.getNode()->getNumValues()) 984 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 985 else { 986 assert(N->getValueType(0) == RV.getValueType() && 987 N->getNumValues() == 1 && "Type mismatch"); 988 SDValue OpV = RV; 989 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 990 } 991 992 // Push the new node and any users onto the worklist 993 AddToWorkList(RV.getNode()); 994 AddUsersToWorkList(RV.getNode()); 995 996 // Add any uses of the old node to the worklist in case this node is the 997 // last one that uses them. They may become dead after this node is 998 // deleted. 999 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1000 AddToWorkList(N->getOperand(i).getNode()); 1001 1002 // Finally, if the node is now dead, remove it from the graph. The node 1003 // may not be dead if the replacement process recursively simplified to 1004 // something else needing this node. 1005 if (N->use_empty()) { 1006 // Nodes can be reintroduced into the worklist. Make sure we do not 1007 // process a node that has been replaced. 1008 removeFromWorkList(N); 1009 1010 // Finally, since the node is now dead, remove it from the graph. 1011 DAG.DeleteNode(N); 1012 } 1013 } 1014 1015 // If the root changed (e.g. it was a dead load, update the root). 1016 DAG.setRoot(Dummy.getValue()); 1017} 1018 1019SDValue DAGCombiner::visit(SDNode *N) { 1020 switch (N->getOpcode()) { 1021 default: break; 1022 case ISD::TokenFactor: return visitTokenFactor(N); 1023 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1024 case ISD::ADD: return visitADD(N); 1025 case ISD::SUB: return visitSUB(N); 1026 case ISD::ADDC: return visitADDC(N); 1027 case ISD::ADDE: return visitADDE(N); 1028 case ISD::MUL: return visitMUL(N); 1029 case ISD::SDIV: return visitSDIV(N); 1030 case ISD::UDIV: return visitUDIV(N); 1031 case ISD::SREM: return visitSREM(N); 1032 case ISD::UREM: return visitUREM(N); 1033 case ISD::MULHU: return visitMULHU(N); 1034 case ISD::MULHS: return visitMULHS(N); 1035 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1036 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1037 case ISD::SDIVREM: return visitSDIVREM(N); 1038 case ISD::UDIVREM: return visitUDIVREM(N); 1039 case ISD::AND: return visitAND(N); 1040 case ISD::OR: return visitOR(N); 1041 case ISD::XOR: return visitXOR(N); 1042 case ISD::SHL: return visitSHL(N); 1043 case ISD::SRA: return visitSRA(N); 1044 case ISD::SRL: return visitSRL(N); 1045 case ISD::CTLZ: return visitCTLZ(N); 1046 case ISD::CTTZ: return visitCTTZ(N); 1047 case ISD::CTPOP: return visitCTPOP(N); 1048 case ISD::SELECT: return visitSELECT(N); 1049 case ISD::SELECT_CC: return visitSELECT_CC(N); 1050 case ISD::SETCC: return visitSETCC(N); 1051 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1052 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1053 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1054 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1055 case ISD::TRUNCATE: return visitTRUNCATE(N); 1056 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 1057 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1058 case ISD::FADD: return visitFADD(N); 1059 case ISD::FSUB: return visitFSUB(N); 1060 case ISD::FMUL: return visitFMUL(N); 1061 case ISD::FDIV: return visitFDIV(N); 1062 case ISD::FREM: return visitFREM(N); 1063 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1064 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1065 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1066 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1067 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1068 case ISD::FP_ROUND: return visitFP_ROUND(N); 1069 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1070 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1071 case ISD::FNEG: return visitFNEG(N); 1072 case ISD::FABS: return visitFABS(N); 1073 case ISD::BRCOND: return visitBRCOND(N); 1074 case ISD::BR_CC: return visitBR_CC(N); 1075 case ISD::LOAD: return visitLOAD(N); 1076 case ISD::STORE: return visitSTORE(N); 1077 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1078 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1079 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1080 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1081 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1082 } 1083 return SDValue(); 1084} 1085 1086SDValue DAGCombiner::combine(SDNode *N) { 1087 SDValue RV = visit(N); 1088 1089 // If nothing happened, try a target-specific DAG combine. 1090 if (RV.getNode() == 0) { 1091 assert(N->getOpcode() != ISD::DELETED_NODE && 1092 "Node was deleted but visit returned NULL!"); 1093 1094 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1095 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1096 1097 // Expose the DAG combiner to the target combiner impls. 1098 TargetLowering::DAGCombinerInfo 1099 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1100 1101 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1102 } 1103 } 1104 1105 // If nothing happened still, try promoting the operation. 1106 if (RV.getNode() == 0) { 1107 switch (N->getOpcode()) { 1108 default: break; 1109 case ISD::ADD: 1110 case ISD::SUB: 1111 case ISD::MUL: 1112 case ISD::AND: 1113 case ISD::OR: 1114 case ISD::XOR: 1115 RV = PromoteIntBinOp(SDValue(N, 0)); 1116 break; 1117 case ISD::SHL: 1118 case ISD::SRA: 1119 case ISD::SRL: 1120 RV = PromoteIntShiftOp(SDValue(N, 0)); 1121 break; 1122 case ISD::SIGN_EXTEND: 1123 case ISD::ZERO_EXTEND: 1124 case ISD::ANY_EXTEND: 1125 RV = PromoteExtend(SDValue(N, 0)); 1126 break; 1127 case ISD::LOAD: 1128 if (PromoteLoad(SDValue(N, 0))) 1129 RV = SDValue(N, 0); 1130 break; 1131 } 1132 } 1133 1134 // If N is a commutative binary node, try commuting it to enable more 1135 // sdisel CSE. 1136 if (RV.getNode() == 0 && 1137 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1138 N->getNumValues() == 1) { 1139 SDValue N0 = N->getOperand(0); 1140 SDValue N1 = N->getOperand(1); 1141 1142 // Constant operands are canonicalized to RHS. 1143 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1144 SDValue Ops[] = { N1, N0 }; 1145 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1146 Ops, 2); 1147 if (CSENode) 1148 return SDValue(CSENode, 0); 1149 } 1150 } 1151 1152 return RV; 1153} 1154 1155/// getInputChainForNode - Given a node, return its input chain if it has one, 1156/// otherwise return a null sd operand. 1157static SDValue getInputChainForNode(SDNode *N) { 1158 if (unsigned NumOps = N->getNumOperands()) { 1159 if (N->getOperand(0).getValueType() == MVT::Other) 1160 return N->getOperand(0); 1161 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1162 return N->getOperand(NumOps-1); 1163 for (unsigned i = 1; i < NumOps-1; ++i) 1164 if (N->getOperand(i).getValueType() == MVT::Other) 1165 return N->getOperand(i); 1166 } 1167 return SDValue(); 1168} 1169 1170SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1171 // If N has two operands, where one has an input chain equal to the other, 1172 // the 'other' chain is redundant. 1173 if (N->getNumOperands() == 2) { 1174 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1175 return N->getOperand(0); 1176 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1177 return N->getOperand(1); 1178 } 1179 1180 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1181 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1182 SmallPtrSet<SDNode*, 16> SeenOps; 1183 bool Changed = false; // If we should replace this token factor. 1184 1185 // Start out with this token factor. 1186 TFs.push_back(N); 1187 1188 // Iterate through token factors. The TFs grows when new token factors are 1189 // encountered. 1190 for (unsigned i = 0; i < TFs.size(); ++i) { 1191 SDNode *TF = TFs[i]; 1192 1193 // Check each of the operands. 1194 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1195 SDValue Op = TF->getOperand(i); 1196 1197 switch (Op.getOpcode()) { 1198 case ISD::EntryToken: 1199 // Entry tokens don't need to be added to the list. They are 1200 // rededundant. 1201 Changed = true; 1202 break; 1203 1204 case ISD::TokenFactor: 1205 if (Op.hasOneUse() && 1206 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1207 // Queue up for processing. 1208 TFs.push_back(Op.getNode()); 1209 // Clean up in case the token factor is removed. 1210 AddToWorkList(Op.getNode()); 1211 Changed = true; 1212 break; 1213 } 1214 // Fall thru 1215 1216 default: 1217 // Only add if it isn't already in the list. 1218 if (SeenOps.insert(Op.getNode())) 1219 Ops.push_back(Op); 1220 else 1221 Changed = true; 1222 break; 1223 } 1224 } 1225 } 1226 1227 SDValue Result; 1228 1229 // If we've change things around then replace token factor. 1230 if (Changed) { 1231 if (Ops.empty()) { 1232 // The entry token is the only possible outcome. 1233 Result = DAG.getEntryNode(); 1234 } else { 1235 // New and improved token factor. 1236 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1237 MVT::Other, &Ops[0], Ops.size()); 1238 } 1239 1240 // Don't add users to work list. 1241 return CombineTo(N, Result, false); 1242 } 1243 1244 return Result; 1245} 1246 1247/// MERGE_VALUES can always be eliminated. 1248SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1249 WorkListRemover DeadNodes(*this); 1250 // Replacing results may cause a different MERGE_VALUES to suddenly 1251 // be CSE'd with N, and carry its uses with it. Iterate until no 1252 // uses remain, to ensure that the node can be safely deleted. 1253 do { 1254 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1255 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1256 &DeadNodes); 1257 } while (!N->use_empty()); 1258 removeFromWorkList(N); 1259 DAG.DeleteNode(N); 1260 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1261} 1262 1263static 1264SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1265 SelectionDAG &DAG) { 1266 EVT VT = N0.getValueType(); 1267 SDValue N00 = N0.getOperand(0); 1268 SDValue N01 = N0.getOperand(1); 1269 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1270 1271 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1272 isa<ConstantSDNode>(N00.getOperand(1))) { 1273 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1274 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1275 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1276 N00.getOperand(0), N01), 1277 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1278 N00.getOperand(1), N01)); 1279 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1280 } 1281 1282 return SDValue(); 1283} 1284 1285SDValue DAGCombiner::visitADD(SDNode *N) { 1286 SDValue N0 = N->getOperand(0); 1287 SDValue N1 = N->getOperand(1); 1288 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1289 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1290 EVT VT = N0.getValueType(); 1291 1292 // fold vector ops 1293 if (VT.isVector()) { 1294 SDValue FoldedVOp = SimplifyVBinOp(N); 1295 if (FoldedVOp.getNode()) return FoldedVOp; 1296 } 1297 1298 // fold (add x, undef) -> undef 1299 if (N0.getOpcode() == ISD::UNDEF) 1300 return N0; 1301 if (N1.getOpcode() == ISD::UNDEF) 1302 return N1; 1303 // fold (add c1, c2) -> c1+c2 1304 if (N0C && N1C) 1305 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1306 // canonicalize constant to RHS 1307 if (N0C && !N1C) 1308 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1309 // fold (add x, 0) -> x 1310 if (N1C && N1C->isNullValue()) 1311 return N0; 1312 // fold (add Sym, c) -> Sym+c 1313 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1314 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1315 GA->getOpcode() == ISD::GlobalAddress) 1316 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1317 GA->getOffset() + 1318 (uint64_t)N1C->getSExtValue()); 1319 // fold ((c1-A)+c2) -> (c1+c2)-A 1320 if (N1C && N0.getOpcode() == ISD::SUB) 1321 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1322 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1323 DAG.getConstant(N1C->getAPIntValue()+ 1324 N0C->getAPIntValue(), VT), 1325 N0.getOperand(1)); 1326 // reassociate add 1327 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1328 if (RADD.getNode() != 0) 1329 return RADD; 1330 // fold ((0-A) + B) -> B-A 1331 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1332 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1333 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1334 // fold (A + (0-B)) -> A-B 1335 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1336 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1337 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1338 // fold (A+(B-A)) -> B 1339 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1340 return N1.getOperand(0); 1341 // fold ((B-A)+A) -> B 1342 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1343 return N0.getOperand(0); 1344 // fold (A+(B-(A+C))) to (B-C) 1345 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1346 N0 == N1.getOperand(1).getOperand(0)) 1347 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1348 N1.getOperand(1).getOperand(1)); 1349 // fold (A+(B-(C+A))) to (B-C) 1350 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1351 N0 == N1.getOperand(1).getOperand(1)) 1352 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1353 N1.getOperand(1).getOperand(0)); 1354 // fold (A+((B-A)+or-C)) to (B+or-C) 1355 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1356 N1.getOperand(0).getOpcode() == ISD::SUB && 1357 N0 == N1.getOperand(0).getOperand(1)) 1358 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1359 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1360 1361 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1362 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1363 SDValue N00 = N0.getOperand(0); 1364 SDValue N01 = N0.getOperand(1); 1365 SDValue N10 = N1.getOperand(0); 1366 SDValue N11 = N1.getOperand(1); 1367 1368 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1369 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1370 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1371 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1372 } 1373 1374 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1375 return SDValue(N, 0); 1376 1377 // fold (a+b) -> (a|b) iff a and b share no bits. 1378 if (VT.isInteger() && !VT.isVector()) { 1379 APInt LHSZero, LHSOne; 1380 APInt RHSZero, RHSOne; 1381 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1382 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1383 1384 if (LHSZero.getBoolValue()) { 1385 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1386 1387 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1388 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1389 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1390 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1391 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1392 } 1393 } 1394 1395 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1396 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1397 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1398 if (Result.getNode()) return Result; 1399 } 1400 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1401 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1402 if (Result.getNode()) return Result; 1403 } 1404 1405 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1406 if (N1.getOpcode() == ISD::SHL && 1407 N1.getOperand(0).getOpcode() == ISD::SUB) 1408 if (ConstantSDNode *C = 1409 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1410 if (C->getAPIntValue() == 0) 1411 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1412 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1413 N1.getOperand(0).getOperand(1), 1414 N1.getOperand(1))); 1415 if (N0.getOpcode() == ISD::SHL && 1416 N0.getOperand(0).getOpcode() == ISD::SUB) 1417 if (ConstantSDNode *C = 1418 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1419 if (C->getAPIntValue() == 0) 1420 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1421 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1422 N0.getOperand(0).getOperand(1), 1423 N0.getOperand(1))); 1424 1425 return SDValue(); 1426} 1427 1428SDValue DAGCombiner::visitADDC(SDNode *N) { 1429 SDValue N0 = N->getOperand(0); 1430 SDValue N1 = N->getOperand(1); 1431 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1432 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1433 EVT VT = N0.getValueType(); 1434 1435 // If the flag result is dead, turn this into an ADD. 1436 if (N->hasNUsesOfValue(0, 1)) 1437 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1438 DAG.getNode(ISD::CARRY_FALSE, 1439 N->getDebugLoc(), MVT::Flag)); 1440 1441 // canonicalize constant to RHS. 1442 if (N0C && !N1C) 1443 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1444 1445 // fold (addc x, 0) -> x + no carry out 1446 if (N1C && N1C->isNullValue()) 1447 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1448 N->getDebugLoc(), MVT::Flag)); 1449 1450 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1451 APInt LHSZero, LHSOne; 1452 APInt RHSZero, RHSOne; 1453 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1454 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1455 1456 if (LHSZero.getBoolValue()) { 1457 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1458 1459 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1460 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1461 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1462 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1463 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1464 DAG.getNode(ISD::CARRY_FALSE, 1465 N->getDebugLoc(), MVT::Flag)); 1466 } 1467 1468 return SDValue(); 1469} 1470 1471SDValue DAGCombiner::visitADDE(SDNode *N) { 1472 SDValue N0 = N->getOperand(0); 1473 SDValue N1 = N->getOperand(1); 1474 SDValue CarryIn = N->getOperand(2); 1475 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1476 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1477 1478 // canonicalize constant to RHS 1479 if (N0C && !N1C) 1480 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1481 N1, N0, CarryIn); 1482 1483 // fold (adde x, y, false) -> (addc x, y) 1484 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1485 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1486 1487 return SDValue(); 1488} 1489 1490SDValue DAGCombiner::visitSUB(SDNode *N) { 1491 SDValue N0 = N->getOperand(0); 1492 SDValue N1 = N->getOperand(1); 1493 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1494 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1495 EVT VT = N0.getValueType(); 1496 1497 // fold vector ops 1498 if (VT.isVector()) { 1499 SDValue FoldedVOp = SimplifyVBinOp(N); 1500 if (FoldedVOp.getNode()) return FoldedVOp; 1501 } 1502 1503 // fold (sub x, x) -> 0 1504 if (N0 == N1) 1505 return DAG.getConstant(0, N->getValueType(0)); 1506 // fold (sub c1, c2) -> c1-c2 1507 if (N0C && N1C) 1508 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1509 // fold (sub x, c) -> (add x, -c) 1510 if (N1C) 1511 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1512 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1513 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1514 if (N0C && N0C->isAllOnesValue()) 1515 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1516 // fold (A+B)-A -> B 1517 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1518 return N0.getOperand(1); 1519 // fold (A+B)-B -> A 1520 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1521 return N0.getOperand(0); 1522 // fold ((A+(B+or-C))-B) -> A+or-C 1523 if (N0.getOpcode() == ISD::ADD && 1524 (N0.getOperand(1).getOpcode() == ISD::SUB || 1525 N0.getOperand(1).getOpcode() == ISD::ADD) && 1526 N0.getOperand(1).getOperand(0) == N1) 1527 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1528 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1529 // fold ((A+(C+B))-B) -> A+C 1530 if (N0.getOpcode() == ISD::ADD && 1531 N0.getOperand(1).getOpcode() == ISD::ADD && 1532 N0.getOperand(1).getOperand(1) == N1) 1533 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1534 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1535 // fold ((A-(B-C))-C) -> A-B 1536 if (N0.getOpcode() == ISD::SUB && 1537 N0.getOperand(1).getOpcode() == ISD::SUB && 1538 N0.getOperand(1).getOperand(1) == N1) 1539 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1540 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1541 1542 // If either operand of a sub is undef, the result is undef 1543 if (N0.getOpcode() == ISD::UNDEF) 1544 return N0; 1545 if (N1.getOpcode() == ISD::UNDEF) 1546 return N1; 1547 1548 // If the relocation model supports it, consider symbol offsets. 1549 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1550 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1551 // fold (sub Sym, c) -> Sym-c 1552 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1553 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1554 GA->getOffset() - 1555 (uint64_t)N1C->getSExtValue()); 1556 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1557 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1558 if (GA->getGlobal() == GB->getGlobal()) 1559 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1560 VT); 1561 } 1562 1563 return SDValue(); 1564} 1565 1566SDValue DAGCombiner::visitMUL(SDNode *N) { 1567 SDValue N0 = N->getOperand(0); 1568 SDValue N1 = N->getOperand(1); 1569 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1570 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1571 EVT VT = N0.getValueType(); 1572 1573 // fold vector ops 1574 if (VT.isVector()) { 1575 SDValue FoldedVOp = SimplifyVBinOp(N); 1576 if (FoldedVOp.getNode()) return FoldedVOp; 1577 } 1578 1579 // fold (mul x, undef) -> 0 1580 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1581 return DAG.getConstant(0, VT); 1582 // fold (mul c1, c2) -> c1*c2 1583 if (N0C && N1C) 1584 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1585 // canonicalize constant to RHS 1586 if (N0C && !N1C) 1587 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1588 // fold (mul x, 0) -> 0 1589 if (N1C && N1C->isNullValue()) 1590 return N1; 1591 // fold (mul x, -1) -> 0-x 1592 if (N1C && N1C->isAllOnesValue()) 1593 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1594 DAG.getConstant(0, VT), N0); 1595 // fold (mul x, (1 << c)) -> x << c 1596 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1597 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1598 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1599 getShiftAmountTy())); 1600 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1601 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1602 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1603 // FIXME: If the input is something that is easily negated (e.g. a 1604 // single-use add), we should put the negate there. 1605 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1606 DAG.getConstant(0, VT), 1607 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1608 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1609 } 1610 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1611 if (N1C && N0.getOpcode() == ISD::SHL && 1612 isa<ConstantSDNode>(N0.getOperand(1))) { 1613 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1614 N1, N0.getOperand(1)); 1615 AddToWorkList(C3.getNode()); 1616 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1617 N0.getOperand(0), C3); 1618 } 1619 1620 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1621 // use. 1622 { 1623 SDValue Sh(0,0), Y(0,0); 1624 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1625 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1626 N0.getNode()->hasOneUse()) { 1627 Sh = N0; Y = N1; 1628 } else if (N1.getOpcode() == ISD::SHL && 1629 isa<ConstantSDNode>(N1.getOperand(1)) && 1630 N1.getNode()->hasOneUse()) { 1631 Sh = N1; Y = N0; 1632 } 1633 1634 if (Sh.getNode()) { 1635 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1636 Sh.getOperand(0), Y); 1637 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1638 Mul, Sh.getOperand(1)); 1639 } 1640 } 1641 1642 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1643 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1644 isa<ConstantSDNode>(N0.getOperand(1))) 1645 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1646 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1647 N0.getOperand(0), N1), 1648 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1649 N0.getOperand(1), N1)); 1650 1651 // reassociate mul 1652 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1653 if (RMUL.getNode() != 0) 1654 return RMUL; 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitSDIV(SDNode *N) { 1660 SDValue N0 = N->getOperand(0); 1661 SDValue N1 = N->getOperand(1); 1662 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1663 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1664 EVT VT = N->getValueType(0); 1665 1666 // fold vector ops 1667 if (VT.isVector()) { 1668 SDValue FoldedVOp = SimplifyVBinOp(N); 1669 if (FoldedVOp.getNode()) return FoldedVOp; 1670 } 1671 1672 // fold (sdiv c1, c2) -> c1/c2 1673 if (N0C && N1C && !N1C->isNullValue()) 1674 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1675 // fold (sdiv X, 1) -> X 1676 if (N1C && N1C->getSExtValue() == 1LL) 1677 return N0; 1678 // fold (sdiv X, -1) -> 0-X 1679 if (N1C && N1C->isAllOnesValue()) 1680 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1681 DAG.getConstant(0, VT), N0); 1682 // If we know the sign bits of both operands are zero, strength reduce to a 1683 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1684 if (!VT.isVector()) { 1685 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1686 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1687 N0, N1); 1688 } 1689 // fold (sdiv X, pow2) -> simple ops after legalize 1690 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1691 (isPowerOf2_64(N1C->getSExtValue()) || 1692 isPowerOf2_64(-N1C->getSExtValue()))) { 1693 // If dividing by powers of two is cheap, then don't perform the following 1694 // fold. 1695 if (TLI.isPow2DivCheap()) 1696 return SDValue(); 1697 1698 int64_t pow2 = N1C->getSExtValue(); 1699 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1700 unsigned lg2 = Log2_64(abs2); 1701 1702 // Splat the sign bit into the register 1703 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1704 DAG.getConstant(VT.getSizeInBits()-1, 1705 getShiftAmountTy())); 1706 AddToWorkList(SGN.getNode()); 1707 1708 // Add (N0 < 0) ? abs2 - 1 : 0; 1709 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1710 DAG.getConstant(VT.getSizeInBits() - lg2, 1711 getShiftAmountTy())); 1712 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1713 AddToWorkList(SRL.getNode()); 1714 AddToWorkList(ADD.getNode()); // Divide by pow2 1715 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1716 DAG.getConstant(lg2, getShiftAmountTy())); 1717 1718 // If we're dividing by a positive value, we're done. Otherwise, we must 1719 // negate the result. 1720 if (pow2 > 0) 1721 return SRA; 1722 1723 AddToWorkList(SRA.getNode()); 1724 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1725 DAG.getConstant(0, VT), SRA); 1726 } 1727 1728 // if integer divide is expensive and we satisfy the requirements, emit an 1729 // alternate sequence. 1730 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1731 !TLI.isIntDivCheap()) { 1732 SDValue Op = BuildSDIV(N); 1733 if (Op.getNode()) return Op; 1734 } 1735 1736 // undef / X -> 0 1737 if (N0.getOpcode() == ISD::UNDEF) 1738 return DAG.getConstant(0, VT); 1739 // X / undef -> undef 1740 if (N1.getOpcode() == ISD::UNDEF) 1741 return N1; 1742 1743 return SDValue(); 1744} 1745 1746SDValue DAGCombiner::visitUDIV(SDNode *N) { 1747 SDValue N0 = N->getOperand(0); 1748 SDValue N1 = N->getOperand(1); 1749 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1750 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1751 EVT VT = N->getValueType(0); 1752 1753 // fold vector ops 1754 if (VT.isVector()) { 1755 SDValue FoldedVOp = SimplifyVBinOp(N); 1756 if (FoldedVOp.getNode()) return FoldedVOp; 1757 } 1758 1759 // fold (udiv c1, c2) -> c1/c2 1760 if (N0C && N1C && !N1C->isNullValue()) 1761 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1762 // fold (udiv x, (1 << c)) -> x >>u c 1763 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1764 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1765 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1766 getShiftAmountTy())); 1767 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1768 if (N1.getOpcode() == ISD::SHL) { 1769 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1770 if (SHC->getAPIntValue().isPowerOf2()) { 1771 EVT ADDVT = N1.getOperand(1).getValueType(); 1772 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1773 N1.getOperand(1), 1774 DAG.getConstant(SHC->getAPIntValue() 1775 .logBase2(), 1776 ADDVT)); 1777 AddToWorkList(Add.getNode()); 1778 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1779 } 1780 } 1781 } 1782 // fold (udiv x, c) -> alternate 1783 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1784 SDValue Op = BuildUDIV(N); 1785 if (Op.getNode()) return Op; 1786 } 1787 1788 // undef / X -> 0 1789 if (N0.getOpcode() == ISD::UNDEF) 1790 return DAG.getConstant(0, VT); 1791 // X / undef -> undef 1792 if (N1.getOpcode() == ISD::UNDEF) 1793 return N1; 1794 1795 return SDValue(); 1796} 1797 1798SDValue DAGCombiner::visitSREM(SDNode *N) { 1799 SDValue N0 = N->getOperand(0); 1800 SDValue N1 = N->getOperand(1); 1801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1803 EVT VT = N->getValueType(0); 1804 1805 // fold (srem c1, c2) -> c1%c2 1806 if (N0C && N1C && !N1C->isNullValue()) 1807 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1808 // If we know the sign bits of both operands are zero, strength reduce to a 1809 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1810 if (!VT.isVector()) { 1811 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1812 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1813 } 1814 1815 // If X/C can be simplified by the division-by-constant logic, lower 1816 // X%C to the equivalent of X-X/C*C. 1817 if (N1C && !N1C->isNullValue()) { 1818 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1819 AddToWorkList(Div.getNode()); 1820 SDValue OptimizedDiv = combine(Div.getNode()); 1821 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1822 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1823 OptimizedDiv, N1); 1824 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1825 AddToWorkList(Mul.getNode()); 1826 return Sub; 1827 } 1828 } 1829 1830 // undef % X -> 0 1831 if (N0.getOpcode() == ISD::UNDEF) 1832 return DAG.getConstant(0, VT); 1833 // X % undef -> undef 1834 if (N1.getOpcode() == ISD::UNDEF) 1835 return N1; 1836 1837 return SDValue(); 1838} 1839 1840SDValue DAGCombiner::visitUREM(SDNode *N) { 1841 SDValue N0 = N->getOperand(0); 1842 SDValue N1 = N->getOperand(1); 1843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1845 EVT VT = N->getValueType(0); 1846 1847 // fold (urem c1, c2) -> c1%c2 1848 if (N0C && N1C && !N1C->isNullValue()) 1849 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1850 // fold (urem x, pow2) -> (and x, pow2-1) 1851 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1852 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1853 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1854 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1855 if (N1.getOpcode() == ISD::SHL) { 1856 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1857 if (SHC->getAPIntValue().isPowerOf2()) { 1858 SDValue Add = 1859 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1860 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1861 VT)); 1862 AddToWorkList(Add.getNode()); 1863 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1864 } 1865 } 1866 } 1867 1868 // If X/C can be simplified by the division-by-constant logic, lower 1869 // X%C to the equivalent of X-X/C*C. 1870 if (N1C && !N1C->isNullValue()) { 1871 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1872 AddToWorkList(Div.getNode()); 1873 SDValue OptimizedDiv = combine(Div.getNode()); 1874 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1875 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1876 OptimizedDiv, N1); 1877 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1878 AddToWorkList(Mul.getNode()); 1879 return Sub; 1880 } 1881 } 1882 1883 // undef % X -> 0 1884 if (N0.getOpcode() == ISD::UNDEF) 1885 return DAG.getConstant(0, VT); 1886 // X % undef -> undef 1887 if (N1.getOpcode() == ISD::UNDEF) 1888 return N1; 1889 1890 return SDValue(); 1891} 1892 1893SDValue DAGCombiner::visitMULHS(SDNode *N) { 1894 SDValue N0 = N->getOperand(0); 1895 SDValue N1 = N->getOperand(1); 1896 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1897 EVT VT = N->getValueType(0); 1898 1899 // fold (mulhs x, 0) -> 0 1900 if (N1C && N1C->isNullValue()) 1901 return N1; 1902 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1903 if (N1C && N1C->getAPIntValue() == 1) 1904 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1905 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1906 getShiftAmountTy())); 1907 // fold (mulhs x, undef) -> 0 1908 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1909 return DAG.getConstant(0, VT); 1910 1911 return SDValue(); 1912} 1913 1914SDValue DAGCombiner::visitMULHU(SDNode *N) { 1915 SDValue N0 = N->getOperand(0); 1916 SDValue N1 = N->getOperand(1); 1917 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1918 EVT VT = N->getValueType(0); 1919 1920 // fold (mulhu x, 0) -> 0 1921 if (N1C && N1C->isNullValue()) 1922 return N1; 1923 // fold (mulhu x, 1) -> 0 1924 if (N1C && N1C->getAPIntValue() == 1) 1925 return DAG.getConstant(0, N0.getValueType()); 1926 // fold (mulhu x, undef) -> 0 1927 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1928 return DAG.getConstant(0, VT); 1929 1930 return SDValue(); 1931} 1932 1933/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1934/// compute two values. LoOp and HiOp give the opcodes for the two computations 1935/// that are being performed. Return true if a simplification was made. 1936/// 1937SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1938 unsigned HiOp) { 1939 // If the high half is not needed, just compute the low half. 1940 bool HiExists = N->hasAnyUseOfValue(1); 1941 if (!HiExists && 1942 (!LegalOperations || 1943 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1944 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1945 N->op_begin(), N->getNumOperands()); 1946 return CombineTo(N, Res, Res); 1947 } 1948 1949 // If the low half is not needed, just compute the high half. 1950 bool LoExists = N->hasAnyUseOfValue(0); 1951 if (!LoExists && 1952 (!LegalOperations || 1953 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1954 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1955 N->op_begin(), N->getNumOperands()); 1956 return CombineTo(N, Res, Res); 1957 } 1958 1959 // If both halves are used, return as it is. 1960 if (LoExists && HiExists) 1961 return SDValue(); 1962 1963 // If the two computed results can be simplified separately, separate them. 1964 if (LoExists) { 1965 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1966 N->op_begin(), N->getNumOperands()); 1967 AddToWorkList(Lo.getNode()); 1968 SDValue LoOpt = combine(Lo.getNode()); 1969 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1970 (!LegalOperations || 1971 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1972 return CombineTo(N, LoOpt, LoOpt); 1973 } 1974 1975 if (HiExists) { 1976 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1977 N->op_begin(), N->getNumOperands()); 1978 AddToWorkList(Hi.getNode()); 1979 SDValue HiOpt = combine(Hi.getNode()); 1980 if (HiOpt.getNode() && HiOpt != Hi && 1981 (!LegalOperations || 1982 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1983 return CombineTo(N, HiOpt, HiOpt); 1984 } 1985 1986 return SDValue(); 1987} 1988 1989SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1990 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1991 if (Res.getNode()) return Res; 1992 1993 return SDValue(); 1994} 1995 1996SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1997 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1998 if (Res.getNode()) return Res; 1999 2000 return SDValue(); 2001} 2002 2003SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2004 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2005 if (Res.getNode()) return Res; 2006 2007 return SDValue(); 2008} 2009 2010SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2011 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2012 if (Res.getNode()) return Res; 2013 2014 return SDValue(); 2015} 2016 2017/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2018/// two operands of the same opcode, try to simplify it. 2019SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2020 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2021 EVT VT = N0.getValueType(); 2022 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2023 2024 // Bail early if none of these transforms apply. 2025 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2026 2027 // For each of OP in AND/OR/XOR: 2028 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2029 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2030 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2031 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2032 // 2033 // do not sink logical op inside of a vector extend, since it may combine 2034 // into a vsetcc. 2035 EVT Op0VT = N0.getOperand(0).getValueType(); 2036 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2037 N0.getOpcode() == ISD::SIGN_EXTEND || 2038 // Avoid infinite looping with PromoteIntBinOp. 2039 (N0.getOpcode() == ISD::ANY_EXTEND && 2040 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2041 (N0.getOpcode() == ISD::TRUNCATE && 2042 (!TLI.isZExtFree(VT, Op0VT) || 2043 !TLI.isTruncateFree(Op0VT, VT)) && 2044 TLI.isTypeLegal(Op0VT))) && 2045 !VT.isVector() && 2046 Op0VT == N1.getOperand(0).getValueType() && 2047 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2048 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2049 N0.getOperand(0).getValueType(), 2050 N0.getOperand(0), N1.getOperand(0)); 2051 AddToWorkList(ORNode.getNode()); 2052 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2053 } 2054 2055 // For each of OP in SHL/SRL/SRA/AND... 2056 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2057 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2058 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2059 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2060 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2061 N0.getOperand(1) == N1.getOperand(1)) { 2062 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2063 N0.getOperand(0).getValueType(), 2064 N0.getOperand(0), N1.getOperand(0)); 2065 AddToWorkList(ORNode.getNode()); 2066 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2067 ORNode, N0.getOperand(1)); 2068 } 2069 2070 return SDValue(); 2071} 2072 2073SDValue DAGCombiner::visitAND(SDNode *N) { 2074 SDValue N0 = N->getOperand(0); 2075 SDValue N1 = N->getOperand(1); 2076 SDValue LL, LR, RL, RR, CC0, CC1; 2077 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2078 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2079 EVT VT = N1.getValueType(); 2080 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2081 2082 // fold vector ops 2083 if (VT.isVector()) { 2084 SDValue FoldedVOp = SimplifyVBinOp(N); 2085 if (FoldedVOp.getNode()) return FoldedVOp; 2086 } 2087 2088 // fold (and x, undef) -> 0 2089 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2090 return DAG.getConstant(0, VT); 2091 // fold (and c1, c2) -> c1&c2 2092 if (N0C && N1C) 2093 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2094 // canonicalize constant to RHS 2095 if (N0C && !N1C) 2096 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2097 // fold (and x, -1) -> x 2098 if (N1C && N1C->isAllOnesValue()) 2099 return N0; 2100 // if (and x, c) is known to be zero, return 0 2101 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2102 APInt::getAllOnesValue(BitWidth))) 2103 return DAG.getConstant(0, VT); 2104 // reassociate and 2105 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2106 if (RAND.getNode() != 0) 2107 return RAND; 2108 // fold (and (or x, C), D) -> D if (C & D) == D 2109 if (N1C && N0.getOpcode() == ISD::OR) 2110 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2111 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2112 return N1; 2113 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2114 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2115 SDValue N0Op0 = N0.getOperand(0); 2116 APInt Mask = ~N1C->getAPIntValue(); 2117 Mask.trunc(N0Op0.getValueSizeInBits()); 2118 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2119 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2120 N0.getValueType(), N0Op0); 2121 2122 // Replace uses of the AND with uses of the Zero extend node. 2123 CombineTo(N, Zext); 2124 2125 // We actually want to replace all uses of the any_extend with the 2126 // zero_extend, to avoid duplicating things. This will later cause this 2127 // AND to be folded. 2128 CombineTo(N0.getNode(), Zext); 2129 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2130 } 2131 } 2132 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2133 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2134 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2135 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2136 2137 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2138 LL.getValueType().isInteger()) { 2139 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2140 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2141 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2142 LR.getValueType(), LL, RL); 2143 AddToWorkList(ORNode.getNode()); 2144 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2145 } 2146 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2147 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2148 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2149 LR.getValueType(), LL, RL); 2150 AddToWorkList(ANDNode.getNode()); 2151 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2152 } 2153 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2154 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2155 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2156 LR.getValueType(), LL, RL); 2157 AddToWorkList(ORNode.getNode()); 2158 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2159 } 2160 } 2161 // canonicalize equivalent to ll == rl 2162 if (LL == RR && LR == RL) { 2163 Op1 = ISD::getSetCCSwappedOperands(Op1); 2164 std::swap(RL, RR); 2165 } 2166 if (LL == RL && LR == RR) { 2167 bool isInteger = LL.getValueType().isInteger(); 2168 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2169 if (Result != ISD::SETCC_INVALID && 2170 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2171 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2172 LL, LR, Result); 2173 } 2174 } 2175 2176 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2177 if (N0.getOpcode() == N1.getOpcode()) { 2178 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2179 if (Tmp.getNode()) return Tmp; 2180 } 2181 2182 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2183 // fold (and (sra)) -> (and (srl)) when possible. 2184 if (!VT.isVector() && 2185 SimplifyDemandedBits(SDValue(N, 0))) 2186 return SDValue(N, 0); 2187 2188 // fold (zext_inreg (extload x)) -> (zextload x) 2189 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2190 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2191 EVT MemVT = LN0->getMemoryVT(); 2192 // If we zero all the possible extended bits, then we can turn this into 2193 // a zextload if we are running before legalize or the operation is legal. 2194 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2195 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2196 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2197 ((!LegalOperations && !LN0->isVolatile()) || 2198 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2199 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2200 LN0->getChain(), LN0->getBasePtr(), 2201 LN0->getSrcValue(), 2202 LN0->getSrcValueOffset(), MemVT, 2203 LN0->isVolatile(), LN0->isNonTemporal(), 2204 LN0->getAlignment()); 2205 AddToWorkList(N); 2206 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2207 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2208 } 2209 } 2210 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2211 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2212 N0.hasOneUse()) { 2213 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2214 EVT MemVT = LN0->getMemoryVT(); 2215 // If we zero all the possible extended bits, then we can turn this into 2216 // a zextload if we are running before legalize or the operation is legal. 2217 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2218 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2219 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2220 ((!LegalOperations && !LN0->isVolatile()) || 2221 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2222 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2223 LN0->getChain(), 2224 LN0->getBasePtr(), LN0->getSrcValue(), 2225 LN0->getSrcValueOffset(), MemVT, 2226 LN0->isVolatile(), LN0->isNonTemporal(), 2227 LN0->getAlignment()); 2228 AddToWorkList(N); 2229 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2230 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2231 } 2232 } 2233 2234 // fold (and (load x), 255) -> (zextload x, i8) 2235 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2236 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2237 if (N1C && (N0.getOpcode() == ISD::LOAD || 2238 (N0.getOpcode() == ISD::ANY_EXTEND && 2239 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2240 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2241 LoadSDNode *LN0 = HasAnyExt 2242 ? cast<LoadSDNode>(N0.getOperand(0)) 2243 : cast<LoadSDNode>(N0); 2244 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2245 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2246 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2247 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2248 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2249 EVT LoadedVT = LN0->getMemoryVT(); 2250 2251 if (ExtVT == LoadedVT && 2252 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2253 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2254 2255 SDValue NewLoad = 2256 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2257 LN0->getChain(), LN0->getBasePtr(), 2258 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2259 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2260 LN0->getAlignment()); 2261 AddToWorkList(N); 2262 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2263 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2264 } 2265 2266 // Do not change the width of a volatile load. 2267 // Do not generate loads of non-round integer types since these can 2268 // be expensive (and would be wrong if the type is not byte sized). 2269 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2270 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2271 EVT PtrType = LN0->getOperand(1).getValueType(); 2272 2273 unsigned Alignment = LN0->getAlignment(); 2274 SDValue NewPtr = LN0->getBasePtr(); 2275 2276 // For big endian targets, we need to add an offset to the pointer 2277 // to load the correct bytes. For little endian systems, we merely 2278 // need to read fewer bytes from the same pointer. 2279 if (TLI.isBigEndian()) { 2280 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2281 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2282 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2283 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2284 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2285 Alignment = MinAlign(Alignment, PtrOff); 2286 } 2287 2288 AddToWorkList(NewPtr.getNode()); 2289 2290 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2291 SDValue Load = 2292 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2293 LN0->getChain(), NewPtr, 2294 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2295 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2296 Alignment); 2297 AddToWorkList(N); 2298 CombineTo(LN0, Load, Load.getValue(1)); 2299 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2300 } 2301 } 2302 } 2303 } 2304 2305 return SDValue(); 2306} 2307 2308SDValue DAGCombiner::visitOR(SDNode *N) { 2309 SDValue N0 = N->getOperand(0); 2310 SDValue N1 = N->getOperand(1); 2311 SDValue LL, LR, RL, RR, CC0, CC1; 2312 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2313 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2314 EVT VT = N1.getValueType(); 2315 2316 // fold vector ops 2317 if (VT.isVector()) { 2318 SDValue FoldedVOp = SimplifyVBinOp(N); 2319 if (FoldedVOp.getNode()) return FoldedVOp; 2320 } 2321 2322 // fold (or x, undef) -> -1 2323 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 2324 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2325 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2326 } 2327 // fold (or c1, c2) -> c1|c2 2328 if (N0C && N1C) 2329 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2330 // canonicalize constant to RHS 2331 if (N0C && !N1C) 2332 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2333 // fold (or x, 0) -> x 2334 if (N1C && N1C->isNullValue()) 2335 return N0; 2336 // fold (or x, -1) -> -1 2337 if (N1C && N1C->isAllOnesValue()) 2338 return N1; 2339 // fold (or x, c) -> c iff (x & ~c) == 0 2340 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2341 return N1; 2342 // reassociate or 2343 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2344 if (ROR.getNode() != 0) 2345 return ROR; 2346 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2347 // iff (c1 & c2) == 0. 2348 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2349 isa<ConstantSDNode>(N0.getOperand(1))) { 2350 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2351 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2352 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2353 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2354 N0.getOperand(0), N1), 2355 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2356 } 2357 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2358 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2359 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2360 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2361 2362 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2363 LL.getValueType().isInteger()) { 2364 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2365 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2366 if (cast<ConstantSDNode>(LR)->isNullValue() && 2367 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2368 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2369 LR.getValueType(), LL, RL); 2370 AddToWorkList(ORNode.getNode()); 2371 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2372 } 2373 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2374 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2375 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2376 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2377 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2378 LR.getValueType(), LL, RL); 2379 AddToWorkList(ANDNode.getNode()); 2380 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2381 } 2382 } 2383 // canonicalize equivalent to ll == rl 2384 if (LL == RR && LR == RL) { 2385 Op1 = ISD::getSetCCSwappedOperands(Op1); 2386 std::swap(RL, RR); 2387 } 2388 if (LL == RL && LR == RR) { 2389 bool isInteger = LL.getValueType().isInteger(); 2390 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2391 if (Result != ISD::SETCC_INVALID && 2392 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2393 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2394 LL, LR, Result); 2395 } 2396 } 2397 2398 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2399 if (N0.getOpcode() == N1.getOpcode()) { 2400 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2401 if (Tmp.getNode()) return Tmp; 2402 } 2403 2404 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2405 if (N0.getOpcode() == ISD::AND && 2406 N1.getOpcode() == ISD::AND && 2407 N0.getOperand(1).getOpcode() == ISD::Constant && 2408 N1.getOperand(1).getOpcode() == ISD::Constant && 2409 // Don't increase # computations. 2410 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2411 // We can only do this xform if we know that bits from X that are set in C2 2412 // but not in C1 are already zero. Likewise for Y. 2413 const APInt &LHSMask = 2414 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2415 const APInt &RHSMask = 2416 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2417 2418 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2419 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2420 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2421 N0.getOperand(0), N1.getOperand(0)); 2422 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2423 DAG.getConstant(LHSMask | RHSMask, VT)); 2424 } 2425 } 2426 2427 // See if this is some rotate idiom. 2428 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2429 return SDValue(Rot, 0); 2430 2431 // Simplify the operands using demanded-bits information. 2432 if (!VT.isVector() && 2433 SimplifyDemandedBits(SDValue(N, 0))) 2434 return SDValue(N, 0); 2435 2436 return SDValue(); 2437} 2438 2439/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2440static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2441 if (Op.getOpcode() == ISD::AND) { 2442 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2443 Mask = Op.getOperand(1); 2444 Op = Op.getOperand(0); 2445 } else { 2446 return false; 2447 } 2448 } 2449 2450 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2451 Shift = Op; 2452 return true; 2453 } 2454 2455 return false; 2456} 2457 2458// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2459// idioms for rotate, and if the target supports rotation instructions, generate 2460// a rot[lr]. 2461SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2462 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2463 EVT VT = LHS.getValueType(); 2464 if (!TLI.isTypeLegal(VT)) return 0; 2465 2466 // The target must have at least one rotate flavor. 2467 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2468 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2469 if (!HasROTL && !HasROTR) return 0; 2470 2471 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2472 SDValue LHSShift; // The shift. 2473 SDValue LHSMask; // AND value if any. 2474 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2475 return 0; // Not part of a rotate. 2476 2477 SDValue RHSShift; // The shift. 2478 SDValue RHSMask; // AND value if any. 2479 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2480 return 0; // Not part of a rotate. 2481 2482 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2483 return 0; // Not shifting the same value. 2484 2485 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2486 return 0; // Shifts must disagree. 2487 2488 // Canonicalize shl to left side in a shl/srl pair. 2489 if (RHSShift.getOpcode() == ISD::SHL) { 2490 std::swap(LHS, RHS); 2491 std::swap(LHSShift, RHSShift); 2492 std::swap(LHSMask , RHSMask ); 2493 } 2494 2495 unsigned OpSizeInBits = VT.getSizeInBits(); 2496 SDValue LHSShiftArg = LHSShift.getOperand(0); 2497 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2498 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2499 2500 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2501 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2502 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2503 RHSShiftAmt.getOpcode() == ISD::Constant) { 2504 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2505 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2506 if ((LShVal + RShVal) != OpSizeInBits) 2507 return 0; 2508 2509 SDValue Rot; 2510 if (HasROTL) 2511 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2512 else 2513 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2514 2515 // If there is an AND of either shifted operand, apply it to the result. 2516 if (LHSMask.getNode() || RHSMask.getNode()) { 2517 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2518 2519 if (LHSMask.getNode()) { 2520 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2521 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2522 } 2523 if (RHSMask.getNode()) { 2524 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2525 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2526 } 2527 2528 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2529 } 2530 2531 return Rot.getNode(); 2532 } 2533 2534 // If there is a mask here, and we have a variable shift, we can't be sure 2535 // that we're masking out the right stuff. 2536 if (LHSMask.getNode() || RHSMask.getNode()) 2537 return 0; 2538 2539 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2540 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2541 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2542 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2543 if (ConstantSDNode *SUBC = 2544 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2545 if (SUBC->getAPIntValue() == OpSizeInBits) { 2546 if (HasROTL) 2547 return DAG.getNode(ISD::ROTL, DL, VT, 2548 LHSShiftArg, LHSShiftAmt).getNode(); 2549 else 2550 return DAG.getNode(ISD::ROTR, DL, VT, 2551 LHSShiftArg, RHSShiftAmt).getNode(); 2552 } 2553 } 2554 } 2555 2556 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2557 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2558 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2559 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2560 if (ConstantSDNode *SUBC = 2561 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2562 if (SUBC->getAPIntValue() == OpSizeInBits) { 2563 if (HasROTR) 2564 return DAG.getNode(ISD::ROTR, DL, VT, 2565 LHSShiftArg, RHSShiftAmt).getNode(); 2566 else 2567 return DAG.getNode(ISD::ROTL, DL, VT, 2568 LHSShiftArg, LHSShiftAmt).getNode(); 2569 } 2570 } 2571 } 2572 2573 // Look for sign/zext/any-extended or truncate cases: 2574 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2575 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2576 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2577 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2578 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2579 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2580 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2581 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2582 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2583 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2584 if (RExtOp0.getOpcode() == ISD::SUB && 2585 RExtOp0.getOperand(1) == LExtOp0) { 2586 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2587 // (rotl x, y) 2588 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2589 // (rotr x, (sub 32, y)) 2590 if (ConstantSDNode *SUBC = 2591 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2592 if (SUBC->getAPIntValue() == OpSizeInBits) { 2593 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2594 LHSShiftArg, 2595 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2596 } 2597 } 2598 } else if (LExtOp0.getOpcode() == ISD::SUB && 2599 RExtOp0 == LExtOp0.getOperand(1)) { 2600 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2601 // (rotr x, y) 2602 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2603 // (rotl x, (sub 32, y)) 2604 if (ConstantSDNode *SUBC = 2605 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2606 if (SUBC->getAPIntValue() == OpSizeInBits) { 2607 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2608 LHSShiftArg, 2609 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2610 } 2611 } 2612 } 2613 } 2614 2615 return 0; 2616} 2617 2618SDValue DAGCombiner::visitXOR(SDNode *N) { 2619 SDValue N0 = N->getOperand(0); 2620 SDValue N1 = N->getOperand(1); 2621 SDValue LHS, RHS, CC; 2622 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2623 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2624 EVT VT = N0.getValueType(); 2625 2626 // fold vector ops 2627 if (VT.isVector()) { 2628 SDValue FoldedVOp = SimplifyVBinOp(N); 2629 if (FoldedVOp.getNode()) return FoldedVOp; 2630 } 2631 2632 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2633 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2634 return DAG.getConstant(0, VT); 2635 // fold (xor x, undef) -> undef 2636 if (N0.getOpcode() == ISD::UNDEF) 2637 return N0; 2638 if (N1.getOpcode() == ISD::UNDEF) 2639 return N1; 2640 // fold (xor c1, c2) -> c1^c2 2641 if (N0C && N1C) 2642 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2643 // canonicalize constant to RHS 2644 if (N0C && !N1C) 2645 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2646 // fold (xor x, 0) -> x 2647 if (N1C && N1C->isNullValue()) 2648 return N0; 2649 // reassociate xor 2650 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2651 if (RXOR.getNode() != 0) 2652 return RXOR; 2653 2654 // fold !(x cc y) -> (x !cc y) 2655 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2656 bool isInt = LHS.getValueType().isInteger(); 2657 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2658 isInt); 2659 2660 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2661 switch (N0.getOpcode()) { 2662 default: 2663 llvm_unreachable("Unhandled SetCC Equivalent!"); 2664 case ISD::SETCC: 2665 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2666 case ISD::SELECT_CC: 2667 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2668 N0.getOperand(3), NotCC); 2669 } 2670 } 2671 } 2672 2673 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2674 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2675 N0.getNode()->hasOneUse() && 2676 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2677 SDValue V = N0.getOperand(0); 2678 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2679 DAG.getConstant(1, V.getValueType())); 2680 AddToWorkList(V.getNode()); 2681 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2682 } 2683 2684 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2685 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2686 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2687 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2688 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2689 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2690 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2691 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2692 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2693 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2694 } 2695 } 2696 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2697 if (N1C && N1C->isAllOnesValue() && 2698 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2699 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2700 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2701 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2702 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2703 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2704 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2705 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2706 } 2707 } 2708 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2709 if (N1C && N0.getOpcode() == ISD::XOR) { 2710 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2711 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2712 if (N00C) 2713 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2714 DAG.getConstant(N1C->getAPIntValue() ^ 2715 N00C->getAPIntValue(), VT)); 2716 if (N01C) 2717 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2718 DAG.getConstant(N1C->getAPIntValue() ^ 2719 N01C->getAPIntValue(), VT)); 2720 } 2721 // fold (xor x, x) -> 0 2722 if (N0 == N1) { 2723 if (!VT.isVector()) { 2724 return DAG.getConstant(0, VT); 2725 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2726 // Produce a vector of zeros. 2727 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2728 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2729 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2730 &Ops[0], Ops.size()); 2731 } 2732 } 2733 2734 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2735 if (N0.getOpcode() == N1.getOpcode()) { 2736 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2737 if (Tmp.getNode()) return Tmp; 2738 } 2739 2740 // Simplify the expression using non-local knowledge. 2741 if (!VT.isVector() && 2742 SimplifyDemandedBits(SDValue(N, 0))) 2743 return SDValue(N, 0); 2744 2745 return SDValue(); 2746} 2747 2748/// visitShiftByConstant - Handle transforms common to the three shifts, when 2749/// the shift amount is a constant. 2750SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2751 SDNode *LHS = N->getOperand(0).getNode(); 2752 if (!LHS->hasOneUse()) return SDValue(); 2753 2754 // We want to pull some binops through shifts, so that we have (and (shift)) 2755 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2756 // thing happens with address calculations, so it's important to canonicalize 2757 // it. 2758 bool HighBitSet = false; // Can we transform this if the high bit is set? 2759 2760 switch (LHS->getOpcode()) { 2761 default: return SDValue(); 2762 case ISD::OR: 2763 case ISD::XOR: 2764 HighBitSet = false; // We can only transform sra if the high bit is clear. 2765 break; 2766 case ISD::AND: 2767 HighBitSet = true; // We can only transform sra if the high bit is set. 2768 break; 2769 case ISD::ADD: 2770 if (N->getOpcode() != ISD::SHL) 2771 return SDValue(); // only shl(add) not sr[al](add). 2772 HighBitSet = false; // We can only transform sra if the high bit is clear. 2773 break; 2774 } 2775 2776 // We require the RHS of the binop to be a constant as well. 2777 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2778 if (!BinOpCst) return SDValue(); 2779 2780 // FIXME: disable this unless the input to the binop is a shift by a constant. 2781 // If it is not a shift, it pessimizes some common cases like: 2782 // 2783 // void foo(int *X, int i) { X[i & 1235] = 1; } 2784 // int bar(int *X, int i) { return X[i & 255]; } 2785 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2786 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2787 BinOpLHSVal->getOpcode() != ISD::SRA && 2788 BinOpLHSVal->getOpcode() != ISD::SRL) || 2789 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2790 return SDValue(); 2791 2792 EVT VT = N->getValueType(0); 2793 2794 // If this is a signed shift right, and the high bit is modified by the 2795 // logical operation, do not perform the transformation. The highBitSet 2796 // boolean indicates the value of the high bit of the constant which would 2797 // cause it to be modified for this operation. 2798 if (N->getOpcode() == ISD::SRA) { 2799 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2800 if (BinOpRHSSignSet != HighBitSet) 2801 return SDValue(); 2802 } 2803 2804 // Fold the constants, shifting the binop RHS by the shift amount. 2805 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2806 N->getValueType(0), 2807 LHS->getOperand(1), N->getOperand(1)); 2808 2809 // Create the new shift. 2810 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2811 VT, LHS->getOperand(0), N->getOperand(1)); 2812 2813 // Create the new binop. 2814 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2815} 2816 2817SDValue DAGCombiner::visitSHL(SDNode *N) { 2818 SDValue N0 = N->getOperand(0); 2819 SDValue N1 = N->getOperand(1); 2820 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2821 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2822 EVT VT = N0.getValueType(); 2823 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2824 2825 // fold (shl c1, c2) -> c1<<c2 2826 if (N0C && N1C) 2827 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2828 // fold (shl 0, x) -> 0 2829 if (N0C && N0C->isNullValue()) 2830 return N0; 2831 // fold (shl x, c >= size(x)) -> undef 2832 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2833 return DAG.getUNDEF(VT); 2834 // fold (shl x, 0) -> x 2835 if (N1C && N1C->isNullValue()) 2836 return N0; 2837 // if (shl x, c) is known to be zero, return 0 2838 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2839 APInt::getAllOnesValue(OpSizeInBits))) 2840 return DAG.getConstant(0, VT); 2841 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2842 if (N1.getOpcode() == ISD::TRUNCATE && 2843 N1.getOperand(0).getOpcode() == ISD::AND && 2844 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2845 SDValue N101 = N1.getOperand(0).getOperand(1); 2846 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2847 EVT TruncVT = N1.getValueType(); 2848 SDValue N100 = N1.getOperand(0).getOperand(0); 2849 APInt TruncC = N101C->getAPIntValue(); 2850 TruncC.trunc(TruncVT.getSizeInBits()); 2851 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2852 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2853 DAG.getNode(ISD::TRUNCATE, 2854 N->getDebugLoc(), 2855 TruncVT, N100), 2856 DAG.getConstant(TruncC, TruncVT))); 2857 } 2858 } 2859 2860 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2861 return SDValue(N, 0); 2862 2863 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2864 if (N1C && N0.getOpcode() == ISD::SHL && 2865 N0.getOperand(1).getOpcode() == ISD::Constant) { 2866 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2867 uint64_t c2 = N1C->getZExtValue(); 2868 if (c1 + c2 > OpSizeInBits) 2869 return DAG.getConstant(0, VT); 2870 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2871 DAG.getConstant(c1 + c2, N1.getValueType())); 2872 } 2873 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2874 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2875 if (N1C && N0.getOpcode() == ISD::SRL && 2876 N0.getOperand(1).getOpcode() == ISD::Constant) { 2877 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2878 if (c1 < VT.getSizeInBits()) { 2879 uint64_t c2 = N1C->getZExtValue(); 2880 SDValue HiBitsMask = 2881 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2882 VT.getSizeInBits() - c1), 2883 VT); 2884 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2885 N0.getOperand(0), 2886 HiBitsMask); 2887 if (c2 > c1) 2888 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2889 DAG.getConstant(c2-c1, N1.getValueType())); 2890 else 2891 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2892 DAG.getConstant(c1-c2, N1.getValueType())); 2893 } 2894 } 2895 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2896 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2897 SDValue HiBitsMask = 2898 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2899 VT.getSizeInBits() - 2900 N1C->getZExtValue()), 2901 VT); 2902 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2903 HiBitsMask); 2904 } 2905 2906 if (N1C) { 2907 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 2908 if (NewSHL.getNode()) 2909 return NewSHL; 2910 } 2911 2912 return SDValue(); 2913} 2914 2915SDValue DAGCombiner::visitSRA(SDNode *N) { 2916 SDValue N0 = N->getOperand(0); 2917 SDValue N1 = N->getOperand(1); 2918 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2919 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2920 EVT VT = N0.getValueType(); 2921 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2922 2923 // fold (sra c1, c2) -> (sra c1, c2) 2924 if (N0C && N1C) 2925 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2926 // fold (sra 0, x) -> 0 2927 if (N0C && N0C->isNullValue()) 2928 return N0; 2929 // fold (sra -1, x) -> -1 2930 if (N0C && N0C->isAllOnesValue()) 2931 return N0; 2932 // fold (sra x, (setge c, size(x))) -> undef 2933 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2934 return DAG.getUNDEF(VT); 2935 // fold (sra x, 0) -> x 2936 if (N1C && N1C->isNullValue()) 2937 return N0; 2938 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2939 // sext_inreg. 2940 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2941 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2942 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2943 if (VT.isVector()) 2944 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2945 ExtVT, VT.getVectorNumElements()); 2946 if ((!LegalOperations || 2947 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2948 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2949 N0.getOperand(0), DAG.getValueType(ExtVT)); 2950 } 2951 2952 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2953 if (N1C && N0.getOpcode() == ISD::SRA) { 2954 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2955 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2956 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2957 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2958 DAG.getConstant(Sum, N1C->getValueType(0))); 2959 } 2960 } 2961 2962 // fold (sra (shl X, m), (sub result_size, n)) 2963 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2964 // result_size - n != m. 2965 // If truncate is free for the target sext(shl) is likely to result in better 2966 // code. 2967 if (N0.getOpcode() == ISD::SHL) { 2968 // Get the two constanst of the shifts, CN0 = m, CN = n. 2969 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2970 if (N01C && N1C) { 2971 // Determine what the truncate's result bitsize and type would be. 2972 EVT TruncVT = 2973 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2974 // Determine the residual right-shift amount. 2975 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2976 2977 // If the shift is not a no-op (in which case this should be just a sign 2978 // extend already), the truncated to type is legal, sign_extend is legal 2979 // on that type, and the truncate to that type is both legal and free, 2980 // perform the transform. 2981 if ((ShiftAmt > 0) && 2982 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2983 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2984 TLI.isTruncateFree(VT, TruncVT)) { 2985 2986 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2987 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2988 N0.getOperand(0), Amt); 2989 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2990 Shift); 2991 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2992 N->getValueType(0), Trunc); 2993 } 2994 } 2995 } 2996 2997 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2998 if (N1.getOpcode() == ISD::TRUNCATE && 2999 N1.getOperand(0).getOpcode() == ISD::AND && 3000 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3001 SDValue N101 = N1.getOperand(0).getOperand(1); 3002 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3003 EVT TruncVT = N1.getValueType(); 3004 SDValue N100 = N1.getOperand(0).getOperand(0); 3005 APInt TruncC = N101C->getAPIntValue(); 3006 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3007 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3008 DAG.getNode(ISD::AND, N->getDebugLoc(), 3009 TruncVT, 3010 DAG.getNode(ISD::TRUNCATE, 3011 N->getDebugLoc(), 3012 TruncVT, N100), 3013 DAG.getConstant(TruncC, TruncVT))); 3014 } 3015 } 3016 3017 // Simplify, based on bits shifted out of the LHS. 3018 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3019 return SDValue(N, 0); 3020 3021 3022 // If the sign bit is known to be zero, switch this to a SRL. 3023 if (DAG.SignBitIsZero(N0)) 3024 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3025 3026 if (N1C) { 3027 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3028 if (NewSRA.getNode()) 3029 return NewSRA; 3030 } 3031 3032 return SDValue(); 3033} 3034 3035SDValue DAGCombiner::visitSRL(SDNode *N) { 3036 SDValue N0 = N->getOperand(0); 3037 SDValue N1 = N->getOperand(1); 3038 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3039 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3040 EVT VT = N0.getValueType(); 3041 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3042 3043 // fold (srl c1, c2) -> c1 >>u c2 3044 if (N0C && N1C) 3045 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3046 // fold (srl 0, x) -> 0 3047 if (N0C && N0C->isNullValue()) 3048 return N0; 3049 // fold (srl x, c >= size(x)) -> undef 3050 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3051 return DAG.getUNDEF(VT); 3052 // fold (srl x, 0) -> x 3053 if (N1C && N1C->isNullValue()) 3054 return N0; 3055 // if (srl x, c) is known to be zero, return 0 3056 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3057 APInt::getAllOnesValue(OpSizeInBits))) 3058 return DAG.getConstant(0, VT); 3059 3060 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3061 if (N1C && N0.getOpcode() == ISD::SRL && 3062 N0.getOperand(1).getOpcode() == ISD::Constant) { 3063 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3064 uint64_t c2 = N1C->getZExtValue(); 3065 if (c1 + c2 > OpSizeInBits) 3066 return DAG.getConstant(0, VT); 3067 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3068 DAG.getConstant(c1 + c2, N1.getValueType())); 3069 } 3070 3071 // fold (srl (shl x, c), c) -> (and x, cst2) 3072 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3073 N0.getValueSizeInBits() <= 64) { 3074 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3075 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3076 DAG.getConstant(~0ULL >> ShAmt, VT)); 3077 } 3078 3079 3080 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3081 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3082 // Shifting in all undef bits? 3083 EVT SmallVT = N0.getOperand(0).getValueType(); 3084 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3085 return DAG.getUNDEF(VT); 3086 3087 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3088 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3089 N0.getOperand(0), N1); 3090 AddToWorkList(SmallShift.getNode()); 3091 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3092 } 3093 } 3094 3095 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3096 // bit, which is unmodified by sra. 3097 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3098 if (N0.getOpcode() == ISD::SRA) 3099 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3100 } 3101 3102 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3103 if (N1C && N0.getOpcode() == ISD::CTLZ && 3104 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3105 APInt KnownZero, KnownOne; 3106 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3107 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3108 3109 // If any of the input bits are KnownOne, then the input couldn't be all 3110 // zeros, thus the result of the srl will always be zero. 3111 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3112 3113 // If all of the bits input the to ctlz node are known to be zero, then 3114 // the result of the ctlz is "32" and the result of the shift is one. 3115 APInt UnknownBits = ~KnownZero & Mask; 3116 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3117 3118 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3119 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3120 // Okay, we know that only that the single bit specified by UnknownBits 3121 // could be set on input to the CTLZ node. If this bit is set, the SRL 3122 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3123 // to an SRL/XOR pair, which is likely to simplify more. 3124 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3125 SDValue Op = N0.getOperand(0); 3126 3127 if (ShAmt) { 3128 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3129 DAG.getConstant(ShAmt, getShiftAmountTy())); 3130 AddToWorkList(Op.getNode()); 3131 } 3132 3133 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3134 Op, DAG.getConstant(1, VT)); 3135 } 3136 } 3137 3138 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3139 if (N1.getOpcode() == ISD::TRUNCATE && 3140 N1.getOperand(0).getOpcode() == ISD::AND && 3141 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3142 SDValue N101 = N1.getOperand(0).getOperand(1); 3143 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3144 EVT TruncVT = N1.getValueType(); 3145 SDValue N100 = N1.getOperand(0).getOperand(0); 3146 APInt TruncC = N101C->getAPIntValue(); 3147 TruncC.trunc(TruncVT.getSizeInBits()); 3148 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3149 DAG.getNode(ISD::AND, N->getDebugLoc(), 3150 TruncVT, 3151 DAG.getNode(ISD::TRUNCATE, 3152 N->getDebugLoc(), 3153 TruncVT, N100), 3154 DAG.getConstant(TruncC, TruncVT))); 3155 } 3156 } 3157 3158 // fold operands of srl based on knowledge that the low bits are not 3159 // demanded. 3160 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3161 return SDValue(N, 0); 3162 3163 if (N1C) { 3164 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3165 if (NewSRL.getNode()) 3166 return NewSRL; 3167 } 3168 3169 // Attempt to convert a srl of a load into a narrower zero-extending load. 3170 SDValue NarrowLoad = ReduceLoadWidth(N); 3171 if (NarrowLoad.getNode()) 3172 return NarrowLoad; 3173 3174 // Here is a common situation. We want to optimize: 3175 // 3176 // %a = ... 3177 // %b = and i32 %a, 2 3178 // %c = srl i32 %b, 1 3179 // brcond i32 %c ... 3180 // 3181 // into 3182 // 3183 // %a = ... 3184 // %b = and %a, 2 3185 // %c = setcc eq %b, 0 3186 // brcond %c ... 3187 // 3188 // However when after the source operand of SRL is optimized into AND, the SRL 3189 // itself may not be optimized further. Look for it and add the BRCOND into 3190 // the worklist. 3191 if (N->hasOneUse()) { 3192 SDNode *Use = *N->use_begin(); 3193 if (Use->getOpcode() == ISD::BRCOND) 3194 AddToWorkList(Use); 3195 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3196 // Also look pass the truncate. 3197 Use = *Use->use_begin(); 3198 if (Use->getOpcode() == ISD::BRCOND) 3199 AddToWorkList(Use); 3200 } 3201 } 3202 3203 return SDValue(); 3204} 3205 3206SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3207 SDValue N0 = N->getOperand(0); 3208 EVT VT = N->getValueType(0); 3209 3210 // fold (ctlz c1) -> c2 3211 if (isa<ConstantSDNode>(N0)) 3212 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3213 return SDValue(); 3214} 3215 3216SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3217 SDValue N0 = N->getOperand(0); 3218 EVT VT = N->getValueType(0); 3219 3220 // fold (cttz c1) -> c2 3221 if (isa<ConstantSDNode>(N0)) 3222 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3223 return SDValue(); 3224} 3225 3226SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3227 SDValue N0 = N->getOperand(0); 3228 EVT VT = N->getValueType(0); 3229 3230 // fold (ctpop c1) -> c2 3231 if (isa<ConstantSDNode>(N0)) 3232 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3233 return SDValue(); 3234} 3235 3236SDValue DAGCombiner::visitSELECT(SDNode *N) { 3237 SDValue N0 = N->getOperand(0); 3238 SDValue N1 = N->getOperand(1); 3239 SDValue N2 = N->getOperand(2); 3240 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3241 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3242 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3243 EVT VT = N->getValueType(0); 3244 EVT VT0 = N0.getValueType(); 3245 3246 // fold (select C, X, X) -> X 3247 if (N1 == N2) 3248 return N1; 3249 // fold (select true, X, Y) -> X 3250 if (N0C && !N0C->isNullValue()) 3251 return N1; 3252 // fold (select false, X, Y) -> Y 3253 if (N0C && N0C->isNullValue()) 3254 return N2; 3255 // fold (select C, 1, X) -> (or C, X) 3256 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3257 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3258 // fold (select C, 0, 1) -> (xor C, 1) 3259 if (VT.isInteger() && 3260 (VT0 == MVT::i1 || 3261 (VT0.isInteger() && 3262 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3263 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3264 SDValue XORNode; 3265 if (VT == VT0) 3266 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3267 N0, DAG.getConstant(1, VT0)); 3268 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3269 N0, DAG.getConstant(1, VT0)); 3270 AddToWorkList(XORNode.getNode()); 3271 if (VT.bitsGT(VT0)) 3272 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3273 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3274 } 3275 // fold (select C, 0, X) -> (and (not C), X) 3276 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3277 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3278 AddToWorkList(NOTNode.getNode()); 3279 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3280 } 3281 // fold (select C, X, 1) -> (or (not C), X) 3282 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3283 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3284 AddToWorkList(NOTNode.getNode()); 3285 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3286 } 3287 // fold (select C, X, 0) -> (and C, X) 3288 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3289 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3290 // fold (select X, X, Y) -> (or X, Y) 3291 // fold (select X, 1, Y) -> (or X, Y) 3292 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3293 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3294 // fold (select X, Y, X) -> (and X, Y) 3295 // fold (select X, Y, 0) -> (and X, Y) 3296 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3297 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3298 3299 // If we can fold this based on the true/false value, do so. 3300 if (SimplifySelectOps(N, N1, N2)) 3301 return SDValue(N, 0); // Don't revisit N. 3302 3303 // fold selects based on a setcc into other things, such as min/max/abs 3304 if (N0.getOpcode() == ISD::SETCC) { 3305 // FIXME: 3306 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3307 // having to say they don't support SELECT_CC on every type the DAG knows 3308 // about, since there is no way to mark an opcode illegal at all value types 3309 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3310 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3311 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3312 N0.getOperand(0), N0.getOperand(1), 3313 N1, N2, N0.getOperand(2)); 3314 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3315 } 3316 3317 return SDValue(); 3318} 3319 3320SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3321 SDValue N0 = N->getOperand(0); 3322 SDValue N1 = N->getOperand(1); 3323 SDValue N2 = N->getOperand(2); 3324 SDValue N3 = N->getOperand(3); 3325 SDValue N4 = N->getOperand(4); 3326 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3327 3328 // fold select_cc lhs, rhs, x, x, cc -> x 3329 if (N2 == N3) 3330 return N2; 3331 3332 // Determine if the condition we're dealing with is constant 3333 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3334 N0, N1, CC, N->getDebugLoc(), false); 3335 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3336 3337 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3338 if (!SCCC->isNullValue()) 3339 return N2; // cond always true -> true val 3340 else 3341 return N3; // cond always false -> false val 3342 } 3343 3344 // Fold to a simpler select_cc 3345 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3346 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3347 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3348 SCC.getOperand(2)); 3349 3350 // If we can fold this based on the true/false value, do so. 3351 if (SimplifySelectOps(N, N2, N3)) 3352 return SDValue(N, 0); // Don't revisit N. 3353 3354 // fold select_cc into other things, such as min/max/abs 3355 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3356} 3357 3358SDValue DAGCombiner::visitSETCC(SDNode *N) { 3359 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3360 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3361 N->getDebugLoc()); 3362} 3363 3364// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3365// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3366// transformation. Returns true if extension are possible and the above 3367// mentioned transformation is profitable. 3368static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3369 unsigned ExtOpc, 3370 SmallVector<SDNode*, 4> &ExtendNodes, 3371 const TargetLowering &TLI) { 3372 bool HasCopyToRegUses = false; 3373 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3374 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3375 UE = N0.getNode()->use_end(); 3376 UI != UE; ++UI) { 3377 SDNode *User = *UI; 3378 if (User == N) 3379 continue; 3380 if (UI.getUse().getResNo() != N0.getResNo()) 3381 continue; 3382 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3383 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3384 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3385 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3386 // Sign bits will be lost after a zext. 3387 return false; 3388 bool Add = false; 3389 for (unsigned i = 0; i != 2; ++i) { 3390 SDValue UseOp = User->getOperand(i); 3391 if (UseOp == N0) 3392 continue; 3393 if (!isa<ConstantSDNode>(UseOp)) 3394 return false; 3395 Add = true; 3396 } 3397 if (Add) 3398 ExtendNodes.push_back(User); 3399 continue; 3400 } 3401 // If truncates aren't free and there are users we can't 3402 // extend, it isn't worthwhile. 3403 if (!isTruncFree) 3404 return false; 3405 // Remember if this value is live-out. 3406 if (User->getOpcode() == ISD::CopyToReg) 3407 HasCopyToRegUses = true; 3408 } 3409 3410 if (HasCopyToRegUses) { 3411 bool BothLiveOut = false; 3412 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3413 UI != UE; ++UI) { 3414 SDUse &Use = UI.getUse(); 3415 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3416 BothLiveOut = true; 3417 break; 3418 } 3419 } 3420 if (BothLiveOut) 3421 // Both unextended and extended values are live out. There had better be 3422 // good a reason for the transformation. 3423 return ExtendNodes.size(); 3424 } 3425 return true; 3426} 3427 3428SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3429 SDValue N0 = N->getOperand(0); 3430 EVT VT = N->getValueType(0); 3431 3432 // fold (sext c1) -> c1 3433 if (isa<ConstantSDNode>(N0)) 3434 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3435 3436 // fold (sext (sext x)) -> (sext x) 3437 // fold (sext (aext x)) -> (sext x) 3438 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3439 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3440 N0.getOperand(0)); 3441 3442 if (N0.getOpcode() == ISD::TRUNCATE) { 3443 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3444 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3445 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3446 if (NarrowLoad.getNode()) { 3447 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3448 if (NarrowLoad.getNode() != N0.getNode()) { 3449 CombineTo(N0.getNode(), NarrowLoad); 3450 // CombineTo deleted the truncate, if needed, but not what's under it. 3451 AddToWorkList(oye); 3452 } 3453 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3454 } 3455 3456 // See if the value being truncated is already sign extended. If so, just 3457 // eliminate the trunc/sext pair. 3458 SDValue Op = N0.getOperand(0); 3459 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3460 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3461 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3462 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3463 3464 if (OpBits == DestBits) { 3465 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3466 // bits, it is already ready. 3467 if (NumSignBits > DestBits-MidBits) 3468 return Op; 3469 } else if (OpBits < DestBits) { 3470 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3471 // bits, just sext from i32. 3472 if (NumSignBits > OpBits-MidBits) 3473 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3474 } else { 3475 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3476 // bits, just truncate to i32. 3477 if (NumSignBits > OpBits-MidBits) 3478 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3479 } 3480 3481 // fold (sext (truncate x)) -> (sextinreg x). 3482 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3483 N0.getValueType())) { 3484 if (OpBits < DestBits) 3485 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3486 else if (OpBits > DestBits) 3487 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3488 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3489 DAG.getValueType(N0.getValueType())); 3490 } 3491 } 3492 3493 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3494 if (ISD::isNON_EXTLoad(N0.getNode()) && 3495 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3496 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3497 bool DoXform = true; 3498 SmallVector<SDNode*, 4> SetCCs; 3499 if (!N0.hasOneUse()) 3500 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3501 if (DoXform) { 3502 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3503 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3504 LN0->getChain(), 3505 LN0->getBasePtr(), LN0->getSrcValue(), 3506 LN0->getSrcValueOffset(), 3507 N0.getValueType(), 3508 LN0->isVolatile(), LN0->isNonTemporal(), 3509 LN0->getAlignment()); 3510 CombineTo(N, ExtLoad); 3511 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3512 N0.getValueType(), ExtLoad); 3513 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3514 3515 // Extend SetCC uses if necessary. 3516 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3517 SDNode *SetCC = SetCCs[i]; 3518 SmallVector<SDValue, 4> Ops; 3519 3520 for (unsigned j = 0; j != 2; ++j) { 3521 SDValue SOp = SetCC->getOperand(j); 3522 if (SOp == Trunc) 3523 Ops.push_back(ExtLoad); 3524 else 3525 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3526 N->getDebugLoc(), VT, SOp)); 3527 } 3528 3529 Ops.push_back(SetCC->getOperand(2)); 3530 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3531 SetCC->getValueType(0), 3532 &Ops[0], Ops.size())); 3533 } 3534 3535 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3536 } 3537 } 3538 3539 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3540 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3541 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3542 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3543 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3544 EVT MemVT = LN0->getMemoryVT(); 3545 if ((!LegalOperations && !LN0->isVolatile()) || 3546 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3547 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3548 LN0->getChain(), 3549 LN0->getBasePtr(), LN0->getSrcValue(), 3550 LN0->getSrcValueOffset(), MemVT, 3551 LN0->isVolatile(), LN0->isNonTemporal(), 3552 LN0->getAlignment()); 3553 CombineTo(N, ExtLoad); 3554 CombineTo(N0.getNode(), 3555 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3556 N0.getValueType(), ExtLoad), 3557 ExtLoad.getValue(1)); 3558 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3559 } 3560 } 3561 3562 if (N0.getOpcode() == ISD::SETCC) { 3563 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3564 // Only do this before legalize for now. 3565 if (VT.isVector() && !LegalOperations) { 3566 EVT N0VT = N0.getOperand(0).getValueType(); 3567 // We know that the # elements of the results is the same as the 3568 // # elements of the compare (and the # elements of the compare result 3569 // for that matter). Check to see that they are the same size. If so, 3570 // we know that the element size of the sext'd result matches the 3571 // element size of the compare operands. 3572 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3573 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3574 N0.getOperand(1), 3575 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3576 // If the desired elements are smaller or larger than the source 3577 // elements we can use a matching integer vector type and then 3578 // truncate/sign extend 3579 else { 3580 EVT MatchingElementType = 3581 EVT::getIntegerVT(*DAG.getContext(), 3582 N0VT.getScalarType().getSizeInBits()); 3583 EVT MatchingVectorType = 3584 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3585 N0VT.getVectorNumElements()); 3586 SDValue VsetCC = 3587 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3588 N0.getOperand(1), 3589 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3590 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3591 } 3592 } 3593 3594 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3595 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3596 SDValue NegOne = 3597 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3598 SDValue SCC = 3599 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3600 NegOne, DAG.getConstant(0, VT), 3601 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3602 if (SCC.getNode()) return SCC; 3603 if (!LegalOperations || 3604 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3605 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3606 DAG.getSetCC(N->getDebugLoc(), 3607 TLI.getSetCCResultType(VT), 3608 N0.getOperand(0), N0.getOperand(1), 3609 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3610 NegOne, DAG.getConstant(0, VT)); 3611 } 3612 3613 // fold (sext x) -> (zext x) if the sign bit is known zero. 3614 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3615 DAG.SignBitIsZero(N0)) 3616 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3617 3618 return SDValue(); 3619} 3620 3621SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3622 SDValue N0 = N->getOperand(0); 3623 EVT VT = N->getValueType(0); 3624 3625 // fold (zext c1) -> c1 3626 if (isa<ConstantSDNode>(N0)) 3627 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3628 // fold (zext (zext x)) -> (zext x) 3629 // fold (zext (aext x)) -> (zext x) 3630 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3631 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3632 N0.getOperand(0)); 3633 3634 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3635 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3636 if (N0.getOpcode() == ISD::TRUNCATE) { 3637 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3638 if (NarrowLoad.getNode()) { 3639 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3640 if (NarrowLoad.getNode() != N0.getNode()) { 3641 CombineTo(N0.getNode(), NarrowLoad); 3642 // CombineTo deleted the truncate, if needed, but not what's under it. 3643 AddToWorkList(oye); 3644 } 3645 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3646 } 3647 } 3648 3649 // fold (zext (truncate x)) -> (and x, mask) 3650 if (N0.getOpcode() == ISD::TRUNCATE && 3651 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3652 SDValue Op = N0.getOperand(0); 3653 if (Op.getValueType().bitsLT(VT)) { 3654 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3655 } else if (Op.getValueType().bitsGT(VT)) { 3656 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3657 } 3658 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3659 N0.getValueType().getScalarType()); 3660 } 3661 3662 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3663 // if either of the casts is not free. 3664 if (N0.getOpcode() == ISD::AND && 3665 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3666 N0.getOperand(1).getOpcode() == ISD::Constant && 3667 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3668 N0.getValueType()) || 3669 !TLI.isZExtFree(N0.getValueType(), VT))) { 3670 SDValue X = N0.getOperand(0).getOperand(0); 3671 if (X.getValueType().bitsLT(VT)) { 3672 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3673 } else if (X.getValueType().bitsGT(VT)) { 3674 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3675 } 3676 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3677 Mask.zext(VT.getSizeInBits()); 3678 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3679 X, DAG.getConstant(Mask, VT)); 3680 } 3681 3682 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3683 if (ISD::isNON_EXTLoad(N0.getNode()) && 3684 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3685 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3686 bool DoXform = true; 3687 SmallVector<SDNode*, 4> SetCCs; 3688 if (!N0.hasOneUse()) 3689 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3690 if (DoXform) { 3691 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3692 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3693 LN0->getChain(), 3694 LN0->getBasePtr(), LN0->getSrcValue(), 3695 LN0->getSrcValueOffset(), 3696 N0.getValueType(), 3697 LN0->isVolatile(), LN0->isNonTemporal(), 3698 LN0->getAlignment()); 3699 CombineTo(N, ExtLoad); 3700 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3701 N0.getValueType(), ExtLoad); 3702 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3703 3704 // Extend SetCC uses if necessary. 3705 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3706 SDNode *SetCC = SetCCs[i]; 3707 SmallVector<SDValue, 4> Ops; 3708 3709 for (unsigned j = 0; j != 2; ++j) { 3710 SDValue SOp = SetCC->getOperand(j); 3711 if (SOp == Trunc) 3712 Ops.push_back(ExtLoad); 3713 else 3714 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3715 N->getDebugLoc(), VT, SOp)); 3716 } 3717 3718 Ops.push_back(SetCC->getOperand(2)); 3719 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3720 SetCC->getValueType(0), 3721 &Ops[0], Ops.size())); 3722 } 3723 3724 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3725 } 3726 } 3727 3728 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3729 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3730 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3731 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3732 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3733 EVT MemVT = LN0->getMemoryVT(); 3734 if ((!LegalOperations && !LN0->isVolatile()) || 3735 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3736 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3737 LN0->getChain(), 3738 LN0->getBasePtr(), LN0->getSrcValue(), 3739 LN0->getSrcValueOffset(), MemVT, 3740 LN0->isVolatile(), LN0->isNonTemporal(), 3741 LN0->getAlignment()); 3742 CombineTo(N, ExtLoad); 3743 CombineTo(N0.getNode(), 3744 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3745 ExtLoad), 3746 ExtLoad.getValue(1)); 3747 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3748 } 3749 } 3750 3751 if (N0.getOpcode() == ISD::SETCC) { 3752 if (!LegalOperations && VT.isVector()) { 3753 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 3754 // Only do this before legalize for now. 3755 EVT N0VT = N0.getOperand(0).getValueType(); 3756 EVT EltVT = VT.getVectorElementType(); 3757 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 3758 DAG.getConstant(1, EltVT)); 3759 if (VT.getSizeInBits() == N0VT.getSizeInBits()) { 3760 // We know that the # elements of the results is the same as the 3761 // # elements of the compare (and the # elements of the compare result 3762 // for that matter). Check to see that they are the same size. If so, 3763 // we know that the element size of the sext'd result matches the 3764 // element size of the compare operands. 3765 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3766 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3767 N0.getOperand(1), 3768 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3769 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3770 &OneOps[0], OneOps.size())); 3771 } else { 3772 // If the desired elements are smaller or larger than the source 3773 // elements we can use a matching integer vector type and then 3774 // truncate/sign extend 3775 EVT MatchingElementType = 3776 EVT::getIntegerVT(*DAG.getContext(), 3777 N0VT.getScalarType().getSizeInBits()); 3778 EVT MatchingVectorType = 3779 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3780 N0VT.getVectorNumElements()); 3781 SDValue VsetCC = 3782 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3783 N0.getOperand(1), 3784 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3785 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3786 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 3787 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3788 &OneOps[0], OneOps.size())); 3789 } 3790 } 3791 3792 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3793 SDValue SCC = 3794 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3795 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3796 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3797 if (SCC.getNode()) return SCC; 3798 } 3799 3800 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3801 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3802 isa<ConstantSDNode>(N0.getOperand(1)) && 3803 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3804 N0.hasOneUse()) { 3805 if (N0.getOpcode() == ISD::SHL) { 3806 // If the original shl may be shifting out bits, do not perform this 3807 // transformation. 3808 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3809 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3810 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3811 if (ShAmt > KnownZeroBits) 3812 return SDValue(); 3813 } 3814 DebugLoc dl = N->getDebugLoc(); 3815 return DAG.getNode(N0.getOpcode(), dl, VT, 3816 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3817 DAG.getNode(ISD::ZERO_EXTEND, dl, 3818 N0.getOperand(1).getValueType(), 3819 N0.getOperand(1))); 3820 } 3821 3822 return SDValue(); 3823} 3824 3825SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3826 SDValue N0 = N->getOperand(0); 3827 EVT VT = N->getValueType(0); 3828 3829 // fold (aext c1) -> c1 3830 if (isa<ConstantSDNode>(N0)) 3831 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3832 // fold (aext (aext x)) -> (aext x) 3833 // fold (aext (zext x)) -> (zext x) 3834 // fold (aext (sext x)) -> (sext x) 3835 if (N0.getOpcode() == ISD::ANY_EXTEND || 3836 N0.getOpcode() == ISD::ZERO_EXTEND || 3837 N0.getOpcode() == ISD::SIGN_EXTEND) 3838 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3839 3840 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3841 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3842 if (N0.getOpcode() == ISD::TRUNCATE) { 3843 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3844 if (NarrowLoad.getNode()) { 3845 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3846 if (NarrowLoad.getNode() != N0.getNode()) { 3847 CombineTo(N0.getNode(), NarrowLoad); 3848 // CombineTo deleted the truncate, if needed, but not what's under it. 3849 AddToWorkList(oye); 3850 } 3851 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3852 } 3853 } 3854 3855 // fold (aext (truncate x)) 3856 if (N0.getOpcode() == ISD::TRUNCATE) { 3857 SDValue TruncOp = N0.getOperand(0); 3858 if (TruncOp.getValueType() == VT) 3859 return TruncOp; // x iff x size == zext size. 3860 if (TruncOp.getValueType().bitsGT(VT)) 3861 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3862 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3863 } 3864 3865 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3866 // if the trunc is not free. 3867 if (N0.getOpcode() == ISD::AND && 3868 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3869 N0.getOperand(1).getOpcode() == ISD::Constant && 3870 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3871 N0.getValueType())) { 3872 SDValue X = N0.getOperand(0).getOperand(0); 3873 if (X.getValueType().bitsLT(VT)) { 3874 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3875 } else if (X.getValueType().bitsGT(VT)) { 3876 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3877 } 3878 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3879 Mask.zext(VT.getSizeInBits()); 3880 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3881 X, DAG.getConstant(Mask, VT)); 3882 } 3883 3884 // fold (aext (load x)) -> (aext (truncate (extload x))) 3885 if (ISD::isNON_EXTLoad(N0.getNode()) && 3886 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3887 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3888 bool DoXform = true; 3889 SmallVector<SDNode*, 4> SetCCs; 3890 if (!N0.hasOneUse()) 3891 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3892 if (DoXform) { 3893 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3894 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3895 LN0->getChain(), 3896 LN0->getBasePtr(), LN0->getSrcValue(), 3897 LN0->getSrcValueOffset(), 3898 N0.getValueType(), 3899 LN0->isVolatile(), LN0->isNonTemporal(), 3900 LN0->getAlignment()); 3901 CombineTo(N, ExtLoad); 3902 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3903 N0.getValueType(), ExtLoad); 3904 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3905 3906 // Extend SetCC uses if necessary. 3907 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3908 SDNode *SetCC = SetCCs[i]; 3909 SmallVector<SDValue, 4> Ops; 3910 3911 for (unsigned j = 0; j != 2; ++j) { 3912 SDValue SOp = SetCC->getOperand(j); 3913 if (SOp == Trunc) 3914 Ops.push_back(ExtLoad); 3915 else 3916 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3917 N->getDebugLoc(), VT, SOp)); 3918 } 3919 3920 Ops.push_back(SetCC->getOperand(2)); 3921 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3922 SetCC->getValueType(0), 3923 &Ops[0], Ops.size())); 3924 } 3925 3926 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3927 } 3928 } 3929 3930 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3931 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3932 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3933 if (N0.getOpcode() == ISD::LOAD && 3934 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3935 N0.hasOneUse()) { 3936 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3937 EVT MemVT = LN0->getMemoryVT(); 3938 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3939 VT, LN0->getChain(), LN0->getBasePtr(), 3940 LN0->getSrcValue(), 3941 LN0->getSrcValueOffset(), MemVT, 3942 LN0->isVolatile(), LN0->isNonTemporal(), 3943 LN0->getAlignment()); 3944 CombineTo(N, ExtLoad); 3945 CombineTo(N0.getNode(), 3946 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3947 N0.getValueType(), ExtLoad), 3948 ExtLoad.getValue(1)); 3949 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3950 } 3951 3952 if (N0.getOpcode() == ISD::SETCC) { 3953 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 3954 // Only do this before legalize for now. 3955 if (VT.isVector() && !LegalOperations) { 3956 EVT N0VT = N0.getOperand(0).getValueType(); 3957 // We know that the # elements of the results is the same as the 3958 // # elements of the compare (and the # elements of the compare result 3959 // for that matter). Check to see that they are the same size. If so, 3960 // we know that the element size of the sext'd result matches the 3961 // element size of the compare operands. 3962 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3963 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3964 N0.getOperand(1), 3965 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3966 // If the desired elements are smaller or larger than the source 3967 // elements we can use a matching integer vector type and then 3968 // truncate/sign extend 3969 else { 3970 EVT MatchingElementType = 3971 EVT::getIntegerVT(*DAG.getContext(), 3972 N0VT.getScalarType().getSizeInBits()); 3973 EVT MatchingVectorType = 3974 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3975 N0VT.getVectorNumElements()); 3976 SDValue VsetCC = 3977 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3978 N0.getOperand(1), 3979 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3980 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3981 } 3982 } 3983 3984 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3985 SDValue SCC = 3986 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3987 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3988 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3989 if (SCC.getNode()) 3990 return SCC; 3991 } 3992 3993 return SDValue(); 3994} 3995 3996/// GetDemandedBits - See if the specified operand can be simplified with the 3997/// knowledge that only the bits specified by Mask are used. If so, return the 3998/// simpler operand, otherwise return a null SDValue. 3999SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4000 switch (V.getOpcode()) { 4001 default: break; 4002 case ISD::OR: 4003 case ISD::XOR: 4004 // If the LHS or RHS don't contribute bits to the or, drop them. 4005 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4006 return V.getOperand(1); 4007 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4008 return V.getOperand(0); 4009 break; 4010 case ISD::SRL: 4011 // Only look at single-use SRLs. 4012 if (!V.getNode()->hasOneUse()) 4013 break; 4014 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4015 // See if we can recursively simplify the LHS. 4016 unsigned Amt = RHSC->getZExtValue(); 4017 4018 // Watch out for shift count overflow though. 4019 if (Amt >= Mask.getBitWidth()) break; 4020 APInt NewMask = Mask << Amt; 4021 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4022 if (SimplifyLHS.getNode()) 4023 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4024 SimplifyLHS, V.getOperand(1)); 4025 } 4026 } 4027 return SDValue(); 4028} 4029 4030/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4031/// bits and then truncated to a narrower type and where N is a multiple 4032/// of number of bits of the narrower type, transform it to a narrower load 4033/// from address + N / num of bits of new type. If the result is to be 4034/// extended, also fold the extension to form a extending load. 4035SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4036 unsigned Opc = N->getOpcode(); 4037 4038 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4039 SDValue N0 = N->getOperand(0); 4040 EVT VT = N->getValueType(0); 4041 EVT ExtVT = VT; 4042 4043 // This transformation isn't valid for vector loads. 4044 if (VT.isVector()) 4045 return SDValue(); 4046 4047 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4048 // extended to VT. 4049 if (Opc == ISD::SIGN_EXTEND_INREG) { 4050 ExtType = ISD::SEXTLOAD; 4051 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4052 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 4053 return SDValue(); 4054 } else if (Opc == ISD::SRL) { 4055 // Annother special-case: SRL is basically zero-extending a narrower 4056 // value. 4057 ExtType = ISD::ZEXTLOAD; 4058 N0 = SDValue(N, 0); 4059 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4060 if (!N01) return SDValue(); 4061 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4062 VT.getSizeInBits() - N01->getZExtValue()); 4063 } 4064 4065 unsigned EVTBits = ExtVT.getSizeInBits(); 4066 unsigned ShAmt = 0; 4067 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 4068 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4069 ShAmt = N01->getZExtValue(); 4070 // Is the shift amount a multiple of size of VT? 4071 if ((ShAmt & (EVTBits-1)) == 0) { 4072 N0 = N0.getOperand(0); 4073 // Is the load width a multiple of size of VT? 4074 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4075 return SDValue(); 4076 } 4077 } 4078 } 4079 4080 // Do not generate loads of non-round integer types since these can 4081 // be expensive (and would be wrong if the type is not byte sized). 4082 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 4083 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits && 4084 // Do not change the width of a volatile load. 4085 !cast<LoadSDNode>(N0)->isVolatile()) { 4086 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4087 EVT PtrType = N0.getOperand(1).getValueType(); 4088 4089 // For big endian targets, we need to adjust the offset to the pointer to 4090 // load the correct bytes. 4091 if (TLI.isBigEndian()) { 4092 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4093 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4094 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4095 } 4096 4097 uint64_t PtrOff = ShAmt / 8; 4098 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4099 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4100 PtrType, LN0->getBasePtr(), 4101 DAG.getConstant(PtrOff, PtrType)); 4102 AddToWorkList(NewPtr.getNode()); 4103 4104 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 4105 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4106 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 4107 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign) 4108 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 4109 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 4110 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4111 NewAlign); 4112 4113 // Replace the old load's chain with the new load's chain. 4114 WorkListRemover DeadNodes(*this); 4115 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4116 &DeadNodes); 4117 4118 // Return the new loaded value. 4119 return Load; 4120 } 4121 4122 return SDValue(); 4123} 4124 4125SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4126 SDValue N0 = N->getOperand(0); 4127 SDValue N1 = N->getOperand(1); 4128 EVT VT = N->getValueType(0); 4129 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4130 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4131 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4132 4133 // fold (sext_in_reg c1) -> c1 4134 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4135 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4136 4137 // If the input is already sign extended, just drop the extension. 4138 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4139 return N0; 4140 4141 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4142 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4143 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4144 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4145 N0.getOperand(0), N1); 4146 } 4147 4148 // fold (sext_in_reg (sext x)) -> (sext x) 4149 // fold (sext_in_reg (aext x)) -> (sext x) 4150 // if x is small enough. 4151 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4152 SDValue N00 = N0.getOperand(0); 4153 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4154 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4155 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4156 } 4157 4158 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4159 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4160 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4161 4162 // fold operands of sext_in_reg based on knowledge that the top bits are not 4163 // demanded. 4164 if (SimplifyDemandedBits(SDValue(N, 0))) 4165 return SDValue(N, 0); 4166 4167 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4168 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4169 SDValue NarrowLoad = ReduceLoadWidth(N); 4170 if (NarrowLoad.getNode()) 4171 return NarrowLoad; 4172 4173 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4174 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4175 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4176 if (N0.getOpcode() == ISD::SRL) { 4177 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4178 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4179 // We can turn this into an SRA iff the input to the SRL is already sign 4180 // extended enough. 4181 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4182 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4183 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4184 N0.getOperand(0), N0.getOperand(1)); 4185 } 4186 } 4187 4188 // fold (sext_inreg (extload x)) -> (sextload x) 4189 if (ISD::isEXTLoad(N0.getNode()) && 4190 ISD::isUNINDEXEDLoad(N0.getNode()) && 4191 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4192 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4193 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4194 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4195 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4196 LN0->getChain(), 4197 LN0->getBasePtr(), LN0->getSrcValue(), 4198 LN0->getSrcValueOffset(), EVT, 4199 LN0->isVolatile(), LN0->isNonTemporal(), 4200 LN0->getAlignment()); 4201 CombineTo(N, ExtLoad); 4202 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4203 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4204 } 4205 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4206 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4207 N0.hasOneUse() && 4208 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4209 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4210 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4211 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4212 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4213 LN0->getChain(), 4214 LN0->getBasePtr(), LN0->getSrcValue(), 4215 LN0->getSrcValueOffset(), EVT, 4216 LN0->isVolatile(), LN0->isNonTemporal(), 4217 LN0->getAlignment()); 4218 CombineTo(N, ExtLoad); 4219 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4220 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4221 } 4222 return SDValue(); 4223} 4224 4225SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4226 SDValue N0 = N->getOperand(0); 4227 EVT VT = N->getValueType(0); 4228 4229 // noop truncate 4230 if (N0.getValueType() == N->getValueType(0)) 4231 return N0; 4232 // fold (truncate c1) -> c1 4233 if (isa<ConstantSDNode>(N0)) 4234 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4235 // fold (truncate (truncate x)) -> (truncate x) 4236 if (N0.getOpcode() == ISD::TRUNCATE) 4237 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4238 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4239 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4240 N0.getOpcode() == ISD::SIGN_EXTEND || 4241 N0.getOpcode() == ISD::ANY_EXTEND) { 4242 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4243 // if the source is smaller than the dest, we still need an extend 4244 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4245 N0.getOperand(0)); 4246 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4247 // if the source is larger than the dest, than we just need the truncate 4248 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4249 else 4250 // if the source and dest are the same type, we can drop both the extend 4251 // and the truncate. 4252 return N0.getOperand(0); 4253 } 4254 4255 // See if we can simplify the input to this truncate through knowledge that 4256 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 4257 // -> trunc y 4258 SDValue Shorter = 4259 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4260 VT.getSizeInBits())); 4261 if (Shorter.getNode()) 4262 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4263 4264 // fold (truncate (load x)) -> (smaller load x) 4265 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4266 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4267 SDValue Reduced = ReduceLoadWidth(N); 4268 if (Reduced.getNode()) 4269 return Reduced; 4270 } 4271 4272 // Simplify the operands using demanded-bits information. 4273 if (!VT.isVector() && 4274 SimplifyDemandedBits(SDValue(N, 0))) 4275 return SDValue(N, 0); 4276 4277 return SDValue(); 4278} 4279 4280static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4281 SDValue Elt = N->getOperand(i); 4282 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4283 return Elt.getNode(); 4284 return Elt.getOperand(Elt.getResNo()).getNode(); 4285} 4286 4287/// CombineConsecutiveLoads - build_pair (load, load) -> load 4288/// if load locations are consecutive. 4289SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4290 assert(N->getOpcode() == ISD::BUILD_PAIR); 4291 4292 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4293 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4294 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 4295 return SDValue(); 4296 EVT LD1VT = LD1->getValueType(0); 4297 4298 if (ISD::isNON_EXTLoad(LD2) && 4299 LD2->hasOneUse() && 4300 // If both are volatile this would reduce the number of volatile loads. 4301 // If one is volatile it might be ok, but play conservative and bail out. 4302 !LD1->isVolatile() && 4303 !LD2->isVolatile() && 4304 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4305 unsigned Align = LD1->getAlignment(); 4306 unsigned NewAlign = TLI.getTargetData()-> 4307 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4308 4309 if (NewAlign <= Align && 4310 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4311 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4312 LD1->getBasePtr(), LD1->getSrcValue(), 4313 LD1->getSrcValueOffset(), false, false, Align); 4314 } 4315 4316 return SDValue(); 4317} 4318 4319SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 4320 SDValue N0 = N->getOperand(0); 4321 EVT VT = N->getValueType(0); 4322 4323 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4324 // Only do this before legalize, since afterward the target may be depending 4325 // on the bitconvert. 4326 // First check to see if this is all constant. 4327 if (!LegalTypes && 4328 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4329 VT.isVector()) { 4330 bool isSimple = true; 4331 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4332 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4333 N0.getOperand(i).getOpcode() != ISD::Constant && 4334 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4335 isSimple = false; 4336 break; 4337 } 4338 4339 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4340 assert(!DestEltVT.isVector() && 4341 "Element type of vector ValueType must not be vector!"); 4342 if (isSimple) 4343 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4344 } 4345 4346 // If the input is a constant, let getNode fold it. 4347 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4348 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 4349 if (Res.getNode() != N) { 4350 if (!LegalOperations || 4351 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4352 return Res; 4353 4354 // Folding it resulted in an illegal node, and it's too late to 4355 // do that. Clean up the old node and forego the transformation. 4356 // Ideally this won't happen very often, because instcombine 4357 // and the earlier dagcombine runs (where illegal nodes are 4358 // permitted) should have folded most of them already. 4359 DAG.DeleteNode(Res.getNode()); 4360 } 4361 } 4362 4363 // (conv (conv x, t1), t2) -> (conv x, t2) 4364 if (N0.getOpcode() == ISD::BIT_CONVERT) 4365 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 4366 N0.getOperand(0)); 4367 4368 // fold (conv (load x)) -> (load (conv*)x) 4369 // If the resultant load doesn't need a higher alignment than the original! 4370 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4371 // Do not change the width of a volatile load. 4372 !cast<LoadSDNode>(N0)->isVolatile() && 4373 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4374 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4375 unsigned Align = TLI.getTargetData()-> 4376 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4377 unsigned OrigAlign = LN0->getAlignment(); 4378 4379 if (Align <= OrigAlign) { 4380 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4381 LN0->getBasePtr(), 4382 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4383 LN0->isVolatile(), LN0->isNonTemporal(), 4384 OrigAlign); 4385 AddToWorkList(N); 4386 CombineTo(N0.getNode(), 4387 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4388 N0.getValueType(), Load), 4389 Load.getValue(1)); 4390 return Load; 4391 } 4392 } 4393 4394 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4395 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4396 // This often reduces constant pool loads. 4397 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4398 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4399 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 4400 N0.getOperand(0)); 4401 AddToWorkList(NewConv.getNode()); 4402 4403 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4404 if (N0.getOpcode() == ISD::FNEG) 4405 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4406 NewConv, DAG.getConstant(SignBit, VT)); 4407 assert(N0.getOpcode() == ISD::FABS); 4408 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4409 NewConv, DAG.getConstant(~SignBit, VT)); 4410 } 4411 4412 // fold (bitconvert (fcopysign cst, x)) -> 4413 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4414 // Note that we don't handle (copysign x, cst) because this can always be 4415 // folded to an fneg or fabs. 4416 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4417 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4418 VT.isInteger() && !VT.isVector()) { 4419 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4420 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4421 if (isTypeLegal(IntXVT)) { 4422 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4423 IntXVT, N0.getOperand(1)); 4424 AddToWorkList(X.getNode()); 4425 4426 // If X has a different width than the result/lhs, sext it or truncate it. 4427 unsigned VTWidth = VT.getSizeInBits(); 4428 if (OrigXWidth < VTWidth) { 4429 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4430 AddToWorkList(X.getNode()); 4431 } else if (OrigXWidth > VTWidth) { 4432 // To get the sign bit in the right place, we have to shift it right 4433 // before truncating. 4434 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4435 X.getValueType(), X, 4436 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4437 AddToWorkList(X.getNode()); 4438 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4439 AddToWorkList(X.getNode()); 4440 } 4441 4442 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4443 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4444 X, DAG.getConstant(SignBit, VT)); 4445 AddToWorkList(X.getNode()); 4446 4447 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4448 VT, N0.getOperand(0)); 4449 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4450 Cst, DAG.getConstant(~SignBit, VT)); 4451 AddToWorkList(Cst.getNode()); 4452 4453 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4454 } 4455 } 4456 4457 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4458 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4459 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4460 if (CombineLD.getNode()) 4461 return CombineLD; 4462 } 4463 4464 return SDValue(); 4465} 4466 4467SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4468 EVT VT = N->getValueType(0); 4469 return CombineConsecutiveLoads(N, VT); 4470} 4471 4472/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 4473/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4474/// destination element value type. 4475SDValue DAGCombiner:: 4476ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4477 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4478 4479 // If this is already the right type, we're done. 4480 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4481 4482 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4483 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4484 4485 // If this is a conversion of N elements of one type to N elements of another 4486 // type, convert each element. This handles FP<->INT cases. 4487 if (SrcBitSize == DstBitSize) { 4488 SmallVector<SDValue, 8> Ops; 4489 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4490 SDValue Op = BV->getOperand(i); 4491 // If the vector element type is not legal, the BUILD_VECTOR operands 4492 // are promoted and implicitly truncated. Make that explicit here. 4493 if (Op.getValueType() != SrcEltVT) 4494 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4495 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 4496 DstEltVT, Op)); 4497 AddToWorkList(Ops.back().getNode()); 4498 } 4499 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4500 BV->getValueType(0).getVectorNumElements()); 4501 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4502 &Ops[0], Ops.size()); 4503 } 4504 4505 // Otherwise, we're growing or shrinking the elements. To avoid having to 4506 // handle annoying details of growing/shrinking FP values, we convert them to 4507 // int first. 4508 if (SrcEltVT.isFloatingPoint()) { 4509 // Convert the input float vector to a int vector where the elements are the 4510 // same sizes. 4511 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4512 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4513 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 4514 SrcEltVT = IntVT; 4515 } 4516 4517 // Now we know the input is an integer vector. If the output is a FP type, 4518 // convert to integer first, then to FP of the right size. 4519 if (DstEltVT.isFloatingPoint()) { 4520 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4521 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4522 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4523 4524 // Next, convert to FP elements of the same size. 4525 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4526 } 4527 4528 // Okay, we know the src/dst types are both integers of differing types. 4529 // Handling growing first. 4530 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4531 if (SrcBitSize < DstBitSize) { 4532 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4533 4534 SmallVector<SDValue, 8> Ops; 4535 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4536 i += NumInputsPerOutput) { 4537 bool isLE = TLI.isLittleEndian(); 4538 APInt NewBits = APInt(DstBitSize, 0); 4539 bool EltIsUndef = true; 4540 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4541 // Shift the previously computed bits over. 4542 NewBits <<= SrcBitSize; 4543 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4544 if (Op.getOpcode() == ISD::UNDEF) continue; 4545 EltIsUndef = false; 4546 4547 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4548 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4549 } 4550 4551 if (EltIsUndef) 4552 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4553 else 4554 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4555 } 4556 4557 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4558 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4559 &Ops[0], Ops.size()); 4560 } 4561 4562 // Finally, this must be the case where we are shrinking elements: each input 4563 // turns into multiple outputs. 4564 bool isS2V = ISD::isScalarToVector(BV); 4565 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4566 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4567 NumOutputsPerInput*BV->getNumOperands()); 4568 SmallVector<SDValue, 8> Ops; 4569 4570 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4571 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4572 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4573 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4574 continue; 4575 } 4576 4577 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4578 getAPIntValue()).zextOrTrunc(SrcBitSize); 4579 4580 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4581 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4582 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4583 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4584 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4585 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4586 Ops[0]); 4587 OpVal = OpVal.lshr(DstBitSize); 4588 } 4589 4590 // For big endian targets, swap the order of the pieces of each element. 4591 if (TLI.isBigEndian()) 4592 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4593 } 4594 4595 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4596 &Ops[0], Ops.size()); 4597} 4598 4599SDValue DAGCombiner::visitFADD(SDNode *N) { 4600 SDValue N0 = N->getOperand(0); 4601 SDValue N1 = N->getOperand(1); 4602 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4603 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4604 EVT VT = N->getValueType(0); 4605 4606 // fold vector ops 4607 if (VT.isVector()) { 4608 SDValue FoldedVOp = SimplifyVBinOp(N); 4609 if (FoldedVOp.getNode()) return FoldedVOp; 4610 } 4611 4612 // fold (fadd c1, c2) -> (fadd c1, c2) 4613 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4614 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4615 // canonicalize constant to RHS 4616 if (N0CFP && !N1CFP) 4617 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4618 // fold (fadd A, 0) -> A 4619 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4620 return N0; 4621 // fold (fadd A, (fneg B)) -> (fsub A, B) 4622 if (isNegatibleForFree(N1, LegalOperations) == 2) 4623 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4624 GetNegatedExpression(N1, DAG, LegalOperations)); 4625 // fold (fadd (fneg A), B) -> (fsub B, A) 4626 if (isNegatibleForFree(N0, LegalOperations) == 2) 4627 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4628 GetNegatedExpression(N0, DAG, LegalOperations)); 4629 4630 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4631 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4632 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4633 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4634 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4635 N0.getOperand(1), N1)); 4636 4637 return SDValue(); 4638} 4639 4640SDValue DAGCombiner::visitFSUB(SDNode *N) { 4641 SDValue N0 = N->getOperand(0); 4642 SDValue N1 = N->getOperand(1); 4643 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4644 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4645 EVT VT = N->getValueType(0); 4646 4647 // fold vector ops 4648 if (VT.isVector()) { 4649 SDValue FoldedVOp = SimplifyVBinOp(N); 4650 if (FoldedVOp.getNode()) return FoldedVOp; 4651 } 4652 4653 // fold (fsub c1, c2) -> c1-c2 4654 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4655 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4656 // fold (fsub A, 0) -> A 4657 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4658 return N0; 4659 // fold (fsub 0, B) -> -B 4660 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4661 if (isNegatibleForFree(N1, LegalOperations)) 4662 return GetNegatedExpression(N1, DAG, LegalOperations); 4663 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4664 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4665 } 4666 // fold (fsub A, (fneg B)) -> (fadd A, B) 4667 if (isNegatibleForFree(N1, LegalOperations)) 4668 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4669 GetNegatedExpression(N1, DAG, LegalOperations)); 4670 4671 return SDValue(); 4672} 4673 4674SDValue DAGCombiner::visitFMUL(SDNode *N) { 4675 SDValue N0 = N->getOperand(0); 4676 SDValue N1 = N->getOperand(1); 4677 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4678 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4679 EVT VT = N->getValueType(0); 4680 4681 // fold vector ops 4682 if (VT.isVector()) { 4683 SDValue FoldedVOp = SimplifyVBinOp(N); 4684 if (FoldedVOp.getNode()) return FoldedVOp; 4685 } 4686 4687 // fold (fmul c1, c2) -> c1*c2 4688 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4689 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4690 // canonicalize constant to RHS 4691 if (N0CFP && !N1CFP) 4692 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4693 // fold (fmul A, 0) -> 0 4694 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4695 return N1; 4696 // fold (fmul A, 0) -> 0, vector edition. 4697 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4698 return N1; 4699 // fold (fmul X, 2.0) -> (fadd X, X) 4700 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4701 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4702 // fold (fmul X, -1.0) -> (fneg X) 4703 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4704 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4705 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4706 4707 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4708 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4709 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4710 // Both can be negated for free, check to see if at least one is cheaper 4711 // negated. 4712 if (LHSNeg == 2 || RHSNeg == 2) 4713 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4714 GetNegatedExpression(N0, DAG, LegalOperations), 4715 GetNegatedExpression(N1, DAG, LegalOperations)); 4716 } 4717 } 4718 4719 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4720 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4721 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4722 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4723 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4724 N0.getOperand(1), N1)); 4725 4726 return SDValue(); 4727} 4728 4729SDValue DAGCombiner::visitFDIV(SDNode *N) { 4730 SDValue N0 = N->getOperand(0); 4731 SDValue N1 = N->getOperand(1); 4732 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4733 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4734 EVT VT = N->getValueType(0); 4735 4736 // fold vector ops 4737 if (VT.isVector()) { 4738 SDValue FoldedVOp = SimplifyVBinOp(N); 4739 if (FoldedVOp.getNode()) return FoldedVOp; 4740 } 4741 4742 // fold (fdiv c1, c2) -> c1/c2 4743 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4744 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4745 4746 4747 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4748 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4749 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4750 // Both can be negated for free, check to see if at least one is cheaper 4751 // negated. 4752 if (LHSNeg == 2 || RHSNeg == 2) 4753 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4754 GetNegatedExpression(N0, DAG, LegalOperations), 4755 GetNegatedExpression(N1, DAG, LegalOperations)); 4756 } 4757 } 4758 4759 return SDValue(); 4760} 4761 4762SDValue DAGCombiner::visitFREM(SDNode *N) { 4763 SDValue N0 = N->getOperand(0); 4764 SDValue N1 = N->getOperand(1); 4765 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4766 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4767 EVT VT = N->getValueType(0); 4768 4769 // fold (frem c1, c2) -> fmod(c1,c2) 4770 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4771 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4772 4773 return SDValue(); 4774} 4775 4776SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4777 SDValue N0 = N->getOperand(0); 4778 SDValue N1 = N->getOperand(1); 4779 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4780 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4781 EVT VT = N->getValueType(0); 4782 4783 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4784 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4785 4786 if (N1CFP) { 4787 const APFloat& V = N1CFP->getValueAPF(); 4788 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4789 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4790 if (!V.isNegative()) { 4791 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4792 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4793 } else { 4794 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4795 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4796 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4797 } 4798 } 4799 4800 // copysign(fabs(x), y) -> copysign(x, y) 4801 // copysign(fneg(x), y) -> copysign(x, y) 4802 // copysign(copysign(x,z), y) -> copysign(x, y) 4803 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4804 N0.getOpcode() == ISD::FCOPYSIGN) 4805 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4806 N0.getOperand(0), N1); 4807 4808 // copysign(x, abs(y)) -> abs(x) 4809 if (N1.getOpcode() == ISD::FABS) 4810 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4811 4812 // copysign(x, copysign(y,z)) -> copysign(x, z) 4813 if (N1.getOpcode() == ISD::FCOPYSIGN) 4814 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4815 N0, N1.getOperand(1)); 4816 4817 // copysign(x, fp_extend(y)) -> copysign(x, y) 4818 // copysign(x, fp_round(y)) -> copysign(x, y) 4819 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4820 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4821 N0, N1.getOperand(0)); 4822 4823 return SDValue(); 4824} 4825 4826SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4827 SDValue N0 = N->getOperand(0); 4828 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4829 EVT VT = N->getValueType(0); 4830 EVT OpVT = N0.getValueType(); 4831 4832 // fold (sint_to_fp c1) -> c1fp 4833 if (N0C && OpVT != MVT::ppcf128) 4834 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4835 4836 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4837 // but UINT_TO_FP is legal on this target, try to convert. 4838 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4839 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4840 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4841 if (DAG.SignBitIsZero(N0)) 4842 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4843 } 4844 4845 return SDValue(); 4846} 4847 4848SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4849 SDValue N0 = N->getOperand(0); 4850 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4851 EVT VT = N->getValueType(0); 4852 EVT OpVT = N0.getValueType(); 4853 4854 // fold (uint_to_fp c1) -> c1fp 4855 if (N0C && OpVT != MVT::ppcf128) 4856 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4857 4858 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4859 // but SINT_TO_FP is legal on this target, try to convert. 4860 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4861 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4862 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4863 if (DAG.SignBitIsZero(N0)) 4864 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4865 } 4866 4867 return SDValue(); 4868} 4869 4870SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4871 SDValue N0 = N->getOperand(0); 4872 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4873 EVT VT = N->getValueType(0); 4874 4875 // fold (fp_to_sint c1fp) -> c1 4876 if (N0CFP) 4877 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4878 4879 return SDValue(); 4880} 4881 4882SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4883 SDValue N0 = N->getOperand(0); 4884 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4885 EVT VT = N->getValueType(0); 4886 4887 // fold (fp_to_uint c1fp) -> c1 4888 if (N0CFP && VT != MVT::ppcf128) 4889 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4890 4891 return SDValue(); 4892} 4893 4894SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4895 SDValue N0 = N->getOperand(0); 4896 SDValue N1 = N->getOperand(1); 4897 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4898 EVT VT = N->getValueType(0); 4899 4900 // fold (fp_round c1fp) -> c1fp 4901 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4902 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4903 4904 // fold (fp_round (fp_extend x)) -> x 4905 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4906 return N0.getOperand(0); 4907 4908 // fold (fp_round (fp_round x)) -> (fp_round x) 4909 if (N0.getOpcode() == ISD::FP_ROUND) { 4910 // This is a value preserving truncation if both round's are. 4911 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4912 N0.getNode()->getConstantOperandVal(1) == 1; 4913 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4914 DAG.getIntPtrConstant(IsTrunc)); 4915 } 4916 4917 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4918 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4919 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4920 N0.getOperand(0), N1); 4921 AddToWorkList(Tmp.getNode()); 4922 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4923 Tmp, N0.getOperand(1)); 4924 } 4925 4926 return SDValue(); 4927} 4928 4929SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4930 SDValue N0 = N->getOperand(0); 4931 EVT VT = N->getValueType(0); 4932 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4933 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4934 4935 // fold (fp_round_inreg c1fp) -> c1fp 4936 if (N0CFP && isTypeLegal(EVT)) { 4937 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4938 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4939 } 4940 4941 return SDValue(); 4942} 4943 4944SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4945 SDValue N0 = N->getOperand(0); 4946 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4947 EVT VT = N->getValueType(0); 4948 4949 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4950 if (N->hasOneUse() && 4951 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4952 return SDValue(); 4953 4954 // fold (fp_extend c1fp) -> c1fp 4955 if (N0CFP && VT != MVT::ppcf128) 4956 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4957 4958 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4959 // value of X. 4960 if (N0.getOpcode() == ISD::FP_ROUND 4961 && N0.getNode()->getConstantOperandVal(1) == 1) { 4962 SDValue In = N0.getOperand(0); 4963 if (In.getValueType() == VT) return In; 4964 if (VT.bitsLT(In.getValueType())) 4965 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4966 In, N0.getOperand(1)); 4967 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4968 } 4969 4970 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4971 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4972 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4973 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4974 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4975 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4976 LN0->getChain(), 4977 LN0->getBasePtr(), LN0->getSrcValue(), 4978 LN0->getSrcValueOffset(), 4979 N0.getValueType(), 4980 LN0->isVolatile(), LN0->isNonTemporal(), 4981 LN0->getAlignment()); 4982 CombineTo(N, ExtLoad); 4983 CombineTo(N0.getNode(), 4984 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4985 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4986 ExtLoad.getValue(1)); 4987 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4988 } 4989 4990 return SDValue(); 4991} 4992 4993SDValue DAGCombiner::visitFNEG(SDNode *N) { 4994 SDValue N0 = N->getOperand(0); 4995 EVT VT = N->getValueType(0); 4996 4997 if (isNegatibleForFree(N0, LegalOperations)) 4998 return GetNegatedExpression(N0, DAG, LegalOperations); 4999 5000 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5001 // constant pool values. 5002 if (N0.getOpcode() == ISD::BIT_CONVERT && 5003 !VT.isVector() && 5004 N0.getNode()->hasOneUse() && 5005 N0.getOperand(0).getValueType().isInteger()) { 5006 SDValue Int = N0.getOperand(0); 5007 EVT IntVT = Int.getValueType(); 5008 if (IntVT.isInteger() && !IntVT.isVector()) { 5009 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5010 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5011 AddToWorkList(Int.getNode()); 5012 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5013 VT, Int); 5014 } 5015 } 5016 5017 return SDValue(); 5018} 5019 5020SDValue DAGCombiner::visitFABS(SDNode *N) { 5021 SDValue N0 = N->getOperand(0); 5022 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5023 EVT VT = N->getValueType(0); 5024 5025 // fold (fabs c1) -> fabs(c1) 5026 if (N0CFP && VT != MVT::ppcf128) 5027 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5028 // fold (fabs (fabs x)) -> (fabs x) 5029 if (N0.getOpcode() == ISD::FABS) 5030 return N->getOperand(0); 5031 // fold (fabs (fneg x)) -> (fabs x) 5032 // fold (fabs (fcopysign x, y)) -> (fabs x) 5033 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5034 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5035 5036 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5037 // constant pool values. 5038 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 5039 N0.getOperand(0).getValueType().isInteger() && 5040 !N0.getOperand(0).getValueType().isVector()) { 5041 SDValue Int = N0.getOperand(0); 5042 EVT IntVT = Int.getValueType(); 5043 if (IntVT.isInteger() && !IntVT.isVector()) { 5044 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5045 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5046 AddToWorkList(Int.getNode()); 5047 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5048 N->getValueType(0), Int); 5049 } 5050 } 5051 5052 return SDValue(); 5053} 5054 5055SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5056 SDValue Chain = N->getOperand(0); 5057 SDValue N1 = N->getOperand(1); 5058 SDValue N2 = N->getOperand(2); 5059 5060 // If N is a constant we could fold this into a fallthrough or unconditional 5061 // branch. However that doesn't happen very often in normal code, because 5062 // Instcombine/SimplifyCFG should have handled the available opportunities. 5063 // If we did this folding here, it would be necessary to update the 5064 // MachineBasicBlock CFG, which is awkward. 5065 5066 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5067 // on the target. 5068 if (N1.getOpcode() == ISD::SETCC && 5069 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5070 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5071 Chain, N1.getOperand(2), 5072 N1.getOperand(0), N1.getOperand(1), N2); 5073 } 5074 5075 SDNode *Trunc = 0; 5076 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 5077 // Look past truncate. 5078 Trunc = N1.getNode(); 5079 N1 = N1.getOperand(0); 5080 } 5081 5082 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 5083 // Match this pattern so that we can generate simpler code: 5084 // 5085 // %a = ... 5086 // %b = and i32 %a, 2 5087 // %c = srl i32 %b, 1 5088 // brcond i32 %c ... 5089 // 5090 // into 5091 // 5092 // %a = ... 5093 // %b = and i32 %a, 2 5094 // %c = setcc eq %b, 0 5095 // brcond %c ... 5096 // 5097 // This applies only when the AND constant value has one bit set and the 5098 // SRL constant is equal to the log2 of the AND constant. The back-end is 5099 // smart enough to convert the result into a TEST/JMP sequence. 5100 SDValue Op0 = N1.getOperand(0); 5101 SDValue Op1 = N1.getOperand(1); 5102 5103 if (Op0.getOpcode() == ISD::AND && 5104 Op1.getOpcode() == ISD::Constant) { 5105 SDValue AndOp1 = Op0.getOperand(1); 5106 5107 if (AndOp1.getOpcode() == ISD::Constant) { 5108 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5109 5110 if (AndConst.isPowerOf2() && 5111 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5112 SDValue SetCC = 5113 DAG.getSetCC(N->getDebugLoc(), 5114 TLI.getSetCCResultType(Op0.getValueType()), 5115 Op0, DAG.getConstant(0, Op0.getValueType()), 5116 ISD::SETNE); 5117 5118 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5119 MVT::Other, Chain, SetCC, N2); 5120 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5121 // will convert it back to (X & C1) >> C2. 5122 CombineTo(N, NewBRCond, false); 5123 // Truncate is dead. 5124 if (Trunc) { 5125 removeFromWorkList(Trunc); 5126 DAG.DeleteNode(Trunc); 5127 } 5128 // Replace the uses of SRL with SETCC 5129 WorkListRemover DeadNodes(*this); 5130 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5131 removeFromWorkList(N1.getNode()); 5132 DAG.DeleteNode(N1.getNode()); 5133 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5134 } 5135 } 5136 } 5137 } 5138 5139 // Transform br(xor(x, y)) -> br(x != y) 5140 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5141 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5142 SDNode *TheXor = N1.getNode(); 5143 SDValue Op0 = TheXor->getOperand(0); 5144 SDValue Op1 = TheXor->getOperand(1); 5145 if (Op0.getOpcode() == Op1.getOpcode()) { 5146 // Avoid missing important xor optimizations. 5147 SDValue Tmp = visitXOR(TheXor); 5148 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5149 DEBUG(dbgs() << "\nReplacing.8 "; 5150 TheXor->dump(&DAG); 5151 dbgs() << "\nWith: "; 5152 Tmp.getNode()->dump(&DAG); 5153 dbgs() << '\n'); 5154 WorkListRemover DeadNodes(*this); 5155 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5156 removeFromWorkList(TheXor); 5157 DAG.DeleteNode(TheXor); 5158 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5159 MVT::Other, Chain, Tmp, N2); 5160 } 5161 } 5162 5163 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5164 bool Equal = false; 5165 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5166 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5167 Op0.getOpcode() == ISD::XOR) { 5168 TheXor = Op0.getNode(); 5169 Equal = true; 5170 } 5171 5172 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; 5173 5174 EVT SetCCVT = NodeToReplace.getValueType(); 5175 if (LegalTypes) 5176 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5177 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5178 SetCCVT, 5179 Op0, Op1, 5180 Equal ? ISD::SETEQ : ISD::SETNE); 5181 // Replace the uses of XOR with SETCC 5182 WorkListRemover DeadNodes(*this); 5183 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes); 5184 removeFromWorkList(NodeToReplace.getNode()); 5185 DAG.DeleteNode(NodeToReplace.getNode()); 5186 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5187 MVT::Other, Chain, SetCC, N2); 5188 } 5189 } 5190 5191 return SDValue(); 5192} 5193 5194// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5195// 5196SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5197 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5198 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5199 5200 // If N is a constant we could fold this into a fallthrough or unconditional 5201 // branch. However that doesn't happen very often in normal code, because 5202 // Instcombine/SimplifyCFG should have handled the available opportunities. 5203 // If we did this folding here, it would be necessary to update the 5204 // MachineBasicBlock CFG, which is awkward. 5205 5206 // Use SimplifySetCC to simplify SETCC's. 5207 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5208 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5209 false); 5210 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5211 5212 // fold to a simpler setcc 5213 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5214 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5215 N->getOperand(0), Simp.getOperand(2), 5216 Simp.getOperand(0), Simp.getOperand(1), 5217 N->getOperand(4)); 5218 5219 return SDValue(); 5220} 5221 5222/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5223/// pre-indexed load / store when the base pointer is an add or subtract 5224/// and it has other uses besides the load / store. After the 5225/// transformation, the new indexed load / store has effectively folded 5226/// the add / subtract in and all of its other uses are redirected to the 5227/// new load / store. 5228bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5229 if (!LegalOperations) 5230 return false; 5231 5232 bool isLoad = true; 5233 SDValue Ptr; 5234 EVT VT; 5235 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5236 if (LD->isIndexed()) 5237 return false; 5238 VT = LD->getMemoryVT(); 5239 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5240 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5241 return false; 5242 Ptr = LD->getBasePtr(); 5243 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5244 if (ST->isIndexed()) 5245 return false; 5246 VT = ST->getMemoryVT(); 5247 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5248 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5249 return false; 5250 Ptr = ST->getBasePtr(); 5251 isLoad = false; 5252 } else { 5253 return false; 5254 } 5255 5256 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5257 // out. There is no reason to make this a preinc/predec. 5258 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5259 Ptr.getNode()->hasOneUse()) 5260 return false; 5261 5262 // Ask the target to do addressing mode selection. 5263 SDValue BasePtr; 5264 SDValue Offset; 5265 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5266 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5267 return false; 5268 // Don't create a indexed load / store with zero offset. 5269 if (isa<ConstantSDNode>(Offset) && 5270 cast<ConstantSDNode>(Offset)->isNullValue()) 5271 return false; 5272 5273 // Try turning it into a pre-indexed load / store except when: 5274 // 1) The new base ptr is a frame index. 5275 // 2) If N is a store and the new base ptr is either the same as or is a 5276 // predecessor of the value being stored. 5277 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5278 // that would create a cycle. 5279 // 4) All uses are load / store ops that use it as old base ptr. 5280 5281 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5282 // (plus the implicit offset) to a register to preinc anyway. 5283 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5284 return false; 5285 5286 // Check #2. 5287 if (!isLoad) { 5288 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5289 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5290 return false; 5291 } 5292 5293 // Now check for #3 and #4. 5294 bool RealUse = false; 5295 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5296 E = Ptr.getNode()->use_end(); I != E; ++I) { 5297 SDNode *Use = *I; 5298 if (Use == N) 5299 continue; 5300 if (Use->isPredecessorOf(N)) 5301 return false; 5302 5303 if (!((Use->getOpcode() == ISD::LOAD && 5304 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5305 (Use->getOpcode() == ISD::STORE && 5306 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5307 RealUse = true; 5308 } 5309 5310 if (!RealUse) 5311 return false; 5312 5313 SDValue Result; 5314 if (isLoad) 5315 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5316 BasePtr, Offset, AM); 5317 else 5318 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5319 BasePtr, Offset, AM); 5320 ++PreIndexedNodes; 5321 ++NodesCombined; 5322 DEBUG(dbgs() << "\nReplacing.4 "; 5323 N->dump(&DAG); 5324 dbgs() << "\nWith: "; 5325 Result.getNode()->dump(&DAG); 5326 dbgs() << '\n'); 5327 WorkListRemover DeadNodes(*this); 5328 if (isLoad) { 5329 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5330 &DeadNodes); 5331 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5332 &DeadNodes); 5333 } else { 5334 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5335 &DeadNodes); 5336 } 5337 5338 // Finally, since the node is now dead, remove it from the graph. 5339 DAG.DeleteNode(N); 5340 5341 // Replace the uses of Ptr with uses of the updated base value. 5342 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5343 &DeadNodes); 5344 removeFromWorkList(Ptr.getNode()); 5345 DAG.DeleteNode(Ptr.getNode()); 5346 5347 return true; 5348} 5349 5350/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5351/// add / sub of the base pointer node into a post-indexed load / store. 5352/// The transformation folded the add / subtract into the new indexed 5353/// load / store effectively and all of its uses are redirected to the 5354/// new load / store. 5355bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5356 if (!LegalOperations) 5357 return false; 5358 5359 bool isLoad = true; 5360 SDValue Ptr; 5361 EVT VT; 5362 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5363 if (LD->isIndexed()) 5364 return false; 5365 VT = LD->getMemoryVT(); 5366 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5367 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5368 return false; 5369 Ptr = LD->getBasePtr(); 5370 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5371 if (ST->isIndexed()) 5372 return false; 5373 VT = ST->getMemoryVT(); 5374 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5375 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5376 return false; 5377 Ptr = ST->getBasePtr(); 5378 isLoad = false; 5379 } else { 5380 return false; 5381 } 5382 5383 if (Ptr.getNode()->hasOneUse()) 5384 return false; 5385 5386 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5387 E = Ptr.getNode()->use_end(); I != E; ++I) { 5388 SDNode *Op = *I; 5389 if (Op == N || 5390 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5391 continue; 5392 5393 SDValue BasePtr; 5394 SDValue Offset; 5395 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5396 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5397 // Don't create a indexed load / store with zero offset. 5398 if (isa<ConstantSDNode>(Offset) && 5399 cast<ConstantSDNode>(Offset)->isNullValue()) 5400 continue; 5401 5402 // Try turning it into a post-indexed load / store except when 5403 // 1) All uses are load / store ops that use it as base ptr. 5404 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5405 // nor a successor of N. Otherwise, if Op is folded that would 5406 // create a cycle. 5407 5408 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5409 continue; 5410 5411 // Check for #1. 5412 bool TryNext = false; 5413 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5414 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5415 SDNode *Use = *II; 5416 if (Use == Ptr.getNode()) 5417 continue; 5418 5419 // If all the uses are load / store addresses, then don't do the 5420 // transformation. 5421 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5422 bool RealUse = false; 5423 for (SDNode::use_iterator III = Use->use_begin(), 5424 EEE = Use->use_end(); III != EEE; ++III) { 5425 SDNode *UseUse = *III; 5426 if (!((UseUse->getOpcode() == ISD::LOAD && 5427 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5428 (UseUse->getOpcode() == ISD::STORE && 5429 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5430 RealUse = true; 5431 } 5432 5433 if (!RealUse) { 5434 TryNext = true; 5435 break; 5436 } 5437 } 5438 } 5439 5440 if (TryNext) 5441 continue; 5442 5443 // Check for #2 5444 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5445 SDValue Result = isLoad 5446 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5447 BasePtr, Offset, AM) 5448 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5449 BasePtr, Offset, AM); 5450 ++PostIndexedNodes; 5451 ++NodesCombined; 5452 DEBUG(dbgs() << "\nReplacing.5 "; 5453 N->dump(&DAG); 5454 dbgs() << "\nWith: "; 5455 Result.getNode()->dump(&DAG); 5456 dbgs() << '\n'); 5457 WorkListRemover DeadNodes(*this); 5458 if (isLoad) { 5459 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5460 &DeadNodes); 5461 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5462 &DeadNodes); 5463 } else { 5464 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5465 &DeadNodes); 5466 } 5467 5468 // Finally, since the node is now dead, remove it from the graph. 5469 DAG.DeleteNode(N); 5470 5471 // Replace the uses of Use with uses of the updated base value. 5472 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5473 Result.getValue(isLoad ? 1 : 0), 5474 &DeadNodes); 5475 removeFromWorkList(Op); 5476 DAG.DeleteNode(Op); 5477 return true; 5478 } 5479 } 5480 } 5481 5482 return false; 5483} 5484 5485SDValue DAGCombiner::visitLOAD(SDNode *N) { 5486 LoadSDNode *LD = cast<LoadSDNode>(N); 5487 SDValue Chain = LD->getChain(); 5488 SDValue Ptr = LD->getBasePtr(); 5489 5490 // If load is not volatile and there are no uses of the loaded value (and 5491 // the updated indexed value in case of indexed loads), change uses of the 5492 // chain value into uses of the chain input (i.e. delete the dead load). 5493 if (!LD->isVolatile()) { 5494 if (N->getValueType(1) == MVT::Other) { 5495 // Unindexed loads. 5496 if (N->hasNUsesOfValue(0, 0)) { 5497 // It's not safe to use the two value CombineTo variant here. e.g. 5498 // v1, chain2 = load chain1, loc 5499 // v2, chain3 = load chain2, loc 5500 // v3 = add v2, c 5501 // Now we replace use of chain2 with chain1. This makes the second load 5502 // isomorphic to the one we are deleting, and thus makes this load live. 5503 DEBUG(dbgs() << "\nReplacing.6 "; 5504 N->dump(&DAG); 5505 dbgs() << "\nWith chain: "; 5506 Chain.getNode()->dump(&DAG); 5507 dbgs() << "\n"); 5508 WorkListRemover DeadNodes(*this); 5509 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5510 5511 if (N->use_empty()) { 5512 removeFromWorkList(N); 5513 DAG.DeleteNode(N); 5514 } 5515 5516 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5517 } 5518 } else { 5519 // Indexed loads. 5520 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5521 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5522 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5523 DEBUG(dbgs() << "\nReplacing.7 "; 5524 N->dump(&DAG); 5525 dbgs() << "\nWith: "; 5526 Undef.getNode()->dump(&DAG); 5527 dbgs() << " and 2 other values\n"); 5528 WorkListRemover DeadNodes(*this); 5529 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5530 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5531 DAG.getUNDEF(N->getValueType(1)), 5532 &DeadNodes); 5533 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5534 removeFromWorkList(N); 5535 DAG.DeleteNode(N); 5536 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5537 } 5538 } 5539 } 5540 5541 // If this load is directly stored, replace the load value with the stored 5542 // value. 5543 // TODO: Handle store large -> read small portion. 5544 // TODO: Handle TRUNCSTORE/LOADEXT 5545 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5546 !LD->isVolatile()) { 5547 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5548 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5549 if (PrevST->getBasePtr() == Ptr && 5550 PrevST->getValue().getValueType() == N->getValueType(0)) 5551 return CombineTo(N, Chain.getOperand(1), Chain); 5552 } 5553 } 5554 5555 // Try to infer better alignment information than the load already has. 5556 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5557 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5558 if (Align > LD->getAlignment()) 5559 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5560 LD->getValueType(0), 5561 Chain, Ptr, LD->getSrcValue(), 5562 LD->getSrcValueOffset(), LD->getMemoryVT(), 5563 LD->isVolatile(), LD->isNonTemporal(), Align); 5564 } 5565 } 5566 5567 if (CombinerAA) { 5568 // Walk up chain skipping non-aliasing memory nodes. 5569 SDValue BetterChain = FindBetterChain(N, Chain); 5570 5571 // If there is a better chain. 5572 if (Chain != BetterChain) { 5573 SDValue ReplLoad; 5574 5575 // Replace the chain to void dependency. 5576 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5577 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5578 BetterChain, Ptr, 5579 LD->getSrcValue(), LD->getSrcValueOffset(), 5580 LD->isVolatile(), LD->isNonTemporal(), 5581 LD->getAlignment()); 5582 } else { 5583 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5584 LD->getValueType(0), 5585 BetterChain, Ptr, LD->getSrcValue(), 5586 LD->getSrcValueOffset(), 5587 LD->getMemoryVT(), 5588 LD->isVolatile(), 5589 LD->isNonTemporal(), 5590 LD->getAlignment()); 5591 } 5592 5593 // Create token factor to keep old chain connected. 5594 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5595 MVT::Other, Chain, ReplLoad.getValue(1)); 5596 5597 // Make sure the new and old chains are cleaned up. 5598 AddToWorkList(Token.getNode()); 5599 5600 // Replace uses with load result and token factor. Don't add users 5601 // to work list. 5602 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5603 } 5604 } 5605 5606 // Try transforming N to an indexed load. 5607 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5608 return SDValue(N, 0); 5609 5610 return SDValue(); 5611} 5612 5613/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5614/// load is having specific bytes cleared out. If so, return the byte size 5615/// being masked out and the shift amount. 5616static std::pair<unsigned, unsigned> 5617CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5618 std::pair<unsigned, unsigned> Result(0, 0); 5619 5620 // Check for the structure we're looking for. 5621 if (V->getOpcode() != ISD::AND || 5622 !isa<ConstantSDNode>(V->getOperand(1)) || 5623 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5624 return Result; 5625 5626 // Check the chain and pointer. 5627 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5628 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5629 5630 // The store should be chained directly to the load or be an operand of a 5631 // tokenfactor. 5632 if (LD == Chain.getNode()) 5633 ; // ok. 5634 else if (Chain->getOpcode() != ISD::TokenFactor) 5635 return Result; // Fail. 5636 else { 5637 bool isOk = false; 5638 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5639 if (Chain->getOperand(i).getNode() == LD) { 5640 isOk = true; 5641 break; 5642 } 5643 if (!isOk) return Result; 5644 } 5645 5646 // This only handles simple types. 5647 if (V.getValueType() != MVT::i16 && 5648 V.getValueType() != MVT::i32 && 5649 V.getValueType() != MVT::i64) 5650 return Result; 5651 5652 // Check the constant mask. Invert it so that the bits being masked out are 5653 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5654 // follow the sign bit for uniformity. 5655 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5656 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5657 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5658 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5659 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5660 if (NotMaskLZ == 64) return Result; // All zero mask. 5661 5662 // See if we have a continuous run of bits. If so, we have 0*1+0* 5663 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5664 return Result; 5665 5666 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5667 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5668 NotMaskLZ -= 64-V.getValueSizeInBits(); 5669 5670 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5671 switch (MaskedBytes) { 5672 case 1: 5673 case 2: 5674 case 4: break; 5675 default: return Result; // All one mask, or 5-byte mask. 5676 } 5677 5678 // Verify that the first bit starts at a multiple of mask so that the access 5679 // is aligned the same as the access width. 5680 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 5681 5682 Result.first = MaskedBytes; 5683 Result.second = NotMaskTZ/8; 5684 return Result; 5685} 5686 5687 5688/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 5689/// provides a value as specified by MaskInfo. If so, replace the specified 5690/// store with a narrower store of truncated IVal. 5691static SDNode * 5692ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 5693 SDValue IVal, StoreSDNode *St, 5694 DAGCombiner *DC) { 5695 unsigned NumBytes = MaskInfo.first; 5696 unsigned ByteShift = MaskInfo.second; 5697 SelectionDAG &DAG = DC->getDAG(); 5698 5699 // Check to see if IVal is all zeros in the part being masked in by the 'or' 5700 // that uses this. If not, this is not a replacement. 5701 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 5702 ByteShift*8, (ByteShift+NumBytes)*8); 5703 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 5704 5705 // Check that it is legal on the target to do this. It is legal if the new 5706 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 5707 // legalization. 5708 MVT VT = MVT::getIntegerVT(NumBytes*8); 5709 if (!DC->isTypeLegal(VT)) 5710 return 0; 5711 5712 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 5713 // shifted by ByteShift and truncated down to NumBytes. 5714 if (ByteShift) 5715 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 5716 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy())); 5717 5718 // Figure out the offset for the store and the alignment of the access. 5719 unsigned StOffset; 5720 unsigned NewAlign = St->getAlignment(); 5721 5722 if (DAG.getTargetLoweringInfo().isLittleEndian()) 5723 StOffset = ByteShift; 5724 else 5725 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 5726 5727 SDValue Ptr = St->getBasePtr(); 5728 if (StOffset) { 5729 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 5730 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 5731 NewAlign = MinAlign(NewAlign, StOffset); 5732 } 5733 5734 // Truncate down to the new size. 5735 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 5736 5737 ++OpsNarrowed; 5738 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 5739 St->getSrcValue(), St->getSrcValueOffset()+StOffset, 5740 false, false, NewAlign).getNode(); 5741} 5742 5743 5744/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5745/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5746/// of the loaded bits, try narrowing the load and store if it would end up 5747/// being a win for performance or code size. 5748SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5749 StoreSDNode *ST = cast<StoreSDNode>(N); 5750 if (ST->isVolatile()) 5751 return SDValue(); 5752 5753 SDValue Chain = ST->getChain(); 5754 SDValue Value = ST->getValue(); 5755 SDValue Ptr = ST->getBasePtr(); 5756 EVT VT = Value.getValueType(); 5757 5758 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5759 return SDValue(); 5760 5761 unsigned Opc = Value.getOpcode(); 5762 5763 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 5764 // is a byte mask indicating a consecutive number of bytes, check to see if 5765 // Y is known to provide just those bytes. If so, we try to replace the 5766 // load + replace + store sequence with a single (narrower) store, which makes 5767 // the load dead. 5768 if (Opc == ISD::OR) { 5769 std::pair<unsigned, unsigned> MaskedLoad; 5770 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 5771 if (MaskedLoad.first) 5772 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5773 Value.getOperand(1), ST,this)) 5774 return SDValue(NewST, 0); 5775 5776 // Or is commutative, so try swapping X and Y. 5777 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 5778 if (MaskedLoad.first) 5779 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5780 Value.getOperand(0), ST,this)) 5781 return SDValue(NewST, 0); 5782 } 5783 5784 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5785 Value.getOperand(1).getOpcode() != ISD::Constant) 5786 return SDValue(); 5787 5788 SDValue N0 = Value.getOperand(0); 5789 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5790 LoadSDNode *LD = cast<LoadSDNode>(N0); 5791 if (LD->getBasePtr() != Ptr) 5792 return SDValue(); 5793 5794 // Find the type to narrow it the load / op / store to. 5795 SDValue N1 = Value.getOperand(1); 5796 unsigned BitWidth = N1.getValueSizeInBits(); 5797 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5798 if (Opc == ISD::AND) 5799 Imm ^= APInt::getAllOnesValue(BitWidth); 5800 if (Imm == 0 || Imm.isAllOnesValue()) 5801 return SDValue(); 5802 unsigned ShAmt = Imm.countTrailingZeros(); 5803 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5804 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5805 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5806 while (NewBW < BitWidth && 5807 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5808 TLI.isNarrowingProfitable(VT, NewVT))) { 5809 NewBW = NextPowerOf2(NewBW); 5810 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5811 } 5812 if (NewBW >= BitWidth) 5813 return SDValue(); 5814 5815 // If the lsb changed does not start at the type bitwidth boundary, 5816 // start at the previous one. 5817 if (ShAmt % NewBW) 5818 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5819 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5820 if ((Imm & Mask) == Imm) { 5821 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5822 if (Opc == ISD::AND) 5823 NewImm ^= APInt::getAllOnesValue(NewBW); 5824 uint64_t PtrOff = ShAmt / 8; 5825 // For big endian targets, we need to adjust the offset to the pointer to 5826 // load the correct bytes. 5827 if (TLI.isBigEndian()) 5828 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5829 5830 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5831 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 5832 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 5833 return SDValue(); 5834 5835 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5836 Ptr.getValueType(), Ptr, 5837 DAG.getConstant(PtrOff, Ptr.getValueType())); 5838 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5839 LD->getChain(), NewPtr, 5840 LD->getSrcValue(), LD->getSrcValueOffset(), 5841 LD->isVolatile(), LD->isNonTemporal(), 5842 NewAlign); 5843 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5844 DAG.getConstant(NewImm, NewVT)); 5845 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5846 NewVal, NewPtr, 5847 ST->getSrcValue(), ST->getSrcValueOffset(), 5848 false, false, NewAlign); 5849 5850 AddToWorkList(NewPtr.getNode()); 5851 AddToWorkList(NewLD.getNode()); 5852 AddToWorkList(NewVal.getNode()); 5853 WorkListRemover DeadNodes(*this); 5854 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5855 &DeadNodes); 5856 ++OpsNarrowed; 5857 return NewST; 5858 } 5859 } 5860 5861 return SDValue(); 5862} 5863 5864SDValue DAGCombiner::visitSTORE(SDNode *N) { 5865 StoreSDNode *ST = cast<StoreSDNode>(N); 5866 SDValue Chain = ST->getChain(); 5867 SDValue Value = ST->getValue(); 5868 SDValue Ptr = ST->getBasePtr(); 5869 5870 // If this is a store of a bit convert, store the input value if the 5871 // resultant store does not need a higher alignment than the original. 5872 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5873 ST->isUnindexed()) { 5874 unsigned OrigAlign = ST->getAlignment(); 5875 EVT SVT = Value.getOperand(0).getValueType(); 5876 unsigned Align = TLI.getTargetData()-> 5877 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5878 if (Align <= OrigAlign && 5879 ((!LegalOperations && !ST->isVolatile()) || 5880 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5881 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5882 Ptr, ST->getSrcValue(), 5883 ST->getSrcValueOffset(), ST->isVolatile(), 5884 ST->isNonTemporal(), OrigAlign); 5885 } 5886 5887 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5888 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5889 // NOTE: If the original store is volatile, this transform must not increase 5890 // the number of stores. For example, on x86-32 an f64 can be stored in one 5891 // processor operation but an i64 (which is not legal) requires two. So the 5892 // transform should not be done in this case. 5893 if (Value.getOpcode() != ISD::TargetConstantFP) { 5894 SDValue Tmp; 5895 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5896 default: llvm_unreachable("Unknown FP type"); 5897 case MVT::f80: // We don't do this for these yet. 5898 case MVT::f128: 5899 case MVT::ppcf128: 5900 break; 5901 case MVT::f32: 5902 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 5903 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5904 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5905 bitcastToAPInt().getZExtValue(), MVT::i32); 5906 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5907 Ptr, ST->getSrcValue(), 5908 ST->getSrcValueOffset(), ST->isVolatile(), 5909 ST->isNonTemporal(), ST->getAlignment()); 5910 } 5911 break; 5912 case MVT::f64: 5913 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 5914 !ST->isVolatile()) || 5915 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5916 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5917 getZExtValue(), MVT::i64); 5918 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5919 Ptr, ST->getSrcValue(), 5920 ST->getSrcValueOffset(), ST->isVolatile(), 5921 ST->isNonTemporal(), ST->getAlignment()); 5922 } else if (!ST->isVolatile() && 5923 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5924 // Many FP stores are not made apparent until after legalize, e.g. for 5925 // argument passing. Since this is so common, custom legalize the 5926 // 64-bit integer store into two 32-bit stores. 5927 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5928 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5929 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5930 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5931 5932 int SVOffset = ST->getSrcValueOffset(); 5933 unsigned Alignment = ST->getAlignment(); 5934 bool isVolatile = ST->isVolatile(); 5935 bool isNonTemporal = ST->isNonTemporal(); 5936 5937 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5938 Ptr, ST->getSrcValue(), 5939 ST->getSrcValueOffset(), 5940 isVolatile, isNonTemporal, 5941 ST->getAlignment()); 5942 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5943 DAG.getConstant(4, Ptr.getValueType())); 5944 SVOffset += 4; 5945 Alignment = MinAlign(Alignment, 4U); 5946 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5947 Ptr, ST->getSrcValue(), 5948 SVOffset, isVolatile, isNonTemporal, 5949 Alignment); 5950 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5951 St0, St1); 5952 } 5953 5954 break; 5955 } 5956 } 5957 } 5958 5959 // Try to infer better alignment information than the store already has. 5960 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5961 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5962 if (Align > ST->getAlignment()) 5963 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5964 Ptr, ST->getSrcValue(), 5965 ST->getSrcValueOffset(), ST->getMemoryVT(), 5966 ST->isVolatile(), ST->isNonTemporal(), Align); 5967 } 5968 } 5969 5970 if (CombinerAA) { 5971 // Walk up chain skipping non-aliasing memory nodes. 5972 SDValue BetterChain = FindBetterChain(N, Chain); 5973 5974 // If there is a better chain. 5975 if (Chain != BetterChain) { 5976 SDValue ReplStore; 5977 5978 // Replace the chain to avoid dependency. 5979 if (ST->isTruncatingStore()) { 5980 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5981 ST->getSrcValue(),ST->getSrcValueOffset(), 5982 ST->getMemoryVT(), ST->isVolatile(), 5983 ST->isNonTemporal(), ST->getAlignment()); 5984 } else { 5985 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5986 ST->getSrcValue(), ST->getSrcValueOffset(), 5987 ST->isVolatile(), ST->isNonTemporal(), 5988 ST->getAlignment()); 5989 } 5990 5991 // Create token to keep both nodes around. 5992 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5993 MVT::Other, Chain, ReplStore); 5994 5995 // Make sure the new and old chains are cleaned up. 5996 AddToWorkList(Token.getNode()); 5997 5998 // Don't add users to work list. 5999 return CombineTo(N, Token, false); 6000 } 6001 } 6002 6003 // Try transforming N to an indexed store. 6004 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6005 return SDValue(N, 0); 6006 6007 // FIXME: is there such a thing as a truncating indexed store? 6008 if (ST->isTruncatingStore() && ST->isUnindexed() && 6009 Value.getValueType().isInteger()) { 6010 // See if we can simplify the input to this truncstore with knowledge that 6011 // only the low bits are being used. For example: 6012 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6013 SDValue Shorter = 6014 GetDemandedBits(Value, 6015 APInt::getLowBitsSet(Value.getValueSizeInBits(), 6016 ST->getMemoryVT().getSizeInBits())); 6017 AddToWorkList(Value.getNode()); 6018 if (Shorter.getNode()) 6019 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6020 Ptr, ST->getSrcValue(), 6021 ST->getSrcValueOffset(), ST->getMemoryVT(), 6022 ST->isVolatile(), ST->isNonTemporal(), 6023 ST->getAlignment()); 6024 6025 // Otherwise, see if we can simplify the operation with 6026 // SimplifyDemandedBits, which only works if the value has a single use. 6027 if (SimplifyDemandedBits(Value, 6028 APInt::getLowBitsSet( 6029 Value.getValueType().getScalarType().getSizeInBits(), 6030 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6031 return SDValue(N, 0); 6032 } 6033 6034 // If this is a load followed by a store to the same location, then the store 6035 // is dead/noop. 6036 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6037 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6038 ST->isUnindexed() && !ST->isVolatile() && 6039 // There can't be any side effects between the load and store, such as 6040 // a call or store. 6041 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6042 // The store is dead, remove it. 6043 return Chain; 6044 } 6045 } 6046 6047 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6048 // truncating store. We can do this even if this is already a truncstore. 6049 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6050 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6051 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6052 ST->getMemoryVT())) { 6053 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6054 Ptr, ST->getSrcValue(), 6055 ST->getSrcValueOffset(), ST->getMemoryVT(), 6056 ST->isVolatile(), ST->isNonTemporal(), 6057 ST->getAlignment()); 6058 } 6059 6060 return ReduceLoadOpStoreWidth(N); 6061} 6062 6063SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6064 SDValue InVec = N->getOperand(0); 6065 SDValue InVal = N->getOperand(1); 6066 SDValue EltNo = N->getOperand(2); 6067 6068 // If the inserted element is an UNDEF, just use the input vector. 6069 if (InVal.getOpcode() == ISD::UNDEF) 6070 return InVec; 6071 6072 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6073 // vector with the inserted element. 6074 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6075 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6076 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6077 InVec.getNode()->op_end()); 6078 if (Elt < Ops.size()) 6079 Ops[Elt] = InVal; 6080 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6081 InVec.getValueType(), &Ops[0], Ops.size()); 6082 } 6083 // If the invec is an UNDEF and if EltNo is a constant, create a new 6084 // BUILD_VECTOR with undef elements and the inserted element. 6085 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 6086 isa<ConstantSDNode>(EltNo)) { 6087 EVT VT = InVec.getValueType(); 6088 EVT EltVT = VT.getVectorElementType(); 6089 unsigned NElts = VT.getVectorNumElements(); 6090 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6091 6092 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6093 if (Elt < Ops.size()) 6094 Ops[Elt] = InVal; 6095 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6096 InVec.getValueType(), &Ops[0], Ops.size()); 6097 } 6098 return SDValue(); 6099} 6100 6101SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6102 // (vextract (scalar_to_vector val, 0) -> val 6103 SDValue InVec = N->getOperand(0); 6104 6105 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6106 // Check if the result type doesn't match the inserted element type. A 6107 // SCALAR_TO_VECTOR may truncate the inserted element and the 6108 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6109 EVT EltVT = InVec.getValueType().getVectorElementType(); 6110 SDValue InOp = InVec.getOperand(0); 6111 EVT NVT = N->getValueType(0); 6112 if (InOp.getValueType() != NVT) { 6113 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6114 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6115 } 6116 return InOp; 6117 } 6118 6119 // Perform only after legalization to ensure build_vector / vector_shuffle 6120 // optimizations have already been done. 6121 if (!LegalOperations) return SDValue(); 6122 6123 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6124 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6125 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6126 SDValue EltNo = N->getOperand(1); 6127 6128 if (isa<ConstantSDNode>(EltNo)) { 6129 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6130 bool NewLoad = false; 6131 bool BCNumEltsChanged = false; 6132 EVT VT = InVec.getValueType(); 6133 EVT ExtVT = VT.getVectorElementType(); 6134 EVT LVT = ExtVT; 6135 6136 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 6137 EVT BCVT = InVec.getOperand(0).getValueType(); 6138 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6139 return SDValue(); 6140 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6141 BCNumEltsChanged = true; 6142 InVec = InVec.getOperand(0); 6143 ExtVT = BCVT.getVectorElementType(); 6144 NewLoad = true; 6145 } 6146 6147 LoadSDNode *LN0 = NULL; 6148 const ShuffleVectorSDNode *SVN = NULL; 6149 if (ISD::isNormalLoad(InVec.getNode())) { 6150 LN0 = cast<LoadSDNode>(InVec); 6151 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6152 InVec.getOperand(0).getValueType() == ExtVT && 6153 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6154 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6155 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6156 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6157 // => 6158 // (load $addr+1*size) 6159 6160 // If the bit convert changed the number of elements, it is unsafe 6161 // to examine the mask. 6162 if (BCNumEltsChanged) 6163 return SDValue(); 6164 6165 // Select the input vector, guarding against out of range extract vector. 6166 unsigned NumElems = VT.getVectorNumElements(); 6167 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 6168 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6169 6170 if (InVec.getOpcode() == ISD::BIT_CONVERT) 6171 InVec = InVec.getOperand(0); 6172 if (ISD::isNormalLoad(InVec.getNode())) { 6173 LN0 = cast<LoadSDNode>(InVec); 6174 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6175 } 6176 } 6177 6178 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 6179 return SDValue(); 6180 6181 unsigned Align = LN0->getAlignment(); 6182 if (NewLoad) { 6183 // Check the resultant load doesn't need a higher alignment than the 6184 // original load. 6185 unsigned NewAlign = 6186 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6187 6188 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6189 return SDValue(); 6190 6191 Align = NewAlign; 6192 } 6193 6194 SDValue NewPtr = LN0->getBasePtr(); 6195 if (Elt) { 6196 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 6197 EVT PtrType = NewPtr.getValueType(); 6198 if (TLI.isBigEndian()) 6199 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6200 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6201 DAG.getConstant(PtrOff, PtrType)); 6202 } 6203 6204 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6205 LN0->getSrcValue(), LN0->getSrcValueOffset(), 6206 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6207 } 6208 6209 return SDValue(); 6210} 6211 6212SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6213 unsigned NumInScalars = N->getNumOperands(); 6214 EVT VT = N->getValueType(0); 6215 6216 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6217 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6218 // at most two distinct vectors, turn this into a shuffle node. 6219 SDValue VecIn1, VecIn2; 6220 for (unsigned i = 0; i != NumInScalars; ++i) { 6221 // Ignore undef inputs. 6222 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6223 6224 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6225 // constant index, bail out. 6226 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6227 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6228 VecIn1 = VecIn2 = SDValue(0, 0); 6229 break; 6230 } 6231 6232 // If the input vector type disagrees with the result of the build_vector, 6233 // we can't make a shuffle. 6234 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6235 if (ExtractedFromVec.getValueType() != VT) { 6236 VecIn1 = VecIn2 = SDValue(0, 0); 6237 break; 6238 } 6239 6240 // Otherwise, remember this. We allow up to two distinct input vectors. 6241 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6242 continue; 6243 6244 if (VecIn1.getNode() == 0) { 6245 VecIn1 = ExtractedFromVec; 6246 } else if (VecIn2.getNode() == 0) { 6247 VecIn2 = ExtractedFromVec; 6248 } else { 6249 // Too many inputs. 6250 VecIn1 = VecIn2 = SDValue(0, 0); 6251 break; 6252 } 6253 } 6254 6255 // If everything is good, we can make a shuffle operation. 6256 if (VecIn1.getNode()) { 6257 SmallVector<int, 8> Mask; 6258 for (unsigned i = 0; i != NumInScalars; ++i) { 6259 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6260 Mask.push_back(-1); 6261 continue; 6262 } 6263 6264 // If extracting from the first vector, just use the index directly. 6265 SDValue Extract = N->getOperand(i); 6266 SDValue ExtVal = Extract.getOperand(1); 6267 if (Extract.getOperand(0) == VecIn1) { 6268 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6269 if (ExtIndex > VT.getVectorNumElements()) 6270 return SDValue(); 6271 6272 Mask.push_back(ExtIndex); 6273 continue; 6274 } 6275 6276 // Otherwise, use InIdx + VecSize 6277 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6278 Mask.push_back(Idx+NumInScalars); 6279 } 6280 6281 // Add count and size info. 6282 if (!isTypeLegal(VT)) 6283 return SDValue(); 6284 6285 // Return the new VECTOR_SHUFFLE node. 6286 SDValue Ops[2]; 6287 Ops[0] = VecIn1; 6288 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6289 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6290 } 6291 6292 return SDValue(); 6293} 6294 6295SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6296 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6297 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6298 // inputs come from at most two distinct vectors, turn this into a shuffle 6299 // node. 6300 6301 // If we only have one input vector, we don't need to do any concatenation. 6302 if (N->getNumOperands() == 1) 6303 return N->getOperand(0); 6304 6305 return SDValue(); 6306} 6307 6308SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6309 return SDValue(); 6310 6311 EVT VT = N->getValueType(0); 6312 unsigned NumElts = VT.getVectorNumElements(); 6313 6314 SDValue N0 = N->getOperand(0); 6315 6316 assert(N0.getValueType().getVectorNumElements() == NumElts && 6317 "Vector shuffle must be normalized in DAG"); 6318 6319 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6320 6321 // If it is a splat, check if the argument vector is a build_vector with 6322 // all scalar elements the same. 6323 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 6324 SDNode *V = N0.getNode(); 6325 6326 // If this is a bit convert that changes the element type of the vector but 6327 // not the number of vector elements, look through it. Be careful not to 6328 // look though conversions that change things like v4f32 to v2f64. 6329 if (V->getOpcode() == ISD::BIT_CONVERT) { 6330 SDValue ConvInput = V->getOperand(0); 6331 if (ConvInput.getValueType().isVector() && 6332 ConvInput.getValueType().getVectorNumElements() == NumElts) 6333 V = ConvInput.getNode(); 6334 } 6335 6336 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6337 unsigned NumElems = V->getNumOperands(); 6338 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 6339 if (NumElems > BaseIdx) { 6340 SDValue Base; 6341 bool AllSame = true; 6342 for (unsigned i = 0; i != NumElems; ++i) { 6343 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6344 Base = V->getOperand(i); 6345 break; 6346 } 6347 } 6348 // Splat of <u, u, u, u>, return <u, u, u, u> 6349 if (!Base.getNode()) 6350 return N0; 6351 for (unsigned i = 0; i != NumElems; ++i) { 6352 if (V->getOperand(i) != Base) { 6353 AllSame = false; 6354 break; 6355 } 6356 } 6357 // Splat of <x, x, x, x>, return <x, x, x, x> 6358 if (AllSame) 6359 return N0; 6360 } 6361 } 6362 } 6363 return SDValue(); 6364} 6365 6366/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6367/// an AND to a vector_shuffle with the destination vector and a zero vector. 6368/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6369/// vector_shuffle V, Zero, <0, 4, 2, 4> 6370SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6371 EVT VT = N->getValueType(0); 6372 DebugLoc dl = N->getDebugLoc(); 6373 SDValue LHS = N->getOperand(0); 6374 SDValue RHS = N->getOperand(1); 6375 if (N->getOpcode() == ISD::AND) { 6376 if (RHS.getOpcode() == ISD::BIT_CONVERT) 6377 RHS = RHS.getOperand(0); 6378 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6379 SmallVector<int, 8> Indices; 6380 unsigned NumElts = RHS.getNumOperands(); 6381 for (unsigned i = 0; i != NumElts; ++i) { 6382 SDValue Elt = RHS.getOperand(i); 6383 if (!isa<ConstantSDNode>(Elt)) 6384 return SDValue(); 6385 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6386 Indices.push_back(i); 6387 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6388 Indices.push_back(NumElts); 6389 else 6390 return SDValue(); 6391 } 6392 6393 // Let's see if the target supports this vector_shuffle. 6394 EVT RVT = RHS.getValueType(); 6395 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6396 return SDValue(); 6397 6398 // Return the new VECTOR_SHUFFLE node. 6399 EVT EltVT = RVT.getVectorElementType(); 6400 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6401 DAG.getConstant(0, EltVT)); 6402 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6403 RVT, &ZeroOps[0], ZeroOps.size()); 6404 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 6405 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6406 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 6407 } 6408 } 6409 6410 return SDValue(); 6411} 6412 6413/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6414SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6415 // After legalize, the target may be depending on adds and other 6416 // binary ops to provide legal ways to construct constants or other 6417 // things. Simplifying them may result in a loss of legality. 6418 if (LegalOperations) return SDValue(); 6419 6420 EVT VT = N->getValueType(0); 6421 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 6422 6423 EVT EltType = VT.getVectorElementType(); 6424 SDValue LHS = N->getOperand(0); 6425 SDValue RHS = N->getOperand(1); 6426 SDValue Shuffle = XformToShuffleWithZero(N); 6427 if (Shuffle.getNode()) return Shuffle; 6428 6429 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6430 // this operation. 6431 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6432 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6433 SmallVector<SDValue, 8> Ops; 6434 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6435 SDValue LHSOp = LHS.getOperand(i); 6436 SDValue RHSOp = RHS.getOperand(i); 6437 // If these two elements can't be folded, bail out. 6438 if ((LHSOp.getOpcode() != ISD::UNDEF && 6439 LHSOp.getOpcode() != ISD::Constant && 6440 LHSOp.getOpcode() != ISD::ConstantFP) || 6441 (RHSOp.getOpcode() != ISD::UNDEF && 6442 RHSOp.getOpcode() != ISD::Constant && 6443 RHSOp.getOpcode() != ISD::ConstantFP)) 6444 break; 6445 6446 // Can't fold divide by zero. 6447 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6448 N->getOpcode() == ISD::FDIV) { 6449 if ((RHSOp.getOpcode() == ISD::Constant && 6450 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6451 (RHSOp.getOpcode() == ISD::ConstantFP && 6452 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6453 break; 6454 } 6455 6456 // If the vector element type is not legal, the BUILD_VECTOR operands 6457 // are promoted and implicitly truncated. Make that explicit here. 6458 if (LHSOp.getValueType() != EltType) 6459 LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp); 6460 if (RHSOp.getValueType() != EltType) 6461 RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp); 6462 6463 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType, 6464 LHSOp, RHSOp); 6465 if (FoldOp.getOpcode() != ISD::UNDEF && 6466 FoldOp.getOpcode() != ISD::Constant && 6467 FoldOp.getOpcode() != ISD::ConstantFP) 6468 break; 6469 Ops.push_back(FoldOp); 6470 AddToWorkList(FoldOp.getNode()); 6471 } 6472 6473 if (Ops.size() == LHS.getNumOperands()) { 6474 EVT VT = LHS.getValueType(); 6475 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 6476 &Ops[0], Ops.size()); 6477 } 6478 } 6479 6480 return SDValue(); 6481} 6482 6483SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6484 SDValue N1, SDValue N2){ 6485 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6486 6487 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6488 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6489 6490 // If we got a simplified select_cc node back from SimplifySelectCC, then 6491 // break it down into a new SETCC node, and a new SELECT node, and then return 6492 // the SELECT node, since we were called with a SELECT node. 6493 if (SCC.getNode()) { 6494 // Check to see if we got a select_cc back (to turn into setcc/select). 6495 // Otherwise, just return whatever node we got back, like fabs. 6496 if (SCC.getOpcode() == ISD::SELECT_CC) { 6497 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6498 N0.getValueType(), 6499 SCC.getOperand(0), SCC.getOperand(1), 6500 SCC.getOperand(4)); 6501 AddToWorkList(SETCC.getNode()); 6502 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6503 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6504 } 6505 6506 return SCC; 6507 } 6508 return SDValue(); 6509} 6510 6511/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6512/// are the two values being selected between, see if we can simplify the 6513/// select. Callers of this should assume that TheSelect is deleted if this 6514/// returns true. As such, they should return the appropriate thing (e.g. the 6515/// node) back to the top-level of the DAG combiner loop to avoid it being 6516/// looked at. 6517bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6518 SDValue RHS) { 6519 6520 // If this is a select from two identical things, try to pull the operation 6521 // through the select. 6522 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 6523 // If this is a load and the token chain is identical, replace the select 6524 // of two loads with a load through a select of the address to load from. 6525 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6526 // constants have been dropped into the constant pool. 6527 if (LHS.getOpcode() == ISD::LOAD && 6528 // Do not let this transformation reduce the number of volatile loads. 6529 !cast<LoadSDNode>(LHS)->isVolatile() && 6530 !cast<LoadSDNode>(RHS)->isVolatile() && 6531 // Token chains must be identical. 6532 LHS.getOperand(0) == RHS.getOperand(0)) { 6533 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6534 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6535 6536 // If this is an EXTLOAD, the VT's must match. 6537 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 6538 // FIXME: this discards src value information. This is 6539 // over-conservative. It would be beneficial to be able to remember 6540 // both potential memory locations. Since we are discarding 6541 // src value info, don't do the transformation if the memory 6542 // locations are not in the default address space. 6543 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0; 6544 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) { 6545 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType())) 6546 LLDAddrSpace = PT->getAddressSpace(); 6547 } 6548 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) { 6549 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType())) 6550 RLDAddrSpace = PT->getAddressSpace(); 6551 } 6552 SDValue Addr; 6553 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) { 6554 if (TheSelect->getOpcode() == ISD::SELECT) { 6555 // Check that the condition doesn't reach either load. If so, folding 6556 // this will induce a cycle into the DAG. 6557 if ((!LLD->hasAnyUseOfValue(1) || 6558 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 6559 (!RLD->hasAnyUseOfValue(1) || 6560 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 6561 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 6562 LLD->getBasePtr().getValueType(), 6563 TheSelect->getOperand(0), LLD->getBasePtr(), 6564 RLD->getBasePtr()); 6565 } 6566 } else { 6567 // Check that the condition doesn't reach either load. If so, folding 6568 // this will induce a cycle into the DAG. 6569 if ((!LLD->hasAnyUseOfValue(1) || 6570 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 6571 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 6572 (!RLD->hasAnyUseOfValue(1) || 6573 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 6574 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 6575 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 6576 LLD->getBasePtr().getValueType(), 6577 TheSelect->getOperand(0), 6578 TheSelect->getOperand(1), 6579 LLD->getBasePtr(), RLD->getBasePtr(), 6580 TheSelect->getOperand(4)); 6581 } 6582 } 6583 } 6584 6585 if (Addr.getNode()) { 6586 SDValue Load; 6587 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 6588 Load = DAG.getLoad(TheSelect->getValueType(0), 6589 TheSelect->getDebugLoc(), 6590 LLD->getChain(), 6591 Addr, 0, 0, 6592 LLD->isVolatile(), 6593 LLD->isNonTemporal(), 6594 LLD->getAlignment()); 6595 } else { 6596 Load = DAG.getExtLoad(LLD->getExtensionType(), 6597 TheSelect->getDebugLoc(), 6598 TheSelect->getValueType(0), 6599 LLD->getChain(), Addr, 0, 0, 6600 LLD->getMemoryVT(), 6601 LLD->isVolatile(), 6602 LLD->isNonTemporal(), 6603 LLD->getAlignment()); 6604 } 6605 6606 // Users of the select now use the result of the load. 6607 CombineTo(TheSelect, Load); 6608 6609 // Users of the old loads now use the new load's chain. We know the 6610 // old-load value is dead now. 6611 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 6612 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 6613 return true; 6614 } 6615 } 6616 } 6617 } 6618 6619 return false; 6620} 6621 6622/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 6623/// where 'cond' is the comparison specified by CC. 6624SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 6625 SDValue N2, SDValue N3, 6626 ISD::CondCode CC, bool NotExtCompare) { 6627 // (x ? y : y) -> y. 6628 if (N2 == N3) return N2; 6629 6630 EVT VT = N2.getValueType(); 6631 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 6632 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 6633 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 6634 6635 // Determine if the condition we're dealing with is constant 6636 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 6637 N0, N1, CC, DL, false); 6638 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 6639 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 6640 6641 // fold select_cc true, x, y -> x 6642 if (SCCC && !SCCC->isNullValue()) 6643 return N2; 6644 // fold select_cc false, x, y -> y 6645 if (SCCC && SCCC->isNullValue()) 6646 return N3; 6647 6648 // Check to see if we can simplify the select into an fabs node 6649 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 6650 // Allow either -0.0 or 0.0 6651 if (CFP->getValueAPF().isZero()) { 6652 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 6653 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 6654 N0 == N2 && N3.getOpcode() == ISD::FNEG && 6655 N2 == N3.getOperand(0)) 6656 return DAG.getNode(ISD::FABS, DL, VT, N0); 6657 6658 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 6659 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 6660 N0 == N3 && N2.getOpcode() == ISD::FNEG && 6661 N2.getOperand(0) == N3) 6662 return DAG.getNode(ISD::FABS, DL, VT, N3); 6663 } 6664 } 6665 6666 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 6667 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 6668 // in it. This is a win when the constant is not otherwise available because 6669 // it replaces two constant pool loads with one. We only do this if the FP 6670 // type is known to be legal, because if it isn't, then we are before legalize 6671 // types an we want the other legalization to happen first (e.g. to avoid 6672 // messing with soft float) and if the ConstantFP is not legal, because if 6673 // it is legal, we may not need to store the FP constant in a constant pool. 6674 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 6675 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 6676 if (TLI.isTypeLegal(N2.getValueType()) && 6677 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 6678 TargetLowering::Legal) && 6679 // If both constants have multiple uses, then we won't need to do an 6680 // extra load, they are likely around in registers for other users. 6681 (TV->hasOneUse() || FV->hasOneUse())) { 6682 Constant *Elts[] = { 6683 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6684 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6685 }; 6686 const Type *FPTy = Elts[0]->getType(); 6687 const TargetData &TD = *TLI.getTargetData(); 6688 6689 // Create a ConstantArray of the two constants. 6690 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6691 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6692 TD.getPrefTypeAlignment(FPTy)); 6693 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6694 6695 // Get the offsets to the 0 and 1 element of the array so that we can 6696 // select between them. 6697 SDValue Zero = DAG.getIntPtrConstant(0); 6698 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6699 SDValue One = DAG.getIntPtrConstant(EltSize); 6700 6701 SDValue Cond = DAG.getSetCC(DL, 6702 TLI.getSetCCResultType(N0.getValueType()), 6703 N0, N1, CC); 6704 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6705 Cond, One, Zero); 6706 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6707 CstOffset); 6708 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6709 PseudoSourceValue::getConstantPool(), 0, false, 6710 false, Alignment); 6711 6712 } 6713 } 6714 6715 // Check to see if we can perform the "gzip trick", transforming 6716 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6717 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6718 N0.getValueType().isInteger() && 6719 N2.getValueType().isInteger() && 6720 (N1C->isNullValue() || // (a < 0) ? b : 0 6721 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6722 EVT XType = N0.getValueType(); 6723 EVT AType = N2.getValueType(); 6724 if (XType.bitsGE(AType)) { 6725 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6726 // single-bit constant. 6727 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6728 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6729 ShCtV = XType.getSizeInBits()-ShCtV-1; 6730 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6731 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6732 XType, N0, ShCt); 6733 AddToWorkList(Shift.getNode()); 6734 6735 if (XType.bitsGT(AType)) { 6736 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6737 AddToWorkList(Shift.getNode()); 6738 } 6739 6740 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6741 } 6742 6743 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6744 XType, N0, 6745 DAG.getConstant(XType.getSizeInBits()-1, 6746 getShiftAmountTy())); 6747 AddToWorkList(Shift.getNode()); 6748 6749 if (XType.bitsGT(AType)) { 6750 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6751 AddToWorkList(Shift.getNode()); 6752 } 6753 6754 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6755 } 6756 } 6757 6758 // fold select C, 16, 0 -> shl C, 4 6759 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6760 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6761 6762 // If the caller doesn't want us to simplify this into a zext of a compare, 6763 // don't do it. 6764 if (NotExtCompare && N2C->getAPIntValue() == 1) 6765 return SDValue(); 6766 6767 // Get a SetCC of the condition 6768 // FIXME: Should probably make sure that setcc is legal if we ever have a 6769 // target where it isn't. 6770 SDValue Temp, SCC; 6771 // cast from setcc result type to select result type 6772 if (LegalTypes) { 6773 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6774 N0, N1, CC); 6775 if (N2.getValueType().bitsLT(SCC.getValueType())) 6776 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6777 else 6778 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6779 N2.getValueType(), SCC); 6780 } else { 6781 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6782 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6783 N2.getValueType(), SCC); 6784 } 6785 6786 AddToWorkList(SCC.getNode()); 6787 AddToWorkList(Temp.getNode()); 6788 6789 if (N2C->getAPIntValue() == 1) 6790 return Temp; 6791 6792 // shl setcc result by log2 n2c 6793 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6794 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6795 getShiftAmountTy())); 6796 } 6797 6798 // Check to see if this is the equivalent of setcc 6799 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6800 // otherwise, go ahead with the folds. 6801 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6802 EVT XType = N0.getValueType(); 6803 if (!LegalOperations || 6804 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6805 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6806 if (Res.getValueType() != VT) 6807 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6808 return Res; 6809 } 6810 6811 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6812 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6813 (!LegalOperations || 6814 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6815 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6816 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6817 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6818 getShiftAmountTy())); 6819 } 6820 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6821 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6822 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6823 XType, DAG.getConstant(0, XType), N0); 6824 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6825 return DAG.getNode(ISD::SRL, DL, XType, 6826 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6827 DAG.getConstant(XType.getSizeInBits()-1, 6828 getShiftAmountTy())); 6829 } 6830 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6831 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6832 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6833 DAG.getConstant(XType.getSizeInBits()-1, 6834 getShiftAmountTy())); 6835 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6836 } 6837 } 6838 6839 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6840 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6841 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6842 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6843 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6844 EVT XType = N0.getValueType(); 6845 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6846 DAG.getConstant(XType.getSizeInBits()-1, 6847 getShiftAmountTy())); 6848 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6849 N0, Shift); 6850 AddToWorkList(Shift.getNode()); 6851 AddToWorkList(Add.getNode()); 6852 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6853 } 6854 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6855 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6856 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6857 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6858 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6859 EVT XType = N0.getValueType(); 6860 if (SubC->isNullValue() && XType.isInteger()) { 6861 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6862 N0, 6863 DAG.getConstant(XType.getSizeInBits()-1, 6864 getShiftAmountTy())); 6865 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6866 XType, N0, Shift); 6867 AddToWorkList(Shift.getNode()); 6868 AddToWorkList(Add.getNode()); 6869 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6870 } 6871 } 6872 } 6873 6874 return SDValue(); 6875} 6876 6877/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6878SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6879 SDValue N1, ISD::CondCode Cond, 6880 DebugLoc DL, bool foldBooleans) { 6881 TargetLowering::DAGCombinerInfo 6882 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6883 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6884} 6885 6886/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6887/// return a DAG expression to select that will generate the same value by 6888/// multiplying by a magic number. See: 6889/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6890SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6891 std::vector<SDNode*> Built; 6892 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6893 6894 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6895 ii != ee; ++ii) 6896 AddToWorkList(*ii); 6897 return S; 6898} 6899 6900/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6901/// return a DAG expression to select that will generate the same value by 6902/// multiplying by a magic number. See: 6903/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6904SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6905 std::vector<SDNode*> Built; 6906 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6907 6908 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6909 ii != ee; ++ii) 6910 AddToWorkList(*ii); 6911 return S; 6912} 6913 6914/// FindBaseOffset - Return true if base is a frame index, which is known not 6915// to alias with anything but itself. Provides base object and offset as results. 6916static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6917 const GlobalValue *&GV, void *&CV) { 6918 // Assume it is a primitive operation. 6919 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6920 6921 // If it's an adding a simple constant then integrate the offset. 6922 if (Base.getOpcode() == ISD::ADD) { 6923 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6924 Base = Base.getOperand(0); 6925 Offset += C->getZExtValue(); 6926 } 6927 } 6928 6929 // Return the underlying GlobalValue, and update the Offset. Return false 6930 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6931 // by multiple nodes with different offsets. 6932 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6933 GV = G->getGlobal(); 6934 Offset += G->getOffset(); 6935 return false; 6936 } 6937 6938 // Return the underlying Constant value, and update the Offset. Return false 6939 // for ConstantSDNodes since the same constant pool entry may be represented 6940 // by multiple nodes with different offsets. 6941 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6942 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6943 : (void *)C->getConstVal(); 6944 Offset += C->getOffset(); 6945 return false; 6946 } 6947 // If it's any of the following then it can't alias with anything but itself. 6948 return isa<FrameIndexSDNode>(Base); 6949} 6950 6951/// isAlias - Return true if there is any possibility that the two addresses 6952/// overlap. 6953bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6954 const Value *SrcValue1, int SrcValueOffset1, 6955 unsigned SrcValueAlign1, 6956 SDValue Ptr2, int64_t Size2, 6957 const Value *SrcValue2, int SrcValueOffset2, 6958 unsigned SrcValueAlign2) const { 6959 // If they are the same then they must be aliases. 6960 if (Ptr1 == Ptr2) return true; 6961 6962 // Gather base node and offset information. 6963 SDValue Base1, Base2; 6964 int64_t Offset1, Offset2; 6965 const GlobalValue *GV1, *GV2; 6966 void *CV1, *CV2; 6967 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6968 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6969 6970 // If they have a same base address then check to see if they overlap. 6971 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6972 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6973 6974 // If we know what the bases are, and they aren't identical, then we know they 6975 // cannot alias. 6976 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6977 return false; 6978 6979 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6980 // compared to the size and offset of the access, we may be able to prove they 6981 // do not alias. This check is conservative for now to catch cases created by 6982 // splitting vector types. 6983 if ((SrcValueAlign1 == SrcValueAlign2) && 6984 (SrcValueOffset1 != SrcValueOffset2) && 6985 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6986 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6987 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6988 6989 // There is no overlap between these relatively aligned accesses of similar 6990 // size, return no alias. 6991 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6992 return false; 6993 } 6994 6995 if (CombinerGlobalAA) { 6996 // Use alias analysis information. 6997 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6998 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6999 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7000 AliasAnalysis::AliasResult AAResult = 7001 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 7002 if (AAResult == AliasAnalysis::NoAlias) 7003 return false; 7004 } 7005 7006 // Otherwise we have to assume they alias. 7007 return true; 7008} 7009 7010/// FindAliasInfo - Extracts the relevant alias information from the memory 7011/// node. Returns true if the operand was a load. 7012bool DAGCombiner::FindAliasInfo(SDNode *N, 7013 SDValue &Ptr, int64_t &Size, 7014 const Value *&SrcValue, 7015 int &SrcValueOffset, 7016 unsigned &SrcValueAlign) const { 7017 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7018 Ptr = LD->getBasePtr(); 7019 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7020 SrcValue = LD->getSrcValue(); 7021 SrcValueOffset = LD->getSrcValueOffset(); 7022 SrcValueAlign = LD->getOriginalAlignment(); 7023 return true; 7024 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7025 Ptr = ST->getBasePtr(); 7026 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7027 SrcValue = ST->getSrcValue(); 7028 SrcValueOffset = ST->getSrcValueOffset(); 7029 SrcValueAlign = ST->getOriginalAlignment(); 7030 } else { 7031 llvm_unreachable("FindAliasInfo expected a memory operand"); 7032 } 7033 7034 return false; 7035} 7036 7037/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7038/// looking for aliasing nodes and adding them to the Aliases vector. 7039void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7040 SmallVector<SDValue, 8> &Aliases) { 7041 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7042 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7043 7044 // Get alias information for node. 7045 SDValue Ptr; 7046 int64_t Size; 7047 const Value *SrcValue; 7048 int SrcValueOffset; 7049 unsigned SrcValueAlign; 7050 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7051 SrcValueAlign); 7052 7053 // Starting off. 7054 Chains.push_back(OriginalChain); 7055 unsigned Depth = 0; 7056 7057 // Look at each chain and determine if it is an alias. If so, add it to the 7058 // aliases list. If not, then continue up the chain looking for the next 7059 // candidate. 7060 while (!Chains.empty()) { 7061 SDValue Chain = Chains.back(); 7062 Chains.pop_back(); 7063 7064 // For TokenFactor nodes, look at each operand and only continue up the 7065 // chain until we find two aliases. If we've seen two aliases, assume we'll 7066 // find more and revert to original chain since the xform is unlikely to be 7067 // profitable. 7068 // 7069 // FIXME: The depth check could be made to return the last non-aliasing 7070 // chain we found before we hit a tokenfactor rather than the original 7071 // chain. 7072 if (Depth > 6 || Aliases.size() == 2) { 7073 Aliases.clear(); 7074 Aliases.push_back(OriginalChain); 7075 break; 7076 } 7077 7078 // Don't bother if we've been before. 7079 if (!Visited.insert(Chain.getNode())) 7080 continue; 7081 7082 switch (Chain.getOpcode()) { 7083 case ISD::EntryToken: 7084 // Entry token is ideal chain operand, but handled in FindBetterChain. 7085 break; 7086 7087 case ISD::LOAD: 7088 case ISD::STORE: { 7089 // Get alias information for Chain. 7090 SDValue OpPtr; 7091 int64_t OpSize; 7092 const Value *OpSrcValue; 7093 int OpSrcValueOffset; 7094 unsigned OpSrcValueAlign; 7095 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7096 OpSrcValue, OpSrcValueOffset, 7097 OpSrcValueAlign); 7098 7099 // If chain is alias then stop here. 7100 if (!(IsLoad && IsOpLoad) && 7101 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7102 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7103 OpSrcValueAlign)) { 7104 Aliases.push_back(Chain); 7105 } else { 7106 // Look further up the chain. 7107 Chains.push_back(Chain.getOperand(0)); 7108 ++Depth; 7109 } 7110 break; 7111 } 7112 7113 case ISD::TokenFactor: 7114 // We have to check each of the operands of the token factor for "small" 7115 // token factors, so we queue them up. Adding the operands to the queue 7116 // (stack) in reverse order maintains the original order and increases the 7117 // likelihood that getNode will find a matching token factor (CSE.) 7118 if (Chain.getNumOperands() > 16) { 7119 Aliases.push_back(Chain); 7120 break; 7121 } 7122 for (unsigned n = Chain.getNumOperands(); n;) 7123 Chains.push_back(Chain.getOperand(--n)); 7124 ++Depth; 7125 break; 7126 7127 default: 7128 // For all other instructions we will just have to take what we can get. 7129 Aliases.push_back(Chain); 7130 break; 7131 } 7132 } 7133} 7134 7135/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7136/// for a better chain (aliasing node.) 7137SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7138 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7139 7140 // Accumulate all the aliases to this node. 7141 GatherAllAliases(N, OldChain, Aliases); 7142 7143 if (Aliases.size() == 0) { 7144 // If no operands then chain to entry token. 7145 return DAG.getEntryNode(); 7146 } else if (Aliases.size() == 1) { 7147 // If a single operand then chain to it. We don't need to revisit it. 7148 return Aliases[0]; 7149 } 7150 7151 // Construct a custom tailored token factor. 7152 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7153 &Aliases[0], Aliases.size()); 7154} 7155 7156// SelectionDAG::Combine - This is the entry point for the file. 7157// 7158void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7159 CodeGenOpt::Level OptLevel) { 7160 /// run - This is the main entry point to this class. 7161 /// 7162 DAGCombiner(*this, AA, OptLevel).Run(Level); 7163} 7164