DAGCombiner.cpp revision 97121ba2afb8d566ff1bf5c4e8fc5d4077940a7f
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/DerivedTypes.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/Analysis/AliasAnalysis.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetFrameInfo.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/ADT/SmallPtrSet.h" 28#include "llvm/ADT/Statistic.h" 29#include "llvm/Support/Compiler.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/MathExtras.h" 33#include <algorithm> 34#include <set> 35using namespace llvm; 36 37STATISTIC(NodesCombined , "Number of dag nodes combined"); 38STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 39STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 40 41namespace { 42 static cl::opt<bool> 43 CombinerAA("combiner-alias-analysis", cl::Hidden, 44 cl::desc("Turn on alias analysis during testing")); 45 46 static cl::opt<bool> 47 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 48 cl::desc("Include global information in alias analysis")); 49 50//------------------------------ DAGCombiner ---------------------------------// 51 52 class VISIBILITY_HIDDEN DAGCombiner { 53 SelectionDAG &DAG; 54 const TargetLowering &TLI; 55 CombineLevel Level; 56 bool LegalOperations; 57 bool LegalTypes; 58 bool Fast; 59 60 // Worklist of all of the nodes that need to be simplified. 61 std::vector<SDNode*> WorkList; 62 63 // AA - Used for DAG load/store alias analysis. 64 AliasAnalysis &AA; 65 66 /// AddUsersToWorkList - When an instruction is simplified, add all users of 67 /// the instruction to the work lists because they might get more simplified 68 /// now. 69 /// 70 void AddUsersToWorkList(SDNode *N) { 71 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 72 UI != UE; ++UI) 73 AddToWorkList(*UI); 74 } 75 76 /// visit - call the node-specific routine that knows how to fold each 77 /// particular type of node. 78 SDValue visit(SDNode *N); 79 80 public: 81 /// AddToWorkList - Add to the work list making sure it's instance is at the 82 /// the back (next to be processed.) 83 void AddToWorkList(SDNode *N) { 84 removeFromWorkList(N); 85 WorkList.push_back(N); 86 } 87 88 /// removeFromWorkList - remove all instances of N from the worklist. 89 /// 90 void removeFromWorkList(SDNode *N) { 91 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 92 WorkList.end()); 93 } 94 95 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 96 bool AddTo = true); 97 98 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 99 return CombineTo(N, &Res, 1, AddTo); 100 } 101 102 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 103 bool AddTo = true) { 104 SDValue To[] = { Res0, Res1 }; 105 return CombineTo(N, To, 2, AddTo); 106 } 107 108 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 109 110 private: 111 112 /// SimplifyDemandedBits - Check the specified integer node value to see if 113 /// it can be simplified or if things it uses can be simplified by bit 114 /// propagation. If so, return true. 115 bool SimplifyDemandedBits(SDValue Op) { 116 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 117 return SimplifyDemandedBits(Op, Demanded); 118 } 119 120 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 121 122 bool CombineToPreIndexedLoadStore(SDNode *N); 123 bool CombineToPostIndexedLoadStore(SDNode *N); 124 125 126 /// combine - call the node-specific routine that knows how to fold each 127 /// particular type of node. If that doesn't do anything, try the 128 /// target-specific DAG combines. 129 SDValue combine(SDNode *N); 130 131 // Visitation implementation - Implement dag node combining for different 132 // node types. The semantics are as follows: 133 // Return Value: 134 // SDValue.getNode() == 0 - No change was made 135 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 136 // otherwise - N should be replaced by the returned Operand. 137 // 138 SDValue visitTokenFactor(SDNode *N); 139 SDValue visitMERGE_VALUES(SDNode *N); 140 SDValue visitADD(SDNode *N); 141 SDValue visitSUB(SDNode *N); 142 SDValue visitADDC(SDNode *N); 143 SDValue visitADDE(SDNode *N); 144 SDValue visitMUL(SDNode *N); 145 SDValue visitSDIV(SDNode *N); 146 SDValue visitUDIV(SDNode *N); 147 SDValue visitSREM(SDNode *N); 148 SDValue visitUREM(SDNode *N); 149 SDValue visitMULHU(SDNode *N); 150 SDValue visitMULHS(SDNode *N); 151 SDValue visitSMUL_LOHI(SDNode *N); 152 SDValue visitUMUL_LOHI(SDNode *N); 153 SDValue visitSDIVREM(SDNode *N); 154 SDValue visitUDIVREM(SDNode *N); 155 SDValue visitAND(SDNode *N); 156 SDValue visitOR(SDNode *N); 157 SDValue visitXOR(SDNode *N); 158 SDValue SimplifyVBinOp(SDNode *N); 159 SDValue visitSHL(SDNode *N); 160 SDValue visitSRA(SDNode *N); 161 SDValue visitSRL(SDNode *N); 162 SDValue visitCTLZ(SDNode *N); 163 SDValue visitCTTZ(SDNode *N); 164 SDValue visitCTPOP(SDNode *N); 165 SDValue visitSELECT(SDNode *N); 166 SDValue visitSELECT_CC(SDNode *N); 167 SDValue visitSETCC(SDNode *N); 168 SDValue visitSIGN_EXTEND(SDNode *N); 169 SDValue visitZERO_EXTEND(SDNode *N); 170 SDValue visitANY_EXTEND(SDNode *N); 171 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 172 SDValue visitTRUNCATE(SDNode *N); 173 SDValue visitBIT_CONVERT(SDNode *N); 174 SDValue visitBUILD_PAIR(SDNode *N); 175 SDValue visitFADD(SDNode *N); 176 SDValue visitFSUB(SDNode *N); 177 SDValue visitFMUL(SDNode *N); 178 SDValue visitFDIV(SDNode *N); 179 SDValue visitFREM(SDNode *N); 180 SDValue visitFCOPYSIGN(SDNode *N); 181 SDValue visitSINT_TO_FP(SDNode *N); 182 SDValue visitUINT_TO_FP(SDNode *N); 183 SDValue visitFP_TO_SINT(SDNode *N); 184 SDValue visitFP_TO_UINT(SDNode *N); 185 SDValue visitFP_ROUND(SDNode *N); 186 SDValue visitFP_ROUND_INREG(SDNode *N); 187 SDValue visitFP_EXTEND(SDNode *N); 188 SDValue visitFNEG(SDNode *N); 189 SDValue visitFABS(SDNode *N); 190 SDValue visitBRCOND(SDNode *N); 191 SDValue visitBR_CC(SDNode *N); 192 SDValue visitLOAD(SDNode *N); 193 SDValue visitSTORE(SDNode *N); 194 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 195 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 196 SDValue visitBUILD_VECTOR(SDNode *N); 197 SDValue visitCONCAT_VECTORS(SDNode *N); 198 SDValue visitVECTOR_SHUFFLE(SDNode *N); 199 200 SDValue XformToShuffleWithZero(SDNode *N); 201 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 202 203 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 204 205 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 206 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 207 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 208 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 209 SDValue N3, ISD::CondCode CC, 210 bool NotExtCompare = false); 211 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 212 DebugLoc DL, bool foldBooleans = true); 213 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 214 unsigned HiOp); 215 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 216 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 217 SDValue BuildSDIV(SDNode *N); 218 SDValue BuildUDIV(SDNode *N); 219 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 220 SDValue ReduceLoadWidth(SDNode *N); 221 222 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 223 224 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 225 /// looking for aliasing nodes and adding them to the Aliases vector. 226 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 227 SmallVector<SDValue, 8> &Aliases); 228 229 /// isAlias - Return true if there is any possibility that the two addresses 230 /// overlap. 231 bool isAlias(SDValue Ptr1, int64_t Size1, 232 const Value *SrcValue1, int SrcValueOffset1, 233 SDValue Ptr2, int64_t Size2, 234 const Value *SrcValue2, int SrcValueOffset2) const; 235 236 /// FindAliasInfo - Extracts the relevant alias information from the memory 237 /// node. Returns true if the operand was a load. 238 bool FindAliasInfo(SDNode *N, 239 SDValue &Ptr, int64_t &Size, 240 const Value *&SrcValue, int &SrcValueOffset) const; 241 242 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 243 /// looking for a better chain (aliasing node.) 244 SDValue FindBetterChain(SDNode *N, SDValue Chain); 245 246 /// getShiftAmountTy - Returns a type large enough to hold any valid 247 /// shift amount - before type legalization these can be huge. 248 MVT getShiftAmountTy() { 249 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 250 } 251 252public: 253 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 254 : DAG(D), 255 TLI(D.getTargetLoweringInfo()), 256 Level(Unrestricted), 257 LegalOperations(false), 258 LegalTypes(false), 259 Fast(fast), 260 AA(A) {} 261 262 /// Run - runs the dag combiner on all nodes in the work list 263 void Run(CombineLevel AtLevel); 264 }; 265} 266 267 268namespace { 269/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 270/// nodes from the worklist. 271class VISIBILITY_HIDDEN WorkListRemover : 272 public SelectionDAG::DAGUpdateListener { 273 DAGCombiner &DC; 274public: 275 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 276 277 virtual void NodeDeleted(SDNode *N, SDNode *E) { 278 DC.removeFromWorkList(N); 279 } 280 281 virtual void NodeUpdated(SDNode *N) { 282 // Ignore updates. 283 } 284}; 285} 286 287//===----------------------------------------------------------------------===// 288// TargetLowering::DAGCombinerInfo implementation 289//===----------------------------------------------------------------------===// 290 291void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 292 ((DAGCombiner*)DC)->AddToWorkList(N); 293} 294 295SDValue TargetLowering::DAGCombinerInfo:: 296CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 297 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 298} 299 300SDValue TargetLowering::DAGCombinerInfo:: 301CombineTo(SDNode *N, SDValue Res, bool AddTo) { 302 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 303} 304 305 306SDValue TargetLowering::DAGCombinerInfo:: 307CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 308 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 309} 310 311void TargetLowering::DAGCombinerInfo:: 312CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 313 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 314} 315 316//===----------------------------------------------------------------------===// 317// Helper Functions 318//===----------------------------------------------------------------------===// 319 320/// isNegatibleForFree - Return 1 if we can compute the negated form of the 321/// specified expression for the same cost as the expression itself, or 2 if we 322/// can compute the negated form more cheaply than the expression itself. 323static char isNegatibleForFree(SDValue Op, bool LegalOperations, 324 unsigned Depth = 0) { 325 // No compile time optimizations on this type. 326 if (Op.getValueType() == MVT::ppcf128) 327 return 0; 328 329 // fneg is removable even if it has multiple uses. 330 if (Op.getOpcode() == ISD::FNEG) return 2; 331 332 // Don't allow anything with multiple uses. 333 if (!Op.hasOneUse()) return 0; 334 335 // Don't recurse exponentially. 336 if (Depth > 6) return 0; 337 338 switch (Op.getOpcode()) { 339 default: return false; 340 case ISD::ConstantFP: 341 // Don't invert constant FP values after legalize. The negated constant 342 // isn't necessarily legal. 343 return LegalOperations ? 0 : 1; 344 case ISD::FADD: 345 // FIXME: determine better conditions for this xform. 346 if (!UnsafeFPMath) return 0; 347 348 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 349 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 350 return V; 351 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 352 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 353 case ISD::FSUB: 354 // We can't turn -(A-B) into B-A when we honor signed zeros. 355 if (!UnsafeFPMath) return 0; 356 357 // fold (fneg (fsub A, B)) -> (fsub B, A) 358 return 1; 359 360 case ISD::FMUL: 361 case ISD::FDIV: 362 if (HonorSignDependentRoundingFPMath()) return 0; 363 364 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 365 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 366 return V; 367 368 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 369 370 case ISD::FP_EXTEND: 371 case ISD::FP_ROUND: 372 case ISD::FSIN: 373 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 374 } 375} 376 377/// GetNegatedExpression - If isNegatibleForFree returns true, this function 378/// returns the newly negated expression. 379static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 380 bool LegalOperations, unsigned Depth = 0) { 381 // fneg is removable even if it has multiple uses. 382 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 383 384 // Don't allow anything with multiple uses. 385 assert(Op.hasOneUse() && "Unknown reuse!"); 386 387 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 388 switch (Op.getOpcode()) { 389 default: assert(0 && "Unknown code"); 390 case ISD::ConstantFP: { 391 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 392 V.changeSign(); 393 return DAG.getConstantFP(V, Op.getValueType()); 394 } 395 case ISD::FADD: 396 // FIXME: determine better conditions for this xform. 397 assert(UnsafeFPMath); 398 399 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 400 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 401 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 402 GetNegatedExpression(Op.getOperand(0), DAG, 403 LegalOperations, Depth+1), 404 Op.getOperand(1)); 405 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 406 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 407 GetNegatedExpression(Op.getOperand(1), DAG, 408 LegalOperations, Depth+1), 409 Op.getOperand(0)); 410 case ISD::FSUB: 411 // We can't turn -(A-B) into B-A when we honor signed zeros. 412 assert(UnsafeFPMath); 413 414 // fold (fneg (fsub 0, B)) -> B 415 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 416 if (N0CFP->getValueAPF().isZero()) 417 return Op.getOperand(1); 418 419 // fold (fneg (fsub A, B)) -> (fsub B, A) 420 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 421 Op.getOperand(1), Op.getOperand(0)); 422 423 case ISD::FMUL: 424 case ISD::FDIV: 425 assert(!HonorSignDependentRoundingFPMath()); 426 427 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 428 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 429 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 430 GetNegatedExpression(Op.getOperand(0), DAG, 431 LegalOperations, Depth+1), 432 Op.getOperand(1)); 433 434 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 435 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 436 Op.getOperand(0), 437 GetNegatedExpression(Op.getOperand(1), DAG, 438 LegalOperations, Depth+1)); 439 440 case ISD::FP_EXTEND: 441 case ISD::FSIN: 442 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 443 GetNegatedExpression(Op.getOperand(0), DAG, 444 LegalOperations, Depth+1)); 445 case ISD::FP_ROUND: 446 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 447 GetNegatedExpression(Op.getOperand(0), DAG, 448 LegalOperations, Depth+1), 449 Op.getOperand(1)); 450 } 451} 452 453 454// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 455// that selects between the values 1 and 0, making it equivalent to a setcc. 456// Also, set the incoming LHS, RHS, and CC references to the appropriate 457// nodes based on the type of node we are checking. This simplifies life a 458// bit for the callers. 459static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 460 SDValue &CC) { 461 if (N.getOpcode() == ISD::SETCC) { 462 LHS = N.getOperand(0); 463 RHS = N.getOperand(1); 464 CC = N.getOperand(2); 465 return true; 466 } 467 if (N.getOpcode() == ISD::SELECT_CC && 468 N.getOperand(2).getOpcode() == ISD::Constant && 469 N.getOperand(3).getOpcode() == ISD::Constant && 470 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 471 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 472 LHS = N.getOperand(0); 473 RHS = N.getOperand(1); 474 CC = N.getOperand(4); 475 return true; 476 } 477 return false; 478} 479 480// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 481// one use. If this is true, it allows the users to invert the operation for 482// free when it is profitable to do so. 483static bool isOneUseSetCC(SDValue N) { 484 SDValue N0, N1, N2; 485 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 486 return true; 487 return false; 488} 489 490SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 491 SDValue N0, SDValue N1) { 492 MVT VT = N0.getValueType(); 493 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 494 if (isa<ConstantSDNode>(N1)) { 495 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 496 SDValue OpNode = 497 DAG.FoldConstantArithmetic(Opc, VT, 498 cast<ConstantSDNode>(N0.getOperand(1)), 499 cast<ConstantSDNode>(N1)); 500 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 501 } else if (N0.hasOneUse()) { 502 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 503 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 504 N0.getOperand(0), N1); 505 AddToWorkList(OpNode.getNode()); 506 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 507 } 508 } 509 510 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 511 if (isa<ConstantSDNode>(N0)) { 512 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 513 SDValue OpNode = 514 DAG.FoldConstantArithmetic(Opc, VT, 515 cast<ConstantSDNode>(N1.getOperand(1)), 516 cast<ConstantSDNode>(N0)); 517 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 518 } else if (N1.hasOneUse()) { 519 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 520 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 521 N1.getOperand(0), N0); 522 AddToWorkList(OpNode.getNode()); 523 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 524 } 525 } 526 527 return SDValue(); 528} 529 530SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 531 bool AddTo) { 532 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 533 ++NodesCombined; 534 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 535 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 536 DOUT << " and " << NumTo-1 << " other values\n"; 537 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 538 assert(N->getValueType(i) == To[i].getValueType() && 539 "Cannot combine value to value of different type!")); 540 WorkListRemover DeadNodes(*this); 541 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 542 543 if (AddTo) { 544 // Push the new nodes and any users onto the worklist 545 for (unsigned i = 0, e = NumTo; i != e; ++i) { 546 if (To[i].getNode()) { 547 AddToWorkList(To[i].getNode()); 548 AddUsersToWorkList(To[i].getNode()); 549 } 550 } 551 } 552 553 // Finally, if the node is now dead, remove it from the graph. The node 554 // may not be dead if the replacement process recursively simplified to 555 // something else needing this node. 556 if (N->use_empty()) { 557 // Nodes can be reintroduced into the worklist. Make sure we do not 558 // process a node that has been replaced. 559 removeFromWorkList(N); 560 561 // Finally, since the node is now dead, remove it from the graph. 562 DAG.DeleteNode(N); 563 } 564 return SDValue(N, 0); 565} 566 567void 568DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 569 TLO) { 570 // Replace all uses. If any nodes become isomorphic to other nodes and 571 // are deleted, make sure to remove them from our worklist. 572 WorkListRemover DeadNodes(*this); 573 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 574 575 // Push the new node and any (possibly new) users onto the worklist. 576 AddToWorkList(TLO.New.getNode()); 577 AddUsersToWorkList(TLO.New.getNode()); 578 579 // Finally, if the node is now dead, remove it from the graph. The node 580 // may not be dead if the replacement process recursively simplified to 581 // something else needing this node. 582 if (TLO.Old.getNode()->use_empty()) { 583 removeFromWorkList(TLO.Old.getNode()); 584 585 // If the operands of this node are only used by the node, they will now 586 // be dead. Make sure to visit them first to delete dead nodes early. 587 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 588 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 589 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 590 591 DAG.DeleteNode(TLO.Old.getNode()); 592 } 593} 594 595/// SimplifyDemandedBits - Check the specified integer node value to see if 596/// it can be simplified or if things it uses can be simplified by bit 597/// propagation. If so, return true. 598bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 599 TargetLowering::TargetLoweringOpt TLO(DAG); 600 APInt KnownZero, KnownOne; 601 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 602 return false; 603 604 // Revisit the node. 605 AddToWorkList(Op.getNode()); 606 607 // Replace the old value with the new one. 608 ++NodesCombined; 609 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 610 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 611 DOUT << '\n'; 612 613 CommitTargetLoweringOpt(TLO); 614 return true; 615} 616 617//===----------------------------------------------------------------------===// 618// Main DAG Combiner implementation 619//===----------------------------------------------------------------------===// 620 621void DAGCombiner::Run(CombineLevel AtLevel) { 622 // set the instance variables, so that the various visit routines may use it. 623 Level = AtLevel; 624 LegalOperations = Level >= NoIllegalOperations; 625 LegalTypes = Level >= NoIllegalTypes; 626 627 // Add all the dag nodes to the worklist. 628 WorkList.reserve(DAG.allnodes_size()); 629 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 630 E = DAG.allnodes_end(); I != E; ++I) 631 WorkList.push_back(I); 632 633 // Create a dummy node (which is not added to allnodes), that adds a reference 634 // to the root node, preventing it from being deleted, and tracking any 635 // changes of the root. 636 HandleSDNode Dummy(DAG.getRoot()); 637 638 // The root of the dag may dangle to deleted nodes until the dag combiner is 639 // done. Set it to null to avoid confusion. 640 DAG.setRoot(SDValue()); 641 642 // while the worklist isn't empty, inspect the node on the end of it and 643 // try and combine it. 644 while (!WorkList.empty()) { 645 SDNode *N = WorkList.back(); 646 WorkList.pop_back(); 647 648 // If N has no uses, it is dead. Make sure to revisit all N's operands once 649 // N is deleted from the DAG, since they too may now be dead or may have a 650 // reduced number of uses, allowing other xforms. 651 if (N->use_empty() && N != &Dummy) { 652 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 653 AddToWorkList(N->getOperand(i).getNode()); 654 655 DAG.DeleteNode(N); 656 continue; 657 } 658 659 SDValue RV = combine(N); 660 661 if (RV.getNode() == 0) 662 continue; 663 664 ++NodesCombined; 665 666 // If we get back the same node we passed in, rather than a new node or 667 // zero, we know that the node must have defined multiple values and 668 // CombineTo was used. Since CombineTo takes care of the worklist 669 // mechanics for us, we have no work to do in this case. 670 if (RV.getNode() == N) 671 continue; 672 673 assert(N->getOpcode() != ISD::DELETED_NODE && 674 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 675 "Node was deleted but visit returned new node!"); 676 677 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 678 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 679 DOUT << '\n'; 680 WorkListRemover DeadNodes(*this); 681 if (N->getNumValues() == RV.getNode()->getNumValues()) 682 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 683 else { 684 assert(N->getValueType(0) == RV.getValueType() && 685 N->getNumValues() == 1 && "Type mismatch"); 686 SDValue OpV = RV; 687 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 688 } 689 690 // Push the new node and any users onto the worklist 691 AddToWorkList(RV.getNode()); 692 AddUsersToWorkList(RV.getNode()); 693 694 // Add any uses of the old node to the worklist in case this node is the 695 // last one that uses them. They may become dead after this node is 696 // deleted. 697 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 698 AddToWorkList(N->getOperand(i).getNode()); 699 700 // Finally, if the node is now dead, remove it from the graph. The node 701 // may not be dead if the replacement process recursively simplified to 702 // something else needing this node. 703 if (N->use_empty()) { 704 // Nodes can be reintroduced into the worklist. Make sure we do not 705 // process a node that has been replaced. 706 removeFromWorkList(N); 707 708 // Finally, since the node is now dead, remove it from the graph. 709 DAG.DeleteNode(N); 710 } 711 } 712 713 // If the root changed (e.g. it was a dead load, update the root). 714 DAG.setRoot(Dummy.getValue()); 715} 716 717SDValue DAGCombiner::visit(SDNode *N) { 718 switch(N->getOpcode()) { 719 default: break; 720 case ISD::TokenFactor: return visitTokenFactor(N); 721 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 722 case ISD::ADD: return visitADD(N); 723 case ISD::SUB: return visitSUB(N); 724 case ISD::ADDC: return visitADDC(N); 725 case ISD::ADDE: return visitADDE(N); 726 case ISD::MUL: return visitMUL(N); 727 case ISD::SDIV: return visitSDIV(N); 728 case ISD::UDIV: return visitUDIV(N); 729 case ISD::SREM: return visitSREM(N); 730 case ISD::UREM: return visitUREM(N); 731 case ISD::MULHU: return visitMULHU(N); 732 case ISD::MULHS: return visitMULHS(N); 733 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 734 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 735 case ISD::SDIVREM: return visitSDIVREM(N); 736 case ISD::UDIVREM: return visitUDIVREM(N); 737 case ISD::AND: return visitAND(N); 738 case ISD::OR: return visitOR(N); 739 case ISD::XOR: return visitXOR(N); 740 case ISD::SHL: return visitSHL(N); 741 case ISD::SRA: return visitSRA(N); 742 case ISD::SRL: return visitSRL(N); 743 case ISD::CTLZ: return visitCTLZ(N); 744 case ISD::CTTZ: return visitCTTZ(N); 745 case ISD::CTPOP: return visitCTPOP(N); 746 case ISD::SELECT: return visitSELECT(N); 747 case ISD::SELECT_CC: return visitSELECT_CC(N); 748 case ISD::SETCC: return visitSETCC(N); 749 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 750 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 751 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 752 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 753 case ISD::TRUNCATE: return visitTRUNCATE(N); 754 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 755 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 756 case ISD::FADD: return visitFADD(N); 757 case ISD::FSUB: return visitFSUB(N); 758 case ISD::FMUL: return visitFMUL(N); 759 case ISD::FDIV: return visitFDIV(N); 760 case ISD::FREM: return visitFREM(N); 761 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 762 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 763 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 764 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 765 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 766 case ISD::FP_ROUND: return visitFP_ROUND(N); 767 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 768 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 769 case ISD::FNEG: return visitFNEG(N); 770 case ISD::FABS: return visitFABS(N); 771 case ISD::BRCOND: return visitBRCOND(N); 772 case ISD::BR_CC: return visitBR_CC(N); 773 case ISD::LOAD: return visitLOAD(N); 774 case ISD::STORE: return visitSTORE(N); 775 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 776 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 777 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 778 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 779 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 780 } 781 return SDValue(); 782} 783 784SDValue DAGCombiner::combine(SDNode *N) { 785 SDValue RV = visit(N); 786 787 // If nothing happened, try a target-specific DAG combine. 788 if (RV.getNode() == 0) { 789 assert(N->getOpcode() != ISD::DELETED_NODE && 790 "Node was deleted but visit returned NULL!"); 791 792 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 793 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 794 795 // Expose the DAG combiner to the target combiner impls. 796 TargetLowering::DAGCombinerInfo 797 DagCombineInfo(DAG, Level == Unrestricted, false, this); 798 799 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 800 } 801 } 802 803 // If N is a commutative binary node, try commuting it to enable more 804 // sdisel CSE. 805 if (RV.getNode() == 0 && 806 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 807 N->getNumValues() == 1) { 808 SDValue N0 = N->getOperand(0); 809 SDValue N1 = N->getOperand(1); 810 811 // Constant operands are canonicalized to RHS. 812 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 813 SDValue Ops[] = { N1, N0 }; 814 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 815 Ops, 2); 816 if (CSENode) 817 return SDValue(CSENode, 0); 818 } 819 } 820 821 return RV; 822} 823 824/// getInputChainForNode - Given a node, return its input chain if it has one, 825/// otherwise return a null sd operand. 826static SDValue getInputChainForNode(SDNode *N) { 827 if (unsigned NumOps = N->getNumOperands()) { 828 if (N->getOperand(0).getValueType() == MVT::Other) 829 return N->getOperand(0); 830 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 831 return N->getOperand(NumOps-1); 832 for (unsigned i = 1; i < NumOps-1; ++i) 833 if (N->getOperand(i).getValueType() == MVT::Other) 834 return N->getOperand(i); 835 } 836 return SDValue(); 837} 838 839SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 840 // If N has two operands, where one has an input chain equal to the other, 841 // the 'other' chain is redundant. 842 if (N->getNumOperands() == 2) { 843 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 844 return N->getOperand(0); 845 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 846 return N->getOperand(1); 847 } 848 849 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 850 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 851 SmallPtrSet<SDNode*, 16> SeenOps; 852 bool Changed = false; // If we should replace this token factor. 853 854 // Start out with this token factor. 855 TFs.push_back(N); 856 857 // Iterate through token factors. The TFs grows when new token factors are 858 // encountered. 859 for (unsigned i = 0; i < TFs.size(); ++i) { 860 SDNode *TF = TFs[i]; 861 862 // Check each of the operands. 863 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 864 SDValue Op = TF->getOperand(i); 865 866 switch (Op.getOpcode()) { 867 case ISD::EntryToken: 868 // Entry tokens don't need to be added to the list. They are 869 // rededundant. 870 Changed = true; 871 break; 872 873 case ISD::TokenFactor: 874 if ((CombinerAA || Op.hasOneUse()) && 875 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 876 // Queue up for processing. 877 TFs.push_back(Op.getNode()); 878 // Clean up in case the token factor is removed. 879 AddToWorkList(Op.getNode()); 880 Changed = true; 881 break; 882 } 883 // Fall thru 884 885 default: 886 // Only add if it isn't already in the list. 887 if (SeenOps.insert(Op.getNode())) 888 Ops.push_back(Op); 889 else 890 Changed = true; 891 break; 892 } 893 } 894 } 895 896 SDValue Result; 897 898 // If we've change things around then replace token factor. 899 if (Changed) { 900 if (Ops.empty()) { 901 // The entry token is the only possible outcome. 902 Result = DAG.getEntryNode(); 903 } else { 904 // New and improved token factor. 905 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 906 MVT::Other, &Ops[0], Ops.size()); 907 } 908 909 // Don't add users to work list. 910 return CombineTo(N, Result, false); 911 } 912 913 return Result; 914} 915 916/// MERGE_VALUES can always be eliminated. 917SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 918 WorkListRemover DeadNodes(*this); 919 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 920 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 921 &DeadNodes); 922 removeFromWorkList(N); 923 DAG.DeleteNode(N); 924 return SDValue(N, 0); // Return N so it doesn't get rechecked! 925} 926 927static 928SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 929 SelectionDAG &DAG) { 930 MVT VT = N0.getValueType(); 931 SDValue N00 = N0.getOperand(0); 932 SDValue N01 = N0.getOperand(1); 933 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 934 935 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 936 isa<ConstantSDNode>(N00.getOperand(1))) { 937 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 938 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 939 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 940 N00.getOperand(0), N01), 941 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 942 N00.getOperand(1), N01)); 943 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 944 } 945 946 return SDValue(); 947} 948 949SDValue DAGCombiner::visitADD(SDNode *N) { 950 SDValue N0 = N->getOperand(0); 951 SDValue N1 = N->getOperand(1); 952 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 953 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 954 MVT VT = N0.getValueType(); 955 956 // fold vector ops 957 if (VT.isVector()) { 958 SDValue FoldedVOp = SimplifyVBinOp(N); 959 if (FoldedVOp.getNode()) return FoldedVOp; 960 } 961 962 // fold (add x, undef) -> undef 963 if (N0.getOpcode() == ISD::UNDEF) 964 return N0; 965 if (N1.getOpcode() == ISD::UNDEF) 966 return N1; 967 // fold (add c1, c2) -> c1+c2 968 if (N0C && N1C) 969 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 970 // canonicalize constant to RHS 971 if (N0C && !N1C) 972 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 973 // fold (add x, 0) -> x 974 if (N1C && N1C->isNullValue()) 975 return N0; 976 // fold (add Sym, c) -> Sym+c 977 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 978 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 979 GA->getOpcode() == ISD::GlobalAddress) 980 return DAG.getGlobalAddress(GA->getGlobal(), VT, 981 GA->getOffset() + 982 (uint64_t)N1C->getSExtValue()); 983 // fold ((c1-A)+c2) -> (c1+c2)-A 984 if (N1C && N0.getOpcode() == ISD::SUB) 985 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 986 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 987 DAG.getConstant(N1C->getAPIntValue()+ 988 N0C->getAPIntValue(), VT), 989 N0.getOperand(1)); 990 // reassociate add 991 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 992 if (RADD.getNode() != 0) 993 return RADD; 994 // fold ((0-A) + B) -> B-A 995 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 996 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 997 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 998 // fold (A + (0-B)) -> A-B 999 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1000 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1001 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1002 // fold (A+(B-A)) -> B 1003 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1004 return N1.getOperand(0); 1005 // fold ((B-A)+A) -> B 1006 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1007 return N0.getOperand(0); 1008 // fold (A+(B-(A+C))) to (B-C) 1009 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1010 N0 == N1.getOperand(1).getOperand(0)) 1011 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1012 N1.getOperand(1).getOperand(1)); 1013 // fold (A+(B-(C+A))) to (B-C) 1014 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1015 N0 == N1.getOperand(1).getOperand(1)) 1016 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1017 N1.getOperand(1).getOperand(0)); 1018 // fold (A+((B-A)+or-C)) to (B+or-C) 1019 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1020 N1.getOperand(0).getOpcode() == ISD::SUB && 1021 N0 == N1.getOperand(0).getOperand(1)) 1022 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1023 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1024 1025 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1026 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1027 SDValue N00 = N0.getOperand(0); 1028 SDValue N01 = N0.getOperand(1); 1029 SDValue N10 = N1.getOperand(0); 1030 SDValue N11 = N1.getOperand(1); 1031 1032 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1034 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1035 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1036 } 1037 1038 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1039 return SDValue(N, 0); 1040 1041 // fold (a+b) -> (a|b) iff a and b share no bits. 1042 if (VT.isInteger() && !VT.isVector()) { 1043 APInt LHSZero, LHSOne; 1044 APInt RHSZero, RHSOne; 1045 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1046 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1047 1048 if (LHSZero.getBoolValue()) { 1049 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1050 1051 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1052 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1053 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1054 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1055 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1056 } 1057 } 1058 1059 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1060 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1061 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1062 if (Result.getNode()) return Result; 1063 } 1064 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1065 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1066 if (Result.getNode()) return Result; 1067 } 1068 1069 return SDValue(); 1070} 1071 1072SDValue DAGCombiner::visitADDC(SDNode *N) { 1073 SDValue N0 = N->getOperand(0); 1074 SDValue N1 = N->getOperand(1); 1075 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1076 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1077 MVT VT = N0.getValueType(); 1078 1079 // If the flag result is dead, turn this into an ADD. 1080 if (N->hasNUsesOfValue(0, 1)) 1081 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1082 DAG.getNode(ISD::CARRY_FALSE, 1083 N->getDebugLoc(), MVT::Flag)); 1084 1085 // canonicalize constant to RHS. 1086 if (N0C && !N1C) 1087 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1088 1089 // fold (addc x, 0) -> x + no carry out 1090 if (N1C && N1C->isNullValue()) 1091 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1092 N->getDebugLoc(), MVT::Flag)); 1093 1094 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1095 APInt LHSZero, LHSOne; 1096 APInt RHSZero, RHSOne; 1097 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1098 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1099 1100 if (LHSZero.getBoolValue()) { 1101 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1102 1103 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1104 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1105 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1106 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1107 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1108 DAG.getNode(ISD::CARRY_FALSE, 1109 N->getDebugLoc(), MVT::Flag)); 1110 } 1111 1112 return SDValue(); 1113} 1114 1115SDValue DAGCombiner::visitADDE(SDNode *N) { 1116 SDValue N0 = N->getOperand(0); 1117 SDValue N1 = N->getOperand(1); 1118 SDValue CarryIn = N->getOperand(2); 1119 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1120 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1121 1122 // canonicalize constant to RHS 1123 if (N0C && !N1C) 1124 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1125 N1, N0, CarryIn); 1126 1127 // fold (adde x, y, false) -> (addc x, y) 1128 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1129 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1130 1131 return SDValue(); 1132} 1133 1134SDValue DAGCombiner::visitSUB(SDNode *N) { 1135 SDValue N0 = N->getOperand(0); 1136 SDValue N1 = N->getOperand(1); 1137 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1138 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1139 MVT VT = N0.getValueType(); 1140 1141 // fold vector ops 1142 if (VT.isVector()) { 1143 SDValue FoldedVOp = SimplifyVBinOp(N); 1144 if (FoldedVOp.getNode()) return FoldedVOp; 1145 } 1146 1147 // fold (sub x, x) -> 0 1148 if (N0 == N1) 1149 return DAG.getConstant(0, N->getValueType(0)); 1150 // fold (sub c1, c2) -> c1-c2 1151 if (N0C && N1C) 1152 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1153 // fold (sub x, c) -> (add x, -c) 1154 if (N1C) 1155 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1156 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1157 // fold (A+B)-A -> B 1158 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1159 return N0.getOperand(1); 1160 // fold (A+B)-B -> A 1161 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1162 return N0.getOperand(0); 1163 // fold ((A+(B+or-C))-B) -> A+or-C 1164 if (N0.getOpcode() == ISD::ADD && 1165 (N0.getOperand(1).getOpcode() == ISD::SUB || 1166 N0.getOperand(1).getOpcode() == ISD::ADD) && 1167 N0.getOperand(1).getOperand(0) == N1) 1168 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1169 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1170 // fold ((A+(C+B))-B) -> A+C 1171 if (N0.getOpcode() == ISD::ADD && 1172 N0.getOperand(1).getOpcode() == ISD::ADD && 1173 N0.getOperand(1).getOperand(1) == N1) 1174 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1175 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1176 // fold ((A-(B-C))-C) -> A-B 1177 if (N0.getOpcode() == ISD::SUB && 1178 N0.getOperand(1).getOpcode() == ISD::SUB && 1179 N0.getOperand(1).getOperand(1) == N1) 1180 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1181 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1182 1183 // If either operand of a sub is undef, the result is undef 1184 if (N0.getOpcode() == ISD::UNDEF) 1185 return N0; 1186 if (N1.getOpcode() == ISD::UNDEF) 1187 return N1; 1188 1189 // If the relocation model supports it, consider symbol offsets. 1190 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1191 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1192 // fold (sub Sym, c) -> Sym-c 1193 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1194 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1195 GA->getOffset() - 1196 (uint64_t)N1C->getSExtValue()); 1197 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1198 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1199 if (GA->getGlobal() == GB->getGlobal()) 1200 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1201 VT); 1202 } 1203 1204 return SDValue(); 1205} 1206 1207SDValue DAGCombiner::visitMUL(SDNode *N) { 1208 SDValue N0 = N->getOperand(0); 1209 SDValue N1 = N->getOperand(1); 1210 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1211 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1212 MVT VT = N0.getValueType(); 1213 1214 // fold vector ops 1215 if (VT.isVector()) { 1216 SDValue FoldedVOp = SimplifyVBinOp(N); 1217 if (FoldedVOp.getNode()) return FoldedVOp; 1218 } 1219 1220 // fold (mul x, undef) -> 0 1221 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1222 return DAG.getConstant(0, VT); 1223 // fold (mul c1, c2) -> c1*c2 1224 if (N0C && N1C) 1225 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1226 // canonicalize constant to RHS 1227 if (N0C && !N1C) 1228 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1229 // fold (mul x, 0) -> 0 1230 if (N1C && N1C->isNullValue()) 1231 return N1; 1232 // fold (mul x, -1) -> 0-x 1233 if (N1C && N1C->isAllOnesValue()) 1234 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1235 DAG.getConstant(0, VT), N0); 1236 // fold (mul x, (1 << c)) -> x << c 1237 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1238 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1239 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1240 getShiftAmountTy())); 1241 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1242 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1243 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1244 // FIXME: If the input is something that is easily negated (e.g. a 1245 // single-use add), we should put the negate there. 1246 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1247 DAG.getConstant(0, VT), 1248 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1249 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1250 } 1251 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1252 if (N1C && N0.getOpcode() == ISD::SHL && 1253 isa<ConstantSDNode>(N0.getOperand(1))) { 1254 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1255 N1, N0.getOperand(1)); 1256 AddToWorkList(C3.getNode()); 1257 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1258 N0.getOperand(0), C3); 1259 } 1260 1261 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1262 // use. 1263 { 1264 SDValue Sh(0,0), Y(0,0); 1265 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1266 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1267 N0.getNode()->hasOneUse()) { 1268 Sh = N0; Y = N1; 1269 } else if (N1.getOpcode() == ISD::SHL && 1270 isa<ConstantSDNode>(N1.getOperand(1)) && 1271 N1.getNode()->hasOneUse()) { 1272 Sh = N1; Y = N0; 1273 } 1274 1275 if (Sh.getNode()) { 1276 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1277 Sh.getOperand(0), Y); 1278 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1279 Mul, Sh.getOperand(1)); 1280 } 1281 } 1282 1283 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1284 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1285 isa<ConstantSDNode>(N0.getOperand(1))) 1286 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1287 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1288 N0.getOperand(0), N1), 1289 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1290 N0.getOperand(1), N1)); 1291 1292 // reassociate mul 1293 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1294 if (RMUL.getNode() != 0) 1295 return RMUL; 1296 1297 return SDValue(); 1298} 1299 1300SDValue DAGCombiner::visitSDIV(SDNode *N) { 1301 SDValue N0 = N->getOperand(0); 1302 SDValue N1 = N->getOperand(1); 1303 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1304 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1305 MVT VT = N->getValueType(0); 1306 1307 // fold vector ops 1308 if (VT.isVector()) { 1309 SDValue FoldedVOp = SimplifyVBinOp(N); 1310 if (FoldedVOp.getNode()) return FoldedVOp; 1311 } 1312 1313 // fold (sdiv c1, c2) -> c1/c2 1314 if (N0C && N1C && !N1C->isNullValue()) 1315 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1316 // fold (sdiv X, 1) -> X 1317 if (N1C && N1C->getSExtValue() == 1LL) 1318 return N0; 1319 // fold (sdiv X, -1) -> 0-X 1320 if (N1C && N1C->isAllOnesValue()) 1321 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1322 DAG.getConstant(0, VT), N0); 1323 // If we know the sign bits of both operands are zero, strength reduce to a 1324 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1325 if (!VT.isVector()) { 1326 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1327 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1328 N0, N1); 1329 } 1330 // fold (sdiv X, pow2) -> simple ops after legalize 1331 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1332 (isPowerOf2_64(N1C->getSExtValue()) || 1333 isPowerOf2_64(-N1C->getSExtValue()))) { 1334 // If dividing by powers of two is cheap, then don't perform the following 1335 // fold. 1336 if (TLI.isPow2DivCheap()) 1337 return SDValue(); 1338 1339 int64_t pow2 = N1C->getSExtValue(); 1340 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1341 unsigned lg2 = Log2_64(abs2); 1342 1343 // Splat the sign bit into the register 1344 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1345 DAG.getConstant(VT.getSizeInBits()-1, 1346 getShiftAmountTy())); 1347 AddToWorkList(SGN.getNode()); 1348 1349 // Add (N0 < 0) ? abs2 - 1 : 0; 1350 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1351 DAG.getConstant(VT.getSizeInBits() - lg2, 1352 getShiftAmountTy())); 1353 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1354 AddToWorkList(SRL.getNode()); 1355 AddToWorkList(ADD.getNode()); // Divide by pow2 1356 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1357 DAG.getConstant(lg2, getShiftAmountTy())); 1358 1359 // If we're dividing by a positive value, we're done. Otherwise, we must 1360 // negate the result. 1361 if (pow2 > 0) 1362 return SRA; 1363 1364 AddToWorkList(SRA.getNode()); 1365 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1366 DAG.getConstant(0, VT), SRA); 1367 } 1368 1369 // if integer divide is expensive and we satisfy the requirements, emit an 1370 // alternate sequence. 1371 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1372 !TLI.isIntDivCheap()) { 1373 SDValue Op = BuildSDIV(N); 1374 if (Op.getNode()) return Op; 1375 } 1376 1377 // undef / X -> 0 1378 if (N0.getOpcode() == ISD::UNDEF) 1379 return DAG.getConstant(0, VT); 1380 // X / undef -> undef 1381 if (N1.getOpcode() == ISD::UNDEF) 1382 return N1; 1383 1384 return SDValue(); 1385} 1386 1387SDValue DAGCombiner::visitUDIV(SDNode *N) { 1388 SDValue N0 = N->getOperand(0); 1389 SDValue N1 = N->getOperand(1); 1390 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1391 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1392 MVT VT = N->getValueType(0); 1393 1394 // fold vector ops 1395 if (VT.isVector()) { 1396 SDValue FoldedVOp = SimplifyVBinOp(N); 1397 if (FoldedVOp.getNode()) return FoldedVOp; 1398 } 1399 1400 // fold (udiv c1, c2) -> c1/c2 1401 if (N0C && N1C && !N1C->isNullValue()) 1402 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1403 // fold (udiv x, (1 << c)) -> x >>u c 1404 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1405 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1406 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1407 getShiftAmountTy())); 1408 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1409 if (N1.getOpcode() == ISD::SHL) { 1410 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1411 if (SHC->getAPIntValue().isPowerOf2()) { 1412 MVT ADDVT = N1.getOperand(1).getValueType(); 1413 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1414 N1.getOperand(1), 1415 DAG.getConstant(SHC->getAPIntValue() 1416 .logBase2(), 1417 ADDVT)); 1418 AddToWorkList(Add.getNode()); 1419 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1420 } 1421 } 1422 } 1423 // fold (udiv x, c) -> alternate 1424 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1425 SDValue Op = BuildUDIV(N); 1426 if (Op.getNode()) return Op; 1427 } 1428 1429 // undef / X -> 0 1430 if (N0.getOpcode() == ISD::UNDEF) 1431 return DAG.getConstant(0, VT); 1432 // X / undef -> undef 1433 if (N1.getOpcode() == ISD::UNDEF) 1434 return N1; 1435 1436 return SDValue(); 1437} 1438 1439SDValue DAGCombiner::visitSREM(SDNode *N) { 1440 SDValue N0 = N->getOperand(0); 1441 SDValue N1 = N->getOperand(1); 1442 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1443 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1444 MVT VT = N->getValueType(0); 1445 1446 // fold (srem c1, c2) -> c1%c2 1447 if (N0C && N1C && !N1C->isNullValue()) 1448 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1449 // If we know the sign bits of both operands are zero, strength reduce to a 1450 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1451 if (!VT.isVector()) { 1452 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1453 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1454 } 1455 1456 // If X/C can be simplified by the division-by-constant logic, lower 1457 // X%C to the equivalent of X-X/C*C. 1458 if (N1C && !N1C->isNullValue()) { 1459 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1460 AddToWorkList(Div.getNode()); 1461 SDValue OptimizedDiv = combine(Div.getNode()); 1462 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1463 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1464 OptimizedDiv, N1); 1465 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1466 AddToWorkList(Mul.getNode()); 1467 return Sub; 1468 } 1469 } 1470 1471 // undef % X -> 0 1472 if (N0.getOpcode() == ISD::UNDEF) 1473 return DAG.getConstant(0, VT); 1474 // X % undef -> undef 1475 if (N1.getOpcode() == ISD::UNDEF) 1476 return N1; 1477 1478 return SDValue(); 1479} 1480 1481SDValue DAGCombiner::visitUREM(SDNode *N) { 1482 SDValue N0 = N->getOperand(0); 1483 SDValue N1 = N->getOperand(1); 1484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1486 MVT VT = N->getValueType(0); 1487 1488 // fold (urem c1, c2) -> c1%c2 1489 if (N0C && N1C && !N1C->isNullValue()) 1490 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1491 // fold (urem x, pow2) -> (and x, pow2-1) 1492 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1493 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1494 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1495 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1496 if (N1.getOpcode() == ISD::SHL) { 1497 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1498 if (SHC->getAPIntValue().isPowerOf2()) { 1499 SDValue Add = 1500 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1501 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1502 VT)); 1503 AddToWorkList(Add.getNode()); 1504 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1505 } 1506 } 1507 } 1508 1509 // If X/C can be simplified by the division-by-constant logic, lower 1510 // X%C to the equivalent of X-X/C*C. 1511 if (N1C && !N1C->isNullValue()) { 1512 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1513 AddToWorkList(Div.getNode()); 1514 SDValue OptimizedDiv = combine(Div.getNode()); 1515 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1516 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1517 OptimizedDiv, N1); 1518 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1519 AddToWorkList(Mul.getNode()); 1520 return Sub; 1521 } 1522 } 1523 1524 // undef % X -> 0 1525 if (N0.getOpcode() == ISD::UNDEF) 1526 return DAG.getConstant(0, VT); 1527 // X % undef -> undef 1528 if (N1.getOpcode() == ISD::UNDEF) 1529 return N1; 1530 1531 return SDValue(); 1532} 1533 1534SDValue DAGCombiner::visitMULHS(SDNode *N) { 1535 SDValue N0 = N->getOperand(0); 1536 SDValue N1 = N->getOperand(1); 1537 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1538 MVT VT = N->getValueType(0); 1539 1540 // fold (mulhs x, 0) -> 0 1541 if (N1C && N1C->isNullValue()) 1542 return N1; 1543 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1544 if (N1C && N1C->getAPIntValue() == 1) 1545 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1546 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1547 getShiftAmountTy())); 1548 // fold (mulhs x, undef) -> 0 1549 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1550 return DAG.getConstant(0, VT); 1551 1552 return SDValue(); 1553} 1554 1555SDValue DAGCombiner::visitMULHU(SDNode *N) { 1556 SDValue N0 = N->getOperand(0); 1557 SDValue N1 = N->getOperand(1); 1558 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1559 MVT VT = N->getValueType(0); 1560 1561 // fold (mulhu x, 0) -> 0 1562 if (N1C && N1C->isNullValue()) 1563 return N1; 1564 // fold (mulhu x, 1) -> 0 1565 if (N1C && N1C->getAPIntValue() == 1) 1566 return DAG.getConstant(0, N0.getValueType()); 1567 // fold (mulhu x, undef) -> 0 1568 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1569 return DAG.getConstant(0, VT); 1570 1571 return SDValue(); 1572} 1573 1574/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1575/// compute two values. LoOp and HiOp give the opcodes for the two computations 1576/// that are being performed. Return true if a simplification was made. 1577/// 1578SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1579 unsigned HiOp) { 1580 // If the high half is not needed, just compute the low half. 1581 bool HiExists = N->hasAnyUseOfValue(1); 1582 if (!HiExists && 1583 (!LegalOperations || 1584 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1585 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1586 N->op_begin(), N->getNumOperands()); 1587 return CombineTo(N, Res, Res); 1588 } 1589 1590 // If the low half is not needed, just compute the high half. 1591 bool LoExists = N->hasAnyUseOfValue(0); 1592 if (!LoExists && 1593 (!LegalOperations || 1594 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1595 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1596 N->op_begin(), N->getNumOperands()); 1597 return CombineTo(N, Res, Res); 1598 } 1599 1600 // If both halves are used, return as it is. 1601 if (LoExists && HiExists) 1602 return SDValue(); 1603 1604 // If the two computed results can be simplified separately, separate them. 1605 if (LoExists) { 1606 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1607 N->op_begin(), N->getNumOperands()); 1608 AddToWorkList(Lo.getNode()); 1609 SDValue LoOpt = combine(Lo.getNode()); 1610 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1611 (!LegalOperations || 1612 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1613 return CombineTo(N, LoOpt, LoOpt); 1614 } 1615 1616 if (HiExists) { 1617 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1618 N->op_begin(), N->getNumOperands()); 1619 AddToWorkList(Hi.getNode()); 1620 SDValue HiOpt = combine(Hi.getNode()); 1621 if (HiOpt.getNode() && HiOpt != Hi && 1622 (!LegalOperations || 1623 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1624 return CombineTo(N, HiOpt, HiOpt); 1625 } 1626 1627 return SDValue(); 1628} 1629 1630SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1631 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1632 if (Res.getNode()) return Res; 1633 1634 return SDValue(); 1635} 1636 1637SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1638 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1639 if (Res.getNode()) return Res; 1640 1641 return SDValue(); 1642} 1643 1644SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1645 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1646 if (Res.getNode()) return Res; 1647 1648 return SDValue(); 1649} 1650 1651SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1652 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1653 if (Res.getNode()) return Res; 1654 1655 return SDValue(); 1656} 1657 1658/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1659/// two operands of the same opcode, try to simplify it. 1660SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1661 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1662 MVT VT = N0.getValueType(); 1663 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1664 1665 // For each of OP in AND/OR/XOR: 1666 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1667 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1668 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1669 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1670 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1671 N0.getOpcode() == ISD::SIGN_EXTEND || 1672 (N0.getOpcode() == ISD::TRUNCATE && 1673 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1674 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1675 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1676 N0.getOperand(0).getValueType(), 1677 N0.getOperand(0), N1.getOperand(0)); 1678 AddToWorkList(ORNode.getNode()); 1679 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1680 } 1681 1682 // For each of OP in SHL/SRL/SRA/AND... 1683 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1684 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1685 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1686 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1687 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1688 N0.getOperand(1) == N1.getOperand(1)) { 1689 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1690 N0.getOperand(0).getValueType(), 1691 N0.getOperand(0), N1.getOperand(0)); 1692 AddToWorkList(ORNode.getNode()); 1693 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1694 ORNode, N0.getOperand(1)); 1695 } 1696 1697 return SDValue(); 1698} 1699 1700SDValue DAGCombiner::visitAND(SDNode *N) { 1701 SDValue N0 = N->getOperand(0); 1702 SDValue N1 = N->getOperand(1); 1703 SDValue LL, LR, RL, RR, CC0, CC1; 1704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1706 MVT VT = N1.getValueType(); 1707 unsigned BitWidth = VT.getSizeInBits(); 1708 1709 // fold vector ops 1710 if (VT.isVector()) { 1711 SDValue FoldedVOp = SimplifyVBinOp(N); 1712 if (FoldedVOp.getNode()) return FoldedVOp; 1713 } 1714 1715 // fold (and x, undef) -> 0 1716 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1717 return DAG.getConstant(0, VT); 1718 // fold (and c1, c2) -> c1&c2 1719 if (N0C && N1C) 1720 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1721 // canonicalize constant to RHS 1722 if (N0C && !N1C) 1723 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1724 // fold (and x, -1) -> x 1725 if (N1C && N1C->isAllOnesValue()) 1726 return N0; 1727 // if (and x, c) is known to be zero, return 0 1728 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1729 APInt::getAllOnesValue(BitWidth))) 1730 return DAG.getConstant(0, VT); 1731 // reassociate and 1732 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1733 if (RAND.getNode() != 0) 1734 return RAND; 1735 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1736 if (N1C && N0.getOpcode() == ISD::OR) 1737 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1738 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1739 return N1; 1740 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1741 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1742 SDValue N0Op0 = N0.getOperand(0); 1743 APInt Mask = ~N1C->getAPIntValue(); 1744 Mask.trunc(N0Op0.getValueSizeInBits()); 1745 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1746 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1747 N0.getValueType(), N0Op0); 1748 1749 // Replace uses of the AND with uses of the Zero extend node. 1750 CombineTo(N, Zext); 1751 1752 // We actually want to replace all uses of the any_extend with the 1753 // zero_extend, to avoid duplicating things. This will later cause this 1754 // AND to be folded. 1755 CombineTo(N0.getNode(), Zext); 1756 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1757 } 1758 } 1759 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1760 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1761 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1762 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1763 1764 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1765 LL.getValueType().isInteger()) { 1766 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1767 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1768 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1769 LR.getValueType(), LL, RL); 1770 AddToWorkList(ORNode.getNode()); 1771 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1772 } 1773 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1774 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1775 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1776 LR.getValueType(), LL, RL); 1777 AddToWorkList(ANDNode.getNode()); 1778 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1779 } 1780 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1781 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1782 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1783 LR.getValueType(), LL, RL); 1784 AddToWorkList(ORNode.getNode()); 1785 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1786 } 1787 } 1788 // canonicalize equivalent to ll == rl 1789 if (LL == RR && LR == RL) { 1790 Op1 = ISD::getSetCCSwappedOperands(Op1); 1791 std::swap(RL, RR); 1792 } 1793 if (LL == RL && LR == RR) { 1794 bool isInteger = LL.getValueType().isInteger(); 1795 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1796 if (Result != ISD::SETCC_INVALID && 1797 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1798 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1799 LL, LR, Result); 1800 } 1801 } 1802 1803 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1804 if (N0.getOpcode() == N1.getOpcode()) { 1805 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1806 if (Tmp.getNode()) return Tmp; 1807 } 1808 1809 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1810 // fold (and (sra)) -> (and (srl)) when possible. 1811 if (!VT.isVector() && 1812 SimplifyDemandedBits(SDValue(N, 0))) 1813 return SDValue(N, 0); 1814 // fold (zext_inreg (extload x)) -> (zextload x) 1815 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1816 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1817 MVT EVT = LN0->getMemoryVT(); 1818 // If we zero all the possible extended bits, then we can turn this into 1819 // a zextload if we are running before legalize or the operation is legal. 1820 unsigned BitWidth = N1.getValueSizeInBits(); 1821 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1822 BitWidth - EVT.getSizeInBits())) && 1823 ((!LegalOperations && !LN0->isVolatile()) || 1824 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1825 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1826 LN0->getChain(), LN0->getBasePtr(), 1827 LN0->getSrcValue(), 1828 LN0->getSrcValueOffset(), EVT, 1829 LN0->isVolatile(), LN0->getAlignment()); 1830 AddToWorkList(N); 1831 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1832 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1833 } 1834 } 1835 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1836 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1837 N0.hasOneUse()) { 1838 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1839 MVT EVT = LN0->getMemoryVT(); 1840 // If we zero all the possible extended bits, then we can turn this into 1841 // a zextload if we are running before legalize or the operation is legal. 1842 unsigned BitWidth = N1.getValueSizeInBits(); 1843 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1844 BitWidth - EVT.getSizeInBits())) && 1845 ((!LegalOperations && !LN0->isVolatile()) || 1846 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1847 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1848 LN0->getChain(), 1849 LN0->getBasePtr(), LN0->getSrcValue(), 1850 LN0->getSrcValueOffset(), EVT, 1851 LN0->isVolatile(), LN0->getAlignment()); 1852 AddToWorkList(N); 1853 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1854 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1855 } 1856 } 1857 1858 // fold (and (load x), 255) -> (zextload x, i8) 1859 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1860 if (N1C && N0.getOpcode() == ISD::LOAD) { 1861 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1862 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1863 LN0->isUnindexed() && N0.hasOneUse() && 1864 // Do not change the width of a volatile load. 1865 !LN0->isVolatile()) { 1866 MVT EVT = MVT::Other; 1867 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1868 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1869 EVT = MVT::getIntegerVT(ActiveBits); 1870 1871 MVT LoadedVT = LN0->getMemoryVT(); 1872 1873 // Do not generate loads of non-round integer types since these can 1874 // be expensive (and would be wrong if the type is not byte sized). 1875 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1876 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1877 MVT PtrType = N0.getOperand(1).getValueType(); 1878 1879 // For big endian targets, we need to add an offset to the pointer to 1880 // load the correct bytes. For little endian systems, we merely need to 1881 // read fewer bytes from the same pointer. 1882 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1883 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1884 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1885 unsigned Alignment = LN0->getAlignment(); 1886 SDValue NewPtr = LN0->getBasePtr(); 1887 1888 if (TLI.isBigEndian()) { 1889 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1890 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1891 Alignment = MinAlign(Alignment, PtrOff); 1892 } 1893 1894 AddToWorkList(NewPtr.getNode()); 1895 SDValue Load = 1896 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1897 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1898 EVT, LN0->isVolatile(), Alignment); 1899 AddToWorkList(N); 1900 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1901 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1902 } 1903 } 1904 } 1905 1906 return SDValue(); 1907} 1908 1909SDValue DAGCombiner::visitOR(SDNode *N) { 1910 SDValue N0 = N->getOperand(0); 1911 SDValue N1 = N->getOperand(1); 1912 SDValue LL, LR, RL, RR, CC0, CC1; 1913 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1914 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1915 MVT VT = N1.getValueType(); 1916 1917 // fold vector ops 1918 if (VT.isVector()) { 1919 SDValue FoldedVOp = SimplifyVBinOp(N); 1920 if (FoldedVOp.getNode()) return FoldedVOp; 1921 } 1922 1923 // fold (or x, undef) -> -1 1924 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1925 return DAG.getConstant(~0ULL, VT); 1926 // fold (or c1, c2) -> c1|c2 1927 if (N0C && N1C) 1928 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1929 // canonicalize constant to RHS 1930 if (N0C && !N1C) 1931 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1932 // fold (or x, 0) -> x 1933 if (N1C && N1C->isNullValue()) 1934 return N0; 1935 // fold (or x, -1) -> -1 1936 if (N1C && N1C->isAllOnesValue()) 1937 return N1; 1938 // fold (or x, c) -> c iff (x & ~c) == 0 1939 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1940 return N1; 1941 // reassociate or 1942 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1943 if (ROR.getNode() != 0) 1944 return ROR; 1945 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1946 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1947 isa<ConstantSDNode>(N0.getOperand(1))) { 1948 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1949 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1950 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1951 N0.getOperand(0), N1), 1952 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1953 } 1954 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1955 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1956 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1957 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1958 1959 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1960 LL.getValueType().isInteger()) { 1961 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1962 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1963 if (cast<ConstantSDNode>(LR)->isNullValue() && 1964 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1965 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1966 LR.getValueType(), LL, RL); 1967 AddToWorkList(ORNode.getNode()); 1968 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1969 } 1970 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 1971 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 1972 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1973 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1974 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 1975 LR.getValueType(), LL, RL); 1976 AddToWorkList(ANDNode.getNode()); 1977 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1978 } 1979 } 1980 // canonicalize equivalent to ll == rl 1981 if (LL == RR && LR == RL) { 1982 Op1 = ISD::getSetCCSwappedOperands(Op1); 1983 std::swap(RL, RR); 1984 } 1985 if (LL == RL && LR == RR) { 1986 bool isInteger = LL.getValueType().isInteger(); 1987 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1988 if (Result != ISD::SETCC_INVALID && 1989 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1990 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1991 LL, LR, Result); 1992 } 1993 } 1994 1995 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 1996 if (N0.getOpcode() == N1.getOpcode()) { 1997 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1998 if (Tmp.getNode()) return Tmp; 1999 } 2000 2001 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2002 if (N0.getOpcode() == ISD::AND && 2003 N1.getOpcode() == ISD::AND && 2004 N0.getOperand(1).getOpcode() == ISD::Constant && 2005 N1.getOperand(1).getOpcode() == ISD::Constant && 2006 // Don't increase # computations. 2007 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2008 // We can only do this xform if we know that bits from X that are set in C2 2009 // but not in C1 are already zero. Likewise for Y. 2010 const APInt &LHSMask = 2011 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2012 const APInt &RHSMask = 2013 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2014 2015 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2016 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2017 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2018 N0.getOperand(0), N1.getOperand(0)); 2019 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2020 DAG.getConstant(LHSMask | RHSMask, VT)); 2021 } 2022 } 2023 2024 // See if this is some rotate idiom. 2025 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2026 return SDValue(Rot, 0); 2027 2028 return SDValue(); 2029} 2030 2031/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2032static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2033 if (Op.getOpcode() == ISD::AND) { 2034 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2035 Mask = Op.getOperand(1); 2036 Op = Op.getOperand(0); 2037 } else { 2038 return false; 2039 } 2040 } 2041 2042 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2043 Shift = Op; 2044 return true; 2045 } 2046 2047 return false; 2048} 2049 2050// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2051// idioms for rotate, and if the target supports rotation instructions, generate 2052// a rot[lr]. 2053SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2054 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2055 MVT VT = LHS.getValueType(); 2056 if (!TLI.isTypeLegal(VT)) return 0; 2057 2058 // The target must have at least one rotate flavor. 2059 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2060 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2061 if (!HasROTL && !HasROTR) return 0; 2062 2063 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2064 SDValue LHSShift; // The shift. 2065 SDValue LHSMask; // AND value if any. 2066 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2067 return 0; // Not part of a rotate. 2068 2069 SDValue RHSShift; // The shift. 2070 SDValue RHSMask; // AND value if any. 2071 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2072 return 0; // Not part of a rotate. 2073 2074 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2075 return 0; // Not shifting the same value. 2076 2077 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2078 return 0; // Shifts must disagree. 2079 2080 // Canonicalize shl to left side in a shl/srl pair. 2081 if (RHSShift.getOpcode() == ISD::SHL) { 2082 std::swap(LHS, RHS); 2083 std::swap(LHSShift, RHSShift); 2084 std::swap(LHSMask , RHSMask ); 2085 } 2086 2087 unsigned OpSizeInBits = VT.getSizeInBits(); 2088 SDValue LHSShiftArg = LHSShift.getOperand(0); 2089 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2090 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2091 2092 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2093 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2094 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2095 RHSShiftAmt.getOpcode() == ISD::Constant) { 2096 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2097 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2098 if ((LShVal + RShVal) != OpSizeInBits) 2099 return 0; 2100 2101 SDValue Rot; 2102 if (HasROTL) 2103 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2104 else 2105 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2106 2107 // If there is an AND of either shifted operand, apply it to the result. 2108 if (LHSMask.getNode() || RHSMask.getNode()) { 2109 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2110 2111 if (LHSMask.getNode()) { 2112 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2113 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2114 } 2115 if (RHSMask.getNode()) { 2116 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2117 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2118 } 2119 2120 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2121 } 2122 2123 return Rot.getNode(); 2124 } 2125 2126 // If there is a mask here, and we have a variable shift, we can't be sure 2127 // that we're masking out the right stuff. 2128 if (LHSMask.getNode() || RHSMask.getNode()) 2129 return 0; 2130 2131 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2132 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2133 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2134 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2135 if (ConstantSDNode *SUBC = 2136 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2137 if (SUBC->getAPIntValue() == OpSizeInBits) { 2138 if (HasROTL) 2139 return DAG.getNode(ISD::ROTL, DL, VT, 2140 LHSShiftArg, LHSShiftAmt).getNode(); 2141 else 2142 return DAG.getNode(ISD::ROTR, DL, VT, 2143 LHSShiftArg, RHSShiftAmt).getNode(); 2144 } 2145 } 2146 } 2147 2148 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2149 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2150 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2151 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2152 if (ConstantSDNode *SUBC = 2153 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2154 if (SUBC->getAPIntValue() == OpSizeInBits) { 2155 if (HasROTR) 2156 return DAG.getNode(ISD::ROTR, DL, VT, 2157 LHSShiftArg, RHSShiftAmt).getNode(); 2158 else 2159 return DAG.getNode(ISD::ROTL, DL, VT, 2160 LHSShiftArg, LHSShiftAmt).getNode(); 2161 } 2162 } 2163 } 2164 2165 // Look for sign/zext/any-extended or truncate cases: 2166 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2167 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2168 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2169 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2170 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2171 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2172 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2173 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2174 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2175 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2176 if (RExtOp0.getOpcode() == ISD::SUB && 2177 RExtOp0.getOperand(1) == LExtOp0) { 2178 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2179 // (rotl x, y) 2180 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2181 // (rotr x, (sub 32, y)) 2182 if (ConstantSDNode *SUBC = 2183 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2184 if (SUBC->getAPIntValue() == OpSizeInBits) { 2185 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2186 LHSShiftArg, 2187 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2188 } 2189 } 2190 } else if (LExtOp0.getOpcode() == ISD::SUB && 2191 RExtOp0 == LExtOp0.getOperand(1)) { 2192 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2193 // (rotr x, y) 2194 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2195 // (rotl x, (sub 32, y)) 2196 if (ConstantSDNode *SUBC = 2197 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2198 if (SUBC->getAPIntValue() == OpSizeInBits) { 2199 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2200 LHSShiftArg, 2201 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2202 } 2203 } 2204 } 2205 } 2206 2207 return 0; 2208} 2209 2210SDValue DAGCombiner::visitXOR(SDNode *N) { 2211 SDValue N0 = N->getOperand(0); 2212 SDValue N1 = N->getOperand(1); 2213 SDValue LHS, RHS, CC; 2214 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2215 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2216 MVT VT = N0.getValueType(); 2217 2218 // fold vector ops 2219 if (VT.isVector()) { 2220 SDValue FoldedVOp = SimplifyVBinOp(N); 2221 if (FoldedVOp.getNode()) return FoldedVOp; 2222 } 2223 2224 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2225 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2226 return DAG.getConstant(0, VT); 2227 // fold (xor x, undef) -> undef 2228 if (N0.getOpcode() == ISD::UNDEF) 2229 return N0; 2230 if (N1.getOpcode() == ISD::UNDEF) 2231 return N1; 2232 // fold (xor c1, c2) -> c1^c2 2233 if (N0C && N1C) 2234 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2235 // canonicalize constant to RHS 2236 if (N0C && !N1C) 2237 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2238 // fold (xor x, 0) -> x 2239 if (N1C && N1C->isNullValue()) 2240 return N0; 2241 // reassociate xor 2242 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2243 if (RXOR.getNode() != 0) 2244 return RXOR; 2245 2246 // fold !(x cc y) -> (x !cc y) 2247 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2248 bool isInt = LHS.getValueType().isInteger(); 2249 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2250 isInt); 2251 2252 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2253 switch (N0.getOpcode()) { 2254 default: 2255 assert(0 && "Unhandled SetCC Equivalent!"); 2256 abort(); 2257 case ISD::SETCC: 2258 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2259 case ISD::SELECT_CC: 2260 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2261 N0.getOperand(3), NotCC); 2262 } 2263 } 2264 } 2265 2266 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2267 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2268 N0.getNode()->hasOneUse() && 2269 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2270 SDValue V = N0.getOperand(0); 2271 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2272 DAG.getConstant(1, V.getValueType())); 2273 AddToWorkList(V.getNode()); 2274 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2275 } 2276 2277 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2278 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2279 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2280 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2281 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2282 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2283 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2284 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2285 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2286 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2287 } 2288 } 2289 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2290 if (N1C && N1C->isAllOnesValue() && 2291 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2292 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2293 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2294 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2295 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2296 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2297 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2298 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2299 } 2300 } 2301 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2302 if (N1C && N0.getOpcode() == ISD::XOR) { 2303 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2304 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2305 if (N00C) 2306 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2307 DAG.getConstant(N1C->getAPIntValue() ^ 2308 N00C->getAPIntValue(), VT)); 2309 if (N01C) 2310 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2311 DAG.getConstant(N1C->getAPIntValue() ^ 2312 N01C->getAPIntValue(), VT)); 2313 } 2314 // fold (xor x, x) -> 0 2315 if (N0 == N1) { 2316 if (!VT.isVector()) { 2317 return DAG.getConstant(0, VT); 2318 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2319 // Produce a vector of zeros. 2320 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2321 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2322 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2323 &Ops[0], Ops.size()); 2324 } 2325 } 2326 2327 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2328 if (N0.getOpcode() == N1.getOpcode()) { 2329 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2330 if (Tmp.getNode()) return Tmp; 2331 } 2332 2333 // Simplify the expression using non-local knowledge. 2334 if (!VT.isVector() && 2335 SimplifyDemandedBits(SDValue(N, 0))) 2336 return SDValue(N, 0); 2337 2338 return SDValue(); 2339} 2340 2341/// visitShiftByConstant - Handle transforms common to the three shifts, when 2342/// the shift amount is a constant. 2343SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2344 SDNode *LHS = N->getOperand(0).getNode(); 2345 if (!LHS->hasOneUse()) return SDValue(); 2346 2347 // We want to pull some binops through shifts, so that we have (and (shift)) 2348 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2349 // thing happens with address calculations, so it's important to canonicalize 2350 // it. 2351 bool HighBitSet = false; // Can we transform this if the high bit is set? 2352 2353 switch (LHS->getOpcode()) { 2354 default: return SDValue(); 2355 case ISD::OR: 2356 case ISD::XOR: 2357 HighBitSet = false; // We can only transform sra if the high bit is clear. 2358 break; 2359 case ISD::AND: 2360 HighBitSet = true; // We can only transform sra if the high bit is set. 2361 break; 2362 case ISD::ADD: 2363 if (N->getOpcode() != ISD::SHL) 2364 return SDValue(); // only shl(add) not sr[al](add). 2365 HighBitSet = false; // We can only transform sra if the high bit is clear. 2366 break; 2367 } 2368 2369 // We require the RHS of the binop to be a constant as well. 2370 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2371 if (!BinOpCst) return SDValue(); 2372 2373 // FIXME: disable this unless the input to the binop is a shift by a constant. 2374 // If it is not a shift, it pessimizes some common cases like: 2375 // 2376 // void foo(int *X, int i) { X[i & 1235] = 1; } 2377 // int bar(int *X, int i) { return X[i & 255]; } 2378 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2379 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2380 BinOpLHSVal->getOpcode() != ISD::SRA && 2381 BinOpLHSVal->getOpcode() != ISD::SRL) || 2382 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2383 return SDValue(); 2384 2385 MVT VT = N->getValueType(0); 2386 2387 // If this is a signed shift right, and the high bit is modified by the 2388 // logical operation, do not perform the transformation. The highBitSet 2389 // boolean indicates the value of the high bit of the constant which would 2390 // cause it to be modified for this operation. 2391 if (N->getOpcode() == ISD::SRA) { 2392 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2393 if (BinOpRHSSignSet != HighBitSet) 2394 return SDValue(); 2395 } 2396 2397 // Fold the constants, shifting the binop RHS by the shift amount. 2398 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2399 N->getValueType(0), 2400 LHS->getOperand(1), N->getOperand(1)); 2401 2402 // Create the new shift. 2403 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2404 VT, LHS->getOperand(0), N->getOperand(1)); 2405 2406 // Create the new binop. 2407 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2408} 2409 2410SDValue DAGCombiner::visitSHL(SDNode *N) { 2411 SDValue N0 = N->getOperand(0); 2412 SDValue N1 = N->getOperand(1); 2413 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2414 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2415 MVT VT = N0.getValueType(); 2416 unsigned OpSizeInBits = VT.getSizeInBits(); 2417 2418 // fold (shl c1, c2) -> c1<<c2 2419 if (N0C && N1C) 2420 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2421 // fold (shl 0, x) -> 0 2422 if (N0C && N0C->isNullValue()) 2423 return N0; 2424 // fold (shl x, c >= size(x)) -> undef 2425 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2426 return DAG.getUNDEF(VT); 2427 // fold (shl x, 0) -> x 2428 if (N1C && N1C->isNullValue()) 2429 return N0; 2430 // if (shl x, c) is known to be zero, return 0 2431 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2432 APInt::getAllOnesValue(VT.getSizeInBits()))) 2433 return DAG.getConstant(0, VT); 2434 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2435 if (N1.getOpcode() == ISD::TRUNCATE && 2436 N1.getOperand(0).getOpcode() == ISD::AND && 2437 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2438 SDValue N101 = N1.getOperand(0).getOperand(1); 2439 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2440 MVT TruncVT = N1.getValueType(); 2441 SDValue N100 = N1.getOperand(0).getOperand(0); 2442 APInt TruncC = N101C->getAPIntValue(); 2443 TruncC.trunc(TruncVT.getSizeInBits()); 2444 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2445 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2446 DAG.getNode(ISD::TRUNCATE, 2447 N->getDebugLoc(), 2448 TruncVT, N100), 2449 DAG.getConstant(TruncC, TruncVT))); 2450 } 2451 } 2452 2453 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2454 return SDValue(N, 0); 2455 2456 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2457 if (N1C && N0.getOpcode() == ISD::SHL && 2458 N0.getOperand(1).getOpcode() == ISD::Constant) { 2459 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2460 uint64_t c2 = N1C->getZExtValue(); 2461 if (c1 + c2 > OpSizeInBits) 2462 return DAG.getConstant(0, VT); 2463 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2464 DAG.getConstant(c1 + c2, N1.getValueType())); 2465 } 2466 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2467 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2468 if (N1C && N0.getOpcode() == ISD::SRL && 2469 N0.getOperand(1).getOpcode() == ISD::Constant) { 2470 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2471 uint64_t c2 = N1C->getZExtValue(); 2472 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), 2473 DAG.getConstant(~0ULL << c1, VT)); 2474 if (c2 > c1) 2475 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2476 DAG.getConstant(c2-c1, N1.getValueType())); 2477 else 2478 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2479 DAG.getConstant(c1-c2, N1.getValueType())); 2480 } 2481 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2482 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2483 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2484 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2485 2486 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2487} 2488 2489SDValue DAGCombiner::visitSRA(SDNode *N) { 2490 SDValue N0 = N->getOperand(0); 2491 SDValue N1 = N->getOperand(1); 2492 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2493 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2494 MVT VT = N0.getValueType(); 2495 2496 // fold (sra c1, c2) -> (sra c1, c2) 2497 if (N0C && N1C) 2498 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2499 // fold (sra 0, x) -> 0 2500 if (N0C && N0C->isNullValue()) 2501 return N0; 2502 // fold (sra -1, x) -> -1 2503 if (N0C && N0C->isAllOnesValue()) 2504 return N0; 2505 // fold (sra x, (setge c, size(x))) -> undef 2506 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2507 return DAG.getUNDEF(VT); 2508 // fold (sra x, 0) -> x 2509 if (N1C && N1C->isNullValue()) 2510 return N0; 2511 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2512 // sext_inreg. 2513 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2514 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2515 MVT EVT = MVT::getIntegerVT(LowBits); 2516 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2517 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2518 N0.getOperand(0), DAG.getValueType(EVT)); 2519 } 2520 2521 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2522 if (N1C && N0.getOpcode() == ISD::SRA) { 2523 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2524 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2525 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2526 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2527 DAG.getConstant(Sum, N1C->getValueType(0))); 2528 } 2529 } 2530 2531 // fold (sra (shl X, m), (sub result_size, n)) 2532 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2533 // result_size - n != m. 2534 // If truncate is free for the target sext(shl) is likely to result in better 2535 // code. 2536 if (N0.getOpcode() == ISD::SHL) { 2537 // Get the two constanst of the shifts, CN0 = m, CN = n. 2538 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2539 if (N01C && N1C) { 2540 // Determine what the truncate's result bitsize and type would be. 2541 unsigned VTValSize = VT.getSizeInBits(); 2542 MVT TruncVT = 2543 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2544 // Determine the residual right-shift amount. 2545 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2546 2547 // If the shift is not a no-op (in which case this should be just a sign 2548 // extend already), the truncated to type is legal, sign_extend is legal 2549 // on that type, and the the truncate to that type is both legal and free, 2550 // perform the transform. 2551 if (ShiftAmt && 2552 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2553 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2554 TLI.isTruncateFree(VT, TruncVT)) { 2555 2556 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2557 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2558 N0.getOperand(0), Amt); 2559 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2560 Shift); 2561 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2562 N->getValueType(0), Trunc); 2563 } 2564 } 2565 } 2566 2567 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2568 if (N1.getOpcode() == ISD::TRUNCATE && 2569 N1.getOperand(0).getOpcode() == ISD::AND && 2570 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2571 SDValue N101 = N1.getOperand(0).getOperand(1); 2572 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2573 MVT TruncVT = N1.getValueType(); 2574 SDValue N100 = N1.getOperand(0).getOperand(0); 2575 APInt TruncC = N101C->getAPIntValue(); 2576 TruncC.trunc(TruncVT.getSizeInBits()); 2577 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2578 DAG.getNode(ISD::AND, N->getDebugLoc(), 2579 TruncVT, 2580 DAG.getNode(ISD::TRUNCATE, 2581 N->getDebugLoc(), 2582 TruncVT, N100), 2583 DAG.getConstant(TruncC, TruncVT))); 2584 } 2585 } 2586 2587 // Simplify, based on bits shifted out of the LHS. 2588 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2589 return SDValue(N, 0); 2590 2591 2592 // If the sign bit is known to be zero, switch this to a SRL. 2593 if (DAG.SignBitIsZero(N0)) 2594 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2595 2596 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2597} 2598 2599SDValue DAGCombiner::visitSRL(SDNode *N) { 2600 SDValue N0 = N->getOperand(0); 2601 SDValue N1 = N->getOperand(1); 2602 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2603 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2604 MVT VT = N0.getValueType(); 2605 unsigned OpSizeInBits = VT.getSizeInBits(); 2606 2607 // fold (srl c1, c2) -> c1 >>u c2 2608 if (N0C && N1C) 2609 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2610 // fold (srl 0, x) -> 0 2611 if (N0C && N0C->isNullValue()) 2612 return N0; 2613 // fold (srl x, c >= size(x)) -> undef 2614 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2615 return DAG.getUNDEF(VT); 2616 // fold (srl x, 0) -> x 2617 if (N1C && N1C->isNullValue()) 2618 return N0; 2619 // if (srl x, c) is known to be zero, return 0 2620 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2621 APInt::getAllOnesValue(OpSizeInBits))) 2622 return DAG.getConstant(0, VT); 2623 2624 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2625 if (N1C && N0.getOpcode() == ISD::SRL && 2626 N0.getOperand(1).getOpcode() == ISD::Constant) { 2627 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2628 uint64_t c2 = N1C->getZExtValue(); 2629 if (c1 + c2 > OpSizeInBits) 2630 return DAG.getConstant(0, VT); 2631 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2632 DAG.getConstant(c1 + c2, N1.getValueType())); 2633 } 2634 2635 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2636 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2637 // Shifting in all undef bits? 2638 MVT SmallVT = N0.getOperand(0).getValueType(); 2639 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2640 return DAG.getUNDEF(VT); 2641 2642 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2643 N0.getOperand(0), N1); 2644 AddToWorkList(SmallShift.getNode()); 2645 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2646 } 2647 2648 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2649 // bit, which is unmodified by sra. 2650 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2651 if (N0.getOpcode() == ISD::SRA) 2652 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2653 } 2654 2655 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2656 if (N1C && N0.getOpcode() == ISD::CTLZ && 2657 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2658 APInt KnownZero, KnownOne; 2659 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2660 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2661 2662 // If any of the input bits are KnownOne, then the input couldn't be all 2663 // zeros, thus the result of the srl will always be zero. 2664 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2665 2666 // If all of the bits input the to ctlz node are known to be zero, then 2667 // the result of the ctlz is "32" and the result of the shift is one. 2668 APInt UnknownBits = ~KnownZero & Mask; 2669 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2670 2671 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2672 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2673 // Okay, we know that only that the single bit specified by UnknownBits 2674 // could be set on input to the CTLZ node. If this bit is set, the SRL 2675 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2676 // to an SRL/XOR pair, which is likely to simplify more. 2677 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2678 SDValue Op = N0.getOperand(0); 2679 2680 if (ShAmt) { 2681 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2682 DAG.getConstant(ShAmt, getShiftAmountTy())); 2683 AddToWorkList(Op.getNode()); 2684 } 2685 2686 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2687 Op, DAG.getConstant(1, VT)); 2688 } 2689 } 2690 2691 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2692 if (N1.getOpcode() == ISD::TRUNCATE && 2693 N1.getOperand(0).getOpcode() == ISD::AND && 2694 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2695 SDValue N101 = N1.getOperand(0).getOperand(1); 2696 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2697 MVT TruncVT = N1.getValueType(); 2698 SDValue N100 = N1.getOperand(0).getOperand(0); 2699 APInt TruncC = N101C->getAPIntValue(); 2700 TruncC.trunc(TruncVT.getSizeInBits()); 2701 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2702 DAG.getNode(ISD::AND, N->getDebugLoc(), 2703 TruncVT, 2704 DAG.getNode(ISD::TRUNCATE, 2705 N->getDebugLoc(), 2706 TruncVT, N100), 2707 DAG.getConstant(TruncC, TruncVT))); 2708 } 2709 } 2710 2711 // fold operands of srl based on knowledge that the low bits are not 2712 // demanded. 2713 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2714 return SDValue(N, 0); 2715 2716 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2717} 2718 2719SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2720 SDValue N0 = N->getOperand(0); 2721 MVT VT = N->getValueType(0); 2722 2723 // fold (ctlz c1) -> c2 2724 if (isa<ConstantSDNode>(N0)) 2725 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2726 return SDValue(); 2727} 2728 2729SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2730 SDValue N0 = N->getOperand(0); 2731 MVT VT = N->getValueType(0); 2732 2733 // fold (cttz c1) -> c2 2734 if (isa<ConstantSDNode>(N0)) 2735 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2736 return SDValue(); 2737} 2738 2739SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2740 SDValue N0 = N->getOperand(0); 2741 MVT VT = N->getValueType(0); 2742 2743 // fold (ctpop c1) -> c2 2744 if (isa<ConstantSDNode>(N0)) 2745 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2746 return SDValue(); 2747} 2748 2749SDValue DAGCombiner::visitSELECT(SDNode *N) { 2750 SDValue N0 = N->getOperand(0); 2751 SDValue N1 = N->getOperand(1); 2752 SDValue N2 = N->getOperand(2); 2753 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2754 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2755 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2756 MVT VT = N->getValueType(0); 2757 MVT VT0 = N0.getValueType(); 2758 2759 // fold (select C, X, X) -> X 2760 if (N1 == N2) 2761 return N1; 2762 // fold (select true, X, Y) -> X 2763 if (N0C && !N0C->isNullValue()) 2764 return N1; 2765 // fold (select false, X, Y) -> Y 2766 if (N0C && N0C->isNullValue()) 2767 return N2; 2768 // fold (select C, 1, X) -> (or C, X) 2769 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2770 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2771 // fold (select C, 0, 1) -> (xor C, 1) 2772 if (VT.isInteger() && 2773 (VT0 == MVT::i1 || 2774 (VT0.isInteger() && 2775 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2776 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2777 SDValue XORNode; 2778 if (VT == VT0) 2779 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2780 N0, DAG.getConstant(1, VT0)); 2781 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2782 N0, DAG.getConstant(1, VT0)); 2783 AddToWorkList(XORNode.getNode()); 2784 if (VT.bitsGT(VT0)) 2785 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2786 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2787 } 2788 // fold (select C, 0, X) -> (and (not C), X) 2789 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2790 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2791 AddToWorkList(NOTNode.getNode()); 2792 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2793 } 2794 // fold (select C, X, 1) -> (or (not C), X) 2795 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2796 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2797 AddToWorkList(NOTNode.getNode()); 2798 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2799 } 2800 // fold (select C, X, 0) -> (and C, X) 2801 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2802 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2803 // fold (select X, X, Y) -> (or X, Y) 2804 // fold (select X, 1, Y) -> (or X, Y) 2805 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2806 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2807 // fold (select X, Y, X) -> (and X, Y) 2808 // fold (select X, Y, 0) -> (and X, Y) 2809 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2810 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2811 2812 // If we can fold this based on the true/false value, do so. 2813 if (SimplifySelectOps(N, N1, N2)) 2814 return SDValue(N, 0); // Don't revisit N. 2815 2816 // fold selects based on a setcc into other things, such as min/max/abs 2817 if (N0.getOpcode() == ISD::SETCC) { 2818 // FIXME: 2819 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2820 // having to say they don't support SELECT_CC on every type the DAG knows 2821 // about, since there is no way to mark an opcode illegal at all value types 2822 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2823 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2824 N0.getOperand(0), N0.getOperand(1), 2825 N1, N2, N0.getOperand(2)); 2826 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2827 } 2828 2829 return SDValue(); 2830} 2831 2832SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2833 SDValue N0 = N->getOperand(0); 2834 SDValue N1 = N->getOperand(1); 2835 SDValue N2 = N->getOperand(2); 2836 SDValue N3 = N->getOperand(3); 2837 SDValue N4 = N->getOperand(4); 2838 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2839 2840 // fold select_cc lhs, rhs, x, x, cc -> x 2841 if (N2 == N3) 2842 return N2; 2843 2844 // Determine if the condition we're dealing with is constant 2845 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2846 N0, N1, CC, N->getDebugLoc(), false); 2847 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2848 2849 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2850 if (!SCCC->isNullValue()) 2851 return N2; // cond always true -> true val 2852 else 2853 return N3; // cond always false -> false val 2854 } 2855 2856 // Fold to a simpler select_cc 2857 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2858 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2859 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2860 SCC.getOperand(2)); 2861 2862 // If we can fold this based on the true/false value, do so. 2863 if (SimplifySelectOps(N, N2, N3)) 2864 return SDValue(N, 0); // Don't revisit N. 2865 2866 // fold select_cc into other things, such as min/max/abs 2867 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2868} 2869 2870SDValue DAGCombiner::visitSETCC(SDNode *N) { 2871 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2872 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2873 N->getDebugLoc()); 2874} 2875 2876// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2877// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2878// transformation. Returns true if extension are possible and the above 2879// mentioned transformation is profitable. 2880static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2881 unsigned ExtOpc, 2882 SmallVector<SDNode*, 4> &ExtendNodes, 2883 const TargetLowering &TLI) { 2884 bool HasCopyToRegUses = false; 2885 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2886 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2887 UE = N0.getNode()->use_end(); 2888 UI != UE; ++UI) { 2889 SDNode *User = *UI; 2890 if (User == N) 2891 continue; 2892 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2893 if (User->getOpcode() == ISD::SETCC) { 2894 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2895 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2896 // Sign bits will be lost after a zext. 2897 return false; 2898 bool Add = false; 2899 for (unsigned i = 0; i != 2; ++i) { 2900 SDValue UseOp = User->getOperand(i); 2901 if (UseOp == N0) 2902 continue; 2903 if (!isa<ConstantSDNode>(UseOp)) 2904 return false; 2905 Add = true; 2906 } 2907 if (Add) 2908 ExtendNodes.push_back(User); 2909 } else { 2910 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2911 SDValue UseOp = User->getOperand(i); 2912 if (UseOp == N0) { 2913 // If truncate from extended type to original load type is free 2914 // on this target, then it's ok to extend a CopyToReg. 2915 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2916 HasCopyToRegUses = true; 2917 else 2918 return false; 2919 } 2920 } 2921 } 2922 } 2923 2924 if (HasCopyToRegUses) { 2925 bool BothLiveOut = false; 2926 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2927 UI != UE; ++UI) { 2928 SDNode *User = *UI; 2929 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2930 SDValue UseOp = User->getOperand(i); 2931 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2932 BothLiveOut = true; 2933 break; 2934 } 2935 } 2936 } 2937 if (BothLiveOut) 2938 // Both unextended and extended values are live out. There had better be 2939 // good a reason for the transformation. 2940 return ExtendNodes.size(); 2941 } 2942 return true; 2943} 2944 2945SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2946 SDValue N0 = N->getOperand(0); 2947 MVT VT = N->getValueType(0); 2948 2949 // fold (sext c1) -> c1 2950 if (isa<ConstantSDNode>(N0)) 2951 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2952 2953 // fold (sext (sext x)) -> (sext x) 2954 // fold (sext (aext x)) -> (sext x) 2955 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2956 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2957 N0.getOperand(0)); 2958 2959 if (N0.getOpcode() == ISD::TRUNCATE) { 2960 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2961 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2962 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2963 if (NarrowLoad.getNode()) { 2964 if (NarrowLoad.getNode() != N0.getNode()) 2965 CombineTo(N0.getNode(), NarrowLoad); 2966 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 2967 } 2968 2969 // See if the value being truncated is already sign extended. If so, just 2970 // eliminate the trunc/sext pair. 2971 SDValue Op = N0.getOperand(0); 2972 unsigned OpBits = Op.getValueType().getSizeInBits(); 2973 unsigned MidBits = N0.getValueType().getSizeInBits(); 2974 unsigned DestBits = VT.getSizeInBits(); 2975 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2976 2977 if (OpBits == DestBits) { 2978 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2979 // bits, it is already ready. 2980 if (NumSignBits > DestBits-MidBits) 2981 return Op; 2982 } else if (OpBits < DestBits) { 2983 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2984 // bits, just sext from i32. 2985 if (NumSignBits > OpBits-MidBits) 2986 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 2987 } else { 2988 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2989 // bits, just truncate to i32. 2990 if (NumSignBits > OpBits-MidBits) 2991 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 2992 } 2993 2994 // fold (sext (truncate x)) -> (sextinreg x). 2995 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2996 N0.getValueType())) { 2997 if (Op.getValueType().bitsLT(VT)) 2998 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 2999 else if (Op.getValueType().bitsGT(VT)) 3000 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3001 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3002 DAG.getValueType(N0.getValueType())); 3003 } 3004 } 3005 3006 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3007 if (ISD::isNON_EXTLoad(N0.getNode()) && 3008 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3009 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3010 bool DoXform = true; 3011 SmallVector<SDNode*, 4> SetCCs; 3012 if (!N0.hasOneUse()) 3013 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3014 if (DoXform) { 3015 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3016 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), 3017 VT, LN0->getChain(), 3018 LN0->getBasePtr(), LN0->getSrcValue(), 3019 LN0->getSrcValueOffset(), 3020 N0.getValueType(), 3021 LN0->isVolatile(), LN0->getAlignment()); 3022 CombineTo(N, ExtLoad); 3023 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3024 N0.getValueType(), ExtLoad); 3025 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3026 3027 // Extend SetCC uses if necessary. 3028 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3029 SDNode *SetCC = SetCCs[i]; 3030 SmallVector<SDValue, 4> Ops; 3031 3032 for (unsigned j = 0; j != 2; ++j) { 3033 SDValue SOp = SetCC->getOperand(j); 3034 if (SOp == Trunc) 3035 Ops.push_back(ExtLoad); 3036 else 3037 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3038 VT, SOp)); 3039 } 3040 3041 Ops.push_back(SetCC->getOperand(2)); 3042 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3043 SetCC->getValueType(0), 3044 &Ops[0], Ops.size())); 3045 } 3046 3047 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3048 } 3049 } 3050 3051 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3052 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3053 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3054 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3055 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3056 MVT EVT = LN0->getMemoryVT(); 3057 if ((!LegalOperations && !LN0->isVolatile()) || 3058 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3059 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3060 LN0->getChain(), 3061 LN0->getBasePtr(), LN0->getSrcValue(), 3062 LN0->getSrcValueOffset(), EVT, 3063 LN0->isVolatile(), LN0->getAlignment()); 3064 CombineTo(N, ExtLoad); 3065 CombineTo(N0.getNode(), 3066 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3067 N0.getValueType(), ExtLoad), 3068 ExtLoad.getValue(1)); 3069 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3070 } 3071 } 3072 3073 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3074 if (N0.getOpcode() == ISD::SETCC) { 3075 SDValue SCC = 3076 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3077 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3078 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3079 if (SCC.getNode()) return SCC; 3080 } 3081 3082 // fold (sext x) -> (zext x) if the sign bit is known zero. 3083 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3084 DAG.SignBitIsZero(N0)) 3085 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3086 3087 return SDValue(); 3088} 3089 3090SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3091 SDValue N0 = N->getOperand(0); 3092 MVT VT = N->getValueType(0); 3093 3094 // fold (zext c1) -> c1 3095 if (isa<ConstantSDNode>(N0)) 3096 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3097 // fold (zext (zext x)) -> (zext x) 3098 // fold (zext (aext x)) -> (zext x) 3099 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3100 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3101 N0.getOperand(0)); 3102 3103 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3104 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3105 if (N0.getOpcode() == ISD::TRUNCATE) { 3106 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3107 if (NarrowLoad.getNode()) { 3108 if (NarrowLoad.getNode() != N0.getNode()) 3109 CombineTo(N0.getNode(), NarrowLoad); 3110 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3111 } 3112 } 3113 3114 // fold (zext (truncate x)) -> (and x, mask) 3115 if (N0.getOpcode() == ISD::TRUNCATE && 3116 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3117 SDValue Op = N0.getOperand(0); 3118 if (Op.getValueType().bitsLT(VT)) { 3119 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3120 } else if (Op.getValueType().bitsGT(VT)) { 3121 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3122 } 3123 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3124 } 3125 3126 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3127 // if either of the casts is not free. 3128 if (N0.getOpcode() == ISD::AND && 3129 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3130 N0.getOperand(1).getOpcode() == ISD::Constant && 3131 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3132 N0.getValueType()) || 3133 !TLI.isZExtFree(N0.getValueType(), VT))) { 3134 SDValue X = N0.getOperand(0).getOperand(0); 3135 if (X.getValueType().bitsLT(VT)) { 3136 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3137 } else if (X.getValueType().bitsGT(VT)) { 3138 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3139 } 3140 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3141 Mask.zext(VT.getSizeInBits()); 3142 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3143 X, DAG.getConstant(Mask, VT)); 3144 } 3145 3146 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3147 if (ISD::isNON_EXTLoad(N0.getNode()) && 3148 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3149 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3150 bool DoXform = true; 3151 SmallVector<SDNode*, 4> SetCCs; 3152 if (!N0.hasOneUse()) 3153 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3154 if (DoXform) { 3155 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3156 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3157 LN0->getChain(), 3158 LN0->getBasePtr(), LN0->getSrcValue(), 3159 LN0->getSrcValueOffset(), 3160 N0.getValueType(), 3161 LN0->isVolatile(), LN0->getAlignment()); 3162 CombineTo(N, ExtLoad); 3163 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3164 N0.getValueType(), ExtLoad); 3165 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3166 3167 // Extend SetCC uses if necessary. 3168 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3169 SDNode *SetCC = SetCCs[i]; 3170 SmallVector<SDValue, 4> Ops; 3171 3172 for (unsigned j = 0; j != 2; ++j) { 3173 SDValue SOp = SetCC->getOperand(j); 3174 if (SOp == Trunc) 3175 Ops.push_back(ExtLoad); 3176 else 3177 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3178 N->getDebugLoc(), VT, SOp)); 3179 } 3180 3181 Ops.push_back(SetCC->getOperand(2)); 3182 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3183 SetCC->getValueType(0), 3184 &Ops[0], Ops.size())); 3185 } 3186 3187 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3188 } 3189 } 3190 3191 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3192 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3193 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3194 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3195 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3196 MVT EVT = LN0->getMemoryVT(); 3197 if ((!LegalOperations && !LN0->isVolatile()) || 3198 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3199 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3200 LN0->getChain(), 3201 LN0->getBasePtr(), LN0->getSrcValue(), 3202 LN0->getSrcValueOffset(), EVT, 3203 LN0->isVolatile(), LN0->getAlignment()); 3204 CombineTo(N, ExtLoad); 3205 CombineTo(N0.getNode(), 3206 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3207 ExtLoad), 3208 ExtLoad.getValue(1)); 3209 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3210 } 3211 } 3212 3213 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3214 if (N0.getOpcode() == ISD::SETCC) { 3215 SDValue SCC = 3216 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3217 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3218 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3219 if (SCC.getNode()) return SCC; 3220 } 3221 3222 return SDValue(); 3223} 3224 3225SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3226 SDValue N0 = N->getOperand(0); 3227 MVT VT = N->getValueType(0); 3228 3229 // fold (aext c1) -> c1 3230 if (isa<ConstantSDNode>(N0)) 3231 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3232 // fold (aext (aext x)) -> (aext x) 3233 // fold (aext (zext x)) -> (zext x) 3234 // fold (aext (sext x)) -> (sext x) 3235 if (N0.getOpcode() == ISD::ANY_EXTEND || 3236 N0.getOpcode() == ISD::ZERO_EXTEND || 3237 N0.getOpcode() == ISD::SIGN_EXTEND) 3238 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3239 3240 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3241 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3242 if (N0.getOpcode() == ISD::TRUNCATE) { 3243 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3244 if (NarrowLoad.getNode()) { 3245 if (NarrowLoad.getNode() != N0.getNode()) 3246 CombineTo(N0.getNode(), NarrowLoad); 3247 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3248 } 3249 } 3250 3251 // fold (aext (truncate x)) 3252 if (N0.getOpcode() == ISD::TRUNCATE) { 3253 SDValue TruncOp = N0.getOperand(0); 3254 if (TruncOp.getValueType() == VT) 3255 return TruncOp; // x iff x size == zext size. 3256 if (TruncOp.getValueType().bitsGT(VT)) 3257 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3258 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3259 } 3260 3261 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3262 // if the trunc is not free. 3263 if (N0.getOpcode() == ISD::AND && 3264 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3265 N0.getOperand(1).getOpcode() == ISD::Constant && 3266 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3267 N0.getValueType())) { 3268 SDValue X = N0.getOperand(0).getOperand(0); 3269 if (X.getValueType().bitsLT(VT)) { 3270 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3271 } else if (X.getValueType().bitsGT(VT)) { 3272 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3273 } 3274 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3275 Mask.zext(VT.getSizeInBits()); 3276 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3277 X, DAG.getConstant(Mask, VT)); 3278 } 3279 3280 // fold (aext (load x)) -> (aext (truncate (extload x))) 3281 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3282 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3283 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3284 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3285 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3286 LN0->getChain(), 3287 LN0->getBasePtr(), LN0->getSrcValue(), 3288 LN0->getSrcValueOffset(), 3289 N0.getValueType(), 3290 LN0->isVolatile(), LN0->getAlignment()); 3291 CombineTo(N, ExtLoad); 3292 // Redirect any chain users to the new load. 3293 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3294 SDValue(ExtLoad.getNode(), 1)); 3295 // If any node needs the original loaded value, recompute it. 3296 if (!LN0->use_empty()) 3297 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3298 N0.getValueType(), ExtLoad), 3299 ExtLoad.getValue(1)); 3300 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3301 } 3302 3303 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3304 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3305 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3306 if (N0.getOpcode() == ISD::LOAD && 3307 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3308 N0.hasOneUse()) { 3309 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3310 MVT EVT = LN0->getMemoryVT(); 3311 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3312 VT, LN0->getChain(), LN0->getBasePtr(), 3313 LN0->getSrcValue(), 3314 LN0->getSrcValueOffset(), EVT, 3315 LN0->isVolatile(), LN0->getAlignment()); 3316 CombineTo(N, ExtLoad); 3317 CombineTo(N0.getNode(), 3318 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3319 N0.getValueType(), ExtLoad), 3320 ExtLoad.getValue(1)); 3321 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3322 } 3323 3324 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3325 if (N0.getOpcode() == ISD::SETCC) { 3326 SDValue SCC = 3327 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3328 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3329 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3330 if (SCC.getNode()) 3331 return SCC; 3332 } 3333 3334 return SDValue(); 3335} 3336 3337/// GetDemandedBits - See if the specified operand can be simplified with the 3338/// knowledge that only the bits specified by Mask are used. If so, return the 3339/// simpler operand, otherwise return a null SDValue. 3340SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3341 switch (V.getOpcode()) { 3342 default: break; 3343 case ISD::OR: 3344 case ISD::XOR: 3345 // If the LHS or RHS don't contribute bits to the or, drop them. 3346 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3347 return V.getOperand(1); 3348 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3349 return V.getOperand(0); 3350 break; 3351 case ISD::SRL: 3352 // Only look at single-use SRLs. 3353 if (!V.getNode()->hasOneUse()) 3354 break; 3355 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3356 // See if we can recursively simplify the LHS. 3357 unsigned Amt = RHSC->getZExtValue(); 3358 3359 // Watch out for shift count overflow though. 3360 if (Amt >= Mask.getBitWidth()) break; 3361 APInt NewMask = Mask << Amt; 3362 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3363 if (SimplifyLHS.getNode()) 3364 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3365 SimplifyLHS, V.getOperand(1)); 3366 } 3367 } 3368 return SDValue(); 3369} 3370 3371/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3372/// bits and then truncated to a narrower type and where N is a multiple 3373/// of number of bits of the narrower type, transform it to a narrower load 3374/// from address + N / num of bits of new type. If the result is to be 3375/// extended, also fold the extension to form a extending load. 3376SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3377 unsigned Opc = N->getOpcode(); 3378 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3379 SDValue N0 = N->getOperand(0); 3380 MVT VT = N->getValueType(0); 3381 MVT EVT = VT; 3382 3383 // This transformation isn't valid for vector loads. 3384 if (VT.isVector()) 3385 return SDValue(); 3386 3387 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3388 // extended to VT. 3389 if (Opc == ISD::SIGN_EXTEND_INREG) { 3390 ExtType = ISD::SEXTLOAD; 3391 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3392 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3393 return SDValue(); 3394 } 3395 3396 unsigned EVTBits = EVT.getSizeInBits(); 3397 unsigned ShAmt = 0; 3398 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3399 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3400 ShAmt = N01->getZExtValue(); 3401 // Is the shift amount a multiple of size of VT? 3402 if ((ShAmt & (EVTBits-1)) == 0) { 3403 N0 = N0.getOperand(0); 3404 if (N0.getValueType().getSizeInBits() <= EVTBits) 3405 return SDValue(); 3406 } 3407 } 3408 } 3409 3410 // Do not generate loads of non-round integer types since these can 3411 // be expensive (and would be wrong if the type is not byte sized). 3412 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3413 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3414 // Do not change the width of a volatile load. 3415 !cast<LoadSDNode>(N0)->isVolatile()) { 3416 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3417 MVT PtrType = N0.getOperand(1).getValueType(); 3418 3419 // For big endian targets, we need to adjust the offset to the pointer to 3420 // load the correct bytes. 3421 if (TLI.isBigEndian()) { 3422 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3423 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3424 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3425 } 3426 3427 uint64_t PtrOff = ShAmt / 8; 3428 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3429 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3430 PtrType, LN0->getBasePtr(), 3431 DAG.getConstant(PtrOff, PtrType)); 3432 AddToWorkList(NewPtr.getNode()); 3433 3434 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3435 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3436 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3437 LN0->isVolatile(), NewAlign) 3438 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3439 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3440 EVT, LN0->isVolatile(), NewAlign); 3441 3442 // Replace the old load's chain with the new load's chain. 3443 WorkListRemover DeadNodes(*this); 3444 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3445 &DeadNodes); 3446 3447 // Return the new loaded value. 3448 return Load; 3449 } 3450 3451 return SDValue(); 3452} 3453 3454SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3455 SDValue N0 = N->getOperand(0); 3456 SDValue N1 = N->getOperand(1); 3457 MVT VT = N->getValueType(0); 3458 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3459 unsigned VTBits = VT.getSizeInBits(); 3460 unsigned EVTBits = EVT.getSizeInBits(); 3461 3462 // fold (sext_in_reg c1) -> c1 3463 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3464 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3465 3466 // If the input is already sign extended, just drop the extension. 3467 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3468 return N0; 3469 3470 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3471 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3472 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3473 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3474 N0.getOperand(0), N1); 3475 } 3476 3477 // fold (sext_in_reg (sext x)) -> (sext x) 3478 // fold (sext_in_reg (aext x)) -> (sext x) 3479 // if x is small enough. 3480 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3481 SDValue N00 = N0.getOperand(0); 3482 if (N00.getValueType().getSizeInBits() < EVTBits) 3483 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3484 } 3485 3486 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3487 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3488 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3489 3490 // fold operands of sext_in_reg based on knowledge that the top bits are not 3491 // demanded. 3492 if (SimplifyDemandedBits(SDValue(N, 0))) 3493 return SDValue(N, 0); 3494 3495 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3496 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3497 SDValue NarrowLoad = ReduceLoadWidth(N); 3498 if (NarrowLoad.getNode()) 3499 return NarrowLoad; 3500 3501 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3502 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3503 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3504 if (N0.getOpcode() == ISD::SRL) { 3505 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3506 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3507 // We can turn this into an SRA iff the input to the SRL is already sign 3508 // extended enough. 3509 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3510 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3511 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3512 N0.getOperand(0), N0.getOperand(1)); 3513 } 3514 } 3515 3516 // fold (sext_inreg (extload x)) -> (sextload x) 3517 if (ISD::isEXTLoad(N0.getNode()) && 3518 ISD::isUNINDEXEDLoad(N0.getNode()) && 3519 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3520 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3521 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3522 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3523 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3524 LN0->getChain(), 3525 LN0->getBasePtr(), LN0->getSrcValue(), 3526 LN0->getSrcValueOffset(), EVT, 3527 LN0->isVolatile(), LN0->getAlignment()); 3528 CombineTo(N, ExtLoad); 3529 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3530 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3531 } 3532 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3533 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3534 N0.hasOneUse() && 3535 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3536 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3537 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3538 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3539 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3540 LN0->getChain(), 3541 LN0->getBasePtr(), LN0->getSrcValue(), 3542 LN0->getSrcValueOffset(), EVT, 3543 LN0->isVolatile(), LN0->getAlignment()); 3544 CombineTo(N, ExtLoad); 3545 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3546 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3547 } 3548 return SDValue(); 3549} 3550 3551SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3552 SDValue N0 = N->getOperand(0); 3553 MVT VT = N->getValueType(0); 3554 3555 // noop truncate 3556 if (N0.getValueType() == N->getValueType(0)) 3557 return N0; 3558 // fold (truncate c1) -> c1 3559 if (isa<ConstantSDNode>(N0)) 3560 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3561 // fold (truncate (truncate x)) -> (truncate x) 3562 if (N0.getOpcode() == ISD::TRUNCATE) 3563 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3564 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3565 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3566 N0.getOpcode() == ISD::ANY_EXTEND) { 3567 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3568 // if the source is smaller than the dest, we still need an extend 3569 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3570 N0.getOperand(0)); 3571 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3572 // if the source is larger than the dest, than we just need the truncate 3573 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3574 else 3575 // if the source and dest are the same type, we can drop both the extend 3576 // and the truncate 3577 return N0.getOperand(0); 3578 } 3579 3580 // See if we can simplify the input to this truncate through knowledge that 3581 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3582 // -> trunc y 3583 SDValue Shorter = 3584 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3585 VT.getSizeInBits())); 3586 if (Shorter.getNode()) 3587 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3588 3589 // fold (truncate (load x)) -> (smaller load x) 3590 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3591 return ReduceLoadWidth(N); 3592} 3593 3594static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3595 SDValue Elt = N->getOperand(i); 3596 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3597 return Elt.getNode(); 3598 return Elt.getOperand(Elt.getResNo()).getNode(); 3599} 3600 3601/// CombineConsecutiveLoads - build_pair (load, load) -> load 3602/// if load locations are consecutive. 3603SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3604 assert(N->getOpcode() == ISD::BUILD_PAIR); 3605 3606 SDNode *LD1 = getBuildPairElt(N, 0); 3607 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3608 return SDValue(); 3609 MVT LD1VT = LD1->getValueType(0); 3610 SDNode *LD2 = getBuildPairElt(N, 1); 3611 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3612 3613 if (ISD::isNON_EXTLoad(LD2) && 3614 LD2->hasOneUse() && 3615 // If both are volatile this would reduce the number of volatile loads. 3616 // If one is volatile it might be ok, but play conservative and bail out. 3617 !cast<LoadSDNode>(LD1)->isVolatile() && 3618 !cast<LoadSDNode>(LD2)->isVolatile() && 3619 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3620 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3621 unsigned Align = LD->getAlignment(); 3622 unsigned NewAlign = TLI.getTargetData()-> 3623 getABITypeAlignment(VT.getTypeForMVT()); 3624 3625 if (NewAlign <= Align && 3626 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3627 return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(), 3628 LD->getSrcValue(), LD->getSrcValueOffset(), 3629 false, Align); 3630 } 3631 3632 return SDValue(); 3633} 3634 3635SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3636 SDValue N0 = N->getOperand(0); 3637 MVT VT = N->getValueType(0); 3638 3639 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3640 // Only do this before legalize, since afterward the target may be depending 3641 // on the bitconvert. 3642 // First check to see if this is all constant. 3643 if (!LegalTypes && 3644 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3645 VT.isVector()) { 3646 bool isSimple = true; 3647 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3648 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3649 N0.getOperand(i).getOpcode() != ISD::Constant && 3650 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3651 isSimple = false; 3652 break; 3653 } 3654 3655 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3656 assert(!DestEltVT.isVector() && 3657 "Element type of vector ValueType must not be vector!"); 3658 if (isSimple) 3659 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3660 } 3661 3662 // If the input is a constant, let getNode fold it. 3663 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3664 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3665 if (Res.getNode() != N) return Res; 3666 } 3667 3668 // (conv (conv x, t1), t2) -> (conv x, t2) 3669 if (N0.getOpcode() == ISD::BIT_CONVERT) 3670 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3671 N0.getOperand(0)); 3672 3673 // fold (conv (load x)) -> (load (conv*)x) 3674 // If the resultant load doesn't need a higher alignment than the original! 3675 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3676 // Do not change the width of a volatile load. 3677 !cast<LoadSDNode>(N0)->isVolatile() && 3678 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3679 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3680 unsigned Align = TLI.getTargetData()-> 3681 getABITypeAlignment(VT.getTypeForMVT()); 3682 unsigned OrigAlign = LN0->getAlignment(); 3683 3684 if (Align <= OrigAlign) { 3685 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3686 LN0->getBasePtr(), 3687 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3688 LN0->isVolatile(), OrigAlign); 3689 AddToWorkList(N); 3690 CombineTo(N0.getNode(), 3691 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3692 N0.getValueType(), Load), 3693 Load.getValue(1)); 3694 return Load; 3695 } 3696 } 3697 3698 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3699 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3700 // This often reduces constant pool loads. 3701 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3702 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3703 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3704 N0.getOperand(0)); 3705 AddToWorkList(NewConv.getNode()); 3706 3707 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3708 if (N0.getOpcode() == ISD::FNEG) 3709 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3710 NewConv, DAG.getConstant(SignBit, VT)); 3711 assert(N0.getOpcode() == ISD::FABS); 3712 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3713 NewConv, DAG.getConstant(~SignBit, VT)); 3714 } 3715 3716 // fold (bitconvert (fcopysign cst, x)) -> 3717 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3718 // Note that we don't handle (copysign x, cst) because this can always be 3719 // folded to an fneg or fabs. 3720 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3721 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3722 VT.isInteger() && !VT.isVector()) { 3723 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3724 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3725 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3726 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3727 IntXVT, N0.getOperand(1)); 3728 AddToWorkList(X.getNode()); 3729 3730 // If X has a different width than the result/lhs, sext it or truncate it. 3731 unsigned VTWidth = VT.getSizeInBits(); 3732 if (OrigXWidth < VTWidth) { 3733 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3734 AddToWorkList(X.getNode()); 3735 } else if (OrigXWidth > VTWidth) { 3736 // To get the sign bit in the right place, we have to shift it right 3737 // before truncating. 3738 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3739 X.getValueType(), X, 3740 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3741 AddToWorkList(X.getNode()); 3742 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3743 AddToWorkList(X.getNode()); 3744 } 3745 3746 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3747 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3748 X, DAG.getConstant(SignBit, VT)); 3749 AddToWorkList(X.getNode()); 3750 3751 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3752 VT, N0.getOperand(0)); 3753 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3754 Cst, DAG.getConstant(~SignBit, VT)); 3755 AddToWorkList(Cst.getNode()); 3756 3757 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3758 } 3759 } 3760 3761 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3762 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3763 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3764 if (CombineLD.getNode()) 3765 return CombineLD; 3766 } 3767 3768 return SDValue(); 3769} 3770 3771SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3772 MVT VT = N->getValueType(0); 3773 return CombineConsecutiveLoads(N, VT); 3774} 3775 3776/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3777/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3778/// destination element value type. 3779SDValue DAGCombiner:: 3780ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3781 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3782 3783 // If this is already the right type, we're done. 3784 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3785 3786 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3787 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3788 3789 // If this is a conversion of N elements of one type to N elements of another 3790 // type, convert each element. This handles FP<->INT cases. 3791 if (SrcBitSize == DstBitSize) { 3792 SmallVector<SDValue, 8> Ops; 3793 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3794 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3795 DstEltVT, BV->getOperand(i))); 3796 AddToWorkList(Ops.back().getNode()); 3797 } 3798 MVT VT = MVT::getVectorVT(DstEltVT, 3799 BV->getValueType(0).getVectorNumElements()); 3800 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3801 &Ops[0], Ops.size()); 3802 } 3803 3804 // Otherwise, we're growing or shrinking the elements. To avoid having to 3805 // handle annoying details of growing/shrinking FP values, we convert them to 3806 // int first. 3807 if (SrcEltVT.isFloatingPoint()) { 3808 // Convert the input float vector to a int vector where the elements are the 3809 // same sizes. 3810 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3811 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3812 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3813 SrcEltVT = IntVT; 3814 } 3815 3816 // Now we know the input is an integer vector. If the output is a FP type, 3817 // convert to integer first, then to FP of the right size. 3818 if (DstEltVT.isFloatingPoint()) { 3819 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3820 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3821 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3822 3823 // Next, convert to FP elements of the same size. 3824 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3825 } 3826 3827 // Okay, we know the src/dst types are both integers of differing types. 3828 // Handling growing first. 3829 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3830 if (SrcBitSize < DstBitSize) { 3831 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3832 3833 SmallVector<SDValue, 8> Ops; 3834 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3835 i += NumInputsPerOutput) { 3836 bool isLE = TLI.isLittleEndian(); 3837 APInt NewBits = APInt(DstBitSize, 0); 3838 bool EltIsUndef = true; 3839 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3840 // Shift the previously computed bits over. 3841 NewBits <<= SrcBitSize; 3842 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3843 if (Op.getOpcode() == ISD::UNDEF) continue; 3844 EltIsUndef = false; 3845 3846 NewBits |= 3847 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3848 } 3849 3850 if (EltIsUndef) 3851 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3852 else 3853 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3854 } 3855 3856 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3857 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3858 &Ops[0], Ops.size()); 3859 } 3860 3861 // Finally, this must be the case where we are shrinking elements: each input 3862 // turns into multiple outputs. 3863 bool isS2V = ISD::isScalarToVector(BV); 3864 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3865 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3866 SmallVector<SDValue, 8> Ops; 3867 3868 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3869 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3870 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3871 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3872 continue; 3873 } 3874 3875 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3876 3877 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3878 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3879 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3880 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3881 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3882 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3883 Ops[0]); 3884 OpVal = OpVal.lshr(DstBitSize); 3885 } 3886 3887 // For big endian targets, swap the order of the pieces of each element. 3888 if (TLI.isBigEndian()) 3889 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3890 } 3891 3892 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3893 &Ops[0], Ops.size()); 3894} 3895 3896SDValue DAGCombiner::visitFADD(SDNode *N) { 3897 SDValue N0 = N->getOperand(0); 3898 SDValue N1 = N->getOperand(1); 3899 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3900 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3901 MVT VT = N->getValueType(0); 3902 3903 // fold vector ops 3904 if (VT.isVector()) { 3905 SDValue FoldedVOp = SimplifyVBinOp(N); 3906 if (FoldedVOp.getNode()) return FoldedVOp; 3907 } 3908 3909 // fold (fadd c1, c2) -> (fadd c1, c2) 3910 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3911 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3912 // canonicalize constant to RHS 3913 if (N0CFP && !N1CFP) 3914 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3915 // fold (fadd A, 0) -> A 3916 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3917 return N0; 3918 // fold (fadd A, (fneg B)) -> (fsub A, B) 3919 if (isNegatibleForFree(N1, LegalOperations) == 2) 3920 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3921 GetNegatedExpression(N1, DAG, LegalOperations)); 3922 // fold (fadd (fneg A), B) -> (fsub B, A) 3923 if (isNegatibleForFree(N0, LegalOperations) == 2) 3924 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3925 GetNegatedExpression(N0, DAG, LegalOperations)); 3926 3927 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3928 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3929 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3930 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3931 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3932 N0.getOperand(1), N1)); 3933 3934 return SDValue(); 3935} 3936 3937SDValue DAGCombiner::visitFSUB(SDNode *N) { 3938 SDValue N0 = N->getOperand(0); 3939 SDValue N1 = N->getOperand(1); 3940 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3941 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3942 MVT VT = N->getValueType(0); 3943 3944 // fold vector ops 3945 if (VT.isVector()) { 3946 SDValue FoldedVOp = SimplifyVBinOp(N); 3947 if (FoldedVOp.getNode()) return FoldedVOp; 3948 } 3949 3950 // fold (fsub c1, c2) -> c1-c2 3951 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3952 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 3953 // fold (fsub A, 0) -> A 3954 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3955 return N0; 3956 // fold (fsub 0, B) -> -B 3957 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3958 if (isNegatibleForFree(N1, LegalOperations)) 3959 return GetNegatedExpression(N1, DAG, LegalOperations); 3960 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3961 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 3962 } 3963 // fold (fsub A, (fneg B)) -> (fadd A, B) 3964 if (isNegatibleForFree(N1, LegalOperations)) 3965 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 3966 GetNegatedExpression(N1, DAG, LegalOperations)); 3967 3968 return SDValue(); 3969} 3970 3971SDValue DAGCombiner::visitFMUL(SDNode *N) { 3972 SDValue N0 = N->getOperand(0); 3973 SDValue N1 = N->getOperand(1); 3974 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3975 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3976 MVT VT = N->getValueType(0); 3977 3978 // fold vector ops 3979 if (VT.isVector()) { 3980 SDValue FoldedVOp = SimplifyVBinOp(N); 3981 if (FoldedVOp.getNode()) return FoldedVOp; 3982 } 3983 3984 // fold (fmul c1, c2) -> c1*c2 3985 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3986 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 3987 // canonicalize constant to RHS 3988 if (N0CFP && !N1CFP) 3989 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 3990 // fold (fmul A, 0) -> 0 3991 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3992 return N1; 3993 // fold (fmul X, 2.0) -> (fadd X, X) 3994 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3995 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 3996 // fold (fmul X, (fneg 1.0)) -> (fneg X) 3997 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3998 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3999 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4000 4001 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4002 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4003 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4004 // Both can be negated for free, check to see if at least one is cheaper 4005 // negated. 4006 if (LHSNeg == 2 || RHSNeg == 2) 4007 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4008 GetNegatedExpression(N0, DAG, LegalOperations), 4009 GetNegatedExpression(N1, DAG, LegalOperations)); 4010 } 4011 } 4012 4013 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4014 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4015 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4016 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4017 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4018 N0.getOperand(1), N1)); 4019 4020 return SDValue(); 4021} 4022 4023SDValue DAGCombiner::visitFDIV(SDNode *N) { 4024 SDValue N0 = N->getOperand(0); 4025 SDValue N1 = N->getOperand(1); 4026 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4027 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4028 MVT VT = N->getValueType(0); 4029 4030 // fold vector ops 4031 if (VT.isVector()) { 4032 SDValue FoldedVOp = SimplifyVBinOp(N); 4033 if (FoldedVOp.getNode()) return FoldedVOp; 4034 } 4035 4036 // fold (fdiv c1, c2) -> c1/c2 4037 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4038 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4039 4040 4041 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4042 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4043 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4044 // Both can be negated for free, check to see if at least one is cheaper 4045 // negated. 4046 if (LHSNeg == 2 || RHSNeg == 2) 4047 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4048 GetNegatedExpression(N0, DAG, LegalOperations), 4049 GetNegatedExpression(N1, DAG, LegalOperations)); 4050 } 4051 } 4052 4053 return SDValue(); 4054} 4055 4056SDValue DAGCombiner::visitFREM(SDNode *N) { 4057 SDValue N0 = N->getOperand(0); 4058 SDValue N1 = N->getOperand(1); 4059 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4060 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4061 MVT VT = N->getValueType(0); 4062 4063 // fold (frem c1, c2) -> fmod(c1,c2) 4064 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4065 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4066 4067 return SDValue(); 4068} 4069 4070SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4071 SDValue N0 = N->getOperand(0); 4072 SDValue N1 = N->getOperand(1); 4073 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4074 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4075 MVT VT = N->getValueType(0); 4076 4077 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4078 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4079 4080 if (N1CFP) { 4081 const APFloat& V = N1CFP->getValueAPF(); 4082 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4083 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4084 if (!V.isNegative()) { 4085 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4086 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4087 } else { 4088 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4089 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4090 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4091 } 4092 } 4093 4094 // copysign(fabs(x), y) -> copysign(x, y) 4095 // copysign(fneg(x), y) -> copysign(x, y) 4096 // copysign(copysign(x,z), y) -> copysign(x, y) 4097 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4098 N0.getOpcode() == ISD::FCOPYSIGN) 4099 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4100 N0.getOperand(0), N1); 4101 4102 // copysign(x, abs(y)) -> abs(x) 4103 if (N1.getOpcode() == ISD::FABS) 4104 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4105 4106 // copysign(x, copysign(y,z)) -> copysign(x, z) 4107 if (N1.getOpcode() == ISD::FCOPYSIGN) 4108 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4109 N0, N1.getOperand(1)); 4110 4111 // copysign(x, fp_extend(y)) -> copysign(x, y) 4112 // copysign(x, fp_round(y)) -> copysign(x, y) 4113 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4114 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4115 N0, N1.getOperand(0)); 4116 4117 return SDValue(); 4118} 4119 4120SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4121 SDValue N0 = N->getOperand(0); 4122 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4123 MVT VT = N->getValueType(0); 4124 MVT OpVT = N0.getValueType(); 4125 4126 // fold (sint_to_fp c1) -> c1fp 4127 if (N0C && OpVT != MVT::ppcf128) 4128 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4129 4130 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4131 // but UINT_TO_FP is legal on this target, try to convert. 4132 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4133 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4134 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4135 if (DAG.SignBitIsZero(N0)) 4136 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4137 } 4138 4139 return SDValue(); 4140} 4141 4142SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4143 SDValue N0 = N->getOperand(0); 4144 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4145 MVT VT = N->getValueType(0); 4146 MVT OpVT = N0.getValueType(); 4147 4148 // fold (uint_to_fp c1) -> c1fp 4149 if (N0C && OpVT != MVT::ppcf128) 4150 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4151 4152 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4153 // but SINT_TO_FP is legal on this target, try to convert. 4154 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4155 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4156 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4157 if (DAG.SignBitIsZero(N0)) 4158 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4159 } 4160 4161 return SDValue(); 4162} 4163 4164SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4165 SDValue N0 = N->getOperand(0); 4166 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4167 MVT VT = N->getValueType(0); 4168 4169 // fold (fp_to_sint c1fp) -> c1 4170 if (N0CFP) 4171 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4172 4173 return SDValue(); 4174} 4175 4176SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4177 SDValue N0 = N->getOperand(0); 4178 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4179 MVT VT = N->getValueType(0); 4180 4181 // fold (fp_to_uint c1fp) -> c1 4182 if (N0CFP && VT != MVT::ppcf128) 4183 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4184 4185 return SDValue(); 4186} 4187 4188SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4189 SDValue N0 = N->getOperand(0); 4190 SDValue N1 = N->getOperand(1); 4191 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4192 MVT VT = N->getValueType(0); 4193 4194 // fold (fp_round c1fp) -> c1fp 4195 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4196 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4197 4198 // fold (fp_round (fp_extend x)) -> x 4199 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4200 return N0.getOperand(0); 4201 4202 // fold (fp_round (fp_round x)) -> (fp_round x) 4203 if (N0.getOpcode() == ISD::FP_ROUND) { 4204 // This is a value preserving truncation if both round's are. 4205 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4206 N0.getNode()->getConstantOperandVal(1) == 1; 4207 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4208 DAG.getIntPtrConstant(IsTrunc)); 4209 } 4210 4211 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4212 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4213 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4214 N0.getOperand(0), N1); 4215 AddToWorkList(Tmp.getNode()); 4216 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4217 Tmp, N0.getOperand(1)); 4218 } 4219 4220 return SDValue(); 4221} 4222 4223SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4224 SDValue N0 = N->getOperand(0); 4225 MVT VT = N->getValueType(0); 4226 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4227 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4228 4229 // fold (fp_round_inreg c1fp) -> c1fp 4230 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4231 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4232 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4233 } 4234 4235 return SDValue(); 4236} 4237 4238SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4239 SDValue N0 = N->getOperand(0); 4240 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4241 MVT VT = N->getValueType(0); 4242 4243 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4244 if (N->hasOneUse() && 4245 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4246 return SDValue(); 4247 4248 // fold (fp_extend c1fp) -> c1fp 4249 if (N0CFP && VT != MVT::ppcf128) 4250 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4251 4252 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4253 // value of X. 4254 if (N0.getOpcode() == ISD::FP_ROUND 4255 && N0.getNode()->getConstantOperandVal(1) == 1) { 4256 SDValue In = N0.getOperand(0); 4257 if (In.getValueType() == VT) return In; 4258 if (VT.bitsLT(In.getValueType())) 4259 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4260 In, N0.getOperand(1)); 4261 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4262 } 4263 4264 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4265 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4266 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4267 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4268 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4269 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4270 LN0->getChain(), 4271 LN0->getBasePtr(), LN0->getSrcValue(), 4272 LN0->getSrcValueOffset(), 4273 N0.getValueType(), 4274 LN0->isVolatile(), LN0->getAlignment()); 4275 CombineTo(N, ExtLoad); 4276 CombineTo(N0.getNode(), 4277 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4278 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4279 ExtLoad.getValue(1)); 4280 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4281 } 4282 4283 return SDValue(); 4284} 4285 4286SDValue DAGCombiner::visitFNEG(SDNode *N) { 4287 SDValue N0 = N->getOperand(0); 4288 4289 if (isNegatibleForFree(N0, LegalOperations)) 4290 return GetNegatedExpression(N0, DAG, LegalOperations); 4291 4292 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4293 // constant pool values. 4294 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4295 N0.getOperand(0).getValueType().isInteger() && 4296 !N0.getOperand(0).getValueType().isVector()) { 4297 SDValue Int = N0.getOperand(0); 4298 MVT IntVT = Int.getValueType(); 4299 if (IntVT.isInteger() && !IntVT.isVector()) { 4300 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4301 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4302 AddToWorkList(Int.getNode()); 4303 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4304 N->getValueType(0), Int); 4305 } 4306 } 4307 4308 return SDValue(); 4309} 4310 4311SDValue DAGCombiner::visitFABS(SDNode *N) { 4312 SDValue N0 = N->getOperand(0); 4313 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4314 MVT VT = N->getValueType(0); 4315 4316 // fold (fabs c1) -> fabs(c1) 4317 if (N0CFP && VT != MVT::ppcf128) 4318 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4319 // fold (fabs (fabs x)) -> (fabs x) 4320 if (N0.getOpcode() == ISD::FABS) 4321 return N->getOperand(0); 4322 // fold (fabs (fneg x)) -> (fabs x) 4323 // fold (fabs (fcopysign x, y)) -> (fabs x) 4324 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4325 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4326 4327 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4328 // constant pool values. 4329 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4330 N0.getOperand(0).getValueType().isInteger() && 4331 !N0.getOperand(0).getValueType().isVector()) { 4332 SDValue Int = N0.getOperand(0); 4333 MVT IntVT = Int.getValueType(); 4334 if (IntVT.isInteger() && !IntVT.isVector()) { 4335 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4336 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4337 AddToWorkList(Int.getNode()); 4338 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4339 N->getValueType(0), Int); 4340 } 4341 } 4342 4343 return SDValue(); 4344} 4345 4346SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4347 SDValue Chain = N->getOperand(0); 4348 SDValue N1 = N->getOperand(1); 4349 SDValue N2 = N->getOperand(2); 4350 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4351 4352 // never taken branch, fold to chain 4353 if (N1C && N1C->isNullValue()) 4354 return Chain; 4355 // unconditional branch 4356 if (N1C && N1C->getAPIntValue() == 1) 4357 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4358 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4359 // on the target. 4360 if (N1.getOpcode() == ISD::SETCC && 4361 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4362 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4363 Chain, N1.getOperand(2), 4364 N1.getOperand(0), N1.getOperand(1), N2); 4365 } 4366 4367 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4368 // Match this pattern so that we can generate simpler code: 4369 // 4370 // %a = ... 4371 // %b = and i32 %a, 2 4372 // %c = srl i32 %b, 1 4373 // brcond i32 %c ... 4374 // 4375 // into 4376 // 4377 // %a = ... 4378 // %b = and %a, 2 4379 // %c = setcc eq %b, 0 4380 // brcond %c ... 4381 // 4382 // This applies only when the AND constant value has one bit set and the 4383 // SRL constant is equal to the log2 of the AND constant. The back-end is 4384 // smart enough to convert the result into a TEST/JMP sequence. 4385 SDValue Op0 = N1.getOperand(0); 4386 SDValue Op1 = N1.getOperand(1); 4387 4388 if (Op0.getOpcode() == ISD::AND && 4389 Op0.hasOneUse() && 4390 Op1.getOpcode() == ISD::Constant) { 4391 SDValue AndOp0 = Op0.getOperand(0); 4392 SDValue AndOp1 = Op0.getOperand(1); 4393 4394 if (AndOp1.getOpcode() == ISD::Constant) { 4395 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4396 4397 if (AndConst.isPowerOf2() && 4398 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4399 SDValue SetCC = 4400 DAG.getSetCC(N->getDebugLoc(), 4401 TLI.getSetCCResultType(Op0.getValueType()), 4402 Op0, DAG.getConstant(0, Op0.getValueType()), 4403 ISD::SETNE); 4404 4405 // Replace the uses of SRL with SETCC 4406 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4407 removeFromWorkList(N1.getNode()); 4408 DAG.DeleteNode(N1.getNode()); 4409 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4410 MVT::Other, Chain, SetCC, N2); 4411 } 4412 } 4413 } 4414 } 4415 4416 return SDValue(); 4417} 4418 4419// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4420// 4421SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4422 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4423 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4424 4425 // Use SimplifySetCC to simplify SETCC's. 4426 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4427 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4428 false); 4429 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4430 4431 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4432 4433 // fold br_cc true, dest -> br dest (unconditional branch) 4434 if (SCCC && !SCCC->isNullValue()) 4435 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4436 N->getOperand(0), N->getOperand(4)); 4437 // fold br_cc false, dest -> unconditional fall through 4438 if (SCCC && SCCC->isNullValue()) 4439 return N->getOperand(0); 4440 4441 // fold to a simpler setcc 4442 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4443 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4444 N->getOperand(0), Simp.getOperand(2), 4445 Simp.getOperand(0), Simp.getOperand(1), 4446 N->getOperand(4)); 4447 4448 return SDValue(); 4449} 4450 4451/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4452/// pre-indexed load / store when the base pointer is an add or subtract 4453/// and it has other uses besides the load / store. After the 4454/// transformation, the new indexed load / store has effectively folded 4455/// the add / subtract in and all of its other uses are redirected to the 4456/// new load / store. 4457bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4458 if (!LegalOperations) 4459 return false; 4460 4461 bool isLoad = true; 4462 SDValue Ptr; 4463 MVT VT; 4464 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4465 if (LD->isIndexed()) 4466 return false; 4467 VT = LD->getMemoryVT(); 4468 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4469 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4470 return false; 4471 Ptr = LD->getBasePtr(); 4472 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4473 if (ST->isIndexed()) 4474 return false; 4475 VT = ST->getMemoryVT(); 4476 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4477 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4478 return false; 4479 Ptr = ST->getBasePtr(); 4480 isLoad = false; 4481 } else { 4482 return false; 4483 } 4484 4485 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4486 // out. There is no reason to make this a preinc/predec. 4487 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4488 Ptr.getNode()->hasOneUse()) 4489 return false; 4490 4491 // Ask the target to do addressing mode selection. 4492 SDValue BasePtr; 4493 SDValue Offset; 4494 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4495 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4496 return false; 4497 // Don't create a indexed load / store with zero offset. 4498 if (isa<ConstantSDNode>(Offset) && 4499 cast<ConstantSDNode>(Offset)->isNullValue()) 4500 return false; 4501 4502 // Try turning it into a pre-indexed load / store except when: 4503 // 1) The new base ptr is a frame index. 4504 // 2) If N is a store and the new base ptr is either the same as or is a 4505 // predecessor of the value being stored. 4506 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4507 // that would create a cycle. 4508 // 4) All uses are load / store ops that use it as old base ptr. 4509 4510 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4511 // (plus the implicit offset) to a register to preinc anyway. 4512 if (isa<FrameIndexSDNode>(BasePtr)) 4513 return false; 4514 4515 // Check #2. 4516 if (!isLoad) { 4517 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4518 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4519 return false; 4520 } 4521 4522 // Now check for #3 and #4. 4523 bool RealUse = false; 4524 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4525 E = Ptr.getNode()->use_end(); I != E; ++I) { 4526 SDNode *Use = *I; 4527 if (Use == N) 4528 continue; 4529 if (Use->isPredecessorOf(N)) 4530 return false; 4531 4532 if (!((Use->getOpcode() == ISD::LOAD && 4533 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4534 (Use->getOpcode() == ISD::STORE && 4535 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4536 RealUse = true; 4537 } 4538 4539 if (!RealUse) 4540 return false; 4541 4542 SDValue Result; 4543 if (isLoad) 4544 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4545 BasePtr, Offset, AM); 4546 else 4547 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4548 BasePtr, Offset, AM); 4549 ++PreIndexedNodes; 4550 ++NodesCombined; 4551 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4552 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4553 DOUT << '\n'; 4554 WorkListRemover DeadNodes(*this); 4555 if (isLoad) { 4556 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4557 &DeadNodes); 4558 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4559 &DeadNodes); 4560 } else { 4561 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4562 &DeadNodes); 4563 } 4564 4565 // Finally, since the node is now dead, remove it from the graph. 4566 DAG.DeleteNode(N); 4567 4568 // Replace the uses of Ptr with uses of the updated base value. 4569 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4570 &DeadNodes); 4571 removeFromWorkList(Ptr.getNode()); 4572 DAG.DeleteNode(Ptr.getNode()); 4573 4574 return true; 4575} 4576 4577/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4578/// add / sub of the base pointer node into a post-indexed load / store. 4579/// The transformation folded the add / subtract into the new indexed 4580/// load / store effectively and all of its uses are redirected to the 4581/// new load / store. 4582bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4583 if (!LegalOperations) 4584 return false; 4585 4586 bool isLoad = true; 4587 SDValue Ptr; 4588 MVT VT; 4589 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4590 if (LD->isIndexed()) 4591 return false; 4592 VT = LD->getMemoryVT(); 4593 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4594 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4595 return false; 4596 Ptr = LD->getBasePtr(); 4597 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4598 if (ST->isIndexed()) 4599 return false; 4600 VT = ST->getMemoryVT(); 4601 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4602 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4603 return false; 4604 Ptr = ST->getBasePtr(); 4605 isLoad = false; 4606 } else { 4607 return false; 4608 } 4609 4610 if (Ptr.getNode()->hasOneUse()) 4611 return false; 4612 4613 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4614 E = Ptr.getNode()->use_end(); I != E; ++I) { 4615 SDNode *Op = *I; 4616 if (Op == N || 4617 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4618 continue; 4619 4620 SDValue BasePtr; 4621 SDValue Offset; 4622 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4623 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4624 if (Ptr == Offset) 4625 std::swap(BasePtr, Offset); 4626 if (Ptr != BasePtr) 4627 continue; 4628 // Don't create a indexed load / store with zero offset. 4629 if (isa<ConstantSDNode>(Offset) && 4630 cast<ConstantSDNode>(Offset)->isNullValue()) 4631 continue; 4632 4633 // Try turning it into a post-indexed load / store except when 4634 // 1) All uses are load / store ops that use it as base ptr. 4635 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4636 // nor a successor of N. Otherwise, if Op is folded that would 4637 // create a cycle. 4638 4639 // Check for #1. 4640 bool TryNext = false; 4641 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4642 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4643 SDNode *Use = *II; 4644 if (Use == Ptr.getNode()) 4645 continue; 4646 4647 // If all the uses are load / store addresses, then don't do the 4648 // transformation. 4649 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4650 bool RealUse = false; 4651 for (SDNode::use_iterator III = Use->use_begin(), 4652 EEE = Use->use_end(); III != EEE; ++III) { 4653 SDNode *UseUse = *III; 4654 if (!((UseUse->getOpcode() == ISD::LOAD && 4655 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4656 (UseUse->getOpcode() == ISD::STORE && 4657 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4658 RealUse = true; 4659 } 4660 4661 if (!RealUse) { 4662 TryNext = true; 4663 break; 4664 } 4665 } 4666 } 4667 4668 if (TryNext) 4669 continue; 4670 4671 // Check for #2 4672 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4673 SDValue Result = isLoad 4674 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4675 BasePtr, Offset, AM) 4676 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4677 BasePtr, Offset, AM); 4678 ++PostIndexedNodes; 4679 ++NodesCombined; 4680 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4681 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4682 DOUT << '\n'; 4683 WorkListRemover DeadNodes(*this); 4684 if (isLoad) { 4685 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4686 &DeadNodes); 4687 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4688 &DeadNodes); 4689 } else { 4690 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4691 &DeadNodes); 4692 } 4693 4694 // Finally, since the node is now dead, remove it from the graph. 4695 DAG.DeleteNode(N); 4696 4697 // Replace the uses of Use with uses of the updated base value. 4698 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4699 Result.getValue(isLoad ? 1 : 0), 4700 &DeadNodes); 4701 removeFromWorkList(Op); 4702 DAG.DeleteNode(Op); 4703 return true; 4704 } 4705 } 4706 } 4707 4708 return false; 4709} 4710 4711/// InferAlignment - If we can infer some alignment information from this 4712/// pointer, return it. 4713static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4714 // If this is a direct reference to a stack slot, use information about the 4715 // stack slot's alignment. 4716 int FrameIdx = 1 << 31; 4717 int64_t FrameOffset = 0; 4718 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4719 FrameIdx = FI->getIndex(); 4720 } else if (Ptr.getOpcode() == ISD::ADD && 4721 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4722 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4723 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4724 FrameOffset = Ptr.getConstantOperandVal(1); 4725 } 4726 4727 if (FrameIdx != (1 << 31)) { 4728 // FIXME: Handle FI+CST. 4729 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4730 if (MFI.isFixedObjectIndex(FrameIdx)) { 4731 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4732 4733 // The alignment of the frame index can be determined from its offset from 4734 // the incoming frame position. If the frame object is at offset 32 and 4735 // the stack is guaranteed to be 16-byte aligned, then we know that the 4736 // object is 16-byte aligned. 4737 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4738 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4739 4740 // Finally, the frame object itself may have a known alignment. Factor 4741 // the alignment + offset into a new alignment. For example, if we know 4742 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4743 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4744 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4745 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4746 FrameOffset); 4747 return std::max(Align, FIInfoAlign); 4748 } 4749 } 4750 4751 return 0; 4752} 4753 4754SDValue DAGCombiner::visitLOAD(SDNode *N) { 4755 LoadSDNode *LD = cast<LoadSDNode>(N); 4756 SDValue Chain = LD->getChain(); 4757 SDValue Ptr = LD->getBasePtr(); 4758 4759 // Try to infer better alignment information than the load already has. 4760 if (!Fast && LD->isUnindexed()) { 4761 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4762 if (Align > LD->getAlignment()) 4763 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4764 LD->getValueType(0), 4765 Chain, Ptr, LD->getSrcValue(), 4766 LD->getSrcValueOffset(), LD->getMemoryVT(), 4767 LD->isVolatile(), Align); 4768 } 4769 } 4770 4771 // If load is not volatile and there are no uses of the loaded value (and 4772 // the updated indexed value in case of indexed loads), change uses of the 4773 // chain value into uses of the chain input (i.e. delete the dead load). 4774 if (!LD->isVolatile()) { 4775 if (N->getValueType(1) == MVT::Other) { 4776 // Unindexed loads. 4777 if (N->hasNUsesOfValue(0, 0)) { 4778 // It's not safe to use the two value CombineTo variant here. e.g. 4779 // v1, chain2 = load chain1, loc 4780 // v2, chain3 = load chain2, loc 4781 // v3 = add v2, c 4782 // Now we replace use of chain2 with chain1. This makes the second load 4783 // isomorphic to the one we are deleting, and thus makes this load live. 4784 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4785 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4786 DOUT << "\n"; 4787 WorkListRemover DeadNodes(*this); 4788 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4789 4790 if (N->use_empty()) { 4791 removeFromWorkList(N); 4792 DAG.DeleteNode(N); 4793 } 4794 4795 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4796 } 4797 } else { 4798 // Indexed loads. 4799 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4800 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4801 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4802 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4803 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4804 DOUT << " and 2 other values\n"; 4805 WorkListRemover DeadNodes(*this); 4806 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4807 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4808 DAG.getUNDEF(N->getValueType(1)), 4809 &DeadNodes); 4810 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4811 removeFromWorkList(N); 4812 DAG.DeleteNode(N); 4813 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4814 } 4815 } 4816 } 4817 4818 // If this load is directly stored, replace the load value with the stored 4819 // value. 4820 // TODO: Handle store large -> read small portion. 4821 // TODO: Handle TRUNCSTORE/LOADEXT 4822 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4823 !LD->isVolatile()) { 4824 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4825 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4826 if (PrevST->getBasePtr() == Ptr && 4827 PrevST->getValue().getValueType() == N->getValueType(0)) 4828 return CombineTo(N, Chain.getOperand(1), Chain); 4829 } 4830 } 4831 4832 if (CombinerAA) { 4833 // Walk up chain skipping non-aliasing memory nodes. 4834 SDValue BetterChain = FindBetterChain(N, Chain); 4835 4836 // If there is a better chain. 4837 if (Chain != BetterChain) { 4838 SDValue ReplLoad; 4839 4840 // Replace the chain to void dependency. 4841 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4842 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4843 BetterChain, Ptr, 4844 LD->getSrcValue(), LD->getSrcValueOffset(), 4845 LD->isVolatile(), LD->getAlignment()); 4846 } else { 4847 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4848 LD->getValueType(0), 4849 BetterChain, Ptr, LD->getSrcValue(), 4850 LD->getSrcValueOffset(), 4851 LD->getMemoryVT(), 4852 LD->isVolatile(), 4853 LD->getAlignment()); 4854 } 4855 4856 // Create token factor to keep old chain connected. 4857 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4858 MVT::Other, Chain, ReplLoad.getValue(1)); 4859 4860 // Replace uses with load result and token factor. Don't add users 4861 // to work list. 4862 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4863 } 4864 } 4865 4866 // Try transforming N to an indexed load. 4867 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4868 return SDValue(N, 0); 4869 4870 return SDValue(); 4871} 4872 4873SDValue DAGCombiner::visitSTORE(SDNode *N) { 4874 StoreSDNode *ST = cast<StoreSDNode>(N); 4875 SDValue Chain = ST->getChain(); 4876 SDValue Value = ST->getValue(); 4877 SDValue Ptr = ST->getBasePtr(); 4878 4879 // Try to infer better alignment information than the store already has. 4880 if (!Fast && ST->isUnindexed()) { 4881 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4882 if (Align > ST->getAlignment()) 4883 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 4884 Ptr, ST->getSrcValue(), 4885 ST->getSrcValueOffset(), ST->getMemoryVT(), 4886 ST->isVolatile(), Align); 4887 } 4888 } 4889 4890 // If this is a store of a bit convert, store the input value if the 4891 // resultant store does not need a higher alignment than the original. 4892 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4893 ST->isUnindexed()) { 4894 unsigned OrigAlign = ST->getAlignment(); 4895 MVT SVT = Value.getOperand(0).getValueType(); 4896 unsigned Align = TLI.getTargetData()-> 4897 getABITypeAlignment(SVT.getTypeForMVT()); 4898 if (Align <= OrigAlign && 4899 ((!LegalOperations && !ST->isVolatile()) || 4900 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 4901 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 4902 Ptr, ST->getSrcValue(), 4903 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4904 } 4905 4906 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4907 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4908 // NOTE: If the original store is volatile, this transform must not increase 4909 // the number of stores. For example, on x86-32 an f64 can be stored in one 4910 // processor operation but an i64 (which is not legal) requires two. So the 4911 // transform should not be done in this case. 4912 if (Value.getOpcode() != ISD::TargetConstantFP) { 4913 SDValue Tmp; 4914 switch (CFP->getValueType(0).getSimpleVT()) { 4915 default: assert(0 && "Unknown FP type"); 4916 case MVT::f80: // We don't do this for these yet. 4917 case MVT::f128: 4918 case MVT::ppcf128: 4919 break; 4920 case MVT::f32: 4921 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 4922 !ST->isVolatile()) || 4923 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4924 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4925 bitcastToAPInt().getZExtValue(), MVT::i32); 4926 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 4927 Ptr, ST->getSrcValue(), 4928 ST->getSrcValueOffset(), ST->isVolatile(), 4929 ST->getAlignment()); 4930 } 4931 break; 4932 case MVT::f64: 4933 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 4934 !ST->isVolatile()) || 4935 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 4936 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4937 getZExtValue(), MVT::i64); 4938 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 4939 Ptr, ST->getSrcValue(), 4940 ST->getSrcValueOffset(), ST->isVolatile(), 4941 ST->getAlignment()); 4942 } else if (!ST->isVolatile() && 4943 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4944 // Many FP stores are not made apparent until after legalize, e.g. for 4945 // argument passing. Since this is so common, custom legalize the 4946 // 64-bit integer store into two 32-bit stores. 4947 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4948 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4949 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4950 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4951 4952 int SVOffset = ST->getSrcValueOffset(); 4953 unsigned Alignment = ST->getAlignment(); 4954 bool isVolatile = ST->isVolatile(); 4955 4956 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 4957 Ptr, ST->getSrcValue(), 4958 ST->getSrcValueOffset(), 4959 isVolatile, ST->getAlignment()); 4960 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 4961 DAG.getConstant(4, Ptr.getValueType())); 4962 SVOffset += 4; 4963 Alignment = MinAlign(Alignment, 4U); 4964 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 4965 Ptr, ST->getSrcValue(), 4966 SVOffset, isVolatile, Alignment); 4967 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 4968 St0, St1); 4969 } 4970 4971 break; 4972 } 4973 } 4974 } 4975 4976 if (CombinerAA) { 4977 // Walk up chain skipping non-aliasing memory nodes. 4978 SDValue BetterChain = FindBetterChain(N, Chain); 4979 4980 // If there is a better chain. 4981 if (Chain != BetterChain) { 4982 // Replace the chain to avoid dependency. 4983 SDValue ReplStore; 4984 if (ST->isTruncatingStore()) { 4985 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 4986 ST->getSrcValue(),ST->getSrcValueOffset(), 4987 ST->getMemoryVT(), 4988 ST->isVolatile(), ST->getAlignment()); 4989 } else { 4990 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 4991 ST->getSrcValue(), ST->getSrcValueOffset(), 4992 ST->isVolatile(), ST->getAlignment()); 4993 } 4994 4995 // Create token to keep both nodes around. 4996 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4997 MVT::Other, Chain, ReplStore); 4998 4999 // Don't add users to work list. 5000 return CombineTo(N, Token, false); 5001 } 5002 } 5003 5004 // Try transforming N to an indexed store. 5005 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5006 return SDValue(N, 0); 5007 5008 // FIXME: is there such a thing as a truncating indexed store? 5009 if (ST->isTruncatingStore() && ST->isUnindexed() && 5010 Value.getValueType().isInteger()) { 5011 // See if we can simplify the input to this truncstore with knowledge that 5012 // only the low bits are being used. For example: 5013 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5014 SDValue Shorter = 5015 GetDemandedBits(Value, 5016 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5017 ST->getMemoryVT().getSizeInBits())); 5018 AddToWorkList(Value.getNode()); 5019 if (Shorter.getNode()) 5020 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5021 Ptr, ST->getSrcValue(), 5022 ST->getSrcValueOffset(), ST->getMemoryVT(), 5023 ST->isVolatile(), ST->getAlignment()); 5024 5025 // Otherwise, see if we can simplify the operation with 5026 // SimplifyDemandedBits, which only works if the value has a single use. 5027 if (SimplifyDemandedBits(Value, 5028 APInt::getLowBitsSet( 5029 Value.getValueSizeInBits(), 5030 ST->getMemoryVT().getSizeInBits()))) 5031 return SDValue(N, 0); 5032 } 5033 5034 // If this is a load followed by a store to the same location, then the store 5035 // is dead/noop. 5036 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5037 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5038 ST->isUnindexed() && !ST->isVolatile() && 5039 // There can't be any side effects between the load and store, such as 5040 // a call or store. 5041 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5042 // The store is dead, remove it. 5043 return Chain; 5044 } 5045 } 5046 5047 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5048 // truncating store. We can do this even if this is already a truncstore. 5049 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5050 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5051 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5052 ST->getMemoryVT())) { 5053 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5054 Ptr, ST->getSrcValue(), 5055 ST->getSrcValueOffset(), ST->getMemoryVT(), 5056 ST->isVolatile(), ST->getAlignment()); 5057 } 5058 5059 return SDValue(); 5060} 5061 5062SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5063 SDValue InVec = N->getOperand(0); 5064 SDValue InVal = N->getOperand(1); 5065 SDValue EltNo = N->getOperand(2); 5066 5067 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5068 // vector with the inserted element. 5069 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5070 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5071 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5072 InVec.getNode()->op_end()); 5073 if (Elt < Ops.size()) 5074 Ops[Elt] = InVal; 5075 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5076 InVec.getValueType(), &Ops[0], Ops.size()); 5077 } 5078 5079 return SDValue(); 5080} 5081 5082SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5083 // (vextract (scalar_to_vector val, 0) -> val 5084 SDValue InVec = N->getOperand(0); 5085 5086 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) 5087 return InVec.getOperand(0); 5088 5089 // Perform only after legalization to ensure build_vector / vector_shuffle 5090 // optimizations have already been done. 5091 if (!LegalOperations) return SDValue(); 5092 5093 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5094 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5095 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5096 SDValue EltNo = N->getOperand(1); 5097 5098 if (isa<ConstantSDNode>(EltNo)) { 5099 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5100 bool NewLoad = false; 5101 bool BCNumEltsChanged = false; 5102 MVT VT = InVec.getValueType(); 5103 MVT EVT = VT.getVectorElementType(); 5104 MVT LVT = EVT; 5105 5106 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5107 MVT BCVT = InVec.getOperand(0).getValueType(); 5108 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5109 return SDValue(); 5110 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5111 BCNumEltsChanged = true; 5112 InVec = InVec.getOperand(0); 5113 EVT = BCVT.getVectorElementType(); 5114 NewLoad = true; 5115 } 5116 5117 LoadSDNode *LN0 = NULL; 5118 if (ISD::isNormalLoad(InVec.getNode())) { 5119 LN0 = cast<LoadSDNode>(InVec); 5120 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5121 InVec.getOperand(0).getValueType() == EVT && 5122 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5123 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5124 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 5125 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5126 // => 5127 // (load $addr+1*size) 5128 5129 // If the bit convert changed the number of elements, it is unsafe 5130 // to examine the mask. 5131 if (BCNumEltsChanged) 5132 return SDValue(); 5133 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 5134 getOperand(Elt))->getZExtValue(); 5135 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 5136 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5137 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5138 InVec = InVec.getOperand(0); 5139 if (ISD::isNormalLoad(InVec.getNode())) { 5140 LN0 = cast<LoadSDNode>(InVec); 5141 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 5142 } 5143 } 5144 5145 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5146 return SDValue(); 5147 5148 unsigned Align = LN0->getAlignment(); 5149 if (NewLoad) { 5150 // Check the resultant load doesn't need a higher alignment than the 5151 // original load. 5152 unsigned NewAlign = 5153 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); 5154 5155 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5156 return SDValue(); 5157 5158 Align = NewAlign; 5159 } 5160 5161 SDValue NewPtr = LN0->getBasePtr(); 5162 if (Elt) { 5163 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5164 MVT PtrType = NewPtr.getValueType(); 5165 if (TLI.isBigEndian()) 5166 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5167 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5168 DAG.getConstant(PtrOff, PtrType)); 5169 } 5170 5171 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5172 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5173 LN0->isVolatile(), Align); 5174 } 5175 5176 return SDValue(); 5177} 5178 5179SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5180 unsigned NumInScalars = N->getNumOperands(); 5181 MVT VT = N->getValueType(0); 5182 unsigned NumElts = VT.getVectorNumElements(); 5183 MVT EltType = VT.getVectorElementType(); 5184 5185 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5186 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5187 // at most two distinct vectors, turn this into a shuffle node. 5188 SDValue VecIn1, VecIn2; 5189 for (unsigned i = 0; i != NumInScalars; ++i) { 5190 // Ignore undef inputs. 5191 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5192 5193 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5194 // constant index, bail out. 5195 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5196 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5197 VecIn1 = VecIn2 = SDValue(0, 0); 5198 break; 5199 } 5200 5201 // If the input vector type disagrees with the result of the build_vector, 5202 // we can't make a shuffle. 5203 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5204 if (ExtractedFromVec.getValueType() != VT) { 5205 VecIn1 = VecIn2 = SDValue(0, 0); 5206 break; 5207 } 5208 5209 // Otherwise, remember this. We allow up to two distinct input vectors. 5210 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5211 continue; 5212 5213 if (VecIn1.getNode() == 0) { 5214 VecIn1 = ExtractedFromVec; 5215 } else if (VecIn2.getNode() == 0) { 5216 VecIn2 = ExtractedFromVec; 5217 } else { 5218 // Too many inputs. 5219 VecIn1 = VecIn2 = SDValue(0, 0); 5220 break; 5221 } 5222 } 5223 5224 // If everything is good, we can make a shuffle operation. 5225 MVT IndexVT = MVT::i32; 5226 if (VecIn1.getNode()) { 5227 SmallVector<SDValue, 8> BuildVecIndices; 5228 for (unsigned i = 0; i != NumInScalars; ++i) { 5229 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5230 BuildVecIndices.push_back(DAG.getUNDEF(IndexVT)); 5231 continue; 5232 } 5233 5234 SDValue Extract = N->getOperand(i); 5235 5236 // If extracting from the first vector, just use the index directly. 5237 SDValue ExtVal = Extract.getOperand(1); 5238 if (Extract.getOperand(0) == VecIn1) { 5239 if (ExtVal.getValueType() == IndexVT) 5240 BuildVecIndices.push_back(ExtVal); 5241 else { 5242 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5243 BuildVecIndices.push_back(DAG.getConstant(Idx, IndexVT)); 5244 } 5245 continue; 5246 } 5247 5248 // Otherwise, use InIdx + VecSize 5249 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5250 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, IndexVT)); 5251 } 5252 5253 // Add count and size info. 5254 MVT BuildVecVT = MVT::getVectorVT(IndexVT, NumElts); 5255 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes) 5256 return SDValue(); 5257 5258 // Return the new VECTOR_SHUFFLE node. 5259 SDValue Ops[5]; 5260 Ops[0] = VecIn1; 5261 if (VecIn2.getNode()) { 5262 Ops[1] = VecIn2; 5263 } else { 5264 // Use an undef build_vector as input for the second operand. 5265 std::vector<SDValue> UnOps(NumInScalars, 5266 DAG.getUNDEF(EltType)); 5267 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5268 &UnOps[0], UnOps.size()); 5269 AddToWorkList(Ops[1].getNode()); 5270 } 5271 5272 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), BuildVecVT, 5273 &BuildVecIndices[0], BuildVecIndices.size()); 5274 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3); 5275 } 5276 5277 return SDValue(); 5278} 5279 5280SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5281 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5282 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5283 // inputs come from at most two distinct vectors, turn this into a shuffle 5284 // node. 5285 5286 // If we only have one input vector, we don't need to do any concatenation. 5287 if (N->getNumOperands() == 1) 5288 return N->getOperand(0); 5289 5290 return SDValue(); 5291} 5292 5293SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5294 SDValue ShufMask = N->getOperand(2); 5295 unsigned NumElts = ShufMask.getNumOperands(); 5296 5297 SDValue N0 = N->getOperand(0); 5298 SDValue N1 = N->getOperand(1); 5299 5300 assert(N0.getValueType().getVectorNumElements() == NumElts && 5301 "Vector shuffle must be normalized in DAG"); 5302 5303 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5304 bool isIdentity = true; 5305 for (unsigned i = 0; i != NumElts; ++i) { 5306 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5307 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5308 isIdentity = false; 5309 break; 5310 } 5311 } 5312 if (isIdentity) return N->getOperand(0); 5313 5314 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5315 isIdentity = true; 5316 for (unsigned i = 0; i != NumElts; ++i) { 5317 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5318 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5319 i+NumElts) { 5320 isIdentity = false; 5321 break; 5322 } 5323 } 5324 if (isIdentity) return N->getOperand(1); 5325 5326 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5327 // needed at all. 5328 bool isUnary = true; 5329 bool isSplat = true; 5330 int VecNum = -1; 5331 unsigned BaseIdx = 0; 5332 for (unsigned i = 0; i != NumElts; ++i) 5333 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5334 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5335 int V = (Idx < NumElts) ? 0 : 1; 5336 if (VecNum == -1) { 5337 VecNum = V; 5338 BaseIdx = Idx; 5339 } else { 5340 if (BaseIdx != Idx) 5341 isSplat = false; 5342 if (VecNum != V) { 5343 isUnary = false; 5344 break; 5345 } 5346 } 5347 } 5348 5349 // Normalize unary shuffle so the RHS is undef. 5350 if (isUnary && VecNum == 1) 5351 std::swap(N0, N1); 5352 5353 // If it is a splat, check if the argument vector is a build_vector with 5354 // all scalar elements the same. 5355 if (isSplat) { 5356 SDNode *V = N0.getNode(); 5357 5358 // If this is a bit convert that changes the element type of the vector but 5359 // not the number of vector elements, look through it. Be careful not to 5360 // look though conversions that change things like v4f32 to v2f64. 5361 if (V->getOpcode() == ISD::BIT_CONVERT) { 5362 SDValue ConvInput = V->getOperand(0); 5363 if (ConvInput.getValueType().isVector() && 5364 ConvInput.getValueType().getVectorNumElements() == NumElts) 5365 V = ConvInput.getNode(); 5366 } 5367 5368 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5369 unsigned NumElems = V->getNumOperands(); 5370 if (NumElems > BaseIdx) { 5371 SDValue Base; 5372 bool AllSame = true; 5373 for (unsigned i = 0; i != NumElems; ++i) { 5374 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5375 Base = V->getOperand(i); 5376 break; 5377 } 5378 } 5379 // Splat of <u, u, u, u>, return <u, u, u, u> 5380 if (!Base.getNode()) 5381 return N0; 5382 for (unsigned i = 0; i != NumElems; ++i) { 5383 if (V->getOperand(i) != Base) { 5384 AllSame = false; 5385 break; 5386 } 5387 } 5388 // Splat of <x, x, x, x>, return <x, x, x, x> 5389 if (AllSame) 5390 return N0; 5391 } 5392 } 5393 } 5394 5395 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5396 // into an undef. 5397 if (isUnary || N0 == N1) { 5398 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5399 // first operand. 5400 SmallVector<SDValue, 8> MappedOps; 5401 5402 for (unsigned i = 0; i != NumElts; ++i) { 5403 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5404 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5405 NumElts) { 5406 MappedOps.push_back(ShufMask.getOperand(i)); 5407 } else { 5408 unsigned NewIdx = 5409 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5410 NumElts; 5411 MappedOps.push_back(DAG.getConstant(NewIdx, 5412 ShufMask.getOperand(i).getValueType())); 5413 } 5414 } 5415 5416 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5417 ShufMask.getValueType(), 5418 &MappedOps[0], MappedOps.size()); 5419 AddToWorkList(ShufMask.getNode()); 5420 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), 5421 N->getValueType(0), N0, 5422 DAG.getUNDEF(N->getValueType(0)), 5423 ShufMask); 5424 } 5425 5426 return SDValue(); 5427} 5428 5429/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5430/// an AND to a vector_shuffle with the destination vector and a zero vector. 5431/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5432/// vector_shuffle V, Zero, <0, 4, 2, 4> 5433SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5434 SDValue LHS = N->getOperand(0); 5435 SDValue RHS = N->getOperand(1); 5436 if (N->getOpcode() == ISD::AND) { 5437 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5438 RHS = RHS.getOperand(0); 5439 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5440 std::vector<SDValue> IdxOps; 5441 unsigned NumOps = RHS.getNumOperands(); 5442 unsigned NumElts = NumOps; 5443 for (unsigned i = 0; i != NumElts; ++i) { 5444 SDValue Elt = RHS.getOperand(i); 5445 if (!isa<ConstantSDNode>(Elt)) 5446 return SDValue(); 5447 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5448 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5449 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5450 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5451 else 5452 return SDValue(); 5453 } 5454 5455 // Let's see if the target supports this vector_shuffle. 5456 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5457 return SDValue(); 5458 5459 // Return the new VECTOR_SHUFFLE node. 5460 MVT EVT = RHS.getValueType().getVectorElementType(); 5461 MVT VT = MVT::getVectorVT(EVT, NumElts); 5462 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5463 std::vector<SDValue> Ops; 5464 LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS); 5465 Ops.push_back(LHS); 5466 AddToWorkList(LHS.getNode()); 5467 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5468 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5469 VT, &ZeroOps[0], ZeroOps.size())); 5470 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5471 MaskVT, &IdxOps[0], IdxOps.size())); 5472 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), 5473 VT, &Ops[0], Ops.size()); 5474 5475 if (VT != N->getValueType(0)) 5476 Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5477 N->getValueType(0), Result); 5478 5479 return Result; 5480 } 5481 } 5482 5483 return SDValue(); 5484} 5485 5486/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5487SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5488 // After legalize, the target may be depending on adds and other 5489 // binary ops to provide legal ways to construct constants or other 5490 // things. Simplifying them may result in a loss of legality. 5491 if (LegalOperations) return SDValue(); 5492 5493 MVT VT = N->getValueType(0); 5494 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5495 5496 MVT EltType = VT.getVectorElementType(); 5497 SDValue LHS = N->getOperand(0); 5498 SDValue RHS = N->getOperand(1); 5499 SDValue Shuffle = XformToShuffleWithZero(N); 5500 if (Shuffle.getNode()) return Shuffle; 5501 5502 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5503 // this operation. 5504 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5505 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5506 SmallVector<SDValue, 8> Ops; 5507 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5508 SDValue LHSOp = LHS.getOperand(i); 5509 SDValue RHSOp = RHS.getOperand(i); 5510 // If these two elements can't be folded, bail out. 5511 if ((LHSOp.getOpcode() != ISD::UNDEF && 5512 LHSOp.getOpcode() != ISD::Constant && 5513 LHSOp.getOpcode() != ISD::ConstantFP) || 5514 (RHSOp.getOpcode() != ISD::UNDEF && 5515 RHSOp.getOpcode() != ISD::Constant && 5516 RHSOp.getOpcode() != ISD::ConstantFP)) 5517 break; 5518 5519 // Can't fold divide by zero. 5520 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5521 N->getOpcode() == ISD::FDIV) { 5522 if ((RHSOp.getOpcode() == ISD::Constant && 5523 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5524 (RHSOp.getOpcode() == ISD::ConstantFP && 5525 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5526 break; 5527 } 5528 5529 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5530 EltType, LHSOp, RHSOp)); 5531 AddToWorkList(Ops.back().getNode()); 5532 assert((Ops.back().getOpcode() == ISD::UNDEF || 5533 Ops.back().getOpcode() == ISD::Constant || 5534 Ops.back().getOpcode() == ISD::ConstantFP) && 5535 "Scalar binop didn't fold!"); 5536 } 5537 5538 if (Ops.size() == LHS.getNumOperands()) { 5539 MVT VT = LHS.getValueType(); 5540 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5541 &Ops[0], Ops.size()); 5542 } 5543 } 5544 5545 return SDValue(); 5546} 5547 5548SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5549 SDValue N1, SDValue N2){ 5550 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5551 5552 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5553 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5554 5555 // If we got a simplified select_cc node back from SimplifySelectCC, then 5556 // break it down into a new SETCC node, and a new SELECT node, and then return 5557 // the SELECT node, since we were called with a SELECT node. 5558 if (SCC.getNode()) { 5559 // Check to see if we got a select_cc back (to turn into setcc/select). 5560 // Otherwise, just return whatever node we got back, like fabs. 5561 if (SCC.getOpcode() == ISD::SELECT_CC) { 5562 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5563 N0.getValueType(), 5564 SCC.getOperand(0), SCC.getOperand(1), 5565 SCC.getOperand(4)); 5566 AddToWorkList(SETCC.getNode()); 5567 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5568 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5569 } 5570 5571 return SCC; 5572 } 5573 return SDValue(); 5574} 5575 5576/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5577/// are the two values being selected between, see if we can simplify the 5578/// select. Callers of this should assume that TheSelect is deleted if this 5579/// returns true. As such, they should return the appropriate thing (e.g. the 5580/// node) back to the top-level of the DAG combiner loop to avoid it being 5581/// looked at. 5582bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5583 SDValue RHS) { 5584 5585 // If this is a select from two identical things, try to pull the operation 5586 // through the select. 5587 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5588 // If this is a load and the token chain is identical, replace the select 5589 // of two loads with a load through a select of the address to load from. 5590 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5591 // constants have been dropped into the constant pool. 5592 if (LHS.getOpcode() == ISD::LOAD && 5593 // Do not let this transformation reduce the number of volatile loads. 5594 !cast<LoadSDNode>(LHS)->isVolatile() && 5595 !cast<LoadSDNode>(RHS)->isVolatile() && 5596 // Token chains must be identical. 5597 LHS.getOperand(0) == RHS.getOperand(0)) { 5598 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5599 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5600 5601 // If this is an EXTLOAD, the VT's must match. 5602 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5603 // FIXME: this conflates two src values, discarding one. This is not 5604 // the right thing to do, but nothing uses srcvalues now. When they do, 5605 // turn SrcValue into a list of locations. 5606 SDValue Addr; 5607 if (TheSelect->getOpcode() == ISD::SELECT) { 5608 // Check that the condition doesn't reach either load. If so, folding 5609 // this will induce a cycle into the DAG. 5610 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5611 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5612 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5613 LLD->getBasePtr().getValueType(), 5614 TheSelect->getOperand(0), LLD->getBasePtr(), 5615 RLD->getBasePtr()); 5616 } 5617 } else { 5618 // Check that the condition doesn't reach either load. If so, folding 5619 // this will induce a cycle into the DAG. 5620 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5621 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5622 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5623 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5624 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5625 LLD->getBasePtr().getValueType(), 5626 TheSelect->getOperand(0), 5627 TheSelect->getOperand(1), 5628 LLD->getBasePtr(), RLD->getBasePtr(), 5629 TheSelect->getOperand(4)); 5630 } 5631 } 5632 5633 if (Addr.getNode()) { 5634 SDValue Load; 5635 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5636 Load = DAG.getLoad(TheSelect->getValueType(0), 5637 TheSelect->getDebugLoc(), 5638 LLD->getChain(), 5639 Addr,LLD->getSrcValue(), 5640 LLD->getSrcValueOffset(), 5641 LLD->isVolatile(), 5642 LLD->getAlignment()); 5643 } else { 5644 Load = DAG.getExtLoad(LLD->getExtensionType(), 5645 TheSelect->getDebugLoc(), 5646 TheSelect->getValueType(0), 5647 LLD->getChain(), Addr, LLD->getSrcValue(), 5648 LLD->getSrcValueOffset(), 5649 LLD->getMemoryVT(), 5650 LLD->isVolatile(), 5651 LLD->getAlignment()); 5652 } 5653 5654 // Users of the select now use the result of the load. 5655 CombineTo(TheSelect, Load); 5656 5657 // Users of the old loads now use the new load's chain. We know the 5658 // old-load value is dead now. 5659 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5660 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5661 return true; 5662 } 5663 } 5664 } 5665 } 5666 5667 return false; 5668} 5669 5670/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5671/// where 'cond' is the comparison specified by CC. 5672SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5673 SDValue N2, SDValue N3, 5674 ISD::CondCode CC, bool NotExtCompare) { 5675 // (x ? y : y) -> y. 5676 if (N2 == N3) return N2; 5677 5678 MVT VT = N2.getValueType(); 5679 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5680 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5681 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5682 5683 // Determine if the condition we're dealing with is constant 5684 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5685 N0, N1, CC, DL, false); 5686 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5687 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5688 5689 // fold select_cc true, x, y -> x 5690 if (SCCC && !SCCC->isNullValue()) 5691 return N2; 5692 // fold select_cc false, x, y -> y 5693 if (SCCC && SCCC->isNullValue()) 5694 return N3; 5695 5696 // Check to see if we can simplify the select into an fabs node 5697 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5698 // Allow either -0.0 or 0.0 5699 if (CFP->getValueAPF().isZero()) { 5700 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5701 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5702 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5703 N2 == N3.getOperand(0)) 5704 return DAG.getNode(ISD::FABS, DL, VT, N0); 5705 5706 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5707 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5708 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5709 N2.getOperand(0) == N3) 5710 return DAG.getNode(ISD::FABS, DL, VT, N3); 5711 } 5712 } 5713 5714 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5715 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5716 // in it. This is a win when the constant is not otherwise available because 5717 // it replaces two constant pool loads with one. We only do this if the FP 5718 // type is known to be legal, because if it isn't, then we are before legalize 5719 // types an we want the other legalization to happen first (e.g. to avoid 5720 // messing with soft float) and if the ConstantFP is not legal, because if 5721 // it is legal, we may not need to store the FP constant in a constant pool. 5722 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5723 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5724 if (TLI.isTypeLegal(N2.getValueType()) && 5725 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5726 TargetLowering::Legal) && 5727 // If both constants have multiple uses, then we won't need to do an 5728 // extra load, they are likely around in registers for other users. 5729 (TV->hasOneUse() || FV->hasOneUse())) { 5730 Constant *Elts[] = { 5731 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5732 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5733 }; 5734 const Type *FPTy = Elts[0]->getType(); 5735 const TargetData &TD = *TLI.getTargetData(); 5736 5737 // Create a ConstantArray of the two constants. 5738 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5739 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5740 TD.getPrefTypeAlignment(FPTy)); 5741 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5742 5743 // Get the offsets to the 0 and 1 element of the array so that we can 5744 // select between them. 5745 SDValue Zero = DAG.getIntPtrConstant(0); 5746 unsigned EltSize = (unsigned)TD.getTypePaddedSize(Elts[0]->getType()); 5747 SDValue One = DAG.getIntPtrConstant(EltSize); 5748 5749 SDValue Cond = DAG.getSetCC(DL, 5750 TLI.getSetCCResultType(N0.getValueType()), 5751 N0, N1, CC); 5752 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5753 Cond, One, Zero); 5754 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5755 CstOffset); 5756 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5757 PseudoSourceValue::getConstantPool(), 0, false, 5758 Alignment); 5759 5760 } 5761 } 5762 5763 // Check to see if we can perform the "gzip trick", transforming 5764 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5765 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5766 N0.getValueType().isInteger() && 5767 N2.getValueType().isInteger() && 5768 (N1C->isNullValue() || // (a < 0) ? b : 0 5769 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5770 MVT XType = N0.getValueType(); 5771 MVT AType = N2.getValueType(); 5772 if (XType.bitsGE(AType)) { 5773 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5774 // single-bit constant. 5775 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5776 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5777 ShCtV = XType.getSizeInBits()-ShCtV-1; 5778 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5779 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5780 XType, N0, ShCt); 5781 AddToWorkList(Shift.getNode()); 5782 5783 if (XType.bitsGT(AType)) { 5784 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5785 AddToWorkList(Shift.getNode()); 5786 } 5787 5788 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5789 } 5790 5791 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5792 XType, N0, 5793 DAG.getConstant(XType.getSizeInBits()-1, 5794 getShiftAmountTy())); 5795 AddToWorkList(Shift.getNode()); 5796 5797 if (XType.bitsGT(AType)) { 5798 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5799 AddToWorkList(Shift.getNode()); 5800 } 5801 5802 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5803 } 5804 } 5805 5806 // fold select C, 16, 0 -> shl C, 4 5807 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5808 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5809 5810 // If the caller doesn't want us to simplify this into a zext of a compare, 5811 // don't do it. 5812 if (NotExtCompare && N2C->getAPIntValue() == 1) 5813 return SDValue(); 5814 5815 // Get a SetCC of the condition 5816 // FIXME: Should probably make sure that setcc is legal if we ever have a 5817 // target where it isn't. 5818 SDValue Temp, SCC; 5819 // cast from setcc result type to select result type 5820 if (LegalTypes) { 5821 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5822 N0, N1, CC); 5823 if (N2.getValueType().bitsLT(SCC.getValueType())) 5824 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5825 else 5826 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5827 N2.getValueType(), SCC); 5828 } else { 5829 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5830 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5831 N2.getValueType(), SCC); 5832 } 5833 5834 AddToWorkList(SCC.getNode()); 5835 AddToWorkList(Temp.getNode()); 5836 5837 if (N2C->getAPIntValue() == 1) 5838 return Temp; 5839 5840 // shl setcc result by log2 n2c 5841 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5842 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5843 getShiftAmountTy())); 5844 } 5845 5846 // Check to see if this is the equivalent of setcc 5847 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5848 // otherwise, go ahead with the folds. 5849 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5850 MVT XType = N0.getValueType(); 5851 if (!LegalOperations || 5852 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5853 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5854 if (Res.getValueType() != VT) 5855 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5856 return Res; 5857 } 5858 5859 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5860 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5861 (!LegalOperations || 5862 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5863 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5864 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5865 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5866 getShiftAmountTy())); 5867 } 5868 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5869 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5870 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5871 XType, DAG.getConstant(0, XType), N0); 5872 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5873 return DAG.getNode(ISD::SRL, DL, XType, 5874 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5875 DAG.getConstant(XType.getSizeInBits()-1, 5876 getShiftAmountTy())); 5877 } 5878 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5879 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5880 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5881 DAG.getConstant(XType.getSizeInBits()-1, 5882 getShiftAmountTy())); 5883 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5884 } 5885 } 5886 5887 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5888 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5889 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5890 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5891 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5892 MVT XType = N0.getValueType(); 5893 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5894 DAG.getConstant(XType.getSizeInBits()-1, 5895 getShiftAmountTy())); 5896 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5897 N0, Shift); 5898 AddToWorkList(Shift.getNode()); 5899 AddToWorkList(Add.getNode()); 5900 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5901 } 5902 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5903 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5904 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5905 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5906 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5907 MVT XType = N0.getValueType(); 5908 if (SubC->isNullValue() && XType.isInteger()) { 5909 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5910 N0, 5911 DAG.getConstant(XType.getSizeInBits()-1, 5912 getShiftAmountTy())); 5913 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 5914 XType, N0, Shift); 5915 AddToWorkList(Shift.getNode()); 5916 AddToWorkList(Add.getNode()); 5917 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5918 } 5919 } 5920 } 5921 5922 return SDValue(); 5923} 5924 5925/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5926SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5927 SDValue N1, ISD::CondCode Cond, 5928 DebugLoc DL, bool foldBooleans) { 5929 TargetLowering::DAGCombinerInfo 5930 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5931 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 5932} 5933 5934/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5935/// return a DAG expression to select that will generate the same value by 5936/// multiplying by a magic number. See: 5937/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5938SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5939 std::vector<SDNode*> Built; 5940 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5941 5942 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5943 ii != ee; ++ii) 5944 AddToWorkList(*ii); 5945 return S; 5946} 5947 5948/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5949/// return a DAG expression to select that will generate the same value by 5950/// multiplying by a magic number. See: 5951/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5952SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5953 std::vector<SDNode*> Built; 5954 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5955 5956 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5957 ii != ee; ++ii) 5958 AddToWorkList(*ii); 5959 return S; 5960} 5961 5962/// FindBaseOffset - Return true if base is known not to alias with anything 5963/// but itself. Provides base object and offset as results. 5964static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5965 // Assume it is a primitive operation. 5966 Base = Ptr; Offset = 0; 5967 5968 // If it's an adding a simple constant then integrate the offset. 5969 if (Base.getOpcode() == ISD::ADD) { 5970 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5971 Base = Base.getOperand(0); 5972 Offset += C->getZExtValue(); 5973 } 5974 } 5975 5976 // If it's any of the following then it can't alias with anything but itself. 5977 return isa<FrameIndexSDNode>(Base) || 5978 isa<ConstantPoolSDNode>(Base) || 5979 isa<GlobalAddressSDNode>(Base); 5980} 5981 5982/// isAlias - Return true if there is any possibility that the two addresses 5983/// overlap. 5984bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5985 const Value *SrcValue1, int SrcValueOffset1, 5986 SDValue Ptr2, int64_t Size2, 5987 const Value *SrcValue2, int SrcValueOffset2) const { 5988 // If they are the same then they must be aliases. 5989 if (Ptr1 == Ptr2) return true; 5990 5991 // Gather base node and offset information. 5992 SDValue Base1, Base2; 5993 int64_t Offset1, Offset2; 5994 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5995 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5996 5997 // If they have a same base address then... 5998 if (Base1 == Base2) 5999 // Check to see if the addresses overlap. 6000 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6001 6002 // If we know both bases then they can't alias. 6003 if (KnownBase1 && KnownBase2) return false; 6004 6005 if (CombinerGlobalAA) { 6006 // Use alias analysis information. 6007 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6008 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6009 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6010 AliasAnalysis::AliasResult AAResult = 6011 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6012 if (AAResult == AliasAnalysis::NoAlias) 6013 return false; 6014 } 6015 6016 // Otherwise we have to assume they alias. 6017 return true; 6018} 6019 6020/// FindAliasInfo - Extracts the relevant alias information from the memory 6021/// node. Returns true if the operand was a load. 6022bool DAGCombiner::FindAliasInfo(SDNode *N, 6023 SDValue &Ptr, int64_t &Size, 6024 const Value *&SrcValue, int &SrcValueOffset) const { 6025 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6026 Ptr = LD->getBasePtr(); 6027 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6028 SrcValue = LD->getSrcValue(); 6029 SrcValueOffset = LD->getSrcValueOffset(); 6030 return true; 6031 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6032 Ptr = ST->getBasePtr(); 6033 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6034 SrcValue = ST->getSrcValue(); 6035 SrcValueOffset = ST->getSrcValueOffset(); 6036 } else { 6037 assert(0 && "FindAliasInfo expected a memory operand"); 6038 } 6039 6040 return false; 6041} 6042 6043/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6044/// looking for aliasing nodes and adding them to the Aliases vector. 6045void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6046 SmallVector<SDValue, 8> &Aliases) { 6047 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6048 std::set<SDNode *> Visited; // Visited node set. 6049 6050 // Get alias information for node. 6051 SDValue Ptr; 6052 int64_t Size; 6053 const Value *SrcValue; 6054 int SrcValueOffset; 6055 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6056 6057 // Starting off. 6058 Chains.push_back(OriginalChain); 6059 6060 // Look at each chain and determine if it is an alias. If so, add it to the 6061 // aliases list. If not, then continue up the chain looking for the next 6062 // candidate. 6063 while (!Chains.empty()) { 6064 SDValue Chain = Chains.back(); 6065 Chains.pop_back(); 6066 6067 // Don't bother if we've been before. 6068 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6069 Visited.insert(Chain.getNode()); 6070 6071 switch (Chain.getOpcode()) { 6072 case ISD::EntryToken: 6073 // Entry token is ideal chain operand, but handled in FindBetterChain. 6074 break; 6075 6076 case ISD::LOAD: 6077 case ISD::STORE: { 6078 // Get alias information for Chain. 6079 SDValue OpPtr; 6080 int64_t OpSize; 6081 const Value *OpSrcValue; 6082 int OpSrcValueOffset; 6083 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6084 OpSrcValue, OpSrcValueOffset); 6085 6086 // If chain is alias then stop here. 6087 if (!(IsLoad && IsOpLoad) && 6088 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6089 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6090 Aliases.push_back(Chain); 6091 } else { 6092 // Look further up the chain. 6093 Chains.push_back(Chain.getOperand(0)); 6094 // Clean up old chain. 6095 AddToWorkList(Chain.getNode()); 6096 } 6097 break; 6098 } 6099 6100 case ISD::TokenFactor: 6101 // We have to check each of the operands of the token factor, so we queue 6102 // then up. Adding the operands to the queue (stack) in reverse order 6103 // maintains the original order and increases the likelihood that getNode 6104 // will find a matching token factor (CSE.) 6105 for (unsigned n = Chain.getNumOperands(); n;) 6106 Chains.push_back(Chain.getOperand(--n)); 6107 // Eliminate the token factor if we can. 6108 AddToWorkList(Chain.getNode()); 6109 break; 6110 6111 default: 6112 // For all other instructions we will just have to take what we can get. 6113 Aliases.push_back(Chain); 6114 break; 6115 } 6116 } 6117} 6118 6119/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6120/// for a better chain (aliasing node.) 6121SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6122 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6123 6124 // Accumulate all the aliases to this node. 6125 GatherAllAliases(N, OldChain, Aliases); 6126 6127 if (Aliases.size() == 0) { 6128 // If no operands then chain to entry token. 6129 return DAG.getEntryNode(); 6130 } else if (Aliases.size() == 1) { 6131 // If a single operand then chain to it. We don't need to revisit it. 6132 return Aliases[0]; 6133 } 6134 6135 // Construct a custom tailored token factor. 6136 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6137 &Aliases[0], Aliases.size()); 6138 6139 // Make sure the old chain gets cleaned up. 6140 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6141 6142 return NewChain; 6143} 6144 6145// SelectionDAG::Combine - This is the entry point for the file. 6146// 6147void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { 6148 /// run - This is the main entry point to this class. 6149 /// 6150 DAGCombiner(*this, AA, Fast).Run(Level); 6151} 6152