DAGCombiner.cpp revision a4c5d8c6b4e91b880fcd1b8b293f330e3aa198a3
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: make truncate see through SIGN_EXTEND and AND 26// FIXME: divide by zero is currently left unfolded. do we want to turn this 27// into an undef? 28// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "dagcombine" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include <algorithm> 39#include <cmath> 40#include <iostream> 41using namespace llvm; 42 43namespace { 44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 45 46 class DAGCombiner { 47 SelectionDAG &DAG; 48 TargetLowering &TLI; 49 bool AfterLegalize; 50 51 // Worklist of all of the nodes that need to be simplified. 52 std::vector<SDNode*> WorkList; 53 54 /// AddUsersToWorkList - When an instruction is simplified, add all users of 55 /// the instruction to the work lists because they might get more simplified 56 /// now. 57 /// 58 void AddUsersToWorkList(SDNode *N) { 59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 60 UI != UE; ++UI) 61 WorkList.push_back(*UI); 62 } 63 64 /// removeFromWorkList - remove all instances of N from the worklist. 65 /// 66 void removeFromWorkList(SDNode *N) { 67 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 68 WorkList.end()); 69 } 70 71 public: 72 void AddToWorkList(SDNode *N) { 73 WorkList.push_back(N); 74 } 75 76 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 77 ++NodesCombined; 78 DEBUG(std::cerr << "\nReplacing "; N->dump(); 79 std::cerr << "\nWith: "; To[0].Val->dump(); 80 std::cerr << " and " << To.size()-1 << " other values\n"); 81 std::vector<SDNode*> NowDead; 82 DAG.ReplaceAllUsesWith(N, To, &NowDead); 83 84 // Push the new nodes and any users onto the worklist 85 for (unsigned i = 0, e = To.size(); i != e; ++i) { 86 WorkList.push_back(To[i].Val); 87 AddUsersToWorkList(To[i].Val); 88 } 89 90 // Nodes can end up on the worklist more than once. Make sure we do 91 // not process a node that has been replaced. 92 removeFromWorkList(N); 93 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 94 removeFromWorkList(NowDead[i]); 95 96 // Finally, since the node is now dead, remove it from the graph. 97 DAG.DeleteNode(N); 98 return SDOperand(N, 0); 99 } 100 101 SDOperand CombineTo(SDNode *N, SDOperand Res) { 102 std::vector<SDOperand> To; 103 To.push_back(Res); 104 return CombineTo(N, To); 105 } 106 107 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 108 std::vector<SDOperand> To; 109 To.push_back(Res0); 110 To.push_back(Res1); 111 return CombineTo(N, To); 112 } 113 private: 114 115 /// SimplifyDemandedBits - Check the specified integer node value to see if 116 /// it can be simplified or if things it uses can be simplified by bit 117 /// propagation. If so, return true. 118 bool SimplifyDemandedBits(SDOperand Op) { 119 TargetLowering::TargetLoweringOpt TLO(DAG); 120 uint64_t KnownZero, KnownOne; 121 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 122 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 123 return false; 124 125 // Revisit the node. 126 WorkList.push_back(Op.Val); 127 128 // Replace the old value with the new one. 129 ++NodesCombined; 130 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 131 std::cerr << "\nWith: "; TLO.New.Val->dump()); 132 133 std::vector<SDNode*> NowDead; 134 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 135 136 // Push the new node and any (possibly new) users onto the worklist. 137 WorkList.push_back(TLO.New.Val); 138 AddUsersToWorkList(TLO.New.Val); 139 140 // Nodes can end up on the worklist more than once. Make sure we do 141 // not process a node that has been replaced. 142 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 143 removeFromWorkList(NowDead[i]); 144 145 // Finally, if the node is now dead, remove it from the graph. The node 146 // may not be dead if the replacement process recursively simplified to 147 // something else needing this node. 148 if (TLO.Old.Val->use_empty()) { 149 removeFromWorkList(TLO.Old.Val); 150 DAG.DeleteNode(TLO.Old.Val); 151 } 152 return true; 153 } 154 155 /// visit - call the node-specific routine that knows how to fold each 156 /// particular type of node. 157 SDOperand visit(SDNode *N); 158 159 // Visitation implementation - Implement dag node combining for different 160 // node types. The semantics are as follows: 161 // Return Value: 162 // SDOperand.Val == 0 - No change was made 163 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 164 // otherwise - N should be replaced by the returned Operand. 165 // 166 SDOperand visitTokenFactor(SDNode *N); 167 SDOperand visitADD(SDNode *N); 168 SDOperand visitSUB(SDNode *N); 169 SDOperand visitMUL(SDNode *N); 170 SDOperand visitSDIV(SDNode *N); 171 SDOperand visitUDIV(SDNode *N); 172 SDOperand visitSREM(SDNode *N); 173 SDOperand visitUREM(SDNode *N); 174 SDOperand visitMULHU(SDNode *N); 175 SDOperand visitMULHS(SDNode *N); 176 SDOperand visitAND(SDNode *N); 177 SDOperand visitOR(SDNode *N); 178 SDOperand visitXOR(SDNode *N); 179 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 180 SDOperand visitSHL(SDNode *N); 181 SDOperand visitSRA(SDNode *N); 182 SDOperand visitSRL(SDNode *N); 183 SDOperand visitCTLZ(SDNode *N); 184 SDOperand visitCTTZ(SDNode *N); 185 SDOperand visitCTPOP(SDNode *N); 186 SDOperand visitSELECT(SDNode *N); 187 SDOperand visitSELECT_CC(SDNode *N); 188 SDOperand visitSETCC(SDNode *N); 189 SDOperand visitSIGN_EXTEND(SDNode *N); 190 SDOperand visitZERO_EXTEND(SDNode *N); 191 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 192 SDOperand visitTRUNCATE(SDNode *N); 193 SDOperand visitBIT_CONVERT(SDNode *N); 194 SDOperand visitVBIT_CONVERT(SDNode *N); 195 SDOperand visitFADD(SDNode *N); 196 SDOperand visitFSUB(SDNode *N); 197 SDOperand visitFMUL(SDNode *N); 198 SDOperand visitFDIV(SDNode *N); 199 SDOperand visitFREM(SDNode *N); 200 SDOperand visitFCOPYSIGN(SDNode *N); 201 SDOperand visitSINT_TO_FP(SDNode *N); 202 SDOperand visitUINT_TO_FP(SDNode *N); 203 SDOperand visitFP_TO_SINT(SDNode *N); 204 SDOperand visitFP_TO_UINT(SDNode *N); 205 SDOperand visitFP_ROUND(SDNode *N); 206 SDOperand visitFP_ROUND_INREG(SDNode *N); 207 SDOperand visitFP_EXTEND(SDNode *N); 208 SDOperand visitFNEG(SDNode *N); 209 SDOperand visitFABS(SDNode *N); 210 SDOperand visitBRCOND(SDNode *N); 211 SDOperand visitBR_CC(SDNode *N); 212 SDOperand visitLOAD(SDNode *N); 213 SDOperand visitXEXTLOAD(SDNode *N); 214 SDOperand visitSTORE(SDNode *N); 215 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 216 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 217 SDOperand visitVBUILD_VECTOR(SDNode *N); 218 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 219 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 220 221 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 222 223 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 224 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 225 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 226 SDOperand N3, ISD::CondCode CC); 227 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 228 ISD::CondCode Cond, bool foldBooleans = true); 229 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 230 SDOperand BuildSDIV(SDNode *N); 231 SDOperand BuildUDIV(SDNode *N); 232public: 233 DAGCombiner(SelectionDAG &D) 234 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 235 236 /// Run - runs the dag combiner on all nodes in the work list 237 void Run(bool RunningAfterLegalize); 238 }; 239} 240 241//===----------------------------------------------------------------------===// 242// TargetLowering::DAGCombinerInfo implementation 243//===----------------------------------------------------------------------===// 244 245void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 246 ((DAGCombiner*)DC)->AddToWorkList(N); 247} 248 249SDOperand TargetLowering::DAGCombinerInfo:: 250CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 251 return ((DAGCombiner*)DC)->CombineTo(N, To); 252} 253 254SDOperand TargetLowering::DAGCombinerInfo:: 255CombineTo(SDNode *N, SDOperand Res) { 256 return ((DAGCombiner*)DC)->CombineTo(N, Res); 257} 258 259 260SDOperand TargetLowering::DAGCombinerInfo:: 261CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 262 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 263} 264 265 266 267 268//===----------------------------------------------------------------------===// 269 270 271struct ms { 272 int64_t m; // magic number 273 int64_t s; // shift amount 274}; 275 276struct mu { 277 uint64_t m; // magic number 278 int64_t a; // add indicator 279 int64_t s; // shift amount 280}; 281 282/// magic - calculate the magic numbers required to codegen an integer sdiv as 283/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 284/// or -1. 285static ms magic32(int32_t d) { 286 int32_t p; 287 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 288 const uint32_t two31 = 0x80000000U; 289 struct ms mag; 290 291 ad = abs(d); 292 t = two31 + ((uint32_t)d >> 31); 293 anc = t - 1 - t%ad; // absolute value of nc 294 p = 31; // initialize p 295 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 296 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 297 q2 = two31/ad; // initialize q2 = 2p/abs(d) 298 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 299 do { 300 p = p + 1; 301 q1 = 2*q1; // update q1 = 2p/abs(nc) 302 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 303 if (r1 >= anc) { // must be unsigned comparison 304 q1 = q1 + 1; 305 r1 = r1 - anc; 306 } 307 q2 = 2*q2; // update q2 = 2p/abs(d) 308 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 309 if (r2 >= ad) { // must be unsigned comparison 310 q2 = q2 + 1; 311 r2 = r2 - ad; 312 } 313 delta = ad - r2; 314 } while (q1 < delta || (q1 == delta && r1 == 0)); 315 316 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 317 if (d < 0) mag.m = -mag.m; // resulting magic number 318 mag.s = p - 32; // resulting shift 319 return mag; 320} 321 322/// magicu - calculate the magic numbers required to codegen an integer udiv as 323/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 324static mu magicu32(uint32_t d) { 325 int32_t p; 326 uint32_t nc, delta, q1, r1, q2, r2; 327 struct mu magu; 328 magu.a = 0; // initialize "add" indicator 329 nc = - 1 - (-d)%d; 330 p = 31; // initialize p 331 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 332 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 333 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 334 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 335 do { 336 p = p + 1; 337 if (r1 >= nc - r1 ) { 338 q1 = 2*q1 + 1; // update q1 339 r1 = 2*r1 - nc; // update r1 340 } 341 else { 342 q1 = 2*q1; // update q1 343 r1 = 2*r1; // update r1 344 } 345 if (r2 + 1 >= d - r2) { 346 if (q2 >= 0x7FFFFFFF) magu.a = 1; 347 q2 = 2*q2 + 1; // update q2 348 r2 = 2*r2 + 1 - d; // update r2 349 } 350 else { 351 if (q2 >= 0x80000000) magu.a = 1; 352 q2 = 2*q2; // update q2 353 r2 = 2*r2 + 1; // update r2 354 } 355 delta = d - 1 - r2; 356 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 357 magu.m = q2 + 1; // resulting magic number 358 magu.s = p - 32; // resulting shift 359 return magu; 360} 361 362/// magic - calculate the magic numbers required to codegen an integer sdiv as 363/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 364/// or -1. 365static ms magic64(int64_t d) { 366 int64_t p; 367 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 368 const uint64_t two63 = 9223372036854775808ULL; // 2^63 369 struct ms mag; 370 371 ad = d >= 0 ? d : -d; 372 t = two63 + ((uint64_t)d >> 63); 373 anc = t - 1 - t%ad; // absolute value of nc 374 p = 63; // initialize p 375 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 376 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 377 q2 = two63/ad; // initialize q2 = 2p/abs(d) 378 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 379 do { 380 p = p + 1; 381 q1 = 2*q1; // update q1 = 2p/abs(nc) 382 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 383 if (r1 >= anc) { // must be unsigned comparison 384 q1 = q1 + 1; 385 r1 = r1 - anc; 386 } 387 q2 = 2*q2; // update q2 = 2p/abs(d) 388 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 389 if (r2 >= ad) { // must be unsigned comparison 390 q2 = q2 + 1; 391 r2 = r2 - ad; 392 } 393 delta = ad - r2; 394 } while (q1 < delta || (q1 == delta && r1 == 0)); 395 396 mag.m = q2 + 1; 397 if (d < 0) mag.m = -mag.m; // resulting magic number 398 mag.s = p - 64; // resulting shift 399 return mag; 400} 401 402/// magicu - calculate the magic numbers required to codegen an integer udiv as 403/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 404static mu magicu64(uint64_t d) 405{ 406 int64_t p; 407 uint64_t nc, delta, q1, r1, q2, r2; 408 struct mu magu; 409 magu.a = 0; // initialize "add" indicator 410 nc = - 1 - (-d)%d; 411 p = 63; // initialize p 412 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 413 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 414 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 415 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 416 do { 417 p = p + 1; 418 if (r1 >= nc - r1 ) { 419 q1 = 2*q1 + 1; // update q1 420 r1 = 2*r1 - nc; // update r1 421 } 422 else { 423 q1 = 2*q1; // update q1 424 r1 = 2*r1; // update r1 425 } 426 if (r2 + 1 >= d - r2) { 427 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 428 q2 = 2*q2 + 1; // update q2 429 r2 = 2*r2 + 1 - d; // update r2 430 } 431 else { 432 if (q2 >= 0x8000000000000000ull) magu.a = 1; 433 q2 = 2*q2; // update q2 434 r2 = 2*r2 + 1; // update r2 435 } 436 delta = d - 1 - r2; 437 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 438 magu.m = q2 + 1; // resulting magic number 439 magu.s = p - 64; // resulting shift 440 return magu; 441} 442 443// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 444// that selects between the values 1 and 0, making it equivalent to a setcc. 445// Also, set the incoming LHS, RHS, and CC references to the appropriate 446// nodes based on the type of node we are checking. This simplifies life a 447// bit for the callers. 448static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 449 SDOperand &CC) { 450 if (N.getOpcode() == ISD::SETCC) { 451 LHS = N.getOperand(0); 452 RHS = N.getOperand(1); 453 CC = N.getOperand(2); 454 return true; 455 } 456 if (N.getOpcode() == ISD::SELECT_CC && 457 N.getOperand(2).getOpcode() == ISD::Constant && 458 N.getOperand(3).getOpcode() == ISD::Constant && 459 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 460 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 461 LHS = N.getOperand(0); 462 RHS = N.getOperand(1); 463 CC = N.getOperand(4); 464 return true; 465 } 466 return false; 467} 468 469// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 470// one use. If this is true, it allows the users to invert the operation for 471// free when it is profitable to do so. 472static bool isOneUseSetCC(SDOperand N) { 473 SDOperand N0, N1, N2; 474 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 475 return true; 476 return false; 477} 478 479// FIXME: This should probably go in the ISD class rather than being duplicated 480// in several files. 481static bool isCommutativeBinOp(unsigned Opcode) { 482 switch (Opcode) { 483 case ISD::ADD: 484 case ISD::MUL: 485 case ISD::AND: 486 case ISD::OR: 487 case ISD::XOR: return true; 488 default: return false; // FIXME: Need commutative info for user ops! 489 } 490} 491 492SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 493 MVT::ValueType VT = N0.getValueType(); 494 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 495 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 496 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 497 if (isa<ConstantSDNode>(N1)) { 498 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 499 AddToWorkList(OpNode.Val); 500 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 501 } else if (N0.hasOneUse()) { 502 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 503 AddToWorkList(OpNode.Val); 504 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 505 } 506 } 507 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 508 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 509 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 510 if (isa<ConstantSDNode>(N0)) { 511 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 512 AddToWorkList(OpNode.Val); 513 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 514 } else if (N1.hasOneUse()) { 515 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 516 AddToWorkList(OpNode.Val); 517 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 518 } 519 } 520 return SDOperand(); 521} 522 523void DAGCombiner::Run(bool RunningAfterLegalize) { 524 // set the instance variable, so that the various visit routines may use it. 525 AfterLegalize = RunningAfterLegalize; 526 527 // Add all the dag nodes to the worklist. 528 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 529 E = DAG.allnodes_end(); I != E; ++I) 530 WorkList.push_back(I); 531 532 // Create a dummy node (which is not added to allnodes), that adds a reference 533 // to the root node, preventing it from being deleted, and tracking any 534 // changes of the root. 535 HandleSDNode Dummy(DAG.getRoot()); 536 537 538 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 539 TargetLowering::DAGCombinerInfo 540 DagCombineInfo(DAG, !RunningAfterLegalize, this); 541 542 // while the worklist isn't empty, inspect the node on the end of it and 543 // try and combine it. 544 while (!WorkList.empty()) { 545 SDNode *N = WorkList.back(); 546 WorkList.pop_back(); 547 548 // If N has no uses, it is dead. Make sure to revisit all N's operands once 549 // N is deleted from the DAG, since they too may now be dead or may have a 550 // reduced number of uses, allowing other xforms. 551 if (N->use_empty() && N != &Dummy) { 552 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 553 WorkList.push_back(N->getOperand(i).Val); 554 555 removeFromWorkList(N); 556 DAG.DeleteNode(N); 557 continue; 558 } 559 560 SDOperand RV = visit(N); 561 562 // If nothing happened, try a target-specific DAG combine. 563 if (RV.Val == 0) { 564 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 565 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 566 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 567 } 568 569 if (RV.Val) { 570 ++NodesCombined; 571 // If we get back the same node we passed in, rather than a new node or 572 // zero, we know that the node must have defined multiple values and 573 // CombineTo was used. Since CombineTo takes care of the worklist 574 // mechanics for us, we have no work to do in this case. 575 if (RV.Val != N) { 576 DEBUG(std::cerr << "\nReplacing "; N->dump(); 577 std::cerr << "\nWith: "; RV.Val->dump(); 578 std::cerr << '\n'); 579 std::vector<SDNode*> NowDead; 580 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 581 582 // Push the new node and any users onto the worklist 583 WorkList.push_back(RV.Val); 584 AddUsersToWorkList(RV.Val); 585 586 // Nodes can end up on the worklist more than once. Make sure we do 587 // not process a node that has been replaced. 588 removeFromWorkList(N); 589 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 590 removeFromWorkList(NowDead[i]); 591 592 // Finally, since the node is now dead, remove it from the graph. 593 DAG.DeleteNode(N); 594 } 595 } 596 } 597 598 // If the root changed (e.g. it was a dead load, update the root). 599 DAG.setRoot(Dummy.getValue()); 600} 601 602SDOperand DAGCombiner::visit(SDNode *N) { 603 switch(N->getOpcode()) { 604 default: break; 605 case ISD::TokenFactor: return visitTokenFactor(N); 606 case ISD::ADD: return visitADD(N); 607 case ISD::SUB: return visitSUB(N); 608 case ISD::MUL: return visitMUL(N); 609 case ISD::SDIV: return visitSDIV(N); 610 case ISD::UDIV: return visitUDIV(N); 611 case ISD::SREM: return visitSREM(N); 612 case ISD::UREM: return visitUREM(N); 613 case ISD::MULHU: return visitMULHU(N); 614 case ISD::MULHS: return visitMULHS(N); 615 case ISD::AND: return visitAND(N); 616 case ISD::OR: return visitOR(N); 617 case ISD::XOR: return visitXOR(N); 618 case ISD::SHL: return visitSHL(N); 619 case ISD::SRA: return visitSRA(N); 620 case ISD::SRL: return visitSRL(N); 621 case ISD::CTLZ: return visitCTLZ(N); 622 case ISD::CTTZ: return visitCTTZ(N); 623 case ISD::CTPOP: return visitCTPOP(N); 624 case ISD::SELECT: return visitSELECT(N); 625 case ISD::SELECT_CC: return visitSELECT_CC(N); 626 case ISD::SETCC: return visitSETCC(N); 627 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 628 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 629 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 630 case ISD::TRUNCATE: return visitTRUNCATE(N); 631 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 632 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 633 case ISD::FADD: return visitFADD(N); 634 case ISD::FSUB: return visitFSUB(N); 635 case ISD::FMUL: return visitFMUL(N); 636 case ISD::FDIV: return visitFDIV(N); 637 case ISD::FREM: return visitFREM(N); 638 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 639 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 640 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 641 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 642 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 643 case ISD::FP_ROUND: return visitFP_ROUND(N); 644 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 645 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 646 case ISD::FNEG: return visitFNEG(N); 647 case ISD::FABS: return visitFABS(N); 648 case ISD::BRCOND: return visitBRCOND(N); 649 case ISD::BR_CC: return visitBR_CC(N); 650 case ISD::LOAD: return visitLOAD(N); 651 case ISD::EXTLOAD: 652 case ISD::SEXTLOAD: 653 case ISD::ZEXTLOAD: return visitXEXTLOAD(N); 654 case ISD::STORE: return visitSTORE(N); 655 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 656 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 657 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 658 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 659 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 660 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 661 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 662 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 663 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 664 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 665 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 666 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 667 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 668 } 669 return SDOperand(); 670} 671 672SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 673 std::vector<SDOperand> Ops; 674 bool Changed = false; 675 676 // If the token factor has two operands and one is the entry token, replace 677 // the token factor with the other operand. 678 if (N->getNumOperands() == 2) { 679 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 680 return N->getOperand(1); 681 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 682 return N->getOperand(0); 683 } 684 685 // fold (tokenfactor (tokenfactor)) -> tokenfactor 686 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 687 SDOperand Op = N->getOperand(i); 688 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 689 AddToWorkList(Op.Val); // Remove dead node. 690 Changed = true; 691 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 692 Ops.push_back(Op.getOperand(j)); 693 } else { 694 Ops.push_back(Op); 695 } 696 } 697 if (Changed) 698 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 699 return SDOperand(); 700} 701 702SDOperand DAGCombiner::visitADD(SDNode *N) { 703 SDOperand N0 = N->getOperand(0); 704 SDOperand N1 = N->getOperand(1); 705 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 706 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 707 MVT::ValueType VT = N0.getValueType(); 708 709 // fold (add c1, c2) -> c1+c2 710 if (N0C && N1C) 711 return DAG.getNode(ISD::ADD, VT, N0, N1); 712 // canonicalize constant to RHS 713 if (N0C && !N1C) 714 return DAG.getNode(ISD::ADD, VT, N1, N0); 715 // fold (add x, 0) -> x 716 if (N1C && N1C->isNullValue()) 717 return N0; 718 // fold ((c1-A)+c2) -> (c1+c2)-A 719 if (N1C && N0.getOpcode() == ISD::SUB) 720 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 721 return DAG.getNode(ISD::SUB, VT, 722 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 723 N0.getOperand(1)); 724 // reassociate add 725 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 726 if (RADD.Val != 0) 727 return RADD; 728 // fold ((0-A) + B) -> B-A 729 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 730 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 731 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 732 // fold (A + (0-B)) -> A-B 733 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 734 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 735 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 736 // fold (A+(B-A)) -> B 737 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 738 return N1.getOperand(0); 739 740 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 741 return SDOperand(); 742 743 // fold (a+b) -> (a|b) iff a and b share no bits. 744 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 745 uint64_t LHSZero, LHSOne; 746 uint64_t RHSZero, RHSOne; 747 uint64_t Mask = MVT::getIntVTBitMask(VT); 748 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 749 if (LHSZero) { 750 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 751 752 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 753 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 754 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 755 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 756 return DAG.getNode(ISD::OR, VT, N0, N1); 757 } 758 } 759 760 return SDOperand(); 761} 762 763SDOperand DAGCombiner::visitSUB(SDNode *N) { 764 SDOperand N0 = N->getOperand(0); 765 SDOperand N1 = N->getOperand(1); 766 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 767 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 768 MVT::ValueType VT = N0.getValueType(); 769 770 // fold (sub x, x) -> 0 771 if (N0 == N1) 772 return DAG.getConstant(0, N->getValueType(0)); 773 // fold (sub c1, c2) -> c1-c2 774 if (N0C && N1C) 775 return DAG.getNode(ISD::SUB, VT, N0, N1); 776 // fold (sub x, c) -> (add x, -c) 777 if (N1C) 778 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 779 // fold (A+B)-A -> B 780 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 781 return N0.getOperand(1); 782 // fold (A+B)-B -> A 783 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 784 return N0.getOperand(0); 785 return SDOperand(); 786} 787 788SDOperand DAGCombiner::visitMUL(SDNode *N) { 789 SDOperand N0 = N->getOperand(0); 790 SDOperand N1 = N->getOperand(1); 791 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 792 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 793 MVT::ValueType VT = N0.getValueType(); 794 795 // fold (mul c1, c2) -> c1*c2 796 if (N0C && N1C) 797 return DAG.getNode(ISD::MUL, VT, N0, N1); 798 // canonicalize constant to RHS 799 if (N0C && !N1C) 800 return DAG.getNode(ISD::MUL, VT, N1, N0); 801 // fold (mul x, 0) -> 0 802 if (N1C && N1C->isNullValue()) 803 return N1; 804 // fold (mul x, -1) -> 0-x 805 if (N1C && N1C->isAllOnesValue()) 806 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 807 // fold (mul x, (1 << c)) -> x << c 808 if (N1C && isPowerOf2_64(N1C->getValue())) 809 return DAG.getNode(ISD::SHL, VT, N0, 810 DAG.getConstant(Log2_64(N1C->getValue()), 811 TLI.getShiftAmountTy())); 812 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 813 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 814 // FIXME: If the input is something that is easily negated (e.g. a 815 // single-use add), we should put the negate there. 816 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 817 DAG.getNode(ISD::SHL, VT, N0, 818 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 819 TLI.getShiftAmountTy()))); 820 } 821 822 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 823 if (N1C && N0.getOpcode() == ISD::SHL && 824 isa<ConstantSDNode>(N0.getOperand(1))) { 825 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 826 AddToWorkList(C3.Val); 827 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 828 } 829 830 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 831 // use. 832 { 833 SDOperand Sh(0,0), Y(0,0); 834 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 835 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 836 N0.Val->hasOneUse()) { 837 Sh = N0; Y = N1; 838 } else if (N1.getOpcode() == ISD::SHL && 839 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 840 Sh = N1; Y = N0; 841 } 842 if (Sh.Val) { 843 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 844 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 845 } 846 } 847 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 848 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 849 isa<ConstantSDNode>(N0.getOperand(1))) { 850 return DAG.getNode(ISD::ADD, VT, 851 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 852 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 853 } 854 855 // reassociate mul 856 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 857 if (RMUL.Val != 0) 858 return RMUL; 859 return SDOperand(); 860} 861 862SDOperand DAGCombiner::visitSDIV(SDNode *N) { 863 SDOperand N0 = N->getOperand(0); 864 SDOperand N1 = N->getOperand(1); 865 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 866 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 867 MVT::ValueType VT = N->getValueType(0); 868 869 // fold (sdiv c1, c2) -> c1/c2 870 if (N0C && N1C && !N1C->isNullValue()) 871 return DAG.getNode(ISD::SDIV, VT, N0, N1); 872 // fold (sdiv X, 1) -> X 873 if (N1C && N1C->getSignExtended() == 1LL) 874 return N0; 875 // fold (sdiv X, -1) -> 0-X 876 if (N1C && N1C->isAllOnesValue()) 877 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 878 // If we know the sign bits of both operands are zero, strength reduce to a 879 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 880 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 881 if (TLI.MaskedValueIsZero(N1, SignBit) && 882 TLI.MaskedValueIsZero(N0, SignBit)) 883 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 884 // fold (sdiv X, pow2) -> simple ops after legalize 885 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 886 (isPowerOf2_64(N1C->getSignExtended()) || 887 isPowerOf2_64(-N1C->getSignExtended()))) { 888 // If dividing by powers of two is cheap, then don't perform the following 889 // fold. 890 if (TLI.isPow2DivCheap()) 891 return SDOperand(); 892 int64_t pow2 = N1C->getSignExtended(); 893 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 894 unsigned lg2 = Log2_64(abs2); 895 // Splat the sign bit into the register 896 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 897 DAG.getConstant(MVT::getSizeInBits(VT)-1, 898 TLI.getShiftAmountTy())); 899 AddToWorkList(SGN.Val); 900 // Add (N0 < 0) ? abs2 - 1 : 0; 901 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 902 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 903 TLI.getShiftAmountTy())); 904 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 905 AddToWorkList(SRL.Val); 906 AddToWorkList(ADD.Val); // Divide by pow2 907 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 908 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 909 // If we're dividing by a positive value, we're done. Otherwise, we must 910 // negate the result. 911 if (pow2 > 0) 912 return SRA; 913 AddToWorkList(SRA.Val); 914 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 915 } 916 // if integer divide is expensive and we satisfy the requirements, emit an 917 // alternate sequence. 918 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 919 !TLI.isIntDivCheap()) { 920 SDOperand Op = BuildSDIV(N); 921 if (Op.Val) return Op; 922 } 923 return SDOperand(); 924} 925 926SDOperand DAGCombiner::visitUDIV(SDNode *N) { 927 SDOperand N0 = N->getOperand(0); 928 SDOperand N1 = N->getOperand(1); 929 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 930 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 931 MVT::ValueType VT = N->getValueType(0); 932 933 // fold (udiv c1, c2) -> c1/c2 934 if (N0C && N1C && !N1C->isNullValue()) 935 return DAG.getNode(ISD::UDIV, VT, N0, N1); 936 // fold (udiv x, (1 << c)) -> x >>u c 937 if (N1C && isPowerOf2_64(N1C->getValue())) 938 return DAG.getNode(ISD::SRL, VT, N0, 939 DAG.getConstant(Log2_64(N1C->getValue()), 940 TLI.getShiftAmountTy())); 941 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 942 if (N1.getOpcode() == ISD::SHL) { 943 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 944 if (isPowerOf2_64(SHC->getValue())) { 945 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 946 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 947 DAG.getConstant(Log2_64(SHC->getValue()), 948 ADDVT)); 949 AddToWorkList(Add.Val); 950 return DAG.getNode(ISD::SRL, VT, N0, Add); 951 } 952 } 953 } 954 // fold (udiv x, c) -> alternate 955 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 956 SDOperand Op = BuildUDIV(N); 957 if (Op.Val) return Op; 958 } 959 return SDOperand(); 960} 961 962SDOperand DAGCombiner::visitSREM(SDNode *N) { 963 SDOperand N0 = N->getOperand(0); 964 SDOperand N1 = N->getOperand(1); 965 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 966 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 967 MVT::ValueType VT = N->getValueType(0); 968 969 // fold (srem c1, c2) -> c1%c2 970 if (N0C && N1C && !N1C->isNullValue()) 971 return DAG.getNode(ISD::SREM, VT, N0, N1); 972 // If we know the sign bits of both operands are zero, strength reduce to a 973 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 974 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 975 if (TLI.MaskedValueIsZero(N1, SignBit) && 976 TLI.MaskedValueIsZero(N0, SignBit)) 977 return DAG.getNode(ISD::UREM, VT, N0, N1); 978 return SDOperand(); 979} 980 981SDOperand DAGCombiner::visitUREM(SDNode *N) { 982 SDOperand N0 = N->getOperand(0); 983 SDOperand N1 = N->getOperand(1); 984 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 985 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 986 MVT::ValueType VT = N->getValueType(0); 987 988 // fold (urem c1, c2) -> c1%c2 989 if (N0C && N1C && !N1C->isNullValue()) 990 return DAG.getNode(ISD::UREM, VT, N0, N1); 991 // fold (urem x, pow2) -> (and x, pow2-1) 992 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 993 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 994 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 995 if (N1.getOpcode() == ISD::SHL) { 996 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 997 if (isPowerOf2_64(SHC->getValue())) { 998 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 999 AddToWorkList(Add.Val); 1000 return DAG.getNode(ISD::AND, VT, N0, Add); 1001 } 1002 } 1003 } 1004 return SDOperand(); 1005} 1006 1007SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1008 SDOperand N0 = N->getOperand(0); 1009 SDOperand N1 = N->getOperand(1); 1010 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1011 1012 // fold (mulhs x, 0) -> 0 1013 if (N1C && N1C->isNullValue()) 1014 return N1; 1015 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1016 if (N1C && N1C->getValue() == 1) 1017 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1018 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1019 TLI.getShiftAmountTy())); 1020 return SDOperand(); 1021} 1022 1023SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1024 SDOperand N0 = N->getOperand(0); 1025 SDOperand N1 = N->getOperand(1); 1026 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1027 1028 // fold (mulhu x, 0) -> 0 1029 if (N1C && N1C->isNullValue()) 1030 return N1; 1031 // fold (mulhu x, 1) -> 0 1032 if (N1C && N1C->getValue() == 1) 1033 return DAG.getConstant(0, N0.getValueType()); 1034 return SDOperand(); 1035} 1036 1037SDOperand DAGCombiner::visitAND(SDNode *N) { 1038 SDOperand N0 = N->getOperand(0); 1039 SDOperand N1 = N->getOperand(1); 1040 SDOperand LL, LR, RL, RR, CC0, CC1; 1041 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1042 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1043 MVT::ValueType VT = N1.getValueType(); 1044 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1045 1046 // fold (and c1, c2) -> c1&c2 1047 if (N0C && N1C) 1048 return DAG.getNode(ISD::AND, VT, N0, N1); 1049 // canonicalize constant to RHS 1050 if (N0C && !N1C) 1051 return DAG.getNode(ISD::AND, VT, N1, N0); 1052 // fold (and x, -1) -> x 1053 if (N1C && N1C->isAllOnesValue()) 1054 return N0; 1055 // if (and x, c) is known to be zero, return 0 1056 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1057 return DAG.getConstant(0, VT); 1058 // reassociate and 1059 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1060 if (RAND.Val != 0) 1061 return RAND; 1062 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1063 if (N1C && N0.getOpcode() == ISD::OR) 1064 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1065 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1066 return N1; 1067 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1068 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1069 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1070 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1071 ~N1C->getValue() & InMask)) { 1072 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1073 N0.getOperand(0)); 1074 1075 // Replace uses of the AND with uses of the Zero extend node. 1076 CombineTo(N, Zext); 1077 1078 // We actually want to replace all uses of the any_extend with the 1079 // zero_extend, to avoid duplicating things. This will later cause this 1080 // AND to be folded. 1081 CombineTo(N0.Val, Zext); 1082 return SDOperand(); 1083 } 1084 } 1085 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1086 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1087 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1088 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1089 1090 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1091 MVT::isInteger(LL.getValueType())) { 1092 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1093 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1094 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1095 AddToWorkList(ORNode.Val); 1096 return DAG.getSetCC(VT, ORNode, LR, Op1); 1097 } 1098 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1099 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1100 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1101 AddToWorkList(ANDNode.Val); 1102 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1103 } 1104 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1105 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1106 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1107 AddToWorkList(ORNode.Val); 1108 return DAG.getSetCC(VT, ORNode, LR, Op1); 1109 } 1110 } 1111 // canonicalize equivalent to ll == rl 1112 if (LL == RR && LR == RL) { 1113 Op1 = ISD::getSetCCSwappedOperands(Op1); 1114 std::swap(RL, RR); 1115 } 1116 if (LL == RL && LR == RR) { 1117 bool isInteger = MVT::isInteger(LL.getValueType()); 1118 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1119 if (Result != ISD::SETCC_INVALID) 1120 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1121 } 1122 } 1123 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 1124 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1125 N1.getOpcode() == ISD::ZERO_EXTEND && 1126 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1127 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1128 N0.getOperand(0), N1.getOperand(0)); 1129 AddToWorkList(ANDNode.Val); 1130 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 1131 } 1132 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y)) 1133 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1134 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1135 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1136 N0.getOperand(1) == N1.getOperand(1)) { 1137 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1138 N0.getOperand(0), N1.getOperand(0)); 1139 AddToWorkList(ANDNode.Val); 1140 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 1141 } 1142 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1143 // fold (and (sra)) -> (and (srl)) when possible. 1144 if (!MVT::isVector(VT) && 1145 SimplifyDemandedBits(SDOperand(N, 0))) 1146 return SDOperand(); 1147 // fold (zext_inreg (extload x)) -> (zextload x) 1148 if (N0.getOpcode() == ISD::EXTLOAD) { 1149 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1150 // If we zero all the possible extended bits, then we can turn this into 1151 // a zextload if we are running before legalize or the operation is legal. 1152 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1153 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1154 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1155 N0.getOperand(1), N0.getOperand(2), 1156 EVT); 1157 AddToWorkList(N); 1158 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1159 return SDOperand(); 1160 } 1161 } 1162 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1163 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1164 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1165 // If we zero all the possible extended bits, then we can turn this into 1166 // a zextload if we are running before legalize or the operation is legal. 1167 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1168 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1169 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1170 N0.getOperand(1), N0.getOperand(2), 1171 EVT); 1172 AddToWorkList(N); 1173 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1174 return SDOperand(); 1175 } 1176 } 1177 1178 // fold (and (load x), 255) -> (zextload x, i8) 1179 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1180 if (N1C && 1181 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD || 1182 N0.getOpcode() == ISD::ZEXTLOAD) && 1183 N0.hasOneUse()) { 1184 MVT::ValueType EVT, LoadedVT; 1185 if (N1C->getValue() == 255) 1186 EVT = MVT::i8; 1187 else if (N1C->getValue() == 65535) 1188 EVT = MVT::i16; 1189 else if (N1C->getValue() == ~0U) 1190 EVT = MVT::i32; 1191 else 1192 EVT = MVT::Other; 1193 1194 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : 1195 cast<VTSDNode>(N0.getOperand(3))->getVT(); 1196 if (EVT != MVT::Other && LoadedVT > EVT) { 1197 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1198 // For big endian targets, we need to add an offset to the pointer to load 1199 // the correct bytes. For little endian systems, we merely need to read 1200 // fewer bytes from the same pointer. 1201 unsigned PtrOff = 1202 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1203 SDOperand NewPtr = N0.getOperand(1); 1204 if (!TLI.isLittleEndian()) 1205 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1206 DAG.getConstant(PtrOff, PtrType)); 1207 AddToWorkList(NewPtr.Val); 1208 SDOperand Load = 1209 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr, 1210 N0.getOperand(2), EVT); 1211 AddToWorkList(N); 1212 CombineTo(N0.Val, Load, Load.getValue(1)); 1213 return SDOperand(); 1214 } 1215 } 1216 1217 return SDOperand(); 1218} 1219 1220SDOperand DAGCombiner::visitOR(SDNode *N) { 1221 SDOperand N0 = N->getOperand(0); 1222 SDOperand N1 = N->getOperand(1); 1223 SDOperand LL, LR, RL, RR, CC0, CC1; 1224 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1225 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1226 MVT::ValueType VT = N1.getValueType(); 1227 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1228 1229 // fold (or c1, c2) -> c1|c2 1230 if (N0C && N1C) 1231 return DAG.getNode(ISD::OR, VT, N0, N1); 1232 // canonicalize constant to RHS 1233 if (N0C && !N1C) 1234 return DAG.getNode(ISD::OR, VT, N1, N0); 1235 // fold (or x, 0) -> x 1236 if (N1C && N1C->isNullValue()) 1237 return N0; 1238 // fold (or x, -1) -> -1 1239 if (N1C && N1C->isAllOnesValue()) 1240 return N1; 1241 // fold (or x, c) -> c iff (x & ~c) == 0 1242 if (N1C && 1243 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1244 return N1; 1245 // reassociate or 1246 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1247 if (ROR.Val != 0) 1248 return ROR; 1249 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1250 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1251 isa<ConstantSDNode>(N0.getOperand(1))) { 1252 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1253 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1254 N1), 1255 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1256 } 1257 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1258 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1259 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1260 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1261 1262 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1263 MVT::isInteger(LL.getValueType())) { 1264 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1265 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1266 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1267 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1268 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1269 AddToWorkList(ORNode.Val); 1270 return DAG.getSetCC(VT, ORNode, LR, Op1); 1271 } 1272 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1273 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1274 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1275 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1276 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1277 AddToWorkList(ANDNode.Val); 1278 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1279 } 1280 } 1281 // canonicalize equivalent to ll == rl 1282 if (LL == RR && LR == RL) { 1283 Op1 = ISD::getSetCCSwappedOperands(Op1); 1284 std::swap(RL, RR); 1285 } 1286 if (LL == RL && LR == RR) { 1287 bool isInteger = MVT::isInteger(LL.getValueType()); 1288 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1289 if (Result != ISD::SETCC_INVALID) 1290 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1291 } 1292 } 1293 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 1294 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1295 N1.getOpcode() == ISD::ZERO_EXTEND && 1296 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1297 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1298 N0.getOperand(0), N1.getOperand(0)); 1299 AddToWorkList(ORNode.Val); 1300 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 1301 } 1302 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y)) 1303 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1304 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1305 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1306 N0.getOperand(1) == N1.getOperand(1)) { 1307 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1308 N0.getOperand(0), N1.getOperand(0)); 1309 AddToWorkList(ORNode.Val); 1310 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1311 } 1312 // canonicalize shl to left side in a shl/srl pair, to match rotate 1313 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 1314 std::swap(N0, N1); 1315 // check for rotl, rotr 1316 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 1317 N0.getOperand(0) == N1.getOperand(0) && 1318 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 1319 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1320 if (N0.getOperand(1).getOpcode() == ISD::Constant && 1321 N1.getOperand(1).getOpcode() == ISD::Constant) { 1322 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1323 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1324 if ((c1val + c2val) == OpSizeInBits) 1325 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1326 } 1327 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1328 if (N1.getOperand(1).getOpcode() == ISD::SUB && 1329 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 1330 if (ConstantSDNode *SUBC = 1331 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 1332 if (SUBC->getValue() == OpSizeInBits) 1333 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1334 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1335 if (N0.getOperand(1).getOpcode() == ISD::SUB && 1336 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 1337 if (ConstantSDNode *SUBC = 1338 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 1339 if (SUBC->getValue() == OpSizeInBits) { 1340 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 1341 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 1342 N1.getOperand(1)); 1343 else 1344 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 1345 N0.getOperand(1)); 1346 } 1347 } 1348 return SDOperand(); 1349} 1350 1351SDOperand DAGCombiner::visitXOR(SDNode *N) { 1352 SDOperand N0 = N->getOperand(0); 1353 SDOperand N1 = N->getOperand(1); 1354 SDOperand LHS, RHS, CC; 1355 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1356 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1357 MVT::ValueType VT = N0.getValueType(); 1358 1359 // fold (xor c1, c2) -> c1^c2 1360 if (N0C && N1C) 1361 return DAG.getNode(ISD::XOR, VT, N0, N1); 1362 // canonicalize constant to RHS 1363 if (N0C && !N1C) 1364 return DAG.getNode(ISD::XOR, VT, N1, N0); 1365 // fold (xor x, 0) -> x 1366 if (N1C && N1C->isNullValue()) 1367 return N0; 1368 // reassociate xor 1369 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1370 if (RXOR.Val != 0) 1371 return RXOR; 1372 // fold !(x cc y) -> (x !cc y) 1373 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1374 bool isInt = MVT::isInteger(LHS.getValueType()); 1375 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1376 isInt); 1377 if (N0.getOpcode() == ISD::SETCC) 1378 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1379 if (N0.getOpcode() == ISD::SELECT_CC) 1380 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1381 assert(0 && "Unhandled SetCC Equivalent!"); 1382 abort(); 1383 } 1384 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1385 if (N1C && N1C->getValue() == 1 && 1386 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1387 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1388 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1389 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1390 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1391 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1392 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1393 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1394 } 1395 } 1396 // fold !(x or y) -> (!x and !y) iff x or y are constants 1397 if (N1C && N1C->isAllOnesValue() && 1398 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1399 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1400 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1401 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1402 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1403 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1404 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1405 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1406 } 1407 } 1408 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1409 if (N1C && N0.getOpcode() == ISD::XOR) { 1410 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1411 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1412 if (N00C) 1413 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1414 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1415 if (N01C) 1416 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1417 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1418 } 1419 // fold (xor x, x) -> 0 1420 if (N0 == N1) { 1421 if (!MVT::isVector(VT)) { 1422 return DAG.getConstant(0, VT); 1423 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1424 // Produce a vector of zeros. 1425 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1426 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1427 return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); 1428 } 1429 } 1430 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1431 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1432 N1.getOpcode() == ISD::ZERO_EXTEND && 1433 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1434 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1435 N0.getOperand(0), N1.getOperand(0)); 1436 AddToWorkList(XORNode.Val); 1437 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1438 } 1439 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y)) 1440 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1441 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1442 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1443 N0.getOperand(1) == N1.getOperand(1)) { 1444 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1445 N0.getOperand(0), N1.getOperand(0)); 1446 AddToWorkList(XORNode.Val); 1447 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1)); 1448 } 1449 return SDOperand(); 1450} 1451 1452SDOperand DAGCombiner::visitSHL(SDNode *N) { 1453 SDOperand N0 = N->getOperand(0); 1454 SDOperand N1 = N->getOperand(1); 1455 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1456 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1457 MVT::ValueType VT = N0.getValueType(); 1458 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1459 1460 // fold (shl c1, c2) -> c1<<c2 1461 if (N0C && N1C) 1462 return DAG.getNode(ISD::SHL, VT, N0, N1); 1463 // fold (shl 0, x) -> 0 1464 if (N0C && N0C->isNullValue()) 1465 return N0; 1466 // fold (shl x, c >= size(x)) -> undef 1467 if (N1C && N1C->getValue() >= OpSizeInBits) 1468 return DAG.getNode(ISD::UNDEF, VT); 1469 // fold (shl x, 0) -> x 1470 if (N1C && N1C->isNullValue()) 1471 return N0; 1472 // if (shl x, c) is known to be zero, return 0 1473 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1474 return DAG.getConstant(0, VT); 1475 if (SimplifyDemandedBits(SDOperand(N, 0))) 1476 return SDOperand(); 1477 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1478 if (N1C && N0.getOpcode() == ISD::SHL && 1479 N0.getOperand(1).getOpcode() == ISD::Constant) { 1480 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1481 uint64_t c2 = N1C->getValue(); 1482 if (c1 + c2 > OpSizeInBits) 1483 return DAG.getConstant(0, VT); 1484 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1485 DAG.getConstant(c1 + c2, N1.getValueType())); 1486 } 1487 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1488 // (srl (and x, -1 << c1), c1-c2) 1489 if (N1C && N0.getOpcode() == ISD::SRL && 1490 N0.getOperand(1).getOpcode() == ISD::Constant) { 1491 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1492 uint64_t c2 = N1C->getValue(); 1493 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1494 DAG.getConstant(~0ULL << c1, VT)); 1495 if (c2 > c1) 1496 return DAG.getNode(ISD::SHL, VT, Mask, 1497 DAG.getConstant(c2-c1, N1.getValueType())); 1498 else 1499 return DAG.getNode(ISD::SRL, VT, Mask, 1500 DAG.getConstant(c1-c2, N1.getValueType())); 1501 } 1502 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1503 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1504 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1505 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1506 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) 1507 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1508 isa<ConstantSDNode>(N0.getOperand(1))) { 1509 return DAG.getNode(ISD::ADD, VT, 1510 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1), 1511 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1)); 1512 } 1513 return SDOperand(); 1514} 1515 1516SDOperand DAGCombiner::visitSRA(SDNode *N) { 1517 SDOperand N0 = N->getOperand(0); 1518 SDOperand N1 = N->getOperand(1); 1519 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1521 MVT::ValueType VT = N0.getValueType(); 1522 1523 // fold (sra c1, c2) -> c1>>c2 1524 if (N0C && N1C) 1525 return DAG.getNode(ISD::SRA, VT, N0, N1); 1526 // fold (sra 0, x) -> 0 1527 if (N0C && N0C->isNullValue()) 1528 return N0; 1529 // fold (sra -1, x) -> -1 1530 if (N0C && N0C->isAllOnesValue()) 1531 return N0; 1532 // fold (sra x, c >= size(x)) -> undef 1533 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1534 return DAG.getNode(ISD::UNDEF, VT); 1535 // fold (sra x, 0) -> x 1536 if (N1C && N1C->isNullValue()) 1537 return N0; 1538 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1539 // sext_inreg. 1540 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1541 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1542 MVT::ValueType EVT; 1543 switch (LowBits) { 1544 default: EVT = MVT::Other; break; 1545 case 1: EVT = MVT::i1; break; 1546 case 8: EVT = MVT::i8; break; 1547 case 16: EVT = MVT::i16; break; 1548 case 32: EVT = MVT::i32; break; 1549 } 1550 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1551 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1552 DAG.getValueType(EVT)); 1553 } 1554 1555 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1556 if (N1C && N0.getOpcode() == ISD::SRA) { 1557 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1558 unsigned Sum = N1C->getValue() + C1->getValue(); 1559 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1560 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1561 DAG.getConstant(Sum, N1C->getValueType(0))); 1562 } 1563 } 1564 1565 // If the sign bit is known to be zero, switch this to a SRL. 1566 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1567 return DAG.getNode(ISD::SRL, VT, N0, N1); 1568 return SDOperand(); 1569} 1570 1571SDOperand DAGCombiner::visitSRL(SDNode *N) { 1572 SDOperand N0 = N->getOperand(0); 1573 SDOperand N1 = N->getOperand(1); 1574 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1575 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1576 MVT::ValueType VT = N0.getValueType(); 1577 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1578 1579 // fold (srl c1, c2) -> c1 >>u c2 1580 if (N0C && N1C) 1581 return DAG.getNode(ISD::SRL, VT, N0, N1); 1582 // fold (srl 0, x) -> 0 1583 if (N0C && N0C->isNullValue()) 1584 return N0; 1585 // fold (srl x, c >= size(x)) -> undef 1586 if (N1C && N1C->getValue() >= OpSizeInBits) 1587 return DAG.getNode(ISD::UNDEF, VT); 1588 // fold (srl x, 0) -> x 1589 if (N1C && N1C->isNullValue()) 1590 return N0; 1591 // if (srl x, c) is known to be zero, return 0 1592 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1593 return DAG.getConstant(0, VT); 1594 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1595 if (N1C && N0.getOpcode() == ISD::SRL && 1596 N0.getOperand(1).getOpcode() == ISD::Constant) { 1597 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1598 uint64_t c2 = N1C->getValue(); 1599 if (c1 + c2 > OpSizeInBits) 1600 return DAG.getConstant(0, VT); 1601 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1602 DAG.getConstant(c1 + c2, N1.getValueType())); 1603 } 1604 1605 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1606 if (N1C && N0.getOpcode() == ISD::CTLZ && 1607 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1608 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1609 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1610 1611 // If any of the input bits are KnownOne, then the input couldn't be all 1612 // zeros, thus the result of the srl will always be zero. 1613 if (KnownOne) return DAG.getConstant(0, VT); 1614 1615 // If all of the bits input the to ctlz node are known to be zero, then 1616 // the result of the ctlz is "32" and the result of the shift is one. 1617 uint64_t UnknownBits = ~KnownZero & Mask; 1618 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1619 1620 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1621 if ((UnknownBits & (UnknownBits-1)) == 0) { 1622 // Okay, we know that only that the single bit specified by UnknownBits 1623 // could be set on input to the CTLZ node. If this bit is set, the SRL 1624 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1625 // to an SRL,XOR pair, which is likely to simplify more. 1626 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1627 SDOperand Op = N0.getOperand(0); 1628 if (ShAmt) { 1629 Op = DAG.getNode(ISD::SRL, VT, Op, 1630 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1631 AddToWorkList(Op.Val); 1632 } 1633 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1634 } 1635 } 1636 1637 return SDOperand(); 1638} 1639 1640SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1641 SDOperand N0 = N->getOperand(0); 1642 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1643 MVT::ValueType VT = N->getValueType(0); 1644 1645 // fold (ctlz c1) -> c2 1646 if (N0C) 1647 return DAG.getNode(ISD::CTLZ, VT, N0); 1648 return SDOperand(); 1649} 1650 1651SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1652 SDOperand N0 = N->getOperand(0); 1653 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1654 MVT::ValueType VT = N->getValueType(0); 1655 1656 // fold (cttz c1) -> c2 1657 if (N0C) 1658 return DAG.getNode(ISD::CTTZ, VT, N0); 1659 return SDOperand(); 1660} 1661 1662SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1663 SDOperand N0 = N->getOperand(0); 1664 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1665 MVT::ValueType VT = N->getValueType(0); 1666 1667 // fold (ctpop c1) -> c2 1668 if (N0C) 1669 return DAG.getNode(ISD::CTPOP, VT, N0); 1670 return SDOperand(); 1671} 1672 1673SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1674 SDOperand N0 = N->getOperand(0); 1675 SDOperand N1 = N->getOperand(1); 1676 SDOperand N2 = N->getOperand(2); 1677 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1678 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1679 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1680 MVT::ValueType VT = N->getValueType(0); 1681 1682 // fold select C, X, X -> X 1683 if (N1 == N2) 1684 return N1; 1685 // fold select true, X, Y -> X 1686 if (N0C && !N0C->isNullValue()) 1687 return N1; 1688 // fold select false, X, Y -> Y 1689 if (N0C && N0C->isNullValue()) 1690 return N2; 1691 // fold select C, 1, X -> C | X 1692 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1693 return DAG.getNode(ISD::OR, VT, N0, N2); 1694 // fold select C, 0, X -> ~C & X 1695 // FIXME: this should check for C type == X type, not i1? 1696 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1697 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1698 AddToWorkList(XORNode.Val); 1699 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1700 } 1701 // fold select C, X, 1 -> ~C | X 1702 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1703 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1704 AddToWorkList(XORNode.Val); 1705 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1706 } 1707 // fold select C, X, 0 -> C & X 1708 // FIXME: this should check for C type == X type, not i1? 1709 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1710 return DAG.getNode(ISD::AND, VT, N0, N1); 1711 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1712 if (MVT::i1 == VT && N0 == N1) 1713 return DAG.getNode(ISD::OR, VT, N0, N2); 1714 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1715 if (MVT::i1 == VT && N0 == N2) 1716 return DAG.getNode(ISD::AND, VT, N0, N1); 1717 // If we can fold this based on the true/false value, do so. 1718 if (SimplifySelectOps(N, N1, N2)) 1719 return SDOperand(); 1720 // fold selects based on a setcc into other things, such as min/max/abs 1721 if (N0.getOpcode() == ISD::SETCC) 1722 // FIXME: 1723 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1724 // having to say they don't support SELECT_CC on every type the DAG knows 1725 // about, since there is no way to mark an opcode illegal at all value types 1726 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1727 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1728 N1, N2, N0.getOperand(2)); 1729 else 1730 return SimplifySelect(N0, N1, N2); 1731 return SDOperand(); 1732} 1733 1734SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1735 SDOperand N0 = N->getOperand(0); 1736 SDOperand N1 = N->getOperand(1); 1737 SDOperand N2 = N->getOperand(2); 1738 SDOperand N3 = N->getOperand(3); 1739 SDOperand N4 = N->getOperand(4); 1740 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1741 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1742 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1743 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1744 1745 // Determine if the condition we're dealing with is constant 1746 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1747 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1748 1749 // fold select_cc lhs, rhs, x, x, cc -> x 1750 if (N2 == N3) 1751 return N2; 1752 1753 // If we can fold this based on the true/false value, do so. 1754 if (SimplifySelectOps(N, N2, N3)) 1755 return SDOperand(); 1756 1757 // fold select_cc into other things, such as min/max/abs 1758 return SimplifySelectCC(N0, N1, N2, N3, CC); 1759} 1760 1761SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1762 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1763 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1764} 1765 1766SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1767 SDOperand N0 = N->getOperand(0); 1768 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1769 MVT::ValueType VT = N->getValueType(0); 1770 1771 // fold (sext c1) -> c1 1772 if (N0C) 1773 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1774 // fold (sext (sext x)) -> (sext x) 1775 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1776 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1777 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1778 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1779 (!AfterLegalize || 1780 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1781 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1782 DAG.getValueType(N0.getValueType())); 1783 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1784 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1785 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1786 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1787 N0.getOperand(1), N0.getOperand(2), 1788 N0.getValueType()); 1789 CombineTo(N, ExtLoad); 1790 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1791 ExtLoad.getValue(1)); 1792 return SDOperand(); 1793 } 1794 1795 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1796 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1797 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1798 N0.hasOneUse()) { 1799 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0), 1800 N0.getOperand(1), N0.getOperand(2), 1801 N0.getOperand(3)); 1802 CombineTo(N, ExtLoad); 1803 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1804 ExtLoad.getValue(1)); 1805 return SDOperand(); 1806 } 1807 1808 return SDOperand(); 1809} 1810 1811SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1812 SDOperand N0 = N->getOperand(0); 1813 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1814 MVT::ValueType VT = N->getValueType(0); 1815 1816 // fold (zext c1) -> c1 1817 if (N0C) 1818 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1819 // fold (zext (zext x)) -> (zext x) 1820 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1821 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1822 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1823 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1824 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1825 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1826 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1827 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1828 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1829 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1830 N0.getOperand(1), N0.getOperand(2), 1831 N0.getValueType()); 1832 CombineTo(N, ExtLoad); 1833 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1834 ExtLoad.getValue(1)); 1835 return SDOperand(); 1836 } 1837 1838 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1839 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1840 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1841 N0.hasOneUse()) { 1842 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1843 N0.getOperand(1), N0.getOperand(2), 1844 N0.getOperand(3)); 1845 CombineTo(N, ExtLoad); 1846 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1847 ExtLoad.getValue(1)); 1848 return SDOperand(); 1849 } 1850 return SDOperand(); 1851} 1852 1853SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1854 SDOperand N0 = N->getOperand(0); 1855 SDOperand N1 = N->getOperand(1); 1856 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1857 MVT::ValueType VT = N->getValueType(0); 1858 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1859 unsigned EVTBits = MVT::getSizeInBits(EVT); 1860 1861 // fold (sext_in_reg c1) -> c1 1862 if (N0C) { 1863 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1864 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1865 } 1866 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1867 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1868 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1869 return N0; 1870 } 1871 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1872 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1873 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1874 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1875 } 1876 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1877 if (N0.getOpcode() == ISD::AssertSext && 1878 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1879 return N0; 1880 } 1881 // fold (sext_in_reg (sextload x)) -> (sextload x) 1882 if (N0.getOpcode() == ISD::SEXTLOAD && 1883 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1884 return N0; 1885 } 1886 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1887 if (N0.getOpcode() == ISD::SETCC && 1888 TLI.getSetCCResultContents() == 1889 TargetLowering::ZeroOrNegativeOneSetCCResult) 1890 return N0; 1891 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1892 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1893 return DAG.getZeroExtendInReg(N0, EVT); 1894 // fold (sext_in_reg (srl x)) -> sra x 1895 if (N0.getOpcode() == ISD::SRL && 1896 N0.getOperand(1).getOpcode() == ISD::Constant && 1897 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1898 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1899 N0.getOperand(1)); 1900 } 1901 // fold (sext_inreg (extload x)) -> (sextload x) 1902 if (N0.getOpcode() == ISD::EXTLOAD && 1903 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1904 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1905 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1906 N0.getOperand(1), N0.getOperand(2), 1907 EVT); 1908 CombineTo(N, ExtLoad); 1909 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1910 return SDOperand(); 1911 } 1912 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1913 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1914 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1915 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1916 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1917 N0.getOperand(1), N0.getOperand(2), 1918 EVT); 1919 CombineTo(N, ExtLoad); 1920 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1921 return SDOperand(); 1922 } 1923 return SDOperand(); 1924} 1925 1926SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1927 SDOperand N0 = N->getOperand(0); 1928 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1929 MVT::ValueType VT = N->getValueType(0); 1930 1931 // noop truncate 1932 if (N0.getValueType() == N->getValueType(0)) 1933 return N0; 1934 // fold (truncate c1) -> c1 1935 if (N0C) 1936 return DAG.getNode(ISD::TRUNCATE, VT, N0); 1937 // fold (truncate (truncate x)) -> (truncate x) 1938 if (N0.getOpcode() == ISD::TRUNCATE) 1939 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1940 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1941 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1942 if (N0.getValueType() < VT) 1943 // if the source is smaller than the dest, we still need an extend 1944 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1945 else if (N0.getValueType() > VT) 1946 // if the source is larger than the dest, than we just need the truncate 1947 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1948 else 1949 // if the source and dest are the same type, we can drop both the extend 1950 // and the truncate 1951 return N0.getOperand(0); 1952 } 1953 // fold (truncate (load x)) -> (smaller load x) 1954 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1955 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1956 "Cannot truncate to larger type!"); 1957 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1958 // For big endian targets, we need to add an offset to the pointer to load 1959 // the correct bytes. For little endian systems, we merely need to read 1960 // fewer bytes from the same pointer. 1961 uint64_t PtrOff = 1962 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1963 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1964 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1965 DAG.getConstant(PtrOff, PtrType)); 1966 AddToWorkList(NewPtr.Val); 1967 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1968 AddToWorkList(N); 1969 CombineTo(N0.Val, Load, Load.getValue(1)); 1970 return SDOperand(); 1971 } 1972 return SDOperand(); 1973} 1974 1975SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 1976 SDOperand N0 = N->getOperand(0); 1977 MVT::ValueType VT = N->getValueType(0); 1978 1979 // If the input is a constant, let getNode() fold it. 1980 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 1981 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 1982 if (Res.Val != N) return Res; 1983 } 1984 1985 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 1986 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 1987 1988 // fold (conv (load x)) -> (load (conv*)x) 1989 // FIXME: These xforms need to know that the resultant load doesn't need a 1990 // higher alignment than the original! 1991 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1992 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 1993 N0.getOperand(2)); 1994 AddToWorkList(N); 1995 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 1996 Load.getValue(1)); 1997 return Load; 1998 } 1999 2000 return SDOperand(); 2001} 2002 2003SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2004 SDOperand N0 = N->getOperand(0); 2005 MVT::ValueType VT = N->getValueType(0); 2006 2007 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2008 // First check to see if this is all constant. 2009 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2010 VT == MVT::Vector) { 2011 bool isSimple = true; 2012 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2013 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2014 N0.getOperand(i).getOpcode() != ISD::Constant && 2015 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2016 isSimple = false; 2017 break; 2018 } 2019 2020 if (isSimple) { 2021 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2022 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2023 } 2024 } 2025 2026 return SDOperand(); 2027} 2028 2029/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2030/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2031/// destination element value type. 2032SDOperand DAGCombiner:: 2033ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2034 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2035 2036 // If this is already the right type, we're done. 2037 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2038 2039 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2040 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2041 2042 // If this is a conversion of N elements of one type to N elements of another 2043 // type, convert each element. This handles FP<->INT cases. 2044 if (SrcBitSize == DstBitSize) { 2045 std::vector<SDOperand> Ops; 2046 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) 2047 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2048 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2049 Ops.push_back(DAG.getValueType(DstEltVT)); 2050 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2051 } 2052 2053 // Otherwise, we're growing or shrinking the elements. To avoid having to 2054 // handle annoying details of growing/shrinking FP values, we convert them to 2055 // int first. 2056 if (MVT::isFloatingPoint(SrcEltVT)) { 2057 // Convert the input float vector to a int vector where the elements are the 2058 // same sizes. 2059 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2060 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2061 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2062 SrcEltVT = IntVT; 2063 } 2064 2065 // Now we know the input is an integer vector. If the output is a FP type, 2066 // convert to integer first, then to FP of the right size. 2067 if (MVT::isFloatingPoint(DstEltVT)) { 2068 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2069 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2070 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2071 2072 // Next, convert to FP elements of the same size. 2073 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2074 } 2075 2076 // Okay, we know the src/dst types are both integers of differing types. 2077 // Handling growing first. 2078 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2079 if (SrcBitSize < DstBitSize) { 2080 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2081 2082 std::vector<SDOperand> Ops; 2083 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2084 i += NumInputsPerOutput) { 2085 bool isLE = TLI.isLittleEndian(); 2086 uint64_t NewBits = 0; 2087 bool EltIsUndef = true; 2088 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2089 // Shift the previously computed bits over. 2090 NewBits <<= SrcBitSize; 2091 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2092 if (Op.getOpcode() == ISD::UNDEF) continue; 2093 EltIsUndef = false; 2094 2095 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2096 } 2097 2098 if (EltIsUndef) 2099 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2100 else 2101 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2102 } 2103 2104 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2105 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2106 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2107 } 2108 2109 // Finally, this must be the case where we are shrinking elements: each input 2110 // turns into multiple outputs. 2111 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2112 std::vector<SDOperand> Ops; 2113 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2114 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2115 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2116 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2117 continue; 2118 } 2119 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2120 2121 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2122 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2123 OpVal >>= DstBitSize; 2124 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2125 } 2126 2127 // For big endian targets, swap the order of the pieces of each element. 2128 if (!TLI.isLittleEndian()) 2129 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2130 } 2131 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2132 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2133 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2134} 2135 2136 2137 2138SDOperand DAGCombiner::visitFADD(SDNode *N) { 2139 SDOperand N0 = N->getOperand(0); 2140 SDOperand N1 = N->getOperand(1); 2141 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2142 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2143 MVT::ValueType VT = N->getValueType(0); 2144 2145 // fold (fadd c1, c2) -> c1+c2 2146 if (N0CFP && N1CFP) 2147 return DAG.getNode(ISD::FADD, VT, N0, N1); 2148 // canonicalize constant to RHS 2149 if (N0CFP && !N1CFP) 2150 return DAG.getNode(ISD::FADD, VT, N1, N0); 2151 // fold (A + (-B)) -> A-B 2152 if (N1.getOpcode() == ISD::FNEG) 2153 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2154 // fold ((-A) + B) -> B-A 2155 if (N0.getOpcode() == ISD::FNEG) 2156 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2157 return SDOperand(); 2158} 2159 2160SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2161 SDOperand N0 = N->getOperand(0); 2162 SDOperand N1 = N->getOperand(1); 2163 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2164 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2165 MVT::ValueType VT = N->getValueType(0); 2166 2167 // fold (fsub c1, c2) -> c1-c2 2168 if (N0CFP && N1CFP) 2169 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2170 // fold (A-(-B)) -> A+B 2171 if (N1.getOpcode() == ISD::FNEG) 2172 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2173 return SDOperand(); 2174} 2175 2176SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2177 SDOperand N0 = N->getOperand(0); 2178 SDOperand N1 = N->getOperand(1); 2179 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2180 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2181 MVT::ValueType VT = N->getValueType(0); 2182 2183 // fold (fmul c1, c2) -> c1*c2 2184 if (N0CFP && N1CFP) 2185 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2186 // canonicalize constant to RHS 2187 if (N0CFP && !N1CFP) 2188 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2189 // fold (fmul X, 2.0) -> (fadd X, X) 2190 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2191 return DAG.getNode(ISD::FADD, VT, N0, N0); 2192 return SDOperand(); 2193} 2194 2195SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2196 SDOperand N0 = N->getOperand(0); 2197 SDOperand N1 = N->getOperand(1); 2198 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2199 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2200 MVT::ValueType VT = N->getValueType(0); 2201 2202 // fold (fdiv c1, c2) -> c1/c2 2203 if (N0CFP && N1CFP) 2204 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2205 return SDOperand(); 2206} 2207 2208SDOperand DAGCombiner::visitFREM(SDNode *N) { 2209 SDOperand N0 = N->getOperand(0); 2210 SDOperand N1 = N->getOperand(1); 2211 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2212 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2213 MVT::ValueType VT = N->getValueType(0); 2214 2215 // fold (frem c1, c2) -> fmod(c1,c2) 2216 if (N0CFP && N1CFP) 2217 return DAG.getNode(ISD::FREM, VT, N0, N1); 2218 return SDOperand(); 2219} 2220 2221SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2222 SDOperand N0 = N->getOperand(0); 2223 SDOperand N1 = N->getOperand(1); 2224 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2225 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2226 MVT::ValueType VT = N->getValueType(0); 2227 2228 if (N0CFP && N1CFP) // Constant fold 2229 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2230 2231 if (N1CFP) { 2232 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2233 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2234 union { 2235 double d; 2236 int64_t i; 2237 } u; 2238 u.d = N1CFP->getValue(); 2239 if (u.i >= 0) 2240 return DAG.getNode(ISD::FABS, VT, N0); 2241 else 2242 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2243 } 2244 2245 // copysign(fabs(x), y) -> copysign(x, y) 2246 // copysign(fneg(x), y) -> copysign(x, y) 2247 // copysign(copysign(x,z), y) -> copysign(x, y) 2248 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2249 N0.getOpcode() == ISD::FCOPYSIGN) 2250 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2251 2252 // copysign(x, abs(y)) -> abs(x) 2253 if (N1.getOpcode() == ISD::FABS) 2254 return DAG.getNode(ISD::FABS, VT, N0); 2255 2256 // copysign(x, copysign(y,z)) -> copysign(x, z) 2257 if (N1.getOpcode() == ISD::FCOPYSIGN) 2258 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2259 2260 // copysign(x, fp_extend(y)) -> copysign(x, y) 2261 // copysign(x, fp_round(y)) -> copysign(x, y) 2262 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2263 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2264 2265 return SDOperand(); 2266} 2267 2268 2269 2270SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2271 SDOperand N0 = N->getOperand(0); 2272 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2273 MVT::ValueType VT = N->getValueType(0); 2274 2275 // fold (sint_to_fp c1) -> c1fp 2276 if (N0C) 2277 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2278 return SDOperand(); 2279} 2280 2281SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2282 SDOperand N0 = N->getOperand(0); 2283 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2284 MVT::ValueType VT = N->getValueType(0); 2285 2286 // fold (uint_to_fp c1) -> c1fp 2287 if (N0C) 2288 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2289 return SDOperand(); 2290} 2291 2292SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2293 SDOperand N0 = N->getOperand(0); 2294 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2295 MVT::ValueType VT = N->getValueType(0); 2296 2297 // fold (fp_to_sint c1fp) -> c1 2298 if (N0CFP) 2299 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2300 return SDOperand(); 2301} 2302 2303SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2304 SDOperand N0 = N->getOperand(0); 2305 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2306 MVT::ValueType VT = N->getValueType(0); 2307 2308 // fold (fp_to_uint c1fp) -> c1 2309 if (N0CFP) 2310 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2311 return SDOperand(); 2312} 2313 2314SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2315 SDOperand N0 = N->getOperand(0); 2316 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2317 MVT::ValueType VT = N->getValueType(0); 2318 2319 // fold (fp_round c1fp) -> c1fp 2320 if (N0CFP) 2321 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2322 2323 // fold (fp_round (fp_extend x)) -> x 2324 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2325 return N0.getOperand(0); 2326 2327 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2328 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2329 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2330 AddToWorkList(Tmp.Val); 2331 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2332 } 2333 2334 return SDOperand(); 2335} 2336 2337SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2338 SDOperand N0 = N->getOperand(0); 2339 MVT::ValueType VT = N->getValueType(0); 2340 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2341 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2342 2343 // fold (fp_round_inreg c1fp) -> c1fp 2344 if (N0CFP) { 2345 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2346 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2347 } 2348 return SDOperand(); 2349} 2350 2351SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2352 SDOperand N0 = N->getOperand(0); 2353 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2354 MVT::ValueType VT = N->getValueType(0); 2355 2356 // fold (fp_extend c1fp) -> c1fp 2357 if (N0CFP) 2358 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2359 return SDOperand(); 2360} 2361 2362SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2363 SDOperand N0 = N->getOperand(0); 2364 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2365 MVT::ValueType VT = N->getValueType(0); 2366 2367 // fold (fneg c1) -> -c1 2368 if (N0CFP) 2369 return DAG.getNode(ISD::FNEG, VT, N0); 2370 // fold (fneg (sub x, y)) -> (sub y, x) 2371 if (N0.getOpcode() == ISD::SUB) 2372 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2373 // fold (fneg (fneg x)) -> x 2374 if (N0.getOpcode() == ISD::FNEG) 2375 return N0.getOperand(0); 2376 return SDOperand(); 2377} 2378 2379SDOperand DAGCombiner::visitFABS(SDNode *N) { 2380 SDOperand N0 = N->getOperand(0); 2381 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2382 MVT::ValueType VT = N->getValueType(0); 2383 2384 // fold (fabs c1) -> fabs(c1) 2385 if (N0CFP) 2386 return DAG.getNode(ISD::FABS, VT, N0); 2387 // fold (fabs (fabs x)) -> (fabs x) 2388 if (N0.getOpcode() == ISD::FABS) 2389 return N->getOperand(0); 2390 // fold (fabs (fneg x)) -> (fabs x) 2391 // fold (fabs (fcopysign x, y)) -> (fabs x) 2392 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2393 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2394 2395 return SDOperand(); 2396} 2397 2398SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2399 SDOperand Chain = N->getOperand(0); 2400 SDOperand N1 = N->getOperand(1); 2401 SDOperand N2 = N->getOperand(2); 2402 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2403 2404 // never taken branch, fold to chain 2405 if (N1C && N1C->isNullValue()) 2406 return Chain; 2407 // unconditional branch 2408 if (N1C && N1C->getValue() == 1) 2409 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2410 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2411 // on the target. 2412 if (N1.getOpcode() == ISD::SETCC && 2413 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2414 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2415 N1.getOperand(0), N1.getOperand(1), N2); 2416 } 2417 return SDOperand(); 2418} 2419 2420// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2421// 2422SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2423 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2424 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2425 2426 // Use SimplifySetCC to simplify SETCC's. 2427 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2428 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2429 2430 // fold br_cc true, dest -> br dest (unconditional branch) 2431 if (SCCC && SCCC->getValue()) 2432 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2433 N->getOperand(4)); 2434 // fold br_cc false, dest -> unconditional fall through 2435 if (SCCC && SCCC->isNullValue()) 2436 return N->getOperand(0); 2437 // fold to a simpler setcc 2438 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2439 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2440 Simp.getOperand(2), Simp.getOperand(0), 2441 Simp.getOperand(1), N->getOperand(4)); 2442 return SDOperand(); 2443} 2444 2445SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2446 SDOperand Chain = N->getOperand(0); 2447 SDOperand Ptr = N->getOperand(1); 2448 SDOperand SrcValue = N->getOperand(2); 2449 2450 // If there are no uses of the loaded value, change uses of the chain value 2451 // into uses of the chain input (i.e. delete the dead load). 2452 if (N->hasNUsesOfValue(0, 0)) 2453 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2454 2455 // If this load is directly stored, replace the load value with the stored 2456 // value. 2457 // TODO: Handle store large -> read small portion. 2458 // TODO: Handle TRUNCSTORE/EXTLOAD 2459 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2460 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2461 return CombineTo(N, Chain.getOperand(1), Chain); 2462 2463 return SDOperand(); 2464} 2465 2466/// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD. 2467SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) { 2468 SDOperand Chain = N->getOperand(0); 2469 SDOperand Ptr = N->getOperand(1); 2470 SDOperand SrcValue = N->getOperand(2); 2471 SDOperand EVT = N->getOperand(3); 2472 2473 // If there are no uses of the loaded value, change uses of the chain value 2474 // into uses of the chain input (i.e. delete the dead load). 2475 if (N->hasNUsesOfValue(0, 0)) 2476 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2477 2478 return SDOperand(); 2479} 2480 2481SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2482 SDOperand Chain = N->getOperand(0); 2483 SDOperand Value = N->getOperand(1); 2484 SDOperand Ptr = N->getOperand(2); 2485 SDOperand SrcValue = N->getOperand(3); 2486 2487 // If this is a store that kills a previous store, remove the previous store. 2488 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2489 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2490 // Make sure that these stores are the same value type: 2491 // FIXME: we really care that the second store is >= size of the first. 2492 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2493 // Create a new store of Value that replaces both stores. 2494 SDNode *PrevStore = Chain.Val; 2495 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2496 return Chain; 2497 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2498 PrevStore->getOperand(0), Value, Ptr, 2499 SrcValue); 2500 CombineTo(N, NewStore); // Nuke this store. 2501 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2502 return SDOperand(N, 0); 2503 } 2504 2505 // If this is a store of a bit convert, store the input value. 2506 // FIXME: This needs to know that the resultant store does not need a 2507 // higher alignment than the original. 2508 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2509 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2510 Ptr, SrcValue); 2511 2512 return SDOperand(); 2513} 2514 2515SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 2516 SDOperand InVec = N->getOperand(0); 2517 SDOperand InVal = N->getOperand(1); 2518 SDOperand EltNo = N->getOperand(2); 2519 2520 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 2521 // vector with the inserted element. 2522 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2523 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2524 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2525 if (Elt < Ops.size()) 2526 Ops[Elt] = InVal; 2527 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops); 2528 } 2529 2530 return SDOperand(); 2531} 2532 2533SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 2534 SDOperand InVec = N->getOperand(0); 2535 SDOperand InVal = N->getOperand(1); 2536 SDOperand EltNo = N->getOperand(2); 2537 SDOperand NumElts = N->getOperand(3); 2538 SDOperand EltType = N->getOperand(4); 2539 2540 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 2541 // vector with the inserted element. 2542 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2543 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2544 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2545 if (Elt < Ops.size()-2) 2546 Ops[Elt] = InVal; 2547 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops); 2548 } 2549 2550 return SDOperand(); 2551} 2552 2553SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 2554 unsigned NumInScalars = N->getNumOperands()-2; 2555 SDOperand NumElts = N->getOperand(NumInScalars); 2556 SDOperand EltType = N->getOperand(NumInScalars+1); 2557 2558 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 2559 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 2560 // two distinct vectors, turn this into a shuffle node. 2561 SDOperand VecIn1, VecIn2; 2562 for (unsigned i = 0; i != NumInScalars; ++i) { 2563 // Ignore undef inputs. 2564 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 2565 2566 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 2567 // constant index, bail out. 2568 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 2569 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 2570 VecIn1 = VecIn2 = SDOperand(0, 0); 2571 break; 2572 } 2573 2574 // If the input vector type disagrees with the result of the vbuild_vector, 2575 // we can't make a shuffle. 2576 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 2577 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 2578 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 2579 VecIn1 = VecIn2 = SDOperand(0, 0); 2580 break; 2581 } 2582 2583 // Otherwise, remember this. We allow up to two distinct input vectors. 2584 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 2585 continue; 2586 2587 if (VecIn1.Val == 0) { 2588 VecIn1 = ExtractedFromVec; 2589 } else if (VecIn2.Val == 0) { 2590 VecIn2 = ExtractedFromVec; 2591 } else { 2592 // Too many inputs. 2593 VecIn1 = VecIn2 = SDOperand(0, 0); 2594 break; 2595 } 2596 } 2597 2598 // If everything is good, we can make a shuffle operation. 2599 if (VecIn1.Val) { 2600 std::vector<SDOperand> BuildVecIndices; 2601 for (unsigned i = 0; i != NumInScalars; ++i) { 2602 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 2603 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 2604 continue; 2605 } 2606 2607 SDOperand Extract = N->getOperand(i); 2608 2609 // If extracting from the first vector, just use the index directly. 2610 if (Extract.getOperand(0) == VecIn1) { 2611 BuildVecIndices.push_back(Extract.getOperand(1)); 2612 continue; 2613 } 2614 2615 // Otherwise, use InIdx + VecSize 2616 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 2617 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32)); 2618 } 2619 2620 // Add count and size info. 2621 BuildVecIndices.push_back(NumElts); 2622 BuildVecIndices.push_back(DAG.getValueType(MVT::i32)); 2623 2624 // Return the new VVECTOR_SHUFFLE node. 2625 std::vector<SDOperand> Ops; 2626 Ops.push_back(VecIn1); 2627 if (VecIn2.Val) { 2628 Ops.push_back(VecIn2); 2629 } else { 2630 // Use an undef vbuild_vector as input for the second operand. 2631 std::vector<SDOperand> UnOps(NumInScalars, 2632 DAG.getNode(ISD::UNDEF, 2633 cast<VTSDNode>(EltType)->getVT())); 2634 UnOps.push_back(NumElts); 2635 UnOps.push_back(EltType); 2636 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps)); 2637 } 2638 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices)); 2639 Ops.push_back(NumElts); 2640 Ops.push_back(EltType); 2641 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops); 2642 } 2643 2644 return SDOperand(); 2645} 2646 2647SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 2648 SDOperand ShufMask = N->getOperand(2); 2649 unsigned NumElts = ShufMask.getNumOperands(); 2650 2651 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2652 bool isIdentity = true; 2653 for (unsigned i = 0; i != NumElts; ++i) { 2654 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2655 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2656 isIdentity = false; 2657 break; 2658 } 2659 } 2660 if (isIdentity) return N->getOperand(0); 2661 2662 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2663 isIdentity = true; 2664 for (unsigned i = 0; i != NumElts; ++i) { 2665 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2666 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2667 isIdentity = false; 2668 break; 2669 } 2670 } 2671 if (isIdentity) return N->getOperand(1); 2672 2673 // If the LHS and the RHS are the same node, turn the RHS into an undef. 2674 if (N->getOperand(0) == N->getOperand(1)) { 2675 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 2676 // first operand. 2677 std::vector<SDOperand> MappedOps; 2678 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 2679 if (cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() >= NumElts) { 2680 unsigned NewIdx = 2681 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 2682 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 2683 } else { 2684 MappedOps.push_back(ShufMask.getOperand(i)); 2685 } 2686 } 2687 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 2688 MappedOps); 2689 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 2690 N->getOperand(0), 2691 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 2692 ShufMask); 2693 } 2694 2695 return SDOperand(); 2696} 2697 2698SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 2699 SDOperand ShufMask = N->getOperand(2); 2700 unsigned NumElts = ShufMask.getNumOperands()-2; 2701 2702 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2703 bool isIdentity = true; 2704 for (unsigned i = 0; i != NumElts; ++i) { 2705 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2706 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2707 isIdentity = false; 2708 break; 2709 } 2710 } 2711 if (isIdentity) return N->getOperand(0); 2712 2713 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2714 isIdentity = true; 2715 for (unsigned i = 0; i != NumElts; ++i) { 2716 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2717 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2718 isIdentity = false; 2719 break; 2720 } 2721 } 2722 if (isIdentity) return N->getOperand(1); 2723 2724 return SDOperand(); 2725} 2726 2727/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 2728/// the scalar operation of the vop if it is operating on an integer vector 2729/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 2730SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 2731 ISD::NodeType FPOp) { 2732 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 2733 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 2734 SDOperand LHS = N->getOperand(0); 2735 SDOperand RHS = N->getOperand(1); 2736 2737 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 2738 // this operation. 2739 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 2740 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 2741 std::vector<SDOperand> Ops; 2742 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 2743 SDOperand LHSOp = LHS.getOperand(i); 2744 SDOperand RHSOp = RHS.getOperand(i); 2745 // If these two elements can't be folded, bail out. 2746 if ((LHSOp.getOpcode() != ISD::UNDEF && 2747 LHSOp.getOpcode() != ISD::Constant && 2748 LHSOp.getOpcode() != ISD::ConstantFP) || 2749 (RHSOp.getOpcode() != ISD::UNDEF && 2750 RHSOp.getOpcode() != ISD::Constant && 2751 RHSOp.getOpcode() != ISD::ConstantFP)) 2752 break; 2753 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 2754 assert((Ops.back().getOpcode() == ISD::UNDEF || 2755 Ops.back().getOpcode() == ISD::Constant || 2756 Ops.back().getOpcode() == ISD::ConstantFP) && 2757 "Scalar binop didn't fold!"); 2758 } 2759 2760 if (Ops.size() == LHS.getNumOperands()-2) { 2761 Ops.push_back(*(LHS.Val->op_end()-2)); 2762 Ops.push_back(*(LHS.Val->op_end()-1)); 2763 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2764 } 2765 } 2766 2767 return SDOperand(); 2768} 2769 2770SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2771 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2772 2773 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2774 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2775 // If we got a simplified select_cc node back from SimplifySelectCC, then 2776 // break it down into a new SETCC node, and a new SELECT node, and then return 2777 // the SELECT node, since we were called with a SELECT node. 2778 if (SCC.Val) { 2779 // Check to see if we got a select_cc back (to turn into setcc/select). 2780 // Otherwise, just return whatever node we got back, like fabs. 2781 if (SCC.getOpcode() == ISD::SELECT_CC) { 2782 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2783 SCC.getOperand(0), SCC.getOperand(1), 2784 SCC.getOperand(4)); 2785 AddToWorkList(SETCC.Val); 2786 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2787 SCC.getOperand(3), SETCC); 2788 } 2789 return SCC; 2790 } 2791 return SDOperand(); 2792} 2793 2794/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2795/// are the two values being selected between, see if we can simplify the 2796/// select. 2797/// 2798bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2799 SDOperand RHS) { 2800 2801 // If this is a select from two identical things, try to pull the operation 2802 // through the select. 2803 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2804#if 0 2805 std::cerr << "SELECT: ["; LHS.Val->dump(); 2806 std::cerr << "] ["; RHS.Val->dump(); 2807 std::cerr << "]\n"; 2808#endif 2809 2810 // If this is a load and the token chain is identical, replace the select 2811 // of two loads with a load through a select of the address to load from. 2812 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2813 // constants have been dropped into the constant pool. 2814 if ((LHS.getOpcode() == ISD::LOAD || 2815 LHS.getOpcode() == ISD::EXTLOAD || 2816 LHS.getOpcode() == ISD::ZEXTLOAD || 2817 LHS.getOpcode() == ISD::SEXTLOAD) && 2818 // Token chains must be identical. 2819 LHS.getOperand(0) == RHS.getOperand(0) && 2820 // If this is an EXTLOAD, the VT's must match. 2821 (LHS.getOpcode() == ISD::LOAD || 2822 LHS.getOperand(3) == RHS.getOperand(3))) { 2823 // FIXME: this conflates two src values, discarding one. This is not 2824 // the right thing to do, but nothing uses srcvalues now. When they do, 2825 // turn SrcValue into a list of locations. 2826 SDOperand Addr; 2827 if (TheSelect->getOpcode() == ISD::SELECT) 2828 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2829 TheSelect->getOperand(0), LHS.getOperand(1), 2830 RHS.getOperand(1)); 2831 else 2832 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2833 TheSelect->getOperand(0), 2834 TheSelect->getOperand(1), 2835 LHS.getOperand(1), RHS.getOperand(1), 2836 TheSelect->getOperand(4)); 2837 2838 SDOperand Load; 2839 if (LHS.getOpcode() == ISD::LOAD) 2840 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2841 Addr, LHS.getOperand(2)); 2842 else 2843 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2844 LHS.getOperand(0), Addr, LHS.getOperand(2), 2845 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2846 // Users of the select now use the result of the load. 2847 CombineTo(TheSelect, Load); 2848 2849 // Users of the old loads now use the new load's chain. We know the 2850 // old-load value is dead now. 2851 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2852 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2853 return true; 2854 } 2855 } 2856 2857 return false; 2858} 2859 2860SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2861 SDOperand N2, SDOperand N3, 2862 ISD::CondCode CC) { 2863 2864 MVT::ValueType VT = N2.getValueType(); 2865 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2866 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2867 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2868 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2869 2870 // Determine if the condition we're dealing with is constant 2871 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2872 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2873 2874 // fold select_cc true, x, y -> x 2875 if (SCCC && SCCC->getValue()) 2876 return N2; 2877 // fold select_cc false, x, y -> y 2878 if (SCCC && SCCC->getValue() == 0) 2879 return N3; 2880 2881 // Check to see if we can simplify the select into an fabs node 2882 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2883 // Allow either -0.0 or 0.0 2884 if (CFP->getValue() == 0.0) { 2885 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2886 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2887 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2888 N2 == N3.getOperand(0)) 2889 return DAG.getNode(ISD::FABS, VT, N0); 2890 2891 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2892 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2893 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2894 N2.getOperand(0) == N3) 2895 return DAG.getNode(ISD::FABS, VT, N3); 2896 } 2897 } 2898 2899 // Check to see if we can perform the "gzip trick", transforming 2900 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2901 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2902 MVT::isInteger(N0.getValueType()) && 2903 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2904 MVT::ValueType XType = N0.getValueType(); 2905 MVT::ValueType AType = N2.getValueType(); 2906 if (XType >= AType) { 2907 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2908 // single-bit constant. 2909 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2910 unsigned ShCtV = Log2_64(N2C->getValue()); 2911 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 2912 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 2913 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 2914 AddToWorkList(Shift.Val); 2915 if (XType > AType) { 2916 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2917 AddToWorkList(Shift.Val); 2918 } 2919 return DAG.getNode(ISD::AND, AType, Shift, N2); 2920 } 2921 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2922 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2923 TLI.getShiftAmountTy())); 2924 AddToWorkList(Shift.Val); 2925 if (XType > AType) { 2926 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2927 AddToWorkList(Shift.Val); 2928 } 2929 return DAG.getNode(ISD::AND, AType, Shift, N2); 2930 } 2931 } 2932 2933 // fold select C, 16, 0 -> shl C, 4 2934 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 2935 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 2936 // Get a SetCC of the condition 2937 // FIXME: Should probably make sure that setcc is legal if we ever have a 2938 // target where it isn't. 2939 SDOperand Temp, SCC; 2940 // cast from setcc result type to select result type 2941 if (AfterLegalize) { 2942 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2943 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 2944 } else { 2945 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 2946 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 2947 } 2948 AddToWorkList(SCC.Val); 2949 AddToWorkList(Temp.Val); 2950 // shl setcc result by log2 n2c 2951 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 2952 DAG.getConstant(Log2_64(N2C->getValue()), 2953 TLI.getShiftAmountTy())); 2954 } 2955 2956 // Check to see if this is the equivalent of setcc 2957 // FIXME: Turn all of these into setcc if setcc if setcc is legal 2958 // otherwise, go ahead with the folds. 2959 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 2960 MVT::ValueType XType = N0.getValueType(); 2961 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 2962 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2963 if (Res.getValueType() != VT) 2964 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 2965 return Res; 2966 } 2967 2968 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 2969 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 2970 TLI.isOperationLegal(ISD::CTLZ, XType)) { 2971 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 2972 return DAG.getNode(ISD::SRL, XType, Ctlz, 2973 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 2974 TLI.getShiftAmountTy())); 2975 } 2976 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 2977 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 2978 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 2979 N0); 2980 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 2981 DAG.getConstant(~0ULL, XType)); 2982 return DAG.getNode(ISD::SRL, XType, 2983 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 2984 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2985 TLI.getShiftAmountTy())); 2986 } 2987 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 2988 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 2989 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 2990 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2991 TLI.getShiftAmountTy())); 2992 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 2993 } 2994 } 2995 2996 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 2997 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2998 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 2999 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 3000 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 3001 MVT::ValueType XType = N0.getValueType(); 3002 if (SubC->isNullValue() && MVT::isInteger(XType)) { 3003 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3004 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3005 TLI.getShiftAmountTy())); 3006 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 3007 AddToWorkList(Shift.Val); 3008 AddToWorkList(Add.Val); 3009 return DAG.getNode(ISD::XOR, XType, Add, Shift); 3010 } 3011 } 3012 } 3013 3014 return SDOperand(); 3015} 3016 3017SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 3018 SDOperand N1, ISD::CondCode Cond, 3019 bool foldBooleans) { 3020 // These setcc operations always fold. 3021 switch (Cond) { 3022 default: break; 3023 case ISD::SETFALSE: 3024 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 3025 case ISD::SETTRUE: 3026 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 3027 } 3028 3029 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 3030 uint64_t C1 = N1C->getValue(); 3031 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 3032 uint64_t C0 = N0C->getValue(); 3033 3034 // Sign extend the operands if required 3035 if (ISD::isSignedIntSetCC(Cond)) { 3036 C0 = N0C->getSignExtended(); 3037 C1 = N1C->getSignExtended(); 3038 } 3039 3040 switch (Cond) { 3041 default: assert(0 && "Unknown integer setcc!"); 3042 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3043 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3044 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 3045 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 3046 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 3047 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 3048 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 3049 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 3050 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 3051 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 3052 } 3053 } else { 3054 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 3055 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 3056 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 3057 3058 // If the comparison constant has bits in the upper part, the 3059 // zero-extended value could never match. 3060 if (C1 & (~0ULL << InSize)) { 3061 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 3062 switch (Cond) { 3063 case ISD::SETUGT: 3064 case ISD::SETUGE: 3065 case ISD::SETEQ: return DAG.getConstant(0, VT); 3066 case ISD::SETULT: 3067 case ISD::SETULE: 3068 case ISD::SETNE: return DAG.getConstant(1, VT); 3069 case ISD::SETGT: 3070 case ISD::SETGE: 3071 // True if the sign bit of C1 is set. 3072 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 3073 case ISD::SETLT: 3074 case ISD::SETLE: 3075 // True if the sign bit of C1 isn't set. 3076 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 3077 default: 3078 break; 3079 } 3080 } 3081 3082 // Otherwise, we can perform the comparison with the low bits. 3083 switch (Cond) { 3084 case ISD::SETEQ: 3085 case ISD::SETNE: 3086 case ISD::SETUGT: 3087 case ISD::SETUGE: 3088 case ISD::SETULT: 3089 case ISD::SETULE: 3090 return DAG.getSetCC(VT, N0.getOperand(0), 3091 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 3092 Cond); 3093 default: 3094 break; // todo, be more careful with signed comparisons 3095 } 3096 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3097 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 3098 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 3099 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 3100 MVT::ValueType ExtDstTy = N0.getValueType(); 3101 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 3102 3103 // If the extended part has any inconsistent bits, it cannot ever 3104 // compare equal. In other words, they have to be all ones or all 3105 // zeros. 3106 uint64_t ExtBits = 3107 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 3108 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 3109 return DAG.getConstant(Cond == ISD::SETNE, VT); 3110 3111 SDOperand ZextOp; 3112 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 3113 if (Op0Ty == ExtSrcTy) { 3114 ZextOp = N0.getOperand(0); 3115 } else { 3116 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 3117 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 3118 DAG.getConstant(Imm, Op0Ty)); 3119 } 3120 AddToWorkList(ZextOp.Val); 3121 // Otherwise, make this a use of a zext. 3122 return DAG.getSetCC(VT, ZextOp, 3123 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 3124 ExtDstTy), 3125 Cond); 3126 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 3127 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3128 (N0.getOpcode() == ISD::XOR || 3129 (N0.getOpcode() == ISD::AND && 3130 N0.getOperand(0).getOpcode() == ISD::XOR && 3131 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 3132 isa<ConstantSDNode>(N0.getOperand(1)) && 3133 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 3134 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 3135 // only do this if the top bits are known zero. 3136 if (TLI.MaskedValueIsZero(N1, 3137 MVT::getIntVTBitMask(N0.getValueType())-1)) { 3138 // Okay, get the un-inverted input value. 3139 SDOperand Val; 3140 if (N0.getOpcode() == ISD::XOR) 3141 Val = N0.getOperand(0); 3142 else { 3143 assert(N0.getOpcode() == ISD::AND && 3144 N0.getOperand(0).getOpcode() == ISD::XOR); 3145 // ((X^1)&1)^1 -> X & 1 3146 Val = DAG.getNode(ISD::AND, N0.getValueType(), 3147 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 3148 } 3149 return DAG.getSetCC(VT, Val, N1, 3150 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 3151 } 3152 } 3153 3154 uint64_t MinVal, MaxVal; 3155 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 3156 if (ISD::isSignedIntSetCC(Cond)) { 3157 MinVal = 1ULL << (OperandBitSize-1); 3158 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 3159 MaxVal = ~0ULL >> (65-OperandBitSize); 3160 else 3161 MaxVal = 0; 3162 } else { 3163 MinVal = 0; 3164 MaxVal = ~0ULL >> (64-OperandBitSize); 3165 } 3166 3167 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 3168 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 3169 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 3170 --C1; // X >= C0 --> X > (C0-1) 3171 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3172 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 3173 } 3174 3175 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 3176 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 3177 ++C1; // X <= C0 --> X < (C0+1) 3178 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3179 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 3180 } 3181 3182 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 3183 return DAG.getConstant(0, VT); // X < MIN --> false 3184 3185 // Canonicalize setgt X, Min --> setne X, Min 3186 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 3187 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3188 // Canonicalize setlt X, Max --> setne X, Max 3189 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 3190 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3191 3192 // If we have setult X, 1, turn it into seteq X, 0 3193 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 3194 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 3195 ISD::SETEQ); 3196 // If we have setugt X, Max-1, turn it into seteq X, Max 3197 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 3198 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 3199 ISD::SETEQ); 3200 3201 // If we have "setcc X, C0", check to see if we can shrink the immediate 3202 // by changing cc. 3203 3204 // SETUGT X, SINTMAX -> SETLT X, 0 3205 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 3206 C1 == (~0ULL >> (65-OperandBitSize))) 3207 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 3208 ISD::SETLT); 3209 3210 // FIXME: Implement the rest of these. 3211 3212 // Fold bit comparisons when we can. 3213 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3214 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 3215 if (ConstantSDNode *AndRHS = 3216 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3217 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 3218 // Perform the xform if the AND RHS is a single bit. 3219 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 3220 return DAG.getNode(ISD::SRL, VT, N0, 3221 DAG.getConstant(Log2_64(AndRHS->getValue()), 3222 TLI.getShiftAmountTy())); 3223 } 3224 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 3225 // (X & 8) == 8 --> (X & 8) >> 3 3226 // Perform the xform if C1 is a single bit. 3227 if ((C1 & (C1-1)) == 0) { 3228 return DAG.getNode(ISD::SRL, VT, N0, 3229 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 3230 } 3231 } 3232 } 3233 } 3234 } else if (isa<ConstantSDNode>(N0.Val)) { 3235 // Ensure that the constant occurs on the RHS. 3236 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3237 } 3238 3239 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 3240 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 3241 double C0 = N0C->getValue(), C1 = N1C->getValue(); 3242 3243 switch (Cond) { 3244 default: break; // FIXME: Implement the rest of these! 3245 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3246 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3247 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 3248 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 3249 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 3250 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 3251 } 3252 } else { 3253 // Ensure that the constant occurs on the RHS. 3254 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3255 } 3256 3257 if (N0 == N1) { 3258 // We can always fold X == Y for integer setcc's. 3259 if (MVT::isInteger(N0.getValueType())) 3260 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3261 unsigned UOF = ISD::getUnorderedFlavor(Cond); 3262 if (UOF == 2) // FP operators that are undefined on NaNs. 3263 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3264 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 3265 return DAG.getConstant(UOF, VT); 3266 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 3267 // if it is not already. 3268 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 3269 if (NewCond != Cond) 3270 return DAG.getSetCC(VT, N0, N1, NewCond); 3271 } 3272 3273 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3274 MVT::isInteger(N0.getValueType())) { 3275 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 3276 N0.getOpcode() == ISD::XOR) { 3277 // Simplify (X+Y) == (X+Z) --> Y == Z 3278 if (N0.getOpcode() == N1.getOpcode()) { 3279 if (N0.getOperand(0) == N1.getOperand(0)) 3280 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 3281 if (N0.getOperand(1) == N1.getOperand(1)) 3282 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 3283 if (isCommutativeBinOp(N0.getOpcode())) { 3284 // If X op Y == Y op X, try other combinations. 3285 if (N0.getOperand(0) == N1.getOperand(1)) 3286 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 3287 if (N0.getOperand(1) == N1.getOperand(0)) 3288 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 3289 } 3290 } 3291 3292 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 3293 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3294 // Turn (X+C1) == C2 --> X == C2-C1 3295 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 3296 return DAG.getSetCC(VT, N0.getOperand(0), 3297 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 3298 N0.getValueType()), Cond); 3299 } 3300 3301 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 3302 if (N0.getOpcode() == ISD::XOR) 3303 // If we know that all of the inverted bits are zero, don't bother 3304 // performing the inversion. 3305 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 3306 return DAG.getSetCC(VT, N0.getOperand(0), 3307 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 3308 N0.getValueType()), Cond); 3309 } 3310 3311 // Turn (C1-X) == C2 --> X == C1-C2 3312 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 3313 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 3314 return DAG.getSetCC(VT, N0.getOperand(1), 3315 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 3316 N0.getValueType()), Cond); 3317 } 3318 } 3319 } 3320 3321 // Simplify (X+Z) == X --> Z == 0 3322 if (N0.getOperand(0) == N1) 3323 return DAG.getSetCC(VT, N0.getOperand(1), 3324 DAG.getConstant(0, N0.getValueType()), Cond); 3325 if (N0.getOperand(1) == N1) { 3326 if (isCommutativeBinOp(N0.getOpcode())) 3327 return DAG.getSetCC(VT, N0.getOperand(0), 3328 DAG.getConstant(0, N0.getValueType()), Cond); 3329 else { 3330 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 3331 // (Z-X) == X --> Z == X<<1 3332 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 3333 N1, 3334 DAG.getConstant(1,TLI.getShiftAmountTy())); 3335 AddToWorkList(SH.Val); 3336 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 3337 } 3338 } 3339 } 3340 3341 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 3342 N1.getOpcode() == ISD::XOR) { 3343 // Simplify X == (X+Z) --> Z == 0 3344 if (N1.getOperand(0) == N0) { 3345 return DAG.getSetCC(VT, N1.getOperand(1), 3346 DAG.getConstant(0, N1.getValueType()), Cond); 3347 } else if (N1.getOperand(1) == N0) { 3348 if (isCommutativeBinOp(N1.getOpcode())) { 3349 return DAG.getSetCC(VT, N1.getOperand(0), 3350 DAG.getConstant(0, N1.getValueType()), Cond); 3351 } else { 3352 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 3353 // X == (Z-X) --> X<<1 == Z 3354 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 3355 DAG.getConstant(1,TLI.getShiftAmountTy())); 3356 AddToWorkList(SH.Val); 3357 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 3358 } 3359 } 3360 } 3361 } 3362 3363 // Fold away ALL boolean setcc's. 3364 SDOperand Temp; 3365 if (N0.getValueType() == MVT::i1 && foldBooleans) { 3366 switch (Cond) { 3367 default: assert(0 && "Unknown integer setcc!"); 3368 case ISD::SETEQ: // X == Y -> (X^Y)^1 3369 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3370 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 3371 AddToWorkList(Temp.Val); 3372 break; 3373 case ISD::SETNE: // X != Y --> (X^Y) 3374 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3375 break; 3376 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 3377 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 3378 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3379 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 3380 AddToWorkList(Temp.Val); 3381 break; 3382 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 3383 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 3384 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3385 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 3386 AddToWorkList(Temp.Val); 3387 break; 3388 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 3389 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 3390 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3391 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 3392 AddToWorkList(Temp.Val); 3393 break; 3394 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 3395 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 3396 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3397 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 3398 break; 3399 } 3400 if (VT != MVT::i1) { 3401 AddToWorkList(N0.Val); 3402 // FIXME: If running after legalize, we probably can't do this. 3403 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3404 } 3405 return N0; 3406 } 3407 3408 // Could not fold it. 3409 return SDOperand(); 3410} 3411 3412/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3413/// return a DAG expression to select that will generate the same value by 3414/// multiplying by a magic number. See: 3415/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3416SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 3417 MVT::ValueType VT = N->getValueType(0); 3418 3419 // Check to see if we can do this. 3420 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 3421 return SDOperand(); // BuildSDIV only operates on i32 or i64 3422 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 3423 return SDOperand(); // Make sure the target supports MULHS. 3424 3425 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 3426 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 3427 3428 // Multiply the numerator (operand 0) by the magic value 3429 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 3430 DAG.getConstant(magics.m, VT)); 3431 // If d > 0 and m < 0, add the numerator 3432 if (d > 0 && magics.m < 0) { 3433 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 3434 AddToWorkList(Q.Val); 3435 } 3436 // If d < 0 and m > 0, subtract the numerator. 3437 if (d < 0 && magics.m > 0) { 3438 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 3439 AddToWorkList(Q.Val); 3440 } 3441 // Shift right algebraic if shift value is nonzero 3442 if (magics.s > 0) { 3443 Q = DAG.getNode(ISD::SRA, VT, Q, 3444 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 3445 AddToWorkList(Q.Val); 3446 } 3447 // Extract the sign bit and add it to the quotient 3448 SDOperand T = 3449 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 3450 TLI.getShiftAmountTy())); 3451 AddToWorkList(T.Val); 3452 return DAG.getNode(ISD::ADD, VT, Q, T); 3453} 3454 3455/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3456/// return a DAG expression to select that will generate the same value by 3457/// multiplying by a magic number. See: 3458/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3459SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 3460 MVT::ValueType VT = N->getValueType(0); 3461 3462 // Check to see if we can do this. 3463 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 3464 return SDOperand(); // BuildUDIV only operates on i32 or i64 3465 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 3466 return SDOperand(); // Make sure the target supports MULHU. 3467 3468 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 3469 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 3470 3471 // Multiply the numerator (operand 0) by the magic value 3472 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 3473 DAG.getConstant(magics.m, VT)); 3474 AddToWorkList(Q.Val); 3475 3476 if (magics.a == 0) { 3477 return DAG.getNode(ISD::SRL, VT, Q, 3478 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 3479 } else { 3480 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 3481 AddToWorkList(NPQ.Val); 3482 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 3483 DAG.getConstant(1, TLI.getShiftAmountTy())); 3484 AddToWorkList(NPQ.Val); 3485 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 3486 AddToWorkList(NPQ.Val); 3487 return DAG.getNode(ISD::SRL, VT, NPQ, 3488 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 3489 } 3490} 3491 3492// SelectionDAG::Combine - This is the entry point for the file. 3493// 3494void SelectionDAG::Combine(bool RunningAfterLegalize) { 3495 /// run - This is the main entry point to this class. 3496 /// 3497 DAGCombiner(*this).Run(RunningAfterLegalize); 3498} 3499