DAGCombiner.cpp revision a7be36c8eb4717e44b05e00008544b883fc87de9
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/SmallPtrSet.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/Analysis/AliasAnalysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/IR/DataLayout.h" 27#include "llvm/IR/DerivedTypes.h" 28#include "llvm/IR/Function.h" 29#include "llvm/IR/LLVMContext.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetSubtargetInfo.h" 40#include <algorithm> 41using namespace llvm; 42 43STATISTIC(NodesCombined , "Number of dag nodes combined"); 44STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 45STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 46STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 47STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 48STATISTIC(SlicedLoads, "Number of load sliced"); 49 50namespace { 51 static cl::opt<bool> 52 CombinerAA("combiner-alias-analysis", cl::Hidden, 53 cl::desc("Turn on alias analysis during testing")); 54 55 static cl::opt<bool> 56 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 57 cl::desc("Include global information in alias analysis")); 58 59 /// Hidden option to stress test load slicing, i.e., when this option 60 /// is enabled, load slicing bypasses most of its profitability guards. 61 static cl::opt<bool> 62 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden, 63 cl::desc("Bypass the profitability model of load " 64 "slicing"), 65 cl::init(false)); 66 67//------------------------------ DAGCombiner ---------------------------------// 68 69 class DAGCombiner { 70 SelectionDAG &DAG; 71 const TargetLowering &TLI; 72 CombineLevel Level; 73 CodeGenOpt::Level OptLevel; 74 bool LegalOperations; 75 bool LegalTypes; 76 bool ForCodeSize; 77 78 // Worklist of all of the nodes that need to be simplified. 79 // 80 // This has the semantics that when adding to the worklist, 81 // the item added must be next to be processed. It should 82 // also only appear once. The naive approach to this takes 83 // linear time. 84 // 85 // To reduce the insert/remove time to logarithmic, we use 86 // a set and a vector to maintain our worklist. 87 // 88 // The set contains the items on the worklist, but does not 89 // maintain the order they should be visited. 90 // 91 // The vector maintains the order nodes should be visited, but may 92 // contain duplicate or removed nodes. When choosing a node to 93 // visit, we pop off the order stack until we find an item that is 94 // also in the contents set. All operations are O(log N). 95 SmallPtrSet<SDNode*, 64> WorkListContents; 96 SmallVector<SDNode*, 64> WorkListOrder; 97 98 // AA - Used for DAG load/store alias analysis. 99 AliasAnalysis &AA; 100 101 /// AddUsersToWorkList - When an instruction is simplified, add all users of 102 /// the instruction to the work lists because they might get more simplified 103 /// now. 104 /// 105 void AddUsersToWorkList(SDNode *N) { 106 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 107 UI != UE; ++UI) 108 AddToWorkList(*UI); 109 } 110 111 /// visit - call the node-specific routine that knows how to fold each 112 /// particular type of node. 113 SDValue visit(SDNode *N); 114 115 public: 116 /// AddToWorkList - Add to the work list making sure its instance is at the 117 /// back (next to be processed.) 118 void AddToWorkList(SDNode *N) { 119 WorkListContents.insert(N); 120 WorkListOrder.push_back(N); 121 } 122 123 /// removeFromWorkList - remove all instances of N from the worklist. 124 /// 125 void removeFromWorkList(SDNode *N) { 126 WorkListContents.erase(N); 127 } 128 129 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 130 bool AddTo = true); 131 132 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 133 return CombineTo(N, &Res, 1, AddTo); 134 } 135 136 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 137 bool AddTo = true) { 138 SDValue To[] = { Res0, Res1 }; 139 return CombineTo(N, To, 2, AddTo); 140 } 141 142 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 143 144 private: 145 146 /// SimplifyDemandedBits - Check the specified integer node value to see if 147 /// it can be simplified or if things it uses can be simplified by bit 148 /// propagation. If so, return true. 149 bool SimplifyDemandedBits(SDValue Op) { 150 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 151 APInt Demanded = APInt::getAllOnesValue(BitWidth); 152 return SimplifyDemandedBits(Op, Demanded); 153 } 154 155 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 156 157 bool CombineToPreIndexedLoadStore(SDNode *N); 158 bool CombineToPostIndexedLoadStore(SDNode *N); 159 bool SliceUpLoad(SDNode *N); 160 161 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 162 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 163 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 164 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 165 SDValue PromoteIntBinOp(SDValue Op); 166 SDValue PromoteIntShiftOp(SDValue Op); 167 SDValue PromoteExtend(SDValue Op); 168 bool PromoteLoad(SDValue Op); 169 170 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs, 171 SDValue Trunc, SDValue ExtLoad, SDLoc DL, 172 ISD::NodeType ExtType); 173 174 /// combine - call the node-specific routine that knows how to fold each 175 /// particular type of node. If that doesn't do anything, try the 176 /// target-specific DAG combines. 177 SDValue combine(SDNode *N); 178 179 // Visitation implementation - Implement dag node combining for different 180 // node types. The semantics are as follows: 181 // Return Value: 182 // SDValue.getNode() == 0 - No change was made 183 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 184 // otherwise - N should be replaced by the returned Operand. 185 // 186 SDValue visitTokenFactor(SDNode *N); 187 SDValue visitMERGE_VALUES(SDNode *N); 188 SDValue visitADD(SDNode *N); 189 SDValue visitSUB(SDNode *N); 190 SDValue visitADDC(SDNode *N); 191 SDValue visitSUBC(SDNode *N); 192 SDValue visitADDE(SDNode *N); 193 SDValue visitSUBE(SDNode *N); 194 SDValue visitMUL(SDNode *N); 195 SDValue visitSDIV(SDNode *N); 196 SDValue visitUDIV(SDNode *N); 197 SDValue visitSREM(SDNode *N); 198 SDValue visitUREM(SDNode *N); 199 SDValue visitMULHU(SDNode *N); 200 SDValue visitMULHS(SDNode *N); 201 SDValue visitSMUL_LOHI(SDNode *N); 202 SDValue visitUMUL_LOHI(SDNode *N); 203 SDValue visitSMULO(SDNode *N); 204 SDValue visitUMULO(SDNode *N); 205 SDValue visitSDIVREM(SDNode *N); 206 SDValue visitUDIVREM(SDNode *N); 207 SDValue visitAND(SDNode *N); 208 SDValue visitOR(SDNode *N); 209 SDValue visitXOR(SDNode *N); 210 SDValue SimplifyVBinOp(SDNode *N); 211 SDValue SimplifyVUnaryOp(SDNode *N); 212 SDValue visitSHL(SDNode *N); 213 SDValue visitSRA(SDNode *N); 214 SDValue visitSRL(SDNode *N); 215 SDValue visitCTLZ(SDNode *N); 216 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 217 SDValue visitCTTZ(SDNode *N); 218 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 219 SDValue visitCTPOP(SDNode *N); 220 SDValue visitSELECT(SDNode *N); 221 SDValue visitVSELECT(SDNode *N); 222 SDValue visitSELECT_CC(SDNode *N); 223 SDValue visitSETCC(SDNode *N); 224 SDValue visitSIGN_EXTEND(SDNode *N); 225 SDValue visitZERO_EXTEND(SDNode *N); 226 SDValue visitANY_EXTEND(SDNode *N); 227 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 228 SDValue visitTRUNCATE(SDNode *N); 229 SDValue visitBITCAST(SDNode *N); 230 SDValue visitBUILD_PAIR(SDNode *N); 231 SDValue visitFADD(SDNode *N); 232 SDValue visitFSUB(SDNode *N); 233 SDValue visitFMUL(SDNode *N); 234 SDValue visitFMA(SDNode *N); 235 SDValue visitFDIV(SDNode *N); 236 SDValue visitFREM(SDNode *N); 237 SDValue visitFCOPYSIGN(SDNode *N); 238 SDValue visitSINT_TO_FP(SDNode *N); 239 SDValue visitUINT_TO_FP(SDNode *N); 240 SDValue visitFP_TO_SINT(SDNode *N); 241 SDValue visitFP_TO_UINT(SDNode *N); 242 SDValue visitFP_ROUND(SDNode *N); 243 SDValue visitFP_ROUND_INREG(SDNode *N); 244 SDValue visitFP_EXTEND(SDNode *N); 245 SDValue visitFNEG(SDNode *N); 246 SDValue visitFABS(SDNode *N); 247 SDValue visitFCEIL(SDNode *N); 248 SDValue visitFTRUNC(SDNode *N); 249 SDValue visitFFLOOR(SDNode *N); 250 SDValue visitBRCOND(SDNode *N); 251 SDValue visitBR_CC(SDNode *N); 252 SDValue visitLOAD(SDNode *N); 253 SDValue visitSTORE(SDNode *N); 254 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 255 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 256 SDValue visitBUILD_VECTOR(SDNode *N); 257 SDValue visitCONCAT_VECTORS(SDNode *N); 258 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 259 SDValue visitVECTOR_SHUFFLE(SDNode *N); 260 261 SDValue XformToShuffleWithZero(SDNode *N); 262 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS); 263 264 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 265 266 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 267 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 268 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2); 269 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2, 270 SDValue N3, ISD::CondCode CC, 271 bool NotExtCompare = false); 272 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 273 SDLoc DL, bool foldBooleans = true); 274 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 275 unsigned HiOp); 276 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 277 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 278 SDValue BuildSDIV(SDNode *N); 279 SDValue BuildUDIV(SDNode *N); 280 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 281 bool DemandHighBits = true); 282 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 283 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL); 284 SDValue ReduceLoadWidth(SDNode *N); 285 SDValue ReduceLoadOpStoreWidth(SDNode *N); 286 SDValue TransformFPLoadStorePair(SDNode *N); 287 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N); 288 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N); 289 290 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 291 292 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 293 /// looking for aliasing nodes and adding them to the Aliases vector. 294 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 295 SmallVectorImpl<SDValue> &Aliases); 296 297 /// isAlias - Return true if there is any possibility that the two addresses 298 /// overlap. 299 bool isAlias(SDValue Ptr1, int64_t Size1, bool IsVolatile1, 300 const Value *SrcValue1, int SrcValueOffset1, 301 unsigned SrcValueAlign1, 302 const MDNode *TBAAInfo1, 303 SDValue Ptr2, int64_t Size2, bool IsVolatile2, 304 const Value *SrcValue2, int SrcValueOffset2, 305 unsigned SrcValueAlign2, 306 const MDNode *TBAAInfo2) const; 307 308 /// isAlias - Return true if there is any possibility that the two addresses 309 /// overlap. 310 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1); 311 312 /// FindAliasInfo - Extracts the relevant alias information from the memory 313 /// node. Returns true if the operand was a load. 314 bool FindAliasInfo(SDNode *N, 315 SDValue &Ptr, int64_t &Size, bool &IsVolatile, 316 const Value *&SrcValue, int &SrcValueOffset, 317 unsigned &SrcValueAlignment, 318 const MDNode *&TBAAInfo) const; 319 320 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 321 /// looking for a better chain (aliasing node.) 322 SDValue FindBetterChain(SDNode *N, SDValue Chain); 323 324 /// Merge consecutive store operations into a wide store. 325 /// This optimization uses wide integers or vectors when possible. 326 /// \return True if some memory operations were changed. 327 bool MergeConsecutiveStores(StoreSDNode *N); 328 329 public: 330 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 331 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 332 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) { 333 AttributeSet FnAttrs = 334 DAG.getMachineFunction().getFunction()->getAttributes(); 335 ForCodeSize = 336 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, 337 Attribute::OptimizeForSize) || 338 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize); 339 } 340 341 /// Run - runs the dag combiner on all nodes in the work list 342 void Run(CombineLevel AtLevel); 343 344 SelectionDAG &getDAG() const { return DAG; } 345 346 /// getShiftAmountTy - Returns a type large enough to hold any valid 347 /// shift amount - before type legalization these can be huge. 348 EVT getShiftAmountTy(EVT LHSTy) { 349 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 350 if (LHSTy.isVector()) 351 return LHSTy; 352 return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy) 353 : TLI.getPointerTy(); 354 } 355 356 /// isTypeLegal - This method returns true if we are running before type 357 /// legalization or if the specified VT is legal. 358 bool isTypeLegal(const EVT &VT) { 359 if (!LegalTypes) return true; 360 return TLI.isTypeLegal(VT); 361 } 362 363 /// getSetCCResultType - Convenience wrapper around 364 /// TargetLowering::getSetCCResultType 365 EVT getSetCCResultType(EVT VT) const { 366 return TLI.getSetCCResultType(*DAG.getContext(), VT); 367 } 368 }; 369} 370 371 372namespace { 373/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 374/// nodes from the worklist. 375class WorkListRemover : public SelectionDAG::DAGUpdateListener { 376 DAGCombiner &DC; 377public: 378 explicit WorkListRemover(DAGCombiner &dc) 379 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 380 381 virtual void NodeDeleted(SDNode *N, SDNode *E) { 382 DC.removeFromWorkList(N); 383 } 384}; 385} 386 387//===----------------------------------------------------------------------===// 388// TargetLowering::DAGCombinerInfo implementation 389//===----------------------------------------------------------------------===// 390 391void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 392 ((DAGCombiner*)DC)->AddToWorkList(N); 393} 394 395void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 396 ((DAGCombiner*)DC)->removeFromWorkList(N); 397} 398 399SDValue TargetLowering::DAGCombinerInfo:: 400CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 401 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 402} 403 404SDValue TargetLowering::DAGCombinerInfo:: 405CombineTo(SDNode *N, SDValue Res, bool AddTo) { 406 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 407} 408 409 410SDValue TargetLowering::DAGCombinerInfo:: 411CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 412 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 413} 414 415void TargetLowering::DAGCombinerInfo:: 416CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 417 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 418} 419 420//===----------------------------------------------------------------------===// 421// Helper Functions 422//===----------------------------------------------------------------------===// 423 424/// isNegatibleForFree - Return 1 if we can compute the negated form of the 425/// specified expression for the same cost as the expression itself, or 2 if we 426/// can compute the negated form more cheaply than the expression itself. 427static char isNegatibleForFree(SDValue Op, bool LegalOperations, 428 const TargetLowering &TLI, 429 const TargetOptions *Options, 430 unsigned Depth = 0) { 431 // fneg is removable even if it has multiple uses. 432 if (Op.getOpcode() == ISD::FNEG) return 2; 433 434 // Don't allow anything with multiple uses. 435 if (!Op.hasOneUse()) return 0; 436 437 // Don't recurse exponentially. 438 if (Depth > 6) return 0; 439 440 switch (Op.getOpcode()) { 441 default: return false; 442 case ISD::ConstantFP: 443 // Don't invert constant FP values after legalize. The negated constant 444 // isn't necessarily legal. 445 return LegalOperations ? 0 : 1; 446 case ISD::FADD: 447 // FIXME: determine better conditions for this xform. 448 if (!Options->UnsafeFPMath) return 0; 449 450 // After operation legalization, it might not be legal to create new FSUBs. 451 if (LegalOperations && 452 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 453 return 0; 454 455 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 456 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 457 Options, Depth + 1)) 458 return V; 459 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 460 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 461 Depth + 1); 462 case ISD::FSUB: 463 // We can't turn -(A-B) into B-A when we honor signed zeros. 464 if (!Options->UnsafeFPMath) return 0; 465 466 // fold (fneg (fsub A, B)) -> (fsub B, A) 467 return 1; 468 469 case ISD::FMUL: 470 case ISD::FDIV: 471 if (Options->HonorSignDependentRoundingFPMath()) return 0; 472 473 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 474 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 475 Options, Depth + 1)) 476 return V; 477 478 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 479 Depth + 1); 480 481 case ISD::FP_EXTEND: 482 case ISD::FP_ROUND: 483 case ISD::FSIN: 484 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 485 Depth + 1); 486 } 487} 488 489/// GetNegatedExpression - If isNegatibleForFree returns true, this function 490/// returns the newly negated expression. 491static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 492 bool LegalOperations, unsigned Depth = 0) { 493 // fneg is removable even if it has multiple uses. 494 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 495 496 // Don't allow anything with multiple uses. 497 assert(Op.hasOneUse() && "Unknown reuse!"); 498 499 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 500 switch (Op.getOpcode()) { 501 default: llvm_unreachable("Unknown code"); 502 case ISD::ConstantFP: { 503 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 504 V.changeSign(); 505 return DAG.getConstantFP(V, Op.getValueType()); 506 } 507 case ISD::FADD: 508 // FIXME: determine better conditions for this xform. 509 assert(DAG.getTarget().Options.UnsafeFPMath); 510 511 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 512 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 513 DAG.getTargetLoweringInfo(), 514 &DAG.getTarget().Options, Depth+1)) 515 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), 516 GetNegatedExpression(Op.getOperand(0), DAG, 517 LegalOperations, Depth+1), 518 Op.getOperand(1)); 519 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 520 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), 521 GetNegatedExpression(Op.getOperand(1), DAG, 522 LegalOperations, Depth+1), 523 Op.getOperand(0)); 524 case ISD::FSUB: 525 // We can't turn -(A-B) into B-A when we honor signed zeros. 526 assert(DAG.getTarget().Options.UnsafeFPMath); 527 528 // fold (fneg (fsub 0, B)) -> B 529 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 530 if (N0CFP->getValueAPF().isZero()) 531 return Op.getOperand(1); 532 533 // fold (fneg (fsub A, B)) -> (fsub B, A) 534 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), 535 Op.getOperand(1), Op.getOperand(0)); 536 537 case ISD::FMUL: 538 case ISD::FDIV: 539 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 540 541 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 542 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 543 DAG.getTargetLoweringInfo(), 544 &DAG.getTarget().Options, Depth+1)) 545 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), 546 GetNegatedExpression(Op.getOperand(0), DAG, 547 LegalOperations, Depth+1), 548 Op.getOperand(1)); 549 550 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 551 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), 552 Op.getOperand(0), 553 GetNegatedExpression(Op.getOperand(1), DAG, 554 LegalOperations, Depth+1)); 555 556 case ISD::FP_EXTEND: 557 case ISD::FSIN: 558 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), 559 GetNegatedExpression(Op.getOperand(0), DAG, 560 LegalOperations, Depth+1)); 561 case ISD::FP_ROUND: 562 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), 563 GetNegatedExpression(Op.getOperand(0), DAG, 564 LegalOperations, Depth+1), 565 Op.getOperand(1)); 566 } 567} 568 569 570// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 571// that selects between the values 1 and 0, making it equivalent to a setcc. 572// Also, set the incoming LHS, RHS, and CC references to the appropriate 573// nodes based on the type of node we are checking. This simplifies life a 574// bit for the callers. 575static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 576 SDValue &CC) { 577 if (N.getOpcode() == ISD::SETCC) { 578 LHS = N.getOperand(0); 579 RHS = N.getOperand(1); 580 CC = N.getOperand(2); 581 return true; 582 } 583 if (N.getOpcode() == ISD::SELECT_CC && 584 N.getOperand(2).getOpcode() == ISD::Constant && 585 N.getOperand(3).getOpcode() == ISD::Constant && 586 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 587 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 588 LHS = N.getOperand(0); 589 RHS = N.getOperand(1); 590 CC = N.getOperand(4); 591 return true; 592 } 593 return false; 594} 595 596// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 597// one use. If this is true, it allows the users to invert the operation for 598// free when it is profitable to do so. 599static bool isOneUseSetCC(SDValue N) { 600 SDValue N0, N1, N2; 601 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 602 return true; 603 return false; 604} 605 606SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL, 607 SDValue N0, SDValue N1) { 608 EVT VT = N0.getValueType(); 609 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 610 if (isa<ConstantSDNode>(N1)) { 611 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 612 SDValue OpNode = 613 DAG.FoldConstantArithmetic(Opc, VT, 614 cast<ConstantSDNode>(N0.getOperand(1)), 615 cast<ConstantSDNode>(N1)); 616 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 617 } 618 if (N0.hasOneUse()) { 619 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 620 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, 621 N0.getOperand(0), N1); 622 AddToWorkList(OpNode.getNode()); 623 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 624 } 625 } 626 627 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 628 if (isa<ConstantSDNode>(N0)) { 629 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 630 SDValue OpNode = 631 DAG.FoldConstantArithmetic(Opc, VT, 632 cast<ConstantSDNode>(N1.getOperand(1)), 633 cast<ConstantSDNode>(N0)); 634 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 635 } 636 if (N1.hasOneUse()) { 637 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 638 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, 639 N1.getOperand(0), N0); 640 AddToWorkList(OpNode.getNode()); 641 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 642 } 643 } 644 645 return SDValue(); 646} 647 648SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 649 bool AddTo) { 650 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 651 ++NodesCombined; 652 DEBUG(dbgs() << "\nReplacing.1 "; 653 N->dump(&DAG); 654 dbgs() << "\nWith: "; 655 To[0].getNode()->dump(&DAG); 656 dbgs() << " and " << NumTo-1 << " other values\n"; 657 for (unsigned i = 0, e = NumTo; i != e; ++i) 658 assert((!To[i].getNode() || 659 N->getValueType(i) == To[i].getValueType()) && 660 "Cannot combine value to value of different type!")); 661 WorkListRemover DeadNodes(*this); 662 DAG.ReplaceAllUsesWith(N, To); 663 if (AddTo) { 664 // Push the new nodes and any users onto the worklist 665 for (unsigned i = 0, e = NumTo; i != e; ++i) { 666 if (To[i].getNode()) { 667 AddToWorkList(To[i].getNode()); 668 AddUsersToWorkList(To[i].getNode()); 669 } 670 } 671 } 672 673 // Finally, if the node is now dead, remove it from the graph. The node 674 // may not be dead if the replacement process recursively simplified to 675 // something else needing this node. 676 if (N->use_empty()) { 677 // Nodes can be reintroduced into the worklist. Make sure we do not 678 // process a node that has been replaced. 679 removeFromWorkList(N); 680 681 // Finally, since the node is now dead, remove it from the graph. 682 DAG.DeleteNode(N); 683 } 684 return SDValue(N, 0); 685} 686 687void DAGCombiner:: 688CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 689 // Replace all uses. If any nodes become isomorphic to other nodes and 690 // are deleted, make sure to remove them from our worklist. 691 WorkListRemover DeadNodes(*this); 692 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 693 694 // Push the new node and any (possibly new) users onto the worklist. 695 AddToWorkList(TLO.New.getNode()); 696 AddUsersToWorkList(TLO.New.getNode()); 697 698 // Finally, if the node is now dead, remove it from the graph. The node 699 // may not be dead if the replacement process recursively simplified to 700 // something else needing this node. 701 if (TLO.Old.getNode()->use_empty()) { 702 removeFromWorkList(TLO.Old.getNode()); 703 704 // If the operands of this node are only used by the node, they will now 705 // be dead. Make sure to visit them first to delete dead nodes early. 706 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 707 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 708 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 709 710 DAG.DeleteNode(TLO.Old.getNode()); 711 } 712} 713 714/// SimplifyDemandedBits - Check the specified integer node value to see if 715/// it can be simplified or if things it uses can be simplified by bit 716/// propagation. If so, return true. 717bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 718 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 719 APInt KnownZero, KnownOne; 720 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 721 return false; 722 723 // Revisit the node. 724 AddToWorkList(Op.getNode()); 725 726 // Replace the old value with the new one. 727 ++NodesCombined; 728 DEBUG(dbgs() << "\nReplacing.2 "; 729 TLO.Old.getNode()->dump(&DAG); 730 dbgs() << "\nWith: "; 731 TLO.New.getNode()->dump(&DAG); 732 dbgs() << '\n'); 733 734 CommitTargetLoweringOpt(TLO); 735 return true; 736} 737 738void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 739 SDLoc dl(Load); 740 EVT VT = Load->getValueType(0); 741 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 742 743 DEBUG(dbgs() << "\nReplacing.9 "; 744 Load->dump(&DAG); 745 dbgs() << "\nWith: "; 746 Trunc.getNode()->dump(&DAG); 747 dbgs() << '\n'); 748 WorkListRemover DeadNodes(*this); 749 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 750 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 751 removeFromWorkList(Load); 752 DAG.DeleteNode(Load); 753 AddToWorkList(Trunc.getNode()); 754} 755 756SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 757 Replace = false; 758 SDLoc dl(Op); 759 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 760 EVT MemVT = LD->getMemoryVT(); 761 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 762 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 763 : ISD::EXTLOAD) 764 : LD->getExtensionType(); 765 Replace = true; 766 return DAG.getExtLoad(ExtType, dl, PVT, 767 LD->getChain(), LD->getBasePtr(), 768 MemVT, LD->getMemOperand()); 769 } 770 771 unsigned Opc = Op.getOpcode(); 772 switch (Opc) { 773 default: break; 774 case ISD::AssertSext: 775 return DAG.getNode(ISD::AssertSext, dl, PVT, 776 SExtPromoteOperand(Op.getOperand(0), PVT), 777 Op.getOperand(1)); 778 case ISD::AssertZext: 779 return DAG.getNode(ISD::AssertZext, dl, PVT, 780 ZExtPromoteOperand(Op.getOperand(0), PVT), 781 Op.getOperand(1)); 782 case ISD::Constant: { 783 unsigned ExtOpc = 784 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 785 return DAG.getNode(ExtOpc, dl, PVT, Op); 786 } 787 } 788 789 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 790 return SDValue(); 791 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 792} 793 794SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 795 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 796 return SDValue(); 797 EVT OldVT = Op.getValueType(); 798 SDLoc dl(Op); 799 bool Replace = false; 800 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 801 if (NewOp.getNode() == 0) 802 return SDValue(); 803 AddToWorkList(NewOp.getNode()); 804 805 if (Replace) 806 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 807 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 808 DAG.getValueType(OldVT)); 809} 810 811SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 812 EVT OldVT = Op.getValueType(); 813 SDLoc dl(Op); 814 bool Replace = false; 815 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 816 if (NewOp.getNode() == 0) 817 return SDValue(); 818 AddToWorkList(NewOp.getNode()); 819 820 if (Replace) 821 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 822 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 823} 824 825/// PromoteIntBinOp - Promote the specified integer binary operation if the 826/// target indicates it is beneficial. e.g. On x86, it's usually better to 827/// promote i16 operations to i32 since i16 instructions are longer. 828SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 829 if (!LegalOperations) 830 return SDValue(); 831 832 EVT VT = Op.getValueType(); 833 if (VT.isVector() || !VT.isInteger()) 834 return SDValue(); 835 836 // If operation type is 'undesirable', e.g. i16 on x86, consider 837 // promoting it. 838 unsigned Opc = Op.getOpcode(); 839 if (TLI.isTypeDesirableForOp(Opc, VT)) 840 return SDValue(); 841 842 EVT PVT = VT; 843 // Consult target whether it is a good idea to promote this operation and 844 // what's the right type to promote it to. 845 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 846 assert(PVT != VT && "Don't know what type to promote to!"); 847 848 bool Replace0 = false; 849 SDValue N0 = Op.getOperand(0); 850 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 851 if (NN0.getNode() == 0) 852 return SDValue(); 853 854 bool Replace1 = false; 855 SDValue N1 = Op.getOperand(1); 856 SDValue NN1; 857 if (N0 == N1) 858 NN1 = NN0; 859 else { 860 NN1 = PromoteOperand(N1, PVT, Replace1); 861 if (NN1.getNode() == 0) 862 return SDValue(); 863 } 864 865 AddToWorkList(NN0.getNode()); 866 if (NN1.getNode()) 867 AddToWorkList(NN1.getNode()); 868 869 if (Replace0) 870 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 871 if (Replace1) 872 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 873 874 DEBUG(dbgs() << "\nPromoting "; 875 Op.getNode()->dump(&DAG)); 876 SDLoc dl(Op); 877 return DAG.getNode(ISD::TRUNCATE, dl, VT, 878 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 879 } 880 return SDValue(); 881} 882 883/// PromoteIntShiftOp - Promote the specified integer shift operation if the 884/// target indicates it is beneficial. e.g. On x86, it's usually better to 885/// promote i16 operations to i32 since i16 instructions are longer. 886SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 887 if (!LegalOperations) 888 return SDValue(); 889 890 EVT VT = Op.getValueType(); 891 if (VT.isVector() || !VT.isInteger()) 892 return SDValue(); 893 894 // If operation type is 'undesirable', e.g. i16 on x86, consider 895 // promoting it. 896 unsigned Opc = Op.getOpcode(); 897 if (TLI.isTypeDesirableForOp(Opc, VT)) 898 return SDValue(); 899 900 EVT PVT = VT; 901 // Consult target whether it is a good idea to promote this operation and 902 // what's the right type to promote it to. 903 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 904 assert(PVT != VT && "Don't know what type to promote to!"); 905 906 bool Replace = false; 907 SDValue N0 = Op.getOperand(0); 908 if (Opc == ISD::SRA) 909 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 910 else if (Opc == ISD::SRL) 911 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 912 else 913 N0 = PromoteOperand(N0, PVT, Replace); 914 if (N0.getNode() == 0) 915 return SDValue(); 916 917 AddToWorkList(N0.getNode()); 918 if (Replace) 919 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 920 921 DEBUG(dbgs() << "\nPromoting "; 922 Op.getNode()->dump(&DAG)); 923 SDLoc dl(Op); 924 return DAG.getNode(ISD::TRUNCATE, dl, VT, 925 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 926 } 927 return SDValue(); 928} 929 930SDValue DAGCombiner::PromoteExtend(SDValue Op) { 931 if (!LegalOperations) 932 return SDValue(); 933 934 EVT VT = Op.getValueType(); 935 if (VT.isVector() || !VT.isInteger()) 936 return SDValue(); 937 938 // If operation type is 'undesirable', e.g. i16 on x86, consider 939 // promoting it. 940 unsigned Opc = Op.getOpcode(); 941 if (TLI.isTypeDesirableForOp(Opc, VT)) 942 return SDValue(); 943 944 EVT PVT = VT; 945 // Consult target whether it is a good idea to promote this operation and 946 // what's the right type to promote it to. 947 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 948 assert(PVT != VT && "Don't know what type to promote to!"); 949 // fold (aext (aext x)) -> (aext x) 950 // fold (aext (zext x)) -> (zext x) 951 // fold (aext (sext x)) -> (sext x) 952 DEBUG(dbgs() << "\nPromoting "; 953 Op.getNode()->dump(&DAG)); 954 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); 955 } 956 return SDValue(); 957} 958 959bool DAGCombiner::PromoteLoad(SDValue Op) { 960 if (!LegalOperations) 961 return false; 962 963 EVT VT = Op.getValueType(); 964 if (VT.isVector() || !VT.isInteger()) 965 return false; 966 967 // If operation type is 'undesirable', e.g. i16 on x86, consider 968 // promoting it. 969 unsigned Opc = Op.getOpcode(); 970 if (TLI.isTypeDesirableForOp(Opc, VT)) 971 return false; 972 973 EVT PVT = VT; 974 // Consult target whether it is a good idea to promote this operation and 975 // what's the right type to promote it to. 976 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 977 assert(PVT != VT && "Don't know what type to promote to!"); 978 979 SDLoc dl(Op); 980 SDNode *N = Op.getNode(); 981 LoadSDNode *LD = cast<LoadSDNode>(N); 982 EVT MemVT = LD->getMemoryVT(); 983 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 984 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 985 : ISD::EXTLOAD) 986 : LD->getExtensionType(); 987 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 988 LD->getChain(), LD->getBasePtr(), 989 MemVT, LD->getMemOperand()); 990 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 991 992 DEBUG(dbgs() << "\nPromoting "; 993 N->dump(&DAG); 994 dbgs() << "\nTo: "; 995 Result.getNode()->dump(&DAG); 996 dbgs() << '\n'); 997 WorkListRemover DeadNodes(*this); 998 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 999 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 1000 removeFromWorkList(N); 1001 DAG.DeleteNode(N); 1002 AddToWorkList(Result.getNode()); 1003 return true; 1004 } 1005 return false; 1006} 1007 1008 1009//===----------------------------------------------------------------------===// 1010// Main DAG Combiner implementation 1011//===----------------------------------------------------------------------===// 1012 1013void DAGCombiner::Run(CombineLevel AtLevel) { 1014 // set the instance variables, so that the various visit routines may use it. 1015 Level = AtLevel; 1016 LegalOperations = Level >= AfterLegalizeVectorOps; 1017 LegalTypes = Level >= AfterLegalizeTypes; 1018 1019 // Add all the dag nodes to the worklist. 1020 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 1021 E = DAG.allnodes_end(); I != E; ++I) 1022 AddToWorkList(I); 1023 1024 // Create a dummy node (which is not added to allnodes), that adds a reference 1025 // to the root node, preventing it from being deleted, and tracking any 1026 // changes of the root. 1027 HandleSDNode Dummy(DAG.getRoot()); 1028 1029 // The root of the dag may dangle to deleted nodes until the dag combiner is 1030 // done. Set it to null to avoid confusion. 1031 DAG.setRoot(SDValue()); 1032 1033 // while the worklist isn't empty, find a node and 1034 // try and combine it. 1035 while (!WorkListContents.empty()) { 1036 SDNode *N; 1037 // The WorkListOrder holds the SDNodes in order, but it may contain 1038 // duplicates. 1039 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1040 // worklist *should* contain, and check the node we want to visit is should 1041 // actually be visited. 1042 do { 1043 N = WorkListOrder.pop_back_val(); 1044 } while (!WorkListContents.erase(N)); 1045 1046 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1047 // N is deleted from the DAG, since they too may now be dead or may have a 1048 // reduced number of uses, allowing other xforms. 1049 if (N->use_empty() && N != &Dummy) { 1050 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1051 AddToWorkList(N->getOperand(i).getNode()); 1052 1053 DAG.DeleteNode(N); 1054 continue; 1055 } 1056 1057 SDValue RV = combine(N); 1058 1059 if (RV.getNode() == 0) 1060 continue; 1061 1062 ++NodesCombined; 1063 1064 // If we get back the same node we passed in, rather than a new node or 1065 // zero, we know that the node must have defined multiple values and 1066 // CombineTo was used. Since CombineTo takes care of the worklist 1067 // mechanics for us, we have no work to do in this case. 1068 if (RV.getNode() == N) 1069 continue; 1070 1071 assert(N->getOpcode() != ISD::DELETED_NODE && 1072 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1073 "Node was deleted but visit returned new node!"); 1074 1075 DEBUG(dbgs() << "\nReplacing.3 "; 1076 N->dump(&DAG); 1077 dbgs() << "\nWith: "; 1078 RV.getNode()->dump(&DAG); 1079 dbgs() << '\n'); 1080 1081 // Transfer debug value. 1082 DAG.TransferDbgValues(SDValue(N, 0), RV); 1083 WorkListRemover DeadNodes(*this); 1084 if (N->getNumValues() == RV.getNode()->getNumValues()) 1085 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1086 else { 1087 assert(N->getValueType(0) == RV.getValueType() && 1088 N->getNumValues() == 1 && "Type mismatch"); 1089 SDValue OpV = RV; 1090 DAG.ReplaceAllUsesWith(N, &OpV); 1091 } 1092 1093 // Push the new node and any users onto the worklist 1094 AddToWorkList(RV.getNode()); 1095 AddUsersToWorkList(RV.getNode()); 1096 1097 // Add any uses of the old node to the worklist in case this node is the 1098 // last one that uses them. They may become dead after this node is 1099 // deleted. 1100 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1101 AddToWorkList(N->getOperand(i).getNode()); 1102 1103 // Finally, if the node is now dead, remove it from the graph. The node 1104 // may not be dead if the replacement process recursively simplified to 1105 // something else needing this node. 1106 if (N->use_empty()) { 1107 // Nodes can be reintroduced into the worklist. Make sure we do not 1108 // process a node that has been replaced. 1109 removeFromWorkList(N); 1110 1111 // Finally, since the node is now dead, remove it from the graph. 1112 DAG.DeleteNode(N); 1113 } 1114 } 1115 1116 // If the root changed (e.g. it was a dead load, update the root). 1117 DAG.setRoot(Dummy.getValue()); 1118 DAG.RemoveDeadNodes(); 1119} 1120 1121SDValue DAGCombiner::visit(SDNode *N) { 1122 switch (N->getOpcode()) { 1123 default: break; 1124 case ISD::TokenFactor: return visitTokenFactor(N); 1125 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1126 case ISD::ADD: return visitADD(N); 1127 case ISD::SUB: return visitSUB(N); 1128 case ISD::ADDC: return visitADDC(N); 1129 case ISD::SUBC: return visitSUBC(N); 1130 case ISD::ADDE: return visitADDE(N); 1131 case ISD::SUBE: return visitSUBE(N); 1132 case ISD::MUL: return visitMUL(N); 1133 case ISD::SDIV: return visitSDIV(N); 1134 case ISD::UDIV: return visitUDIV(N); 1135 case ISD::SREM: return visitSREM(N); 1136 case ISD::UREM: return visitUREM(N); 1137 case ISD::MULHU: return visitMULHU(N); 1138 case ISD::MULHS: return visitMULHS(N); 1139 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1140 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1141 case ISD::SMULO: return visitSMULO(N); 1142 case ISD::UMULO: return visitUMULO(N); 1143 case ISD::SDIVREM: return visitSDIVREM(N); 1144 case ISD::UDIVREM: return visitUDIVREM(N); 1145 case ISD::AND: return visitAND(N); 1146 case ISD::OR: return visitOR(N); 1147 case ISD::XOR: return visitXOR(N); 1148 case ISD::SHL: return visitSHL(N); 1149 case ISD::SRA: return visitSRA(N); 1150 case ISD::SRL: return visitSRL(N); 1151 case ISD::CTLZ: return visitCTLZ(N); 1152 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1153 case ISD::CTTZ: return visitCTTZ(N); 1154 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1155 case ISD::CTPOP: return visitCTPOP(N); 1156 case ISD::SELECT: return visitSELECT(N); 1157 case ISD::VSELECT: return visitVSELECT(N); 1158 case ISD::SELECT_CC: return visitSELECT_CC(N); 1159 case ISD::SETCC: return visitSETCC(N); 1160 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1161 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1162 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1163 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1164 case ISD::TRUNCATE: return visitTRUNCATE(N); 1165 case ISD::BITCAST: return visitBITCAST(N); 1166 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1167 case ISD::FADD: return visitFADD(N); 1168 case ISD::FSUB: return visitFSUB(N); 1169 case ISD::FMUL: return visitFMUL(N); 1170 case ISD::FMA: return visitFMA(N); 1171 case ISD::FDIV: return visitFDIV(N); 1172 case ISD::FREM: return visitFREM(N); 1173 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1174 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1175 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1176 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1177 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1178 case ISD::FP_ROUND: return visitFP_ROUND(N); 1179 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1180 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1181 case ISD::FNEG: return visitFNEG(N); 1182 case ISD::FABS: return visitFABS(N); 1183 case ISD::FFLOOR: return visitFFLOOR(N); 1184 case ISD::FCEIL: return visitFCEIL(N); 1185 case ISD::FTRUNC: return visitFTRUNC(N); 1186 case ISD::BRCOND: return visitBRCOND(N); 1187 case ISD::BR_CC: return visitBR_CC(N); 1188 case ISD::LOAD: return visitLOAD(N); 1189 case ISD::STORE: return visitSTORE(N); 1190 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1191 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1192 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1193 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1194 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1195 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1196 } 1197 return SDValue(); 1198} 1199 1200SDValue DAGCombiner::combine(SDNode *N) { 1201 SDValue RV = visit(N); 1202 1203 // If nothing happened, try a target-specific DAG combine. 1204 if (RV.getNode() == 0) { 1205 assert(N->getOpcode() != ISD::DELETED_NODE && 1206 "Node was deleted but visit returned NULL!"); 1207 1208 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1209 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1210 1211 // Expose the DAG combiner to the target combiner impls. 1212 TargetLowering::DAGCombinerInfo 1213 DagCombineInfo(DAG, Level, false, this); 1214 1215 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1216 } 1217 } 1218 1219 // If nothing happened still, try promoting the operation. 1220 if (RV.getNode() == 0) { 1221 switch (N->getOpcode()) { 1222 default: break; 1223 case ISD::ADD: 1224 case ISD::SUB: 1225 case ISD::MUL: 1226 case ISD::AND: 1227 case ISD::OR: 1228 case ISD::XOR: 1229 RV = PromoteIntBinOp(SDValue(N, 0)); 1230 break; 1231 case ISD::SHL: 1232 case ISD::SRA: 1233 case ISD::SRL: 1234 RV = PromoteIntShiftOp(SDValue(N, 0)); 1235 break; 1236 case ISD::SIGN_EXTEND: 1237 case ISD::ZERO_EXTEND: 1238 case ISD::ANY_EXTEND: 1239 RV = PromoteExtend(SDValue(N, 0)); 1240 break; 1241 case ISD::LOAD: 1242 if (PromoteLoad(SDValue(N, 0))) 1243 RV = SDValue(N, 0); 1244 break; 1245 } 1246 } 1247 1248 // If N is a commutative binary node, try commuting it to enable more 1249 // sdisel CSE. 1250 if (RV.getNode() == 0 && 1251 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1252 N->getNumValues() == 1) { 1253 SDValue N0 = N->getOperand(0); 1254 SDValue N1 = N->getOperand(1); 1255 1256 // Constant operands are canonicalized to RHS. 1257 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1258 SDValue Ops[] = { N1, N0 }; 1259 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1260 Ops, 2); 1261 if (CSENode) 1262 return SDValue(CSENode, 0); 1263 } 1264 } 1265 1266 return RV; 1267} 1268 1269/// getInputChainForNode - Given a node, return its input chain if it has one, 1270/// otherwise return a null sd operand. 1271static SDValue getInputChainForNode(SDNode *N) { 1272 if (unsigned NumOps = N->getNumOperands()) { 1273 if (N->getOperand(0).getValueType() == MVT::Other) 1274 return N->getOperand(0); 1275 if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1276 return N->getOperand(NumOps-1); 1277 for (unsigned i = 1; i < NumOps-1; ++i) 1278 if (N->getOperand(i).getValueType() == MVT::Other) 1279 return N->getOperand(i); 1280 } 1281 return SDValue(); 1282} 1283 1284SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1285 // If N has two operands, where one has an input chain equal to the other, 1286 // the 'other' chain is redundant. 1287 if (N->getNumOperands() == 2) { 1288 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1289 return N->getOperand(0); 1290 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1291 return N->getOperand(1); 1292 } 1293 1294 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1295 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1296 SmallPtrSet<SDNode*, 16> SeenOps; 1297 bool Changed = false; // If we should replace this token factor. 1298 1299 // Start out with this token factor. 1300 TFs.push_back(N); 1301 1302 // Iterate through token factors. The TFs grows when new token factors are 1303 // encountered. 1304 for (unsigned i = 0; i < TFs.size(); ++i) { 1305 SDNode *TF = TFs[i]; 1306 1307 // Check each of the operands. 1308 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1309 SDValue Op = TF->getOperand(i); 1310 1311 switch (Op.getOpcode()) { 1312 case ISD::EntryToken: 1313 // Entry tokens don't need to be added to the list. They are 1314 // rededundant. 1315 Changed = true; 1316 break; 1317 1318 case ISD::TokenFactor: 1319 if (Op.hasOneUse() && 1320 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1321 // Queue up for processing. 1322 TFs.push_back(Op.getNode()); 1323 // Clean up in case the token factor is removed. 1324 AddToWorkList(Op.getNode()); 1325 Changed = true; 1326 break; 1327 } 1328 // Fall thru 1329 1330 default: 1331 // Only add if it isn't already in the list. 1332 if (SeenOps.insert(Op.getNode())) 1333 Ops.push_back(Op); 1334 else 1335 Changed = true; 1336 break; 1337 } 1338 } 1339 } 1340 1341 SDValue Result; 1342 1343 // If we've change things around then replace token factor. 1344 if (Changed) { 1345 if (Ops.empty()) { 1346 // The entry token is the only possible outcome. 1347 Result = DAG.getEntryNode(); 1348 } else { 1349 // New and improved token factor. 1350 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), 1351 MVT::Other, &Ops[0], Ops.size()); 1352 } 1353 1354 // Don't add users to work list. 1355 return CombineTo(N, Result, false); 1356 } 1357 1358 return Result; 1359} 1360 1361/// MERGE_VALUES can always be eliminated. 1362SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1363 WorkListRemover DeadNodes(*this); 1364 // Replacing results may cause a different MERGE_VALUES to suddenly 1365 // be CSE'd with N, and carry its uses with it. Iterate until no 1366 // uses remain, to ensure that the node can be safely deleted. 1367 // First add the users of this node to the work list so that they 1368 // can be tried again once they have new operands. 1369 AddUsersToWorkList(N); 1370 do { 1371 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1372 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1373 } while (!N->use_empty()); 1374 removeFromWorkList(N); 1375 DAG.DeleteNode(N); 1376 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1377} 1378 1379static 1380SDValue combineShlAddConstant(SDLoc DL, SDValue N0, SDValue N1, 1381 SelectionDAG &DAG) { 1382 EVT VT = N0.getValueType(); 1383 SDValue N00 = N0.getOperand(0); 1384 SDValue N01 = N0.getOperand(1); 1385 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1386 1387 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1388 isa<ConstantSDNode>(N00.getOperand(1))) { 1389 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1390 N0 = DAG.getNode(ISD::ADD, SDLoc(N0), VT, 1391 DAG.getNode(ISD::SHL, SDLoc(N00), VT, 1392 N00.getOperand(0), N01), 1393 DAG.getNode(ISD::SHL, SDLoc(N01), VT, 1394 N00.getOperand(1), N01)); 1395 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1396 } 1397 1398 return SDValue(); 1399} 1400 1401SDValue DAGCombiner::visitADD(SDNode *N) { 1402 SDValue N0 = N->getOperand(0); 1403 SDValue N1 = N->getOperand(1); 1404 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1405 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1406 EVT VT = N0.getValueType(); 1407 1408 // fold vector ops 1409 if (VT.isVector()) { 1410 SDValue FoldedVOp = SimplifyVBinOp(N); 1411 if (FoldedVOp.getNode()) return FoldedVOp; 1412 1413 // fold (add x, 0) -> x, vector edition 1414 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1415 return N0; 1416 if (ISD::isBuildVectorAllZeros(N0.getNode())) 1417 return N1; 1418 } 1419 1420 // fold (add x, undef) -> undef 1421 if (N0.getOpcode() == ISD::UNDEF) 1422 return N0; 1423 if (N1.getOpcode() == ISD::UNDEF) 1424 return N1; 1425 // fold (add c1, c2) -> c1+c2 1426 if (N0C && N1C) 1427 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1428 // canonicalize constant to RHS 1429 if (N0C && !N1C) 1430 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0); 1431 // fold (add x, 0) -> x 1432 if (N1C && N1C->isNullValue()) 1433 return N0; 1434 // fold (add Sym, c) -> Sym+c 1435 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1436 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1437 GA->getOpcode() == ISD::GlobalAddress) 1438 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT, 1439 GA->getOffset() + 1440 (uint64_t)N1C->getSExtValue()); 1441 // fold ((c1-A)+c2) -> (c1+c2)-A 1442 if (N1C && N0.getOpcode() == ISD::SUB) 1443 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1444 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1445 DAG.getConstant(N1C->getAPIntValue()+ 1446 N0C->getAPIntValue(), VT), 1447 N0.getOperand(1)); 1448 // reassociate add 1449 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1); 1450 if (RADD.getNode() != 0) 1451 return RADD; 1452 // fold ((0-A) + B) -> B-A 1453 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1454 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1455 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1)); 1456 // fold (A + (0-B)) -> A-B 1457 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1458 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1459 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1)); 1460 // fold (A+(B-A)) -> B 1461 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1462 return N1.getOperand(0); 1463 // fold ((B-A)+A) -> B 1464 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1465 return N0.getOperand(0); 1466 // fold (A+(B-(A+C))) to (B-C) 1467 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1468 N0 == N1.getOperand(1).getOperand(0)) 1469 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0), 1470 N1.getOperand(1).getOperand(1)); 1471 // fold (A+(B-(C+A))) to (B-C) 1472 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1473 N0 == N1.getOperand(1).getOperand(1)) 1474 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0), 1475 N1.getOperand(1).getOperand(0)); 1476 // fold (A+((B-A)+or-C)) to (B+or-C) 1477 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1478 N1.getOperand(0).getOpcode() == ISD::SUB && 1479 N0 == N1.getOperand(0).getOperand(1)) 1480 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT, 1481 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1482 1483 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1484 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1485 SDValue N00 = N0.getOperand(0); 1486 SDValue N01 = N0.getOperand(1); 1487 SDValue N10 = N1.getOperand(0); 1488 SDValue N11 = N1.getOperand(1); 1489 1490 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1491 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1492 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10), 1493 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11)); 1494 } 1495 1496 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1497 return SDValue(N, 0); 1498 1499 // fold (a+b) -> (a|b) iff a and b share no bits. 1500 if (VT.isInteger() && !VT.isVector()) { 1501 APInt LHSZero, LHSOne; 1502 APInt RHSZero, RHSOne; 1503 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1504 1505 if (LHSZero.getBoolValue()) { 1506 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1507 1508 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1509 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1510 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1511 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1); 1512 } 1513 } 1514 1515 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1516 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1517 SDValue Result = combineShlAddConstant(SDLoc(N), N0, N1, DAG); 1518 if (Result.getNode()) return Result; 1519 } 1520 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1521 SDValue Result = combineShlAddConstant(SDLoc(N), N1, N0, DAG); 1522 if (Result.getNode()) return Result; 1523 } 1524 1525 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1526 if (N1.getOpcode() == ISD::SHL && 1527 N1.getOperand(0).getOpcode() == ISD::SUB) 1528 if (ConstantSDNode *C = 1529 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1530 if (C->getAPIntValue() == 0) 1531 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, 1532 DAG.getNode(ISD::SHL, SDLoc(N), VT, 1533 N1.getOperand(0).getOperand(1), 1534 N1.getOperand(1))); 1535 if (N0.getOpcode() == ISD::SHL && 1536 N0.getOperand(0).getOpcode() == ISD::SUB) 1537 if (ConstantSDNode *C = 1538 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1539 if (C->getAPIntValue() == 0) 1540 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, 1541 DAG.getNode(ISD::SHL, SDLoc(N), VT, 1542 N0.getOperand(0).getOperand(1), 1543 N0.getOperand(1))); 1544 1545 if (N1.getOpcode() == ISD::AND) { 1546 SDValue AndOp0 = N1.getOperand(0); 1547 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1548 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1549 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1550 1551 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1552 // and similar xforms where the inner op is either ~0 or 0. 1553 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1554 SDLoc DL(N); 1555 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1556 } 1557 } 1558 1559 // add (sext i1), X -> sub X, (zext i1) 1560 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1561 N0.getOperand(0).getValueType() == MVT::i1 && 1562 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1563 SDLoc DL(N); 1564 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1565 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1566 } 1567 1568 return SDValue(); 1569} 1570 1571SDValue DAGCombiner::visitADDC(SDNode *N) { 1572 SDValue N0 = N->getOperand(0); 1573 SDValue N1 = N->getOperand(1); 1574 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1575 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1576 EVT VT = N0.getValueType(); 1577 1578 // If the flag result is dead, turn this into an ADD. 1579 if (!N->hasAnyUseOfValue(1)) 1580 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1), 1581 DAG.getNode(ISD::CARRY_FALSE, 1582 SDLoc(N), MVT::Glue)); 1583 1584 // canonicalize constant to RHS. 1585 if (N0C && !N1C) 1586 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0); 1587 1588 // fold (addc x, 0) -> x + no carry out 1589 if (N1C && N1C->isNullValue()) 1590 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1591 SDLoc(N), MVT::Glue)); 1592 1593 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1594 APInt LHSZero, LHSOne; 1595 APInt RHSZero, RHSOne; 1596 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1597 1598 if (LHSZero.getBoolValue()) { 1599 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1600 1601 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1602 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1603 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1604 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1), 1605 DAG.getNode(ISD::CARRY_FALSE, 1606 SDLoc(N), MVT::Glue)); 1607 } 1608 1609 return SDValue(); 1610} 1611 1612SDValue DAGCombiner::visitADDE(SDNode *N) { 1613 SDValue N0 = N->getOperand(0); 1614 SDValue N1 = N->getOperand(1); 1615 SDValue CarryIn = N->getOperand(2); 1616 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1617 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1618 1619 // canonicalize constant to RHS 1620 if (N0C && !N1C) 1621 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(), 1622 N1, N0, CarryIn); 1623 1624 // fold (adde x, y, false) -> (addc x, y) 1625 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1626 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1); 1627 1628 return SDValue(); 1629} 1630 1631// Since it may not be valid to emit a fold to zero for vector initializers 1632// check if we can before folding. 1633static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT, 1634 SelectionDAG &DAG, 1635 bool LegalOperations, bool LegalTypes) { 1636 if (!VT.isVector()) 1637 return DAG.getConstant(0, VT); 1638 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1639 // Produce a vector of zeros. 1640 EVT ElemTy = VT.getVectorElementType(); 1641 if (LegalTypes && TLI.getTypeAction(*DAG.getContext(), ElemTy) == 1642 TargetLowering::TypePromoteInteger) 1643 ElemTy = TLI.getTypeToTransformTo(*DAG.getContext(), ElemTy); 1644 assert((!LegalTypes || TLI.isTypeLegal(ElemTy)) && 1645 "Type for zero vector elements is not legal"); 1646 SDValue El = DAG.getConstant(0, ElemTy); 1647 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1648 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1649 &Ops[0], Ops.size()); 1650 } 1651 return SDValue(); 1652} 1653 1654SDValue DAGCombiner::visitSUB(SDNode *N) { 1655 SDValue N0 = N->getOperand(0); 1656 SDValue N1 = N->getOperand(1); 1657 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1658 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1659 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1660 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1661 EVT VT = N0.getValueType(); 1662 1663 // fold vector ops 1664 if (VT.isVector()) { 1665 SDValue FoldedVOp = SimplifyVBinOp(N); 1666 if (FoldedVOp.getNode()) return FoldedVOp; 1667 1668 // fold (sub x, 0) -> x, vector edition 1669 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1670 return N0; 1671 } 1672 1673 // fold (sub x, x) -> 0 1674 // FIXME: Refactor this and xor and other similar operations together. 1675 if (N0 == N1) 1676 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes); 1677 // fold (sub c1, c2) -> c1-c2 1678 if (N0C && N1C) 1679 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1680 // fold (sub x, c) -> (add x, -c) 1681 if (N1C) 1682 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, 1683 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1684 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1685 if (N0C && N0C->isAllOnesValue()) 1686 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0); 1687 // fold A-(A-B) -> B 1688 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1689 return N1.getOperand(1); 1690 // fold (A+B)-A -> B 1691 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1692 return N0.getOperand(1); 1693 // fold (A+B)-B -> A 1694 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1695 return N0.getOperand(0); 1696 // fold C2-(A+C1) -> (C2-C1)-A 1697 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1698 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), 1699 VT); 1700 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC, 1701 N1.getOperand(0)); 1702 } 1703 // fold ((A+(B+or-C))-B) -> A+or-C 1704 if (N0.getOpcode() == ISD::ADD && 1705 (N0.getOperand(1).getOpcode() == ISD::SUB || 1706 N0.getOperand(1).getOpcode() == ISD::ADD) && 1707 N0.getOperand(1).getOperand(0) == N1) 1708 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT, 1709 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1710 // fold ((A+(C+B))-B) -> A+C 1711 if (N0.getOpcode() == ISD::ADD && 1712 N0.getOperand(1).getOpcode() == ISD::ADD && 1713 N0.getOperand(1).getOperand(1) == N1) 1714 return DAG.getNode(ISD::ADD, SDLoc(N), VT, 1715 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1716 // fold ((A-(B-C))-C) -> A-B 1717 if (N0.getOpcode() == ISD::SUB && 1718 N0.getOperand(1).getOpcode() == ISD::SUB && 1719 N0.getOperand(1).getOperand(1) == N1) 1720 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1721 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1722 1723 // If either operand of a sub is undef, the result is undef 1724 if (N0.getOpcode() == ISD::UNDEF) 1725 return N0; 1726 if (N1.getOpcode() == ISD::UNDEF) 1727 return N1; 1728 1729 // If the relocation model supports it, consider symbol offsets. 1730 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1731 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1732 // fold (sub Sym, c) -> Sym-c 1733 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1734 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT, 1735 GA->getOffset() - 1736 (uint64_t)N1C->getSExtValue()); 1737 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1738 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1739 if (GA->getGlobal() == GB->getGlobal()) 1740 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1741 VT); 1742 } 1743 1744 return SDValue(); 1745} 1746 1747SDValue DAGCombiner::visitSUBC(SDNode *N) { 1748 SDValue N0 = N->getOperand(0); 1749 SDValue N1 = N->getOperand(1); 1750 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1751 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1752 EVT VT = N0.getValueType(); 1753 1754 // If the flag result is dead, turn this into an SUB. 1755 if (!N->hasAnyUseOfValue(1)) 1756 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1), 1757 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N), 1758 MVT::Glue)); 1759 1760 // fold (subc x, x) -> 0 + no borrow 1761 if (N0 == N1) 1762 return CombineTo(N, DAG.getConstant(0, VT), 1763 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N), 1764 MVT::Glue)); 1765 1766 // fold (subc x, 0) -> x + no borrow 1767 if (N1C && N1C->isNullValue()) 1768 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N), 1769 MVT::Glue)); 1770 1771 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1772 if (N0C && N0C->isAllOnesValue()) 1773 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0), 1774 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N), 1775 MVT::Glue)); 1776 1777 return SDValue(); 1778} 1779 1780SDValue DAGCombiner::visitSUBE(SDNode *N) { 1781 SDValue N0 = N->getOperand(0); 1782 SDValue N1 = N->getOperand(1); 1783 SDValue CarryIn = N->getOperand(2); 1784 1785 // fold (sube x, y, false) -> (subc x, y) 1786 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1787 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1); 1788 1789 return SDValue(); 1790} 1791 1792/// isConstantSplatVector - Returns true if N is a BUILD_VECTOR node whose 1793/// elements are all the same constant or undefined. 1794static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) { 1795 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N); 1796 if (!C) 1797 return false; 1798 1799 APInt SplatUndef; 1800 unsigned SplatBitSize; 1801 bool HasAnyUndefs; 1802 EVT EltVT = N->getValueType(0).getVectorElementType(); 1803 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 1804 HasAnyUndefs) && 1805 EltVT.getSizeInBits() >= SplatBitSize); 1806} 1807 1808SDValue DAGCombiner::visitMUL(SDNode *N) { 1809 SDValue N0 = N->getOperand(0); 1810 SDValue N1 = N->getOperand(1); 1811 EVT VT = N0.getValueType(); 1812 1813 // fold (mul x, undef) -> 0 1814 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1815 return DAG.getConstant(0, VT); 1816 1817 bool N0IsConst = false; 1818 bool N1IsConst = false; 1819 APInt ConstValue0, ConstValue1; 1820 // fold vector ops 1821 if (VT.isVector()) { 1822 SDValue FoldedVOp = SimplifyVBinOp(N); 1823 if (FoldedVOp.getNode()) return FoldedVOp; 1824 1825 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0); 1826 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1); 1827 } else { 1828 N0IsConst = dyn_cast<ConstantSDNode>(N0) != 0; 1829 ConstValue0 = N0IsConst ? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue() 1830 : APInt(); 1831 N1IsConst = dyn_cast<ConstantSDNode>(N1) != 0; 1832 ConstValue1 = N1IsConst ? (dyn_cast<ConstantSDNode>(N1))->getAPIntValue() 1833 : APInt(); 1834 } 1835 1836 // fold (mul c1, c2) -> c1*c2 1837 if (N0IsConst && N1IsConst) 1838 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode()); 1839 1840 // canonicalize constant to RHS 1841 if (N0IsConst && !N1IsConst) 1842 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0); 1843 // fold (mul x, 0) -> 0 1844 if (N1IsConst && ConstValue1 == 0) 1845 return N1; 1846 // We require a splat of the entire scalar bit width for non-contiguous 1847 // bit patterns. 1848 bool IsFullSplat = 1849 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits(); 1850 // fold (mul x, 1) -> x 1851 if (N1IsConst && ConstValue1 == 1 && IsFullSplat) 1852 return N0; 1853 // fold (mul x, -1) -> 0-x 1854 if (N1IsConst && ConstValue1.isAllOnesValue()) 1855 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1856 DAG.getConstant(0, VT), N0); 1857 // fold (mul x, (1 << c)) -> x << c 1858 if (N1IsConst && ConstValue1.isPowerOf2() && IsFullSplat) 1859 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, 1860 DAG.getConstant(ConstValue1.logBase2(), 1861 getShiftAmountTy(N0.getValueType()))); 1862 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1863 if (N1IsConst && (-ConstValue1).isPowerOf2() && IsFullSplat) { 1864 unsigned Log2Val = (-ConstValue1).logBase2(); 1865 // FIXME: If the input is something that is easily negated (e.g. a 1866 // single-use add), we should put the negate there. 1867 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1868 DAG.getConstant(0, VT), 1869 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, 1870 DAG.getConstant(Log2Val, 1871 getShiftAmountTy(N0.getValueType())))); 1872 } 1873 1874 APInt Val; 1875 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1876 if (N1IsConst && N0.getOpcode() == ISD::SHL && 1877 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) || 1878 isa<ConstantSDNode>(N0.getOperand(1)))) { 1879 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, 1880 N1, N0.getOperand(1)); 1881 AddToWorkList(C3.getNode()); 1882 return DAG.getNode(ISD::MUL, SDLoc(N), VT, 1883 N0.getOperand(0), C3); 1884 } 1885 1886 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1887 // use. 1888 { 1889 SDValue Sh(0,0), Y(0,0); 1890 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1891 if (N0.getOpcode() == ISD::SHL && 1892 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) || 1893 isa<ConstantSDNode>(N0.getOperand(1))) && 1894 N0.getNode()->hasOneUse()) { 1895 Sh = N0; Y = N1; 1896 } else if (N1.getOpcode() == ISD::SHL && 1897 isa<ConstantSDNode>(N1.getOperand(1)) && 1898 N1.getNode()->hasOneUse()) { 1899 Sh = N1; Y = N0; 1900 } 1901 1902 if (Sh.getNode()) { 1903 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, 1904 Sh.getOperand(0), Y); 1905 return DAG.getNode(ISD::SHL, SDLoc(N), VT, 1906 Mul, Sh.getOperand(1)); 1907 } 1908 } 1909 1910 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1911 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1912 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) || 1913 isa<ConstantSDNode>(N0.getOperand(1)))) 1914 return DAG.getNode(ISD::ADD, SDLoc(N), VT, 1915 DAG.getNode(ISD::MUL, SDLoc(N0), VT, 1916 N0.getOperand(0), N1), 1917 DAG.getNode(ISD::MUL, SDLoc(N1), VT, 1918 N0.getOperand(1), N1)); 1919 1920 // reassociate mul 1921 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1); 1922 if (RMUL.getNode() != 0) 1923 return RMUL; 1924 1925 return SDValue(); 1926} 1927 1928SDValue DAGCombiner::visitSDIV(SDNode *N) { 1929 SDValue N0 = N->getOperand(0); 1930 SDValue N1 = N->getOperand(1); 1931 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1932 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1933 EVT VT = N->getValueType(0); 1934 1935 // fold vector ops 1936 if (VT.isVector()) { 1937 SDValue FoldedVOp = SimplifyVBinOp(N); 1938 if (FoldedVOp.getNode()) return FoldedVOp; 1939 } 1940 1941 // fold (sdiv c1, c2) -> c1/c2 1942 if (N0C && N1C && !N1C->isNullValue()) 1943 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1944 // fold (sdiv X, 1) -> X 1945 if (N1C && N1C->getAPIntValue() == 1LL) 1946 return N0; 1947 // fold (sdiv X, -1) -> 0-X 1948 if (N1C && N1C->isAllOnesValue()) 1949 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1950 DAG.getConstant(0, VT), N0); 1951 // If we know the sign bits of both operands are zero, strength reduce to a 1952 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1953 if (!VT.isVector()) { 1954 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1955 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(), 1956 N0, N1); 1957 } 1958 // fold (sdiv X, pow2) -> simple ops after legalize 1959 if (N1C && !N1C->isNullValue() && 1960 (N1C->getAPIntValue().isPowerOf2() || 1961 (-N1C->getAPIntValue()).isPowerOf2())) { 1962 // If dividing by powers of two is cheap, then don't perform the following 1963 // fold. 1964 if (TLI.isPow2DivCheap()) 1965 return SDValue(); 1966 1967 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1968 1969 // Splat the sign bit into the register 1970 SDValue SGN = DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, 1971 DAG.getConstant(VT.getSizeInBits()-1, 1972 getShiftAmountTy(N0.getValueType()))); 1973 AddToWorkList(SGN.getNode()); 1974 1975 // Add (N0 < 0) ? abs2 - 1 : 0; 1976 SDValue SRL = DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN, 1977 DAG.getConstant(VT.getSizeInBits() - lg2, 1978 getShiftAmountTy(SGN.getValueType()))); 1979 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL); 1980 AddToWorkList(SRL.getNode()); 1981 AddToWorkList(ADD.getNode()); // Divide by pow2 1982 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD, 1983 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1984 1985 // If we're dividing by a positive value, we're done. Otherwise, we must 1986 // negate the result. 1987 if (N1C->getAPIntValue().isNonNegative()) 1988 return SRA; 1989 1990 AddToWorkList(SRA.getNode()); 1991 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1992 DAG.getConstant(0, VT), SRA); 1993 } 1994 1995 // if integer divide is expensive and we satisfy the requirements, emit an 1996 // alternate sequence. 1997 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1998 SDValue Op = BuildSDIV(N); 1999 if (Op.getNode()) return Op; 2000 } 2001 2002 // undef / X -> 0 2003 if (N0.getOpcode() == ISD::UNDEF) 2004 return DAG.getConstant(0, VT); 2005 // X / undef -> undef 2006 if (N1.getOpcode() == ISD::UNDEF) 2007 return N1; 2008 2009 return SDValue(); 2010} 2011 2012SDValue DAGCombiner::visitUDIV(SDNode *N) { 2013 SDValue N0 = N->getOperand(0); 2014 SDValue N1 = N->getOperand(1); 2015 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 2016 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2017 EVT VT = N->getValueType(0); 2018 2019 // fold vector ops 2020 if (VT.isVector()) { 2021 SDValue FoldedVOp = SimplifyVBinOp(N); 2022 if (FoldedVOp.getNode()) return FoldedVOp; 2023 } 2024 2025 // fold (udiv c1, c2) -> c1/c2 2026 if (N0C && N1C && !N1C->isNullValue()) 2027 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 2028 // fold (udiv x, (1 << c)) -> x >>u c 2029 if (N1C && N1C->getAPIntValue().isPowerOf2()) 2030 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, 2031 DAG.getConstant(N1C->getAPIntValue().logBase2(), 2032 getShiftAmountTy(N0.getValueType()))); 2033 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 2034 if (N1.getOpcode() == ISD::SHL) { 2035 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2036 if (SHC->getAPIntValue().isPowerOf2()) { 2037 EVT ADDVT = N1.getOperand(1).getValueType(); 2038 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT, 2039 N1.getOperand(1), 2040 DAG.getConstant(SHC->getAPIntValue() 2041 .logBase2(), 2042 ADDVT)); 2043 AddToWorkList(Add.getNode()); 2044 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add); 2045 } 2046 } 2047 } 2048 // fold (udiv x, c) -> alternate 2049 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 2050 SDValue Op = BuildUDIV(N); 2051 if (Op.getNode()) return Op; 2052 } 2053 2054 // undef / X -> 0 2055 if (N0.getOpcode() == ISD::UNDEF) 2056 return DAG.getConstant(0, VT); 2057 // X / undef -> undef 2058 if (N1.getOpcode() == ISD::UNDEF) 2059 return N1; 2060 2061 return SDValue(); 2062} 2063 2064SDValue DAGCombiner::visitSREM(SDNode *N) { 2065 SDValue N0 = N->getOperand(0); 2066 SDValue N1 = N->getOperand(1); 2067 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2068 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2069 EVT VT = N->getValueType(0); 2070 2071 // fold (srem c1, c2) -> c1%c2 2072 if (N0C && N1C && !N1C->isNullValue()) 2073 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 2074 // If we know the sign bits of both operands are zero, strength reduce to a 2075 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 2076 if (!VT.isVector()) { 2077 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 2078 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1); 2079 } 2080 2081 // If X/C can be simplified by the division-by-constant logic, lower 2082 // X%C to the equivalent of X-X/C*C. 2083 if (N1C && !N1C->isNullValue()) { 2084 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1); 2085 AddToWorkList(Div.getNode()); 2086 SDValue OptimizedDiv = combine(Div.getNode()); 2087 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2088 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, 2089 OptimizedDiv, N1); 2090 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul); 2091 AddToWorkList(Mul.getNode()); 2092 return Sub; 2093 } 2094 } 2095 2096 // undef % X -> 0 2097 if (N0.getOpcode() == ISD::UNDEF) 2098 return DAG.getConstant(0, VT); 2099 // X % undef -> undef 2100 if (N1.getOpcode() == ISD::UNDEF) 2101 return N1; 2102 2103 return SDValue(); 2104} 2105 2106SDValue DAGCombiner::visitUREM(SDNode *N) { 2107 SDValue N0 = N->getOperand(0); 2108 SDValue N1 = N->getOperand(1); 2109 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2110 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2111 EVT VT = N->getValueType(0); 2112 2113 // fold (urem c1, c2) -> c1%c2 2114 if (N0C && N1C && !N1C->isNullValue()) 2115 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2116 // fold (urem x, pow2) -> (and x, pow2-1) 2117 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2118 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, 2119 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2120 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2121 if (N1.getOpcode() == ISD::SHL) { 2122 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2123 if (SHC->getAPIntValue().isPowerOf2()) { 2124 SDValue Add = 2125 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, 2126 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2127 VT)); 2128 AddToWorkList(Add.getNode()); 2129 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add); 2130 } 2131 } 2132 } 2133 2134 // If X/C can be simplified by the division-by-constant logic, lower 2135 // X%C to the equivalent of X-X/C*C. 2136 if (N1C && !N1C->isNullValue()) { 2137 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1); 2138 AddToWorkList(Div.getNode()); 2139 SDValue OptimizedDiv = combine(Div.getNode()); 2140 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2141 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, 2142 OptimizedDiv, N1); 2143 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul); 2144 AddToWorkList(Mul.getNode()); 2145 return Sub; 2146 } 2147 } 2148 2149 // undef % X -> 0 2150 if (N0.getOpcode() == ISD::UNDEF) 2151 return DAG.getConstant(0, VT); 2152 // X % undef -> undef 2153 if (N1.getOpcode() == ISD::UNDEF) 2154 return N1; 2155 2156 return SDValue(); 2157} 2158 2159SDValue DAGCombiner::visitMULHS(SDNode *N) { 2160 SDValue N0 = N->getOperand(0); 2161 SDValue N1 = N->getOperand(1); 2162 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2163 EVT VT = N->getValueType(0); 2164 SDLoc DL(N); 2165 2166 // fold (mulhs x, 0) -> 0 2167 if (N1C && N1C->isNullValue()) 2168 return N1; 2169 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2170 if (N1C && N1C->getAPIntValue() == 1) 2171 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0, 2172 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2173 getShiftAmountTy(N0.getValueType()))); 2174 // fold (mulhs x, undef) -> 0 2175 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2176 return DAG.getConstant(0, VT); 2177 2178 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2179 // plus a shift. 2180 if (VT.isSimple() && !VT.isVector()) { 2181 MVT Simple = VT.getSimpleVT(); 2182 unsigned SimpleSize = Simple.getSizeInBits(); 2183 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2184 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2185 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2186 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2187 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2188 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2189 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2190 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2191 } 2192 } 2193 2194 return SDValue(); 2195} 2196 2197SDValue DAGCombiner::visitMULHU(SDNode *N) { 2198 SDValue N0 = N->getOperand(0); 2199 SDValue N1 = N->getOperand(1); 2200 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2201 EVT VT = N->getValueType(0); 2202 SDLoc DL(N); 2203 2204 // fold (mulhu x, 0) -> 0 2205 if (N1C && N1C->isNullValue()) 2206 return N1; 2207 // fold (mulhu x, 1) -> 0 2208 if (N1C && N1C->getAPIntValue() == 1) 2209 return DAG.getConstant(0, N0.getValueType()); 2210 // fold (mulhu x, undef) -> 0 2211 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2212 return DAG.getConstant(0, VT); 2213 2214 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2215 // plus a shift. 2216 if (VT.isSimple() && !VT.isVector()) { 2217 MVT Simple = VT.getSimpleVT(); 2218 unsigned SimpleSize = Simple.getSizeInBits(); 2219 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2220 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2221 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2222 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2223 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2224 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2225 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2226 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2227 } 2228 } 2229 2230 return SDValue(); 2231} 2232 2233/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2234/// compute two values. LoOp and HiOp give the opcodes for the two computations 2235/// that are being performed. Return true if a simplification was made. 2236/// 2237SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2238 unsigned HiOp) { 2239 // If the high half is not needed, just compute the low half. 2240 bool HiExists = N->hasAnyUseOfValue(1); 2241 if (!HiExists && 2242 (!LegalOperations || 2243 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2244 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), 2245 N->op_begin(), N->getNumOperands()); 2246 return CombineTo(N, Res, Res); 2247 } 2248 2249 // If the low half is not needed, just compute the high half. 2250 bool LoExists = N->hasAnyUseOfValue(0); 2251 if (!LoExists && 2252 (!LegalOperations || 2253 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2254 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), 2255 N->op_begin(), N->getNumOperands()); 2256 return CombineTo(N, Res, Res); 2257 } 2258 2259 // If both halves are used, return as it is. 2260 if (LoExists && HiExists) 2261 return SDValue(); 2262 2263 // If the two computed results can be simplified separately, separate them. 2264 if (LoExists) { 2265 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), 2266 N->op_begin(), N->getNumOperands()); 2267 AddToWorkList(Lo.getNode()); 2268 SDValue LoOpt = combine(Lo.getNode()); 2269 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2270 (!LegalOperations || 2271 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2272 return CombineTo(N, LoOpt, LoOpt); 2273 } 2274 2275 if (HiExists) { 2276 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), 2277 N->op_begin(), N->getNumOperands()); 2278 AddToWorkList(Hi.getNode()); 2279 SDValue HiOpt = combine(Hi.getNode()); 2280 if (HiOpt.getNode() && HiOpt != Hi && 2281 (!LegalOperations || 2282 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2283 return CombineTo(N, HiOpt, HiOpt); 2284 } 2285 2286 return SDValue(); 2287} 2288 2289SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2290 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2291 if (Res.getNode()) return Res; 2292 2293 EVT VT = N->getValueType(0); 2294 SDLoc DL(N); 2295 2296 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2297 // plus a shift. 2298 if (VT.isSimple() && !VT.isVector()) { 2299 MVT Simple = VT.getSimpleVT(); 2300 unsigned SimpleSize = Simple.getSizeInBits(); 2301 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2302 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2303 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2304 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2305 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2306 // Compute the high part as N1. 2307 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2308 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2309 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2310 // Compute the low part as N0. 2311 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2312 return CombineTo(N, Lo, Hi); 2313 } 2314 } 2315 2316 return SDValue(); 2317} 2318 2319SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2320 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2321 if (Res.getNode()) return Res; 2322 2323 EVT VT = N->getValueType(0); 2324 SDLoc DL(N); 2325 2326 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2327 // plus a shift. 2328 if (VT.isSimple() && !VT.isVector()) { 2329 MVT Simple = VT.getSimpleVT(); 2330 unsigned SimpleSize = Simple.getSizeInBits(); 2331 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2332 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2333 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2334 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2335 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2336 // Compute the high part as N1. 2337 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2338 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2339 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2340 // Compute the low part as N0. 2341 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2342 return CombineTo(N, Lo, Hi); 2343 } 2344 } 2345 2346 return SDValue(); 2347} 2348 2349SDValue DAGCombiner::visitSMULO(SDNode *N) { 2350 // (smulo x, 2) -> (saddo x, x) 2351 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2352 if (C2->getAPIntValue() == 2) 2353 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(), 2354 N->getOperand(0), N->getOperand(0)); 2355 2356 return SDValue(); 2357} 2358 2359SDValue DAGCombiner::visitUMULO(SDNode *N) { 2360 // (umulo x, 2) -> (uaddo x, x) 2361 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2362 if (C2->getAPIntValue() == 2) 2363 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(), 2364 N->getOperand(0), N->getOperand(0)); 2365 2366 return SDValue(); 2367} 2368 2369SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2370 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2371 if (Res.getNode()) return Res; 2372 2373 return SDValue(); 2374} 2375 2376SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2377 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2378 if (Res.getNode()) return Res; 2379 2380 return SDValue(); 2381} 2382 2383/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2384/// two operands of the same opcode, try to simplify it. 2385SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2386 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2387 EVT VT = N0.getValueType(); 2388 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2389 2390 // Bail early if none of these transforms apply. 2391 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2392 2393 // For each of OP in AND/OR/XOR: 2394 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2395 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2396 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2397 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2398 // 2399 // do not sink logical op inside of a vector extend, since it may combine 2400 // into a vsetcc. 2401 EVT Op0VT = N0.getOperand(0).getValueType(); 2402 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2403 N0.getOpcode() == ISD::SIGN_EXTEND || 2404 // Avoid infinite looping with PromoteIntBinOp. 2405 (N0.getOpcode() == ISD::ANY_EXTEND && 2406 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2407 (N0.getOpcode() == ISD::TRUNCATE && 2408 (!TLI.isZExtFree(VT, Op0VT) || 2409 !TLI.isTruncateFree(Op0VT, VT)) && 2410 TLI.isTypeLegal(Op0VT))) && 2411 !VT.isVector() && 2412 Op0VT == N1.getOperand(0).getValueType() && 2413 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2414 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0), 2415 N0.getOperand(0).getValueType(), 2416 N0.getOperand(0), N1.getOperand(0)); 2417 AddToWorkList(ORNode.getNode()); 2418 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode); 2419 } 2420 2421 // For each of OP in SHL/SRL/SRA/AND... 2422 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2423 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2424 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2425 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2426 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2427 N0.getOperand(1) == N1.getOperand(1)) { 2428 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0), 2429 N0.getOperand(0).getValueType(), 2430 N0.getOperand(0), N1.getOperand(0)); 2431 AddToWorkList(ORNode.getNode()); 2432 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, 2433 ORNode, N0.getOperand(1)); 2434 } 2435 2436 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2437 // Only perform this optimization after type legalization and before 2438 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2439 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2440 // we don't want to undo this promotion. 2441 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2442 // on scalars. 2443 if ((N0.getOpcode() == ISD::BITCAST || 2444 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && 2445 Level == AfterLegalizeTypes) { 2446 SDValue In0 = N0.getOperand(0); 2447 SDValue In1 = N1.getOperand(0); 2448 EVT In0Ty = In0.getValueType(); 2449 EVT In1Ty = In1.getValueType(); 2450 SDLoc DL(N); 2451 // If both incoming values are integers, and the original types are the 2452 // same. 2453 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2454 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1); 2455 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op); 2456 AddToWorkList(Op.getNode()); 2457 return BC; 2458 } 2459 } 2460 2461 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2462 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2463 // If both shuffles use the same mask, and both shuffle within a single 2464 // vector, then it is worthwhile to move the swizzle after the operation. 2465 // The type-legalizer generates this pattern when loading illegal 2466 // vector types from memory. In many cases this allows additional shuffle 2467 // optimizations. 2468 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2469 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2470 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2471 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2472 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2473 2474 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2475 "Inputs to shuffles are not the same type"); 2476 2477 unsigned NumElts = VT.getVectorNumElements(); 2478 2479 // Check that both shuffles use the same mask. The masks are known to be of 2480 // the same length because the result vector type is the same. 2481 bool SameMask = true; 2482 for (unsigned i = 0; i != NumElts; ++i) { 2483 int Idx0 = SVN0->getMaskElt(i); 2484 int Idx1 = SVN1->getMaskElt(i); 2485 if (Idx0 != Idx1) { 2486 SameMask = false; 2487 break; 2488 } 2489 } 2490 2491 if (SameMask) { 2492 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N), VT, 2493 N0.getOperand(0), N1.getOperand(0)); 2494 AddToWorkList(Op.getNode()); 2495 return DAG.getVectorShuffle(VT, SDLoc(N), Op, 2496 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2497 } 2498 } 2499 2500 return SDValue(); 2501} 2502 2503SDValue DAGCombiner::visitAND(SDNode *N) { 2504 SDValue N0 = N->getOperand(0); 2505 SDValue N1 = N->getOperand(1); 2506 SDValue LL, LR, RL, RR, CC0, CC1; 2507 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2508 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2509 EVT VT = N1.getValueType(); 2510 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2511 2512 // fold vector ops 2513 if (VT.isVector()) { 2514 SDValue FoldedVOp = SimplifyVBinOp(N); 2515 if (FoldedVOp.getNode()) return FoldedVOp; 2516 2517 // fold (and x, 0) -> 0, vector edition 2518 if (ISD::isBuildVectorAllZeros(N0.getNode())) 2519 return N0; 2520 if (ISD::isBuildVectorAllZeros(N1.getNode())) 2521 return N1; 2522 2523 // fold (and x, -1) -> x, vector edition 2524 if (ISD::isBuildVectorAllOnes(N0.getNode())) 2525 return N1; 2526 if (ISD::isBuildVectorAllOnes(N1.getNode())) 2527 return N0; 2528 } 2529 2530 // fold (and x, undef) -> 0 2531 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2532 return DAG.getConstant(0, VT); 2533 // fold (and c1, c2) -> c1&c2 2534 if (N0C && N1C) 2535 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2536 // canonicalize constant to RHS 2537 if (N0C && !N1C) 2538 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0); 2539 // fold (and x, -1) -> x 2540 if (N1C && N1C->isAllOnesValue()) 2541 return N0; 2542 // if (and x, c) is known to be zero, return 0 2543 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2544 APInt::getAllOnesValue(BitWidth))) 2545 return DAG.getConstant(0, VT); 2546 // reassociate and 2547 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1); 2548 if (RAND.getNode() != 0) 2549 return RAND; 2550 // fold (and (or x, C), D) -> D if (C & D) == D 2551 if (N1C && N0.getOpcode() == ISD::OR) 2552 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2553 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2554 return N1; 2555 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2556 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2557 SDValue N0Op0 = N0.getOperand(0); 2558 APInt Mask = ~N1C->getAPIntValue(); 2559 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2560 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2561 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), 2562 N0.getValueType(), N0Op0); 2563 2564 // Replace uses of the AND with uses of the Zero extend node. 2565 CombineTo(N, Zext); 2566 2567 // We actually want to replace all uses of the any_extend with the 2568 // zero_extend, to avoid duplicating things. This will later cause this 2569 // AND to be folded. 2570 CombineTo(N0.getNode(), Zext); 2571 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2572 } 2573 } 2574 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2575 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2576 // already be zero by virtue of the width of the base type of the load. 2577 // 2578 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2579 // more cases. 2580 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2581 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2582 N0.getOpcode() == ISD::LOAD) { 2583 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2584 N0 : N0.getOperand(0) ); 2585 2586 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2587 // This can be a pure constant or a vector splat, in which case we treat the 2588 // vector as a scalar and use the splat value. 2589 APInt Constant = APInt::getNullValue(1); 2590 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2591 Constant = C->getAPIntValue(); 2592 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2593 APInt SplatValue, SplatUndef; 2594 unsigned SplatBitSize; 2595 bool HasAnyUndefs; 2596 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2597 SplatBitSize, HasAnyUndefs); 2598 if (IsSplat) { 2599 // Undef bits can contribute to a possible optimisation if set, so 2600 // set them. 2601 SplatValue |= SplatUndef; 2602 2603 // The splat value may be something like "0x00FFFFFF", which means 0 for 2604 // the first vector value and FF for the rest, repeating. We need a mask 2605 // that will apply equally to all members of the vector, so AND all the 2606 // lanes of the constant together. 2607 EVT VT = Vector->getValueType(0); 2608 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2609 2610 // If the splat value has been compressed to a bitlength lower 2611 // than the size of the vector lane, we need to re-expand it to 2612 // the lane size. 2613 if (BitWidth > SplatBitSize) 2614 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2615 SplatBitSize < BitWidth; 2616 SplatBitSize = SplatBitSize * 2) 2617 SplatValue |= SplatValue.shl(SplatBitSize); 2618 2619 Constant = APInt::getAllOnesValue(BitWidth); 2620 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2621 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2622 } 2623 } 2624 2625 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2626 // actually legal and isn't going to get expanded, else this is a false 2627 // optimisation. 2628 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2629 Load->getMemoryVT()); 2630 2631 // Resize the constant to the same size as the original memory access before 2632 // extension. If it is still the AllOnesValue then this AND is completely 2633 // unneeded. 2634 Constant = 2635 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2636 2637 bool B; 2638 switch (Load->getExtensionType()) { 2639 default: B = false; break; 2640 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2641 case ISD::ZEXTLOAD: 2642 case ISD::NON_EXTLOAD: B = true; break; 2643 } 2644 2645 if (B && Constant.isAllOnesValue()) { 2646 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2647 // preserve semantics once we get rid of the AND. 2648 SDValue NewLoad(Load, 0); 2649 if (Load->getExtensionType() == ISD::EXTLOAD) { 2650 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2651 Load->getValueType(0), SDLoc(Load), 2652 Load->getChain(), Load->getBasePtr(), 2653 Load->getOffset(), Load->getMemoryVT(), 2654 Load->getMemOperand()); 2655 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2656 if (Load->getNumValues() == 3) { 2657 // PRE/POST_INC loads have 3 values. 2658 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2659 NewLoad.getValue(2) }; 2660 CombineTo(Load, To, 3, true); 2661 } else { 2662 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2663 } 2664 } 2665 2666 // Fold the AND away, taking care not to fold to the old load node if we 2667 // replaced it. 2668 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2669 2670 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2671 } 2672 } 2673 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2674 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2675 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2676 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2677 2678 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2679 LL.getValueType().isInteger()) { 2680 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2681 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2682 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0), 2683 LR.getValueType(), LL, RL); 2684 AddToWorkList(ORNode.getNode()); 2685 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1); 2686 } 2687 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2688 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2689 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0), 2690 LR.getValueType(), LL, RL); 2691 AddToWorkList(ANDNode.getNode()); 2692 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1); 2693 } 2694 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2695 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2696 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0), 2697 LR.getValueType(), LL, RL); 2698 AddToWorkList(ORNode.getNode()); 2699 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1); 2700 } 2701 } 2702 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2) 2703 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) && 2704 Op0 == Op1 && LL.getValueType().isInteger() && 2705 Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() && 2706 cast<ConstantSDNode>(RR)->isAllOnesValue()) || 2707 (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2708 cast<ConstantSDNode>(RR)->isNullValue()))) { 2709 SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(), 2710 LL, DAG.getConstant(1, LL.getValueType())); 2711 AddToWorkList(ADDNode.getNode()); 2712 return DAG.getSetCC(SDLoc(N), VT, ADDNode, 2713 DAG.getConstant(2, LL.getValueType()), ISD::SETUGE); 2714 } 2715 // canonicalize equivalent to ll == rl 2716 if (LL == RR && LR == RL) { 2717 Op1 = ISD::getSetCCSwappedOperands(Op1); 2718 std::swap(RL, RR); 2719 } 2720 if (LL == RL && LR == RR) { 2721 bool isInteger = LL.getValueType().isInteger(); 2722 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2723 if (Result != ISD::SETCC_INVALID && 2724 (!LegalOperations || 2725 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) && 2726 TLI.isOperationLegal(ISD::SETCC, 2727 getSetCCResultType(N0.getSimpleValueType()))))) 2728 return DAG.getSetCC(SDLoc(N), N0.getValueType(), 2729 LL, LR, Result); 2730 } 2731 } 2732 2733 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2734 if (N0.getOpcode() == N1.getOpcode()) { 2735 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2736 if (Tmp.getNode()) return Tmp; 2737 } 2738 2739 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2740 // fold (and (sra)) -> (and (srl)) when possible. 2741 if (!VT.isVector() && 2742 SimplifyDemandedBits(SDValue(N, 0))) 2743 return SDValue(N, 0); 2744 2745 // fold (zext_inreg (extload x)) -> (zextload x) 2746 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2747 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2748 EVT MemVT = LN0->getMemoryVT(); 2749 // If we zero all the possible extended bits, then we can turn this into 2750 // a zextload if we are running before legalize or the operation is legal. 2751 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2752 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2753 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2754 ((!LegalOperations && !LN0->isVolatile()) || 2755 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2756 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, 2757 LN0->getChain(), LN0->getBasePtr(), 2758 MemVT, LN0->getMemOperand()); 2759 AddToWorkList(N); 2760 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2761 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2762 } 2763 } 2764 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2765 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2766 N0.hasOneUse()) { 2767 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2768 EVT MemVT = LN0->getMemoryVT(); 2769 // If we zero all the possible extended bits, then we can turn this into 2770 // a zextload if we are running before legalize or the operation is legal. 2771 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2772 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2773 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2774 ((!LegalOperations && !LN0->isVolatile()) || 2775 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2776 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, 2777 LN0->getChain(), LN0->getBasePtr(), 2778 MemVT, LN0->getMemOperand()); 2779 AddToWorkList(N); 2780 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2781 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2782 } 2783 } 2784 2785 // fold (and (load x), 255) -> (zextload x, i8) 2786 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2787 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2788 if (N1C && (N0.getOpcode() == ISD::LOAD || 2789 (N0.getOpcode() == ISD::ANY_EXTEND && 2790 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2791 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2792 LoadSDNode *LN0 = HasAnyExt 2793 ? cast<LoadSDNode>(N0.getOperand(0)) 2794 : cast<LoadSDNode>(N0); 2795 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2796 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) { 2797 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2798 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2799 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2800 EVT LoadedVT = LN0->getMemoryVT(); 2801 2802 if (ExtVT == LoadedVT && 2803 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2804 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2805 2806 SDValue NewLoad = 2807 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, 2808 LN0->getChain(), LN0->getBasePtr(), ExtVT, 2809 LN0->getMemOperand()); 2810 AddToWorkList(N); 2811 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2812 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2813 } 2814 2815 // Do not change the width of a volatile load. 2816 // Do not generate loads of non-round integer types since these can 2817 // be expensive (and would be wrong if the type is not byte sized). 2818 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2819 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2820 EVT PtrType = LN0->getOperand(1).getValueType(); 2821 2822 unsigned Alignment = LN0->getAlignment(); 2823 SDValue NewPtr = LN0->getBasePtr(); 2824 2825 // For big endian targets, we need to add an offset to the pointer 2826 // to load the correct bytes. For little endian systems, we merely 2827 // need to read fewer bytes from the same pointer. 2828 if (TLI.isBigEndian()) { 2829 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2830 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2831 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2832 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType, 2833 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2834 Alignment = MinAlign(Alignment, PtrOff); 2835 } 2836 2837 AddToWorkList(NewPtr.getNode()); 2838 2839 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2840 SDValue Load = 2841 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, 2842 LN0->getChain(), NewPtr, 2843 LN0->getPointerInfo(), 2844 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2845 Alignment, LN0->getTBAAInfo()); 2846 AddToWorkList(N); 2847 CombineTo(LN0, Load, Load.getValue(1)); 2848 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2849 } 2850 } 2851 } 2852 } 2853 2854 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2855 VT.getSizeInBits() <= 64) { 2856 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2857 APInt ADDC = ADDI->getAPIntValue(); 2858 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2859 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2860 // immediate for an add, but it is legal if its top c2 bits are set, 2861 // transform the ADD so the immediate doesn't need to be materialized 2862 // in a register. 2863 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2864 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2865 SRLI->getZExtValue()); 2866 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2867 ADDC |= Mask; 2868 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2869 SDValue NewAdd = 2870 DAG.getNode(ISD::ADD, SDLoc(N0), VT, 2871 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2872 CombineTo(N0.getNode(), NewAdd); 2873 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2874 } 2875 } 2876 } 2877 } 2878 } 2879 } 2880 2881 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const) 2882 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) { 2883 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 2884 N0.getOperand(1), false); 2885 if (BSwap.getNode()) 2886 return BSwap; 2887 } 2888 2889 return SDValue(); 2890} 2891 2892/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2893/// 2894SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2895 bool DemandHighBits) { 2896 if (!LegalOperations) 2897 return SDValue(); 2898 2899 EVT VT = N->getValueType(0); 2900 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2901 return SDValue(); 2902 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2903 return SDValue(); 2904 2905 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2906 bool LookPassAnd0 = false; 2907 bool LookPassAnd1 = false; 2908 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2909 std::swap(N0, N1); 2910 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2911 std::swap(N0, N1); 2912 if (N0.getOpcode() == ISD::AND) { 2913 if (!N0.getNode()->hasOneUse()) 2914 return SDValue(); 2915 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2916 if (!N01C || N01C->getZExtValue() != 0xFF00) 2917 return SDValue(); 2918 N0 = N0.getOperand(0); 2919 LookPassAnd0 = true; 2920 } 2921 2922 if (N1.getOpcode() == ISD::AND) { 2923 if (!N1.getNode()->hasOneUse()) 2924 return SDValue(); 2925 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2926 if (!N11C || N11C->getZExtValue() != 0xFF) 2927 return SDValue(); 2928 N1 = N1.getOperand(0); 2929 LookPassAnd1 = true; 2930 } 2931 2932 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2933 std::swap(N0, N1); 2934 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2935 return SDValue(); 2936 if (!N0.getNode()->hasOneUse() || 2937 !N1.getNode()->hasOneUse()) 2938 return SDValue(); 2939 2940 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2941 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2942 if (!N01C || !N11C) 2943 return SDValue(); 2944 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2945 return SDValue(); 2946 2947 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2948 SDValue N00 = N0->getOperand(0); 2949 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2950 if (!N00.getNode()->hasOneUse()) 2951 return SDValue(); 2952 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2953 if (!N001C || N001C->getZExtValue() != 0xFF) 2954 return SDValue(); 2955 N00 = N00.getOperand(0); 2956 LookPassAnd0 = true; 2957 } 2958 2959 SDValue N10 = N1->getOperand(0); 2960 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2961 if (!N10.getNode()->hasOneUse()) 2962 return SDValue(); 2963 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2964 if (!N101C || N101C->getZExtValue() != 0xFF00) 2965 return SDValue(); 2966 N10 = N10.getOperand(0); 2967 LookPassAnd1 = true; 2968 } 2969 2970 if (N00 != N10) 2971 return SDValue(); 2972 2973 // Make sure everything beyond the low halfword gets set to zero since the SRL 2974 // 16 will clear the top bits. 2975 unsigned OpSizeInBits = VT.getSizeInBits(); 2976 if (DemandHighBits && OpSizeInBits > 16) { 2977 // If the left-shift isn't masked out then the only way this is a bswap is 2978 // if all bits beyond the low 8 are 0. In that case the entire pattern 2979 // reduces to a left shift anyway: leave it for other parts of the combiner. 2980 if (!LookPassAnd0) 2981 return SDValue(); 2982 2983 // However, if the right shift isn't masked out then it might be because 2984 // it's not needed. See if we can spot that too. 2985 if (!LookPassAnd1 && 2986 !DAG.MaskedValueIsZero( 2987 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16))) 2988 return SDValue(); 2989 } 2990 2991 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00); 2992 if (OpSizeInBits > 16) 2993 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res, 2994 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2995 return Res; 2996} 2997 2998/// isBSwapHWordElement - Return true if the specified node is an element 2999/// that makes up a 32-bit packed halfword byteswap. i.e. 3000/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 3001static bool isBSwapHWordElement(SDValue N, SmallVectorImpl<SDNode *> &Parts) { 3002 if (!N.getNode()->hasOneUse()) 3003 return false; 3004 3005 unsigned Opc = N.getOpcode(); 3006 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 3007 return false; 3008 3009 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 3010 if (!N1C) 3011 return false; 3012 3013 unsigned Num; 3014 switch (N1C->getZExtValue()) { 3015 default: 3016 return false; 3017 case 0xFF: Num = 0; break; 3018 case 0xFF00: Num = 1; break; 3019 case 0xFF0000: Num = 2; break; 3020 case 0xFF000000: Num = 3; break; 3021 } 3022 3023 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 3024 SDValue N0 = N.getOperand(0); 3025 if (Opc == ISD::AND) { 3026 if (Num == 0 || Num == 2) { 3027 // (x >> 8) & 0xff 3028 // (x >> 8) & 0xff0000 3029 if (N0.getOpcode() != ISD::SRL) 3030 return false; 3031 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3032 if (!C || C->getZExtValue() != 8) 3033 return false; 3034 } else { 3035 // (x << 8) & 0xff00 3036 // (x << 8) & 0xff000000 3037 if (N0.getOpcode() != ISD::SHL) 3038 return false; 3039 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3040 if (!C || C->getZExtValue() != 8) 3041 return false; 3042 } 3043 } else if (Opc == ISD::SHL) { 3044 // (x & 0xff) << 8 3045 // (x & 0xff0000) << 8 3046 if (Num != 0 && Num != 2) 3047 return false; 3048 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 3049 if (!C || C->getZExtValue() != 8) 3050 return false; 3051 } else { // Opc == ISD::SRL 3052 // (x & 0xff00) >> 8 3053 // (x & 0xff000000) >> 8 3054 if (Num != 1 && Num != 3) 3055 return false; 3056 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 3057 if (!C || C->getZExtValue() != 8) 3058 return false; 3059 } 3060 3061 if (Parts[Num]) 3062 return false; 3063 3064 Parts[Num] = N0.getOperand(0).getNode(); 3065 return true; 3066} 3067 3068/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 3069/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 3070/// => (rotl (bswap x), 16) 3071SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 3072 if (!LegalOperations) 3073 return SDValue(); 3074 3075 EVT VT = N->getValueType(0); 3076 if (VT != MVT::i32) 3077 return SDValue(); 3078 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 3079 return SDValue(); 3080 3081 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 3082 // Look for either 3083 // (or (or (and), (and)), (or (and), (and))) 3084 // (or (or (or (and), (and)), (and)), (and)) 3085 if (N0.getOpcode() != ISD::OR) 3086 return SDValue(); 3087 SDValue N00 = N0.getOperand(0); 3088 SDValue N01 = N0.getOperand(1); 3089 3090 if (N1.getOpcode() == ISD::OR && 3091 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) { 3092 // (or (or (and), (and)), (or (and), (and))) 3093 SDValue N000 = N00.getOperand(0); 3094 if (!isBSwapHWordElement(N000, Parts)) 3095 return SDValue(); 3096 3097 SDValue N001 = N00.getOperand(1); 3098 if (!isBSwapHWordElement(N001, Parts)) 3099 return SDValue(); 3100 SDValue N010 = N01.getOperand(0); 3101 if (!isBSwapHWordElement(N010, Parts)) 3102 return SDValue(); 3103 SDValue N011 = N01.getOperand(1); 3104 if (!isBSwapHWordElement(N011, Parts)) 3105 return SDValue(); 3106 } else { 3107 // (or (or (or (and), (and)), (and)), (and)) 3108 if (!isBSwapHWordElement(N1, Parts)) 3109 return SDValue(); 3110 if (!isBSwapHWordElement(N01, Parts)) 3111 return SDValue(); 3112 if (N00.getOpcode() != ISD::OR) 3113 return SDValue(); 3114 SDValue N000 = N00.getOperand(0); 3115 if (!isBSwapHWordElement(N000, Parts)) 3116 return SDValue(); 3117 SDValue N001 = N00.getOperand(1); 3118 if (!isBSwapHWordElement(N001, Parts)) 3119 return SDValue(); 3120 } 3121 3122 // Make sure the parts are all coming from the same node. 3123 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 3124 return SDValue(); 3125 3126 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, 3127 SDValue(Parts[0],0)); 3128 3129 // Result of the bswap should be rotated by 16. If it's not legal, then 3130 // do (x << 16) | (x >> 16). 3131 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 3132 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3133 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt); 3134 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3135 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt); 3136 return DAG.getNode(ISD::OR, SDLoc(N), VT, 3137 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt), 3138 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt)); 3139} 3140 3141SDValue DAGCombiner::visitOR(SDNode *N) { 3142 SDValue N0 = N->getOperand(0); 3143 SDValue N1 = N->getOperand(1); 3144 SDValue LL, LR, RL, RR, CC0, CC1; 3145 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3146 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3147 EVT VT = N1.getValueType(); 3148 3149 // fold vector ops 3150 if (VT.isVector()) { 3151 SDValue FoldedVOp = SimplifyVBinOp(N); 3152 if (FoldedVOp.getNode()) return FoldedVOp; 3153 3154 // fold (or x, 0) -> x, vector edition 3155 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3156 return N1; 3157 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3158 return N0; 3159 3160 // fold (or x, -1) -> -1, vector edition 3161 if (ISD::isBuildVectorAllOnes(N0.getNode())) 3162 return N0; 3163 if (ISD::isBuildVectorAllOnes(N1.getNode())) 3164 return N1; 3165 } 3166 3167 // fold (or x, undef) -> -1 3168 if (!LegalOperations && 3169 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3170 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3171 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3172 } 3173 // fold (or c1, c2) -> c1|c2 3174 if (N0C && N1C) 3175 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3176 // canonicalize constant to RHS 3177 if (N0C && !N1C) 3178 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0); 3179 // fold (or x, 0) -> x 3180 if (N1C && N1C->isNullValue()) 3181 return N0; 3182 // fold (or x, -1) -> -1 3183 if (N1C && N1C->isAllOnesValue()) 3184 return N1; 3185 // fold (or x, c) -> c iff (x & ~c) == 0 3186 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3187 return N1; 3188 3189 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3190 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3191 if (BSwap.getNode() != 0) 3192 return BSwap; 3193 BSwap = MatchBSwapHWordLow(N, N0, N1); 3194 if (BSwap.getNode() != 0) 3195 return BSwap; 3196 3197 // reassociate or 3198 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1); 3199 if (ROR.getNode() != 0) 3200 return ROR; 3201 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3202 // iff (c1 & c2) == 0. 3203 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3204 isa<ConstantSDNode>(N0.getOperand(1))) { 3205 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3206 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3207 return DAG.getNode(ISD::AND, SDLoc(N), VT, 3208 DAG.getNode(ISD::OR, SDLoc(N0), VT, 3209 N0.getOperand(0), N1), 3210 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3211 } 3212 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3213 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3214 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3215 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3216 3217 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3218 LL.getValueType().isInteger()) { 3219 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3220 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3221 if (cast<ConstantSDNode>(LR)->isNullValue() && 3222 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3223 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR), 3224 LR.getValueType(), LL, RL); 3225 AddToWorkList(ORNode.getNode()); 3226 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1); 3227 } 3228 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3229 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3230 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3231 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3232 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR), 3233 LR.getValueType(), LL, RL); 3234 AddToWorkList(ANDNode.getNode()); 3235 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1); 3236 } 3237 } 3238 // canonicalize equivalent to ll == rl 3239 if (LL == RR && LR == RL) { 3240 Op1 = ISD::getSetCCSwappedOperands(Op1); 3241 std::swap(RL, RR); 3242 } 3243 if (LL == RL && LR == RR) { 3244 bool isInteger = LL.getValueType().isInteger(); 3245 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3246 if (Result != ISD::SETCC_INVALID && 3247 (!LegalOperations || 3248 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) && 3249 TLI.isOperationLegal(ISD::SETCC, 3250 getSetCCResultType(N0.getValueType()))))) 3251 return DAG.getSetCC(SDLoc(N), N0.getValueType(), 3252 LL, LR, Result); 3253 } 3254 } 3255 3256 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3257 if (N0.getOpcode() == N1.getOpcode()) { 3258 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3259 if (Tmp.getNode()) return Tmp; 3260 } 3261 3262 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3263 if (N0.getOpcode() == ISD::AND && 3264 N1.getOpcode() == ISD::AND && 3265 N0.getOperand(1).getOpcode() == ISD::Constant && 3266 N1.getOperand(1).getOpcode() == ISD::Constant && 3267 // Don't increase # computations. 3268 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3269 // We can only do this xform if we know that bits from X that are set in C2 3270 // but not in C1 are already zero. Likewise for Y. 3271 const APInt &LHSMask = 3272 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3273 const APInt &RHSMask = 3274 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3275 3276 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3277 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3278 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT, 3279 N0.getOperand(0), N1.getOperand(0)); 3280 return DAG.getNode(ISD::AND, SDLoc(N), VT, X, 3281 DAG.getConstant(LHSMask | RHSMask, VT)); 3282 } 3283 } 3284 3285 // See if this is some rotate idiom. 3286 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N))) 3287 return SDValue(Rot, 0); 3288 3289 // Simplify the operands using demanded-bits information. 3290 if (!VT.isVector() && 3291 SimplifyDemandedBits(SDValue(N, 0))) 3292 return SDValue(N, 0); 3293 3294 return SDValue(); 3295} 3296 3297/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3298static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3299 if (Op.getOpcode() == ISD::AND) { 3300 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3301 Mask = Op.getOperand(1); 3302 Op = Op.getOperand(0); 3303 } else { 3304 return false; 3305 } 3306 } 3307 3308 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3309 Shift = Op; 3310 return true; 3311 } 3312 3313 return false; 3314} 3315 3316// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3317// idioms for rotate, and if the target supports rotation instructions, generate 3318// a rot[lr]. 3319SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) { 3320 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3321 EVT VT = LHS.getValueType(); 3322 if (!TLI.isTypeLegal(VT)) return 0; 3323 3324 // The target must have at least one rotate flavor. 3325 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3326 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3327 if (!HasROTL && !HasROTR) return 0; 3328 3329 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3330 SDValue LHSShift; // The shift. 3331 SDValue LHSMask; // AND value if any. 3332 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3333 return 0; // Not part of a rotate. 3334 3335 SDValue RHSShift; // The shift. 3336 SDValue RHSMask; // AND value if any. 3337 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3338 return 0; // Not part of a rotate. 3339 3340 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3341 return 0; // Not shifting the same value. 3342 3343 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3344 return 0; // Shifts must disagree. 3345 3346 // Canonicalize shl to left side in a shl/srl pair. 3347 if (RHSShift.getOpcode() == ISD::SHL) { 3348 std::swap(LHS, RHS); 3349 std::swap(LHSShift, RHSShift); 3350 std::swap(LHSMask , RHSMask ); 3351 } 3352 3353 unsigned OpSizeInBits = VT.getSizeInBits(); 3354 SDValue LHSShiftArg = LHSShift.getOperand(0); 3355 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3356 SDValue RHSShiftArg = RHSShift.getOperand(0); 3357 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3358 3359 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3360 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3361 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3362 RHSShiftAmt.getOpcode() == ISD::Constant) { 3363 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3364 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3365 if ((LShVal + RShVal) != OpSizeInBits) 3366 return 0; 3367 3368 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3369 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt); 3370 3371 // If there is an AND of either shifted operand, apply it to the result. 3372 if (LHSMask.getNode() || RHSMask.getNode()) { 3373 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3374 3375 if (LHSMask.getNode()) { 3376 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3377 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3378 } 3379 if (RHSMask.getNode()) { 3380 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3381 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3382 } 3383 3384 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3385 } 3386 3387 return Rot.getNode(); 3388 } 3389 3390 // If there is a mask here, and we have a variable shift, we can't be sure 3391 // that we're masking out the right stuff. 3392 if (LHSMask.getNode() || RHSMask.getNode()) 3393 return 0; 3394 3395 // If the shift amount is sign/zext/any-extended just peel it off. 3396 SDValue LExtOp0 = LHSShiftAmt; 3397 SDValue RExtOp0 = RHSShiftAmt; 3398 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3399 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3400 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3401 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3402 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3403 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3404 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3405 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3406 LExtOp0 = LHSShiftAmt.getOperand(0); 3407 RExtOp0 = RHSShiftAmt.getOperand(0); 3408 } 3409 3410 if (RExtOp0.getOpcode() == ISD::SUB && RExtOp0.getOperand(1) == LExtOp0) { 3411 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3412 // (rotl x, y) 3413 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3414 // (rotr x, (sub 32, y)) 3415 if (ConstantSDNode *SUBC = 3416 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3417 if (SUBC->getAPIntValue() == OpSizeInBits) { 3418 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, 3419 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3420 } else if (LHSShiftArg.getOpcode() == ISD::ZERO_EXTEND || 3421 LHSShiftArg.getOpcode() == ISD::ANY_EXTEND) { 3422 // fold (or (shl (*ext x), (*ext y)), 3423 // (srl (*ext x), (*ext (sub 32, y)))) -> 3424 // (*ext (rotl x, y)) 3425 // fold (or (shl (*ext x), (*ext y)), 3426 // (srl (*ext x), (*ext (sub 32, y)))) -> 3427 // (*ext (rotr x, (sub 32, y))) 3428 SDValue LArgExtOp0 = LHSShiftArg.getOperand(0); 3429 EVT LArgVT = LArgExtOp0.getValueType(); 3430 bool HasROTRWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTR, LArgVT); 3431 bool HasROTLWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTL, LArgVT); 3432 if (HasROTRWithLArg || HasROTLWithLArg) { 3433 if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) { 3434 SDValue V = 3435 DAG.getNode(HasROTLWithLArg ? ISD::ROTL : ISD::ROTR, DL, LArgVT, 3436 LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt); 3437 return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode(); 3438 } 3439 } 3440 } 3441 } 3442 } else if (LExtOp0.getOpcode() == ISD::SUB && 3443 RExtOp0 == LExtOp0.getOperand(1)) { 3444 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3445 // (rotr x, y) 3446 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3447 // (rotl x, (sub 32, y)) 3448 if (ConstantSDNode *SUBC = 3449 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3450 if (SUBC->getAPIntValue() == OpSizeInBits) { 3451 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, 3452 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3453 } else if (RHSShiftArg.getOpcode() == ISD::ZERO_EXTEND || 3454 RHSShiftArg.getOpcode() == ISD::ANY_EXTEND) { 3455 // fold (or (shl (*ext x), (*ext (sub 32, y))), 3456 // (srl (*ext x), (*ext y))) -> 3457 // (*ext (rotl x, y)) 3458 // fold (or (shl (*ext x), (*ext (sub 32, y))), 3459 // (srl (*ext x), (*ext y))) -> 3460 // (*ext (rotr x, (sub 32, y))) 3461 SDValue RArgExtOp0 = RHSShiftArg.getOperand(0); 3462 EVT RArgVT = RArgExtOp0.getValueType(); 3463 bool HasROTRWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTR, RArgVT); 3464 bool HasROTLWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTL, RArgVT); 3465 if (HasROTRWithRArg || HasROTLWithRArg) { 3466 if (RArgVT.getSizeInBits() == SUBC->getAPIntValue()) { 3467 SDValue V = 3468 DAG.getNode(HasROTRWithRArg ? ISD::ROTR : ISD::ROTL, DL, RArgVT, 3469 RArgExtOp0, HasROTR ? RHSShiftAmt : LHSShiftAmt); 3470 return DAG.getNode(RHSShiftArg.getOpcode(), DL, VT, V).getNode(); 3471 } 3472 } 3473 } 3474 } 3475 } 3476 3477 return 0; 3478} 3479 3480SDValue DAGCombiner::visitXOR(SDNode *N) { 3481 SDValue N0 = N->getOperand(0); 3482 SDValue N1 = N->getOperand(1); 3483 SDValue LHS, RHS, CC; 3484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3486 EVT VT = N0.getValueType(); 3487 3488 // fold vector ops 3489 if (VT.isVector()) { 3490 SDValue FoldedVOp = SimplifyVBinOp(N); 3491 if (FoldedVOp.getNode()) return FoldedVOp; 3492 3493 // fold (xor x, 0) -> x, vector edition 3494 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3495 return N1; 3496 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3497 return N0; 3498 } 3499 3500 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3501 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3502 return DAG.getConstant(0, VT); 3503 // fold (xor x, undef) -> undef 3504 if (N0.getOpcode() == ISD::UNDEF) 3505 return N0; 3506 if (N1.getOpcode() == ISD::UNDEF) 3507 return N1; 3508 // fold (xor c1, c2) -> c1^c2 3509 if (N0C && N1C) 3510 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3511 // canonicalize constant to RHS 3512 if (N0C && !N1C) 3513 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0); 3514 // fold (xor x, 0) -> x 3515 if (N1C && N1C->isNullValue()) 3516 return N0; 3517 // reassociate xor 3518 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1); 3519 if (RXOR.getNode() != 0) 3520 return RXOR; 3521 3522 // fold !(x cc y) -> (x !cc y) 3523 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3524 bool isInt = LHS.getValueType().isInteger(); 3525 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3526 isInt); 3527 3528 if (!LegalOperations || 3529 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) { 3530 switch (N0.getOpcode()) { 3531 default: 3532 llvm_unreachable("Unhandled SetCC Equivalent!"); 3533 case ISD::SETCC: 3534 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC); 3535 case ISD::SELECT_CC: 3536 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2), 3537 N0.getOperand(3), NotCC); 3538 } 3539 } 3540 } 3541 3542 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3543 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3544 N0.getNode()->hasOneUse() && 3545 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3546 SDValue V = N0.getOperand(0); 3547 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V, 3548 DAG.getConstant(1, V.getValueType())); 3549 AddToWorkList(V.getNode()); 3550 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V); 3551 } 3552 3553 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3554 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3555 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3556 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3557 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3558 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3559 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS 3560 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS 3561 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3562 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); 3563 } 3564 } 3565 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3566 if (N1C && N1C->isAllOnesValue() && 3567 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3568 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3569 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3570 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3571 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS 3572 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS 3573 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3574 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); 3575 } 3576 } 3577 // fold (xor (and x, y), y) -> (and (not x), y) 3578 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3579 N0->getOperand(1) == N1 && isTypeLegal(VT.getScalarType())) { 3580 SDValue X = N0->getOperand(0); 3581 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT); 3582 AddToWorkList(NotX.getNode()); 3583 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1); 3584 } 3585 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3586 if (N1C && N0.getOpcode() == ISD::XOR) { 3587 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3588 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3589 if (N00C) 3590 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1), 3591 DAG.getConstant(N1C->getAPIntValue() ^ 3592 N00C->getAPIntValue(), VT)); 3593 if (N01C) 3594 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0), 3595 DAG.getConstant(N1C->getAPIntValue() ^ 3596 N01C->getAPIntValue(), VT)); 3597 } 3598 // fold (xor x, x) -> 0 3599 if (N0 == N1) 3600 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes); 3601 3602 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3603 if (N0.getOpcode() == N1.getOpcode()) { 3604 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3605 if (Tmp.getNode()) return Tmp; 3606 } 3607 3608 // Simplify the expression using non-local knowledge. 3609 if (!VT.isVector() && 3610 SimplifyDemandedBits(SDValue(N, 0))) 3611 return SDValue(N, 0); 3612 3613 return SDValue(); 3614} 3615 3616/// visitShiftByConstant - Handle transforms common to the three shifts, when 3617/// the shift amount is a constant. 3618SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3619 SDNode *LHS = N->getOperand(0).getNode(); 3620 if (!LHS->hasOneUse()) return SDValue(); 3621 3622 // We want to pull some binops through shifts, so that we have (and (shift)) 3623 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3624 // thing happens with address calculations, so it's important to canonicalize 3625 // it. 3626 bool HighBitSet = false; // Can we transform this if the high bit is set? 3627 3628 switch (LHS->getOpcode()) { 3629 default: return SDValue(); 3630 case ISD::OR: 3631 case ISD::XOR: 3632 HighBitSet = false; // We can only transform sra if the high bit is clear. 3633 break; 3634 case ISD::AND: 3635 HighBitSet = true; // We can only transform sra if the high bit is set. 3636 break; 3637 case ISD::ADD: 3638 if (N->getOpcode() != ISD::SHL) 3639 return SDValue(); // only shl(add) not sr[al](add). 3640 HighBitSet = false; // We can only transform sra if the high bit is clear. 3641 break; 3642 } 3643 3644 // We require the RHS of the binop to be a constant as well. 3645 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3646 if (!BinOpCst) return SDValue(); 3647 3648 // FIXME: disable this unless the input to the binop is a shift by a constant. 3649 // If it is not a shift, it pessimizes some common cases like: 3650 // 3651 // void foo(int *X, int i) { X[i & 1235] = 1; } 3652 // int bar(int *X, int i) { return X[i & 255]; } 3653 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3654 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3655 BinOpLHSVal->getOpcode() != ISD::SRA && 3656 BinOpLHSVal->getOpcode() != ISD::SRL) || 3657 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3658 return SDValue(); 3659 3660 EVT VT = N->getValueType(0); 3661 3662 // If this is a signed shift right, and the high bit is modified by the 3663 // logical operation, do not perform the transformation. The highBitSet 3664 // boolean indicates the value of the high bit of the constant which would 3665 // cause it to be modified for this operation. 3666 if (N->getOpcode() == ISD::SRA) { 3667 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3668 if (BinOpRHSSignSet != HighBitSet) 3669 return SDValue(); 3670 } 3671 3672 // Fold the constants, shifting the binop RHS by the shift amount. 3673 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)), 3674 N->getValueType(0), 3675 LHS->getOperand(1), N->getOperand(1)); 3676 3677 // Create the new shift. 3678 SDValue NewShift = DAG.getNode(N->getOpcode(), 3679 SDLoc(LHS->getOperand(0)), 3680 VT, LHS->getOperand(0), N->getOperand(1)); 3681 3682 // Create the new binop. 3683 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS); 3684} 3685 3686SDValue DAGCombiner::visitSHL(SDNode *N) { 3687 SDValue N0 = N->getOperand(0); 3688 SDValue N1 = N->getOperand(1); 3689 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3690 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3691 EVT VT = N0.getValueType(); 3692 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3693 3694 // fold (shl c1, c2) -> c1<<c2 3695 if (N0C && N1C) 3696 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3697 // fold (shl 0, x) -> 0 3698 if (N0C && N0C->isNullValue()) 3699 return N0; 3700 // fold (shl x, c >= size(x)) -> undef 3701 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3702 return DAG.getUNDEF(VT); 3703 // fold (shl x, 0) -> x 3704 if (N1C && N1C->isNullValue()) 3705 return N0; 3706 // fold (shl undef, x) -> 0 3707 if (N0.getOpcode() == ISD::UNDEF) 3708 return DAG.getConstant(0, VT); 3709 // if (shl x, c) is known to be zero, return 0 3710 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3711 APInt::getAllOnesValue(OpSizeInBits))) 3712 return DAG.getConstant(0, VT); 3713 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3714 if (N1.getOpcode() == ISD::TRUNCATE && 3715 N1.getOperand(0).getOpcode() == ISD::AND && 3716 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3717 SDValue N101 = N1.getOperand(0).getOperand(1); 3718 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3719 EVT TruncVT = N1.getValueType(); 3720 SDValue N100 = N1.getOperand(0).getOperand(0); 3721 APInt TruncC = N101C->getAPIntValue(); 3722 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3723 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, 3724 DAG.getNode(ISD::AND, SDLoc(N), TruncVT, 3725 DAG.getNode(ISD::TRUNCATE, 3726 SDLoc(N), 3727 TruncVT, N100), 3728 DAG.getConstant(TruncC, TruncVT))); 3729 } 3730 } 3731 3732 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3733 return SDValue(N, 0); 3734 3735 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3736 if (N1C && N0.getOpcode() == ISD::SHL && 3737 N0.getOperand(1).getOpcode() == ISD::Constant) { 3738 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3739 uint64_t c2 = N1C->getZExtValue(); 3740 if (c1 + c2 >= OpSizeInBits) 3741 return DAG.getConstant(0, VT); 3742 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0), 3743 DAG.getConstant(c1 + c2, N1.getValueType())); 3744 } 3745 3746 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3747 // For this to be valid, the second form must not preserve any of the bits 3748 // that are shifted out by the inner shift in the first form. This means 3749 // the outer shift size must be >= the number of bits added by the ext. 3750 // As a corollary, we don't care what kind of ext it is. 3751 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3752 N0.getOpcode() == ISD::ANY_EXTEND || 3753 N0.getOpcode() == ISD::SIGN_EXTEND) && 3754 N0.getOperand(0).getOpcode() == ISD::SHL && 3755 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3756 uint64_t c1 = 3757 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3758 uint64_t c2 = N1C->getZExtValue(); 3759 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3760 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3761 if (c2 >= OpSizeInBits - InnerShiftSize) { 3762 if (c1 + c2 >= OpSizeInBits) 3763 return DAG.getConstant(0, VT); 3764 return DAG.getNode(ISD::SHL, SDLoc(N0), VT, 3765 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT, 3766 N0.getOperand(0)->getOperand(0)), 3767 DAG.getConstant(c1 + c2, N1.getValueType())); 3768 } 3769 } 3770 3771 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C)) 3772 // Only fold this if the inner zext has no other uses to avoid increasing 3773 // the total number of instructions. 3774 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() && 3775 N0.getOperand(0).getOpcode() == ISD::SRL && 3776 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3777 uint64_t c1 = 3778 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3779 if (c1 < VT.getSizeInBits()) { 3780 uint64_t c2 = N1C->getZExtValue(); 3781 if (c1 == c2) { 3782 SDValue NewOp0 = N0.getOperand(0); 3783 EVT CountVT = NewOp0.getOperand(1).getValueType(); 3784 SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(), 3785 NewOp0, DAG.getConstant(c2, CountVT)); 3786 AddToWorkList(NewSHL.getNode()); 3787 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL); 3788 } 3789 } 3790 } 3791 3792 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3793 // (and (srl x, (sub c1, c2), MASK) 3794 // Only fold this if the inner shift has no other uses -- if it does, folding 3795 // this will increase the total number of instructions. 3796 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3797 N0.getOperand(1).getOpcode() == ISD::Constant) { 3798 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3799 if (c1 < VT.getSizeInBits()) { 3800 uint64_t c2 = N1C->getZExtValue(); 3801 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3802 VT.getSizeInBits() - c1); 3803 SDValue Shift; 3804 if (c2 > c1) { 3805 Mask = Mask.shl(c2-c1); 3806 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0), 3807 DAG.getConstant(c2-c1, N1.getValueType())); 3808 } else { 3809 Mask = Mask.lshr(c1-c2); 3810 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), 3811 DAG.getConstant(c1-c2, N1.getValueType())); 3812 } 3813 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift, 3814 DAG.getConstant(Mask, VT)); 3815 } 3816 } 3817 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3818 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3819 SDValue HiBitsMask = 3820 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3821 VT.getSizeInBits() - 3822 N1C->getZExtValue()), 3823 VT); 3824 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0), 3825 HiBitsMask); 3826 } 3827 3828 if (N1C) { 3829 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3830 if (NewSHL.getNode()) 3831 return NewSHL; 3832 } 3833 3834 return SDValue(); 3835} 3836 3837SDValue DAGCombiner::visitSRA(SDNode *N) { 3838 SDValue N0 = N->getOperand(0); 3839 SDValue N1 = N->getOperand(1); 3840 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3841 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3842 EVT VT = N0.getValueType(); 3843 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3844 3845 // fold (sra c1, c2) -> (sra c1, c2) 3846 if (N0C && N1C) 3847 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3848 // fold (sra 0, x) -> 0 3849 if (N0C && N0C->isNullValue()) 3850 return N0; 3851 // fold (sra -1, x) -> -1 3852 if (N0C && N0C->isAllOnesValue()) 3853 return N0; 3854 // fold (sra x, (setge c, size(x))) -> undef 3855 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3856 return DAG.getUNDEF(VT); 3857 // fold (sra x, 0) -> x 3858 if (N1C && N1C->isNullValue()) 3859 return N0; 3860 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3861 // sext_inreg. 3862 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3863 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3864 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3865 if (VT.isVector()) 3866 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3867 ExtVT, VT.getVectorNumElements()); 3868 if ((!LegalOperations || 3869 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3870 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, 3871 N0.getOperand(0), DAG.getValueType(ExtVT)); 3872 } 3873 3874 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3875 if (N1C && N0.getOpcode() == ISD::SRA) { 3876 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3877 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3878 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3879 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0), 3880 DAG.getConstant(Sum, N1C->getValueType(0))); 3881 } 3882 } 3883 3884 // fold (sra (shl X, m), (sub result_size, n)) 3885 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3886 // result_size - n != m. 3887 // If truncate is free for the target sext(shl) is likely to result in better 3888 // code. 3889 if (N0.getOpcode() == ISD::SHL) { 3890 // Get the two constanst of the shifts, CN0 = m, CN = n. 3891 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3892 if (N01C && N1C) { 3893 // Determine what the truncate's result bitsize and type would be. 3894 EVT TruncVT = 3895 EVT::getIntegerVT(*DAG.getContext(), 3896 OpSizeInBits - N1C->getZExtValue()); 3897 // Determine the residual right-shift amount. 3898 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3899 3900 // If the shift is not a no-op (in which case this should be just a sign 3901 // extend already), the truncated to type is legal, sign_extend is legal 3902 // on that type, and the truncate to that type is both legal and free, 3903 // perform the transform. 3904 if ((ShiftAmt > 0) && 3905 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3906 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3907 TLI.isTruncateFree(VT, TruncVT)) { 3908 3909 SDValue Amt = DAG.getConstant(ShiftAmt, 3910 getShiftAmountTy(N0.getOperand(0).getValueType())); 3911 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT, 3912 N0.getOperand(0), Amt); 3913 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT, 3914 Shift); 3915 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), 3916 N->getValueType(0), Trunc); 3917 } 3918 } 3919 } 3920 3921 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3922 if (N1.getOpcode() == ISD::TRUNCATE && 3923 N1.getOperand(0).getOpcode() == ISD::AND && 3924 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3925 SDValue N101 = N1.getOperand(0).getOperand(1); 3926 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3927 EVT TruncVT = N1.getValueType(); 3928 SDValue N100 = N1.getOperand(0).getOperand(0); 3929 APInt TruncC = N101C->getAPIntValue(); 3930 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3931 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, 3932 DAG.getNode(ISD::AND, SDLoc(N), 3933 TruncVT, 3934 DAG.getNode(ISD::TRUNCATE, 3935 SDLoc(N), 3936 TruncVT, N100), 3937 DAG.getConstant(TruncC, TruncVT))); 3938 } 3939 } 3940 3941 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3942 // if c1 is equal to the number of bits the trunc removes 3943 if (N0.getOpcode() == ISD::TRUNCATE && 3944 (N0.getOperand(0).getOpcode() == ISD::SRL || 3945 N0.getOperand(0).getOpcode() == ISD::SRA) && 3946 N0.getOperand(0).hasOneUse() && 3947 N0.getOperand(0).getOperand(1).hasOneUse() && 3948 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3949 EVT LargeVT = N0.getOperand(0).getValueType(); 3950 ConstantSDNode *LargeShiftAmt = 3951 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3952 3953 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3954 LargeShiftAmt->getZExtValue()) { 3955 SDValue Amt = 3956 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3957 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3958 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT, 3959 N0.getOperand(0).getOperand(0), Amt); 3960 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA); 3961 } 3962 } 3963 3964 // Simplify, based on bits shifted out of the LHS. 3965 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3966 return SDValue(N, 0); 3967 3968 3969 // If the sign bit is known to be zero, switch this to a SRL. 3970 if (DAG.SignBitIsZero(N0)) 3971 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1); 3972 3973 if (N1C) { 3974 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3975 if (NewSRA.getNode()) 3976 return NewSRA; 3977 } 3978 3979 return SDValue(); 3980} 3981 3982SDValue DAGCombiner::visitSRL(SDNode *N) { 3983 SDValue N0 = N->getOperand(0); 3984 SDValue N1 = N->getOperand(1); 3985 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3986 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3987 EVT VT = N0.getValueType(); 3988 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3989 3990 // fold (srl c1, c2) -> c1 >>u c2 3991 if (N0C && N1C) 3992 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3993 // fold (srl 0, x) -> 0 3994 if (N0C && N0C->isNullValue()) 3995 return N0; 3996 // fold (srl x, c >= size(x)) -> undef 3997 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3998 return DAG.getUNDEF(VT); 3999 // fold (srl x, 0) -> x 4000 if (N1C && N1C->isNullValue()) 4001 return N0; 4002 // if (srl x, c) is known to be zero, return 0 4003 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 4004 APInt::getAllOnesValue(OpSizeInBits))) 4005 return DAG.getConstant(0, VT); 4006 4007 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 4008 if (N1C && N0.getOpcode() == ISD::SRL && 4009 N0.getOperand(1).getOpcode() == ISD::Constant) { 4010 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 4011 uint64_t c2 = N1C->getZExtValue(); 4012 if (c1 + c2 >= OpSizeInBits) 4013 return DAG.getConstant(0, VT); 4014 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), 4015 DAG.getConstant(c1 + c2, N1.getValueType())); 4016 } 4017 4018 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 4019 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 4020 N0.getOperand(0).getOpcode() == ISD::SRL && 4021 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 4022 uint64_t c1 = 4023 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 4024 uint64_t c2 = N1C->getZExtValue(); 4025 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 4026 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 4027 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 4028 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 4029 if (c1 + OpSizeInBits == InnerShiftSize) { 4030 if (c1 + c2 >= InnerShiftSize) 4031 return DAG.getConstant(0, VT); 4032 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, 4033 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT, 4034 N0.getOperand(0)->getOperand(0), 4035 DAG.getConstant(c1 + c2, ShiftCountVT))); 4036 } 4037 } 4038 4039 // fold (srl (shl x, c), c) -> (and x, cst2) 4040 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 4041 N0.getValueSizeInBits() <= 64) { 4042 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 4043 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0), 4044 DAG.getConstant(~0ULL >> ShAmt, VT)); 4045 } 4046 4047 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask) 4048 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 4049 // Shifting in all undef bits? 4050 EVT SmallVT = N0.getOperand(0).getValueType(); 4051 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 4052 return DAG.getUNDEF(VT); 4053 4054 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 4055 uint64_t ShiftAmt = N1C->getZExtValue(); 4056 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT, 4057 N0.getOperand(0), 4058 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 4059 AddToWorkList(SmallShift.getNode()); 4060 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()).lshr(ShiftAmt); 4061 return DAG.getNode(ISD::AND, SDLoc(N), VT, 4062 DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift), 4063 DAG.getConstant(Mask, VT)); 4064 } 4065 } 4066 4067 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 4068 // bit, which is unmodified by sra. 4069 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 4070 if (N0.getOpcode() == ISD::SRA) 4071 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1); 4072 } 4073 4074 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 4075 if (N1C && N0.getOpcode() == ISD::CTLZ && 4076 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 4077 APInt KnownZero, KnownOne; 4078 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 4079 4080 // If any of the input bits are KnownOne, then the input couldn't be all 4081 // zeros, thus the result of the srl will always be zero. 4082 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 4083 4084 // If all of the bits input the to ctlz node are known to be zero, then 4085 // the result of the ctlz is "32" and the result of the shift is one. 4086 APInt UnknownBits = ~KnownZero; 4087 if (UnknownBits == 0) return DAG.getConstant(1, VT); 4088 4089 // Otherwise, check to see if there is exactly one bit input to the ctlz. 4090 if ((UnknownBits & (UnknownBits - 1)) == 0) { 4091 // Okay, we know that only that the single bit specified by UnknownBits 4092 // could be set on input to the CTLZ node. If this bit is set, the SRL 4093 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 4094 // to an SRL/XOR pair, which is likely to simplify more. 4095 unsigned ShAmt = UnknownBits.countTrailingZeros(); 4096 SDValue Op = N0.getOperand(0); 4097 4098 if (ShAmt) { 4099 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op, 4100 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 4101 AddToWorkList(Op.getNode()); 4102 } 4103 4104 return DAG.getNode(ISD::XOR, SDLoc(N), VT, 4105 Op, DAG.getConstant(1, VT)); 4106 } 4107 } 4108 4109 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 4110 if (N1.getOpcode() == ISD::TRUNCATE && 4111 N1.getOperand(0).getOpcode() == ISD::AND && 4112 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 4113 SDValue N101 = N1.getOperand(0).getOperand(1); 4114 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 4115 EVT TruncVT = N1.getValueType(); 4116 SDValue N100 = N1.getOperand(0).getOperand(0); 4117 APInt TruncC = N101C->getAPIntValue(); 4118 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 4119 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, 4120 DAG.getNode(ISD::AND, SDLoc(N), 4121 TruncVT, 4122 DAG.getNode(ISD::TRUNCATE, 4123 SDLoc(N), 4124 TruncVT, N100), 4125 DAG.getConstant(TruncC, TruncVT))); 4126 } 4127 } 4128 4129 // fold operands of srl based on knowledge that the low bits are not 4130 // demanded. 4131 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 4132 return SDValue(N, 0); 4133 4134 if (N1C) { 4135 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 4136 if (NewSRL.getNode()) 4137 return NewSRL; 4138 } 4139 4140 // Attempt to convert a srl of a load into a narrower zero-extending load. 4141 SDValue NarrowLoad = ReduceLoadWidth(N); 4142 if (NarrowLoad.getNode()) 4143 return NarrowLoad; 4144 4145 // Here is a common situation. We want to optimize: 4146 // 4147 // %a = ... 4148 // %b = and i32 %a, 2 4149 // %c = srl i32 %b, 1 4150 // brcond i32 %c ... 4151 // 4152 // into 4153 // 4154 // %a = ... 4155 // %b = and %a, 2 4156 // %c = setcc eq %b, 0 4157 // brcond %c ... 4158 // 4159 // However when after the source operand of SRL is optimized into AND, the SRL 4160 // itself may not be optimized further. Look for it and add the BRCOND into 4161 // the worklist. 4162 if (N->hasOneUse()) { 4163 SDNode *Use = *N->use_begin(); 4164 if (Use->getOpcode() == ISD::BRCOND) 4165 AddToWorkList(Use); 4166 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 4167 // Also look pass the truncate. 4168 Use = *Use->use_begin(); 4169 if (Use->getOpcode() == ISD::BRCOND) 4170 AddToWorkList(Use); 4171 } 4172 } 4173 4174 return SDValue(); 4175} 4176 4177SDValue DAGCombiner::visitCTLZ(SDNode *N) { 4178 SDValue N0 = N->getOperand(0); 4179 EVT VT = N->getValueType(0); 4180 4181 // fold (ctlz c1) -> c2 4182 if (isa<ConstantSDNode>(N0)) 4183 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0); 4184 return SDValue(); 4185} 4186 4187SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 4188 SDValue N0 = N->getOperand(0); 4189 EVT VT = N->getValueType(0); 4190 4191 // fold (ctlz_zero_undef c1) -> c2 4192 if (isa<ConstantSDNode>(N0)) 4193 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0); 4194 return SDValue(); 4195} 4196 4197SDValue DAGCombiner::visitCTTZ(SDNode *N) { 4198 SDValue N0 = N->getOperand(0); 4199 EVT VT = N->getValueType(0); 4200 4201 // fold (cttz c1) -> c2 4202 if (isa<ConstantSDNode>(N0)) 4203 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0); 4204 return SDValue(); 4205} 4206 4207SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4208 SDValue N0 = N->getOperand(0); 4209 EVT VT = N->getValueType(0); 4210 4211 // fold (cttz_zero_undef c1) -> c2 4212 if (isa<ConstantSDNode>(N0)) 4213 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0); 4214 return SDValue(); 4215} 4216 4217SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4218 SDValue N0 = N->getOperand(0); 4219 EVT VT = N->getValueType(0); 4220 4221 // fold (ctpop c1) -> c2 4222 if (isa<ConstantSDNode>(N0)) 4223 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0); 4224 return SDValue(); 4225} 4226 4227SDValue DAGCombiner::visitSELECT(SDNode *N) { 4228 SDValue N0 = N->getOperand(0); 4229 SDValue N1 = N->getOperand(1); 4230 SDValue N2 = N->getOperand(2); 4231 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4232 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4233 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4234 EVT VT = N->getValueType(0); 4235 EVT VT0 = N0.getValueType(); 4236 4237 // fold (select C, X, X) -> X 4238 if (N1 == N2) 4239 return N1; 4240 // fold (select true, X, Y) -> X 4241 if (N0C && !N0C->isNullValue()) 4242 return N1; 4243 // fold (select false, X, Y) -> Y 4244 if (N0C && N0C->isNullValue()) 4245 return N2; 4246 // fold (select C, 1, X) -> (or C, X) 4247 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4248 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2); 4249 // fold (select C, 0, 1) -> (xor C, 1) 4250 if (VT.isInteger() && 4251 (VT0 == MVT::i1 || 4252 (VT0.isInteger() && 4253 TLI.getBooleanContents(false) == 4254 TargetLowering::ZeroOrOneBooleanContent)) && 4255 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4256 SDValue XORNode; 4257 if (VT == VT0) 4258 return DAG.getNode(ISD::XOR, SDLoc(N), VT0, 4259 N0, DAG.getConstant(1, VT0)); 4260 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0, 4261 N0, DAG.getConstant(1, VT0)); 4262 AddToWorkList(XORNode.getNode()); 4263 if (VT.bitsGT(VT0)) 4264 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode); 4265 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode); 4266 } 4267 // fold (select C, 0, X) -> (and (not C), X) 4268 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4269 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT); 4270 AddToWorkList(NOTNode.getNode()); 4271 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2); 4272 } 4273 // fold (select C, X, 1) -> (or (not C), X) 4274 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4275 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT); 4276 AddToWorkList(NOTNode.getNode()); 4277 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1); 4278 } 4279 // fold (select C, X, 0) -> (and C, X) 4280 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4281 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1); 4282 // fold (select X, X, Y) -> (or X, Y) 4283 // fold (select X, 1, Y) -> (or X, Y) 4284 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4285 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2); 4286 // fold (select X, Y, X) -> (and X, Y) 4287 // fold (select X, Y, 0) -> (and X, Y) 4288 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4289 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1); 4290 4291 // If we can fold this based on the true/false value, do so. 4292 if (SimplifySelectOps(N, N1, N2)) 4293 return SDValue(N, 0); // Don't revisit N. 4294 4295 // fold selects based on a setcc into other things, such as min/max/abs 4296 if (N0.getOpcode() == ISD::SETCC) { 4297 // FIXME: 4298 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4299 // having to say they don't support SELECT_CC on every type the DAG knows 4300 // about, since there is no way to mark an opcode illegal at all value types 4301 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4302 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4303 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, 4304 N0.getOperand(0), N0.getOperand(1), 4305 N1, N2, N0.getOperand(2)); 4306 return SimplifySelect(SDLoc(N), N0, N1, N2); 4307 } 4308 4309 return SDValue(); 4310} 4311 4312SDValue DAGCombiner::visitVSELECT(SDNode *N) { 4313 SDValue N0 = N->getOperand(0); 4314 SDValue N1 = N->getOperand(1); 4315 SDValue N2 = N->getOperand(2); 4316 SDLoc DL(N); 4317 4318 // Canonicalize integer abs. 4319 // vselect (setg[te] X, 0), X, -X -> 4320 // vselect (setgt X, -1), X, -X -> 4321 // vselect (setl[te] X, 0), -X, X -> 4322 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4323 if (N0.getOpcode() == ISD::SETCC) { 4324 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 4325 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 4326 bool isAbs = false; 4327 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode()); 4328 4329 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) || 4330 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) && 4331 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1)) 4332 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode()); 4333 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) && 4334 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1)) 4335 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode()); 4336 4337 if (isAbs) { 4338 EVT VT = LHS.getValueType(); 4339 SDValue Shift = DAG.getNode( 4340 ISD::SRA, DL, VT, LHS, 4341 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, VT)); 4342 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift); 4343 AddToWorkList(Shift.getNode()); 4344 AddToWorkList(Add.getNode()); 4345 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift); 4346 } 4347 } 4348 4349 return SDValue(); 4350} 4351 4352SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4353 SDValue N0 = N->getOperand(0); 4354 SDValue N1 = N->getOperand(1); 4355 SDValue N2 = N->getOperand(2); 4356 SDValue N3 = N->getOperand(3); 4357 SDValue N4 = N->getOperand(4); 4358 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4359 4360 // fold select_cc lhs, rhs, x, x, cc -> x 4361 if (N2 == N3) 4362 return N2; 4363 4364 // Determine if the condition we're dealing with is constant 4365 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()), 4366 N0, N1, CC, SDLoc(N), false); 4367 if (SCC.getNode()) { 4368 AddToWorkList(SCC.getNode()); 4369 4370 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) { 4371 if (!SCCC->isNullValue()) 4372 return N2; // cond always true -> true val 4373 else 4374 return N3; // cond always false -> false val 4375 } 4376 4377 // Fold to a simpler select_cc 4378 if (SCC.getOpcode() == ISD::SETCC) 4379 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(), 4380 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4381 SCC.getOperand(2)); 4382 } 4383 4384 // If we can fold this based on the true/false value, do so. 4385 if (SimplifySelectOps(N, N2, N3)) 4386 return SDValue(N, 0); // Don't revisit N. 4387 4388 // fold select_cc into other things, such as min/max/abs 4389 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC); 4390} 4391 4392SDValue DAGCombiner::visitSETCC(SDNode *N) { 4393 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4394 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4395 SDLoc(N)); 4396} 4397 4398// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4399// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4400// transformation. Returns true if extension are possible and the above 4401// mentioned transformation is profitable. 4402static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4403 unsigned ExtOpc, 4404 SmallVectorImpl<SDNode *> &ExtendNodes, 4405 const TargetLowering &TLI) { 4406 bool HasCopyToRegUses = false; 4407 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4408 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4409 UE = N0.getNode()->use_end(); 4410 UI != UE; ++UI) { 4411 SDNode *User = *UI; 4412 if (User == N) 4413 continue; 4414 if (UI.getUse().getResNo() != N0.getResNo()) 4415 continue; 4416 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4417 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4418 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4419 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4420 // Sign bits will be lost after a zext. 4421 return false; 4422 bool Add = false; 4423 for (unsigned i = 0; i != 2; ++i) { 4424 SDValue UseOp = User->getOperand(i); 4425 if (UseOp == N0) 4426 continue; 4427 if (!isa<ConstantSDNode>(UseOp)) 4428 return false; 4429 Add = true; 4430 } 4431 if (Add) 4432 ExtendNodes.push_back(User); 4433 continue; 4434 } 4435 // If truncates aren't free and there are users we can't 4436 // extend, it isn't worthwhile. 4437 if (!isTruncFree) 4438 return false; 4439 // Remember if this value is live-out. 4440 if (User->getOpcode() == ISD::CopyToReg) 4441 HasCopyToRegUses = true; 4442 } 4443 4444 if (HasCopyToRegUses) { 4445 bool BothLiveOut = false; 4446 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4447 UI != UE; ++UI) { 4448 SDUse &Use = UI.getUse(); 4449 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4450 BothLiveOut = true; 4451 break; 4452 } 4453 } 4454 if (BothLiveOut) 4455 // Both unextended and extended values are live out. There had better be 4456 // a good reason for the transformation. 4457 return ExtendNodes.size(); 4458 } 4459 return true; 4460} 4461 4462void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs, 4463 SDValue Trunc, SDValue ExtLoad, SDLoc DL, 4464 ISD::NodeType ExtType) { 4465 // Extend SetCC uses if necessary. 4466 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4467 SDNode *SetCC = SetCCs[i]; 4468 SmallVector<SDValue, 4> Ops; 4469 4470 for (unsigned j = 0; j != 2; ++j) { 4471 SDValue SOp = SetCC->getOperand(j); 4472 if (SOp == Trunc) 4473 Ops.push_back(ExtLoad); 4474 else 4475 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4476 } 4477 4478 Ops.push_back(SetCC->getOperand(2)); 4479 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4480 &Ops[0], Ops.size())); 4481 } 4482} 4483 4484SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4485 SDValue N0 = N->getOperand(0); 4486 EVT VT = N->getValueType(0); 4487 4488 // fold (sext c1) -> c1 4489 if (isa<ConstantSDNode>(N0)) 4490 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N0); 4491 4492 // fold (sext (sext x)) -> (sext x) 4493 // fold (sext (aext x)) -> (sext x) 4494 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4495 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, 4496 N0.getOperand(0)); 4497 4498 if (N0.getOpcode() == ISD::TRUNCATE) { 4499 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4500 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4501 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4502 if (NarrowLoad.getNode()) { 4503 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4504 if (NarrowLoad.getNode() != N0.getNode()) { 4505 CombineTo(N0.getNode(), NarrowLoad); 4506 // CombineTo deleted the truncate, if needed, but not what's under it. 4507 AddToWorkList(oye); 4508 } 4509 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4510 } 4511 4512 // See if the value being truncated is already sign extended. If so, just 4513 // eliminate the trunc/sext pair. 4514 SDValue Op = N0.getOperand(0); 4515 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4516 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4517 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4518 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4519 4520 if (OpBits == DestBits) { 4521 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4522 // bits, it is already ready. 4523 if (NumSignBits > DestBits-MidBits) 4524 return Op; 4525 } else if (OpBits < DestBits) { 4526 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4527 // bits, just sext from i32. 4528 if (NumSignBits > OpBits-MidBits) 4529 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op); 4530 } else { 4531 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4532 // bits, just truncate to i32. 4533 if (NumSignBits > OpBits-MidBits) 4534 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op); 4535 } 4536 4537 // fold (sext (truncate x)) -> (sextinreg x). 4538 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4539 N0.getValueType())) { 4540 if (OpBits < DestBits) 4541 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op); 4542 else if (OpBits > DestBits) 4543 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op); 4544 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op, 4545 DAG.getValueType(N0.getValueType())); 4546 } 4547 } 4548 4549 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4550 // None of the supported targets knows how to perform load and sign extend 4551 // on vectors in one instruction. We only perform this transformation on 4552 // scalars. 4553 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4554 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4555 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4556 bool DoXform = true; 4557 SmallVector<SDNode*, 4> SetCCs; 4558 if (!N0.hasOneUse()) 4559 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4560 if (DoXform) { 4561 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4562 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, 4563 LN0->getChain(), 4564 LN0->getBasePtr(), N0.getValueType(), 4565 LN0->getMemOperand()); 4566 CombineTo(N, ExtLoad); 4567 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), 4568 N0.getValueType(), ExtLoad); 4569 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4570 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), 4571 ISD::SIGN_EXTEND); 4572 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4573 } 4574 } 4575 4576 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4577 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4578 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4579 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4580 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4581 EVT MemVT = LN0->getMemoryVT(); 4582 if ((!LegalOperations && !LN0->isVolatile()) || 4583 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4584 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, 4585 LN0->getChain(), 4586 LN0->getBasePtr(), MemVT, 4587 LN0->getMemOperand()); 4588 CombineTo(N, ExtLoad); 4589 CombineTo(N0.getNode(), 4590 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), 4591 N0.getValueType(), ExtLoad), 4592 ExtLoad.getValue(1)); 4593 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4594 } 4595 } 4596 4597 // fold (sext (and/or/xor (load x), cst)) -> 4598 // (and/or/xor (sextload x), (sext cst)) 4599 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4600 N0.getOpcode() == ISD::XOR) && 4601 isa<LoadSDNode>(N0.getOperand(0)) && 4602 N0.getOperand(1).getOpcode() == ISD::Constant && 4603 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4604 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4605 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4606 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4607 bool DoXform = true; 4608 SmallVector<SDNode*, 4> SetCCs; 4609 if (!N0.hasOneUse()) 4610 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4611 SetCCs, TLI); 4612 if (DoXform) { 4613 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT, 4614 LN0->getChain(), LN0->getBasePtr(), 4615 LN0->getMemoryVT(), 4616 LN0->getMemOperand()); 4617 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4618 Mask = Mask.sext(VT.getSizeInBits()); 4619 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT, 4620 ExtLoad, DAG.getConstant(Mask, VT)); 4621 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4622 SDLoc(N0.getOperand(0)), 4623 N0.getOperand(0).getValueType(), ExtLoad); 4624 CombineTo(N, And); 4625 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4626 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), 4627 ISD::SIGN_EXTEND); 4628 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4629 } 4630 } 4631 } 4632 4633 if (N0.getOpcode() == ISD::SETCC) { 4634 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4635 // Only do this before legalize for now. 4636 if (VT.isVector() && !LegalOperations && 4637 TLI.getBooleanContents(true) == 4638 TargetLowering::ZeroOrNegativeOneBooleanContent) { 4639 EVT N0VT = N0.getOperand(0).getValueType(); 4640 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4641 // of the same size as the compared operands. Only optimize sext(setcc()) 4642 // if this is the case. 4643 EVT SVT = getSetCCResultType(N0VT); 4644 4645 // We know that the # elements of the results is the same as the 4646 // # elements of the compare (and the # elements of the compare result 4647 // for that matter). Check to see that they are the same size. If so, 4648 // we know that the element size of the sext'd result matches the 4649 // element size of the compare operands. 4650 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4651 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0), 4652 N0.getOperand(1), 4653 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4654 4655 // If the desired elements are smaller or larger than the source 4656 // elements we can use a matching integer vector type and then 4657 // truncate/sign extend 4658 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger(); 4659 if (SVT == MatchingVectorType) { 4660 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType, 4661 N0.getOperand(0), N0.getOperand(1), 4662 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4663 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT); 4664 } 4665 } 4666 4667 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4668 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4669 SDValue NegOne = 4670 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4671 SDValue SCC = 4672 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1), 4673 NegOne, DAG.getConstant(0, VT), 4674 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4675 if (SCC.getNode()) return SCC; 4676 if (!VT.isVector() && 4677 (!LegalOperations || 4678 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(VT)))) { 4679 return DAG.getSelect(SDLoc(N), VT, 4680 DAG.getSetCC(SDLoc(N), 4681 getSetCCResultType(VT), 4682 N0.getOperand(0), N0.getOperand(1), 4683 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4684 NegOne, DAG.getConstant(0, VT)); 4685 } 4686 } 4687 4688 // fold (sext x) -> (zext x) if the sign bit is known zero. 4689 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4690 DAG.SignBitIsZero(N0)) 4691 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0); 4692 4693 return SDValue(); 4694} 4695 4696// isTruncateOf - If N is a truncate of some other value, return true, record 4697// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4698// This function computes KnownZero to avoid a duplicated call to 4699// ComputeMaskedBits in the caller. 4700static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4701 APInt &KnownZero) { 4702 APInt KnownOne; 4703 if (N->getOpcode() == ISD::TRUNCATE) { 4704 Op = N->getOperand(0); 4705 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4706 return true; 4707 } 4708 4709 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4710 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4711 return false; 4712 4713 SDValue Op0 = N->getOperand(0); 4714 SDValue Op1 = N->getOperand(1); 4715 assert(Op0.getValueType() == Op1.getValueType()); 4716 4717 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4718 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4719 if (COp0 && COp0->isNullValue()) 4720 Op = Op1; 4721 else if (COp1 && COp1->isNullValue()) 4722 Op = Op0; 4723 else 4724 return false; 4725 4726 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4727 4728 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4729 return false; 4730 4731 return true; 4732} 4733 4734SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4735 SDValue N0 = N->getOperand(0); 4736 EVT VT = N->getValueType(0); 4737 4738 // fold (zext c1) -> c1 4739 if (isa<ConstantSDNode>(N0)) 4740 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0); 4741 // fold (zext (zext x)) -> (zext x) 4742 // fold (zext (aext x)) -> (zext x) 4743 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4744 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, 4745 N0.getOperand(0)); 4746 4747 // fold (zext (truncate x)) -> (zext x) or 4748 // (zext (truncate x)) -> (truncate x) 4749 // This is valid when the truncated bits of x are already zero. 4750 // FIXME: We should extend this to work for vectors too. 4751 SDValue Op; 4752 APInt KnownZero; 4753 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4754 APInt TruncatedBits = 4755 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4756 APInt(Op.getValueSizeInBits(), 0) : 4757 APInt::getBitsSet(Op.getValueSizeInBits(), 4758 N0.getValueSizeInBits(), 4759 std::min(Op.getValueSizeInBits(), 4760 VT.getSizeInBits())); 4761 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4762 if (VT.bitsGT(Op.getValueType())) 4763 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op); 4764 if (VT.bitsLT(Op.getValueType())) 4765 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op); 4766 4767 return Op; 4768 } 4769 } 4770 4771 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4772 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4773 if (N0.getOpcode() == ISD::TRUNCATE) { 4774 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4775 if (NarrowLoad.getNode()) { 4776 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4777 if (NarrowLoad.getNode() != N0.getNode()) { 4778 CombineTo(N0.getNode(), NarrowLoad); 4779 // CombineTo deleted the truncate, if needed, but not what's under it. 4780 AddToWorkList(oye); 4781 } 4782 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4783 } 4784 } 4785 4786 // fold (zext (truncate x)) -> (and x, mask) 4787 if (N0.getOpcode() == ISD::TRUNCATE && 4788 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4789 4790 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4791 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4792 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4793 if (NarrowLoad.getNode()) { 4794 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4795 if (NarrowLoad.getNode() != N0.getNode()) { 4796 CombineTo(N0.getNode(), NarrowLoad); 4797 // CombineTo deleted the truncate, if needed, but not what's under it. 4798 AddToWorkList(oye); 4799 } 4800 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4801 } 4802 4803 SDValue Op = N0.getOperand(0); 4804 if (Op.getValueType().bitsLT(VT)) { 4805 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op); 4806 AddToWorkList(Op.getNode()); 4807 } else if (Op.getValueType().bitsGT(VT)) { 4808 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op); 4809 AddToWorkList(Op.getNode()); 4810 } 4811 return DAG.getZeroExtendInReg(Op, SDLoc(N), 4812 N0.getValueType().getScalarType()); 4813 } 4814 4815 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4816 // if either of the casts is not free. 4817 if (N0.getOpcode() == ISD::AND && 4818 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4819 N0.getOperand(1).getOpcode() == ISD::Constant && 4820 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4821 N0.getValueType()) || 4822 !TLI.isZExtFree(N0.getValueType(), VT))) { 4823 SDValue X = N0.getOperand(0).getOperand(0); 4824 if (X.getValueType().bitsLT(VT)) { 4825 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X); 4826 } else if (X.getValueType().bitsGT(VT)) { 4827 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X); 4828 } 4829 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4830 Mask = Mask.zext(VT.getSizeInBits()); 4831 return DAG.getNode(ISD::AND, SDLoc(N), VT, 4832 X, DAG.getConstant(Mask, VT)); 4833 } 4834 4835 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4836 // None of the supported targets knows how to perform load and vector_zext 4837 // on vectors in one instruction. We only perform this transformation on 4838 // scalars. 4839 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4840 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4841 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4842 bool DoXform = true; 4843 SmallVector<SDNode*, 4> SetCCs; 4844 if (!N0.hasOneUse()) 4845 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4846 if (DoXform) { 4847 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4848 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT, 4849 LN0->getChain(), 4850 LN0->getBasePtr(), N0.getValueType(), 4851 LN0->getMemOperand()); 4852 CombineTo(N, ExtLoad); 4853 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), 4854 N0.getValueType(), ExtLoad); 4855 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4856 4857 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), 4858 ISD::ZERO_EXTEND); 4859 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4860 } 4861 } 4862 4863 // fold (zext (and/or/xor (load x), cst)) -> 4864 // (and/or/xor (zextload x), (zext cst)) 4865 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4866 N0.getOpcode() == ISD::XOR) && 4867 isa<LoadSDNode>(N0.getOperand(0)) && 4868 N0.getOperand(1).getOpcode() == ISD::Constant && 4869 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4870 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4871 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4872 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4873 bool DoXform = true; 4874 SmallVector<SDNode*, 4> SetCCs; 4875 if (!N0.hasOneUse()) 4876 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4877 SetCCs, TLI); 4878 if (DoXform) { 4879 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT, 4880 LN0->getChain(), LN0->getBasePtr(), 4881 LN0->getMemoryVT(), 4882 LN0->getMemOperand()); 4883 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4884 Mask = Mask.zext(VT.getSizeInBits()); 4885 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT, 4886 ExtLoad, DAG.getConstant(Mask, VT)); 4887 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4888 SDLoc(N0.getOperand(0)), 4889 N0.getOperand(0).getValueType(), ExtLoad); 4890 CombineTo(N, And); 4891 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4892 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), 4893 ISD::ZERO_EXTEND); 4894 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4895 } 4896 } 4897 } 4898 4899 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4900 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4901 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4902 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4903 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4904 EVT MemVT = LN0->getMemoryVT(); 4905 if ((!LegalOperations && !LN0->isVolatile()) || 4906 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4907 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT, 4908 LN0->getChain(), 4909 LN0->getBasePtr(), MemVT, 4910 LN0->getMemOperand()); 4911 CombineTo(N, ExtLoad); 4912 CombineTo(N0.getNode(), 4913 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), 4914 ExtLoad), 4915 ExtLoad.getValue(1)); 4916 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4917 } 4918 } 4919 4920 if (N0.getOpcode() == ISD::SETCC) { 4921 if (!LegalOperations && VT.isVector()) { 4922 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4923 // Only do this before legalize for now. 4924 EVT N0VT = N0.getOperand(0).getValueType(); 4925 EVT EltVT = VT.getVectorElementType(); 4926 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4927 DAG.getConstant(1, EltVT)); 4928 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4929 // We know that the # elements of the results is the same as the 4930 // # elements of the compare (and the # elements of the compare result 4931 // for that matter). Check to see that they are the same size. If so, 4932 // we know that the element size of the sext'd result matches the 4933 // element size of the compare operands. 4934 return DAG.getNode(ISD::AND, SDLoc(N), VT, 4935 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0), 4936 N0.getOperand(1), 4937 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4938 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, 4939 &OneOps[0], OneOps.size())); 4940 4941 // If the desired elements are smaller or larger than the source 4942 // elements we can use a matching integer vector type and then 4943 // truncate/sign extend 4944 EVT MatchingElementType = 4945 EVT::getIntegerVT(*DAG.getContext(), 4946 N0VT.getScalarType().getSizeInBits()); 4947 EVT MatchingVectorType = 4948 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4949 N0VT.getVectorNumElements()); 4950 SDValue VsetCC = 4951 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0), 4952 N0.getOperand(1), 4953 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4954 return DAG.getNode(ISD::AND, SDLoc(N), VT, 4955 DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT), 4956 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, 4957 &OneOps[0], OneOps.size())); 4958 } 4959 4960 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4961 SDValue SCC = 4962 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1), 4963 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4964 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4965 if (SCC.getNode()) return SCC; 4966 } 4967 4968 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4969 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4970 isa<ConstantSDNode>(N0.getOperand(1)) && 4971 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4972 N0.hasOneUse()) { 4973 SDValue ShAmt = N0.getOperand(1); 4974 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4975 if (N0.getOpcode() == ISD::SHL) { 4976 SDValue InnerZExt = N0.getOperand(0); 4977 // If the original shl may be shifting out bits, do not perform this 4978 // transformation. 4979 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4980 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4981 if (ShAmtVal > KnownZeroBits) 4982 return SDValue(); 4983 } 4984 4985 SDLoc DL(N); 4986 4987 // Ensure that the shift amount is wide enough for the shifted value. 4988 if (VT.getSizeInBits() >= 256) 4989 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4990 4991 return DAG.getNode(N0.getOpcode(), DL, VT, 4992 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4993 ShAmt); 4994 } 4995 4996 return SDValue(); 4997} 4998 4999SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 5000 SDValue N0 = N->getOperand(0); 5001 EVT VT = N->getValueType(0); 5002 5003 // fold (aext c1) -> c1 5004 if (isa<ConstantSDNode>(N0)) 5005 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, N0); 5006 // fold (aext (aext x)) -> (aext x) 5007 // fold (aext (zext x)) -> (zext x) 5008 // fold (aext (sext x)) -> (sext x) 5009 if (N0.getOpcode() == ISD::ANY_EXTEND || 5010 N0.getOpcode() == ISD::ZERO_EXTEND || 5011 N0.getOpcode() == ISD::SIGN_EXTEND) 5012 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); 5013 5014 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 5015 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 5016 if (N0.getOpcode() == ISD::TRUNCATE) { 5017 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 5018 if (NarrowLoad.getNode()) { 5019 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 5020 if (NarrowLoad.getNode() != N0.getNode()) { 5021 CombineTo(N0.getNode(), NarrowLoad); 5022 // CombineTo deleted the truncate, if needed, but not what's under it. 5023 AddToWorkList(oye); 5024 } 5025 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5026 } 5027 } 5028 5029 // fold (aext (truncate x)) 5030 if (N0.getOpcode() == ISD::TRUNCATE) { 5031 SDValue TruncOp = N0.getOperand(0); 5032 if (TruncOp.getValueType() == VT) 5033 return TruncOp; // x iff x size == zext size. 5034 if (TruncOp.getValueType().bitsGT(VT)) 5035 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp); 5036 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp); 5037 } 5038 5039 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 5040 // if the trunc is not free. 5041 if (N0.getOpcode() == ISD::AND && 5042 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 5043 N0.getOperand(1).getOpcode() == ISD::Constant && 5044 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 5045 N0.getValueType())) { 5046 SDValue X = N0.getOperand(0).getOperand(0); 5047 if (X.getValueType().bitsLT(VT)) { 5048 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X); 5049 } else if (X.getValueType().bitsGT(VT)) { 5050 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X); 5051 } 5052 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 5053 Mask = Mask.zext(VT.getSizeInBits()); 5054 return DAG.getNode(ISD::AND, SDLoc(N), VT, 5055 X, DAG.getConstant(Mask, VT)); 5056 } 5057 5058 // fold (aext (load x)) -> (aext (truncate (extload x))) 5059 // None of the supported targets knows how to perform load and any_ext 5060 // on vectors in one instruction. We only perform this transformation on 5061 // scalars. 5062 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 5063 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5064 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5065 bool DoXform = true; 5066 SmallVector<SDNode*, 4> SetCCs; 5067 if (!N0.hasOneUse()) 5068 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 5069 if (DoXform) { 5070 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5071 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, 5072 LN0->getChain(), 5073 LN0->getBasePtr(), N0.getValueType(), 5074 LN0->getMemOperand()); 5075 CombineTo(N, ExtLoad); 5076 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), 5077 N0.getValueType(), ExtLoad); 5078 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 5079 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), 5080 ISD::ANY_EXTEND); 5081 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5082 } 5083 } 5084 5085 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 5086 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 5087 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 5088 if (N0.getOpcode() == ISD::LOAD && 5089 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5090 N0.hasOneUse()) { 5091 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5092 EVT MemVT = LN0->getMemoryVT(); 5093 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(N), 5094 VT, LN0->getChain(), LN0->getBasePtr(), 5095 MemVT, LN0->getMemOperand()); 5096 CombineTo(N, ExtLoad); 5097 CombineTo(N0.getNode(), 5098 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), 5099 N0.getValueType(), ExtLoad), 5100 ExtLoad.getValue(1)); 5101 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5102 } 5103 5104 if (N0.getOpcode() == ISD::SETCC) { 5105 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 5106 // Only do this before legalize for now. 5107 if (VT.isVector() && !LegalOperations) { 5108 EVT N0VT = N0.getOperand(0).getValueType(); 5109 // We know that the # elements of the results is the same as the 5110 // # elements of the compare (and the # elements of the compare result 5111 // for that matter). Check to see that they are the same size. If so, 5112 // we know that the element size of the sext'd result matches the 5113 // element size of the compare operands. 5114 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 5115 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0), 5116 N0.getOperand(1), 5117 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5118 // If the desired elements are smaller or larger than the source 5119 // elements we can use a matching integer vector type and then 5120 // truncate/sign extend 5121 else { 5122 EVT MatchingElementType = 5123 EVT::getIntegerVT(*DAG.getContext(), 5124 N0VT.getScalarType().getSizeInBits()); 5125 EVT MatchingVectorType = 5126 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 5127 N0VT.getVectorNumElements()); 5128 SDValue VsetCC = 5129 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0), 5130 N0.getOperand(1), 5131 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5132 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT); 5133 } 5134 } 5135 5136 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 5137 SDValue SCC = 5138 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1), 5139 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 5140 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 5141 if (SCC.getNode()) 5142 return SCC; 5143 } 5144 5145 return SDValue(); 5146} 5147 5148/// GetDemandedBits - See if the specified operand can be simplified with the 5149/// knowledge that only the bits specified by Mask are used. If so, return the 5150/// simpler operand, otherwise return a null SDValue. 5151SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 5152 switch (V.getOpcode()) { 5153 default: break; 5154 case ISD::Constant: { 5155 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 5156 assert(CV != 0 && "Const value should be ConstSDNode."); 5157 const APInt &CVal = CV->getAPIntValue(); 5158 APInt NewVal = CVal & Mask; 5159 if (NewVal != CVal) 5160 return DAG.getConstant(NewVal, V.getValueType()); 5161 break; 5162 } 5163 case ISD::OR: 5164 case ISD::XOR: 5165 // If the LHS or RHS don't contribute bits to the or, drop them. 5166 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 5167 return V.getOperand(1); 5168 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 5169 return V.getOperand(0); 5170 break; 5171 case ISD::SRL: 5172 // Only look at single-use SRLs. 5173 if (!V.getNode()->hasOneUse()) 5174 break; 5175 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 5176 // See if we can recursively simplify the LHS. 5177 unsigned Amt = RHSC->getZExtValue(); 5178 5179 // Watch out for shift count overflow though. 5180 if (Amt >= Mask.getBitWidth()) break; 5181 APInt NewMask = Mask << Amt; 5182 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 5183 if (SimplifyLHS.getNode()) 5184 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(), 5185 SimplifyLHS, V.getOperand(1)); 5186 } 5187 } 5188 return SDValue(); 5189} 5190 5191/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 5192/// bits and then truncated to a narrower type and where N is a multiple 5193/// of number of bits of the narrower type, transform it to a narrower load 5194/// from address + N / num of bits of new type. If the result is to be 5195/// extended, also fold the extension to form a extending load. 5196SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 5197 unsigned Opc = N->getOpcode(); 5198 5199 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 5200 SDValue N0 = N->getOperand(0); 5201 EVT VT = N->getValueType(0); 5202 EVT ExtVT = VT; 5203 5204 // This transformation isn't valid for vector loads. 5205 if (VT.isVector()) 5206 return SDValue(); 5207 5208 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 5209 // extended to VT. 5210 if (Opc == ISD::SIGN_EXTEND_INREG) { 5211 ExtType = ISD::SEXTLOAD; 5212 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5213 } else if (Opc == ISD::SRL) { 5214 // Another special-case: SRL is basically zero-extending a narrower value. 5215 ExtType = ISD::ZEXTLOAD; 5216 N0 = SDValue(N, 0); 5217 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 5218 if (!N01) return SDValue(); 5219 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 5220 VT.getSizeInBits() - N01->getZExtValue()); 5221 } 5222 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5223 return SDValue(); 5224 5225 unsigned EVTBits = ExtVT.getSizeInBits(); 5226 5227 // Do not generate loads of non-round integer types since these can 5228 // be expensive (and would be wrong if the type is not byte sized). 5229 if (!ExtVT.isRound()) 5230 return SDValue(); 5231 5232 unsigned ShAmt = 0; 5233 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5234 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5235 ShAmt = N01->getZExtValue(); 5236 // Is the shift amount a multiple of size of VT? 5237 if ((ShAmt & (EVTBits-1)) == 0) { 5238 N0 = N0.getOperand(0); 5239 // Is the load width a multiple of size of VT? 5240 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5241 return SDValue(); 5242 } 5243 5244 // At this point, we must have a load or else we can't do the transform. 5245 if (!isa<LoadSDNode>(N0)) return SDValue(); 5246 5247 // Because a SRL must be assumed to *need* to zero-extend the high bits 5248 // (as opposed to anyext the high bits), we can't combine the zextload 5249 // lowering of SRL and an sextload. 5250 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD) 5251 return SDValue(); 5252 5253 // If the shift amount is larger than the input type then we're not 5254 // accessing any of the loaded bytes. If the load was a zextload/extload 5255 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5256 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5257 return SDValue(); 5258 } 5259 } 5260 5261 // If the load is shifted left (and the result isn't shifted back right), 5262 // we can fold the truncate through the shift. 5263 unsigned ShLeftAmt = 0; 5264 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5265 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5266 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5267 ShLeftAmt = N01->getZExtValue(); 5268 N0 = N0.getOperand(0); 5269 } 5270 } 5271 5272 // If we haven't found a load, we can't narrow it. Don't transform one with 5273 // multiple uses, this would require adding a new load. 5274 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse()) 5275 return SDValue(); 5276 5277 // Don't change the width of a volatile load. 5278 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5279 if (LN0->isVolatile()) 5280 return SDValue(); 5281 5282 // Verify that we are actually reducing a load width here. 5283 if (LN0->getMemoryVT().getSizeInBits() < EVTBits) 5284 return SDValue(); 5285 5286 // For the transform to be legal, the load must produce only two values 5287 // (the value loaded and the chain). Don't transform a pre-increment 5288 // load, for example, which produces an extra value. Otherwise the 5289 // transformation is not equivalent, and the downstream logic to replace 5290 // uses gets things wrong. 5291 if (LN0->getNumValues() > 2) 5292 return SDValue(); 5293 5294 // If the load that we're shrinking is an extload and we're not just 5295 // discarding the extension we can't simply shrink the load. Bail. 5296 // TODO: It would be possible to merge the extensions in some cases. 5297 if (LN0->getExtensionType() != ISD::NON_EXTLOAD && 5298 LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt) 5299 return SDValue(); 5300 5301 EVT PtrType = N0.getOperand(1).getValueType(); 5302 5303 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5304 // It's not possible to generate a constant of extended or untyped type. 5305 return SDValue(); 5306 5307 // For big endian targets, we need to adjust the offset to the pointer to 5308 // load the correct bytes. 5309 if (TLI.isBigEndian()) { 5310 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5311 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5312 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5313 } 5314 5315 uint64_t PtrOff = ShAmt / 8; 5316 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5317 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), 5318 PtrType, LN0->getBasePtr(), 5319 DAG.getConstant(PtrOff, PtrType)); 5320 AddToWorkList(NewPtr.getNode()); 5321 5322 SDValue Load; 5323 if (ExtType == ISD::NON_EXTLOAD) 5324 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr, 5325 LN0->getPointerInfo().getWithOffset(PtrOff), 5326 LN0->isVolatile(), LN0->isNonTemporal(), 5327 LN0->isInvariant(), NewAlign, LN0->getTBAAInfo()); 5328 else 5329 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr, 5330 LN0->getPointerInfo().getWithOffset(PtrOff), 5331 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5332 NewAlign, LN0->getTBAAInfo()); 5333 5334 // Replace the old load's chain with the new load's chain. 5335 WorkListRemover DeadNodes(*this); 5336 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5337 5338 // Shift the result left, if we've swallowed a left shift. 5339 SDValue Result = Load; 5340 if (ShLeftAmt != 0) { 5341 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5342 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5343 ShImmTy = VT; 5344 // If the shift amount is as large as the result size (but, presumably, 5345 // no larger than the source) then the useful bits of the result are 5346 // zero; we can't simply return the shortened shift, because the result 5347 // of that operation is undefined. 5348 if (ShLeftAmt >= VT.getSizeInBits()) 5349 Result = DAG.getConstant(0, VT); 5350 else 5351 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT, 5352 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5353 } 5354 5355 // Return the new loaded value. 5356 return Result; 5357} 5358 5359SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5360 SDValue N0 = N->getOperand(0); 5361 SDValue N1 = N->getOperand(1); 5362 EVT VT = N->getValueType(0); 5363 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5364 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5365 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5366 5367 // fold (sext_in_reg c1) -> c1 5368 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5369 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1); 5370 5371 // If the input is already sign extended, just drop the extension. 5372 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5373 return N0; 5374 5375 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5376 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5377 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) 5378 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, 5379 N0.getOperand(0), N1); 5380 5381 // fold (sext_in_reg (sext x)) -> (sext x) 5382 // fold (sext_in_reg (aext x)) -> (sext x) 5383 // if x is small enough. 5384 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5385 SDValue N00 = N0.getOperand(0); 5386 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5387 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5388 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1); 5389 } 5390 5391 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5392 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5393 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT); 5394 5395 // fold operands of sext_in_reg based on knowledge that the top bits are not 5396 // demanded. 5397 if (SimplifyDemandedBits(SDValue(N, 0))) 5398 return SDValue(N, 0); 5399 5400 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5401 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5402 SDValue NarrowLoad = ReduceLoadWidth(N); 5403 if (NarrowLoad.getNode()) 5404 return NarrowLoad; 5405 5406 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5407 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5408 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5409 if (N0.getOpcode() == ISD::SRL) { 5410 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5411 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5412 // We can turn this into an SRA iff the input to the SRL is already sign 5413 // extended enough. 5414 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5415 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5416 return DAG.getNode(ISD::SRA, SDLoc(N), VT, 5417 N0.getOperand(0), N0.getOperand(1)); 5418 } 5419 } 5420 5421 // fold (sext_inreg (extload x)) -> (sextload x) 5422 if (ISD::isEXTLoad(N0.getNode()) && 5423 ISD::isUNINDEXEDLoad(N0.getNode()) && 5424 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5425 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5426 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5427 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5428 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, 5429 LN0->getChain(), 5430 LN0->getBasePtr(), EVT, 5431 LN0->getMemOperand()); 5432 CombineTo(N, ExtLoad); 5433 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5434 AddToWorkList(ExtLoad.getNode()); 5435 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5436 } 5437 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5438 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5439 N0.hasOneUse() && 5440 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5441 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5442 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5443 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5444 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, 5445 LN0->getChain(), 5446 LN0->getBasePtr(), EVT, 5447 LN0->getMemOperand()); 5448 CombineTo(N, ExtLoad); 5449 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5450 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5451 } 5452 5453 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5454 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5455 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5456 N0.getOperand(1), false); 5457 if (BSwap.getNode() != 0) 5458 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, 5459 BSwap, N1); 5460 } 5461 5462 return SDValue(); 5463} 5464 5465SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5466 SDValue N0 = N->getOperand(0); 5467 EVT VT = N->getValueType(0); 5468 bool isLE = TLI.isLittleEndian(); 5469 5470 // noop truncate 5471 if (N0.getValueType() == N->getValueType(0)) 5472 return N0; 5473 // fold (truncate c1) -> c1 5474 if (isa<ConstantSDNode>(N0)) 5475 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0); 5476 // fold (truncate (truncate x)) -> (truncate x) 5477 if (N0.getOpcode() == ISD::TRUNCATE) 5478 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0)); 5479 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5480 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5481 N0.getOpcode() == ISD::SIGN_EXTEND || 5482 N0.getOpcode() == ISD::ANY_EXTEND) { 5483 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5484 // if the source is smaller than the dest, we still need an extend 5485 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, 5486 N0.getOperand(0)); 5487 if (N0.getOperand(0).getValueType().bitsGT(VT)) 5488 // if the source is larger than the dest, than we just need the truncate 5489 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0)); 5490 // if the source and dest are the same type, we can drop both the extend 5491 // and the truncate. 5492 return N0.getOperand(0); 5493 } 5494 5495 // Fold extract-and-trunc into a narrow extract. For example: 5496 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5497 // i32 y = TRUNCATE(i64 x) 5498 // -- becomes -- 5499 // v16i8 b = BITCAST (v2i64 val) 5500 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5501 // 5502 // Note: We only run this optimization after type legalization (which often 5503 // creates this pattern) and before operation legalization after which 5504 // we need to be more careful about the vector instructions that we generate. 5505 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5506 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5507 5508 EVT VecTy = N0.getOperand(0).getValueType(); 5509 EVT ExTy = N0.getValueType(); 5510 EVT TrTy = N->getValueType(0); 5511 5512 unsigned NumElem = VecTy.getVectorNumElements(); 5513 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5514 5515 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5516 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5517 5518 SDValue EltNo = N0->getOperand(1); 5519 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5520 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5521 EVT IndexTy = TLI.getVectorIdxTy(); 5522 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5523 5524 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N), 5525 NVT, N0.getOperand(0)); 5526 5527 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5528 SDLoc(N), TrTy, V, 5529 DAG.getConstant(Index, IndexTy)); 5530 } 5531 } 5532 5533 // Fold a series of buildvector, bitcast, and truncate if possible. 5534 // For example fold 5535 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to 5536 // (2xi32 (buildvector x, y)). 5537 if (Level == AfterLegalizeVectorOps && VT.isVector() && 5538 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && 5539 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && 5540 N0.getOperand(0).hasOneUse()) { 5541 5542 SDValue BuildVect = N0.getOperand(0); 5543 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType(); 5544 EVT TruncVecEltTy = VT.getVectorElementType(); 5545 5546 // Check that the element types match. 5547 if (BuildVectEltTy == TruncVecEltTy) { 5548 // Now we only need to compute the offset of the truncated elements. 5549 unsigned BuildVecNumElts = BuildVect.getNumOperands(); 5550 unsigned TruncVecNumElts = VT.getVectorNumElements(); 5551 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts; 5552 5553 assert((BuildVecNumElts % TruncVecNumElts) == 0 && 5554 "Invalid number of elements"); 5555 5556 SmallVector<SDValue, 8> Opnds; 5557 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset) 5558 Opnds.push_back(BuildVect.getOperand(i)); 5559 5560 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, &Opnds[0], 5561 Opnds.size()); 5562 } 5563 } 5564 5565 // See if we can simplify the input to this truncate through knowledge that 5566 // only the low bits are being used. 5567 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5568 // Currently we only perform this optimization on scalars because vectors 5569 // may have different active low bits. 5570 if (!VT.isVector()) { 5571 SDValue Shorter = 5572 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5573 VT.getSizeInBits())); 5574 if (Shorter.getNode()) 5575 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter); 5576 } 5577 // fold (truncate (load x)) -> (smaller load x) 5578 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5579 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5580 SDValue Reduced = ReduceLoadWidth(N); 5581 if (Reduced.getNode()) 5582 return Reduced; 5583 } 5584 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)), 5585 // where ... are all 'undef'. 5586 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { 5587 SmallVector<EVT, 8> VTs; 5588 SDValue V; 5589 unsigned Idx = 0; 5590 unsigned NumDefs = 0; 5591 5592 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 5593 SDValue X = N0.getOperand(i); 5594 if (X.getOpcode() != ISD::UNDEF) { 5595 V = X; 5596 Idx = i; 5597 NumDefs++; 5598 } 5599 // Stop if more than one members are non-undef. 5600 if (NumDefs > 1) 5601 break; 5602 VTs.push_back(EVT::getVectorVT(*DAG.getContext(), 5603 VT.getVectorElementType(), 5604 X.getValueType().getVectorNumElements())); 5605 } 5606 5607 if (NumDefs == 0) 5608 return DAG.getUNDEF(VT); 5609 5610 if (NumDefs == 1) { 5611 assert(V.getNode() && "The single defined operand is empty!"); 5612 SmallVector<SDValue, 8> Opnds; 5613 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 5614 if (i != Idx) { 5615 Opnds.push_back(DAG.getUNDEF(VTs[i])); 5616 continue; 5617 } 5618 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V); 5619 AddToWorkList(NV.getNode()); 5620 Opnds.push_back(NV); 5621 } 5622 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, 5623 &Opnds[0], Opnds.size()); 5624 } 5625 } 5626 5627 // Simplify the operands using demanded-bits information. 5628 if (!VT.isVector() && 5629 SimplifyDemandedBits(SDValue(N, 0))) 5630 return SDValue(N, 0); 5631 5632 return SDValue(); 5633} 5634 5635static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5636 SDValue Elt = N->getOperand(i); 5637 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5638 return Elt.getNode(); 5639 return Elt.getOperand(Elt.getResNo()).getNode(); 5640} 5641 5642/// CombineConsecutiveLoads - build_pair (load, load) -> load 5643/// if load locations are consecutive. 5644SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5645 assert(N->getOpcode() == ISD::BUILD_PAIR); 5646 5647 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5648 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5649 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5650 LD1->getPointerInfo().getAddrSpace() != 5651 LD2->getPointerInfo().getAddrSpace()) 5652 return SDValue(); 5653 EVT LD1VT = LD1->getValueType(0); 5654 5655 if (ISD::isNON_EXTLoad(LD2) && 5656 LD2->hasOneUse() && 5657 // If both are volatile this would reduce the number of volatile loads. 5658 // If one is volatile it might be ok, but play conservative and bail out. 5659 !LD1->isVolatile() && 5660 !LD2->isVolatile() && 5661 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5662 unsigned Align = LD1->getAlignment(); 5663 unsigned NewAlign = TLI.getDataLayout()-> 5664 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5665 5666 if (NewAlign <= Align && 5667 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5668 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(), 5669 LD1->getBasePtr(), LD1->getPointerInfo(), 5670 false, false, false, Align); 5671 } 5672 5673 return SDValue(); 5674} 5675 5676SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5677 SDValue N0 = N->getOperand(0); 5678 EVT VT = N->getValueType(0); 5679 5680 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5681 // Only do this before legalize, since afterward the target may be depending 5682 // on the bitconvert. 5683 // First check to see if this is all constant. 5684 if (!LegalTypes && 5685 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5686 VT.isVector()) { 5687 bool isSimple = true; 5688 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5689 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5690 N0.getOperand(i).getOpcode() != ISD::Constant && 5691 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5692 isSimple = false; 5693 break; 5694 } 5695 5696 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5697 assert(!DestEltVT.isVector() && 5698 "Element type of vector ValueType must not be vector!"); 5699 if (isSimple) 5700 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5701 } 5702 5703 // If the input is a constant, let getNode fold it. 5704 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5705 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0); 5706 if (Res.getNode() != N) { 5707 if (!LegalOperations || 5708 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5709 return Res; 5710 5711 // Folding it resulted in an illegal node, and it's too late to 5712 // do that. Clean up the old node and forego the transformation. 5713 // Ideally this won't happen very often, because instcombine 5714 // and the earlier dagcombine runs (where illegal nodes are 5715 // permitted) should have folded most of them already. 5716 DAG.DeleteNode(Res.getNode()); 5717 } 5718 } 5719 5720 // (conv (conv x, t1), t2) -> (conv x, t2) 5721 if (N0.getOpcode() == ISD::BITCAST) 5722 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, 5723 N0.getOperand(0)); 5724 5725 // fold (conv (load x)) -> (load (conv*)x) 5726 // If the resultant load doesn't need a higher alignment than the original! 5727 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5728 // Do not change the width of a volatile load. 5729 !cast<LoadSDNode>(N0)->isVolatile() && 5730 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5731 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5732 unsigned Align = TLI.getDataLayout()-> 5733 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5734 unsigned OrigAlign = LN0->getAlignment(); 5735 5736 if (Align <= OrigAlign) { 5737 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), 5738 LN0->getBasePtr(), LN0->getPointerInfo(), 5739 LN0->isVolatile(), LN0->isNonTemporal(), 5740 LN0->isInvariant(), OrigAlign, 5741 LN0->getTBAAInfo()); 5742 AddToWorkList(N); 5743 CombineTo(N0.getNode(), 5744 DAG.getNode(ISD::BITCAST, SDLoc(N0), 5745 N0.getValueType(), Load), 5746 Load.getValue(1)); 5747 return Load; 5748 } 5749 } 5750 5751 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5752 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5753 // This often reduces constant pool loads. 5754 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || 5755 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && 5756 N0.getNode()->hasOneUse() && VT.isInteger() && 5757 !VT.isVector() && !N0.getValueType().isVector()) { 5758 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT, 5759 N0.getOperand(0)); 5760 AddToWorkList(NewConv.getNode()); 5761 5762 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5763 if (N0.getOpcode() == ISD::FNEG) 5764 return DAG.getNode(ISD::XOR, SDLoc(N), VT, 5765 NewConv, DAG.getConstant(SignBit, VT)); 5766 assert(N0.getOpcode() == ISD::FABS); 5767 return DAG.getNode(ISD::AND, SDLoc(N), VT, 5768 NewConv, DAG.getConstant(~SignBit, VT)); 5769 } 5770 5771 // fold (bitconvert (fcopysign cst, x)) -> 5772 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5773 // Note that we don't handle (copysign x, cst) because this can always be 5774 // folded to an fneg or fabs. 5775 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5776 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5777 VT.isInteger() && !VT.isVector()) { 5778 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5779 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5780 if (isTypeLegal(IntXVT)) { 5781 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0), 5782 IntXVT, N0.getOperand(1)); 5783 AddToWorkList(X.getNode()); 5784 5785 // If X has a different width than the result/lhs, sext it or truncate it. 5786 unsigned VTWidth = VT.getSizeInBits(); 5787 if (OrigXWidth < VTWidth) { 5788 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X); 5789 AddToWorkList(X.getNode()); 5790 } else if (OrigXWidth > VTWidth) { 5791 // To get the sign bit in the right place, we have to shift it right 5792 // before truncating. 5793 X = DAG.getNode(ISD::SRL, SDLoc(X), 5794 X.getValueType(), X, 5795 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5796 AddToWorkList(X.getNode()); 5797 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X); 5798 AddToWorkList(X.getNode()); 5799 } 5800 5801 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5802 X = DAG.getNode(ISD::AND, SDLoc(X), VT, 5803 X, DAG.getConstant(SignBit, VT)); 5804 AddToWorkList(X.getNode()); 5805 5806 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0), 5807 VT, N0.getOperand(0)); 5808 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT, 5809 Cst, DAG.getConstant(~SignBit, VT)); 5810 AddToWorkList(Cst.getNode()); 5811 5812 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst); 5813 } 5814 } 5815 5816 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5817 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5818 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5819 if (CombineLD.getNode()) 5820 return CombineLD; 5821 } 5822 5823 return SDValue(); 5824} 5825 5826SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5827 EVT VT = N->getValueType(0); 5828 return CombineConsecutiveLoads(N, VT); 5829} 5830 5831/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5832/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5833/// destination element value type. 5834SDValue DAGCombiner:: 5835ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5836 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5837 5838 // If this is already the right type, we're done. 5839 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5840 5841 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5842 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5843 5844 // If this is a conversion of N elements of one type to N elements of another 5845 // type, convert each element. This handles FP<->INT cases. 5846 if (SrcBitSize == DstBitSize) { 5847 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5848 BV->getValueType(0).getVectorNumElements()); 5849 5850 // Due to the FP element handling below calling this routine recursively, 5851 // we can end up with a scalar-to-vector node here. 5852 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5853 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT, 5854 DAG.getNode(ISD::BITCAST, SDLoc(BV), 5855 DstEltVT, BV->getOperand(0))); 5856 5857 SmallVector<SDValue, 8> Ops; 5858 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5859 SDValue Op = BV->getOperand(i); 5860 // If the vector element type is not legal, the BUILD_VECTOR operands 5861 // are promoted and implicitly truncated. Make that explicit here. 5862 if (Op.getValueType() != SrcEltVT) 5863 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op); 5864 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV), 5865 DstEltVT, Op)); 5866 AddToWorkList(Ops.back().getNode()); 5867 } 5868 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, 5869 &Ops[0], Ops.size()); 5870 } 5871 5872 // Otherwise, we're growing or shrinking the elements. To avoid having to 5873 // handle annoying details of growing/shrinking FP values, we convert them to 5874 // int first. 5875 if (SrcEltVT.isFloatingPoint()) { 5876 // Convert the input float vector to a int vector where the elements are the 5877 // same sizes. 5878 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5879 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5880 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5881 SrcEltVT = IntVT; 5882 } 5883 5884 // Now we know the input is an integer vector. If the output is a FP type, 5885 // convert to integer first, then to FP of the right size. 5886 if (DstEltVT.isFloatingPoint()) { 5887 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5888 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5889 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5890 5891 // Next, convert to FP elements of the same size. 5892 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5893 } 5894 5895 // Okay, we know the src/dst types are both integers of differing types. 5896 // Handling growing first. 5897 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5898 if (SrcBitSize < DstBitSize) { 5899 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5900 5901 SmallVector<SDValue, 8> Ops; 5902 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5903 i += NumInputsPerOutput) { 5904 bool isLE = TLI.isLittleEndian(); 5905 APInt NewBits = APInt(DstBitSize, 0); 5906 bool EltIsUndef = true; 5907 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5908 // Shift the previously computed bits over. 5909 NewBits <<= SrcBitSize; 5910 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5911 if (Op.getOpcode() == ISD::UNDEF) continue; 5912 EltIsUndef = false; 5913 5914 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5915 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5916 } 5917 5918 if (EltIsUndef) 5919 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5920 else 5921 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5922 } 5923 5924 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5925 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, 5926 &Ops[0], Ops.size()); 5927 } 5928 5929 // Finally, this must be the case where we are shrinking elements: each input 5930 // turns into multiple outputs. 5931 bool isS2V = ISD::isScalarToVector(BV); 5932 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5933 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5934 NumOutputsPerInput*BV->getNumOperands()); 5935 SmallVector<SDValue, 8> Ops; 5936 5937 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5938 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5939 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5940 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5941 continue; 5942 } 5943 5944 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5945 getAPIntValue().zextOrTrunc(SrcBitSize); 5946 5947 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5948 APInt ThisVal = OpVal.trunc(DstBitSize); 5949 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5950 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5951 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5952 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT, 5953 Ops[0]); 5954 OpVal = OpVal.lshr(DstBitSize); 5955 } 5956 5957 // For big endian targets, swap the order of the pieces of each element. 5958 if (TLI.isBigEndian()) 5959 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5960 } 5961 5962 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, 5963 &Ops[0], Ops.size()); 5964} 5965 5966SDValue DAGCombiner::visitFADD(SDNode *N) { 5967 SDValue N0 = N->getOperand(0); 5968 SDValue N1 = N->getOperand(1); 5969 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5970 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5971 EVT VT = N->getValueType(0); 5972 5973 // fold vector ops 5974 if (VT.isVector()) { 5975 SDValue FoldedVOp = SimplifyVBinOp(N); 5976 if (FoldedVOp.getNode()) return FoldedVOp; 5977 } 5978 5979 // fold (fadd c1, c2) -> c1 + c2 5980 if (N0CFP && N1CFP) 5981 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1); 5982 // canonicalize constant to RHS 5983 if (N0CFP && !N1CFP) 5984 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0); 5985 // fold (fadd A, 0) -> A 5986 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5987 N1CFP->getValueAPF().isZero()) 5988 return N0; 5989 // fold (fadd A, (fneg B)) -> (fsub A, B) 5990 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5991 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5992 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, 5993 GetNegatedExpression(N1, DAG, LegalOperations)); 5994 // fold (fadd (fneg A), B) -> (fsub B, A) 5995 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5996 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5997 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N1, 5998 GetNegatedExpression(N0, DAG, LegalOperations)); 5999 6000 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 6001 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6002 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 6003 isa<ConstantFPSDNode>(N0.getOperand(1))) 6004 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0), 6005 DAG.getNode(ISD::FADD, SDLoc(N), VT, 6006 N0.getOperand(1), N1)); 6007 6008 // No FP constant should be created after legalization as Instruction 6009 // Selection pass has hard time in dealing with FP constant. 6010 // 6011 // We don't need test this condition for transformation like following, as 6012 // the DAG being transformed implies it is legal to take FP constant as 6013 // operand. 6014 // 6015 // (fadd (fmul c, x), x) -> (fmul c+1, x) 6016 // 6017 bool AllowNewFpConst = (Level < AfterLegalizeDAG); 6018 6019 // If allow, fold (fadd (fneg x), x) -> 0.0 6020 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath && 6021 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) 6022 return DAG.getConstantFP(0.0, VT); 6023 6024 // If allow, fold (fadd x, (fneg x)) -> 0.0 6025 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath && 6026 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) 6027 return DAG.getConstantFP(0.0, VT); 6028 6029 // In unsafe math mode, we can fold chains of FADD's of the same value 6030 // into multiplications. This transform is not safe in general because 6031 // we are reducing the number of rounding steps. 6032 if (DAG.getTarget().Options.UnsafeFPMath && 6033 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 6034 !N0CFP && !N1CFP) { 6035 if (N0.getOpcode() == ISD::FMUL) { 6036 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 6037 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6038 6039 // (fadd (fmul c, x), x) -> (fmul x, c+1) 6040 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 6041 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 6042 SDValue(CFP00, 0), 6043 DAG.getConstantFP(1.0, VT)); 6044 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6045 N1, NewCFP); 6046 } 6047 6048 // (fadd (fmul x, c), x) -> (fmul x, c+1) 6049 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 6050 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 6051 SDValue(CFP01, 0), 6052 DAG.getConstantFP(1.0, VT)); 6053 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6054 N1, NewCFP); 6055 } 6056 6057 // (fadd (fmul c, x), (fadd x, x)) -> (fmul x, c+2) 6058 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 6059 N1.getOperand(0) == N1.getOperand(1) && 6060 N0.getOperand(1) == N1.getOperand(0)) { 6061 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 6062 SDValue(CFP00, 0), 6063 DAG.getConstantFP(2.0, VT)); 6064 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6065 N0.getOperand(1), NewCFP); 6066 } 6067 6068 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2) 6069 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 6070 N1.getOperand(0) == N1.getOperand(1) && 6071 N0.getOperand(0) == N1.getOperand(0)) { 6072 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 6073 SDValue(CFP01, 0), 6074 DAG.getConstantFP(2.0, VT)); 6075 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6076 N0.getOperand(0), NewCFP); 6077 } 6078 } 6079 6080 if (N1.getOpcode() == ISD::FMUL) { 6081 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 6082 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 6083 6084 // (fadd x, (fmul c, x)) -> (fmul x, c+1) 6085 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 6086 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 6087 SDValue(CFP10, 0), 6088 DAG.getConstantFP(1.0, VT)); 6089 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6090 N0, NewCFP); 6091 } 6092 6093 // (fadd x, (fmul x, c)) -> (fmul x, c+1) 6094 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 6095 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 6096 SDValue(CFP11, 0), 6097 DAG.getConstantFP(1.0, VT)); 6098 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6099 N0, NewCFP); 6100 } 6101 6102 6103 // (fadd (fadd x, x), (fmul c, x)) -> (fmul x, c+2) 6104 if (CFP10 && !CFP11 && N0.getOpcode() == ISD::FADD && 6105 N0.getOperand(0) == N0.getOperand(1) && 6106 N1.getOperand(1) == N0.getOperand(0)) { 6107 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 6108 SDValue(CFP10, 0), 6109 DAG.getConstantFP(2.0, VT)); 6110 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6111 N1.getOperand(1), NewCFP); 6112 } 6113 6114 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2) 6115 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD && 6116 N0.getOperand(0) == N0.getOperand(1) && 6117 N1.getOperand(0) == N0.getOperand(0)) { 6118 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 6119 SDValue(CFP11, 0), 6120 DAG.getConstantFP(2.0, VT)); 6121 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6122 N1.getOperand(0), NewCFP); 6123 } 6124 } 6125 6126 if (N0.getOpcode() == ISD::FADD && AllowNewFpConst) { 6127 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 6128 // (fadd (fadd x, x), x) -> (fmul x, 3.0) 6129 if (!CFP && N0.getOperand(0) == N0.getOperand(1) && 6130 (N0.getOperand(0) == N1)) 6131 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6132 N1, DAG.getConstantFP(3.0, VT)); 6133 } 6134 6135 if (N1.getOpcode() == ISD::FADD && AllowNewFpConst) { 6136 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 6137 // (fadd x, (fadd x, x)) -> (fmul x, 3.0) 6138 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) && 6139 N1.getOperand(0) == N0) 6140 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6141 N0, DAG.getConstantFP(3.0, VT)); 6142 } 6143 6144 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0) 6145 if (AllowNewFpConst && 6146 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 6147 N0.getOperand(0) == N0.getOperand(1) && 6148 N1.getOperand(0) == N1.getOperand(1) && 6149 N0.getOperand(0) == N1.getOperand(0)) 6150 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6151 N0.getOperand(0), 6152 DAG.getConstantFP(4.0, VT)); 6153 } 6154 6155 // FADD -> FMA combines: 6156 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 6157 DAG.getTarget().Options.UnsafeFPMath) && 6158 DAG.getTarget().getTargetLowering()->isFMAFasterThanFMulAndFAdd(VT) && 6159 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) { 6160 6161 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 6162 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) 6163 return DAG.getNode(ISD::FMA, SDLoc(N), VT, 6164 N0.getOperand(0), N0.getOperand(1), N1); 6165 6166 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 6167 // Note: Commutes FADD operands. 6168 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) 6169 return DAG.getNode(ISD::FMA, SDLoc(N), VT, 6170 N1.getOperand(0), N1.getOperand(1), N0); 6171 } 6172 6173 return SDValue(); 6174} 6175 6176SDValue DAGCombiner::visitFSUB(SDNode *N) { 6177 SDValue N0 = N->getOperand(0); 6178 SDValue N1 = N->getOperand(1); 6179 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6180 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6181 EVT VT = N->getValueType(0); 6182 SDLoc dl(N); 6183 6184 // fold vector ops 6185 if (VT.isVector()) { 6186 SDValue FoldedVOp = SimplifyVBinOp(N); 6187 if (FoldedVOp.getNode()) return FoldedVOp; 6188 } 6189 6190 // fold (fsub c1, c2) -> c1-c2 6191 if (N0CFP && N1CFP) 6192 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1); 6193 // fold (fsub A, 0) -> A 6194 if (DAG.getTarget().Options.UnsafeFPMath && 6195 N1CFP && N1CFP->getValueAPF().isZero()) 6196 return N0; 6197 // fold (fsub 0, B) -> -B 6198 if (DAG.getTarget().Options.UnsafeFPMath && 6199 N0CFP && N0CFP->getValueAPF().isZero()) { 6200 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 6201 return GetNegatedExpression(N1, DAG, LegalOperations); 6202 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6203 return DAG.getNode(ISD::FNEG, dl, VT, N1); 6204 } 6205 // fold (fsub A, (fneg B)) -> (fadd A, B) 6206 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 6207 return DAG.getNode(ISD::FADD, dl, VT, N0, 6208 GetNegatedExpression(N1, DAG, LegalOperations)); 6209 6210 // If 'unsafe math' is enabled, fold 6211 // (fsub x, x) -> 0.0 & 6212 // (fsub x, (fadd x, y)) -> (fneg y) & 6213 // (fsub x, (fadd y, x)) -> (fneg y) 6214 if (DAG.getTarget().Options.UnsafeFPMath) { 6215 if (N0 == N1) 6216 return DAG.getConstantFP(0.0f, VT); 6217 6218 if (N1.getOpcode() == ISD::FADD) { 6219 SDValue N10 = N1->getOperand(0); 6220 SDValue N11 = N1->getOperand(1); 6221 6222 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 6223 &DAG.getTarget().Options)) 6224 return GetNegatedExpression(N11, DAG, LegalOperations); 6225 6226 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 6227 &DAG.getTarget().Options)) 6228 return GetNegatedExpression(N10, DAG, LegalOperations); 6229 } 6230 } 6231 6232 // FSUB -> FMA combines: 6233 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 6234 DAG.getTarget().Options.UnsafeFPMath) && 6235 DAG.getTarget().getTargetLowering()->isFMAFasterThanFMulAndFAdd(VT) && 6236 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) { 6237 6238 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 6239 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) 6240 return DAG.getNode(ISD::FMA, dl, VT, 6241 N0.getOperand(0), N0.getOperand(1), 6242 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6243 6244 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 6245 // Note: Commutes FSUB operands. 6246 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) 6247 return DAG.getNode(ISD::FMA, dl, VT, 6248 DAG.getNode(ISD::FNEG, dl, VT, 6249 N1.getOperand(0)), 6250 N1.getOperand(1), N0); 6251 6252 // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 6253 if (N0.getOpcode() == ISD::FNEG && 6254 N0.getOperand(0).getOpcode() == ISD::FMUL && 6255 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 6256 SDValue N00 = N0.getOperand(0).getOperand(0); 6257 SDValue N01 = N0.getOperand(0).getOperand(1); 6258 return DAG.getNode(ISD::FMA, dl, VT, 6259 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 6260 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6261 } 6262 } 6263 6264 return SDValue(); 6265} 6266 6267SDValue DAGCombiner::visitFMUL(SDNode *N) { 6268 SDValue N0 = N->getOperand(0); 6269 SDValue N1 = N->getOperand(1); 6270 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6271 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6272 EVT VT = N->getValueType(0); 6273 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6274 6275 // fold vector ops 6276 if (VT.isVector()) { 6277 SDValue FoldedVOp = SimplifyVBinOp(N); 6278 if (FoldedVOp.getNode()) return FoldedVOp; 6279 } 6280 6281 // fold (fmul c1, c2) -> c1*c2 6282 if (N0CFP && N1CFP) 6283 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1); 6284 // canonicalize constant to RHS 6285 if (N0CFP && !N1CFP) 6286 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0); 6287 // fold (fmul A, 0) -> 0 6288 if (DAG.getTarget().Options.UnsafeFPMath && 6289 N1CFP && N1CFP->getValueAPF().isZero()) 6290 return N1; 6291 // fold (fmul A, 0) -> 0, vector edition. 6292 if (DAG.getTarget().Options.UnsafeFPMath && 6293 ISD::isBuildVectorAllZeros(N1.getNode())) 6294 return N1; 6295 // fold (fmul A, 1.0) -> A 6296 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6297 return N0; 6298 // fold (fmul X, 2.0) -> (fadd X, X) 6299 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 6300 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0); 6301 // fold (fmul X, -1.0) -> (fneg X) 6302 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 6303 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6304 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0); 6305 6306 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 6307 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6308 &DAG.getTarget().Options)) { 6309 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6310 &DAG.getTarget().Options)) { 6311 // Both can be negated for free, check to see if at least one is cheaper 6312 // negated. 6313 if (LHSNeg == 2 || RHSNeg == 2) 6314 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6315 GetNegatedExpression(N0, DAG, LegalOperations), 6316 GetNegatedExpression(N1, DAG, LegalOperations)); 6317 } 6318 } 6319 6320 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 6321 if (DAG.getTarget().Options.UnsafeFPMath && 6322 N1CFP && N0.getOpcode() == ISD::FMUL && 6323 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 6324 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0), 6325 DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6326 N0.getOperand(1), N1)); 6327 6328 return SDValue(); 6329} 6330 6331SDValue DAGCombiner::visitFMA(SDNode *N) { 6332 SDValue N0 = N->getOperand(0); 6333 SDValue N1 = N->getOperand(1); 6334 SDValue N2 = N->getOperand(2); 6335 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6336 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6337 EVT VT = N->getValueType(0); 6338 SDLoc dl(N); 6339 6340 if (DAG.getTarget().Options.UnsafeFPMath) { 6341 if (N0CFP && N0CFP->isZero()) 6342 return N2; 6343 if (N1CFP && N1CFP->isZero()) 6344 return N2; 6345 } 6346 if (N0CFP && N0CFP->isExactlyValue(1.0)) 6347 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2); 6348 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6349 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2); 6350 6351 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6352 if (N0CFP && !N1CFP) 6353 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2); 6354 6355 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6356 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6357 N2.getOpcode() == ISD::FMUL && 6358 N0 == N2.getOperand(0) && 6359 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6360 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6361 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6362 } 6363 6364 6365 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6366 if (DAG.getTarget().Options.UnsafeFPMath && 6367 N0.getOpcode() == ISD::FMUL && N1CFP && 6368 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6369 return DAG.getNode(ISD::FMA, dl, VT, 6370 N0.getOperand(0), 6371 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6372 N2); 6373 } 6374 6375 // (fma x, 1, y) -> (fadd x, y) 6376 // (fma x, -1, y) -> (fadd (fneg x), y) 6377 if (N1CFP) { 6378 if (N1CFP->isExactlyValue(1.0)) 6379 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6380 6381 if (N1CFP->isExactlyValue(-1.0) && 6382 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6383 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6384 AddToWorkList(RHSNeg.getNode()); 6385 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6386 } 6387 } 6388 6389 // (fma x, c, x) -> (fmul x, (c+1)) 6390 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) 6391 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6392 DAG.getNode(ISD::FADD, dl, VT, 6393 N1, DAG.getConstantFP(1.0, VT))); 6394 6395 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6396 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6397 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) 6398 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6399 DAG.getNode(ISD::FADD, dl, VT, 6400 N1, DAG.getConstantFP(-1.0, VT))); 6401 6402 6403 return SDValue(); 6404} 6405 6406SDValue DAGCombiner::visitFDIV(SDNode *N) { 6407 SDValue N0 = N->getOperand(0); 6408 SDValue N1 = N->getOperand(1); 6409 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6410 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6411 EVT VT = N->getValueType(0); 6412 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6413 6414 // fold vector ops 6415 if (VT.isVector()) { 6416 SDValue FoldedVOp = SimplifyVBinOp(N); 6417 if (FoldedVOp.getNode()) return FoldedVOp; 6418 } 6419 6420 // fold (fdiv c1, c2) -> c1/c2 6421 if (N0CFP && N1CFP) 6422 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1); 6423 6424 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6425 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) { 6426 // Compute the reciprocal 1.0 / c2. 6427 APFloat N1APF = N1CFP->getValueAPF(); 6428 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6429 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6430 // Only do the transform if the reciprocal is a legal fp immediate that 6431 // isn't too nasty (eg NaN, denormal, ...). 6432 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6433 (!LegalOperations || 6434 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6435 // backend)... we should handle this gracefully after Legalize. 6436 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6437 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6438 TLI.isFPImmLegal(Recip, VT))) 6439 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, 6440 DAG.getConstantFP(Recip, VT)); 6441 } 6442 6443 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6444 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6445 &DAG.getTarget().Options)) { 6446 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6447 &DAG.getTarget().Options)) { 6448 // Both can be negated for free, check to see if at least one is cheaper 6449 // negated. 6450 if (LHSNeg == 2 || RHSNeg == 2) 6451 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, 6452 GetNegatedExpression(N0, DAG, LegalOperations), 6453 GetNegatedExpression(N1, DAG, LegalOperations)); 6454 } 6455 } 6456 6457 return SDValue(); 6458} 6459 6460SDValue DAGCombiner::visitFREM(SDNode *N) { 6461 SDValue N0 = N->getOperand(0); 6462 SDValue N1 = N->getOperand(1); 6463 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6464 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6465 EVT VT = N->getValueType(0); 6466 6467 // fold (frem c1, c2) -> fmod(c1,c2) 6468 if (N0CFP && N1CFP) 6469 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1); 6470 6471 return SDValue(); 6472} 6473 6474SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6475 SDValue N0 = N->getOperand(0); 6476 SDValue N1 = N->getOperand(1); 6477 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6478 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6479 EVT VT = N->getValueType(0); 6480 6481 if (N0CFP && N1CFP) // Constant fold 6482 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1); 6483 6484 if (N1CFP) { 6485 const APFloat& V = N1CFP->getValueAPF(); 6486 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6487 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6488 if (!V.isNegative()) { 6489 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6490 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); 6491 } else { 6492 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6493 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, 6494 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0)); 6495 } 6496 } 6497 6498 // copysign(fabs(x), y) -> copysign(x, y) 6499 // copysign(fneg(x), y) -> copysign(x, y) 6500 // copysign(copysign(x,z), y) -> copysign(x, y) 6501 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6502 N0.getOpcode() == ISD::FCOPYSIGN) 6503 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, 6504 N0.getOperand(0), N1); 6505 6506 // copysign(x, abs(y)) -> abs(x) 6507 if (N1.getOpcode() == ISD::FABS) 6508 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); 6509 6510 // copysign(x, copysign(y,z)) -> copysign(x, z) 6511 if (N1.getOpcode() == ISD::FCOPYSIGN) 6512 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, 6513 N0, N1.getOperand(1)); 6514 6515 // copysign(x, fp_extend(y)) -> copysign(x, y) 6516 // copysign(x, fp_round(y)) -> copysign(x, y) 6517 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6518 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, 6519 N0, N1.getOperand(0)); 6520 6521 return SDValue(); 6522} 6523 6524SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6525 SDValue N0 = N->getOperand(0); 6526 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6527 EVT VT = N->getValueType(0); 6528 EVT OpVT = N0.getValueType(); 6529 6530 // fold (sint_to_fp c1) -> c1fp 6531 if (N0C && 6532 // ...but only if the target supports immediate floating-point values 6533 (!LegalOperations || 6534 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6535 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); 6536 6537 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6538 // but UINT_TO_FP is legal on this target, try to convert. 6539 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6540 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6541 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6542 if (DAG.SignBitIsZero(N0)) 6543 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); 6544 } 6545 6546 // The next optimizations are desireable only if SELECT_CC can be lowered. 6547 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6548 // having to say they don't support SELECT_CC on every type the DAG knows 6549 // about, since there is no way to mark an opcode illegal at all value types 6550 // (See also visitSELECT) 6551 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6552 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6553 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6554 !VT.isVector() && 6555 (!LegalOperations || 6556 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6557 SDValue Ops[] = 6558 { N0.getOperand(0), N0.getOperand(1), 6559 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6560 N0.getOperand(2) }; 6561 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5); 6562 } 6563 6564 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6565 // (select_cc x, y, 1.0, 0.0,, cc) 6566 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6567 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6568 (!LegalOperations || 6569 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6570 SDValue Ops[] = 6571 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6572 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6573 N0.getOperand(0).getOperand(2) }; 6574 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5); 6575 } 6576 } 6577 6578 return SDValue(); 6579} 6580 6581SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6582 SDValue N0 = N->getOperand(0); 6583 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6584 EVT VT = N->getValueType(0); 6585 EVT OpVT = N0.getValueType(); 6586 6587 // fold (uint_to_fp c1) -> c1fp 6588 if (N0C && 6589 // ...but only if the target supports immediate floating-point values 6590 (!LegalOperations || 6591 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6592 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); 6593 6594 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6595 // but SINT_TO_FP is legal on this target, try to convert. 6596 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6597 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6598 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6599 if (DAG.SignBitIsZero(N0)) 6600 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); 6601 } 6602 6603 // The next optimizations are desireable only if SELECT_CC can be lowered. 6604 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6605 // having to say they don't support SELECT_CC on every type the DAG knows 6606 // about, since there is no way to mark an opcode illegal at all value types 6607 // (See also visitSELECT) 6608 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6609 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6610 6611 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6612 (!LegalOperations || 6613 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6614 SDValue Ops[] = 6615 { N0.getOperand(0), N0.getOperand(1), 6616 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6617 N0.getOperand(2) }; 6618 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5); 6619 } 6620 } 6621 6622 return SDValue(); 6623} 6624 6625SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6626 SDValue N0 = N->getOperand(0); 6627 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6628 EVT VT = N->getValueType(0); 6629 6630 // fold (fp_to_sint c1fp) -> c1 6631 if (N0CFP) 6632 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0); 6633 6634 return SDValue(); 6635} 6636 6637SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6638 SDValue N0 = N->getOperand(0); 6639 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6640 EVT VT = N->getValueType(0); 6641 6642 // fold (fp_to_uint c1fp) -> c1 6643 if (N0CFP) 6644 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0); 6645 6646 return SDValue(); 6647} 6648 6649SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6650 SDValue N0 = N->getOperand(0); 6651 SDValue N1 = N->getOperand(1); 6652 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6653 EVT VT = N->getValueType(0); 6654 6655 // fold (fp_round c1fp) -> c1fp 6656 if (N0CFP) 6657 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1); 6658 6659 // fold (fp_round (fp_extend x)) -> x 6660 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6661 return N0.getOperand(0); 6662 6663 // fold (fp_round (fp_round x)) -> (fp_round x) 6664 if (N0.getOpcode() == ISD::FP_ROUND) { 6665 // This is a value preserving truncation if both round's are. 6666 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6667 N0.getNode()->getConstantOperandVal(1) == 1; 6668 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0), 6669 DAG.getIntPtrConstant(IsTrunc)); 6670 } 6671 6672 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6673 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6674 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT, 6675 N0.getOperand(0), N1); 6676 AddToWorkList(Tmp.getNode()); 6677 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, 6678 Tmp, N0.getOperand(1)); 6679 } 6680 6681 return SDValue(); 6682} 6683 6684SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6685 SDValue N0 = N->getOperand(0); 6686 EVT VT = N->getValueType(0); 6687 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6688 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6689 6690 // fold (fp_round_inreg c1fp) -> c1fp 6691 if (N0CFP && isTypeLegal(EVT)) { 6692 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6693 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Round); 6694 } 6695 6696 return SDValue(); 6697} 6698 6699SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6700 SDValue N0 = N->getOperand(0); 6701 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6702 EVT VT = N->getValueType(0); 6703 6704 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6705 if (N->hasOneUse() && 6706 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6707 return SDValue(); 6708 6709 // fold (fp_extend c1fp) -> c1fp 6710 if (N0CFP) 6711 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0); 6712 6713 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6714 // value of X. 6715 if (N0.getOpcode() == ISD::FP_ROUND 6716 && N0.getNode()->getConstantOperandVal(1) == 1) { 6717 SDValue In = N0.getOperand(0); 6718 if (In.getValueType() == VT) return In; 6719 if (VT.bitsLT(In.getValueType())) 6720 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, 6721 In, N0.getOperand(1)); 6722 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In); 6723 } 6724 6725 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6726 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6727 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6728 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6729 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6730 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, 6731 LN0->getChain(), 6732 LN0->getBasePtr(), N0.getValueType(), 6733 LN0->getMemOperand()); 6734 CombineTo(N, ExtLoad); 6735 CombineTo(N0.getNode(), 6736 DAG.getNode(ISD::FP_ROUND, SDLoc(N0), 6737 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6738 ExtLoad.getValue(1)); 6739 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6740 } 6741 6742 return SDValue(); 6743} 6744 6745SDValue DAGCombiner::visitFNEG(SDNode *N) { 6746 SDValue N0 = N->getOperand(0); 6747 EVT VT = N->getValueType(0); 6748 6749 if (VT.isVector()) { 6750 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6751 if (FoldedVOp.getNode()) return FoldedVOp; 6752 } 6753 6754 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6755 &DAG.getTarget().Options)) 6756 return GetNegatedExpression(N0, DAG, LegalOperations); 6757 6758 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6759 // constant pool values. 6760 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6761 !VT.isVector() && 6762 N0.getNode()->hasOneUse() && 6763 N0.getOperand(0).getValueType().isInteger()) { 6764 SDValue Int = N0.getOperand(0); 6765 EVT IntVT = Int.getValueType(); 6766 if (IntVT.isInteger() && !IntVT.isVector()) { 6767 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int, 6768 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6769 AddToWorkList(Int.getNode()); 6770 return DAG.getNode(ISD::BITCAST, SDLoc(N), 6771 VT, Int); 6772 } 6773 } 6774 6775 // (fneg (fmul c, x)) -> (fmul -c, x) 6776 if (N0.getOpcode() == ISD::FMUL) { 6777 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6778 if (CFP1) 6779 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6780 N0.getOperand(0), 6781 DAG.getNode(ISD::FNEG, SDLoc(N), VT, 6782 N0.getOperand(1))); 6783 } 6784 6785 return SDValue(); 6786} 6787 6788SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6789 SDValue N0 = N->getOperand(0); 6790 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6791 EVT VT = N->getValueType(0); 6792 6793 // fold (fceil c1) -> fceil(c1) 6794 if (N0CFP) 6795 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0); 6796 6797 return SDValue(); 6798} 6799 6800SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6801 SDValue N0 = N->getOperand(0); 6802 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6803 EVT VT = N->getValueType(0); 6804 6805 // fold (ftrunc c1) -> ftrunc(c1) 6806 if (N0CFP) 6807 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0); 6808 6809 return SDValue(); 6810} 6811 6812SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6813 SDValue N0 = N->getOperand(0); 6814 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6815 EVT VT = N->getValueType(0); 6816 6817 // fold (ffloor c1) -> ffloor(c1) 6818 if (N0CFP) 6819 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0); 6820 6821 return SDValue(); 6822} 6823 6824SDValue DAGCombiner::visitFABS(SDNode *N) { 6825 SDValue N0 = N->getOperand(0); 6826 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6827 EVT VT = N->getValueType(0); 6828 6829 if (VT.isVector()) { 6830 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6831 if (FoldedVOp.getNode()) return FoldedVOp; 6832 } 6833 6834 // fold (fabs c1) -> fabs(c1) 6835 if (N0CFP) 6836 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); 6837 // fold (fabs (fabs x)) -> (fabs x) 6838 if (N0.getOpcode() == ISD::FABS) 6839 return N->getOperand(0); 6840 // fold (fabs (fneg x)) -> (fabs x) 6841 // fold (fabs (fcopysign x, y)) -> (fabs x) 6842 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6843 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0)); 6844 6845 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6846 // constant pool values. 6847 if (!TLI.isFAbsFree(VT) && 6848 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6849 N0.getOperand(0).getValueType().isInteger() && 6850 !N0.getOperand(0).getValueType().isVector()) { 6851 SDValue Int = N0.getOperand(0); 6852 EVT IntVT = Int.getValueType(); 6853 if (IntVT.isInteger() && !IntVT.isVector()) { 6854 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int, 6855 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6856 AddToWorkList(Int.getNode()); 6857 return DAG.getNode(ISD::BITCAST, SDLoc(N), 6858 N->getValueType(0), Int); 6859 } 6860 } 6861 6862 return SDValue(); 6863} 6864 6865SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6866 SDValue Chain = N->getOperand(0); 6867 SDValue N1 = N->getOperand(1); 6868 SDValue N2 = N->getOperand(2); 6869 6870 // If N is a constant we could fold this into a fallthrough or unconditional 6871 // branch. However that doesn't happen very often in normal code, because 6872 // Instcombine/SimplifyCFG should have handled the available opportunities. 6873 // If we did this folding here, it would be necessary to update the 6874 // MachineBasicBlock CFG, which is awkward. 6875 6876 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6877 // on the target. 6878 if (N1.getOpcode() == ISD::SETCC && 6879 TLI.isOperationLegalOrCustom(ISD::BR_CC, 6880 N1.getOperand(0).getValueType())) { 6881 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, 6882 Chain, N1.getOperand(2), 6883 N1.getOperand(0), N1.getOperand(1), N2); 6884 } 6885 6886 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6887 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6888 (N1.getOperand(0).hasOneUse() && 6889 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6890 SDNode *Trunc = 0; 6891 if (N1.getOpcode() == ISD::TRUNCATE) { 6892 // Look pass the truncate. 6893 Trunc = N1.getNode(); 6894 N1 = N1.getOperand(0); 6895 } 6896 6897 // Match this pattern so that we can generate simpler code: 6898 // 6899 // %a = ... 6900 // %b = and i32 %a, 2 6901 // %c = srl i32 %b, 1 6902 // brcond i32 %c ... 6903 // 6904 // into 6905 // 6906 // %a = ... 6907 // %b = and i32 %a, 2 6908 // %c = setcc eq %b, 0 6909 // brcond %c ... 6910 // 6911 // This applies only when the AND constant value has one bit set and the 6912 // SRL constant is equal to the log2 of the AND constant. The back-end is 6913 // smart enough to convert the result into a TEST/JMP sequence. 6914 SDValue Op0 = N1.getOperand(0); 6915 SDValue Op1 = N1.getOperand(1); 6916 6917 if (Op0.getOpcode() == ISD::AND && 6918 Op1.getOpcode() == ISD::Constant) { 6919 SDValue AndOp1 = Op0.getOperand(1); 6920 6921 if (AndOp1.getOpcode() == ISD::Constant) { 6922 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6923 6924 if (AndConst.isPowerOf2() && 6925 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6926 SDValue SetCC = 6927 DAG.getSetCC(SDLoc(N), 6928 getSetCCResultType(Op0.getValueType()), 6929 Op0, DAG.getConstant(0, Op0.getValueType()), 6930 ISD::SETNE); 6931 6932 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N), 6933 MVT::Other, Chain, SetCC, N2); 6934 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6935 // will convert it back to (X & C1) >> C2. 6936 CombineTo(N, NewBRCond, false); 6937 // Truncate is dead. 6938 if (Trunc) { 6939 removeFromWorkList(Trunc); 6940 DAG.DeleteNode(Trunc); 6941 } 6942 // Replace the uses of SRL with SETCC 6943 WorkListRemover DeadNodes(*this); 6944 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6945 removeFromWorkList(N1.getNode()); 6946 DAG.DeleteNode(N1.getNode()); 6947 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6948 } 6949 } 6950 } 6951 6952 if (Trunc) 6953 // Restore N1 if the above transformation doesn't match. 6954 N1 = N->getOperand(1); 6955 } 6956 6957 // Transform br(xor(x, y)) -> br(x != y) 6958 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6959 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6960 SDNode *TheXor = N1.getNode(); 6961 SDValue Op0 = TheXor->getOperand(0); 6962 SDValue Op1 = TheXor->getOperand(1); 6963 if (Op0.getOpcode() == Op1.getOpcode()) { 6964 // Avoid missing important xor optimizations. 6965 SDValue Tmp = visitXOR(TheXor); 6966 if (Tmp.getNode()) { 6967 if (Tmp.getNode() != TheXor) { 6968 DEBUG(dbgs() << "\nReplacing.8 "; 6969 TheXor->dump(&DAG); 6970 dbgs() << "\nWith: "; 6971 Tmp.getNode()->dump(&DAG); 6972 dbgs() << '\n'); 6973 WorkListRemover DeadNodes(*this); 6974 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6975 removeFromWorkList(TheXor); 6976 DAG.DeleteNode(TheXor); 6977 return DAG.getNode(ISD::BRCOND, SDLoc(N), 6978 MVT::Other, Chain, Tmp, N2); 6979 } 6980 6981 // visitXOR has changed XOR's operands or replaced the XOR completely, 6982 // bail out. 6983 return SDValue(N, 0); 6984 } 6985 } 6986 6987 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6988 bool Equal = false; 6989 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6990 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6991 Op0.getOpcode() == ISD::XOR) { 6992 TheXor = Op0.getNode(); 6993 Equal = true; 6994 } 6995 6996 EVT SetCCVT = N1.getValueType(); 6997 if (LegalTypes) 6998 SetCCVT = getSetCCResultType(SetCCVT); 6999 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor), 7000 SetCCVT, 7001 Op0, Op1, 7002 Equal ? ISD::SETEQ : ISD::SETNE); 7003 // Replace the uses of XOR with SETCC 7004 WorkListRemover DeadNodes(*this); 7005 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 7006 removeFromWorkList(N1.getNode()); 7007 DAG.DeleteNode(N1.getNode()); 7008 return DAG.getNode(ISD::BRCOND, SDLoc(N), 7009 MVT::Other, Chain, SetCC, N2); 7010 } 7011 } 7012 7013 return SDValue(); 7014} 7015 7016// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 7017// 7018SDValue DAGCombiner::visitBR_CC(SDNode *N) { 7019 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 7020 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 7021 7022 // If N is a constant we could fold this into a fallthrough or unconditional 7023 // branch. However that doesn't happen very often in normal code, because 7024 // Instcombine/SimplifyCFG should have handled the available opportunities. 7025 // If we did this folding here, it would be necessary to update the 7026 // MachineBasicBlock CFG, which is awkward. 7027 7028 // Use SimplifySetCC to simplify SETCC's. 7029 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()), 7030 CondLHS, CondRHS, CC->get(), SDLoc(N), 7031 false); 7032 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 7033 7034 // fold to a simpler setcc 7035 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 7036 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, 7037 N->getOperand(0), Simp.getOperand(2), 7038 Simp.getOperand(0), Simp.getOperand(1), 7039 N->getOperand(4)); 7040 7041 return SDValue(); 7042} 7043 7044/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 7045/// uses N as its base pointer and that N may be folded in the load / store 7046/// addressing mode. 7047static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 7048 SelectionDAG &DAG, 7049 const TargetLowering &TLI) { 7050 EVT VT; 7051 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 7052 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 7053 return false; 7054 VT = Use->getValueType(0); 7055 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 7056 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 7057 return false; 7058 VT = ST->getValue().getValueType(); 7059 } else 7060 return false; 7061 7062 TargetLowering::AddrMode AM; 7063 if (N->getOpcode() == ISD::ADD) { 7064 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7065 if (Offset) 7066 // [reg +/- imm] 7067 AM.BaseOffs = Offset->getSExtValue(); 7068 else 7069 // [reg +/- reg] 7070 AM.Scale = 1; 7071 } else if (N->getOpcode() == ISD::SUB) { 7072 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7073 if (Offset) 7074 // [reg +/- imm] 7075 AM.BaseOffs = -Offset->getSExtValue(); 7076 else 7077 // [reg +/- reg] 7078 AM.Scale = 1; 7079 } else 7080 return false; 7081 7082 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 7083} 7084 7085/// CombineToPreIndexedLoadStore - Try turning a load / store into a 7086/// pre-indexed load / store when the base pointer is an add or subtract 7087/// and it has other uses besides the load / store. After the 7088/// transformation, the new indexed load / store has effectively folded 7089/// the add / subtract in and all of its other uses are redirected to the 7090/// new load / store. 7091bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 7092 if (Level < AfterLegalizeDAG) 7093 return false; 7094 7095 bool isLoad = true; 7096 SDValue Ptr; 7097 EVT VT; 7098 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7099 if (LD->isIndexed()) 7100 return false; 7101 VT = LD->getMemoryVT(); 7102 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 7103 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 7104 return false; 7105 Ptr = LD->getBasePtr(); 7106 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7107 if (ST->isIndexed()) 7108 return false; 7109 VT = ST->getMemoryVT(); 7110 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 7111 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 7112 return false; 7113 Ptr = ST->getBasePtr(); 7114 isLoad = false; 7115 } else { 7116 return false; 7117 } 7118 7119 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 7120 // out. There is no reason to make this a preinc/predec. 7121 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 7122 Ptr.getNode()->hasOneUse()) 7123 return false; 7124 7125 // Ask the target to do addressing mode selection. 7126 SDValue BasePtr; 7127 SDValue Offset; 7128 ISD::MemIndexedMode AM = ISD::UNINDEXED; 7129 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 7130 return false; 7131 7132 // Backends without true r+i pre-indexed forms may need to pass a 7133 // constant base with a variable offset so that constant coercion 7134 // will work with the patterns in canonical form. 7135 bool Swapped = false; 7136 if (isa<ConstantSDNode>(BasePtr)) { 7137 std::swap(BasePtr, Offset); 7138 Swapped = true; 7139 } 7140 7141 // Don't create a indexed load / store with zero offset. 7142 if (isa<ConstantSDNode>(Offset) && 7143 cast<ConstantSDNode>(Offset)->isNullValue()) 7144 return false; 7145 7146 // Try turning it into a pre-indexed load / store except when: 7147 // 1) The new base ptr is a frame index. 7148 // 2) If N is a store and the new base ptr is either the same as or is a 7149 // predecessor of the value being stored. 7150 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 7151 // that would create a cycle. 7152 // 4) All uses are load / store ops that use it as old base ptr. 7153 7154 // Check #1. Preinc'ing a frame index would require copying the stack pointer 7155 // (plus the implicit offset) to a register to preinc anyway. 7156 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 7157 return false; 7158 7159 // Check #2. 7160 if (!isLoad) { 7161 SDValue Val = cast<StoreSDNode>(N)->getValue(); 7162 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 7163 return false; 7164 } 7165 7166 // If the offset is a constant, there may be other adds of constants that 7167 // can be folded with this one. We should do this to avoid having to keep 7168 // a copy of the original base pointer. 7169 SmallVector<SDNode *, 16> OtherUses; 7170 if (isa<ConstantSDNode>(Offset)) 7171 for (SDNode::use_iterator I = BasePtr.getNode()->use_begin(), 7172 E = BasePtr.getNode()->use_end(); I != E; ++I) { 7173 SDNode *Use = *I; 7174 if (Use == Ptr.getNode()) 7175 continue; 7176 7177 if (Use->isPredecessorOf(N)) 7178 continue; 7179 7180 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) { 7181 OtherUses.clear(); 7182 break; 7183 } 7184 7185 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1); 7186 if (Op1.getNode() == BasePtr.getNode()) 7187 std::swap(Op0, Op1); 7188 assert(Op0.getNode() == BasePtr.getNode() && 7189 "Use of ADD/SUB but not an operand"); 7190 7191 if (!isa<ConstantSDNode>(Op1)) { 7192 OtherUses.clear(); 7193 break; 7194 } 7195 7196 // FIXME: In some cases, we can be smarter about this. 7197 if (Op1.getValueType() != Offset.getValueType()) { 7198 OtherUses.clear(); 7199 break; 7200 } 7201 7202 OtherUses.push_back(Use); 7203 } 7204 7205 if (Swapped) 7206 std::swap(BasePtr, Offset); 7207 7208 // Now check for #3 and #4. 7209 bool RealUse = false; 7210 7211 // Caches for hasPredecessorHelper 7212 SmallPtrSet<const SDNode *, 32> Visited; 7213 SmallVector<const SDNode *, 16> Worklist; 7214 7215 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 7216 E = Ptr.getNode()->use_end(); I != E; ++I) { 7217 SDNode *Use = *I; 7218 if (Use == N) 7219 continue; 7220 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 7221 return false; 7222 7223 // If Ptr may be folded in addressing mode of other use, then it's 7224 // not profitable to do this transformation. 7225 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 7226 RealUse = true; 7227 } 7228 7229 if (!RealUse) 7230 return false; 7231 7232 SDValue Result; 7233 if (isLoad) 7234 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N), 7235 BasePtr, Offset, AM); 7236 else 7237 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N), 7238 BasePtr, Offset, AM); 7239 ++PreIndexedNodes; 7240 ++NodesCombined; 7241 DEBUG(dbgs() << "\nReplacing.4 "; 7242 N->dump(&DAG); 7243 dbgs() << "\nWith: "; 7244 Result.getNode()->dump(&DAG); 7245 dbgs() << '\n'); 7246 WorkListRemover DeadNodes(*this); 7247 if (isLoad) { 7248 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7249 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7250 } else { 7251 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7252 } 7253 7254 // Finally, since the node is now dead, remove it from the graph. 7255 DAG.DeleteNode(N); 7256 7257 if (Swapped) 7258 std::swap(BasePtr, Offset); 7259 7260 // Replace other uses of BasePtr that can be updated to use Ptr 7261 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) { 7262 unsigned OffsetIdx = 1; 7263 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode()) 7264 OffsetIdx = 0; 7265 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() == 7266 BasePtr.getNode() && "Expected BasePtr operand"); 7267 7268 // We need to replace ptr0 in the following expression: 7269 // x0 * offset0 + y0 * ptr0 = t0 7270 // knowing that 7271 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store) 7272 // 7273 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the 7274 // indexed load/store and the expresion that needs to be re-written. 7275 // 7276 // Therefore, we have: 7277 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1 7278 7279 ConstantSDNode *CN = 7280 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx)); 7281 int X0, X1, Y0, Y1; 7282 APInt Offset0 = CN->getAPIntValue(); 7283 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue(); 7284 7285 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; 7286 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; 7287 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1; 7288 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1; 7289 7290 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD; 7291 7292 APInt CNV = Offset0; 7293 if (X0 < 0) CNV = -CNV; 7294 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1; 7295 else CNV = CNV - Offset1; 7296 7297 // We can now generate the new expression. 7298 SDValue NewOp1 = DAG.getConstant(CNV, CN->getValueType(0)); 7299 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0); 7300 7301 SDValue NewUse = DAG.getNode(Opcode, 7302 SDLoc(OtherUses[i]), 7303 OtherUses[i]->getValueType(0), NewOp1, NewOp2); 7304 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse); 7305 removeFromWorkList(OtherUses[i]); 7306 DAG.DeleteNode(OtherUses[i]); 7307 } 7308 7309 // Replace the uses of Ptr with uses of the updated base value. 7310 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 7311 removeFromWorkList(Ptr.getNode()); 7312 DAG.DeleteNode(Ptr.getNode()); 7313 7314 return true; 7315} 7316 7317/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 7318/// add / sub of the base pointer node into a post-indexed load / store. 7319/// The transformation folded the add / subtract into the new indexed 7320/// load / store effectively and all of its uses are redirected to the 7321/// new load / store. 7322bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 7323 if (Level < AfterLegalizeDAG) 7324 return false; 7325 7326 bool isLoad = true; 7327 SDValue Ptr; 7328 EVT VT; 7329 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7330 if (LD->isIndexed()) 7331 return false; 7332 VT = LD->getMemoryVT(); 7333 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 7334 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 7335 return false; 7336 Ptr = LD->getBasePtr(); 7337 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7338 if (ST->isIndexed()) 7339 return false; 7340 VT = ST->getMemoryVT(); 7341 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 7342 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 7343 return false; 7344 Ptr = ST->getBasePtr(); 7345 isLoad = false; 7346 } else { 7347 return false; 7348 } 7349 7350 if (Ptr.getNode()->hasOneUse()) 7351 return false; 7352 7353 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 7354 E = Ptr.getNode()->use_end(); I != E; ++I) { 7355 SDNode *Op = *I; 7356 if (Op == N || 7357 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 7358 continue; 7359 7360 SDValue BasePtr; 7361 SDValue Offset; 7362 ISD::MemIndexedMode AM = ISD::UNINDEXED; 7363 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 7364 // Don't create a indexed load / store with zero offset. 7365 if (isa<ConstantSDNode>(Offset) && 7366 cast<ConstantSDNode>(Offset)->isNullValue()) 7367 continue; 7368 7369 // Try turning it into a post-indexed load / store except when 7370 // 1) All uses are load / store ops that use it as base ptr (and 7371 // it may be folded as addressing mmode). 7372 // 2) Op must be independent of N, i.e. Op is neither a predecessor 7373 // nor a successor of N. Otherwise, if Op is folded that would 7374 // create a cycle. 7375 7376 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 7377 continue; 7378 7379 // Check for #1. 7380 bool TryNext = false; 7381 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 7382 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 7383 SDNode *Use = *II; 7384 if (Use == Ptr.getNode()) 7385 continue; 7386 7387 // If all the uses are load / store addresses, then don't do the 7388 // transformation. 7389 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 7390 bool RealUse = false; 7391 for (SDNode::use_iterator III = Use->use_begin(), 7392 EEE = Use->use_end(); III != EEE; ++III) { 7393 SDNode *UseUse = *III; 7394 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 7395 RealUse = true; 7396 } 7397 7398 if (!RealUse) { 7399 TryNext = true; 7400 break; 7401 } 7402 } 7403 } 7404 7405 if (TryNext) 7406 continue; 7407 7408 // Check for #2 7409 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 7410 SDValue Result = isLoad 7411 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N), 7412 BasePtr, Offset, AM) 7413 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N), 7414 BasePtr, Offset, AM); 7415 ++PostIndexedNodes; 7416 ++NodesCombined; 7417 DEBUG(dbgs() << "\nReplacing.5 "; 7418 N->dump(&DAG); 7419 dbgs() << "\nWith: "; 7420 Result.getNode()->dump(&DAG); 7421 dbgs() << '\n'); 7422 WorkListRemover DeadNodes(*this); 7423 if (isLoad) { 7424 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7425 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7426 } else { 7427 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7428 } 7429 7430 // Finally, since the node is now dead, remove it from the graph. 7431 DAG.DeleteNode(N); 7432 7433 // Replace the uses of Use with uses of the updated base value. 7434 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 7435 Result.getValue(isLoad ? 1 : 0)); 7436 removeFromWorkList(Op); 7437 DAG.DeleteNode(Op); 7438 return true; 7439 } 7440 } 7441 } 7442 7443 return false; 7444} 7445 7446SDValue DAGCombiner::visitLOAD(SDNode *N) { 7447 LoadSDNode *LD = cast<LoadSDNode>(N); 7448 SDValue Chain = LD->getChain(); 7449 SDValue Ptr = LD->getBasePtr(); 7450 7451 // If load is not volatile and there are no uses of the loaded value (and 7452 // the updated indexed value in case of indexed loads), change uses of the 7453 // chain value into uses of the chain input (i.e. delete the dead load). 7454 if (!LD->isVolatile()) { 7455 if (N->getValueType(1) == MVT::Other) { 7456 // Unindexed loads. 7457 if (!N->hasAnyUseOfValue(0)) { 7458 // It's not safe to use the two value CombineTo variant here. e.g. 7459 // v1, chain2 = load chain1, loc 7460 // v2, chain3 = load chain2, loc 7461 // v3 = add v2, c 7462 // Now we replace use of chain2 with chain1. This makes the second load 7463 // isomorphic to the one we are deleting, and thus makes this load live. 7464 DEBUG(dbgs() << "\nReplacing.6 "; 7465 N->dump(&DAG); 7466 dbgs() << "\nWith chain: "; 7467 Chain.getNode()->dump(&DAG); 7468 dbgs() << "\n"); 7469 WorkListRemover DeadNodes(*this); 7470 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7471 7472 if (N->use_empty()) { 7473 removeFromWorkList(N); 7474 DAG.DeleteNode(N); 7475 } 7476 7477 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7478 } 7479 } else { 7480 // Indexed loads. 7481 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7482 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7483 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7484 DEBUG(dbgs() << "\nReplacing.7 "; 7485 N->dump(&DAG); 7486 dbgs() << "\nWith: "; 7487 Undef.getNode()->dump(&DAG); 7488 dbgs() << " and 2 other values\n"); 7489 WorkListRemover DeadNodes(*this); 7490 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7491 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7492 DAG.getUNDEF(N->getValueType(1))); 7493 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7494 removeFromWorkList(N); 7495 DAG.DeleteNode(N); 7496 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7497 } 7498 } 7499 } 7500 7501 // If this load is directly stored, replace the load value with the stored 7502 // value. 7503 // TODO: Handle store large -> read small portion. 7504 // TODO: Handle TRUNCSTORE/LOADEXT 7505 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7506 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7507 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7508 if (PrevST->getBasePtr() == Ptr && 7509 PrevST->getValue().getValueType() == N->getValueType(0)) 7510 return CombineTo(N, Chain.getOperand(1), Chain); 7511 } 7512 } 7513 7514 // Try to infer better alignment information than the load already has. 7515 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7516 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7517 if (Align > LD->getMemOperand()->getBaseAlignment()) { 7518 SDValue NewLoad = 7519 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N), 7520 LD->getValueType(0), 7521 Chain, Ptr, LD->getPointerInfo(), 7522 LD->getMemoryVT(), 7523 LD->isVolatile(), LD->isNonTemporal(), Align, 7524 LD->getTBAAInfo()); 7525 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true); 7526 } 7527 } 7528 } 7529 7530 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA : 7531 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA(); 7532 if (UseAA) { 7533 // Walk up chain skipping non-aliasing memory nodes. 7534 SDValue BetterChain = FindBetterChain(N, Chain); 7535 7536 // If there is a better chain. 7537 if (Chain != BetterChain) { 7538 SDValue ReplLoad; 7539 7540 // Replace the chain to void dependency. 7541 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7542 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD), 7543 BetterChain, Ptr, LD->getMemOperand()); 7544 } else { 7545 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), 7546 LD->getValueType(0), 7547 BetterChain, Ptr, LD->getMemoryVT(), 7548 LD->getMemOperand()); 7549 } 7550 7551 // Create token factor to keep old chain connected. 7552 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N), 7553 MVT::Other, Chain, ReplLoad.getValue(1)); 7554 7555 // Make sure the new and old chains are cleaned up. 7556 AddToWorkList(Token.getNode()); 7557 7558 // Replace uses with load result and token factor. Don't add users 7559 // to work list. 7560 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7561 } 7562 } 7563 7564 // Try transforming N to an indexed load. 7565 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7566 return SDValue(N, 0); 7567 7568 // Try to slice up N to more direct loads if the slices are mapped to 7569 // different register banks or pairing can take place. 7570 if (SliceUpLoad(N)) 7571 return SDValue(N, 0); 7572 7573 return SDValue(); 7574} 7575 7576namespace { 7577/// \brief Helper structure used to slice a load in smaller loads. 7578/// Basically a slice is obtained from the following sequence: 7579/// Origin = load Ty1, Base 7580/// Shift = srl Ty1 Origin, CstTy Amount 7581/// Inst = trunc Shift to Ty2 7582/// 7583/// Then, it will be rewriten into: 7584/// Slice = load SliceTy, Base + SliceOffset 7585/// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2 7586/// 7587/// SliceTy is deduced from the number of bits that are actually used to 7588/// build Inst. 7589struct LoadedSlice { 7590 /// \brief Helper structure used to compute the cost of a slice. 7591 struct Cost { 7592 /// Are we optimizing for code size. 7593 bool ForCodeSize; 7594 /// Various cost. 7595 unsigned Loads; 7596 unsigned Truncates; 7597 unsigned CrossRegisterBanksCopies; 7598 unsigned ZExts; 7599 unsigned Shift; 7600 7601 Cost(bool ForCodeSize = false) 7602 : ForCodeSize(ForCodeSize), Loads(0), Truncates(0), 7603 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {} 7604 7605 /// \brief Get the cost of one isolated slice. 7606 Cost(const LoadedSlice &LS, bool ForCodeSize = false) 7607 : ForCodeSize(ForCodeSize), Loads(1), Truncates(0), 7608 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) { 7609 EVT TruncType = LS.Inst->getValueType(0); 7610 EVT LoadedType = LS.getLoadedType(); 7611 if (TruncType != LoadedType && 7612 !LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType)) 7613 ZExts = 1; 7614 } 7615 7616 /// \brief Account for slicing gain in the current cost. 7617 /// Slicing provide a few gains like removing a shift or a 7618 /// truncate. This method allows to grow the cost of the original 7619 /// load with the gain from this slice. 7620 void addSliceGain(const LoadedSlice &LS) { 7621 // Each slice saves a truncate. 7622 const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo(); 7623 if (!TLI.isTruncateFree(LS.Inst->getValueType(0), 7624 LS.Inst->getOperand(0).getValueType())) 7625 ++Truncates; 7626 // If there is a shift amount, this slice gets rid of it. 7627 if (LS.Shift) 7628 ++Shift; 7629 // If this slice can merge a cross register bank copy, account for it. 7630 if (LS.canMergeExpensiveCrossRegisterBankCopy()) 7631 ++CrossRegisterBanksCopies; 7632 } 7633 7634 Cost &operator+=(const Cost &RHS) { 7635 Loads += RHS.Loads; 7636 Truncates += RHS.Truncates; 7637 CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies; 7638 ZExts += RHS.ZExts; 7639 Shift += RHS.Shift; 7640 return *this; 7641 } 7642 7643 bool operator==(const Cost &RHS) const { 7644 return Loads == RHS.Loads && Truncates == RHS.Truncates && 7645 CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies && 7646 ZExts == RHS.ZExts && Shift == RHS.Shift; 7647 } 7648 7649 bool operator!=(const Cost &RHS) const { return !(*this == RHS); } 7650 7651 bool operator<(const Cost &RHS) const { 7652 // Assume cross register banks copies are as expensive as loads. 7653 // FIXME: Do we want some more target hooks? 7654 unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies; 7655 unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies; 7656 // Unless we are optimizing for code size, consider the 7657 // expensive operation first. 7658 if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS) 7659 return ExpensiveOpsLHS < ExpensiveOpsRHS; 7660 return (Truncates + ZExts + Shift + ExpensiveOpsLHS) < 7661 (RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS); 7662 } 7663 7664 bool operator>(const Cost &RHS) const { return RHS < *this; } 7665 7666 bool operator<=(const Cost &RHS) const { return !(RHS < *this); } 7667 7668 bool operator>=(const Cost &RHS) const { return !(*this < RHS); } 7669 }; 7670 // The last instruction that represent the slice. This should be a 7671 // truncate instruction. 7672 SDNode *Inst; 7673 // The original load instruction. 7674 LoadSDNode *Origin; 7675 // The right shift amount in bits from the original load. 7676 unsigned Shift; 7677 // The DAG from which Origin came from. 7678 // This is used to get some contextual information about legal types, etc. 7679 SelectionDAG *DAG; 7680 7681 LoadedSlice(SDNode *Inst = NULL, LoadSDNode *Origin = NULL, 7682 unsigned Shift = 0, SelectionDAG *DAG = NULL) 7683 : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {} 7684 7685 LoadedSlice(const LoadedSlice &LS) 7686 : Inst(LS.Inst), Origin(LS.Origin), Shift(LS.Shift), DAG(LS.DAG) {} 7687 7688 /// \brief Get the bits used in a chunk of bits \p BitWidth large. 7689 /// \return Result is \p BitWidth and has used bits set to 1 and 7690 /// not used bits set to 0. 7691 APInt getUsedBits() const { 7692 // Reproduce the trunc(lshr) sequence: 7693 // - Start from the truncated value. 7694 // - Zero extend to the desired bit width. 7695 // - Shift left. 7696 assert(Origin && "No original load to compare against."); 7697 unsigned BitWidth = Origin->getValueSizeInBits(0); 7698 assert(Inst && "This slice is not bound to an instruction"); 7699 assert(Inst->getValueSizeInBits(0) <= BitWidth && 7700 "Extracted slice is bigger than the whole type!"); 7701 APInt UsedBits(Inst->getValueSizeInBits(0), 0); 7702 UsedBits.setAllBits(); 7703 UsedBits = UsedBits.zext(BitWidth); 7704 UsedBits <<= Shift; 7705 return UsedBits; 7706 } 7707 7708 /// \brief Get the size of the slice to be loaded in bytes. 7709 unsigned getLoadedSize() const { 7710 unsigned SliceSize = getUsedBits().countPopulation(); 7711 assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte."); 7712 return SliceSize / 8; 7713 } 7714 7715 /// \brief Get the type that will be loaded for this slice. 7716 /// Note: This may not be the final type for the slice. 7717 EVT getLoadedType() const { 7718 assert(DAG && "Missing context"); 7719 LLVMContext &Ctxt = *DAG->getContext(); 7720 return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8); 7721 } 7722 7723 /// \brief Get the alignment of the load used for this slice. 7724 unsigned getAlignment() const { 7725 unsigned Alignment = Origin->getAlignment(); 7726 unsigned Offset = getOffsetFromBase(); 7727 if (Offset != 0) 7728 Alignment = MinAlign(Alignment, Alignment + Offset); 7729 return Alignment; 7730 } 7731 7732 /// \brief Check if this slice can be rewritten with legal operations. 7733 bool isLegal() const { 7734 // An invalid slice is not legal. 7735 if (!Origin || !Inst || !DAG) 7736 return false; 7737 7738 // Offsets are for indexed load only, we do not handle that. 7739 if (Origin->getOffset().getOpcode() != ISD::UNDEF) 7740 return false; 7741 7742 const TargetLowering &TLI = DAG->getTargetLoweringInfo(); 7743 7744 // Check that the type is legal. 7745 EVT SliceType = getLoadedType(); 7746 if (!TLI.isTypeLegal(SliceType)) 7747 return false; 7748 7749 // Check that the load is legal for this type. 7750 if (!TLI.isOperationLegal(ISD::LOAD, SliceType)) 7751 return false; 7752 7753 // Check that the offset can be computed. 7754 // 1. Check its type. 7755 EVT PtrType = Origin->getBasePtr().getValueType(); 7756 if (PtrType == MVT::Untyped || PtrType.isExtended()) 7757 return false; 7758 7759 // 2. Check that it fits in the immediate. 7760 if (!TLI.isLegalAddImmediate(getOffsetFromBase())) 7761 return false; 7762 7763 // 3. Check that the computation is legal. 7764 if (!TLI.isOperationLegal(ISD::ADD, PtrType)) 7765 return false; 7766 7767 // Check that the zext is legal if it needs one. 7768 EVT TruncateType = Inst->getValueType(0); 7769 if (TruncateType != SliceType && 7770 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType)) 7771 return false; 7772 7773 return true; 7774 } 7775 7776 /// \brief Get the offset in bytes of this slice in the original chunk of 7777 /// bits. 7778 /// \pre DAG != NULL. 7779 uint64_t getOffsetFromBase() const { 7780 assert(DAG && "Missing context."); 7781 bool IsBigEndian = 7782 DAG->getTargetLoweringInfo().getDataLayout()->isBigEndian(); 7783 assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported."); 7784 uint64_t Offset = Shift / 8; 7785 unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8; 7786 assert(!(Origin->getValueSizeInBits(0) & 0x7) && 7787 "The size of the original loaded type is not a multiple of a" 7788 " byte."); 7789 // If Offset is bigger than TySizeInBytes, it means we are loading all 7790 // zeros. This should have been optimized before in the process. 7791 assert(TySizeInBytes > Offset && 7792 "Invalid shift amount for given loaded size"); 7793 if (IsBigEndian) 7794 Offset = TySizeInBytes - Offset - getLoadedSize(); 7795 return Offset; 7796 } 7797 7798 /// \brief Generate the sequence of instructions to load the slice 7799 /// represented by this object and redirect the uses of this slice to 7800 /// this new sequence of instructions. 7801 /// \pre this->Inst && this->Origin are valid Instructions and this 7802 /// object passed the legal check: LoadedSlice::isLegal returned true. 7803 /// \return The last instruction of the sequence used to load the slice. 7804 SDValue loadSlice() const { 7805 assert(Inst && Origin && "Unable to replace a non-existing slice."); 7806 const SDValue &OldBaseAddr = Origin->getBasePtr(); 7807 SDValue BaseAddr = OldBaseAddr; 7808 // Get the offset in that chunk of bytes w.r.t. the endianess. 7809 int64_t Offset = static_cast<int64_t>(getOffsetFromBase()); 7810 assert(Offset >= 0 && "Offset too big to fit in int64_t!"); 7811 if (Offset) { 7812 // BaseAddr = BaseAddr + Offset. 7813 EVT ArithType = BaseAddr.getValueType(); 7814 BaseAddr = DAG->getNode(ISD::ADD, SDLoc(Origin), ArithType, BaseAddr, 7815 DAG->getConstant(Offset, ArithType)); 7816 } 7817 7818 // Create the type of the loaded slice according to its size. 7819 EVT SliceType = getLoadedType(); 7820 7821 // Create the load for the slice. 7822 SDValue LastInst = DAG->getLoad( 7823 SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr, 7824 Origin->getPointerInfo().getWithOffset(Offset), Origin->isVolatile(), 7825 Origin->isNonTemporal(), Origin->isInvariant(), getAlignment()); 7826 // If the final type is not the same as the loaded type, this means that 7827 // we have to pad with zero. Create a zero extend for that. 7828 EVT FinalType = Inst->getValueType(0); 7829 if (SliceType != FinalType) 7830 LastInst = 7831 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst); 7832 return LastInst; 7833 } 7834 7835 /// \brief Check if this slice can be merged with an expensive cross register 7836 /// bank copy. E.g., 7837 /// i = load i32 7838 /// f = bitcast i32 i to float 7839 bool canMergeExpensiveCrossRegisterBankCopy() const { 7840 if (!Inst || !Inst->hasOneUse()) 7841 return false; 7842 SDNode *Use = *Inst->use_begin(); 7843 if (Use->getOpcode() != ISD::BITCAST) 7844 return false; 7845 assert(DAG && "Missing context"); 7846 const TargetLowering &TLI = DAG->getTargetLoweringInfo(); 7847 EVT ResVT = Use->getValueType(0); 7848 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT()); 7849 const TargetRegisterClass *ArgRC = 7850 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT()); 7851 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) 7852 return false; 7853 7854 // At this point, we know that we perform a cross-register-bank copy. 7855 // Check if it is expensive. 7856 const TargetRegisterInfo *TRI = TLI.getTargetMachine().getRegisterInfo(); 7857 // Assume bitcasts are cheap, unless both register classes do not 7858 // explicitly share a common sub class. 7859 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC)) 7860 return false; 7861 7862 // Check if it will be merged with the load. 7863 // 1. Check the alignment constraint. 7864 unsigned RequiredAlignment = TLI.getDataLayout()->getABITypeAlignment( 7865 ResVT.getTypeForEVT(*DAG->getContext())); 7866 7867 if (RequiredAlignment > getAlignment()) 7868 return false; 7869 7870 // 2. Check that the load is a legal operation for that type. 7871 if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) 7872 return false; 7873 7874 // 3. Check that we do not have a zext in the way. 7875 if (Inst->getValueType(0) != getLoadedType()) 7876 return false; 7877 7878 return true; 7879 } 7880}; 7881} 7882 7883/// \brief Sorts LoadedSlice according to their offset. 7884struct LoadedSliceSorter { 7885 bool operator()(const LoadedSlice &LHS, const LoadedSlice &RHS) { 7886 assert(LHS.Origin == RHS.Origin && "Different bases not implemented."); 7887 return LHS.getOffsetFromBase() < RHS.getOffsetFromBase(); 7888 } 7889}; 7890 7891/// \brief Check that all bits set in \p UsedBits form a dense region, i.e., 7892/// \p UsedBits looks like 0..0 1..1 0..0. 7893static bool areUsedBitsDense(const APInt &UsedBits) { 7894 // If all the bits are one, this is dense! 7895 if (UsedBits.isAllOnesValue()) 7896 return true; 7897 7898 // Get rid of the unused bits on the right. 7899 APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros()); 7900 // Get rid of the unused bits on the left. 7901 if (NarrowedUsedBits.countLeadingZeros()) 7902 NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits()); 7903 // Check that the chunk of bits is completely used. 7904 return NarrowedUsedBits.isAllOnesValue(); 7905} 7906 7907/// \brief Check whether or not \p First and \p Second are next to each other 7908/// in memory. This means that there is no hole between the bits loaded 7909/// by \p First and the bits loaded by \p Second. 7910static bool areSlicesNextToEachOther(const LoadedSlice &First, 7911 const LoadedSlice &Second) { 7912 assert(First.Origin == Second.Origin && First.Origin && 7913 "Unable to match different memory origins."); 7914 APInt UsedBits = First.getUsedBits(); 7915 assert((UsedBits & Second.getUsedBits()) == 0 && 7916 "Slices are not supposed to overlap."); 7917 UsedBits |= Second.getUsedBits(); 7918 return areUsedBitsDense(UsedBits); 7919} 7920 7921/// \brief Adjust the \p GlobalLSCost according to the target 7922/// paring capabilities and the layout of the slices. 7923/// \pre \p GlobalLSCost should account for at least as many loads as 7924/// there is in the slices in \p LoadedSlices. 7925static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices, 7926 LoadedSlice::Cost &GlobalLSCost) { 7927 unsigned NumberOfSlices = LoadedSlices.size(); 7928 // If there is less than 2 elements, no pairing is possible. 7929 if (NumberOfSlices < 2) 7930 return; 7931 7932 // Sort the slices so that elements that are likely to be next to each 7933 // other in memory are next to each other in the list. 7934 std::sort(LoadedSlices.begin(), LoadedSlices.end(), LoadedSliceSorter()); 7935 const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo(); 7936 // First (resp. Second) is the first (resp. Second) potentially candidate 7937 // to be placed in a paired load. 7938 const LoadedSlice *First = NULL; 7939 const LoadedSlice *Second = NULL; 7940 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice, 7941 // Set the beginning of the pair. 7942 First = Second) { 7943 7944 Second = &LoadedSlices[CurrSlice]; 7945 7946 // If First is NULL, it means we start a new pair. 7947 // Get to the next slice. 7948 if (!First) 7949 continue; 7950 7951 EVT LoadedType = First->getLoadedType(); 7952 7953 // If the types of the slices are different, we cannot pair them. 7954 if (LoadedType != Second->getLoadedType()) 7955 continue; 7956 7957 // Check if the target supplies paired loads for this type. 7958 unsigned RequiredAlignment = 0; 7959 if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) { 7960 // move to the next pair, this type is hopeless. 7961 Second = NULL; 7962 continue; 7963 } 7964 // Check if we meet the alignment requirement. 7965 if (RequiredAlignment > First->getAlignment()) 7966 continue; 7967 7968 // Check that both loads are next to each other in memory. 7969 if (!areSlicesNextToEachOther(*First, *Second)) 7970 continue; 7971 7972 assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!"); 7973 --GlobalLSCost.Loads; 7974 // Move to the next pair. 7975 Second = NULL; 7976 } 7977} 7978 7979/// \brief Check the profitability of all involved LoadedSlice. 7980/// Currently, it is considered profitable if there is exactly two 7981/// involved slices (1) which are (2) next to each other in memory, and 7982/// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3). 7983/// 7984/// Note: The order of the elements in \p LoadedSlices may be modified, but not 7985/// the elements themselves. 7986/// 7987/// FIXME: When the cost model will be mature enough, we can relax 7988/// constraints (1) and (2). 7989static bool isSlicingProfitable(SmallVectorImpl<LoadedSlice> &LoadedSlices, 7990 const APInt &UsedBits, bool ForCodeSize) { 7991 unsigned NumberOfSlices = LoadedSlices.size(); 7992 if (StressLoadSlicing) 7993 return NumberOfSlices > 1; 7994 7995 // Check (1). 7996 if (NumberOfSlices != 2) 7997 return false; 7998 7999 // Check (2). 8000 if (!areUsedBitsDense(UsedBits)) 8001 return false; 8002 8003 // Check (3). 8004 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize); 8005 // The original code has one big load. 8006 OrigCost.Loads = 1; 8007 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) { 8008 const LoadedSlice &LS = LoadedSlices[CurrSlice]; 8009 // Accumulate the cost of all the slices. 8010 LoadedSlice::Cost SliceCost(LS, ForCodeSize); 8011 GlobalSlicingCost += SliceCost; 8012 8013 // Account as cost in the original configuration the gain obtained 8014 // with the current slices. 8015 OrigCost.addSliceGain(LS); 8016 } 8017 8018 // If the target supports paired load, adjust the cost accordingly. 8019 adjustCostForPairing(LoadedSlices, GlobalSlicingCost); 8020 return OrigCost > GlobalSlicingCost; 8021} 8022 8023/// \brief If the given load, \p LI, is used only by trunc or trunc(lshr) 8024/// operations, split it in the various pieces being extracted. 8025/// 8026/// This sort of thing is introduced by SROA. 8027/// This slicing takes care not to insert overlapping loads. 8028/// \pre LI is a simple load (i.e., not an atomic or volatile load). 8029bool DAGCombiner::SliceUpLoad(SDNode *N) { 8030 if (Level < AfterLegalizeDAG) 8031 return false; 8032 8033 LoadSDNode *LD = cast<LoadSDNode>(N); 8034 if (LD->isVolatile() || !ISD::isNormalLoad(LD) || 8035 !LD->getValueType(0).isInteger()) 8036 return false; 8037 8038 // Keep track of already used bits to detect overlapping values. 8039 // In that case, we will just abort the transformation. 8040 APInt UsedBits(LD->getValueSizeInBits(0), 0); 8041 8042 SmallVector<LoadedSlice, 4> LoadedSlices; 8043 8044 // Check if this load is used as several smaller chunks of bits. 8045 // Basically, look for uses in trunc or trunc(lshr) and record a new chain 8046 // of computation for each trunc. 8047 for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end(); 8048 UI != UIEnd; ++UI) { 8049 // Skip the uses of the chain. 8050 if (UI.getUse().getResNo() != 0) 8051 continue; 8052 8053 SDNode *User = *UI; 8054 unsigned Shift = 0; 8055 8056 // Check if this is a trunc(lshr). 8057 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && 8058 isa<ConstantSDNode>(User->getOperand(1))) { 8059 Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue(); 8060 User = *User->use_begin(); 8061 } 8062 8063 // At this point, User is a Truncate, iff we encountered, trunc or 8064 // trunc(lshr). 8065 if (User->getOpcode() != ISD::TRUNCATE) 8066 return false; 8067 8068 // The width of the type must be a power of 2 and greater than 8-bits. 8069 // Otherwise the load cannot be represented in LLVM IR. 8070 // Moreover, if we shifted with a non 8-bits multiple, the slice 8071 // will be accross several bytes. We do not support that. 8072 unsigned Width = User->getValueSizeInBits(0); 8073 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7)) 8074 return 0; 8075 8076 // Build the slice for this chain of computations. 8077 LoadedSlice LS(User, LD, Shift, &DAG); 8078 APInt CurrentUsedBits = LS.getUsedBits(); 8079 8080 // Check if this slice overlaps with another. 8081 if ((CurrentUsedBits & UsedBits) != 0) 8082 return false; 8083 // Update the bits used globally. 8084 UsedBits |= CurrentUsedBits; 8085 8086 // Check if the new slice would be legal. 8087 if (!LS.isLegal()) 8088 return false; 8089 8090 // Record the slice. 8091 LoadedSlices.push_back(LS); 8092 } 8093 8094 // Abort slicing if it does not seem to be profitable. 8095 if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize)) 8096 return false; 8097 8098 ++SlicedLoads; 8099 8100 // Rewrite each chain to use an independent load. 8101 // By construction, each chain can be represented by a unique load. 8102 8103 // Prepare the argument for the new token factor for all the slices. 8104 SmallVector<SDValue, 8> ArgChains; 8105 for (SmallVectorImpl<LoadedSlice>::const_iterator 8106 LSIt = LoadedSlices.begin(), 8107 LSItEnd = LoadedSlices.end(); 8108 LSIt != LSItEnd; ++LSIt) { 8109 SDValue SliceInst = LSIt->loadSlice(); 8110 CombineTo(LSIt->Inst, SliceInst, true); 8111 if (SliceInst.getNode()->getOpcode() != ISD::LOAD) 8112 SliceInst = SliceInst.getOperand(0); 8113 assert(SliceInst->getOpcode() == ISD::LOAD && 8114 "It takes more than a zext to get to the loaded slice!!"); 8115 ArgChains.push_back(SliceInst.getValue(1)); 8116 } 8117 8118 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, 8119 &ArgChains[0], ArgChains.size()); 8120 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 8121 return true; 8122} 8123 8124/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 8125/// load is having specific bytes cleared out. If so, return the byte size 8126/// being masked out and the shift amount. 8127static std::pair<unsigned, unsigned> 8128CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 8129 std::pair<unsigned, unsigned> Result(0, 0); 8130 8131 // Check for the structure we're looking for. 8132 if (V->getOpcode() != ISD::AND || 8133 !isa<ConstantSDNode>(V->getOperand(1)) || 8134 !ISD::isNormalLoad(V->getOperand(0).getNode())) 8135 return Result; 8136 8137 // Check the chain and pointer. 8138 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 8139 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 8140 8141 // The store should be chained directly to the load or be an operand of a 8142 // tokenfactor. 8143 if (LD == Chain.getNode()) 8144 ; // ok. 8145 else if (Chain->getOpcode() != ISD::TokenFactor) 8146 return Result; // Fail. 8147 else { 8148 bool isOk = false; 8149 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 8150 if (Chain->getOperand(i).getNode() == LD) { 8151 isOk = true; 8152 break; 8153 } 8154 if (!isOk) return Result; 8155 } 8156 8157 // This only handles simple types. 8158 if (V.getValueType() != MVT::i16 && 8159 V.getValueType() != MVT::i32 && 8160 V.getValueType() != MVT::i64) 8161 return Result; 8162 8163 // Check the constant mask. Invert it so that the bits being masked out are 8164 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 8165 // follow the sign bit for uniformity. 8166 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 8167 unsigned NotMaskLZ = countLeadingZeros(NotMask); 8168 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 8169 unsigned NotMaskTZ = countTrailingZeros(NotMask); 8170 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 8171 if (NotMaskLZ == 64) return Result; // All zero mask. 8172 8173 // See if we have a continuous run of bits. If so, we have 0*1+0* 8174 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 8175 return Result; 8176 8177 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 8178 if (V.getValueType() != MVT::i64 && NotMaskLZ) 8179 NotMaskLZ -= 64-V.getValueSizeInBits(); 8180 8181 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 8182 switch (MaskedBytes) { 8183 case 1: 8184 case 2: 8185 case 4: break; 8186 default: return Result; // All one mask, or 5-byte mask. 8187 } 8188 8189 // Verify that the first bit starts at a multiple of mask so that the access 8190 // is aligned the same as the access width. 8191 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 8192 8193 Result.first = MaskedBytes; 8194 Result.second = NotMaskTZ/8; 8195 return Result; 8196} 8197 8198 8199/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 8200/// provides a value as specified by MaskInfo. If so, replace the specified 8201/// store with a narrower store of truncated IVal. 8202static SDNode * 8203ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 8204 SDValue IVal, StoreSDNode *St, 8205 DAGCombiner *DC) { 8206 unsigned NumBytes = MaskInfo.first; 8207 unsigned ByteShift = MaskInfo.second; 8208 SelectionDAG &DAG = DC->getDAG(); 8209 8210 // Check to see if IVal is all zeros in the part being masked in by the 'or' 8211 // that uses this. If not, this is not a replacement. 8212 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 8213 ByteShift*8, (ByteShift+NumBytes)*8); 8214 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 8215 8216 // Check that it is legal on the target to do this. It is legal if the new 8217 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 8218 // legalization. 8219 MVT VT = MVT::getIntegerVT(NumBytes*8); 8220 if (!DC->isTypeLegal(VT)) 8221 return 0; 8222 8223 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 8224 // shifted by ByteShift and truncated down to NumBytes. 8225 if (ByteShift) 8226 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal, 8227 DAG.getConstant(ByteShift*8, 8228 DC->getShiftAmountTy(IVal.getValueType()))); 8229 8230 // Figure out the offset for the store and the alignment of the access. 8231 unsigned StOffset; 8232 unsigned NewAlign = St->getAlignment(); 8233 8234 if (DAG.getTargetLoweringInfo().isLittleEndian()) 8235 StOffset = ByteShift; 8236 else 8237 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 8238 8239 SDValue Ptr = St->getBasePtr(); 8240 if (StOffset) { 8241 Ptr = DAG.getNode(ISD::ADD, SDLoc(IVal), Ptr.getValueType(), 8242 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 8243 NewAlign = MinAlign(NewAlign, StOffset); 8244 } 8245 8246 // Truncate down to the new size. 8247 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal); 8248 8249 ++OpsNarrowed; 8250 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr, 8251 St->getPointerInfo().getWithOffset(StOffset), 8252 false, false, NewAlign).getNode(); 8253} 8254 8255 8256/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 8257/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 8258/// of the loaded bits, try narrowing the load and store if it would end up 8259/// being a win for performance or code size. 8260SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 8261 StoreSDNode *ST = cast<StoreSDNode>(N); 8262 if (ST->isVolatile()) 8263 return SDValue(); 8264 8265 SDValue Chain = ST->getChain(); 8266 SDValue Value = ST->getValue(); 8267 SDValue Ptr = ST->getBasePtr(); 8268 EVT VT = Value.getValueType(); 8269 8270 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 8271 return SDValue(); 8272 8273 unsigned Opc = Value.getOpcode(); 8274 8275 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 8276 // is a byte mask indicating a consecutive number of bytes, check to see if 8277 // Y is known to provide just those bytes. If so, we try to replace the 8278 // load + replace + store sequence with a single (narrower) store, which makes 8279 // the load dead. 8280 if (Opc == ISD::OR) { 8281 std::pair<unsigned, unsigned> MaskedLoad; 8282 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 8283 if (MaskedLoad.first) 8284 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 8285 Value.getOperand(1), ST,this)) 8286 return SDValue(NewST, 0); 8287 8288 // Or is commutative, so try swapping X and Y. 8289 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 8290 if (MaskedLoad.first) 8291 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 8292 Value.getOperand(0), ST,this)) 8293 return SDValue(NewST, 0); 8294 } 8295 8296 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 8297 Value.getOperand(1).getOpcode() != ISD::Constant) 8298 return SDValue(); 8299 8300 SDValue N0 = Value.getOperand(0); 8301 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 8302 Chain == SDValue(N0.getNode(), 1)) { 8303 LoadSDNode *LD = cast<LoadSDNode>(N0); 8304 if (LD->getBasePtr() != Ptr || 8305 LD->getPointerInfo().getAddrSpace() != 8306 ST->getPointerInfo().getAddrSpace()) 8307 return SDValue(); 8308 8309 // Find the type to narrow it the load / op / store to. 8310 SDValue N1 = Value.getOperand(1); 8311 unsigned BitWidth = N1.getValueSizeInBits(); 8312 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 8313 if (Opc == ISD::AND) 8314 Imm ^= APInt::getAllOnesValue(BitWidth); 8315 if (Imm == 0 || Imm.isAllOnesValue()) 8316 return SDValue(); 8317 unsigned ShAmt = Imm.countTrailingZeros(); 8318 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 8319 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 8320 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 8321 while (NewBW < BitWidth && 8322 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 8323 TLI.isNarrowingProfitable(VT, NewVT))) { 8324 NewBW = NextPowerOf2(NewBW); 8325 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 8326 } 8327 if (NewBW >= BitWidth) 8328 return SDValue(); 8329 8330 // If the lsb changed does not start at the type bitwidth boundary, 8331 // start at the previous one. 8332 if (ShAmt % NewBW) 8333 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 8334 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, 8335 std::min(BitWidth, ShAmt + NewBW)); 8336 if ((Imm & Mask) == Imm) { 8337 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 8338 if (Opc == ISD::AND) 8339 NewImm ^= APInt::getAllOnesValue(NewBW); 8340 uint64_t PtrOff = ShAmt / 8; 8341 // For big endian targets, we need to adjust the offset to the pointer to 8342 // load the correct bytes. 8343 if (TLI.isBigEndian()) 8344 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 8345 8346 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 8347 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 8348 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy)) 8349 return SDValue(); 8350 8351 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD), 8352 Ptr.getValueType(), Ptr, 8353 DAG.getConstant(PtrOff, Ptr.getValueType())); 8354 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0), 8355 LD->getChain(), NewPtr, 8356 LD->getPointerInfo().getWithOffset(PtrOff), 8357 LD->isVolatile(), LD->isNonTemporal(), 8358 LD->isInvariant(), NewAlign, 8359 LD->getTBAAInfo()); 8360 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD, 8361 DAG.getConstant(NewImm, NewVT)); 8362 SDValue NewST = DAG.getStore(Chain, SDLoc(N), 8363 NewVal, NewPtr, 8364 ST->getPointerInfo().getWithOffset(PtrOff), 8365 false, false, NewAlign); 8366 8367 AddToWorkList(NewPtr.getNode()); 8368 AddToWorkList(NewLD.getNode()); 8369 AddToWorkList(NewVal.getNode()); 8370 WorkListRemover DeadNodes(*this); 8371 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 8372 ++OpsNarrowed; 8373 return NewST; 8374 } 8375 } 8376 8377 return SDValue(); 8378} 8379 8380/// TransformFPLoadStorePair - For a given floating point load / store pair, 8381/// if the load value isn't used by any other operations, then consider 8382/// transforming the pair to integer load / store operations if the target 8383/// deems the transformation profitable. 8384SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 8385 StoreSDNode *ST = cast<StoreSDNode>(N); 8386 SDValue Chain = ST->getChain(); 8387 SDValue Value = ST->getValue(); 8388 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 8389 Value.hasOneUse() && 8390 Chain == SDValue(Value.getNode(), 1)) { 8391 LoadSDNode *LD = cast<LoadSDNode>(Value); 8392 EVT VT = LD->getMemoryVT(); 8393 if (!VT.isFloatingPoint() || 8394 VT != ST->getMemoryVT() || 8395 LD->isNonTemporal() || 8396 ST->isNonTemporal() || 8397 LD->getPointerInfo().getAddrSpace() != 0 || 8398 ST->getPointerInfo().getAddrSpace() != 0) 8399 return SDValue(); 8400 8401 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 8402 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 8403 !TLI.isOperationLegal(ISD::STORE, IntVT) || 8404 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 8405 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 8406 return SDValue(); 8407 8408 unsigned LDAlign = LD->getAlignment(); 8409 unsigned STAlign = ST->getAlignment(); 8410 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 8411 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy); 8412 if (LDAlign < ABIAlign || STAlign < ABIAlign) 8413 return SDValue(); 8414 8415 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value), 8416 LD->getChain(), LD->getBasePtr(), 8417 LD->getPointerInfo(), 8418 false, false, false, LDAlign); 8419 8420 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N), 8421 NewLD, ST->getBasePtr(), 8422 ST->getPointerInfo(), 8423 false, false, STAlign); 8424 8425 AddToWorkList(NewLD.getNode()); 8426 AddToWorkList(NewST.getNode()); 8427 WorkListRemover DeadNodes(*this); 8428 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 8429 ++LdStFP2Int; 8430 return NewST; 8431 } 8432 8433 return SDValue(); 8434} 8435 8436/// Helper struct to parse and store a memory address as base + index + offset. 8437/// We ignore sign extensions when it is safe to do so. 8438/// The following two expressions are not equivalent. To differentiate we need 8439/// to store whether there was a sign extension involved in the index 8440/// computation. 8441/// (load (i64 add (i64 copyfromreg %c) 8442/// (i64 signextend (add (i8 load %index) 8443/// (i8 1)))) 8444/// vs 8445/// 8446/// (load (i64 add (i64 copyfromreg %c) 8447/// (i64 signextend (i32 add (i32 signextend (i8 load %index)) 8448/// (i32 1))))) 8449struct BaseIndexOffset { 8450 SDValue Base; 8451 SDValue Index; 8452 int64_t Offset; 8453 bool IsIndexSignExt; 8454 8455 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {} 8456 8457 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset, 8458 bool IsIndexSignExt) : 8459 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {} 8460 8461 bool equalBaseIndex(const BaseIndexOffset &Other) { 8462 return Other.Base == Base && Other.Index == Index && 8463 Other.IsIndexSignExt == IsIndexSignExt; 8464 } 8465 8466 /// Parses tree in Ptr for base, index, offset addresses. 8467 static BaseIndexOffset match(SDValue Ptr) { 8468 bool IsIndexSignExt = false; 8469 8470 // We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD 8471 // instruction, then it could be just the BASE or everything else we don't 8472 // know how to handle. Just use Ptr as BASE and give up. 8473 if (Ptr->getOpcode() != ISD::ADD) 8474 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt); 8475 8476 // We know that we have at least an ADD instruction. Try to pattern match 8477 // the simple case of BASE + OFFSET. 8478 if (isa<ConstantSDNode>(Ptr->getOperand(1))) { 8479 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue(); 8480 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset, 8481 IsIndexSignExt); 8482 } 8483 8484 // Inside a loop the current BASE pointer is calculated using an ADD and a 8485 // MUL instruction. In this case Ptr is the actual BASE pointer. 8486 // (i64 add (i64 %array_ptr) 8487 // (i64 mul (i64 %induction_var) 8488 // (i64 %element_size))) 8489 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL) 8490 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt); 8491 8492 // Look at Base + Index + Offset cases. 8493 SDValue Base = Ptr->getOperand(0); 8494 SDValue IndexOffset = Ptr->getOperand(1); 8495 8496 // Skip signextends. 8497 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) { 8498 IndexOffset = IndexOffset->getOperand(0); 8499 IsIndexSignExt = true; 8500 } 8501 8502 // Either the case of Base + Index (no offset) or something else. 8503 if (IndexOffset->getOpcode() != ISD::ADD) 8504 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt); 8505 8506 // Now we have the case of Base + Index + offset. 8507 SDValue Index = IndexOffset->getOperand(0); 8508 SDValue Offset = IndexOffset->getOperand(1); 8509 8510 if (!isa<ConstantSDNode>(Offset)) 8511 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt); 8512 8513 // Ignore signextends. 8514 if (Index->getOpcode() == ISD::SIGN_EXTEND) { 8515 Index = Index->getOperand(0); 8516 IsIndexSignExt = true; 8517 } else IsIndexSignExt = false; 8518 8519 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue(); 8520 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt); 8521 } 8522}; 8523 8524/// Holds a pointer to an LSBaseSDNode as well as information on where it 8525/// is located in a sequence of memory operations connected by a chain. 8526struct MemOpLink { 8527 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq): 8528 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { } 8529 // Ptr to the mem node. 8530 LSBaseSDNode *MemNode; 8531 // Offset from the base ptr. 8532 int64_t OffsetFromBase; 8533 // What is the sequence number of this mem node. 8534 // Lowest mem operand in the DAG starts at zero. 8535 unsigned SequenceNum; 8536}; 8537 8538/// Sorts store nodes in a link according to their offset from a shared 8539// base ptr. 8540struct ConsecutiveMemoryChainSorter { 8541 bool operator()(MemOpLink LHS, MemOpLink RHS) { 8542 return LHS.OffsetFromBase < RHS.OffsetFromBase; 8543 } 8544}; 8545 8546bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) { 8547 EVT MemVT = St->getMemoryVT(); 8548 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8; 8549 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes(). 8550 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat); 8551 8552 // Don't merge vectors into wider inputs. 8553 if (MemVT.isVector() || !MemVT.isSimple()) 8554 return false; 8555 8556 // Perform an early exit check. Do not bother looking at stored values that 8557 // are not constants or loads. 8558 SDValue StoredVal = St->getValue(); 8559 bool IsLoadSrc = isa<LoadSDNode>(StoredVal); 8560 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) && 8561 !IsLoadSrc) 8562 return false; 8563 8564 // Only look at ends of store sequences. 8565 SDValue Chain = SDValue(St, 1); 8566 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE) 8567 return false; 8568 8569 // This holds the base pointer, index, and the offset in bytes from the base 8570 // pointer. 8571 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr()); 8572 8573 // We must have a base and an offset. 8574 if (!BasePtr.Base.getNode()) 8575 return false; 8576 8577 // Do not handle stores to undef base pointers. 8578 if (BasePtr.Base.getOpcode() == ISD::UNDEF) 8579 return false; 8580 8581 // Save the LoadSDNodes that we find in the chain. 8582 // We need to make sure that these nodes do not interfere with 8583 // any of the store nodes. 8584 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes; 8585 8586 // Save the StoreSDNodes that we find in the chain. 8587 SmallVector<MemOpLink, 8> StoreNodes; 8588 8589 // Walk up the chain and look for nodes with offsets from the same 8590 // base pointer. Stop when reaching an instruction with a different kind 8591 // or instruction which has a different base pointer. 8592 unsigned Seq = 0; 8593 StoreSDNode *Index = St; 8594 while (Index) { 8595 // If the chain has more than one use, then we can't reorder the mem ops. 8596 if (Index != St && !SDValue(Index, 1)->hasOneUse()) 8597 break; 8598 8599 // Find the base pointer and offset for this memory node. 8600 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr()); 8601 8602 // Check that the base pointer is the same as the original one. 8603 if (!Ptr.equalBaseIndex(BasePtr)) 8604 break; 8605 8606 // Check that the alignment is the same. 8607 if (Index->getAlignment() != St->getAlignment()) 8608 break; 8609 8610 // The memory operands must not be volatile. 8611 if (Index->isVolatile() || Index->isIndexed()) 8612 break; 8613 8614 // No truncation. 8615 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index)) 8616 if (St->isTruncatingStore()) 8617 break; 8618 8619 // The stored memory type must be the same. 8620 if (Index->getMemoryVT() != MemVT) 8621 break; 8622 8623 // We do not allow unaligned stores because we want to prevent overriding 8624 // stores. 8625 if (Index->getAlignment()*8 != MemVT.getSizeInBits()) 8626 break; 8627 8628 // We found a potential memory operand to merge. 8629 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++)); 8630 8631 // Find the next memory operand in the chain. If the next operand in the 8632 // chain is a store then move up and continue the scan with the next 8633 // memory operand. If the next operand is a load save it and use alias 8634 // information to check if it interferes with anything. 8635 SDNode *NextInChain = Index->getChain().getNode(); 8636 while (1) { 8637 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) { 8638 // We found a store node. Use it for the next iteration. 8639 Index = STn; 8640 break; 8641 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) { 8642 // Save the load node for later. Continue the scan. 8643 AliasLoadNodes.push_back(Ldn); 8644 NextInChain = Ldn->getChain().getNode(); 8645 continue; 8646 } else { 8647 Index = NULL; 8648 break; 8649 } 8650 } 8651 } 8652 8653 // Check if there is anything to merge. 8654 if (StoreNodes.size() < 2) 8655 return false; 8656 8657 // Sort the memory operands according to their distance from the base pointer. 8658 std::sort(StoreNodes.begin(), StoreNodes.end(), 8659 ConsecutiveMemoryChainSorter()); 8660 8661 // Scan the memory operations on the chain and find the first non-consecutive 8662 // store memory address. 8663 unsigned LastConsecutiveStore = 0; 8664 int64_t StartAddress = StoreNodes[0].OffsetFromBase; 8665 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) { 8666 8667 // Check that the addresses are consecutive starting from the second 8668 // element in the list of stores. 8669 if (i > 0) { 8670 int64_t CurrAddress = StoreNodes[i].OffsetFromBase; 8671 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 8672 break; 8673 } 8674 8675 bool Alias = false; 8676 // Check if this store interferes with any of the loads that we found. 8677 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld) 8678 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) { 8679 Alias = true; 8680 break; 8681 } 8682 // We found a load that alias with this store. Stop the sequence. 8683 if (Alias) 8684 break; 8685 8686 // Mark this node as useful. 8687 LastConsecutiveStore = i; 8688 } 8689 8690 // The node with the lowest store address. 8691 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; 8692 8693 // Store the constants into memory as one consecutive store. 8694 if (!IsLoadSrc) { 8695 unsigned LastLegalType = 0; 8696 unsigned LastLegalVectorType = 0; 8697 bool NonZero = false; 8698 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 8699 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8700 SDValue StoredVal = St->getValue(); 8701 8702 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) { 8703 NonZero |= !C->isNullValue(); 8704 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) { 8705 NonZero |= !C->getConstantFPValue()->isNullValue(); 8706 } else { 8707 // Non constant. 8708 break; 8709 } 8710 8711 // Find a legal type for the constant store. 8712 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 8713 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 8714 if (TLI.isTypeLegal(StoreTy)) 8715 LastLegalType = i+1; 8716 // Or check whether a truncstore is legal. 8717 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) == 8718 TargetLowering::TypePromoteInteger) { 8719 EVT LegalizedStoredValueTy = 8720 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType()); 8721 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy)) 8722 LastLegalType = i+1; 8723 } 8724 8725 // Find a legal type for the vector store. 8726 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 8727 if (TLI.isTypeLegal(Ty)) 8728 LastLegalVectorType = i + 1; 8729 } 8730 8731 // We only use vectors if the constant is known to be zero and the 8732 // function is not marked with the noimplicitfloat attribute. 8733 if (NonZero || NoVectors) 8734 LastLegalVectorType = 0; 8735 8736 // Check if we found a legal integer type to store. 8737 if (LastLegalType == 0 && LastLegalVectorType == 0) 8738 return false; 8739 8740 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors; 8741 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType; 8742 8743 // Make sure we have something to merge. 8744 if (NumElem < 2) 8745 return false; 8746 8747 unsigned EarliestNodeUsed = 0; 8748 for (unsigned i=0; i < NumElem; ++i) { 8749 // Find a chain for the new wide-store operand. Notice that some 8750 // of the store nodes that we found may not be selected for inclusion 8751 // in the wide store. The chain we use needs to be the chain of the 8752 // earliest store node which is *used* and replaced by the wide store. 8753 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 8754 EarliestNodeUsed = i; 8755 } 8756 8757 // The earliest Node in the DAG. 8758 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 8759 SDLoc DL(StoreNodes[0].MemNode); 8760 8761 SDValue StoredVal; 8762 if (UseVector) { 8763 // Find a legal type for the vector store. 8764 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 8765 assert(TLI.isTypeLegal(Ty) && "Illegal vector store"); 8766 StoredVal = DAG.getConstant(0, Ty); 8767 } else { 8768 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 8769 APInt StoreInt(StoreBW, 0); 8770 8771 // Construct a single integer constant which is made of the smaller 8772 // constant inputs. 8773 bool IsLE = TLI.isLittleEndian(); 8774 for (unsigned i = 0; i < NumElem ; ++i) { 8775 unsigned Idx = IsLE ?(NumElem - 1 - i) : i; 8776 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode); 8777 SDValue Val = St->getValue(); 8778 StoreInt<<=ElementSizeBytes*8; 8779 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) { 8780 StoreInt|=C->getAPIntValue().zext(StoreBW); 8781 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) { 8782 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW); 8783 } else { 8784 assert(false && "Invalid constant element type"); 8785 } 8786 } 8787 8788 // Create the new Load and Store operations. 8789 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 8790 StoredVal = DAG.getConstant(StoreInt, StoreTy); 8791 } 8792 8793 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal, 8794 FirstInChain->getBasePtr(), 8795 FirstInChain->getPointerInfo(), 8796 false, false, 8797 FirstInChain->getAlignment()); 8798 8799 // Replace the first store with the new store 8800 CombineTo(EarliestOp, NewStore); 8801 // Erase all other stores. 8802 for (unsigned i = 0; i < NumElem ; ++i) { 8803 if (StoreNodes[i].MemNode == EarliestOp) 8804 continue; 8805 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8806 // ReplaceAllUsesWith will replace all uses that existed when it was 8807 // called, but graph optimizations may cause new ones to appear. For 8808 // example, the case in pr14333 looks like 8809 // 8810 // St's chain -> St -> another store -> X 8811 // 8812 // And the only difference from St to the other store is the chain. 8813 // When we change it's chain to be St's chain they become identical, 8814 // get CSEed and the net result is that X is now a use of St. 8815 // Since we know that St is redundant, just iterate. 8816 while (!St->use_empty()) 8817 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain()); 8818 removeFromWorkList(St); 8819 DAG.DeleteNode(St); 8820 } 8821 8822 return true; 8823 } 8824 8825 // Below we handle the case of multiple consecutive stores that 8826 // come from multiple consecutive loads. We merge them into a single 8827 // wide load and a single wide store. 8828 8829 // Look for load nodes which are used by the stored values. 8830 SmallVector<MemOpLink, 8> LoadNodes; 8831 8832 // Find acceptable loads. Loads need to have the same chain (token factor), 8833 // must not be zext, volatile, indexed, and they must be consecutive. 8834 BaseIndexOffset LdBasePtr; 8835 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 8836 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8837 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue()); 8838 if (!Ld) break; 8839 8840 // Loads must only have one use. 8841 if (!Ld->hasNUsesOfValue(1, 0)) 8842 break; 8843 8844 // Check that the alignment is the same as the stores. 8845 if (Ld->getAlignment() != St->getAlignment()) 8846 break; 8847 8848 // The memory operands must not be volatile. 8849 if (Ld->isVolatile() || Ld->isIndexed()) 8850 break; 8851 8852 // We do not accept ext loads. 8853 if (Ld->getExtensionType() != ISD::NON_EXTLOAD) 8854 break; 8855 8856 // The stored memory type must be the same. 8857 if (Ld->getMemoryVT() != MemVT) 8858 break; 8859 8860 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr()); 8861 // If this is not the first ptr that we check. 8862 if (LdBasePtr.Base.getNode()) { 8863 // The base ptr must be the same. 8864 if (!LdPtr.equalBaseIndex(LdBasePtr)) 8865 break; 8866 } else { 8867 // Check that all other base pointers are the same as this one. 8868 LdBasePtr = LdPtr; 8869 } 8870 8871 // We found a potential memory operand to merge. 8872 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0)); 8873 } 8874 8875 if (LoadNodes.size() < 2) 8876 return false; 8877 8878 // Scan the memory operations on the chain and find the first non-consecutive 8879 // load memory address. These variables hold the index in the store node 8880 // array. 8881 unsigned LastConsecutiveLoad = 0; 8882 // This variable refers to the size and not index in the array. 8883 unsigned LastLegalVectorType = 0; 8884 unsigned LastLegalIntegerType = 0; 8885 StartAddress = LoadNodes[0].OffsetFromBase; 8886 SDValue FirstChain = LoadNodes[0].MemNode->getChain(); 8887 for (unsigned i = 1; i < LoadNodes.size(); ++i) { 8888 // All loads much share the same chain. 8889 if (LoadNodes[i].MemNode->getChain() != FirstChain) 8890 break; 8891 8892 int64_t CurrAddress = LoadNodes[i].OffsetFromBase; 8893 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 8894 break; 8895 LastConsecutiveLoad = i; 8896 8897 // Find a legal type for the vector store. 8898 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 8899 if (TLI.isTypeLegal(StoreTy)) 8900 LastLegalVectorType = i + 1; 8901 8902 // Find a legal type for the integer store. 8903 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 8904 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 8905 if (TLI.isTypeLegal(StoreTy)) 8906 LastLegalIntegerType = i + 1; 8907 // Or check whether a truncstore and extload is legal. 8908 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) == 8909 TargetLowering::TypePromoteInteger) { 8910 EVT LegalizedStoredValueTy = 8911 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy); 8912 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) && 8913 TLI.isLoadExtLegal(ISD::ZEXTLOAD, StoreTy) && 8914 TLI.isLoadExtLegal(ISD::SEXTLOAD, StoreTy) && 8915 TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy)) 8916 LastLegalIntegerType = i+1; 8917 } 8918 } 8919 8920 // Only use vector types if the vector type is larger than the integer type. 8921 // If they are the same, use integers. 8922 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors; 8923 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType); 8924 8925 // We add +1 here because the LastXXX variables refer to location while 8926 // the NumElem refers to array/index size. 8927 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1; 8928 NumElem = std::min(LastLegalType, NumElem); 8929 8930 if (NumElem < 2) 8931 return false; 8932 8933 // The earliest Node in the DAG. 8934 unsigned EarliestNodeUsed = 0; 8935 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 8936 for (unsigned i=1; i<NumElem; ++i) { 8937 // Find a chain for the new wide-store operand. Notice that some 8938 // of the store nodes that we found may not be selected for inclusion 8939 // in the wide store. The chain we use needs to be the chain of the 8940 // earliest store node which is *used* and replaced by the wide store. 8941 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 8942 EarliestNodeUsed = i; 8943 } 8944 8945 // Find if it is better to use vectors or integers to load and store 8946 // to memory. 8947 EVT JointMemOpVT; 8948 if (UseVectorTy) { 8949 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 8950 } else { 8951 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 8952 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 8953 } 8954 8955 SDLoc LoadDL(LoadNodes[0].MemNode); 8956 SDLoc StoreDL(StoreNodes[0].MemNode); 8957 8958 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode); 8959 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL, 8960 FirstLoad->getChain(), 8961 FirstLoad->getBasePtr(), 8962 FirstLoad->getPointerInfo(), 8963 false, false, false, 8964 FirstLoad->getAlignment()); 8965 8966 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad, 8967 FirstInChain->getBasePtr(), 8968 FirstInChain->getPointerInfo(), false, false, 8969 FirstInChain->getAlignment()); 8970 8971 // Replace one of the loads with the new load. 8972 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode); 8973 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), 8974 SDValue(NewLoad.getNode(), 1)); 8975 8976 // Remove the rest of the load chains. 8977 for (unsigned i = 1; i < NumElem ; ++i) { 8978 // Replace all chain users of the old load nodes with the chain of the new 8979 // load node. 8980 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode); 8981 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain()); 8982 } 8983 8984 // Replace the first store with the new store. 8985 CombineTo(EarliestOp, NewStore); 8986 // Erase all other stores. 8987 for (unsigned i = 0; i < NumElem ; ++i) { 8988 // Remove all Store nodes. 8989 if (StoreNodes[i].MemNode == EarliestOp) 8990 continue; 8991 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8992 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain()); 8993 removeFromWorkList(St); 8994 DAG.DeleteNode(St); 8995 } 8996 8997 return true; 8998} 8999 9000SDValue DAGCombiner::visitSTORE(SDNode *N) { 9001 StoreSDNode *ST = cast<StoreSDNode>(N); 9002 SDValue Chain = ST->getChain(); 9003 SDValue Value = ST->getValue(); 9004 SDValue Ptr = ST->getBasePtr(); 9005 9006 // If this is a store of a bit convert, store the input value if the 9007 // resultant store does not need a higher alignment than the original. 9008 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 9009 ST->isUnindexed()) { 9010 unsigned OrigAlign = ST->getAlignment(); 9011 EVT SVT = Value.getOperand(0).getValueType(); 9012 unsigned Align = TLI.getDataLayout()-> 9013 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 9014 if (Align <= OrigAlign && 9015 ((!LegalOperations && !ST->isVolatile()) || 9016 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 9017 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0), 9018 Ptr, ST->getPointerInfo(), ST->isVolatile(), 9019 ST->isNonTemporal(), OrigAlign, 9020 ST->getTBAAInfo()); 9021 } 9022 9023 // Turn 'store undef, Ptr' -> nothing. 9024 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 9025 return Chain; 9026 9027 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 9028 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 9029 // NOTE: If the original store is volatile, this transform must not increase 9030 // the number of stores. For example, on x86-32 an f64 can be stored in one 9031 // processor operation but an i64 (which is not legal) requires two. So the 9032 // transform should not be done in this case. 9033 if (Value.getOpcode() != ISD::TargetConstantFP) { 9034 SDValue Tmp; 9035 switch (CFP->getSimpleValueType(0).SimpleTy) { 9036 default: llvm_unreachable("Unknown FP type"); 9037 case MVT::f16: // We don't do this for these yet. 9038 case MVT::f80: 9039 case MVT::f128: 9040 case MVT::ppcf128: 9041 break; 9042 case MVT::f32: 9043 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 9044 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 9045 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 9046 bitcastToAPInt().getZExtValue(), MVT::i32); 9047 return DAG.getStore(Chain, SDLoc(N), Tmp, 9048 Ptr, ST->getMemOperand()); 9049 } 9050 break; 9051 case MVT::f64: 9052 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 9053 !ST->isVolatile()) || 9054 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 9055 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 9056 getZExtValue(), MVT::i64); 9057 return DAG.getStore(Chain, SDLoc(N), Tmp, 9058 Ptr, ST->getMemOperand()); 9059 } 9060 9061 if (!ST->isVolatile() && 9062 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 9063 // Many FP stores are not made apparent until after legalize, e.g. for 9064 // argument passing. Since this is so common, custom legalize the 9065 // 64-bit integer store into two 32-bit stores. 9066 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 9067 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 9068 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 9069 if (TLI.isBigEndian()) std::swap(Lo, Hi); 9070 9071 unsigned Alignment = ST->getAlignment(); 9072 bool isVolatile = ST->isVolatile(); 9073 bool isNonTemporal = ST->isNonTemporal(); 9074 const MDNode *TBAAInfo = ST->getTBAAInfo(); 9075 9076 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo, 9077 Ptr, ST->getPointerInfo(), 9078 isVolatile, isNonTemporal, 9079 ST->getAlignment(), TBAAInfo); 9080 Ptr = DAG.getNode(ISD::ADD, SDLoc(N), Ptr.getValueType(), Ptr, 9081 DAG.getConstant(4, Ptr.getValueType())); 9082 Alignment = MinAlign(Alignment, 4U); 9083 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi, 9084 Ptr, ST->getPointerInfo().getWithOffset(4), 9085 isVolatile, isNonTemporal, 9086 Alignment, TBAAInfo); 9087 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, 9088 St0, St1); 9089 } 9090 9091 break; 9092 } 9093 } 9094 } 9095 9096 // Try to infer better alignment information than the store already has. 9097 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 9098 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 9099 if (Align > ST->getAlignment()) 9100 return DAG.getTruncStore(Chain, SDLoc(N), Value, 9101 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 9102 ST->isVolatile(), ST->isNonTemporal(), Align, 9103 ST->getTBAAInfo()); 9104 } 9105 } 9106 9107 // Try transforming a pair floating point load / store ops to integer 9108 // load / store ops. 9109 SDValue NewST = TransformFPLoadStorePair(N); 9110 if (NewST.getNode()) 9111 return NewST; 9112 9113 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA : 9114 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA(); 9115 if (UseAA) { 9116 // Walk up chain skipping non-aliasing memory nodes. 9117 SDValue BetterChain = FindBetterChain(N, Chain); 9118 9119 // If there is a better chain. 9120 if (Chain != BetterChain) { 9121 SDValue ReplStore; 9122 9123 // Replace the chain to avoid dependency. 9124 if (ST->isTruncatingStore()) { 9125 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr, 9126 ST->getMemoryVT(), ST->getMemOperand()); 9127 } else { 9128 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr, 9129 ST->getMemOperand()); 9130 } 9131 9132 // Create token to keep both nodes around. 9133 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N), 9134 MVT::Other, Chain, ReplStore); 9135 9136 // Make sure the new and old chains are cleaned up. 9137 AddToWorkList(Token.getNode()); 9138 9139 // Don't add users to work list. 9140 return CombineTo(N, Token, false); 9141 } 9142 } 9143 9144 // Try transforming N to an indexed store. 9145 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 9146 return SDValue(N, 0); 9147 9148 // FIXME: is there such a thing as a truncating indexed store? 9149 if (ST->isTruncatingStore() && ST->isUnindexed() && 9150 Value.getValueType().isInteger()) { 9151 // See if we can simplify the input to this truncstore with knowledge that 9152 // only the low bits are being used. For example: 9153 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 9154 SDValue Shorter = 9155 GetDemandedBits(Value, 9156 APInt::getLowBitsSet( 9157 Value.getValueType().getScalarType().getSizeInBits(), 9158 ST->getMemoryVT().getScalarType().getSizeInBits())); 9159 AddToWorkList(Value.getNode()); 9160 if (Shorter.getNode()) 9161 return DAG.getTruncStore(Chain, SDLoc(N), Shorter, 9162 Ptr, ST->getMemoryVT(), ST->getMemOperand()); 9163 9164 // Otherwise, see if we can simplify the operation with 9165 // SimplifyDemandedBits, which only works if the value has a single use. 9166 if (SimplifyDemandedBits(Value, 9167 APInt::getLowBitsSet( 9168 Value.getValueType().getScalarType().getSizeInBits(), 9169 ST->getMemoryVT().getScalarType().getSizeInBits()))) 9170 return SDValue(N, 0); 9171 } 9172 9173 // If this is a load followed by a store to the same location, then the store 9174 // is dead/noop. 9175 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 9176 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 9177 ST->isUnindexed() && !ST->isVolatile() && 9178 // There can't be any side effects between the load and store, such as 9179 // a call or store. 9180 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 9181 // The store is dead, remove it. 9182 return Chain; 9183 } 9184 } 9185 9186 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 9187 // truncating store. We can do this even if this is already a truncstore. 9188 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 9189 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 9190 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 9191 ST->getMemoryVT())) { 9192 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0), 9193 Ptr, ST->getMemoryVT(), ST->getMemOperand()); 9194 } 9195 9196 // Only perform this optimization before the types are legal, because we 9197 // don't want to perform this optimization on every DAGCombine invocation. 9198 if (!LegalTypes) { 9199 bool EverChanged = false; 9200 9201 do { 9202 // There can be multiple store sequences on the same chain. 9203 // Keep trying to merge store sequences until we are unable to do so 9204 // or until we merge the last store on the chain. 9205 bool Changed = MergeConsecutiveStores(ST); 9206 EverChanged |= Changed; 9207 if (!Changed) break; 9208 } while (ST->getOpcode() != ISD::DELETED_NODE); 9209 9210 if (EverChanged) 9211 return SDValue(N, 0); 9212 } 9213 9214 return ReduceLoadOpStoreWidth(N); 9215} 9216 9217SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 9218 SDValue InVec = N->getOperand(0); 9219 SDValue InVal = N->getOperand(1); 9220 SDValue EltNo = N->getOperand(2); 9221 SDLoc dl(N); 9222 9223 // If the inserted element is an UNDEF, just use the input vector. 9224 if (InVal.getOpcode() == ISD::UNDEF) 9225 return InVec; 9226 9227 EVT VT = InVec.getValueType(); 9228 9229 // If we can't generate a legal BUILD_VECTOR, exit 9230 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 9231 return SDValue(); 9232 9233 // Check that we know which element is being inserted 9234 if (!isa<ConstantSDNode>(EltNo)) 9235 return SDValue(); 9236 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 9237 9238 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 9239 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 9240 // vector elements. 9241 SmallVector<SDValue, 8> Ops; 9242 // Do not combine these two vectors if the output vector will not replace 9243 // the input vector. 9244 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) { 9245 Ops.append(InVec.getNode()->op_begin(), 9246 InVec.getNode()->op_end()); 9247 } else if (InVec.getOpcode() == ISD::UNDEF) { 9248 unsigned NElts = VT.getVectorNumElements(); 9249 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 9250 } else { 9251 return SDValue(); 9252 } 9253 9254 // Insert the element 9255 if (Elt < Ops.size()) { 9256 // All the operands of BUILD_VECTOR must have the same type; 9257 // we enforce that here. 9258 EVT OpVT = Ops[0].getValueType(); 9259 if (InVal.getValueType() != OpVT) 9260 InVal = OpVT.bitsGT(InVal.getValueType()) ? 9261 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 9262 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 9263 Ops[Elt] = InVal; 9264 } 9265 9266 // Return the new vector 9267 return DAG.getNode(ISD::BUILD_VECTOR, dl, 9268 VT, &Ops[0], Ops.size()); 9269} 9270 9271SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 9272 // (vextract (scalar_to_vector val, 0) -> val 9273 SDValue InVec = N->getOperand(0); 9274 EVT VT = InVec.getValueType(); 9275 EVT NVT = N->getValueType(0); 9276 9277 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 9278 // Check if the result type doesn't match the inserted element type. A 9279 // SCALAR_TO_VECTOR may truncate the inserted element and the 9280 // EXTRACT_VECTOR_ELT may widen the extracted vector. 9281 SDValue InOp = InVec.getOperand(0); 9282 if (InOp.getValueType() != NVT) { 9283 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 9284 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT); 9285 } 9286 return InOp; 9287 } 9288 9289 SDValue EltNo = N->getOperand(1); 9290 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 9291 9292 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 9293 // We only perform this optimization before the op legalization phase because 9294 // we may introduce new vector instructions which are not backed by TD 9295 // patterns. For example on AVX, extracting elements from a wide vector 9296 // without using extract_subvector. 9297 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 9298 && ConstEltNo && !LegalOperations) { 9299 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 9300 int NumElem = VT.getVectorNumElements(); 9301 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 9302 // Find the new index to extract from. 9303 int OrigElt = SVOp->getMaskElt(Elt); 9304 9305 // Extracting an undef index is undef. 9306 if (OrigElt == -1) 9307 return DAG.getUNDEF(NVT); 9308 9309 // Select the right vector half to extract from. 9310 if (OrigElt < NumElem) { 9311 InVec = InVec->getOperand(0); 9312 } else { 9313 InVec = InVec->getOperand(1); 9314 OrigElt -= NumElem; 9315 } 9316 9317 EVT IndexTy = TLI.getVectorIdxTy(); 9318 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT, 9319 InVec, DAG.getConstant(OrigElt, IndexTy)); 9320 } 9321 9322 // Perform only after legalization to ensure build_vector / vector_shuffle 9323 // optimizations have already been done. 9324 if (!LegalOperations) return SDValue(); 9325 9326 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 9327 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 9328 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 9329 9330 if (ConstEltNo) { 9331 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 9332 bool NewLoad = false; 9333 bool BCNumEltsChanged = false; 9334 EVT ExtVT = VT.getVectorElementType(); 9335 EVT LVT = ExtVT; 9336 9337 // If the result of load has to be truncated, then it's not necessarily 9338 // profitable. 9339 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 9340 return SDValue(); 9341 9342 if (InVec.getOpcode() == ISD::BITCAST) { 9343 // Don't duplicate a load with other uses. 9344 if (!InVec.hasOneUse()) 9345 return SDValue(); 9346 9347 EVT BCVT = InVec.getOperand(0).getValueType(); 9348 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 9349 return SDValue(); 9350 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 9351 BCNumEltsChanged = true; 9352 InVec = InVec.getOperand(0); 9353 ExtVT = BCVT.getVectorElementType(); 9354 NewLoad = true; 9355 } 9356 9357 LoadSDNode *LN0 = NULL; 9358 const ShuffleVectorSDNode *SVN = NULL; 9359 if (ISD::isNormalLoad(InVec.getNode())) { 9360 LN0 = cast<LoadSDNode>(InVec); 9361 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 9362 InVec.getOperand(0).getValueType() == ExtVT && 9363 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 9364 // Don't duplicate a load with other uses. 9365 if (!InVec.hasOneUse()) 9366 return SDValue(); 9367 9368 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 9369 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 9370 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 9371 // => 9372 // (load $addr+1*size) 9373 9374 // Don't duplicate a load with other uses. 9375 if (!InVec.hasOneUse()) 9376 return SDValue(); 9377 9378 // If the bit convert changed the number of elements, it is unsafe 9379 // to examine the mask. 9380 if (BCNumEltsChanged) 9381 return SDValue(); 9382 9383 // Select the input vector, guarding against out of range extract vector. 9384 unsigned NumElems = VT.getVectorNumElements(); 9385 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 9386 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 9387 9388 if (InVec.getOpcode() == ISD::BITCAST) { 9389 // Don't duplicate a load with other uses. 9390 if (!InVec.hasOneUse()) 9391 return SDValue(); 9392 9393 InVec = InVec.getOperand(0); 9394 } 9395 if (ISD::isNormalLoad(InVec.getNode())) { 9396 LN0 = cast<LoadSDNode>(InVec); 9397 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 9398 } 9399 } 9400 9401 // Make sure we found a non-volatile load and the extractelement is 9402 // the only use. 9403 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 9404 return SDValue(); 9405 9406 // If Idx was -1 above, Elt is going to be -1, so just return undef. 9407 if (Elt == -1) 9408 return DAG.getUNDEF(LVT); 9409 9410 unsigned Align = LN0->getAlignment(); 9411 if (NewLoad) { 9412 // Check the resultant load doesn't need a higher alignment than the 9413 // original load. 9414 unsigned NewAlign = 9415 TLI.getDataLayout() 9416 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 9417 9418 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 9419 return SDValue(); 9420 9421 Align = NewAlign; 9422 } 9423 9424 SDValue NewPtr = LN0->getBasePtr(); 9425 unsigned PtrOff = 0; 9426 9427 if (Elt) { 9428 PtrOff = LVT.getSizeInBits() * Elt / 8; 9429 EVT PtrType = NewPtr.getValueType(); 9430 if (TLI.isBigEndian()) 9431 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 9432 NewPtr = DAG.getNode(ISD::ADD, SDLoc(N), PtrType, NewPtr, 9433 DAG.getConstant(PtrOff, PtrType)); 9434 } 9435 9436 // The replacement we need to do here is a little tricky: we need to 9437 // replace an extractelement of a load with a load. 9438 // Use ReplaceAllUsesOfValuesWith to do the replacement. 9439 // Note that this replacement assumes that the extractvalue is the only 9440 // use of the load; that's okay because we don't want to perform this 9441 // transformation in other cases anyway. 9442 SDValue Load; 9443 SDValue Chain; 9444 if (NVT.bitsGT(LVT)) { 9445 // If the result type of vextract is wider than the load, then issue an 9446 // extending load instead. 9447 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 9448 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 9449 Load = DAG.getExtLoad(ExtType, SDLoc(N), NVT, LN0->getChain(), 9450 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 9451 LVT, LN0->isVolatile(), LN0->isNonTemporal(), 9452 Align, LN0->getTBAAInfo()); 9453 Chain = Load.getValue(1); 9454 } else { 9455 Load = DAG.getLoad(LVT, SDLoc(N), LN0->getChain(), NewPtr, 9456 LN0->getPointerInfo().getWithOffset(PtrOff), 9457 LN0->isVolatile(), LN0->isNonTemporal(), 9458 LN0->isInvariant(), Align, LN0->getTBAAInfo()); 9459 Chain = Load.getValue(1); 9460 if (NVT.bitsLT(LVT)) 9461 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(N), NVT, Load); 9462 else 9463 Load = DAG.getNode(ISD::BITCAST, SDLoc(N), NVT, Load); 9464 } 9465 WorkListRemover DeadNodes(*this); 9466 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 9467 SDValue To[] = { Load, Chain }; 9468 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 9469 // Since we're explcitly calling ReplaceAllUses, add the new node to the 9470 // worklist explicitly as well. 9471 AddToWorkList(Load.getNode()); 9472 AddUsersToWorkList(Load.getNode()); // Add users too 9473 // Make sure to revisit this node to clean it up; it will usually be dead. 9474 AddToWorkList(N); 9475 return SDValue(N, 0); 9476 } 9477 9478 return SDValue(); 9479} 9480 9481// Simplify (build_vec (ext )) to (bitcast (build_vec )) 9482SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) { 9483 // We perform this optimization post type-legalization because 9484 // the type-legalizer often scalarizes integer-promoted vectors. 9485 // Performing this optimization before may create bit-casts which 9486 // will be type-legalized to complex code sequences. 9487 // We perform this optimization only before the operation legalizer because we 9488 // may introduce illegal operations. 9489 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) 9490 return SDValue(); 9491 9492 unsigned NumInScalars = N->getNumOperands(); 9493 SDLoc dl(N); 9494 EVT VT = N->getValueType(0); 9495 9496 // Check to see if this is a BUILD_VECTOR of a bunch of values 9497 // which come from any_extend or zero_extend nodes. If so, we can create 9498 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 9499 // optimizations. We do not handle sign-extend because we can't fill the sign 9500 // using shuffles. 9501 EVT SourceType = MVT::Other; 9502 bool AllAnyExt = true; 9503 9504 for (unsigned i = 0; i != NumInScalars; ++i) { 9505 SDValue In = N->getOperand(i); 9506 // Ignore undef inputs. 9507 if (In.getOpcode() == ISD::UNDEF) continue; 9508 9509 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 9510 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 9511 9512 // Abort if the element is not an extension. 9513 if (!ZeroExt && !AnyExt) { 9514 SourceType = MVT::Other; 9515 break; 9516 } 9517 9518 // The input is a ZeroExt or AnyExt. Check the original type. 9519 EVT InTy = In.getOperand(0).getValueType(); 9520 9521 // Check that all of the widened source types are the same. 9522 if (SourceType == MVT::Other) 9523 // First time. 9524 SourceType = InTy; 9525 else if (InTy != SourceType) { 9526 // Multiple income types. Abort. 9527 SourceType = MVT::Other; 9528 break; 9529 } 9530 9531 // Check if all of the extends are ANY_EXTENDs. 9532 AllAnyExt &= AnyExt; 9533 } 9534 9535 // In order to have valid types, all of the inputs must be extended from the 9536 // same source type and all of the inputs must be any or zero extend. 9537 // Scalar sizes must be a power of two. 9538 EVT OutScalarTy = VT.getScalarType(); 9539 bool ValidTypes = SourceType != MVT::Other && 9540 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 9541 isPowerOf2_32(SourceType.getSizeInBits()); 9542 9543 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 9544 // turn into a single shuffle instruction. 9545 if (!ValidTypes) 9546 return SDValue(); 9547 9548 bool isLE = TLI.isLittleEndian(); 9549 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 9550 assert(ElemRatio > 1 && "Invalid element size ratio"); 9551 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 9552 DAG.getConstant(0, SourceType); 9553 9554 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements(); 9555 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 9556 9557 // Populate the new build_vector 9558 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 9559 SDValue Cast = N->getOperand(i); 9560 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 9561 Cast.getOpcode() == ISD::ZERO_EXTEND || 9562 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 9563 SDValue In; 9564 if (Cast.getOpcode() == ISD::UNDEF) 9565 In = DAG.getUNDEF(SourceType); 9566 else 9567 In = Cast->getOperand(0); 9568 unsigned Index = isLE ? (i * ElemRatio) : 9569 (i * ElemRatio + (ElemRatio - 1)); 9570 9571 assert(Index < Ops.size() && "Invalid index"); 9572 Ops[Index] = In; 9573 } 9574 9575 // The type of the new BUILD_VECTOR node. 9576 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 9577 assert(VecVT.getSizeInBits() == VT.getSizeInBits() && 9578 "Invalid vector size"); 9579 // Check if the new vector type is legal. 9580 if (!isTypeLegal(VecVT)) return SDValue(); 9581 9582 // Make the new BUILD_VECTOR. 9583 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size()); 9584 9585 // The new BUILD_VECTOR node has the potential to be further optimized. 9586 AddToWorkList(BV.getNode()); 9587 // Bitcast to the desired type. 9588 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 9589} 9590 9591SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) { 9592 EVT VT = N->getValueType(0); 9593 9594 unsigned NumInScalars = N->getNumOperands(); 9595 SDLoc dl(N); 9596 9597 EVT SrcVT = MVT::Other; 9598 unsigned Opcode = ISD::DELETED_NODE; 9599 unsigned NumDefs = 0; 9600 9601 for (unsigned i = 0; i != NumInScalars; ++i) { 9602 SDValue In = N->getOperand(i); 9603 unsigned Opc = In.getOpcode(); 9604 9605 if (Opc == ISD::UNDEF) 9606 continue; 9607 9608 // If all scalar values are floats and converted from integers. 9609 if (Opcode == ISD::DELETED_NODE && 9610 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { 9611 Opcode = Opc; 9612 } 9613 9614 if (Opc != Opcode) 9615 return SDValue(); 9616 9617 EVT InVT = In.getOperand(0).getValueType(); 9618 9619 // If all scalar values are typed differently, bail out. It's chosen to 9620 // simplify BUILD_VECTOR of integer types. 9621 if (SrcVT == MVT::Other) 9622 SrcVT = InVT; 9623 if (SrcVT != InVT) 9624 return SDValue(); 9625 NumDefs++; 9626 } 9627 9628 // If the vector has just one element defined, it's not worth to fold it into 9629 // a vectorized one. 9630 if (NumDefs < 2) 9631 return SDValue(); 9632 9633 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) 9634 && "Should only handle conversion from integer to float."); 9635 assert(SrcVT != MVT::Other && "Cannot determine source type!"); 9636 9637 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars); 9638 9639 if (!TLI.isOperationLegalOrCustom(Opcode, NVT)) 9640 return SDValue(); 9641 9642 SmallVector<SDValue, 8> Opnds; 9643 for (unsigned i = 0; i != NumInScalars; ++i) { 9644 SDValue In = N->getOperand(i); 9645 9646 if (In.getOpcode() == ISD::UNDEF) 9647 Opnds.push_back(DAG.getUNDEF(SrcVT)); 9648 else 9649 Opnds.push_back(In.getOperand(0)); 9650 } 9651 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, 9652 &Opnds[0], Opnds.size()); 9653 AddToWorkList(BV.getNode()); 9654 9655 return DAG.getNode(Opcode, dl, VT, BV); 9656} 9657 9658SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 9659 unsigned NumInScalars = N->getNumOperands(); 9660 SDLoc dl(N); 9661 EVT VT = N->getValueType(0); 9662 9663 // A vector built entirely of undefs is undef. 9664 if (ISD::allOperandsUndef(N)) 9665 return DAG.getUNDEF(VT); 9666 9667 SDValue V = reduceBuildVecExtToExtBuildVec(N); 9668 if (V.getNode()) 9669 return V; 9670 9671 V = reduceBuildVecConvertToConvertBuildVec(N); 9672 if (V.getNode()) 9673 return V; 9674 9675 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 9676 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 9677 // at most two distinct vectors, turn this into a shuffle node. 9678 9679 // May only combine to shuffle after legalize if shuffle is legal. 9680 if (LegalOperations && 9681 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 9682 return SDValue(); 9683 9684 SDValue VecIn1, VecIn2; 9685 for (unsigned i = 0; i != NumInScalars; ++i) { 9686 // Ignore undef inputs. 9687 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 9688 9689 // If this input is something other than a EXTRACT_VECTOR_ELT with a 9690 // constant index, bail out. 9691 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 9692 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 9693 VecIn1 = VecIn2 = SDValue(0, 0); 9694 break; 9695 } 9696 9697 // We allow up to two distinct input vectors. 9698 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 9699 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 9700 continue; 9701 9702 if (VecIn1.getNode() == 0) { 9703 VecIn1 = ExtractedFromVec; 9704 } else if (VecIn2.getNode() == 0) { 9705 VecIn2 = ExtractedFromVec; 9706 } else { 9707 // Too many inputs. 9708 VecIn1 = VecIn2 = SDValue(0, 0); 9709 break; 9710 } 9711 } 9712 9713 // If everything is good, we can make a shuffle operation. 9714 if (VecIn1.getNode()) { 9715 SmallVector<int, 8> Mask; 9716 for (unsigned i = 0; i != NumInScalars; ++i) { 9717 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 9718 Mask.push_back(-1); 9719 continue; 9720 } 9721 9722 // If extracting from the first vector, just use the index directly. 9723 SDValue Extract = N->getOperand(i); 9724 SDValue ExtVal = Extract.getOperand(1); 9725 if (Extract.getOperand(0) == VecIn1) { 9726 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 9727 if (ExtIndex > VT.getVectorNumElements()) 9728 return SDValue(); 9729 9730 Mask.push_back(ExtIndex); 9731 continue; 9732 } 9733 9734 // Otherwise, use InIdx + VecSize 9735 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 9736 Mask.push_back(Idx+NumInScalars); 9737 } 9738 9739 // We can't generate a shuffle node with mismatched input and output types. 9740 // Attempt to transform a single input vector to the correct type. 9741 if ((VT != VecIn1.getValueType())) { 9742 // We don't support shuffeling between TWO values of different types. 9743 if (VecIn2.getNode() != 0) 9744 return SDValue(); 9745 9746 // We only support widening of vectors which are half the size of the 9747 // output registers. For example XMM->YMM widening on X86 with AVX. 9748 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 9749 return SDValue(); 9750 9751 // If the input vector type has a different base type to the output 9752 // vector type, bail out. 9753 if (VecIn1.getValueType().getVectorElementType() != 9754 VT.getVectorElementType()) 9755 return SDValue(); 9756 9757 // Widen the input vector by adding undef values. 9758 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9759 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 9760 } 9761 9762 // If VecIn2 is unused then change it to undef. 9763 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 9764 9765 // Check that we were able to transform all incoming values to the same 9766 // type. 9767 if (VecIn2.getValueType() != VecIn1.getValueType() || 9768 VecIn1.getValueType() != VT) 9769 return SDValue(); 9770 9771 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 9772 if (!isTypeLegal(VT)) 9773 return SDValue(); 9774 9775 // Return the new VECTOR_SHUFFLE node. 9776 SDValue Ops[2]; 9777 Ops[0] = VecIn1; 9778 Ops[1] = VecIn2; 9779 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]); 9780 } 9781 9782 return SDValue(); 9783} 9784 9785SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 9786 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 9787 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 9788 // inputs come from at most two distinct vectors, turn this into a shuffle 9789 // node. 9790 9791 // If we only have one input vector, we don't need to do any concatenation. 9792 if (N->getNumOperands() == 1) 9793 return N->getOperand(0); 9794 9795 // Check if all of the operands are undefs. 9796 EVT VT = N->getValueType(0); 9797 if (ISD::allOperandsUndef(N)) 9798 return DAG.getUNDEF(VT); 9799 9800 // Optimize concat_vectors where one of the vectors is undef. 9801 if (N->getNumOperands() == 2 && 9802 N->getOperand(1)->getOpcode() == ISD::UNDEF) { 9803 SDValue In = N->getOperand(0); 9804 assert(In->getValueType(0).isVector() && "Must concat vectors"); 9805 9806 // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr). 9807 if (In->getOpcode() == ISD::BITCAST && 9808 !In->getOperand(0)->getValueType(0).isVector()) { 9809 SDValue Scalar = In->getOperand(0); 9810 EVT SclTy = Scalar->getValueType(0); 9811 9812 if (!SclTy.isFloatingPoint() && !SclTy.isInteger()) 9813 return SDValue(); 9814 9815 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy, 9816 VT.getSizeInBits() / SclTy.getSizeInBits()); 9817 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType())) 9818 return SDValue(); 9819 9820 SDLoc dl = SDLoc(N); 9821 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar); 9822 return DAG.getNode(ISD::BITCAST, dl, VT, Res); 9823 } 9824 } 9825 9826 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR 9827 // nodes often generate nop CONCAT_VECTOR nodes. 9828 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that 9829 // place the incoming vectors at the exact same location. 9830 SDValue SingleSource = SDValue(); 9831 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements(); 9832 9833 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 9834 SDValue Op = N->getOperand(i); 9835 9836 if (Op.getOpcode() == ISD::UNDEF) 9837 continue; 9838 9839 // Check if this is the identity extract: 9840 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) 9841 return SDValue(); 9842 9843 // Find the single incoming vector for the extract_subvector. 9844 if (SingleSource.getNode()) { 9845 if (Op.getOperand(0) != SingleSource) 9846 return SDValue(); 9847 } else { 9848 SingleSource = Op.getOperand(0); 9849 9850 // Check the source type is the same as the type of the result. 9851 // If not, this concat may extend the vector, so we can not 9852 // optimize it away. 9853 if (SingleSource.getValueType() != N->getValueType(0)) 9854 return SDValue(); 9855 } 9856 9857 unsigned IdentityIndex = i * PartNumElem; 9858 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 9859 // The extract index must be constant. 9860 if (!CS) 9861 return SDValue(); 9862 9863 // Check that we are reading from the identity index. 9864 if (CS->getZExtValue() != IdentityIndex) 9865 return SDValue(); 9866 } 9867 9868 if (SingleSource.getNode()) 9869 return SingleSource; 9870 9871 return SDValue(); 9872} 9873 9874SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 9875 EVT NVT = N->getValueType(0); 9876 SDValue V = N->getOperand(0); 9877 9878 if (V->getOpcode() == ISD::CONCAT_VECTORS) { 9879 // Combine: 9880 // (extract_subvec (concat V1, V2, ...), i) 9881 // Into: 9882 // Vi if possible 9883 // Only operand 0 is checked as 'concat' assumes all inputs of the same 9884 // type. 9885 if (V->getOperand(0).getValueType() != NVT) 9886 return SDValue(); 9887 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 9888 unsigned NumElems = NVT.getVectorNumElements(); 9889 assert((Idx % NumElems) == 0 && 9890 "IDX in concat is not a multiple of the result vector length."); 9891 return V->getOperand(Idx / NumElems); 9892 } 9893 9894 // Skip bitcasting 9895 if (V->getOpcode() == ISD::BITCAST) 9896 V = V.getOperand(0); 9897 9898 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 9899 SDLoc dl(N); 9900 // Handle only simple case where vector being inserted and vector 9901 // being extracted are of same type, and are half size of larger vectors. 9902 EVT BigVT = V->getOperand(0).getValueType(); 9903 EVT SmallVT = V->getOperand(1).getValueType(); 9904 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 9905 return SDValue(); 9906 9907 // Only handle cases where both indexes are constants with the same type. 9908 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 9909 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 9910 9911 if (InsIdx && ExtIdx && 9912 InsIdx->getValueType(0).getSizeInBits() <= 64 && 9913 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 9914 // Combine: 9915 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 9916 // Into: 9917 // indices are equal or bit offsets are equal => V1 9918 // otherwise => (extract_subvec V1, ExtIdx) 9919 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() == 9920 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits()) 9921 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1)); 9922 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, 9923 DAG.getNode(ISD::BITCAST, dl, 9924 N->getOperand(0).getValueType(), 9925 V->getOperand(0)), N->getOperand(1)); 9926 } 9927 } 9928 9929 return SDValue(); 9930} 9931 9932// Tries to turn a shuffle of two CONCAT_VECTORS into a single concat. 9933static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) { 9934 EVT VT = N->getValueType(0); 9935 unsigned NumElts = VT.getVectorNumElements(); 9936 9937 SDValue N0 = N->getOperand(0); 9938 SDValue N1 = N->getOperand(1); 9939 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 9940 9941 SmallVector<SDValue, 4> Ops; 9942 EVT ConcatVT = N0.getOperand(0).getValueType(); 9943 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements(); 9944 unsigned NumConcats = NumElts / NumElemsPerConcat; 9945 9946 // Look at every vector that's inserted. We're looking for exact 9947 // subvector-sized copies from a concatenated vector 9948 for (unsigned I = 0; I != NumConcats; ++I) { 9949 // Make sure we're dealing with a copy. 9950 unsigned Begin = I * NumElemsPerConcat; 9951 bool AllUndef = true, NoUndef = true; 9952 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) { 9953 if (SVN->getMaskElt(J) >= 0) 9954 AllUndef = false; 9955 else 9956 NoUndef = false; 9957 } 9958 9959 if (NoUndef) { 9960 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0) 9961 return SDValue(); 9962 9963 for (unsigned J = 1; J != NumElemsPerConcat; ++J) 9964 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J)) 9965 return SDValue(); 9966 9967 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat; 9968 if (FirstElt < N0.getNumOperands()) 9969 Ops.push_back(N0.getOperand(FirstElt)); 9970 else 9971 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands())); 9972 9973 } else if (AllUndef) { 9974 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType())); 9975 } else { // Mixed with general masks and undefs, can't do optimization. 9976 return SDValue(); 9977 } 9978 } 9979 9980 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops.data(), 9981 Ops.size()); 9982} 9983 9984SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 9985 EVT VT = N->getValueType(0); 9986 unsigned NumElts = VT.getVectorNumElements(); 9987 9988 SDValue N0 = N->getOperand(0); 9989 SDValue N1 = N->getOperand(1); 9990 9991 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 9992 9993 // Canonicalize shuffle undef, undef -> undef 9994 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 9995 return DAG.getUNDEF(VT); 9996 9997 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 9998 9999 // Canonicalize shuffle v, v -> v, undef 10000 if (N0 == N1) { 10001 SmallVector<int, 8> NewMask; 10002 for (unsigned i = 0; i != NumElts; ++i) { 10003 int Idx = SVN->getMaskElt(i); 10004 if (Idx >= (int)NumElts) Idx -= NumElts; 10005 NewMask.push_back(Idx); 10006 } 10007 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT), 10008 &NewMask[0]); 10009 } 10010 10011 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 10012 if (N0.getOpcode() == ISD::UNDEF) { 10013 SmallVector<int, 8> NewMask; 10014 for (unsigned i = 0; i != NumElts; ++i) { 10015 int Idx = SVN->getMaskElt(i); 10016 if (Idx >= 0) { 10017 if (Idx >= (int)NumElts) 10018 Idx -= NumElts; 10019 else 10020 Idx = -1; // remove reference to lhs 10021 } 10022 NewMask.push_back(Idx); 10023 } 10024 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT), 10025 &NewMask[0]); 10026 } 10027 10028 // Remove references to rhs if it is undef 10029 if (N1.getOpcode() == ISD::UNDEF) { 10030 bool Changed = false; 10031 SmallVector<int, 8> NewMask; 10032 for (unsigned i = 0; i != NumElts; ++i) { 10033 int Idx = SVN->getMaskElt(i); 10034 if (Idx >= (int)NumElts) { 10035 Idx = -1; 10036 Changed = true; 10037 } 10038 NewMask.push_back(Idx); 10039 } 10040 if (Changed) 10041 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]); 10042 } 10043 10044 // If it is a splat, check if the argument vector is another splat or a 10045 // build_vector with all scalar elements the same. 10046 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 10047 SDNode *V = N0.getNode(); 10048 10049 // If this is a bit convert that changes the element type of the vector but 10050 // not the number of vector elements, look through it. Be careful not to 10051 // look though conversions that change things like v4f32 to v2f64. 10052 if (V->getOpcode() == ISD::BITCAST) { 10053 SDValue ConvInput = V->getOperand(0); 10054 if (ConvInput.getValueType().isVector() && 10055 ConvInput.getValueType().getVectorNumElements() == NumElts) 10056 V = ConvInput.getNode(); 10057 } 10058 10059 if (V->getOpcode() == ISD::BUILD_VECTOR) { 10060 assert(V->getNumOperands() == NumElts && 10061 "BUILD_VECTOR has wrong number of operands"); 10062 SDValue Base; 10063 bool AllSame = true; 10064 for (unsigned i = 0; i != NumElts; ++i) { 10065 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 10066 Base = V->getOperand(i); 10067 break; 10068 } 10069 } 10070 // Splat of <u, u, u, u>, return <u, u, u, u> 10071 if (!Base.getNode()) 10072 return N0; 10073 for (unsigned i = 0; i != NumElts; ++i) { 10074 if (V->getOperand(i) != Base) { 10075 AllSame = false; 10076 break; 10077 } 10078 } 10079 // Splat of <x, x, x, x>, return <x, x, x, x> 10080 if (AllSame) 10081 return N0; 10082 } 10083 } 10084 10085 if (N0.getOpcode() == ISD::CONCAT_VECTORS && 10086 Level < AfterLegalizeVectorOps && 10087 (N1.getOpcode() == ISD::UNDEF || 10088 (N1.getOpcode() == ISD::CONCAT_VECTORS && 10089 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) { 10090 SDValue V = partitionShuffleOfConcats(N, DAG); 10091 10092 if (V.getNode()) 10093 return V; 10094 } 10095 10096 // If this shuffle node is simply a swizzle of another shuffle node, 10097 // and it reverses the swizzle of the previous shuffle then we can 10098 // optimize shuffle(shuffle(x, undef), undef) -> x. 10099 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 10100 N1.getOpcode() == ISD::UNDEF) { 10101 10102 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 10103 10104 // Shuffle nodes can only reverse shuffles with a single non-undef value. 10105 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 10106 return SDValue(); 10107 10108 // The incoming shuffle must be of the same type as the result of the 10109 // current shuffle. 10110 assert(OtherSV->getOperand(0).getValueType() == VT && 10111 "Shuffle types don't match"); 10112 10113 for (unsigned i = 0; i != NumElts; ++i) { 10114 int Idx = SVN->getMaskElt(i); 10115 assert(Idx < (int)NumElts && "Index references undef operand"); 10116 // Next, this index comes from the first value, which is the incoming 10117 // shuffle. Adopt the incoming index. 10118 if (Idx >= 0) 10119 Idx = OtherSV->getMaskElt(Idx); 10120 10121 // The combined shuffle must map each index to itself. 10122 if (Idx >= 0 && (unsigned)Idx != i) 10123 return SDValue(); 10124 } 10125 10126 return OtherSV->getOperand(0); 10127 } 10128 10129 return SDValue(); 10130} 10131 10132/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 10133/// an AND to a vector_shuffle with the destination vector and a zero vector. 10134/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 10135/// vector_shuffle V, Zero, <0, 4, 2, 4> 10136SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 10137 EVT VT = N->getValueType(0); 10138 SDLoc dl(N); 10139 SDValue LHS = N->getOperand(0); 10140 SDValue RHS = N->getOperand(1); 10141 if (N->getOpcode() == ISD::AND) { 10142 if (RHS.getOpcode() == ISD::BITCAST) 10143 RHS = RHS.getOperand(0); 10144 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 10145 SmallVector<int, 8> Indices; 10146 unsigned NumElts = RHS.getNumOperands(); 10147 for (unsigned i = 0; i != NumElts; ++i) { 10148 SDValue Elt = RHS.getOperand(i); 10149 if (!isa<ConstantSDNode>(Elt)) 10150 return SDValue(); 10151 10152 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 10153 Indices.push_back(i); 10154 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 10155 Indices.push_back(NumElts); 10156 else 10157 return SDValue(); 10158 } 10159 10160 // Let's see if the target supports this vector_shuffle. 10161 EVT RVT = RHS.getValueType(); 10162 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 10163 return SDValue(); 10164 10165 // Return the new VECTOR_SHUFFLE node. 10166 EVT EltVT = RVT.getVectorElementType(); 10167 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 10168 DAG.getConstant(0, EltVT)); 10169 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), 10170 RVT, &ZeroOps[0], ZeroOps.size()); 10171 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 10172 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 10173 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 10174 } 10175 } 10176 10177 return SDValue(); 10178} 10179 10180/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 10181SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 10182 assert(N->getValueType(0).isVector() && 10183 "SimplifyVBinOp only works on vectors!"); 10184 10185 SDValue LHS = N->getOperand(0); 10186 SDValue RHS = N->getOperand(1); 10187 SDValue Shuffle = XformToShuffleWithZero(N); 10188 if (Shuffle.getNode()) return Shuffle; 10189 10190 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 10191 // this operation. 10192 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 10193 RHS.getOpcode() == ISD::BUILD_VECTOR) { 10194 SmallVector<SDValue, 8> Ops; 10195 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 10196 SDValue LHSOp = LHS.getOperand(i); 10197 SDValue RHSOp = RHS.getOperand(i); 10198 // If these two elements can't be folded, bail out. 10199 if ((LHSOp.getOpcode() != ISD::UNDEF && 10200 LHSOp.getOpcode() != ISD::Constant && 10201 LHSOp.getOpcode() != ISD::ConstantFP) || 10202 (RHSOp.getOpcode() != ISD::UNDEF && 10203 RHSOp.getOpcode() != ISD::Constant && 10204 RHSOp.getOpcode() != ISD::ConstantFP)) 10205 break; 10206 10207 // Can't fold divide by zero. 10208 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 10209 N->getOpcode() == ISD::FDIV) { 10210 if ((RHSOp.getOpcode() == ISD::Constant && 10211 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 10212 (RHSOp.getOpcode() == ISD::ConstantFP && 10213 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 10214 break; 10215 } 10216 10217 EVT VT = LHSOp.getValueType(); 10218 EVT RVT = RHSOp.getValueType(); 10219 if (RVT != VT) { 10220 // Integer BUILD_VECTOR operands may have types larger than the element 10221 // size (e.g., when the element type is not legal). Prior to type 10222 // legalization, the types may not match between the two BUILD_VECTORS. 10223 // Truncate one of the operands to make them match. 10224 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 10225 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp); 10226 } else { 10227 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp); 10228 VT = RVT; 10229 } 10230 } 10231 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT, 10232 LHSOp, RHSOp); 10233 if (FoldOp.getOpcode() != ISD::UNDEF && 10234 FoldOp.getOpcode() != ISD::Constant && 10235 FoldOp.getOpcode() != ISD::ConstantFP) 10236 break; 10237 Ops.push_back(FoldOp); 10238 AddToWorkList(FoldOp.getNode()); 10239 } 10240 10241 if (Ops.size() == LHS.getNumOperands()) 10242 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), 10243 LHS.getValueType(), &Ops[0], Ops.size()); 10244 } 10245 10246 return SDValue(); 10247} 10248 10249/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 10250SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 10251 assert(N->getValueType(0).isVector() && 10252 "SimplifyVUnaryOp only works on vectors!"); 10253 10254 SDValue N0 = N->getOperand(0); 10255 10256 if (N0.getOpcode() != ISD::BUILD_VECTOR) 10257 return SDValue(); 10258 10259 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 10260 SmallVector<SDValue, 8> Ops; 10261 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 10262 SDValue Op = N0.getOperand(i); 10263 if (Op.getOpcode() != ISD::UNDEF && 10264 Op.getOpcode() != ISD::ConstantFP) 10265 break; 10266 EVT EltVT = Op.getValueType(); 10267 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(N0), EltVT, Op); 10268 if (FoldOp.getOpcode() != ISD::UNDEF && 10269 FoldOp.getOpcode() != ISD::ConstantFP) 10270 break; 10271 Ops.push_back(FoldOp); 10272 AddToWorkList(FoldOp.getNode()); 10273 } 10274 10275 if (Ops.size() != N0.getNumOperands()) 10276 return SDValue(); 10277 10278 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), 10279 N0.getValueType(), &Ops[0], Ops.size()); 10280} 10281 10282SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0, 10283 SDValue N1, SDValue N2){ 10284 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 10285 10286 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 10287 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 10288 10289 // If we got a simplified select_cc node back from SimplifySelectCC, then 10290 // break it down into a new SETCC node, and a new SELECT node, and then return 10291 // the SELECT node, since we were called with a SELECT node. 10292 if (SCC.getNode()) { 10293 // Check to see if we got a select_cc back (to turn into setcc/select). 10294 // Otherwise, just return whatever node we got back, like fabs. 10295 if (SCC.getOpcode() == ISD::SELECT_CC) { 10296 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0), 10297 N0.getValueType(), 10298 SCC.getOperand(0), SCC.getOperand(1), 10299 SCC.getOperand(4)); 10300 AddToWorkList(SETCC.getNode()); 10301 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(), 10302 SCC.getOperand(2), SCC.getOperand(3), SETCC); 10303 } 10304 10305 return SCC; 10306 } 10307 return SDValue(); 10308} 10309 10310/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 10311/// are the two values being selected between, see if we can simplify the 10312/// select. Callers of this should assume that TheSelect is deleted if this 10313/// returns true. As such, they should return the appropriate thing (e.g. the 10314/// node) back to the top-level of the DAG combiner loop to avoid it being 10315/// looked at. 10316bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 10317 SDValue RHS) { 10318 10319 // Cannot simplify select with vector condition 10320 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 10321 10322 // If this is a select from two identical things, try to pull the operation 10323 // through the select. 10324 if (LHS.getOpcode() != RHS.getOpcode() || 10325 !LHS.hasOneUse() || !RHS.hasOneUse()) 10326 return false; 10327 10328 // If this is a load and the token chain is identical, replace the select 10329 // of two loads with a load through a select of the address to load from. 10330 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 10331 // constants have been dropped into the constant pool. 10332 if (LHS.getOpcode() == ISD::LOAD) { 10333 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 10334 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 10335 10336 // Token chains must be identical. 10337 if (LHS.getOperand(0) != RHS.getOperand(0) || 10338 // Do not let this transformation reduce the number of volatile loads. 10339 LLD->isVolatile() || RLD->isVolatile() || 10340 // If this is an EXTLOAD, the VT's must match. 10341 LLD->getMemoryVT() != RLD->getMemoryVT() || 10342 // If this is an EXTLOAD, the kind of extension must match. 10343 (LLD->getExtensionType() != RLD->getExtensionType() && 10344 // The only exception is if one of the extensions is anyext. 10345 LLD->getExtensionType() != ISD::EXTLOAD && 10346 RLD->getExtensionType() != ISD::EXTLOAD) || 10347 // FIXME: this discards src value information. This is 10348 // over-conservative. It would be beneficial to be able to remember 10349 // both potential memory locations. Since we are discarding 10350 // src value info, don't do the transformation if the memory 10351 // locations are not in the default address space. 10352 LLD->getPointerInfo().getAddrSpace() != 0 || 10353 RLD->getPointerInfo().getAddrSpace() != 0 || 10354 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), 10355 LLD->getBasePtr().getValueType())) 10356 return false; 10357 10358 // Check that the select condition doesn't reach either load. If so, 10359 // folding this will induce a cycle into the DAG. If not, this is safe to 10360 // xform, so create a select of the addresses. 10361 SDValue Addr; 10362 if (TheSelect->getOpcode() == ISD::SELECT) { 10363 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 10364 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 10365 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 10366 return false; 10367 // The loads must not depend on one another. 10368 if (LLD->isPredecessorOf(RLD) || 10369 RLD->isPredecessorOf(LLD)) 10370 return false; 10371 Addr = DAG.getSelect(SDLoc(TheSelect), 10372 LLD->getBasePtr().getValueType(), 10373 TheSelect->getOperand(0), LLD->getBasePtr(), 10374 RLD->getBasePtr()); 10375 } else { // Otherwise SELECT_CC 10376 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 10377 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 10378 10379 if ((LLD->hasAnyUseOfValue(1) && 10380 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 10381 (RLD->hasAnyUseOfValue(1) && 10382 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 10383 return false; 10384 10385 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect), 10386 LLD->getBasePtr().getValueType(), 10387 TheSelect->getOperand(0), 10388 TheSelect->getOperand(1), 10389 LLD->getBasePtr(), RLD->getBasePtr(), 10390 TheSelect->getOperand(4)); 10391 } 10392 10393 SDValue Load; 10394 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 10395 Load = DAG.getLoad(TheSelect->getValueType(0), 10396 SDLoc(TheSelect), 10397 // FIXME: Discards pointer and TBAA info. 10398 LLD->getChain(), Addr, MachinePointerInfo(), 10399 LLD->isVolatile(), LLD->isNonTemporal(), 10400 LLD->isInvariant(), LLD->getAlignment()); 10401 } else { 10402 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 10403 RLD->getExtensionType() : LLD->getExtensionType(), 10404 SDLoc(TheSelect), 10405 TheSelect->getValueType(0), 10406 // FIXME: Discards pointer and TBAA info. 10407 LLD->getChain(), Addr, MachinePointerInfo(), 10408 LLD->getMemoryVT(), LLD->isVolatile(), 10409 LLD->isNonTemporal(), LLD->getAlignment()); 10410 } 10411 10412 // Users of the select now use the result of the load. 10413 CombineTo(TheSelect, Load); 10414 10415 // Users of the old loads now use the new load's chain. We know the 10416 // old-load value is dead now. 10417 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 10418 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 10419 return true; 10420 } 10421 10422 return false; 10423} 10424 10425/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 10426/// where 'cond' is the comparison specified by CC. 10427SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, 10428 SDValue N2, SDValue N3, 10429 ISD::CondCode CC, bool NotExtCompare) { 10430 // (x ? y : y) -> y. 10431 if (N2 == N3) return N2; 10432 10433 EVT VT = N2.getValueType(); 10434 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 10435 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 10436 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 10437 10438 // Determine if the condition we're dealing with is constant 10439 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()), 10440 N0, N1, CC, DL, false); 10441 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 10442 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 10443 10444 // fold select_cc true, x, y -> x 10445 if (SCCC && !SCCC->isNullValue()) 10446 return N2; 10447 // fold select_cc false, x, y -> y 10448 if (SCCC && SCCC->isNullValue()) 10449 return N3; 10450 10451 // Check to see if we can simplify the select into an fabs node 10452 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 10453 // Allow either -0.0 or 0.0 10454 if (CFP->getValueAPF().isZero()) { 10455 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 10456 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 10457 N0 == N2 && N3.getOpcode() == ISD::FNEG && 10458 N2 == N3.getOperand(0)) 10459 return DAG.getNode(ISD::FABS, DL, VT, N0); 10460 10461 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 10462 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 10463 N0 == N3 && N2.getOpcode() == ISD::FNEG && 10464 N2.getOperand(0) == N3) 10465 return DAG.getNode(ISD::FABS, DL, VT, N3); 10466 } 10467 } 10468 10469 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 10470 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 10471 // in it. This is a win when the constant is not otherwise available because 10472 // it replaces two constant pool loads with one. We only do this if the FP 10473 // type is known to be legal, because if it isn't, then we are before legalize 10474 // types an we want the other legalization to happen first (e.g. to avoid 10475 // messing with soft float) and if the ConstantFP is not legal, because if 10476 // it is legal, we may not need to store the FP constant in a constant pool. 10477 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 10478 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 10479 if (TLI.isTypeLegal(N2.getValueType()) && 10480 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 10481 TargetLowering::Legal) && 10482 // If both constants have multiple uses, then we won't need to do an 10483 // extra load, they are likely around in registers for other users. 10484 (TV->hasOneUse() || FV->hasOneUse())) { 10485 Constant *Elts[] = { 10486 const_cast<ConstantFP*>(FV->getConstantFPValue()), 10487 const_cast<ConstantFP*>(TV->getConstantFPValue()) 10488 }; 10489 Type *FPTy = Elts[0]->getType(); 10490 const DataLayout &TD = *TLI.getDataLayout(); 10491 10492 // Create a ConstantArray of the two constants. 10493 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 10494 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 10495 TD.getPrefTypeAlignment(FPTy)); 10496 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 10497 10498 // Get the offsets to the 0 and 1 element of the array so that we can 10499 // select between them. 10500 SDValue Zero = DAG.getIntPtrConstant(0); 10501 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 10502 SDValue One = DAG.getIntPtrConstant(EltSize); 10503 10504 SDValue Cond = DAG.getSetCC(DL, 10505 getSetCCResultType(N0.getValueType()), 10506 N0, N1, CC); 10507 AddToWorkList(Cond.getNode()); 10508 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(), 10509 Cond, One, Zero); 10510 AddToWorkList(CstOffset.getNode()); 10511 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx, 10512 CstOffset); 10513 AddToWorkList(CPIdx.getNode()); 10514 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 10515 MachinePointerInfo::getConstantPool(), false, 10516 false, false, Alignment); 10517 10518 } 10519 } 10520 10521 // Check to see if we can perform the "gzip trick", transforming 10522 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 10523 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 10524 (N1C->isNullValue() || // (a < 0) ? b : 0 10525 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 10526 EVT XType = N0.getValueType(); 10527 EVT AType = N2.getValueType(); 10528 if (XType.bitsGE(AType)) { 10529 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 10530 // single-bit constant. 10531 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 10532 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 10533 ShCtV = XType.getSizeInBits()-ShCtV-1; 10534 SDValue ShCt = DAG.getConstant(ShCtV, 10535 getShiftAmountTy(N0.getValueType())); 10536 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), 10537 XType, N0, ShCt); 10538 AddToWorkList(Shift.getNode()); 10539 10540 if (XType.bitsGT(AType)) { 10541 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 10542 AddToWorkList(Shift.getNode()); 10543 } 10544 10545 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 10546 } 10547 10548 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), 10549 XType, N0, 10550 DAG.getConstant(XType.getSizeInBits()-1, 10551 getShiftAmountTy(N0.getValueType()))); 10552 AddToWorkList(Shift.getNode()); 10553 10554 if (XType.bitsGT(AType)) { 10555 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 10556 AddToWorkList(Shift.getNode()); 10557 } 10558 10559 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 10560 } 10561 } 10562 10563 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 10564 // where y is has a single bit set. 10565 // A plaintext description would be, we can turn the SELECT_CC into an AND 10566 // when the condition can be materialized as an all-ones register. Any 10567 // single bit-test can be materialized as an all-ones register with 10568 // shift-left and shift-right-arith. 10569 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 10570 N0->getValueType(0) == VT && 10571 N1C && N1C->isNullValue() && 10572 N2C && N2C->isNullValue()) { 10573 SDValue AndLHS = N0->getOperand(0); 10574 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 10575 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 10576 // Shift the tested bit over the sign bit. 10577 APInt AndMask = ConstAndRHS->getAPIntValue(); 10578 SDValue ShlAmt = 10579 DAG.getConstant(AndMask.countLeadingZeros(), 10580 getShiftAmountTy(AndLHS.getValueType())); 10581 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt); 10582 10583 // Now arithmetic right shift it all the way over, so the result is either 10584 // all-ones, or zero. 10585 SDValue ShrAmt = 10586 DAG.getConstant(AndMask.getBitWidth()-1, 10587 getShiftAmountTy(Shl.getValueType())); 10588 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt); 10589 10590 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 10591 } 10592 } 10593 10594 // fold select C, 16, 0 -> shl C, 4 10595 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 10596 TLI.getBooleanContents(N0.getValueType().isVector()) == 10597 TargetLowering::ZeroOrOneBooleanContent) { 10598 10599 // If the caller doesn't want us to simplify this into a zext of a compare, 10600 // don't do it. 10601 if (NotExtCompare && N2C->getAPIntValue() == 1) 10602 return SDValue(); 10603 10604 // Get a SetCC of the condition 10605 // NOTE: Don't create a SETCC if it's not legal on this target. 10606 if (!LegalOperations || 10607 TLI.isOperationLegal(ISD::SETCC, 10608 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) { 10609 SDValue Temp, SCC; 10610 // cast from setcc result type to select result type 10611 if (LegalTypes) { 10612 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()), 10613 N0, N1, CC); 10614 if (N2.getValueType().bitsLT(SCC.getValueType())) 10615 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2), 10616 N2.getValueType()); 10617 else 10618 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), 10619 N2.getValueType(), SCC); 10620 } else { 10621 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC); 10622 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), 10623 N2.getValueType(), SCC); 10624 } 10625 10626 AddToWorkList(SCC.getNode()); 10627 AddToWorkList(Temp.getNode()); 10628 10629 if (N2C->getAPIntValue() == 1) 10630 return Temp; 10631 10632 // shl setcc result by log2 n2c 10633 return DAG.getNode( 10634 ISD::SHL, DL, N2.getValueType(), Temp, 10635 DAG.getConstant(N2C->getAPIntValue().logBase2(), 10636 getShiftAmountTy(Temp.getValueType()))); 10637 } 10638 } 10639 10640 // Check to see if this is the equivalent of setcc 10641 // FIXME: Turn all of these into setcc if setcc if setcc is legal 10642 // otherwise, go ahead with the folds. 10643 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 10644 EVT XType = N0.getValueType(); 10645 if (!LegalOperations || 10646 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) { 10647 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC); 10648 if (Res.getValueType() != VT) 10649 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 10650 return Res; 10651 } 10652 10653 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 10654 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 10655 (!LegalOperations || 10656 TLI.isOperationLegal(ISD::CTLZ, XType))) { 10657 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0); 10658 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 10659 DAG.getConstant(Log2_32(XType.getSizeInBits()), 10660 getShiftAmountTy(Ctlz.getValueType()))); 10661 } 10662 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 10663 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 10664 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0), 10665 XType, DAG.getConstant(0, XType), N0); 10666 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType); 10667 return DAG.getNode(ISD::SRL, DL, XType, 10668 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 10669 DAG.getConstant(XType.getSizeInBits()-1, 10670 getShiftAmountTy(XType))); 10671 } 10672 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 10673 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 10674 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0, 10675 DAG.getConstant(XType.getSizeInBits()-1, 10676 getShiftAmountTy(N0.getValueType()))); 10677 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 10678 } 10679 } 10680 10681 // Check to see if this is an integer abs. 10682 // select_cc setg[te] X, 0, X, -X -> 10683 // select_cc setgt X, -1, X, -X -> 10684 // select_cc setl[te] X, 0, -X, X -> 10685 // select_cc setlt X, 1, -X, X -> 10686 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 10687 if (N1C) { 10688 ConstantSDNode *SubC = NULL; 10689 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 10690 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 10691 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 10692 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 10693 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 10694 (N1C->isOne() && CC == ISD::SETLT)) && 10695 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 10696 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 10697 10698 EVT XType = N0.getValueType(); 10699 if (SubC && SubC->isNullValue() && XType.isInteger()) { 10700 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType, 10701 N0, 10702 DAG.getConstant(XType.getSizeInBits()-1, 10703 getShiftAmountTy(N0.getValueType()))); 10704 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), 10705 XType, N0, Shift); 10706 AddToWorkList(Shift.getNode()); 10707 AddToWorkList(Add.getNode()); 10708 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 10709 } 10710 } 10711 10712 return SDValue(); 10713} 10714 10715/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 10716SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 10717 SDValue N1, ISD::CondCode Cond, 10718 SDLoc DL, bool foldBooleans) { 10719 TargetLowering::DAGCombinerInfo 10720 DagCombineInfo(DAG, Level, false, this); 10721 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 10722} 10723 10724/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 10725/// return a DAG expression to select that will generate the same value by 10726/// multiplying by a magic number. See: 10727/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 10728SDValue DAGCombiner::BuildSDIV(SDNode *N) { 10729 std::vector<SDNode*> Built; 10730 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 10731 10732 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 10733 ii != ee; ++ii) 10734 AddToWorkList(*ii); 10735 return S; 10736} 10737 10738/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 10739/// return a DAG expression to select that will generate the same value by 10740/// multiplying by a magic number. See: 10741/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 10742SDValue DAGCombiner::BuildUDIV(SDNode *N) { 10743 std::vector<SDNode*> Built; 10744 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 10745 10746 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 10747 ii != ee; ++ii) 10748 AddToWorkList(*ii); 10749 return S; 10750} 10751 10752/// FindBaseOffset - Return true if base is a frame index, which is known not 10753// to alias with anything but itself. Provides base object and offset as 10754// results. 10755static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 10756 const GlobalValue *&GV, const void *&CV) { 10757 // Assume it is a primitive operation. 10758 Base = Ptr; Offset = 0; GV = 0; CV = 0; 10759 10760 // If it's an adding a simple constant then integrate the offset. 10761 if (Base.getOpcode() == ISD::ADD) { 10762 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 10763 Base = Base.getOperand(0); 10764 Offset += C->getZExtValue(); 10765 } 10766 } 10767 10768 // Return the underlying GlobalValue, and update the Offset. Return false 10769 // for GlobalAddressSDNode since the same GlobalAddress may be represented 10770 // by multiple nodes with different offsets. 10771 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 10772 GV = G->getGlobal(); 10773 Offset += G->getOffset(); 10774 return false; 10775 } 10776 10777 // Return the underlying Constant value, and update the Offset. Return false 10778 // for ConstantSDNodes since the same constant pool entry may be represented 10779 // by multiple nodes with different offsets. 10780 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 10781 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 10782 : (const void *)C->getConstVal(); 10783 Offset += C->getOffset(); 10784 return false; 10785 } 10786 // If it's any of the following then it can't alias with anything but itself. 10787 return isa<FrameIndexSDNode>(Base); 10788} 10789 10790/// isAlias - Return true if there is any possibility that the two addresses 10791/// overlap. 10792bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, bool IsVolatile1, 10793 const Value *SrcValue1, int SrcValueOffset1, 10794 unsigned SrcValueAlign1, 10795 const MDNode *TBAAInfo1, 10796 SDValue Ptr2, int64_t Size2, bool IsVolatile2, 10797 const Value *SrcValue2, int SrcValueOffset2, 10798 unsigned SrcValueAlign2, 10799 const MDNode *TBAAInfo2) const { 10800 // If they are the same then they must be aliases. 10801 if (Ptr1 == Ptr2) return true; 10802 10803 // If they are both volatile then they cannot be reordered. 10804 if (IsVolatile1 && IsVolatile2) return true; 10805 10806 // Gather base node and offset information. 10807 SDValue Base1, Base2; 10808 int64_t Offset1, Offset2; 10809 const GlobalValue *GV1, *GV2; 10810 const void *CV1, *CV2; 10811 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 10812 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 10813 10814 // If they have a same base address then check to see if they overlap. 10815 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 10816 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 10817 10818 // It is possible for different frame indices to alias each other, mostly 10819 // when tail call optimization reuses return address slots for arguments. 10820 // To catch this case, look up the actual index of frame indices to compute 10821 // the real alias relationship. 10822 if (isFrameIndex1 && isFrameIndex2) { 10823 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 10824 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 10825 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 10826 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 10827 } 10828 10829 // Otherwise, if we know what the bases are, and they aren't identical, then 10830 // we know they cannot alias. 10831 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 10832 return false; 10833 10834 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 10835 // compared to the size and offset of the access, we may be able to prove they 10836 // do not alias. This check is conservative for now to catch cases created by 10837 // splitting vector types. 10838 if ((SrcValueAlign1 == SrcValueAlign2) && 10839 (SrcValueOffset1 != SrcValueOffset2) && 10840 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 10841 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 10842 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 10843 10844 // There is no overlap between these relatively aligned accesses of similar 10845 // size, return no alias. 10846 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 10847 return false; 10848 } 10849 10850 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0 ? CombinerGlobalAA : 10851 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA(); 10852 if (UseAA && SrcValue1 && SrcValue2) { 10853 // Use alias analysis information. 10854 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 10855 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 10856 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 10857 AliasAnalysis::AliasResult AAResult = 10858 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 10859 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 10860 if (AAResult == AliasAnalysis::NoAlias) 10861 return false; 10862 } 10863 10864 // Otherwise we have to assume they alias. 10865 return true; 10866} 10867 10868bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) { 10869 SDValue Ptr0, Ptr1; 10870 int64_t Size0, Size1; 10871 bool IsVolatile0, IsVolatile1; 10872 const Value *SrcValue0, *SrcValue1; 10873 int SrcValueOffset0, SrcValueOffset1; 10874 unsigned SrcValueAlign0, SrcValueAlign1; 10875 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1; 10876 FindAliasInfo(Op0, Ptr0, Size0, IsVolatile0, SrcValue0, SrcValueOffset0, 10877 SrcValueAlign0, SrcTBAAInfo0); 10878 FindAliasInfo(Op1, Ptr1, Size1, IsVolatile1, SrcValue1, SrcValueOffset1, 10879 SrcValueAlign1, SrcTBAAInfo1); 10880 return isAlias(Ptr0, Size0, IsVolatile0, SrcValue0, SrcValueOffset0, 10881 SrcValueAlign0, SrcTBAAInfo0, 10882 Ptr1, Size1, IsVolatile1, SrcValue1, SrcValueOffset1, 10883 SrcValueAlign1, SrcTBAAInfo1); 10884} 10885 10886/// FindAliasInfo - Extracts the relevant alias information from the memory 10887/// node. Returns true if the operand was a nonvolatile load. 10888bool DAGCombiner::FindAliasInfo(SDNode *N, 10889 SDValue &Ptr, int64_t &Size, bool &IsVolatile, 10890 const Value *&SrcValue, 10891 int &SrcValueOffset, 10892 unsigned &SrcValueAlign, 10893 const MDNode *&TBAAInfo) const { 10894 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 10895 10896 Ptr = LS->getBasePtr(); 10897 Size = LS->getMemoryVT().getSizeInBits() >> 3; 10898 IsVolatile = LS->isVolatile(); 10899 SrcValue = LS->getSrcValue(); 10900 SrcValueOffset = LS->getSrcValueOffset(); 10901 SrcValueAlign = LS->getOriginalAlignment(); 10902 TBAAInfo = LS->getTBAAInfo(); 10903 return isa<LoadSDNode>(LS) && !IsVolatile; 10904} 10905 10906/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 10907/// looking for aliasing nodes and adding them to the Aliases vector. 10908void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 10909 SmallVectorImpl<SDValue> &Aliases) { 10910 SmallVector<SDValue, 8> Chains; // List of chains to visit. 10911 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 10912 10913 // Get alias information for node. 10914 SDValue Ptr; 10915 int64_t Size; 10916 bool IsVolatile; 10917 const Value *SrcValue; 10918 int SrcValueOffset; 10919 unsigned SrcValueAlign; 10920 const MDNode *SrcTBAAInfo; 10921 bool IsLoad = FindAliasInfo(N, Ptr, Size, IsVolatile, SrcValue, 10922 SrcValueOffset, SrcValueAlign, SrcTBAAInfo); 10923 10924 // Starting off. 10925 Chains.push_back(OriginalChain); 10926 unsigned Depth = 0; 10927 10928 // Look at each chain and determine if it is an alias. If so, add it to the 10929 // aliases list. If not, then continue up the chain looking for the next 10930 // candidate. 10931 while (!Chains.empty()) { 10932 SDValue Chain = Chains.back(); 10933 Chains.pop_back(); 10934 10935 // For TokenFactor nodes, look at each operand and only continue up the 10936 // chain until we find two aliases. If we've seen two aliases, assume we'll 10937 // find more and revert to original chain since the xform is unlikely to be 10938 // profitable. 10939 // 10940 // FIXME: The depth check could be made to return the last non-aliasing 10941 // chain we found before we hit a tokenfactor rather than the original 10942 // chain. 10943 if (Depth > 6 || Aliases.size() == 2) { 10944 Aliases.clear(); 10945 Aliases.push_back(OriginalChain); 10946 break; 10947 } 10948 10949 // Don't bother if we've been before. 10950 if (!Visited.insert(Chain.getNode())) 10951 continue; 10952 10953 switch (Chain.getOpcode()) { 10954 case ISD::EntryToken: 10955 // Entry token is ideal chain operand, but handled in FindBetterChain. 10956 break; 10957 10958 case ISD::LOAD: 10959 case ISD::STORE: { 10960 // Get alias information for Chain. 10961 SDValue OpPtr; 10962 int64_t OpSize; 10963 bool OpIsVolatile; 10964 const Value *OpSrcValue; 10965 int OpSrcValueOffset; 10966 unsigned OpSrcValueAlign; 10967 const MDNode *OpSrcTBAAInfo; 10968 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 10969 OpIsVolatile, OpSrcValue, OpSrcValueOffset, 10970 OpSrcValueAlign, 10971 OpSrcTBAAInfo); 10972 10973 // If chain is alias then stop here. 10974 if (!(IsLoad && IsOpLoad) && 10975 isAlias(Ptr, Size, IsVolatile, SrcValue, SrcValueOffset, 10976 SrcValueAlign, SrcTBAAInfo, 10977 OpPtr, OpSize, OpIsVolatile, OpSrcValue, OpSrcValueOffset, 10978 OpSrcValueAlign, OpSrcTBAAInfo)) { 10979 Aliases.push_back(Chain); 10980 } else { 10981 // Look further up the chain. 10982 Chains.push_back(Chain.getOperand(0)); 10983 ++Depth; 10984 } 10985 break; 10986 } 10987 10988 case ISD::TokenFactor: 10989 // We have to check each of the operands of the token factor for "small" 10990 // token factors, so we queue them up. Adding the operands to the queue 10991 // (stack) in reverse order maintains the original order and increases the 10992 // likelihood that getNode will find a matching token factor (CSE.) 10993 if (Chain.getNumOperands() > 16) { 10994 Aliases.push_back(Chain); 10995 break; 10996 } 10997 for (unsigned n = Chain.getNumOperands(); n;) 10998 Chains.push_back(Chain.getOperand(--n)); 10999 ++Depth; 11000 break; 11001 11002 default: 11003 // For all other instructions we will just have to take what we can get. 11004 Aliases.push_back(Chain); 11005 break; 11006 } 11007 } 11008} 11009 11010/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 11011/// for a better chain (aliasing node.) 11012SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 11013 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 11014 11015 // Accumulate all the aliases to this node. 11016 GatherAllAliases(N, OldChain, Aliases); 11017 11018 // If no operands then chain to entry token. 11019 if (Aliases.size() == 0) 11020 return DAG.getEntryNode(); 11021 11022 // If a single operand then chain to it. We don't need to revisit it. 11023 if (Aliases.size() == 1) 11024 return Aliases[0]; 11025 11026 // Construct a custom tailored token factor. 11027 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, 11028 &Aliases[0], Aliases.size()); 11029} 11030 11031// SelectionDAG::Combine - This is the entry point for the file. 11032// 11033void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 11034 CodeGenOpt::Level OptLevel) { 11035 /// run - This is the main entry point to this class. 11036 /// 11037 DAGCombiner(*this, AA, OptLevel).Run(Level); 11038} 11039