DAGCombiner.cpp revision a90b3dc2f1f70ab7102ec3f1fc57f199fd56d7cc
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/Compiler.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/MathExtras.h" 39#include <algorithm> 40#include <set> 41using namespace llvm; 42 43STATISTIC(NodesCombined , "Number of dag nodes combined"); 44STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 45STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 46STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 47 48namespace { 49 static cl::opt<bool> 50 CombinerAA("combiner-alias-analysis", cl::Hidden, 51 cl::desc("Turn on alias analysis during testing")); 52 53 static cl::opt<bool> 54 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 55 cl::desc("Include global information in alias analysis")); 56 57//------------------------------ DAGCombiner ---------------------------------// 58 59 class VISIBILITY_HIDDEN DAGCombiner { 60 SelectionDAG &DAG; 61 const TargetLowering &TLI; 62 CombineLevel Level; 63 CodeGenOpt::Level OptLevel; 64 bool LegalOperations; 65 bool LegalTypes; 66 67 // Worklist of all of the nodes that need to be simplified. 68 std::vector<SDNode*> WorkList; 69 70 // AA - Used for DAG load/store alias analysis. 71 AliasAnalysis &AA; 72 73 /// AddUsersToWorkList - When an instruction is simplified, add all users of 74 /// the instruction to the work lists because they might get more simplified 75 /// now. 76 /// 77 void AddUsersToWorkList(SDNode *N) { 78 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 79 UI != UE; ++UI) 80 AddToWorkList(*UI); 81 } 82 83 /// visit - call the node-specific routine that knows how to fold each 84 /// particular type of node. 85 SDValue visit(SDNode *N); 86 87 public: 88 /// AddToWorkList - Add to the work list making sure it's instance is at the 89 /// the back (next to be processed.) 90 void AddToWorkList(SDNode *N) { 91 removeFromWorkList(N); 92 WorkList.push_back(N); 93 } 94 95 /// removeFromWorkList - remove all instances of N from the worklist. 96 /// 97 void removeFromWorkList(SDNode *N) { 98 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 99 WorkList.end()); 100 } 101 102 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 103 bool AddTo = true); 104 105 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 106 return CombineTo(N, &Res, 1, AddTo); 107 } 108 109 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 110 bool AddTo = true) { 111 SDValue To[] = { Res0, Res1 }; 112 return CombineTo(N, To, 2, AddTo); 113 } 114 115 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 116 117 private: 118 119 /// SimplifyDemandedBits - Check the specified integer node value to see if 120 /// it can be simplified or if things it uses can be simplified by bit 121 /// propagation. If so, return true. 122 bool SimplifyDemandedBits(SDValue Op) { 123 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 SDValue Ptr2, int64_t Size2, 242 const Value *SrcValue2, int SrcValueOffset2) const; 243 244 /// FindAliasInfo - Extracts the relevant alias information from the memory 245 /// node. Returns true if the operand was a load. 246 bool FindAliasInfo(SDNode *N, 247 SDValue &Ptr, int64_t &Size, 248 const Value *&SrcValue, int &SrcValueOffset) const; 249 250 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 251 /// looking for a better chain (aliasing node.) 252 SDValue FindBetterChain(SDNode *N, SDValue Chain); 253 254 /// getShiftAmountTy - Returns a type large enough to hold any valid 255 /// shift amount - before type legalization these can be huge. 256 MVT getShiftAmountTy() { 257 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 258 } 259 260public: 261 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 262 : DAG(D), 263 TLI(D.getTargetLoweringInfo()), 264 Level(Unrestricted), 265 OptLevel(OL), 266 LegalOperations(false), 267 LegalTypes(false), 268 AA(A) {} 269 270 /// Run - runs the dag combiner on all nodes in the work list 271 void Run(CombineLevel AtLevel); 272 }; 273} 274 275 276namespace { 277/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 278/// nodes from the worklist. 279class VISIBILITY_HIDDEN WorkListRemover : 280 public SelectionDAG::DAGUpdateListener { 281 DAGCombiner &DC; 282public: 283 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 284 285 virtual void NodeDeleted(SDNode *N, SDNode *E) { 286 DC.removeFromWorkList(N); 287 } 288 289 virtual void NodeUpdated(SDNode *N) { 290 // Ignore updates. 291 } 292}; 293} 294 295//===----------------------------------------------------------------------===// 296// TargetLowering::DAGCombinerInfo implementation 297//===----------------------------------------------------------------------===// 298 299void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 300 ((DAGCombiner*)DC)->AddToWorkList(N); 301} 302 303SDValue TargetLowering::DAGCombinerInfo:: 304CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 305 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 306} 307 308SDValue TargetLowering::DAGCombinerInfo:: 309CombineTo(SDNode *N, SDValue Res, bool AddTo) { 310 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 311} 312 313 314SDValue TargetLowering::DAGCombinerInfo:: 315CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 316 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 317} 318 319void TargetLowering::DAGCombinerInfo:: 320CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 321 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 322} 323 324//===----------------------------------------------------------------------===// 325// Helper Functions 326//===----------------------------------------------------------------------===// 327 328/// isNegatibleForFree - Return 1 if we can compute the negated form of the 329/// specified expression for the same cost as the expression itself, or 2 if we 330/// can compute the negated form more cheaply than the expression itself. 331static char isNegatibleForFree(SDValue Op, bool LegalOperations, 332 unsigned Depth = 0) { 333 // No compile time optimizations on this type. 334 if (Op.getValueType() == MVT::ppcf128) 335 return 0; 336 337 // fneg is removable even if it has multiple uses. 338 if (Op.getOpcode() == ISD::FNEG) return 2; 339 340 // Don't allow anything with multiple uses. 341 if (!Op.hasOneUse()) return 0; 342 343 // Don't recurse exponentially. 344 if (Depth > 6) return 0; 345 346 switch (Op.getOpcode()) { 347 default: return false; 348 case ISD::ConstantFP: 349 // Don't invert constant FP values after legalize. The negated constant 350 // isn't necessarily legal. 351 return LegalOperations ? 0 : 1; 352 case ISD::FADD: 353 // FIXME: determine better conditions for this xform. 354 if (!UnsafeFPMath) return 0; 355 356 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 357 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 358 return V; 359 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 360 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 361 case ISD::FSUB: 362 // We can't turn -(A-B) into B-A when we honor signed zeros. 363 if (!UnsafeFPMath) return 0; 364 365 // fold (fneg (fsub A, B)) -> (fsub B, A) 366 return 1; 367 368 case ISD::FMUL: 369 case ISD::FDIV: 370 if (HonorSignDependentRoundingFPMath()) return 0; 371 372 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 373 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 374 return V; 375 376 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 377 378 case ISD::FP_EXTEND: 379 case ISD::FP_ROUND: 380 case ISD::FSIN: 381 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 382 } 383} 384 385/// GetNegatedExpression - If isNegatibleForFree returns true, this function 386/// returns the newly negated expression. 387static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 388 bool LegalOperations, unsigned Depth = 0) { 389 // fneg is removable even if it has multiple uses. 390 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 391 392 // Don't allow anything with multiple uses. 393 assert(Op.hasOneUse() && "Unknown reuse!"); 394 395 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 396 switch (Op.getOpcode()) { 397 default: llvm_unreachable("Unknown code"); 398 case ISD::ConstantFP: { 399 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 400 V.changeSign(); 401 return DAG.getConstantFP(V, Op.getValueType()); 402 } 403 case ISD::FADD: 404 // FIXME: determine better conditions for this xform. 405 assert(UnsafeFPMath); 406 407 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 408 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 409 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 410 GetNegatedExpression(Op.getOperand(0), DAG, 411 LegalOperations, Depth+1), 412 Op.getOperand(1)); 413 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 414 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 415 GetNegatedExpression(Op.getOperand(1), DAG, 416 LegalOperations, Depth+1), 417 Op.getOperand(0)); 418 case ISD::FSUB: 419 // We can't turn -(A-B) into B-A when we honor signed zeros. 420 assert(UnsafeFPMath); 421 422 // fold (fneg (fsub 0, B)) -> B 423 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 424 if (N0CFP->getValueAPF().isZero()) 425 return Op.getOperand(1); 426 427 // fold (fneg (fsub A, B)) -> (fsub B, A) 428 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 429 Op.getOperand(1), Op.getOperand(0)); 430 431 case ISD::FMUL: 432 case ISD::FDIV: 433 assert(!HonorSignDependentRoundingFPMath()); 434 435 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 436 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 437 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(0), DAG, 439 LegalOperations, Depth+1), 440 Op.getOperand(1)); 441 442 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 443 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 444 Op.getOperand(0), 445 GetNegatedExpression(Op.getOperand(1), DAG, 446 LegalOperations, Depth+1)); 447 448 case ISD::FP_EXTEND: 449 case ISD::FSIN: 450 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 451 GetNegatedExpression(Op.getOperand(0), DAG, 452 LegalOperations, Depth+1)); 453 case ISD::FP_ROUND: 454 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 455 GetNegatedExpression(Op.getOperand(0), DAG, 456 LegalOperations, Depth+1), 457 Op.getOperand(1)); 458 } 459} 460 461 462// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 463// that selects between the values 1 and 0, making it equivalent to a setcc. 464// Also, set the incoming LHS, RHS, and CC references to the appropriate 465// nodes based on the type of node we are checking. This simplifies life a 466// bit for the callers. 467static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 468 SDValue &CC) { 469 if (N.getOpcode() == ISD::SETCC) { 470 LHS = N.getOperand(0); 471 RHS = N.getOperand(1); 472 CC = N.getOperand(2); 473 return true; 474 } 475 if (N.getOpcode() == ISD::SELECT_CC && 476 N.getOperand(2).getOpcode() == ISD::Constant && 477 N.getOperand(3).getOpcode() == ISD::Constant && 478 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 479 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 480 LHS = N.getOperand(0); 481 RHS = N.getOperand(1); 482 CC = N.getOperand(4); 483 return true; 484 } 485 return false; 486} 487 488// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 489// one use. If this is true, it allows the users to invert the operation for 490// free when it is profitable to do so. 491static bool isOneUseSetCC(SDValue N) { 492 SDValue N0, N1, N2; 493 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 494 return true; 495 return false; 496} 497 498SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 499 SDValue N0, SDValue N1) { 500 MVT VT = N0.getValueType(); 501 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 502 if (isa<ConstantSDNode>(N1)) { 503 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 504 SDValue OpNode = 505 DAG.FoldConstantArithmetic(Opc, VT, 506 cast<ConstantSDNode>(N0.getOperand(1)), 507 cast<ConstantSDNode>(N1)); 508 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 509 } else if (N0.hasOneUse()) { 510 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 511 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 512 N0.getOperand(0), N1); 513 AddToWorkList(OpNode.getNode()); 514 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 515 } 516 } 517 518 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 519 if (isa<ConstantSDNode>(N0)) { 520 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 521 SDValue OpNode = 522 DAG.FoldConstantArithmetic(Opc, VT, 523 cast<ConstantSDNode>(N1.getOperand(1)), 524 cast<ConstantSDNode>(N0)); 525 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 526 } else if (N1.hasOneUse()) { 527 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 528 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 529 N1.getOperand(0), N0); 530 AddToWorkList(OpNode.getNode()); 531 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 532 } 533 } 534 535 return SDValue(); 536} 537 538SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 539 bool AddTo) { 540 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 541 ++NodesCombined; 542 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 543 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 544 DOUT << " and " << NumTo-1 << " other values\n"; 545 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 546 assert(N->getValueType(i) == To[i].getValueType() && 547 "Cannot combine value to value of different type!")); 548 WorkListRemover DeadNodes(*this); 549 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 550 551 if (AddTo) { 552 // Push the new nodes and any users onto the worklist 553 for (unsigned i = 0, e = NumTo; i != e; ++i) { 554 if (To[i].getNode()) { 555 AddToWorkList(To[i].getNode()); 556 AddUsersToWorkList(To[i].getNode()); 557 } 558 } 559 } 560 561 // Finally, if the node is now dead, remove it from the graph. The node 562 // may not be dead if the replacement process recursively simplified to 563 // something else needing this node. 564 if (N->use_empty()) { 565 // Nodes can be reintroduced into the worklist. Make sure we do not 566 // process a node that has been replaced. 567 removeFromWorkList(N); 568 569 // Finally, since the node is now dead, remove it from the graph. 570 DAG.DeleteNode(N); 571 } 572 return SDValue(N, 0); 573} 574 575void 576DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 577 TLO) { 578 // Replace all uses. If any nodes become isomorphic to other nodes and 579 // are deleted, make sure to remove them from our worklist. 580 WorkListRemover DeadNodes(*this); 581 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 582 583 // Push the new node and any (possibly new) users onto the worklist. 584 AddToWorkList(TLO.New.getNode()); 585 AddUsersToWorkList(TLO.New.getNode()); 586 587 // Finally, if the node is now dead, remove it from the graph. The node 588 // may not be dead if the replacement process recursively simplified to 589 // something else needing this node. 590 if (TLO.Old.getNode()->use_empty()) { 591 removeFromWorkList(TLO.Old.getNode()); 592 593 // If the operands of this node are only used by the node, they will now 594 // be dead. Make sure to visit them first to delete dead nodes early. 595 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 596 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 597 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 598 599 DAG.DeleteNode(TLO.Old.getNode()); 600 } 601} 602 603/// SimplifyDemandedBits - Check the specified integer node value to see if 604/// it can be simplified or if things it uses can be simplified by bit 605/// propagation. If so, return true. 606bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 607 TargetLowering::TargetLoweringOpt TLO(DAG); 608 APInt KnownZero, KnownOne; 609 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 610 return false; 611 612 // Revisit the node. 613 AddToWorkList(Op.getNode()); 614 615 // Replace the old value with the new one. 616 ++NodesCombined; 617 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 618 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 619 DOUT << '\n'; 620 621 CommitTargetLoweringOpt(TLO); 622 return true; 623} 624 625//===----------------------------------------------------------------------===// 626// Main DAG Combiner implementation 627//===----------------------------------------------------------------------===// 628 629void DAGCombiner::Run(CombineLevel AtLevel) { 630 // set the instance variables, so that the various visit routines may use it. 631 Level = AtLevel; 632 LegalOperations = Level >= NoIllegalOperations; 633 LegalTypes = Level >= NoIllegalTypes; 634 635 // Add all the dag nodes to the worklist. 636 WorkList.reserve(DAG.allnodes_size()); 637 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 638 E = DAG.allnodes_end(); I != E; ++I) 639 WorkList.push_back(I); 640 641 // Create a dummy node (which is not added to allnodes), that adds a reference 642 // to the root node, preventing it from being deleted, and tracking any 643 // changes of the root. 644 HandleSDNode Dummy(DAG.getRoot()); 645 646 // The root of the dag may dangle to deleted nodes until the dag combiner is 647 // done. Set it to null to avoid confusion. 648 DAG.setRoot(SDValue()); 649 650 // while the worklist isn't empty, inspect the node on the end of it and 651 // try and combine it. 652 while (!WorkList.empty()) { 653 SDNode *N = WorkList.back(); 654 WorkList.pop_back(); 655 656 // If N has no uses, it is dead. Make sure to revisit all N's operands once 657 // N is deleted from the DAG, since they too may now be dead or may have a 658 // reduced number of uses, allowing other xforms. 659 if (N->use_empty() && N != &Dummy) { 660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 661 AddToWorkList(N->getOperand(i).getNode()); 662 663 DAG.DeleteNode(N); 664 continue; 665 } 666 667 SDValue RV = combine(N); 668 669 if (RV.getNode() == 0) 670 continue; 671 672 ++NodesCombined; 673 674 // If we get back the same node we passed in, rather than a new node or 675 // zero, we know that the node must have defined multiple values and 676 // CombineTo was used. Since CombineTo takes care of the worklist 677 // mechanics for us, we have no work to do in this case. 678 if (RV.getNode() == N) 679 continue; 680 681 assert(N->getOpcode() != ISD::DELETED_NODE && 682 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 683 "Node was deleted but visit returned new node!"); 684 685 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 686 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 687 DOUT << '\n'; 688 WorkListRemover DeadNodes(*this); 689 if (N->getNumValues() == RV.getNode()->getNumValues()) 690 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 691 else { 692 assert(N->getValueType(0) == RV.getValueType() && 693 N->getNumValues() == 1 && "Type mismatch"); 694 SDValue OpV = RV; 695 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 696 } 697 698 // Push the new node and any users onto the worklist 699 AddToWorkList(RV.getNode()); 700 AddUsersToWorkList(RV.getNode()); 701 702 // Add any uses of the old node to the worklist in case this node is the 703 // last one that uses them. They may become dead after this node is 704 // deleted. 705 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 706 AddToWorkList(N->getOperand(i).getNode()); 707 708 // Finally, if the node is now dead, remove it from the graph. The node 709 // may not be dead if the replacement process recursively simplified to 710 // something else needing this node. 711 if (N->use_empty()) { 712 // Nodes can be reintroduced into the worklist. Make sure we do not 713 // process a node that has been replaced. 714 removeFromWorkList(N); 715 716 // Finally, since the node is now dead, remove it from the graph. 717 DAG.DeleteNode(N); 718 } 719 } 720 721 // If the root changed (e.g. it was a dead load, update the root). 722 DAG.setRoot(Dummy.getValue()); 723} 724 725SDValue DAGCombiner::visit(SDNode *N) { 726 switch(N->getOpcode()) { 727 default: break; 728 case ISD::TokenFactor: return visitTokenFactor(N); 729 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 730 case ISD::ADD: return visitADD(N); 731 case ISD::SUB: return visitSUB(N); 732 case ISD::ADDC: return visitADDC(N); 733 case ISD::ADDE: return visitADDE(N); 734 case ISD::MUL: return visitMUL(N); 735 case ISD::SDIV: return visitSDIV(N); 736 case ISD::UDIV: return visitUDIV(N); 737 case ISD::SREM: return visitSREM(N); 738 case ISD::UREM: return visitUREM(N); 739 case ISD::MULHU: return visitMULHU(N); 740 case ISD::MULHS: return visitMULHS(N); 741 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 742 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 743 case ISD::SDIVREM: return visitSDIVREM(N); 744 case ISD::UDIVREM: return visitUDIVREM(N); 745 case ISD::AND: return visitAND(N); 746 case ISD::OR: return visitOR(N); 747 case ISD::XOR: return visitXOR(N); 748 case ISD::SHL: return visitSHL(N); 749 case ISD::SRA: return visitSRA(N); 750 case ISD::SRL: return visitSRL(N); 751 case ISD::CTLZ: return visitCTLZ(N); 752 case ISD::CTTZ: return visitCTTZ(N); 753 case ISD::CTPOP: return visitCTPOP(N); 754 case ISD::SELECT: return visitSELECT(N); 755 case ISD::SELECT_CC: return visitSELECT_CC(N); 756 case ISD::SETCC: return visitSETCC(N); 757 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 758 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 759 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 760 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 761 case ISD::TRUNCATE: return visitTRUNCATE(N); 762 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 763 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 764 case ISD::FADD: return visitFADD(N); 765 case ISD::FSUB: return visitFSUB(N); 766 case ISD::FMUL: return visitFMUL(N); 767 case ISD::FDIV: return visitFDIV(N); 768 case ISD::FREM: return visitFREM(N); 769 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 770 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 771 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 772 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 773 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 774 case ISD::FP_ROUND: return visitFP_ROUND(N); 775 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 776 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 777 case ISD::FNEG: return visitFNEG(N); 778 case ISD::FABS: return visitFABS(N); 779 case ISD::BRCOND: return visitBRCOND(N); 780 case ISD::BR_CC: return visitBR_CC(N); 781 case ISD::LOAD: return visitLOAD(N); 782 case ISD::STORE: return visitSTORE(N); 783 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 784 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 785 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 786 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 787 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 788 } 789 return SDValue(); 790} 791 792SDValue DAGCombiner::combine(SDNode *N) { 793 SDValue RV = visit(N); 794 795 // If nothing happened, try a target-specific DAG combine. 796 if (RV.getNode() == 0) { 797 assert(N->getOpcode() != ISD::DELETED_NODE && 798 "Node was deleted but visit returned NULL!"); 799 800 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 801 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 802 803 // Expose the DAG combiner to the target combiner impls. 804 TargetLowering::DAGCombinerInfo 805 DagCombineInfo(DAG, Level == Unrestricted, false, this); 806 807 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 808 } 809 } 810 811 // If N is a commutative binary node, try commuting it to enable more 812 // sdisel CSE. 813 if (RV.getNode() == 0 && 814 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 815 N->getNumValues() == 1) { 816 SDValue N0 = N->getOperand(0); 817 SDValue N1 = N->getOperand(1); 818 819 // Constant operands are canonicalized to RHS. 820 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 821 SDValue Ops[] = { N1, N0 }; 822 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 823 Ops, 2); 824 if (CSENode) 825 return SDValue(CSENode, 0); 826 } 827 } 828 829 return RV; 830} 831 832/// getInputChainForNode - Given a node, return its input chain if it has one, 833/// otherwise return a null sd operand. 834static SDValue getInputChainForNode(SDNode *N) { 835 if (unsigned NumOps = N->getNumOperands()) { 836 if (N->getOperand(0).getValueType() == MVT::Other) 837 return N->getOperand(0); 838 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 839 return N->getOperand(NumOps-1); 840 for (unsigned i = 1; i < NumOps-1; ++i) 841 if (N->getOperand(i).getValueType() == MVT::Other) 842 return N->getOperand(i); 843 } 844 return SDValue(); 845} 846 847SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 848 // If N has two operands, where one has an input chain equal to the other, 849 // the 'other' chain is redundant. 850 if (N->getNumOperands() == 2) { 851 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 852 return N->getOperand(0); 853 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 854 return N->getOperand(1); 855 } 856 857 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 858 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 859 SmallPtrSet<SDNode*, 16> SeenOps; 860 bool Changed = false; // If we should replace this token factor. 861 862 // Start out with this token factor. 863 TFs.push_back(N); 864 865 // Iterate through token factors. The TFs grows when new token factors are 866 // encountered. 867 for (unsigned i = 0; i < TFs.size(); ++i) { 868 SDNode *TF = TFs[i]; 869 870 // Check each of the operands. 871 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 872 SDValue Op = TF->getOperand(i); 873 874 switch (Op.getOpcode()) { 875 case ISD::EntryToken: 876 // Entry tokens don't need to be added to the list. They are 877 // rededundant. 878 Changed = true; 879 break; 880 881 case ISD::TokenFactor: 882 if ((CombinerAA || Op.hasOneUse()) && 883 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 884 // Queue up for processing. 885 TFs.push_back(Op.getNode()); 886 // Clean up in case the token factor is removed. 887 AddToWorkList(Op.getNode()); 888 Changed = true; 889 break; 890 } 891 // Fall thru 892 893 default: 894 // Only add if it isn't already in the list. 895 if (SeenOps.insert(Op.getNode())) 896 Ops.push_back(Op); 897 else 898 Changed = true; 899 break; 900 } 901 } 902 } 903 904 SDValue Result; 905 906 // If we've change things around then replace token factor. 907 if (Changed) { 908 if (Ops.empty()) { 909 // The entry token is the only possible outcome. 910 Result = DAG.getEntryNode(); 911 } else { 912 // New and improved token factor. 913 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 914 MVT::Other, &Ops[0], Ops.size()); 915 } 916 917 // Don't add users to work list. 918 return CombineTo(N, Result, false); 919 } 920 921 return Result; 922} 923 924/// MERGE_VALUES can always be eliminated. 925SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 926 WorkListRemover DeadNodes(*this); 927 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 928 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 929 &DeadNodes); 930 removeFromWorkList(N); 931 DAG.DeleteNode(N); 932 return SDValue(N, 0); // Return N so it doesn't get rechecked! 933} 934 935static 936SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 937 SelectionDAG &DAG) { 938 MVT VT = N0.getValueType(); 939 SDValue N00 = N0.getOperand(0); 940 SDValue N01 = N0.getOperand(1); 941 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 942 943 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 944 isa<ConstantSDNode>(N00.getOperand(1))) { 945 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 946 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 947 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 948 N00.getOperand(0), N01), 949 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 950 N00.getOperand(1), N01)); 951 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 952 } 953 954 return SDValue(); 955} 956 957SDValue DAGCombiner::visitADD(SDNode *N) { 958 SDValue N0 = N->getOperand(0); 959 SDValue N1 = N->getOperand(1); 960 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 961 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 962 MVT VT = N0.getValueType(); 963 964 // fold vector ops 965 if (VT.isVector()) { 966 SDValue FoldedVOp = SimplifyVBinOp(N); 967 if (FoldedVOp.getNode()) return FoldedVOp; 968 } 969 970 // fold (add x, undef) -> undef 971 if (N0.getOpcode() == ISD::UNDEF) 972 return N0; 973 if (N1.getOpcode() == ISD::UNDEF) 974 return N1; 975 // fold (add c1, c2) -> c1+c2 976 if (N0C && N1C) 977 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 978 // canonicalize constant to RHS 979 if (N0C && !N1C) 980 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 981 // fold (add x, 0) -> x 982 if (N1C && N1C->isNullValue()) 983 return N0; 984 // fold (add Sym, c) -> Sym+c 985 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 986 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 987 GA->getOpcode() == ISD::GlobalAddress) 988 return DAG.getGlobalAddress(GA->getGlobal(), VT, 989 GA->getOffset() + 990 (uint64_t)N1C->getSExtValue()); 991 // fold ((c1-A)+c2) -> (c1+c2)-A 992 if (N1C && N0.getOpcode() == ISD::SUB) 993 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 994 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 995 DAG.getConstant(N1C->getAPIntValue()+ 996 N0C->getAPIntValue(), VT), 997 N0.getOperand(1)); 998 // reassociate add 999 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1000 if (RADD.getNode() != 0) 1001 return RADD; 1002 // fold ((0-A) + B) -> B-A 1003 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1004 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1005 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1006 // fold (A + (0-B)) -> A-B 1007 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1008 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1009 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1010 // fold (A+(B-A)) -> B 1011 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1012 return N1.getOperand(0); 1013 // fold ((B-A)+A) -> B 1014 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1015 return N0.getOperand(0); 1016 // fold (A+(B-(A+C))) to (B-C) 1017 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1018 N0 == N1.getOperand(1).getOperand(0)) 1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1020 N1.getOperand(1).getOperand(1)); 1021 // fold (A+(B-(C+A))) to (B-C) 1022 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1023 N0 == N1.getOperand(1).getOperand(1)) 1024 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1025 N1.getOperand(1).getOperand(0)); 1026 // fold (A+((B-A)+or-C)) to (B+or-C) 1027 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1028 N1.getOperand(0).getOpcode() == ISD::SUB && 1029 N0 == N1.getOperand(0).getOperand(1)) 1030 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1031 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1032 1033 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1034 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1035 SDValue N00 = N0.getOperand(0); 1036 SDValue N01 = N0.getOperand(1); 1037 SDValue N10 = N1.getOperand(0); 1038 SDValue N11 = N1.getOperand(1); 1039 1040 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1041 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1042 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1043 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1044 } 1045 1046 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1047 return SDValue(N, 0); 1048 1049 // fold (a+b) -> (a|b) iff a and b share no bits. 1050 if (VT.isInteger() && !VT.isVector()) { 1051 APInt LHSZero, LHSOne; 1052 APInt RHSZero, RHSOne; 1053 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1054 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1055 1056 if (LHSZero.getBoolValue()) { 1057 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1058 1059 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1060 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1061 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1062 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1063 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1064 } 1065 } 1066 1067 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1068 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1069 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1070 if (Result.getNode()) return Result; 1071 } 1072 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1073 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1074 if (Result.getNode()) return Result; 1075 } 1076 1077 return SDValue(); 1078} 1079 1080SDValue DAGCombiner::visitADDC(SDNode *N) { 1081 SDValue N0 = N->getOperand(0); 1082 SDValue N1 = N->getOperand(1); 1083 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1085 MVT VT = N0.getValueType(); 1086 1087 // If the flag result is dead, turn this into an ADD. 1088 if (N->hasNUsesOfValue(0, 1)) 1089 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1090 DAG.getNode(ISD::CARRY_FALSE, 1091 N->getDebugLoc(), MVT::Flag)); 1092 1093 // canonicalize constant to RHS. 1094 if (N0C && !N1C) 1095 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1096 1097 // fold (addc x, 0) -> x + no carry out 1098 if (N1C && N1C->isNullValue()) 1099 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1100 N->getDebugLoc(), MVT::Flag)); 1101 1102 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1103 APInt LHSZero, LHSOne; 1104 APInt RHSZero, RHSOne; 1105 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1106 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1107 1108 if (LHSZero.getBoolValue()) { 1109 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1110 1111 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1112 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1113 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1114 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1115 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1116 DAG.getNode(ISD::CARRY_FALSE, 1117 N->getDebugLoc(), MVT::Flag)); 1118 } 1119 1120 return SDValue(); 1121} 1122 1123SDValue DAGCombiner::visitADDE(SDNode *N) { 1124 SDValue N0 = N->getOperand(0); 1125 SDValue N1 = N->getOperand(1); 1126 SDValue CarryIn = N->getOperand(2); 1127 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1128 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1129 1130 // canonicalize constant to RHS 1131 if (N0C && !N1C) 1132 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1133 N1, N0, CarryIn); 1134 1135 // fold (adde x, y, false) -> (addc x, y) 1136 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1137 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1138 1139 return SDValue(); 1140} 1141 1142SDValue DAGCombiner::visitSUB(SDNode *N) { 1143 SDValue N0 = N->getOperand(0); 1144 SDValue N1 = N->getOperand(1); 1145 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1146 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1147 MVT VT = N0.getValueType(); 1148 1149 // fold vector ops 1150 if (VT.isVector()) { 1151 SDValue FoldedVOp = SimplifyVBinOp(N); 1152 if (FoldedVOp.getNode()) return FoldedVOp; 1153 } 1154 1155 // fold (sub x, x) -> 0 1156 if (N0 == N1) 1157 return DAG.getConstant(0, N->getValueType(0)); 1158 // fold (sub c1, c2) -> c1-c2 1159 if (N0C && N1C) 1160 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1161 // fold (sub x, c) -> (add x, -c) 1162 if (N1C) 1163 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1164 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1165 // fold (A+B)-A -> B 1166 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1167 return N0.getOperand(1); 1168 // fold (A+B)-B -> A 1169 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1170 return N0.getOperand(0); 1171 // fold ((A+(B+or-C))-B) -> A+or-C 1172 if (N0.getOpcode() == ISD::ADD && 1173 (N0.getOperand(1).getOpcode() == ISD::SUB || 1174 N0.getOperand(1).getOpcode() == ISD::ADD) && 1175 N0.getOperand(1).getOperand(0) == N1) 1176 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1177 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1178 // fold ((A+(C+B))-B) -> A+C 1179 if (N0.getOpcode() == ISD::ADD && 1180 N0.getOperand(1).getOpcode() == ISD::ADD && 1181 N0.getOperand(1).getOperand(1) == N1) 1182 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1183 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1184 // fold ((A-(B-C))-C) -> A-B 1185 if (N0.getOpcode() == ISD::SUB && 1186 N0.getOperand(1).getOpcode() == ISD::SUB && 1187 N0.getOperand(1).getOperand(1) == N1) 1188 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1189 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1190 1191 // If either operand of a sub is undef, the result is undef 1192 if (N0.getOpcode() == ISD::UNDEF) 1193 return N0; 1194 if (N1.getOpcode() == ISD::UNDEF) 1195 return N1; 1196 1197 // If the relocation model supports it, consider symbol offsets. 1198 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1199 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1200 // fold (sub Sym, c) -> Sym-c 1201 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1202 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1203 GA->getOffset() - 1204 (uint64_t)N1C->getSExtValue()); 1205 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1206 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1207 if (GA->getGlobal() == GB->getGlobal()) 1208 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1209 VT); 1210 } 1211 1212 return SDValue(); 1213} 1214 1215SDValue DAGCombiner::visitMUL(SDNode *N) { 1216 SDValue N0 = N->getOperand(0); 1217 SDValue N1 = N->getOperand(1); 1218 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1219 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1220 MVT VT = N0.getValueType(); 1221 1222 // fold vector ops 1223 if (VT.isVector()) { 1224 SDValue FoldedVOp = SimplifyVBinOp(N); 1225 if (FoldedVOp.getNode()) return FoldedVOp; 1226 } 1227 1228 // fold (mul x, undef) -> 0 1229 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1230 return DAG.getConstant(0, VT); 1231 // fold (mul c1, c2) -> c1*c2 1232 if (N0C && N1C) 1233 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1234 // canonicalize constant to RHS 1235 if (N0C && !N1C) 1236 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1237 // fold (mul x, 0) -> 0 1238 if (N1C && N1C->isNullValue()) 1239 return N1; 1240 // fold (mul x, -1) -> 0-x 1241 if (N1C && N1C->isAllOnesValue()) 1242 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1243 DAG.getConstant(0, VT), N0); 1244 // fold (mul x, (1 << c)) -> x << c 1245 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1246 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1247 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1248 getShiftAmountTy())); 1249 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1250 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1251 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1252 // FIXME: If the input is something that is easily negated (e.g. a 1253 // single-use add), we should put the negate there. 1254 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1255 DAG.getConstant(0, VT), 1256 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1257 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1258 } 1259 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1260 if (N1C && N0.getOpcode() == ISD::SHL && 1261 isa<ConstantSDNode>(N0.getOperand(1))) { 1262 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1263 N1, N0.getOperand(1)); 1264 AddToWorkList(C3.getNode()); 1265 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1266 N0.getOperand(0), C3); 1267 } 1268 1269 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1270 // use. 1271 { 1272 SDValue Sh(0,0), Y(0,0); 1273 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1274 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1275 N0.getNode()->hasOneUse()) { 1276 Sh = N0; Y = N1; 1277 } else if (N1.getOpcode() == ISD::SHL && 1278 isa<ConstantSDNode>(N1.getOperand(1)) && 1279 N1.getNode()->hasOneUse()) { 1280 Sh = N1; Y = N0; 1281 } 1282 1283 if (Sh.getNode()) { 1284 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1285 Sh.getOperand(0), Y); 1286 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1287 Mul, Sh.getOperand(1)); 1288 } 1289 } 1290 1291 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1292 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1293 isa<ConstantSDNode>(N0.getOperand(1))) 1294 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1295 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1296 N0.getOperand(0), N1), 1297 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1298 N0.getOperand(1), N1)); 1299 1300 // reassociate mul 1301 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1302 if (RMUL.getNode() != 0) 1303 return RMUL; 1304 1305 return SDValue(); 1306} 1307 1308SDValue DAGCombiner::visitSDIV(SDNode *N) { 1309 SDValue N0 = N->getOperand(0); 1310 SDValue N1 = N->getOperand(1); 1311 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1312 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1313 MVT VT = N->getValueType(0); 1314 1315 // fold vector ops 1316 if (VT.isVector()) { 1317 SDValue FoldedVOp = SimplifyVBinOp(N); 1318 if (FoldedVOp.getNode()) return FoldedVOp; 1319 } 1320 1321 // fold (sdiv c1, c2) -> c1/c2 1322 if (N0C && N1C && !N1C->isNullValue()) 1323 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1324 // fold (sdiv X, 1) -> X 1325 if (N1C && N1C->getSExtValue() == 1LL) 1326 return N0; 1327 // fold (sdiv X, -1) -> 0-X 1328 if (N1C && N1C->isAllOnesValue()) 1329 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1330 DAG.getConstant(0, VT), N0); 1331 // If we know the sign bits of both operands are zero, strength reduce to a 1332 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1333 if (!VT.isVector()) { 1334 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1335 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1336 N0, N1); 1337 } 1338 // fold (sdiv X, pow2) -> simple ops after legalize 1339 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1340 (isPowerOf2_64(N1C->getSExtValue()) || 1341 isPowerOf2_64(-N1C->getSExtValue()))) { 1342 // If dividing by powers of two is cheap, then don't perform the following 1343 // fold. 1344 if (TLI.isPow2DivCheap()) 1345 return SDValue(); 1346 1347 int64_t pow2 = N1C->getSExtValue(); 1348 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1349 unsigned lg2 = Log2_64(abs2); 1350 1351 // Splat the sign bit into the register 1352 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1353 DAG.getConstant(VT.getSizeInBits()-1, 1354 getShiftAmountTy())); 1355 AddToWorkList(SGN.getNode()); 1356 1357 // Add (N0 < 0) ? abs2 - 1 : 0; 1358 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1359 DAG.getConstant(VT.getSizeInBits() - lg2, 1360 getShiftAmountTy())); 1361 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1362 AddToWorkList(SRL.getNode()); 1363 AddToWorkList(ADD.getNode()); // Divide by pow2 1364 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1365 DAG.getConstant(lg2, getShiftAmountTy())); 1366 1367 // If we're dividing by a positive value, we're done. Otherwise, we must 1368 // negate the result. 1369 if (pow2 > 0) 1370 return SRA; 1371 1372 AddToWorkList(SRA.getNode()); 1373 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1374 DAG.getConstant(0, VT), SRA); 1375 } 1376 1377 // if integer divide is expensive and we satisfy the requirements, emit an 1378 // alternate sequence. 1379 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1380 !TLI.isIntDivCheap()) { 1381 SDValue Op = BuildSDIV(N); 1382 if (Op.getNode()) return Op; 1383 } 1384 1385 // undef / X -> 0 1386 if (N0.getOpcode() == ISD::UNDEF) 1387 return DAG.getConstant(0, VT); 1388 // X / undef -> undef 1389 if (N1.getOpcode() == ISD::UNDEF) 1390 return N1; 1391 1392 return SDValue(); 1393} 1394 1395SDValue DAGCombiner::visitUDIV(SDNode *N) { 1396 SDValue N0 = N->getOperand(0); 1397 SDValue N1 = N->getOperand(1); 1398 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1400 MVT VT = N->getValueType(0); 1401 1402 // fold vector ops 1403 if (VT.isVector()) { 1404 SDValue FoldedVOp = SimplifyVBinOp(N); 1405 if (FoldedVOp.getNode()) return FoldedVOp; 1406 } 1407 1408 // fold (udiv c1, c2) -> c1/c2 1409 if (N0C && N1C && !N1C->isNullValue()) 1410 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1411 // fold (udiv x, (1 << c)) -> x >>u c 1412 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1413 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1414 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1415 getShiftAmountTy())); 1416 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1417 if (N1.getOpcode() == ISD::SHL) { 1418 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1419 if (SHC->getAPIntValue().isPowerOf2()) { 1420 MVT ADDVT = N1.getOperand(1).getValueType(); 1421 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1422 N1.getOperand(1), 1423 DAG.getConstant(SHC->getAPIntValue() 1424 .logBase2(), 1425 ADDVT)); 1426 AddToWorkList(Add.getNode()); 1427 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1428 } 1429 } 1430 } 1431 // fold (udiv x, c) -> alternate 1432 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1433 SDValue Op = BuildUDIV(N); 1434 if (Op.getNode()) return Op; 1435 } 1436 1437 // undef / X -> 0 1438 if (N0.getOpcode() == ISD::UNDEF) 1439 return DAG.getConstant(0, VT); 1440 // X / undef -> undef 1441 if (N1.getOpcode() == ISD::UNDEF) 1442 return N1; 1443 1444 return SDValue(); 1445} 1446 1447SDValue DAGCombiner::visitSREM(SDNode *N) { 1448 SDValue N0 = N->getOperand(0); 1449 SDValue N1 = N->getOperand(1); 1450 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1451 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1452 MVT VT = N->getValueType(0); 1453 1454 // fold (srem c1, c2) -> c1%c2 1455 if (N0C && N1C && !N1C->isNullValue()) 1456 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1457 // If we know the sign bits of both operands are zero, strength reduce to a 1458 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1459 if (!VT.isVector()) { 1460 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1461 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1462 } 1463 1464 // If X/C can be simplified by the division-by-constant logic, lower 1465 // X%C to the equivalent of X-X/C*C. 1466 if (N1C && !N1C->isNullValue()) { 1467 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1468 AddToWorkList(Div.getNode()); 1469 SDValue OptimizedDiv = combine(Div.getNode()); 1470 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1471 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1472 OptimizedDiv, N1); 1473 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1474 AddToWorkList(Mul.getNode()); 1475 return Sub; 1476 } 1477 } 1478 1479 // undef % X -> 0 1480 if (N0.getOpcode() == ISD::UNDEF) 1481 return DAG.getConstant(0, VT); 1482 // X % undef -> undef 1483 if (N1.getOpcode() == ISD::UNDEF) 1484 return N1; 1485 1486 return SDValue(); 1487} 1488 1489SDValue DAGCombiner::visitUREM(SDNode *N) { 1490 SDValue N0 = N->getOperand(0); 1491 SDValue N1 = N->getOperand(1); 1492 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1493 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1494 MVT VT = N->getValueType(0); 1495 1496 // fold (urem c1, c2) -> c1%c2 1497 if (N0C && N1C && !N1C->isNullValue()) 1498 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1499 // fold (urem x, pow2) -> (and x, pow2-1) 1500 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1501 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1502 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1503 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1504 if (N1.getOpcode() == ISD::SHL) { 1505 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1506 if (SHC->getAPIntValue().isPowerOf2()) { 1507 SDValue Add = 1508 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1509 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1510 VT)); 1511 AddToWorkList(Add.getNode()); 1512 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1513 } 1514 } 1515 } 1516 1517 // If X/C can be simplified by the division-by-constant logic, lower 1518 // X%C to the equivalent of X-X/C*C. 1519 if (N1C && !N1C->isNullValue()) { 1520 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1521 AddToWorkList(Div.getNode()); 1522 SDValue OptimizedDiv = combine(Div.getNode()); 1523 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1524 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1525 OptimizedDiv, N1); 1526 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1527 AddToWorkList(Mul.getNode()); 1528 return Sub; 1529 } 1530 } 1531 1532 // undef % X -> 0 1533 if (N0.getOpcode() == ISD::UNDEF) 1534 return DAG.getConstant(0, VT); 1535 // X % undef -> undef 1536 if (N1.getOpcode() == ISD::UNDEF) 1537 return N1; 1538 1539 return SDValue(); 1540} 1541 1542SDValue DAGCombiner::visitMULHS(SDNode *N) { 1543 SDValue N0 = N->getOperand(0); 1544 SDValue N1 = N->getOperand(1); 1545 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1546 MVT VT = N->getValueType(0); 1547 1548 // fold (mulhs x, 0) -> 0 1549 if (N1C && N1C->isNullValue()) 1550 return N1; 1551 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1552 if (N1C && N1C->getAPIntValue() == 1) 1553 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1554 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1555 getShiftAmountTy())); 1556 // fold (mulhs x, undef) -> 0 1557 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1558 return DAG.getConstant(0, VT); 1559 1560 return SDValue(); 1561} 1562 1563SDValue DAGCombiner::visitMULHU(SDNode *N) { 1564 SDValue N0 = N->getOperand(0); 1565 SDValue N1 = N->getOperand(1); 1566 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1567 MVT VT = N->getValueType(0); 1568 1569 // fold (mulhu x, 0) -> 0 1570 if (N1C && N1C->isNullValue()) 1571 return N1; 1572 // fold (mulhu x, 1) -> 0 1573 if (N1C && N1C->getAPIntValue() == 1) 1574 return DAG.getConstant(0, N0.getValueType()); 1575 // fold (mulhu x, undef) -> 0 1576 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1577 return DAG.getConstant(0, VT); 1578 1579 return SDValue(); 1580} 1581 1582/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1583/// compute two values. LoOp and HiOp give the opcodes for the two computations 1584/// that are being performed. Return true if a simplification was made. 1585/// 1586SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1587 unsigned HiOp) { 1588 // If the high half is not needed, just compute the low half. 1589 bool HiExists = N->hasAnyUseOfValue(1); 1590 if (!HiExists && 1591 (!LegalOperations || 1592 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1593 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1594 N->op_begin(), N->getNumOperands()); 1595 return CombineTo(N, Res, Res); 1596 } 1597 1598 // If the low half is not needed, just compute the high half. 1599 bool LoExists = N->hasAnyUseOfValue(0); 1600 if (!LoExists && 1601 (!LegalOperations || 1602 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1603 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1604 N->op_begin(), N->getNumOperands()); 1605 return CombineTo(N, Res, Res); 1606 } 1607 1608 // If both halves are used, return as it is. 1609 if (LoExists && HiExists) 1610 return SDValue(); 1611 1612 // If the two computed results can be simplified separately, separate them. 1613 if (LoExists) { 1614 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1615 N->op_begin(), N->getNumOperands()); 1616 AddToWorkList(Lo.getNode()); 1617 SDValue LoOpt = combine(Lo.getNode()); 1618 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1619 (!LegalOperations || 1620 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1621 return CombineTo(N, LoOpt, LoOpt); 1622 } 1623 1624 if (HiExists) { 1625 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1626 N->op_begin(), N->getNumOperands()); 1627 AddToWorkList(Hi.getNode()); 1628 SDValue HiOpt = combine(Hi.getNode()); 1629 if (HiOpt.getNode() && HiOpt != Hi && 1630 (!LegalOperations || 1631 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1632 return CombineTo(N, HiOpt, HiOpt); 1633 } 1634 1635 return SDValue(); 1636} 1637 1638SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1639 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1640 if (Res.getNode()) return Res; 1641 1642 return SDValue(); 1643} 1644 1645SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1646 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1647 if (Res.getNode()) return Res; 1648 1649 return SDValue(); 1650} 1651 1652SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1653 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1654 if (Res.getNode()) return Res; 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1660 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1661 if (Res.getNode()) return Res; 1662 1663 return SDValue(); 1664} 1665 1666/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1667/// two operands of the same opcode, try to simplify it. 1668SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1669 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1670 MVT VT = N0.getValueType(); 1671 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1672 1673 // For each of OP in AND/OR/XOR: 1674 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1675 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1676 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1677 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1678 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1679 N0.getOpcode() == ISD::SIGN_EXTEND || 1680 (N0.getOpcode() == ISD::TRUNCATE && 1681 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1682 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1683 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1684 N0.getOperand(0).getValueType(), 1685 N0.getOperand(0), N1.getOperand(0)); 1686 AddToWorkList(ORNode.getNode()); 1687 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1688 } 1689 1690 // For each of OP in SHL/SRL/SRA/AND... 1691 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1692 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1693 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1694 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1695 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1696 N0.getOperand(1) == N1.getOperand(1)) { 1697 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1698 N0.getOperand(0).getValueType(), 1699 N0.getOperand(0), N1.getOperand(0)); 1700 AddToWorkList(ORNode.getNode()); 1701 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1702 ORNode, N0.getOperand(1)); 1703 } 1704 1705 return SDValue(); 1706} 1707 1708SDValue DAGCombiner::visitAND(SDNode *N) { 1709 SDValue N0 = N->getOperand(0); 1710 SDValue N1 = N->getOperand(1); 1711 SDValue LL, LR, RL, RR, CC0, CC1; 1712 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1713 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1714 MVT VT = N1.getValueType(); 1715 unsigned BitWidth = VT.getSizeInBits(); 1716 1717 // fold vector ops 1718 if (VT.isVector()) { 1719 SDValue FoldedVOp = SimplifyVBinOp(N); 1720 if (FoldedVOp.getNode()) return FoldedVOp; 1721 } 1722 1723 // fold (and x, undef) -> 0 1724 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1725 return DAG.getConstant(0, VT); 1726 // fold (and c1, c2) -> c1&c2 1727 if (N0C && N1C) 1728 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1729 // canonicalize constant to RHS 1730 if (N0C && !N1C) 1731 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1732 // fold (and x, -1) -> x 1733 if (N1C && N1C->isAllOnesValue()) 1734 return N0; 1735 // if (and x, c) is known to be zero, return 0 1736 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1737 APInt::getAllOnesValue(BitWidth))) 1738 return DAG.getConstant(0, VT); 1739 // reassociate and 1740 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1741 if (RAND.getNode() != 0) 1742 return RAND; 1743 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1744 if (N1C && N0.getOpcode() == ISD::OR) 1745 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1746 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1747 return N1; 1748 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1749 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1750 SDValue N0Op0 = N0.getOperand(0); 1751 APInt Mask = ~N1C->getAPIntValue(); 1752 Mask.trunc(N0Op0.getValueSizeInBits()); 1753 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1754 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1755 N0.getValueType(), N0Op0); 1756 1757 // Replace uses of the AND with uses of the Zero extend node. 1758 CombineTo(N, Zext); 1759 1760 // We actually want to replace all uses of the any_extend with the 1761 // zero_extend, to avoid duplicating things. This will later cause this 1762 // AND to be folded. 1763 CombineTo(N0.getNode(), Zext); 1764 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1765 } 1766 } 1767 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1768 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1769 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1770 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1771 1772 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1773 LL.getValueType().isInteger()) { 1774 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1775 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1776 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1777 LR.getValueType(), LL, RL); 1778 AddToWorkList(ORNode.getNode()); 1779 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1780 } 1781 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1782 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1783 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1784 LR.getValueType(), LL, RL); 1785 AddToWorkList(ANDNode.getNode()); 1786 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1787 } 1788 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1789 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1790 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1791 LR.getValueType(), LL, RL); 1792 AddToWorkList(ORNode.getNode()); 1793 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1794 } 1795 } 1796 // canonicalize equivalent to ll == rl 1797 if (LL == RR && LR == RL) { 1798 Op1 = ISD::getSetCCSwappedOperands(Op1); 1799 std::swap(RL, RR); 1800 } 1801 if (LL == RL && LR == RR) { 1802 bool isInteger = LL.getValueType().isInteger(); 1803 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1804 if (Result != ISD::SETCC_INVALID && 1805 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1806 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1807 LL, LR, Result); 1808 } 1809 } 1810 1811 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1812 if (N0.getOpcode() == N1.getOpcode()) { 1813 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1814 if (Tmp.getNode()) return Tmp; 1815 } 1816 1817 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1818 // fold (and (sra)) -> (and (srl)) when possible. 1819 if (!VT.isVector() && 1820 SimplifyDemandedBits(SDValue(N, 0))) 1821 return SDValue(N, 0); 1822 // fold (zext_inreg (extload x)) -> (zextload x) 1823 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1824 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1825 MVT EVT = LN0->getMemoryVT(); 1826 // If we zero all the possible extended bits, then we can turn this into 1827 // a zextload if we are running before legalize or the operation is legal. 1828 unsigned BitWidth = N1.getValueSizeInBits(); 1829 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1830 BitWidth - EVT.getSizeInBits())) && 1831 ((!LegalOperations && !LN0->isVolatile()) || 1832 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1833 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1834 LN0->getChain(), LN0->getBasePtr(), 1835 LN0->getSrcValue(), 1836 LN0->getSrcValueOffset(), EVT, 1837 LN0->isVolatile(), LN0->getAlignment()); 1838 AddToWorkList(N); 1839 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1840 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1841 } 1842 } 1843 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1844 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1845 N0.hasOneUse()) { 1846 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1847 MVT EVT = LN0->getMemoryVT(); 1848 // If we zero all the possible extended bits, then we can turn this into 1849 // a zextload if we are running before legalize or the operation is legal. 1850 unsigned BitWidth = N1.getValueSizeInBits(); 1851 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1852 BitWidth - EVT.getSizeInBits())) && 1853 ((!LegalOperations && !LN0->isVolatile()) || 1854 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1855 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1856 LN0->getChain(), 1857 LN0->getBasePtr(), LN0->getSrcValue(), 1858 LN0->getSrcValueOffset(), EVT, 1859 LN0->isVolatile(), LN0->getAlignment()); 1860 AddToWorkList(N); 1861 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1862 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1863 } 1864 } 1865 1866 // fold (and (load x), 255) -> (zextload x, i8) 1867 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1868 if (N1C && N0.getOpcode() == ISD::LOAD) { 1869 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1870 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1871 LN0->isUnindexed() && N0.hasOneUse() && 1872 // Do not change the width of a volatile load. 1873 !LN0->isVolatile()) { 1874 MVT EVT = MVT::Other; 1875 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1876 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1877 EVT = MVT::getIntegerVT(ActiveBits); 1878 1879 MVT LoadedVT = LN0->getMemoryVT(); 1880 1881 // Do not generate loads of non-round integer types since these can 1882 // be expensive (and would be wrong if the type is not byte sized). 1883 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1884 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1885 MVT PtrType = N0.getOperand(1).getValueType(); 1886 1887 // For big endian targets, we need to add an offset to the pointer to 1888 // load the correct bytes. For little endian systems, we merely need to 1889 // read fewer bytes from the same pointer. 1890 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1891 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1892 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1893 unsigned Alignment = LN0->getAlignment(); 1894 SDValue NewPtr = LN0->getBasePtr(); 1895 1896 if (TLI.isBigEndian()) { 1897 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1898 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1899 Alignment = MinAlign(Alignment, PtrOff); 1900 } 1901 1902 AddToWorkList(NewPtr.getNode()); 1903 SDValue Load = 1904 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1905 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1906 EVT, LN0->isVolatile(), Alignment); 1907 AddToWorkList(N); 1908 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1909 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1910 } 1911 } 1912 } 1913 1914 return SDValue(); 1915} 1916 1917SDValue DAGCombiner::visitOR(SDNode *N) { 1918 SDValue N0 = N->getOperand(0); 1919 SDValue N1 = N->getOperand(1); 1920 SDValue LL, LR, RL, RR, CC0, CC1; 1921 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1922 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1923 MVT VT = N1.getValueType(); 1924 1925 // fold vector ops 1926 if (VT.isVector()) { 1927 SDValue FoldedVOp = SimplifyVBinOp(N); 1928 if (FoldedVOp.getNode()) return FoldedVOp; 1929 } 1930 1931 // fold (or x, undef) -> -1 1932 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1933 return DAG.getConstant(~0ULL, VT); 1934 // fold (or c1, c2) -> c1|c2 1935 if (N0C && N1C) 1936 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1937 // canonicalize constant to RHS 1938 if (N0C && !N1C) 1939 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1940 // fold (or x, 0) -> x 1941 if (N1C && N1C->isNullValue()) 1942 return N0; 1943 // fold (or x, -1) -> -1 1944 if (N1C && N1C->isAllOnesValue()) 1945 return N1; 1946 // fold (or x, c) -> c iff (x & ~c) == 0 1947 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1948 return N1; 1949 // reassociate or 1950 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1951 if (ROR.getNode() != 0) 1952 return ROR; 1953 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1954 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1955 isa<ConstantSDNode>(N0.getOperand(1))) { 1956 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1957 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1958 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1959 N0.getOperand(0), N1), 1960 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1961 } 1962 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1963 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1964 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1965 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1966 1967 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1968 LL.getValueType().isInteger()) { 1969 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1970 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1971 if (cast<ConstantSDNode>(LR)->isNullValue() && 1972 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1973 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1974 LR.getValueType(), LL, RL); 1975 AddToWorkList(ORNode.getNode()); 1976 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1977 } 1978 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 1979 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 1980 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1981 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1982 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 1983 LR.getValueType(), LL, RL); 1984 AddToWorkList(ANDNode.getNode()); 1985 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1986 } 1987 } 1988 // canonicalize equivalent to ll == rl 1989 if (LL == RR && LR == RL) { 1990 Op1 = ISD::getSetCCSwappedOperands(Op1); 1991 std::swap(RL, RR); 1992 } 1993 if (LL == RL && LR == RR) { 1994 bool isInteger = LL.getValueType().isInteger(); 1995 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1996 if (Result != ISD::SETCC_INVALID && 1997 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1998 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1999 LL, LR, Result); 2000 } 2001 } 2002 2003 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2004 if (N0.getOpcode() == N1.getOpcode()) { 2005 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2006 if (Tmp.getNode()) return Tmp; 2007 } 2008 2009 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2010 if (N0.getOpcode() == ISD::AND && 2011 N1.getOpcode() == ISD::AND && 2012 N0.getOperand(1).getOpcode() == ISD::Constant && 2013 N1.getOperand(1).getOpcode() == ISD::Constant && 2014 // Don't increase # computations. 2015 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2016 // We can only do this xform if we know that bits from X that are set in C2 2017 // but not in C1 are already zero. Likewise for Y. 2018 const APInt &LHSMask = 2019 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2020 const APInt &RHSMask = 2021 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2022 2023 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2024 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2025 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2026 N0.getOperand(0), N1.getOperand(0)); 2027 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2028 DAG.getConstant(LHSMask | RHSMask, VT)); 2029 } 2030 } 2031 2032 // See if this is some rotate idiom. 2033 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2034 return SDValue(Rot, 0); 2035 2036 return SDValue(); 2037} 2038 2039/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2040static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2041 if (Op.getOpcode() == ISD::AND) { 2042 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2043 Mask = Op.getOperand(1); 2044 Op = Op.getOperand(0); 2045 } else { 2046 return false; 2047 } 2048 } 2049 2050 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2051 Shift = Op; 2052 return true; 2053 } 2054 2055 return false; 2056} 2057 2058// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2059// idioms for rotate, and if the target supports rotation instructions, generate 2060// a rot[lr]. 2061SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2062 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2063 MVT VT = LHS.getValueType(); 2064 if (!TLI.isTypeLegal(VT)) return 0; 2065 2066 // The target must have at least one rotate flavor. 2067 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2068 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2069 if (!HasROTL && !HasROTR) return 0; 2070 2071 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2072 SDValue LHSShift; // The shift. 2073 SDValue LHSMask; // AND value if any. 2074 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2075 return 0; // Not part of a rotate. 2076 2077 SDValue RHSShift; // The shift. 2078 SDValue RHSMask; // AND value if any. 2079 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2080 return 0; // Not part of a rotate. 2081 2082 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2083 return 0; // Not shifting the same value. 2084 2085 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2086 return 0; // Shifts must disagree. 2087 2088 // Canonicalize shl to left side in a shl/srl pair. 2089 if (RHSShift.getOpcode() == ISD::SHL) { 2090 std::swap(LHS, RHS); 2091 std::swap(LHSShift, RHSShift); 2092 std::swap(LHSMask , RHSMask ); 2093 } 2094 2095 unsigned OpSizeInBits = VT.getSizeInBits(); 2096 SDValue LHSShiftArg = LHSShift.getOperand(0); 2097 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2098 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2099 2100 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2101 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2102 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2103 RHSShiftAmt.getOpcode() == ISD::Constant) { 2104 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2105 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2106 if ((LShVal + RShVal) != OpSizeInBits) 2107 return 0; 2108 2109 SDValue Rot; 2110 if (HasROTL) 2111 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2112 else 2113 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2114 2115 // If there is an AND of either shifted operand, apply it to the result. 2116 if (LHSMask.getNode() || RHSMask.getNode()) { 2117 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2118 2119 if (LHSMask.getNode()) { 2120 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2121 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2122 } 2123 if (RHSMask.getNode()) { 2124 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2125 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2126 } 2127 2128 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2129 } 2130 2131 return Rot.getNode(); 2132 } 2133 2134 // If there is a mask here, and we have a variable shift, we can't be sure 2135 // that we're masking out the right stuff. 2136 if (LHSMask.getNode() || RHSMask.getNode()) 2137 return 0; 2138 2139 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2140 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2141 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2142 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2143 if (ConstantSDNode *SUBC = 2144 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2145 if (SUBC->getAPIntValue() == OpSizeInBits) { 2146 if (HasROTL) 2147 return DAG.getNode(ISD::ROTL, DL, VT, 2148 LHSShiftArg, LHSShiftAmt).getNode(); 2149 else 2150 return DAG.getNode(ISD::ROTR, DL, VT, 2151 LHSShiftArg, RHSShiftAmt).getNode(); 2152 } 2153 } 2154 } 2155 2156 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2157 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2158 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2159 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2160 if (ConstantSDNode *SUBC = 2161 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2162 if (SUBC->getAPIntValue() == OpSizeInBits) { 2163 if (HasROTR) 2164 return DAG.getNode(ISD::ROTR, DL, VT, 2165 LHSShiftArg, RHSShiftAmt).getNode(); 2166 else 2167 return DAG.getNode(ISD::ROTL, DL, VT, 2168 LHSShiftArg, LHSShiftAmt).getNode(); 2169 } 2170 } 2171 } 2172 2173 // Look for sign/zext/any-extended or truncate cases: 2174 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2175 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2176 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2177 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2178 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2179 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2180 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2181 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2182 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2183 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2184 if (RExtOp0.getOpcode() == ISD::SUB && 2185 RExtOp0.getOperand(1) == LExtOp0) { 2186 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2187 // (rotl x, y) 2188 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2189 // (rotr x, (sub 32, y)) 2190 if (ConstantSDNode *SUBC = 2191 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2192 if (SUBC->getAPIntValue() == OpSizeInBits) { 2193 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2194 LHSShiftArg, 2195 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2196 } 2197 } 2198 } else if (LExtOp0.getOpcode() == ISD::SUB && 2199 RExtOp0 == LExtOp0.getOperand(1)) { 2200 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2201 // (rotr x, y) 2202 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2203 // (rotl x, (sub 32, y)) 2204 if (ConstantSDNode *SUBC = 2205 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2206 if (SUBC->getAPIntValue() == OpSizeInBits) { 2207 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2208 LHSShiftArg, 2209 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2210 } 2211 } 2212 } 2213 } 2214 2215 return 0; 2216} 2217 2218SDValue DAGCombiner::visitXOR(SDNode *N) { 2219 SDValue N0 = N->getOperand(0); 2220 SDValue N1 = N->getOperand(1); 2221 SDValue LHS, RHS, CC; 2222 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2223 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2224 MVT VT = N0.getValueType(); 2225 2226 // fold vector ops 2227 if (VT.isVector()) { 2228 SDValue FoldedVOp = SimplifyVBinOp(N); 2229 if (FoldedVOp.getNode()) return FoldedVOp; 2230 } 2231 2232 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2233 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2234 return DAG.getConstant(0, VT); 2235 // fold (xor x, undef) -> undef 2236 if (N0.getOpcode() == ISD::UNDEF) 2237 return N0; 2238 if (N1.getOpcode() == ISD::UNDEF) 2239 return N1; 2240 // fold (xor c1, c2) -> c1^c2 2241 if (N0C && N1C) 2242 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2243 // canonicalize constant to RHS 2244 if (N0C && !N1C) 2245 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2246 // fold (xor x, 0) -> x 2247 if (N1C && N1C->isNullValue()) 2248 return N0; 2249 // reassociate xor 2250 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2251 if (RXOR.getNode() != 0) 2252 return RXOR; 2253 2254 // fold !(x cc y) -> (x !cc y) 2255 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2256 bool isInt = LHS.getValueType().isInteger(); 2257 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2258 isInt); 2259 2260 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2261 switch (N0.getOpcode()) { 2262 default: 2263 llvm_unreachable("Unhandled SetCC Equivalent!"); 2264 case ISD::SETCC: 2265 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2266 case ISD::SELECT_CC: 2267 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2268 N0.getOperand(3), NotCC); 2269 } 2270 } 2271 } 2272 2273 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2274 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2275 N0.getNode()->hasOneUse() && 2276 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2277 SDValue V = N0.getOperand(0); 2278 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2279 DAG.getConstant(1, V.getValueType())); 2280 AddToWorkList(V.getNode()); 2281 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2282 } 2283 2284 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2285 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2286 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2287 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2288 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2289 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2290 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2291 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2292 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2293 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2294 } 2295 } 2296 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2297 if (N1C && N1C->isAllOnesValue() && 2298 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2299 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2300 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2301 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2302 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2303 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2304 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2305 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2306 } 2307 } 2308 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2309 if (N1C && N0.getOpcode() == ISD::XOR) { 2310 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2311 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2312 if (N00C) 2313 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2314 DAG.getConstant(N1C->getAPIntValue() ^ 2315 N00C->getAPIntValue(), VT)); 2316 if (N01C) 2317 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2318 DAG.getConstant(N1C->getAPIntValue() ^ 2319 N01C->getAPIntValue(), VT)); 2320 } 2321 // fold (xor x, x) -> 0 2322 if (N0 == N1) { 2323 if (!VT.isVector()) { 2324 return DAG.getConstant(0, VT); 2325 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2326 // Produce a vector of zeros. 2327 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2328 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2329 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2330 &Ops[0], Ops.size()); 2331 } 2332 } 2333 2334 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2335 if (N0.getOpcode() == N1.getOpcode()) { 2336 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2337 if (Tmp.getNode()) return Tmp; 2338 } 2339 2340 // Simplify the expression using non-local knowledge. 2341 if (!VT.isVector() && 2342 SimplifyDemandedBits(SDValue(N, 0))) 2343 return SDValue(N, 0); 2344 2345 return SDValue(); 2346} 2347 2348/// visitShiftByConstant - Handle transforms common to the three shifts, when 2349/// the shift amount is a constant. 2350SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2351 SDNode *LHS = N->getOperand(0).getNode(); 2352 if (!LHS->hasOneUse()) return SDValue(); 2353 2354 // We want to pull some binops through shifts, so that we have (and (shift)) 2355 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2356 // thing happens with address calculations, so it's important to canonicalize 2357 // it. 2358 bool HighBitSet = false; // Can we transform this if the high bit is set? 2359 2360 switch (LHS->getOpcode()) { 2361 default: return SDValue(); 2362 case ISD::OR: 2363 case ISD::XOR: 2364 HighBitSet = false; // We can only transform sra if the high bit is clear. 2365 break; 2366 case ISD::AND: 2367 HighBitSet = true; // We can only transform sra if the high bit is set. 2368 break; 2369 case ISD::ADD: 2370 if (N->getOpcode() != ISD::SHL) 2371 return SDValue(); // only shl(add) not sr[al](add). 2372 HighBitSet = false; // We can only transform sra if the high bit is clear. 2373 break; 2374 } 2375 2376 // We require the RHS of the binop to be a constant as well. 2377 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2378 if (!BinOpCst) return SDValue(); 2379 2380 // FIXME: disable this unless the input to the binop is a shift by a constant. 2381 // If it is not a shift, it pessimizes some common cases like: 2382 // 2383 // void foo(int *X, int i) { X[i & 1235] = 1; } 2384 // int bar(int *X, int i) { return X[i & 255]; } 2385 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2386 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2387 BinOpLHSVal->getOpcode() != ISD::SRA && 2388 BinOpLHSVal->getOpcode() != ISD::SRL) || 2389 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2390 return SDValue(); 2391 2392 MVT VT = N->getValueType(0); 2393 2394 // If this is a signed shift right, and the high bit is modified by the 2395 // logical operation, do not perform the transformation. The highBitSet 2396 // boolean indicates the value of the high bit of the constant which would 2397 // cause it to be modified for this operation. 2398 if (N->getOpcode() == ISD::SRA) { 2399 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2400 if (BinOpRHSSignSet != HighBitSet) 2401 return SDValue(); 2402 } 2403 2404 // Fold the constants, shifting the binop RHS by the shift amount. 2405 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2406 N->getValueType(0), 2407 LHS->getOperand(1), N->getOperand(1)); 2408 2409 // Create the new shift. 2410 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2411 VT, LHS->getOperand(0), N->getOperand(1)); 2412 2413 // Create the new binop. 2414 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2415} 2416 2417SDValue DAGCombiner::visitSHL(SDNode *N) { 2418 SDValue N0 = N->getOperand(0); 2419 SDValue N1 = N->getOperand(1); 2420 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2421 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2422 MVT VT = N0.getValueType(); 2423 unsigned OpSizeInBits = VT.getSizeInBits(); 2424 2425 // fold (shl c1, c2) -> c1<<c2 2426 if (N0C && N1C) 2427 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2428 // fold (shl 0, x) -> 0 2429 if (N0C && N0C->isNullValue()) 2430 return N0; 2431 // fold (shl x, c >= size(x)) -> undef 2432 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2433 return DAG.getUNDEF(VT); 2434 // fold (shl x, 0) -> x 2435 if (N1C && N1C->isNullValue()) 2436 return N0; 2437 // if (shl x, c) is known to be zero, return 0 2438 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2439 APInt::getAllOnesValue(VT.getSizeInBits()))) 2440 return DAG.getConstant(0, VT); 2441 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2442 if (N1.getOpcode() == ISD::TRUNCATE && 2443 N1.getOperand(0).getOpcode() == ISD::AND && 2444 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2445 SDValue N101 = N1.getOperand(0).getOperand(1); 2446 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2447 MVT TruncVT = N1.getValueType(); 2448 SDValue N100 = N1.getOperand(0).getOperand(0); 2449 APInt TruncC = N101C->getAPIntValue(); 2450 TruncC.trunc(TruncVT.getSizeInBits()); 2451 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2452 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2453 DAG.getNode(ISD::TRUNCATE, 2454 N->getDebugLoc(), 2455 TruncVT, N100), 2456 DAG.getConstant(TruncC, TruncVT))); 2457 } 2458 } 2459 2460 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2461 return SDValue(N, 0); 2462 2463 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2464 if (N1C && N0.getOpcode() == ISD::SHL && 2465 N0.getOperand(1).getOpcode() == ISD::Constant) { 2466 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2467 uint64_t c2 = N1C->getZExtValue(); 2468 if (c1 + c2 > OpSizeInBits) 2469 return DAG.getConstant(0, VT); 2470 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2471 DAG.getConstant(c1 + c2, N1.getValueType())); 2472 } 2473 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2474 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2475 if (N1C && N0.getOpcode() == ISD::SRL && 2476 N0.getOperand(1).getOpcode() == ISD::Constant) { 2477 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2478 uint64_t c2 = N1C->getZExtValue(); 2479 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), 2480 DAG.getConstant(~0ULL << c1, VT)); 2481 if (c2 > c1) 2482 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2483 DAG.getConstant(c2-c1, N1.getValueType())); 2484 else 2485 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2486 DAG.getConstant(c1-c2, N1.getValueType())); 2487 } 2488 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2489 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2490 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2491 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2492 2493 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2494} 2495 2496SDValue DAGCombiner::visitSRA(SDNode *N) { 2497 SDValue N0 = N->getOperand(0); 2498 SDValue N1 = N->getOperand(1); 2499 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2500 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2501 MVT VT = N0.getValueType(); 2502 2503 // fold (sra c1, c2) -> (sra c1, c2) 2504 if (N0C && N1C) 2505 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2506 // fold (sra 0, x) -> 0 2507 if (N0C && N0C->isNullValue()) 2508 return N0; 2509 // fold (sra -1, x) -> -1 2510 if (N0C && N0C->isAllOnesValue()) 2511 return N0; 2512 // fold (sra x, (setge c, size(x))) -> undef 2513 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2514 return DAG.getUNDEF(VT); 2515 // fold (sra x, 0) -> x 2516 if (N1C && N1C->isNullValue()) 2517 return N0; 2518 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2519 // sext_inreg. 2520 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2521 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2522 MVT EVT = MVT::getIntegerVT(LowBits); 2523 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2524 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2525 N0.getOperand(0), DAG.getValueType(EVT)); 2526 } 2527 2528 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2529 if (N1C && N0.getOpcode() == ISD::SRA) { 2530 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2531 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2532 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2533 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2534 DAG.getConstant(Sum, N1C->getValueType(0))); 2535 } 2536 } 2537 2538 // fold (sra (shl X, m), (sub result_size, n)) 2539 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2540 // result_size - n != m. 2541 // If truncate is free for the target sext(shl) is likely to result in better 2542 // code. 2543 if (N0.getOpcode() == ISD::SHL) { 2544 // Get the two constanst of the shifts, CN0 = m, CN = n. 2545 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2546 if (N01C && N1C) { 2547 // Determine what the truncate's result bitsize and type would be. 2548 unsigned VTValSize = VT.getSizeInBits(); 2549 MVT TruncVT = 2550 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2551 // Determine the residual right-shift amount. 2552 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2553 2554 // If the shift is not a no-op (in which case this should be just a sign 2555 // extend already), the truncated to type is legal, sign_extend is legal 2556 // on that type, and the the truncate to that type is both legal and free, 2557 // perform the transform. 2558 if ((ShiftAmt > 0) && 2559 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2560 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2561 TLI.isTruncateFree(VT, TruncVT)) { 2562 2563 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2564 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2565 N0.getOperand(0), Amt); 2566 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2567 Shift); 2568 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2569 N->getValueType(0), Trunc); 2570 } 2571 } 2572 } 2573 2574 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2575 if (N1.getOpcode() == ISD::TRUNCATE && 2576 N1.getOperand(0).getOpcode() == ISD::AND && 2577 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2578 SDValue N101 = N1.getOperand(0).getOperand(1); 2579 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2580 MVT TruncVT = N1.getValueType(); 2581 SDValue N100 = N1.getOperand(0).getOperand(0); 2582 APInt TruncC = N101C->getAPIntValue(); 2583 TruncC.trunc(TruncVT.getSizeInBits()); 2584 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2585 DAG.getNode(ISD::AND, N->getDebugLoc(), 2586 TruncVT, 2587 DAG.getNode(ISD::TRUNCATE, 2588 N->getDebugLoc(), 2589 TruncVT, N100), 2590 DAG.getConstant(TruncC, TruncVT))); 2591 } 2592 } 2593 2594 // Simplify, based on bits shifted out of the LHS. 2595 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2596 return SDValue(N, 0); 2597 2598 2599 // If the sign bit is known to be zero, switch this to a SRL. 2600 if (DAG.SignBitIsZero(N0)) 2601 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2602 2603 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2604} 2605 2606SDValue DAGCombiner::visitSRL(SDNode *N) { 2607 SDValue N0 = N->getOperand(0); 2608 SDValue N1 = N->getOperand(1); 2609 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2610 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2611 MVT VT = N0.getValueType(); 2612 unsigned OpSizeInBits = VT.getSizeInBits(); 2613 2614 // fold (srl c1, c2) -> c1 >>u c2 2615 if (N0C && N1C) 2616 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2617 // fold (srl 0, x) -> 0 2618 if (N0C && N0C->isNullValue()) 2619 return N0; 2620 // fold (srl x, c >= size(x)) -> undef 2621 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2622 return DAG.getUNDEF(VT); 2623 // fold (srl x, 0) -> x 2624 if (N1C && N1C->isNullValue()) 2625 return N0; 2626 // if (srl x, c) is known to be zero, return 0 2627 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2628 APInt::getAllOnesValue(OpSizeInBits))) 2629 return DAG.getConstant(0, VT); 2630 2631 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2632 if (N1C && N0.getOpcode() == ISD::SRL && 2633 N0.getOperand(1).getOpcode() == ISD::Constant) { 2634 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2635 uint64_t c2 = N1C->getZExtValue(); 2636 if (c1 + c2 > OpSizeInBits) 2637 return DAG.getConstant(0, VT); 2638 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2639 DAG.getConstant(c1 + c2, N1.getValueType())); 2640 } 2641 2642 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2643 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2644 // Shifting in all undef bits? 2645 MVT SmallVT = N0.getOperand(0).getValueType(); 2646 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2647 return DAG.getUNDEF(VT); 2648 2649 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2650 N0.getOperand(0), N1); 2651 AddToWorkList(SmallShift.getNode()); 2652 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2653 } 2654 2655 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2656 // bit, which is unmodified by sra. 2657 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2658 if (N0.getOpcode() == ISD::SRA) 2659 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2660 } 2661 2662 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2663 if (N1C && N0.getOpcode() == ISD::CTLZ && 2664 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2665 APInt KnownZero, KnownOne; 2666 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2667 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2668 2669 // If any of the input bits are KnownOne, then the input couldn't be all 2670 // zeros, thus the result of the srl will always be zero. 2671 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2672 2673 // If all of the bits input the to ctlz node are known to be zero, then 2674 // the result of the ctlz is "32" and the result of the shift is one. 2675 APInt UnknownBits = ~KnownZero & Mask; 2676 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2677 2678 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2679 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2680 // Okay, we know that only that the single bit specified by UnknownBits 2681 // could be set on input to the CTLZ node. If this bit is set, the SRL 2682 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2683 // to an SRL/XOR pair, which is likely to simplify more. 2684 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2685 SDValue Op = N0.getOperand(0); 2686 2687 if (ShAmt) { 2688 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2689 DAG.getConstant(ShAmt, getShiftAmountTy())); 2690 AddToWorkList(Op.getNode()); 2691 } 2692 2693 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2694 Op, DAG.getConstant(1, VT)); 2695 } 2696 } 2697 2698 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2699 if (N1.getOpcode() == ISD::TRUNCATE && 2700 N1.getOperand(0).getOpcode() == ISD::AND && 2701 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2702 SDValue N101 = N1.getOperand(0).getOperand(1); 2703 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2704 MVT TruncVT = N1.getValueType(); 2705 SDValue N100 = N1.getOperand(0).getOperand(0); 2706 APInt TruncC = N101C->getAPIntValue(); 2707 TruncC.trunc(TruncVT.getSizeInBits()); 2708 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2709 DAG.getNode(ISD::AND, N->getDebugLoc(), 2710 TruncVT, 2711 DAG.getNode(ISD::TRUNCATE, 2712 N->getDebugLoc(), 2713 TruncVT, N100), 2714 DAG.getConstant(TruncC, TruncVT))); 2715 } 2716 } 2717 2718 // fold operands of srl based on knowledge that the low bits are not 2719 // demanded. 2720 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2721 return SDValue(N, 0); 2722 2723 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2724} 2725 2726SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2727 SDValue N0 = N->getOperand(0); 2728 MVT VT = N->getValueType(0); 2729 2730 // fold (ctlz c1) -> c2 2731 if (isa<ConstantSDNode>(N0)) 2732 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2733 return SDValue(); 2734} 2735 2736SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2737 SDValue N0 = N->getOperand(0); 2738 MVT VT = N->getValueType(0); 2739 2740 // fold (cttz c1) -> c2 2741 if (isa<ConstantSDNode>(N0)) 2742 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2743 return SDValue(); 2744} 2745 2746SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2747 SDValue N0 = N->getOperand(0); 2748 MVT VT = N->getValueType(0); 2749 2750 // fold (ctpop c1) -> c2 2751 if (isa<ConstantSDNode>(N0)) 2752 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2753 return SDValue(); 2754} 2755 2756SDValue DAGCombiner::visitSELECT(SDNode *N) { 2757 SDValue N0 = N->getOperand(0); 2758 SDValue N1 = N->getOperand(1); 2759 SDValue N2 = N->getOperand(2); 2760 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2761 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2762 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2763 MVT VT = N->getValueType(0); 2764 MVT VT0 = N0.getValueType(); 2765 2766 // fold (select C, X, X) -> X 2767 if (N1 == N2) 2768 return N1; 2769 // fold (select true, X, Y) -> X 2770 if (N0C && !N0C->isNullValue()) 2771 return N1; 2772 // fold (select false, X, Y) -> Y 2773 if (N0C && N0C->isNullValue()) 2774 return N2; 2775 // fold (select C, 1, X) -> (or C, X) 2776 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2777 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2778 // fold (select C, 0, 1) -> (xor C, 1) 2779 if (VT.isInteger() && 2780 (VT0 == MVT::i1 || 2781 (VT0.isInteger() && 2782 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2783 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2784 SDValue XORNode; 2785 if (VT == VT0) 2786 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2787 N0, DAG.getConstant(1, VT0)); 2788 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2789 N0, DAG.getConstant(1, VT0)); 2790 AddToWorkList(XORNode.getNode()); 2791 if (VT.bitsGT(VT0)) 2792 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2793 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2794 } 2795 // fold (select C, 0, X) -> (and (not C), X) 2796 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2797 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2798 AddToWorkList(NOTNode.getNode()); 2799 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2800 } 2801 // fold (select C, X, 1) -> (or (not C), X) 2802 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2803 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2804 AddToWorkList(NOTNode.getNode()); 2805 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2806 } 2807 // fold (select C, X, 0) -> (and C, X) 2808 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2809 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2810 // fold (select X, X, Y) -> (or X, Y) 2811 // fold (select X, 1, Y) -> (or X, Y) 2812 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2813 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2814 // fold (select X, Y, X) -> (and X, Y) 2815 // fold (select X, Y, 0) -> (and X, Y) 2816 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2817 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2818 2819 // If we can fold this based on the true/false value, do so. 2820 if (SimplifySelectOps(N, N1, N2)) 2821 return SDValue(N, 0); // Don't revisit N. 2822 2823 // fold selects based on a setcc into other things, such as min/max/abs 2824 if (N0.getOpcode() == ISD::SETCC) { 2825 // FIXME: 2826 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2827 // having to say they don't support SELECT_CC on every type the DAG knows 2828 // about, since there is no way to mark an opcode illegal at all value types 2829 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2830 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2831 N0.getOperand(0), N0.getOperand(1), 2832 N1, N2, N0.getOperand(2)); 2833 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2834 } 2835 2836 return SDValue(); 2837} 2838 2839SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2840 SDValue N0 = N->getOperand(0); 2841 SDValue N1 = N->getOperand(1); 2842 SDValue N2 = N->getOperand(2); 2843 SDValue N3 = N->getOperand(3); 2844 SDValue N4 = N->getOperand(4); 2845 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2846 2847 // fold select_cc lhs, rhs, x, x, cc -> x 2848 if (N2 == N3) 2849 return N2; 2850 2851 // Determine if the condition we're dealing with is constant 2852 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2853 N0, N1, CC, N->getDebugLoc(), false); 2854 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2855 2856 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2857 if (!SCCC->isNullValue()) 2858 return N2; // cond always true -> true val 2859 else 2860 return N3; // cond always false -> false val 2861 } 2862 2863 // Fold to a simpler select_cc 2864 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2865 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2866 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2867 SCC.getOperand(2)); 2868 2869 // If we can fold this based on the true/false value, do so. 2870 if (SimplifySelectOps(N, N2, N3)) 2871 return SDValue(N, 0); // Don't revisit N. 2872 2873 // fold select_cc into other things, such as min/max/abs 2874 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2875} 2876 2877SDValue DAGCombiner::visitSETCC(SDNode *N) { 2878 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2879 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2880 N->getDebugLoc()); 2881} 2882 2883// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2884// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2885// transformation. Returns true if extension are possible and the above 2886// mentioned transformation is profitable. 2887static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2888 unsigned ExtOpc, 2889 SmallVector<SDNode*, 4> &ExtendNodes, 2890 const TargetLowering &TLI) { 2891 bool HasCopyToRegUses = false; 2892 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2893 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2894 UE = N0.getNode()->use_end(); 2895 UI != UE; ++UI) { 2896 SDNode *User = *UI; 2897 if (User == N) 2898 continue; 2899 if (UI.getUse().getResNo() != N0.getResNo()) 2900 continue; 2901 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2902 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 2903 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2904 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2905 // Sign bits will be lost after a zext. 2906 return false; 2907 bool Add = false; 2908 for (unsigned i = 0; i != 2; ++i) { 2909 SDValue UseOp = User->getOperand(i); 2910 if (UseOp == N0) 2911 continue; 2912 if (!isa<ConstantSDNode>(UseOp)) 2913 return false; 2914 Add = true; 2915 } 2916 if (Add) 2917 ExtendNodes.push_back(User); 2918 continue; 2919 } 2920 // If truncates aren't free and there are users we can't 2921 // extend, it isn't worthwhile. 2922 if (!isTruncFree) 2923 return false; 2924 // Remember if this value is live-out. 2925 if (User->getOpcode() == ISD::CopyToReg) 2926 HasCopyToRegUses = true; 2927 } 2928 2929 if (HasCopyToRegUses) { 2930 bool BothLiveOut = false; 2931 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2932 UI != UE; ++UI) { 2933 SDUse &Use = UI.getUse(); 2934 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 2935 BothLiveOut = true; 2936 break; 2937 } 2938 } 2939 if (BothLiveOut) 2940 // Both unextended and extended values are live out. There had better be 2941 // good a reason for the transformation. 2942 return ExtendNodes.size(); 2943 } 2944 return true; 2945} 2946 2947SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2948 SDValue N0 = N->getOperand(0); 2949 MVT VT = N->getValueType(0); 2950 2951 // fold (sext c1) -> c1 2952 if (isa<ConstantSDNode>(N0)) 2953 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2954 2955 // fold (sext (sext x)) -> (sext x) 2956 // fold (sext (aext x)) -> (sext x) 2957 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2958 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2959 N0.getOperand(0)); 2960 2961 if (N0.getOpcode() == ISD::TRUNCATE) { 2962 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2963 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2964 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2965 if (NarrowLoad.getNode()) { 2966 if (NarrowLoad.getNode() != N0.getNode()) 2967 CombineTo(N0.getNode(), NarrowLoad); 2968 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2969 } 2970 2971 // See if the value being truncated is already sign extended. If so, just 2972 // eliminate the trunc/sext pair. 2973 SDValue Op = N0.getOperand(0); 2974 unsigned OpBits = Op.getValueType().getSizeInBits(); 2975 unsigned MidBits = N0.getValueType().getSizeInBits(); 2976 unsigned DestBits = VT.getSizeInBits(); 2977 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2978 2979 if (OpBits == DestBits) { 2980 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2981 // bits, it is already ready. 2982 if (NumSignBits > DestBits-MidBits) 2983 return Op; 2984 } else if (OpBits < DestBits) { 2985 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2986 // bits, just sext from i32. 2987 if (NumSignBits > OpBits-MidBits) 2988 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 2989 } else { 2990 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2991 // bits, just truncate to i32. 2992 if (NumSignBits > OpBits-MidBits) 2993 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 2994 } 2995 2996 // fold (sext (truncate x)) -> (sextinreg x). 2997 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2998 N0.getValueType())) { 2999 if (Op.getValueType().bitsLT(VT)) 3000 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3001 else if (Op.getValueType().bitsGT(VT)) 3002 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3003 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3004 DAG.getValueType(N0.getValueType())); 3005 } 3006 } 3007 3008 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3009 if (ISD::isNON_EXTLoad(N0.getNode()) && 3010 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3011 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3012 bool DoXform = true; 3013 SmallVector<SDNode*, 4> SetCCs; 3014 if (!N0.hasOneUse()) 3015 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3016 if (DoXform) { 3017 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3018 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3019 LN0->getChain(), 3020 LN0->getBasePtr(), LN0->getSrcValue(), 3021 LN0->getSrcValueOffset(), 3022 N0.getValueType(), 3023 LN0->isVolatile(), LN0->getAlignment()); 3024 CombineTo(N, ExtLoad); 3025 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3026 N0.getValueType(), ExtLoad); 3027 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3028 3029 // Extend SetCC uses if necessary. 3030 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3031 SDNode *SetCC = SetCCs[i]; 3032 SmallVector<SDValue, 4> Ops; 3033 3034 for (unsigned j = 0; j != 2; ++j) { 3035 SDValue SOp = SetCC->getOperand(j); 3036 if (SOp == Trunc) 3037 Ops.push_back(ExtLoad); 3038 else 3039 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3040 N->getDebugLoc(), VT, SOp)); 3041 } 3042 3043 Ops.push_back(SetCC->getOperand(2)); 3044 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3045 SetCC->getValueType(0), 3046 &Ops[0], Ops.size())); 3047 } 3048 3049 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3050 } 3051 } 3052 3053 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3054 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3055 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3056 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3057 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3058 MVT EVT = LN0->getMemoryVT(); 3059 if ((!LegalOperations && !LN0->isVolatile()) || 3060 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3061 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3062 LN0->getChain(), 3063 LN0->getBasePtr(), LN0->getSrcValue(), 3064 LN0->getSrcValueOffset(), EVT, 3065 LN0->isVolatile(), LN0->getAlignment()); 3066 CombineTo(N, ExtLoad); 3067 CombineTo(N0.getNode(), 3068 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3069 N0.getValueType(), ExtLoad), 3070 ExtLoad.getValue(1)); 3071 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3072 } 3073 } 3074 3075 if (N0.getOpcode() == ISD::SETCC) { 3076 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3077 if (VT.isVector() && 3078 // We know that the # elements of the results is the same as the 3079 // # elements of the compare (and the # elements of the compare result 3080 // for that matter). Check to see that they are the same size. If so, 3081 // we know that the element size of the sext'd result matches the 3082 // element size of the compare operands. 3083 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3084 3085 // Only do this before legalize for now. 3086 !LegalOperations) { 3087 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3088 N0.getOperand(1), 3089 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3090 } 3091 3092 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3093 SDValue SCC = 3094 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3095 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3096 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3097 if (SCC.getNode()) return SCC; 3098 } 3099 3100 3101 3102 // fold (sext x) -> (zext x) if the sign bit is known zero. 3103 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3104 DAG.SignBitIsZero(N0)) 3105 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3106 3107 return SDValue(); 3108} 3109 3110SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3111 SDValue N0 = N->getOperand(0); 3112 MVT VT = N->getValueType(0); 3113 3114 // fold (zext c1) -> c1 3115 if (isa<ConstantSDNode>(N0)) 3116 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3117 // fold (zext (zext x)) -> (zext x) 3118 // fold (zext (aext x)) -> (zext x) 3119 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3120 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3121 N0.getOperand(0)); 3122 3123 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3124 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3125 if (N0.getOpcode() == ISD::TRUNCATE) { 3126 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3127 if (NarrowLoad.getNode()) { 3128 if (NarrowLoad.getNode() != N0.getNode()) 3129 CombineTo(N0.getNode(), NarrowLoad); 3130 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3131 } 3132 } 3133 3134 // fold (zext (truncate x)) -> (and x, mask) 3135 if (N0.getOpcode() == ISD::TRUNCATE && 3136 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3137 SDValue Op = N0.getOperand(0); 3138 if (Op.getValueType().bitsLT(VT)) { 3139 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3140 } else if (Op.getValueType().bitsGT(VT)) { 3141 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3142 } 3143 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3144 } 3145 3146 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3147 // if either of the casts is not free. 3148 if (N0.getOpcode() == ISD::AND && 3149 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3150 N0.getOperand(1).getOpcode() == ISD::Constant && 3151 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3152 N0.getValueType()) || 3153 !TLI.isZExtFree(N0.getValueType(), VT))) { 3154 SDValue X = N0.getOperand(0).getOperand(0); 3155 if (X.getValueType().bitsLT(VT)) { 3156 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3157 } else if (X.getValueType().bitsGT(VT)) { 3158 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3159 } 3160 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3161 Mask.zext(VT.getSizeInBits()); 3162 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3163 X, DAG.getConstant(Mask, VT)); 3164 } 3165 3166 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3167 if (ISD::isNON_EXTLoad(N0.getNode()) && 3168 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3169 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3170 bool DoXform = true; 3171 SmallVector<SDNode*, 4> SetCCs; 3172 if (!N0.hasOneUse()) 3173 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3174 if (DoXform) { 3175 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3176 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3177 LN0->getChain(), 3178 LN0->getBasePtr(), LN0->getSrcValue(), 3179 LN0->getSrcValueOffset(), 3180 N0.getValueType(), 3181 LN0->isVolatile(), LN0->getAlignment()); 3182 CombineTo(N, ExtLoad); 3183 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3184 N0.getValueType(), ExtLoad); 3185 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3186 3187 // Extend SetCC uses if necessary. 3188 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3189 SDNode *SetCC = SetCCs[i]; 3190 SmallVector<SDValue, 4> Ops; 3191 3192 for (unsigned j = 0; j != 2; ++j) { 3193 SDValue SOp = SetCC->getOperand(j); 3194 if (SOp == Trunc) 3195 Ops.push_back(ExtLoad); 3196 else 3197 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3198 N->getDebugLoc(), VT, SOp)); 3199 } 3200 3201 Ops.push_back(SetCC->getOperand(2)); 3202 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3203 SetCC->getValueType(0), 3204 &Ops[0], Ops.size())); 3205 } 3206 3207 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3208 } 3209 } 3210 3211 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3212 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3213 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3214 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3215 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3216 MVT EVT = LN0->getMemoryVT(); 3217 if ((!LegalOperations && !LN0->isVolatile()) || 3218 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3219 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3220 LN0->getChain(), 3221 LN0->getBasePtr(), LN0->getSrcValue(), 3222 LN0->getSrcValueOffset(), EVT, 3223 LN0->isVolatile(), LN0->getAlignment()); 3224 CombineTo(N, ExtLoad); 3225 CombineTo(N0.getNode(), 3226 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3227 ExtLoad), 3228 ExtLoad.getValue(1)); 3229 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3230 } 3231 } 3232 3233 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3234 if (N0.getOpcode() == ISD::SETCC) { 3235 SDValue SCC = 3236 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3237 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3238 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3239 if (SCC.getNode()) return SCC; 3240 } 3241 3242 return SDValue(); 3243} 3244 3245SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3246 SDValue N0 = N->getOperand(0); 3247 MVT VT = N->getValueType(0); 3248 3249 // fold (aext c1) -> c1 3250 if (isa<ConstantSDNode>(N0)) 3251 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3252 // fold (aext (aext x)) -> (aext x) 3253 // fold (aext (zext x)) -> (zext x) 3254 // fold (aext (sext x)) -> (sext x) 3255 if (N0.getOpcode() == ISD::ANY_EXTEND || 3256 N0.getOpcode() == ISD::ZERO_EXTEND || 3257 N0.getOpcode() == ISD::SIGN_EXTEND) 3258 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3259 3260 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3261 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3262 if (N0.getOpcode() == ISD::TRUNCATE) { 3263 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3264 if (NarrowLoad.getNode()) { 3265 if (NarrowLoad.getNode() != N0.getNode()) 3266 CombineTo(N0.getNode(), NarrowLoad); 3267 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3268 } 3269 } 3270 3271 // fold (aext (truncate x)) 3272 if (N0.getOpcode() == ISD::TRUNCATE) { 3273 SDValue TruncOp = N0.getOperand(0); 3274 if (TruncOp.getValueType() == VT) 3275 return TruncOp; // x iff x size == zext size. 3276 if (TruncOp.getValueType().bitsGT(VT)) 3277 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3278 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3279 } 3280 3281 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3282 // if the trunc is not free. 3283 if (N0.getOpcode() == ISD::AND && 3284 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3285 N0.getOperand(1).getOpcode() == ISD::Constant && 3286 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3287 N0.getValueType())) { 3288 SDValue X = N0.getOperand(0).getOperand(0); 3289 if (X.getValueType().bitsLT(VT)) { 3290 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3291 } else if (X.getValueType().bitsGT(VT)) { 3292 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3293 } 3294 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3295 Mask.zext(VT.getSizeInBits()); 3296 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3297 X, DAG.getConstant(Mask, VT)); 3298 } 3299 3300 // fold (aext (load x)) -> (aext (truncate (extload x))) 3301 if (ISD::isNON_EXTLoad(N0.getNode()) && 3302 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3303 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3304 bool DoXform = true; 3305 SmallVector<SDNode*, 4> SetCCs; 3306 if (!N0.hasOneUse()) 3307 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3308 if (DoXform) { 3309 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3310 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3311 LN0->getChain(), 3312 LN0->getBasePtr(), LN0->getSrcValue(), 3313 LN0->getSrcValueOffset(), 3314 N0.getValueType(), 3315 LN0->isVolatile(), LN0->getAlignment()); 3316 CombineTo(N, ExtLoad); 3317 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3318 N0.getValueType(), ExtLoad); 3319 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3320 3321 // Extend SetCC uses if necessary. 3322 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3323 SDNode *SetCC = SetCCs[i]; 3324 SmallVector<SDValue, 4> Ops; 3325 3326 for (unsigned j = 0; j != 2; ++j) { 3327 SDValue SOp = SetCC->getOperand(j); 3328 if (SOp == Trunc) 3329 Ops.push_back(ExtLoad); 3330 else 3331 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3332 N->getDebugLoc(), VT, SOp)); 3333 } 3334 3335 Ops.push_back(SetCC->getOperand(2)); 3336 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3337 SetCC->getValueType(0), 3338 &Ops[0], Ops.size())); 3339 } 3340 3341 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3342 } 3343 } 3344 3345 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3346 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3347 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3348 if (N0.getOpcode() == ISD::LOAD && 3349 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3350 N0.hasOneUse()) { 3351 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3352 MVT EVT = LN0->getMemoryVT(); 3353 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3354 VT, LN0->getChain(), LN0->getBasePtr(), 3355 LN0->getSrcValue(), 3356 LN0->getSrcValueOffset(), EVT, 3357 LN0->isVolatile(), LN0->getAlignment()); 3358 CombineTo(N, ExtLoad); 3359 CombineTo(N0.getNode(), 3360 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3361 N0.getValueType(), ExtLoad), 3362 ExtLoad.getValue(1)); 3363 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3364 } 3365 3366 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3367 if (N0.getOpcode() == ISD::SETCC) { 3368 SDValue SCC = 3369 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3370 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3371 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3372 if (SCC.getNode()) 3373 return SCC; 3374 } 3375 3376 return SDValue(); 3377} 3378 3379/// GetDemandedBits - See if the specified operand can be simplified with the 3380/// knowledge that only the bits specified by Mask are used. If so, return the 3381/// simpler operand, otherwise return a null SDValue. 3382SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3383 switch (V.getOpcode()) { 3384 default: break; 3385 case ISD::OR: 3386 case ISD::XOR: 3387 // If the LHS or RHS don't contribute bits to the or, drop them. 3388 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3389 return V.getOperand(1); 3390 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3391 return V.getOperand(0); 3392 break; 3393 case ISD::SRL: 3394 // Only look at single-use SRLs. 3395 if (!V.getNode()->hasOneUse()) 3396 break; 3397 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3398 // See if we can recursively simplify the LHS. 3399 unsigned Amt = RHSC->getZExtValue(); 3400 3401 // Watch out for shift count overflow though. 3402 if (Amt >= Mask.getBitWidth()) break; 3403 APInt NewMask = Mask << Amt; 3404 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3405 if (SimplifyLHS.getNode()) 3406 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3407 SimplifyLHS, V.getOperand(1)); 3408 } 3409 } 3410 return SDValue(); 3411} 3412 3413/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3414/// bits and then truncated to a narrower type and where N is a multiple 3415/// of number of bits of the narrower type, transform it to a narrower load 3416/// from address + N / num of bits of new type. If the result is to be 3417/// extended, also fold the extension to form a extending load. 3418SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3419 unsigned Opc = N->getOpcode(); 3420 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3421 SDValue N0 = N->getOperand(0); 3422 MVT VT = N->getValueType(0); 3423 MVT EVT = VT; 3424 3425 // This transformation isn't valid for vector loads. 3426 if (VT.isVector()) 3427 return SDValue(); 3428 3429 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3430 // extended to VT. 3431 if (Opc == ISD::SIGN_EXTEND_INREG) { 3432 ExtType = ISD::SEXTLOAD; 3433 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3434 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3435 return SDValue(); 3436 } 3437 3438 unsigned EVTBits = EVT.getSizeInBits(); 3439 unsigned ShAmt = 0; 3440 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3441 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3442 ShAmt = N01->getZExtValue(); 3443 // Is the shift amount a multiple of size of VT? 3444 if ((ShAmt & (EVTBits-1)) == 0) { 3445 N0 = N0.getOperand(0); 3446 if (N0.getValueType().getSizeInBits() <= EVTBits) 3447 return SDValue(); 3448 } 3449 } 3450 } 3451 3452 // Do not generate loads of non-round integer types since these can 3453 // be expensive (and would be wrong if the type is not byte sized). 3454 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3455 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3456 // Do not change the width of a volatile load. 3457 !cast<LoadSDNode>(N0)->isVolatile()) { 3458 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3459 MVT PtrType = N0.getOperand(1).getValueType(); 3460 3461 // For big endian targets, we need to adjust the offset to the pointer to 3462 // load the correct bytes. 3463 if (TLI.isBigEndian()) { 3464 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3465 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3466 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3467 } 3468 3469 uint64_t PtrOff = ShAmt / 8; 3470 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3471 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3472 PtrType, LN0->getBasePtr(), 3473 DAG.getConstant(PtrOff, PtrType)); 3474 AddToWorkList(NewPtr.getNode()); 3475 3476 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3477 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3478 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3479 LN0->isVolatile(), NewAlign) 3480 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3481 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3482 EVT, LN0->isVolatile(), NewAlign); 3483 3484 // Replace the old load's chain with the new load's chain. 3485 WorkListRemover DeadNodes(*this); 3486 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3487 &DeadNodes); 3488 3489 // Return the new loaded value. 3490 return Load; 3491 } 3492 3493 return SDValue(); 3494} 3495 3496SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3497 SDValue N0 = N->getOperand(0); 3498 SDValue N1 = N->getOperand(1); 3499 MVT VT = N->getValueType(0); 3500 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3501 unsigned VTBits = VT.getSizeInBits(); 3502 unsigned EVTBits = EVT.getSizeInBits(); 3503 3504 // fold (sext_in_reg c1) -> c1 3505 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3506 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3507 3508 // If the input is already sign extended, just drop the extension. 3509 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3510 return N0; 3511 3512 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3513 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3514 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3515 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3516 N0.getOperand(0), N1); 3517 } 3518 3519 // fold (sext_in_reg (sext x)) -> (sext x) 3520 // fold (sext_in_reg (aext x)) -> (sext x) 3521 // if x is small enough. 3522 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3523 SDValue N00 = N0.getOperand(0); 3524 if (N00.getValueType().getSizeInBits() < EVTBits) 3525 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3526 } 3527 3528 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3529 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3530 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3531 3532 // fold operands of sext_in_reg based on knowledge that the top bits are not 3533 // demanded. 3534 if (SimplifyDemandedBits(SDValue(N, 0))) 3535 return SDValue(N, 0); 3536 3537 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3538 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3539 SDValue NarrowLoad = ReduceLoadWidth(N); 3540 if (NarrowLoad.getNode()) 3541 return NarrowLoad; 3542 3543 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3544 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3545 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3546 if (N0.getOpcode() == ISD::SRL) { 3547 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3548 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3549 // We can turn this into an SRA iff the input to the SRL is already sign 3550 // extended enough. 3551 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3552 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3553 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3554 N0.getOperand(0), N0.getOperand(1)); 3555 } 3556 } 3557 3558 // fold (sext_inreg (extload x)) -> (sextload x) 3559 if (ISD::isEXTLoad(N0.getNode()) && 3560 ISD::isUNINDEXEDLoad(N0.getNode()) && 3561 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3562 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3563 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3564 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3565 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3566 LN0->getChain(), 3567 LN0->getBasePtr(), LN0->getSrcValue(), 3568 LN0->getSrcValueOffset(), EVT, 3569 LN0->isVolatile(), LN0->getAlignment()); 3570 CombineTo(N, ExtLoad); 3571 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3572 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3573 } 3574 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3575 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3576 N0.hasOneUse() && 3577 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3578 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3579 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3580 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3581 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3582 LN0->getChain(), 3583 LN0->getBasePtr(), LN0->getSrcValue(), 3584 LN0->getSrcValueOffset(), EVT, 3585 LN0->isVolatile(), LN0->getAlignment()); 3586 CombineTo(N, ExtLoad); 3587 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3588 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3589 } 3590 return SDValue(); 3591} 3592 3593SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3594 SDValue N0 = N->getOperand(0); 3595 MVT VT = N->getValueType(0); 3596 3597 // noop truncate 3598 if (N0.getValueType() == N->getValueType(0)) 3599 return N0; 3600 // fold (truncate c1) -> c1 3601 if (isa<ConstantSDNode>(N0)) 3602 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3603 // fold (truncate (truncate x)) -> (truncate x) 3604 if (N0.getOpcode() == ISD::TRUNCATE) 3605 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3606 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3607 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3608 N0.getOpcode() == ISD::ANY_EXTEND) { 3609 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3610 // if the source is smaller than the dest, we still need an extend 3611 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3612 N0.getOperand(0)); 3613 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3614 // if the source is larger than the dest, than we just need the truncate 3615 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3616 else 3617 // if the source and dest are the same type, we can drop both the extend 3618 // and the truncate 3619 return N0.getOperand(0); 3620 } 3621 3622 // See if we can simplify the input to this truncate through knowledge that 3623 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3624 // -> trunc y 3625 SDValue Shorter = 3626 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3627 VT.getSizeInBits())); 3628 if (Shorter.getNode()) 3629 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3630 3631 // fold (truncate (load x)) -> (smaller load x) 3632 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3633 return ReduceLoadWidth(N); 3634} 3635 3636static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3637 SDValue Elt = N->getOperand(i); 3638 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3639 return Elt.getNode(); 3640 return Elt.getOperand(Elt.getResNo()).getNode(); 3641} 3642 3643/// CombineConsecutiveLoads - build_pair (load, load) -> load 3644/// if load locations are consecutive. 3645SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3646 assert(N->getOpcode() == ISD::BUILD_PAIR); 3647 3648 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3649 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3650 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3651 return SDValue(); 3652 MVT LD1VT = LD1->getValueType(0); 3653 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3654 3655 if (ISD::isNON_EXTLoad(LD2) && 3656 LD2->hasOneUse() && 3657 // If both are volatile this would reduce the number of volatile loads. 3658 // If one is volatile it might be ok, but play conservative and bail out. 3659 !LD1->isVolatile() && 3660 !LD2->isVolatile() && 3661 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3662 unsigned Align = LD1->getAlignment(); 3663 unsigned NewAlign = TLI.getTargetData()-> 3664 getABITypeAlignment(VT.getTypeForMVT(*DAG.getContext())); 3665 3666 if (NewAlign <= Align && 3667 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3668 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3669 LD1->getBasePtr(), LD1->getSrcValue(), 3670 LD1->getSrcValueOffset(), false, Align); 3671 } 3672 3673 return SDValue(); 3674} 3675 3676SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3677 SDValue N0 = N->getOperand(0); 3678 MVT VT = N->getValueType(0); 3679 3680 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3681 // Only do this before legalize, since afterward the target may be depending 3682 // on the bitconvert. 3683 // First check to see if this is all constant. 3684 if (!LegalTypes && 3685 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3686 VT.isVector()) { 3687 bool isSimple = true; 3688 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3689 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3690 N0.getOperand(i).getOpcode() != ISD::Constant && 3691 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3692 isSimple = false; 3693 break; 3694 } 3695 3696 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3697 assert(!DestEltVT.isVector() && 3698 "Element type of vector ValueType must not be vector!"); 3699 if (isSimple) 3700 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3701 } 3702 3703 // If the input is a constant, let getNode fold it. 3704 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3705 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3706 if (Res.getNode() != N) return Res; 3707 } 3708 3709 // (conv (conv x, t1), t2) -> (conv x, t2) 3710 if (N0.getOpcode() == ISD::BIT_CONVERT) 3711 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3712 N0.getOperand(0)); 3713 3714 // fold (conv (load x)) -> (load (conv*)x) 3715 // If the resultant load doesn't need a higher alignment than the original! 3716 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3717 // Do not change the width of a volatile load. 3718 !cast<LoadSDNode>(N0)->isVolatile() && 3719 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3720 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3721 unsigned Align = TLI.getTargetData()-> 3722 getABITypeAlignment(VT.getTypeForMVT(*DAG.getContext())); 3723 unsigned OrigAlign = LN0->getAlignment(); 3724 3725 if (Align <= OrigAlign) { 3726 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3727 LN0->getBasePtr(), 3728 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3729 LN0->isVolatile(), OrigAlign); 3730 AddToWorkList(N); 3731 CombineTo(N0.getNode(), 3732 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3733 N0.getValueType(), Load), 3734 Load.getValue(1)); 3735 return Load; 3736 } 3737 } 3738 3739 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3740 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3741 // This often reduces constant pool loads. 3742 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3743 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3744 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3745 N0.getOperand(0)); 3746 AddToWorkList(NewConv.getNode()); 3747 3748 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3749 if (N0.getOpcode() == ISD::FNEG) 3750 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3751 NewConv, DAG.getConstant(SignBit, VT)); 3752 assert(N0.getOpcode() == ISD::FABS); 3753 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3754 NewConv, DAG.getConstant(~SignBit, VT)); 3755 } 3756 3757 // fold (bitconvert (fcopysign cst, x)) -> 3758 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3759 // Note that we don't handle (copysign x, cst) because this can always be 3760 // folded to an fneg or fabs. 3761 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3762 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3763 VT.isInteger() && !VT.isVector()) { 3764 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3765 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3766 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3767 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3768 IntXVT, N0.getOperand(1)); 3769 AddToWorkList(X.getNode()); 3770 3771 // If X has a different width than the result/lhs, sext it or truncate it. 3772 unsigned VTWidth = VT.getSizeInBits(); 3773 if (OrigXWidth < VTWidth) { 3774 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3775 AddToWorkList(X.getNode()); 3776 } else if (OrigXWidth > VTWidth) { 3777 // To get the sign bit in the right place, we have to shift it right 3778 // before truncating. 3779 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3780 X.getValueType(), X, 3781 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3782 AddToWorkList(X.getNode()); 3783 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3784 AddToWorkList(X.getNode()); 3785 } 3786 3787 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3788 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3789 X, DAG.getConstant(SignBit, VT)); 3790 AddToWorkList(X.getNode()); 3791 3792 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3793 VT, N0.getOperand(0)); 3794 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3795 Cst, DAG.getConstant(~SignBit, VT)); 3796 AddToWorkList(Cst.getNode()); 3797 3798 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3799 } 3800 } 3801 3802 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3803 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3804 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3805 if (CombineLD.getNode()) 3806 return CombineLD; 3807 } 3808 3809 return SDValue(); 3810} 3811 3812SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3813 MVT VT = N->getValueType(0); 3814 return CombineConsecutiveLoads(N, VT); 3815} 3816 3817/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3818/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3819/// destination element value type. 3820SDValue DAGCombiner:: 3821ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3822 MVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3823 3824 // If this is already the right type, we're done. 3825 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3826 3827 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3828 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3829 3830 // If this is a conversion of N elements of one type to N elements of another 3831 // type, convert each element. This handles FP<->INT cases. 3832 if (SrcBitSize == DstBitSize) { 3833 SmallVector<SDValue, 8> Ops; 3834 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3835 SDValue Op = BV->getOperand(i); 3836 // If the vector element type is not legal, the BUILD_VECTOR operands 3837 // are promoted and implicitly truncated. Make that explicit here. 3838 if (Op.getValueType() != SrcEltVT) 3839 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3840 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3841 DstEltVT, Op)); 3842 AddToWorkList(Ops.back().getNode()); 3843 } 3844 MVT VT = MVT::getVectorVT(DstEltVT, 3845 BV->getValueType(0).getVectorNumElements()); 3846 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3847 &Ops[0], Ops.size()); 3848 } 3849 3850 // Otherwise, we're growing or shrinking the elements. To avoid having to 3851 // handle annoying details of growing/shrinking FP values, we convert them to 3852 // int first. 3853 if (SrcEltVT.isFloatingPoint()) { 3854 // Convert the input float vector to a int vector where the elements are the 3855 // same sizes. 3856 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3857 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3858 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3859 SrcEltVT = IntVT; 3860 } 3861 3862 // Now we know the input is an integer vector. If the output is a FP type, 3863 // convert to integer first, then to FP of the right size. 3864 if (DstEltVT.isFloatingPoint()) { 3865 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3866 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3867 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3868 3869 // Next, convert to FP elements of the same size. 3870 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3871 } 3872 3873 // Okay, we know the src/dst types are both integers of differing types. 3874 // Handling growing first. 3875 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3876 if (SrcBitSize < DstBitSize) { 3877 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3878 3879 SmallVector<SDValue, 8> Ops; 3880 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3881 i += NumInputsPerOutput) { 3882 bool isLE = TLI.isLittleEndian(); 3883 APInt NewBits = APInt(DstBitSize, 0); 3884 bool EltIsUndef = true; 3885 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3886 // Shift the previously computed bits over. 3887 NewBits <<= SrcBitSize; 3888 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3889 if (Op.getOpcode() == ISD::UNDEF) continue; 3890 EltIsUndef = false; 3891 3892 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 3893 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 3894 } 3895 3896 if (EltIsUndef) 3897 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3898 else 3899 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3900 } 3901 3902 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3903 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3904 &Ops[0], Ops.size()); 3905 } 3906 3907 // Finally, this must be the case where we are shrinking elements: each input 3908 // turns into multiple outputs. 3909 bool isS2V = ISD::isScalarToVector(BV); 3910 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3911 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3912 SmallVector<SDValue, 8> Ops; 3913 3914 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3915 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3916 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3917 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3918 continue; 3919 } 3920 3921 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 3922 getAPIntValue()).zextOrTrunc(SrcBitSize); 3923 3924 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3925 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3926 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3927 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3928 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3929 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3930 Ops[0]); 3931 OpVal = OpVal.lshr(DstBitSize); 3932 } 3933 3934 // For big endian targets, swap the order of the pieces of each element. 3935 if (TLI.isBigEndian()) 3936 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3937 } 3938 3939 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3940 &Ops[0], Ops.size()); 3941} 3942 3943SDValue DAGCombiner::visitFADD(SDNode *N) { 3944 SDValue N0 = N->getOperand(0); 3945 SDValue N1 = N->getOperand(1); 3946 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3947 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3948 MVT VT = N->getValueType(0); 3949 3950 // fold vector ops 3951 if (VT.isVector()) { 3952 SDValue FoldedVOp = SimplifyVBinOp(N); 3953 if (FoldedVOp.getNode()) return FoldedVOp; 3954 } 3955 3956 // fold (fadd c1, c2) -> (fadd c1, c2) 3957 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3958 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3959 // canonicalize constant to RHS 3960 if (N0CFP && !N1CFP) 3961 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3962 // fold (fadd A, 0) -> A 3963 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3964 return N0; 3965 // fold (fadd A, (fneg B)) -> (fsub A, B) 3966 if (isNegatibleForFree(N1, LegalOperations) == 2) 3967 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3968 GetNegatedExpression(N1, DAG, LegalOperations)); 3969 // fold (fadd (fneg A), B) -> (fsub B, A) 3970 if (isNegatibleForFree(N0, LegalOperations) == 2) 3971 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3972 GetNegatedExpression(N0, DAG, LegalOperations)); 3973 3974 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3975 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3976 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3977 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3978 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3979 N0.getOperand(1), N1)); 3980 3981 return SDValue(); 3982} 3983 3984SDValue DAGCombiner::visitFSUB(SDNode *N) { 3985 SDValue N0 = N->getOperand(0); 3986 SDValue N1 = N->getOperand(1); 3987 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3988 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3989 MVT VT = N->getValueType(0); 3990 3991 // fold vector ops 3992 if (VT.isVector()) { 3993 SDValue FoldedVOp = SimplifyVBinOp(N); 3994 if (FoldedVOp.getNode()) return FoldedVOp; 3995 } 3996 3997 // fold (fsub c1, c2) -> c1-c2 3998 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3999 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4000 // fold (fsub A, 0) -> A 4001 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4002 return N0; 4003 // fold (fsub 0, B) -> -B 4004 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4005 if (isNegatibleForFree(N1, LegalOperations)) 4006 return GetNegatedExpression(N1, DAG, LegalOperations); 4007 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4008 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4009 } 4010 // fold (fsub A, (fneg B)) -> (fadd A, B) 4011 if (isNegatibleForFree(N1, LegalOperations)) 4012 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4013 GetNegatedExpression(N1, DAG, LegalOperations)); 4014 4015 return SDValue(); 4016} 4017 4018SDValue DAGCombiner::visitFMUL(SDNode *N) { 4019 SDValue N0 = N->getOperand(0); 4020 SDValue N1 = N->getOperand(1); 4021 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4022 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4023 MVT VT = N->getValueType(0); 4024 4025 // fold vector ops 4026 if (VT.isVector()) { 4027 SDValue FoldedVOp = SimplifyVBinOp(N); 4028 if (FoldedVOp.getNode()) return FoldedVOp; 4029 } 4030 4031 // fold (fmul c1, c2) -> c1*c2 4032 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4033 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4034 // canonicalize constant to RHS 4035 if (N0CFP && !N1CFP) 4036 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4037 // fold (fmul A, 0) -> 0 4038 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4039 return N1; 4040 // fold (fmul A, 0) -> 0, vector edition. 4041 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4042 return N1; 4043 // fold (fmul X, 2.0) -> (fadd X, X) 4044 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4045 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4046 // fold (fmul X, (fneg 1.0)) -> (fneg X) 4047 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4048 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4049 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4050 4051 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4052 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4053 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4054 // Both can be negated for free, check to see if at least one is cheaper 4055 // negated. 4056 if (LHSNeg == 2 || RHSNeg == 2) 4057 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4058 GetNegatedExpression(N0, DAG, LegalOperations), 4059 GetNegatedExpression(N1, DAG, LegalOperations)); 4060 } 4061 } 4062 4063 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4064 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4065 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4066 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4067 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4068 N0.getOperand(1), N1)); 4069 4070 return SDValue(); 4071} 4072 4073SDValue DAGCombiner::visitFDIV(SDNode *N) { 4074 SDValue N0 = N->getOperand(0); 4075 SDValue N1 = N->getOperand(1); 4076 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4077 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4078 MVT VT = N->getValueType(0); 4079 4080 // fold vector ops 4081 if (VT.isVector()) { 4082 SDValue FoldedVOp = SimplifyVBinOp(N); 4083 if (FoldedVOp.getNode()) return FoldedVOp; 4084 } 4085 4086 // fold (fdiv c1, c2) -> c1/c2 4087 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4088 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4089 4090 4091 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4092 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4093 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4094 // Both can be negated for free, check to see if at least one is cheaper 4095 // negated. 4096 if (LHSNeg == 2 || RHSNeg == 2) 4097 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4098 GetNegatedExpression(N0, DAG, LegalOperations), 4099 GetNegatedExpression(N1, DAG, LegalOperations)); 4100 } 4101 } 4102 4103 return SDValue(); 4104} 4105 4106SDValue DAGCombiner::visitFREM(SDNode *N) { 4107 SDValue N0 = N->getOperand(0); 4108 SDValue N1 = N->getOperand(1); 4109 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4110 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4111 MVT VT = N->getValueType(0); 4112 4113 // fold (frem c1, c2) -> fmod(c1,c2) 4114 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4115 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4116 4117 return SDValue(); 4118} 4119 4120SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4121 SDValue N0 = N->getOperand(0); 4122 SDValue N1 = N->getOperand(1); 4123 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4124 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4125 MVT VT = N->getValueType(0); 4126 4127 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4128 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4129 4130 if (N1CFP) { 4131 const APFloat& V = N1CFP->getValueAPF(); 4132 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4133 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4134 if (!V.isNegative()) { 4135 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4136 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4137 } else { 4138 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4139 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4140 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4141 } 4142 } 4143 4144 // copysign(fabs(x), y) -> copysign(x, y) 4145 // copysign(fneg(x), y) -> copysign(x, y) 4146 // copysign(copysign(x,z), y) -> copysign(x, y) 4147 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4148 N0.getOpcode() == ISD::FCOPYSIGN) 4149 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4150 N0.getOperand(0), N1); 4151 4152 // copysign(x, abs(y)) -> abs(x) 4153 if (N1.getOpcode() == ISD::FABS) 4154 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4155 4156 // copysign(x, copysign(y,z)) -> copysign(x, z) 4157 if (N1.getOpcode() == ISD::FCOPYSIGN) 4158 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4159 N0, N1.getOperand(1)); 4160 4161 // copysign(x, fp_extend(y)) -> copysign(x, y) 4162 // copysign(x, fp_round(y)) -> copysign(x, y) 4163 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4164 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4165 N0, N1.getOperand(0)); 4166 4167 return SDValue(); 4168} 4169 4170SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4171 SDValue N0 = N->getOperand(0); 4172 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4173 MVT VT = N->getValueType(0); 4174 MVT OpVT = N0.getValueType(); 4175 4176 // fold (sint_to_fp c1) -> c1fp 4177 if (N0C && OpVT != MVT::ppcf128) 4178 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4179 4180 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4181 // but UINT_TO_FP is legal on this target, try to convert. 4182 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4183 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4184 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4185 if (DAG.SignBitIsZero(N0)) 4186 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4187 } 4188 4189 return SDValue(); 4190} 4191 4192SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4193 SDValue N0 = N->getOperand(0); 4194 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4195 MVT VT = N->getValueType(0); 4196 MVT OpVT = N0.getValueType(); 4197 4198 // fold (uint_to_fp c1) -> c1fp 4199 if (N0C && OpVT != MVT::ppcf128) 4200 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4201 4202 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4203 // but SINT_TO_FP is legal on this target, try to convert. 4204 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4205 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4206 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4207 if (DAG.SignBitIsZero(N0)) 4208 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4209 } 4210 4211 return SDValue(); 4212} 4213 4214SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4215 SDValue N0 = N->getOperand(0); 4216 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4217 MVT VT = N->getValueType(0); 4218 4219 // fold (fp_to_sint c1fp) -> c1 4220 if (N0CFP) 4221 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4222 4223 return SDValue(); 4224} 4225 4226SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4227 SDValue N0 = N->getOperand(0); 4228 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4229 MVT VT = N->getValueType(0); 4230 4231 // fold (fp_to_uint c1fp) -> c1 4232 if (N0CFP && VT != MVT::ppcf128) 4233 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4234 4235 return SDValue(); 4236} 4237 4238SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4239 SDValue N0 = N->getOperand(0); 4240 SDValue N1 = N->getOperand(1); 4241 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4242 MVT VT = N->getValueType(0); 4243 4244 // fold (fp_round c1fp) -> c1fp 4245 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4246 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4247 4248 // fold (fp_round (fp_extend x)) -> x 4249 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4250 return N0.getOperand(0); 4251 4252 // fold (fp_round (fp_round x)) -> (fp_round x) 4253 if (N0.getOpcode() == ISD::FP_ROUND) { 4254 // This is a value preserving truncation if both round's are. 4255 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4256 N0.getNode()->getConstantOperandVal(1) == 1; 4257 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4258 DAG.getIntPtrConstant(IsTrunc)); 4259 } 4260 4261 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4262 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4263 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4264 N0.getOperand(0), N1); 4265 AddToWorkList(Tmp.getNode()); 4266 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4267 Tmp, N0.getOperand(1)); 4268 } 4269 4270 return SDValue(); 4271} 4272 4273SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4274 SDValue N0 = N->getOperand(0); 4275 MVT VT = N->getValueType(0); 4276 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4277 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4278 4279 // fold (fp_round_inreg c1fp) -> c1fp 4280 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4281 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4282 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4283 } 4284 4285 return SDValue(); 4286} 4287 4288SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4289 SDValue N0 = N->getOperand(0); 4290 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4291 MVT VT = N->getValueType(0); 4292 4293 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4294 if (N->hasOneUse() && 4295 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4296 return SDValue(); 4297 4298 // fold (fp_extend c1fp) -> c1fp 4299 if (N0CFP && VT != MVT::ppcf128) 4300 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4301 4302 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4303 // value of X. 4304 if (N0.getOpcode() == ISD::FP_ROUND 4305 && N0.getNode()->getConstantOperandVal(1) == 1) { 4306 SDValue In = N0.getOperand(0); 4307 if (In.getValueType() == VT) return In; 4308 if (VT.bitsLT(In.getValueType())) 4309 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4310 In, N0.getOperand(1)); 4311 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4312 } 4313 4314 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4315 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4316 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4317 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4318 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4319 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4320 LN0->getChain(), 4321 LN0->getBasePtr(), LN0->getSrcValue(), 4322 LN0->getSrcValueOffset(), 4323 N0.getValueType(), 4324 LN0->isVolatile(), LN0->getAlignment()); 4325 CombineTo(N, ExtLoad); 4326 CombineTo(N0.getNode(), 4327 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4328 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4329 ExtLoad.getValue(1)); 4330 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4331 } 4332 4333 return SDValue(); 4334} 4335 4336SDValue DAGCombiner::visitFNEG(SDNode *N) { 4337 SDValue N0 = N->getOperand(0); 4338 4339 if (isNegatibleForFree(N0, LegalOperations)) 4340 return GetNegatedExpression(N0, DAG, LegalOperations); 4341 4342 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4343 // constant pool values. 4344 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4345 N0.getOperand(0).getValueType().isInteger() && 4346 !N0.getOperand(0).getValueType().isVector()) { 4347 SDValue Int = N0.getOperand(0); 4348 MVT IntVT = Int.getValueType(); 4349 if (IntVT.isInteger() && !IntVT.isVector()) { 4350 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4351 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4352 AddToWorkList(Int.getNode()); 4353 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4354 N->getValueType(0), Int); 4355 } 4356 } 4357 4358 return SDValue(); 4359} 4360 4361SDValue DAGCombiner::visitFABS(SDNode *N) { 4362 SDValue N0 = N->getOperand(0); 4363 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4364 MVT VT = N->getValueType(0); 4365 4366 // fold (fabs c1) -> fabs(c1) 4367 if (N0CFP && VT != MVT::ppcf128) 4368 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4369 // fold (fabs (fabs x)) -> (fabs x) 4370 if (N0.getOpcode() == ISD::FABS) 4371 return N->getOperand(0); 4372 // fold (fabs (fneg x)) -> (fabs x) 4373 // fold (fabs (fcopysign x, y)) -> (fabs x) 4374 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4375 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4376 4377 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4378 // constant pool values. 4379 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4380 N0.getOperand(0).getValueType().isInteger() && 4381 !N0.getOperand(0).getValueType().isVector()) { 4382 SDValue Int = N0.getOperand(0); 4383 MVT IntVT = Int.getValueType(); 4384 if (IntVT.isInteger() && !IntVT.isVector()) { 4385 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4386 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4387 AddToWorkList(Int.getNode()); 4388 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4389 N->getValueType(0), Int); 4390 } 4391 } 4392 4393 return SDValue(); 4394} 4395 4396SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4397 SDValue Chain = N->getOperand(0); 4398 SDValue N1 = N->getOperand(1); 4399 SDValue N2 = N->getOperand(2); 4400 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4401 4402 // never taken branch, fold to chain 4403 if (N1C && N1C->isNullValue()) 4404 return Chain; 4405 // unconditional branch 4406 if (N1C && N1C->getAPIntValue() == 1) 4407 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4408 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4409 // on the target. 4410 if (N1.getOpcode() == ISD::SETCC && 4411 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4412 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4413 Chain, N1.getOperand(2), 4414 N1.getOperand(0), N1.getOperand(1), N2); 4415 } 4416 4417 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4418 // Match this pattern so that we can generate simpler code: 4419 // 4420 // %a = ... 4421 // %b = and i32 %a, 2 4422 // %c = srl i32 %b, 1 4423 // brcond i32 %c ... 4424 // 4425 // into 4426 // 4427 // %a = ... 4428 // %b = and %a, 2 4429 // %c = setcc eq %b, 0 4430 // brcond %c ... 4431 // 4432 // This applies only when the AND constant value has one bit set and the 4433 // SRL constant is equal to the log2 of the AND constant. The back-end is 4434 // smart enough to convert the result into a TEST/JMP sequence. 4435 SDValue Op0 = N1.getOperand(0); 4436 SDValue Op1 = N1.getOperand(1); 4437 4438 if (Op0.getOpcode() == ISD::AND && 4439 Op0.hasOneUse() && 4440 Op1.getOpcode() == ISD::Constant) { 4441 SDValue AndOp0 = Op0.getOperand(0); 4442 SDValue AndOp1 = Op0.getOperand(1); 4443 4444 if (AndOp1.getOpcode() == ISD::Constant) { 4445 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4446 4447 if (AndConst.isPowerOf2() && 4448 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4449 SDValue SetCC = 4450 DAG.getSetCC(N->getDebugLoc(), 4451 TLI.getSetCCResultType(Op0.getValueType()), 4452 Op0, DAG.getConstant(0, Op0.getValueType()), 4453 ISD::SETNE); 4454 4455 // Replace the uses of SRL with SETCC 4456 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4457 removeFromWorkList(N1.getNode()); 4458 DAG.DeleteNode(N1.getNode()); 4459 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4460 MVT::Other, Chain, SetCC, N2); 4461 } 4462 } 4463 } 4464 } 4465 4466 return SDValue(); 4467} 4468 4469// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4470// 4471SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4472 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4473 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4474 4475 // Use SimplifySetCC to simplify SETCC's. 4476 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4477 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4478 false); 4479 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4480 4481 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4482 4483 // fold br_cc true, dest -> br dest (unconditional branch) 4484 if (SCCC && !SCCC->isNullValue()) 4485 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4486 N->getOperand(0), N->getOperand(4)); 4487 // fold br_cc false, dest -> unconditional fall through 4488 if (SCCC && SCCC->isNullValue()) 4489 return N->getOperand(0); 4490 4491 // fold to a simpler setcc 4492 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4493 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4494 N->getOperand(0), Simp.getOperand(2), 4495 Simp.getOperand(0), Simp.getOperand(1), 4496 N->getOperand(4)); 4497 4498 return SDValue(); 4499} 4500 4501/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4502/// pre-indexed load / store when the base pointer is an add or subtract 4503/// and it has other uses besides the load / store. After the 4504/// transformation, the new indexed load / store has effectively folded 4505/// the add / subtract in and all of its other uses are redirected to the 4506/// new load / store. 4507bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4508 if (!LegalOperations) 4509 return false; 4510 4511 bool isLoad = true; 4512 SDValue Ptr; 4513 MVT VT; 4514 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4515 if (LD->isIndexed()) 4516 return false; 4517 VT = LD->getMemoryVT(); 4518 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4519 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4520 return false; 4521 Ptr = LD->getBasePtr(); 4522 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4523 if (ST->isIndexed()) 4524 return false; 4525 VT = ST->getMemoryVT(); 4526 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4527 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4528 return false; 4529 Ptr = ST->getBasePtr(); 4530 isLoad = false; 4531 } else { 4532 return false; 4533 } 4534 4535 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4536 // out. There is no reason to make this a preinc/predec. 4537 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4538 Ptr.getNode()->hasOneUse()) 4539 return false; 4540 4541 // Ask the target to do addressing mode selection. 4542 SDValue BasePtr; 4543 SDValue Offset; 4544 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4545 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4546 return false; 4547 // Don't create a indexed load / store with zero offset. 4548 if (isa<ConstantSDNode>(Offset) && 4549 cast<ConstantSDNode>(Offset)->isNullValue()) 4550 return false; 4551 4552 // Try turning it into a pre-indexed load / store except when: 4553 // 1) The new base ptr is a frame index. 4554 // 2) If N is a store and the new base ptr is either the same as or is a 4555 // predecessor of the value being stored. 4556 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4557 // that would create a cycle. 4558 // 4) All uses are load / store ops that use it as old base ptr. 4559 4560 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4561 // (plus the implicit offset) to a register to preinc anyway. 4562 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4563 return false; 4564 4565 // Check #2. 4566 if (!isLoad) { 4567 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4568 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4569 return false; 4570 } 4571 4572 // Now check for #3 and #4. 4573 bool RealUse = false; 4574 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4575 E = Ptr.getNode()->use_end(); I != E; ++I) { 4576 SDNode *Use = *I; 4577 if (Use == N) 4578 continue; 4579 if (Use->isPredecessorOf(N)) 4580 return false; 4581 4582 if (!((Use->getOpcode() == ISD::LOAD && 4583 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4584 (Use->getOpcode() == ISD::STORE && 4585 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4586 RealUse = true; 4587 } 4588 4589 if (!RealUse) 4590 return false; 4591 4592 SDValue Result; 4593 if (isLoad) 4594 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4595 BasePtr, Offset, AM); 4596 else 4597 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4598 BasePtr, Offset, AM); 4599 ++PreIndexedNodes; 4600 ++NodesCombined; 4601 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4602 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4603 DOUT << '\n'; 4604 WorkListRemover DeadNodes(*this); 4605 if (isLoad) { 4606 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4607 &DeadNodes); 4608 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4609 &DeadNodes); 4610 } else { 4611 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4612 &DeadNodes); 4613 } 4614 4615 // Finally, since the node is now dead, remove it from the graph. 4616 DAG.DeleteNode(N); 4617 4618 // Replace the uses of Ptr with uses of the updated base value. 4619 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4620 &DeadNodes); 4621 removeFromWorkList(Ptr.getNode()); 4622 DAG.DeleteNode(Ptr.getNode()); 4623 4624 return true; 4625} 4626 4627/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4628/// add / sub of the base pointer node into a post-indexed load / store. 4629/// The transformation folded the add / subtract into the new indexed 4630/// load / store effectively and all of its uses are redirected to the 4631/// new load / store. 4632bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4633 if (!LegalOperations) 4634 return false; 4635 4636 bool isLoad = true; 4637 SDValue Ptr; 4638 MVT VT; 4639 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4640 if (LD->isIndexed()) 4641 return false; 4642 VT = LD->getMemoryVT(); 4643 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4644 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4645 return false; 4646 Ptr = LD->getBasePtr(); 4647 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4648 if (ST->isIndexed()) 4649 return false; 4650 VT = ST->getMemoryVT(); 4651 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4652 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4653 return false; 4654 Ptr = ST->getBasePtr(); 4655 isLoad = false; 4656 } else { 4657 return false; 4658 } 4659 4660 if (Ptr.getNode()->hasOneUse()) 4661 return false; 4662 4663 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4664 E = Ptr.getNode()->use_end(); I != E; ++I) { 4665 SDNode *Op = *I; 4666 if (Op == N || 4667 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4668 continue; 4669 4670 SDValue BasePtr; 4671 SDValue Offset; 4672 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4673 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4674 if (Ptr == Offset) 4675 std::swap(BasePtr, Offset); 4676 if (Ptr != BasePtr) 4677 continue; 4678 // Don't create a indexed load / store with zero offset. 4679 if (isa<ConstantSDNode>(Offset) && 4680 cast<ConstantSDNode>(Offset)->isNullValue()) 4681 continue; 4682 4683 // Try turning it into a post-indexed load / store except when 4684 // 1) All uses are load / store ops that use it as base ptr. 4685 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4686 // nor a successor of N. Otherwise, if Op is folded that would 4687 // create a cycle. 4688 4689 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4690 continue; 4691 4692 // Check for #1. 4693 bool TryNext = false; 4694 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4695 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4696 SDNode *Use = *II; 4697 if (Use == Ptr.getNode()) 4698 continue; 4699 4700 // If all the uses are load / store addresses, then don't do the 4701 // transformation. 4702 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4703 bool RealUse = false; 4704 for (SDNode::use_iterator III = Use->use_begin(), 4705 EEE = Use->use_end(); III != EEE; ++III) { 4706 SDNode *UseUse = *III; 4707 if (!((UseUse->getOpcode() == ISD::LOAD && 4708 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4709 (UseUse->getOpcode() == ISD::STORE && 4710 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4711 RealUse = true; 4712 } 4713 4714 if (!RealUse) { 4715 TryNext = true; 4716 break; 4717 } 4718 } 4719 } 4720 4721 if (TryNext) 4722 continue; 4723 4724 // Check for #2 4725 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4726 SDValue Result = isLoad 4727 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4728 BasePtr, Offset, AM) 4729 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4730 BasePtr, Offset, AM); 4731 ++PostIndexedNodes; 4732 ++NodesCombined; 4733 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4734 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4735 DOUT << '\n'; 4736 WorkListRemover DeadNodes(*this); 4737 if (isLoad) { 4738 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4739 &DeadNodes); 4740 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4741 &DeadNodes); 4742 } else { 4743 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4744 &DeadNodes); 4745 } 4746 4747 // Finally, since the node is now dead, remove it from the graph. 4748 DAG.DeleteNode(N); 4749 4750 // Replace the uses of Use with uses of the updated base value. 4751 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4752 Result.getValue(isLoad ? 1 : 0), 4753 &DeadNodes); 4754 removeFromWorkList(Op); 4755 DAG.DeleteNode(Op); 4756 return true; 4757 } 4758 } 4759 } 4760 4761 return false; 4762} 4763 4764/// InferAlignment - If we can infer some alignment information from this 4765/// pointer, return it. 4766static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4767 // If this is a direct reference to a stack slot, use information about the 4768 // stack slot's alignment. 4769 int FrameIdx = 1 << 31; 4770 int64_t FrameOffset = 0; 4771 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4772 FrameIdx = FI->getIndex(); 4773 } else if (Ptr.getOpcode() == ISD::ADD && 4774 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4775 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4776 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4777 FrameOffset = Ptr.getConstantOperandVal(1); 4778 } 4779 4780 if (FrameIdx != (1 << 31)) { 4781 // FIXME: Handle FI+CST. 4782 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4783 if (MFI.isFixedObjectIndex(FrameIdx)) { 4784 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4785 4786 // The alignment of the frame index can be determined from its offset from 4787 // the incoming frame position. If the frame object is at offset 32 and 4788 // the stack is guaranteed to be 16-byte aligned, then we know that the 4789 // object is 16-byte aligned. 4790 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4791 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4792 4793 // Finally, the frame object itself may have a known alignment. Factor 4794 // the alignment + offset into a new alignment. For example, if we know 4795 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4796 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4797 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4798 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4799 FrameOffset); 4800 return std::max(Align, FIInfoAlign); 4801 } 4802 } 4803 4804 return 0; 4805} 4806 4807SDValue DAGCombiner::visitLOAD(SDNode *N) { 4808 LoadSDNode *LD = cast<LoadSDNode>(N); 4809 SDValue Chain = LD->getChain(); 4810 SDValue Ptr = LD->getBasePtr(); 4811 4812 // Try to infer better alignment information than the load already has. 4813 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4814 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4815 if (Align > LD->getAlignment()) 4816 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4817 LD->getValueType(0), 4818 Chain, Ptr, LD->getSrcValue(), 4819 LD->getSrcValueOffset(), LD->getMemoryVT(), 4820 LD->isVolatile(), Align); 4821 } 4822 } 4823 4824 // If load is not volatile and there are no uses of the loaded value (and 4825 // the updated indexed value in case of indexed loads), change uses of the 4826 // chain value into uses of the chain input (i.e. delete the dead load). 4827 if (!LD->isVolatile()) { 4828 if (N->getValueType(1) == MVT::Other) { 4829 // Unindexed loads. 4830 if (N->hasNUsesOfValue(0, 0)) { 4831 // It's not safe to use the two value CombineTo variant here. e.g. 4832 // v1, chain2 = load chain1, loc 4833 // v2, chain3 = load chain2, loc 4834 // v3 = add v2, c 4835 // Now we replace use of chain2 with chain1. This makes the second load 4836 // isomorphic to the one we are deleting, and thus makes this load live. 4837 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4838 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4839 DOUT << "\n"; 4840 WorkListRemover DeadNodes(*this); 4841 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4842 4843 if (N->use_empty()) { 4844 removeFromWorkList(N); 4845 DAG.DeleteNode(N); 4846 } 4847 4848 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4849 } 4850 } else { 4851 // Indexed loads. 4852 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4853 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4854 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4855 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4856 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4857 DOUT << " and 2 other values\n"; 4858 WorkListRemover DeadNodes(*this); 4859 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4860 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4861 DAG.getUNDEF(N->getValueType(1)), 4862 &DeadNodes); 4863 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4864 removeFromWorkList(N); 4865 DAG.DeleteNode(N); 4866 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4867 } 4868 } 4869 } 4870 4871 // If this load is directly stored, replace the load value with the stored 4872 // value. 4873 // TODO: Handle store large -> read small portion. 4874 // TODO: Handle TRUNCSTORE/LOADEXT 4875 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4876 !LD->isVolatile()) { 4877 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4878 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4879 if (PrevST->getBasePtr() == Ptr && 4880 PrevST->getValue().getValueType() == N->getValueType(0)) 4881 return CombineTo(N, Chain.getOperand(1), Chain); 4882 } 4883 } 4884 4885 if (CombinerAA) { 4886 // Walk up chain skipping non-aliasing memory nodes. 4887 SDValue BetterChain = FindBetterChain(N, Chain); 4888 4889 // If there is a better chain. 4890 if (Chain != BetterChain) { 4891 SDValue ReplLoad; 4892 4893 // Replace the chain to void dependency. 4894 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4895 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4896 BetterChain, Ptr, 4897 LD->getSrcValue(), LD->getSrcValueOffset(), 4898 LD->isVolatile(), LD->getAlignment()); 4899 } else { 4900 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4901 LD->getValueType(0), 4902 BetterChain, Ptr, LD->getSrcValue(), 4903 LD->getSrcValueOffset(), 4904 LD->getMemoryVT(), 4905 LD->isVolatile(), 4906 LD->getAlignment()); 4907 } 4908 4909 // Create token factor to keep old chain connected. 4910 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4911 MVT::Other, Chain, ReplLoad.getValue(1)); 4912 4913 // Replace uses with load result and token factor. Don't add users 4914 // to work list. 4915 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4916 } 4917 } 4918 4919 // Try transforming N to an indexed load. 4920 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4921 return SDValue(N, 0); 4922 4923 return SDValue(); 4924} 4925 4926 4927/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 4928/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 4929/// of the loaded bits, try narrowing the load and store if it would end up 4930/// being a win for performance or code size. 4931SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 4932 StoreSDNode *ST = cast<StoreSDNode>(N); 4933 if (ST->isVolatile()) 4934 return SDValue(); 4935 4936 SDValue Chain = ST->getChain(); 4937 SDValue Value = ST->getValue(); 4938 SDValue Ptr = ST->getBasePtr(); 4939 MVT VT = Value.getValueType(); 4940 4941 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 4942 return SDValue(); 4943 4944 unsigned Opc = Value.getOpcode(); 4945 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 4946 Value.getOperand(1).getOpcode() != ISD::Constant) 4947 return SDValue(); 4948 4949 SDValue N0 = Value.getOperand(0); 4950 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 4951 LoadSDNode *LD = cast<LoadSDNode>(N0); 4952 if (LD->getBasePtr() != Ptr) 4953 return SDValue(); 4954 4955 // Find the type to narrow it the load / op / store to. 4956 SDValue N1 = Value.getOperand(1); 4957 unsigned BitWidth = N1.getValueSizeInBits(); 4958 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 4959 if (Opc == ISD::AND) 4960 Imm ^= APInt::getAllOnesValue(BitWidth); 4961 if (Imm == 0 || Imm.isAllOnesValue()) 4962 return SDValue(); 4963 unsigned ShAmt = Imm.countTrailingZeros(); 4964 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 4965 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 4966 MVT NewVT = MVT::getIntegerVT(NewBW); 4967 while (NewBW < BitWidth && 4968 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 4969 TLI.isNarrowingProfitable(VT, NewVT))) { 4970 NewBW = NextPowerOf2(NewBW); 4971 NewVT = MVT::getIntegerVT(NewBW); 4972 } 4973 if (NewBW >= BitWidth) 4974 return SDValue(); 4975 4976 // If the lsb changed does not start at the type bitwidth boundary, 4977 // start at the previous one. 4978 if (ShAmt % NewBW) 4979 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 4980 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 4981 if ((Imm & Mask) == Imm) { 4982 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 4983 if (Opc == ISD::AND) 4984 NewImm ^= APInt::getAllOnesValue(NewBW); 4985 uint64_t PtrOff = ShAmt / 8; 4986 // For big endian targets, we need to adjust the offset to the pointer to 4987 // load the correct bytes. 4988 if (TLI.isBigEndian()) 4989 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 4990 4991 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 4992 if (NewAlign < 4993 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT( 4994 *DAG.getContext()))) 4995 return SDValue(); 4996 4997 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 4998 Ptr.getValueType(), Ptr, 4999 DAG.getConstant(PtrOff, Ptr.getValueType())); 5000 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5001 LD->getChain(), NewPtr, 5002 LD->getSrcValue(), LD->getSrcValueOffset(), 5003 LD->isVolatile(), NewAlign); 5004 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5005 DAG.getConstant(NewImm, NewVT)); 5006 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5007 NewVal, NewPtr, 5008 ST->getSrcValue(), ST->getSrcValueOffset(), 5009 false, NewAlign); 5010 5011 AddToWorkList(NewPtr.getNode()); 5012 AddToWorkList(NewLD.getNode()); 5013 AddToWorkList(NewVal.getNode()); 5014 WorkListRemover DeadNodes(*this); 5015 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5016 &DeadNodes); 5017 ++OpsNarrowed; 5018 return NewST; 5019 } 5020 } 5021 5022 return SDValue(); 5023} 5024 5025SDValue DAGCombiner::visitSTORE(SDNode *N) { 5026 StoreSDNode *ST = cast<StoreSDNode>(N); 5027 SDValue Chain = ST->getChain(); 5028 SDValue Value = ST->getValue(); 5029 SDValue Ptr = ST->getBasePtr(); 5030 5031 // Try to infer better alignment information than the store already has. 5032 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5033 if (unsigned Align = InferAlignment(Ptr, DAG)) { 5034 if (Align > ST->getAlignment()) 5035 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5036 Ptr, ST->getSrcValue(), 5037 ST->getSrcValueOffset(), ST->getMemoryVT(), 5038 ST->isVolatile(), Align); 5039 } 5040 } 5041 5042 // If this is a store of a bit convert, store the input value if the 5043 // resultant store does not need a higher alignment than the original. 5044 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5045 ST->isUnindexed()) { 5046 unsigned OrigAlign = ST->getAlignment(); 5047 MVT SVT = Value.getOperand(0).getValueType(); 5048 unsigned Align = TLI.getTargetData()-> 5049 getABITypeAlignment(SVT.getTypeForMVT(*DAG.getContext())); 5050 if (Align <= OrigAlign && 5051 ((!LegalOperations && !ST->isVolatile()) || 5052 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5053 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5054 Ptr, ST->getSrcValue(), 5055 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5056 } 5057 5058 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5059 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5060 // NOTE: If the original store is volatile, this transform must not increase 5061 // the number of stores. For example, on x86-32 an f64 can be stored in one 5062 // processor operation but an i64 (which is not legal) requires two. So the 5063 // transform should not be done in this case. 5064 if (Value.getOpcode() != ISD::TargetConstantFP) { 5065 SDValue Tmp; 5066 switch (CFP->getValueType(0).getSimpleVT()) { 5067 default: llvm_unreachable("Unknown FP type"); 5068 case MVT::f80: // We don't do this for these yet. 5069 case MVT::f128: 5070 case MVT::ppcf128: 5071 break; 5072 case MVT::f32: 5073 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5074 !ST->isVolatile()) || 5075 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5076 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5077 bitcastToAPInt().getZExtValue(), MVT::i32); 5078 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5079 Ptr, ST->getSrcValue(), 5080 ST->getSrcValueOffset(), ST->isVolatile(), 5081 ST->getAlignment()); 5082 } 5083 break; 5084 case MVT::f64: 5085 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5086 !ST->isVolatile()) || 5087 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5088 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5089 getZExtValue(), MVT::i64); 5090 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5091 Ptr, ST->getSrcValue(), 5092 ST->getSrcValueOffset(), ST->isVolatile(), 5093 ST->getAlignment()); 5094 } else if (!ST->isVolatile() && 5095 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5096 // Many FP stores are not made apparent until after legalize, e.g. for 5097 // argument passing. Since this is so common, custom legalize the 5098 // 64-bit integer store into two 32-bit stores. 5099 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5100 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5101 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5102 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5103 5104 int SVOffset = ST->getSrcValueOffset(); 5105 unsigned Alignment = ST->getAlignment(); 5106 bool isVolatile = ST->isVolatile(); 5107 5108 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5109 Ptr, ST->getSrcValue(), 5110 ST->getSrcValueOffset(), 5111 isVolatile, ST->getAlignment()); 5112 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5113 DAG.getConstant(4, Ptr.getValueType())); 5114 SVOffset += 4; 5115 Alignment = MinAlign(Alignment, 4U); 5116 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5117 Ptr, ST->getSrcValue(), 5118 SVOffset, isVolatile, Alignment); 5119 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5120 St0, St1); 5121 } 5122 5123 break; 5124 } 5125 } 5126 } 5127 5128 if (CombinerAA) { 5129 // Walk up chain skipping non-aliasing memory nodes. 5130 SDValue BetterChain = FindBetterChain(N, Chain); 5131 5132 // If there is a better chain. 5133 if (Chain != BetterChain) { 5134 // Replace the chain to avoid dependency. 5135 SDValue ReplStore; 5136 if (ST->isTruncatingStore()) { 5137 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5138 ST->getSrcValue(),ST->getSrcValueOffset(), 5139 ST->getMemoryVT(), 5140 ST->isVolatile(), ST->getAlignment()); 5141 } else { 5142 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5143 ST->getSrcValue(), ST->getSrcValueOffset(), 5144 ST->isVolatile(), ST->getAlignment()); 5145 } 5146 5147 // Create token to keep both nodes around. 5148 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5149 MVT::Other, Chain, ReplStore); 5150 5151 // Don't add users to work list. 5152 return CombineTo(N, Token, false); 5153 } 5154 } 5155 5156 // Try transforming N to an indexed store. 5157 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5158 return SDValue(N, 0); 5159 5160 // FIXME: is there such a thing as a truncating indexed store? 5161 if (ST->isTruncatingStore() && ST->isUnindexed() && 5162 Value.getValueType().isInteger()) { 5163 // See if we can simplify the input to this truncstore with knowledge that 5164 // only the low bits are being used. For example: 5165 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5166 SDValue Shorter = 5167 GetDemandedBits(Value, 5168 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5169 ST->getMemoryVT().getSizeInBits())); 5170 AddToWorkList(Value.getNode()); 5171 if (Shorter.getNode()) 5172 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5173 Ptr, ST->getSrcValue(), 5174 ST->getSrcValueOffset(), ST->getMemoryVT(), 5175 ST->isVolatile(), ST->getAlignment()); 5176 5177 // Otherwise, see if we can simplify the operation with 5178 // SimplifyDemandedBits, which only works if the value has a single use. 5179 if (SimplifyDemandedBits(Value, 5180 APInt::getLowBitsSet( 5181 Value.getValueSizeInBits(), 5182 ST->getMemoryVT().getSizeInBits()))) 5183 return SDValue(N, 0); 5184 } 5185 5186 // If this is a load followed by a store to the same location, then the store 5187 // is dead/noop. 5188 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5189 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5190 ST->isUnindexed() && !ST->isVolatile() && 5191 // There can't be any side effects between the load and store, such as 5192 // a call or store. 5193 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5194 // The store is dead, remove it. 5195 return Chain; 5196 } 5197 } 5198 5199 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5200 // truncating store. We can do this even if this is already a truncstore. 5201 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5202 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5203 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5204 ST->getMemoryVT())) { 5205 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5206 Ptr, ST->getSrcValue(), 5207 ST->getSrcValueOffset(), ST->getMemoryVT(), 5208 ST->isVolatile(), ST->getAlignment()); 5209 } 5210 5211 return ReduceLoadOpStoreWidth(N); 5212} 5213 5214SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5215 SDValue InVec = N->getOperand(0); 5216 SDValue InVal = N->getOperand(1); 5217 SDValue EltNo = N->getOperand(2); 5218 5219 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5220 // vector with the inserted element. 5221 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5222 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5223 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5224 InVec.getNode()->op_end()); 5225 if (Elt < Ops.size()) 5226 Ops[Elt] = InVal; 5227 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5228 InVec.getValueType(), &Ops[0], Ops.size()); 5229 } 5230 // If the invec is an UNDEF and if EltNo is a constant, create a new 5231 // BUILD_VECTOR with undef elements and the inserted element. 5232 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5233 isa<ConstantSDNode>(EltNo)) { 5234 MVT VT = InVec.getValueType(); 5235 MVT EVT = VT.getVectorElementType(); 5236 unsigned NElts = VT.getVectorNumElements(); 5237 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT)); 5238 5239 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5240 if (Elt < Ops.size()) 5241 Ops[Elt] = InVal; 5242 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5243 InVec.getValueType(), &Ops[0], Ops.size()); 5244 } 5245 return SDValue(); 5246} 5247 5248SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5249 // (vextract (scalar_to_vector val, 0) -> val 5250 SDValue InVec = N->getOperand(0); 5251 5252 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5253 // If the operand is wider than the vector element type then it is implicitly 5254 // truncated. Make that explicit here. 5255 MVT EltVT = InVec.getValueType().getVectorElementType(); 5256 SDValue InOp = InVec.getOperand(0); 5257 if (InOp.getValueType() != EltVT) 5258 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5259 return InOp; 5260 } 5261 5262 // Perform only after legalization to ensure build_vector / vector_shuffle 5263 // optimizations have already been done. 5264 if (!LegalOperations) return SDValue(); 5265 5266 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5267 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5268 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5269 SDValue EltNo = N->getOperand(1); 5270 5271 if (isa<ConstantSDNode>(EltNo)) { 5272 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5273 bool NewLoad = false; 5274 bool BCNumEltsChanged = false; 5275 MVT VT = InVec.getValueType(); 5276 MVT EVT = VT.getVectorElementType(); 5277 MVT LVT = EVT; 5278 5279 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5280 MVT BCVT = InVec.getOperand(0).getValueType(); 5281 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5282 return SDValue(); 5283 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5284 BCNumEltsChanged = true; 5285 InVec = InVec.getOperand(0); 5286 EVT = BCVT.getVectorElementType(); 5287 NewLoad = true; 5288 } 5289 5290 LoadSDNode *LN0 = NULL; 5291 const ShuffleVectorSDNode *SVN = NULL; 5292 if (ISD::isNormalLoad(InVec.getNode())) { 5293 LN0 = cast<LoadSDNode>(InVec); 5294 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5295 InVec.getOperand(0).getValueType() == EVT && 5296 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5297 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5298 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5299 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5300 // => 5301 // (load $addr+1*size) 5302 5303 // If the bit convert changed the number of elements, it is unsafe 5304 // to examine the mask. 5305 if (BCNumEltsChanged) 5306 return SDValue(); 5307 5308 // Select the input vector, guarding against out of range extract vector. 5309 unsigned NumElems = VT.getVectorNumElements(); 5310 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5311 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5312 5313 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5314 InVec = InVec.getOperand(0); 5315 if (ISD::isNormalLoad(InVec.getNode())) { 5316 LN0 = cast<LoadSDNode>(InVec); 5317 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5318 } 5319 } 5320 5321 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5322 return SDValue(); 5323 5324 unsigned Align = LN0->getAlignment(); 5325 if (NewLoad) { 5326 // Check the resultant load doesn't need a higher alignment than the 5327 // original load. 5328 unsigned NewAlign = 5329 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT( 5330 *DAG.getContext())); 5331 5332 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5333 return SDValue(); 5334 5335 Align = NewAlign; 5336 } 5337 5338 SDValue NewPtr = LN0->getBasePtr(); 5339 if (Elt) { 5340 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5341 MVT PtrType = NewPtr.getValueType(); 5342 if (TLI.isBigEndian()) 5343 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5344 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5345 DAG.getConstant(PtrOff, PtrType)); 5346 } 5347 5348 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5349 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5350 LN0->isVolatile(), Align); 5351 } 5352 5353 return SDValue(); 5354} 5355 5356SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5357 unsigned NumInScalars = N->getNumOperands(); 5358 MVT VT = N->getValueType(0); 5359 MVT EltType = VT.getVectorElementType(); 5360 5361 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5362 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5363 // at most two distinct vectors, turn this into a shuffle node. 5364 SDValue VecIn1, VecIn2; 5365 for (unsigned i = 0; i != NumInScalars; ++i) { 5366 // Ignore undef inputs. 5367 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5368 5369 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5370 // constant index, bail out. 5371 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5372 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5373 VecIn1 = VecIn2 = SDValue(0, 0); 5374 break; 5375 } 5376 5377 // If the input vector type disagrees with the result of the build_vector, 5378 // we can't make a shuffle. 5379 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5380 if (ExtractedFromVec.getValueType() != VT) { 5381 VecIn1 = VecIn2 = SDValue(0, 0); 5382 break; 5383 } 5384 5385 // Otherwise, remember this. We allow up to two distinct input vectors. 5386 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5387 continue; 5388 5389 if (VecIn1.getNode() == 0) { 5390 VecIn1 = ExtractedFromVec; 5391 } else if (VecIn2.getNode() == 0) { 5392 VecIn2 = ExtractedFromVec; 5393 } else { 5394 // Too many inputs. 5395 VecIn1 = VecIn2 = SDValue(0, 0); 5396 break; 5397 } 5398 } 5399 5400 // If everything is good, we can make a shuffle operation. 5401 if (VecIn1.getNode()) { 5402 SmallVector<int, 8> Mask; 5403 for (unsigned i = 0; i != NumInScalars; ++i) { 5404 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5405 Mask.push_back(-1); 5406 continue; 5407 } 5408 5409 // If extracting from the first vector, just use the index directly. 5410 SDValue Extract = N->getOperand(i); 5411 SDValue ExtVal = Extract.getOperand(1); 5412 if (Extract.getOperand(0) == VecIn1) { 5413 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5414 if (ExtIndex > VT.getVectorNumElements()) 5415 return SDValue(); 5416 5417 Mask.push_back(ExtIndex); 5418 continue; 5419 } 5420 5421 // Otherwise, use InIdx + VecSize 5422 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5423 Mask.push_back(Idx+NumInScalars); 5424 } 5425 5426 // Add count and size info. 5427 if (!TLI.isTypeLegal(VT) && LegalTypes) 5428 return SDValue(); 5429 5430 // Return the new VECTOR_SHUFFLE node. 5431 SDValue Ops[2]; 5432 Ops[0] = VecIn1; 5433 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5434 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5435 } 5436 5437 return SDValue(); 5438} 5439 5440SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5441 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5442 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5443 // inputs come from at most two distinct vectors, turn this into a shuffle 5444 // node. 5445 5446 // If we only have one input vector, we don't need to do any concatenation. 5447 if (N->getNumOperands() == 1) 5448 return N->getOperand(0); 5449 5450 return SDValue(); 5451} 5452 5453SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5454 return SDValue(); 5455 5456 MVT VT = N->getValueType(0); 5457 unsigned NumElts = VT.getVectorNumElements(); 5458 5459 SDValue N0 = N->getOperand(0); 5460 SDValue N1 = N->getOperand(1); 5461 5462 assert(N0.getValueType().getVectorNumElements() == NumElts && 5463 "Vector shuffle must be normalized in DAG"); 5464 5465 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5466 5467 // If it is a splat, check if the argument vector is a build_vector with 5468 // all scalar elements the same. 5469 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5470 SDNode *V = N0.getNode(); 5471 5472 5473 // If this is a bit convert that changes the element type of the vector but 5474 // not the number of vector elements, look through it. Be careful not to 5475 // look though conversions that change things like v4f32 to v2f64. 5476 if (V->getOpcode() == ISD::BIT_CONVERT) { 5477 SDValue ConvInput = V->getOperand(0); 5478 if (ConvInput.getValueType().isVector() && 5479 ConvInput.getValueType().getVectorNumElements() == NumElts) 5480 V = ConvInput.getNode(); 5481 } 5482 5483 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5484 unsigned NumElems = V->getNumOperands(); 5485 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5486 if (NumElems > BaseIdx) { 5487 SDValue Base; 5488 bool AllSame = true; 5489 for (unsigned i = 0; i != NumElems; ++i) { 5490 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5491 Base = V->getOperand(i); 5492 break; 5493 } 5494 } 5495 // Splat of <u, u, u, u>, return <u, u, u, u> 5496 if (!Base.getNode()) 5497 return N0; 5498 for (unsigned i = 0; i != NumElems; ++i) { 5499 if (V->getOperand(i) != Base) { 5500 AllSame = false; 5501 break; 5502 } 5503 } 5504 // Splat of <x, x, x, x>, return <x, x, x, x> 5505 if (AllSame) 5506 return N0; 5507 } 5508 } 5509 } 5510 return SDValue(); 5511} 5512 5513/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5514/// an AND to a vector_shuffle with the destination vector and a zero vector. 5515/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5516/// vector_shuffle V, Zero, <0, 4, 2, 4> 5517SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5518 MVT VT = N->getValueType(0); 5519 DebugLoc dl = N->getDebugLoc(); 5520 SDValue LHS = N->getOperand(0); 5521 SDValue RHS = N->getOperand(1); 5522 if (N->getOpcode() == ISD::AND) { 5523 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5524 RHS = RHS.getOperand(0); 5525 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5526 SmallVector<int, 8> Indices; 5527 unsigned NumElts = RHS.getNumOperands(); 5528 for (unsigned i = 0; i != NumElts; ++i) { 5529 SDValue Elt = RHS.getOperand(i); 5530 if (!isa<ConstantSDNode>(Elt)) 5531 return SDValue(); 5532 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5533 Indices.push_back(i); 5534 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5535 Indices.push_back(NumElts); 5536 else 5537 return SDValue(); 5538 } 5539 5540 // Let's see if the target supports this vector_shuffle. 5541 MVT RVT = RHS.getValueType(); 5542 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5543 return SDValue(); 5544 5545 // Return the new VECTOR_SHUFFLE node. 5546 MVT EVT = RVT.getVectorElementType(); 5547 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5548 DAG.getConstant(0, EVT)); 5549 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5550 RVT, &ZeroOps[0], ZeroOps.size()); 5551 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5552 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5553 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5554 } 5555 } 5556 5557 return SDValue(); 5558} 5559 5560/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5561SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5562 // After legalize, the target may be depending on adds and other 5563 // binary ops to provide legal ways to construct constants or other 5564 // things. Simplifying them may result in a loss of legality. 5565 if (LegalOperations) return SDValue(); 5566 5567 MVT VT = N->getValueType(0); 5568 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5569 5570 MVT EltType = VT.getVectorElementType(); 5571 SDValue LHS = N->getOperand(0); 5572 SDValue RHS = N->getOperand(1); 5573 SDValue Shuffle = XformToShuffleWithZero(N); 5574 if (Shuffle.getNode()) return Shuffle; 5575 5576 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5577 // this operation. 5578 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5579 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5580 SmallVector<SDValue, 8> Ops; 5581 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5582 SDValue LHSOp = LHS.getOperand(i); 5583 SDValue RHSOp = RHS.getOperand(i); 5584 // If these two elements can't be folded, bail out. 5585 if ((LHSOp.getOpcode() != ISD::UNDEF && 5586 LHSOp.getOpcode() != ISD::Constant && 5587 LHSOp.getOpcode() != ISD::ConstantFP) || 5588 (RHSOp.getOpcode() != ISD::UNDEF && 5589 RHSOp.getOpcode() != ISD::Constant && 5590 RHSOp.getOpcode() != ISD::ConstantFP)) 5591 break; 5592 5593 // Can't fold divide by zero. 5594 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5595 N->getOpcode() == ISD::FDIV) { 5596 if ((RHSOp.getOpcode() == ISD::Constant && 5597 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5598 (RHSOp.getOpcode() == ISD::ConstantFP && 5599 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5600 break; 5601 } 5602 5603 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5604 EltType, LHSOp, RHSOp)); 5605 AddToWorkList(Ops.back().getNode()); 5606 assert((Ops.back().getOpcode() == ISD::UNDEF || 5607 Ops.back().getOpcode() == ISD::Constant || 5608 Ops.back().getOpcode() == ISD::ConstantFP) && 5609 "Scalar binop didn't fold!"); 5610 } 5611 5612 if (Ops.size() == LHS.getNumOperands()) { 5613 MVT VT = LHS.getValueType(); 5614 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5615 &Ops[0], Ops.size()); 5616 } 5617 } 5618 5619 return SDValue(); 5620} 5621 5622SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5623 SDValue N1, SDValue N2){ 5624 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5625 5626 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5627 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5628 5629 // If we got a simplified select_cc node back from SimplifySelectCC, then 5630 // break it down into a new SETCC node, and a new SELECT node, and then return 5631 // the SELECT node, since we were called with a SELECT node. 5632 if (SCC.getNode()) { 5633 // Check to see if we got a select_cc back (to turn into setcc/select). 5634 // Otherwise, just return whatever node we got back, like fabs. 5635 if (SCC.getOpcode() == ISD::SELECT_CC) { 5636 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5637 N0.getValueType(), 5638 SCC.getOperand(0), SCC.getOperand(1), 5639 SCC.getOperand(4)); 5640 AddToWorkList(SETCC.getNode()); 5641 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5642 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5643 } 5644 5645 return SCC; 5646 } 5647 return SDValue(); 5648} 5649 5650/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5651/// are the two values being selected between, see if we can simplify the 5652/// select. Callers of this should assume that TheSelect is deleted if this 5653/// returns true. As such, they should return the appropriate thing (e.g. the 5654/// node) back to the top-level of the DAG combiner loop to avoid it being 5655/// looked at. 5656bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5657 SDValue RHS) { 5658 5659 // If this is a select from two identical things, try to pull the operation 5660 // through the select. 5661 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5662 // If this is a load and the token chain is identical, replace the select 5663 // of two loads with a load through a select of the address to load from. 5664 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5665 // constants have been dropped into the constant pool. 5666 if (LHS.getOpcode() == ISD::LOAD && 5667 // Do not let this transformation reduce the number of volatile loads. 5668 !cast<LoadSDNode>(LHS)->isVolatile() && 5669 !cast<LoadSDNode>(RHS)->isVolatile() && 5670 // Token chains must be identical. 5671 LHS.getOperand(0) == RHS.getOperand(0)) { 5672 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5673 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5674 5675 // If this is an EXTLOAD, the VT's must match. 5676 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5677 // FIXME: this conflates two src values, discarding one. This is not 5678 // the right thing to do, but nothing uses srcvalues now. When they do, 5679 // turn SrcValue into a list of locations. 5680 SDValue Addr; 5681 if (TheSelect->getOpcode() == ISD::SELECT) { 5682 // Check that the condition doesn't reach either load. If so, folding 5683 // this will induce a cycle into the DAG. 5684 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5685 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5686 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5687 LLD->getBasePtr().getValueType(), 5688 TheSelect->getOperand(0), LLD->getBasePtr(), 5689 RLD->getBasePtr()); 5690 } 5691 } else { 5692 // Check that the condition doesn't reach either load. If so, folding 5693 // this will induce a cycle into the DAG. 5694 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5695 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5696 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5697 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5698 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5699 LLD->getBasePtr().getValueType(), 5700 TheSelect->getOperand(0), 5701 TheSelect->getOperand(1), 5702 LLD->getBasePtr(), RLD->getBasePtr(), 5703 TheSelect->getOperand(4)); 5704 } 5705 } 5706 5707 if (Addr.getNode()) { 5708 SDValue Load; 5709 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5710 Load = DAG.getLoad(TheSelect->getValueType(0), 5711 TheSelect->getDebugLoc(), 5712 LLD->getChain(), 5713 Addr,LLD->getSrcValue(), 5714 LLD->getSrcValueOffset(), 5715 LLD->isVolatile(), 5716 LLD->getAlignment()); 5717 } else { 5718 Load = DAG.getExtLoad(LLD->getExtensionType(), 5719 TheSelect->getDebugLoc(), 5720 TheSelect->getValueType(0), 5721 LLD->getChain(), Addr, LLD->getSrcValue(), 5722 LLD->getSrcValueOffset(), 5723 LLD->getMemoryVT(), 5724 LLD->isVolatile(), 5725 LLD->getAlignment()); 5726 } 5727 5728 // Users of the select now use the result of the load. 5729 CombineTo(TheSelect, Load); 5730 5731 // Users of the old loads now use the new load's chain. We know the 5732 // old-load value is dead now. 5733 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5734 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5735 return true; 5736 } 5737 } 5738 } 5739 } 5740 5741 return false; 5742} 5743 5744/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5745/// where 'cond' is the comparison specified by CC. 5746SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5747 SDValue N2, SDValue N3, 5748 ISD::CondCode CC, bool NotExtCompare) { 5749 // (x ? y : y) -> y. 5750 if (N2 == N3) return N2; 5751 5752 MVT VT = N2.getValueType(); 5753 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5754 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5755 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5756 5757 // Determine if the condition we're dealing with is constant 5758 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5759 N0, N1, CC, DL, false); 5760 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5761 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5762 5763 // fold select_cc true, x, y -> x 5764 if (SCCC && !SCCC->isNullValue()) 5765 return N2; 5766 // fold select_cc false, x, y -> y 5767 if (SCCC && SCCC->isNullValue()) 5768 return N3; 5769 5770 // Check to see if we can simplify the select into an fabs node 5771 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5772 // Allow either -0.0 or 0.0 5773 if (CFP->getValueAPF().isZero()) { 5774 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5775 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5776 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5777 N2 == N3.getOperand(0)) 5778 return DAG.getNode(ISD::FABS, DL, VT, N0); 5779 5780 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5781 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5782 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5783 N2.getOperand(0) == N3) 5784 return DAG.getNode(ISD::FABS, DL, VT, N3); 5785 } 5786 } 5787 5788 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5789 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5790 // in it. This is a win when the constant is not otherwise available because 5791 // it replaces two constant pool loads with one. We only do this if the FP 5792 // type is known to be legal, because if it isn't, then we are before legalize 5793 // types an we want the other legalization to happen first (e.g. to avoid 5794 // messing with soft float) and if the ConstantFP is not legal, because if 5795 // it is legal, we may not need to store the FP constant in a constant pool. 5796 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5797 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5798 if (TLI.isTypeLegal(N2.getValueType()) && 5799 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5800 TargetLowering::Legal) && 5801 // If both constants have multiple uses, then we won't need to do an 5802 // extra load, they are likely around in registers for other users. 5803 (TV->hasOneUse() || FV->hasOneUse())) { 5804 Constant *Elts[] = { 5805 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5806 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5807 }; 5808 const Type *FPTy = Elts[0]->getType(); 5809 const TargetData &TD = *TLI.getTargetData(); 5810 5811 // Create a ConstantArray of the two constants. 5812 Constant *CA = DAG.getContext()->getConstantArray( 5813 DAG.getContext()->getArrayType(FPTy, 2), Elts, 2); 5814 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5815 TD.getPrefTypeAlignment(FPTy)); 5816 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5817 5818 // Get the offsets to the 0 and 1 element of the array so that we can 5819 // select between them. 5820 SDValue Zero = DAG.getIntPtrConstant(0); 5821 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5822 SDValue One = DAG.getIntPtrConstant(EltSize); 5823 5824 SDValue Cond = DAG.getSetCC(DL, 5825 TLI.getSetCCResultType(N0.getValueType()), 5826 N0, N1, CC); 5827 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5828 Cond, One, Zero); 5829 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5830 CstOffset); 5831 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5832 PseudoSourceValue::getConstantPool(), 0, false, 5833 Alignment); 5834 5835 } 5836 } 5837 5838 // Check to see if we can perform the "gzip trick", transforming 5839 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5840 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5841 N0.getValueType().isInteger() && 5842 N2.getValueType().isInteger() && 5843 (N1C->isNullValue() || // (a < 0) ? b : 0 5844 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5845 MVT XType = N0.getValueType(); 5846 MVT AType = N2.getValueType(); 5847 if (XType.bitsGE(AType)) { 5848 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5849 // single-bit constant. 5850 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5851 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5852 ShCtV = XType.getSizeInBits()-ShCtV-1; 5853 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5854 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5855 XType, N0, ShCt); 5856 AddToWorkList(Shift.getNode()); 5857 5858 if (XType.bitsGT(AType)) { 5859 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5860 AddToWorkList(Shift.getNode()); 5861 } 5862 5863 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5864 } 5865 5866 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5867 XType, N0, 5868 DAG.getConstant(XType.getSizeInBits()-1, 5869 getShiftAmountTy())); 5870 AddToWorkList(Shift.getNode()); 5871 5872 if (XType.bitsGT(AType)) { 5873 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5874 AddToWorkList(Shift.getNode()); 5875 } 5876 5877 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5878 } 5879 } 5880 5881 // fold select C, 16, 0 -> shl C, 4 5882 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5883 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5884 5885 // If the caller doesn't want us to simplify this into a zext of a compare, 5886 // don't do it. 5887 if (NotExtCompare && N2C->getAPIntValue() == 1) 5888 return SDValue(); 5889 5890 // Get a SetCC of the condition 5891 // FIXME: Should probably make sure that setcc is legal if we ever have a 5892 // target where it isn't. 5893 SDValue Temp, SCC; 5894 // cast from setcc result type to select result type 5895 if (LegalTypes) { 5896 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5897 N0, N1, CC); 5898 if (N2.getValueType().bitsLT(SCC.getValueType())) 5899 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5900 else 5901 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5902 N2.getValueType(), SCC); 5903 } else { 5904 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5905 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5906 N2.getValueType(), SCC); 5907 } 5908 5909 AddToWorkList(SCC.getNode()); 5910 AddToWorkList(Temp.getNode()); 5911 5912 if (N2C->getAPIntValue() == 1) 5913 return Temp; 5914 5915 // shl setcc result by log2 n2c 5916 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5917 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5918 getShiftAmountTy())); 5919 } 5920 5921 // Check to see if this is the equivalent of setcc 5922 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5923 // otherwise, go ahead with the folds. 5924 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5925 MVT XType = N0.getValueType(); 5926 if (!LegalOperations || 5927 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5928 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5929 if (Res.getValueType() != VT) 5930 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5931 return Res; 5932 } 5933 5934 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5935 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5936 (!LegalOperations || 5937 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5938 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5939 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5940 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5941 getShiftAmountTy())); 5942 } 5943 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5944 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5945 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5946 XType, DAG.getConstant(0, XType), N0); 5947 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5948 return DAG.getNode(ISD::SRL, DL, XType, 5949 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5950 DAG.getConstant(XType.getSizeInBits()-1, 5951 getShiftAmountTy())); 5952 } 5953 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5954 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5955 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5956 DAG.getConstant(XType.getSizeInBits()-1, 5957 getShiftAmountTy())); 5958 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5959 } 5960 } 5961 5962 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5963 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5964 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5965 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5966 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5967 MVT XType = N0.getValueType(); 5968 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5969 DAG.getConstant(XType.getSizeInBits()-1, 5970 getShiftAmountTy())); 5971 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5972 N0, Shift); 5973 AddToWorkList(Shift.getNode()); 5974 AddToWorkList(Add.getNode()); 5975 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5976 } 5977 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5978 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5979 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5980 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5981 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5982 MVT XType = N0.getValueType(); 5983 if (SubC->isNullValue() && XType.isInteger()) { 5984 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5985 N0, 5986 DAG.getConstant(XType.getSizeInBits()-1, 5987 getShiftAmountTy())); 5988 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 5989 XType, N0, Shift); 5990 AddToWorkList(Shift.getNode()); 5991 AddToWorkList(Add.getNode()); 5992 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5993 } 5994 } 5995 } 5996 5997 return SDValue(); 5998} 5999 6000/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6001SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 6002 SDValue N1, ISD::CondCode Cond, 6003 DebugLoc DL, bool foldBooleans) { 6004 TargetLowering::DAGCombinerInfo 6005 DagCombineInfo(DAG, Level == Unrestricted, false, this); 6006 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6007} 6008 6009/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6010/// return a DAG expression to select that will generate the same value by 6011/// multiplying by a magic number. See: 6012/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6013SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6014 std::vector<SDNode*> Built; 6015 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6016 6017 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6018 ii != ee; ++ii) 6019 AddToWorkList(*ii); 6020 return S; 6021} 6022 6023/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6024/// return a DAG expression to select that will generate the same value by 6025/// multiplying by a magic number. See: 6026/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6027SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6028 std::vector<SDNode*> Built; 6029 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6030 6031 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6032 ii != ee; ++ii) 6033 AddToWorkList(*ii); 6034 return S; 6035} 6036 6037/// FindBaseOffset - Return true if base is known not to alias with anything 6038/// but itself. Provides base object and offset as results. 6039static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 6040 // Assume it is a primitive operation. 6041 Base = Ptr; Offset = 0; 6042 6043 // If it's an adding a simple constant then integrate the offset. 6044 if (Base.getOpcode() == ISD::ADD) { 6045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6046 Base = Base.getOperand(0); 6047 Offset += C->getZExtValue(); 6048 } 6049 } 6050 6051 // If it's any of the following then it can't alias with anything but itself. 6052 return isa<FrameIndexSDNode>(Base) || 6053 isa<ConstantPoolSDNode>(Base) || 6054 isa<GlobalAddressSDNode>(Base); 6055} 6056 6057/// isAlias - Return true if there is any possibility that the two addresses 6058/// overlap. 6059bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6060 const Value *SrcValue1, int SrcValueOffset1, 6061 SDValue Ptr2, int64_t Size2, 6062 const Value *SrcValue2, int SrcValueOffset2) const { 6063 // If they are the same then they must be aliases. 6064 if (Ptr1 == Ptr2) return true; 6065 6066 // Gather base node and offset information. 6067 SDValue Base1, Base2; 6068 int64_t Offset1, Offset2; 6069 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 6070 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 6071 6072 // If they have a same base address then... 6073 if (Base1 == Base2) 6074 // Check to see if the addresses overlap. 6075 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6076 6077 // If we know both bases then they can't alias. 6078 if (KnownBase1 && KnownBase2) return false; 6079 6080 if (CombinerGlobalAA) { 6081 // Use alias analysis information. 6082 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6083 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6084 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6085 AliasAnalysis::AliasResult AAResult = 6086 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6087 if (AAResult == AliasAnalysis::NoAlias) 6088 return false; 6089 } 6090 6091 // Otherwise we have to assume they alias. 6092 return true; 6093} 6094 6095/// FindAliasInfo - Extracts the relevant alias information from the memory 6096/// node. Returns true if the operand was a load. 6097bool DAGCombiner::FindAliasInfo(SDNode *N, 6098 SDValue &Ptr, int64_t &Size, 6099 const Value *&SrcValue, int &SrcValueOffset) const { 6100 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6101 Ptr = LD->getBasePtr(); 6102 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6103 SrcValue = LD->getSrcValue(); 6104 SrcValueOffset = LD->getSrcValueOffset(); 6105 return true; 6106 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6107 Ptr = ST->getBasePtr(); 6108 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6109 SrcValue = ST->getSrcValue(); 6110 SrcValueOffset = ST->getSrcValueOffset(); 6111 } else { 6112 llvm_unreachable("FindAliasInfo expected a memory operand"); 6113 } 6114 6115 return false; 6116} 6117 6118/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6119/// looking for aliasing nodes and adding them to the Aliases vector. 6120void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6121 SmallVector<SDValue, 8> &Aliases) { 6122 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6123 std::set<SDNode *> Visited; // Visited node set. 6124 6125 // Get alias information for node. 6126 SDValue Ptr; 6127 int64_t Size = 0; 6128 const Value *SrcValue = 0; 6129 int SrcValueOffset = 0; 6130 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6131 6132 // Starting off. 6133 Chains.push_back(OriginalChain); 6134 6135 // Look at each chain and determine if it is an alias. If so, add it to the 6136 // aliases list. If not, then continue up the chain looking for the next 6137 // candidate. 6138 while (!Chains.empty()) { 6139 SDValue Chain = Chains.back(); 6140 Chains.pop_back(); 6141 6142 // Don't bother if we've been before. 6143 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6144 Visited.insert(Chain.getNode()); 6145 6146 switch (Chain.getOpcode()) { 6147 case ISD::EntryToken: 6148 // Entry token is ideal chain operand, but handled in FindBetterChain. 6149 break; 6150 6151 case ISD::LOAD: 6152 case ISD::STORE: { 6153 // Get alias information for Chain. 6154 SDValue OpPtr; 6155 int64_t OpSize = 0; 6156 const Value *OpSrcValue = 0; 6157 int OpSrcValueOffset = 0; 6158 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6159 OpSrcValue, OpSrcValueOffset); 6160 6161 // If chain is alias then stop here. 6162 if (!(IsLoad && IsOpLoad) && 6163 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6164 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6165 Aliases.push_back(Chain); 6166 } else { 6167 // Look further up the chain. 6168 Chains.push_back(Chain.getOperand(0)); 6169 // Clean up old chain. 6170 AddToWorkList(Chain.getNode()); 6171 } 6172 break; 6173 } 6174 6175 case ISD::TokenFactor: 6176 // We have to check each of the operands of the token factor, so we queue 6177 // then up. Adding the operands to the queue (stack) in reverse order 6178 // maintains the original order and increases the likelihood that getNode 6179 // will find a matching token factor (CSE.) 6180 for (unsigned n = Chain.getNumOperands(); n;) 6181 Chains.push_back(Chain.getOperand(--n)); 6182 // Eliminate the token factor if we can. 6183 AddToWorkList(Chain.getNode()); 6184 break; 6185 6186 default: 6187 // For all other instructions we will just have to take what we can get. 6188 Aliases.push_back(Chain); 6189 break; 6190 } 6191 } 6192} 6193 6194/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6195/// for a better chain (aliasing node.) 6196SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6197 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6198 6199 // Accumulate all the aliases to this node. 6200 GatherAllAliases(N, OldChain, Aliases); 6201 6202 if (Aliases.size() == 0) { 6203 // If no operands then chain to entry token. 6204 return DAG.getEntryNode(); 6205 } else if (Aliases.size() == 1) { 6206 // If a single operand then chain to it. We don't need to revisit it. 6207 return Aliases[0]; 6208 } 6209 6210 // Construct a custom tailored token factor. 6211 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6212 &Aliases[0], Aliases.size()); 6213 6214 // Make sure the old chain gets cleaned up. 6215 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6216 6217 return NewChain; 6218} 6219 6220// SelectionDAG::Combine - This is the entry point for the file. 6221// 6222void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6223 CodeGenOpt::Level OptLevel) { 6224 /// run - This is the main entry point to this class. 6225 /// 6226 DAGCombiner(*this, AA, OptLevel).Run(Level); 6227} 6228