DAGCombiner.cpp revision ad25d4e2df3fe01541d62ab0fd22c7de22ce3a42
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: Should add a corresponding version of fold AND with 20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 21// we don't have yet. 22// 23// FIXME: select C, pow2, pow2 -> something smart 24// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 25// FIXME: Dead stores -> nuke 26// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 27// FIXME: mul (x, const) -> shifts + adds 28// FIXME: undef values 29// FIXME: make truncate see through SIGN_EXTEND and AND 30// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 31// FIXME: verify that getNode can't return extends with an operand whose type 32// is >= to that of the extend. 33// FIXME: divide by zero is currently left unfolded. do we want to turn this 34// into an undef? 35// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 36// FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use 37// 38//===----------------------------------------------------------------------===// 39 40#define DEBUG_TYPE "dagcombine" 41#include "llvm/ADT/Statistic.h" 42#include "llvm/CodeGen/SelectionDAG.h" 43#include "llvm/Support/Debug.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Target/TargetLowering.h" 46#include <algorithm> 47#include <cmath> 48using namespace llvm; 49 50namespace { 51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 52 53 class DAGCombiner { 54 SelectionDAG &DAG; 55 TargetLowering &TLI; 56 bool AfterLegalize; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 /// AddUsersToWorkList - When an instruction is simplified, add all users of 62 /// the instruction to the work lists because they might get more simplified 63 /// now. 64 /// 65 void AddUsersToWorkList(SDNode *N) { 66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 67 UI != UE; ++UI) 68 WorkList.push_back(*UI); 69 } 70 71 /// removeFromWorkList - remove all instances of N from the worklist. 72 void removeFromWorkList(SDNode *N) { 73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 74 WorkList.end()); 75 } 76 77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 78 ++NodesCombined; 79 DEBUG(std::cerr << "\nReplacing "; N->dump(); 80 std::cerr << "\nWith: "; To[0].Val->dump(); 81 std::cerr << " and " << To.size()-1 << " other values\n"); 82 std::vector<SDNode*> NowDead; 83 DAG.ReplaceAllUsesWith(N, To, &NowDead); 84 85 // Push the new nodes and any users onto the worklist 86 for (unsigned i = 0, e = To.size(); i != e; ++i) { 87 WorkList.push_back(To[i].Val); 88 AddUsersToWorkList(To[i].Val); 89 } 90 91 // Nodes can end up on the worklist more than once. Make sure we do 92 // not process a node that has been replaced. 93 removeFromWorkList(N); 94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 95 removeFromWorkList(NowDead[i]); 96 97 // Finally, since the node is now dead, remove it from the graph. 98 DAG.DeleteNode(N); 99 return SDOperand(N, 0); 100 } 101 102 SDOperand CombineTo(SDNode *N, SDOperand Res) { 103 std::vector<SDOperand> To; 104 To.push_back(Res); 105 return CombineTo(N, To); 106 } 107 108 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 109 std::vector<SDOperand> To; 110 To.push_back(Res0); 111 To.push_back(Res1); 112 return CombineTo(N, To); 113 } 114 115 /// visit - call the node-specific routine that knows how to fold each 116 /// particular type of node. 117 SDOperand visit(SDNode *N); 118 119 // Visitation implementation - Implement dag node combining for different 120 // node types. The semantics are as follows: 121 // Return Value: 122 // SDOperand.Val == 0 - No change was made 123 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 124 // otherwise - N should be replaced by the returned Operand. 125 // 126 SDOperand visitTokenFactor(SDNode *N); 127 SDOperand visitADD(SDNode *N); 128 SDOperand visitSUB(SDNode *N); 129 SDOperand visitMUL(SDNode *N); 130 SDOperand visitSDIV(SDNode *N); 131 SDOperand visitUDIV(SDNode *N); 132 SDOperand visitSREM(SDNode *N); 133 SDOperand visitUREM(SDNode *N); 134 SDOperand visitMULHU(SDNode *N); 135 SDOperand visitMULHS(SDNode *N); 136 SDOperand visitAND(SDNode *N); 137 SDOperand visitOR(SDNode *N); 138 SDOperand visitXOR(SDNode *N); 139 SDOperand visitSHL(SDNode *N); 140 SDOperand visitSRA(SDNode *N); 141 SDOperand visitSRL(SDNode *N); 142 SDOperand visitCTLZ(SDNode *N); 143 SDOperand visitCTTZ(SDNode *N); 144 SDOperand visitCTPOP(SDNode *N); 145 SDOperand visitSELECT(SDNode *N); 146 SDOperand visitSELECT_CC(SDNode *N); 147 SDOperand visitSETCC(SDNode *N); 148 SDOperand visitADD_PARTS(SDNode *N); 149 SDOperand visitSUB_PARTS(SDNode *N); 150 SDOperand visitSIGN_EXTEND(SDNode *N); 151 SDOperand visitZERO_EXTEND(SDNode *N); 152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 153 SDOperand visitTRUNCATE(SDNode *N); 154 155 SDOperand visitFADD(SDNode *N); 156 SDOperand visitFSUB(SDNode *N); 157 SDOperand visitFMUL(SDNode *N); 158 SDOperand visitFDIV(SDNode *N); 159 SDOperand visitFREM(SDNode *N); 160 SDOperand visitSINT_TO_FP(SDNode *N); 161 SDOperand visitUINT_TO_FP(SDNode *N); 162 SDOperand visitFP_TO_SINT(SDNode *N); 163 SDOperand visitFP_TO_UINT(SDNode *N); 164 SDOperand visitFP_ROUND(SDNode *N); 165 SDOperand visitFP_ROUND_INREG(SDNode *N); 166 SDOperand visitFP_EXTEND(SDNode *N); 167 SDOperand visitFNEG(SDNode *N); 168 SDOperand visitFABS(SDNode *N); 169 SDOperand visitBRCOND(SDNode *N); 170 SDOperand visitBRCONDTWOWAY(SDNode *N); 171 SDOperand visitBR_CC(SDNode *N); 172 SDOperand visitBRTWOWAY_CC(SDNode *N); 173 174 SDOperand visitLOAD(SDNode *N); 175 SDOperand visitSTORE(SDNode *N); 176 177 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 178 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 179 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 180 SDOperand N3, ISD::CondCode CC); 181 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 182 ISD::CondCode Cond, bool foldBooleans = true); 183 184 SDOperand BuildSDIV(SDNode *N); 185 SDOperand BuildUDIV(SDNode *N); 186public: 187 DAGCombiner(SelectionDAG &D) 188 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 189 190 /// Run - runs the dag combiner on all nodes in the work list 191 void Run(bool RunningAfterLegalize); 192 }; 193} 194 195struct ms { 196 int64_t m; // magic number 197 int64_t s; // shift amount 198}; 199 200struct mu { 201 uint64_t m; // magic number 202 int64_t a; // add indicator 203 int64_t s; // shift amount 204}; 205 206/// magic - calculate the magic numbers required to codegen an integer sdiv as 207/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 208/// or -1. 209static ms magic32(int32_t d) { 210 int32_t p; 211 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 212 const uint32_t two31 = 0x80000000U; 213 struct ms mag; 214 215 ad = abs(d); 216 t = two31 + ((uint32_t)d >> 31); 217 anc = t - 1 - t%ad; // absolute value of nc 218 p = 31; // initialize p 219 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 220 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 221 q2 = two31/ad; // initialize q2 = 2p/abs(d) 222 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 223 do { 224 p = p + 1; 225 q1 = 2*q1; // update q1 = 2p/abs(nc) 226 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 227 if (r1 >= anc) { // must be unsigned comparison 228 q1 = q1 + 1; 229 r1 = r1 - anc; 230 } 231 q2 = 2*q2; // update q2 = 2p/abs(d) 232 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 233 if (r2 >= ad) { // must be unsigned comparison 234 q2 = q2 + 1; 235 r2 = r2 - ad; 236 } 237 delta = ad - r2; 238 } while (q1 < delta || (q1 == delta && r1 == 0)); 239 240 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 241 if (d < 0) mag.m = -mag.m; // resulting magic number 242 mag.s = p - 32; // resulting shift 243 return mag; 244} 245 246/// magicu - calculate the magic numbers required to codegen an integer udiv as 247/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 248static mu magicu32(uint32_t d) { 249 int32_t p; 250 uint32_t nc, delta, q1, r1, q2, r2; 251 struct mu magu; 252 magu.a = 0; // initialize "add" indicator 253 nc = - 1 - (-d)%d; 254 p = 31; // initialize p 255 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 256 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 257 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 258 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 259 do { 260 p = p + 1; 261 if (r1 >= nc - r1 ) { 262 q1 = 2*q1 + 1; // update q1 263 r1 = 2*r1 - nc; // update r1 264 } 265 else { 266 q1 = 2*q1; // update q1 267 r1 = 2*r1; // update r1 268 } 269 if (r2 + 1 >= d - r2) { 270 if (q2 >= 0x7FFFFFFF) magu.a = 1; 271 q2 = 2*q2 + 1; // update q2 272 r2 = 2*r2 + 1 - d; // update r2 273 } 274 else { 275 if (q2 >= 0x80000000) magu.a = 1; 276 q2 = 2*q2; // update q2 277 r2 = 2*r2 + 1; // update r2 278 } 279 delta = d - 1 - r2; 280 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 281 magu.m = q2 + 1; // resulting magic number 282 magu.s = p - 32; // resulting shift 283 return magu; 284} 285 286/// magic - calculate the magic numbers required to codegen an integer sdiv as 287/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 288/// or -1. 289static ms magic64(int64_t d) { 290 int64_t p; 291 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 292 const uint64_t two63 = 9223372036854775808ULL; // 2^63 293 struct ms mag; 294 295 ad = d >= 0 ? d : -d; 296 t = two63 + ((uint64_t)d >> 63); 297 anc = t - 1 - t%ad; // absolute value of nc 298 p = 63; // initialize p 299 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 300 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 301 q2 = two63/ad; // initialize q2 = 2p/abs(d) 302 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 303 do { 304 p = p + 1; 305 q1 = 2*q1; // update q1 = 2p/abs(nc) 306 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 307 if (r1 >= anc) { // must be unsigned comparison 308 q1 = q1 + 1; 309 r1 = r1 - anc; 310 } 311 q2 = 2*q2; // update q2 = 2p/abs(d) 312 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 313 if (r2 >= ad) { // must be unsigned comparison 314 q2 = q2 + 1; 315 r2 = r2 - ad; 316 } 317 delta = ad - r2; 318 } while (q1 < delta || (q1 == delta && r1 == 0)); 319 320 mag.m = q2 + 1; 321 if (d < 0) mag.m = -mag.m; // resulting magic number 322 mag.s = p - 64; // resulting shift 323 return mag; 324} 325 326/// magicu - calculate the magic numbers required to codegen an integer udiv as 327/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 328static mu magicu64(uint64_t d) 329{ 330 int64_t p; 331 uint64_t nc, delta, q1, r1, q2, r2; 332 struct mu magu; 333 magu.a = 0; // initialize "add" indicator 334 nc = - 1 - (-d)%d; 335 p = 63; // initialize p 336 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 337 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 338 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 339 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 340 do { 341 p = p + 1; 342 if (r1 >= nc - r1 ) { 343 q1 = 2*q1 + 1; // update q1 344 r1 = 2*r1 - nc; // update r1 345 } 346 else { 347 q1 = 2*q1; // update q1 348 r1 = 2*r1; // update r1 349 } 350 if (r2 + 1 >= d - r2) { 351 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 352 q2 = 2*q2 + 1; // update q2 353 r2 = 2*r2 + 1 - d; // update r2 354 } 355 else { 356 if (q2 >= 0x8000000000000000ull) magu.a = 1; 357 q2 = 2*q2; // update q2 358 r2 = 2*r2 + 1; // update r2 359 } 360 delta = d - 1 - r2; 361 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 362 magu.m = q2 + 1; // resulting magic number 363 magu.s = p - 64; // resulting shift 364 return magu; 365} 366 367/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use 368/// this predicate to simplify operations downstream. Op and Mask are known to 369/// be the same type. 370static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 371 const TargetLowering &TLI) { 372 unsigned SrcBits; 373 if (Mask == 0) return true; 374 375 // If we know the result of a setcc has the top bits zero, use this info. 376 switch (Op.getOpcode()) { 377 case ISD::Constant: 378 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 379 case ISD::SETCC: 380 return ((Mask & 1) == 0) && 381 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 382 case ISD::ZEXTLOAD: 383 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 384 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 385 case ISD::ZERO_EXTEND: 386 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 387 return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)),TLI); 388 case ISD::AssertZext: 389 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 390 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 391 case ISD::AND: 392 // If either of the operands has zero bits, the result will too. 393 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) || 394 MaskedValueIsZero(Op.getOperand(0), Mask, TLI)) 395 return true; 396 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 397 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 398 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 399 return false; 400 case ISD::OR: 401 case ISD::XOR: 402 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 403 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 404 case ISD::SELECT: 405 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 406 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 407 case ISD::SELECT_CC: 408 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 409 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 410 case ISD::SRL: 411 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 412 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 413 uint64_t NewVal = Mask << ShAmt->getValue(); 414 SrcBits = MVT::getSizeInBits(Op.getValueType()); 415 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 416 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 417 } 418 return false; 419 case ISD::SHL: 420 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 421 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 422 uint64_t NewVal = Mask >> ShAmt->getValue(); 423 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 424 } 425 return false; 426 case ISD::ADD: 427 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits. 428 if ((Mask&(Mask+1)) == 0) { // All low bits 429 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 430 MaskedValueIsZero(Op.getOperand(1), Mask, TLI)) 431 return true; 432 } 433 break; 434 case ISD::SUB: 435 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 436 // We know that the top bits of C-X are clear if X contains less bits 437 // than C (i.e. no wrap-around can happen). For example, 20-X is 438 // positive if we can prove that X is >= 0 and < 16. 439 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0)); 440 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear 441 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 442 uint64_t MaskV = (1ULL << (63-NLZ))-1; 443 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) { 444 // High bits are clear this value is known to be >= C. 445 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 446 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0) 447 return true; 448 } 449 } 450 } 451 break; 452 case ISD::CTTZ: 453 case ISD::CTLZ: 454 case ISD::CTPOP: 455 // Bit counting instructions can not set the high bits of the result 456 // register. The max number of bits sets depends on the input. 457 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 458 default: break; 459 } 460 return false; 461} 462 463// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 464// that selects between the values 1 and 0, making it equivalent to a setcc. 465// Also, set the incoming LHS, RHS, and CC references to the appropriate 466// nodes based on the type of node we are checking. This simplifies life a 467// bit for the callers. 468static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 469 SDOperand &CC) { 470 if (N.getOpcode() == ISD::SETCC) { 471 LHS = N.getOperand(0); 472 RHS = N.getOperand(1); 473 CC = N.getOperand(2); 474 return true; 475 } 476 if (N.getOpcode() == ISD::SELECT_CC && 477 N.getOperand(2).getOpcode() == ISD::Constant && 478 N.getOperand(3).getOpcode() == ISD::Constant && 479 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 480 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 481 LHS = N.getOperand(0); 482 RHS = N.getOperand(1); 483 CC = N.getOperand(4); 484 return true; 485 } 486 return false; 487} 488 489// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 490// one use. If this is true, it allows the users to invert the operation for 491// free when it is profitable to do so. 492static bool isOneUseSetCC(SDOperand N) { 493 SDOperand N0, N1, N2; 494 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 495 return true; 496 return false; 497} 498 499// FIXME: This should probably go in the ISD class rather than being duplicated 500// in several files. 501static bool isCommutativeBinOp(unsigned Opcode) { 502 switch (Opcode) { 503 case ISD::ADD: 504 case ISD::MUL: 505 case ISD::AND: 506 case ISD::OR: 507 case ISD::XOR: return true; 508 default: return false; // FIXME: Need commutative info for user ops! 509 } 510} 511 512void DAGCombiner::Run(bool RunningAfterLegalize) { 513 // set the instance variable, so that the various visit routines may use it. 514 AfterLegalize = RunningAfterLegalize; 515 516 // Add all the dag nodes to the worklist. 517 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 518 E = DAG.allnodes_end(); I != E; ++I) 519 WorkList.push_back(I); 520 521 // Create a dummy node (which is not added to allnodes), that adds a reference 522 // to the root node, preventing it from being deleted, and tracking any 523 // changes of the root. 524 HandleSDNode Dummy(DAG.getRoot()); 525 526 // while the worklist isn't empty, inspect the node on the end of it and 527 // try and combine it. 528 while (!WorkList.empty()) { 529 SDNode *N = WorkList.back(); 530 WorkList.pop_back(); 531 532 // If N has no uses, it is dead. Make sure to revisit all N's operands once 533 // N is deleted from the DAG, since they too may now be dead or may have a 534 // reduced number of uses, allowing other xforms. 535 if (N->use_empty() && N != &Dummy) { 536 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 537 WorkList.push_back(N->getOperand(i).Val); 538 539 removeFromWorkList(N); 540 DAG.DeleteNode(N); 541 continue; 542 } 543 544 SDOperand RV = visit(N); 545 if (RV.Val) { 546 ++NodesCombined; 547 // If we get back the same node we passed in, rather than a new node or 548 // zero, we know that the node must have defined multiple values and 549 // CombineTo was used. Since CombineTo takes care of the worklist 550 // mechanics for us, we have no work to do in this case. 551 if (RV.Val != N) { 552 DEBUG(std::cerr << "\nReplacing "; N->dump(); 553 std::cerr << "\nWith: "; RV.Val->dump(); 554 std::cerr << '\n'); 555 std::vector<SDNode*> NowDead; 556 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 557 558 // Push the new node and any users onto the worklist 559 WorkList.push_back(RV.Val); 560 AddUsersToWorkList(RV.Val); 561 562 // Nodes can end up on the worklist more than once. Make sure we do 563 // not process a node that has been replaced. 564 removeFromWorkList(N); 565 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 566 removeFromWorkList(NowDead[i]); 567 568 // Finally, since the node is now dead, remove it from the graph. 569 DAG.DeleteNode(N); 570 } 571 } 572 } 573 574 // If the root changed (e.g. it was a dead load, update the root). 575 DAG.setRoot(Dummy.getValue()); 576} 577 578SDOperand DAGCombiner::visit(SDNode *N) { 579 switch(N->getOpcode()) { 580 default: break; 581 case ISD::TokenFactor: return visitTokenFactor(N); 582 case ISD::ADD: return visitADD(N); 583 case ISD::SUB: return visitSUB(N); 584 case ISD::MUL: return visitMUL(N); 585 case ISD::SDIV: return visitSDIV(N); 586 case ISD::UDIV: return visitUDIV(N); 587 case ISD::SREM: return visitSREM(N); 588 case ISD::UREM: return visitUREM(N); 589 case ISD::MULHU: return visitMULHU(N); 590 case ISD::MULHS: return visitMULHS(N); 591 case ISD::AND: return visitAND(N); 592 case ISD::OR: return visitOR(N); 593 case ISD::XOR: return visitXOR(N); 594 case ISD::SHL: return visitSHL(N); 595 case ISD::SRA: return visitSRA(N); 596 case ISD::SRL: return visitSRL(N); 597 case ISD::CTLZ: return visitCTLZ(N); 598 case ISD::CTTZ: return visitCTTZ(N); 599 case ISD::CTPOP: return visitCTPOP(N); 600 case ISD::SELECT: return visitSELECT(N); 601 case ISD::SELECT_CC: return visitSELECT_CC(N); 602 case ISD::SETCC: return visitSETCC(N); 603 case ISD::ADD_PARTS: return visitADD_PARTS(N); 604 case ISD::SUB_PARTS: return visitSUB_PARTS(N); 605 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 606 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 607 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 608 case ISD::TRUNCATE: return visitTRUNCATE(N); 609 case ISD::FADD: return visitFADD(N); 610 case ISD::FSUB: return visitFSUB(N); 611 case ISD::FMUL: return visitFMUL(N); 612 case ISD::FDIV: return visitFDIV(N); 613 case ISD::FREM: return visitFREM(N); 614 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 615 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 616 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 617 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 618 case ISD::FP_ROUND: return visitFP_ROUND(N); 619 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 620 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 621 case ISD::FNEG: return visitFNEG(N); 622 case ISD::FABS: return visitFABS(N); 623 case ISD::BRCOND: return visitBRCOND(N); 624 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 625 case ISD::BR_CC: return visitBR_CC(N); 626 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 627 case ISD::LOAD: return visitLOAD(N); 628 case ISD::STORE: return visitSTORE(N); 629 } 630 return SDOperand(); 631} 632 633SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 634 std::vector<SDOperand> Ops; 635 bool Changed = false; 636 637 // If the token factor has two operands and one is the entry token, replace 638 // the token factor with the other operand. 639 if (N->getNumOperands() == 2) { 640 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 641 return N->getOperand(1); 642 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 643 return N->getOperand(0); 644 } 645 646 // fold (tokenfactor (tokenfactor)) -> tokenfactor 647 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 648 SDOperand Op = N->getOperand(i); 649 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 650 Changed = true; 651 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 652 Ops.push_back(Op.getOperand(j)); 653 } else { 654 Ops.push_back(Op); 655 } 656 } 657 if (Changed) 658 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 659 return SDOperand(); 660} 661 662SDOperand DAGCombiner::visitADD(SDNode *N) { 663 SDOperand N0 = N->getOperand(0); 664 SDOperand N1 = N->getOperand(1); 665 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 666 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 667 MVT::ValueType VT = N0.getValueType(); 668 669 // fold (add c1, c2) -> c1+c2 670 if (N0C && N1C) 671 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); 672 // canonicalize constant to RHS 673 if (N0C && !N1C) 674 return DAG.getNode(ISD::ADD, VT, N1, N0); 675 // fold (add x, 0) -> x 676 if (N1C && N1C->isNullValue()) 677 return N0; 678 // fold (add (add x, c1), c2) -> (add x, c1+c2) 679 if (N1C && N0.getOpcode() == ISD::ADD) { 680 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 681 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 682 if (N00C) 683 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1), 684 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT)); 685 if (N01C) 686 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0), 687 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT)); 688 } 689 // fold ((0-A) + B) -> B-A 690 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 691 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 692 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 693 // fold (A + (0-B)) -> A-B 694 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 695 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 696 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 697 // fold (A+(B-A)) -> B 698 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 699 return N1.getOperand(0); 700 return SDOperand(); 701} 702 703SDOperand DAGCombiner::visitSUB(SDNode *N) { 704 SDOperand N0 = N->getOperand(0); 705 SDOperand N1 = N->getOperand(1); 706 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 707 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 708 709 // fold (sub x, x) -> 0 710 if (N0 == N1) 711 return DAG.getConstant(0, N->getValueType(0)); 712 713 // fold (sub c1, c2) -> c1-c2 714 if (N0C && N1C) 715 return DAG.getConstant(N0C->getValue() - N1C->getValue(), 716 N->getValueType(0)); 717 // fold (sub x, c) -> (add x, -c) 718 if (N1C) 719 return DAG.getNode(ISD::ADD, N0.getValueType(), N0, 720 DAG.getConstant(-N1C->getValue(), N0.getValueType())); 721 722 // fold (A+B)-A -> B 723 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 724 return N0.getOperand(1); 725 // fold (A+B)-B -> A 726 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 727 return N0.getOperand(0); 728 return SDOperand(); 729} 730 731SDOperand DAGCombiner::visitMUL(SDNode *N) { 732 SDOperand N0 = N->getOperand(0); 733 SDOperand N1 = N->getOperand(1); 734 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 735 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 736 MVT::ValueType VT = N0.getValueType(); 737 738 // fold (mul c1, c2) -> c1*c2 739 if (N0C && N1C) 740 return DAG.getConstant(N0C->getValue() * N1C->getValue(), VT); 741 // canonicalize constant to RHS 742 if (N0C && !N1C) 743 return DAG.getNode(ISD::MUL, VT, N1, N0); 744 // fold (mul x, 0) -> 0 745 if (N1C && N1C->isNullValue()) 746 return N1; 747 // fold (mul x, -1) -> 0-x 748 if (N1C && N1C->isAllOnesValue()) 749 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 750 // fold (mul x, (1 << c)) -> x << c 751 if (N1C && isPowerOf2_64(N1C->getValue())) 752 return DAG.getNode(ISD::SHL, VT, N0, 753 DAG.getConstant(Log2_64(N1C->getValue()), 754 TLI.getShiftAmountTy())); 755 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 756 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 757 // FIXME: If the input is something that is easily negated (e.g. a 758 // single-use add), we should put the negate there. 759 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 760 DAG.getNode(ISD::SHL, VT, N0, 761 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 762 TLI.getShiftAmountTy()))); 763 } 764 765 766 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2) 767 if (N1C && N0.getOpcode() == ISD::MUL) { 768 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 769 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 770 if (N00C) 771 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1), 772 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT)); 773 if (N01C) 774 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), 775 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT)); 776 } 777 return SDOperand(); 778} 779 780SDOperand DAGCombiner::visitSDIV(SDNode *N) { 781 SDOperand N0 = N->getOperand(0); 782 SDOperand N1 = N->getOperand(1); 783 MVT::ValueType VT = N->getValueType(0); 784 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 785 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 786 787 // fold (sdiv c1, c2) -> c1/c2 788 if (N0C && N1C && !N1C->isNullValue()) 789 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(), 790 N->getValueType(0)); 791 // fold (sdiv X, 1) -> X 792 if (N1C && N1C->getSignExtended() == 1LL) 793 return N0; 794 // fold (sdiv X, -1) -> 0-X 795 if (N1C && N1C->isAllOnesValue()) 796 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 797 // If we know the sign bits of both operands are zero, strength reduce to a 798 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 799 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 800 if (MaskedValueIsZero(N1, SignBit, TLI) && 801 MaskedValueIsZero(N0, SignBit, TLI)) 802 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 803 // fold (sdiv X, pow2) -> (add (sra X, log(pow2)), (srl X, sizeof(X)-1)) 804 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 805 (isPowerOf2_64(N1C->getSignExtended()) || 806 isPowerOf2_64(-N1C->getSignExtended()))) { 807 // If dividing by powers of two is cheap, then don't perform the following 808 // fold. 809 if (TLI.isPow2DivCheap()) 810 return SDOperand(); 811 int64_t pow2 = N1C->getSignExtended(); 812 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 813 SDOperand SRL = DAG.getNode(ISD::SRL, VT, N0, 814 DAG.getConstant(MVT::getSizeInBits(VT)-1, 815 TLI.getShiftAmountTy())); 816 WorkList.push_back(SRL.Val); 817 SDOperand SGN = DAG.getNode(ISD::ADD, VT, N0, SRL); 818 WorkList.push_back(SGN.Val); 819 SDOperand SRA = DAG.getNode(ISD::SRA, VT, SGN, 820 DAG.getConstant(Log2_64(abs2), 821 TLI.getShiftAmountTy())); 822 // If we're dividing by a positive value, we're done. Otherwise, we must 823 // negate the result. 824 if (pow2 > 0) 825 return SRA; 826 WorkList.push_back(SRA.Val); 827 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 828 } 829 // if integer divide is expensive and we satisfy the requirements, emit an 830 // alternate sequence. 831 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 832 !TLI.isIntDivCheap()) { 833 SDOperand Op = BuildSDIV(N); 834 if (Op.Val) return Op; 835 } 836 return SDOperand(); 837} 838 839SDOperand DAGCombiner::visitUDIV(SDNode *N) { 840 SDOperand N0 = N->getOperand(0); 841 SDOperand N1 = N->getOperand(1); 842 MVT::ValueType VT = N->getValueType(0); 843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 845 846 // fold (udiv c1, c2) -> c1/c2 847 if (N0C && N1C && !N1C->isNullValue()) 848 return DAG.getConstant(N0C->getValue() / N1C->getValue(), 849 N->getValueType(0)); 850 // fold (udiv x, (1 << c)) -> x >>u c 851 if (N1C && isPowerOf2_64(N1C->getValue())) 852 return DAG.getNode(ISD::SRL, N->getValueType(0), N0, 853 DAG.getConstant(Log2_64(N1C->getValue()), 854 TLI.getShiftAmountTy())); 855 // fold (udiv x, c) -> alternate 856 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 857 SDOperand Op = BuildUDIV(N); 858 if (Op.Val) return Op; 859 } 860 861 return SDOperand(); 862} 863 864SDOperand DAGCombiner::visitSREM(SDNode *N) { 865 SDOperand N0 = N->getOperand(0); 866 SDOperand N1 = N->getOperand(1); 867 MVT::ValueType VT = N->getValueType(0); 868 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 869 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 870 871 // fold (srem c1, c2) -> c1%c2 872 if (N0C && N1C && !N1C->isNullValue()) 873 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(), 874 N->getValueType(0)); 875 // If we know the sign bits of both operands are zero, strength reduce to a 876 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 877 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 878 if (MaskedValueIsZero(N1, SignBit, TLI) && 879 MaskedValueIsZero(N0, SignBit, TLI)) 880 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1); 881 return SDOperand(); 882} 883 884SDOperand DAGCombiner::visitUREM(SDNode *N) { 885 SDOperand N0 = N->getOperand(0); 886 SDOperand N1 = N->getOperand(1); 887 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 888 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 889 890 // fold (urem c1, c2) -> c1%c2 891 if (N0C && N1C && !N1C->isNullValue()) 892 return DAG.getConstant(N0C->getValue() % N1C->getValue(), 893 N->getValueType(0)); 894 // fold (urem x, pow2) -> (and x, pow2-1) 895 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 896 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 897 DAG.getConstant(N1C->getValue()-1, N1.getValueType())); 898 return SDOperand(); 899} 900 901SDOperand DAGCombiner::visitMULHS(SDNode *N) { 902 SDOperand N0 = N->getOperand(0); 903 SDOperand N1 = N->getOperand(1); 904 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 905 906 // fold (mulhs x, 0) -> 0 907 if (N1C && N1C->isNullValue()) 908 return N1; 909 // fold (mulhs x, 1) -> (sra x, size(x)-1) 910 if (N1C && N1C->getValue() == 1) 911 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 912 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 913 TLI.getShiftAmountTy())); 914 return SDOperand(); 915} 916 917SDOperand DAGCombiner::visitMULHU(SDNode *N) { 918 SDOperand N0 = N->getOperand(0); 919 SDOperand N1 = N->getOperand(1); 920 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 921 922 // fold (mulhu x, 0) -> 0 923 if (N1C && N1C->isNullValue()) 924 return N1; 925 // fold (mulhu x, 1) -> 0 926 if (N1C && N1C->getValue() == 1) 927 return DAG.getConstant(0, N0.getValueType()); 928 return SDOperand(); 929} 930 931SDOperand DAGCombiner::visitAND(SDNode *N) { 932 SDOperand N0 = N->getOperand(0); 933 SDOperand N1 = N->getOperand(1); 934 SDOperand LL, LR, RL, RR, CC0, CC1; 935 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 936 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 937 MVT::ValueType VT = N1.getValueType(); 938 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 939 940 // fold (and c1, c2) -> c1&c2 941 if (N0C && N1C) 942 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT); 943 // canonicalize constant to RHS 944 if (N0C && !N1C) 945 return DAG.getNode(ISD::AND, VT, N1, N0); 946 // fold (and x, -1) -> x 947 if (N1C && N1C->isAllOnesValue()) 948 return N0; 949 // if (and x, c) is known to be zero, return 0 950 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 951 return DAG.getConstant(0, VT); 952 // fold (and x, c) -> x iff (x & ~c) == 0 953 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 954 TLI)) 955 return N0; 956 // fold (and (and x, c1), c2) -> (and x, c1^c2) 957 if (N1C && N0.getOpcode() == ISD::AND) { 958 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 959 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 960 if (N00C) 961 return DAG.getNode(ISD::AND, VT, N0.getOperand(1), 962 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT)); 963 if (N01C) 964 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 965 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT)); 966 } 967 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 968 if (N1C && N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { 969 unsigned ExtendBits = 970 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT()); 971 if (ExtendBits == 64 || ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)) 972 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1); 973 } 974 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 975 if (N1C && N0.getOpcode() == ISD::OR) 976 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 977 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 978 return N1; 979 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 980 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 981 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 982 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 983 984 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 985 MVT::isInteger(LL.getValueType())) { 986 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 987 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 988 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 989 WorkList.push_back(ORNode.Val); 990 return DAG.getSetCC(VT, ORNode, LR, Op1); 991 } 992 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 993 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 994 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 995 WorkList.push_back(ANDNode.Val); 996 return DAG.getSetCC(VT, ANDNode, LR, Op1); 997 } 998 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 999 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1000 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1001 WorkList.push_back(ORNode.Val); 1002 return DAG.getSetCC(VT, ORNode, LR, Op1); 1003 } 1004 } 1005 // canonicalize equivalent to ll == rl 1006 if (LL == RR && LR == RL) { 1007 Op1 = ISD::getSetCCSwappedOperands(Op1); 1008 std::swap(RL, RR); 1009 } 1010 if (LL == RL && LR == RR) { 1011 bool isInteger = MVT::isInteger(LL.getValueType()); 1012 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1013 if (Result != ISD::SETCC_INVALID) 1014 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1015 } 1016 } 1017 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 1018 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1019 N1.getOpcode() == ISD::ZERO_EXTEND && 1020 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1021 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1022 N0.getOperand(0), N1.getOperand(0)); 1023 WorkList.push_back(ANDNode.Val); 1024 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 1025 } 1026 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y)) 1027 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1028 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) && 1029 N0.getOperand(1) == N1.getOperand(1)) { 1030 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1031 N0.getOperand(0), N1.getOperand(0)); 1032 WorkList.push_back(ANDNode.Val); 1033 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 1034 } 1035 // fold (and (sra)) -> (and (srl)) when possible. 1036 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) { 1037 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1038 // If the RHS of the AND has zeros where the sign bits of the SRA will 1039 // land, turn the SRA into an SRL. 1040 if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) & 1041 (~0ULL>>(64-OpSizeInBits)), TLI)) { 1042 WorkList.push_back(N); 1043 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1044 N0.getOperand(1))); 1045 return SDOperand(); 1046 } 1047 } 1048 } 1049 // fold (zext_inreg (extload x)) -> (zextload x) 1050 if (N0.getOpcode() == ISD::EXTLOAD) { 1051 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1052 // If we zero all the possible extended bits, then we can turn this into 1053 // a zextload if we are running before legalize or the operation is legal. 1054 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) && 1055 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1056 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1057 N0.getOperand(1), N0.getOperand(2), 1058 EVT); 1059 WorkList.push_back(N); 1060 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1061 return SDOperand(); 1062 } 1063 } 1064 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1065 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1066 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1067 // If we zero all the possible extended bits, then we can turn this into 1068 // a zextload if we are running before legalize or the operation is legal. 1069 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) && 1070 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1071 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1072 N0.getOperand(1), N0.getOperand(2), 1073 EVT); 1074 WorkList.push_back(N); 1075 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1076 return SDOperand(); 1077 } 1078 } 1079 return SDOperand(); 1080} 1081 1082SDOperand DAGCombiner::visitOR(SDNode *N) { 1083 SDOperand N0 = N->getOperand(0); 1084 SDOperand N1 = N->getOperand(1); 1085 SDOperand LL, LR, RL, RR, CC0, CC1; 1086 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1087 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1088 MVT::ValueType VT = N1.getValueType(); 1089 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1090 1091 // fold (or c1, c2) -> c1|c2 1092 if (N0C && N1C) 1093 return DAG.getConstant(N0C->getValue() | N1C->getValue(), 1094 N->getValueType(0)); 1095 // canonicalize constant to RHS 1096 if (N0C && !N1C) 1097 return DAG.getNode(ISD::OR, VT, N1, N0); 1098 // fold (or x, 0) -> x 1099 if (N1C && N1C->isNullValue()) 1100 return N0; 1101 // fold (or x, -1) -> -1 1102 if (N1C && N1C->isAllOnesValue()) 1103 return N1; 1104 // fold (or x, c) -> c iff (x & ~c) == 0 1105 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 1106 TLI)) 1107 return N1; 1108 // fold (or (or x, c1), c2) -> (or x, c1|c2) 1109 if (N1C && N0.getOpcode() == ISD::OR) { 1110 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1111 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1112 if (N00C) 1113 return DAG.getNode(ISD::OR, VT, N0.getOperand(1), 1114 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT)); 1115 if (N01C) 1116 return DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1117 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT)); 1118 } else if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1119 isa<ConstantSDNode>(N0.getOperand(1))) { 1120 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1121 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1122 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1123 N1), 1124 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1125 } 1126 1127 1128 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1129 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1130 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1131 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1132 1133 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1134 MVT::isInteger(LL.getValueType())) { 1135 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1136 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1137 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1138 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1139 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1140 WorkList.push_back(ORNode.Val); 1141 return DAG.getSetCC(VT, ORNode, LR, Op1); 1142 } 1143 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1144 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1145 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1146 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1147 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1148 WorkList.push_back(ANDNode.Val); 1149 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1150 } 1151 } 1152 // canonicalize equivalent to ll == rl 1153 if (LL == RR && LR == RL) { 1154 Op1 = ISD::getSetCCSwappedOperands(Op1); 1155 std::swap(RL, RR); 1156 } 1157 if (LL == RL && LR == RR) { 1158 bool isInteger = MVT::isInteger(LL.getValueType()); 1159 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1160 if (Result != ISD::SETCC_INVALID) 1161 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1162 } 1163 } 1164 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 1165 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1166 N1.getOpcode() == ISD::ZERO_EXTEND && 1167 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1168 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1169 N0.getOperand(0), N1.getOperand(0)); 1170 WorkList.push_back(ORNode.Val); 1171 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 1172 } 1173 return SDOperand(); 1174} 1175 1176SDOperand DAGCombiner::visitXOR(SDNode *N) { 1177 SDOperand N0 = N->getOperand(0); 1178 SDOperand N1 = N->getOperand(1); 1179 SDOperand LHS, RHS, CC; 1180 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1181 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1182 MVT::ValueType VT = N0.getValueType(); 1183 1184 // fold (xor c1, c2) -> c1^c2 1185 if (N0C && N1C) 1186 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT); 1187 // canonicalize constant to RHS 1188 if (N0C && !N1C) 1189 return DAG.getNode(ISD::XOR, VT, N1, N0); 1190 // fold (xor x, 0) -> x 1191 if (N1C && N1C->isNullValue()) 1192 return N0; 1193 // fold !(x cc y) -> (x !cc y) 1194 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1195 bool isInt = MVT::isInteger(LHS.getValueType()); 1196 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1197 isInt); 1198 if (N0.getOpcode() == ISD::SETCC) 1199 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1200 if (N0.getOpcode() == ISD::SELECT_CC) 1201 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1202 assert(0 && "Unhandled SetCC Equivalent!"); 1203 abort(); 1204 } 1205 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1206 if (N1C && N1C->getValue() == 1 && 1207 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1208 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1209 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1210 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1211 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1212 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1213 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1214 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1215 } 1216 } 1217 // fold !(x or y) -> (!x and !y) iff x or y are constants 1218 if (N1C && N1C->isAllOnesValue() && 1219 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1220 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1221 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1222 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1223 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1224 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1225 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1226 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1227 } 1228 } 1229 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1230 if (N1C && N0.getOpcode() == ISD::XOR) { 1231 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1232 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1233 if (N00C) 1234 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1235 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1236 if (N01C) 1237 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1238 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1239 } 1240 // fold (xor x, x) -> 0 1241 if (N0 == N1) 1242 return DAG.getConstant(0, VT); 1243 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1244 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1245 N1.getOpcode() == ISD::ZERO_EXTEND && 1246 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1247 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1248 N0.getOperand(0), N1.getOperand(0)); 1249 WorkList.push_back(XORNode.Val); 1250 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1251 } 1252 return SDOperand(); 1253} 1254 1255SDOperand DAGCombiner::visitSHL(SDNode *N) { 1256 SDOperand N0 = N->getOperand(0); 1257 SDOperand N1 = N->getOperand(1); 1258 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1259 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1260 MVT::ValueType VT = N0.getValueType(); 1261 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1262 1263 // fold (shl c1, c2) -> c1<<c2 1264 if (N0C && N1C) 1265 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT); 1266 // fold (shl 0, x) -> 0 1267 if (N0C && N0C->isNullValue()) 1268 return N0; 1269 // fold (shl x, c >= size(x)) -> undef 1270 if (N1C && N1C->getValue() >= OpSizeInBits) 1271 return DAG.getNode(ISD::UNDEF, VT); 1272 // fold (shl x, 0) -> x 1273 if (N1C && N1C->isNullValue()) 1274 return N0; 1275 // if (shl x, c) is known to be zero, return 0 1276 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1277 return DAG.getConstant(0, VT); 1278 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1279 if (N1C && N0.getOpcode() == ISD::SHL && 1280 N0.getOperand(1).getOpcode() == ISD::Constant) { 1281 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1282 uint64_t c2 = N1C->getValue(); 1283 if (c1 + c2 > OpSizeInBits) 1284 return DAG.getConstant(0, VT); 1285 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1286 DAG.getConstant(c1 + c2, N1.getValueType())); 1287 } 1288 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1289 // (srl (and x, -1 << c1), c1-c2) 1290 if (N1C && N0.getOpcode() == ISD::SRL && 1291 N0.getOperand(1).getOpcode() == ISD::Constant) { 1292 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1293 uint64_t c2 = N1C->getValue(); 1294 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1295 DAG.getConstant(~0ULL << c1, VT)); 1296 if (c2 > c1) 1297 return DAG.getNode(ISD::SHL, VT, Mask, 1298 DAG.getConstant(c2-c1, N1.getValueType())); 1299 else 1300 return DAG.getNode(ISD::SRL, VT, Mask, 1301 DAG.getConstant(c1-c2, N1.getValueType())); 1302 } 1303 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1304 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1305 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1306 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1307 return SDOperand(); 1308} 1309 1310SDOperand DAGCombiner::visitSRA(SDNode *N) { 1311 SDOperand N0 = N->getOperand(0); 1312 SDOperand N1 = N->getOperand(1); 1313 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1314 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1315 MVT::ValueType VT = N0.getValueType(); 1316 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1317 1318 // fold (sra c1, c2) -> c1>>c2 1319 if (N0C && N1C) 1320 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT); 1321 // fold (sra 0, x) -> 0 1322 if (N0C && N0C->isNullValue()) 1323 return N0; 1324 // fold (sra -1, x) -> -1 1325 if (N0C && N0C->isAllOnesValue()) 1326 return N0; 1327 // fold (sra x, c >= size(x)) -> undef 1328 if (N1C && N1C->getValue() >= OpSizeInBits) 1329 return DAG.getNode(ISD::UNDEF, VT); 1330 // fold (sra x, 0) -> x 1331 if (N1C && N1C->isNullValue()) 1332 return N0; 1333 // If the sign bit is known to be zero, switch this to a SRL. 1334 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI)) 1335 return DAG.getNode(ISD::SRL, VT, N0, N1); 1336 return SDOperand(); 1337} 1338 1339SDOperand DAGCombiner::visitSRL(SDNode *N) { 1340 SDOperand N0 = N->getOperand(0); 1341 SDOperand N1 = N->getOperand(1); 1342 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1343 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1344 MVT::ValueType VT = N0.getValueType(); 1345 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1346 1347 // fold (srl c1, c2) -> c1 >>u c2 1348 if (N0C && N1C) 1349 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT); 1350 // fold (srl 0, x) -> 0 1351 if (N0C && N0C->isNullValue()) 1352 return N0; 1353 // fold (srl x, c >= size(x)) -> undef 1354 if (N1C && N1C->getValue() >= OpSizeInBits) 1355 return DAG.getNode(ISD::UNDEF, VT); 1356 // fold (srl x, 0) -> x 1357 if (N1C && N1C->isNullValue()) 1358 return N0; 1359 // if (srl x, c) is known to be zero, return 0 1360 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1361 return DAG.getConstant(0, VT); 1362 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1363 if (N1C && N0.getOpcode() == ISD::SRL && 1364 N0.getOperand(1).getOpcode() == ISD::Constant) { 1365 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1366 uint64_t c2 = N1C->getValue(); 1367 if (c1 + c2 > OpSizeInBits) 1368 return DAG.getConstant(0, VT); 1369 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1370 DAG.getConstant(c1 + c2, N1.getValueType())); 1371 } 1372 return SDOperand(); 1373} 1374 1375SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1376 SDOperand N0 = N->getOperand(0); 1377 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1378 1379 // fold (ctlz c1) -> c2 1380 if (N0C) 1381 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()), 1382 N0.getValueType()); 1383 return SDOperand(); 1384} 1385 1386SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1387 SDOperand N0 = N->getOperand(0); 1388 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1389 1390 // fold (cttz c1) -> c2 1391 if (N0C) 1392 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()), 1393 N0.getValueType()); 1394 return SDOperand(); 1395} 1396 1397SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1398 SDOperand N0 = N->getOperand(0); 1399 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1400 1401 // fold (ctpop c1) -> c2 1402 if (N0C) 1403 return DAG.getConstant(CountPopulation_64(N0C->getValue()), 1404 N0.getValueType()); 1405 return SDOperand(); 1406} 1407 1408SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1409 SDOperand N0 = N->getOperand(0); 1410 SDOperand N1 = N->getOperand(1); 1411 SDOperand N2 = N->getOperand(2); 1412 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1414 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1415 MVT::ValueType VT = N->getValueType(0); 1416 1417 // fold select C, X, X -> X 1418 if (N1 == N2) 1419 return N1; 1420 // fold select true, X, Y -> X 1421 if (N0C && !N0C->isNullValue()) 1422 return N1; 1423 // fold select false, X, Y -> Y 1424 if (N0C && N0C->isNullValue()) 1425 return N2; 1426 // fold select C, 1, X -> C | X 1427 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1428 return DAG.getNode(ISD::OR, VT, N0, N2); 1429 // fold select C, 0, X -> ~C & X 1430 // FIXME: this should check for C type == X type, not i1? 1431 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1432 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1433 WorkList.push_back(XORNode.Val); 1434 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1435 } 1436 // fold select C, X, 1 -> ~C | X 1437 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1438 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1439 WorkList.push_back(XORNode.Val); 1440 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1441 } 1442 // fold select C, X, 0 -> C & X 1443 // FIXME: this should check for C type == X type, not i1? 1444 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1445 return DAG.getNode(ISD::AND, VT, N0, N1); 1446 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1447 if (MVT::i1 == VT && N0 == N1) 1448 return DAG.getNode(ISD::OR, VT, N0, N2); 1449 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1450 if (MVT::i1 == VT && N0 == N2) 1451 return DAG.getNode(ISD::AND, VT, N0, N1); 1452 1453 // If we can fold this based on the true/false value, do so. 1454 if (SimplifySelectOps(N, N1, N2)) 1455 return SDOperand(); 1456 1457 // fold selects based on a setcc into other things, such as min/max/abs 1458 if (N0.getOpcode() == ISD::SETCC) 1459 return SimplifySelect(N0, N1, N2); 1460 return SDOperand(); 1461} 1462 1463SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1464 SDOperand N0 = N->getOperand(0); 1465 SDOperand N1 = N->getOperand(1); 1466 SDOperand N2 = N->getOperand(2); 1467 SDOperand N3 = N->getOperand(3); 1468 SDOperand N4 = N->getOperand(4); 1469 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1470 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1471 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1472 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1473 1474 // Determine if the condition we're dealing with is constant 1475 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1476 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1477 1478 // fold select_cc lhs, rhs, x, x, cc -> x 1479 if (N2 == N3) 1480 return N2; 1481 1482 // If we can fold this based on the true/false value, do so. 1483 if (SimplifySelectOps(N, N2, N3)) 1484 return SDOperand(); 1485 1486 // fold select_cc into other things, such as min/max/abs 1487 return SimplifySelectCC(N0, N1, N2, N3, CC); 1488} 1489 1490SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1491 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1492 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1493} 1494 1495SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) { 1496 SDOperand LHSLo = N->getOperand(0); 1497 SDOperand RHSLo = N->getOperand(2); 1498 MVT::ValueType VT = LHSLo.getValueType(); 1499 1500 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo) 1501 if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1502 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1503 N->getOperand(3)); 1504 WorkList.push_back(Hi.Val); 1505 CombineTo(N, RHSLo, Hi); 1506 return SDOperand(); 1507 } 1508 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo) 1509 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1510 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1511 N->getOperand(3)); 1512 WorkList.push_back(Hi.Val); 1513 CombineTo(N, LHSLo, Hi); 1514 return SDOperand(); 1515 } 1516 return SDOperand(); 1517} 1518 1519SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) { 1520 SDOperand LHSLo = N->getOperand(0); 1521 SDOperand RHSLo = N->getOperand(2); 1522 MVT::ValueType VT = LHSLo.getValueType(); 1523 1524 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo) 1525 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1526 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1), 1527 N->getOperand(3)); 1528 WorkList.push_back(Hi.Val); 1529 CombineTo(N, LHSLo, Hi); 1530 return SDOperand(); 1531 } 1532 return SDOperand(); 1533} 1534 1535SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1536 SDOperand N0 = N->getOperand(0); 1537 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1538 MVT::ValueType VT = N->getValueType(0); 1539 1540 // fold (sext c1) -> c1 1541 if (N0C) 1542 return DAG.getConstant(N0C->getSignExtended(), VT); 1543 // fold (sext (sext x)) -> (sext x) 1544 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1545 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1546 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1547 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1548 (!AfterLegalize || 1549 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1550 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1551 DAG.getValueType(N0.getValueType())); 1552 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1553 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1554 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1555 N0.getOperand(1), N0.getOperand(2), 1556 N0.getValueType()); 1557 WorkList.push_back(N); 1558 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1559 ExtLoad.getValue(1)); 1560 return SDOperand(); 1561 } 1562 1563 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1564 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1565 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1566 N0.hasOneUse()) { 1567 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0), 1568 N0.getOperand(1), N0.getOperand(2), 1569 N0.getOperand(3)); 1570 WorkList.push_back(N); 1571 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1572 ExtLoad.getValue(1)); 1573 return SDOperand(); 1574 } 1575 1576 return SDOperand(); 1577} 1578 1579SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1580 SDOperand N0 = N->getOperand(0); 1581 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1582 MVT::ValueType VT = N->getValueType(0); 1583 1584 // fold (zext c1) -> c1 1585 if (N0C) 1586 return DAG.getConstant(N0C->getValue(), VT); 1587 // fold (zext (zext x)) -> (zext x) 1588 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1589 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1590 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1591 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1592 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1593 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1594 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1595 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1596 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1597 N0.getOperand(1), N0.getOperand(2), 1598 N0.getValueType()); 1599 WorkList.push_back(N); 1600 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1601 ExtLoad.getValue(1)); 1602 return SDOperand(); 1603 } 1604 1605 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1606 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1607 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1608 N0.hasOneUse()) { 1609 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1610 N0.getOperand(1), N0.getOperand(2), 1611 N0.getOperand(3)); 1612 WorkList.push_back(N); 1613 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1614 ExtLoad.getValue(1)); 1615 return SDOperand(); 1616 } 1617 return SDOperand(); 1618} 1619 1620SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1621 SDOperand N0 = N->getOperand(0); 1622 SDOperand N1 = N->getOperand(1); 1623 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1624 MVT::ValueType VT = N->getValueType(0); 1625 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1626 unsigned EVTBits = MVT::getSizeInBits(EVT); 1627 1628 // fold (sext_in_reg c1) -> c1 1629 if (N0C) { 1630 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1631 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1632 } 1633 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1634 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1635 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1636 return N0; 1637 } 1638 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1639 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1640 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1641 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1642 } 1643 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1644 if (N0.getOpcode() == ISD::AssertSext && 1645 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1646 return N0; 1647 } 1648 // fold (sext_in_reg (sextload x)) -> (sextload x) 1649 if (N0.getOpcode() == ISD::SEXTLOAD && 1650 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1651 return N0; 1652 } 1653 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1654 if (N0.getOpcode() == ISD::SETCC && 1655 TLI.getSetCCResultContents() == 1656 TargetLowering::ZeroOrNegativeOneSetCCResult) 1657 return N0; 1658 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1659 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI)) 1660 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 1661 DAG.getConstant(~0ULL >> (64-EVTBits), VT)); 1662 // fold (sext_in_reg (srl x)) -> sra x 1663 if (N0.getOpcode() == ISD::SRL && 1664 N0.getOperand(1).getOpcode() == ISD::Constant && 1665 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1666 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1667 N0.getOperand(1)); 1668 } 1669 // fold (sext_inreg (extload x)) -> (sextload x) 1670 if (N0.getOpcode() == ISD::EXTLOAD && 1671 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1672 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1673 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1674 N0.getOperand(1), N0.getOperand(2), 1675 EVT); 1676 WorkList.push_back(N); 1677 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1678 return SDOperand(); 1679 } 1680 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1681 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1682 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1683 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1684 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1685 N0.getOperand(1), N0.getOperand(2), 1686 EVT); 1687 WorkList.push_back(N); 1688 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1689 return SDOperand(); 1690 } 1691 return SDOperand(); 1692} 1693 1694SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1695 SDOperand N0 = N->getOperand(0); 1696 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1697 MVT::ValueType VT = N->getValueType(0); 1698 1699 // noop truncate 1700 if (N0.getValueType() == N->getValueType(0)) 1701 return N0; 1702 // fold (truncate c1) -> c1 1703 if (N0C) 1704 return DAG.getConstant(N0C->getValue(), VT); 1705 // fold (truncate (truncate x)) -> (truncate x) 1706 if (N0.getOpcode() == ISD::TRUNCATE) 1707 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1708 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1709 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1710 if (N0.getValueType() < VT) 1711 // if the source is smaller than the dest, we still need an extend 1712 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1713 else if (N0.getValueType() > VT) 1714 // if the source is larger than the dest, than we just need the truncate 1715 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1716 else 1717 // if the source and dest are the same type, we can drop both the extend 1718 // and the truncate 1719 return N0.getOperand(0); 1720 } 1721 // fold (truncate (load x)) -> (smaller load x) 1722 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1723 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1724 "Cannot truncate to larger type!"); 1725 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1726 // For big endian targets, we need to add an offset to the pointer to load 1727 // the correct bytes. For little endian systems, we merely need to read 1728 // fewer bytes from the same pointer. 1729 uint64_t PtrOff = 1730 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1731 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1732 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1733 DAG.getConstant(PtrOff, PtrType)); 1734 WorkList.push_back(NewPtr.Val); 1735 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1736 WorkList.push_back(N); 1737 CombineTo(N0.Val, Load, Load.getValue(1)); 1738 return SDOperand(); 1739 } 1740 return SDOperand(); 1741} 1742 1743SDOperand DAGCombiner::visitFADD(SDNode *N) { 1744 SDOperand N0 = N->getOperand(0); 1745 SDOperand N1 = N->getOperand(1); 1746 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1747 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1748 MVT::ValueType VT = N->getValueType(0); 1749 1750 // fold (fadd c1, c2) -> c1+c2 1751 if (N0CFP && N1CFP) 1752 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), VT); 1753 // canonicalize constant to RHS 1754 if (N0CFP && !N1CFP) 1755 return DAG.getNode(ISD::FADD, VT, N1, N0); 1756 // fold (A + (-B)) -> A-B 1757 if (N1.getOpcode() == ISD::FNEG) 1758 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1759 // fold ((-A) + B) -> B-A 1760 if (N0.getOpcode() == ISD::FNEG) 1761 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1762 return SDOperand(); 1763} 1764 1765SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1766 SDOperand N0 = N->getOperand(0); 1767 SDOperand N1 = N->getOperand(1); 1768 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1769 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1770 MVT::ValueType VT = N->getValueType(0); 1771 1772 // fold (fsub c1, c2) -> c1-c2 1773 if (N0CFP && N1CFP) 1774 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(), VT); 1775 // fold (A-(-B)) -> A+B 1776 if (N1.getOpcode() == ISD::FNEG) 1777 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0)); 1778 return SDOperand(); 1779} 1780 1781SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1782 SDOperand N0 = N->getOperand(0); 1783 SDOperand N1 = N->getOperand(1); 1784 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1785 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1786 MVT::ValueType VT = N->getValueType(0); 1787 1788 // fold (fmul c1, c2) -> c1*c2 1789 if (N0CFP && N1CFP) 1790 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(), VT); 1791 // canonicalize constant to RHS 1792 if (N0CFP && !N1CFP) 1793 return DAG.getNode(ISD::FMUL, VT, N1, N0); 1794 // fold (fmul X, 2.0) -> (fadd X, X) 1795 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 1796 return DAG.getNode(ISD::FADD, VT, N0, N0); 1797 return SDOperand(); 1798} 1799 1800SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1801 SDOperand N0 = N->getOperand(0); 1802 SDOperand N1 = N->getOperand(1); 1803 MVT::ValueType VT = N->getValueType(0); 1804 1805 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1806 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1807 // fold floating point (fdiv c1, c2) 1808 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(), VT); 1809 } 1810 return SDOperand(); 1811} 1812 1813SDOperand DAGCombiner::visitFREM(SDNode *N) { 1814 SDOperand N0 = N->getOperand(0); 1815 SDOperand N1 = N->getOperand(1); 1816 MVT::ValueType VT = N->getValueType(0); 1817 1818 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1819 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1820 // fold floating point (frem c1, c2) -> fmod(c1, c2) 1821 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()), VT); 1822 } 1823 return SDOperand(); 1824} 1825 1826 1827SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1828 SDOperand N0 = N->getOperand(0); 1829 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1830 1831 // fold (sint_to_fp c1) -> c1fp 1832 if (N0C) 1833 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0)); 1834 return SDOperand(); 1835} 1836 1837SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1838 SDOperand N0 = N->getOperand(0); 1839 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1840 1841 // fold (uint_to_fp c1) -> c1fp 1842 if (N0C) 1843 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0)); 1844 return SDOperand(); 1845} 1846 1847SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1848 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1849 1850 // fold (fp_to_sint c1fp) -> c1 1851 if (N0CFP) 1852 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0)); 1853 return SDOperand(); 1854} 1855 1856SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1857 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1858 1859 // fold (fp_to_uint c1fp) -> c1 1860 if (N0CFP) 1861 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0)); 1862 return SDOperand(); 1863} 1864 1865SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1866 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1867 1868 // fold (fp_round c1fp) -> c1fp 1869 if (N0CFP) 1870 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1871 return SDOperand(); 1872} 1873 1874SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1875 SDOperand N0 = N->getOperand(0); 1876 MVT::ValueType VT = N->getValueType(0); 1877 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1878 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1879 1880 // fold (fp_round_inreg c1fp) -> c1fp 1881 if (N0CFP) { 1882 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1883 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1884 } 1885 return SDOperand(); 1886} 1887 1888SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1889 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1890 1891 // fold (fp_extend c1fp) -> c1fp 1892 if (N0CFP) 1893 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1894 return SDOperand(); 1895} 1896 1897SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1898 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1899 // fold (neg c1) -> -c1 1900 if (N0CFP) 1901 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0)); 1902 // fold (neg (sub x, y)) -> (sub y, x) 1903 if (N->getOperand(0).getOpcode() == ISD::SUB) 1904 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1), 1905 N->getOperand(0)); 1906 // fold (neg (neg x)) -> x 1907 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1908 return N->getOperand(0).getOperand(0); 1909 return SDOperand(); 1910} 1911 1912SDOperand DAGCombiner::visitFABS(SDNode *N) { 1913 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1914 // fold (fabs c1) -> fabs(c1) 1915 if (N0CFP) 1916 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0)); 1917 // fold (fabs (fabs x)) -> (fabs x) 1918 if (N->getOperand(0).getOpcode() == ISD::FABS) 1919 return N->getOperand(0); 1920 // fold (fabs (fneg x)) -> (fabs x) 1921 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1922 return DAG.getNode(ISD::FABS, N->getValueType(0), 1923 N->getOperand(0).getOperand(0)); 1924 return SDOperand(); 1925} 1926 1927SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 1928 SDOperand Chain = N->getOperand(0); 1929 SDOperand N1 = N->getOperand(1); 1930 SDOperand N2 = N->getOperand(2); 1931 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1932 1933 // never taken branch, fold to chain 1934 if (N1C && N1C->isNullValue()) 1935 return Chain; 1936 // unconditional branch 1937 if (N1C && N1C->getValue() == 1) 1938 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1939 return SDOperand(); 1940} 1941 1942SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 1943 SDOperand Chain = N->getOperand(0); 1944 SDOperand N1 = N->getOperand(1); 1945 SDOperand N2 = N->getOperand(2); 1946 SDOperand N3 = N->getOperand(3); 1947 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1948 1949 // unconditional branch to true mbb 1950 if (N1C && N1C->getValue() == 1) 1951 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1952 // unconditional branch to false mbb 1953 if (N1C && N1C->isNullValue()) 1954 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 1955 return SDOperand(); 1956} 1957 1958// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 1959// 1960SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 1961 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 1962 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 1963 1964 // Use SimplifySetCC to simplify SETCC's. 1965 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 1966 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 1967 1968 // fold br_cc true, dest -> br dest (unconditional branch) 1969 if (SCCC && SCCC->getValue()) 1970 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 1971 N->getOperand(4)); 1972 // fold br_cc false, dest -> unconditional fall through 1973 if (SCCC && SCCC->isNullValue()) 1974 return N->getOperand(0); 1975 // fold to a simpler setcc 1976 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 1977 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 1978 Simp.getOperand(2), Simp.getOperand(0), 1979 Simp.getOperand(1), N->getOperand(4)); 1980 return SDOperand(); 1981} 1982 1983SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 1984 SDOperand Chain = N->getOperand(0); 1985 SDOperand CCN = N->getOperand(1); 1986 SDOperand LHS = N->getOperand(2); 1987 SDOperand RHS = N->getOperand(3); 1988 SDOperand N4 = N->getOperand(4); 1989 SDOperand N5 = N->getOperand(5); 1990 1991 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 1992 cast<CondCodeSDNode>(CCN)->get(), false); 1993 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1994 1995 // fold select_cc lhs, rhs, x, x, cc -> x 1996 if (N4 == N5) 1997 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1998 // fold select_cc true, x, y -> x 1999 if (SCCC && SCCC->getValue()) 2000 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2001 // fold select_cc false, x, y -> y 2002 if (SCCC && SCCC->isNullValue()) 2003 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 2004 // fold to a simpler setcc 2005 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2006 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0), 2007 SCC.getOperand(1), N4, N5); 2008 return SDOperand(); 2009} 2010 2011SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2012 SDOperand Chain = N->getOperand(0); 2013 SDOperand Ptr = N->getOperand(1); 2014 SDOperand SrcValue = N->getOperand(2); 2015 2016 // If this load is directly stored, replace the load value with the stored 2017 // value. 2018 // TODO: Handle store large -> read small portion. 2019 // TODO: Handle TRUNCSTORE/EXTLOAD 2020 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2021 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2022 return CombineTo(N, Chain.getOperand(1), Chain); 2023 2024 return SDOperand(); 2025} 2026 2027SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2028 SDOperand Chain = N->getOperand(0); 2029 SDOperand Value = N->getOperand(1); 2030 SDOperand Ptr = N->getOperand(2); 2031 SDOperand SrcValue = N->getOperand(3); 2032 2033 // If this is a store that kills a previous store, remove the previous store. 2034 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2035 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2036 // Make sure that these stores are the same value type: 2037 // FIXME: we really care that the second store is >= size of the first. 2038 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2039 // Create a new store of Value that replaces both stores. 2040 SDNode *PrevStore = Chain.Val; 2041 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2042 return Chain; 2043 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2044 PrevStore->getOperand(0), Value, Ptr, 2045 SrcValue); 2046 CombineTo(N, NewStore); // Nuke this store. 2047 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2048 return SDOperand(N, 0); 2049 } 2050 2051 return SDOperand(); 2052} 2053 2054SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2055 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2056 2057 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2058 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2059 // If we got a simplified select_cc node back from SimplifySelectCC, then 2060 // break it down into a new SETCC node, and a new SELECT node, and then return 2061 // the SELECT node, since we were called with a SELECT node. 2062 if (SCC.Val) { 2063 // Check to see if we got a select_cc back (to turn into setcc/select). 2064 // Otherwise, just return whatever node we got back, like fabs. 2065 if (SCC.getOpcode() == ISD::SELECT_CC) { 2066 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2067 SCC.getOperand(0), SCC.getOperand(1), 2068 SCC.getOperand(4)); 2069 WorkList.push_back(SETCC.Val); 2070 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2071 SCC.getOperand(3), SETCC); 2072 } 2073 return SCC; 2074 } 2075 return SDOperand(); 2076} 2077 2078/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2079/// are the two values being selected between, see if we can simplify the 2080/// select. 2081/// 2082bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2083 SDOperand RHS) { 2084 2085 // If this is a select from two identical things, try to pull the operation 2086 // through the select. 2087 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2088#if 0 2089 std::cerr << "SELECT: ["; LHS.Val->dump(); 2090 std::cerr << "] ["; RHS.Val->dump(); 2091 std::cerr << "]\n"; 2092#endif 2093 2094 // If this is a load and the token chain is identical, replace the select 2095 // of two loads with a load through a select of the address to load from. 2096 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2097 // constants have been dropped into the constant pool. 2098 if ((LHS.getOpcode() == ISD::LOAD || 2099 LHS.getOpcode() == ISD::EXTLOAD || 2100 LHS.getOpcode() == ISD::ZEXTLOAD || 2101 LHS.getOpcode() == ISD::SEXTLOAD) && 2102 // Token chains must be identical. 2103 LHS.getOperand(0) == RHS.getOperand(0) && 2104 // If this is an EXTLOAD, the VT's must match. 2105 (LHS.getOpcode() == ISD::LOAD || 2106 LHS.getOperand(3) == RHS.getOperand(3))) { 2107 // FIXME: this conflates two src values, discarding one. This is not 2108 // the right thing to do, but nothing uses srcvalues now. When they do, 2109 // turn SrcValue into a list of locations. 2110 SDOperand Addr; 2111 if (TheSelect->getOpcode() == ISD::SELECT) 2112 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2113 TheSelect->getOperand(0), LHS.getOperand(1), 2114 RHS.getOperand(1)); 2115 else 2116 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2117 TheSelect->getOperand(0), 2118 TheSelect->getOperand(1), 2119 LHS.getOperand(1), RHS.getOperand(1), 2120 TheSelect->getOperand(4)); 2121 2122 SDOperand Load; 2123 if (LHS.getOpcode() == ISD::LOAD) 2124 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2125 Addr, LHS.getOperand(2)); 2126 else 2127 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2128 LHS.getOperand(0), Addr, LHS.getOperand(2), 2129 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2130 // Users of the select now use the result of the load. 2131 CombineTo(TheSelect, Load); 2132 2133 // Users of the old loads now use the new load's chain. We know the 2134 // old-load value is dead now. 2135 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2136 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2137 return true; 2138 } 2139 } 2140 2141 return false; 2142} 2143 2144SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2145 SDOperand N2, SDOperand N3, 2146 ISD::CondCode CC) { 2147 2148 MVT::ValueType VT = N2.getValueType(); 2149 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2150 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2151 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2152 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2153 2154 // Determine if the condition we're dealing with is constant 2155 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2156 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2157 2158 // fold select_cc true, x, y -> x 2159 if (SCCC && SCCC->getValue()) 2160 return N2; 2161 // fold select_cc false, x, y -> y 2162 if (SCCC && SCCC->getValue() == 0) 2163 return N3; 2164 2165 // Check to see if we can simplify the select into an fabs node 2166 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2167 // Allow either -0.0 or 0.0 2168 if (CFP->getValue() == 0.0) { 2169 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2170 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2171 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2172 N2 == N3.getOperand(0)) 2173 return DAG.getNode(ISD::FABS, VT, N0); 2174 2175 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2176 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2177 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2178 N2.getOperand(0) == N3) 2179 return DAG.getNode(ISD::FABS, VT, N3); 2180 } 2181 } 2182 2183 // Check to see if we can perform the "gzip trick", transforming 2184 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2185 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2186 MVT::isInteger(N0.getValueType()) && 2187 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2188 MVT::ValueType XType = N0.getValueType(); 2189 MVT::ValueType AType = N2.getValueType(); 2190 if (XType >= AType) { 2191 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2192 // single-bit constant. 2193 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2194 unsigned ShCtV = Log2_64(N2C->getValue()); 2195 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 2196 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 2197 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 2198 WorkList.push_back(Shift.Val); 2199 if (XType > AType) { 2200 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2201 WorkList.push_back(Shift.Val); 2202 } 2203 return DAG.getNode(ISD::AND, AType, Shift, N2); 2204 } 2205 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2206 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2207 TLI.getShiftAmountTy())); 2208 WorkList.push_back(Shift.Val); 2209 if (XType > AType) { 2210 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2211 WorkList.push_back(Shift.Val); 2212 } 2213 return DAG.getNode(ISD::AND, AType, Shift, N2); 2214 } 2215 } 2216 2217 // fold select C, 16, 0 -> shl C, 4 2218 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 2219 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 2220 // Get a SetCC of the condition 2221 // FIXME: Should probably make sure that setcc is legal if we ever have a 2222 // target where it isn't. 2223 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2224 WorkList.push_back(SCC.Val); 2225 // cast from setcc result type to select result type 2226 if (AfterLegalize) 2227 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 2228 else 2229 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 2230 WorkList.push_back(Temp.Val); 2231 // shl setcc result by log2 n2c 2232 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 2233 DAG.getConstant(Log2_64(N2C->getValue()), 2234 TLI.getShiftAmountTy())); 2235 } 2236 2237 // Check to see if this is the equivalent of setcc 2238 // FIXME: Turn all of these into setcc if setcc if setcc is legal 2239 // otherwise, go ahead with the folds. 2240 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 2241 MVT::ValueType XType = N0.getValueType(); 2242 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 2243 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2244 if (Res.getValueType() != VT) 2245 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 2246 return Res; 2247 } 2248 2249 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 2250 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 2251 TLI.isOperationLegal(ISD::CTLZ, XType)) { 2252 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 2253 return DAG.getNode(ISD::SRL, XType, Ctlz, 2254 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 2255 TLI.getShiftAmountTy())); 2256 } 2257 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 2258 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 2259 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 2260 N0); 2261 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 2262 DAG.getConstant(~0ULL, XType)); 2263 return DAG.getNode(ISD::SRL, XType, 2264 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 2265 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2266 TLI.getShiftAmountTy())); 2267 } 2268 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 2269 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 2270 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 2271 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2272 TLI.getShiftAmountTy())); 2273 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 2274 } 2275 } 2276 2277 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 2278 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2279 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 2280 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 2281 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 2282 MVT::ValueType XType = N0.getValueType(); 2283 if (SubC->isNullValue() && MVT::isInteger(XType)) { 2284 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2285 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2286 TLI.getShiftAmountTy())); 2287 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 2288 WorkList.push_back(Shift.Val); 2289 WorkList.push_back(Add.Val); 2290 return DAG.getNode(ISD::XOR, XType, Add, Shift); 2291 } 2292 } 2293 } 2294 2295 return SDOperand(); 2296} 2297 2298SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 2299 SDOperand N1, ISD::CondCode Cond, 2300 bool foldBooleans) { 2301 // These setcc operations always fold. 2302 switch (Cond) { 2303 default: break; 2304 case ISD::SETFALSE: 2305 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 2306 case ISD::SETTRUE: 2307 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 2308 } 2309 2310 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 2311 uint64_t C1 = N1C->getValue(); 2312 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 2313 uint64_t C0 = N0C->getValue(); 2314 2315 // Sign extend the operands if required 2316 if (ISD::isSignedIntSetCC(Cond)) { 2317 C0 = N0C->getSignExtended(); 2318 C1 = N1C->getSignExtended(); 2319 } 2320 2321 switch (Cond) { 2322 default: assert(0 && "Unknown integer setcc!"); 2323 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2324 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2325 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 2326 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 2327 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 2328 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 2329 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 2330 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 2331 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 2332 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 2333 } 2334 } else { 2335 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2336 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2337 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 2338 2339 // If the comparison constant has bits in the upper part, the 2340 // zero-extended value could never match. 2341 if (C1 & (~0ULL << InSize)) { 2342 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 2343 switch (Cond) { 2344 case ISD::SETUGT: 2345 case ISD::SETUGE: 2346 case ISD::SETEQ: return DAG.getConstant(0, VT); 2347 case ISD::SETULT: 2348 case ISD::SETULE: 2349 case ISD::SETNE: return DAG.getConstant(1, VT); 2350 case ISD::SETGT: 2351 case ISD::SETGE: 2352 // True if the sign bit of C1 is set. 2353 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 2354 case ISD::SETLT: 2355 case ISD::SETLE: 2356 // True if the sign bit of C1 isn't set. 2357 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 2358 default: 2359 break; 2360 } 2361 } 2362 2363 // Otherwise, we can perform the comparison with the low bits. 2364 switch (Cond) { 2365 case ISD::SETEQ: 2366 case ISD::SETNE: 2367 case ISD::SETUGT: 2368 case ISD::SETUGE: 2369 case ISD::SETULT: 2370 case ISD::SETULE: 2371 return DAG.getSetCC(VT, N0.getOperand(0), 2372 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 2373 Cond); 2374 default: 2375 break; // todo, be more careful with signed comparisons 2376 } 2377 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2378 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2379 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2380 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 2381 MVT::ValueType ExtDstTy = N0.getValueType(); 2382 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 2383 2384 // If the extended part has any inconsistent bits, it cannot ever 2385 // compare equal. In other words, they have to be all ones or all 2386 // zeros. 2387 uint64_t ExtBits = 2388 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 2389 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 2390 return DAG.getConstant(Cond == ISD::SETNE, VT); 2391 2392 SDOperand ZextOp; 2393 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 2394 if (Op0Ty == ExtSrcTy) { 2395 ZextOp = N0.getOperand(0); 2396 } else { 2397 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 2398 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 2399 DAG.getConstant(Imm, Op0Ty)); 2400 } 2401 WorkList.push_back(ZextOp.Val); 2402 // Otherwise, make this a use of a zext. 2403 return DAG.getSetCC(VT, ZextOp, 2404 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 2405 ExtDstTy), 2406 Cond); 2407 } 2408 2409 uint64_t MinVal, MaxVal; 2410 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 2411 if (ISD::isSignedIntSetCC(Cond)) { 2412 MinVal = 1ULL << (OperandBitSize-1); 2413 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2414 MaxVal = ~0ULL >> (65-OperandBitSize); 2415 else 2416 MaxVal = 0; 2417 } else { 2418 MinVal = 0; 2419 MaxVal = ~0ULL >> (64-OperandBitSize); 2420 } 2421 2422 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2423 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2424 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2425 --C1; // X >= C0 --> X > (C0-1) 2426 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2427 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2428 } 2429 2430 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2431 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2432 ++C1; // X <= C0 --> X < (C0+1) 2433 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2434 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2435 } 2436 2437 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2438 return DAG.getConstant(0, VT); // X < MIN --> false 2439 2440 // Canonicalize setgt X, Min --> setne X, Min 2441 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2442 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2443 // Canonicalize setlt X, Max --> setne X, Max 2444 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2445 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2446 2447 // If we have setult X, 1, turn it into seteq X, 0 2448 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2449 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2450 ISD::SETEQ); 2451 // If we have setugt X, Max-1, turn it into seteq X, Max 2452 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2453 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2454 ISD::SETEQ); 2455 2456 // If we have "setcc X, C0", check to see if we can shrink the immediate 2457 // by changing cc. 2458 2459 // SETUGT X, SINTMAX -> SETLT X, 0 2460 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2461 C1 == (~0ULL >> (65-OperandBitSize))) 2462 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2463 ISD::SETLT); 2464 2465 // FIXME: Implement the rest of these. 2466 2467 // Fold bit comparisons when we can. 2468 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2469 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2470 if (ConstantSDNode *AndRHS = 2471 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2472 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2473 // Perform the xform if the AND RHS is a single bit. 2474 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2475 return DAG.getNode(ISD::SRL, VT, N0, 2476 DAG.getConstant(Log2_64(AndRHS->getValue()), 2477 TLI.getShiftAmountTy())); 2478 } 2479 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2480 // (X & 8) == 8 --> (X & 8) >> 3 2481 // Perform the xform if C1 is a single bit. 2482 if ((C1 & (C1-1)) == 0) { 2483 return DAG.getNode(ISD::SRL, VT, N0, 2484 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2485 } 2486 } 2487 } 2488 } 2489 } else if (isa<ConstantSDNode>(N0.Val)) { 2490 // Ensure that the constant occurs on the RHS. 2491 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2492 } 2493 2494 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2495 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2496 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2497 2498 switch (Cond) { 2499 default: break; // FIXME: Implement the rest of these! 2500 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2501 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2502 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2503 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2504 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2505 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2506 } 2507 } else { 2508 // Ensure that the constant occurs on the RHS. 2509 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2510 } 2511 2512 if (N0 == N1) { 2513 // We can always fold X == Y for integer setcc's. 2514 if (MVT::isInteger(N0.getValueType())) 2515 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2516 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2517 if (UOF == 2) // FP operators that are undefined on NaNs. 2518 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2519 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2520 return DAG.getConstant(UOF, VT); 2521 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2522 // if it is not already. 2523 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 2524 if (NewCond != Cond) 2525 return DAG.getSetCC(VT, N0, N1, NewCond); 2526 } 2527 2528 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2529 MVT::isInteger(N0.getValueType())) { 2530 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2531 N0.getOpcode() == ISD::XOR) { 2532 // Simplify (X+Y) == (X+Z) --> Y == Z 2533 if (N0.getOpcode() == N1.getOpcode()) { 2534 if (N0.getOperand(0) == N1.getOperand(0)) 2535 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2536 if (N0.getOperand(1) == N1.getOperand(1)) 2537 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2538 if (isCommutativeBinOp(N0.getOpcode())) { 2539 // If X op Y == Y op X, try other combinations. 2540 if (N0.getOperand(0) == N1.getOperand(1)) 2541 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2542 if (N0.getOperand(1) == N1.getOperand(0)) 2543 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 2544 } 2545 } 2546 2547 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes. 2548 if (N0.getOpcode() == ISD::XOR) 2549 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2550 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2551 // If we know that all of the inverted bits are zero, don't bother 2552 // performing the inversion. 2553 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI)) 2554 return DAG.getSetCC(VT, N0.getOperand(0), 2555 DAG.getConstant(XORC->getValue()^RHSC->getValue(), 2556 N0.getValueType()), Cond); 2557 } 2558 2559 // Simplify (X+Z) == X --> Z == 0 2560 if (N0.getOperand(0) == N1) 2561 return DAG.getSetCC(VT, N0.getOperand(1), 2562 DAG.getConstant(0, N0.getValueType()), Cond); 2563 if (N0.getOperand(1) == N1) { 2564 if (isCommutativeBinOp(N0.getOpcode())) 2565 return DAG.getSetCC(VT, N0.getOperand(0), 2566 DAG.getConstant(0, N0.getValueType()), Cond); 2567 else { 2568 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2569 // (Z-X) == X --> Z == X<<1 2570 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2571 N1, 2572 DAG.getConstant(1,TLI.getShiftAmountTy())); 2573 WorkList.push_back(SH.Val); 2574 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2575 } 2576 } 2577 } 2578 2579 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2580 N1.getOpcode() == ISD::XOR) { 2581 // Simplify X == (X+Z) --> Z == 0 2582 if (N1.getOperand(0) == N0) { 2583 return DAG.getSetCC(VT, N1.getOperand(1), 2584 DAG.getConstant(0, N1.getValueType()), Cond); 2585 } else if (N1.getOperand(1) == N0) { 2586 if (isCommutativeBinOp(N1.getOpcode())) { 2587 return DAG.getSetCC(VT, N1.getOperand(0), 2588 DAG.getConstant(0, N1.getValueType()), Cond); 2589 } else { 2590 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2591 // X == (Z-X) --> X<<1 == Z 2592 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2593 DAG.getConstant(1,TLI.getShiftAmountTy())); 2594 WorkList.push_back(SH.Val); 2595 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2596 } 2597 } 2598 } 2599 } 2600 2601 // Fold away ALL boolean setcc's. 2602 SDOperand Temp; 2603 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2604 switch (Cond) { 2605 default: assert(0 && "Unknown integer setcc!"); 2606 case ISD::SETEQ: // X == Y -> (X^Y)^1 2607 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2608 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2609 WorkList.push_back(Temp.Val); 2610 break; 2611 case ISD::SETNE: // X != Y --> (X^Y) 2612 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2613 break; 2614 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2615 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2616 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2617 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2618 WorkList.push_back(Temp.Val); 2619 break; 2620 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2621 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2622 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2623 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2624 WorkList.push_back(Temp.Val); 2625 break; 2626 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2627 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2628 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2629 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2630 WorkList.push_back(Temp.Val); 2631 break; 2632 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2633 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2634 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2635 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2636 break; 2637 } 2638 if (VT != MVT::i1) { 2639 WorkList.push_back(N0.Val); 2640 // FIXME: If running after legalize, we probably can't do this. 2641 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2642 } 2643 return N0; 2644 } 2645 2646 // Could not fold it. 2647 return SDOperand(); 2648} 2649 2650/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2651/// return a DAG expression to select that will generate the same value by 2652/// multiplying by a magic number. See: 2653/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2654SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 2655 MVT::ValueType VT = N->getValueType(0); 2656 2657 // Check to see if we can do this. 2658 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2659 return SDOperand(); // BuildSDIV only operates on i32 or i64 2660 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 2661 return SDOperand(); // Make sure the target supports MULHS. 2662 2663 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2664 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2665 2666 // Multiply the numerator (operand 0) by the magic value 2667 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2668 DAG.getConstant(magics.m, VT)); 2669 // If d > 0 and m < 0, add the numerator 2670 if (d > 0 && magics.m < 0) { 2671 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2672 WorkList.push_back(Q.Val); 2673 } 2674 // If d < 0 and m > 0, subtract the numerator. 2675 if (d < 0 && magics.m > 0) { 2676 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2677 WorkList.push_back(Q.Val); 2678 } 2679 // Shift right algebraic if shift value is nonzero 2680 if (magics.s > 0) { 2681 Q = DAG.getNode(ISD::SRA, VT, Q, 2682 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2683 WorkList.push_back(Q.Val); 2684 } 2685 // Extract the sign bit and add it to the quotient 2686 SDOperand T = 2687 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 2688 TLI.getShiftAmountTy())); 2689 WorkList.push_back(T.Val); 2690 return DAG.getNode(ISD::ADD, VT, Q, T); 2691} 2692 2693/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2694/// return a DAG expression to select that will generate the same value by 2695/// multiplying by a magic number. See: 2696/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2697SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 2698 MVT::ValueType VT = N->getValueType(0); 2699 2700 // Check to see if we can do this. 2701 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2702 return SDOperand(); // BuildUDIV only operates on i32 or i64 2703 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 2704 return SDOperand(); // Make sure the target supports MULHU. 2705 2706 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2707 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2708 2709 // Multiply the numerator (operand 0) by the magic value 2710 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2711 DAG.getConstant(magics.m, VT)); 2712 WorkList.push_back(Q.Val); 2713 2714 if (magics.a == 0) { 2715 return DAG.getNode(ISD::SRL, VT, Q, 2716 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2717 } else { 2718 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2719 WorkList.push_back(NPQ.Val); 2720 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2721 DAG.getConstant(1, TLI.getShiftAmountTy())); 2722 WorkList.push_back(NPQ.Val); 2723 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2724 WorkList.push_back(NPQ.Val); 2725 return DAG.getNode(ISD::SRL, VT, NPQ, 2726 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 2727 } 2728} 2729 2730// SelectionDAG::Combine - This is the entry point for the file. 2731// 2732void SelectionDAG::Combine(bool RunningAfterLegalize) { 2733 /// run - This is the main entry point to this class. 2734 /// 2735 DAGCombiner(*this).Run(RunningAfterLegalize); 2736} 2737