DAGCombiner.cpp revision afd3d56b9dc791d37120922318293a021bd35598
15f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 25f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 35f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// The LLVM Compiler Infrastructure 45f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 55f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// License. See LICENSE.TXT for details. 75f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 85f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)//===----------------------------------------------------------------------===// 95f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 105f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 115f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// both before and after the DAG is legalized. 125f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 135f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 145f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// primarily intended to handle simplification opportunities that are implicit 155f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// in the LLVM IR and exposed by the various codegen lowering phases. 165f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 175f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)//===----------------------------------------------------------------------===// 185f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 195f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#define DEBUG_TYPE "dagcombine" 205f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/CodeGen/SelectionDAG.h" 215f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/DerivedTypes.h" 225f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/LLVMContext.h" 235f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/CodeGen/MachineFunction.h" 245f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/CodeGen/MachineFrameInfo.h" 255f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Analysis/AliasAnalysis.h" 265f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Target/TargetData.h" 275f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Target/TargetLowering.h" 285f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Target/TargetMachine.h" 295f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Target/TargetOptions.h" 305f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/ADT/SmallPtrSet.h" 315f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/ADT/Statistic.h" 325f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Support/CommandLine.h" 335f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Support/Debug.h" 345f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Support/ErrorHandling.h" 355f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Support/MathExtras.h" 365f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Support/raw_ostream.h" 375f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 std::vector<SDNode*> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue visitSHL(SDNode *N); 198 SDValue visitSRA(SDNode *N); 199 SDValue visitSRL(SDNode *N); 200 SDValue visitCTLZ(SDNode *N); 201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 202 SDValue visitCTTZ(SDNode *N); 203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 204 SDValue visitCTPOP(SDNode *N); 205 SDValue visitSELECT(SDNode *N); 206 SDValue visitSELECT_CC(SDNode *N); 207 SDValue visitSETCC(SDNode *N); 208 SDValue visitSIGN_EXTEND(SDNode *N); 209 SDValue visitZERO_EXTEND(SDNode *N); 210 SDValue visitANY_EXTEND(SDNode *N); 211 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 212 SDValue visitTRUNCATE(SDNode *N); 213 SDValue visitBITCAST(SDNode *N); 214 SDValue visitBUILD_PAIR(SDNode *N); 215 SDValue visitFADD(SDNode *N); 216 SDValue visitFSUB(SDNode *N); 217 SDValue visitFMUL(SDNode *N); 218 SDValue visitFDIV(SDNode *N); 219 SDValue visitFREM(SDNode *N); 220 SDValue visitFCOPYSIGN(SDNode *N); 221 SDValue visitSINT_TO_FP(SDNode *N); 222 SDValue visitUINT_TO_FP(SDNode *N); 223 SDValue visitFP_TO_SINT(SDNode *N); 224 SDValue visitFP_TO_UINT(SDNode *N); 225 SDValue visitFP_ROUND(SDNode *N); 226 SDValue visitFP_ROUND_INREG(SDNode *N); 227 SDValue visitFP_EXTEND(SDNode *N); 228 SDValue visitFNEG(SDNode *N); 229 SDValue visitFABS(SDNode *N); 230 SDValue visitBRCOND(SDNode *N); 231 SDValue visitBR_CC(SDNode *N); 232 SDValue visitLOAD(SDNode *N); 233 SDValue visitSTORE(SDNode *N); 234 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 235 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 236 SDValue visitBUILD_VECTOR(SDNode *N); 237 SDValue visitCONCAT_VECTORS(SDNode *N); 238 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 239 SDValue visitVECTOR_SHUFFLE(SDNode *N); 240 SDValue visitMEMBARRIER(SDNode *N); 241 242 SDValue XformToShuffleWithZero(SDNode *N); 243 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 244 245 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 246 247 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 248 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 249 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 250 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 251 SDValue N3, ISD::CondCode CC, 252 bool NotExtCompare = false); 253 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 254 DebugLoc DL, bool foldBooleans = true); 255 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 256 unsigned HiOp); 257 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 258 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 259 SDValue BuildSDIV(SDNode *N); 260 SDValue BuildUDIV(SDNode *N); 261 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 262 bool DemandHighBits = true); 263 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 264 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 265 SDValue ReduceLoadWidth(SDNode *N); 266 SDValue ReduceLoadOpStoreWidth(SDNode *N); 267 SDValue TransformFPLoadStorePair(SDNode *N); 268 269 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 270 271 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 272 /// looking for aliasing nodes and adding them to the Aliases vector. 273 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 274 SmallVector<SDValue, 8> &Aliases); 275 276 /// isAlias - Return true if there is any possibility that the two addresses 277 /// overlap. 278 bool isAlias(SDValue Ptr1, int64_t Size1, 279 const Value *SrcValue1, int SrcValueOffset1, 280 unsigned SrcValueAlign1, 281 const MDNode *TBAAInfo1, 282 SDValue Ptr2, int64_t Size2, 283 const Value *SrcValue2, int SrcValueOffset2, 284 unsigned SrcValueAlign2, 285 const MDNode *TBAAInfo2) const; 286 287 /// FindAliasInfo - Extracts the relevant alias information from the memory 288 /// node. Returns true if the operand was a load. 289 bool FindAliasInfo(SDNode *N, 290 SDValue &Ptr, int64_t &Size, 291 const Value *&SrcValue, int &SrcValueOffset, 292 unsigned &SrcValueAlignment, 293 const MDNode *&TBAAInfo) const; 294 295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 296 /// looking for a better chain (aliasing node.) 297 SDValue FindBetterChain(SDNode *N, SDValue Chain); 298 299 public: 300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 301 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 302 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 303 304 /// Run - runs the dag combiner on all nodes in the work list 305 void Run(CombineLevel AtLevel); 306 307 SelectionDAG &getDAG() const { return DAG; } 308 309 /// getShiftAmountTy - Returns a type large enough to hold any valid 310 /// shift amount - before type legalization these can be huge. 311 EVT getShiftAmountTy(EVT LHSTy) { 312 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 313 } 314 315 /// isTypeLegal - This method returns true if we are running before type 316 /// legalization or if the specified VT is legal. 317 bool isTypeLegal(const EVT &VT) { 318 if (!LegalTypes) return true; 319 return TLI.isTypeLegal(VT); 320 } 321 }; 322} 323 324 325namespace { 326/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 327/// nodes from the worklist. 328class WorkListRemover : public SelectionDAG::DAGUpdateListener { 329 DAGCombiner &DC; 330public: 331 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 332 333 virtual void NodeDeleted(SDNode *N, SDNode *E) { 334 DC.removeFromWorkList(N); 335 } 336 337 virtual void NodeUpdated(SDNode *N) { 338 // Ignore updates. 339 } 340}; 341} 342 343//===----------------------------------------------------------------------===// 344// TargetLowering::DAGCombinerInfo implementation 345//===----------------------------------------------------------------------===// 346 347void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 348 ((DAGCombiner*)DC)->AddToWorkList(N); 349} 350 351void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 352 ((DAGCombiner*)DC)->removeFromWorkList(N); 353} 354 355SDValue TargetLowering::DAGCombinerInfo:: 356CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 357 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 358} 359 360SDValue TargetLowering::DAGCombinerInfo:: 361CombineTo(SDNode *N, SDValue Res, bool AddTo) { 362 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 363} 364 365 366SDValue TargetLowering::DAGCombinerInfo:: 367CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 368 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 369} 370 371void TargetLowering::DAGCombinerInfo:: 372CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 373 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 374} 375 376//===----------------------------------------------------------------------===// 377// Helper Functions 378//===----------------------------------------------------------------------===// 379 380/// isNegatibleForFree - Return 1 if we can compute the negated form of the 381/// specified expression for the same cost as the expression itself, or 2 if we 382/// can compute the negated form more cheaply than the expression itself. 383static char isNegatibleForFree(SDValue Op, bool LegalOperations, 384 const TargetLowering &TLI, 385 const TargetOptions *Options, 386 unsigned Depth = 0) { 387 // No compile time optimizations on this type. 388 if (Op.getValueType() == MVT::ppcf128) 389 return 0; 390 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return 2; 393 394 // Don't allow anything with multiple uses. 395 if (!Op.hasOneUse()) return 0; 396 397 // Don't recurse exponentially. 398 if (Depth > 6) return 0; 399 400 switch (Op.getOpcode()) { 401 default: return false; 402 case ISD::ConstantFP: 403 // Don't invert constant FP values after legalize. The negated constant 404 // isn't necessarily legal. 405 return LegalOperations ? 0 : 1; 406 case ISD::FADD: 407 // FIXME: determine better conditions for this xform. 408 if (!Options->UnsafeFPMath) return 0; 409 410 // After operation legalization, it might not be legal to create new FSUBs. 411 if (LegalOperations && 412 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 413 return 0; 414 415 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 416 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 417 Options, Depth + 1)) 418 return V; 419 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 420 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 421 Depth + 1); 422 case ISD::FSUB: 423 // We can't turn -(A-B) into B-A when we honor signed zeros. 424 if (!Options->UnsafeFPMath) return 0; 425 426 // fold (fneg (fsub A, B)) -> (fsub B, A) 427 return 1; 428 429 case ISD::FMUL: 430 case ISD::FDIV: 431 if (Options->HonorSignDependentRoundingFPMath()) return 0; 432 433 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 434 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 435 Options, Depth + 1)) 436 return V; 437 438 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 439 Depth + 1); 440 441 case ISD::FP_EXTEND: 442 case ISD::FP_ROUND: 443 case ISD::FSIN: 444 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 445 Depth + 1); 446 } 447} 448 449/// GetNegatedExpression - If isNegatibleForFree returns true, this function 450/// returns the newly negated expression. 451static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 452 bool LegalOperations, unsigned Depth = 0) { 453 // fneg is removable even if it has multiple uses. 454 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 455 456 // Don't allow anything with multiple uses. 457 assert(Op.hasOneUse() && "Unknown reuse!"); 458 459 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 460 switch (Op.getOpcode()) { 461 default: llvm_unreachable("Unknown code"); 462 case ISD::ConstantFP: { 463 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 464 V.changeSign(); 465 return DAG.getConstantFP(V, Op.getValueType()); 466 } 467 case ISD::FADD: 468 // FIXME: determine better conditions for this xform. 469 assert(DAG.getTarget().Options.UnsafeFPMath); 470 471 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 472 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 473 DAG.getTargetLoweringInfo(), 474 &DAG.getTarget().Options, Depth+1)) 475 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 476 GetNegatedExpression(Op.getOperand(0), DAG, 477 LegalOperations, Depth+1), 478 Op.getOperand(1)); 479 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 480 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 481 GetNegatedExpression(Op.getOperand(1), DAG, 482 LegalOperations, Depth+1), 483 Op.getOperand(0)); 484 case ISD::FSUB: 485 // We can't turn -(A-B) into B-A when we honor signed zeros. 486 assert(DAG.getTarget().Options.UnsafeFPMath); 487 488 // fold (fneg (fsub 0, B)) -> B 489 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 490 if (N0CFP->getValueAPF().isZero()) 491 return Op.getOperand(1); 492 493 // fold (fneg (fsub A, B)) -> (fsub B, A) 494 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 495 Op.getOperand(1), Op.getOperand(0)); 496 497 case ISD::FMUL: 498 case ISD::FDIV: 499 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 500 501 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 502 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 503 DAG.getTargetLoweringInfo(), 504 &DAG.getTarget().Options, Depth+1)) 505 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 506 GetNegatedExpression(Op.getOperand(0), DAG, 507 LegalOperations, Depth+1), 508 Op.getOperand(1)); 509 510 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 511 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 512 Op.getOperand(0), 513 GetNegatedExpression(Op.getOperand(1), DAG, 514 LegalOperations, Depth+1)); 515 516 case ISD::FP_EXTEND: 517 case ISD::FSIN: 518 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 519 GetNegatedExpression(Op.getOperand(0), DAG, 520 LegalOperations, Depth+1)); 521 case ISD::FP_ROUND: 522 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 523 GetNegatedExpression(Op.getOperand(0), DAG, 524 LegalOperations, Depth+1), 525 Op.getOperand(1)); 526 } 527} 528 529 530// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 531// that selects between the values 1 and 0, making it equivalent to a setcc. 532// Also, set the incoming LHS, RHS, and CC references to the appropriate 533// nodes based on the type of node we are checking. This simplifies life a 534// bit for the callers. 535static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 536 SDValue &CC) { 537 if (N.getOpcode() == ISD::SETCC) { 538 LHS = N.getOperand(0); 539 RHS = N.getOperand(1); 540 CC = N.getOperand(2); 541 return true; 542 } 543 if (N.getOpcode() == ISD::SELECT_CC && 544 N.getOperand(2).getOpcode() == ISD::Constant && 545 N.getOperand(3).getOpcode() == ISD::Constant && 546 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 547 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 548 LHS = N.getOperand(0); 549 RHS = N.getOperand(1); 550 CC = N.getOperand(4); 551 return true; 552 } 553 return false; 554} 555 556// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 557// one use. If this is true, it allows the users to invert the operation for 558// free when it is profitable to do so. 559static bool isOneUseSetCC(SDValue N) { 560 SDValue N0, N1, N2; 561 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 562 return true; 563 return false; 564} 565 566SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 567 SDValue N0, SDValue N1) { 568 EVT VT = N0.getValueType(); 569 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 570 if (isa<ConstantSDNode>(N1)) { 571 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 572 SDValue OpNode = 573 DAG.FoldConstantArithmetic(Opc, VT, 574 cast<ConstantSDNode>(N0.getOperand(1)), 575 cast<ConstantSDNode>(N1)); 576 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 577 } 578 if (N0.hasOneUse()) { 579 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 580 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 581 N0.getOperand(0), N1); 582 AddToWorkList(OpNode.getNode()); 583 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 584 } 585 } 586 587 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 588 if (isa<ConstantSDNode>(N0)) { 589 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 590 SDValue OpNode = 591 DAG.FoldConstantArithmetic(Opc, VT, 592 cast<ConstantSDNode>(N1.getOperand(1)), 593 cast<ConstantSDNode>(N0)); 594 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 595 } 596 if (N1.hasOneUse()) { 597 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 598 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 599 N1.getOperand(0), N0); 600 AddToWorkList(OpNode.getNode()); 601 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 602 } 603 } 604 605 return SDValue(); 606} 607 608SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 609 bool AddTo) { 610 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 611 ++NodesCombined; 612 DEBUG(dbgs() << "\nReplacing.1 "; 613 N->dump(&DAG); 614 dbgs() << "\nWith: "; 615 To[0].getNode()->dump(&DAG); 616 dbgs() << " and " << NumTo-1 << " other values\n"; 617 for (unsigned i = 0, e = NumTo; i != e; ++i) 618 assert((!To[i].getNode() || 619 N->getValueType(i) == To[i].getValueType()) && 620 "Cannot combine value to value of different type!")); 621 WorkListRemover DeadNodes(*this); 622 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 623 624 if (AddTo) { 625 // Push the new nodes and any users onto the worklist 626 for (unsigned i = 0, e = NumTo; i != e; ++i) { 627 if (To[i].getNode()) { 628 AddToWorkList(To[i].getNode()); 629 AddUsersToWorkList(To[i].getNode()); 630 } 631 } 632 } 633 634 // Finally, if the node is now dead, remove it from the graph. The node 635 // may not be dead if the replacement process recursively simplified to 636 // something else needing this node. 637 if (N->use_empty()) { 638 // Nodes can be reintroduced into the worklist. Make sure we do not 639 // process a node that has been replaced. 640 removeFromWorkList(N); 641 642 // Finally, since the node is now dead, remove it from the graph. 643 DAG.DeleteNode(N); 644 } 645 return SDValue(N, 0); 646} 647 648void DAGCombiner:: 649CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 650 // Replace all uses. If any nodes become isomorphic to other nodes and 651 // are deleted, make sure to remove them from our worklist. 652 WorkListRemover DeadNodes(*this); 653 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 654 655 // Push the new node and any (possibly new) users onto the worklist. 656 AddToWorkList(TLO.New.getNode()); 657 AddUsersToWorkList(TLO.New.getNode()); 658 659 // Finally, if the node is now dead, remove it from the graph. The node 660 // may not be dead if the replacement process recursively simplified to 661 // something else needing this node. 662 if (TLO.Old.getNode()->use_empty()) { 663 removeFromWorkList(TLO.Old.getNode()); 664 665 // If the operands of this node are only used by the node, they will now 666 // be dead. Make sure to visit them first to delete dead nodes early. 667 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 668 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 669 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 670 671 DAG.DeleteNode(TLO.Old.getNode()); 672 } 673} 674 675/// SimplifyDemandedBits - Check the specified integer node value to see if 676/// it can be simplified or if things it uses can be simplified by bit 677/// propagation. If so, return true. 678bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 679 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 680 APInt KnownZero, KnownOne; 681 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 682 return false; 683 684 // Revisit the node. 685 AddToWorkList(Op.getNode()); 686 687 // Replace the old value with the new one. 688 ++NodesCombined; 689 DEBUG(dbgs() << "\nReplacing.2 "; 690 TLO.Old.getNode()->dump(&DAG); 691 dbgs() << "\nWith: "; 692 TLO.New.getNode()->dump(&DAG); 693 dbgs() << '\n'); 694 695 CommitTargetLoweringOpt(TLO); 696 return true; 697} 698 699void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 700 DebugLoc dl = Load->getDebugLoc(); 701 EVT VT = Load->getValueType(0); 702 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 703 704 DEBUG(dbgs() << "\nReplacing.9 "; 705 Load->dump(&DAG); 706 dbgs() << "\nWith: "; 707 Trunc.getNode()->dump(&DAG); 708 dbgs() << '\n'); 709 WorkListRemover DeadNodes(*this); 710 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 711 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 712 &DeadNodes); 713 removeFromWorkList(Load); 714 DAG.DeleteNode(Load); 715 AddToWorkList(Trunc.getNode()); 716} 717 718SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 719 Replace = false; 720 DebugLoc dl = Op.getDebugLoc(); 721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 722 EVT MemVT = LD->getMemoryVT(); 723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 725 : ISD::EXTLOAD) 726 : LD->getExtensionType(); 727 Replace = true; 728 return DAG.getExtLoad(ExtType, dl, PVT, 729 LD->getChain(), LD->getBasePtr(), 730 LD->getPointerInfo(), 731 MemVT, LD->isVolatile(), 732 LD->isNonTemporal(), LD->getAlignment()); 733 } 734 735 unsigned Opc = Op.getOpcode(); 736 switch (Opc) { 737 default: break; 738 case ISD::AssertSext: 739 return DAG.getNode(ISD::AssertSext, dl, PVT, 740 SExtPromoteOperand(Op.getOperand(0), PVT), 741 Op.getOperand(1)); 742 case ISD::AssertZext: 743 return DAG.getNode(ISD::AssertZext, dl, PVT, 744 ZExtPromoteOperand(Op.getOperand(0), PVT), 745 Op.getOperand(1)); 746 case ISD::Constant: { 747 unsigned ExtOpc = 748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 749 return DAG.getNode(ExtOpc, dl, PVT, Op); 750 } 751 } 752 753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 754 return SDValue(); 755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 756} 757 758SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 760 return SDValue(); 761 EVT OldVT = Op.getValueType(); 762 DebugLoc dl = Op.getDebugLoc(); 763 bool Replace = false; 764 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 765 if (NewOp.getNode() == 0) 766 return SDValue(); 767 AddToWorkList(NewOp.getNode()); 768 769 if (Replace) 770 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 772 DAG.getValueType(OldVT)); 773} 774 775SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 776 EVT OldVT = Op.getValueType(); 777 DebugLoc dl = Op.getDebugLoc(); 778 bool Replace = false; 779 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 780 if (NewOp.getNode() == 0) 781 return SDValue(); 782 AddToWorkList(NewOp.getNode()); 783 784 if (Replace) 785 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 786 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 787} 788 789/// PromoteIntBinOp - Promote the specified integer binary operation if the 790/// target indicates it is beneficial. e.g. On x86, it's usually better to 791/// promote i16 operations to i32 since i16 instructions are longer. 792SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 793 if (!LegalOperations) 794 return SDValue(); 795 796 EVT VT = Op.getValueType(); 797 if (VT.isVector() || !VT.isInteger()) 798 return SDValue(); 799 800 // If operation type is 'undesirable', e.g. i16 on x86, consider 801 // promoting it. 802 unsigned Opc = Op.getOpcode(); 803 if (TLI.isTypeDesirableForOp(Opc, VT)) 804 return SDValue(); 805 806 EVT PVT = VT; 807 // Consult target whether it is a good idea to promote this operation and 808 // what's the right type to promote it to. 809 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 810 assert(PVT != VT && "Don't know what type to promote to!"); 811 812 bool Replace0 = false; 813 SDValue N0 = Op.getOperand(0); 814 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 815 if (NN0.getNode() == 0) 816 return SDValue(); 817 818 bool Replace1 = false; 819 SDValue N1 = Op.getOperand(1); 820 SDValue NN1; 821 if (N0 == N1) 822 NN1 = NN0; 823 else { 824 NN1 = PromoteOperand(N1, PVT, Replace1); 825 if (NN1.getNode() == 0) 826 return SDValue(); 827 } 828 829 AddToWorkList(NN0.getNode()); 830 if (NN1.getNode()) 831 AddToWorkList(NN1.getNode()); 832 833 if (Replace0) 834 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 835 if (Replace1) 836 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 837 838 DEBUG(dbgs() << "\nPromoting "; 839 Op.getNode()->dump(&DAG)); 840 DebugLoc dl = Op.getDebugLoc(); 841 return DAG.getNode(ISD::TRUNCATE, dl, VT, 842 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 843 } 844 return SDValue(); 845} 846 847/// PromoteIntShiftOp - Promote the specified integer shift operation if the 848/// target indicates it is beneficial. e.g. On x86, it's usually better to 849/// promote i16 operations to i32 since i16 instructions are longer. 850SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 851 if (!LegalOperations) 852 return SDValue(); 853 854 EVT VT = Op.getValueType(); 855 if (VT.isVector() || !VT.isInteger()) 856 return SDValue(); 857 858 // If operation type is 'undesirable', e.g. i16 on x86, consider 859 // promoting it. 860 unsigned Opc = Op.getOpcode(); 861 if (TLI.isTypeDesirableForOp(Opc, VT)) 862 return SDValue(); 863 864 EVT PVT = VT; 865 // Consult target whether it is a good idea to promote this operation and 866 // what's the right type to promote it to. 867 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 868 assert(PVT != VT && "Don't know what type to promote to!"); 869 870 bool Replace = false; 871 SDValue N0 = Op.getOperand(0); 872 if (Opc == ISD::SRA) 873 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 874 else if (Opc == ISD::SRL) 875 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 876 else 877 N0 = PromoteOperand(N0, PVT, Replace); 878 if (N0.getNode() == 0) 879 return SDValue(); 880 881 AddToWorkList(N0.getNode()); 882 if (Replace) 883 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 884 885 DEBUG(dbgs() << "\nPromoting "; 886 Op.getNode()->dump(&DAG)); 887 DebugLoc dl = Op.getDebugLoc(); 888 return DAG.getNode(ISD::TRUNCATE, dl, VT, 889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 890 } 891 return SDValue(); 892} 893 894SDValue DAGCombiner::PromoteExtend(SDValue Op) { 895 if (!LegalOperations) 896 return SDValue(); 897 898 EVT VT = Op.getValueType(); 899 if (VT.isVector() || !VT.isInteger()) 900 return SDValue(); 901 902 // If operation type is 'undesirable', e.g. i16 on x86, consider 903 // promoting it. 904 unsigned Opc = Op.getOpcode(); 905 if (TLI.isTypeDesirableForOp(Opc, VT)) 906 return SDValue(); 907 908 EVT PVT = VT; 909 // Consult target whether it is a good idea to promote this operation and 910 // what's the right type to promote it to. 911 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 912 assert(PVT != VT && "Don't know what type to promote to!"); 913 // fold (aext (aext x)) -> (aext x) 914 // fold (aext (zext x)) -> (zext x) 915 // fold (aext (sext x)) -> (sext x) 916 DEBUG(dbgs() << "\nPromoting "; 917 Op.getNode()->dump(&DAG)); 918 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 919 } 920 return SDValue(); 921} 922 923bool DAGCombiner::PromoteLoad(SDValue Op) { 924 if (!LegalOperations) 925 return false; 926 927 EVT VT = Op.getValueType(); 928 if (VT.isVector() || !VT.isInteger()) 929 return false; 930 931 // If operation type is 'undesirable', e.g. i16 on x86, consider 932 // promoting it. 933 unsigned Opc = Op.getOpcode(); 934 if (TLI.isTypeDesirableForOp(Opc, VT)) 935 return false; 936 937 EVT PVT = VT; 938 // Consult target whether it is a good idea to promote this operation and 939 // what's the right type to promote it to. 940 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 941 assert(PVT != VT && "Don't know what type to promote to!"); 942 943 DebugLoc dl = Op.getDebugLoc(); 944 SDNode *N = Op.getNode(); 945 LoadSDNode *LD = cast<LoadSDNode>(N); 946 EVT MemVT = LD->getMemoryVT(); 947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 949 : ISD::EXTLOAD) 950 : LD->getExtensionType(); 951 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 952 LD->getChain(), LD->getBasePtr(), 953 LD->getPointerInfo(), 954 MemVT, LD->isVolatile(), 955 LD->isNonTemporal(), LD->getAlignment()); 956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 957 958 DEBUG(dbgs() << "\nPromoting "; 959 N->dump(&DAG); 960 dbgs() << "\nTo: "; 961 Result.getNode()->dump(&DAG); 962 dbgs() << '\n'); 963 WorkListRemover DeadNodes(*this); 964 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 965 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 966 removeFromWorkList(N); 967 DAG.DeleteNode(N); 968 AddToWorkList(Result.getNode()); 969 return true; 970 } 971 return false; 972} 973 974 975//===----------------------------------------------------------------------===// 976// Main DAG Combiner implementation 977//===----------------------------------------------------------------------===// 978 979void DAGCombiner::Run(CombineLevel AtLevel) { 980 // set the instance variables, so that the various visit routines may use it. 981 Level = AtLevel; 982 LegalOperations = Level >= AfterLegalizeVectorOps; 983 LegalTypes = Level >= AfterLegalizeTypes; 984 985 // Add all the dag nodes to the worklist. 986 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 987 E = DAG.allnodes_end(); I != E; ++I) 988 AddToWorkList(I); 989 990 // Create a dummy node (which is not added to allnodes), that adds a reference 991 // to the root node, preventing it from being deleted, and tracking any 992 // changes of the root. 993 HandleSDNode Dummy(DAG.getRoot()); 994 995 // The root of the dag may dangle to deleted nodes until the dag combiner is 996 // done. Set it to null to avoid confusion. 997 DAG.setRoot(SDValue()); 998 999 // while the worklist isn't empty, find a node and 1000 // try and combine it. 1001 while (!WorkListContents.empty()) { 1002 SDNode *N; 1003 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1004 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1005 // worklist *should* contain, and check the node we want to visit is should 1006 // actually be visited. 1007 do { 1008 N = WorkListOrder.back(); 1009 WorkListOrder.pop_back(); 1010 } while (!WorkListContents.erase(N)); 1011 1012 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1013 // N is deleted from the DAG, since they too may now be dead or may have a 1014 // reduced number of uses, allowing other xforms. 1015 if (N->use_empty() && N != &Dummy) { 1016 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1017 AddToWorkList(N->getOperand(i).getNode()); 1018 1019 DAG.DeleteNode(N); 1020 continue; 1021 } 1022 1023 SDValue RV = combine(N); 1024 1025 if (RV.getNode() == 0) 1026 continue; 1027 1028 ++NodesCombined; 1029 1030 // If we get back the same node we passed in, rather than a new node or 1031 // zero, we know that the node must have defined multiple values and 1032 // CombineTo was used. Since CombineTo takes care of the worklist 1033 // mechanics for us, we have no work to do in this case. 1034 if (RV.getNode() == N) 1035 continue; 1036 1037 assert(N->getOpcode() != ISD::DELETED_NODE && 1038 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1039 "Node was deleted but visit returned new node!"); 1040 1041 DEBUG(dbgs() << "\nReplacing.3 "; 1042 N->dump(&DAG); 1043 dbgs() << "\nWith: "; 1044 RV.getNode()->dump(&DAG); 1045 dbgs() << '\n'); 1046 1047 // Transfer debug value. 1048 DAG.TransferDbgValues(SDValue(N, 0), RV); 1049 WorkListRemover DeadNodes(*this); 1050 if (N->getNumValues() == RV.getNode()->getNumValues()) 1051 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 1052 else { 1053 assert(N->getValueType(0) == RV.getValueType() && 1054 N->getNumValues() == 1 && "Type mismatch"); 1055 SDValue OpV = RV; 1056 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1057 } 1058 1059 // Push the new node and any users onto the worklist 1060 AddToWorkList(RV.getNode()); 1061 AddUsersToWorkList(RV.getNode()); 1062 1063 // Add any uses of the old node to the worklist in case this node is the 1064 // last one that uses them. They may become dead after this node is 1065 // deleted. 1066 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1067 AddToWorkList(N->getOperand(i).getNode()); 1068 1069 // Finally, if the node is now dead, remove it from the graph. The node 1070 // may not be dead if the replacement process recursively simplified to 1071 // something else needing this node. 1072 if (N->use_empty()) { 1073 // Nodes can be reintroduced into the worklist. Make sure we do not 1074 // process a node that has been replaced. 1075 removeFromWorkList(N); 1076 1077 // Finally, since the node is now dead, remove it from the graph. 1078 DAG.DeleteNode(N); 1079 } 1080 } 1081 1082 // If the root changed (e.g. it was a dead load, update the root). 1083 DAG.setRoot(Dummy.getValue()); 1084} 1085 1086SDValue DAGCombiner::visit(SDNode *N) { 1087 switch (N->getOpcode()) { 1088 default: break; 1089 case ISD::TokenFactor: return visitTokenFactor(N); 1090 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1091 case ISD::ADD: return visitADD(N); 1092 case ISD::SUB: return visitSUB(N); 1093 case ISD::ADDC: return visitADDC(N); 1094 case ISD::SUBC: return visitSUBC(N); 1095 case ISD::ADDE: return visitADDE(N); 1096 case ISD::SUBE: return visitSUBE(N); 1097 case ISD::MUL: return visitMUL(N); 1098 case ISD::SDIV: return visitSDIV(N); 1099 case ISD::UDIV: return visitUDIV(N); 1100 case ISD::SREM: return visitSREM(N); 1101 case ISD::UREM: return visitUREM(N); 1102 case ISD::MULHU: return visitMULHU(N); 1103 case ISD::MULHS: return visitMULHS(N); 1104 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1105 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1106 case ISD::SMULO: return visitSMULO(N); 1107 case ISD::UMULO: return visitUMULO(N); 1108 case ISD::SDIVREM: return visitSDIVREM(N); 1109 case ISD::UDIVREM: return visitUDIVREM(N); 1110 case ISD::AND: return visitAND(N); 1111 case ISD::OR: return visitOR(N); 1112 case ISD::XOR: return visitXOR(N); 1113 case ISD::SHL: return visitSHL(N); 1114 case ISD::SRA: return visitSRA(N); 1115 case ISD::SRL: return visitSRL(N); 1116 case ISD::CTLZ: return visitCTLZ(N); 1117 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1118 case ISD::CTTZ: return visitCTTZ(N); 1119 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1120 case ISD::CTPOP: return visitCTPOP(N); 1121 case ISD::SELECT: return visitSELECT(N); 1122 case ISD::SELECT_CC: return visitSELECT_CC(N); 1123 case ISD::SETCC: return visitSETCC(N); 1124 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1125 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1126 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1127 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1128 case ISD::TRUNCATE: return visitTRUNCATE(N); 1129 case ISD::BITCAST: return visitBITCAST(N); 1130 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1131 case ISD::FADD: return visitFADD(N); 1132 case ISD::FSUB: return visitFSUB(N); 1133 case ISD::FMUL: return visitFMUL(N); 1134 case ISD::FDIV: return visitFDIV(N); 1135 case ISD::FREM: return visitFREM(N); 1136 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1137 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1138 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1139 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1140 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1141 case ISD::FP_ROUND: return visitFP_ROUND(N); 1142 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1143 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1144 case ISD::FNEG: return visitFNEG(N); 1145 case ISD::FABS: return visitFABS(N); 1146 case ISD::BRCOND: return visitBRCOND(N); 1147 case ISD::BR_CC: return visitBR_CC(N); 1148 case ISD::LOAD: return visitLOAD(N); 1149 case ISD::STORE: return visitSTORE(N); 1150 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1151 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1152 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1153 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1154 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1155 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1156 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1157 } 1158 return SDValue(); 1159} 1160 1161SDValue DAGCombiner::combine(SDNode *N) { 1162 SDValue RV = visit(N); 1163 1164 // If nothing happened, try a target-specific DAG combine. 1165 if (RV.getNode() == 0) { 1166 assert(N->getOpcode() != ISD::DELETED_NODE && 1167 "Node was deleted but visit returned NULL!"); 1168 1169 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1170 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1171 1172 // Expose the DAG combiner to the target combiner impls. 1173 TargetLowering::DAGCombinerInfo 1174 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1175 1176 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1177 } 1178 } 1179 1180 // If nothing happened still, try promoting the operation. 1181 if (RV.getNode() == 0) { 1182 switch (N->getOpcode()) { 1183 default: break; 1184 case ISD::ADD: 1185 case ISD::SUB: 1186 case ISD::MUL: 1187 case ISD::AND: 1188 case ISD::OR: 1189 case ISD::XOR: 1190 RV = PromoteIntBinOp(SDValue(N, 0)); 1191 break; 1192 case ISD::SHL: 1193 case ISD::SRA: 1194 case ISD::SRL: 1195 RV = PromoteIntShiftOp(SDValue(N, 0)); 1196 break; 1197 case ISD::SIGN_EXTEND: 1198 case ISD::ZERO_EXTEND: 1199 case ISD::ANY_EXTEND: 1200 RV = PromoteExtend(SDValue(N, 0)); 1201 break; 1202 case ISD::LOAD: 1203 if (PromoteLoad(SDValue(N, 0))) 1204 RV = SDValue(N, 0); 1205 break; 1206 } 1207 } 1208 1209 // If N is a commutative binary node, try commuting it to enable more 1210 // sdisel CSE. 1211 if (RV.getNode() == 0 && 1212 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1213 N->getNumValues() == 1) { 1214 SDValue N0 = N->getOperand(0); 1215 SDValue N1 = N->getOperand(1); 1216 1217 // Constant operands are canonicalized to RHS. 1218 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1219 SDValue Ops[] = { N1, N0 }; 1220 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1221 Ops, 2); 1222 if (CSENode) 1223 return SDValue(CSENode, 0); 1224 } 1225 } 1226 1227 return RV; 1228} 1229 1230/// getInputChainForNode - Given a node, return its input chain if it has one, 1231/// otherwise return a null sd operand. 1232static SDValue getInputChainForNode(SDNode *N) { 1233 if (unsigned NumOps = N->getNumOperands()) { 1234 if (N->getOperand(0).getValueType() == MVT::Other) 1235 return N->getOperand(0); 1236 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1237 return N->getOperand(NumOps-1); 1238 for (unsigned i = 1; i < NumOps-1; ++i) 1239 if (N->getOperand(i).getValueType() == MVT::Other) 1240 return N->getOperand(i); 1241 } 1242 return SDValue(); 1243} 1244 1245SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1246 // If N has two operands, where one has an input chain equal to the other, 1247 // the 'other' chain is redundant. 1248 if (N->getNumOperands() == 2) { 1249 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1250 return N->getOperand(0); 1251 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1252 return N->getOperand(1); 1253 } 1254 1255 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1256 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1257 SmallPtrSet<SDNode*, 16> SeenOps; 1258 bool Changed = false; // If we should replace this token factor. 1259 1260 // Start out with this token factor. 1261 TFs.push_back(N); 1262 1263 // Iterate through token factors. The TFs grows when new token factors are 1264 // encountered. 1265 for (unsigned i = 0; i < TFs.size(); ++i) { 1266 SDNode *TF = TFs[i]; 1267 1268 // Check each of the operands. 1269 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1270 SDValue Op = TF->getOperand(i); 1271 1272 switch (Op.getOpcode()) { 1273 case ISD::EntryToken: 1274 // Entry tokens don't need to be added to the list. They are 1275 // rededundant. 1276 Changed = true; 1277 break; 1278 1279 case ISD::TokenFactor: 1280 if (Op.hasOneUse() && 1281 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1282 // Queue up for processing. 1283 TFs.push_back(Op.getNode()); 1284 // Clean up in case the token factor is removed. 1285 AddToWorkList(Op.getNode()); 1286 Changed = true; 1287 break; 1288 } 1289 // Fall thru 1290 1291 default: 1292 // Only add if it isn't already in the list. 1293 if (SeenOps.insert(Op.getNode())) 1294 Ops.push_back(Op); 1295 else 1296 Changed = true; 1297 break; 1298 } 1299 } 1300 } 1301 1302 SDValue Result; 1303 1304 // If we've change things around then replace token factor. 1305 if (Changed) { 1306 if (Ops.empty()) { 1307 // The entry token is the only possible outcome. 1308 Result = DAG.getEntryNode(); 1309 } else { 1310 // New and improved token factor. 1311 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1312 MVT::Other, &Ops[0], Ops.size()); 1313 } 1314 1315 // Don't add users to work list. 1316 return CombineTo(N, Result, false); 1317 } 1318 1319 return Result; 1320} 1321 1322/// MERGE_VALUES can always be eliminated. 1323SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1324 WorkListRemover DeadNodes(*this); 1325 // Replacing results may cause a different MERGE_VALUES to suddenly 1326 // be CSE'd with N, and carry its uses with it. Iterate until no 1327 // uses remain, to ensure that the node can be safely deleted. 1328 do { 1329 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1330 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1331 &DeadNodes); 1332 } while (!N->use_empty()); 1333 removeFromWorkList(N); 1334 DAG.DeleteNode(N); 1335 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1336} 1337 1338static 1339SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1340 SelectionDAG &DAG) { 1341 EVT VT = N0.getValueType(); 1342 SDValue N00 = N0.getOperand(0); 1343 SDValue N01 = N0.getOperand(1); 1344 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1345 1346 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1347 isa<ConstantSDNode>(N00.getOperand(1))) { 1348 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1349 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1350 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1351 N00.getOperand(0), N01), 1352 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1353 N00.getOperand(1), N01)); 1354 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1355 } 1356 1357 return SDValue(); 1358} 1359 1360SDValue DAGCombiner::visitADD(SDNode *N) { 1361 SDValue N0 = N->getOperand(0); 1362 SDValue N1 = N->getOperand(1); 1363 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1364 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1365 EVT VT = N0.getValueType(); 1366 1367 // fold vector ops 1368 if (VT.isVector()) { 1369 SDValue FoldedVOp = SimplifyVBinOp(N); 1370 if (FoldedVOp.getNode()) return FoldedVOp; 1371 } 1372 1373 // fold (add x, undef) -> undef 1374 if (N0.getOpcode() == ISD::UNDEF) 1375 return N0; 1376 if (N1.getOpcode() == ISD::UNDEF) 1377 return N1; 1378 // fold (add c1, c2) -> c1+c2 1379 if (N0C && N1C) 1380 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1381 // canonicalize constant to RHS 1382 if (N0C && !N1C) 1383 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1384 // fold (add x, 0) -> x 1385 if (N1C && N1C->isNullValue()) 1386 return N0; 1387 // fold (add Sym, c) -> Sym+c 1388 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1389 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1390 GA->getOpcode() == ISD::GlobalAddress) 1391 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1392 GA->getOffset() + 1393 (uint64_t)N1C->getSExtValue()); 1394 // fold ((c1-A)+c2) -> (c1+c2)-A 1395 if (N1C && N0.getOpcode() == ISD::SUB) 1396 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1397 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1398 DAG.getConstant(N1C->getAPIntValue()+ 1399 N0C->getAPIntValue(), VT), 1400 N0.getOperand(1)); 1401 // reassociate add 1402 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1403 if (RADD.getNode() != 0) 1404 return RADD; 1405 // fold ((0-A) + B) -> B-A 1406 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1407 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1408 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1409 // fold (A + (0-B)) -> A-B 1410 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1411 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1412 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1413 // fold (A+(B-A)) -> B 1414 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1415 return N1.getOperand(0); 1416 // fold ((B-A)+A) -> B 1417 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1418 return N0.getOperand(0); 1419 // fold (A+(B-(A+C))) to (B-C) 1420 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1421 N0 == N1.getOperand(1).getOperand(0)) 1422 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1423 N1.getOperand(1).getOperand(1)); 1424 // fold (A+(B-(C+A))) to (B-C) 1425 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1426 N0 == N1.getOperand(1).getOperand(1)) 1427 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1428 N1.getOperand(1).getOperand(0)); 1429 // fold (A+((B-A)+or-C)) to (B+or-C) 1430 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1431 N1.getOperand(0).getOpcode() == ISD::SUB && 1432 N0 == N1.getOperand(0).getOperand(1)) 1433 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1434 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1435 1436 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1437 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1438 SDValue N00 = N0.getOperand(0); 1439 SDValue N01 = N0.getOperand(1); 1440 SDValue N10 = N1.getOperand(0); 1441 SDValue N11 = N1.getOperand(1); 1442 1443 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1444 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1445 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1446 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1447 } 1448 1449 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1450 return SDValue(N, 0); 1451 1452 // fold (a+b) -> (a|b) iff a and b share no bits. 1453 if (VT.isInteger() && !VT.isVector()) { 1454 APInt LHSZero, LHSOne; 1455 APInt RHSZero, RHSOne; 1456 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1457 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1458 1459 if (LHSZero.getBoolValue()) { 1460 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1461 1462 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1463 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1464 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1465 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1466 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1467 } 1468 } 1469 1470 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1471 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1472 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1473 if (Result.getNode()) return Result; 1474 } 1475 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1476 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1477 if (Result.getNode()) return Result; 1478 } 1479 1480 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1481 if (N1.getOpcode() == ISD::SHL && 1482 N1.getOperand(0).getOpcode() == ISD::SUB) 1483 if (ConstantSDNode *C = 1484 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1485 if (C->getAPIntValue() == 0) 1486 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1487 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1488 N1.getOperand(0).getOperand(1), 1489 N1.getOperand(1))); 1490 if (N0.getOpcode() == ISD::SHL && 1491 N0.getOperand(0).getOpcode() == ISD::SUB) 1492 if (ConstantSDNode *C = 1493 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1494 if (C->getAPIntValue() == 0) 1495 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1496 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1497 N0.getOperand(0).getOperand(1), 1498 N0.getOperand(1))); 1499 1500 if (N1.getOpcode() == ISD::AND) { 1501 SDValue AndOp0 = N1.getOperand(0); 1502 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1503 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1504 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1505 1506 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1507 // and similar xforms where the inner op is either ~0 or 0. 1508 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1509 DebugLoc DL = N->getDebugLoc(); 1510 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1511 } 1512 } 1513 1514 // add (sext i1), X -> sub X, (zext i1) 1515 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1516 N0.getOperand(0).getValueType() == MVT::i1 && 1517 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1518 DebugLoc DL = N->getDebugLoc(); 1519 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1520 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1521 } 1522 1523 return SDValue(); 1524} 1525 1526SDValue DAGCombiner::visitADDC(SDNode *N) { 1527 SDValue N0 = N->getOperand(0); 1528 SDValue N1 = N->getOperand(1); 1529 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1531 EVT VT = N0.getValueType(); 1532 1533 // If the flag result is dead, turn this into an ADD. 1534 if (!N->hasAnyUseOfValue(1)) 1535 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1536 DAG.getNode(ISD::CARRY_FALSE, 1537 N->getDebugLoc(), MVT::Glue)); 1538 1539 // canonicalize constant to RHS. 1540 if (N0C && !N1C) 1541 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1542 1543 // fold (addc x, 0) -> x + no carry out 1544 if (N1C && N1C->isNullValue()) 1545 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1546 N->getDebugLoc(), MVT::Glue)); 1547 1548 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1549 APInt LHSZero, LHSOne; 1550 APInt RHSZero, RHSOne; 1551 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1552 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1553 1554 if (LHSZero.getBoolValue()) { 1555 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1556 1557 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1558 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1559 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1560 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1561 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1562 DAG.getNode(ISD::CARRY_FALSE, 1563 N->getDebugLoc(), MVT::Glue)); 1564 } 1565 1566 return SDValue(); 1567} 1568 1569SDValue DAGCombiner::visitADDE(SDNode *N) { 1570 SDValue N0 = N->getOperand(0); 1571 SDValue N1 = N->getOperand(1); 1572 SDValue CarryIn = N->getOperand(2); 1573 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1574 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1575 1576 // canonicalize constant to RHS 1577 if (N0C && !N1C) 1578 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1579 N1, N0, CarryIn); 1580 1581 // fold (adde x, y, false) -> (addc x, y) 1582 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1583 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1584 1585 return SDValue(); 1586} 1587 1588// Since it may not be valid to emit a fold to zero for vector initializers 1589// check if we can before folding. 1590static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1591 SelectionDAG &DAG, bool LegalOperations) { 1592 if (!VT.isVector()) { 1593 return DAG.getConstant(0, VT); 1594 } 1595 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1596 // Produce a vector of zeros. 1597 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1598 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1599 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1600 &Ops[0], Ops.size()); 1601 } 1602 return SDValue(); 1603} 1604 1605SDValue DAGCombiner::visitSUB(SDNode *N) { 1606 SDValue N0 = N->getOperand(0); 1607 SDValue N1 = N->getOperand(1); 1608 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1609 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1610 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1611 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1612 EVT VT = N0.getValueType(); 1613 1614 // fold vector ops 1615 if (VT.isVector()) { 1616 SDValue FoldedVOp = SimplifyVBinOp(N); 1617 if (FoldedVOp.getNode()) return FoldedVOp; 1618 } 1619 1620 // fold (sub x, x) -> 0 1621 // FIXME: Refactor this and xor and other similar operations together. 1622 if (N0 == N1) 1623 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1624 // fold (sub c1, c2) -> c1-c2 1625 if (N0C && N1C) 1626 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1627 // fold (sub x, c) -> (add x, -c) 1628 if (N1C) 1629 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1630 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1631 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1632 if (N0C && N0C->isAllOnesValue()) 1633 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1634 // fold A-(A-B) -> B 1635 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1636 return N1.getOperand(1); 1637 // fold (A+B)-A -> B 1638 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1639 return N0.getOperand(1); 1640 // fold (A+B)-B -> A 1641 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1642 return N0.getOperand(0); 1643 // fold C2-(A+C1) -> (C2-C1)-A 1644 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1645 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT); 1646 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1647 N1.getOperand(0)); 1648 } 1649 // fold ((A+(B+or-C))-B) -> A+or-C 1650 if (N0.getOpcode() == ISD::ADD && 1651 (N0.getOperand(1).getOpcode() == ISD::SUB || 1652 N0.getOperand(1).getOpcode() == ISD::ADD) && 1653 N0.getOperand(1).getOperand(0) == N1) 1654 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1655 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1656 // fold ((A+(C+B))-B) -> A+C 1657 if (N0.getOpcode() == ISD::ADD && 1658 N0.getOperand(1).getOpcode() == ISD::ADD && 1659 N0.getOperand(1).getOperand(1) == N1) 1660 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1661 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1662 // fold ((A-(B-C))-C) -> A-B 1663 if (N0.getOpcode() == ISD::SUB && 1664 N0.getOperand(1).getOpcode() == ISD::SUB && 1665 N0.getOperand(1).getOperand(1) == N1) 1666 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1667 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1668 1669 // If either operand of a sub is undef, the result is undef 1670 if (N0.getOpcode() == ISD::UNDEF) 1671 return N0; 1672 if (N1.getOpcode() == ISD::UNDEF) 1673 return N1; 1674 1675 // If the relocation model supports it, consider symbol offsets. 1676 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1677 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1678 // fold (sub Sym, c) -> Sym-c 1679 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1680 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1681 GA->getOffset() - 1682 (uint64_t)N1C->getSExtValue()); 1683 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1684 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1685 if (GA->getGlobal() == GB->getGlobal()) 1686 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1687 VT); 1688 } 1689 1690 return SDValue(); 1691} 1692 1693SDValue DAGCombiner::visitSUBC(SDNode *N) { 1694 SDValue N0 = N->getOperand(0); 1695 SDValue N1 = N->getOperand(1); 1696 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1697 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1698 EVT VT = N0.getValueType(); 1699 1700 // If the flag result is dead, turn this into an SUB. 1701 if (!N->hasAnyUseOfValue(1)) 1702 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1703 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1704 MVT::Glue)); 1705 1706 // fold (subc x, x) -> 0 + no borrow 1707 if (N0 == N1) 1708 return CombineTo(N, DAG.getConstant(0, VT), 1709 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1710 MVT::Glue)); 1711 1712 // fold (subc x, 0) -> x + no borrow 1713 if (N1C && N1C->isNullValue()) 1714 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1715 MVT::Glue)); 1716 1717 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1718 if (N0C && N0C->isAllOnesValue()) 1719 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1720 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1721 MVT::Glue)); 1722 1723 return SDValue(); 1724} 1725 1726SDValue DAGCombiner::visitSUBE(SDNode *N) { 1727 SDValue N0 = N->getOperand(0); 1728 SDValue N1 = N->getOperand(1); 1729 SDValue CarryIn = N->getOperand(2); 1730 1731 // fold (sube x, y, false) -> (subc x, y) 1732 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1733 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1734 1735 return SDValue(); 1736} 1737 1738SDValue DAGCombiner::visitMUL(SDNode *N) { 1739 SDValue N0 = N->getOperand(0); 1740 SDValue N1 = N->getOperand(1); 1741 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1742 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1743 EVT VT = N0.getValueType(); 1744 1745 // fold vector ops 1746 if (VT.isVector()) { 1747 SDValue FoldedVOp = SimplifyVBinOp(N); 1748 if (FoldedVOp.getNode()) return FoldedVOp; 1749 } 1750 1751 // fold (mul x, undef) -> 0 1752 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1753 return DAG.getConstant(0, VT); 1754 // fold (mul c1, c2) -> c1*c2 1755 if (N0C && N1C) 1756 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1757 // canonicalize constant to RHS 1758 if (N0C && !N1C) 1759 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1760 // fold (mul x, 0) -> 0 1761 if (N1C && N1C->isNullValue()) 1762 return N1; 1763 // fold (mul x, -1) -> 0-x 1764 if (N1C && N1C->isAllOnesValue()) 1765 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1766 DAG.getConstant(0, VT), N0); 1767 // fold (mul x, (1 << c)) -> x << c 1768 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1769 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1770 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1771 getShiftAmountTy(N0.getValueType()))); 1772 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1773 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1774 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1775 // FIXME: If the input is something that is easily negated (e.g. a 1776 // single-use add), we should put the negate there. 1777 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1778 DAG.getConstant(0, VT), 1779 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1780 DAG.getConstant(Log2Val, 1781 getShiftAmountTy(N0.getValueType())))); 1782 } 1783 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1784 if (N1C && N0.getOpcode() == ISD::SHL && 1785 isa<ConstantSDNode>(N0.getOperand(1))) { 1786 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1787 N1, N0.getOperand(1)); 1788 AddToWorkList(C3.getNode()); 1789 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1790 N0.getOperand(0), C3); 1791 } 1792 1793 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1794 // use. 1795 { 1796 SDValue Sh(0,0), Y(0,0); 1797 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1798 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1799 N0.getNode()->hasOneUse()) { 1800 Sh = N0; Y = N1; 1801 } else if (N1.getOpcode() == ISD::SHL && 1802 isa<ConstantSDNode>(N1.getOperand(1)) && 1803 N1.getNode()->hasOneUse()) { 1804 Sh = N1; Y = N0; 1805 } 1806 1807 if (Sh.getNode()) { 1808 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1809 Sh.getOperand(0), Y); 1810 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1811 Mul, Sh.getOperand(1)); 1812 } 1813 } 1814 1815 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1816 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1817 isa<ConstantSDNode>(N0.getOperand(1))) 1818 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1819 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1820 N0.getOperand(0), N1), 1821 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1822 N0.getOperand(1), N1)); 1823 1824 // reassociate mul 1825 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1826 if (RMUL.getNode() != 0) 1827 return RMUL; 1828 1829 return SDValue(); 1830} 1831 1832SDValue DAGCombiner::visitSDIV(SDNode *N) { 1833 SDValue N0 = N->getOperand(0); 1834 SDValue N1 = N->getOperand(1); 1835 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1836 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1837 EVT VT = N->getValueType(0); 1838 1839 // fold vector ops 1840 if (VT.isVector()) { 1841 SDValue FoldedVOp = SimplifyVBinOp(N); 1842 if (FoldedVOp.getNode()) return FoldedVOp; 1843 } 1844 1845 // fold (sdiv c1, c2) -> c1/c2 1846 if (N0C && N1C && !N1C->isNullValue()) 1847 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1848 // fold (sdiv X, 1) -> X 1849 if (N1C && N1C->getAPIntValue() == 1LL) 1850 return N0; 1851 // fold (sdiv X, -1) -> 0-X 1852 if (N1C && N1C->isAllOnesValue()) 1853 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1854 DAG.getConstant(0, VT), N0); 1855 // If we know the sign bits of both operands are zero, strength reduce to a 1856 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1857 if (!VT.isVector()) { 1858 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1859 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1860 N0, N1); 1861 } 1862 // fold (sdiv X, pow2) -> simple ops after legalize 1863 if (N1C && !N1C->isNullValue() && 1864 (N1C->getAPIntValue().isPowerOf2() || 1865 (-N1C->getAPIntValue()).isPowerOf2())) { 1866 // If dividing by powers of two is cheap, then don't perform the following 1867 // fold. 1868 if (TLI.isPow2DivCheap()) 1869 return SDValue(); 1870 1871 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1872 1873 // Splat the sign bit into the register 1874 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1875 DAG.getConstant(VT.getSizeInBits()-1, 1876 getShiftAmountTy(N0.getValueType()))); 1877 AddToWorkList(SGN.getNode()); 1878 1879 // Add (N0 < 0) ? abs2 - 1 : 0; 1880 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1881 DAG.getConstant(VT.getSizeInBits() - lg2, 1882 getShiftAmountTy(SGN.getValueType()))); 1883 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1884 AddToWorkList(SRL.getNode()); 1885 AddToWorkList(ADD.getNode()); // Divide by pow2 1886 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1887 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1888 1889 // If we're dividing by a positive value, we're done. Otherwise, we must 1890 // negate the result. 1891 if (N1C->getAPIntValue().isNonNegative()) 1892 return SRA; 1893 1894 AddToWorkList(SRA.getNode()); 1895 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1896 DAG.getConstant(0, VT), SRA); 1897 } 1898 1899 // if integer divide is expensive and we satisfy the requirements, emit an 1900 // alternate sequence. 1901 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1902 SDValue Op = BuildSDIV(N); 1903 if (Op.getNode()) return Op; 1904 } 1905 1906 // undef / X -> 0 1907 if (N0.getOpcode() == ISD::UNDEF) 1908 return DAG.getConstant(0, VT); 1909 // X / undef -> undef 1910 if (N1.getOpcode() == ISD::UNDEF) 1911 return N1; 1912 1913 return SDValue(); 1914} 1915 1916SDValue DAGCombiner::visitUDIV(SDNode *N) { 1917 SDValue N0 = N->getOperand(0); 1918 SDValue N1 = N->getOperand(1); 1919 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1920 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1921 EVT VT = N->getValueType(0); 1922 1923 // fold vector ops 1924 if (VT.isVector()) { 1925 SDValue FoldedVOp = SimplifyVBinOp(N); 1926 if (FoldedVOp.getNode()) return FoldedVOp; 1927 } 1928 1929 // fold (udiv c1, c2) -> c1/c2 1930 if (N0C && N1C && !N1C->isNullValue()) 1931 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1932 // fold (udiv x, (1 << c)) -> x >>u c 1933 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1934 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1935 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1936 getShiftAmountTy(N0.getValueType()))); 1937 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1938 if (N1.getOpcode() == ISD::SHL) { 1939 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1940 if (SHC->getAPIntValue().isPowerOf2()) { 1941 EVT ADDVT = N1.getOperand(1).getValueType(); 1942 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1943 N1.getOperand(1), 1944 DAG.getConstant(SHC->getAPIntValue() 1945 .logBase2(), 1946 ADDVT)); 1947 AddToWorkList(Add.getNode()); 1948 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1949 } 1950 } 1951 } 1952 // fold (udiv x, c) -> alternate 1953 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1954 SDValue Op = BuildUDIV(N); 1955 if (Op.getNode()) return Op; 1956 } 1957 1958 // undef / X -> 0 1959 if (N0.getOpcode() == ISD::UNDEF) 1960 return DAG.getConstant(0, VT); 1961 // X / undef -> undef 1962 if (N1.getOpcode() == ISD::UNDEF) 1963 return N1; 1964 1965 return SDValue(); 1966} 1967 1968SDValue DAGCombiner::visitSREM(SDNode *N) { 1969 SDValue N0 = N->getOperand(0); 1970 SDValue N1 = N->getOperand(1); 1971 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1972 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1973 EVT VT = N->getValueType(0); 1974 1975 // fold (srem c1, c2) -> c1%c2 1976 if (N0C && N1C && !N1C->isNullValue()) 1977 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1978 // If we know the sign bits of both operands are zero, strength reduce to a 1979 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1980 if (!VT.isVector()) { 1981 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1982 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1983 } 1984 1985 // If X/C can be simplified by the division-by-constant logic, lower 1986 // X%C to the equivalent of X-X/C*C. 1987 if (N1C && !N1C->isNullValue()) { 1988 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1989 AddToWorkList(Div.getNode()); 1990 SDValue OptimizedDiv = combine(Div.getNode()); 1991 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1992 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1993 OptimizedDiv, N1); 1994 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1995 AddToWorkList(Mul.getNode()); 1996 return Sub; 1997 } 1998 } 1999 2000 // undef % X -> 0 2001 if (N0.getOpcode() == ISD::UNDEF) 2002 return DAG.getConstant(0, VT); 2003 // X % undef -> undef 2004 if (N1.getOpcode() == ISD::UNDEF) 2005 return N1; 2006 2007 return SDValue(); 2008} 2009 2010SDValue DAGCombiner::visitUREM(SDNode *N) { 2011 SDValue N0 = N->getOperand(0); 2012 SDValue N1 = N->getOperand(1); 2013 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2015 EVT VT = N->getValueType(0); 2016 2017 // fold (urem c1, c2) -> c1%c2 2018 if (N0C && N1C && !N1C->isNullValue()) 2019 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2020 // fold (urem x, pow2) -> (and x, pow2-1) 2021 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2022 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2023 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2024 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2025 if (N1.getOpcode() == ISD::SHL) { 2026 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2027 if (SHC->getAPIntValue().isPowerOf2()) { 2028 SDValue Add = 2029 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2030 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2031 VT)); 2032 AddToWorkList(Add.getNode()); 2033 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2034 } 2035 } 2036 } 2037 2038 // If X/C can be simplified by the division-by-constant logic, lower 2039 // X%C to the equivalent of X-X/C*C. 2040 if (N1C && !N1C->isNullValue()) { 2041 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2042 AddToWorkList(Div.getNode()); 2043 SDValue OptimizedDiv = combine(Div.getNode()); 2044 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2045 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2046 OptimizedDiv, N1); 2047 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2048 AddToWorkList(Mul.getNode()); 2049 return Sub; 2050 } 2051 } 2052 2053 // undef % X -> 0 2054 if (N0.getOpcode() == ISD::UNDEF) 2055 return DAG.getConstant(0, VT); 2056 // X % undef -> undef 2057 if (N1.getOpcode() == ISD::UNDEF) 2058 return N1; 2059 2060 return SDValue(); 2061} 2062 2063SDValue DAGCombiner::visitMULHS(SDNode *N) { 2064 SDValue N0 = N->getOperand(0); 2065 SDValue N1 = N->getOperand(1); 2066 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2067 EVT VT = N->getValueType(0); 2068 DebugLoc DL = N->getDebugLoc(); 2069 2070 // fold (mulhs x, 0) -> 0 2071 if (N1C && N1C->isNullValue()) 2072 return N1; 2073 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2074 if (N1C && N1C->getAPIntValue() == 1) 2075 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2076 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2077 getShiftAmountTy(N0.getValueType()))); 2078 // fold (mulhs x, undef) -> 0 2079 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2080 return DAG.getConstant(0, VT); 2081 2082 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2083 // plus a shift. 2084 if (VT.isSimple() && !VT.isVector()) { 2085 MVT Simple = VT.getSimpleVT(); 2086 unsigned SimpleSize = Simple.getSizeInBits(); 2087 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2088 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2089 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2090 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2091 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2092 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2093 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2094 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2095 } 2096 } 2097 2098 return SDValue(); 2099} 2100 2101SDValue DAGCombiner::visitMULHU(SDNode *N) { 2102 SDValue N0 = N->getOperand(0); 2103 SDValue N1 = N->getOperand(1); 2104 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2105 EVT VT = N->getValueType(0); 2106 DebugLoc DL = N->getDebugLoc(); 2107 2108 // fold (mulhu x, 0) -> 0 2109 if (N1C && N1C->isNullValue()) 2110 return N1; 2111 // fold (mulhu x, 1) -> 0 2112 if (N1C && N1C->getAPIntValue() == 1) 2113 return DAG.getConstant(0, N0.getValueType()); 2114 // fold (mulhu x, undef) -> 0 2115 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2116 return DAG.getConstant(0, VT); 2117 2118 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2119 // plus a shift. 2120 if (VT.isSimple() && !VT.isVector()) { 2121 MVT Simple = VT.getSimpleVT(); 2122 unsigned SimpleSize = Simple.getSizeInBits(); 2123 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2124 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2125 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2126 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2127 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2128 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2129 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2130 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2131 } 2132 } 2133 2134 return SDValue(); 2135} 2136 2137/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2138/// compute two values. LoOp and HiOp give the opcodes for the two computations 2139/// that are being performed. Return true if a simplification was made. 2140/// 2141SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2142 unsigned HiOp) { 2143 // If the high half is not needed, just compute the low half. 2144 bool HiExists = N->hasAnyUseOfValue(1); 2145 if (!HiExists && 2146 (!LegalOperations || 2147 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2148 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2149 N->op_begin(), N->getNumOperands()); 2150 return CombineTo(N, Res, Res); 2151 } 2152 2153 // If the low half is not needed, just compute the high half. 2154 bool LoExists = N->hasAnyUseOfValue(0); 2155 if (!LoExists && 2156 (!LegalOperations || 2157 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2158 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2159 N->op_begin(), N->getNumOperands()); 2160 return CombineTo(N, Res, Res); 2161 } 2162 2163 // If both halves are used, return as it is. 2164 if (LoExists && HiExists) 2165 return SDValue(); 2166 2167 // If the two computed results can be simplified separately, separate them. 2168 if (LoExists) { 2169 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2170 N->op_begin(), N->getNumOperands()); 2171 AddToWorkList(Lo.getNode()); 2172 SDValue LoOpt = combine(Lo.getNode()); 2173 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2174 (!LegalOperations || 2175 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2176 return CombineTo(N, LoOpt, LoOpt); 2177 } 2178 2179 if (HiExists) { 2180 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2181 N->op_begin(), N->getNumOperands()); 2182 AddToWorkList(Hi.getNode()); 2183 SDValue HiOpt = combine(Hi.getNode()); 2184 if (HiOpt.getNode() && HiOpt != Hi && 2185 (!LegalOperations || 2186 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2187 return CombineTo(N, HiOpt, HiOpt); 2188 } 2189 2190 return SDValue(); 2191} 2192 2193SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2194 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2195 if (Res.getNode()) return Res; 2196 2197 EVT VT = N->getValueType(0); 2198 DebugLoc DL = N->getDebugLoc(); 2199 2200 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2201 // plus a shift. 2202 if (VT.isSimple() && !VT.isVector()) { 2203 MVT Simple = VT.getSimpleVT(); 2204 unsigned SimpleSize = Simple.getSizeInBits(); 2205 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2206 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2207 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2208 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2209 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2210 // Compute the high part as N1. 2211 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2212 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2213 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2214 // Compute the low part as N0. 2215 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2216 return CombineTo(N, Lo, Hi); 2217 } 2218 } 2219 2220 return SDValue(); 2221} 2222 2223SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2224 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2225 if (Res.getNode()) return Res; 2226 2227 EVT VT = N->getValueType(0); 2228 DebugLoc DL = N->getDebugLoc(); 2229 2230 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2231 // plus a shift. 2232 if (VT.isSimple() && !VT.isVector()) { 2233 MVT Simple = VT.getSimpleVT(); 2234 unsigned SimpleSize = Simple.getSizeInBits(); 2235 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2236 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2237 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2238 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2239 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2240 // Compute the high part as N1. 2241 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2242 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2243 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2244 // Compute the low part as N0. 2245 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2246 return CombineTo(N, Lo, Hi); 2247 } 2248 } 2249 2250 return SDValue(); 2251} 2252 2253SDValue DAGCombiner::visitSMULO(SDNode *N) { 2254 // (smulo x, 2) -> (saddo x, x) 2255 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2256 if (C2->getAPIntValue() == 2) 2257 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2258 N->getOperand(0), N->getOperand(0)); 2259 2260 return SDValue(); 2261} 2262 2263SDValue DAGCombiner::visitUMULO(SDNode *N) { 2264 // (umulo x, 2) -> (uaddo x, x) 2265 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2266 if (C2->getAPIntValue() == 2) 2267 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2268 N->getOperand(0), N->getOperand(0)); 2269 2270 return SDValue(); 2271} 2272 2273SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2274 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2275 if (Res.getNode()) return Res; 2276 2277 return SDValue(); 2278} 2279 2280SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2281 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2282 if (Res.getNode()) return Res; 2283 2284 return SDValue(); 2285} 2286 2287/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2288/// two operands of the same opcode, try to simplify it. 2289SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2290 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2291 EVT VT = N0.getValueType(); 2292 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2293 2294 // Bail early if none of these transforms apply. 2295 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2296 2297 // For each of OP in AND/OR/XOR: 2298 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2299 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2300 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2301 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2302 // 2303 // do not sink logical op inside of a vector extend, since it may combine 2304 // into a vsetcc. 2305 EVT Op0VT = N0.getOperand(0).getValueType(); 2306 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2307 N0.getOpcode() == ISD::SIGN_EXTEND || 2308 // Avoid infinite looping with PromoteIntBinOp. 2309 (N0.getOpcode() == ISD::ANY_EXTEND && 2310 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2311 (N0.getOpcode() == ISD::TRUNCATE && 2312 (!TLI.isZExtFree(VT, Op0VT) || 2313 !TLI.isTruncateFree(Op0VT, VT)) && 2314 TLI.isTypeLegal(Op0VT))) && 2315 !VT.isVector() && 2316 Op0VT == N1.getOperand(0).getValueType() && 2317 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2318 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2319 N0.getOperand(0).getValueType(), 2320 N0.getOperand(0), N1.getOperand(0)); 2321 AddToWorkList(ORNode.getNode()); 2322 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2323 } 2324 2325 // For each of OP in SHL/SRL/SRA/AND... 2326 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2327 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2328 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2329 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2330 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2331 N0.getOperand(1) == N1.getOperand(1)) { 2332 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2333 N0.getOperand(0).getValueType(), 2334 N0.getOperand(0), N1.getOperand(0)); 2335 AddToWorkList(ORNode.getNode()); 2336 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2337 ORNode, N0.getOperand(1)); 2338 } 2339 2340 return SDValue(); 2341} 2342 2343SDValue DAGCombiner::visitAND(SDNode *N) { 2344 SDValue N0 = N->getOperand(0); 2345 SDValue N1 = N->getOperand(1); 2346 SDValue LL, LR, RL, RR, CC0, CC1; 2347 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2348 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2349 EVT VT = N1.getValueType(); 2350 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2351 2352 // fold vector ops 2353 if (VT.isVector()) { 2354 SDValue FoldedVOp = SimplifyVBinOp(N); 2355 if (FoldedVOp.getNode()) return FoldedVOp; 2356 } 2357 2358 // fold (and x, undef) -> 0 2359 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2360 return DAG.getConstant(0, VT); 2361 // fold (and c1, c2) -> c1&c2 2362 if (N0C && N1C) 2363 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2364 // canonicalize constant to RHS 2365 if (N0C && !N1C) 2366 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2367 // fold (and x, -1) -> x 2368 if (N1C && N1C->isAllOnesValue()) 2369 return N0; 2370 // if (and x, c) is known to be zero, return 0 2371 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2372 APInt::getAllOnesValue(BitWidth))) 2373 return DAG.getConstant(0, VT); 2374 // reassociate and 2375 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2376 if (RAND.getNode() != 0) 2377 return RAND; 2378 // fold (and (or x, C), D) -> D if (C & D) == D 2379 if (N1C && N0.getOpcode() == ISD::OR) 2380 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2381 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2382 return N1; 2383 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2384 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2385 SDValue N0Op0 = N0.getOperand(0); 2386 APInt Mask = ~N1C->getAPIntValue(); 2387 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2388 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2389 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2390 N0.getValueType(), N0Op0); 2391 2392 // Replace uses of the AND with uses of the Zero extend node. 2393 CombineTo(N, Zext); 2394 2395 // We actually want to replace all uses of the any_extend with the 2396 // zero_extend, to avoid duplicating things. This will later cause this 2397 // AND to be folded. 2398 CombineTo(N0.getNode(), Zext); 2399 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2400 } 2401 } 2402 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2403 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2404 // already be zero by virtue of the width of the base type of the load. 2405 // 2406 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2407 // more cases. 2408 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2409 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2410 N0.getOpcode() == ISD::LOAD) { 2411 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2412 N0 : N0.getOperand(0) ); 2413 2414 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2415 // This can be a pure constant or a vector splat, in which case we treat the 2416 // vector as a scalar and use the splat value. 2417 APInt Constant = APInt::getNullValue(1); 2418 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2419 Constant = C->getAPIntValue(); 2420 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2421 APInt SplatValue, SplatUndef; 2422 unsigned SplatBitSize; 2423 bool HasAnyUndefs; 2424 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2425 SplatBitSize, HasAnyUndefs); 2426 if (IsSplat) { 2427 // Undef bits can contribute to a possible optimisation if set, so 2428 // set them. 2429 SplatValue |= SplatUndef; 2430 2431 // The splat value may be something like "0x00FFFFFF", which means 0 for 2432 // the first vector value and FF for the rest, repeating. We need a mask 2433 // that will apply equally to all members of the vector, so AND all the 2434 // lanes of the constant together. 2435 EVT VT = Vector->getValueType(0); 2436 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2437 Constant = APInt::getAllOnesValue(BitWidth); 2438 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i) 2439 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2440 } 2441 } 2442 2443 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2444 // actually legal and isn't going to get expanded, else this is a false 2445 // optimisation. 2446 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2447 Load->getMemoryVT()); 2448 2449 // Resize the constant to the same size as the original memory access before 2450 // extension. If it is still the AllOnesValue then this AND is completely 2451 // unneeded. 2452 Constant = 2453 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2454 2455 bool B; 2456 switch (Load->getExtensionType()) { 2457 default: B = false; break; 2458 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2459 case ISD::ZEXTLOAD: 2460 case ISD::NON_EXTLOAD: B = true; break; 2461 } 2462 2463 if (B && Constant.isAllOnesValue()) { 2464 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2465 // preserve semantics once we get rid of the AND. 2466 SDValue NewLoad(Load, 0); 2467 if (Load->getExtensionType() == ISD::EXTLOAD) { 2468 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2469 Load->getValueType(0), Load->getDebugLoc(), 2470 Load->getChain(), Load->getBasePtr(), 2471 Load->getOffset(), Load->getMemoryVT(), 2472 Load->getMemOperand()); 2473 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2474 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2475 } 2476 2477 // Fold the AND away, taking care not to fold to the old load node if we 2478 // replaced it. 2479 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2480 2481 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2482 } 2483 } 2484 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2485 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2486 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2487 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2488 2489 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2490 LL.getValueType().isInteger()) { 2491 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2492 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2493 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2494 LR.getValueType(), LL, RL); 2495 AddToWorkList(ORNode.getNode()); 2496 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2497 } 2498 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2499 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2500 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2501 LR.getValueType(), LL, RL); 2502 AddToWorkList(ANDNode.getNode()); 2503 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2504 } 2505 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2506 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2507 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2508 LR.getValueType(), LL, RL); 2509 AddToWorkList(ORNode.getNode()); 2510 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2511 } 2512 } 2513 // canonicalize equivalent to ll == rl 2514 if (LL == RR && LR == RL) { 2515 Op1 = ISD::getSetCCSwappedOperands(Op1); 2516 std::swap(RL, RR); 2517 } 2518 if (LL == RL && LR == RR) { 2519 bool isInteger = LL.getValueType().isInteger(); 2520 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2521 if (Result != ISD::SETCC_INVALID && 2522 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2523 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2524 LL, LR, Result); 2525 } 2526 } 2527 2528 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2529 if (N0.getOpcode() == N1.getOpcode()) { 2530 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2531 if (Tmp.getNode()) return Tmp; 2532 } 2533 2534 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2535 // fold (and (sra)) -> (and (srl)) when possible. 2536 if (!VT.isVector() && 2537 SimplifyDemandedBits(SDValue(N, 0))) 2538 return SDValue(N, 0); 2539 2540 // fold (zext_inreg (extload x)) -> (zextload x) 2541 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2542 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2543 EVT MemVT = LN0->getMemoryVT(); 2544 // If we zero all the possible extended bits, then we can turn this into 2545 // a zextload if we are running before legalize or the operation is legal. 2546 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2547 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2548 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2549 ((!LegalOperations && !LN0->isVolatile()) || 2550 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2551 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2552 LN0->getChain(), LN0->getBasePtr(), 2553 LN0->getPointerInfo(), MemVT, 2554 LN0->isVolatile(), LN0->isNonTemporal(), 2555 LN0->getAlignment()); 2556 AddToWorkList(N); 2557 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2558 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2559 } 2560 } 2561 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2562 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2563 N0.hasOneUse()) { 2564 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2565 EVT MemVT = LN0->getMemoryVT(); 2566 // If we zero all the possible extended bits, then we can turn this into 2567 // a zextload if we are running before legalize or the operation is legal. 2568 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2569 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2570 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2571 ((!LegalOperations && !LN0->isVolatile()) || 2572 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2573 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2574 LN0->getChain(), 2575 LN0->getBasePtr(), LN0->getPointerInfo(), 2576 MemVT, 2577 LN0->isVolatile(), LN0->isNonTemporal(), 2578 LN0->getAlignment()); 2579 AddToWorkList(N); 2580 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2581 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2582 } 2583 } 2584 2585 // fold (and (load x), 255) -> (zextload x, i8) 2586 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2587 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2588 if (N1C && (N0.getOpcode() == ISD::LOAD || 2589 (N0.getOpcode() == ISD::ANY_EXTEND && 2590 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2591 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2592 LoadSDNode *LN0 = HasAnyExt 2593 ? cast<LoadSDNode>(N0.getOperand(0)) 2594 : cast<LoadSDNode>(N0); 2595 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2596 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2597 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2598 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2599 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2600 EVT LoadedVT = LN0->getMemoryVT(); 2601 2602 if (ExtVT == LoadedVT && 2603 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2604 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2605 2606 SDValue NewLoad = 2607 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2608 LN0->getChain(), LN0->getBasePtr(), 2609 LN0->getPointerInfo(), 2610 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2611 LN0->getAlignment()); 2612 AddToWorkList(N); 2613 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2614 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2615 } 2616 2617 // Do not change the width of a volatile load. 2618 // Do not generate loads of non-round integer types since these can 2619 // be expensive (and would be wrong if the type is not byte sized). 2620 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2621 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2622 EVT PtrType = LN0->getOperand(1).getValueType(); 2623 2624 unsigned Alignment = LN0->getAlignment(); 2625 SDValue NewPtr = LN0->getBasePtr(); 2626 2627 // For big endian targets, we need to add an offset to the pointer 2628 // to load the correct bytes. For little endian systems, we merely 2629 // need to read fewer bytes from the same pointer. 2630 if (TLI.isBigEndian()) { 2631 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2632 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2633 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2634 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2635 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2636 Alignment = MinAlign(Alignment, PtrOff); 2637 } 2638 2639 AddToWorkList(NewPtr.getNode()); 2640 2641 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2642 SDValue Load = 2643 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2644 LN0->getChain(), NewPtr, 2645 LN0->getPointerInfo(), 2646 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2647 Alignment); 2648 AddToWorkList(N); 2649 CombineTo(LN0, Load, Load.getValue(1)); 2650 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2651 } 2652 } 2653 } 2654 } 2655 2656 return SDValue(); 2657} 2658 2659/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2660/// 2661SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2662 bool DemandHighBits) { 2663 if (!LegalOperations) 2664 return SDValue(); 2665 2666 EVT VT = N->getValueType(0); 2667 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2668 return SDValue(); 2669 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2670 return SDValue(); 2671 2672 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2673 bool LookPassAnd0 = false; 2674 bool LookPassAnd1 = false; 2675 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2676 std::swap(N0, N1); 2677 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2678 std::swap(N0, N1); 2679 if (N0.getOpcode() == ISD::AND) { 2680 if (!N0.getNode()->hasOneUse()) 2681 return SDValue(); 2682 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2683 if (!N01C || N01C->getZExtValue() != 0xFF00) 2684 return SDValue(); 2685 N0 = N0.getOperand(0); 2686 LookPassAnd0 = true; 2687 } 2688 2689 if (N1.getOpcode() == ISD::AND) { 2690 if (!N1.getNode()->hasOneUse()) 2691 return SDValue(); 2692 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2693 if (!N11C || N11C->getZExtValue() != 0xFF) 2694 return SDValue(); 2695 N1 = N1.getOperand(0); 2696 LookPassAnd1 = true; 2697 } 2698 2699 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2700 std::swap(N0, N1); 2701 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2702 return SDValue(); 2703 if (!N0.getNode()->hasOneUse() || 2704 !N1.getNode()->hasOneUse()) 2705 return SDValue(); 2706 2707 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2708 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2709 if (!N01C || !N11C) 2710 return SDValue(); 2711 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2712 return SDValue(); 2713 2714 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2715 SDValue N00 = N0->getOperand(0); 2716 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2717 if (!N00.getNode()->hasOneUse()) 2718 return SDValue(); 2719 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2720 if (!N001C || N001C->getZExtValue() != 0xFF) 2721 return SDValue(); 2722 N00 = N00.getOperand(0); 2723 LookPassAnd0 = true; 2724 } 2725 2726 SDValue N10 = N1->getOperand(0); 2727 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2728 if (!N10.getNode()->hasOneUse()) 2729 return SDValue(); 2730 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2731 if (!N101C || N101C->getZExtValue() != 0xFF00) 2732 return SDValue(); 2733 N10 = N10.getOperand(0); 2734 LookPassAnd1 = true; 2735 } 2736 2737 if (N00 != N10) 2738 return SDValue(); 2739 2740 // Make sure everything beyond the low halfword is zero since the SRL 16 2741 // will clear the top bits. 2742 unsigned OpSizeInBits = VT.getSizeInBits(); 2743 if (DemandHighBits && OpSizeInBits > 16 && 2744 (!LookPassAnd0 || !LookPassAnd1) && 2745 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2746 return SDValue(); 2747 2748 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2749 if (OpSizeInBits > 16) 2750 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2751 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2752 return Res; 2753} 2754 2755/// isBSwapHWordElement - Return true if the specified node is an element 2756/// that makes up a 32-bit packed halfword byteswap. i.e. 2757/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2758static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2759 if (!N.getNode()->hasOneUse()) 2760 return false; 2761 2762 unsigned Opc = N.getOpcode(); 2763 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2764 return false; 2765 2766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2767 if (!N1C) 2768 return false; 2769 2770 unsigned Num; 2771 switch (N1C->getZExtValue()) { 2772 default: 2773 return false; 2774 case 0xFF: Num = 0; break; 2775 case 0xFF00: Num = 1; break; 2776 case 0xFF0000: Num = 2; break; 2777 case 0xFF000000: Num = 3; break; 2778 } 2779 2780 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2781 SDValue N0 = N.getOperand(0); 2782 if (Opc == ISD::AND) { 2783 if (Num == 0 || Num == 2) { 2784 // (x >> 8) & 0xff 2785 // (x >> 8) & 0xff0000 2786 if (N0.getOpcode() != ISD::SRL) 2787 return false; 2788 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2789 if (!C || C->getZExtValue() != 8) 2790 return false; 2791 } else { 2792 // (x << 8) & 0xff00 2793 // (x << 8) & 0xff000000 2794 if (N0.getOpcode() != ISD::SHL) 2795 return false; 2796 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2797 if (!C || C->getZExtValue() != 8) 2798 return false; 2799 } 2800 } else if (Opc == ISD::SHL) { 2801 // (x & 0xff) << 8 2802 // (x & 0xff0000) << 8 2803 if (Num != 0 && Num != 2) 2804 return false; 2805 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2806 if (!C || C->getZExtValue() != 8) 2807 return false; 2808 } else { // Opc == ISD::SRL 2809 // (x & 0xff00) >> 8 2810 // (x & 0xff000000) >> 8 2811 if (Num != 1 && Num != 3) 2812 return false; 2813 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2814 if (!C || C->getZExtValue() != 8) 2815 return false; 2816 } 2817 2818 if (Parts[Num]) 2819 return false; 2820 2821 Parts[Num] = N0.getOperand(0).getNode(); 2822 return true; 2823} 2824 2825/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2826/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2827/// => (rotl (bswap x), 16) 2828SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2829 if (!LegalOperations) 2830 return SDValue(); 2831 2832 EVT VT = N->getValueType(0); 2833 if (VT != MVT::i32) 2834 return SDValue(); 2835 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2836 return SDValue(); 2837 2838 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2839 // Look for either 2840 // (or (or (and), (and)), (or (and), (and))) 2841 // (or (or (or (and), (and)), (and)), (and)) 2842 if (N0.getOpcode() != ISD::OR) 2843 return SDValue(); 2844 SDValue N00 = N0.getOperand(0); 2845 SDValue N01 = N0.getOperand(1); 2846 2847 if (N1.getOpcode() == ISD::OR) { 2848 // (or (or (and), (and)), (or (and), (and))) 2849 SDValue N000 = N00.getOperand(0); 2850 if (!isBSwapHWordElement(N000, Parts)) 2851 return SDValue(); 2852 2853 SDValue N001 = N00.getOperand(1); 2854 if (!isBSwapHWordElement(N001, Parts)) 2855 return SDValue(); 2856 SDValue N010 = N01.getOperand(0); 2857 if (!isBSwapHWordElement(N010, Parts)) 2858 return SDValue(); 2859 SDValue N011 = N01.getOperand(1); 2860 if (!isBSwapHWordElement(N011, Parts)) 2861 return SDValue(); 2862 } else { 2863 // (or (or (or (and), (and)), (and)), (and)) 2864 if (!isBSwapHWordElement(N1, Parts)) 2865 return SDValue(); 2866 if (!isBSwapHWordElement(N01, Parts)) 2867 return SDValue(); 2868 if (N00.getOpcode() != ISD::OR) 2869 return SDValue(); 2870 SDValue N000 = N00.getOperand(0); 2871 if (!isBSwapHWordElement(N000, Parts)) 2872 return SDValue(); 2873 SDValue N001 = N00.getOperand(1); 2874 if (!isBSwapHWordElement(N001, Parts)) 2875 return SDValue(); 2876 } 2877 2878 // Make sure the parts are all coming from the same node. 2879 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2880 return SDValue(); 2881 2882 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2883 SDValue(Parts[0],0)); 2884 2885 // Result of the bswap should be rotated by 16. If it's not legal, than 2886 // do (x << 16) | (x >> 16). 2887 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2888 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2889 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2890 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2891 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 2892 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 2893 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 2894 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 2895} 2896 2897SDValue DAGCombiner::visitOR(SDNode *N) { 2898 SDValue N0 = N->getOperand(0); 2899 SDValue N1 = N->getOperand(1); 2900 SDValue LL, LR, RL, RR, CC0, CC1; 2901 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2902 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2903 EVT VT = N1.getValueType(); 2904 2905 // fold vector ops 2906 if (VT.isVector()) { 2907 SDValue FoldedVOp = SimplifyVBinOp(N); 2908 if (FoldedVOp.getNode()) return FoldedVOp; 2909 } 2910 2911 // fold (or x, undef) -> -1 2912 if (!LegalOperations && 2913 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2914 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2915 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2916 } 2917 // fold (or c1, c2) -> c1|c2 2918 if (N0C && N1C) 2919 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2920 // canonicalize constant to RHS 2921 if (N0C && !N1C) 2922 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2923 // fold (or x, 0) -> x 2924 if (N1C && N1C->isNullValue()) 2925 return N0; 2926 // fold (or x, -1) -> -1 2927 if (N1C && N1C->isAllOnesValue()) 2928 return N1; 2929 // fold (or x, c) -> c iff (x & ~c) == 0 2930 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2931 return N1; 2932 2933 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 2934 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 2935 if (BSwap.getNode() != 0) 2936 return BSwap; 2937 BSwap = MatchBSwapHWordLow(N, N0, N1); 2938 if (BSwap.getNode() != 0) 2939 return BSwap; 2940 2941 // reassociate or 2942 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2943 if (ROR.getNode() != 0) 2944 return ROR; 2945 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2946 // iff (c1 & c2) == 0. 2947 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2948 isa<ConstantSDNode>(N0.getOperand(1))) { 2949 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2950 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2951 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2952 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2953 N0.getOperand(0), N1), 2954 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2955 } 2956 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2957 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2958 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2959 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2960 2961 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2962 LL.getValueType().isInteger()) { 2963 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2964 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2965 if (cast<ConstantSDNode>(LR)->isNullValue() && 2966 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2967 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2968 LR.getValueType(), LL, RL); 2969 AddToWorkList(ORNode.getNode()); 2970 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2971 } 2972 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2973 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2974 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2975 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2976 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2977 LR.getValueType(), LL, RL); 2978 AddToWorkList(ANDNode.getNode()); 2979 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2980 } 2981 } 2982 // canonicalize equivalent to ll == rl 2983 if (LL == RR && LR == RL) { 2984 Op1 = ISD::getSetCCSwappedOperands(Op1); 2985 std::swap(RL, RR); 2986 } 2987 if (LL == RL && LR == RR) { 2988 bool isInteger = LL.getValueType().isInteger(); 2989 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2990 if (Result != ISD::SETCC_INVALID && 2991 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2992 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2993 LL, LR, Result); 2994 } 2995 } 2996 2997 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2998 if (N0.getOpcode() == N1.getOpcode()) { 2999 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3000 if (Tmp.getNode()) return Tmp; 3001 } 3002 3003 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3004 if (N0.getOpcode() == ISD::AND && 3005 N1.getOpcode() == ISD::AND && 3006 N0.getOperand(1).getOpcode() == ISD::Constant && 3007 N1.getOperand(1).getOpcode() == ISD::Constant && 3008 // Don't increase # computations. 3009 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3010 // We can only do this xform if we know that bits from X that are set in C2 3011 // but not in C1 are already zero. Likewise for Y. 3012 const APInt &LHSMask = 3013 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3014 const APInt &RHSMask = 3015 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3016 3017 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3018 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3019 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3020 N0.getOperand(0), N1.getOperand(0)); 3021 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3022 DAG.getConstant(LHSMask | RHSMask, VT)); 3023 } 3024 } 3025 3026 // See if this is some rotate idiom. 3027 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3028 return SDValue(Rot, 0); 3029 3030 // Simplify the operands using demanded-bits information. 3031 if (!VT.isVector() && 3032 SimplifyDemandedBits(SDValue(N, 0))) 3033 return SDValue(N, 0); 3034 3035 return SDValue(); 3036} 3037 3038/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3039static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3040 if (Op.getOpcode() == ISD::AND) { 3041 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3042 Mask = Op.getOperand(1); 3043 Op = Op.getOperand(0); 3044 } else { 3045 return false; 3046 } 3047 } 3048 3049 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3050 Shift = Op; 3051 return true; 3052 } 3053 3054 return false; 3055} 3056 3057// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3058// idioms for rotate, and if the target supports rotation instructions, generate 3059// a rot[lr]. 3060SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3061 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3062 EVT VT = LHS.getValueType(); 3063 if (!TLI.isTypeLegal(VT)) return 0; 3064 3065 // The target must have at least one rotate flavor. 3066 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3067 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3068 if (!HasROTL && !HasROTR) return 0; 3069 3070 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3071 SDValue LHSShift; // The shift. 3072 SDValue LHSMask; // AND value if any. 3073 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3074 return 0; // Not part of a rotate. 3075 3076 SDValue RHSShift; // The shift. 3077 SDValue RHSMask; // AND value if any. 3078 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3079 return 0; // Not part of a rotate. 3080 3081 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3082 return 0; // Not shifting the same value. 3083 3084 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3085 return 0; // Shifts must disagree. 3086 3087 // Canonicalize shl to left side in a shl/srl pair. 3088 if (RHSShift.getOpcode() == ISD::SHL) { 3089 std::swap(LHS, RHS); 3090 std::swap(LHSShift, RHSShift); 3091 std::swap(LHSMask , RHSMask ); 3092 } 3093 3094 unsigned OpSizeInBits = VT.getSizeInBits(); 3095 SDValue LHSShiftArg = LHSShift.getOperand(0); 3096 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3097 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3098 3099 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3100 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3101 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3102 RHSShiftAmt.getOpcode() == ISD::Constant) { 3103 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3104 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3105 if ((LShVal + RShVal) != OpSizeInBits) 3106 return 0; 3107 3108 SDValue Rot; 3109 if (HasROTL) 3110 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 3111 else 3112 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 3113 3114 // If there is an AND of either shifted operand, apply it to the result. 3115 if (LHSMask.getNode() || RHSMask.getNode()) { 3116 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3117 3118 if (LHSMask.getNode()) { 3119 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3120 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3121 } 3122 if (RHSMask.getNode()) { 3123 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3124 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3125 } 3126 3127 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3128 } 3129 3130 return Rot.getNode(); 3131 } 3132 3133 // If there is a mask here, and we have a variable shift, we can't be sure 3134 // that we're masking out the right stuff. 3135 if (LHSMask.getNode() || RHSMask.getNode()) 3136 return 0; 3137 3138 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3139 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3140 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3141 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3142 if (ConstantSDNode *SUBC = 3143 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3144 if (SUBC->getAPIntValue() == OpSizeInBits) { 3145 if (HasROTL) 3146 return DAG.getNode(ISD::ROTL, DL, VT, 3147 LHSShiftArg, LHSShiftAmt).getNode(); 3148 else 3149 return DAG.getNode(ISD::ROTR, DL, VT, 3150 LHSShiftArg, RHSShiftAmt).getNode(); 3151 } 3152 } 3153 } 3154 3155 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3156 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3157 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3158 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3159 if (ConstantSDNode *SUBC = 3160 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3161 if (SUBC->getAPIntValue() == OpSizeInBits) { 3162 if (HasROTR) 3163 return DAG.getNode(ISD::ROTR, DL, VT, 3164 LHSShiftArg, RHSShiftAmt).getNode(); 3165 else 3166 return DAG.getNode(ISD::ROTL, DL, VT, 3167 LHSShiftArg, LHSShiftAmt).getNode(); 3168 } 3169 } 3170 } 3171 3172 // Look for sign/zext/any-extended or truncate cases: 3173 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3174 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3175 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3176 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3177 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3178 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3179 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3180 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3181 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3182 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3183 if (RExtOp0.getOpcode() == ISD::SUB && 3184 RExtOp0.getOperand(1) == LExtOp0) { 3185 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3186 // (rotl x, y) 3187 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3188 // (rotr x, (sub 32, y)) 3189 if (ConstantSDNode *SUBC = 3190 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3191 if (SUBC->getAPIntValue() == OpSizeInBits) { 3192 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3193 LHSShiftArg, 3194 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3195 } 3196 } 3197 } else if (LExtOp0.getOpcode() == ISD::SUB && 3198 RExtOp0 == LExtOp0.getOperand(1)) { 3199 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3200 // (rotr x, y) 3201 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3202 // (rotl x, (sub 32, y)) 3203 if (ConstantSDNode *SUBC = 3204 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3205 if (SUBC->getAPIntValue() == OpSizeInBits) { 3206 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3207 LHSShiftArg, 3208 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3209 } 3210 } 3211 } 3212 } 3213 3214 return 0; 3215} 3216 3217SDValue DAGCombiner::visitXOR(SDNode *N) { 3218 SDValue N0 = N->getOperand(0); 3219 SDValue N1 = N->getOperand(1); 3220 SDValue LHS, RHS, CC; 3221 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3222 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3223 EVT VT = N0.getValueType(); 3224 3225 // fold vector ops 3226 if (VT.isVector()) { 3227 SDValue FoldedVOp = SimplifyVBinOp(N); 3228 if (FoldedVOp.getNode()) return FoldedVOp; 3229 } 3230 3231 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3232 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3233 return DAG.getConstant(0, VT); 3234 // fold (xor x, undef) -> undef 3235 if (N0.getOpcode() == ISD::UNDEF) 3236 return N0; 3237 if (N1.getOpcode() == ISD::UNDEF) 3238 return N1; 3239 // fold (xor c1, c2) -> c1^c2 3240 if (N0C && N1C) 3241 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3242 // canonicalize constant to RHS 3243 if (N0C && !N1C) 3244 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3245 // fold (xor x, 0) -> x 3246 if (N1C && N1C->isNullValue()) 3247 return N0; 3248 // reassociate xor 3249 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3250 if (RXOR.getNode() != 0) 3251 return RXOR; 3252 3253 // fold !(x cc y) -> (x !cc y) 3254 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3255 bool isInt = LHS.getValueType().isInteger(); 3256 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3257 isInt); 3258 3259 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3260 switch (N0.getOpcode()) { 3261 default: 3262 llvm_unreachable("Unhandled SetCC Equivalent!"); 3263 case ISD::SETCC: 3264 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3265 case ISD::SELECT_CC: 3266 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3267 N0.getOperand(3), NotCC); 3268 } 3269 } 3270 } 3271 3272 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3273 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3274 N0.getNode()->hasOneUse() && 3275 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3276 SDValue V = N0.getOperand(0); 3277 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3278 DAG.getConstant(1, V.getValueType())); 3279 AddToWorkList(V.getNode()); 3280 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3281 } 3282 3283 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3284 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3285 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3286 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3287 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3288 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3289 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3290 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3291 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3292 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3293 } 3294 } 3295 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3296 if (N1C && N1C->isAllOnesValue() && 3297 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3298 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3299 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3300 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3301 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3302 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3303 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3304 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3305 } 3306 } 3307 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3308 if (N1C && N0.getOpcode() == ISD::XOR) { 3309 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3310 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3311 if (N00C) 3312 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3313 DAG.getConstant(N1C->getAPIntValue() ^ 3314 N00C->getAPIntValue(), VT)); 3315 if (N01C) 3316 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3317 DAG.getConstant(N1C->getAPIntValue() ^ 3318 N01C->getAPIntValue(), VT)); 3319 } 3320 // fold (xor x, x) -> 0 3321 if (N0 == N1) 3322 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3323 3324 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3325 if (N0.getOpcode() == N1.getOpcode()) { 3326 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3327 if (Tmp.getNode()) return Tmp; 3328 } 3329 3330 // Simplify the expression using non-local knowledge. 3331 if (!VT.isVector() && 3332 SimplifyDemandedBits(SDValue(N, 0))) 3333 return SDValue(N, 0); 3334 3335 return SDValue(); 3336} 3337 3338/// visitShiftByConstant - Handle transforms common to the three shifts, when 3339/// the shift amount is a constant. 3340SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3341 SDNode *LHS = N->getOperand(0).getNode(); 3342 if (!LHS->hasOneUse()) return SDValue(); 3343 3344 // We want to pull some binops through shifts, so that we have (and (shift)) 3345 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3346 // thing happens with address calculations, so it's important to canonicalize 3347 // it. 3348 bool HighBitSet = false; // Can we transform this if the high bit is set? 3349 3350 switch (LHS->getOpcode()) { 3351 default: return SDValue(); 3352 case ISD::OR: 3353 case ISD::XOR: 3354 HighBitSet = false; // We can only transform sra if the high bit is clear. 3355 break; 3356 case ISD::AND: 3357 HighBitSet = true; // We can only transform sra if the high bit is set. 3358 break; 3359 case ISD::ADD: 3360 if (N->getOpcode() != ISD::SHL) 3361 return SDValue(); // only shl(add) not sr[al](add). 3362 HighBitSet = false; // We can only transform sra if the high bit is clear. 3363 break; 3364 } 3365 3366 // We require the RHS of the binop to be a constant as well. 3367 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3368 if (!BinOpCst) return SDValue(); 3369 3370 // FIXME: disable this unless the input to the binop is a shift by a constant. 3371 // If it is not a shift, it pessimizes some common cases like: 3372 // 3373 // void foo(int *X, int i) { X[i & 1235] = 1; } 3374 // int bar(int *X, int i) { return X[i & 255]; } 3375 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3376 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3377 BinOpLHSVal->getOpcode() != ISD::SRA && 3378 BinOpLHSVal->getOpcode() != ISD::SRL) || 3379 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3380 return SDValue(); 3381 3382 EVT VT = N->getValueType(0); 3383 3384 // If this is a signed shift right, and the high bit is modified by the 3385 // logical operation, do not perform the transformation. The highBitSet 3386 // boolean indicates the value of the high bit of the constant which would 3387 // cause it to be modified for this operation. 3388 if (N->getOpcode() == ISD::SRA) { 3389 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3390 if (BinOpRHSSignSet != HighBitSet) 3391 return SDValue(); 3392 } 3393 3394 // Fold the constants, shifting the binop RHS by the shift amount. 3395 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3396 N->getValueType(0), 3397 LHS->getOperand(1), N->getOperand(1)); 3398 3399 // Create the new shift. 3400 SDValue NewShift = DAG.getNode(N->getOpcode(), 3401 LHS->getOperand(0).getDebugLoc(), 3402 VT, LHS->getOperand(0), N->getOperand(1)); 3403 3404 // Create the new binop. 3405 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3406} 3407 3408SDValue DAGCombiner::visitSHL(SDNode *N) { 3409 SDValue N0 = N->getOperand(0); 3410 SDValue N1 = N->getOperand(1); 3411 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3412 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3413 EVT VT = N0.getValueType(); 3414 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3415 3416 // fold (shl c1, c2) -> c1<<c2 3417 if (N0C && N1C) 3418 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3419 // fold (shl 0, x) -> 0 3420 if (N0C && N0C->isNullValue()) 3421 return N0; 3422 // fold (shl x, c >= size(x)) -> undef 3423 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3424 return DAG.getUNDEF(VT); 3425 // fold (shl x, 0) -> x 3426 if (N1C && N1C->isNullValue()) 3427 return N0; 3428 // fold (shl undef, x) -> 0 3429 if (N0.getOpcode() == ISD::UNDEF) 3430 return DAG.getConstant(0, VT); 3431 // if (shl x, c) is known to be zero, return 0 3432 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3433 APInt::getAllOnesValue(OpSizeInBits))) 3434 return DAG.getConstant(0, VT); 3435 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3436 if (N1.getOpcode() == ISD::TRUNCATE && 3437 N1.getOperand(0).getOpcode() == ISD::AND && 3438 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3439 SDValue N101 = N1.getOperand(0).getOperand(1); 3440 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3441 EVT TruncVT = N1.getValueType(); 3442 SDValue N100 = N1.getOperand(0).getOperand(0); 3443 APInt TruncC = N101C->getAPIntValue(); 3444 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3445 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3446 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3447 DAG.getNode(ISD::TRUNCATE, 3448 N->getDebugLoc(), 3449 TruncVT, N100), 3450 DAG.getConstant(TruncC, TruncVT))); 3451 } 3452 } 3453 3454 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3455 return SDValue(N, 0); 3456 3457 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3458 if (N1C && N0.getOpcode() == ISD::SHL && 3459 N0.getOperand(1).getOpcode() == ISD::Constant) { 3460 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3461 uint64_t c2 = N1C->getZExtValue(); 3462 if (c1 + c2 >= OpSizeInBits) 3463 return DAG.getConstant(0, VT); 3464 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3465 DAG.getConstant(c1 + c2, N1.getValueType())); 3466 } 3467 3468 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3469 // For this to be valid, the second form must not preserve any of the bits 3470 // that are shifted out by the inner shift in the first form. This means 3471 // the outer shift size must be >= the number of bits added by the ext. 3472 // As a corollary, we don't care what kind of ext it is. 3473 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3474 N0.getOpcode() == ISD::ANY_EXTEND || 3475 N0.getOpcode() == ISD::SIGN_EXTEND) && 3476 N0.getOperand(0).getOpcode() == ISD::SHL && 3477 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3478 uint64_t c1 = 3479 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3480 uint64_t c2 = N1C->getZExtValue(); 3481 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3482 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3483 if (c2 >= OpSizeInBits - InnerShiftSize) { 3484 if (c1 + c2 >= OpSizeInBits) 3485 return DAG.getConstant(0, VT); 3486 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3487 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3488 N0.getOperand(0)->getOperand(0)), 3489 DAG.getConstant(c1 + c2, N1.getValueType())); 3490 } 3491 } 3492 3493 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3494 // (and (srl x, (sub c1, c2), MASK) 3495 // Only fold this if the inner shift has no other uses -- if it does, folding 3496 // this will increase the total number of instructions. 3497 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3498 N0.getOperand(1).getOpcode() == ISD::Constant) { 3499 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3500 if (c1 < VT.getSizeInBits()) { 3501 uint64_t c2 = N1C->getZExtValue(); 3502 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3503 VT.getSizeInBits() - c1); 3504 SDValue Shift; 3505 if (c2 > c1) { 3506 Mask = Mask.shl(c2-c1); 3507 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3508 DAG.getConstant(c2-c1, N1.getValueType())); 3509 } else { 3510 Mask = Mask.lshr(c1-c2); 3511 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3512 DAG.getConstant(c1-c2, N1.getValueType())); 3513 } 3514 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3515 DAG.getConstant(Mask, VT)); 3516 } 3517 } 3518 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3519 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3520 SDValue HiBitsMask = 3521 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3522 VT.getSizeInBits() - 3523 N1C->getZExtValue()), 3524 VT); 3525 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3526 HiBitsMask); 3527 } 3528 3529 if (N1C) { 3530 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3531 if (NewSHL.getNode()) 3532 return NewSHL; 3533 } 3534 3535 return SDValue(); 3536} 3537 3538SDValue DAGCombiner::visitSRA(SDNode *N) { 3539 SDValue N0 = N->getOperand(0); 3540 SDValue N1 = N->getOperand(1); 3541 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3542 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3543 EVT VT = N0.getValueType(); 3544 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3545 3546 // fold (sra c1, c2) -> (sra c1, c2) 3547 if (N0C && N1C) 3548 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3549 // fold (sra 0, x) -> 0 3550 if (N0C && N0C->isNullValue()) 3551 return N0; 3552 // fold (sra -1, x) -> -1 3553 if (N0C && N0C->isAllOnesValue()) 3554 return N0; 3555 // fold (sra x, (setge c, size(x))) -> undef 3556 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3557 return DAG.getUNDEF(VT); 3558 // fold (sra x, 0) -> x 3559 if (N1C && N1C->isNullValue()) 3560 return N0; 3561 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3562 // sext_inreg. 3563 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3564 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3565 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3566 if (VT.isVector()) 3567 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3568 ExtVT, VT.getVectorNumElements()); 3569 if ((!LegalOperations || 3570 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3571 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3572 N0.getOperand(0), DAG.getValueType(ExtVT)); 3573 } 3574 3575 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3576 if (N1C && N0.getOpcode() == ISD::SRA) { 3577 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3578 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3579 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3580 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3581 DAG.getConstant(Sum, N1C->getValueType(0))); 3582 } 3583 } 3584 3585 // fold (sra (shl X, m), (sub result_size, n)) 3586 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3587 // result_size - n != m. 3588 // If truncate is free for the target sext(shl) is likely to result in better 3589 // code. 3590 if (N0.getOpcode() == ISD::SHL) { 3591 // Get the two constanst of the shifts, CN0 = m, CN = n. 3592 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3593 if (N01C && N1C) { 3594 // Determine what the truncate's result bitsize and type would be. 3595 EVT TruncVT = 3596 EVT::getIntegerVT(*DAG.getContext(), 3597 OpSizeInBits - N1C->getZExtValue()); 3598 // Determine the residual right-shift amount. 3599 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3600 3601 // If the shift is not a no-op (in which case this should be just a sign 3602 // extend already), the truncated to type is legal, sign_extend is legal 3603 // on that type, and the truncate to that type is both legal and free, 3604 // perform the transform. 3605 if ((ShiftAmt > 0) && 3606 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3607 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3608 TLI.isTruncateFree(VT, TruncVT)) { 3609 3610 SDValue Amt = DAG.getConstant(ShiftAmt, 3611 getShiftAmountTy(N0.getOperand(0).getValueType())); 3612 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3613 N0.getOperand(0), Amt); 3614 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3615 Shift); 3616 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3617 N->getValueType(0), Trunc); 3618 } 3619 } 3620 } 3621 3622 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3623 if (N1.getOpcode() == ISD::TRUNCATE && 3624 N1.getOperand(0).getOpcode() == ISD::AND && 3625 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3626 SDValue N101 = N1.getOperand(0).getOperand(1); 3627 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3628 EVT TruncVT = N1.getValueType(); 3629 SDValue N100 = N1.getOperand(0).getOperand(0); 3630 APInt TruncC = N101C->getAPIntValue(); 3631 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3632 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3633 DAG.getNode(ISD::AND, N->getDebugLoc(), 3634 TruncVT, 3635 DAG.getNode(ISD::TRUNCATE, 3636 N->getDebugLoc(), 3637 TruncVT, N100), 3638 DAG.getConstant(TruncC, TruncVT))); 3639 } 3640 } 3641 3642 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3643 // if c1 is equal to the number of bits the trunc removes 3644 if (N0.getOpcode() == ISD::TRUNCATE && 3645 (N0.getOperand(0).getOpcode() == ISD::SRL || 3646 N0.getOperand(0).getOpcode() == ISD::SRA) && 3647 N0.getOperand(0).hasOneUse() && 3648 N0.getOperand(0).getOperand(1).hasOneUse() && 3649 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3650 EVT LargeVT = N0.getOperand(0).getValueType(); 3651 ConstantSDNode *LargeShiftAmt = 3652 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3653 3654 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3655 LargeShiftAmt->getZExtValue()) { 3656 SDValue Amt = 3657 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3658 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3659 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3660 N0.getOperand(0).getOperand(0), Amt); 3661 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3662 } 3663 } 3664 3665 // Simplify, based on bits shifted out of the LHS. 3666 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3667 return SDValue(N, 0); 3668 3669 3670 // If the sign bit is known to be zero, switch this to a SRL. 3671 if (DAG.SignBitIsZero(N0)) 3672 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3673 3674 if (N1C) { 3675 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3676 if (NewSRA.getNode()) 3677 return NewSRA; 3678 } 3679 3680 return SDValue(); 3681} 3682 3683SDValue DAGCombiner::visitSRL(SDNode *N) { 3684 SDValue N0 = N->getOperand(0); 3685 SDValue N1 = N->getOperand(1); 3686 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3687 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3688 EVT VT = N0.getValueType(); 3689 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3690 3691 // fold (srl c1, c2) -> c1 >>u c2 3692 if (N0C && N1C) 3693 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3694 // fold (srl 0, x) -> 0 3695 if (N0C && N0C->isNullValue()) 3696 return N0; 3697 // fold (srl x, c >= size(x)) -> undef 3698 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3699 return DAG.getUNDEF(VT); 3700 // fold (srl x, 0) -> x 3701 if (N1C && N1C->isNullValue()) 3702 return N0; 3703 // if (srl x, c) is known to be zero, return 0 3704 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3705 APInt::getAllOnesValue(OpSizeInBits))) 3706 return DAG.getConstant(0, VT); 3707 3708 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3709 if (N1C && N0.getOpcode() == ISD::SRL && 3710 N0.getOperand(1).getOpcode() == ISD::Constant) { 3711 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3712 uint64_t c2 = N1C->getZExtValue(); 3713 if (c1 + c2 >= OpSizeInBits) 3714 return DAG.getConstant(0, VT); 3715 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3716 DAG.getConstant(c1 + c2, N1.getValueType())); 3717 } 3718 3719 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3720 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3721 N0.getOperand(0).getOpcode() == ISD::SRL && 3722 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3723 uint64_t c1 = 3724 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3725 uint64_t c2 = N1C->getZExtValue(); 3726 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3727 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3728 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3729 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3730 if (c1 + OpSizeInBits == InnerShiftSize) { 3731 if (c1 + c2 >= InnerShiftSize) 3732 return DAG.getConstant(0, VT); 3733 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3734 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3735 N0.getOperand(0)->getOperand(0), 3736 DAG.getConstant(c1 + c2, ShiftCountVT))); 3737 } 3738 } 3739 3740 // fold (srl (shl x, c), c) -> (and x, cst2) 3741 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3742 N0.getValueSizeInBits() <= 64) { 3743 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3744 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3745 DAG.getConstant(~0ULL >> ShAmt, VT)); 3746 } 3747 3748 3749 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3750 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3751 // Shifting in all undef bits? 3752 EVT SmallVT = N0.getOperand(0).getValueType(); 3753 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3754 return DAG.getUNDEF(VT); 3755 3756 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3757 uint64_t ShiftAmt = N1C->getZExtValue(); 3758 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3759 N0.getOperand(0), 3760 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3761 AddToWorkList(SmallShift.getNode()); 3762 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3763 } 3764 } 3765 3766 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3767 // bit, which is unmodified by sra. 3768 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3769 if (N0.getOpcode() == ISD::SRA) 3770 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3771 } 3772 3773 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3774 if (N1C && N0.getOpcode() == ISD::CTLZ && 3775 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3776 APInt KnownZero, KnownOne; 3777 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3778 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3779 3780 // If any of the input bits are KnownOne, then the input couldn't be all 3781 // zeros, thus the result of the srl will always be zero. 3782 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3783 3784 // If all of the bits input the to ctlz node are known to be zero, then 3785 // the result of the ctlz is "32" and the result of the shift is one. 3786 APInt UnknownBits = ~KnownZero & Mask; 3787 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3788 3789 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3790 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3791 // Okay, we know that only that the single bit specified by UnknownBits 3792 // could be set on input to the CTLZ node. If this bit is set, the SRL 3793 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3794 // to an SRL/XOR pair, which is likely to simplify more. 3795 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3796 SDValue Op = N0.getOperand(0); 3797 3798 if (ShAmt) { 3799 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3800 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3801 AddToWorkList(Op.getNode()); 3802 } 3803 3804 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3805 Op, DAG.getConstant(1, VT)); 3806 } 3807 } 3808 3809 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3810 if (N1.getOpcode() == ISD::TRUNCATE && 3811 N1.getOperand(0).getOpcode() == ISD::AND && 3812 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3813 SDValue N101 = N1.getOperand(0).getOperand(1); 3814 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3815 EVT TruncVT = N1.getValueType(); 3816 SDValue N100 = N1.getOperand(0).getOperand(0); 3817 APInt TruncC = N101C->getAPIntValue(); 3818 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3819 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3820 DAG.getNode(ISD::AND, N->getDebugLoc(), 3821 TruncVT, 3822 DAG.getNode(ISD::TRUNCATE, 3823 N->getDebugLoc(), 3824 TruncVT, N100), 3825 DAG.getConstant(TruncC, TruncVT))); 3826 } 3827 } 3828 3829 // fold operands of srl based on knowledge that the low bits are not 3830 // demanded. 3831 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3832 return SDValue(N, 0); 3833 3834 if (N1C) { 3835 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3836 if (NewSRL.getNode()) 3837 return NewSRL; 3838 } 3839 3840 // Attempt to convert a srl of a load into a narrower zero-extending load. 3841 SDValue NarrowLoad = ReduceLoadWidth(N); 3842 if (NarrowLoad.getNode()) 3843 return NarrowLoad; 3844 3845 // Here is a common situation. We want to optimize: 3846 // 3847 // %a = ... 3848 // %b = and i32 %a, 2 3849 // %c = srl i32 %b, 1 3850 // brcond i32 %c ... 3851 // 3852 // into 3853 // 3854 // %a = ... 3855 // %b = and %a, 2 3856 // %c = setcc eq %b, 0 3857 // brcond %c ... 3858 // 3859 // However when after the source operand of SRL is optimized into AND, the SRL 3860 // itself may not be optimized further. Look for it and add the BRCOND into 3861 // the worklist. 3862 if (N->hasOneUse()) { 3863 SDNode *Use = *N->use_begin(); 3864 if (Use->getOpcode() == ISD::BRCOND) 3865 AddToWorkList(Use); 3866 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3867 // Also look pass the truncate. 3868 Use = *Use->use_begin(); 3869 if (Use->getOpcode() == ISD::BRCOND) 3870 AddToWorkList(Use); 3871 } 3872 } 3873 3874 return SDValue(); 3875} 3876 3877SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3878 SDValue N0 = N->getOperand(0); 3879 EVT VT = N->getValueType(0); 3880 3881 // fold (ctlz c1) -> c2 3882 if (isa<ConstantSDNode>(N0)) 3883 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3884 return SDValue(); 3885} 3886 3887SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3888 SDValue N0 = N->getOperand(0); 3889 EVT VT = N->getValueType(0); 3890 3891 // fold (ctlz_zero_undef c1) -> c2 3892 if (isa<ConstantSDNode>(N0)) 3893 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3894 return SDValue(); 3895} 3896 3897SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3898 SDValue N0 = N->getOperand(0); 3899 EVT VT = N->getValueType(0); 3900 3901 // fold (cttz c1) -> c2 3902 if (isa<ConstantSDNode>(N0)) 3903 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3904 return SDValue(); 3905} 3906 3907SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 3908 SDValue N0 = N->getOperand(0); 3909 EVT VT = N->getValueType(0); 3910 3911 // fold (cttz_zero_undef c1) -> c2 3912 if (isa<ConstantSDNode>(N0)) 3913 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3914 return SDValue(); 3915} 3916 3917SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3918 SDValue N0 = N->getOperand(0); 3919 EVT VT = N->getValueType(0); 3920 3921 // fold (ctpop c1) -> c2 3922 if (isa<ConstantSDNode>(N0)) 3923 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3924 return SDValue(); 3925} 3926 3927SDValue DAGCombiner::visitSELECT(SDNode *N) { 3928 SDValue N0 = N->getOperand(0); 3929 SDValue N1 = N->getOperand(1); 3930 SDValue N2 = N->getOperand(2); 3931 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3932 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3933 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3934 EVT VT = N->getValueType(0); 3935 EVT VT0 = N0.getValueType(); 3936 3937 // fold (select C, X, X) -> X 3938 if (N1 == N2) 3939 return N1; 3940 // fold (select true, X, Y) -> X 3941 if (N0C && !N0C->isNullValue()) 3942 return N1; 3943 // fold (select false, X, Y) -> Y 3944 if (N0C && N0C->isNullValue()) 3945 return N2; 3946 // fold (select C, 1, X) -> (or C, X) 3947 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3948 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3949 // fold (select C, 0, 1) -> (xor C, 1) 3950 if (VT.isInteger() && 3951 (VT0 == MVT::i1 || 3952 (VT0.isInteger() && 3953 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) && 3954 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3955 SDValue XORNode; 3956 if (VT == VT0) 3957 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3958 N0, DAG.getConstant(1, VT0)); 3959 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3960 N0, DAG.getConstant(1, VT0)); 3961 AddToWorkList(XORNode.getNode()); 3962 if (VT.bitsGT(VT0)) 3963 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3964 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3965 } 3966 // fold (select C, 0, X) -> (and (not C), X) 3967 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3968 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3969 AddToWorkList(NOTNode.getNode()); 3970 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3971 } 3972 // fold (select C, X, 1) -> (or (not C), X) 3973 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3974 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3975 AddToWorkList(NOTNode.getNode()); 3976 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3977 } 3978 // fold (select C, X, 0) -> (and C, X) 3979 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3980 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3981 // fold (select X, X, Y) -> (or X, Y) 3982 // fold (select X, 1, Y) -> (or X, Y) 3983 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3984 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3985 // fold (select X, Y, X) -> (and X, Y) 3986 // fold (select X, Y, 0) -> (and X, Y) 3987 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3988 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3989 3990 // If we can fold this based on the true/false value, do so. 3991 if (SimplifySelectOps(N, N1, N2)) 3992 return SDValue(N, 0); // Don't revisit N. 3993 3994 // fold selects based on a setcc into other things, such as min/max/abs 3995 if (N0.getOpcode() == ISD::SETCC) { 3996 // FIXME: 3997 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3998 // having to say they don't support SELECT_CC on every type the DAG knows 3999 // about, since there is no way to mark an opcode illegal at all value types 4000 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4001 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4002 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4003 N0.getOperand(0), N0.getOperand(1), 4004 N1, N2, N0.getOperand(2)); 4005 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4006 } 4007 4008 return SDValue(); 4009} 4010 4011SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4012 SDValue N0 = N->getOperand(0); 4013 SDValue N1 = N->getOperand(1); 4014 SDValue N2 = N->getOperand(2); 4015 SDValue N3 = N->getOperand(3); 4016 SDValue N4 = N->getOperand(4); 4017 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4018 4019 // fold select_cc lhs, rhs, x, x, cc -> x 4020 if (N2 == N3) 4021 return N2; 4022 4023 // Determine if the condition we're dealing with is constant 4024 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4025 N0, N1, CC, N->getDebugLoc(), false); 4026 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4027 4028 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4029 if (!SCCC->isNullValue()) 4030 return N2; // cond always true -> true val 4031 else 4032 return N3; // cond always false -> false val 4033 } 4034 4035 // Fold to a simpler select_cc 4036 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4037 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4038 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4039 SCC.getOperand(2)); 4040 4041 // If we can fold this based on the true/false value, do so. 4042 if (SimplifySelectOps(N, N2, N3)) 4043 return SDValue(N, 0); // Don't revisit N. 4044 4045 // fold select_cc into other things, such as min/max/abs 4046 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4047} 4048 4049SDValue DAGCombiner::visitSETCC(SDNode *N) { 4050 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4051 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4052 N->getDebugLoc()); 4053} 4054 4055// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4056// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4057// transformation. Returns true if extension are possible and the above 4058// mentioned transformation is profitable. 4059static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4060 unsigned ExtOpc, 4061 SmallVector<SDNode*, 4> &ExtendNodes, 4062 const TargetLowering &TLI) { 4063 bool HasCopyToRegUses = false; 4064 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4065 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4066 UE = N0.getNode()->use_end(); 4067 UI != UE; ++UI) { 4068 SDNode *User = *UI; 4069 if (User == N) 4070 continue; 4071 if (UI.getUse().getResNo() != N0.getResNo()) 4072 continue; 4073 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4074 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4075 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4076 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4077 // Sign bits will be lost after a zext. 4078 return false; 4079 bool Add = false; 4080 for (unsigned i = 0; i != 2; ++i) { 4081 SDValue UseOp = User->getOperand(i); 4082 if (UseOp == N0) 4083 continue; 4084 if (!isa<ConstantSDNode>(UseOp)) 4085 return false; 4086 Add = true; 4087 } 4088 if (Add) 4089 ExtendNodes.push_back(User); 4090 continue; 4091 } 4092 // If truncates aren't free and there are users we can't 4093 // extend, it isn't worthwhile. 4094 if (!isTruncFree) 4095 return false; 4096 // Remember if this value is live-out. 4097 if (User->getOpcode() == ISD::CopyToReg) 4098 HasCopyToRegUses = true; 4099 } 4100 4101 if (HasCopyToRegUses) { 4102 bool BothLiveOut = false; 4103 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4104 UI != UE; ++UI) { 4105 SDUse &Use = UI.getUse(); 4106 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4107 BothLiveOut = true; 4108 break; 4109 } 4110 } 4111 if (BothLiveOut) 4112 // Both unextended and extended values are live out. There had better be 4113 // a good reason for the transformation. 4114 return ExtendNodes.size(); 4115 } 4116 return true; 4117} 4118 4119void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4120 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4121 ISD::NodeType ExtType) { 4122 // Extend SetCC uses if necessary. 4123 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4124 SDNode *SetCC = SetCCs[i]; 4125 SmallVector<SDValue, 4> Ops; 4126 4127 for (unsigned j = 0; j != 2; ++j) { 4128 SDValue SOp = SetCC->getOperand(j); 4129 if (SOp == Trunc) 4130 Ops.push_back(ExtLoad); 4131 else 4132 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4133 } 4134 4135 Ops.push_back(SetCC->getOperand(2)); 4136 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4137 &Ops[0], Ops.size())); 4138 } 4139} 4140 4141SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4142 SDValue N0 = N->getOperand(0); 4143 EVT VT = N->getValueType(0); 4144 4145 // fold (sext c1) -> c1 4146 if (isa<ConstantSDNode>(N0)) 4147 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4148 4149 // fold (sext (sext x)) -> (sext x) 4150 // fold (sext (aext x)) -> (sext x) 4151 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4152 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4153 N0.getOperand(0)); 4154 4155 if (N0.getOpcode() == ISD::TRUNCATE) { 4156 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4157 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4158 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4159 if (NarrowLoad.getNode()) { 4160 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4161 if (NarrowLoad.getNode() != N0.getNode()) { 4162 CombineTo(N0.getNode(), NarrowLoad); 4163 // CombineTo deleted the truncate, if needed, but not what's under it. 4164 AddToWorkList(oye); 4165 } 4166 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4167 } 4168 4169 // See if the value being truncated is already sign extended. If so, just 4170 // eliminate the trunc/sext pair. 4171 SDValue Op = N0.getOperand(0); 4172 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4173 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4174 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4175 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4176 4177 if (OpBits == DestBits) { 4178 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4179 // bits, it is already ready. 4180 if (NumSignBits > DestBits-MidBits) 4181 return Op; 4182 } else if (OpBits < DestBits) { 4183 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4184 // bits, just sext from i32. 4185 if (NumSignBits > OpBits-MidBits) 4186 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4187 } else { 4188 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4189 // bits, just truncate to i32. 4190 if (NumSignBits > OpBits-MidBits) 4191 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4192 } 4193 4194 // fold (sext (truncate x)) -> (sextinreg x). 4195 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4196 N0.getValueType())) { 4197 if (OpBits < DestBits) 4198 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4199 else if (OpBits > DestBits) 4200 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4201 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4202 DAG.getValueType(N0.getValueType())); 4203 } 4204 } 4205 4206 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4207 // None of the supported targets knows how to perform load and sign extend 4208 // on vectors in one instruction. We only perform this transformation on 4209 // scalars. 4210 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4211 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4212 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4213 bool DoXform = true; 4214 SmallVector<SDNode*, 4> SetCCs; 4215 if (!N0.hasOneUse()) 4216 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4217 if (DoXform) { 4218 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4219 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4220 LN0->getChain(), 4221 LN0->getBasePtr(), LN0->getPointerInfo(), 4222 N0.getValueType(), 4223 LN0->isVolatile(), LN0->isNonTemporal(), 4224 LN0->getAlignment()); 4225 CombineTo(N, ExtLoad); 4226 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4227 N0.getValueType(), ExtLoad); 4228 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4229 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4230 ISD::SIGN_EXTEND); 4231 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4232 } 4233 } 4234 4235 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4236 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4237 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4238 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4239 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4240 EVT MemVT = LN0->getMemoryVT(); 4241 if ((!LegalOperations && !LN0->isVolatile()) || 4242 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4243 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4244 LN0->getChain(), 4245 LN0->getBasePtr(), LN0->getPointerInfo(), 4246 MemVT, 4247 LN0->isVolatile(), LN0->isNonTemporal(), 4248 LN0->getAlignment()); 4249 CombineTo(N, ExtLoad); 4250 CombineTo(N0.getNode(), 4251 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4252 N0.getValueType(), ExtLoad), 4253 ExtLoad.getValue(1)); 4254 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4255 } 4256 } 4257 4258 // fold (sext (and/or/xor (load x), cst)) -> 4259 // (and/or/xor (sextload x), (sext cst)) 4260 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4261 N0.getOpcode() == ISD::XOR) && 4262 isa<LoadSDNode>(N0.getOperand(0)) && 4263 N0.getOperand(1).getOpcode() == ISD::Constant && 4264 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4265 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4266 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4267 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4268 bool DoXform = true; 4269 SmallVector<SDNode*, 4> SetCCs; 4270 if (!N0.hasOneUse()) 4271 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4272 SetCCs, TLI); 4273 if (DoXform) { 4274 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4275 LN0->getChain(), LN0->getBasePtr(), 4276 LN0->getPointerInfo(), 4277 LN0->getMemoryVT(), 4278 LN0->isVolatile(), 4279 LN0->isNonTemporal(), 4280 LN0->getAlignment()); 4281 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4282 Mask = Mask.sext(VT.getSizeInBits()); 4283 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4284 ExtLoad, DAG.getConstant(Mask, VT)); 4285 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4286 N0.getOperand(0).getDebugLoc(), 4287 N0.getOperand(0).getValueType(), ExtLoad); 4288 CombineTo(N, And); 4289 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4290 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4291 ISD::SIGN_EXTEND); 4292 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4293 } 4294 } 4295 } 4296 4297 if (N0.getOpcode() == ISD::SETCC) { 4298 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4299 // Only do this before legalize for now. 4300 if (VT.isVector() && !LegalOperations) { 4301 EVT N0VT = N0.getOperand(0).getValueType(); 4302 // We know that the # elements of the results is the same as the 4303 // # elements of the compare (and the # elements of the compare result 4304 // for that matter). Check to see that they are the same size. If so, 4305 // we know that the element size of the sext'd result matches the 4306 // element size of the compare operands. 4307 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4308 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4309 N0.getOperand(1), 4310 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4311 // If the desired elements are smaller or larger than the source 4312 // elements we can use a matching integer vector type and then 4313 // truncate/sign extend 4314 else { 4315 EVT MatchingElementType = 4316 EVT::getIntegerVT(*DAG.getContext(), 4317 N0VT.getScalarType().getSizeInBits()); 4318 EVT MatchingVectorType = 4319 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4320 N0VT.getVectorNumElements()); 4321 SDValue VsetCC = 4322 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4323 N0.getOperand(1), 4324 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4325 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4326 } 4327 } 4328 4329 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4330 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4331 SDValue NegOne = 4332 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4333 SDValue SCC = 4334 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4335 NegOne, DAG.getConstant(0, VT), 4336 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4337 if (SCC.getNode()) return SCC; 4338 if (!LegalOperations || 4339 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4340 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4341 DAG.getSetCC(N->getDebugLoc(), 4342 TLI.getSetCCResultType(VT), 4343 N0.getOperand(0), N0.getOperand(1), 4344 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4345 NegOne, DAG.getConstant(0, VT)); 4346 } 4347 4348 // fold (sext x) -> (zext x) if the sign bit is known zero. 4349 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4350 DAG.SignBitIsZero(N0)) 4351 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4352 4353 return SDValue(); 4354} 4355 4356SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4357 SDValue N0 = N->getOperand(0); 4358 EVT VT = N->getValueType(0); 4359 4360 // fold (zext c1) -> c1 4361 if (isa<ConstantSDNode>(N0)) 4362 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4363 // fold (zext (zext x)) -> (zext x) 4364 // fold (zext (aext x)) -> (zext x) 4365 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4366 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4367 N0.getOperand(0)); 4368 4369 // fold (zext (truncate x)) -> (zext x) or 4370 // (zext (truncate x)) -> (truncate x) 4371 // This is valid when the truncated bits of x are already zero. 4372 // FIXME: We should extend this to work for vectors too. 4373 if (N0.getOpcode() == ISD::TRUNCATE && !VT.isVector()) { 4374 SDValue Op = N0.getOperand(0); 4375 APInt TruncatedBits 4376 = APInt::getBitsSet(Op.getValueSizeInBits(), 4377 N0.getValueSizeInBits(), 4378 std::min(Op.getValueSizeInBits(), 4379 VT.getSizeInBits())); 4380 APInt KnownZero, KnownOne; 4381 DAG.ComputeMaskedBits(Op, TruncatedBits, KnownZero, KnownOne); 4382 if (TruncatedBits == KnownZero) { 4383 if (VT.bitsGT(Op.getValueType())) 4384 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4385 if (VT.bitsLT(Op.getValueType())) 4386 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4387 4388 return Op; 4389 } 4390 } 4391 4392 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4393 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4394 if (N0.getOpcode() == ISD::TRUNCATE) { 4395 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4396 if (NarrowLoad.getNode()) { 4397 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4398 if (NarrowLoad.getNode() != N0.getNode()) { 4399 CombineTo(N0.getNode(), NarrowLoad); 4400 // CombineTo deleted the truncate, if needed, but not what's under it. 4401 AddToWorkList(oye); 4402 } 4403 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4404 } 4405 } 4406 4407 // fold (zext (truncate x)) -> (and x, mask) 4408 if (N0.getOpcode() == ISD::TRUNCATE && 4409 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4410 4411 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4412 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4413 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4414 if (NarrowLoad.getNode()) { 4415 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4416 if (NarrowLoad.getNode() != N0.getNode()) { 4417 CombineTo(N0.getNode(), NarrowLoad); 4418 // CombineTo deleted the truncate, if needed, but not what's under it. 4419 AddToWorkList(oye); 4420 } 4421 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4422 } 4423 4424 SDValue Op = N0.getOperand(0); 4425 if (Op.getValueType().bitsLT(VT)) { 4426 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4427 } else if (Op.getValueType().bitsGT(VT)) { 4428 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4429 } 4430 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4431 N0.getValueType().getScalarType()); 4432 } 4433 4434 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4435 // if either of the casts is not free. 4436 if (N0.getOpcode() == ISD::AND && 4437 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4438 N0.getOperand(1).getOpcode() == ISD::Constant && 4439 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4440 N0.getValueType()) || 4441 !TLI.isZExtFree(N0.getValueType(), VT))) { 4442 SDValue X = N0.getOperand(0).getOperand(0); 4443 if (X.getValueType().bitsLT(VT)) { 4444 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4445 } else if (X.getValueType().bitsGT(VT)) { 4446 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4447 } 4448 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4449 Mask = Mask.zext(VT.getSizeInBits()); 4450 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4451 X, DAG.getConstant(Mask, VT)); 4452 } 4453 4454 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4455 // None of the supported targets knows how to perform load and vector_zext 4456 // on vectors in one instruction. We only perform this transformation on 4457 // scalars. 4458 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4459 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4460 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4461 bool DoXform = true; 4462 SmallVector<SDNode*, 4> SetCCs; 4463 if (!N0.hasOneUse()) 4464 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4465 if (DoXform) { 4466 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4467 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4468 LN0->getChain(), 4469 LN0->getBasePtr(), LN0->getPointerInfo(), 4470 N0.getValueType(), 4471 LN0->isVolatile(), LN0->isNonTemporal(), 4472 LN0->getAlignment()); 4473 CombineTo(N, ExtLoad); 4474 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4475 N0.getValueType(), ExtLoad); 4476 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4477 4478 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4479 ISD::ZERO_EXTEND); 4480 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4481 } 4482 } 4483 4484 // fold (zext (and/or/xor (load x), cst)) -> 4485 // (and/or/xor (zextload x), (zext cst)) 4486 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4487 N0.getOpcode() == ISD::XOR) && 4488 isa<LoadSDNode>(N0.getOperand(0)) && 4489 N0.getOperand(1).getOpcode() == ISD::Constant && 4490 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4491 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4492 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4493 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4494 bool DoXform = true; 4495 SmallVector<SDNode*, 4> SetCCs; 4496 if (!N0.hasOneUse()) 4497 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4498 SetCCs, TLI); 4499 if (DoXform) { 4500 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4501 LN0->getChain(), LN0->getBasePtr(), 4502 LN0->getPointerInfo(), 4503 LN0->getMemoryVT(), 4504 LN0->isVolatile(), 4505 LN0->isNonTemporal(), 4506 LN0->getAlignment()); 4507 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4508 Mask = Mask.zext(VT.getSizeInBits()); 4509 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4510 ExtLoad, DAG.getConstant(Mask, VT)); 4511 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4512 N0.getOperand(0).getDebugLoc(), 4513 N0.getOperand(0).getValueType(), ExtLoad); 4514 CombineTo(N, And); 4515 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4516 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4517 ISD::ZERO_EXTEND); 4518 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4519 } 4520 } 4521 } 4522 4523 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4524 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4525 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4526 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4527 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4528 EVT MemVT = LN0->getMemoryVT(); 4529 if ((!LegalOperations && !LN0->isVolatile()) || 4530 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4531 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4532 LN0->getChain(), 4533 LN0->getBasePtr(), LN0->getPointerInfo(), 4534 MemVT, 4535 LN0->isVolatile(), LN0->isNonTemporal(), 4536 LN0->getAlignment()); 4537 CombineTo(N, ExtLoad); 4538 CombineTo(N0.getNode(), 4539 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4540 ExtLoad), 4541 ExtLoad.getValue(1)); 4542 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4543 } 4544 } 4545 4546 if (N0.getOpcode() == ISD::SETCC) { 4547 if (!LegalOperations && VT.isVector()) { 4548 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4549 // Only do this before legalize for now. 4550 EVT N0VT = N0.getOperand(0).getValueType(); 4551 EVT EltVT = VT.getVectorElementType(); 4552 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4553 DAG.getConstant(1, EltVT)); 4554 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4555 // We know that the # elements of the results is the same as the 4556 // # elements of the compare (and the # elements of the compare result 4557 // for that matter). Check to see that they are the same size. If so, 4558 // we know that the element size of the sext'd result matches the 4559 // element size of the compare operands. 4560 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4561 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4562 N0.getOperand(1), 4563 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4564 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4565 &OneOps[0], OneOps.size())); 4566 4567 // If the desired elements are smaller or larger than the source 4568 // elements we can use a matching integer vector type and then 4569 // truncate/sign extend 4570 EVT MatchingElementType = 4571 EVT::getIntegerVT(*DAG.getContext(), 4572 N0VT.getScalarType().getSizeInBits()); 4573 EVT MatchingVectorType = 4574 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4575 N0VT.getVectorNumElements()); 4576 SDValue VsetCC = 4577 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4578 N0.getOperand(1), 4579 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4580 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4581 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4582 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4583 &OneOps[0], OneOps.size())); 4584 } 4585 4586 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4587 SDValue SCC = 4588 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4589 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4590 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4591 if (SCC.getNode()) return SCC; 4592 } 4593 4594 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4595 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4596 isa<ConstantSDNode>(N0.getOperand(1)) && 4597 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4598 N0.hasOneUse()) { 4599 SDValue ShAmt = N0.getOperand(1); 4600 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4601 if (N0.getOpcode() == ISD::SHL) { 4602 SDValue InnerZExt = N0.getOperand(0); 4603 // If the original shl may be shifting out bits, do not perform this 4604 // transformation. 4605 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4606 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4607 if (ShAmtVal > KnownZeroBits) 4608 return SDValue(); 4609 } 4610 4611 DebugLoc DL = N->getDebugLoc(); 4612 4613 // Ensure that the shift amount is wide enough for the shifted value. 4614 if (VT.getSizeInBits() >= 256) 4615 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4616 4617 return DAG.getNode(N0.getOpcode(), DL, VT, 4618 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4619 ShAmt); 4620 } 4621 4622 return SDValue(); 4623} 4624 4625SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4626 SDValue N0 = N->getOperand(0); 4627 EVT VT = N->getValueType(0); 4628 4629 // fold (aext c1) -> c1 4630 if (isa<ConstantSDNode>(N0)) 4631 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4632 // fold (aext (aext x)) -> (aext x) 4633 // fold (aext (zext x)) -> (zext x) 4634 // fold (aext (sext x)) -> (sext x) 4635 if (N0.getOpcode() == ISD::ANY_EXTEND || 4636 N0.getOpcode() == ISD::ZERO_EXTEND || 4637 N0.getOpcode() == ISD::SIGN_EXTEND) 4638 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4639 4640 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4641 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4642 if (N0.getOpcode() == ISD::TRUNCATE) { 4643 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4644 if (NarrowLoad.getNode()) { 4645 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4646 if (NarrowLoad.getNode() != N0.getNode()) { 4647 CombineTo(N0.getNode(), NarrowLoad); 4648 // CombineTo deleted the truncate, if needed, but not what's under it. 4649 AddToWorkList(oye); 4650 } 4651 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4652 } 4653 } 4654 4655 // fold (aext (truncate x)) 4656 if (N0.getOpcode() == ISD::TRUNCATE) { 4657 SDValue TruncOp = N0.getOperand(0); 4658 if (TruncOp.getValueType() == VT) 4659 return TruncOp; // x iff x size == zext size. 4660 if (TruncOp.getValueType().bitsGT(VT)) 4661 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4662 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4663 } 4664 4665 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4666 // if the trunc is not free. 4667 if (N0.getOpcode() == ISD::AND && 4668 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4669 N0.getOperand(1).getOpcode() == ISD::Constant && 4670 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4671 N0.getValueType())) { 4672 SDValue X = N0.getOperand(0).getOperand(0); 4673 if (X.getValueType().bitsLT(VT)) { 4674 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4675 } else if (X.getValueType().bitsGT(VT)) { 4676 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4677 } 4678 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4679 Mask = Mask.zext(VT.getSizeInBits()); 4680 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4681 X, DAG.getConstant(Mask, VT)); 4682 } 4683 4684 // fold (aext (load x)) -> (aext (truncate (extload x))) 4685 // None of the supported targets knows how to perform load and any_ext 4686 // on vectors in one instruction. We only perform this transformation on 4687 // scalars. 4688 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4689 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4690 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4691 bool DoXform = true; 4692 SmallVector<SDNode*, 4> SetCCs; 4693 if (!N0.hasOneUse()) 4694 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4695 if (DoXform) { 4696 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4697 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4698 LN0->getChain(), 4699 LN0->getBasePtr(), LN0->getPointerInfo(), 4700 N0.getValueType(), 4701 LN0->isVolatile(), LN0->isNonTemporal(), 4702 LN0->getAlignment()); 4703 CombineTo(N, ExtLoad); 4704 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4705 N0.getValueType(), ExtLoad); 4706 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4707 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4708 ISD::ANY_EXTEND); 4709 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4710 } 4711 } 4712 4713 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4714 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4715 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4716 if (N0.getOpcode() == ISD::LOAD && 4717 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4718 N0.hasOneUse()) { 4719 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4720 EVT MemVT = LN0->getMemoryVT(); 4721 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4722 VT, LN0->getChain(), LN0->getBasePtr(), 4723 LN0->getPointerInfo(), MemVT, 4724 LN0->isVolatile(), LN0->isNonTemporal(), 4725 LN0->getAlignment()); 4726 CombineTo(N, ExtLoad); 4727 CombineTo(N0.getNode(), 4728 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4729 N0.getValueType(), ExtLoad), 4730 ExtLoad.getValue(1)); 4731 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4732 } 4733 4734 if (N0.getOpcode() == ISD::SETCC) { 4735 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4736 // Only do this before legalize for now. 4737 if (VT.isVector() && !LegalOperations) { 4738 EVT N0VT = N0.getOperand(0).getValueType(); 4739 // We know that the # elements of the results is the same as the 4740 // # elements of the compare (and the # elements of the compare result 4741 // for that matter). Check to see that they are the same size. If so, 4742 // we know that the element size of the sext'd result matches the 4743 // element size of the compare operands. 4744 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4745 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4746 N0.getOperand(1), 4747 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4748 // If the desired elements are smaller or larger than the source 4749 // elements we can use a matching integer vector type and then 4750 // truncate/sign extend 4751 else { 4752 EVT MatchingElementType = 4753 EVT::getIntegerVT(*DAG.getContext(), 4754 N0VT.getScalarType().getSizeInBits()); 4755 EVT MatchingVectorType = 4756 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4757 N0VT.getVectorNumElements()); 4758 SDValue VsetCC = 4759 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4760 N0.getOperand(1), 4761 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4762 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4763 } 4764 } 4765 4766 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4767 SDValue SCC = 4768 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4769 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4770 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4771 if (SCC.getNode()) 4772 return SCC; 4773 } 4774 4775 return SDValue(); 4776} 4777 4778/// GetDemandedBits - See if the specified operand can be simplified with the 4779/// knowledge that only the bits specified by Mask are used. If so, return the 4780/// simpler operand, otherwise return a null SDValue. 4781SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4782 switch (V.getOpcode()) { 4783 default: break; 4784 case ISD::Constant: { 4785 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4786 assert(CV != 0 && "Const value should be ConstSDNode."); 4787 const APInt &CVal = CV->getAPIntValue(); 4788 APInt NewVal = CVal & Mask; 4789 if (NewVal != CVal) { 4790 return DAG.getConstant(NewVal, V.getValueType()); 4791 } 4792 break; 4793 } 4794 case ISD::OR: 4795 case ISD::XOR: 4796 // If the LHS or RHS don't contribute bits to the or, drop them. 4797 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4798 return V.getOperand(1); 4799 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4800 return V.getOperand(0); 4801 break; 4802 case ISD::SRL: 4803 // Only look at single-use SRLs. 4804 if (!V.getNode()->hasOneUse()) 4805 break; 4806 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4807 // See if we can recursively simplify the LHS. 4808 unsigned Amt = RHSC->getZExtValue(); 4809 4810 // Watch out for shift count overflow though. 4811 if (Amt >= Mask.getBitWidth()) break; 4812 APInt NewMask = Mask << Amt; 4813 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4814 if (SimplifyLHS.getNode()) 4815 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4816 SimplifyLHS, V.getOperand(1)); 4817 } 4818 } 4819 return SDValue(); 4820} 4821 4822/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4823/// bits and then truncated to a narrower type and where N is a multiple 4824/// of number of bits of the narrower type, transform it to a narrower load 4825/// from address + N / num of bits of new type. If the result is to be 4826/// extended, also fold the extension to form a extending load. 4827SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4828 unsigned Opc = N->getOpcode(); 4829 4830 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4831 SDValue N0 = N->getOperand(0); 4832 EVT VT = N->getValueType(0); 4833 EVT ExtVT = VT; 4834 4835 // This transformation isn't valid for vector loads. 4836 if (VT.isVector()) 4837 return SDValue(); 4838 4839 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4840 // extended to VT. 4841 if (Opc == ISD::SIGN_EXTEND_INREG) { 4842 ExtType = ISD::SEXTLOAD; 4843 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4844 } else if (Opc == ISD::SRL) { 4845 // Another special-case: SRL is basically zero-extending a narrower value. 4846 ExtType = ISD::ZEXTLOAD; 4847 N0 = SDValue(N, 0); 4848 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4849 if (!N01) return SDValue(); 4850 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4851 VT.getSizeInBits() - N01->getZExtValue()); 4852 } 4853 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4854 return SDValue(); 4855 4856 unsigned EVTBits = ExtVT.getSizeInBits(); 4857 4858 // Do not generate loads of non-round integer types since these can 4859 // be expensive (and would be wrong if the type is not byte sized). 4860 if (!ExtVT.isRound()) 4861 return SDValue(); 4862 4863 unsigned ShAmt = 0; 4864 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4865 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4866 ShAmt = N01->getZExtValue(); 4867 // Is the shift amount a multiple of size of VT? 4868 if ((ShAmt & (EVTBits-1)) == 0) { 4869 N0 = N0.getOperand(0); 4870 // Is the load width a multiple of size of VT? 4871 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4872 return SDValue(); 4873 } 4874 4875 // At this point, we must have a load or else we can't do the transform. 4876 if (!isa<LoadSDNode>(N0)) return SDValue(); 4877 4878 // If the shift amount is larger than the input type then we're not 4879 // accessing any of the loaded bytes. If the load was a zextload/extload 4880 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4881 // If the load was a sextload then the result is a splat of the sign bit 4882 // of the extended byte. This is not worth optimizing for. 4883 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4884 return SDValue(); 4885 } 4886 } 4887 4888 // If the load is shifted left (and the result isn't shifted back right), 4889 // we can fold the truncate through the shift. 4890 unsigned ShLeftAmt = 0; 4891 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4892 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4893 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4894 ShLeftAmt = N01->getZExtValue(); 4895 N0 = N0.getOperand(0); 4896 } 4897 } 4898 4899 // If we haven't found a load, we can't narrow it. Don't transform one with 4900 // multiple uses, this would require adding a new load. 4901 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4902 // Don't change the width of a volatile load. 4903 cast<LoadSDNode>(N0)->isVolatile()) 4904 return SDValue(); 4905 4906 // Verify that we are actually reducing a load width here. 4907 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4908 return SDValue(); 4909 4910 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4911 EVT PtrType = N0.getOperand(1).getValueType(); 4912 4913 // For big endian targets, we need to adjust the offset to the pointer to 4914 // load the correct bytes. 4915 if (TLI.isBigEndian()) { 4916 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4917 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4918 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4919 } 4920 4921 uint64_t PtrOff = ShAmt / 8; 4922 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4923 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4924 PtrType, LN0->getBasePtr(), 4925 DAG.getConstant(PtrOff, PtrType)); 4926 AddToWorkList(NewPtr.getNode()); 4927 4928 SDValue Load; 4929 if (ExtType == ISD::NON_EXTLOAD) 4930 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4931 LN0->getPointerInfo().getWithOffset(PtrOff), 4932 LN0->isVolatile(), LN0->isNonTemporal(), 4933 LN0->isInvariant(), NewAlign); 4934 else 4935 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4936 LN0->getPointerInfo().getWithOffset(PtrOff), 4937 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4938 NewAlign); 4939 4940 // Replace the old load's chain with the new load's chain. 4941 WorkListRemover DeadNodes(*this); 4942 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4943 &DeadNodes); 4944 4945 // Shift the result left, if we've swallowed a left shift. 4946 SDValue Result = Load; 4947 if (ShLeftAmt != 0) { 4948 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 4949 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4950 ShImmTy = VT; 4951 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4952 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4953 } 4954 4955 // Return the new loaded value. 4956 return Result; 4957} 4958 4959SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4960 SDValue N0 = N->getOperand(0); 4961 SDValue N1 = N->getOperand(1); 4962 EVT VT = N->getValueType(0); 4963 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4964 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4965 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4966 4967 // fold (sext_in_reg c1) -> c1 4968 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4969 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4970 4971 // If the input is already sign extended, just drop the extension. 4972 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4973 return N0; 4974 4975 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4976 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4977 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4978 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4979 N0.getOperand(0), N1); 4980 } 4981 4982 // fold (sext_in_reg (sext x)) -> (sext x) 4983 // fold (sext_in_reg (aext x)) -> (sext x) 4984 // if x is small enough. 4985 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4986 SDValue N00 = N0.getOperand(0); 4987 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4988 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4989 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4990 } 4991 4992 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4993 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4994 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4995 4996 // fold operands of sext_in_reg based on knowledge that the top bits are not 4997 // demanded. 4998 if (SimplifyDemandedBits(SDValue(N, 0))) 4999 return SDValue(N, 0); 5000 5001 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5002 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5003 SDValue NarrowLoad = ReduceLoadWidth(N); 5004 if (NarrowLoad.getNode()) 5005 return NarrowLoad; 5006 5007 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5008 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5009 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5010 if (N0.getOpcode() == ISD::SRL) { 5011 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5012 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5013 // We can turn this into an SRA iff the input to the SRL is already sign 5014 // extended enough. 5015 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5016 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5017 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5018 N0.getOperand(0), N0.getOperand(1)); 5019 } 5020 } 5021 5022 // fold (sext_inreg (extload x)) -> (sextload x) 5023 if (ISD::isEXTLoad(N0.getNode()) && 5024 ISD::isUNINDEXEDLoad(N0.getNode()) && 5025 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5026 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5027 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5028 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5029 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5030 LN0->getChain(), 5031 LN0->getBasePtr(), LN0->getPointerInfo(), 5032 EVT, 5033 LN0->isVolatile(), LN0->isNonTemporal(), 5034 LN0->getAlignment()); 5035 CombineTo(N, ExtLoad); 5036 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5037 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5038 } 5039 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5040 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5041 N0.hasOneUse() && 5042 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5043 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5044 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5045 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5046 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5047 LN0->getChain(), 5048 LN0->getBasePtr(), LN0->getPointerInfo(), 5049 EVT, 5050 LN0->isVolatile(), LN0->isNonTemporal(), 5051 LN0->getAlignment()); 5052 CombineTo(N, ExtLoad); 5053 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5054 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5055 } 5056 5057 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5058 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5059 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5060 N0.getOperand(1), false); 5061 if (BSwap.getNode() != 0) 5062 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5063 BSwap, N1); 5064 } 5065 5066 return SDValue(); 5067} 5068 5069SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5070 SDValue N0 = N->getOperand(0); 5071 EVT VT = N->getValueType(0); 5072 bool isLE = TLI.isLittleEndian(); 5073 5074 // noop truncate 5075 if (N0.getValueType() == N->getValueType(0)) 5076 return N0; 5077 // fold (truncate c1) -> c1 5078 if (isa<ConstantSDNode>(N0)) 5079 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5080 // fold (truncate (truncate x)) -> (truncate x) 5081 if (N0.getOpcode() == ISD::TRUNCATE) 5082 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5083 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5084 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5085 N0.getOpcode() == ISD::SIGN_EXTEND || 5086 N0.getOpcode() == ISD::ANY_EXTEND) { 5087 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5088 // if the source is smaller than the dest, we still need an extend 5089 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5090 N0.getOperand(0)); 5091 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 5092 // if the source is larger than the dest, than we just need the truncate 5093 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5094 else 5095 // if the source and dest are the same type, we can drop both the extend 5096 // and the truncate. 5097 return N0.getOperand(0); 5098 } 5099 5100 // Fold extract-and-trunc into a narrow extract. For example: 5101 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5102 // i32 y = TRUNCATE(i64 x) 5103 // -- becomes -- 5104 // v16i8 b = BITCAST (v2i64 val) 5105 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5106 // 5107 // Note: We only run this optimization after type legalization (which often 5108 // creates this pattern) and before operation legalization after which 5109 // we need to be more careful about the vector instructions that we generate. 5110 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5111 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5112 5113 EVT VecTy = N0.getOperand(0).getValueType(); 5114 EVT ExTy = N0.getValueType(); 5115 EVT TrTy = N->getValueType(0); 5116 5117 unsigned NumElem = VecTy.getVectorNumElements(); 5118 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5119 5120 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5121 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5122 5123 SDValue EltNo = N0->getOperand(1); 5124 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5125 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5126 5127 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5128 5129 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5130 NVT, N0.getOperand(0)); 5131 5132 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5133 N->getDebugLoc(), TrTy, V, 5134 DAG.getConstant(Index, MVT::i32)); 5135 } 5136 } 5137 5138 // See if we can simplify the input to this truncate through knowledge that 5139 // only the low bits are being used. 5140 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5141 // Currently we only perform this optimization on scalars because vectors 5142 // may have different active low bits. 5143 if (!VT.isVector()) { 5144 SDValue Shorter = 5145 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5146 VT.getSizeInBits())); 5147 if (Shorter.getNode()) 5148 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5149 } 5150 // fold (truncate (load x)) -> (smaller load x) 5151 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5152 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5153 SDValue Reduced = ReduceLoadWidth(N); 5154 if (Reduced.getNode()) 5155 return Reduced; 5156 } 5157 5158 // Simplify the operands using demanded-bits information. 5159 if (!VT.isVector() && 5160 SimplifyDemandedBits(SDValue(N, 0))) 5161 return SDValue(N, 0); 5162 5163 return SDValue(); 5164} 5165 5166static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5167 SDValue Elt = N->getOperand(i); 5168 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5169 return Elt.getNode(); 5170 return Elt.getOperand(Elt.getResNo()).getNode(); 5171} 5172 5173/// CombineConsecutiveLoads - build_pair (load, load) -> load 5174/// if load locations are consecutive. 5175SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5176 assert(N->getOpcode() == ISD::BUILD_PAIR); 5177 5178 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5179 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5180 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5181 LD1->getPointerInfo().getAddrSpace() != 5182 LD2->getPointerInfo().getAddrSpace()) 5183 return SDValue(); 5184 EVT LD1VT = LD1->getValueType(0); 5185 5186 if (ISD::isNON_EXTLoad(LD2) && 5187 LD2->hasOneUse() && 5188 // If both are volatile this would reduce the number of volatile loads. 5189 // If one is volatile it might be ok, but play conservative and bail out. 5190 !LD1->isVolatile() && 5191 !LD2->isVolatile() && 5192 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5193 unsigned Align = LD1->getAlignment(); 5194 unsigned NewAlign = TLI.getTargetData()-> 5195 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5196 5197 if (NewAlign <= Align && 5198 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5199 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5200 LD1->getBasePtr(), LD1->getPointerInfo(), 5201 false, false, false, Align); 5202 } 5203 5204 return SDValue(); 5205} 5206 5207SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5208 SDValue N0 = N->getOperand(0); 5209 EVT VT = N->getValueType(0); 5210 5211 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5212 // Only do this before legalize, since afterward the target may be depending 5213 // on the bitconvert. 5214 // First check to see if this is all constant. 5215 if (!LegalTypes && 5216 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5217 VT.isVector()) { 5218 bool isSimple = true; 5219 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5220 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5221 N0.getOperand(i).getOpcode() != ISD::Constant && 5222 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5223 isSimple = false; 5224 break; 5225 } 5226 5227 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5228 assert(!DestEltVT.isVector() && 5229 "Element type of vector ValueType must not be vector!"); 5230 if (isSimple) 5231 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5232 } 5233 5234 // If the input is a constant, let getNode fold it. 5235 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5236 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5237 if (Res.getNode() != N) { 5238 if (!LegalOperations || 5239 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5240 return Res; 5241 5242 // Folding it resulted in an illegal node, and it's too late to 5243 // do that. Clean up the old node and forego the transformation. 5244 // Ideally this won't happen very often, because instcombine 5245 // and the earlier dagcombine runs (where illegal nodes are 5246 // permitted) should have folded most of them already. 5247 DAG.DeleteNode(Res.getNode()); 5248 } 5249 } 5250 5251 // (conv (conv x, t1), t2) -> (conv x, t2) 5252 if (N0.getOpcode() == ISD::BITCAST) 5253 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5254 N0.getOperand(0)); 5255 5256 // fold (conv (load x)) -> (load (conv*)x) 5257 // If the resultant load doesn't need a higher alignment than the original! 5258 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5259 // Do not change the width of a volatile load. 5260 !cast<LoadSDNode>(N0)->isVolatile() && 5261 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5262 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5263 unsigned Align = TLI.getTargetData()-> 5264 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5265 unsigned OrigAlign = LN0->getAlignment(); 5266 5267 if (Align <= OrigAlign) { 5268 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5269 LN0->getBasePtr(), LN0->getPointerInfo(), 5270 LN0->isVolatile(), LN0->isNonTemporal(), 5271 LN0->isInvariant(), OrigAlign); 5272 AddToWorkList(N); 5273 CombineTo(N0.getNode(), 5274 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5275 N0.getValueType(), Load), 5276 Load.getValue(1)); 5277 return Load; 5278 } 5279 } 5280 5281 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5282 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5283 // This often reduces constant pool loads. 5284 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 5285 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5286 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5287 N0.getOperand(0)); 5288 AddToWorkList(NewConv.getNode()); 5289 5290 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5291 if (N0.getOpcode() == ISD::FNEG) 5292 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5293 NewConv, DAG.getConstant(SignBit, VT)); 5294 assert(N0.getOpcode() == ISD::FABS); 5295 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5296 NewConv, DAG.getConstant(~SignBit, VT)); 5297 } 5298 5299 // fold (bitconvert (fcopysign cst, x)) -> 5300 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5301 // Note that we don't handle (copysign x, cst) because this can always be 5302 // folded to an fneg or fabs. 5303 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5304 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5305 VT.isInteger() && !VT.isVector()) { 5306 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5307 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5308 if (isTypeLegal(IntXVT)) { 5309 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5310 IntXVT, N0.getOperand(1)); 5311 AddToWorkList(X.getNode()); 5312 5313 // If X has a different width than the result/lhs, sext it or truncate it. 5314 unsigned VTWidth = VT.getSizeInBits(); 5315 if (OrigXWidth < VTWidth) { 5316 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5317 AddToWorkList(X.getNode()); 5318 } else if (OrigXWidth > VTWidth) { 5319 // To get the sign bit in the right place, we have to shift it right 5320 // before truncating. 5321 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5322 X.getValueType(), X, 5323 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5324 AddToWorkList(X.getNode()); 5325 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5326 AddToWorkList(X.getNode()); 5327 } 5328 5329 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5330 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5331 X, DAG.getConstant(SignBit, VT)); 5332 AddToWorkList(X.getNode()); 5333 5334 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5335 VT, N0.getOperand(0)); 5336 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5337 Cst, DAG.getConstant(~SignBit, VT)); 5338 AddToWorkList(Cst.getNode()); 5339 5340 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5341 } 5342 } 5343 5344 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5345 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5346 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5347 if (CombineLD.getNode()) 5348 return CombineLD; 5349 } 5350 5351 return SDValue(); 5352} 5353 5354SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5355 EVT VT = N->getValueType(0); 5356 return CombineConsecutiveLoads(N, VT); 5357} 5358 5359/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5360/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5361/// destination element value type. 5362SDValue DAGCombiner:: 5363ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5364 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5365 5366 // If this is already the right type, we're done. 5367 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5368 5369 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5370 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5371 5372 // If this is a conversion of N elements of one type to N elements of another 5373 // type, convert each element. This handles FP<->INT cases. 5374 if (SrcBitSize == DstBitSize) { 5375 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5376 BV->getValueType(0).getVectorNumElements()); 5377 5378 // Due to the FP element handling below calling this routine recursively, 5379 // we can end up with a scalar-to-vector node here. 5380 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5381 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5382 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5383 DstEltVT, BV->getOperand(0))); 5384 5385 SmallVector<SDValue, 8> Ops; 5386 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5387 SDValue Op = BV->getOperand(i); 5388 // If the vector element type is not legal, the BUILD_VECTOR operands 5389 // are promoted and implicitly truncated. Make that explicit here. 5390 if (Op.getValueType() != SrcEltVT) 5391 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5392 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5393 DstEltVT, Op)); 5394 AddToWorkList(Ops.back().getNode()); 5395 } 5396 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5397 &Ops[0], Ops.size()); 5398 } 5399 5400 // Otherwise, we're growing or shrinking the elements. To avoid having to 5401 // handle annoying details of growing/shrinking FP values, we convert them to 5402 // int first. 5403 if (SrcEltVT.isFloatingPoint()) { 5404 // Convert the input float vector to a int vector where the elements are the 5405 // same sizes. 5406 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5407 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5408 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5409 SrcEltVT = IntVT; 5410 } 5411 5412 // Now we know the input is an integer vector. If the output is a FP type, 5413 // convert to integer first, then to FP of the right size. 5414 if (DstEltVT.isFloatingPoint()) { 5415 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5416 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5417 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5418 5419 // Next, convert to FP elements of the same size. 5420 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5421 } 5422 5423 // Okay, we know the src/dst types are both integers of differing types. 5424 // Handling growing first. 5425 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5426 if (SrcBitSize < DstBitSize) { 5427 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5428 5429 SmallVector<SDValue, 8> Ops; 5430 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5431 i += NumInputsPerOutput) { 5432 bool isLE = TLI.isLittleEndian(); 5433 APInt NewBits = APInt(DstBitSize, 0); 5434 bool EltIsUndef = true; 5435 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5436 // Shift the previously computed bits over. 5437 NewBits <<= SrcBitSize; 5438 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5439 if (Op.getOpcode() == ISD::UNDEF) continue; 5440 EltIsUndef = false; 5441 5442 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5443 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5444 } 5445 5446 if (EltIsUndef) 5447 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5448 else 5449 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5450 } 5451 5452 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5453 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5454 &Ops[0], Ops.size()); 5455 } 5456 5457 // Finally, this must be the case where we are shrinking elements: each input 5458 // turns into multiple outputs. 5459 bool isS2V = ISD::isScalarToVector(BV); 5460 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5461 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5462 NumOutputsPerInput*BV->getNumOperands()); 5463 SmallVector<SDValue, 8> Ops; 5464 5465 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5466 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5467 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5468 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5469 continue; 5470 } 5471 5472 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5473 getAPIntValue().zextOrTrunc(SrcBitSize); 5474 5475 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5476 APInt ThisVal = OpVal.trunc(DstBitSize); 5477 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5478 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5479 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5480 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5481 Ops[0]); 5482 OpVal = OpVal.lshr(DstBitSize); 5483 } 5484 5485 // For big endian targets, swap the order of the pieces of each element. 5486 if (TLI.isBigEndian()) 5487 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5488 } 5489 5490 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5491 &Ops[0], Ops.size()); 5492} 5493 5494SDValue DAGCombiner::visitFADD(SDNode *N) { 5495 SDValue N0 = N->getOperand(0); 5496 SDValue N1 = N->getOperand(1); 5497 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5498 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5499 EVT VT = N->getValueType(0); 5500 5501 // fold vector ops 5502 if (VT.isVector()) { 5503 SDValue FoldedVOp = SimplifyVBinOp(N); 5504 if (FoldedVOp.getNode()) return FoldedVOp; 5505 } 5506 5507 // fold (fadd c1, c2) -> (fadd c1, c2) 5508 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5509 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5510 // canonicalize constant to RHS 5511 if (N0CFP && !N1CFP) 5512 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5513 // fold (fadd A, 0) -> A 5514 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5515 N1CFP->getValueAPF().isZero()) 5516 return N0; 5517 // fold (fadd A, (fneg B)) -> (fsub A, B) 5518 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5519 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5520 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5521 GetNegatedExpression(N1, DAG, LegalOperations)); 5522 // fold (fadd (fneg A), B) -> (fsub B, A) 5523 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5524 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5525 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5526 GetNegatedExpression(N0, DAG, LegalOperations)); 5527 5528 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5529 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5530 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5531 isa<ConstantFPSDNode>(N0.getOperand(1))) 5532 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5533 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5534 N0.getOperand(1), N1)); 5535 5536 return SDValue(); 5537} 5538 5539SDValue DAGCombiner::visitFSUB(SDNode *N) { 5540 SDValue N0 = N->getOperand(0); 5541 SDValue N1 = N->getOperand(1); 5542 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5543 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5544 EVT VT = N->getValueType(0); 5545 5546 // fold vector ops 5547 if (VT.isVector()) { 5548 SDValue FoldedVOp = SimplifyVBinOp(N); 5549 if (FoldedVOp.getNode()) return FoldedVOp; 5550 } 5551 5552 // fold (fsub c1, c2) -> c1-c2 5553 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5554 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5555 // fold (fsub A, 0) -> A 5556 if (DAG.getTarget().Options.UnsafeFPMath && 5557 N1CFP && N1CFP->getValueAPF().isZero()) 5558 return N0; 5559 // fold (fsub 0, B) -> -B 5560 if (DAG.getTarget().Options.UnsafeFPMath && 5561 N0CFP && N0CFP->getValueAPF().isZero()) { 5562 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5563 return GetNegatedExpression(N1, DAG, LegalOperations); 5564 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5565 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5566 } 5567 // fold (fsub A, (fneg B)) -> (fadd A, B) 5568 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5569 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5570 GetNegatedExpression(N1, DAG, LegalOperations)); 5571 5572 return SDValue(); 5573} 5574 5575SDValue DAGCombiner::visitFMUL(SDNode *N) { 5576 SDValue N0 = N->getOperand(0); 5577 SDValue N1 = N->getOperand(1); 5578 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5579 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5580 EVT VT = N->getValueType(0); 5581 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5582 5583 // fold vector ops 5584 if (VT.isVector()) { 5585 SDValue FoldedVOp = SimplifyVBinOp(N); 5586 if (FoldedVOp.getNode()) return FoldedVOp; 5587 } 5588 5589 // fold (fmul c1, c2) -> c1*c2 5590 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5591 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5592 // canonicalize constant to RHS 5593 if (N0CFP && !N1CFP) 5594 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5595 // fold (fmul A, 0) -> 0 5596 if (DAG.getTarget().Options.UnsafeFPMath && 5597 N1CFP && N1CFP->getValueAPF().isZero()) 5598 return N1; 5599 // fold (fmul A, 0) -> 0, vector edition. 5600 if (DAG.getTarget().Options.UnsafeFPMath && 5601 ISD::isBuildVectorAllZeros(N1.getNode())) 5602 return N1; 5603 // fold (fmul X, 2.0) -> (fadd X, X) 5604 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5605 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5606 // fold (fmul X, -1.0) -> (fneg X) 5607 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5608 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5609 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5610 5611 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5612 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5613 &DAG.getTarget().Options)) { 5614 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5615 &DAG.getTarget().Options)) { 5616 // Both can be negated for free, check to see if at least one is cheaper 5617 // negated. 5618 if (LHSNeg == 2 || RHSNeg == 2) 5619 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5620 GetNegatedExpression(N0, DAG, LegalOperations), 5621 GetNegatedExpression(N1, DAG, LegalOperations)); 5622 } 5623 } 5624 5625 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5626 if (DAG.getTarget().Options.UnsafeFPMath && 5627 N1CFP && N0.getOpcode() == ISD::FMUL && 5628 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5629 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5630 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5631 N0.getOperand(1), N1)); 5632 5633 return SDValue(); 5634} 5635 5636SDValue DAGCombiner::visitFDIV(SDNode *N) { 5637 SDValue N0 = N->getOperand(0); 5638 SDValue N1 = N->getOperand(1); 5639 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5640 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5641 EVT VT = N->getValueType(0); 5642 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5643 5644 // fold vector ops 5645 if (VT.isVector()) { 5646 SDValue FoldedVOp = SimplifyVBinOp(N); 5647 if (FoldedVOp.getNode()) return FoldedVOp; 5648 } 5649 5650 // fold (fdiv c1, c2) -> c1/c2 5651 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5652 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5653 5654 5655 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5656 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5657 &DAG.getTarget().Options)) { 5658 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5659 &DAG.getTarget().Options)) { 5660 // Both can be negated for free, check to see if at least one is cheaper 5661 // negated. 5662 if (LHSNeg == 2 || RHSNeg == 2) 5663 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5664 GetNegatedExpression(N0, DAG, LegalOperations), 5665 GetNegatedExpression(N1, DAG, LegalOperations)); 5666 } 5667 } 5668 5669 return SDValue(); 5670} 5671 5672SDValue DAGCombiner::visitFREM(SDNode *N) { 5673 SDValue N0 = N->getOperand(0); 5674 SDValue N1 = N->getOperand(1); 5675 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5676 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5677 EVT VT = N->getValueType(0); 5678 5679 // fold (frem c1, c2) -> fmod(c1,c2) 5680 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5681 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5682 5683 return SDValue(); 5684} 5685 5686SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5687 SDValue N0 = N->getOperand(0); 5688 SDValue N1 = N->getOperand(1); 5689 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5690 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5691 EVT VT = N->getValueType(0); 5692 5693 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5694 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5695 5696 if (N1CFP) { 5697 const APFloat& V = N1CFP->getValueAPF(); 5698 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5699 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5700 if (!V.isNegative()) { 5701 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5702 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5703 } else { 5704 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5705 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5706 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5707 } 5708 } 5709 5710 // copysign(fabs(x), y) -> copysign(x, y) 5711 // copysign(fneg(x), y) -> copysign(x, y) 5712 // copysign(copysign(x,z), y) -> copysign(x, y) 5713 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5714 N0.getOpcode() == ISD::FCOPYSIGN) 5715 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5716 N0.getOperand(0), N1); 5717 5718 // copysign(x, abs(y)) -> abs(x) 5719 if (N1.getOpcode() == ISD::FABS) 5720 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5721 5722 // copysign(x, copysign(y,z)) -> copysign(x, z) 5723 if (N1.getOpcode() == ISD::FCOPYSIGN) 5724 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5725 N0, N1.getOperand(1)); 5726 5727 // copysign(x, fp_extend(y)) -> copysign(x, y) 5728 // copysign(x, fp_round(y)) -> copysign(x, y) 5729 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5730 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5731 N0, N1.getOperand(0)); 5732 5733 return SDValue(); 5734} 5735 5736SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5737 SDValue N0 = N->getOperand(0); 5738 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5739 EVT VT = N->getValueType(0); 5740 EVT OpVT = N0.getValueType(); 5741 5742 // fold (sint_to_fp c1) -> c1fp 5743 if (N0C && OpVT != MVT::ppcf128 && 5744 // ...but only if the target supports immediate floating-point values 5745 (!LegalOperations || 5746 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5747 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5748 5749 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5750 // but UINT_TO_FP is legal on this target, try to convert. 5751 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5752 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5753 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5754 if (DAG.SignBitIsZero(N0)) 5755 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5756 } 5757 5758 return SDValue(); 5759} 5760 5761SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5762 SDValue N0 = N->getOperand(0); 5763 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5764 EVT VT = N->getValueType(0); 5765 EVT OpVT = N0.getValueType(); 5766 5767 // fold (uint_to_fp c1) -> c1fp 5768 if (N0C && OpVT != MVT::ppcf128 && 5769 // ...but only if the target supports immediate floating-point values 5770 (!LegalOperations || 5771 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5772 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5773 5774 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5775 // but SINT_TO_FP is legal on this target, try to convert. 5776 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5777 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5778 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5779 if (DAG.SignBitIsZero(N0)) 5780 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5781 } 5782 5783 return SDValue(); 5784} 5785 5786SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5787 SDValue N0 = N->getOperand(0); 5788 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5789 EVT VT = N->getValueType(0); 5790 5791 // fold (fp_to_sint c1fp) -> c1 5792 if (N0CFP) 5793 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5794 5795 return SDValue(); 5796} 5797 5798SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5799 SDValue N0 = N->getOperand(0); 5800 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5801 EVT VT = N->getValueType(0); 5802 5803 // fold (fp_to_uint c1fp) -> c1 5804 if (N0CFP && VT != MVT::ppcf128) 5805 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5806 5807 return SDValue(); 5808} 5809 5810SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5811 SDValue N0 = N->getOperand(0); 5812 SDValue N1 = N->getOperand(1); 5813 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5814 EVT VT = N->getValueType(0); 5815 5816 // fold (fp_round c1fp) -> c1fp 5817 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5818 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5819 5820 // fold (fp_round (fp_extend x)) -> x 5821 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5822 return N0.getOperand(0); 5823 5824 // fold (fp_round (fp_round x)) -> (fp_round x) 5825 if (N0.getOpcode() == ISD::FP_ROUND) { 5826 // This is a value preserving truncation if both round's are. 5827 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5828 N0.getNode()->getConstantOperandVal(1) == 1; 5829 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5830 DAG.getIntPtrConstant(IsTrunc)); 5831 } 5832 5833 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5834 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5835 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5836 N0.getOperand(0), N1); 5837 AddToWorkList(Tmp.getNode()); 5838 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5839 Tmp, N0.getOperand(1)); 5840 } 5841 5842 return SDValue(); 5843} 5844 5845SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5846 SDValue N0 = N->getOperand(0); 5847 EVT VT = N->getValueType(0); 5848 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5849 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5850 5851 // fold (fp_round_inreg c1fp) -> c1fp 5852 if (N0CFP && isTypeLegal(EVT)) { 5853 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5854 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5855 } 5856 5857 return SDValue(); 5858} 5859 5860SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5861 SDValue N0 = N->getOperand(0); 5862 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5863 EVT VT = N->getValueType(0); 5864 5865 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5866 if (N->hasOneUse() && 5867 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5868 return SDValue(); 5869 5870 // fold (fp_extend c1fp) -> c1fp 5871 if (N0CFP && VT != MVT::ppcf128) 5872 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5873 5874 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5875 // value of X. 5876 if (N0.getOpcode() == ISD::FP_ROUND 5877 && N0.getNode()->getConstantOperandVal(1) == 1) { 5878 SDValue In = N0.getOperand(0); 5879 if (In.getValueType() == VT) return In; 5880 if (VT.bitsLT(In.getValueType())) 5881 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5882 In, N0.getOperand(1)); 5883 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5884 } 5885 5886 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5887 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5888 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5889 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5890 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5891 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5892 LN0->getChain(), 5893 LN0->getBasePtr(), LN0->getPointerInfo(), 5894 N0.getValueType(), 5895 LN0->isVolatile(), LN0->isNonTemporal(), 5896 LN0->getAlignment()); 5897 CombineTo(N, ExtLoad); 5898 CombineTo(N0.getNode(), 5899 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5900 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5901 ExtLoad.getValue(1)); 5902 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5903 } 5904 5905 return SDValue(); 5906} 5907 5908SDValue DAGCombiner::visitFNEG(SDNode *N) { 5909 SDValue N0 = N->getOperand(0); 5910 EVT VT = N->getValueType(0); 5911 5912 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 5913 &DAG.getTarget().Options)) 5914 return GetNegatedExpression(N0, DAG, LegalOperations); 5915 5916 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5917 // constant pool values. 5918 if (N0.getOpcode() == ISD::BITCAST && 5919 !VT.isVector() && 5920 N0.getNode()->hasOneUse() && 5921 N0.getOperand(0).getValueType().isInteger()) { 5922 SDValue Int = N0.getOperand(0); 5923 EVT IntVT = Int.getValueType(); 5924 if (IntVT.isInteger() && !IntVT.isVector()) { 5925 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5926 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5927 AddToWorkList(Int.getNode()); 5928 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5929 VT, Int); 5930 } 5931 } 5932 5933 return SDValue(); 5934} 5935 5936SDValue DAGCombiner::visitFABS(SDNode *N) { 5937 SDValue N0 = N->getOperand(0); 5938 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5939 EVT VT = N->getValueType(0); 5940 5941 // fold (fabs c1) -> fabs(c1) 5942 if (N0CFP && VT != MVT::ppcf128) 5943 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5944 // fold (fabs (fabs x)) -> (fabs x) 5945 if (N0.getOpcode() == ISD::FABS) 5946 return N->getOperand(0); 5947 // fold (fabs (fneg x)) -> (fabs x) 5948 // fold (fabs (fcopysign x, y)) -> (fabs x) 5949 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5950 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5951 5952 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5953 // constant pool values. 5954 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5955 N0.getOperand(0).getValueType().isInteger() && 5956 !N0.getOperand(0).getValueType().isVector()) { 5957 SDValue Int = N0.getOperand(0); 5958 EVT IntVT = Int.getValueType(); 5959 if (IntVT.isInteger() && !IntVT.isVector()) { 5960 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5961 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5962 AddToWorkList(Int.getNode()); 5963 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5964 N->getValueType(0), Int); 5965 } 5966 } 5967 5968 return SDValue(); 5969} 5970 5971SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5972 SDValue Chain = N->getOperand(0); 5973 SDValue N1 = N->getOperand(1); 5974 SDValue N2 = N->getOperand(2); 5975 5976 // If N is a constant we could fold this into a fallthrough or unconditional 5977 // branch. However that doesn't happen very often in normal code, because 5978 // Instcombine/SimplifyCFG should have handled the available opportunities. 5979 // If we did this folding here, it would be necessary to update the 5980 // MachineBasicBlock CFG, which is awkward. 5981 5982 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5983 // on the target. 5984 if (N1.getOpcode() == ISD::SETCC && 5985 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5986 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5987 Chain, N1.getOperand(2), 5988 N1.getOperand(0), N1.getOperand(1), N2); 5989 } 5990 5991 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5992 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5993 (N1.getOperand(0).hasOneUse() && 5994 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5995 SDNode *Trunc = 0; 5996 if (N1.getOpcode() == ISD::TRUNCATE) { 5997 // Look pass the truncate. 5998 Trunc = N1.getNode(); 5999 N1 = N1.getOperand(0); 6000 } 6001 6002 // Match this pattern so that we can generate simpler code: 6003 // 6004 // %a = ... 6005 // %b = and i32 %a, 2 6006 // %c = srl i32 %b, 1 6007 // brcond i32 %c ... 6008 // 6009 // into 6010 // 6011 // %a = ... 6012 // %b = and i32 %a, 2 6013 // %c = setcc eq %b, 0 6014 // brcond %c ... 6015 // 6016 // This applies only when the AND constant value has one bit set and the 6017 // SRL constant is equal to the log2 of the AND constant. The back-end is 6018 // smart enough to convert the result into a TEST/JMP sequence. 6019 SDValue Op0 = N1.getOperand(0); 6020 SDValue Op1 = N1.getOperand(1); 6021 6022 if (Op0.getOpcode() == ISD::AND && 6023 Op1.getOpcode() == ISD::Constant) { 6024 SDValue AndOp1 = Op0.getOperand(1); 6025 6026 if (AndOp1.getOpcode() == ISD::Constant) { 6027 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6028 6029 if (AndConst.isPowerOf2() && 6030 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6031 SDValue SetCC = 6032 DAG.getSetCC(N->getDebugLoc(), 6033 TLI.getSetCCResultType(Op0.getValueType()), 6034 Op0, DAG.getConstant(0, Op0.getValueType()), 6035 ISD::SETNE); 6036 6037 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6038 MVT::Other, Chain, SetCC, N2); 6039 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6040 // will convert it back to (X & C1) >> C2. 6041 CombineTo(N, NewBRCond, false); 6042 // Truncate is dead. 6043 if (Trunc) { 6044 removeFromWorkList(Trunc); 6045 DAG.DeleteNode(Trunc); 6046 } 6047 // Replace the uses of SRL with SETCC 6048 WorkListRemover DeadNodes(*this); 6049 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 6050 removeFromWorkList(N1.getNode()); 6051 DAG.DeleteNode(N1.getNode()); 6052 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6053 } 6054 } 6055 } 6056 6057 if (Trunc) 6058 // Restore N1 if the above transformation doesn't match. 6059 N1 = N->getOperand(1); 6060 } 6061 6062 // Transform br(xor(x, y)) -> br(x != y) 6063 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6064 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6065 SDNode *TheXor = N1.getNode(); 6066 SDValue Op0 = TheXor->getOperand(0); 6067 SDValue Op1 = TheXor->getOperand(1); 6068 if (Op0.getOpcode() == Op1.getOpcode()) { 6069 // Avoid missing important xor optimizations. 6070 SDValue Tmp = visitXOR(TheXor); 6071 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6072 DEBUG(dbgs() << "\nReplacing.8 "; 6073 TheXor->dump(&DAG); 6074 dbgs() << "\nWith: "; 6075 Tmp.getNode()->dump(&DAG); 6076 dbgs() << '\n'); 6077 WorkListRemover DeadNodes(*this); 6078 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 6079 removeFromWorkList(TheXor); 6080 DAG.DeleteNode(TheXor); 6081 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6082 MVT::Other, Chain, Tmp, N2); 6083 } 6084 } 6085 6086 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6087 bool Equal = false; 6088 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6089 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6090 Op0.getOpcode() == ISD::XOR) { 6091 TheXor = Op0.getNode(); 6092 Equal = true; 6093 } 6094 6095 EVT SetCCVT = N1.getValueType(); 6096 if (LegalTypes) 6097 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6098 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6099 SetCCVT, 6100 Op0, Op1, 6101 Equal ? ISD::SETEQ : ISD::SETNE); 6102 // Replace the uses of XOR with SETCC 6103 WorkListRemover DeadNodes(*this); 6104 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 6105 removeFromWorkList(N1.getNode()); 6106 DAG.DeleteNode(N1.getNode()); 6107 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6108 MVT::Other, Chain, SetCC, N2); 6109 } 6110 } 6111 6112 return SDValue(); 6113} 6114 6115// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6116// 6117SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6118 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6119 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6120 6121 // If N is a constant we could fold this into a fallthrough or unconditional 6122 // branch. However that doesn't happen very often in normal code, because 6123 // Instcombine/SimplifyCFG should have handled the available opportunities. 6124 // If we did this folding here, it would be necessary to update the 6125 // MachineBasicBlock CFG, which is awkward. 6126 6127 // Use SimplifySetCC to simplify SETCC's. 6128 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6129 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6130 false); 6131 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6132 6133 // fold to a simpler setcc 6134 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6135 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6136 N->getOperand(0), Simp.getOperand(2), 6137 Simp.getOperand(0), Simp.getOperand(1), 6138 N->getOperand(4)); 6139 6140 return SDValue(); 6141} 6142 6143/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6144/// uses N as its base pointer and that N may be folded in the load / store 6145/// addressing mode. FIXME: This currently only looks for folding of 6146/// [reg +/- imm] addressing modes. 6147static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6148 SelectionDAG &DAG, 6149 const TargetLowering &TLI) { 6150 EVT VT; 6151 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6152 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6153 return false; 6154 VT = Use->getValueType(0); 6155 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6156 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6157 return false; 6158 VT = ST->getValue().getValueType(); 6159 } else 6160 return false; 6161 6162 TargetLowering::AddrMode AM; 6163 if (N->getOpcode() == ISD::ADD) { 6164 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6165 if (Offset) 6166 AM.BaseOffs = Offset->getSExtValue(); 6167 else 6168 return false; 6169 } else if (N->getOpcode() == ISD::SUB) { 6170 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6171 if (Offset) 6172 AM.BaseOffs = -Offset->getSExtValue(); 6173 else 6174 return false; 6175 } else 6176 return false; 6177 6178 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6179} 6180 6181/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6182/// pre-indexed load / store when the base pointer is an add or subtract 6183/// and it has other uses besides the load / store. After the 6184/// transformation, the new indexed load / store has effectively folded 6185/// the add / subtract in and all of its other uses are redirected to the 6186/// new load / store. 6187bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6188 if (Level < AfterLegalizeDAG) 6189 return false; 6190 6191 bool isLoad = true; 6192 SDValue Ptr; 6193 EVT VT; 6194 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6195 if (LD->isIndexed()) 6196 return false; 6197 VT = LD->getMemoryVT(); 6198 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6199 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6200 return false; 6201 Ptr = LD->getBasePtr(); 6202 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6203 if (ST->isIndexed()) 6204 return false; 6205 VT = ST->getMemoryVT(); 6206 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6207 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6208 return false; 6209 Ptr = ST->getBasePtr(); 6210 isLoad = false; 6211 } else { 6212 return false; 6213 } 6214 6215 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6216 // out. There is no reason to make this a preinc/predec. 6217 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6218 Ptr.getNode()->hasOneUse()) 6219 return false; 6220 6221 // Ask the target to do addressing mode selection. 6222 SDValue BasePtr; 6223 SDValue Offset; 6224 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6225 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6226 return false; 6227 // Don't create a indexed load / store with zero offset. 6228 if (isa<ConstantSDNode>(Offset) && 6229 cast<ConstantSDNode>(Offset)->isNullValue()) 6230 return false; 6231 6232 // Try turning it into a pre-indexed load / store except when: 6233 // 1) The new base ptr is a frame index. 6234 // 2) If N is a store and the new base ptr is either the same as or is a 6235 // predecessor of the value being stored. 6236 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6237 // that would create a cycle. 6238 // 4) All uses are load / store ops that use it as old base ptr. 6239 6240 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6241 // (plus the implicit offset) to a register to preinc anyway. 6242 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6243 return false; 6244 6245 // Check #2. 6246 if (!isLoad) { 6247 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6248 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6249 return false; 6250 } 6251 6252 // Now check for #3 and #4. 6253 bool RealUse = false; 6254 6255 // Caches for hasPredecessorHelper 6256 SmallPtrSet<const SDNode *, 32> Visited; 6257 SmallVector<const SDNode *, 16> Worklist; 6258 6259 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6260 E = Ptr.getNode()->use_end(); I != E; ++I) { 6261 SDNode *Use = *I; 6262 if (Use == N) 6263 continue; 6264 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6265 return false; 6266 6267 // If Ptr may be folded in addressing mode of other use, then it's 6268 // not profitable to do this transformation. 6269 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6270 RealUse = true; 6271 } 6272 6273 if (!RealUse) 6274 return false; 6275 6276 SDValue Result; 6277 if (isLoad) 6278 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6279 BasePtr, Offset, AM); 6280 else 6281 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6282 BasePtr, Offset, AM); 6283 ++PreIndexedNodes; 6284 ++NodesCombined; 6285 DEBUG(dbgs() << "\nReplacing.4 "; 6286 N->dump(&DAG); 6287 dbgs() << "\nWith: "; 6288 Result.getNode()->dump(&DAG); 6289 dbgs() << '\n'); 6290 WorkListRemover DeadNodes(*this); 6291 if (isLoad) { 6292 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6293 &DeadNodes); 6294 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6295 &DeadNodes); 6296 } else { 6297 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6298 &DeadNodes); 6299 } 6300 6301 // Finally, since the node is now dead, remove it from the graph. 6302 DAG.DeleteNode(N); 6303 6304 // Replace the uses of Ptr with uses of the updated base value. 6305 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 6306 &DeadNodes); 6307 removeFromWorkList(Ptr.getNode()); 6308 DAG.DeleteNode(Ptr.getNode()); 6309 6310 return true; 6311} 6312 6313/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6314/// add / sub of the base pointer node into a post-indexed load / store. 6315/// The transformation folded the add / subtract into the new indexed 6316/// load / store effectively and all of its uses are redirected to the 6317/// new load / store. 6318bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6319 if (Level < AfterLegalizeDAG) 6320 return false; 6321 6322 bool isLoad = true; 6323 SDValue Ptr; 6324 EVT VT; 6325 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6326 if (LD->isIndexed()) 6327 return false; 6328 VT = LD->getMemoryVT(); 6329 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6330 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6331 return false; 6332 Ptr = LD->getBasePtr(); 6333 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6334 if (ST->isIndexed()) 6335 return false; 6336 VT = ST->getMemoryVT(); 6337 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6338 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6339 return false; 6340 Ptr = ST->getBasePtr(); 6341 isLoad = false; 6342 } else { 6343 return false; 6344 } 6345 6346 if (Ptr.getNode()->hasOneUse()) 6347 return false; 6348 6349 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6350 E = Ptr.getNode()->use_end(); I != E; ++I) { 6351 SDNode *Op = *I; 6352 if (Op == N || 6353 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6354 continue; 6355 6356 SDValue BasePtr; 6357 SDValue Offset; 6358 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6359 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6360 // Don't create a indexed load / store with zero offset. 6361 if (isa<ConstantSDNode>(Offset) && 6362 cast<ConstantSDNode>(Offset)->isNullValue()) 6363 continue; 6364 6365 // Try turning it into a post-indexed load / store except when 6366 // 1) All uses are load / store ops that use it as base ptr (and 6367 // it may be folded as addressing mmode). 6368 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6369 // nor a successor of N. Otherwise, if Op is folded that would 6370 // create a cycle. 6371 6372 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6373 continue; 6374 6375 // Check for #1. 6376 bool TryNext = false; 6377 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6378 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6379 SDNode *Use = *II; 6380 if (Use == Ptr.getNode()) 6381 continue; 6382 6383 // If all the uses are load / store addresses, then don't do the 6384 // transformation. 6385 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6386 bool RealUse = false; 6387 for (SDNode::use_iterator III = Use->use_begin(), 6388 EEE = Use->use_end(); III != EEE; ++III) { 6389 SDNode *UseUse = *III; 6390 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6391 RealUse = true; 6392 } 6393 6394 if (!RealUse) { 6395 TryNext = true; 6396 break; 6397 } 6398 } 6399 } 6400 6401 if (TryNext) 6402 continue; 6403 6404 // Check for #2 6405 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6406 SDValue Result = isLoad 6407 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6408 BasePtr, Offset, AM) 6409 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6410 BasePtr, Offset, AM); 6411 ++PostIndexedNodes; 6412 ++NodesCombined; 6413 DEBUG(dbgs() << "\nReplacing.5 "; 6414 N->dump(&DAG); 6415 dbgs() << "\nWith: "; 6416 Result.getNode()->dump(&DAG); 6417 dbgs() << '\n'); 6418 WorkListRemover DeadNodes(*this); 6419 if (isLoad) { 6420 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6421 &DeadNodes); 6422 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6423 &DeadNodes); 6424 } else { 6425 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6426 &DeadNodes); 6427 } 6428 6429 // Finally, since the node is now dead, remove it from the graph. 6430 DAG.DeleteNode(N); 6431 6432 // Replace the uses of Use with uses of the updated base value. 6433 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6434 Result.getValue(isLoad ? 1 : 0), 6435 &DeadNodes); 6436 removeFromWorkList(Op); 6437 DAG.DeleteNode(Op); 6438 return true; 6439 } 6440 } 6441 } 6442 6443 return false; 6444} 6445 6446SDValue DAGCombiner::visitLOAD(SDNode *N) { 6447 LoadSDNode *LD = cast<LoadSDNode>(N); 6448 SDValue Chain = LD->getChain(); 6449 SDValue Ptr = LD->getBasePtr(); 6450 6451 // If load is not volatile and there are no uses of the loaded value (and 6452 // the updated indexed value in case of indexed loads), change uses of the 6453 // chain value into uses of the chain input (i.e. delete the dead load). 6454 if (!LD->isVolatile()) { 6455 if (N->getValueType(1) == MVT::Other) { 6456 // Unindexed loads. 6457 if (!N->hasAnyUseOfValue(0)) { 6458 // It's not safe to use the two value CombineTo variant here. e.g. 6459 // v1, chain2 = load chain1, loc 6460 // v2, chain3 = load chain2, loc 6461 // v3 = add v2, c 6462 // Now we replace use of chain2 with chain1. This makes the second load 6463 // isomorphic to the one we are deleting, and thus makes this load live. 6464 DEBUG(dbgs() << "\nReplacing.6 "; 6465 N->dump(&DAG); 6466 dbgs() << "\nWith chain: "; 6467 Chain.getNode()->dump(&DAG); 6468 dbgs() << "\n"); 6469 WorkListRemover DeadNodes(*this); 6470 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 6471 6472 if (N->use_empty()) { 6473 removeFromWorkList(N); 6474 DAG.DeleteNode(N); 6475 } 6476 6477 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6478 } 6479 } else { 6480 // Indexed loads. 6481 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 6482 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 6483 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 6484 DEBUG(dbgs() << "\nReplacing.7 "; 6485 N->dump(&DAG); 6486 dbgs() << "\nWith: "; 6487 Undef.getNode()->dump(&DAG); 6488 dbgs() << " and 2 other values\n"); 6489 WorkListRemover DeadNodes(*this); 6490 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 6491 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 6492 DAG.getUNDEF(N->getValueType(1)), 6493 &DeadNodes); 6494 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 6495 removeFromWorkList(N); 6496 DAG.DeleteNode(N); 6497 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6498 } 6499 } 6500 } 6501 6502 // If this load is directly stored, replace the load value with the stored 6503 // value. 6504 // TODO: Handle store large -> read small portion. 6505 // TODO: Handle TRUNCSTORE/LOADEXT 6506 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 6507 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 6508 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 6509 if (PrevST->getBasePtr() == Ptr && 6510 PrevST->getValue().getValueType() == N->getValueType(0)) 6511 return CombineTo(N, Chain.getOperand(1), Chain); 6512 } 6513 } 6514 6515 // Try to infer better alignment information than the load already has. 6516 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 6517 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6518 if (Align > LD->getAlignment()) 6519 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 6520 LD->getValueType(0), 6521 Chain, Ptr, LD->getPointerInfo(), 6522 LD->getMemoryVT(), 6523 LD->isVolatile(), LD->isNonTemporal(), Align); 6524 } 6525 } 6526 6527 if (CombinerAA) { 6528 // Walk up chain skipping non-aliasing memory nodes. 6529 SDValue BetterChain = FindBetterChain(N, Chain); 6530 6531 // If there is a better chain. 6532 if (Chain != BetterChain) { 6533 SDValue ReplLoad; 6534 6535 // Replace the chain to void dependency. 6536 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 6537 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 6538 BetterChain, Ptr, LD->getPointerInfo(), 6539 LD->isVolatile(), LD->isNonTemporal(), 6540 LD->isInvariant(), LD->getAlignment()); 6541 } else { 6542 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 6543 LD->getValueType(0), 6544 BetterChain, Ptr, LD->getPointerInfo(), 6545 LD->getMemoryVT(), 6546 LD->isVolatile(), 6547 LD->isNonTemporal(), 6548 LD->getAlignment()); 6549 } 6550 6551 // Create token factor to keep old chain connected. 6552 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6553 MVT::Other, Chain, ReplLoad.getValue(1)); 6554 6555 // Make sure the new and old chains are cleaned up. 6556 AddToWorkList(Token.getNode()); 6557 6558 // Replace uses with load result and token factor. Don't add users 6559 // to work list. 6560 return CombineTo(N, ReplLoad.getValue(0), Token, false); 6561 } 6562 } 6563 6564 // Try transforming N to an indexed load. 6565 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6566 return SDValue(N, 0); 6567 6568 return SDValue(); 6569} 6570 6571/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 6572/// load is having specific bytes cleared out. If so, return the byte size 6573/// being masked out and the shift amount. 6574static std::pair<unsigned, unsigned> 6575CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 6576 std::pair<unsigned, unsigned> Result(0, 0); 6577 6578 // Check for the structure we're looking for. 6579 if (V->getOpcode() != ISD::AND || 6580 !isa<ConstantSDNode>(V->getOperand(1)) || 6581 !ISD::isNormalLoad(V->getOperand(0).getNode())) 6582 return Result; 6583 6584 // Check the chain and pointer. 6585 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 6586 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 6587 6588 // The store should be chained directly to the load or be an operand of a 6589 // tokenfactor. 6590 if (LD == Chain.getNode()) 6591 ; // ok. 6592 else if (Chain->getOpcode() != ISD::TokenFactor) 6593 return Result; // Fail. 6594 else { 6595 bool isOk = false; 6596 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 6597 if (Chain->getOperand(i).getNode() == LD) { 6598 isOk = true; 6599 break; 6600 } 6601 if (!isOk) return Result; 6602 } 6603 6604 // This only handles simple types. 6605 if (V.getValueType() != MVT::i16 && 6606 V.getValueType() != MVT::i32 && 6607 V.getValueType() != MVT::i64) 6608 return Result; 6609 6610 // Check the constant mask. Invert it so that the bits being masked out are 6611 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6612 // follow the sign bit for uniformity. 6613 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6614 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6615 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6616 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6617 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6618 if (NotMaskLZ == 64) return Result; // All zero mask. 6619 6620 // See if we have a continuous run of bits. If so, we have 0*1+0* 6621 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6622 return Result; 6623 6624 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6625 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6626 NotMaskLZ -= 64-V.getValueSizeInBits(); 6627 6628 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6629 switch (MaskedBytes) { 6630 case 1: 6631 case 2: 6632 case 4: break; 6633 default: return Result; // All one mask, or 5-byte mask. 6634 } 6635 6636 // Verify that the first bit starts at a multiple of mask so that the access 6637 // is aligned the same as the access width. 6638 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6639 6640 Result.first = MaskedBytes; 6641 Result.second = NotMaskTZ/8; 6642 return Result; 6643} 6644 6645 6646/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6647/// provides a value as specified by MaskInfo. If so, replace the specified 6648/// store with a narrower store of truncated IVal. 6649static SDNode * 6650ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6651 SDValue IVal, StoreSDNode *St, 6652 DAGCombiner *DC) { 6653 unsigned NumBytes = MaskInfo.first; 6654 unsigned ByteShift = MaskInfo.second; 6655 SelectionDAG &DAG = DC->getDAG(); 6656 6657 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6658 // that uses this. If not, this is not a replacement. 6659 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6660 ByteShift*8, (ByteShift+NumBytes)*8); 6661 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6662 6663 // Check that it is legal on the target to do this. It is legal if the new 6664 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6665 // legalization. 6666 MVT VT = MVT::getIntegerVT(NumBytes*8); 6667 if (!DC->isTypeLegal(VT)) 6668 return 0; 6669 6670 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6671 // shifted by ByteShift and truncated down to NumBytes. 6672 if (ByteShift) 6673 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6674 DAG.getConstant(ByteShift*8, 6675 DC->getShiftAmountTy(IVal.getValueType()))); 6676 6677 // Figure out the offset for the store and the alignment of the access. 6678 unsigned StOffset; 6679 unsigned NewAlign = St->getAlignment(); 6680 6681 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6682 StOffset = ByteShift; 6683 else 6684 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6685 6686 SDValue Ptr = St->getBasePtr(); 6687 if (StOffset) { 6688 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6689 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6690 NewAlign = MinAlign(NewAlign, StOffset); 6691 } 6692 6693 // Truncate down to the new size. 6694 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6695 6696 ++OpsNarrowed; 6697 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6698 St->getPointerInfo().getWithOffset(StOffset), 6699 false, false, NewAlign).getNode(); 6700} 6701 6702 6703/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6704/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6705/// of the loaded bits, try narrowing the load and store if it would end up 6706/// being a win for performance or code size. 6707SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6708 StoreSDNode *ST = cast<StoreSDNode>(N); 6709 if (ST->isVolatile()) 6710 return SDValue(); 6711 6712 SDValue Chain = ST->getChain(); 6713 SDValue Value = ST->getValue(); 6714 SDValue Ptr = ST->getBasePtr(); 6715 EVT VT = Value.getValueType(); 6716 6717 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6718 return SDValue(); 6719 6720 unsigned Opc = Value.getOpcode(); 6721 6722 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6723 // is a byte mask indicating a consecutive number of bytes, check to see if 6724 // Y is known to provide just those bytes. If so, we try to replace the 6725 // load + replace + store sequence with a single (narrower) store, which makes 6726 // the load dead. 6727 if (Opc == ISD::OR) { 6728 std::pair<unsigned, unsigned> MaskedLoad; 6729 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6730 if (MaskedLoad.first) 6731 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6732 Value.getOperand(1), ST,this)) 6733 return SDValue(NewST, 0); 6734 6735 // Or is commutative, so try swapping X and Y. 6736 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6737 if (MaskedLoad.first) 6738 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6739 Value.getOperand(0), ST,this)) 6740 return SDValue(NewST, 0); 6741 } 6742 6743 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6744 Value.getOperand(1).getOpcode() != ISD::Constant) 6745 return SDValue(); 6746 6747 SDValue N0 = Value.getOperand(0); 6748 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6749 Chain == SDValue(N0.getNode(), 1)) { 6750 LoadSDNode *LD = cast<LoadSDNode>(N0); 6751 if (LD->getBasePtr() != Ptr || 6752 LD->getPointerInfo().getAddrSpace() != 6753 ST->getPointerInfo().getAddrSpace()) 6754 return SDValue(); 6755 6756 // Find the type to narrow it the load / op / store to. 6757 SDValue N1 = Value.getOperand(1); 6758 unsigned BitWidth = N1.getValueSizeInBits(); 6759 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6760 if (Opc == ISD::AND) 6761 Imm ^= APInt::getAllOnesValue(BitWidth); 6762 if (Imm == 0 || Imm.isAllOnesValue()) 6763 return SDValue(); 6764 unsigned ShAmt = Imm.countTrailingZeros(); 6765 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6766 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6767 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6768 while (NewBW < BitWidth && 6769 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6770 TLI.isNarrowingProfitable(VT, NewVT))) { 6771 NewBW = NextPowerOf2(NewBW); 6772 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6773 } 6774 if (NewBW >= BitWidth) 6775 return SDValue(); 6776 6777 // If the lsb changed does not start at the type bitwidth boundary, 6778 // start at the previous one. 6779 if (ShAmt % NewBW) 6780 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6781 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6782 if ((Imm & Mask) == Imm) { 6783 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6784 if (Opc == ISD::AND) 6785 NewImm ^= APInt::getAllOnesValue(NewBW); 6786 uint64_t PtrOff = ShAmt / 8; 6787 // For big endian targets, we need to adjust the offset to the pointer to 6788 // load the correct bytes. 6789 if (TLI.isBigEndian()) 6790 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6791 6792 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6793 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6794 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6795 return SDValue(); 6796 6797 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6798 Ptr.getValueType(), Ptr, 6799 DAG.getConstant(PtrOff, Ptr.getValueType())); 6800 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6801 LD->getChain(), NewPtr, 6802 LD->getPointerInfo().getWithOffset(PtrOff), 6803 LD->isVolatile(), LD->isNonTemporal(), 6804 LD->isInvariant(), NewAlign); 6805 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6806 DAG.getConstant(NewImm, NewVT)); 6807 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6808 NewVal, NewPtr, 6809 ST->getPointerInfo().getWithOffset(PtrOff), 6810 false, false, NewAlign); 6811 6812 AddToWorkList(NewPtr.getNode()); 6813 AddToWorkList(NewLD.getNode()); 6814 AddToWorkList(NewVal.getNode()); 6815 WorkListRemover DeadNodes(*this); 6816 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6817 &DeadNodes); 6818 ++OpsNarrowed; 6819 return NewST; 6820 } 6821 } 6822 6823 return SDValue(); 6824} 6825 6826/// TransformFPLoadStorePair - For a given floating point load / store pair, 6827/// if the load value isn't used by any other operations, then consider 6828/// transforming the pair to integer load / store operations if the target 6829/// deems the transformation profitable. 6830SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6831 StoreSDNode *ST = cast<StoreSDNode>(N); 6832 SDValue Chain = ST->getChain(); 6833 SDValue Value = ST->getValue(); 6834 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6835 Value.hasOneUse() && 6836 Chain == SDValue(Value.getNode(), 1)) { 6837 LoadSDNode *LD = cast<LoadSDNode>(Value); 6838 EVT VT = LD->getMemoryVT(); 6839 if (!VT.isFloatingPoint() || 6840 VT != ST->getMemoryVT() || 6841 LD->isNonTemporal() || 6842 ST->isNonTemporal() || 6843 LD->getPointerInfo().getAddrSpace() != 0 || 6844 ST->getPointerInfo().getAddrSpace() != 0) 6845 return SDValue(); 6846 6847 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6848 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6849 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6850 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6851 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6852 return SDValue(); 6853 6854 unsigned LDAlign = LD->getAlignment(); 6855 unsigned STAlign = ST->getAlignment(); 6856 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6857 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6858 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6859 return SDValue(); 6860 6861 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6862 LD->getChain(), LD->getBasePtr(), 6863 LD->getPointerInfo(), 6864 false, false, false, LDAlign); 6865 6866 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6867 NewLD, ST->getBasePtr(), 6868 ST->getPointerInfo(), 6869 false, false, STAlign); 6870 6871 AddToWorkList(NewLD.getNode()); 6872 AddToWorkList(NewST.getNode()); 6873 WorkListRemover DeadNodes(*this); 6874 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6875 &DeadNodes); 6876 ++LdStFP2Int; 6877 return NewST; 6878 } 6879 6880 return SDValue(); 6881} 6882 6883SDValue DAGCombiner::visitSTORE(SDNode *N) { 6884 StoreSDNode *ST = cast<StoreSDNode>(N); 6885 SDValue Chain = ST->getChain(); 6886 SDValue Value = ST->getValue(); 6887 SDValue Ptr = ST->getBasePtr(); 6888 6889 // If this is a store of a bit convert, store the input value if the 6890 // resultant store does not need a higher alignment than the original. 6891 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6892 ST->isUnindexed()) { 6893 unsigned OrigAlign = ST->getAlignment(); 6894 EVT SVT = Value.getOperand(0).getValueType(); 6895 unsigned Align = TLI.getTargetData()-> 6896 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6897 if (Align <= OrigAlign && 6898 ((!LegalOperations && !ST->isVolatile()) || 6899 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6900 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6901 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6902 ST->isNonTemporal(), OrigAlign); 6903 } 6904 6905 // Turn 'store undef, Ptr' -> nothing. 6906 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6907 return Chain; 6908 6909 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6910 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6911 // NOTE: If the original store is volatile, this transform must not increase 6912 // the number of stores. For example, on x86-32 an f64 can be stored in one 6913 // processor operation but an i64 (which is not legal) requires two. So the 6914 // transform should not be done in this case. 6915 if (Value.getOpcode() != ISD::TargetConstantFP) { 6916 SDValue Tmp; 6917 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6918 default: llvm_unreachable("Unknown FP type"); 6919 case MVT::f80: // We don't do this for these yet. 6920 case MVT::f128: 6921 case MVT::ppcf128: 6922 break; 6923 case MVT::f32: 6924 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6925 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6926 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6927 bitcastToAPInt().getZExtValue(), MVT::i32); 6928 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6929 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6930 ST->isNonTemporal(), ST->getAlignment()); 6931 } 6932 break; 6933 case MVT::f64: 6934 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6935 !ST->isVolatile()) || 6936 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6937 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6938 getZExtValue(), MVT::i64); 6939 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6940 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6941 ST->isNonTemporal(), ST->getAlignment()); 6942 } 6943 6944 if (!ST->isVolatile() && 6945 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6946 // Many FP stores are not made apparent until after legalize, e.g. for 6947 // argument passing. Since this is so common, custom legalize the 6948 // 64-bit integer store into two 32-bit stores. 6949 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6950 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6951 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6952 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6953 6954 unsigned Alignment = ST->getAlignment(); 6955 bool isVolatile = ST->isVolatile(); 6956 bool isNonTemporal = ST->isNonTemporal(); 6957 6958 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6959 Ptr, ST->getPointerInfo(), 6960 isVolatile, isNonTemporal, 6961 ST->getAlignment()); 6962 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6963 DAG.getConstant(4, Ptr.getValueType())); 6964 Alignment = MinAlign(Alignment, 4U); 6965 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6966 Ptr, ST->getPointerInfo().getWithOffset(4), 6967 isVolatile, isNonTemporal, 6968 Alignment); 6969 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6970 St0, St1); 6971 } 6972 6973 break; 6974 } 6975 } 6976 } 6977 6978 // Try to infer better alignment information than the store already has. 6979 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6980 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6981 if (Align > ST->getAlignment()) 6982 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6983 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6984 ST->isVolatile(), ST->isNonTemporal(), Align); 6985 } 6986 } 6987 6988 // Try transforming a pair floating point load / store ops to integer 6989 // load / store ops. 6990 SDValue NewST = TransformFPLoadStorePair(N); 6991 if (NewST.getNode()) 6992 return NewST; 6993 6994 if (CombinerAA) { 6995 // Walk up chain skipping non-aliasing memory nodes. 6996 SDValue BetterChain = FindBetterChain(N, Chain); 6997 6998 // If there is a better chain. 6999 if (Chain != BetterChain) { 7000 SDValue ReplStore; 7001 7002 // Replace the chain to avoid dependency. 7003 if (ST->isTruncatingStore()) { 7004 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7005 ST->getPointerInfo(), 7006 ST->getMemoryVT(), ST->isVolatile(), 7007 ST->isNonTemporal(), ST->getAlignment()); 7008 } else { 7009 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7010 ST->getPointerInfo(), 7011 ST->isVolatile(), ST->isNonTemporal(), 7012 ST->getAlignment()); 7013 } 7014 7015 // Create token to keep both nodes around. 7016 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7017 MVT::Other, Chain, ReplStore); 7018 7019 // Make sure the new and old chains are cleaned up. 7020 AddToWorkList(Token.getNode()); 7021 7022 // Don't add users to work list. 7023 return CombineTo(N, Token, false); 7024 } 7025 } 7026 7027 // Try transforming N to an indexed store. 7028 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7029 return SDValue(N, 0); 7030 7031 // FIXME: is there such a thing as a truncating indexed store? 7032 if (ST->isTruncatingStore() && ST->isUnindexed() && 7033 Value.getValueType().isInteger()) { 7034 // See if we can simplify the input to this truncstore with knowledge that 7035 // only the low bits are being used. For example: 7036 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 7037 SDValue Shorter = 7038 GetDemandedBits(Value, 7039 APInt::getLowBitsSet( 7040 Value.getValueType().getScalarType().getSizeInBits(), 7041 ST->getMemoryVT().getScalarType().getSizeInBits())); 7042 AddToWorkList(Value.getNode()); 7043 if (Shorter.getNode()) 7044 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 7045 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7046 ST->isVolatile(), ST->isNonTemporal(), 7047 ST->getAlignment()); 7048 7049 // Otherwise, see if we can simplify the operation with 7050 // SimplifyDemandedBits, which only works if the value has a single use. 7051 if (SimplifyDemandedBits(Value, 7052 APInt::getLowBitsSet( 7053 Value.getValueType().getScalarType().getSizeInBits(), 7054 ST->getMemoryVT().getScalarType().getSizeInBits()))) 7055 return SDValue(N, 0); 7056 } 7057 7058 // If this is a load followed by a store to the same location, then the store 7059 // is dead/noop. 7060 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 7061 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 7062 ST->isUnindexed() && !ST->isVolatile() && 7063 // There can't be any side effects between the load and store, such as 7064 // a call or store. 7065 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 7066 // The store is dead, remove it. 7067 return Chain; 7068 } 7069 } 7070 7071 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 7072 // truncating store. We can do this even if this is already a truncstore. 7073 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 7074 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 7075 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 7076 ST->getMemoryVT())) { 7077 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7078 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7079 ST->isVolatile(), ST->isNonTemporal(), 7080 ST->getAlignment()); 7081 } 7082 7083 return ReduceLoadOpStoreWidth(N); 7084} 7085 7086SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 7087 SDValue InVec = N->getOperand(0); 7088 SDValue InVal = N->getOperand(1); 7089 SDValue EltNo = N->getOperand(2); 7090 DebugLoc dl = N->getDebugLoc(); 7091 7092 // If the inserted element is an UNDEF, just use the input vector. 7093 if (InVal.getOpcode() == ISD::UNDEF) 7094 return InVec; 7095 7096 EVT VT = InVec.getValueType(); 7097 7098 // If we can't generate a legal BUILD_VECTOR, exit 7099 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 7100 return SDValue(); 7101 7102 // Check that we know which element is being inserted 7103 if (!isa<ConstantSDNode>(EltNo)) 7104 return SDValue(); 7105 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7106 7107 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 7108 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 7109 // vector elements. 7110 SmallVector<SDValue, 8> Ops; 7111 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 7112 Ops.append(InVec.getNode()->op_begin(), 7113 InVec.getNode()->op_end()); 7114 } else if (InVec.getOpcode() == ISD::UNDEF) { 7115 unsigned NElts = VT.getVectorNumElements(); 7116 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 7117 } else { 7118 return SDValue(); 7119 } 7120 7121 // Insert the element 7122 if (Elt < Ops.size()) { 7123 // All the operands of BUILD_VECTOR must have the same type; 7124 // we enforce that here. 7125 EVT OpVT = Ops[0].getValueType(); 7126 if (InVal.getValueType() != OpVT) 7127 InVal = OpVT.bitsGT(InVal.getValueType()) ? 7128 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 7129 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 7130 Ops[Elt] = InVal; 7131 } 7132 7133 // Return the new vector 7134 return DAG.getNode(ISD::BUILD_VECTOR, dl, 7135 VT, &Ops[0], Ops.size()); 7136} 7137 7138SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 7139 // (vextract (scalar_to_vector val, 0) -> val 7140 SDValue InVec = N->getOperand(0); 7141 EVT VT = InVec.getValueType(); 7142 EVT NVT = N->getValueType(0); 7143 7144 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 7145 // Check if the result type doesn't match the inserted element type. A 7146 // SCALAR_TO_VECTOR may truncate the inserted element and the 7147 // EXTRACT_VECTOR_ELT may widen the extracted vector. 7148 SDValue InOp = InVec.getOperand(0); 7149 if (InOp.getValueType() != NVT) { 7150 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 7151 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 7152 } 7153 return InOp; 7154 } 7155 7156 SDValue EltNo = N->getOperand(1); 7157 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 7158 7159 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 7160 // We only perform this optimization before the op legalization phase because 7161 // we may introduce new vector instructions which are not backed by TD patterns. 7162 // For example on AVX, extracting elements from a wide vector without using 7163 // extract_subvector. 7164 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 7165 && ConstEltNo && !LegalOperations) { 7166 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7167 int NumElem = VT.getVectorNumElements(); 7168 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 7169 // Find the new index to extract from. 7170 int OrigElt = SVOp->getMaskElt(Elt); 7171 7172 // Extracting an undef index is undef. 7173 if (OrigElt == -1) 7174 return DAG.getUNDEF(NVT); 7175 7176 // Select the right vector half to extract from. 7177 if (OrigElt < NumElem) { 7178 InVec = InVec->getOperand(0); 7179 } else { 7180 InVec = InVec->getOperand(1); 7181 OrigElt -= NumElem; 7182 } 7183 7184 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 7185 InVec, DAG.getConstant(OrigElt, MVT::i32)); 7186 } 7187 7188 // Perform only after legalization to ensure build_vector / vector_shuffle 7189 // optimizations have already been done. 7190 if (!LegalOperations) return SDValue(); 7191 7192 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 7193 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 7194 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 7195 7196 if (ConstEltNo) { 7197 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7198 bool NewLoad = false; 7199 bool BCNumEltsChanged = false; 7200 EVT ExtVT = VT.getVectorElementType(); 7201 EVT LVT = ExtVT; 7202 7203 if (InVec.getOpcode() == ISD::BITCAST) { 7204 // Don't duplicate a load with other uses. 7205 if (!InVec.hasOneUse()) 7206 return SDValue(); 7207 7208 EVT BCVT = InVec.getOperand(0).getValueType(); 7209 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 7210 return SDValue(); 7211 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 7212 BCNumEltsChanged = true; 7213 InVec = InVec.getOperand(0); 7214 ExtVT = BCVT.getVectorElementType(); 7215 NewLoad = true; 7216 } 7217 7218 LoadSDNode *LN0 = NULL; 7219 const ShuffleVectorSDNode *SVN = NULL; 7220 if (ISD::isNormalLoad(InVec.getNode())) { 7221 LN0 = cast<LoadSDNode>(InVec); 7222 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 7223 InVec.getOperand(0).getValueType() == ExtVT && 7224 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 7225 // Don't duplicate a load with other uses. 7226 if (!InVec.hasOneUse()) 7227 return SDValue(); 7228 7229 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 7230 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 7231 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 7232 // => 7233 // (load $addr+1*size) 7234 7235 // Don't duplicate a load with other uses. 7236 if (!InVec.hasOneUse()) 7237 return SDValue(); 7238 7239 // If the bit convert changed the number of elements, it is unsafe 7240 // to examine the mask. 7241 if (BCNumEltsChanged) 7242 return SDValue(); 7243 7244 // Select the input vector, guarding against out of range extract vector. 7245 unsigned NumElems = VT.getVectorNumElements(); 7246 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7247 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7248 7249 if (InVec.getOpcode() == ISD::BITCAST) { 7250 // Don't duplicate a load with other uses. 7251 if (!InVec.hasOneUse()) 7252 return SDValue(); 7253 7254 InVec = InVec.getOperand(0); 7255 } 7256 if (ISD::isNormalLoad(InVec.getNode())) { 7257 LN0 = cast<LoadSDNode>(InVec); 7258 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7259 } 7260 } 7261 7262 // Make sure we found a non-volatile load and the extractelement is 7263 // the only use. 7264 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7265 return SDValue(); 7266 7267 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7268 if (Elt == -1) 7269 return DAG.getUNDEF(LVT); 7270 7271 unsigned Align = LN0->getAlignment(); 7272 if (NewLoad) { 7273 // Check the resultant load doesn't need a higher alignment than the 7274 // original load. 7275 unsigned NewAlign = 7276 TLI.getTargetData() 7277 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7278 7279 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7280 return SDValue(); 7281 7282 Align = NewAlign; 7283 } 7284 7285 SDValue NewPtr = LN0->getBasePtr(); 7286 unsigned PtrOff = 0; 7287 7288 if (Elt) { 7289 PtrOff = LVT.getSizeInBits() * Elt / 8; 7290 EVT PtrType = NewPtr.getValueType(); 7291 if (TLI.isBigEndian()) 7292 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7293 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7294 DAG.getConstant(PtrOff, PtrType)); 7295 } 7296 7297 // The replacement we need to do here is a little tricky: we need to 7298 // replace an extractelement of a load with a load. 7299 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7300 // Note that this replacement assumes that the extractvalue is the only 7301 // use of the load; that's okay because we don't want to perform this 7302 // transformation in other cases anyway. 7303 SDValue Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7304 LN0->getPointerInfo().getWithOffset(PtrOff), 7305 LN0->isVolatile(), LN0->isNonTemporal(), 7306 LN0->isInvariant(), Align); 7307 WorkListRemover DeadNodes(*this); 7308 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7309 SDValue To[] = { Load.getValue(0), Load.getValue(1) }; 7310 DAG.ReplaceAllUsesOfValuesWith(From, To, 2, &DeadNodes); 7311 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7312 // worklist explicitly as well. 7313 AddToWorkList(Load.getNode()); 7314 // Make sure to revisit this node to clean it up; it will usually be dead. 7315 AddToWorkList(N); 7316 return SDValue(N, 0); 7317 } 7318 7319 return SDValue(); 7320} 7321 7322SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7323 unsigned NumInScalars = N->getNumOperands(); 7324 DebugLoc dl = N->getDebugLoc(); 7325 EVT VT = N->getValueType(0); 7326 // Check to see if this is a BUILD_VECTOR of a bunch of values 7327 // which come from any_extend or zero_extend nodes. If so, we can create 7328 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7329 // optimizations. We do not handle sign-extend because we can't fill the sign 7330 // using shuffles. 7331 EVT SourceType = MVT::Other; 7332 bool AllAnyExt = true; 7333 bool AllUndef = true; 7334 for (unsigned i = 0; i != NumInScalars; ++i) { 7335 SDValue In = N->getOperand(i); 7336 // Ignore undef inputs. 7337 if (In.getOpcode() == ISD::UNDEF) continue; 7338 AllUndef = false; 7339 7340 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7341 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7342 7343 // Abort if the element is not an extension. 7344 if (!ZeroExt && !AnyExt) { 7345 SourceType = MVT::Other; 7346 break; 7347 } 7348 7349 // The input is a ZeroExt or AnyExt. Check the original type. 7350 EVT InTy = In.getOperand(0).getValueType(); 7351 7352 // Check that all of the widened source types are the same. 7353 if (SourceType == MVT::Other) 7354 // First time. 7355 SourceType = InTy; 7356 else if (InTy != SourceType) { 7357 // Multiple income types. Abort. 7358 SourceType = MVT::Other; 7359 break; 7360 } 7361 7362 // Check if all of the extends are ANY_EXTENDs. 7363 AllAnyExt &= AnyExt; 7364 } 7365 7366 if (AllUndef) 7367 return DAG.getUNDEF(VT); 7368 7369 // In order to have valid types, all of the inputs must be extended from the 7370 // same source type and all of the inputs must be any or zero extend. 7371 // Scalar sizes must be a power of two. 7372 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7373 bool ValidTypes = SourceType != MVT::Other && 7374 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7375 isPowerOf2_32(SourceType.getSizeInBits()); 7376 7377 // We perform this optimization post type-legalization because 7378 // the type-legalizer often scalarizes integer-promoted vectors. 7379 // Performing this optimization before may create bit-casts which 7380 // will be type-legalized to complex code sequences. 7381 // We perform this optimization only before the operation legalizer because we 7382 // may introduce illegal operations. 7383 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 7384 ValidTypes) { 7385 bool isLE = TLI.isLittleEndian(); 7386 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7387 assert(ElemRatio > 1 && "Invalid element size ratio"); 7388 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 7389 DAG.getConstant(0, SourceType); 7390 7391 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7392 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7393 7394 // Populate the new build_vector 7395 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7396 SDValue Cast = N->getOperand(i); 7397 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7398 Cast.getOpcode() == ISD::ZERO_EXTEND || 7399 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7400 SDValue In; 7401 if (Cast.getOpcode() == ISD::UNDEF) 7402 In = DAG.getUNDEF(SourceType); 7403 else 7404 In = Cast->getOperand(0); 7405 unsigned Index = isLE ? (i * ElemRatio) : 7406 (i * ElemRatio + (ElemRatio - 1)); 7407 7408 assert(Index < Ops.size() && "Invalid index"); 7409 Ops[Index] = In; 7410 } 7411 7412 // The type of the new BUILD_VECTOR node. 7413 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 7414 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 7415 "Invalid vector size"); 7416 // Check if the new vector type is legal. 7417 if (!isTypeLegal(VecVT)) return SDValue(); 7418 7419 // Make the new BUILD_VECTOR. 7420 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7421 VecVT, &Ops[0], Ops.size()); 7422 7423 // Bitcast to the desired type. 7424 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 7425 } 7426 7427 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 7428 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 7429 // at most two distinct vectors, turn this into a shuffle node. 7430 SDValue VecIn1, VecIn2; 7431 for (unsigned i = 0; i != NumInScalars; ++i) { 7432 // Ignore undef inputs. 7433 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 7434 7435 // If this input is something other than a EXTRACT_VECTOR_ELT with a 7436 // constant index, bail out. 7437 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 7438 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 7439 VecIn1 = VecIn2 = SDValue(0, 0); 7440 break; 7441 } 7442 7443 // We allow up to two distinct input vectors. 7444 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 7445 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 7446 continue; 7447 7448 if (VecIn1.getNode() == 0) { 7449 VecIn1 = ExtractedFromVec; 7450 } else if (VecIn2.getNode() == 0) { 7451 VecIn2 = ExtractedFromVec; 7452 } else { 7453 // Too many inputs. 7454 VecIn1 = VecIn2 = SDValue(0, 0); 7455 break; 7456 } 7457 } 7458 7459 // If everything is good, we can make a shuffle operation. 7460 if (VecIn1.getNode()) { 7461 SmallVector<int, 8> Mask; 7462 for (unsigned i = 0; i != NumInScalars; ++i) { 7463 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 7464 Mask.push_back(-1); 7465 continue; 7466 } 7467 7468 // If extracting from the first vector, just use the index directly. 7469 SDValue Extract = N->getOperand(i); 7470 SDValue ExtVal = Extract.getOperand(1); 7471 if (Extract.getOperand(0) == VecIn1) { 7472 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7473 if (ExtIndex > VT.getVectorNumElements()) 7474 return SDValue(); 7475 7476 Mask.push_back(ExtIndex); 7477 continue; 7478 } 7479 7480 // Otherwise, use InIdx + VecSize 7481 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7482 Mask.push_back(Idx+NumInScalars); 7483 } 7484 7485 // We can't generate a shuffle node with mismatched input and output types. 7486 // Attempt to transform a single input vector to the correct type. 7487 if ((VT != VecIn1.getValueType())) { 7488 // We don't support shuffeling between TWO values of different types. 7489 if (VecIn2.getNode() != 0) 7490 return SDValue(); 7491 7492 // We only support widening of vectors which are half the size of the 7493 // output registers. For example XMM->YMM widening on X86 with AVX. 7494 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 7495 return SDValue(); 7496 7497 // Widen the input vector by adding undef values. 7498 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7499 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 7500 } 7501 7502 // If VecIn2 is unused then change it to undef. 7503 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 7504 7505 // Check that we were able to transform all incoming values to the same type. 7506 if (VecIn2.getValueType() != VecIn1.getValueType() || 7507 VecIn1.getValueType() != VT) 7508 return SDValue(); 7509 7510 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 7511 if (!isTypeLegal(VT)) 7512 return SDValue(); 7513 7514 // Return the new VECTOR_SHUFFLE node. 7515 SDValue Ops[2]; 7516 Ops[0] = VecIn1; 7517 Ops[1] = VecIn2; 7518 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 7519 } 7520 7521 return SDValue(); 7522} 7523 7524SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 7525 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 7526 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 7527 // inputs come from at most two distinct vectors, turn this into a shuffle 7528 // node. 7529 7530 // If we only have one input vector, we don't need to do any concatenation. 7531 if (N->getNumOperands() == 1) 7532 return N->getOperand(0); 7533 7534 return SDValue(); 7535} 7536 7537SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 7538 EVT NVT = N->getValueType(0); 7539 SDValue V = N->getOperand(0); 7540 7541 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 7542 // Handle only simple case where vector being inserted and vector 7543 // being extracted are of same type, and are half size of larger vectors. 7544 EVT BigVT = V->getOperand(0).getValueType(); 7545 EVT SmallVT = V->getOperand(1).getValueType(); 7546 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 7547 return SDValue(); 7548 7549 // Only handle cases where both indexes are constants with the same type. 7550 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7551 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 7552 7553 if (InsIdx && ExtIdx && 7554 InsIdx->getValueType(0).getSizeInBits() <= 64 && 7555 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 7556 // Combine: 7557 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 7558 // Into: 7559 // indices are equal => V1 7560 // otherwise => (extract_subvec V1, ExtIdx) 7561 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 7562 return V->getOperand(1); 7563 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 7564 V->getOperand(0), N->getOperand(1)); 7565 } 7566 } 7567 7568 return SDValue(); 7569} 7570 7571SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 7572 EVT VT = N->getValueType(0); 7573 unsigned NumElts = VT.getVectorNumElements(); 7574 7575 SDValue N0 = N->getOperand(0); 7576 SDValue N1 = N->getOperand(1); 7577 7578 assert(N0.getValueType().getVectorNumElements() == NumElts && 7579 "Vector shuffle must be normalized in DAG"); 7580 7581 // Canonicalize shuffle undef, undef -> undef 7582 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 7583 return DAG.getUNDEF(VT); 7584 7585 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7586 7587 // Canonicalize shuffle v, v -> v, undef 7588 if (N0 == N1) { 7589 SmallVector<int, 8> NewMask; 7590 for (unsigned i = 0; i != NumElts; ++i) { 7591 int Idx = SVN->getMaskElt(i); 7592 if (Idx >= (int)NumElts) Idx -= NumElts; 7593 NewMask.push_back(Idx); 7594 } 7595 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 7596 &NewMask[0]); 7597 } 7598 7599 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 7600 if (N0.getOpcode() == ISD::UNDEF) { 7601 SmallVector<int, 8> NewMask; 7602 for (unsigned i = 0; i != NumElts; ++i) { 7603 int Idx = SVN->getMaskElt(i); 7604 if (Idx < 0) 7605 NewMask.push_back(Idx); 7606 else if (Idx < (int)NumElts) 7607 NewMask.push_back(Idx + NumElts); 7608 else 7609 NewMask.push_back(Idx - NumElts); 7610 } 7611 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 7612 &NewMask[0]); 7613 } 7614 7615 // Remove references to rhs if it is undef 7616 if (N1.getOpcode() == ISD::UNDEF) { 7617 bool Changed = false; 7618 SmallVector<int, 8> NewMask; 7619 for (unsigned i = 0; i != NumElts; ++i) { 7620 int Idx = SVN->getMaskElt(i); 7621 if (Idx >= (int)NumElts) { 7622 Idx = -1; 7623 Changed = true; 7624 } 7625 NewMask.push_back(Idx); 7626 } 7627 if (Changed) 7628 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 7629 } 7630 7631 // If it is a splat, check if the argument vector is another splat or a 7632 // build_vector with all scalar elements the same. 7633 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 7634 SDNode *V = N0.getNode(); 7635 7636 // If this is a bit convert that changes the element type of the vector but 7637 // not the number of vector elements, look through it. Be careful not to 7638 // look though conversions that change things like v4f32 to v2f64. 7639 if (V->getOpcode() == ISD::BITCAST) { 7640 SDValue ConvInput = V->getOperand(0); 7641 if (ConvInput.getValueType().isVector() && 7642 ConvInput.getValueType().getVectorNumElements() == NumElts) 7643 V = ConvInput.getNode(); 7644 } 7645 7646 if (V->getOpcode() == ISD::BUILD_VECTOR) { 7647 assert(V->getNumOperands() == NumElts && 7648 "BUILD_VECTOR has wrong number of operands"); 7649 SDValue Base; 7650 bool AllSame = true; 7651 for (unsigned i = 0; i != NumElts; ++i) { 7652 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 7653 Base = V->getOperand(i); 7654 break; 7655 } 7656 } 7657 // Splat of <u, u, u, u>, return <u, u, u, u> 7658 if (!Base.getNode()) 7659 return N0; 7660 for (unsigned i = 0; i != NumElts; ++i) { 7661 if (V->getOperand(i) != Base) { 7662 AllSame = false; 7663 break; 7664 } 7665 } 7666 // Splat of <x, x, x, x>, return <x, x, x, x> 7667 if (AllSame) 7668 return N0; 7669 } 7670 } 7671 return SDValue(); 7672} 7673 7674SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 7675 if (!TLI.getShouldFoldAtomicFences()) 7676 return SDValue(); 7677 7678 SDValue atomic = N->getOperand(0); 7679 switch (atomic.getOpcode()) { 7680 case ISD::ATOMIC_CMP_SWAP: 7681 case ISD::ATOMIC_SWAP: 7682 case ISD::ATOMIC_LOAD_ADD: 7683 case ISD::ATOMIC_LOAD_SUB: 7684 case ISD::ATOMIC_LOAD_AND: 7685 case ISD::ATOMIC_LOAD_OR: 7686 case ISD::ATOMIC_LOAD_XOR: 7687 case ISD::ATOMIC_LOAD_NAND: 7688 case ISD::ATOMIC_LOAD_MIN: 7689 case ISD::ATOMIC_LOAD_MAX: 7690 case ISD::ATOMIC_LOAD_UMIN: 7691 case ISD::ATOMIC_LOAD_UMAX: 7692 break; 7693 default: 7694 return SDValue(); 7695 } 7696 7697 SDValue fence = atomic.getOperand(0); 7698 if (fence.getOpcode() != ISD::MEMBARRIER) 7699 return SDValue(); 7700 7701 switch (atomic.getOpcode()) { 7702 case ISD::ATOMIC_CMP_SWAP: 7703 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7704 fence.getOperand(0), 7705 atomic.getOperand(1), atomic.getOperand(2), 7706 atomic.getOperand(3)), atomic.getResNo()); 7707 case ISD::ATOMIC_SWAP: 7708 case ISD::ATOMIC_LOAD_ADD: 7709 case ISD::ATOMIC_LOAD_SUB: 7710 case ISD::ATOMIC_LOAD_AND: 7711 case ISD::ATOMIC_LOAD_OR: 7712 case ISD::ATOMIC_LOAD_XOR: 7713 case ISD::ATOMIC_LOAD_NAND: 7714 case ISD::ATOMIC_LOAD_MIN: 7715 case ISD::ATOMIC_LOAD_MAX: 7716 case ISD::ATOMIC_LOAD_UMIN: 7717 case ISD::ATOMIC_LOAD_UMAX: 7718 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7719 fence.getOperand(0), 7720 atomic.getOperand(1), atomic.getOperand(2)), 7721 atomic.getResNo()); 7722 default: 7723 return SDValue(); 7724 } 7725} 7726 7727/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 7728/// an AND to a vector_shuffle with the destination vector and a zero vector. 7729/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 7730/// vector_shuffle V, Zero, <0, 4, 2, 4> 7731SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 7732 EVT VT = N->getValueType(0); 7733 DebugLoc dl = N->getDebugLoc(); 7734 SDValue LHS = N->getOperand(0); 7735 SDValue RHS = N->getOperand(1); 7736 if (N->getOpcode() == ISD::AND) { 7737 if (RHS.getOpcode() == ISD::BITCAST) 7738 RHS = RHS.getOperand(0); 7739 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 7740 SmallVector<int, 8> Indices; 7741 unsigned NumElts = RHS.getNumOperands(); 7742 for (unsigned i = 0; i != NumElts; ++i) { 7743 SDValue Elt = RHS.getOperand(i); 7744 if (!isa<ConstantSDNode>(Elt)) 7745 return SDValue(); 7746 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 7747 Indices.push_back(i); 7748 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 7749 Indices.push_back(NumElts); 7750 else 7751 return SDValue(); 7752 } 7753 7754 // Let's see if the target supports this vector_shuffle. 7755 EVT RVT = RHS.getValueType(); 7756 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 7757 return SDValue(); 7758 7759 // Return the new VECTOR_SHUFFLE node. 7760 EVT EltVT = RVT.getVectorElementType(); 7761 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 7762 DAG.getConstant(0, EltVT)); 7763 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7764 RVT, &ZeroOps[0], ZeroOps.size()); 7765 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 7766 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 7767 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 7768 } 7769 } 7770 7771 return SDValue(); 7772} 7773 7774/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 7775SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 7776 // After legalize, the target may be depending on adds and other 7777 // binary ops to provide legal ways to construct constants or other 7778 // things. Simplifying them may result in a loss of legality. 7779 if (LegalOperations) return SDValue(); 7780 7781 assert(N->getValueType(0).isVector() && 7782 "SimplifyVBinOp only works on vectors!"); 7783 7784 SDValue LHS = N->getOperand(0); 7785 SDValue RHS = N->getOperand(1); 7786 SDValue Shuffle = XformToShuffleWithZero(N); 7787 if (Shuffle.getNode()) return Shuffle; 7788 7789 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 7790 // this operation. 7791 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 7792 RHS.getOpcode() == ISD::BUILD_VECTOR) { 7793 SmallVector<SDValue, 8> Ops; 7794 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 7795 SDValue LHSOp = LHS.getOperand(i); 7796 SDValue RHSOp = RHS.getOperand(i); 7797 // If these two elements can't be folded, bail out. 7798 if ((LHSOp.getOpcode() != ISD::UNDEF && 7799 LHSOp.getOpcode() != ISD::Constant && 7800 LHSOp.getOpcode() != ISD::ConstantFP) || 7801 (RHSOp.getOpcode() != ISD::UNDEF && 7802 RHSOp.getOpcode() != ISD::Constant && 7803 RHSOp.getOpcode() != ISD::ConstantFP)) 7804 break; 7805 7806 // Can't fold divide by zero. 7807 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 7808 N->getOpcode() == ISD::FDIV) { 7809 if ((RHSOp.getOpcode() == ISD::Constant && 7810 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 7811 (RHSOp.getOpcode() == ISD::ConstantFP && 7812 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 7813 break; 7814 } 7815 7816 EVT VT = LHSOp.getValueType(); 7817 EVT RVT = RHSOp.getValueType(); 7818 if (RVT != VT) { 7819 // Integer BUILD_VECTOR operands may have types larger than the element 7820 // size (e.g., when the element type is not legal). Prior to type 7821 // legalization, the types may not match between the two BUILD_VECTORS. 7822 // Truncate one of the operands to make them match. 7823 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 7824 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 7825 } else { 7826 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 7827 VT = RVT; 7828 } 7829 } 7830 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 7831 LHSOp, RHSOp); 7832 if (FoldOp.getOpcode() != ISD::UNDEF && 7833 FoldOp.getOpcode() != ISD::Constant && 7834 FoldOp.getOpcode() != ISD::ConstantFP) 7835 break; 7836 Ops.push_back(FoldOp); 7837 AddToWorkList(FoldOp.getNode()); 7838 } 7839 7840 if (Ops.size() == LHS.getNumOperands()) 7841 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7842 LHS.getValueType(), &Ops[0], Ops.size()); 7843 } 7844 7845 return SDValue(); 7846} 7847 7848SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 7849 SDValue N1, SDValue N2){ 7850 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 7851 7852 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 7853 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 7854 7855 // If we got a simplified select_cc node back from SimplifySelectCC, then 7856 // break it down into a new SETCC node, and a new SELECT node, and then return 7857 // the SELECT node, since we were called with a SELECT node. 7858 if (SCC.getNode()) { 7859 // Check to see if we got a select_cc back (to turn into setcc/select). 7860 // Otherwise, just return whatever node we got back, like fabs. 7861 if (SCC.getOpcode() == ISD::SELECT_CC) { 7862 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 7863 N0.getValueType(), 7864 SCC.getOperand(0), SCC.getOperand(1), 7865 SCC.getOperand(4)); 7866 AddToWorkList(SETCC.getNode()); 7867 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 7868 SCC.getOperand(2), SCC.getOperand(3), SETCC); 7869 } 7870 7871 return SCC; 7872 } 7873 return SDValue(); 7874} 7875 7876/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 7877/// are the two values being selected between, see if we can simplify the 7878/// select. Callers of this should assume that TheSelect is deleted if this 7879/// returns true. As such, they should return the appropriate thing (e.g. the 7880/// node) back to the top-level of the DAG combiner loop to avoid it being 7881/// looked at. 7882bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 7883 SDValue RHS) { 7884 7885 // Cannot simplify select with vector condition 7886 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 7887 7888 // If this is a select from two identical things, try to pull the operation 7889 // through the select. 7890 if (LHS.getOpcode() != RHS.getOpcode() || 7891 !LHS.hasOneUse() || !RHS.hasOneUse()) 7892 return false; 7893 7894 // If this is a load and the token chain is identical, replace the select 7895 // of two loads with a load through a select of the address to load from. 7896 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 7897 // constants have been dropped into the constant pool. 7898 if (LHS.getOpcode() == ISD::LOAD) { 7899 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 7900 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 7901 7902 // Token chains must be identical. 7903 if (LHS.getOperand(0) != RHS.getOperand(0) || 7904 // Do not let this transformation reduce the number of volatile loads. 7905 LLD->isVolatile() || RLD->isVolatile() || 7906 // If this is an EXTLOAD, the VT's must match. 7907 LLD->getMemoryVT() != RLD->getMemoryVT() || 7908 // If this is an EXTLOAD, the kind of extension must match. 7909 (LLD->getExtensionType() != RLD->getExtensionType() && 7910 // The only exception is if one of the extensions is anyext. 7911 LLD->getExtensionType() != ISD::EXTLOAD && 7912 RLD->getExtensionType() != ISD::EXTLOAD) || 7913 // FIXME: this discards src value information. This is 7914 // over-conservative. It would be beneficial to be able to remember 7915 // both potential memory locations. Since we are discarding 7916 // src value info, don't do the transformation if the memory 7917 // locations are not in the default address space. 7918 LLD->getPointerInfo().getAddrSpace() != 0 || 7919 RLD->getPointerInfo().getAddrSpace() != 0) 7920 return false; 7921 7922 // Check that the select condition doesn't reach either load. If so, 7923 // folding this will induce a cycle into the DAG. If not, this is safe to 7924 // xform, so create a select of the addresses. 7925 SDValue Addr; 7926 if (TheSelect->getOpcode() == ISD::SELECT) { 7927 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 7928 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 7929 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 7930 return false; 7931 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 7932 LLD->getBasePtr().getValueType(), 7933 TheSelect->getOperand(0), LLD->getBasePtr(), 7934 RLD->getBasePtr()); 7935 } else { // Otherwise SELECT_CC 7936 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 7937 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 7938 7939 if ((LLD->hasAnyUseOfValue(1) && 7940 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 7941 (LLD->hasAnyUseOfValue(1) && 7942 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 7943 return false; 7944 7945 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 7946 LLD->getBasePtr().getValueType(), 7947 TheSelect->getOperand(0), 7948 TheSelect->getOperand(1), 7949 LLD->getBasePtr(), RLD->getBasePtr(), 7950 TheSelect->getOperand(4)); 7951 } 7952 7953 SDValue Load; 7954 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 7955 Load = DAG.getLoad(TheSelect->getValueType(0), 7956 TheSelect->getDebugLoc(), 7957 // FIXME: Discards pointer info. 7958 LLD->getChain(), Addr, MachinePointerInfo(), 7959 LLD->isVolatile(), LLD->isNonTemporal(), 7960 LLD->isInvariant(), LLD->getAlignment()); 7961 } else { 7962 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 7963 RLD->getExtensionType() : LLD->getExtensionType(), 7964 TheSelect->getDebugLoc(), 7965 TheSelect->getValueType(0), 7966 // FIXME: Discards pointer info. 7967 LLD->getChain(), Addr, MachinePointerInfo(), 7968 LLD->getMemoryVT(), LLD->isVolatile(), 7969 LLD->isNonTemporal(), LLD->getAlignment()); 7970 } 7971 7972 // Users of the select now use the result of the load. 7973 CombineTo(TheSelect, Load); 7974 7975 // Users of the old loads now use the new load's chain. We know the 7976 // old-load value is dead now. 7977 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 7978 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 7979 return true; 7980 } 7981 7982 return false; 7983} 7984 7985/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 7986/// where 'cond' is the comparison specified by CC. 7987SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 7988 SDValue N2, SDValue N3, 7989 ISD::CondCode CC, bool NotExtCompare) { 7990 // (x ? y : y) -> y. 7991 if (N2 == N3) return N2; 7992 7993 EVT VT = N2.getValueType(); 7994 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 7995 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 7996 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 7997 7998 // Determine if the condition we're dealing with is constant 7999 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 8000 N0, N1, CC, DL, false); 8001 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 8002 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 8003 8004 // fold select_cc true, x, y -> x 8005 if (SCCC && !SCCC->isNullValue()) 8006 return N2; 8007 // fold select_cc false, x, y -> y 8008 if (SCCC && SCCC->isNullValue()) 8009 return N3; 8010 8011 // Check to see if we can simplify the select into an fabs node 8012 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 8013 // Allow either -0.0 or 0.0 8014 if (CFP->getValueAPF().isZero()) { 8015 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 8016 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 8017 N0 == N2 && N3.getOpcode() == ISD::FNEG && 8018 N2 == N3.getOperand(0)) 8019 return DAG.getNode(ISD::FABS, DL, VT, N0); 8020 8021 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 8022 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 8023 N0 == N3 && N2.getOpcode() == ISD::FNEG && 8024 N2.getOperand(0) == N3) 8025 return DAG.getNode(ISD::FABS, DL, VT, N3); 8026 } 8027 } 8028 8029 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 8030 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 8031 // in it. This is a win when the constant is not otherwise available because 8032 // it replaces two constant pool loads with one. We only do this if the FP 8033 // type is known to be legal, because if it isn't, then we are before legalize 8034 // types an we want the other legalization to happen first (e.g. to avoid 8035 // messing with soft float) and if the ConstantFP is not legal, because if 8036 // it is legal, we may not need to store the FP constant in a constant pool. 8037 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 8038 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 8039 if (TLI.isTypeLegal(N2.getValueType()) && 8040 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 8041 TargetLowering::Legal) && 8042 // If both constants have multiple uses, then we won't need to do an 8043 // extra load, they are likely around in registers for other users. 8044 (TV->hasOneUse() || FV->hasOneUse())) { 8045 Constant *Elts[] = { 8046 const_cast<ConstantFP*>(FV->getConstantFPValue()), 8047 const_cast<ConstantFP*>(TV->getConstantFPValue()) 8048 }; 8049 Type *FPTy = Elts[0]->getType(); 8050 const TargetData &TD = *TLI.getTargetData(); 8051 8052 // Create a ConstantArray of the two constants. 8053 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 8054 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 8055 TD.getPrefTypeAlignment(FPTy)); 8056 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8057 8058 // Get the offsets to the 0 and 1 element of the array so that we can 8059 // select between them. 8060 SDValue Zero = DAG.getIntPtrConstant(0); 8061 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 8062 SDValue One = DAG.getIntPtrConstant(EltSize); 8063 8064 SDValue Cond = DAG.getSetCC(DL, 8065 TLI.getSetCCResultType(N0.getValueType()), 8066 N0, N1, CC); 8067 AddToWorkList(Cond.getNode()); 8068 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 8069 Cond, One, Zero); 8070 AddToWorkList(CstOffset.getNode()); 8071 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 8072 CstOffset); 8073 AddToWorkList(CPIdx.getNode()); 8074 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 8075 MachinePointerInfo::getConstantPool(), false, 8076 false, false, Alignment); 8077 8078 } 8079 } 8080 8081 // Check to see if we can perform the "gzip trick", transforming 8082 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 8083 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 8084 (N1C->isNullValue() || // (a < 0) ? b : 0 8085 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 8086 EVT XType = N0.getValueType(); 8087 EVT AType = N2.getValueType(); 8088 if (XType.bitsGE(AType)) { 8089 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 8090 // single-bit constant. 8091 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 8092 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 8093 ShCtV = XType.getSizeInBits()-ShCtV-1; 8094 SDValue ShCt = DAG.getConstant(ShCtV, 8095 getShiftAmountTy(N0.getValueType())); 8096 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 8097 XType, N0, ShCt); 8098 AddToWorkList(Shift.getNode()); 8099 8100 if (XType.bitsGT(AType)) { 8101 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8102 AddToWorkList(Shift.getNode()); 8103 } 8104 8105 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8106 } 8107 8108 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 8109 XType, N0, 8110 DAG.getConstant(XType.getSizeInBits()-1, 8111 getShiftAmountTy(N0.getValueType()))); 8112 AddToWorkList(Shift.getNode()); 8113 8114 if (XType.bitsGT(AType)) { 8115 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8116 AddToWorkList(Shift.getNode()); 8117 } 8118 8119 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8120 } 8121 } 8122 8123 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 8124 // where y is has a single bit set. 8125 // A plaintext description would be, we can turn the SELECT_CC into an AND 8126 // when the condition can be materialized as an all-ones register. Any 8127 // single bit-test can be materialized as an all-ones register with 8128 // shift-left and shift-right-arith. 8129 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 8130 N0->getValueType(0) == VT && 8131 N1C && N1C->isNullValue() && 8132 N2C && N2C->isNullValue()) { 8133 SDValue AndLHS = N0->getOperand(0); 8134 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 8135 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 8136 // Shift the tested bit over the sign bit. 8137 APInt AndMask = ConstAndRHS->getAPIntValue(); 8138 SDValue ShlAmt = 8139 DAG.getConstant(AndMask.countLeadingZeros(), 8140 getShiftAmountTy(AndLHS.getValueType())); 8141 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 8142 8143 // Now arithmetic right shift it all the way over, so the result is either 8144 // all-ones, or zero. 8145 SDValue ShrAmt = 8146 DAG.getConstant(AndMask.getBitWidth()-1, 8147 getShiftAmountTy(Shl.getValueType())); 8148 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 8149 8150 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 8151 } 8152 } 8153 8154 // fold select C, 16, 0 -> shl C, 4 8155 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 8156 TLI.getBooleanContents(N0.getValueType().isVector()) == 8157 TargetLowering::ZeroOrOneBooleanContent) { 8158 8159 // If the caller doesn't want us to simplify this into a zext of a compare, 8160 // don't do it. 8161 if (NotExtCompare && N2C->getAPIntValue() == 1) 8162 return SDValue(); 8163 8164 // Get a SetCC of the condition 8165 // FIXME: Should probably make sure that setcc is legal if we ever have a 8166 // target where it isn't. 8167 SDValue Temp, SCC; 8168 // cast from setcc result type to select result type 8169 if (LegalTypes) { 8170 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 8171 N0, N1, CC); 8172 if (N2.getValueType().bitsLT(SCC.getValueType())) 8173 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 8174 else 8175 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8176 N2.getValueType(), SCC); 8177 } else { 8178 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 8179 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8180 N2.getValueType(), SCC); 8181 } 8182 8183 AddToWorkList(SCC.getNode()); 8184 AddToWorkList(Temp.getNode()); 8185 8186 if (N2C->getAPIntValue() == 1) 8187 return Temp; 8188 8189 // shl setcc result by log2 n2c 8190 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 8191 DAG.getConstant(N2C->getAPIntValue().logBase2(), 8192 getShiftAmountTy(Temp.getValueType()))); 8193 } 8194 8195 // Check to see if this is the equivalent of setcc 8196 // FIXME: Turn all of these into setcc if setcc if setcc is legal 8197 // otherwise, go ahead with the folds. 8198 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 8199 EVT XType = N0.getValueType(); 8200 if (!LegalOperations || 8201 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 8202 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 8203 if (Res.getValueType() != VT) 8204 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 8205 return Res; 8206 } 8207 8208 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 8209 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 8210 (!LegalOperations || 8211 TLI.isOperationLegal(ISD::CTLZ, XType))) { 8212 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 8213 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 8214 DAG.getConstant(Log2_32(XType.getSizeInBits()), 8215 getShiftAmountTy(Ctlz.getValueType()))); 8216 } 8217 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 8218 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 8219 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 8220 XType, DAG.getConstant(0, XType), N0); 8221 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 8222 return DAG.getNode(ISD::SRL, DL, XType, 8223 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 8224 DAG.getConstant(XType.getSizeInBits()-1, 8225 getShiftAmountTy(XType))); 8226 } 8227 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 8228 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 8229 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 8230 DAG.getConstant(XType.getSizeInBits()-1, 8231 getShiftAmountTy(N0.getValueType()))); 8232 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 8233 } 8234 } 8235 8236 // Check to see if this is an integer abs. 8237 // select_cc setg[te] X, 0, X, -X -> 8238 // select_cc setgt X, -1, X, -X -> 8239 // select_cc setl[te] X, 0, -X, X -> 8240 // select_cc setlt X, 1, -X, X -> 8241 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 8242 if (N1C) { 8243 ConstantSDNode *SubC = NULL; 8244 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8245 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 8246 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 8247 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 8248 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 8249 (N1C->isOne() && CC == ISD::SETLT)) && 8250 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 8251 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 8252 8253 EVT XType = N0.getValueType(); 8254 if (SubC && SubC->isNullValue() && XType.isInteger()) { 8255 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 8256 N0, 8257 DAG.getConstant(XType.getSizeInBits()-1, 8258 getShiftAmountTy(N0.getValueType()))); 8259 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 8260 XType, N0, Shift); 8261 AddToWorkList(Shift.getNode()); 8262 AddToWorkList(Add.getNode()); 8263 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 8264 } 8265 } 8266 8267 return SDValue(); 8268} 8269 8270/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8271SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8272 SDValue N1, ISD::CondCode Cond, 8273 DebugLoc DL, bool foldBooleans) { 8274 TargetLowering::DAGCombinerInfo 8275 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8276 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8277} 8278 8279/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8280/// return a DAG expression to select that will generate the same value by 8281/// multiplying by a magic number. See: 8282/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8283SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8284 std::vector<SDNode*> Built; 8285 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8286 8287 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8288 ii != ee; ++ii) 8289 AddToWorkList(*ii); 8290 return S; 8291} 8292 8293/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8294/// return a DAG expression to select that will generate the same value by 8295/// multiplying by a magic number. See: 8296/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8297SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8298 std::vector<SDNode*> Built; 8299 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8300 8301 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8302 ii != ee; ++ii) 8303 AddToWorkList(*ii); 8304 return S; 8305} 8306 8307/// FindBaseOffset - Return true if base is a frame index, which is known not 8308// to alias with anything but itself. Provides base object and offset as 8309// results. 8310static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8311 const GlobalValue *&GV, void *&CV) { 8312 // Assume it is a primitive operation. 8313 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8314 8315 // If it's an adding a simple constant then integrate the offset. 8316 if (Base.getOpcode() == ISD::ADD) { 8317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8318 Base = Base.getOperand(0); 8319 Offset += C->getZExtValue(); 8320 } 8321 } 8322 8323 // Return the underlying GlobalValue, and update the Offset. Return false 8324 // for GlobalAddressSDNode since the same GlobalAddress may be represented 8325 // by multiple nodes with different offsets. 8326 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 8327 GV = G->getGlobal(); 8328 Offset += G->getOffset(); 8329 return false; 8330 } 8331 8332 // Return the underlying Constant value, and update the Offset. Return false 8333 // for ConstantSDNodes since the same constant pool entry may be represented 8334 // by multiple nodes with different offsets. 8335 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 8336 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 8337 : (void *)C->getConstVal(); 8338 Offset += C->getOffset(); 8339 return false; 8340 } 8341 // If it's any of the following then it can't alias with anything but itself. 8342 return isa<FrameIndexSDNode>(Base); 8343} 8344 8345/// isAlias - Return true if there is any possibility that the two addresses 8346/// overlap. 8347bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 8348 const Value *SrcValue1, int SrcValueOffset1, 8349 unsigned SrcValueAlign1, 8350 const MDNode *TBAAInfo1, 8351 SDValue Ptr2, int64_t Size2, 8352 const Value *SrcValue2, int SrcValueOffset2, 8353 unsigned SrcValueAlign2, 8354 const MDNode *TBAAInfo2) const { 8355 // If they are the same then they must be aliases. 8356 if (Ptr1 == Ptr2) return true; 8357 8358 // Gather base node and offset information. 8359 SDValue Base1, Base2; 8360 int64_t Offset1, Offset2; 8361 const GlobalValue *GV1, *GV2; 8362 void *CV1, *CV2; 8363 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 8364 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 8365 8366 // If they have a same base address then check to see if they overlap. 8367 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 8368 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8369 8370 // It is possible for different frame indices to alias each other, mostly 8371 // when tail call optimization reuses return address slots for arguments. 8372 // To catch this case, look up the actual index of frame indices to compute 8373 // the real alias relationship. 8374 if (isFrameIndex1 && isFrameIndex2) { 8375 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8376 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 8377 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 8378 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8379 } 8380 8381 // Otherwise, if we know what the bases are, and they aren't identical, then 8382 // we know they cannot alias. 8383 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 8384 return false; 8385 8386 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 8387 // compared to the size and offset of the access, we may be able to prove they 8388 // do not alias. This check is conservative for now to catch cases created by 8389 // splitting vector types. 8390 if ((SrcValueAlign1 == SrcValueAlign2) && 8391 (SrcValueOffset1 != SrcValueOffset2) && 8392 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 8393 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 8394 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 8395 8396 // There is no overlap between these relatively aligned accesses of similar 8397 // size, return no alias. 8398 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 8399 return false; 8400 } 8401 8402 if (CombinerGlobalAA) { 8403 // Use alias analysis information. 8404 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 8405 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 8406 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 8407 AliasAnalysis::AliasResult AAResult = 8408 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 8409 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 8410 if (AAResult == AliasAnalysis::NoAlias) 8411 return false; 8412 } 8413 8414 // Otherwise we have to assume they alias. 8415 return true; 8416} 8417 8418/// FindAliasInfo - Extracts the relevant alias information from the memory 8419/// node. Returns true if the operand was a load. 8420bool DAGCombiner::FindAliasInfo(SDNode *N, 8421 SDValue &Ptr, int64_t &Size, 8422 const Value *&SrcValue, 8423 int &SrcValueOffset, 8424 unsigned &SrcValueAlign, 8425 const MDNode *&TBAAInfo) const { 8426 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 8427 8428 Ptr = LS->getBasePtr(); 8429 Size = LS->getMemoryVT().getSizeInBits() >> 3; 8430 SrcValue = LS->getSrcValue(); 8431 SrcValueOffset = LS->getSrcValueOffset(); 8432 SrcValueAlign = LS->getOriginalAlignment(); 8433 TBAAInfo = LS->getTBAAInfo(); 8434 return isa<LoadSDNode>(LS); 8435} 8436 8437/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 8438/// looking for aliasing nodes and adding them to the Aliases vector. 8439void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 8440 SmallVector<SDValue, 8> &Aliases) { 8441 SmallVector<SDValue, 8> Chains; // List of chains to visit. 8442 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 8443 8444 // Get alias information for node. 8445 SDValue Ptr; 8446 int64_t Size; 8447 const Value *SrcValue; 8448 int SrcValueOffset; 8449 unsigned SrcValueAlign; 8450 const MDNode *SrcTBAAInfo; 8451 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 8452 SrcValueAlign, SrcTBAAInfo); 8453 8454 // Starting off. 8455 Chains.push_back(OriginalChain); 8456 unsigned Depth = 0; 8457 8458 // Look at each chain and determine if it is an alias. If so, add it to the 8459 // aliases list. If not, then continue up the chain looking for the next 8460 // candidate. 8461 while (!Chains.empty()) { 8462 SDValue Chain = Chains.back(); 8463 Chains.pop_back(); 8464 8465 // For TokenFactor nodes, look at each operand and only continue up the 8466 // chain until we find two aliases. If we've seen two aliases, assume we'll 8467 // find more and revert to original chain since the xform is unlikely to be 8468 // profitable. 8469 // 8470 // FIXME: The depth check could be made to return the last non-aliasing 8471 // chain we found before we hit a tokenfactor rather than the original 8472 // chain. 8473 if (Depth > 6 || Aliases.size() == 2) { 8474 Aliases.clear(); 8475 Aliases.push_back(OriginalChain); 8476 break; 8477 } 8478 8479 // Don't bother if we've been before. 8480 if (!Visited.insert(Chain.getNode())) 8481 continue; 8482 8483 switch (Chain.getOpcode()) { 8484 case ISD::EntryToken: 8485 // Entry token is ideal chain operand, but handled in FindBetterChain. 8486 break; 8487 8488 case ISD::LOAD: 8489 case ISD::STORE: { 8490 // Get alias information for Chain. 8491 SDValue OpPtr; 8492 int64_t OpSize; 8493 const Value *OpSrcValue; 8494 int OpSrcValueOffset; 8495 unsigned OpSrcValueAlign; 8496 const MDNode *OpSrcTBAAInfo; 8497 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 8498 OpSrcValue, OpSrcValueOffset, 8499 OpSrcValueAlign, 8500 OpSrcTBAAInfo); 8501 8502 // If chain is alias then stop here. 8503 if (!(IsLoad && IsOpLoad) && 8504 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 8505 SrcTBAAInfo, 8506 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 8507 OpSrcValueAlign, OpSrcTBAAInfo)) { 8508 Aliases.push_back(Chain); 8509 } else { 8510 // Look further up the chain. 8511 Chains.push_back(Chain.getOperand(0)); 8512 ++Depth; 8513 } 8514 break; 8515 } 8516 8517 case ISD::TokenFactor: 8518 // We have to check each of the operands of the token factor for "small" 8519 // token factors, so we queue them up. Adding the operands to the queue 8520 // (stack) in reverse order maintains the original order and increases the 8521 // likelihood that getNode will find a matching token factor (CSE.) 8522 if (Chain.getNumOperands() > 16) { 8523 Aliases.push_back(Chain); 8524 break; 8525 } 8526 for (unsigned n = Chain.getNumOperands(); n;) 8527 Chains.push_back(Chain.getOperand(--n)); 8528 ++Depth; 8529 break; 8530 8531 default: 8532 // For all other instructions we will just have to take what we can get. 8533 Aliases.push_back(Chain); 8534 break; 8535 } 8536 } 8537} 8538 8539/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 8540/// for a better chain (aliasing node.) 8541SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 8542 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 8543 8544 // Accumulate all the aliases to this node. 8545 GatherAllAliases(N, OldChain, Aliases); 8546 8547 // If no operands then chain to entry token. 8548 if (Aliases.size() == 0) 8549 return DAG.getEntryNode(); 8550 8551 // If a single operand then chain to it. We don't need to revisit it. 8552 if (Aliases.size() == 1) 8553 return Aliases[0]; 8554 8555 // Construct a custom tailored token factor. 8556 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8557 &Aliases[0], Aliases.size()); 8558} 8559 8560// SelectionDAG::Combine - This is the entry point for the file. 8561// 8562void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 8563 CodeGenOpt::Level OptLevel) { 8564 /// run - This is the main entry point to this class. 8565 /// 8566 DAGCombiner(*this, AA, OptLevel).Run(Level); 8567} 8568