DAGCombiner.cpp revision b0d5cdd52e8448f769cd71aaee6a4b8592dc08b1
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 const TargetLowering &TLI; 53 CombineLevel Level; 54 bool LegalOperations; 55 bool LegalTypes; 56 bool Fast; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 // AA - Used for DAG load/store alias analysis. 62 AliasAnalysis &AA; 63 64 /// AddUsersToWorkList - When an instruction is simplified, add all users of 65 /// the instruction to the work lists because they might get more simplified 66 /// now. 67 /// 68 void AddUsersToWorkList(SDNode *N) { 69 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 70 UI != UE; ++UI) 71 AddToWorkList(*UI); 72 } 73 74 /// visit - call the node-specific routine that knows how to fold each 75 /// particular type of node. 76 SDValue visit(SDNode *N); 77 78 public: 79 /// AddToWorkList - Add to the work list making sure it's instance is at the 80 /// the back (next to be processed.) 81 void AddToWorkList(SDNode *N) { 82 removeFromWorkList(N); 83 WorkList.push_back(N); 84 } 85 86 /// removeFromWorkList - remove all instances of N from the worklist. 87 /// 88 void removeFromWorkList(SDNode *N) { 89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 90 WorkList.end()); 91 } 92 93 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 94 bool AddTo = true); 95 96 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 97 return CombineTo(N, &Res, 1, AddTo); 98 } 99 100 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 101 bool AddTo = true) { 102 SDValue To[] = { Res0, Res1 }; 103 return CombineTo(N, To, 2, AddTo); 104 } 105 106 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 107 108 private: 109 110 /// SimplifyDemandedBits - Check the specified integer node value to see if 111 /// it can be simplified or if things it uses can be simplified by bit 112 /// propagation. If so, return true. 113 bool SimplifyDemandedBits(SDValue Op) { 114 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 115 return SimplifyDemandedBits(Op, Demanded); 116 } 117 118 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 119 120 bool CombineToPreIndexedLoadStore(SDNode *N); 121 bool CombineToPostIndexedLoadStore(SDNode *N); 122 123 124 /// combine - call the node-specific routine that knows how to fold each 125 /// particular type of node. If that doesn't do anything, try the 126 /// target-specific DAG combines. 127 SDValue combine(SDNode *N); 128 129 // Visitation implementation - Implement dag node combining for different 130 // node types. The semantics are as follows: 131 // Return Value: 132 // SDValue.getNode() == 0 - No change was made 133 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 134 // otherwise - N should be replaced by the returned Operand. 135 // 136 SDValue visitTokenFactor(SDNode *N); 137 SDValue visitMERGE_VALUES(SDNode *N); 138 SDValue visitADD(SDNode *N); 139 SDValue visitSUB(SDNode *N); 140 SDValue visitADDC(SDNode *N); 141 SDValue visitADDE(SDNode *N); 142 SDValue visitMUL(SDNode *N); 143 SDValue visitSDIV(SDNode *N); 144 SDValue visitUDIV(SDNode *N); 145 SDValue visitSREM(SDNode *N); 146 SDValue visitUREM(SDNode *N); 147 SDValue visitMULHU(SDNode *N); 148 SDValue visitMULHS(SDNode *N); 149 SDValue visitSMUL_LOHI(SDNode *N); 150 SDValue visitUMUL_LOHI(SDNode *N); 151 SDValue visitSDIVREM(SDNode *N); 152 SDValue visitUDIVREM(SDNode *N); 153 SDValue visitAND(SDNode *N); 154 SDValue visitOR(SDNode *N); 155 SDValue visitXOR(SDNode *N); 156 SDValue SimplifyVBinOp(SDNode *N); 157 SDValue visitSHL(SDNode *N); 158 SDValue visitSRA(SDNode *N); 159 SDValue visitSRL(SDNode *N); 160 SDValue visitCTLZ(SDNode *N); 161 SDValue visitCTTZ(SDNode *N); 162 SDValue visitCTPOP(SDNode *N); 163 SDValue visitSELECT(SDNode *N); 164 SDValue visitSELECT_CC(SDNode *N); 165 SDValue visitSETCC(SDNode *N); 166 SDValue visitSIGN_EXTEND(SDNode *N); 167 SDValue visitZERO_EXTEND(SDNode *N); 168 SDValue visitANY_EXTEND(SDNode *N); 169 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 170 SDValue visitTRUNCATE(SDNode *N); 171 SDValue visitBIT_CONVERT(SDNode *N); 172 SDValue visitBUILD_PAIR(SDNode *N); 173 SDValue visitFADD(SDNode *N); 174 SDValue visitFSUB(SDNode *N); 175 SDValue visitFMUL(SDNode *N); 176 SDValue visitFDIV(SDNode *N); 177 SDValue visitFREM(SDNode *N); 178 SDValue visitFCOPYSIGN(SDNode *N); 179 SDValue visitSINT_TO_FP(SDNode *N); 180 SDValue visitUINT_TO_FP(SDNode *N); 181 SDValue visitFP_TO_SINT(SDNode *N); 182 SDValue visitFP_TO_UINT(SDNode *N); 183 SDValue visitFP_ROUND(SDNode *N); 184 SDValue visitFP_ROUND_INREG(SDNode *N); 185 SDValue visitFP_EXTEND(SDNode *N); 186 SDValue visitFNEG(SDNode *N); 187 SDValue visitFABS(SDNode *N); 188 SDValue visitBRCOND(SDNode *N); 189 SDValue visitBR_CC(SDNode *N); 190 SDValue visitLOAD(SDNode *N); 191 SDValue visitSTORE(SDNode *N); 192 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 193 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 194 SDValue visitBUILD_VECTOR(SDNode *N); 195 SDValue visitCONCAT_VECTORS(SDNode *N); 196 SDValue visitVECTOR_SHUFFLE(SDNode *N); 197 198 SDValue XformToShuffleWithZero(SDNode *N); 199 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 200 201 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 202 203 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 204 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 205 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 206 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 207 SDValue N3, ISD::CondCode CC, 208 bool NotExtCompare = false); 209 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 210 bool foldBooleans = true); 211 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 212 unsigned HiOp); 213 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 214 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 215 SDValue BuildSDIV(SDNode *N); 216 SDValue BuildUDIV(SDNode *N); 217 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 218 SDValue ReduceLoadWidth(SDNode *N); 219 220 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 221 222 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 223 /// looking for aliasing nodes and adding them to the Aliases vector. 224 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 225 SmallVector<SDValue, 8> &Aliases); 226 227 /// isAlias - Return true if there is any possibility that the two addresses 228 /// overlap. 229 bool isAlias(SDValue Ptr1, int64_t Size1, 230 const Value *SrcValue1, int SrcValueOffset1, 231 SDValue Ptr2, int64_t Size2, 232 const Value *SrcValue2, int SrcValueOffset2) const; 233 234 /// FindAliasInfo - Extracts the relevant alias information from the memory 235 /// node. Returns true if the operand was a load. 236 bool FindAliasInfo(SDNode *N, 237 SDValue &Ptr, int64_t &Size, 238 const Value *&SrcValue, int &SrcValueOffset) const; 239 240 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 241 /// looking for a better chain (aliasing node.) 242 SDValue FindBetterChain(SDNode *N, SDValue Chain); 243 244 /// getShiftAmountTy - Returns a type large enough to hold any valid 245 /// shift amount - before type legalization these can be huge. 246 MVT getShiftAmountTy() { 247 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 248 } 249 250public: 251 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 252 : DAG(D), 253 TLI(D.getTargetLoweringInfo()), 254 Level(Unrestricted), 255 LegalOperations(false), 256 LegalTypes(false), 257 Fast(fast), 258 AA(A) {} 259 260 /// Run - runs the dag combiner on all nodes in the work list 261 void Run(CombineLevel AtLevel); 262 }; 263} 264 265 266namespace { 267/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 268/// nodes from the worklist. 269class VISIBILITY_HIDDEN WorkListRemover : 270 public SelectionDAG::DAGUpdateListener { 271 DAGCombiner &DC; 272public: 273 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 274 275 virtual void NodeDeleted(SDNode *N, SDNode *E) { 276 DC.removeFromWorkList(N); 277 } 278 279 virtual void NodeUpdated(SDNode *N) { 280 // Ignore updates. 281 } 282}; 283} 284 285//===----------------------------------------------------------------------===// 286// TargetLowering::DAGCombinerInfo implementation 287//===----------------------------------------------------------------------===// 288 289void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 290 ((DAGCombiner*)DC)->AddToWorkList(N); 291} 292 293SDValue TargetLowering::DAGCombinerInfo:: 294CombineTo(SDNode *N, const std::vector<SDValue> &To) { 295 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 296} 297 298SDValue TargetLowering::DAGCombinerInfo:: 299CombineTo(SDNode *N, SDValue Res) { 300 return ((DAGCombiner*)DC)->CombineTo(N, Res); 301} 302 303 304SDValue TargetLowering::DAGCombinerInfo:: 305CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 306 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 307} 308 309void TargetLowering::DAGCombinerInfo:: 310CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 311 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 312} 313 314//===----------------------------------------------------------------------===// 315// Helper Functions 316//===----------------------------------------------------------------------===// 317 318/// isNegatibleForFree - Return 1 if we can compute the negated form of the 319/// specified expression for the same cost as the expression itself, or 2 if we 320/// can compute the negated form more cheaply than the expression itself. 321static char isNegatibleForFree(SDValue Op, bool LegalOperations, 322 unsigned Depth = 0) { 323 // No compile time optimizations on this type. 324 if (Op.getValueType() == MVT::ppcf128) 325 return 0; 326 327 // fneg is removable even if it has multiple uses. 328 if (Op.getOpcode() == ISD::FNEG) return 2; 329 330 // Don't allow anything with multiple uses. 331 if (!Op.hasOneUse()) return 0; 332 333 // Don't recurse exponentially. 334 if (Depth > 6) return 0; 335 336 switch (Op.getOpcode()) { 337 default: return false; 338 case ISD::ConstantFP: 339 // Don't invert constant FP values after legalize. The negated constant 340 // isn't necessarily legal. 341 return LegalOperations ? 0 : 1; 342 case ISD::FADD: 343 // FIXME: determine better conditions for this xform. 344 if (!UnsafeFPMath) return 0; 345 346 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 347 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 348 return V; 349 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 350 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 351 case ISD::FSUB: 352 // We can't turn -(A-B) into B-A when we honor signed zeros. 353 if (!UnsafeFPMath) return 0; 354 355 // fold (fneg (fsub A, B)) -> (fsub B, A) 356 return 1; 357 358 case ISD::FMUL: 359 case ISD::FDIV: 360 if (HonorSignDependentRoundingFPMath()) return 0; 361 362 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 363 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 364 return V; 365 366 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 367 368 case ISD::FP_EXTEND: 369 case ISD::FP_ROUND: 370 case ISD::FSIN: 371 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 372 } 373} 374 375/// GetNegatedExpression - If isNegatibleForFree returns true, this function 376/// returns the newly negated expression. 377static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 378 bool LegalOperations, unsigned Depth = 0) { 379 // fneg is removable even if it has multiple uses. 380 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 381 382 // Don't allow anything with multiple uses. 383 assert(Op.hasOneUse() && "Unknown reuse!"); 384 385 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 386 switch (Op.getOpcode()) { 387 default: assert(0 && "Unknown code"); 388 case ISD::ConstantFP: { 389 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 390 V.changeSign(); 391 return DAG.getConstantFP(V, Op.getValueType()); 392 } 393 case ISD::FADD: 394 // FIXME: determine better conditions for this xform. 395 assert(UnsafeFPMath); 396 397 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 398 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 399 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 400 GetNegatedExpression(Op.getOperand(0), DAG, 401 LegalOperations, Depth+1), 402 Op.getOperand(1)); 403 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 404 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 405 GetNegatedExpression(Op.getOperand(1), DAG, 406 LegalOperations, Depth+1), 407 Op.getOperand(0)); 408 case ISD::FSUB: 409 // We can't turn -(A-B) into B-A when we honor signed zeros. 410 assert(UnsafeFPMath); 411 412 // fold (fneg (fsub 0, B)) -> B 413 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 414 if (N0CFP->getValueAPF().isZero()) 415 return Op.getOperand(1); 416 417 // fold (fneg (fsub A, B)) -> (fsub B, A) 418 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 419 Op.getOperand(1), Op.getOperand(0)); 420 421 case ISD::FMUL: 422 case ISD::FDIV: 423 assert(!HonorSignDependentRoundingFPMath()); 424 425 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 426 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 427 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 428 GetNegatedExpression(Op.getOperand(0), DAG, 429 LegalOperations, Depth+1), 430 Op.getOperand(1)); 431 432 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 433 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 434 Op.getOperand(0), 435 GetNegatedExpression(Op.getOperand(1), DAG, 436 LegalOperations, Depth+1)); 437 438 case ISD::FP_EXTEND: 439 case ISD::FSIN: 440 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 441 GetNegatedExpression(Op.getOperand(0), DAG, 442 LegalOperations, Depth+1)); 443 case ISD::FP_ROUND: 444 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 445 GetNegatedExpression(Op.getOperand(0), DAG, 446 LegalOperations, Depth+1), 447 Op.getOperand(1)); 448 } 449} 450 451 452// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 453// that selects between the values 1 and 0, making it equivalent to a setcc. 454// Also, set the incoming LHS, RHS, and CC references to the appropriate 455// nodes based on the type of node we are checking. This simplifies life a 456// bit for the callers. 457static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 458 SDValue &CC) { 459 if (N.getOpcode() == ISD::SETCC) { 460 LHS = N.getOperand(0); 461 RHS = N.getOperand(1); 462 CC = N.getOperand(2); 463 return true; 464 } 465 if (N.getOpcode() == ISD::SELECT_CC && 466 N.getOperand(2).getOpcode() == ISD::Constant && 467 N.getOperand(3).getOpcode() == ISD::Constant && 468 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 469 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 470 LHS = N.getOperand(0); 471 RHS = N.getOperand(1); 472 CC = N.getOperand(4); 473 return true; 474 } 475 return false; 476} 477 478// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 479// one use. If this is true, it allows the users to invert the operation for 480// free when it is profitable to do so. 481static bool isOneUseSetCC(SDValue N) { 482 SDValue N0, N1, N2; 483 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 484 return true; 485 return false; 486} 487 488SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 489 SDValue N0, SDValue N1) { 490 MVT VT = N0.getValueType(); 491 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 492 if (isa<ConstantSDNode>(N1)) { 493 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 494 SDValue OpNode = 495 DAG.FoldConstantArithmetic(Opc, VT, 496 cast<ConstantSDNode>(N0.getOperand(1)), 497 cast<ConstantSDNode>(N1)); 498 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 499 } else if (N0.hasOneUse()) { 500 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 501 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 502 N0.getOperand(0), N1); 503 AddToWorkList(OpNode.getNode()); 504 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 505 } 506 } 507 508 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 509 if (isa<ConstantSDNode>(N0)) { 510 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 511 SDValue OpNode = 512 DAG.FoldConstantArithmetic(Opc, VT, 513 cast<ConstantSDNode>(N1.getOperand(1)), 514 cast<ConstantSDNode>(N0)); 515 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 516 } else if (N1.hasOneUse()) { 517 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 518 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 519 N1.getOperand(0), N0); 520 AddToWorkList(OpNode.getNode()); 521 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 522 } 523 } 524 525 return SDValue(); 526} 527 528SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 529 bool AddTo) { 530 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 531 ++NodesCombined; 532 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 533 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 534 DOUT << " and " << NumTo-1 << " other values\n"; 535 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 536 assert(N->getValueType(i) == To[i].getValueType() && 537 "Cannot combine value to value of different type!")); 538 WorkListRemover DeadNodes(*this); 539 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 540 541 if (AddTo) { 542 // Push the new nodes and any users onto the worklist 543 for (unsigned i = 0, e = NumTo; i != e; ++i) { 544 AddToWorkList(To[i].getNode()); 545 AddUsersToWorkList(To[i].getNode()); 546 } 547 } 548 549 // Finally, if the node is now dead, remove it from the graph. The node 550 // may not be dead if the replacement process recursively simplified to 551 // something else needing this node. 552 if (N->use_empty()) { 553 // Nodes can be reintroduced into the worklist. Make sure we do not 554 // process a node that has been replaced. 555 removeFromWorkList(N); 556 557 // Finally, since the node is now dead, remove it from the graph. 558 DAG.DeleteNode(N); 559 } 560 return SDValue(N, 0); 561} 562 563void 564DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 565 TLO) { 566 // Replace all uses. If any nodes become isomorphic to other nodes and 567 // are deleted, make sure to remove them from our worklist. 568 WorkListRemover DeadNodes(*this); 569 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 570 571 // Push the new node and any (possibly new) users onto the worklist. 572 AddToWorkList(TLO.New.getNode()); 573 AddUsersToWorkList(TLO.New.getNode()); 574 575 // Finally, if the node is now dead, remove it from the graph. The node 576 // may not be dead if the replacement process recursively simplified to 577 // something else needing this node. 578 if (TLO.Old.getNode()->use_empty()) { 579 removeFromWorkList(TLO.Old.getNode()); 580 581 // If the operands of this node are only used by the node, they will now 582 // be dead. Make sure to visit them first to delete dead nodes early. 583 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 584 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 585 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 586 587 DAG.DeleteNode(TLO.Old.getNode()); 588 } 589} 590 591/// SimplifyDemandedBits - Check the specified integer node value to see if 592/// it can be simplified or if things it uses can be simplified by bit 593/// propagation. If so, return true. 594bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 595 TargetLowering::TargetLoweringOpt TLO(DAG); 596 APInt KnownZero, KnownOne; 597 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 598 return false; 599 600 // Revisit the node. 601 AddToWorkList(Op.getNode()); 602 603 // Replace the old value with the new one. 604 ++NodesCombined; 605 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 606 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 607 DOUT << '\n'; 608 609 CommitTargetLoweringOpt(TLO); 610 return true; 611} 612 613//===----------------------------------------------------------------------===// 614// Main DAG Combiner implementation 615//===----------------------------------------------------------------------===// 616 617void DAGCombiner::Run(CombineLevel AtLevel) { 618 // set the instance variables, so that the various visit routines may use it. 619 Level = AtLevel; 620 LegalOperations = Level >= NoIllegalOperations; 621 LegalTypes = Level >= NoIllegalTypes; 622 623 // Add all the dag nodes to the worklist. 624 WorkList.reserve(DAG.allnodes_size()); 625 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 626 E = DAG.allnodes_end(); I != E; ++I) 627 WorkList.push_back(I); 628 629 // Create a dummy node (which is not added to allnodes), that adds a reference 630 // to the root node, preventing it from being deleted, and tracking any 631 // changes of the root. 632 HandleSDNode Dummy(DAG.getRoot()); 633 634 // The root of the dag may dangle to deleted nodes until the dag combiner is 635 // done. Set it to null to avoid confusion. 636 DAG.setRoot(SDValue()); 637 638 // while the worklist isn't empty, inspect the node on the end of it and 639 // try and combine it. 640 while (!WorkList.empty()) { 641 SDNode *N = WorkList.back(); 642 WorkList.pop_back(); 643 644 // If N has no uses, it is dead. Make sure to revisit all N's operands once 645 // N is deleted from the DAG, since they too may now be dead or may have a 646 // reduced number of uses, allowing other xforms. 647 if (N->use_empty() && N != &Dummy) { 648 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 649 AddToWorkList(N->getOperand(i).getNode()); 650 651 DAG.DeleteNode(N); 652 continue; 653 } 654 655 SDValue RV = combine(N); 656 657 if (RV.getNode() == 0) 658 continue; 659 660 ++NodesCombined; 661 662 // If we get back the same node we passed in, rather than a new node or 663 // zero, we know that the node must have defined multiple values and 664 // CombineTo was used. Since CombineTo takes care of the worklist 665 // mechanics for us, we have no work to do in this case. 666 if (RV.getNode() == N) 667 continue; 668 669 assert(N->getOpcode() != ISD::DELETED_NODE && 670 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 671 "Node was deleted but visit returned new node!"); 672 673 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 674 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 675 DOUT << '\n'; 676 WorkListRemover DeadNodes(*this); 677 if (N->getNumValues() == RV.getNode()->getNumValues()) 678 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 679 else { 680 assert(N->getValueType(0) == RV.getValueType() && 681 N->getNumValues() == 1 && "Type mismatch"); 682 SDValue OpV = RV; 683 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 684 } 685 686 // Push the new node and any users onto the worklist 687 AddToWorkList(RV.getNode()); 688 AddUsersToWorkList(RV.getNode()); 689 690 // Add any uses of the old node to the worklist in case this node is the 691 // last one that uses them. They may become dead after this node is 692 // deleted. 693 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 694 AddToWorkList(N->getOperand(i).getNode()); 695 696 // Finally, if the node is now dead, remove it from the graph. The node 697 // may not be dead if the replacement process recursively simplified to 698 // something else needing this node. 699 if (N->use_empty()) { 700 // Nodes can be reintroduced into the worklist. Make sure we do not 701 // process a node that has been replaced. 702 removeFromWorkList(N); 703 704 // Finally, since the node is now dead, remove it from the graph. 705 DAG.DeleteNode(N); 706 } 707 } 708 709 // If the root changed (e.g. it was a dead load, update the root). 710 DAG.setRoot(Dummy.getValue()); 711} 712 713SDValue DAGCombiner::visit(SDNode *N) { 714 switch(N->getOpcode()) { 715 default: break; 716 case ISD::TokenFactor: return visitTokenFactor(N); 717 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 718 case ISD::ADD: return visitADD(N); 719 case ISD::SUB: return visitSUB(N); 720 case ISD::ADDC: return visitADDC(N); 721 case ISD::ADDE: return visitADDE(N); 722 case ISD::MUL: return visitMUL(N); 723 case ISD::SDIV: return visitSDIV(N); 724 case ISD::UDIV: return visitUDIV(N); 725 case ISD::SREM: return visitSREM(N); 726 case ISD::UREM: return visitUREM(N); 727 case ISD::MULHU: return visitMULHU(N); 728 case ISD::MULHS: return visitMULHS(N); 729 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 730 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 731 case ISD::SDIVREM: return visitSDIVREM(N); 732 case ISD::UDIVREM: return visitUDIVREM(N); 733 case ISD::AND: return visitAND(N); 734 case ISD::OR: return visitOR(N); 735 case ISD::XOR: return visitXOR(N); 736 case ISD::SHL: return visitSHL(N); 737 case ISD::SRA: return visitSRA(N); 738 case ISD::SRL: return visitSRL(N); 739 case ISD::CTLZ: return visitCTLZ(N); 740 case ISD::CTTZ: return visitCTTZ(N); 741 case ISD::CTPOP: return visitCTPOP(N); 742 case ISD::SELECT: return visitSELECT(N); 743 case ISD::SELECT_CC: return visitSELECT_CC(N); 744 case ISD::SETCC: return visitSETCC(N); 745 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 746 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 747 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 748 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 749 case ISD::TRUNCATE: return visitTRUNCATE(N); 750 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 751 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 752 case ISD::FADD: return visitFADD(N); 753 case ISD::FSUB: return visitFSUB(N); 754 case ISD::FMUL: return visitFMUL(N); 755 case ISD::FDIV: return visitFDIV(N); 756 case ISD::FREM: return visitFREM(N); 757 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 758 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 759 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 760 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 761 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 762 case ISD::FP_ROUND: return visitFP_ROUND(N); 763 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 764 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 765 case ISD::FNEG: return visitFNEG(N); 766 case ISD::FABS: return visitFABS(N); 767 case ISD::BRCOND: return visitBRCOND(N); 768 case ISD::BR_CC: return visitBR_CC(N); 769 case ISD::LOAD: return visitLOAD(N); 770 case ISD::STORE: return visitSTORE(N); 771 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 772 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 773 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 774 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 775 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 776 } 777 return SDValue(); 778} 779 780SDValue DAGCombiner::combine(SDNode *N) { 781 SDValue RV = visit(N); 782 783 // If nothing happened, try a target-specific DAG combine. 784 if (RV.getNode() == 0) { 785 assert(N->getOpcode() != ISD::DELETED_NODE && 786 "Node was deleted but visit returned NULL!"); 787 788 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 789 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 790 791 // Expose the DAG combiner to the target combiner impls. 792 TargetLowering::DAGCombinerInfo 793 DagCombineInfo(DAG, Level == Unrestricted, false, this); 794 795 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 796 } 797 } 798 799 // If N is a commutative binary node, try commuting it to enable more 800 // sdisel CSE. 801 if (RV.getNode() == 0 && 802 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 803 N->getNumValues() == 1) { 804 SDValue N0 = N->getOperand(0); 805 SDValue N1 = N->getOperand(1); 806 807 // Constant operands are canonicalized to RHS. 808 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 809 SDValue Ops[] = { N1, N0 }; 810 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 811 Ops, 2); 812 if (CSENode) 813 return SDValue(CSENode, 0); 814 } 815 } 816 817 return RV; 818} 819 820/// getInputChainForNode - Given a node, return its input chain if it has one, 821/// otherwise return a null sd operand. 822static SDValue getInputChainForNode(SDNode *N) { 823 if (unsigned NumOps = N->getNumOperands()) { 824 if (N->getOperand(0).getValueType() == MVT::Other) 825 return N->getOperand(0); 826 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 827 return N->getOperand(NumOps-1); 828 for (unsigned i = 1; i < NumOps-1; ++i) 829 if (N->getOperand(i).getValueType() == MVT::Other) 830 return N->getOperand(i); 831 } 832 return SDValue(); 833} 834 835SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 836 // If N has two operands, where one has an input chain equal to the other, 837 // the 'other' chain is redundant. 838 if (N->getNumOperands() == 2) { 839 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 840 return N->getOperand(0); 841 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 842 return N->getOperand(1); 843 } 844 845 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 846 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 847 SmallPtrSet<SDNode*, 16> SeenOps; 848 bool Changed = false; // If we should replace this token factor. 849 850 // Start out with this token factor. 851 TFs.push_back(N); 852 853 // Iterate through token factors. The TFs grows when new token factors are 854 // encountered. 855 for (unsigned i = 0; i < TFs.size(); ++i) { 856 SDNode *TF = TFs[i]; 857 858 // Check each of the operands. 859 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 860 SDValue Op = TF->getOperand(i); 861 862 switch (Op.getOpcode()) { 863 case ISD::EntryToken: 864 // Entry tokens don't need to be added to the list. They are 865 // rededundant. 866 Changed = true; 867 break; 868 869 case ISD::TokenFactor: 870 if ((CombinerAA || Op.hasOneUse()) && 871 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 872 // Queue up for processing. 873 TFs.push_back(Op.getNode()); 874 // Clean up in case the token factor is removed. 875 AddToWorkList(Op.getNode()); 876 Changed = true; 877 break; 878 } 879 // Fall thru 880 881 default: 882 // Only add if it isn't already in the list. 883 if (SeenOps.insert(Op.getNode())) 884 Ops.push_back(Op); 885 else 886 Changed = true; 887 break; 888 } 889 } 890 } 891 892 SDValue Result; 893 894 // If we've change things around then replace token factor. 895 if (Changed) { 896 if (Ops.empty()) { 897 // The entry token is the only possible outcome. 898 Result = DAG.getEntryNode(); 899 } else { 900 // New and improved token factor. 901 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 902 MVT::Other, &Ops[0], Ops.size()); 903 } 904 905 // Don't add users to work list. 906 return CombineTo(N, Result, false); 907 } 908 909 return Result; 910} 911 912/// MERGE_VALUES can always be eliminated. 913SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 914 WorkListRemover DeadNodes(*this); 915 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 916 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 917 &DeadNodes); 918 removeFromWorkList(N); 919 DAG.DeleteNode(N); 920 return SDValue(N, 0); // Return N so it doesn't get rechecked! 921} 922 923static 924SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 925 SelectionDAG &DAG) { 926 MVT VT = N0.getValueType(); 927 SDValue N00 = N0.getOperand(0); 928 SDValue N01 = N0.getOperand(1); 929 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 930 931 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 932 isa<ConstantSDNode>(N00.getOperand(1))) { 933 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 934 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 935 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 936 N00.getOperand(0), N01), 937 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 938 N00.getOperand(1), N01)); 939 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 940 } 941 942 return SDValue(); 943} 944 945static 946SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 947 SelectionDAG &DAG, const TargetLowering &TLI, 948 bool LegalOperations) { 949 MVT VT = N->getValueType(0); 950 unsigned Opc = N->getOpcode(); 951 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 952 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 953 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 954 ISD::CondCode CC = ISD::SETCC_INVALID; 955 956 if (isSlctCC) { 957 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 958 } else { 959 SDValue CCOp = Slct.getOperand(0); 960 if (CCOp.getOpcode() == ISD::SETCC) 961 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 962 } 963 964 bool DoXform = false; 965 bool InvCC = false; 966 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 967 "Bad input!"); 968 969 if (LHS.getOpcode() == ISD::Constant && 970 cast<ConstantSDNode>(LHS)->isNullValue()) { 971 DoXform = true; 972 } else if (CC != ISD::SETCC_INVALID && 973 RHS.getOpcode() == ISD::Constant && 974 cast<ConstantSDNode>(RHS)->isNullValue()) { 975 std::swap(LHS, RHS); 976 SDValue Op0 = Slct.getOperand(0); 977 MVT OpVT = isSlctCC ? Op0.getValueType() : 978 Op0.getOperand(0).getValueType(); 979 bool isInt = OpVT.isInteger(); 980 CC = ISD::getSetCCInverse(CC, isInt); 981 982 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT)) 983 return SDValue(); // Inverse operator isn't legal. 984 985 DoXform = true; 986 InvCC = true; 987 } 988 989 if (DoXform) { 990 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 991 if (isSlctCC) 992 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 993 Slct.getOperand(0), Slct.getOperand(1), CC); 994 SDValue CCOp = Slct.getOperand(0); 995 if (InvCC) 996 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 997 CCOp.getOperand(0), CCOp.getOperand(1), CC); 998 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 999 CCOp, OtherOp, Result); 1000 } 1001 return SDValue(); 1002} 1003 1004SDValue DAGCombiner::visitADD(SDNode *N) { 1005 SDValue N0 = N->getOperand(0); 1006 SDValue N1 = N->getOperand(1); 1007 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1008 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1009 MVT VT = N0.getValueType(); 1010 1011 // fold vector ops 1012 if (VT.isVector()) { 1013 SDValue FoldedVOp = SimplifyVBinOp(N); 1014 if (FoldedVOp.getNode()) return FoldedVOp; 1015 } 1016 1017 // fold (add x, undef) -> undef 1018 if (N0.getOpcode() == ISD::UNDEF) 1019 return N0; 1020 if (N1.getOpcode() == ISD::UNDEF) 1021 return N1; 1022 // fold (add c1, c2) -> c1+c2 1023 if (N0C && N1C) 1024 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1025 // canonicalize constant to RHS 1026 if (N0C && !N1C) 1027 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1028 // fold (add x, 0) -> x 1029 if (N1C && N1C->isNullValue()) 1030 return N0; 1031 // fold (add Sym, c) -> Sym+c 1032 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1033 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1034 GA->getOpcode() == ISD::GlobalAddress) 1035 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1036 GA->getOffset() + 1037 (uint64_t)N1C->getSExtValue()); 1038 // fold ((c1-A)+c2) -> (c1+c2)-A 1039 if (N1C && N0.getOpcode() == ISD::SUB) 1040 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1041 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1042 DAG.getConstant(N1C->getAPIntValue()+ 1043 N0C->getAPIntValue(), VT), 1044 N0.getOperand(1)); 1045 // reassociate add 1046 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1047 if (RADD.getNode() != 0) 1048 return RADD; 1049 // fold ((0-A) + B) -> B-A 1050 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1051 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1052 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1053 // fold (A + (0-B)) -> A-B 1054 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1055 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1056 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1057 // fold (A+(B-A)) -> B 1058 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1059 return N1.getOperand(0); 1060 // fold ((B-A)+A) -> B 1061 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1062 return N0.getOperand(0); 1063 // fold (A+(B-(A+C))) to (B-C) 1064 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1065 N0 == N1.getOperand(1).getOperand(0)) 1066 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1067 N1.getOperand(1).getOperand(1)); 1068 // fold (A+(B-(C+A))) to (B-C) 1069 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1070 N0 == N1.getOperand(1).getOperand(1)) 1071 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1072 N1.getOperand(1).getOperand(0)); 1073 // fold (A+((B-A)+or-C)) to (B+or-C) 1074 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1075 N1.getOperand(0).getOpcode() == ISD::SUB && 1076 N0 == N1.getOperand(0).getOperand(1)) 1077 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1078 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1079 1080 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1081 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1082 SDValue N00 = N0.getOperand(0); 1083 SDValue N01 = N0.getOperand(1); 1084 SDValue N10 = N1.getOperand(0); 1085 SDValue N11 = N1.getOperand(1); 1086 1087 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1088 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1089 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1090 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1091 } 1092 1093 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1094 return SDValue(N, 0); 1095 1096 // fold (a+b) -> (a|b) iff a and b share no bits. 1097 if (VT.isInteger() && !VT.isVector()) { 1098 APInt LHSZero, LHSOne; 1099 APInt RHSZero, RHSOne; 1100 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1101 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1102 1103 if (LHSZero.getBoolValue()) { 1104 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1105 1106 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1107 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1108 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1109 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1110 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1111 } 1112 } 1113 1114 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1115 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1116 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1117 if (Result.getNode()) return Result; 1118 } 1119 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1120 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1121 if (Result.getNode()) return Result; 1122 } 1123 1124 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1125 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1126 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations); 1127 if (Result.getNode()) return Result; 1128 } 1129 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1130 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1131 if (Result.getNode()) return Result; 1132 } 1133 1134 return SDValue(); 1135} 1136 1137SDValue DAGCombiner::visitADDC(SDNode *N) { 1138 SDValue N0 = N->getOperand(0); 1139 SDValue N1 = N->getOperand(1); 1140 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1141 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1142 MVT VT = N0.getValueType(); 1143 1144 // If the flag result is dead, turn this into an ADD. 1145 if (N->hasNUsesOfValue(0, 1)) 1146 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1147 DAG.getNode(ISD::CARRY_FALSE, 1148 N->getDebugLoc(), MVT::Flag)); 1149 1150 // canonicalize constant to RHS. 1151 if (N0C && !N1C) 1152 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1153 1154 // fold (addc x, 0) -> x + no carry out 1155 if (N1C && N1C->isNullValue()) 1156 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1157 N->getDebugLoc(), MVT::Flag)); 1158 1159 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1160 APInt LHSZero, LHSOne; 1161 APInt RHSZero, RHSOne; 1162 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1163 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1164 1165 if (LHSZero.getBoolValue()) { 1166 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1167 1168 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1169 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1170 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1171 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1172 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1173 DAG.getNode(ISD::CARRY_FALSE, 1174 N->getDebugLoc(), MVT::Flag)); 1175 } 1176 1177 return SDValue(); 1178} 1179 1180SDValue DAGCombiner::visitADDE(SDNode *N) { 1181 SDValue N0 = N->getOperand(0); 1182 SDValue N1 = N->getOperand(1); 1183 SDValue CarryIn = N->getOperand(2); 1184 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1185 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1186 1187 // canonicalize constant to RHS 1188 if (N0C && !N1C) 1189 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1190 N1, N0, CarryIn); 1191 1192 // fold (adde x, y, false) -> (addc x, y) 1193 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1194 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1195 1196 return SDValue(); 1197} 1198 1199SDValue DAGCombiner::visitSUB(SDNode *N) { 1200 SDValue N0 = N->getOperand(0); 1201 SDValue N1 = N->getOperand(1); 1202 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1203 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1204 MVT VT = N0.getValueType(); 1205 1206 // fold vector ops 1207 if (VT.isVector()) { 1208 SDValue FoldedVOp = SimplifyVBinOp(N); 1209 if (FoldedVOp.getNode()) return FoldedVOp; 1210 } 1211 1212 // fold (sub x, x) -> 0 1213 if (N0 == N1) 1214 return DAG.getConstant(0, N->getValueType(0)); 1215 // fold (sub c1, c2) -> c1-c2 1216 if (N0C && N1C) 1217 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1218 // fold (sub x, c) -> (add x, -c) 1219 if (N1C) 1220 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1221 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1222 // fold (A+B)-A -> B 1223 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1224 return N0.getOperand(1); 1225 // fold (A+B)-B -> A 1226 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1227 return N0.getOperand(0); 1228 // fold ((A+(B+or-C))-B) -> A+or-C 1229 if (N0.getOpcode() == ISD::ADD && 1230 (N0.getOperand(1).getOpcode() == ISD::SUB || 1231 N0.getOperand(1).getOpcode() == ISD::ADD) && 1232 N0.getOperand(1).getOperand(0) == N1) 1233 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1234 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1235 // fold ((A+(C+B))-B) -> A+C 1236 if (N0.getOpcode() == ISD::ADD && 1237 N0.getOperand(1).getOpcode() == ISD::ADD && 1238 N0.getOperand(1).getOperand(1) == N1) 1239 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1240 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1241 // fold ((A-(B-C))-C) -> A-B 1242 if (N0.getOpcode() == ISD::SUB && 1243 N0.getOperand(1).getOpcode() == ISD::SUB && 1244 N0.getOperand(1).getOperand(1) == N1) 1245 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1246 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1247 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1248 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1249 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1250 if (Result.getNode()) return Result; 1251 } 1252 1253 // If either operand of a sub is undef, the result is undef 1254 if (N0.getOpcode() == ISD::UNDEF) 1255 return N0; 1256 if (N1.getOpcode() == ISD::UNDEF) 1257 return N1; 1258 1259 // If the relocation model supports it, consider symbol offsets. 1260 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1261 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1262 // fold (sub Sym, c) -> Sym-c 1263 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1264 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1265 GA->getOffset() - 1266 (uint64_t)N1C->getSExtValue()); 1267 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1268 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1269 if (GA->getGlobal() == GB->getGlobal()) 1270 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1271 VT); 1272 } 1273 1274 return SDValue(); 1275} 1276 1277SDValue DAGCombiner::visitMUL(SDNode *N) { 1278 SDValue N0 = N->getOperand(0); 1279 SDValue N1 = N->getOperand(1); 1280 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1281 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1282 MVT VT = N0.getValueType(); 1283 1284 // fold vector ops 1285 if (VT.isVector()) { 1286 SDValue FoldedVOp = SimplifyVBinOp(N); 1287 if (FoldedVOp.getNode()) return FoldedVOp; 1288 } 1289 1290 // fold (mul x, undef) -> 0 1291 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1292 return DAG.getConstant(0, VT); 1293 // fold (mul c1, c2) -> c1*c2 1294 if (N0C && N1C) 1295 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1296 // canonicalize constant to RHS 1297 if (N0C && !N1C) 1298 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1299 // fold (mul x, 0) -> 0 1300 if (N1C && N1C->isNullValue()) 1301 return N1; 1302 // fold (mul x, -1) -> 0-x 1303 if (N1C && N1C->isAllOnesValue()) 1304 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1305 DAG.getConstant(0, VT), N0); 1306 // fold (mul x, (1 << c)) -> x << c 1307 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1308 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1309 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1310 getShiftAmountTy())); 1311 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1312 if (N1C && isPowerOf2_64(-N1C->getSExtValue())) 1313 // FIXME: If the input is something that is easily negated (e.g. a 1314 // single-use add), we should put the negate there. 1315 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1316 DAG.getConstant(0, VT), 1317 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1318 DAG.getConstant(Log2_64(-N1C->getSExtValue()), 1319 getShiftAmountTy()))); 1320 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1321 if (N1C && N0.getOpcode() == ISD::SHL && 1322 isa<ConstantSDNode>(N0.getOperand(1))) { 1323 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1324 N1, N0.getOperand(1)); 1325 AddToWorkList(C3.getNode()); 1326 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1327 N0.getOperand(0), C3); 1328 } 1329 1330 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1331 // use. 1332 { 1333 SDValue Sh(0,0), Y(0,0); 1334 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1335 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1336 N0.getNode()->hasOneUse()) { 1337 Sh = N0; Y = N1; 1338 } else if (N1.getOpcode() == ISD::SHL && 1339 isa<ConstantSDNode>(N1.getOperand(1)) && 1340 N1.getNode()->hasOneUse()) { 1341 Sh = N1; Y = N0; 1342 } 1343 1344 if (Sh.getNode()) { 1345 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1346 Sh.getOperand(0), Y); 1347 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1348 Mul, Sh.getOperand(1)); 1349 } 1350 } 1351 1352 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1353 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1354 isa<ConstantSDNode>(N0.getOperand(1))) 1355 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1356 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1357 N0.getOperand(0), N1), 1358 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1359 N0.getOperand(1), N1)); 1360 1361 // reassociate mul 1362 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1363 if (RMUL.getNode() != 0) 1364 return RMUL; 1365 1366 return SDValue(); 1367} 1368 1369SDValue DAGCombiner::visitSDIV(SDNode *N) { 1370 SDValue N0 = N->getOperand(0); 1371 SDValue N1 = N->getOperand(1); 1372 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1373 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1374 MVT VT = N->getValueType(0); 1375 1376 // fold vector ops 1377 if (VT.isVector()) { 1378 SDValue FoldedVOp = SimplifyVBinOp(N); 1379 if (FoldedVOp.getNode()) return FoldedVOp; 1380 } 1381 1382 // fold (sdiv c1, c2) -> c1/c2 1383 if (N0C && N1C && !N1C->isNullValue()) 1384 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1385 // fold (sdiv X, 1) -> X 1386 if (N1C && N1C->getSExtValue() == 1LL) 1387 return N0; 1388 // fold (sdiv X, -1) -> 0-X 1389 if (N1C && N1C->isAllOnesValue()) 1390 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1391 DAG.getConstant(0, VT), N0); 1392 // If we know the sign bits of both operands are zero, strength reduce to a 1393 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1394 if (!VT.isVector()) { 1395 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1396 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1397 N0, N1); 1398 } 1399 // fold (sdiv X, pow2) -> simple ops after legalize 1400 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1401 (isPowerOf2_64(N1C->getSExtValue()) || 1402 isPowerOf2_64(-N1C->getSExtValue()))) { 1403 // If dividing by powers of two is cheap, then don't perform the following 1404 // fold. 1405 if (TLI.isPow2DivCheap()) 1406 return SDValue(); 1407 1408 int64_t pow2 = N1C->getSExtValue(); 1409 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1410 unsigned lg2 = Log2_64(abs2); 1411 1412 // Splat the sign bit into the register 1413 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1414 DAG.getConstant(VT.getSizeInBits()-1, 1415 getShiftAmountTy())); 1416 AddToWorkList(SGN.getNode()); 1417 1418 // Add (N0 < 0) ? abs2 - 1 : 0; 1419 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1420 DAG.getConstant(VT.getSizeInBits() - lg2, 1421 getShiftAmountTy())); 1422 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1423 AddToWorkList(SRL.getNode()); 1424 AddToWorkList(ADD.getNode()); // Divide by pow2 1425 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1426 DAG.getConstant(lg2, getShiftAmountTy())); 1427 1428 // If we're dividing by a positive value, we're done. Otherwise, we must 1429 // negate the result. 1430 if (pow2 > 0) 1431 return SRA; 1432 1433 AddToWorkList(SRA.getNode()); 1434 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1435 DAG.getConstant(0, VT), SRA); 1436 } 1437 1438 // if integer divide is expensive and we satisfy the requirements, emit an 1439 // alternate sequence. 1440 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1441 !TLI.isIntDivCheap()) { 1442 SDValue Op = BuildSDIV(N); 1443 if (Op.getNode()) return Op; 1444 } 1445 1446 // undef / X -> 0 1447 if (N0.getOpcode() == ISD::UNDEF) 1448 return DAG.getConstant(0, VT); 1449 // X / undef -> undef 1450 if (N1.getOpcode() == ISD::UNDEF) 1451 return N1; 1452 1453 return SDValue(); 1454} 1455 1456SDValue DAGCombiner::visitUDIV(SDNode *N) { 1457 SDValue N0 = N->getOperand(0); 1458 SDValue N1 = N->getOperand(1); 1459 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1460 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1461 MVT VT = N->getValueType(0); 1462 1463 // fold vector ops 1464 if (VT.isVector()) { 1465 SDValue FoldedVOp = SimplifyVBinOp(N); 1466 if (FoldedVOp.getNode()) return FoldedVOp; 1467 } 1468 1469 // fold (udiv c1, c2) -> c1/c2 1470 if (N0C && N1C && !N1C->isNullValue()) 1471 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1472 // fold (udiv x, (1 << c)) -> x >>u c 1473 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1474 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1475 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1476 getShiftAmountTy())); 1477 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1478 if (N1.getOpcode() == ISD::SHL) { 1479 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1480 if (SHC->getAPIntValue().isPowerOf2()) { 1481 MVT ADDVT = N1.getOperand(1).getValueType(); 1482 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1483 N1.getOperand(1), 1484 DAG.getConstant(SHC->getAPIntValue() 1485 .logBase2(), 1486 ADDVT)); 1487 AddToWorkList(Add.getNode()); 1488 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1489 } 1490 } 1491 } 1492 // fold (udiv x, c) -> alternate 1493 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1494 SDValue Op = BuildUDIV(N); 1495 if (Op.getNode()) return Op; 1496 } 1497 1498 // undef / X -> 0 1499 if (N0.getOpcode() == ISD::UNDEF) 1500 return DAG.getConstant(0, VT); 1501 // X / undef -> undef 1502 if (N1.getOpcode() == ISD::UNDEF) 1503 return N1; 1504 1505 return SDValue(); 1506} 1507 1508SDValue DAGCombiner::visitSREM(SDNode *N) { 1509 SDValue N0 = N->getOperand(0); 1510 SDValue N1 = N->getOperand(1); 1511 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1512 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1513 MVT VT = N->getValueType(0); 1514 1515 // fold (srem c1, c2) -> c1%c2 1516 if (N0C && N1C && !N1C->isNullValue()) 1517 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1518 // If we know the sign bits of both operands are zero, strength reduce to a 1519 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1520 if (!VT.isVector()) { 1521 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1522 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1523 } 1524 1525 // If X/C can be simplified by the division-by-constant logic, lower 1526 // X%C to the equivalent of X-X/C*C. 1527 if (N1C && !N1C->isNullValue()) { 1528 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1529 AddToWorkList(Div.getNode()); 1530 SDValue OptimizedDiv = combine(Div.getNode()); 1531 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1532 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1533 OptimizedDiv, N1); 1534 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1535 AddToWorkList(Mul.getNode()); 1536 return Sub; 1537 } 1538 } 1539 1540 // undef % X -> 0 1541 if (N0.getOpcode() == ISD::UNDEF) 1542 return DAG.getConstant(0, VT); 1543 // X % undef -> undef 1544 if (N1.getOpcode() == ISD::UNDEF) 1545 return N1; 1546 1547 return SDValue(); 1548} 1549 1550SDValue DAGCombiner::visitUREM(SDNode *N) { 1551 SDValue N0 = N->getOperand(0); 1552 SDValue N1 = N->getOperand(1); 1553 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1554 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1555 MVT VT = N->getValueType(0); 1556 1557 // fold (urem c1, c2) -> c1%c2 1558 if (N0C && N1C && !N1C->isNullValue()) 1559 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1560 // fold (urem x, pow2) -> (and x, pow2-1) 1561 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1562 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1563 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1564 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1565 if (N1.getOpcode() == ISD::SHL) { 1566 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1567 if (SHC->getAPIntValue().isPowerOf2()) { 1568 SDValue Add = 1569 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1570 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1571 VT)); 1572 AddToWorkList(Add.getNode()); 1573 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1574 } 1575 } 1576 } 1577 1578 // If X/C can be simplified by the division-by-constant logic, lower 1579 // X%C to the equivalent of X-X/C*C. 1580 if (N1C && !N1C->isNullValue()) { 1581 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1582 AddToWorkList(Div.getNode()); 1583 SDValue OptimizedDiv = combine(Div.getNode()); 1584 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1585 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1586 OptimizedDiv, N1); 1587 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1588 AddToWorkList(Mul.getNode()); 1589 return Sub; 1590 } 1591 } 1592 1593 // undef % X -> 0 1594 if (N0.getOpcode() == ISD::UNDEF) 1595 return DAG.getConstant(0, VT); 1596 // X % undef -> undef 1597 if (N1.getOpcode() == ISD::UNDEF) 1598 return N1; 1599 1600 return SDValue(); 1601} 1602 1603SDValue DAGCombiner::visitMULHS(SDNode *N) { 1604 SDValue N0 = N->getOperand(0); 1605 SDValue N1 = N->getOperand(1); 1606 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1607 MVT VT = N->getValueType(0); 1608 1609 // fold (mulhs x, 0) -> 0 1610 if (N1C && N1C->isNullValue()) 1611 return N1; 1612 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1613 if (N1C && N1C->getAPIntValue() == 1) 1614 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1615 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1616 getShiftAmountTy())); 1617 // fold (mulhs x, undef) -> 0 1618 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1619 return DAG.getConstant(0, VT); 1620 1621 return SDValue(); 1622} 1623 1624SDValue DAGCombiner::visitMULHU(SDNode *N) { 1625 SDValue N0 = N->getOperand(0); 1626 SDValue N1 = N->getOperand(1); 1627 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1628 MVT VT = N->getValueType(0); 1629 1630 // fold (mulhu x, 0) -> 0 1631 if (N1C && N1C->isNullValue()) 1632 return N1; 1633 // fold (mulhu x, 1) -> 0 1634 if (N1C && N1C->getAPIntValue() == 1) 1635 return DAG.getConstant(0, N0.getValueType()); 1636 // fold (mulhu x, undef) -> 0 1637 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1638 return DAG.getConstant(0, VT); 1639 1640 return SDValue(); 1641} 1642 1643/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1644/// compute two values. LoOp and HiOp give the opcodes for the two computations 1645/// that are being performed. Return true if a simplification was made. 1646/// 1647SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1648 unsigned HiOp) { 1649 // If the high half is not needed, just compute the low half. 1650 bool HiExists = N->hasAnyUseOfValue(1); 1651 if (!HiExists && 1652 (!LegalOperations || 1653 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1654 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1655 N->op_begin(), N->getNumOperands()); 1656 return CombineTo(N, Res, Res); 1657 } 1658 1659 // If the low half is not needed, just compute the high half. 1660 bool LoExists = N->hasAnyUseOfValue(0); 1661 if (!LoExists && 1662 (!LegalOperations || 1663 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1664 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1665 N->op_begin(), N->getNumOperands()); 1666 return CombineTo(N, Res, Res); 1667 } 1668 1669 // If both halves are used, return as it is. 1670 if (LoExists && HiExists) 1671 return SDValue(); 1672 1673 // If the two computed results can be simplified separately, separate them. 1674 if (LoExists) { 1675 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1676 N->op_begin(), N->getNumOperands()); 1677 AddToWorkList(Lo.getNode()); 1678 SDValue LoOpt = combine(Lo.getNode()); 1679 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1680 (!LegalOperations || 1681 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1682 return CombineTo(N, LoOpt, LoOpt); 1683 } 1684 1685 if (HiExists) { 1686 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1687 N->op_begin(), N->getNumOperands()); 1688 AddToWorkList(Hi.getNode()); 1689 SDValue HiOpt = combine(Hi.getNode()); 1690 if (HiOpt.getNode() && HiOpt != Hi && 1691 (!LegalOperations || 1692 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1693 return CombineTo(N, HiOpt, HiOpt); 1694 } 1695 1696 return SDValue(); 1697} 1698 1699SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1700 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1701 if (Res.getNode()) return Res; 1702 1703 return SDValue(); 1704} 1705 1706SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1707 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1708 if (Res.getNode()) return Res; 1709 1710 return SDValue(); 1711} 1712 1713SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1714 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1715 if (Res.getNode()) return Res; 1716 1717 return SDValue(); 1718} 1719 1720SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1721 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1722 if (Res.getNode()) return Res; 1723 1724 return SDValue(); 1725} 1726 1727/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1728/// two operands of the same opcode, try to simplify it. 1729SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1730 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1731 MVT VT = N0.getValueType(); 1732 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1733 1734 // For each of OP in AND/OR/XOR: 1735 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1736 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1737 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1738 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1739 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1740 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1741 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1742 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1743 N0.getOperand(0).getValueType(), 1744 N0.getOperand(0), N1.getOperand(0)); 1745 AddToWorkList(ORNode.getNode()); 1746 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1747 } 1748 1749 // For each of OP in SHL/SRL/SRA/AND... 1750 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1751 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1752 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1753 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1754 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1755 N0.getOperand(1) == N1.getOperand(1)) { 1756 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1757 N0.getOperand(0).getValueType(), 1758 N0.getOperand(0), N1.getOperand(0)); 1759 AddToWorkList(ORNode.getNode()); 1760 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1761 ORNode, N0.getOperand(1)); 1762 } 1763 1764 return SDValue(); 1765} 1766 1767SDValue DAGCombiner::visitAND(SDNode *N) { 1768 SDValue N0 = N->getOperand(0); 1769 SDValue N1 = N->getOperand(1); 1770 SDValue LL, LR, RL, RR, CC0, CC1; 1771 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1772 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1773 MVT VT = N1.getValueType(); 1774 unsigned BitWidth = VT.getSizeInBits(); 1775 1776 // fold vector ops 1777 if (VT.isVector()) { 1778 SDValue FoldedVOp = SimplifyVBinOp(N); 1779 if (FoldedVOp.getNode()) return FoldedVOp; 1780 } 1781 1782 // fold (and x, undef) -> 0 1783 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1784 return DAG.getConstant(0, VT); 1785 // fold (and c1, c2) -> c1&c2 1786 if (N0C && N1C) 1787 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1788 // canonicalize constant to RHS 1789 if (N0C && !N1C) 1790 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1791 // fold (and x, -1) -> x 1792 if (N1C && N1C->isAllOnesValue()) 1793 return N0; 1794 // if (and x, c) is known to be zero, return 0 1795 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1796 APInt::getAllOnesValue(BitWidth))) 1797 return DAG.getConstant(0, VT); 1798 // reassociate and 1799 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1800 if (RAND.getNode() != 0) 1801 return RAND; 1802 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1803 if (N1C && N0.getOpcode() == ISD::OR) 1804 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1805 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1806 return N1; 1807 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1808 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1809 SDValue N0Op0 = N0.getOperand(0); 1810 APInt Mask = ~N1C->getAPIntValue(); 1811 Mask.trunc(N0Op0.getValueSizeInBits()); 1812 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1813 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1814 N0.getValueType(), N0Op0); 1815 1816 // Replace uses of the AND with uses of the Zero extend node. 1817 CombineTo(N, Zext); 1818 1819 // We actually want to replace all uses of the any_extend with the 1820 // zero_extend, to avoid duplicating things. This will later cause this 1821 // AND to be folded. 1822 CombineTo(N0.getNode(), Zext); 1823 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1824 } 1825 } 1826 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1827 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1828 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1829 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1830 1831 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1832 LL.getValueType().isInteger()) { 1833 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1834 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1835 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1836 LR.getValueType(), LL, RL); 1837 AddToWorkList(ORNode.getNode()); 1838 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1839 } 1840 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1841 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1842 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1843 LR.getValueType(), LL, RL); 1844 AddToWorkList(ANDNode.getNode()); 1845 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1846 } 1847 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1848 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1849 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1850 LR.getValueType(), LL, RL); 1851 AddToWorkList(ORNode.getNode()); 1852 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1853 } 1854 } 1855 // canonicalize equivalent to ll == rl 1856 if (LL == RR && LR == RL) { 1857 Op1 = ISD::getSetCCSwappedOperands(Op1); 1858 std::swap(RL, RR); 1859 } 1860 if (LL == RL && LR == RR) { 1861 bool isInteger = LL.getValueType().isInteger(); 1862 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1863 if (Result != ISD::SETCC_INVALID && 1864 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1865 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1866 LL, LR, Result); 1867 } 1868 } 1869 1870 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1871 if (N0.getOpcode() == N1.getOpcode()) { 1872 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1873 if (Tmp.getNode()) return Tmp; 1874 } 1875 1876 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1877 // fold (and (sra)) -> (and (srl)) when possible. 1878 if (!VT.isVector() && 1879 SimplifyDemandedBits(SDValue(N, 0))) 1880 return SDValue(N, 0); 1881 // fold (zext_inreg (extload x)) -> (zextload x) 1882 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1883 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1884 MVT EVT = LN0->getMemoryVT(); 1885 // If we zero all the possible extended bits, then we can turn this into 1886 // a zextload if we are running before legalize or the operation is legal. 1887 unsigned BitWidth = N1.getValueSizeInBits(); 1888 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1889 BitWidth - EVT.getSizeInBits())) && 1890 ((!LegalOperations && !LN0->isVolatile()) || 1891 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1892 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1893 LN0->getChain(), LN0->getBasePtr(), 1894 LN0->getSrcValue(), 1895 LN0->getSrcValueOffset(), EVT, 1896 LN0->isVolatile(), LN0->getAlignment()); 1897 AddToWorkList(N); 1898 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1899 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1900 } 1901 } 1902 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1903 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1904 N0.hasOneUse()) { 1905 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1906 MVT EVT = LN0->getMemoryVT(); 1907 // If we zero all the possible extended bits, then we can turn this into 1908 // a zextload if we are running before legalize or the operation is legal. 1909 unsigned BitWidth = N1.getValueSizeInBits(); 1910 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1911 BitWidth - EVT.getSizeInBits())) && 1912 ((!LegalOperations && !LN0->isVolatile()) || 1913 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1914 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1915 LN0->getChain(), 1916 LN0->getBasePtr(), LN0->getSrcValue(), 1917 LN0->getSrcValueOffset(), EVT, 1918 LN0->isVolatile(), LN0->getAlignment()); 1919 AddToWorkList(N); 1920 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1921 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1922 } 1923 } 1924 1925 // fold (and (load x), 255) -> (zextload x, i8) 1926 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1927 if (N1C && N0.getOpcode() == ISD::LOAD) { 1928 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1929 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1930 LN0->isUnindexed() && N0.hasOneUse() && 1931 // Do not change the width of a volatile load. 1932 !LN0->isVolatile()) { 1933 MVT EVT = MVT::Other; 1934 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1935 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1936 EVT = MVT::getIntegerVT(ActiveBits); 1937 1938 MVT LoadedVT = LN0->getMemoryVT(); 1939 1940 // Do not generate loads of non-round integer types since these can 1941 // be expensive (and would be wrong if the type is not byte sized). 1942 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1943 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1944 MVT PtrType = N0.getOperand(1).getValueType(); 1945 1946 // For big endian targets, we need to add an offset to the pointer to 1947 // load the correct bytes. For little endian systems, we merely need to 1948 // read fewer bytes from the same pointer. 1949 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1950 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1951 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1952 unsigned Alignment = LN0->getAlignment(); 1953 SDValue NewPtr = LN0->getBasePtr(); 1954 1955 if (TLI.isBigEndian()) { 1956 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1957 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1958 Alignment = MinAlign(Alignment, PtrOff); 1959 } 1960 1961 AddToWorkList(NewPtr.getNode()); 1962 SDValue Load = 1963 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1964 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1965 EVT, LN0->isVolatile(), Alignment); 1966 AddToWorkList(N); 1967 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1968 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1969 } 1970 } 1971 } 1972 1973 return SDValue(); 1974} 1975 1976SDValue DAGCombiner::visitOR(SDNode *N) { 1977 SDValue N0 = N->getOperand(0); 1978 SDValue N1 = N->getOperand(1); 1979 SDValue LL, LR, RL, RR, CC0, CC1; 1980 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1981 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1982 MVT VT = N1.getValueType(); 1983 1984 // fold vector ops 1985 if (VT.isVector()) { 1986 SDValue FoldedVOp = SimplifyVBinOp(N); 1987 if (FoldedVOp.getNode()) return FoldedVOp; 1988 } 1989 1990 // fold (or x, undef) -> -1 1991 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1992 return DAG.getConstant(~0ULL, VT); 1993 // fold (or c1, c2) -> c1|c2 1994 if (N0C && N1C) 1995 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1996 // canonicalize constant to RHS 1997 if (N0C && !N1C) 1998 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1999 // fold (or x, 0) -> x 2000 if (N1C && N1C->isNullValue()) 2001 return N0; 2002 // fold (or x, -1) -> -1 2003 if (N1C && N1C->isAllOnesValue()) 2004 return N1; 2005 // fold (or x, c) -> c iff (x & ~c) == 0 2006 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2007 return N1; 2008 // reassociate or 2009 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2010 if (ROR.getNode() != 0) 2011 return ROR; 2012 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2013 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2014 isa<ConstantSDNode>(N0.getOperand(1))) { 2015 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2016 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2017 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2018 N0.getOperand(0), N1), 2019 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2020 } 2021 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2022 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2023 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2024 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2025 2026 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2027 LL.getValueType().isInteger()) { 2028 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2029 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2030 if (cast<ConstantSDNode>(LR)->isNullValue() && 2031 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2032 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2033 LR.getValueType(), LL, RL); 2034 AddToWorkList(ORNode.getNode()); 2035 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2036 } 2037 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2038 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2039 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2040 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2041 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2042 LR.getValueType(), LL, RL); 2043 AddToWorkList(ANDNode.getNode()); 2044 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2045 } 2046 } 2047 // canonicalize equivalent to ll == rl 2048 if (LL == RR && LR == RL) { 2049 Op1 = ISD::getSetCCSwappedOperands(Op1); 2050 std::swap(RL, RR); 2051 } 2052 if (LL == RL && LR == RR) { 2053 bool isInteger = LL.getValueType().isInteger(); 2054 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2055 if (Result != ISD::SETCC_INVALID && 2056 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2057 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2058 LL, LR, Result); 2059 } 2060 } 2061 2062 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2063 if (N0.getOpcode() == N1.getOpcode()) { 2064 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2065 if (Tmp.getNode()) return Tmp; 2066 } 2067 2068 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2069 if (N0.getOpcode() == ISD::AND && 2070 N1.getOpcode() == ISD::AND && 2071 N0.getOperand(1).getOpcode() == ISD::Constant && 2072 N1.getOperand(1).getOpcode() == ISD::Constant && 2073 // Don't increase # computations. 2074 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2075 // We can only do this xform if we know that bits from X that are set in C2 2076 // but not in C1 are already zero. Likewise for Y. 2077 const APInt &LHSMask = 2078 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2079 const APInt &RHSMask = 2080 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2081 2082 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2083 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2084 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2085 N0.getOperand(0), N1.getOperand(0)); 2086 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2087 DAG.getConstant(LHSMask | RHSMask, VT)); 2088 } 2089 } 2090 2091 // See if this is some rotate idiom. 2092 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2093 return SDValue(Rot, 0); 2094 2095 return SDValue(); 2096} 2097 2098/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2099static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2100 if (Op.getOpcode() == ISD::AND) { 2101 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2102 Mask = Op.getOperand(1); 2103 Op = Op.getOperand(0); 2104 } else { 2105 return false; 2106 } 2107 } 2108 2109 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2110 Shift = Op; 2111 return true; 2112 } 2113 2114 return false; 2115} 2116 2117// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2118// idioms for rotate, and if the target supports rotation instructions, generate 2119// a rot[lr]. 2120SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2121 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2122 MVT VT = LHS.getValueType(); 2123 if (!TLI.isTypeLegal(VT)) return 0; 2124 2125 // The target must have at least one rotate flavor. 2126 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2127 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2128 if (!HasROTL && !HasROTR) return 0; 2129 2130 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2131 SDValue LHSShift; // The shift. 2132 SDValue LHSMask; // AND value if any. 2133 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2134 return 0; // Not part of a rotate. 2135 2136 SDValue RHSShift; // The shift. 2137 SDValue RHSMask; // AND value if any. 2138 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2139 return 0; // Not part of a rotate. 2140 2141 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2142 return 0; // Not shifting the same value. 2143 2144 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2145 return 0; // Shifts must disagree. 2146 2147 // Canonicalize shl to left side in a shl/srl pair. 2148 if (RHSShift.getOpcode() == ISD::SHL) { 2149 std::swap(LHS, RHS); 2150 std::swap(LHSShift, RHSShift); 2151 std::swap(LHSMask , RHSMask ); 2152 } 2153 2154 unsigned OpSizeInBits = VT.getSizeInBits(); 2155 SDValue LHSShiftArg = LHSShift.getOperand(0); 2156 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2157 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2158 2159 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2160 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2161 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2162 RHSShiftAmt.getOpcode() == ISD::Constant) { 2163 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2164 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2165 if ((LShVal + RShVal) != OpSizeInBits) 2166 return 0; 2167 2168 SDValue Rot; 2169 if (HasROTL) 2170 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2171 else 2172 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2173 2174 // If there is an AND of either shifted operand, apply it to the result. 2175 if (LHSMask.getNode() || RHSMask.getNode()) { 2176 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2177 2178 if (LHSMask.getNode()) { 2179 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2180 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2181 } 2182 if (RHSMask.getNode()) { 2183 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2184 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2185 } 2186 2187 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2188 } 2189 2190 return Rot.getNode(); 2191 } 2192 2193 // If there is a mask here, and we have a variable shift, we can't be sure 2194 // that we're masking out the right stuff. 2195 if (LHSMask.getNode() || RHSMask.getNode()) 2196 return 0; 2197 2198 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2199 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2200 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2201 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2202 if (ConstantSDNode *SUBC = 2203 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2204 if (SUBC->getAPIntValue() == OpSizeInBits) { 2205 if (HasROTL) 2206 return DAG.getNode(ISD::ROTL, DL, VT, 2207 LHSShiftArg, LHSShiftAmt).getNode(); 2208 else 2209 return DAG.getNode(ISD::ROTR, DL, VT, 2210 LHSShiftArg, RHSShiftAmt).getNode(); 2211 } 2212 } 2213 } 2214 2215 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2216 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2217 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2218 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2219 if (ConstantSDNode *SUBC = 2220 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2221 if (SUBC->getAPIntValue() == OpSizeInBits) { 2222 if (HasROTR) 2223 return DAG.getNode(ISD::ROTR, DL, VT, 2224 LHSShiftArg, RHSShiftAmt).getNode(); 2225 else 2226 return DAG.getNode(ISD::ROTL, DL, VT, 2227 LHSShiftArg, LHSShiftAmt).getNode(); 2228 } 2229 } 2230 } 2231 2232 // Look for sign/zext/any-extended or truncate cases: 2233 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2234 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2235 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2236 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2237 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2238 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2239 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2240 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2241 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2242 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2243 if (RExtOp0.getOpcode() == ISD::SUB && 2244 RExtOp0.getOperand(1) == LExtOp0) { 2245 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2246 // (rotl x, y) 2247 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2248 // (rotr x, (sub 32, y)) 2249 if (ConstantSDNode *SUBC = 2250 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2251 if (SUBC->getAPIntValue() == OpSizeInBits) { 2252 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2253 LHSShiftArg, 2254 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2255 } 2256 } 2257 } else if (LExtOp0.getOpcode() == ISD::SUB && 2258 RExtOp0 == LExtOp0.getOperand(1)) { 2259 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2260 // (rotr x, y) 2261 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2262 // (rotl x, (sub 32, y)) 2263 if (ConstantSDNode *SUBC = 2264 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2265 if (SUBC->getAPIntValue() == OpSizeInBits) { 2266 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2267 LHSShiftArg, 2268 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2269 } 2270 } 2271 } 2272 } 2273 2274 return 0; 2275} 2276 2277SDValue DAGCombiner::visitXOR(SDNode *N) { 2278 SDValue N0 = N->getOperand(0); 2279 SDValue N1 = N->getOperand(1); 2280 SDValue LHS, RHS, CC; 2281 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2282 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2283 MVT VT = N0.getValueType(); 2284 2285 // fold vector ops 2286 if (VT.isVector()) { 2287 SDValue FoldedVOp = SimplifyVBinOp(N); 2288 if (FoldedVOp.getNode()) return FoldedVOp; 2289 } 2290 2291 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2292 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2293 return DAG.getConstant(0, VT); 2294 // fold (xor x, undef) -> undef 2295 if (N0.getOpcode() == ISD::UNDEF) 2296 return N0; 2297 if (N1.getOpcode() == ISD::UNDEF) 2298 return N1; 2299 // fold (xor c1, c2) -> c1^c2 2300 if (N0C && N1C) 2301 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2302 // canonicalize constant to RHS 2303 if (N0C && !N1C) 2304 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2305 // fold (xor x, 0) -> x 2306 if (N1C && N1C->isNullValue()) 2307 return N0; 2308 // reassociate xor 2309 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2310 if (RXOR.getNode() != 0) 2311 return RXOR; 2312 2313 // fold !(x cc y) -> (x !cc y) 2314 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2315 bool isInt = LHS.getValueType().isInteger(); 2316 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2317 isInt); 2318 2319 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2320 switch (N0.getOpcode()) { 2321 default: 2322 assert(0 && "Unhandled SetCC Equivalent!"); 2323 abort(); 2324 case ISD::SETCC: 2325 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2326 case ISD::SELECT_CC: 2327 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2328 N0.getOperand(3), NotCC); 2329 } 2330 } 2331 } 2332 2333 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2334 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2335 N0.getNode()->hasOneUse() && 2336 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2337 SDValue V = N0.getOperand(0); 2338 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2339 DAG.getConstant(1, V.getValueType())); 2340 AddToWorkList(V.getNode()); 2341 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2342 } 2343 2344 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2345 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2346 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2347 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2348 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2349 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2350 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2351 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2352 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2353 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2354 } 2355 } 2356 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2357 if (N1C && N1C->isAllOnesValue() && 2358 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2359 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2360 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2361 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2362 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2363 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2364 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2365 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2366 } 2367 } 2368 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2369 if (N1C && N0.getOpcode() == ISD::XOR) { 2370 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2371 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2372 if (N00C) 2373 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2374 DAG.getConstant(N1C->getAPIntValue() ^ 2375 N00C->getAPIntValue(), VT)); 2376 if (N01C) 2377 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2378 DAG.getConstant(N1C->getAPIntValue() ^ 2379 N01C->getAPIntValue(), VT)); 2380 } 2381 // fold (xor x, x) -> 0 2382 if (N0 == N1) { 2383 if (!VT.isVector()) { 2384 return DAG.getConstant(0, VT); 2385 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2386 // Produce a vector of zeros. 2387 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2388 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2389 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2390 &Ops[0], Ops.size()); 2391 } 2392 } 2393 2394 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2395 if (N0.getOpcode() == N1.getOpcode()) { 2396 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2397 if (Tmp.getNode()) return Tmp; 2398 } 2399 2400 // Simplify the expression using non-local knowledge. 2401 if (!VT.isVector() && 2402 SimplifyDemandedBits(SDValue(N, 0))) 2403 return SDValue(N, 0); 2404 2405 return SDValue(); 2406} 2407 2408/// visitShiftByConstant - Handle transforms common to the three shifts, when 2409/// the shift amount is a constant. 2410SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2411 SDNode *LHS = N->getOperand(0).getNode(); 2412 if (!LHS->hasOneUse()) return SDValue(); 2413 2414 // We want to pull some binops through shifts, so that we have (and (shift)) 2415 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2416 // thing happens with address calculations, so it's important to canonicalize 2417 // it. 2418 bool HighBitSet = false; // Can we transform this if the high bit is set? 2419 2420 switch (LHS->getOpcode()) { 2421 default: return SDValue(); 2422 case ISD::OR: 2423 case ISD::XOR: 2424 HighBitSet = false; // We can only transform sra if the high bit is clear. 2425 break; 2426 case ISD::AND: 2427 HighBitSet = true; // We can only transform sra if the high bit is set. 2428 break; 2429 case ISD::ADD: 2430 if (N->getOpcode() != ISD::SHL) 2431 return SDValue(); // only shl(add) not sr[al](add). 2432 HighBitSet = false; // We can only transform sra if the high bit is clear. 2433 break; 2434 } 2435 2436 // We require the RHS of the binop to be a constant as well. 2437 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2438 if (!BinOpCst) return SDValue(); 2439 2440 // FIXME: disable this unless the input to the binop is a shift by a constant. 2441 // If it is not a shift, it pessimizes some common cases like: 2442 // 2443 // void foo(int *X, int i) { X[i & 1235] = 1; } 2444 // int bar(int *X, int i) { return X[i & 255]; } 2445 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2446 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2447 BinOpLHSVal->getOpcode() != ISD::SRA && 2448 BinOpLHSVal->getOpcode() != ISD::SRL) || 2449 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2450 return SDValue(); 2451 2452 MVT VT = N->getValueType(0); 2453 2454 // If this is a signed shift right, and the high bit is modified by the 2455 // logical operation, do not perform the transformation. The highBitSet 2456 // boolean indicates the value of the high bit of the constant which would 2457 // cause it to be modified for this operation. 2458 if (N->getOpcode() == ISD::SRA) { 2459 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2460 if (BinOpRHSSignSet != HighBitSet) 2461 return SDValue(); 2462 } 2463 2464 // Fold the constants, shifting the binop RHS by the shift amount. 2465 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2466 N->getValueType(0), 2467 LHS->getOperand(1), N->getOperand(1)); 2468 2469 // Create the new shift. 2470 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2471 VT, LHS->getOperand(0), N->getOperand(1)); 2472 2473 // Create the new binop. 2474 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2475} 2476 2477SDValue DAGCombiner::visitSHL(SDNode *N) { 2478 SDValue N0 = N->getOperand(0); 2479 SDValue N1 = N->getOperand(1); 2480 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2481 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2482 MVT VT = N0.getValueType(); 2483 unsigned OpSizeInBits = VT.getSizeInBits(); 2484 2485 // fold (shl c1, c2) -> c1<<c2 2486 if (N0C && N1C) 2487 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2488 // fold (shl 0, x) -> 0 2489 if (N0C && N0C->isNullValue()) 2490 return N0; 2491 // fold (shl x, c >= size(x)) -> undef 2492 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2493 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); 2494 // fold (shl x, 0) -> x 2495 if (N1C && N1C->isNullValue()) 2496 return N0; 2497 // if (shl x, c) is known to be zero, return 0 2498 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2499 APInt::getAllOnesValue(VT.getSizeInBits()))) 2500 return DAG.getConstant(0, VT); 2501 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2502 if (N1.getOpcode() == ISD::TRUNCATE && 2503 N1.getOperand(0).getOpcode() == ISD::AND && 2504 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2505 SDValue N101 = N1.getOperand(0).getOperand(1); 2506 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2507 MVT TruncVT = N1.getValueType(); 2508 SDValue N100 = N1.getOperand(0).getOperand(0); 2509 APInt TruncC = N101C->getAPIntValue(); 2510 TruncC.trunc(TruncVT.getSizeInBits()); 2511 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2512 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2513 DAG.getNode(ISD::TRUNCATE, 2514 N->getDebugLoc(), 2515 TruncVT, N100), 2516 DAG.getConstant(TruncC, TruncVT))); 2517 } 2518 } 2519 2520 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2521 return SDValue(N, 0); 2522 2523 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2524 if (N1C && N0.getOpcode() == ISD::SHL && 2525 N0.getOperand(1).getOpcode() == ISD::Constant) { 2526 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2527 uint64_t c2 = N1C->getZExtValue(); 2528 if (c1 + c2 > OpSizeInBits) 2529 return DAG.getConstant(0, VT); 2530 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2531 DAG.getConstant(c1 + c2, N1.getValueType())); 2532 } 2533 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2534 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2535 if (N1C && N0.getOpcode() == ISD::SRL && 2536 N0.getOperand(1).getOpcode() == ISD::Constant) { 2537 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2538 uint64_t c2 = N1C->getZExtValue(); 2539 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), 2540 DAG.getConstant(~0ULL << c1, VT)); 2541 if (c2 > c1) 2542 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2543 DAG.getConstant(c2-c1, N1.getValueType())); 2544 else 2545 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2546 DAG.getConstant(c1-c2, N1.getValueType())); 2547 } 2548 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2549 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2550 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2551 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2552 2553 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2554} 2555 2556SDValue DAGCombiner::visitSRA(SDNode *N) { 2557 SDValue N0 = N->getOperand(0); 2558 SDValue N1 = N->getOperand(1); 2559 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2560 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2561 MVT VT = N0.getValueType(); 2562 2563 // fold (sra c1, c2) -> (sra c1, c2) 2564 if (N0C && N1C) 2565 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2566 // fold (sra 0, x) -> 0 2567 if (N0C && N0C->isNullValue()) 2568 return N0; 2569 // fold (sra -1, x) -> -1 2570 if (N0C && N0C->isAllOnesValue()) 2571 return N0; 2572 // fold (sra x, (setge c, size(x))) -> undef 2573 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2574 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); 2575 // fold (sra x, 0) -> x 2576 if (N1C && N1C->isNullValue()) 2577 return N0; 2578 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2579 // sext_inreg. 2580 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2581 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2582 MVT EVT = MVT::getIntegerVT(LowBits); 2583 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2584 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2585 N0.getOperand(0), DAG.getValueType(EVT)); 2586 } 2587 2588 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2589 if (N1C && N0.getOpcode() == ISD::SRA) { 2590 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2591 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2592 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2593 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2594 DAG.getConstant(Sum, N1C->getValueType(0))); 2595 } 2596 } 2597 2598 // fold (sra (shl X, m), (sub result_size, n)) 2599 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2600 // result_size - n != m. 2601 // If truncate is free for the target sext(shl) is likely to result in better 2602 // code. 2603 if (N0.getOpcode() == ISD::SHL) { 2604 // Get the two constanst of the shifts, CN0 = m, CN = n. 2605 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2606 if (N01C && N1C) { 2607 // Determine what the truncate's result bitsize and type would be. 2608 unsigned VTValSize = VT.getSizeInBits(); 2609 MVT TruncVT = 2610 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2611 // Determine the residual right-shift amount. 2612 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2613 2614 // If the shift is not a no-op (in which case this should be just a sign 2615 // extend already), the truncated to type is legal, sign_extend is legal 2616 // on that type, and the the truncate to that type is both legal and free, 2617 // perform the transform. 2618 if (ShiftAmt && 2619 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2620 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2621 TLI.isTruncateFree(VT, TruncVT)) { 2622 2623 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2624 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2625 N0.getOperand(0), Amt); 2626 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2627 Shift); 2628 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2629 N->getValueType(0), Trunc); 2630 } 2631 } 2632 } 2633 2634 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2635 if (N1.getOpcode() == ISD::TRUNCATE && 2636 N1.getOperand(0).getOpcode() == ISD::AND && 2637 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2638 SDValue N101 = N1.getOperand(0).getOperand(1); 2639 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2640 MVT TruncVT = N1.getValueType(); 2641 SDValue N100 = N1.getOperand(0).getOperand(0); 2642 APInt TruncC = N101C->getAPIntValue(); 2643 TruncC.trunc(TruncVT.getSizeInBits()); 2644 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2645 DAG.getNode(ISD::AND, N->getDebugLoc(), 2646 TruncVT, 2647 DAG.getNode(ISD::TRUNCATE, 2648 N->getDebugLoc(), 2649 TruncVT, N100), 2650 DAG.getConstant(TruncC, TruncVT))); 2651 } 2652 } 2653 2654 // Simplify, based on bits shifted out of the LHS. 2655 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2656 return SDValue(N, 0); 2657 2658 2659 // If the sign bit is known to be zero, switch this to a SRL. 2660 if (DAG.SignBitIsZero(N0)) 2661 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2662 2663 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2664} 2665 2666SDValue DAGCombiner::visitSRL(SDNode *N) { 2667 SDValue N0 = N->getOperand(0); 2668 SDValue N1 = N->getOperand(1); 2669 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2670 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2671 MVT VT = N0.getValueType(); 2672 unsigned OpSizeInBits = VT.getSizeInBits(); 2673 2674 // fold (srl c1, c2) -> c1 >>u c2 2675 if (N0C && N1C) 2676 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2677 // fold (srl 0, x) -> 0 2678 if (N0C && N0C->isNullValue()) 2679 return N0; 2680 // fold (srl x, c >= size(x)) -> undef 2681 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2682 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); 2683 // fold (srl x, 0) -> x 2684 if (N1C && N1C->isNullValue()) 2685 return N0; 2686 // if (srl x, c) is known to be zero, return 0 2687 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2688 APInt::getAllOnesValue(OpSizeInBits))) 2689 return DAG.getConstant(0, VT); 2690 2691 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2692 if (N1C && N0.getOpcode() == ISD::SRL && 2693 N0.getOperand(1).getOpcode() == ISD::Constant) { 2694 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2695 uint64_t c2 = N1C->getZExtValue(); 2696 if (c1 + c2 > OpSizeInBits) 2697 return DAG.getConstant(0, VT); 2698 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2699 DAG.getConstant(c1 + c2, N1.getValueType())); 2700 } 2701 2702 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2703 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2704 // Shifting in all undef bits? 2705 MVT SmallVT = N0.getOperand(0).getValueType(); 2706 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2707 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); 2708 2709 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2710 N0.getOperand(0), N1); 2711 AddToWorkList(SmallShift.getNode()); 2712 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2713 } 2714 2715 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2716 // bit, which is unmodified by sra. 2717 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2718 if (N0.getOpcode() == ISD::SRA) 2719 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2720 } 2721 2722 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2723 if (N1C && N0.getOpcode() == ISD::CTLZ && 2724 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2725 APInt KnownZero, KnownOne; 2726 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2727 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2728 2729 // If any of the input bits are KnownOne, then the input couldn't be all 2730 // zeros, thus the result of the srl will always be zero. 2731 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2732 2733 // If all of the bits input the to ctlz node are known to be zero, then 2734 // the result of the ctlz is "32" and the result of the shift is one. 2735 APInt UnknownBits = ~KnownZero & Mask; 2736 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2737 2738 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2739 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2740 // Okay, we know that only that the single bit specified by UnknownBits 2741 // could be set on input to the CTLZ node. If this bit is set, the SRL 2742 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2743 // to an SRL/XOR pair, which is likely to simplify more. 2744 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2745 SDValue Op = N0.getOperand(0); 2746 2747 if (ShAmt) { 2748 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2749 DAG.getConstant(ShAmt, getShiftAmountTy())); 2750 AddToWorkList(Op.getNode()); 2751 } 2752 2753 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2754 Op, DAG.getConstant(1, VT)); 2755 } 2756 } 2757 2758 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2759 if (N1.getOpcode() == ISD::TRUNCATE && 2760 N1.getOperand(0).getOpcode() == ISD::AND && 2761 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2762 SDValue N101 = N1.getOperand(0).getOperand(1); 2763 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2764 MVT TruncVT = N1.getValueType(); 2765 SDValue N100 = N1.getOperand(0).getOperand(0); 2766 APInt TruncC = N101C->getAPIntValue(); 2767 TruncC.trunc(TruncVT.getSizeInBits()); 2768 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2769 DAG.getNode(ISD::AND, N->getDebugLoc(), 2770 TruncVT, 2771 DAG.getNode(ISD::TRUNCATE, 2772 N->getDebugLoc(), 2773 TruncVT, N100), 2774 DAG.getConstant(TruncC, TruncVT))); 2775 } 2776 } 2777 2778 // fold operands of srl based on knowledge that the low bits are not 2779 // demanded. 2780 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2781 return SDValue(N, 0); 2782 2783 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2784} 2785 2786SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2787 SDValue N0 = N->getOperand(0); 2788 MVT VT = N->getValueType(0); 2789 2790 // fold (ctlz c1) -> c2 2791 if (isa<ConstantSDNode>(N0)) 2792 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2793 return SDValue(); 2794} 2795 2796SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2797 SDValue N0 = N->getOperand(0); 2798 MVT VT = N->getValueType(0); 2799 2800 // fold (cttz c1) -> c2 2801 if (isa<ConstantSDNode>(N0)) 2802 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2803 return SDValue(); 2804} 2805 2806SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2807 SDValue N0 = N->getOperand(0); 2808 MVT VT = N->getValueType(0); 2809 2810 // fold (ctpop c1) -> c2 2811 if (isa<ConstantSDNode>(N0)) 2812 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2813 return SDValue(); 2814} 2815 2816SDValue DAGCombiner::visitSELECT(SDNode *N) { 2817 SDValue N0 = N->getOperand(0); 2818 SDValue N1 = N->getOperand(1); 2819 SDValue N2 = N->getOperand(2); 2820 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2821 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2822 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2823 MVT VT = N->getValueType(0); 2824 MVT VT0 = N0.getValueType(); 2825 2826 // fold (select C, X, X) -> X 2827 if (N1 == N2) 2828 return N1; 2829 // fold (select true, X, Y) -> X 2830 if (N0C && !N0C->isNullValue()) 2831 return N1; 2832 // fold (select false, X, Y) -> Y 2833 if (N0C && N0C->isNullValue()) 2834 return N2; 2835 // fold (select C, 1, X) -> (or C, X) 2836 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2837 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2838 // fold (select C, 0, 1) -> (xor C, 1) 2839 if (VT.isInteger() && 2840 (VT0 == MVT::i1 || 2841 (VT0.isInteger() && 2842 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2843 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2844 SDValue XORNode; 2845 if (VT == VT0) 2846 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2847 N0, DAG.getConstant(1, VT0)); 2848 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2849 N0, DAG.getConstant(1, VT0)); 2850 AddToWorkList(XORNode.getNode()); 2851 if (VT.bitsGT(VT0)) 2852 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2853 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2854 } 2855 // fold (select C, 0, X) -> (and (not C), X) 2856 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2857 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2858 AddToWorkList(NOTNode.getNode()); 2859 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2860 } 2861 // fold (select C, X, 1) -> (or (not C), X) 2862 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2863 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2864 AddToWorkList(NOTNode.getNode()); 2865 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2866 } 2867 // fold (select C, X, 0) -> (and C, X) 2868 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2869 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2870 // fold (select X, X, Y) -> (or X, Y) 2871 // fold (select X, 1, Y) -> (or X, Y) 2872 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2873 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2874 // fold (select X, Y, X) -> (and X, Y) 2875 // fold (select X, Y, 0) -> (and X, Y) 2876 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2877 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2878 2879 // If we can fold this based on the true/false value, do so. 2880 if (SimplifySelectOps(N, N1, N2)) 2881 return SDValue(N, 0); // Don't revisit N. 2882 2883 // fold selects based on a setcc into other things, such as min/max/abs 2884 if (N0.getOpcode() == ISD::SETCC) { 2885 // FIXME: 2886 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2887 // having to say they don't support SELECT_CC on every type the DAG knows 2888 // about, since there is no way to mark an opcode illegal at all value types 2889 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2890 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2891 N0.getOperand(0), N0.getOperand(1), 2892 N1, N2, N0.getOperand(2)); 2893 else 2894 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2895 } 2896 2897 return SDValue(); 2898} 2899 2900SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2901 SDValue N0 = N->getOperand(0); 2902 SDValue N1 = N->getOperand(1); 2903 SDValue N2 = N->getOperand(2); 2904 SDValue N3 = N->getOperand(3); 2905 SDValue N4 = N->getOperand(4); 2906 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2907 2908 // fold select_cc lhs, rhs, x, x, cc -> x 2909 if (N2 == N3) 2910 return N2; 2911 2912 // Determine if the condition we're dealing with is constant 2913 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2914 N0, N1, CC, false); 2915 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2916 2917 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2918 if (!SCCC->isNullValue()) 2919 return N2; // cond always true -> true val 2920 else 2921 return N3; // cond always false -> false val 2922 } 2923 2924 // Fold to a simpler select_cc 2925 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2926 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2927 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2928 SCC.getOperand(2)); 2929 2930 // If we can fold this based on the true/false value, do so. 2931 if (SimplifySelectOps(N, N2, N3)) 2932 return SDValue(N, 0); // Don't revisit N. 2933 2934 // fold select_cc into other things, such as min/max/abs 2935 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2936} 2937 2938SDValue DAGCombiner::visitSETCC(SDNode *N) { 2939 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2940 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2941} 2942 2943// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2944// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2945// transformation. Returns true if extension are possible and the above 2946// mentioned transformation is profitable. 2947static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2948 unsigned ExtOpc, 2949 SmallVector<SDNode*, 4> &ExtendNodes, 2950 const TargetLowering &TLI) { 2951 bool HasCopyToRegUses = false; 2952 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2953 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2954 UE = N0.getNode()->use_end(); 2955 UI != UE; ++UI) { 2956 SDNode *User = *UI; 2957 if (User == N) 2958 continue; 2959 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2960 if (User->getOpcode() == ISD::SETCC) { 2961 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2962 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2963 // Sign bits will be lost after a zext. 2964 return false; 2965 bool Add = false; 2966 for (unsigned i = 0; i != 2; ++i) { 2967 SDValue UseOp = User->getOperand(i); 2968 if (UseOp == N0) 2969 continue; 2970 if (!isa<ConstantSDNode>(UseOp)) 2971 return false; 2972 Add = true; 2973 } 2974 if (Add) 2975 ExtendNodes.push_back(User); 2976 } else { 2977 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2978 SDValue UseOp = User->getOperand(i); 2979 if (UseOp == N0) { 2980 // If truncate from extended type to original load type is free 2981 // on this target, then it's ok to extend a CopyToReg. 2982 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2983 HasCopyToRegUses = true; 2984 else 2985 return false; 2986 } 2987 } 2988 } 2989 } 2990 2991 if (HasCopyToRegUses) { 2992 bool BothLiveOut = false; 2993 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2994 UI != UE; ++UI) { 2995 SDNode *User = *UI; 2996 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2997 SDValue UseOp = User->getOperand(i); 2998 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2999 BothLiveOut = true; 3000 break; 3001 } 3002 } 3003 } 3004 if (BothLiveOut) 3005 // Both unextended and extended values are live out. There had better be 3006 // good a reason for the transformation. 3007 return ExtendNodes.size(); 3008 } 3009 return true; 3010} 3011 3012SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3013 SDValue N0 = N->getOperand(0); 3014 MVT VT = N->getValueType(0); 3015 3016 // fold (sext c1) -> c1 3017 if (isa<ConstantSDNode>(N0)) 3018 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3019 3020 // fold (sext (sext x)) -> (sext x) 3021 // fold (sext (aext x)) -> (sext x) 3022 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3023 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3024 N0.getOperand(0)); 3025 3026 if (N0.getOpcode() == ISD::TRUNCATE) { 3027 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3028 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3029 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3030 if (NarrowLoad.getNode()) { 3031 if (NarrowLoad.getNode() != N0.getNode()) 3032 CombineTo(N0.getNode(), NarrowLoad); 3033 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3034 } 3035 3036 // See if the value being truncated is already sign extended. If so, just 3037 // eliminate the trunc/sext pair. 3038 SDValue Op = N0.getOperand(0); 3039 unsigned OpBits = Op.getValueType().getSizeInBits(); 3040 unsigned MidBits = N0.getValueType().getSizeInBits(); 3041 unsigned DestBits = VT.getSizeInBits(); 3042 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3043 3044 if (OpBits == DestBits) { 3045 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3046 // bits, it is already ready. 3047 if (NumSignBits > DestBits-MidBits) 3048 return Op; 3049 } else if (OpBits < DestBits) { 3050 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3051 // bits, just sext from i32. 3052 if (NumSignBits > OpBits-MidBits) 3053 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3054 } else { 3055 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3056 // bits, just truncate to i32. 3057 if (NumSignBits > OpBits-MidBits) 3058 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3059 } 3060 3061 // fold (sext (truncate x)) -> (sextinreg x). 3062 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3063 N0.getValueType())) { 3064 if (Op.getValueType().bitsLT(VT)) 3065 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3066 else if (Op.getValueType().bitsGT(VT)) 3067 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3068 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3069 DAG.getValueType(N0.getValueType())); 3070 } 3071 } 3072 3073 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3074 if (ISD::isNON_EXTLoad(N0.getNode()) && 3075 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3076 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3077 bool DoXform = true; 3078 SmallVector<SDNode*, 4> SetCCs; 3079 if (!N0.hasOneUse()) 3080 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3081 if (DoXform) { 3082 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3083 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), 3084 VT, LN0->getChain(), 3085 LN0->getBasePtr(), LN0->getSrcValue(), 3086 LN0->getSrcValueOffset(), 3087 N0.getValueType(), 3088 LN0->isVolatile(), LN0->getAlignment()); 3089 CombineTo(N, ExtLoad); 3090 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3091 N0.getValueType(), ExtLoad); 3092 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3093 3094 // Extend SetCC uses if necessary. 3095 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3096 SDNode *SetCC = SetCCs[i]; 3097 SmallVector<SDValue, 4> Ops; 3098 3099 for (unsigned j = 0; j != 2; ++j) { 3100 SDValue SOp = SetCC->getOperand(j); 3101 if (SOp == Trunc) 3102 Ops.push_back(ExtLoad); 3103 else 3104 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3105 VT, SOp)); 3106 } 3107 3108 Ops.push_back(SetCC->getOperand(2)); 3109 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3110 SetCC->getValueType(0), 3111 &Ops[0], Ops.size())); 3112 } 3113 3114 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3115 } 3116 } 3117 3118 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3119 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3120 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3121 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3122 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3123 MVT EVT = LN0->getMemoryVT(); 3124 if ((!LegalOperations && !LN0->isVolatile()) || 3125 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3126 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3127 LN0->getChain(), 3128 LN0->getBasePtr(), LN0->getSrcValue(), 3129 LN0->getSrcValueOffset(), EVT, 3130 LN0->isVolatile(), LN0->getAlignment()); 3131 CombineTo(N, ExtLoad); 3132 CombineTo(N0.getNode(), 3133 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3134 N0.getValueType(), ExtLoad), 3135 ExtLoad.getValue(1)); 3136 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3137 } 3138 } 3139 3140 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3141 if (N0.getOpcode() == ISD::SETCC) { 3142 SDValue SCC = 3143 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3144 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3145 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3146 if (SCC.getNode()) return SCC; 3147 } 3148 3149 // fold (sext x) -> (zext x) if the sign bit is known zero. 3150 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3151 DAG.SignBitIsZero(N0)) 3152 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3153 3154 return SDValue(); 3155} 3156 3157SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3158 SDValue N0 = N->getOperand(0); 3159 MVT VT = N->getValueType(0); 3160 3161 // fold (zext c1) -> c1 3162 if (isa<ConstantSDNode>(N0)) 3163 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3164 // fold (zext (zext x)) -> (zext x) 3165 // fold (zext (aext x)) -> (zext x) 3166 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3167 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3168 N0.getOperand(0)); 3169 3170 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3171 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3172 if (N0.getOpcode() == ISD::TRUNCATE) { 3173 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3174 if (NarrowLoad.getNode()) { 3175 if (NarrowLoad.getNode() != N0.getNode()) 3176 CombineTo(N0.getNode(), NarrowLoad); 3177 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3178 } 3179 } 3180 3181 // fold (zext (truncate x)) -> (and x, mask) 3182 if (N0.getOpcode() == ISD::TRUNCATE && 3183 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3184 SDValue Op = N0.getOperand(0); 3185 if (Op.getValueType().bitsLT(VT)) { 3186 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3187 } else if (Op.getValueType().bitsGT(VT)) { 3188 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3189 } 3190 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3191 } 3192 3193 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3194 if (N0.getOpcode() == ISD::AND && 3195 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3196 N0.getOperand(1).getOpcode() == ISD::Constant) { 3197 SDValue X = N0.getOperand(0).getOperand(0); 3198 if (X.getValueType().bitsLT(VT)) { 3199 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3200 } else if (X.getValueType().bitsGT(VT)) { 3201 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3202 } 3203 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3204 Mask.zext(VT.getSizeInBits()); 3205 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3206 X, DAG.getConstant(Mask, VT)); 3207 } 3208 3209 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3210 if (ISD::isNON_EXTLoad(N0.getNode()) && 3211 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3212 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3213 bool DoXform = true; 3214 SmallVector<SDNode*, 4> SetCCs; 3215 if (!N0.hasOneUse()) 3216 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3217 if (DoXform) { 3218 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3219 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3220 LN0->getChain(), 3221 LN0->getBasePtr(), LN0->getSrcValue(), 3222 LN0->getSrcValueOffset(), 3223 N0.getValueType(), 3224 LN0->isVolatile(), LN0->getAlignment()); 3225 CombineTo(N, ExtLoad); 3226 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3227 N0.getValueType(), ExtLoad); 3228 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3229 3230 // Extend SetCC uses if necessary. 3231 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3232 SDNode *SetCC = SetCCs[i]; 3233 SmallVector<SDValue, 4> Ops; 3234 3235 for (unsigned j = 0; j != 2; ++j) { 3236 SDValue SOp = SetCC->getOperand(j); 3237 if (SOp == Trunc) 3238 Ops.push_back(ExtLoad); 3239 else 3240 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3241 N->getDebugLoc(), VT, SOp)); 3242 } 3243 3244 Ops.push_back(SetCC->getOperand(2)); 3245 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3246 SetCC->getValueType(0), 3247 &Ops[0], Ops.size())); 3248 } 3249 3250 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3251 } 3252 } 3253 3254 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3255 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3256 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3257 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3258 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3259 MVT EVT = LN0->getMemoryVT(); 3260 if ((!LegalOperations && !LN0->isVolatile()) || 3261 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3262 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3263 LN0->getChain(), 3264 LN0->getBasePtr(), LN0->getSrcValue(), 3265 LN0->getSrcValueOffset(), EVT, 3266 LN0->isVolatile(), LN0->getAlignment()); 3267 CombineTo(N, ExtLoad); 3268 CombineTo(N0.getNode(), 3269 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3270 ExtLoad), 3271 ExtLoad.getValue(1)); 3272 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3273 } 3274 } 3275 3276 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3277 if (N0.getOpcode() == ISD::SETCC) { 3278 SDValue SCC = 3279 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3280 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3281 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3282 if (SCC.getNode()) return SCC; 3283 } 3284 3285 return SDValue(); 3286} 3287 3288SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3289 SDValue N0 = N->getOperand(0); 3290 MVT VT = N->getValueType(0); 3291 3292 // fold (aext c1) -> c1 3293 if (isa<ConstantSDNode>(N0)) 3294 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3295 // fold (aext (aext x)) -> (aext x) 3296 // fold (aext (zext x)) -> (zext x) 3297 // fold (aext (sext x)) -> (sext x) 3298 if (N0.getOpcode() == ISD::ANY_EXTEND || 3299 N0.getOpcode() == ISD::ZERO_EXTEND || 3300 N0.getOpcode() == ISD::SIGN_EXTEND) 3301 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3302 3303 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3304 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3305 if (N0.getOpcode() == ISD::TRUNCATE) { 3306 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3307 if (NarrowLoad.getNode()) { 3308 if (NarrowLoad.getNode() != N0.getNode()) 3309 CombineTo(N0.getNode(), NarrowLoad); 3310 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3311 } 3312 } 3313 3314 // fold (aext (truncate x)) 3315 if (N0.getOpcode() == ISD::TRUNCATE) { 3316 SDValue TruncOp = N0.getOperand(0); 3317 if (TruncOp.getValueType() == VT) 3318 return TruncOp; // x iff x size == zext size. 3319 if (TruncOp.getValueType().bitsGT(VT)) 3320 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3321 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3322 } 3323 3324 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3325 if (N0.getOpcode() == ISD::AND && 3326 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3327 N0.getOperand(1).getOpcode() == ISD::Constant) { 3328 SDValue X = N0.getOperand(0).getOperand(0); 3329 if (X.getValueType().bitsLT(VT)) { 3330 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3331 } else if (X.getValueType().bitsGT(VT)) { 3332 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3333 } 3334 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3335 Mask.zext(VT.getSizeInBits()); 3336 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3337 X, DAG.getConstant(Mask, VT)); 3338 } 3339 3340 // fold (aext (load x)) -> (aext (truncate (extload x))) 3341 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3342 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3343 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3344 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3345 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3346 LN0->getChain(), 3347 LN0->getBasePtr(), LN0->getSrcValue(), 3348 LN0->getSrcValueOffset(), 3349 N0.getValueType(), 3350 LN0->isVolatile(), LN0->getAlignment()); 3351 CombineTo(N, ExtLoad); 3352 // Redirect any chain users to the new load. 3353 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3354 SDValue(ExtLoad.getNode(), 1)); 3355 // If any node needs the original loaded value, recompute it. 3356 if (!LN0->use_empty()) 3357 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3358 N0.getValueType(), ExtLoad), 3359 ExtLoad.getValue(1)); 3360 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3361 } 3362 3363 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3364 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3365 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3366 if (N0.getOpcode() == ISD::LOAD && 3367 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3368 N0.hasOneUse()) { 3369 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3370 MVT EVT = LN0->getMemoryVT(); 3371 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3372 VT, LN0->getChain(), LN0->getBasePtr(), 3373 LN0->getSrcValue(), 3374 LN0->getSrcValueOffset(), EVT, 3375 LN0->isVolatile(), LN0->getAlignment()); 3376 CombineTo(N, ExtLoad); 3377 CombineTo(N0.getNode(), 3378 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3379 N0.getValueType(), ExtLoad), 3380 ExtLoad.getValue(1)); 3381 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3382 } 3383 3384 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3385 if (N0.getOpcode() == ISD::SETCC) { 3386 SDValue SCC = 3387 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3388 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3389 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3390 if (SCC.getNode()) 3391 return SCC; 3392 } 3393 3394 return SDValue(); 3395} 3396 3397/// GetDemandedBits - See if the specified operand can be simplified with the 3398/// knowledge that only the bits specified by Mask are used. If so, return the 3399/// simpler operand, otherwise return a null SDValue. 3400SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3401 switch (V.getOpcode()) { 3402 default: break; 3403 case ISD::OR: 3404 case ISD::XOR: 3405 // If the LHS or RHS don't contribute bits to the or, drop them. 3406 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3407 return V.getOperand(1); 3408 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3409 return V.getOperand(0); 3410 break; 3411 case ISD::SRL: 3412 // Only look at single-use SRLs. 3413 if (!V.getNode()->hasOneUse()) 3414 break; 3415 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3416 // See if we can recursively simplify the LHS. 3417 unsigned Amt = RHSC->getZExtValue(); 3418 3419 // Watch out for shift count overflow though. 3420 if (Amt >= Mask.getBitWidth()) break; 3421 APInt NewMask = Mask << Amt; 3422 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3423 if (SimplifyLHS.getNode()) 3424 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3425 SimplifyLHS, V.getOperand(1)); 3426 } 3427 } 3428 return SDValue(); 3429} 3430 3431/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3432/// bits and then truncated to a narrower type and where N is a multiple 3433/// of number of bits of the narrower type, transform it to a narrower load 3434/// from address + N / num of bits of new type. If the result is to be 3435/// extended, also fold the extension to form a extending load. 3436SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3437 unsigned Opc = N->getOpcode(); 3438 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3439 SDValue N0 = N->getOperand(0); 3440 MVT VT = N->getValueType(0); 3441 MVT EVT = VT; 3442 3443 // This transformation isn't valid for vector loads. 3444 if (VT.isVector()) 3445 return SDValue(); 3446 3447 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3448 // extended to VT. 3449 if (Opc == ISD::SIGN_EXTEND_INREG) { 3450 ExtType = ISD::SEXTLOAD; 3451 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3452 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3453 return SDValue(); 3454 } 3455 3456 unsigned EVTBits = EVT.getSizeInBits(); 3457 unsigned ShAmt = 0; 3458 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3459 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3460 ShAmt = N01->getZExtValue(); 3461 // Is the shift amount a multiple of size of VT? 3462 if ((ShAmt & (EVTBits-1)) == 0) { 3463 N0 = N0.getOperand(0); 3464 if (N0.getValueType().getSizeInBits() <= EVTBits) 3465 return SDValue(); 3466 } 3467 } 3468 } 3469 3470 // Do not generate loads of non-round integer types since these can 3471 // be expensive (and would be wrong if the type is not byte sized). 3472 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3473 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3474 // Do not change the width of a volatile load. 3475 !cast<LoadSDNode>(N0)->isVolatile()) { 3476 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3477 MVT PtrType = N0.getOperand(1).getValueType(); 3478 3479 // For big endian targets, we need to adjust the offset to the pointer to 3480 // load the correct bytes. 3481 if (TLI.isBigEndian()) { 3482 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3483 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3484 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3485 } 3486 3487 uint64_t PtrOff = ShAmt / 8; 3488 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3489 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3490 PtrType, LN0->getBasePtr(), 3491 DAG.getConstant(PtrOff, PtrType)); 3492 AddToWorkList(NewPtr.getNode()); 3493 3494 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3495 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3496 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3497 LN0->isVolatile(), NewAlign) 3498 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3499 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3500 EVT, LN0->isVolatile(), NewAlign); 3501 3502 // Replace the old load's chain with the new load's chain. 3503 WorkListRemover DeadNodes(*this); 3504 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3505 &DeadNodes); 3506 3507 // Return the new loaded value. 3508 return Load; 3509 } 3510 3511 return SDValue(); 3512} 3513 3514SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3515 SDValue N0 = N->getOperand(0); 3516 SDValue N1 = N->getOperand(1); 3517 MVT VT = N->getValueType(0); 3518 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3519 unsigned VTBits = VT.getSizeInBits(); 3520 unsigned EVTBits = EVT.getSizeInBits(); 3521 3522 // fold (sext_in_reg c1) -> c1 3523 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3524 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3525 3526 // If the input is already sign extended, just drop the extension. 3527 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3528 return N0; 3529 3530 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3531 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3532 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3533 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3534 N0.getOperand(0), N1); 3535 } 3536 3537 // fold (sext_in_reg (sext x)) -> (sext x) 3538 // fold (sext_in_reg (aext x)) -> (sext x) 3539 // if x is small enough. 3540 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3541 SDValue N00 = N0.getOperand(0); 3542 if (N00.getValueType().getSizeInBits() < EVTBits) 3543 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3544 } 3545 3546 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3547 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3548 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3549 3550 // fold operands of sext_in_reg based on knowledge that the top bits are not 3551 // demanded. 3552 if (SimplifyDemandedBits(SDValue(N, 0))) 3553 return SDValue(N, 0); 3554 3555 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3556 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3557 SDValue NarrowLoad = ReduceLoadWidth(N); 3558 if (NarrowLoad.getNode()) 3559 return NarrowLoad; 3560 3561 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3562 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3563 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3564 if (N0.getOpcode() == ISD::SRL) { 3565 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3566 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3567 // We can turn this into an SRA iff the input to the SRL is already sign 3568 // extended enough. 3569 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3570 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3571 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3572 N0.getOperand(0), N0.getOperand(1)); 3573 } 3574 } 3575 3576 // fold (sext_inreg (extload x)) -> (sextload x) 3577 if (ISD::isEXTLoad(N0.getNode()) && 3578 ISD::isUNINDEXEDLoad(N0.getNode()) && 3579 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3580 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3581 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3582 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3583 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3584 LN0->getChain(), 3585 LN0->getBasePtr(), LN0->getSrcValue(), 3586 LN0->getSrcValueOffset(), EVT, 3587 LN0->isVolatile(), LN0->getAlignment()); 3588 CombineTo(N, ExtLoad); 3589 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3590 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3591 } 3592 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3593 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3594 N0.hasOneUse() && 3595 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3596 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3597 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3598 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3599 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3600 LN0->getChain(), 3601 LN0->getBasePtr(), LN0->getSrcValue(), 3602 LN0->getSrcValueOffset(), EVT, 3603 LN0->isVolatile(), LN0->getAlignment()); 3604 CombineTo(N, ExtLoad); 3605 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3606 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3607 } 3608 return SDValue(); 3609} 3610 3611SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3612 SDValue N0 = N->getOperand(0); 3613 MVT VT = N->getValueType(0); 3614 3615 // noop truncate 3616 if (N0.getValueType() == N->getValueType(0)) 3617 return N0; 3618 // fold (truncate c1) -> c1 3619 if (isa<ConstantSDNode>(N0)) 3620 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3621 // fold (truncate (truncate x)) -> (truncate x) 3622 if (N0.getOpcode() == ISD::TRUNCATE) 3623 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3624 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3625 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3626 N0.getOpcode() == ISD::ANY_EXTEND) { 3627 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3628 // if the source is smaller than the dest, we still need an extend 3629 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3630 N0.getOperand(0)); 3631 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3632 // if the source is larger than the dest, than we just need the truncate 3633 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3634 else 3635 // if the source and dest are the same type, we can drop both the extend 3636 // and the truncate 3637 return N0.getOperand(0); 3638 } 3639 3640 // See if we can simplify the input to this truncate through knowledge that 3641 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3642 // -> trunc y 3643 SDValue Shorter = 3644 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3645 VT.getSizeInBits())); 3646 if (Shorter.getNode()) 3647 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3648 3649 // fold (truncate (load x)) -> (smaller load x) 3650 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3651 return ReduceLoadWidth(N); 3652} 3653 3654static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3655 SDValue Elt = N->getOperand(i); 3656 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3657 return Elt.getNode(); 3658 return Elt.getOperand(Elt.getResNo()).getNode(); 3659} 3660 3661/// CombineConsecutiveLoads - build_pair (load, load) -> load 3662/// if load locations are consecutive. 3663SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3664 assert(N->getOpcode() == ISD::BUILD_PAIR); 3665 3666 SDNode *LD1 = getBuildPairElt(N, 0); 3667 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3668 return SDValue(); 3669 MVT LD1VT = LD1->getValueType(0); 3670 SDNode *LD2 = getBuildPairElt(N, 1); 3671 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3672 3673 if (ISD::isNON_EXTLoad(LD2) && 3674 LD2->hasOneUse() && 3675 // If both are volatile this would reduce the number of volatile loads. 3676 // If one is volatile it might be ok, but play conservative and bail out. 3677 !cast<LoadSDNode>(LD1)->isVolatile() && 3678 !cast<LoadSDNode>(LD2)->isVolatile() && 3679 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3680 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3681 unsigned Align = LD->getAlignment(); 3682 unsigned NewAlign = TLI.getTargetData()-> 3683 getABITypeAlignment(VT.getTypeForMVT()); 3684 3685 if (NewAlign <= Align && 3686 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3687 return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(), 3688 LD->getSrcValue(), LD->getSrcValueOffset(), 3689 false, Align); 3690 } 3691 3692 return SDValue(); 3693} 3694 3695SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3696 SDValue N0 = N->getOperand(0); 3697 MVT VT = N->getValueType(0); 3698 3699 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3700 // Only do this before legalize, since afterward the target may be depending 3701 // on the bitconvert. 3702 // First check to see if this is all constant. 3703 if (!LegalTypes && 3704 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3705 VT.isVector()) { 3706 bool isSimple = true; 3707 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3708 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3709 N0.getOperand(i).getOpcode() != ISD::Constant && 3710 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3711 isSimple = false; 3712 break; 3713 } 3714 3715 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3716 assert(!DestEltVT.isVector() && 3717 "Element type of vector ValueType must not be vector!"); 3718 if (isSimple) 3719 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3720 } 3721 3722 // If the input is a constant, let getNode fold it. 3723 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3724 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3725 if (Res.getNode() != N) return Res; 3726 } 3727 3728 // (conv (conv x, t1), t2) -> (conv x, t2) 3729 if (N0.getOpcode() == ISD::BIT_CONVERT) 3730 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3731 N0.getOperand(0)); 3732 3733 // fold (conv (load x)) -> (load (conv*)x) 3734 // If the resultant load doesn't need a higher alignment than the original! 3735 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3736 // Do not change the width of a volatile load. 3737 !cast<LoadSDNode>(N0)->isVolatile() && 3738 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3739 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3740 unsigned Align = TLI.getTargetData()-> 3741 getABITypeAlignment(VT.getTypeForMVT()); 3742 unsigned OrigAlign = LN0->getAlignment(); 3743 3744 if (Align <= OrigAlign) { 3745 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3746 LN0->getBasePtr(), 3747 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3748 LN0->isVolatile(), OrigAlign); 3749 AddToWorkList(N); 3750 CombineTo(N0.getNode(), 3751 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3752 N0.getValueType(), Load), 3753 Load.getValue(1)); 3754 return Load; 3755 } 3756 } 3757 3758 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3759 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3760 // This often reduces constant pool loads. 3761 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3762 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3763 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3764 N0.getOperand(0)); 3765 AddToWorkList(NewConv.getNode()); 3766 3767 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3768 if (N0.getOpcode() == ISD::FNEG) 3769 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3770 NewConv, DAG.getConstant(SignBit, VT)); 3771 assert(N0.getOpcode() == ISD::FABS); 3772 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3773 NewConv, DAG.getConstant(~SignBit, VT)); 3774 } 3775 3776 // fold (bitconvert (fcopysign cst, x)) -> 3777 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3778 // Note that we don't handle (copysign x, cst) because this can always be 3779 // folded to an fneg or fabs. 3780 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3781 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3782 VT.isInteger() && !VT.isVector()) { 3783 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3784 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3785 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3786 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3787 IntXVT, N0.getOperand(1)); 3788 AddToWorkList(X.getNode()); 3789 3790 // If X has a different width than the result/lhs, sext it or truncate it. 3791 unsigned VTWidth = VT.getSizeInBits(); 3792 if (OrigXWidth < VTWidth) { 3793 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3794 AddToWorkList(X.getNode()); 3795 } else if (OrigXWidth > VTWidth) { 3796 // To get the sign bit in the right place, we have to shift it right 3797 // before truncating. 3798 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3799 X.getValueType(), X, 3800 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3801 AddToWorkList(X.getNode()); 3802 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3803 AddToWorkList(X.getNode()); 3804 } 3805 3806 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3807 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3808 X, DAG.getConstant(SignBit, VT)); 3809 AddToWorkList(X.getNode()); 3810 3811 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3812 VT, N0.getOperand(0)); 3813 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3814 Cst, DAG.getConstant(~SignBit, VT)); 3815 AddToWorkList(Cst.getNode()); 3816 3817 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3818 } 3819 } 3820 3821 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3822 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3823 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3824 if (CombineLD.getNode()) 3825 return CombineLD; 3826 } 3827 3828 return SDValue(); 3829} 3830 3831SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3832 MVT VT = N->getValueType(0); 3833 return CombineConsecutiveLoads(N, VT); 3834} 3835 3836/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3837/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3838/// destination element value type. 3839SDValue DAGCombiner:: 3840ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3841 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3842 3843 // If this is already the right type, we're done. 3844 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3845 3846 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3847 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3848 3849 // If this is a conversion of N elements of one type to N elements of another 3850 // type, convert each element. This handles FP<->INT cases. 3851 if (SrcBitSize == DstBitSize) { 3852 SmallVector<SDValue, 8> Ops; 3853 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3854 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3855 DstEltVT, BV->getOperand(i))); 3856 AddToWorkList(Ops.back().getNode()); 3857 } 3858 MVT VT = MVT::getVectorVT(DstEltVT, 3859 BV->getValueType(0).getVectorNumElements()); 3860 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3861 &Ops[0], Ops.size()); 3862 } 3863 3864 // Otherwise, we're growing or shrinking the elements. To avoid having to 3865 // handle annoying details of growing/shrinking FP values, we convert them to 3866 // int first. 3867 if (SrcEltVT.isFloatingPoint()) { 3868 // Convert the input float vector to a int vector where the elements are the 3869 // same sizes. 3870 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3871 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3872 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3873 SrcEltVT = IntVT; 3874 } 3875 3876 // Now we know the input is an integer vector. If the output is a FP type, 3877 // convert to integer first, then to FP of the right size. 3878 if (DstEltVT.isFloatingPoint()) { 3879 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3880 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3881 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3882 3883 // Next, convert to FP elements of the same size. 3884 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3885 } 3886 3887 // Okay, we know the src/dst types are both integers of differing types. 3888 // Handling growing first. 3889 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3890 if (SrcBitSize < DstBitSize) { 3891 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3892 3893 SmallVector<SDValue, 8> Ops; 3894 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3895 i += NumInputsPerOutput) { 3896 bool isLE = TLI.isLittleEndian(); 3897 APInt NewBits = APInt(DstBitSize, 0); 3898 bool EltIsUndef = true; 3899 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3900 // Shift the previously computed bits over. 3901 NewBits <<= SrcBitSize; 3902 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3903 if (Op.getOpcode() == ISD::UNDEF) continue; 3904 EltIsUndef = false; 3905 3906 NewBits |= 3907 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3908 } 3909 3910 if (EltIsUndef) 3911 Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT)); 3912 else 3913 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3914 } 3915 3916 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3917 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3918 &Ops[0], Ops.size()); 3919 } 3920 3921 // Finally, this must be the case where we are shrinking elements: each input 3922 // turns into multiple outputs. 3923 bool isS2V = ISD::isScalarToVector(BV); 3924 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3925 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3926 SmallVector<SDValue, 8> Ops; 3927 3928 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3929 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3930 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3931 Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT)); 3932 continue; 3933 } 3934 3935 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3936 3937 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3938 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3939 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3940 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3941 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3942 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3943 Ops[0]); 3944 OpVal = OpVal.lshr(DstBitSize); 3945 } 3946 3947 // For big endian targets, swap the order of the pieces of each element. 3948 if (TLI.isBigEndian()) 3949 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3950 } 3951 3952 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3953 &Ops[0], Ops.size()); 3954} 3955 3956SDValue DAGCombiner::visitFADD(SDNode *N) { 3957 SDValue N0 = N->getOperand(0); 3958 SDValue N1 = N->getOperand(1); 3959 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3960 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3961 MVT VT = N->getValueType(0); 3962 3963 // fold vector ops 3964 if (VT.isVector()) { 3965 SDValue FoldedVOp = SimplifyVBinOp(N); 3966 if (FoldedVOp.getNode()) return FoldedVOp; 3967 } 3968 3969 // fold (fadd c1, c2) -> (fadd c1, c2) 3970 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3971 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3972 // canonicalize constant to RHS 3973 if (N0CFP && !N1CFP) 3974 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3975 // fold (fadd A, 0) -> A 3976 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3977 return N0; 3978 // fold (fadd A, (fneg B)) -> (fsub A, B) 3979 if (isNegatibleForFree(N1, LegalOperations) == 2) 3980 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3981 GetNegatedExpression(N1, DAG, LegalOperations)); 3982 // fold (fadd (fneg A), B) -> (fsub B, A) 3983 if (isNegatibleForFree(N0, LegalOperations) == 2) 3984 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3985 GetNegatedExpression(N0, DAG, LegalOperations)); 3986 3987 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3988 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3989 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3990 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3991 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3992 N0.getOperand(1), N1)); 3993 3994 return SDValue(); 3995} 3996 3997SDValue DAGCombiner::visitFSUB(SDNode *N) { 3998 SDValue N0 = N->getOperand(0); 3999 SDValue N1 = N->getOperand(1); 4000 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4001 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4002 MVT VT = N->getValueType(0); 4003 4004 // fold vector ops 4005 if (VT.isVector()) { 4006 SDValue FoldedVOp = SimplifyVBinOp(N); 4007 if (FoldedVOp.getNode()) return FoldedVOp; 4008 } 4009 4010 // fold (fsub c1, c2) -> c1-c2 4011 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4012 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4013 // fold (fsub A, 0) -> A 4014 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4015 return N0; 4016 // fold (fsub 0, B) -> -B 4017 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4018 if (isNegatibleForFree(N1, LegalOperations)) 4019 return GetNegatedExpression(N1, DAG, LegalOperations); 4020 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4021 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4022 } 4023 // fold (fsub A, (fneg B)) -> (fadd A, B) 4024 if (isNegatibleForFree(N1, LegalOperations)) 4025 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4026 GetNegatedExpression(N1, DAG, LegalOperations)); 4027 4028 return SDValue(); 4029} 4030 4031SDValue DAGCombiner::visitFMUL(SDNode *N) { 4032 SDValue N0 = N->getOperand(0); 4033 SDValue N1 = N->getOperand(1); 4034 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4035 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4036 MVT VT = N->getValueType(0); 4037 4038 // fold vector ops 4039 if (VT.isVector()) { 4040 SDValue FoldedVOp = SimplifyVBinOp(N); 4041 if (FoldedVOp.getNode()) return FoldedVOp; 4042 } 4043 4044 // fold (fmul c1, c2) -> c1*c2 4045 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4046 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4047 // canonicalize constant to RHS 4048 if (N0CFP && !N1CFP) 4049 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4050 // fold (fmul A, 0) -> 0 4051 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4052 return N1; 4053 // fold (fmul X, 2.0) -> (fadd X, X) 4054 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4055 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4056 // fold (fmul X, (fneg 1.0)) -> (fneg X) 4057 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4058 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4059 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4060 4061 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4062 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4063 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4064 // Both can be negated for free, check to see if at least one is cheaper 4065 // negated. 4066 if (LHSNeg == 2 || RHSNeg == 2) 4067 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4068 GetNegatedExpression(N0, DAG, LegalOperations), 4069 GetNegatedExpression(N1, DAG, LegalOperations)); 4070 } 4071 } 4072 4073 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4074 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4075 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4076 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4077 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 4078 4079 return SDValue(); 4080} 4081 4082SDValue DAGCombiner::visitFDIV(SDNode *N) { 4083 SDValue N0 = N->getOperand(0); 4084 SDValue N1 = N->getOperand(1); 4085 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4086 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4087 MVT VT = N->getValueType(0); 4088 4089 // fold vector ops 4090 if (VT.isVector()) { 4091 SDValue FoldedVOp = SimplifyVBinOp(N); 4092 if (FoldedVOp.getNode()) return FoldedVOp; 4093 } 4094 4095 // fold (fdiv c1, c2) -> c1/c2 4096 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4097 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4098 4099 4100 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4101 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4102 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4103 // Both can be negated for free, check to see if at least one is cheaper 4104 // negated. 4105 if (LHSNeg == 2 || RHSNeg == 2) 4106 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4107 GetNegatedExpression(N0, DAG, LegalOperations), 4108 GetNegatedExpression(N1, DAG, LegalOperations)); 4109 } 4110 } 4111 4112 return SDValue(); 4113} 4114 4115SDValue DAGCombiner::visitFREM(SDNode *N) { 4116 SDValue N0 = N->getOperand(0); 4117 SDValue N1 = N->getOperand(1); 4118 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4119 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4120 MVT VT = N->getValueType(0); 4121 4122 // fold (frem c1, c2) -> fmod(c1,c2) 4123 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4124 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4125 4126 return SDValue(); 4127} 4128 4129SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4130 SDValue N0 = N->getOperand(0); 4131 SDValue N1 = N->getOperand(1); 4132 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4133 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4134 MVT VT = N->getValueType(0); 4135 4136 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4137 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4138 4139 if (N1CFP) { 4140 const APFloat& V = N1CFP->getValueAPF(); 4141 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4142 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4143 if (!V.isNegative()) { 4144 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4145 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4146 } else { 4147 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4148 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4149 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4150 } 4151 } 4152 4153 // copysign(fabs(x), y) -> copysign(x, y) 4154 // copysign(fneg(x), y) -> copysign(x, y) 4155 // copysign(copysign(x,z), y) -> copysign(x, y) 4156 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4157 N0.getOpcode() == ISD::FCOPYSIGN) 4158 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4159 N0.getOperand(0), N1); 4160 4161 // copysign(x, abs(y)) -> abs(x) 4162 if (N1.getOpcode() == ISD::FABS) 4163 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4164 4165 // copysign(x, copysign(y,z)) -> copysign(x, z) 4166 if (N1.getOpcode() == ISD::FCOPYSIGN) 4167 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4168 N0, N1.getOperand(1)); 4169 4170 // copysign(x, fp_extend(y)) -> copysign(x, y) 4171 // copysign(x, fp_round(y)) -> copysign(x, y) 4172 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4173 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4174 N0, N1.getOperand(0)); 4175 4176 return SDValue(); 4177} 4178 4179SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4180 SDValue N0 = N->getOperand(0); 4181 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4182 MVT VT = N->getValueType(0); 4183 MVT OpVT = N0.getValueType(); 4184 4185 // fold (sint_to_fp c1) -> c1fp 4186 if (N0C && OpVT != MVT::ppcf128) 4187 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4188 4189 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4190 // but UINT_TO_FP is legal on this target, try to convert. 4191 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4192 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4193 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4194 if (DAG.SignBitIsZero(N0)) 4195 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4196 } 4197 4198 return SDValue(); 4199} 4200 4201SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4202 SDValue N0 = N->getOperand(0); 4203 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4204 MVT VT = N->getValueType(0); 4205 MVT OpVT = N0.getValueType(); 4206 4207 // fold (uint_to_fp c1) -> c1fp 4208 if (N0C && OpVT != MVT::ppcf128) 4209 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4210 4211 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4212 // but SINT_TO_FP is legal on this target, try to convert. 4213 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4214 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4215 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4216 if (DAG.SignBitIsZero(N0)) 4217 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4218 } 4219 4220 return SDValue(); 4221} 4222 4223SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4224 SDValue N0 = N->getOperand(0); 4225 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4226 MVT VT = N->getValueType(0); 4227 4228 // fold (fp_to_sint c1fp) -> c1 4229 if (N0CFP) 4230 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4231 4232 return SDValue(); 4233} 4234 4235SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4236 SDValue N0 = N->getOperand(0); 4237 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4238 MVT VT = N->getValueType(0); 4239 4240 // fold (fp_to_uint c1fp) -> c1 4241 if (N0CFP && VT != MVT::ppcf128) 4242 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4243 4244 return SDValue(); 4245} 4246 4247SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4248 SDValue N0 = N->getOperand(0); 4249 SDValue N1 = N->getOperand(1); 4250 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4251 MVT VT = N->getValueType(0); 4252 4253 // fold (fp_round c1fp) -> c1fp 4254 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4255 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4256 4257 // fold (fp_round (fp_extend x)) -> x 4258 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4259 return N0.getOperand(0); 4260 4261 // fold (fp_round (fp_round x)) -> (fp_round x) 4262 if (N0.getOpcode() == ISD::FP_ROUND) { 4263 // This is a value preserving truncation if both round's are. 4264 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4265 N0.getNode()->getConstantOperandVal(1) == 1; 4266 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4267 DAG.getIntPtrConstant(IsTrunc)); 4268 } 4269 4270 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4271 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4272 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4273 N0.getOperand(0), N1); 4274 AddToWorkList(Tmp.getNode()); 4275 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4276 Tmp, N0.getOperand(1)); 4277 } 4278 4279 return SDValue(); 4280} 4281 4282SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4283 SDValue N0 = N->getOperand(0); 4284 MVT VT = N->getValueType(0); 4285 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4286 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4287 4288 // fold (fp_round_inreg c1fp) -> c1fp 4289 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4290 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4291 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4292 } 4293 4294 return SDValue(); 4295} 4296 4297SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4298 SDValue N0 = N->getOperand(0); 4299 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4300 MVT VT = N->getValueType(0); 4301 4302 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4303 if (N->hasOneUse() && 4304 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4305 return SDValue(); 4306 4307 // fold (fp_extend c1fp) -> c1fp 4308 if (N0CFP && VT != MVT::ppcf128) 4309 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4310 4311 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4312 // value of X. 4313 if (N0.getOpcode() == ISD::FP_ROUND 4314 && N0.getNode()->getConstantOperandVal(1) == 1) { 4315 SDValue In = N0.getOperand(0); 4316 if (In.getValueType() == VT) return In; 4317 if (VT.bitsLT(In.getValueType())) 4318 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4319 In, N0.getOperand(1)); 4320 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4321 } 4322 4323 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4324 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4325 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4326 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4327 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4328 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4329 LN0->getChain(), 4330 LN0->getBasePtr(), LN0->getSrcValue(), 4331 LN0->getSrcValueOffset(), 4332 N0.getValueType(), 4333 LN0->isVolatile(), LN0->getAlignment()); 4334 CombineTo(N, ExtLoad); 4335 CombineTo(N0.getNode(), 4336 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4337 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4338 ExtLoad.getValue(1)); 4339 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4340 } 4341 4342 return SDValue(); 4343} 4344 4345SDValue DAGCombiner::visitFNEG(SDNode *N) { 4346 SDValue N0 = N->getOperand(0); 4347 4348 if (isNegatibleForFree(N0, LegalOperations)) 4349 return GetNegatedExpression(N0, DAG, LegalOperations); 4350 4351 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4352 // constant pool values. 4353 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4354 N0.getOperand(0).getValueType().isInteger() && 4355 !N0.getOperand(0).getValueType().isVector()) { 4356 SDValue Int = N0.getOperand(0); 4357 MVT IntVT = Int.getValueType(); 4358 if (IntVT.isInteger() && !IntVT.isVector()) { 4359 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4360 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4361 AddToWorkList(Int.getNode()); 4362 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4363 N->getValueType(0), Int); 4364 } 4365 } 4366 4367 return SDValue(); 4368} 4369 4370SDValue DAGCombiner::visitFABS(SDNode *N) { 4371 SDValue N0 = N->getOperand(0); 4372 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4373 MVT VT = N->getValueType(0); 4374 4375 // fold (fabs c1) -> fabs(c1) 4376 if (N0CFP && VT != MVT::ppcf128) 4377 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4378 // fold (fabs (fabs x)) -> (fabs x) 4379 if (N0.getOpcode() == ISD::FABS) 4380 return N->getOperand(0); 4381 // fold (fabs (fneg x)) -> (fabs x) 4382 // fold (fabs (fcopysign x, y)) -> (fabs x) 4383 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4384 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4385 4386 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4387 // constant pool values. 4388 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4389 N0.getOperand(0).getValueType().isInteger() && 4390 !N0.getOperand(0).getValueType().isVector()) { 4391 SDValue Int = N0.getOperand(0); 4392 MVT IntVT = Int.getValueType(); 4393 if (IntVT.isInteger() && !IntVT.isVector()) { 4394 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4395 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4396 AddToWorkList(Int.getNode()); 4397 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4398 N->getValueType(0), Int); 4399 } 4400 } 4401 4402 return SDValue(); 4403} 4404 4405SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4406 SDValue Chain = N->getOperand(0); 4407 SDValue N1 = N->getOperand(1); 4408 SDValue N2 = N->getOperand(2); 4409 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4410 4411 // never taken branch, fold to chain 4412 if (N1C && N1C->isNullValue()) 4413 return Chain; 4414 // unconditional branch 4415 if (N1C && N1C->getAPIntValue() == 1) 4416 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4417 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4418 // on the target. 4419 if (N1.getOpcode() == ISD::SETCC && 4420 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4421 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4422 Chain, N1.getOperand(2), 4423 N1.getOperand(0), N1.getOperand(1), N2); 4424 } 4425 4426 return SDValue(); 4427} 4428 4429// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4430// 4431SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4432 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4433 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4434 4435 // Use SimplifySetCC to simplify SETCC's. 4436 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4437 CondLHS, CondRHS, CC->get(), false); 4438 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4439 4440 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4441 4442 // fold br_cc true, dest -> br dest (unconditional branch) 4443 if (SCCC && !SCCC->isNullValue()) 4444 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4445 N->getOperand(0), N->getOperand(4)); 4446 // fold br_cc false, dest -> unconditional fall through 4447 if (SCCC && SCCC->isNullValue()) 4448 return N->getOperand(0); 4449 4450 // fold to a simpler setcc 4451 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4452 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4453 N->getOperand(0), Simp.getOperand(2), 4454 Simp.getOperand(0), Simp.getOperand(1), 4455 N->getOperand(4)); 4456 4457 return SDValue(); 4458} 4459 4460/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4461/// pre-indexed load / store when the base pointer is an add or subtract 4462/// and it has other uses besides the load / store. After the 4463/// transformation, the new indexed load / store has effectively folded 4464/// the add / subtract in and all of its other uses are redirected to the 4465/// new load / store. 4466bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4467 if (!LegalOperations) 4468 return false; 4469 4470 bool isLoad = true; 4471 SDValue Ptr; 4472 MVT VT; 4473 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4474 if (LD->isIndexed()) 4475 return false; 4476 VT = LD->getMemoryVT(); 4477 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4478 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4479 return false; 4480 Ptr = LD->getBasePtr(); 4481 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4482 if (ST->isIndexed()) 4483 return false; 4484 VT = ST->getMemoryVT(); 4485 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4486 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4487 return false; 4488 Ptr = ST->getBasePtr(); 4489 isLoad = false; 4490 } else { 4491 return false; 4492 } 4493 4494 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4495 // out. There is no reason to make this a preinc/predec. 4496 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4497 Ptr.getNode()->hasOneUse()) 4498 return false; 4499 4500 // Ask the target to do addressing mode selection. 4501 SDValue BasePtr; 4502 SDValue Offset; 4503 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4504 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4505 return false; 4506 // Don't create a indexed load / store with zero offset. 4507 if (isa<ConstantSDNode>(Offset) && 4508 cast<ConstantSDNode>(Offset)->isNullValue()) 4509 return false; 4510 4511 // Try turning it into a pre-indexed load / store except when: 4512 // 1) The new base ptr is a frame index. 4513 // 2) If N is a store and the new base ptr is either the same as or is a 4514 // predecessor of the value being stored. 4515 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4516 // that would create a cycle. 4517 // 4) All uses are load / store ops that use it as old base ptr. 4518 4519 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4520 // (plus the implicit offset) to a register to preinc anyway. 4521 if (isa<FrameIndexSDNode>(BasePtr)) 4522 return false; 4523 4524 // Check #2. 4525 if (!isLoad) { 4526 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4527 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4528 return false; 4529 } 4530 4531 // Now check for #3 and #4. 4532 bool RealUse = false; 4533 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4534 E = Ptr.getNode()->use_end(); I != E; ++I) { 4535 SDNode *Use = *I; 4536 if (Use == N) 4537 continue; 4538 if (Use->isPredecessorOf(N)) 4539 return false; 4540 4541 if (!((Use->getOpcode() == ISD::LOAD && 4542 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4543 (Use->getOpcode() == ISD::STORE && 4544 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4545 RealUse = true; 4546 } 4547 4548 if (!RealUse) 4549 return false; 4550 4551 SDValue Result; 4552 if (isLoad) 4553 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4554 BasePtr, Offset, AM); 4555 else 4556 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4557 BasePtr, Offset, AM); 4558 ++PreIndexedNodes; 4559 ++NodesCombined; 4560 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4561 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4562 DOUT << '\n'; 4563 WorkListRemover DeadNodes(*this); 4564 if (isLoad) { 4565 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4566 &DeadNodes); 4567 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4568 &DeadNodes); 4569 } else { 4570 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4571 &DeadNodes); 4572 } 4573 4574 // Finally, since the node is now dead, remove it from the graph. 4575 DAG.DeleteNode(N); 4576 4577 // Replace the uses of Ptr with uses of the updated base value. 4578 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4579 &DeadNodes); 4580 removeFromWorkList(Ptr.getNode()); 4581 DAG.DeleteNode(Ptr.getNode()); 4582 4583 return true; 4584} 4585 4586/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4587/// add / sub of the base pointer node into a post-indexed load / store. 4588/// The transformation folded the add / subtract into the new indexed 4589/// load / store effectively and all of its uses are redirected to the 4590/// new load / store. 4591bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4592 if (!LegalOperations) 4593 return false; 4594 4595 bool isLoad = true; 4596 SDValue Ptr; 4597 MVT VT; 4598 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4599 if (LD->isIndexed()) 4600 return false; 4601 VT = LD->getMemoryVT(); 4602 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4603 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4604 return false; 4605 Ptr = LD->getBasePtr(); 4606 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4607 if (ST->isIndexed()) 4608 return false; 4609 VT = ST->getMemoryVT(); 4610 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4611 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4612 return false; 4613 Ptr = ST->getBasePtr(); 4614 isLoad = false; 4615 } else { 4616 return false; 4617 } 4618 4619 if (Ptr.getNode()->hasOneUse()) 4620 return false; 4621 4622 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4623 E = Ptr.getNode()->use_end(); I != E; ++I) { 4624 SDNode *Op = *I; 4625 if (Op == N || 4626 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4627 continue; 4628 4629 SDValue BasePtr; 4630 SDValue Offset; 4631 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4632 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4633 if (Ptr == Offset) 4634 std::swap(BasePtr, Offset); 4635 if (Ptr != BasePtr) 4636 continue; 4637 // Don't create a indexed load / store with zero offset. 4638 if (isa<ConstantSDNode>(Offset) && 4639 cast<ConstantSDNode>(Offset)->isNullValue()) 4640 continue; 4641 4642 // Try turning it into a post-indexed load / store except when 4643 // 1) All uses are load / store ops that use it as base ptr. 4644 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4645 // nor a successor of N. Otherwise, if Op is folded that would 4646 // create a cycle. 4647 4648 // Check for #1. 4649 bool TryNext = false; 4650 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4651 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4652 SDNode *Use = *II; 4653 if (Use == Ptr.getNode()) 4654 continue; 4655 4656 // If all the uses are load / store addresses, then don't do the 4657 // transformation. 4658 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4659 bool RealUse = false; 4660 for (SDNode::use_iterator III = Use->use_begin(), 4661 EEE = Use->use_end(); III != EEE; ++III) { 4662 SDNode *UseUse = *III; 4663 if (!((UseUse->getOpcode() == ISD::LOAD && 4664 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4665 (UseUse->getOpcode() == ISD::STORE && 4666 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4667 RealUse = true; 4668 } 4669 4670 if (!RealUse) { 4671 TryNext = true; 4672 break; 4673 } 4674 } 4675 } 4676 4677 if (TryNext) 4678 continue; 4679 4680 // Check for #2 4681 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4682 SDValue Result = isLoad 4683 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4684 BasePtr, Offset, AM) 4685 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4686 BasePtr, Offset, AM); 4687 ++PostIndexedNodes; 4688 ++NodesCombined; 4689 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4690 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4691 DOUT << '\n'; 4692 WorkListRemover DeadNodes(*this); 4693 if (isLoad) { 4694 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4695 &DeadNodes); 4696 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4697 &DeadNodes); 4698 } else { 4699 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4700 &DeadNodes); 4701 } 4702 4703 // Finally, since the node is now dead, remove it from the graph. 4704 DAG.DeleteNode(N); 4705 4706 // Replace the uses of Use with uses of the updated base value. 4707 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4708 Result.getValue(isLoad ? 1 : 0), 4709 &DeadNodes); 4710 removeFromWorkList(Op); 4711 DAG.DeleteNode(Op); 4712 return true; 4713 } 4714 } 4715 } 4716 4717 return false; 4718} 4719 4720/// InferAlignment - If we can infer some alignment information from this 4721/// pointer, return it. 4722static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4723 // If this is a direct reference to a stack slot, use information about the 4724 // stack slot's alignment. 4725 int FrameIdx = 1 << 31; 4726 int64_t FrameOffset = 0; 4727 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4728 FrameIdx = FI->getIndex(); 4729 } else if (Ptr.getOpcode() == ISD::ADD && 4730 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4731 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4732 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4733 FrameOffset = Ptr.getConstantOperandVal(1); 4734 } 4735 4736 if (FrameIdx != (1 << 31)) { 4737 // FIXME: Handle FI+CST. 4738 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4739 if (MFI.isFixedObjectIndex(FrameIdx)) { 4740 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4741 4742 // The alignment of the frame index can be determined from its offset from 4743 // the incoming frame position. If the frame object is at offset 32 and 4744 // the stack is guaranteed to be 16-byte aligned, then we know that the 4745 // object is 16-byte aligned. 4746 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4747 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4748 4749 // Finally, the frame object itself may have a known alignment. Factor 4750 // the alignment + offset into a new alignment. For example, if we know 4751 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4752 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4753 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4754 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4755 FrameOffset); 4756 return std::max(Align, FIInfoAlign); 4757 } 4758 } 4759 4760 return 0; 4761} 4762 4763SDValue DAGCombiner::visitLOAD(SDNode *N) { 4764 LoadSDNode *LD = cast<LoadSDNode>(N); 4765 SDValue Chain = LD->getChain(); 4766 SDValue Ptr = LD->getBasePtr(); 4767 4768 // Try to infer better alignment information than the load already has. 4769 if (!Fast && LD->isUnindexed()) { 4770 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4771 if (Align > LD->getAlignment()) 4772 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4773 LD->getValueType(0), 4774 Chain, Ptr, LD->getSrcValue(), 4775 LD->getSrcValueOffset(), LD->getMemoryVT(), 4776 LD->isVolatile(), Align); 4777 } 4778 } 4779 4780 // If load is not volatile and there are no uses of the loaded value (and 4781 // the updated indexed value in case of indexed loads), change uses of the 4782 // chain value into uses of the chain input (i.e. delete the dead load). 4783 if (!LD->isVolatile()) { 4784 if (N->getValueType(1) == MVT::Other) { 4785 // Unindexed loads. 4786 if (N->hasNUsesOfValue(0, 0)) { 4787 // It's not safe to use the two value CombineTo variant here. e.g. 4788 // v1, chain2 = load chain1, loc 4789 // v2, chain3 = load chain2, loc 4790 // v3 = add v2, c 4791 // Now we replace use of chain2 with chain1. This makes the second load 4792 // isomorphic to the one we are deleting, and thus makes this load live. 4793 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4794 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4795 DOUT << "\n"; 4796 WorkListRemover DeadNodes(*this); 4797 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4798 4799 if (N->use_empty()) { 4800 removeFromWorkList(N); 4801 DAG.DeleteNode(N); 4802 } 4803 4804 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4805 } 4806 } else { 4807 // Indexed loads. 4808 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4809 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4810 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getDebugLoc(), 4811 N->getValueType(0)); 4812 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4813 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4814 DOUT << " and 2 other values\n"; 4815 WorkListRemover DeadNodes(*this); 4816 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4817 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4818 DAG.getNode(ISD::UNDEF, N->getDebugLoc(), 4819 N->getValueType(1)), 4820 &DeadNodes); 4821 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4822 removeFromWorkList(N); 4823 DAG.DeleteNode(N); 4824 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4825 } 4826 } 4827 } 4828 4829 // If this load is directly stored, replace the load value with the stored 4830 // value. 4831 // TODO: Handle store large -> read small portion. 4832 // TODO: Handle TRUNCSTORE/LOADEXT 4833 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4834 !LD->isVolatile()) { 4835 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4836 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4837 if (PrevST->getBasePtr() == Ptr && 4838 PrevST->getValue().getValueType() == N->getValueType(0)) 4839 return CombineTo(N, Chain.getOperand(1), Chain); 4840 } 4841 } 4842 4843 if (CombinerAA) { 4844 // Walk up chain skipping non-aliasing memory nodes. 4845 SDValue BetterChain = FindBetterChain(N, Chain); 4846 4847 // If there is a better chain. 4848 if (Chain != BetterChain) { 4849 SDValue ReplLoad; 4850 4851 // Replace the chain to void dependency. 4852 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4853 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4854 BetterChain, Ptr, 4855 LD->getSrcValue(), LD->getSrcValueOffset(), 4856 LD->isVolatile(), LD->getAlignment()); 4857 } else { 4858 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4859 LD->getValueType(0), 4860 BetterChain, Ptr, LD->getSrcValue(), 4861 LD->getSrcValueOffset(), 4862 LD->getMemoryVT(), 4863 LD->isVolatile(), 4864 LD->getAlignment()); 4865 } 4866 4867 // Create token factor to keep old chain connected. 4868 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4869 MVT::Other, Chain, ReplLoad.getValue(1)); 4870 4871 // Replace uses with load result and token factor. Don't add users 4872 // to work list. 4873 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4874 } 4875 } 4876 4877 // Try transforming N to an indexed load. 4878 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4879 return SDValue(N, 0); 4880 4881 return SDValue(); 4882} 4883 4884SDValue DAGCombiner::visitSTORE(SDNode *N) { 4885 StoreSDNode *ST = cast<StoreSDNode>(N); 4886 SDValue Chain = ST->getChain(); 4887 SDValue Value = ST->getValue(); 4888 SDValue Ptr = ST->getBasePtr(); 4889 4890 // Try to infer better alignment information than the store already has. 4891 if (!Fast && ST->isUnindexed()) { 4892 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4893 if (Align > ST->getAlignment()) 4894 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 4895 Ptr, ST->getSrcValue(), 4896 ST->getSrcValueOffset(), ST->getMemoryVT(), 4897 ST->isVolatile(), Align); 4898 } 4899 } 4900 4901 // If this is a store of a bit convert, store the input value if the 4902 // resultant store does not need a higher alignment than the original. 4903 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4904 ST->isUnindexed()) { 4905 unsigned Align = ST->getAlignment(); 4906 MVT SVT = Value.getOperand(0).getValueType(); 4907 unsigned OrigAlign = TLI.getTargetData()-> 4908 getABITypeAlignment(SVT.getTypeForMVT()); 4909 if (Align <= OrigAlign && 4910 ((!LegalOperations && !ST->isVolatile()) || 4911 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 4912 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 4913 Ptr, ST->getSrcValue(), 4914 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4915 } 4916 4917 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4918 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4919 // NOTE: If the original store is volatile, this transform must not increase 4920 // the number of stores. For example, on x86-32 an f64 can be stored in one 4921 // processor operation but an i64 (which is not legal) requires two. So the 4922 // transform should not be done in this case. 4923 if (Value.getOpcode() != ISD::TargetConstantFP) { 4924 SDValue Tmp; 4925 switch (CFP->getValueType(0).getSimpleVT()) { 4926 default: assert(0 && "Unknown FP type"); 4927 case MVT::f80: // We don't do this for these yet. 4928 case MVT::f128: 4929 case MVT::ppcf128: 4930 break; 4931 case MVT::f32: 4932 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 4933 !ST->isVolatile()) || 4934 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4935 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4936 bitcastToAPInt().getZExtValue(), MVT::i32); 4937 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 4938 Ptr, ST->getSrcValue(), 4939 ST->getSrcValueOffset(), ST->isVolatile(), 4940 ST->getAlignment()); 4941 } 4942 break; 4943 case MVT::f64: 4944 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 4945 !ST->isVolatile()) || 4946 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 4947 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4948 getZExtValue(), MVT::i64); 4949 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 4950 Ptr, ST->getSrcValue(), 4951 ST->getSrcValueOffset(), ST->isVolatile(), 4952 ST->getAlignment()); 4953 } else if (!ST->isVolatile() && 4954 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4955 // Many FP stores are not made apparent until after legalize, e.g. for 4956 // argument passing. Since this is so common, custom legalize the 4957 // 64-bit integer store into two 32-bit stores. 4958 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4959 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4960 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4961 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4962 4963 int SVOffset = ST->getSrcValueOffset(); 4964 unsigned Alignment = ST->getAlignment(); 4965 bool isVolatile = ST->isVolatile(); 4966 4967 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 4968 Ptr, ST->getSrcValue(), 4969 ST->getSrcValueOffset(), 4970 isVolatile, ST->getAlignment()); 4971 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 4972 DAG.getConstant(4, Ptr.getValueType())); 4973 SVOffset += 4; 4974 Alignment = MinAlign(Alignment, 4U); 4975 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 4976 Ptr, ST->getSrcValue(), 4977 SVOffset, isVolatile, Alignment); 4978 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 4979 St0, St1); 4980 } 4981 4982 break; 4983 } 4984 } 4985 } 4986 4987 if (CombinerAA) { 4988 // Walk up chain skipping non-aliasing memory nodes. 4989 SDValue BetterChain = FindBetterChain(N, Chain); 4990 4991 // If there is a better chain. 4992 if (Chain != BetterChain) { 4993 // Replace the chain to avoid dependency. 4994 SDValue ReplStore; 4995 if (ST->isTruncatingStore()) { 4996 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 4997 ST->getSrcValue(),ST->getSrcValueOffset(), 4998 ST->getMemoryVT(), 4999 ST->isVolatile(), ST->getAlignment()); 5000 } else { 5001 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5002 ST->getSrcValue(), ST->getSrcValueOffset(), 5003 ST->isVolatile(), ST->getAlignment()); 5004 } 5005 5006 // Create token to keep both nodes around. 5007 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5008 MVT::Other, Chain, ReplStore); 5009 5010 // Don't add users to work list. 5011 return CombineTo(N, Token, false); 5012 } 5013 } 5014 5015 // Try transforming N to an indexed store. 5016 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5017 return SDValue(N, 0); 5018 5019 // FIXME: is there such a thing as a truncating indexed store? 5020 if (ST->isTruncatingStore() && ST->isUnindexed() && 5021 Value.getValueType().isInteger()) { 5022 // See if we can simplify the input to this truncstore with knowledge that 5023 // only the low bits are being used. For example: 5024 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5025 SDValue Shorter = 5026 GetDemandedBits(Value, 5027 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5028 ST->getMemoryVT().getSizeInBits())); 5029 AddToWorkList(Value.getNode()); 5030 if (Shorter.getNode()) 5031 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5032 Ptr, ST->getSrcValue(), 5033 ST->getSrcValueOffset(), ST->getMemoryVT(), 5034 ST->isVolatile(), ST->getAlignment()); 5035 5036 // Otherwise, see if we can simplify the operation with 5037 // SimplifyDemandedBits, which only works if the value has a single use. 5038 if (SimplifyDemandedBits(Value, 5039 APInt::getLowBitsSet( 5040 Value.getValueSizeInBits(), 5041 ST->getMemoryVT().getSizeInBits()))) 5042 return SDValue(N, 0); 5043 } 5044 5045 // If this is a load followed by a store to the same location, then the store 5046 // is dead/noop. 5047 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5048 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5049 ST->isUnindexed() && !ST->isVolatile() && 5050 // There can't be any side effects between the load and store, such as 5051 // a call or store. 5052 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5053 // The store is dead, remove it. 5054 return Chain; 5055 } 5056 } 5057 5058 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5059 // truncating store. We can do this even if this is already a truncstore. 5060 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5061 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5062 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5063 ST->getMemoryVT())) { 5064 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5065 Ptr, ST->getSrcValue(), 5066 ST->getSrcValueOffset(), ST->getMemoryVT(), 5067 ST->isVolatile(), ST->getAlignment()); 5068 } 5069 5070 return SDValue(); 5071} 5072 5073SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5074 SDValue InVec = N->getOperand(0); 5075 SDValue InVal = N->getOperand(1); 5076 SDValue EltNo = N->getOperand(2); 5077 5078 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5079 // vector with the inserted element. 5080 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5081 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5082 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5083 InVec.getNode()->op_end()); 5084 if (Elt < Ops.size()) 5085 Ops[Elt] = InVal; 5086 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5087 InVec.getValueType(), &Ops[0], Ops.size()); 5088 } 5089 5090 return SDValue(); 5091} 5092 5093SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5094 // (vextract (scalar_to_vector val, 0) -> val 5095 SDValue InVec = N->getOperand(0); 5096 5097 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) 5098 return InVec.getOperand(0); 5099 5100 // Perform only after legalization to ensure build_vector / vector_shuffle 5101 // optimizations have already been done. 5102 if (!LegalOperations) return SDValue(); 5103 5104 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5105 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5106 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5107 SDValue EltNo = N->getOperand(1); 5108 5109 if (isa<ConstantSDNode>(EltNo)) { 5110 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5111 bool NewLoad = false; 5112 bool BCNumEltsChanged = false; 5113 MVT VT = InVec.getValueType(); 5114 MVT EVT = VT.getVectorElementType(); 5115 MVT LVT = EVT; 5116 5117 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5118 MVT BCVT = InVec.getOperand(0).getValueType(); 5119 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5120 return SDValue(); 5121 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5122 BCNumEltsChanged = true; 5123 InVec = InVec.getOperand(0); 5124 EVT = BCVT.getVectorElementType(); 5125 NewLoad = true; 5126 } 5127 5128 LoadSDNode *LN0 = NULL; 5129 if (ISD::isNormalLoad(InVec.getNode())) { 5130 LN0 = cast<LoadSDNode>(InVec); 5131 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5132 InVec.getOperand(0).getValueType() == EVT && 5133 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5134 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5135 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 5136 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5137 // => 5138 // (load $addr+1*size) 5139 5140 // If the bit convert changed the number of elements, it is unsafe 5141 // to examine the mask. 5142 if (BCNumEltsChanged) 5143 return SDValue(); 5144 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 5145 getOperand(Elt))->getZExtValue(); 5146 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 5147 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5148 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5149 InVec = InVec.getOperand(0); 5150 if (ISD::isNormalLoad(InVec.getNode())) { 5151 LN0 = cast<LoadSDNode>(InVec); 5152 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 5153 } 5154 } 5155 5156 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5157 return SDValue(); 5158 5159 unsigned Align = LN0->getAlignment(); 5160 if (NewLoad) { 5161 // Check the resultant load doesn't need a higher alignment than the 5162 // original load. 5163 unsigned NewAlign = 5164 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); 5165 5166 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5167 return SDValue(); 5168 5169 Align = NewAlign; 5170 } 5171 5172 SDValue NewPtr = LN0->getBasePtr(); 5173 if (Elt) { 5174 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5175 MVT PtrType = NewPtr.getValueType(); 5176 if (TLI.isBigEndian()) 5177 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5178 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5179 DAG.getConstant(PtrOff, PtrType)); 5180 } 5181 5182 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5183 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5184 LN0->isVolatile(), Align); 5185 } 5186 5187 return SDValue(); 5188} 5189 5190SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5191 unsigned NumInScalars = N->getNumOperands(); 5192 MVT VT = N->getValueType(0); 5193 unsigned NumElts = VT.getVectorNumElements(); 5194 MVT EltType = VT.getVectorElementType(); 5195 5196 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5197 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5198 // at most two distinct vectors, turn this into a shuffle node. 5199 SDValue VecIn1, VecIn2; 5200 for (unsigned i = 0; i != NumInScalars; ++i) { 5201 // Ignore undef inputs. 5202 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5203 5204 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5205 // constant index, bail out. 5206 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5207 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5208 VecIn1 = VecIn2 = SDValue(0, 0); 5209 break; 5210 } 5211 5212 // If the input vector type disagrees with the result of the build_vector, 5213 // we can't make a shuffle. 5214 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5215 if (ExtractedFromVec.getValueType() != VT) { 5216 VecIn1 = VecIn2 = SDValue(0, 0); 5217 break; 5218 } 5219 5220 // Otherwise, remember this. We allow up to two distinct input vectors. 5221 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5222 continue; 5223 5224 if (VecIn1.getNode() == 0) { 5225 VecIn1 = ExtractedFromVec; 5226 } else if (VecIn2.getNode() == 0) { 5227 VecIn2 = ExtractedFromVec; 5228 } else { 5229 // Too many inputs. 5230 VecIn1 = VecIn2 = SDValue(0, 0); 5231 break; 5232 } 5233 } 5234 5235 // If everything is good, we can make a shuffle operation. 5236 if (VecIn1.getNode()) { 5237 SmallVector<SDValue, 8> BuildVecIndices; 5238 for (unsigned i = 0; i != NumInScalars; ++i) { 5239 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5240 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, 5241 N->getDebugLoc(), 5242 TLI.getPointerTy())); 5243 continue; 5244 } 5245 5246 SDValue Extract = N->getOperand(i); 5247 5248 // If extracting from the first vector, just use the index directly. 5249 if (Extract.getOperand(0) == VecIn1) { 5250 BuildVecIndices.push_back(Extract.getOperand(1)); 5251 continue; 5252 } 5253 5254 // Otherwise, use InIdx + VecSize 5255 unsigned Idx = 5256 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 5257 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 5258 } 5259 5260 // Add count and size info. 5261 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5262 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes) 5263 return SDValue(); 5264 5265 // Return the new VECTOR_SHUFFLE node. 5266 SDValue Ops[5]; 5267 Ops[0] = VecIn1; 5268 if (VecIn2.getNode()) { 5269 Ops[1] = VecIn2; 5270 } else { 5271 // Use an undef build_vector as input for the second operand. 5272 std::vector<SDValue> UnOps(NumInScalars, 5273 DAG.getNode(ISD::UNDEF, N->getDebugLoc(), 5274 EltType)); 5275 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5276 &UnOps[0], UnOps.size()); 5277 AddToWorkList(Ops[1].getNode()); 5278 } 5279 5280 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), BuildVecVT, 5281 &BuildVecIndices[0], BuildVecIndices.size()); 5282 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3); 5283 } 5284 5285 return SDValue(); 5286} 5287 5288SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5289 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5290 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5291 // inputs come from at most two distinct vectors, turn this into a shuffle 5292 // node. 5293 5294 // If we only have one input vector, we don't need to do any concatenation. 5295 if (N->getNumOperands() == 1) 5296 return N->getOperand(0); 5297 5298 return SDValue(); 5299} 5300 5301SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5302 SDValue ShufMask = N->getOperand(2); 5303 unsigned NumElts = ShufMask.getNumOperands(); 5304 5305 SDValue N0 = N->getOperand(0); 5306 SDValue N1 = N->getOperand(1); 5307 5308 assert(N0.getValueType().getVectorNumElements() == NumElts && 5309 "Vector shuffle must be normalized in DAG"); 5310 5311 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5312 bool isIdentity = true; 5313 for (unsigned i = 0; i != NumElts; ++i) { 5314 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5315 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5316 isIdentity = false; 5317 break; 5318 } 5319 } 5320 if (isIdentity) return N->getOperand(0); 5321 5322 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5323 isIdentity = true; 5324 for (unsigned i = 0; i != NumElts; ++i) { 5325 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5326 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5327 i+NumElts) { 5328 isIdentity = false; 5329 break; 5330 } 5331 } 5332 if (isIdentity) return N->getOperand(1); 5333 5334 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5335 // needed at all. 5336 bool isUnary = true; 5337 bool isSplat = true; 5338 int VecNum = -1; 5339 unsigned BaseIdx = 0; 5340 for (unsigned i = 0; i != NumElts; ++i) 5341 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5342 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5343 int V = (Idx < NumElts) ? 0 : 1; 5344 if (VecNum == -1) { 5345 VecNum = V; 5346 BaseIdx = Idx; 5347 } else { 5348 if (BaseIdx != Idx) 5349 isSplat = false; 5350 if (VecNum != V) { 5351 isUnary = false; 5352 break; 5353 } 5354 } 5355 } 5356 5357 // Normalize unary shuffle so the RHS is undef. 5358 if (isUnary && VecNum == 1) 5359 std::swap(N0, N1); 5360 5361 // If it is a splat, check if the argument vector is a build_vector with 5362 // all scalar elements the same. 5363 if (isSplat) { 5364 SDNode *V = N0.getNode(); 5365 5366 // If this is a bit convert that changes the element type of the vector but 5367 // not the number of vector elements, look through it. Be careful not to 5368 // look though conversions that change things like v4f32 to v2f64. 5369 if (V->getOpcode() == ISD::BIT_CONVERT) { 5370 SDValue ConvInput = V->getOperand(0); 5371 if (ConvInput.getValueType().isVector() && 5372 ConvInput.getValueType().getVectorNumElements() == NumElts) 5373 V = ConvInput.getNode(); 5374 } 5375 5376 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5377 unsigned NumElems = V->getNumOperands(); 5378 if (NumElems > BaseIdx) { 5379 SDValue Base; 5380 bool AllSame = true; 5381 for (unsigned i = 0; i != NumElems; ++i) { 5382 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5383 Base = V->getOperand(i); 5384 break; 5385 } 5386 } 5387 // Splat of <u, u, u, u>, return <u, u, u, u> 5388 if (!Base.getNode()) 5389 return N0; 5390 for (unsigned i = 0; i != NumElems; ++i) { 5391 if (V->getOperand(i) != Base) { 5392 AllSame = false; 5393 break; 5394 } 5395 } 5396 // Splat of <x, x, x, x>, return <x, x, x, x> 5397 if (AllSame) 5398 return N0; 5399 } 5400 } 5401 } 5402 5403 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5404 // into an undef. 5405 if (isUnary || N0 == N1) { 5406 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5407 // first operand. 5408 SmallVector<SDValue, 8> MappedOps; 5409 5410 for (unsigned i = 0; i != NumElts; ++i) { 5411 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5412 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5413 NumElts) { 5414 MappedOps.push_back(ShufMask.getOperand(i)); 5415 } else { 5416 unsigned NewIdx = 5417 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5418 NumElts; 5419 MappedOps.push_back(DAG.getConstant(NewIdx, 5420 ShufMask.getOperand(i).getValueType())); 5421 } 5422 } 5423 5424 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5425 ShufMask.getValueType(), 5426 &MappedOps[0], MappedOps.size()); 5427 AddToWorkList(ShufMask.getNode()); 5428 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), 5429 N->getValueType(0), N0, 5430 DAG.getNode(ISD::UNDEF, N->getDebugLoc(), 5431 N->getValueType(0)), 5432 ShufMask); 5433 } 5434 5435 return SDValue(); 5436} 5437 5438/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5439/// an AND to a vector_shuffle with the destination vector and a zero vector. 5440/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5441/// vector_shuffle V, Zero, <0, 4, 2, 4> 5442SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5443 SDValue LHS = N->getOperand(0); 5444 SDValue RHS = N->getOperand(1); 5445 if (N->getOpcode() == ISD::AND) { 5446 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5447 RHS = RHS.getOperand(0); 5448 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5449 std::vector<SDValue> IdxOps; 5450 unsigned NumOps = RHS.getNumOperands(); 5451 unsigned NumElts = NumOps; 5452 for (unsigned i = 0; i != NumElts; ++i) { 5453 SDValue Elt = RHS.getOperand(i); 5454 if (!isa<ConstantSDNode>(Elt)) 5455 return SDValue(); 5456 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5457 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5458 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5459 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5460 else 5461 return SDValue(); 5462 } 5463 5464 // Let's see if the target supports this vector_shuffle. 5465 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5466 return SDValue(); 5467 5468 // Return the new VECTOR_SHUFFLE node. 5469 MVT EVT = RHS.getValueType().getVectorElementType(); 5470 MVT VT = MVT::getVectorVT(EVT, NumElts); 5471 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5472 std::vector<SDValue> Ops; 5473 LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS); 5474 Ops.push_back(LHS); 5475 AddToWorkList(LHS.getNode()); 5476 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5477 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5478 VT, &ZeroOps[0], ZeroOps.size())); 5479 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5480 MaskVT, &IdxOps[0], IdxOps.size())); 5481 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), 5482 VT, &Ops[0], Ops.size()); 5483 5484 if (VT != N->getValueType(0)) 5485 Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5486 N->getValueType(0), Result); 5487 5488 return Result; 5489 } 5490 } 5491 5492 return SDValue(); 5493} 5494 5495/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5496SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5497 // After legalize, the target may be depending on adds and other 5498 // binary ops to provide legal ways to construct constants or other 5499 // things. Simplifying them may result in a loss of legality. 5500 if (LegalOperations) return SDValue(); 5501 5502 MVT VT = N->getValueType(0); 5503 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5504 5505 MVT EltType = VT.getVectorElementType(); 5506 SDValue LHS = N->getOperand(0); 5507 SDValue RHS = N->getOperand(1); 5508 SDValue Shuffle = XformToShuffleWithZero(N); 5509 if (Shuffle.getNode()) return Shuffle; 5510 5511 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5512 // this operation. 5513 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5514 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5515 SmallVector<SDValue, 8> Ops; 5516 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5517 SDValue LHSOp = LHS.getOperand(i); 5518 SDValue RHSOp = RHS.getOperand(i); 5519 // If these two elements can't be folded, bail out. 5520 if ((LHSOp.getOpcode() != ISD::UNDEF && 5521 LHSOp.getOpcode() != ISD::Constant && 5522 LHSOp.getOpcode() != ISD::ConstantFP) || 5523 (RHSOp.getOpcode() != ISD::UNDEF && 5524 RHSOp.getOpcode() != ISD::Constant && 5525 RHSOp.getOpcode() != ISD::ConstantFP)) 5526 break; 5527 5528 // Can't fold divide by zero. 5529 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5530 N->getOpcode() == ISD::FDIV) { 5531 if ((RHSOp.getOpcode() == ISD::Constant && 5532 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5533 (RHSOp.getOpcode() == ISD::ConstantFP && 5534 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5535 break; 5536 } 5537 5538 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5539 EltType, LHSOp, RHSOp)); 5540 AddToWorkList(Ops.back().getNode()); 5541 assert((Ops.back().getOpcode() == ISD::UNDEF || 5542 Ops.back().getOpcode() == ISD::Constant || 5543 Ops.back().getOpcode() == ISD::ConstantFP) && 5544 "Scalar binop didn't fold!"); 5545 } 5546 5547 if (Ops.size() == LHS.getNumOperands()) { 5548 MVT VT = LHS.getValueType(); 5549 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5550 &Ops[0], Ops.size()); 5551 } 5552 } 5553 5554 return SDValue(); 5555} 5556 5557SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5558 SDValue N1, SDValue N2){ 5559 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5560 5561 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5562 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5563 5564 // If we got a simplified select_cc node back from SimplifySelectCC, then 5565 // break it down into a new SETCC node, and a new SELECT node, and then return 5566 // the SELECT node, since we were called with a SELECT node. 5567 if (SCC.getNode()) { 5568 // Check to see if we got a select_cc back (to turn into setcc/select). 5569 // Otherwise, just return whatever node we got back, like fabs. 5570 if (SCC.getOpcode() == ISD::SELECT_CC) { 5571 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5572 N0.getValueType(), 5573 SCC.getOperand(0), SCC.getOperand(1), 5574 SCC.getOperand(4)); 5575 AddToWorkList(SETCC.getNode()); 5576 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5577 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5578 } 5579 5580 return SCC; 5581 } 5582 return SDValue(); 5583} 5584 5585/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5586/// are the two values being selected between, see if we can simplify the 5587/// select. Callers of this should assume that TheSelect is deleted if this 5588/// returns true. As such, they should return the appropriate thing (e.g. the 5589/// node) back to the top-level of the DAG combiner loop to avoid it being 5590/// looked at. 5591bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5592 SDValue RHS) { 5593 5594 // If this is a select from two identical things, try to pull the operation 5595 // through the select. 5596 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5597 // If this is a load and the token chain is identical, replace the select 5598 // of two loads with a load through a select of the address to load from. 5599 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5600 // constants have been dropped into the constant pool. 5601 if (LHS.getOpcode() == ISD::LOAD && 5602 // Do not let this transformation reduce the number of volatile loads. 5603 !cast<LoadSDNode>(LHS)->isVolatile() && 5604 !cast<LoadSDNode>(RHS)->isVolatile() && 5605 // Token chains must be identical. 5606 LHS.getOperand(0) == RHS.getOperand(0)) { 5607 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5608 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5609 5610 // If this is an EXTLOAD, the VT's must match. 5611 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5612 // FIXME: this conflates two src values, discarding one. This is not 5613 // the right thing to do, but nothing uses srcvalues now. When they do, 5614 // turn SrcValue into a list of locations. 5615 SDValue Addr; 5616 if (TheSelect->getOpcode() == ISD::SELECT) { 5617 // Check that the condition doesn't reach either load. If so, folding 5618 // this will induce a cycle into the DAG. 5619 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5620 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5621 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5622 LLD->getBasePtr().getValueType(), 5623 TheSelect->getOperand(0), LLD->getBasePtr(), 5624 RLD->getBasePtr()); 5625 } 5626 } else { 5627 // Check that the condition doesn't reach either load. If so, folding 5628 // this will induce a cycle into the DAG. 5629 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5630 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5631 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5632 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5633 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5634 LLD->getBasePtr().getValueType(), 5635 TheSelect->getOperand(0), 5636 TheSelect->getOperand(1), 5637 LLD->getBasePtr(), RLD->getBasePtr(), 5638 TheSelect->getOperand(4)); 5639 } 5640 } 5641 5642 if (Addr.getNode()) { 5643 SDValue Load; 5644 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5645 Load = DAG.getLoad(TheSelect->getValueType(0), 5646 TheSelect->getDebugLoc(), 5647 LLD->getChain(), 5648 Addr,LLD->getSrcValue(), 5649 LLD->getSrcValueOffset(), 5650 LLD->isVolatile(), 5651 LLD->getAlignment()); 5652 } else { 5653 Load = DAG.getExtLoad(LLD->getExtensionType(), 5654 TheSelect->getDebugLoc(), 5655 TheSelect->getValueType(0), 5656 LLD->getChain(), Addr, LLD->getSrcValue(), 5657 LLD->getSrcValueOffset(), 5658 LLD->getMemoryVT(), 5659 LLD->isVolatile(), 5660 LLD->getAlignment()); 5661 } 5662 5663 // Users of the select now use the result of the load. 5664 CombineTo(TheSelect, Load); 5665 5666 // Users of the old loads now use the new load's chain. We know the 5667 // old-load value is dead now. 5668 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5669 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5670 return true; 5671 } 5672 } 5673 } 5674 } 5675 5676 return false; 5677} 5678 5679SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5680 SDValue N2, SDValue N3, 5681 ISD::CondCode CC, bool NotExtCompare) { 5682 MVT VT = N2.getValueType(); 5683 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5684 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5685 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5686 5687 // Determine if the condition we're dealing with is constant 5688 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5689 N0, N1, CC, false); 5690 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5691 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5692 5693 // fold select_cc true, x, y -> x 5694 if (SCCC && !SCCC->isNullValue()) 5695 return N2; 5696 // fold select_cc false, x, y -> y 5697 if (SCCC && SCCC->isNullValue()) 5698 return N3; 5699 5700 // Check to see if we can simplify the select into an fabs node 5701 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5702 // Allow either -0.0 or 0.0 5703 if (CFP->getValueAPF().isZero()) { 5704 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5705 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5706 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5707 N2 == N3.getOperand(0)) 5708 return DAG.getNode(ISD::FABS, DL, VT, N0); 5709 5710 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5711 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5712 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5713 N2.getOperand(0) == N3) 5714 return DAG.getNode(ISD::FABS, DL, VT, N3); 5715 } 5716 } 5717 5718 // Check to see if we can perform the "gzip trick", transforming 5719 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5720 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5721 N0.getValueType().isInteger() && 5722 N2.getValueType().isInteger() && 5723 (N1C->isNullValue() || // (a < 0) ? b : 0 5724 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5725 MVT XType = N0.getValueType(); 5726 MVT AType = N2.getValueType(); 5727 if (XType.bitsGE(AType)) { 5728 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5729 // single-bit constant. 5730 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5731 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5732 ShCtV = XType.getSizeInBits()-ShCtV-1; 5733 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5734 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5735 XType, N0, ShCt); 5736 AddToWorkList(Shift.getNode()); 5737 5738 if (XType.bitsGT(AType)) { 5739 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5740 AddToWorkList(Shift.getNode()); 5741 } 5742 5743 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5744 } 5745 5746 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5747 XType, N0, 5748 DAG.getConstant(XType.getSizeInBits()-1, 5749 getShiftAmountTy())); 5750 AddToWorkList(Shift.getNode()); 5751 5752 if (XType.bitsGT(AType)) { 5753 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5754 AddToWorkList(Shift.getNode()); 5755 } 5756 5757 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5758 } 5759 } 5760 5761 // fold select C, 16, 0 -> shl C, 4 5762 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5763 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5764 5765 // If the caller doesn't want us to simplify this into a zext of a compare, 5766 // don't do it. 5767 if (NotExtCompare && N2C->getAPIntValue() == 1) 5768 return SDValue(); 5769 5770 // Get a SetCC of the condition 5771 // FIXME: Should probably make sure that setcc is legal if we ever have a 5772 // target where it isn't. 5773 SDValue Temp, SCC; 5774 // cast from setcc result type to select result type 5775 if (LegalTypes) { 5776 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5777 N0, N1, CC); 5778 if (N2.getValueType().bitsLT(SCC.getValueType())) 5779 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5780 else 5781 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5782 N2.getValueType(), SCC); 5783 } else { 5784 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5785 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5786 N2.getValueType(), SCC); 5787 } 5788 5789 AddToWorkList(SCC.getNode()); 5790 AddToWorkList(Temp.getNode()); 5791 5792 if (N2C->getAPIntValue() == 1) 5793 return Temp; 5794 5795 // shl setcc result by log2 n2c 5796 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5797 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5798 getShiftAmountTy())); 5799 } 5800 5801 // Check to see if this is the equivalent of setcc 5802 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5803 // otherwise, go ahead with the folds. 5804 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5805 MVT XType = N0.getValueType(); 5806 if (!LegalOperations || 5807 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5808 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5809 if (Res.getValueType() != VT) 5810 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5811 return Res; 5812 } 5813 5814 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5815 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5816 (!LegalOperations || 5817 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5818 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5819 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5820 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5821 getShiftAmountTy())); 5822 } 5823 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5824 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5825 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5826 XType, DAG.getConstant(0, XType), N0); 5827 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5828 return DAG.getNode(ISD::SRL, DL, XType, 5829 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5830 DAG.getConstant(XType.getSizeInBits()-1, 5831 getShiftAmountTy())); 5832 } 5833 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5834 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5835 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5836 DAG.getConstant(XType.getSizeInBits()-1, 5837 getShiftAmountTy())); 5838 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5839 } 5840 } 5841 5842 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5843 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5844 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5845 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5846 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5847 MVT XType = N0.getValueType(); 5848 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5849 DAG.getConstant(XType.getSizeInBits()-1, 5850 getShiftAmountTy())); 5851 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5852 N0, Shift); 5853 AddToWorkList(Shift.getNode()); 5854 AddToWorkList(Add.getNode()); 5855 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5856 } 5857 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5858 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5859 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5860 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5861 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5862 MVT XType = N0.getValueType(); 5863 if (SubC->isNullValue() && XType.isInteger()) { 5864 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5865 N0, 5866 DAG.getConstant(XType.getSizeInBits()-1, 5867 getShiftAmountTy())); 5868 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 5869 XType, N0, Shift); 5870 AddToWorkList(Shift.getNode()); 5871 AddToWorkList(Add.getNode()); 5872 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5873 } 5874 } 5875 } 5876 5877 return SDValue(); 5878} 5879 5880/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5881SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5882 SDValue N1, ISD::CondCode Cond, 5883 bool foldBooleans) { 5884 TargetLowering::DAGCombinerInfo 5885 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5886 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5887} 5888 5889/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5890/// return a DAG expression to select that will generate the same value by 5891/// multiplying by a magic number. See: 5892/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5893SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5894 std::vector<SDNode*> Built; 5895 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5896 5897 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5898 ii != ee; ++ii) 5899 AddToWorkList(*ii); 5900 return S; 5901} 5902 5903/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5904/// return a DAG expression to select that will generate the same value by 5905/// multiplying by a magic number. See: 5906/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5907SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5908 std::vector<SDNode*> Built; 5909 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5910 5911 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5912 ii != ee; ++ii) 5913 AddToWorkList(*ii); 5914 return S; 5915} 5916 5917/// FindBaseOffset - Return true if base is known not to alias with anything 5918/// but itself. Provides base object and offset as results. 5919static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5920 // Assume it is a primitive operation. 5921 Base = Ptr; Offset = 0; 5922 5923 // If it's an adding a simple constant then integrate the offset. 5924 if (Base.getOpcode() == ISD::ADD) { 5925 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5926 Base = Base.getOperand(0); 5927 Offset += C->getZExtValue(); 5928 } 5929 } 5930 5931 // If it's any of the following then it can't alias with anything but itself. 5932 return isa<FrameIndexSDNode>(Base) || 5933 isa<ConstantPoolSDNode>(Base) || 5934 isa<GlobalAddressSDNode>(Base); 5935} 5936 5937/// isAlias - Return true if there is any possibility that the two addresses 5938/// overlap. 5939bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5940 const Value *SrcValue1, int SrcValueOffset1, 5941 SDValue Ptr2, int64_t Size2, 5942 const Value *SrcValue2, int SrcValueOffset2) const { 5943 // If they are the same then they must be aliases. 5944 if (Ptr1 == Ptr2) return true; 5945 5946 // Gather base node and offset information. 5947 SDValue Base1, Base2; 5948 int64_t Offset1, Offset2; 5949 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5950 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5951 5952 // If they have a same base address then... 5953 if (Base1 == Base2) 5954 // Check to see if the addresses overlap. 5955 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5956 5957 // If we know both bases then they can't alias. 5958 if (KnownBase1 && KnownBase2) return false; 5959 5960 if (CombinerGlobalAA) { 5961 // Use alias analysis information. 5962 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5963 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5964 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5965 AliasAnalysis::AliasResult AAResult = 5966 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5967 if (AAResult == AliasAnalysis::NoAlias) 5968 return false; 5969 } 5970 5971 // Otherwise we have to assume they alias. 5972 return true; 5973} 5974 5975/// FindAliasInfo - Extracts the relevant alias information from the memory 5976/// node. Returns true if the operand was a load. 5977bool DAGCombiner::FindAliasInfo(SDNode *N, 5978 SDValue &Ptr, int64_t &Size, 5979 const Value *&SrcValue, int &SrcValueOffset) const { 5980 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5981 Ptr = LD->getBasePtr(); 5982 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5983 SrcValue = LD->getSrcValue(); 5984 SrcValueOffset = LD->getSrcValueOffset(); 5985 return true; 5986 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5987 Ptr = ST->getBasePtr(); 5988 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5989 SrcValue = ST->getSrcValue(); 5990 SrcValueOffset = ST->getSrcValueOffset(); 5991 } else { 5992 assert(0 && "FindAliasInfo expected a memory operand"); 5993 } 5994 5995 return false; 5996} 5997 5998/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5999/// looking for aliasing nodes and adding them to the Aliases vector. 6000void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6001 SmallVector<SDValue, 8> &Aliases) { 6002 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6003 std::set<SDNode *> Visited; // Visited node set. 6004 6005 // Get alias information for node. 6006 SDValue Ptr; 6007 int64_t Size; 6008 const Value *SrcValue; 6009 int SrcValueOffset; 6010 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6011 6012 // Starting off. 6013 Chains.push_back(OriginalChain); 6014 6015 // Look at each chain and determine if it is an alias. If so, add it to the 6016 // aliases list. If not, then continue up the chain looking for the next 6017 // candidate. 6018 while (!Chains.empty()) { 6019 SDValue Chain = Chains.back(); 6020 Chains.pop_back(); 6021 6022 // Don't bother if we've been before. 6023 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6024 Visited.insert(Chain.getNode()); 6025 6026 switch (Chain.getOpcode()) { 6027 case ISD::EntryToken: 6028 // Entry token is ideal chain operand, but handled in FindBetterChain. 6029 break; 6030 6031 case ISD::LOAD: 6032 case ISD::STORE: { 6033 // Get alias information for Chain. 6034 SDValue OpPtr; 6035 int64_t OpSize; 6036 const Value *OpSrcValue; 6037 int OpSrcValueOffset; 6038 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6039 OpSrcValue, OpSrcValueOffset); 6040 6041 // If chain is alias then stop here. 6042 if (!(IsLoad && IsOpLoad) && 6043 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6044 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6045 Aliases.push_back(Chain); 6046 } else { 6047 // Look further up the chain. 6048 Chains.push_back(Chain.getOperand(0)); 6049 // Clean up old chain. 6050 AddToWorkList(Chain.getNode()); 6051 } 6052 break; 6053 } 6054 6055 case ISD::TokenFactor: 6056 // We have to check each of the operands of the token factor, so we queue 6057 // then up. Adding the operands to the queue (stack) in reverse order 6058 // maintains the original order and increases the likelihood that getNode 6059 // will find a matching token factor (CSE.) 6060 for (unsigned n = Chain.getNumOperands(); n;) 6061 Chains.push_back(Chain.getOperand(--n)); 6062 // Eliminate the token factor if we can. 6063 AddToWorkList(Chain.getNode()); 6064 break; 6065 6066 default: 6067 // For all other instructions we will just have to take what we can get. 6068 Aliases.push_back(Chain); 6069 break; 6070 } 6071 } 6072} 6073 6074/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6075/// for a better chain (aliasing node.) 6076SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6077 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6078 6079 // Accumulate all the aliases to this node. 6080 GatherAllAliases(N, OldChain, Aliases); 6081 6082 if (Aliases.size() == 0) { 6083 // If no operands then chain to entry token. 6084 return DAG.getEntryNode(); 6085 } else if (Aliases.size() == 1) { 6086 // If a single operand then chain to it. We don't need to revisit it. 6087 return Aliases[0]; 6088 } 6089 6090 // Construct a custom tailored token factor. 6091 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6092 &Aliases[0], Aliases.size()); 6093 6094 // Make sure the old chain gets cleaned up. 6095 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6096 6097 return NewChain; 6098} 6099 6100// SelectionDAG::Combine - This is the entry point for the file. 6101// 6102void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { 6103 /// run - This is the main entry point to this class. 6104 /// 6105 DAGCombiner(*this, AA, Fast).Run(Level); 6106} 6107